Commit | Line | Data |
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2469cfa2 NC |
1 | /* tc-msp430.c -- Assembler code for the Texas Instruments MSP430 |
2 | ||
b90efa5b | 3 | Copyright (C) 2002-2015 Free Software Foundation, Inc. |
2469cfa2 NC |
4 | Contributed by Dmitry Diky <diwil@mail.ru> |
5 | ||
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
2469cfa2 NC |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
20 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
2469cfa2 | 22 | |
df7b86aa | 23 | #include "as.h" |
2469cfa2 | 24 | #include <limits.h> |
2469cfa2 | 25 | #define PUSH_1X_WORKAROUND |
2469cfa2 NC |
26 | #include "subsegs.h" |
27 | #include "opcode/msp430.h" | |
28 | #include "safe-ctype.h" | |
2a9a06c1 | 29 | #include "dwarf2dbg.h" |
13761a11 | 30 | #include "elf/msp430.h" |
2469cfa2 | 31 | |
79cf5950 | 32 | /* We will disable polymorphs by default because it is dangerous. |
708587a4 | 33 | The potential problem here is the following: assume we got the |
77592908 DD |
34 | following code: |
35 | ||
36 | jump .l1 | |
37 | nop | |
38 | jump subroutine ; external symbol | |
39 | .l1: | |
40 | nop | |
41 | ret | |
13761a11 | 42 | |
77592908 DD |
43 | In case of assembly time relaxation we'll get: |
44 | 0: jmp .l1 <.text +0x08> (reloc deleted) | |
45 | 2: nop | |
46 | 4: br subroutine | |
47 | .l1: | |
48 | 8: nop | |
49 | 10: ret | |
50 | ||
79cf5950 NC |
51 | If the 'subroutine' is within +-1024 bytes range then linker |
52 | will produce: | |
77592908 DD |
53 | 0: jmp .text +0x08 |
54 | 2: nop | |
55 | 4: jmp subroutine | |
56 | .l1: | |
57 | 6: nop | |
58 | 8: ret ; 'jmp .text +0x08' will land here. WRONG!!! | |
59 | ||
77592908 | 60 | The workaround is the following: |
79cf5950 | 61 | 1. Declare global var enable_polymorphs which set to 1 via option -mp. |
77592908 DD |
62 | 2. Declare global var enable_relax which set to 1 via option -mQ. |
63 | ||
64 | If polymorphs are enabled, and relax isn't, treat all jumps as long jumps, | |
65 | do not delete any relocs and leave them for linker. | |
13761a11 | 66 | |
79cf5950 | 67 | If relax is enabled, relax at assembly time and kill relocs as necessary. */ |
77592908 DD |
68 | |
69 | int msp430_enable_relax; | |
70 | int msp430_enable_polys; | |
71 | ||
13761a11 NC |
72 | /* Set linkrelax here to avoid fixups in most sections. */ |
73 | int linkrelax = 1; | |
74 | ||
f5c7edf4 AM |
75 | /* GCC uses the some condition codes which we'll |
76 | implement as new polymorph instructions. | |
13761a11 | 77 | |
f5c7edf4 AM |
78 | COND EXPL SHORT JUMP LONG JUMP |
79 | =============================================== | |
80 | eq == jeq jne +4; br lab | |
81 | ne != jne jeq +4; br lab | |
82 | ||
83 | ltn honours no-overflow flag | |
84 | ltn < jn jn +2; jmp +4; br lab | |
85 | ||
13761a11 | 86 | lt < jl jge +4; br lab |
f5c7edf4 AM |
87 | ltu < jlo lhs +4; br lab |
88 | le <= see below | |
89 | leu <= see below | |
90 | ||
91 | gt > see below | |
92 | gtu > see below | |
93 | ge >= jge jl +4; br lab | |
94 | geu >= jhs jlo +4; br lab | |
95 | =============================================== | |
96 | ||
97 | Therefore, new opcodes are (BranchEQ -> beq; and so on...) | |
98 | beq,bne,blt,bltn,bltu,bge,bgeu | |
13761a11 NC |
99 | 'u' means unsigned compares |
100 | ||
f5c7edf4 AM |
101 | Also, we add 'jump' instruction: |
102 | jump UNCOND -> jmp br lab | |
103 | ||
104 | They will have fmt == 4, and insn_opnumb == number of instruction. */ | |
105 | ||
13761a11 | 106 | struct rcodes_s |
f5c7edf4 AM |
107 | { |
108 | char * name; | |
109 | int index; /* Corresponding insn_opnumb. */ | |
110 | int sop; /* Opcode if jump length is short. */ | |
111 | long lpos; /* Label position. */ | |
112 | long lop0; /* Opcode 1 _word_ (16 bits). */ | |
113 | long lop1; /* Opcode second word. */ | |
114 | long lop2; /* Opcode third word. */ | |
115 | }; | |
116 | ||
117 | #define MSP430_RLC(n,i,sop,o1) \ | |
118 | {#n, i, sop, 2, (o1 + 2), 0x4010, 0} | |
119 | ||
13761a11 | 120 | static struct rcodes_s msp430_rcodes[] = |
f5c7edf4 AM |
121 | { |
122 | MSP430_RLC (beq, 0, 0x2400, 0x2000), | |
123 | MSP430_RLC (bne, 1, 0x2000, 0x2400), | |
124 | MSP430_RLC (blt, 2, 0x3800, 0x3400), | |
125 | MSP430_RLC (bltu, 3, 0x2800, 0x2c00), | |
126 | MSP430_RLC (bge, 4, 0x3400, 0x3800), | |
127 | MSP430_RLC (bgeu, 5, 0x2c00, 0x2800), | |
128 | {"bltn", 6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010}, | |
129 | {"jump", 7, 0x3c00, 1, 0x4010, 0, 0}, | |
130 | {0,0,0,0,0,0,0} | |
131 | }; | |
f5c7edf4 | 132 | |
13761a11 NC |
133 | #undef MSP430_RLC |
134 | #define MSP430_RLC(n,i,sop,o1) \ | |
135 | {#n, i, sop, 2, (o1 + 2), 0x0030, 0} | |
136 | ||
137 | static struct rcodes_s msp430x_rcodes[] = | |
138 | { | |
139 | MSP430_RLC (beq, 0, 0x2400, 0x2000), | |
140 | MSP430_RLC (bne, 1, 0x2000, 0x2400), | |
141 | MSP430_RLC (blt, 2, 0x3800, 0x3400), | |
142 | MSP430_RLC (bltu, 3, 0x2800, 0x2c00), | |
143 | MSP430_RLC (bge, 4, 0x3400, 0x3800), | |
144 | MSP430_RLC (bgeu, 5, 0x2c00, 0x2800), | |
145 | {"bltn", 6, 0x3000, 3, 0x0030 + 1, 0x3c00 + 2, 0x3000}, | |
146 | {"jump", 7, 0x3c00, 1, 0x0030, 0, 0}, | |
147 | {0,0,0,0,0,0,0} | |
148 | }; | |
149 | #undef MSP430_RLC | |
f5c7edf4 AM |
150 | |
151 | /* More difficult than above and they have format 5. | |
13761a11 | 152 | |
f5c7edf4 AM |
153 | COND EXPL SHORT LONG |
154 | ================================================================= | |
155 | gt > jeq +2; jge label jeq +6; jl +4; br label | |
156 | gtu > jeq +2; jhs label jeq +6; jlo +4; br label | |
157 | leu <= jeq label; jlo label jeq +2; jhs +4; br label | |
158 | le <= jeq label; jl label jeq +2; jge +4; br label | |
159 | ================================================================= */ | |
160 | ||
13761a11 | 161 | struct hcodes_s |
f5c7edf4 | 162 | { |
13761a11 | 163 | char * name; |
f5c7edf4 AM |
164 | int index; /* Corresponding insn_opnumb. */ |
165 | int tlab; /* Number of labels in short mode. */ | |
166 | int op0; /* Opcode for first word of short jump. */ | |
167 | int op1; /* Opcode for second word of short jump. */ | |
168 | int lop0; /* Opcodes for long jump mode. */ | |
169 | int lop1; | |
170 | int lop2; | |
171 | }; | |
172 | ||
13761a11 | 173 | static struct hcodes_s msp430_hcodes[] = |
f5c7edf4 AM |
174 | { |
175 | {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 }, | |
176 | {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 }, | |
177 | {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 }, | |
178 | {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 }, | |
179 | {0,0,0,0,0,0,0,0} | |
180 | }; | |
181 | ||
13761a11 NC |
182 | static struct hcodes_s msp430x_hcodes[] = |
183 | { | |
184 | {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x0030 }, | |
185 | {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x0030 }, | |
186 | {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x0030 }, | |
187 | {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x0030 }, | |
188 | {0,0,0,0,0,0,0,0} | |
189 | }; | |
190 | ||
2469cfa2 NC |
191 | const char comment_chars[] = ";"; |
192 | const char line_comment_chars[] = "#"; | |
870074dd | 193 | const char line_separator_chars[] = "{"; |
2469cfa2 NC |
194 | const char EXP_CHARS[] = "eE"; |
195 | const char FLT_CHARS[] = "dD"; | |
196 | ||
197 | /* Handle long expressions. */ | |
198 | extern LITTLENUM_TYPE generic_bignum[]; | |
199 | ||
200 | static struct hash_control *msp430_hash; | |
201 | ||
b18c562e NC |
202 | /* Relaxations. */ |
203 | #define STATE_UNCOND_BRANCH 1 /* jump */ | |
204 | #define STATE_NOOV_BRANCH 3 /* bltn */ | |
205 | #define STATE_SIMPLE_BRANCH 2 /* bne, beq, etc... */ | |
206 | #define STATE_EMUL_BRANCH 4 | |
207 | ||
208 | #define CNRL 2 | |
209 | #define CUBL 4 | |
210 | #define CNOL 8 | |
211 | #define CSBL 6 | |
212 | #define CEBL 4 | |
213 | ||
214 | /* Length. */ | |
215 | #define STATE_BITS10 1 /* wild guess. short jump */ | |
216 | #define STATE_WORD 2 /* 2 bytes pc rel. addr. more */ | |
217 | #define STATE_UNDEF 3 /* cannot handle this yet. convert to word mode */ | |
218 | ||
219 | #define ENCODE_RELAX(what,length) (((what) << 2) + (length)) | |
220 | #define RELAX_STATE(s) ((s) & 3) | |
221 | #define RELAX_LEN(s) ((s) >> 2) | |
222 | #define RELAX_NEXT(a,b) ENCODE_RELAX (a, b + 1) | |
223 | ||
224 | relax_typeS md_relax_table[] = | |
225 | { | |
226 | /* Unused. */ | |
227 | {1, 1, 0, 0}, | |
228 | {1, 1, 0, 0}, | |
229 | {1, 1, 0, 0}, | |
230 | {1, 1, 0, 0}, | |
231 | ||
232 | /* Unconditional jump. */ | |
233 | {1, 1, 8, 5}, | |
234 | {1024, -1024, CNRL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_BITS10)}, /* state 10 bits displ */ | |
235 | {0, 0, CUBL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_WORD)}, /* state word */ | |
236 | {1, 1, CUBL, 0}, /* state undef */ | |
237 | ||
238 | /* Simple branches. */ | |
239 | {0, 0, 8, 9}, | |
240 | {1024, -1024, CNRL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_BITS10)}, /* state 10 bits displ */ | |
241 | {0, 0, CSBL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_WORD)}, /* state word */ | |
242 | {1, 1, CSBL, 0}, | |
243 | ||
244 | /* blt no overflow branch. */ | |
245 | {1, 1, 8, 13}, | |
246 | {1024, -1024, CNRL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_BITS10)}, /* state 10 bits displ */ | |
247 | {0, 0, CNOL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_WORD)}, /* state word */ | |
248 | {1, 1, CNOL, 0}, | |
249 | ||
250 | /* Emulated branches. */ | |
251 | {1, 1, 8, 17}, | |
252 | {1020, -1020, CEBL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_BITS10)}, /* state 10 bits displ */ | |
253 | {0, 0, CNOL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_WORD)}, /* state word */ | |
254 | {1, 1, CNOL, 0} | |
255 | }; | |
256 | ||
2469cfa2 | 257 | |
837a17b3 | 258 | #define MAX_OP_LEN 4096 |
2469cfa2 | 259 | |
638d3803 NC |
260 | typedef enum msp_isa |
261 | { | |
262 | MSP_ISA_430, | |
263 | MSP_ISA_430X, | |
264 | MSP_ISA_430Xv2 | |
265 | } msp_isa; | |
266 | ||
65d7bab5 | 267 | static enum msp_isa selected_isa = MSP_ISA_430Xv2; |
638d3803 NC |
268 | |
269 | static inline bfd_boolean | |
270 | target_is_430x (void) | |
271 | { | |
65d7bab5 | 272 | return selected_isa >= MSP_ISA_430X; |
638d3803 NC |
273 | } |
274 | ||
275 | static inline bfd_boolean | |
276 | target_is_430xv2 (void) | |
277 | { | |
65d7bab5 | 278 | return selected_isa == MSP_ISA_430Xv2; |
638d3803 | 279 | } |
13761a11 | 280 | |
00b32ff2 NC |
281 | /* Generate an absolute 16-bit relocation. |
282 | For the 430X we generate a relocation without linker range checking | |
283 | if the value is being used in an extended (ie 20-bit) instruction, | |
284 | otherwise if have a shifted expression we use a HI reloc. | |
13761a11 | 285 | For the 430 we generate a relocation without assembler range checking |
00b32ff2 NC |
286 | if we are handling an immediate value or a byte-width instruction. */ |
287 | ||
13761a11 | 288 | #undef CHECK_RELOC_MSP430 |
00b32ff2 NC |
289 | #define CHECK_RELOC_MSP430(OP) \ |
290 | (target_is_430x () \ | |
291 | ? (extended_op \ | |
292 | ? BFD_RELOC_16 \ | |
293 | : ((OP).vshift == 1) \ | |
294 | ? BFD_RELOC_MSP430_ABS_HI16 \ | |
295 | : BFD_RELOC_MSP430X_ABS16) \ | |
296 | : ((imm_op || byte_op) \ | |
13761a11 NC |
297 | ? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16)) |
298 | ||
299 | /* Generate a 16-bit pc-relative relocation. | |
300 | For the 430X we generate a relocation without linkwer range checking. | |
301 | For the 430 we generate a relocation without assembler range checking | |
302 | if we are handling an immediate value or a byte-width instruction. */ | |
303 | #undef CHECK_RELOC_MSP430_PCREL | |
304 | #define CHECK_RELOC_MSP430_PCREL \ | |
638d3803 | 305 | (target_is_430x () \ |
13761a11 NC |
306 | ? BFD_RELOC_MSP430X_PCR16 \ |
307 | : (imm_op || byte_op) \ | |
308 | ? BFD_RELOC_MSP430_16_PCREL_BYTE : BFD_RELOC_MSP430_16_PCREL) | |
2469cfa2 | 309 | |
b18c562e NC |
310 | /* Profiling capability: |
311 | It is a performance hit to use gcc's profiling approach for this tiny target. | |
312 | Even more -- jtag hardware facility does not perform any profiling functions. | |
313 | However we've got gdb's built-in simulator where we can do anything. | |
314 | Therefore my suggestion is: | |
315 | ||
316 | We define new section ".profiler" which holds all profiling information. | |
317 | We define new pseudo operation .profiler which will instruct assembler to | |
318 | add new profile entry to the object file. Profile should take place at the | |
319 | present address. | |
320 | ||
321 | Pseudo-op format: | |
322 | ||
323 | .profiler flags,function_to_profile [, cycle_corrector, extra] | |
324 | ||
325 | where 'flags' is a combination of the following chars: | |
326 | s - function Start | |
327 | x - function eXit | |
328 | i - function is in Init section | |
329 | f - function is in Fini section | |
330 | l - Library call | |
331 | c - libC standard call | |
332 | d - stack value Demand (saved at run-time in simulator) | |
333 | I - Interrupt service routine | |
334 | P - Prologue start | |
335 | p - Prologue end | |
336 | E - Epilogue start | |
337 | e - Epilogue end | |
338 | j - long Jump/ sjlj unwind | |
339 | a - an Arbitrary code fragment | |
340 | t - exTra parameter saved (constant value like frame size) | |
341 | '""' optional: "sil" == sil | |
342 | ||
343 | function_to_profile - function's address | |
344 | cycle_corrector - a value which should be added to the cycle | |
345 | counter, zero if omitted | |
346 | extra - some extra parameter, zero if omitted. | |
347 | ||
348 | For example: | |
349 | ------------------------------ | |
350 | .global fxx | |
351 | .type fxx,@function | |
352 | fxx: | |
353 | .LFrameOffset_fxx=0x08 | |
354 | .profiler "scdP", fxx ; function entry. | |
355 | ; we also demand stack value to be displayed | |
356 | push r11 | |
357 | push r10 | |
358 | push r9 | |
359 | push r8 | |
360 | .profiler "cdp",fxx,0, .LFrameOffset_fxx ; check stack value at this point | |
361 | ; (this is a prologue end) | |
79cf5950 | 362 | ; note, that spare var filled with the frame size |
b18c562e NC |
363 | mov r15,r8 |
364 | .... | |
365 | .profiler cdE,fxx ; check stack | |
366 | pop r8 | |
367 | pop r9 | |
368 | pop r10 | |
369 | pop r11 | |
370 | .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter | |
371 | ret ; cause 'ret' insn takes 3 cycles | |
372 | ------------------------------- | |
373 | ||
374 | This profiling approach does not produce any overhead and | |
375 | absolutely harmless. | |
376 | So, even profiled code can be uploaded to the MCU. */ | |
377 | #define MSP430_PROFILER_FLAG_ENTRY 1 /* s */ | |
378 | #define MSP430_PROFILER_FLAG_EXIT 2 /* x */ | |
379 | #define MSP430_PROFILER_FLAG_INITSECT 4 /* i */ | |
380 | #define MSP430_PROFILER_FLAG_FINISECT 8 /* f */ | |
381 | #define MSP430_PROFILER_FLAG_LIBCALL 0x10 /* l */ | |
382 | #define MSP430_PROFILER_FLAG_STDCALL 0x20 /* c */ | |
383 | #define MSP430_PROFILER_FLAG_STACKDMD 0x40 /* d */ | |
384 | #define MSP430_PROFILER_FLAG_ISR 0x80 /* I */ | |
385 | #define MSP430_PROFILER_FLAG_PROLSTART 0x100 /* P */ | |
386 | #define MSP430_PROFILER_FLAG_PROLEND 0x200 /* p */ | |
387 | #define MSP430_PROFILER_FLAG_EPISTART 0x400 /* E */ | |
388 | #define MSP430_PROFILER_FLAG_EPIEND 0x800 /* e */ | |
389 | #define MSP430_PROFILER_FLAG_JUMP 0x1000 /* j */ | |
390 | #define MSP430_PROFILER_FLAG_FRAGMENT 0x2000 /* a */ | |
391 | #define MSP430_PROFILER_FLAG_EXTRA 0x4000 /* t */ | |
392 | #define MSP430_PROFILER_FLAG_notyet 0x8000 /* ? */ | |
2469cfa2 | 393 | |
b18c562e NC |
394 | static int |
395 | pow2value (int y) | |
2469cfa2 | 396 | { |
b18c562e NC |
397 | int n = 0; |
398 | unsigned int x; | |
2469cfa2 | 399 | |
b18c562e | 400 | x = y; |
2469cfa2 | 401 | |
b18c562e NC |
402 | if (!x) |
403 | return 1; | |
2469cfa2 | 404 | |
b18c562e NC |
405 | for (; x; x = x >> 1) |
406 | if (x & 1) | |
407 | n++; | |
408 | ||
409 | return n == 1; | |
410 | } | |
411 | ||
412 | /* Parse ordinary expression. */ | |
413 | ||
414 | static char * | |
415 | parse_exp (char * s, expressionS * op) | |
2469cfa2 | 416 | { |
b18c562e NC |
417 | input_line_pointer = s; |
418 | expression (op); | |
419 | if (op->X_op == O_absent) | |
420 | as_bad (_("missing operand")); | |
421 | return input_line_pointer; | |
422 | } | |
2469cfa2 | 423 | |
b18c562e NC |
424 | |
425 | /* Delete spaces from s: X ( r 1 2) => X(r12). */ | |
2469cfa2 NC |
426 | |
427 | static void | |
b18c562e | 428 | del_spaces (char * s) |
2469cfa2 | 429 | { |
b18c562e NC |
430 | while (*s) |
431 | { | |
432 | if (ISSPACE (*s)) | |
433 | { | |
434 | char *m = s + 1; | |
2469cfa2 | 435 | |
b18c562e NC |
436 | while (ISSPACE (*m) && *m) |
437 | m++; | |
438 | memmove (s, m, strlen (m) + 1); | |
439 | } | |
440 | else | |
441 | s++; | |
442 | } | |
443 | } | |
2469cfa2 | 444 | |
b18c562e NC |
445 | static inline char * |
446 | skip_space (char * s) | |
447 | { | |
448 | while (ISSPACE (*s)) | |
449 | ++s; | |
450 | return s; | |
451 | } | |
2469cfa2 | 452 | |
708587a4 | 453 | /* Extract one word from FROM and copy it to TO. Delimiters are ",;\n" */ |
b18c562e NC |
454 | |
455 | static char * | |
456 | extract_operand (char * from, char * to, int limit) | |
457 | { | |
458 | int size = 0; | |
459 | ||
460 | /* Drop leading whitespace. */ | |
461 | from = skip_space (from); | |
462 | ||
463 | while (size < limit && *from) | |
464 | { | |
465 | *(to + size) = *from; | |
466 | if (*from == ',' || *from == ';' || *from == '\n') | |
467 | break; | |
468 | from++; | |
469 | size++; | |
470 | } | |
471 | ||
472 | *(to + size) = 0; | |
473 | del_spaces (to); | |
474 | ||
475 | from++; | |
476 | ||
477 | return from; | |
2469cfa2 NC |
478 | } |
479 | ||
b18c562e NC |
480 | static void |
481 | msp430_profiler (int dummy ATTRIBUTE_UNUSED) | |
2469cfa2 | 482 | { |
b18c562e NC |
483 | char buffer[1024]; |
484 | char f[32]; | |
485 | char * str = buffer; | |
486 | char * flags = f; | |
487 | int p_flags = 0; | |
488 | char * halt; | |
489 | int ops = 0; | |
490 | int left; | |
491 | char * s; | |
492 | segT seg; | |
493 | int subseg; | |
494 | char * end = 0; | |
495 | expressionS exp; | |
496 | expressionS exp1; | |
497 | ||
498 | s = input_line_pointer; | |
499 | end = input_line_pointer; | |
500 | ||
501 | while (*end && *end != '\n') | |
502 | end++; | |
503 | ||
504 | while (*s && *s != '\n') | |
505 | { | |
506 | if (*s == ',') | |
507 | ops++; | |
508 | s++; | |
509 | } | |
2469cfa2 | 510 | |
b18c562e NC |
511 | left = 3 - ops; |
512 | ||
513 | if (ops < 1) | |
514 | { | |
515 | as_bad (_(".profiler pseudo requires at least two operands.")); | |
516 | input_line_pointer = end; | |
517 | return; | |
518 | } | |
519 | ||
520 | input_line_pointer = extract_operand (input_line_pointer, flags, 32); | |
521 | ||
522 | while (*flags) | |
523 | { | |
524 | switch (*flags) | |
525 | { | |
526 | case '"': | |
527 | break; | |
528 | case 'a': | |
529 | p_flags |= MSP430_PROFILER_FLAG_FRAGMENT; | |
530 | break; | |
531 | case 'j': | |
532 | p_flags |= MSP430_PROFILER_FLAG_JUMP; | |
533 | break; | |
534 | case 'P': | |
535 | p_flags |= MSP430_PROFILER_FLAG_PROLSTART; | |
536 | break; | |
537 | case 'p': | |
538 | p_flags |= MSP430_PROFILER_FLAG_PROLEND; | |
539 | break; | |
540 | case 'E': | |
541 | p_flags |= MSP430_PROFILER_FLAG_EPISTART; | |
542 | break; | |
543 | case 'e': | |
544 | p_flags |= MSP430_PROFILER_FLAG_EPIEND; | |
545 | break; | |
546 | case 's': | |
547 | p_flags |= MSP430_PROFILER_FLAG_ENTRY; | |
548 | break; | |
549 | case 'x': | |
550 | p_flags |= MSP430_PROFILER_FLAG_EXIT; | |
551 | break; | |
552 | case 'i': | |
553 | p_flags |= MSP430_PROFILER_FLAG_INITSECT; | |
554 | break; | |
555 | case 'f': | |
556 | p_flags |= MSP430_PROFILER_FLAG_FINISECT; | |
557 | break; | |
558 | case 'l': | |
559 | p_flags |= MSP430_PROFILER_FLAG_LIBCALL; | |
560 | break; | |
561 | case 'c': | |
562 | p_flags |= MSP430_PROFILER_FLAG_STDCALL; | |
563 | break; | |
564 | case 'd': | |
565 | p_flags |= MSP430_PROFILER_FLAG_STACKDMD; | |
566 | break; | |
567 | case 'I': | |
568 | p_flags |= MSP430_PROFILER_FLAG_ISR; | |
569 | break; | |
570 | case 't': | |
571 | p_flags |= MSP430_PROFILER_FLAG_EXTRA; | |
572 | break; | |
573 | default: | |
574 | as_warn (_("unknown profiling flag - ignored.")); | |
575 | break; | |
576 | } | |
577 | flags++; | |
578 | } | |
579 | ||
580 | if (p_flags | |
581 | && ( ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_ENTRY | |
582 | | MSP430_PROFILER_FLAG_EXIT)) | |
583 | || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_PROLSTART | |
584 | | MSP430_PROFILER_FLAG_PROLEND | |
585 | | MSP430_PROFILER_FLAG_EPISTART | |
586 | | MSP430_PROFILER_FLAG_EPIEND)) | |
587 | || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_INITSECT | |
588 | | MSP430_PROFILER_FLAG_FINISECT)))) | |
589 | { | |
79cf5950 | 590 | as_bad (_("ambiguous flags combination - '.profiler' directive ignored.")); |
b18c562e NC |
591 | input_line_pointer = end; |
592 | return; | |
593 | } | |
594 | ||
595 | /* Generate temp symbol which denotes current location. */ | |
79cf5950 | 596 | if (now_seg == absolute_section) /* Paranoia ? */ |
b18c562e NC |
597 | { |
598 | exp1.X_op = O_constant; | |
599 | exp1.X_add_number = abs_section_offset; | |
79cf5950 | 600 | as_warn (_("profiling in absolute section?")); |
b18c562e NC |
601 | } |
602 | else | |
603 | { | |
604 | exp1.X_op = O_symbol; | |
605 | exp1.X_add_symbol = symbol_temp_new_now (); | |
606 | exp1.X_add_number = 0; | |
607 | } | |
608 | ||
609 | /* Generate a symbol which holds flags value. */ | |
610 | exp.X_op = O_constant; | |
611 | exp.X_add_number = p_flags; | |
612 | ||
613 | /* Save current section. */ | |
614 | seg = now_seg; | |
615 | subseg = now_subseg; | |
616 | ||
617 | /* Now go to .profiler section. */ | |
618 | obj_elf_change_section (".profiler", SHT_PROGBITS, 0, 0, 0, 0, 0); | |
619 | ||
620 | /* Save flags. */ | |
621 | emit_expr (& exp, 2); | |
622 | ||
623 | /* Save label value. */ | |
624 | emit_expr (& exp1, 2); | |
625 | ||
626 | while (ops--) | |
627 | { | |
628 | /* Now get profiling info. */ | |
629 | halt = extract_operand (input_line_pointer, str, 1024); | |
630 | /* Process like ".word xxx" directive. */ | |
631 | parse_exp (str, & exp); | |
632 | emit_expr (& exp, 2); | |
633 | input_line_pointer = halt; | |
634 | } | |
635 | ||
636 | /* Fill the rest with zeros. */ | |
637 | exp.X_op = O_constant; | |
638 | exp.X_add_number = 0; | |
639 | while (left--) | |
640 | emit_expr (& exp, 2); | |
641 | ||
642 | /* Return to current section. */ | |
643 | subseg_set (seg, subseg); | |
2469cfa2 NC |
644 | } |
645 | ||
646 | static char * | |
b18c562e | 647 | extract_word (char * from, char * to, int limit) |
2469cfa2 | 648 | { |
2469cfa2 NC |
649 | char *op_end; |
650 | int size = 0; | |
651 | ||
652 | /* Drop leading whitespace. */ | |
653 | from = skip_space (from); | |
654 | *to = 0; | |
655 | ||
656 | /* Find the op code end. */ | |
87975d2a | 657 | for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);) |
2469cfa2 NC |
658 | { |
659 | to[size++] = *op_end++; | |
660 | if (size + 1 >= limit) | |
661 | break; | |
662 | } | |
663 | ||
664 | to[size] = 0; | |
665 | return op_end; | |
666 | } | |
667 | ||
b18c562e | 668 | #define OPTION_MMCU 'm' |
77592908 DD |
669 | #define OPTION_RELAX 'Q' |
670 | #define OPTION_POLYMORPHS 'P' | |
13761a11 NC |
671 | #define OPTION_LARGE 'l' |
672 | static bfd_boolean large_model = FALSE; | |
673 | #define OPTION_NO_INTR_NOPS 'N' | |
65d7bab5 | 674 | #define OPTION_INTR_NOPS 'n' |
a75555d1 | 675 | static bfd_boolean gen_interrupt_nops = FALSE; |
69227609 NC |
676 | #define OPTION_WARN_INTR_NOPS 'y' |
677 | #define OPTION_NO_WARN_INTR_NOPS 'Y' | |
65d7bab5 | 678 | static bfd_boolean warn_interrupt_nops = TRUE; |
638d3803 | 679 | #define OPTION_MCPU 'c' |
ab905915 NC |
680 | #define OPTION_MOVE_DATA 'd' |
681 | static bfd_boolean move_data = FALSE; | |
b18c562e | 682 | |
2469cfa2 | 683 | static void |
638d3803 | 684 | msp430_set_arch (int option) |
2469cfa2 NC |
685 | { |
686 | char *str = (char *) alloca (32); /* 32 for good measure. */ | |
687 | ||
688 | input_line_pointer = extract_word (input_line_pointer, str, 32); | |
689 | ||
638d3803 NC |
690 | md_parse_option (option, str); |
691 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, | |
692 | target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11); | |
2469cfa2 NC |
693 | } |
694 | ||
65d7bab5 NC |
695 | /* This is the full list of MCU names that are known to only |
696 | support the 430 ISA. */ | |
697 | static const char * msp430_mcu_names [] = | |
698 | { | |
699 | "msp430afe221", "msp430afe222", "msp430afe223", "msp430afe231", | |
700 | "msp430afe232", "msp430afe233", "msp430afe251", "msp430afe252", | |
701 | "msp430afe253", "msp430c091", "msp430c092", "msp430c111", | |
702 | "msp430c1111", "msp430c112", "msp430c1121", "msp430c1331", | |
703 | "msp430c1351", "msp430c311s", "msp430c312", "msp430c313", | |
704 | "msp430c314", "msp430c315", "msp430c323", "msp430c325", | |
705 | "msp430c336", "msp430c337", "msp430c412", "msp430c413", | |
706 | "msp430e112", "msp430e313", "msp430e315", "msp430e325", | |
707 | "msp430e337", "msp430f110", "msp430f1101", "msp430f1101a", | |
708 | "msp430f1111", "msp430f1111a", "msp430f112", "msp430f1121", | |
709 | "msp430f1121a", "msp430f1122", "msp430f1132", "msp430f122", | |
710 | "msp430f1222", "msp430f123", "msp430f1232", "msp430f133", | |
711 | "msp430f135", "msp430f147", "msp430f1471", "msp430f148", | |
712 | "msp430f1481", "msp430f149", "msp430f1491", "msp430f155", | |
713 | "msp430f156", "msp430f157", "msp430f1610", "msp430f1611", | |
714 | "msp430f1612", "msp430f167", "msp430f168", "msp430f169", | |
715 | "msp430f2001", "msp430f2002", "msp430f2003", "msp430f2011", | |
716 | "msp430f2012", "msp430f2013", "msp430f2101", "msp430f2111", | |
717 | "msp430f2112", "msp430f2121", "msp430f2122", "msp430f2131", | |
718 | "msp430f2132", "msp430f2232", "msp430f2234", "msp430f2252", | |
719 | "msp430f2254", "msp430f2272", "msp430f2274", "msp430f233", | |
720 | "msp430f2330", "msp430f235", "msp430f2350", "msp430f2370", | |
721 | "msp430f2410", "msp430f247", "msp430f2471", "msp430f248", | |
722 | "msp430f2481", "msp430f249", "msp430f2491", "msp430f412", | |
723 | "msp430f413", "msp430f4132", "msp430f415", "msp430f4152", | |
724 | "msp430f417", "msp430f423", "msp430f423a", "msp430f425", | |
725 | "msp430f4250", "msp430f425a", "msp430f4260", "msp430f427", | |
726 | "msp430f4270", "msp430f427a", "msp430f435", "msp430f4351", | |
727 | "msp430f436", "msp430f4361", "msp430f437", "msp430f4371", | |
728 | "msp430f438", "msp430f439", "msp430f447", "msp430f448", | |
729 | "msp430f4481", "msp430f449", "msp430f4491", "msp430f477", | |
730 | "msp430f478", "msp430f4783", "msp430f4784", "msp430f479", | |
731 | "msp430f4793", "msp430f4794", "msp430fe423", "msp430fe4232", | |
732 | "msp430fe423a", "msp430fe4242", "msp430fe425", "msp430fe4252", | |
733 | "msp430fe425a", "msp430fe427", "msp430fe4272", "msp430fe427a", | |
734 | "msp430fg4250", "msp430fg4260", "msp430fg4270", "msp430fg437", | |
735 | "msp430fg438", "msp430fg439", "msp430fg477", "msp430fg478", | |
736 | "msp430fg479", "msp430fw423", "msp430fw425", "msp430fw427", | |
737 | "msp430fw428", "msp430fw429", "msp430g2001", "msp430g2101", | |
738 | "msp430g2102", "msp430g2111", "msp430g2112", "msp430g2113", | |
739 | "msp430g2121", "msp430g2131", "msp430g2132", "msp430g2152", | |
740 | "msp430g2153", "msp430g2201", "msp430g2202", "msp430g2203", | |
741 | "msp430g2210", "msp430g2211", "msp430g2212", "msp430g2213", | |
742 | "msp430g2221", "msp430g2230", "msp430g2231", "msp430g2232", | |
743 | "msp430g2233", "msp430g2252", "msp430g2253", "msp430g2302", | |
744 | "msp430g2303", "msp430g2312", "msp430g2313", "msp430g2332", | |
745 | "msp430g2333", "msp430g2352", "msp430g2353", "msp430g2402", | |
746 | "msp430g2403", "msp430g2412", "msp430g2413", "msp430g2432", | |
747 | "msp430g2433", "msp430g2444", "msp430g2452", "msp430g2453", | |
748 | "msp430g2513", "msp430g2533", "msp430g2544", "msp430g2553", | |
749 | "msp430g2744", "msp430g2755", "msp430g2855", "msp430g2955", | |
750 | "msp430i2020", "msp430i2021", "msp430i2030", "msp430i2031", | |
751 | "msp430i2040", "msp430i2041", "msp430l092", "msp430p112", | |
752 | "msp430p313", "msp430p315", "msp430p315s", "msp430p325", | |
753 | "msp430p337", "msp430tch5e" | |
754 | }; | |
755 | ||
2469cfa2 | 756 | int |
b18c562e | 757 | md_parse_option (int c, char * arg) |
2469cfa2 | 758 | { |
2469cfa2 NC |
759 | switch (c) |
760 | { | |
761 | case OPTION_MMCU: | |
638d3803 NC |
762 | if (arg == NULL) |
763 | as_fatal (_("MCU option requires a name\n")); | |
764 | ||
65d7bab5 NC |
765 | if (strcasecmp ("msp430", arg) == 0) |
766 | selected_isa = MSP_ISA_430; | |
767 | else if (strcasecmp ("msp430xv2", arg) == 0) | |
768 | selected_isa = MSP_ISA_430Xv2; | |
769 | else if (strcasecmp ("msp430x", arg) == 0) | |
770 | selected_isa = MSP_ISA_430X; | |
771 | else | |
2469cfa2 | 772 | { |
65d7bab5 NC |
773 | int i; |
774 | ||
775 | for (i = sizeof msp430_mcu_names / sizeof msp430_mcu_names[0]; i--;) | |
776 | if (strcasecmp (msp430_mcu_names[i], arg) == 0) | |
777 | { | |
778 | selected_isa = MSP_ISA_430; | |
779 | break; | |
780 | } | |
2469cfa2 | 781 | } |
8e75a78f | 782 | /* It is not an error if we do not match the MCU name. */ |
2469cfa2 | 783 | return 1; |
65d7bab5 | 784 | |
638d3803 | 785 | case OPTION_MCPU: |
8e75a78f NC |
786 | if (strcmp (arg, "430") == 0 |
787 | || strcasecmp (arg, "msp430") == 0) | |
65d7bab5 | 788 | selected_isa = MSP_ISA_430; |
8e75a78f NC |
789 | else if (strcasecmp (arg, "430x") == 0 |
790 | || strcasecmp (arg, "msp430x") == 0) | |
65d7bab5 | 791 | selected_isa = MSP_ISA_430X; |
8e75a78f NC |
792 | else if (strcasecmp (arg, "430xv2") == 0 |
793 | || strcasecmp (arg, "msp430xv2") == 0) | |
65d7bab5 | 794 | selected_isa = MSP_ISA_430Xv2; |
638d3803 NC |
795 | else |
796 | as_fatal (_("unrecognised argument to -mcpu option '%s'"), arg); | |
638d3803 | 797 | return 1; |
38d77545 | 798 | |
77592908 | 799 | case OPTION_RELAX: |
13761a11 | 800 | msp430_enable_relax = 1; |
77592908 | 801 | return 1; |
13761a11 | 802 | |
77592908 DD |
803 | case OPTION_POLYMORPHS: |
804 | msp430_enable_polys = 1; | |
805 | return 1; | |
13761a11 NC |
806 | |
807 | case OPTION_LARGE: | |
808 | large_model = TRUE; | |
809 | return 1; | |
810 | ||
811 | case OPTION_NO_INTR_NOPS: | |
812 | gen_interrupt_nops = FALSE; | |
813 | return 1; | |
a75555d1 NC |
814 | case OPTION_INTR_NOPS: |
815 | gen_interrupt_nops = TRUE; | |
816 | return 1; | |
ab905915 | 817 | |
65d7bab5 NC |
818 | case OPTION_WARN_INTR_NOPS: |
819 | warn_interrupt_nops = TRUE; | |
820 | return 1; | |
821 | case OPTION_NO_WARN_INTR_NOPS: | |
822 | warn_interrupt_nops = FALSE; | |
823 | return 1; | |
824 | ||
ab905915 NC |
825 | case OPTION_MOVE_DATA: |
826 | move_data = TRUE; | |
827 | return 1; | |
2469cfa2 NC |
828 | } |
829 | ||
830 | return 0; | |
831 | } | |
832 | ||
34b822e3 DD |
833 | /* The intention here is to have the mere presence of these sections |
834 | cause the object to have a reference to a well-known symbol. This | |
835 | reference pulls in the bits of the runtime (crt0) that initialize | |
836 | these sections. Thus, for example, the startup code to call | |
837 | memset() to initialize .bss will only be linked in when there is a | |
838 | non-empty .bss section. Otherwise, the call would exist but have a | |
839 | zero length parameter, which is a waste of memory and cycles. | |
840 | ||
841 | The code which initializes these sections should have a global | |
842 | label for these symbols, and should be marked with KEEP() in the | |
837a17b3 NC |
843 | linker script. */ |
844 | ||
ab905915 | 845 | static void |
837a17b3 | 846 | msp430_make_init_symbols (const char * name) |
ab905915 | 847 | { |
ab905915 NC |
848 | if (strncmp (name, ".bss", 4) == 0 |
849 | || strncmp (name, ".gnu.linkonce.b.", 16) == 0) | |
850 | (void) symbol_find_or_make ("__crt0_init_bss"); | |
851 | ||
34b822e3 DD |
852 | if (strncmp (name, ".data", 5) == 0 |
853 | || strncmp (name, ".gnu.linkonce.d.", 16) == 0) | |
ab905915 NC |
854 | (void) symbol_find_or_make ("__crt0_movedata"); |
855 | ||
837a17b3 NC |
856 | /* Note - data assigned to the .either.data section may end up being |
857 | placed in the .upper.data section if the .lower.data section is | |
858 | full. Hence the need to define the crt0 symbol. */ | |
859 | if (strncmp (name, ".either.data", 12) == 0 | |
860 | || strncmp (name, ".upper.data", 11) == 0) | |
861 | (void) symbol_find_or_make ("__crt0_move_highdata"); | |
862 | ||
863 | /* See note about .either.data above. */ | |
864 | if (strncmp (name, ".upper.bss", 10) == 0 | |
865 | || strncmp (name, ".either.bss", 11) == 0) | |
866 | (void) symbol_find_or_make ("__crt0_init_highbss"); | |
867 | } | |
868 | ||
869 | static void | |
870 | msp430_section (int arg) | |
871 | { | |
872 | char * saved_ilp = input_line_pointer; | |
873 | char * name = obj_elf_section_name (); | |
874 | ||
875 | msp430_make_init_symbols (name); | |
876 | ||
ab905915 NC |
877 | input_line_pointer = saved_ilp; |
878 | obj_elf_section (arg); | |
879 | } | |
880 | ||
34b822e3 DD |
881 | void |
882 | msp430_frob_section (asection *sec) | |
883 | { | |
884 | const char *name = sec->name; | |
885 | ||
886 | if (sec->size == 0) | |
887 | return; | |
888 | ||
837a17b3 | 889 | msp430_make_init_symbols (name); |
34b822e3 DD |
890 | } |
891 | ||
892 | static void | |
893 | msp430_lcomm (int ignore ATTRIBUTE_UNUSED) | |
894 | { | |
895 | symbolS *symbolP = s_comm_internal (0, s_lcomm_internal); | |
896 | ||
897 | if (symbolP) | |
898 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; | |
899 | (void) symbol_find_or_make ("__crt0_init_bss"); | |
900 | } | |
901 | ||
902 | static void | |
903 | msp430_comm (int needs_align) | |
904 | { | |
905 | s_comm_internal (needs_align, elf_common_parse); | |
906 | (void) symbol_find_or_make ("__crt0_init_bss"); | |
907 | } | |
908 | ||
96b96102 DD |
909 | static void |
910 | msp430_refsym (int arg ATTRIBUTE_UNUSED) | |
911 | { | |
912 | char sym_name[1024]; | |
913 | input_line_pointer = extract_word (input_line_pointer, sym_name, 1024); | |
914 | ||
915 | (void) symbol_find_or_make (sym_name); | |
916 | } | |
917 | ||
b18c562e | 918 | const pseudo_typeS md_pseudo_table[] = |
2469cfa2 | 919 | { |
638d3803 NC |
920 | {"arch", msp430_set_arch, OPTION_MMCU}, |
921 | {"cpu", msp430_set_arch, OPTION_MCPU}, | |
b18c562e | 922 | {"profiler", msp430_profiler, 0}, |
ab905915 NC |
923 | {"section", msp430_section, 0}, |
924 | {"section.s", msp430_section, 0}, | |
925 | {"sect", msp430_section, 0}, | |
926 | {"sect.s", msp430_section, 0}, | |
927 | {"pushsection", msp430_section, 1}, | |
96b96102 | 928 | {"refsym", msp430_refsym, 0}, |
34b822e3 DD |
929 | {"comm", msp430_comm, 0}, |
930 | {"lcomm", msp430_lcomm, 0}, | |
b18c562e NC |
931 | {NULL, NULL, 0} |
932 | }; | |
2469cfa2 | 933 | |
69227609 | 934 | const char *md_shortopts = "mm:,mP,mQ,ml,mN,mn,my,mY"; |
2469cfa2 | 935 | |
b18c562e | 936 | struct option md_longopts[] = |
2469cfa2 | 937 | { |
b18c562e | 938 | {"mmcu", required_argument, NULL, OPTION_MMCU}, |
638d3803 | 939 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
77592908 DD |
940 | {"mP", no_argument, NULL, OPTION_POLYMORPHS}, |
941 | {"mQ", no_argument, NULL, OPTION_RELAX}, | |
13761a11 NC |
942 | {"ml", no_argument, NULL, OPTION_LARGE}, |
943 | {"mN", no_argument, NULL, OPTION_NO_INTR_NOPS}, | |
a75555d1 | 944 | {"mn", no_argument, NULL, OPTION_INTR_NOPS}, |
69227609 NC |
945 | {"mY", no_argument, NULL, OPTION_NO_WARN_INTR_NOPS}, |
946 | {"my", no_argument, NULL, OPTION_WARN_INTR_NOPS}, | |
ab905915 | 947 | {"md", no_argument, NULL, OPTION_MOVE_DATA}, |
b18c562e NC |
948 | {NULL, no_argument, NULL, 0} |
949 | }; | |
2469cfa2 | 950 | |
b18c562e | 951 | size_t md_longopts_size = sizeof (md_longopts); |
2469cfa2 | 952 | |
b18c562e NC |
953 | void |
954 | md_show_usage (FILE * stream) | |
2469cfa2 | 955 | { |
b18c562e NC |
956 | fprintf (stream, |
957 | _("MSP430 options:\n" | |
638d3803 NC |
958 | " -mmcu=<msp430-name> - select microcontroller type\n" |
959 | " -mcpu={430|430x|430xv2} - select microcontroller architecture\n")); | |
77592908 DD |
960 | fprintf (stream, |
961 | _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n" | |
962 | " -mP - enable polymorph instructions\n")); | |
13761a11 NC |
963 | fprintf (stream, |
964 | _(" -ml - enable large code model\n")); | |
965 | fprintf (stream, | |
65d7bab5 | 966 | _(" -mN - do not insert NOPs after changing interrupts (default)\n")); |
a75555d1 | 967 | fprintf (stream, |
65d7bab5 NC |
968 | _(" -mn - insert a NOP after changing interrupts\n")); |
969 | fprintf (stream, | |
69227609 | 970 | _(" -mY - do not warn about missing NOPs after changing interrupts\n")); |
65d7bab5 | 971 | fprintf (stream, |
69227609 | 972 | _(" -my - warn about missing NOPs after changing interrupts (default)\n")); |
ab905915 NC |
973 | fprintf (stream, |
974 | _(" -md - Force copying of data from ROM to RAM at startup\n")); | |
b18c562e | 975 | } |
2469cfa2 | 976 | |
b18c562e NC |
977 | symbolS * |
978 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
979 | { | |
13761a11 | 980 | return NULL; |
2469cfa2 NC |
981 | } |
982 | ||
983 | static char * | |
b18c562e | 984 | extract_cmd (char * from, char * to, int limit) |
2469cfa2 NC |
985 | { |
986 | int size = 0; | |
987 | ||
988 | while (*from && ! ISSPACE (*from) && *from != '.' && limit > size) | |
989 | { | |
990 | *(to + size) = *from; | |
991 | from++; | |
992 | size++; | |
993 | } | |
994 | ||
995 | *(to + size) = 0; | |
996 | ||
997 | return from; | |
998 | } | |
999 | ||
2469cfa2 | 1000 | char * |
b18c562e | 1001 | md_atof (int type, char * litP, int * sizeP) |
2469cfa2 | 1002 | { |
499ac353 | 1003 | return ieee_md_atof (type, litP, sizeP, FALSE); |
2469cfa2 NC |
1004 | } |
1005 | ||
1006 | void | |
b18c562e | 1007 | md_begin (void) |
2469cfa2 | 1008 | { |
b18c562e | 1009 | struct msp430_opcode_s * opcode; |
2469cfa2 NC |
1010 | msp430_hash = hash_new (); |
1011 | ||
1012 | for (opcode = msp430_opcodes; opcode->name; opcode++) | |
1013 | hash_insert (msp430_hash, opcode->name, (char *) opcode); | |
1014 | ||
638d3803 NC |
1015 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, |
1016 | target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11); | |
2469cfa2 NC |
1017 | } |
1018 | ||
13761a11 NC |
1019 | /* Returns the register number equivalent to the string T. |
1020 | Returns -1 if there is no such register. | |
1021 | Skips a leading 'r' or 'R' character if there is one. | |
1022 | Handles the register aliases PC and SP. */ | |
1023 | ||
1024 | static signed int | |
b18c562e | 1025 | check_reg (char * t) |
2469cfa2 | 1026 | { |
13761a11 | 1027 | signed int val; |
2469cfa2 | 1028 | |
13761a11 NC |
1029 | if (t == NULL) |
1030 | return -1; | |
2469cfa2 | 1031 | |
13761a11 NC |
1032 | if (*t == 'r' || *t == 'R') |
1033 | ++t; | |
1034 | ||
1035 | if (strncasecmp (t, "pc", 2) == 0) | |
1036 | return 0; | |
2469cfa2 | 1037 | |
13761a11 | 1038 | if (strncasecmp (t, "sp", 2) == 0) |
b18c562e | 1039 | return 1; |
2469cfa2 | 1040 | |
13761a11 NC |
1041 | if (strncasecmp (t, "sr", 2) == 0) |
1042 | return 2; | |
1043 | ||
1044 | if (*t == '0') | |
1045 | return 0; | |
2469cfa2 | 1046 | |
13761a11 NC |
1047 | val = atoi (t); |
1048 | ||
1049 | if (val < 1 || val > 15) | |
1050 | return -1; | |
1051 | ||
1052 | return val; | |
1053 | } | |
2469cfa2 | 1054 | |
b18c562e NC |
1055 | static int |
1056 | msp430_srcoperand (struct msp430_operand_s * op, | |
13761a11 NC |
1057 | char * l, |
1058 | int bin, | |
00b32ff2 | 1059 | bfd_boolean * imm_op, |
13761a11 NC |
1060 | bfd_boolean allow_20bit_values, |
1061 | bfd_boolean constants_allowed) | |
2469cfa2 | 1062 | { |
b18c562e | 1063 | char *__tl = l; |
2469cfa2 | 1064 | |
b18c562e NC |
1065 | /* Check if an immediate #VALUE. The hash sign should be only at the beginning! */ |
1066 | if (*l == '#') | |
2469cfa2 | 1067 | { |
b18c562e NC |
1068 | char *h = l; |
1069 | int vshift = -1; | |
1070 | int rval = 0; | |
2469cfa2 | 1071 | |
b18c562e NC |
1072 | /* Check if there is: |
1073 | llo(x) - least significant 16 bits, x &= 0xffff | |
1074 | lhi(x) - x = (x >> 16) & 0xffff, | |
1075 | hlo(x) - x = (x >> 32) & 0xffff, | |
1076 | hhi(x) - x = (x >> 48) & 0xffff | |
1077 | The value _MUST_ be constant expression: #hlo(1231231231). */ | |
2469cfa2 | 1078 | |
00b32ff2 | 1079 | *imm_op = TRUE; |
2469cfa2 | 1080 | |
b18c562e NC |
1081 | if (strncasecmp (h, "#llo(", 5) == 0) |
1082 | { | |
1083 | vshift = 0; | |
1084 | rval = 3; | |
1085 | } | |
1086 | else if (strncasecmp (h, "#lhi(", 5) == 0) | |
1087 | { | |
1088 | vshift = 1; | |
1089 | rval = 3; | |
1090 | } | |
1091 | else if (strncasecmp (h, "#hlo(", 5) == 0) | |
1092 | { | |
1093 | vshift = 2; | |
1094 | rval = 3; | |
1095 | } | |
1096 | else if (strncasecmp (h, "#hhi(", 5) == 0) | |
1097 | { | |
1098 | vshift = 3; | |
1099 | rval = 3; | |
1100 | } | |
1101 | else if (strncasecmp (h, "#lo(", 4) == 0) | |
1102 | { | |
1103 | vshift = 0; | |
1104 | rval = 2; | |
1105 | } | |
1106 | else if (strncasecmp (h, "#hi(", 4) == 0) | |
1107 | { | |
1108 | vshift = 1; | |
1109 | rval = 2; | |
1110 | } | |
2469cfa2 | 1111 | |
b18c562e NC |
1112 | op->reg = 0; /* Reg PC. */ |
1113 | op->am = 3; | |
65d7bab5 | 1114 | op->ol = 1; /* Immediate will follow an instruction. */ |
b18c562e NC |
1115 | __tl = h + 1 + rval; |
1116 | op->mode = OP_EXP; | |
00b32ff2 | 1117 | op->vshift = vshift; |
2469cfa2 | 1118 | |
b18c562e NC |
1119 | parse_exp (__tl, &(op->exp)); |
1120 | if (op->exp.X_op == O_constant) | |
2469cfa2 | 1121 | { |
b18c562e | 1122 | int x = op->exp.X_add_number; |
2469cfa2 | 1123 | |
b18c562e | 1124 | if (vshift == 0) |
2469cfa2 | 1125 | { |
b18c562e NC |
1126 | x = x & 0xffff; |
1127 | op->exp.X_add_number = x; | |
1128 | } | |
1129 | else if (vshift == 1) | |
1130 | { | |
1131 | x = (x >> 16) & 0xffff; | |
1132 | op->exp.X_add_number = x; | |
00b32ff2 | 1133 | op->vshift = 0; |
b18c562e NC |
1134 | } |
1135 | else if (vshift > 1) | |
1136 | { | |
1137 | if (x < 0) | |
1138 | op->exp.X_add_number = -1; | |
2469cfa2 | 1139 | else |
b18c562e NC |
1140 | op->exp.X_add_number = 0; /* Nothing left. */ |
1141 | x = op->exp.X_add_number; | |
00b32ff2 | 1142 | op->vshift = 0; |
2469cfa2 | 1143 | } |
2469cfa2 | 1144 | |
13761a11 NC |
1145 | if (allow_20bit_values) |
1146 | { | |
99b4a5a0 | 1147 | if (op->exp.X_add_number > 0xfffff || op->exp.X_add_number < -524288) |
13761a11 NC |
1148 | { |
1149 | as_bad (_("value 0x%x out of extended range."), x); | |
1150 | return 1; | |
1151 | } | |
1152 | } | |
1153 | else if (op->exp.X_add_number > 65535 || op->exp.X_add_number < -32768) | |
b18c562e NC |
1154 | { |
1155 | as_bad (_("value %d out of range. Use #lo() or #hi()"), x); | |
1156 | return 1; | |
1157 | } | |
2469cfa2 | 1158 | |
b18c562e NC |
1159 | /* Now check constants. */ |
1160 | /* Substitute register mode with a constant generator if applicable. */ | |
2469cfa2 | 1161 | |
13761a11 NC |
1162 | if (!allow_20bit_values) |
1163 | x = (short) x; /* Extend sign. */ | |
2469cfa2 | 1164 | |
13761a11 NC |
1165 | if (! constants_allowed) |
1166 | ; | |
1167 | else if (x == 0) | |
2469cfa2 | 1168 | { |
b18c562e NC |
1169 | op->reg = 3; |
1170 | op->am = 0; | |
1171 | op->ol = 0; | |
1172 | op->mode = OP_REG; | |
1173 | } | |
1174 | else if (x == 1) | |
1175 | { | |
1176 | op->reg = 3; | |
1177 | op->am = 1; | |
1178 | op->ol = 0; | |
1179 | op->mode = OP_REG; | |
1180 | } | |
1181 | else if (x == 2) | |
1182 | { | |
1183 | op->reg = 3; | |
1184 | op->am = 2; | |
1185 | op->ol = 0; | |
1186 | op->mode = OP_REG; | |
1187 | } | |
1188 | else if (x == -1) | |
1189 | { | |
1190 | op->reg = 3; | |
1191 | op->am = 3; | |
1192 | op->ol = 0; | |
1193 | op->mode = OP_REG; | |
1194 | } | |
1195 | else if (x == 4) | |
1196 | { | |
1197 | #ifdef PUSH_1X_WORKAROUND | |
1198 | if (bin == 0x1200) | |
1199 | { | |
1200 | /* Remove warning as confusing. | |
20203fb9 | 1201 | as_warn (_("Hardware push bug workaround")); */ |
b18c562e NC |
1202 | } |
1203 | else | |
1204 | #endif | |
1205 | { | |
1206 | op->reg = 2; | |
1207 | op->am = 2; | |
1208 | op->ol = 0; | |
1209 | op->mode = OP_REG; | |
1210 | } | |
1211 | } | |
1212 | else if (x == 8) | |
1213 | { | |
1214 | #ifdef PUSH_1X_WORKAROUND | |
1215 | if (bin == 0x1200) | |
1216 | { | |
1217 | /* Remove warning as confusing. | |
20203fb9 | 1218 | as_warn (_("Hardware push bug workaround")); */ |
b18c562e NC |
1219 | } |
1220 | else | |
1221 | #endif | |
1222 | { | |
1223 | op->reg = 2; | |
1224 | op->am = 3; | |
1225 | op->ol = 0; | |
1226 | op->mode = OP_REG; | |
1227 | } | |
2469cfa2 | 1228 | } |
2469cfa2 | 1229 | } |
b18c562e NC |
1230 | else if (op->exp.X_op == O_symbol) |
1231 | { | |
00b32ff2 NC |
1232 | if (vshift > 1) |
1233 | as_bad (_("error: unsupported #foo() directive used on symbol")); | |
b18c562e NC |
1234 | op->mode = OP_EXP; |
1235 | } | |
1236 | else if (op->exp.X_op == O_big) | |
1237 | { | |
1238 | short x; | |
65d7bab5 | 1239 | |
b18c562e NC |
1240 | if (vshift != -1) |
1241 | { | |
1242 | op->exp.X_op = O_constant; | |
1243 | op->exp.X_add_number = 0xffff & generic_bignum[vshift]; | |
1244 | x = op->exp.X_add_number; | |
00b32ff2 | 1245 | op->vshift = 0; |
b18c562e NC |
1246 | } |
1247 | else | |
1248 | { | |
1249 | as_bad (_ | |
1250 | ("unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "), | |
1251 | l); | |
1252 | return 1; | |
1253 | } | |
2469cfa2 | 1254 | |
b18c562e NC |
1255 | if (x == 0) |
1256 | { | |
1257 | op->reg = 3; | |
1258 | op->am = 0; | |
1259 | op->ol = 0; | |
1260 | op->mode = OP_REG; | |
1261 | } | |
1262 | else if (x == 1) | |
1263 | { | |
1264 | op->reg = 3; | |
1265 | op->am = 1; | |
1266 | op->ol = 0; | |
1267 | op->mode = OP_REG; | |
1268 | } | |
1269 | else if (x == 2) | |
1270 | { | |
1271 | op->reg = 3; | |
1272 | op->am = 2; | |
1273 | op->ol = 0; | |
1274 | op->mode = OP_REG; | |
1275 | } | |
1276 | else if (x == -1) | |
1277 | { | |
1278 | op->reg = 3; | |
1279 | op->am = 3; | |
1280 | op->ol = 0; | |
1281 | op->mode = OP_REG; | |
1282 | } | |
1283 | else if (x == 4) | |
1284 | { | |
1285 | op->reg = 2; | |
1286 | op->am = 2; | |
1287 | op->ol = 0; | |
1288 | op->mode = OP_REG; | |
1289 | } | |
1290 | else if (x == 8) | |
1291 | { | |
1292 | op->reg = 2; | |
1293 | op->am = 3; | |
1294 | op->ol = 0; | |
1295 | op->mode = OP_REG; | |
1296 | } | |
1297 | } | |
79cf5950 | 1298 | /* Redundant (yet) check. */ |
b18c562e NC |
1299 | else if (op->exp.X_op == O_register) |
1300 | as_bad | |
1301 | (_("Registers cannot be used within immediate expression [%s]"), l); | |
1302 | else | |
1303 | as_bad (_("unknown operand %s"), l); | |
2469cfa2 | 1304 | |
b18c562e NC |
1305 | return 0; |
1306 | } | |
2469cfa2 | 1307 | |
b18c562e NC |
1308 | /* Check if absolute &VALUE (assume that we can construct something like ((a&b)<<7 + 25). */ |
1309 | if (*l == '&') | |
1310 | { | |
1311 | char *h = l; | |
2469cfa2 | 1312 | |
b18c562e NC |
1313 | op->reg = 2; /* reg 2 in absolute addr mode. */ |
1314 | op->am = 1; /* mode As == 01 bin. */ | |
1315 | op->ol = 1; /* Immediate value followed by instruction. */ | |
1316 | __tl = h + 1; | |
1317 | parse_exp (__tl, &(op->exp)); | |
1318 | op->mode = OP_EXP; | |
00b32ff2 | 1319 | op->vshift = 0; |
b18c562e | 1320 | if (op->exp.X_op == O_constant) |
2469cfa2 | 1321 | { |
b18c562e | 1322 | int x = op->exp.X_add_number; |
2469cfa2 | 1323 | |
13761a11 NC |
1324 | if (allow_20bit_values) |
1325 | { | |
1326 | if (x > 0xfffff || x < -(0x7ffff)) | |
1327 | { | |
1328 | as_bad (_("value 0x%x out of extended range."), x); | |
1329 | return 1; | |
1330 | } | |
1331 | } | |
1332 | else if (x > 65535 || x < -32768) | |
b18c562e | 1333 | { |
13761a11 | 1334 | as_bad (_("value out of range: 0x%x"), x); |
b18c562e NC |
1335 | return 1; |
1336 | } | |
2469cfa2 | 1337 | } |
b18c562e NC |
1338 | else if (op->exp.X_op == O_symbol) |
1339 | ; | |
1340 | else | |
2469cfa2 | 1341 | { |
79cf5950 | 1342 | /* Redundant (yet) check. */ |
b18c562e NC |
1343 | if (op->exp.X_op == O_register) |
1344 | as_bad | |
1345 | (_("Registers cannot be used within absolute expression [%s]"), l); | |
2469cfa2 | 1346 | else |
b18c562e NC |
1347 | as_bad (_("unknown expression in operand %s"), l); |
1348 | return 1; | |
2469cfa2 | 1349 | } |
b18c562e NC |
1350 | return 0; |
1351 | } | |
2469cfa2 | 1352 | |
b18c562e NC |
1353 | /* Check if indirect register mode @Rn / postincrement @Rn+. */ |
1354 | if (*l == '@') | |
1355 | { | |
1356 | char *t = l; | |
1357 | char *m = strchr (l, '+'); | |
1358 | ||
1359 | if (t != l) | |
2469cfa2 | 1360 | { |
b18c562e NC |
1361 | as_bad (_("unknown addressing mode %s"), l); |
1362 | return 1; | |
2469cfa2 NC |
1363 | } |
1364 | ||
b18c562e | 1365 | t++; |
2469cfa2 | 1366 | |
13761a11 | 1367 | if ((op->reg = check_reg (t)) == -1) |
2469cfa2 | 1368 | { |
13761a11 | 1369 | as_bad (_("Bad register name %s"), t); |
b18c562e | 1370 | return 1; |
2469cfa2 | 1371 | } |
2469cfa2 | 1372 | |
b18c562e NC |
1373 | op->mode = OP_REG; |
1374 | op->am = m ? 3 : 2; | |
1375 | op->ol = 0; | |
2469cfa2 | 1376 | |
d1706f38 NC |
1377 | /* PC cannot be used in indirect addressing. */ |
1378 | if (target_is_430xv2 () && op->reg == 0) | |
1379 | { | |
1380 | as_bad (_("cannot use indirect addressing with the PC")); | |
1381 | return 1; | |
1382 | } | |
65d7bab5 | 1383 | |
b18c562e NC |
1384 | return 0; |
1385 | } | |
2469cfa2 | 1386 | |
b18c562e NC |
1387 | /* Check if register indexed X(Rn). */ |
1388 | do | |
1389 | { | |
1390 | char *h = strrchr (l, '('); | |
1391 | char *m = strrchr (l, ')'); | |
1392 | char *t; | |
2469cfa2 | 1393 | |
00b32ff2 | 1394 | *imm_op = TRUE; |
2469cfa2 | 1395 | |
b18c562e NC |
1396 | if (!h) |
1397 | break; | |
1398 | if (!m) | |
1399 | { | |
1400 | as_bad (_("')' required")); | |
1401 | return 1; | |
1402 | } | |
2469cfa2 | 1403 | |
b18c562e NC |
1404 | t = h; |
1405 | op->am = 1; | |
1406 | op->ol = 1; | |
2469cfa2 | 1407 | |
13761a11 NC |
1408 | /* Extract a register. */ |
1409 | if ((op->reg = check_reg (t + 1)) == -1) | |
b18c562e NC |
1410 | { |
1411 | as_bad (_ | |
1412 | ("unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"), | |
1413 | l); | |
1414 | return 1; | |
1415 | } | |
2469cfa2 | 1416 | |
13761a11 | 1417 | if (op->reg == 2) |
b18c562e | 1418 | { |
13761a11 | 1419 | as_bad (_("r2 should not be used in indexed addressing mode")); |
b18c562e NC |
1420 | return 1; |
1421 | } | |
b18c562e NC |
1422 | |
1423 | /* Extract constant. */ | |
1424 | __tl = l; | |
1425 | *h = 0; | |
1426 | op->mode = OP_EXP; | |
00b32ff2 | 1427 | op->vshift = 0; |
b18c562e NC |
1428 | parse_exp (__tl, &(op->exp)); |
1429 | if (op->exp.X_op == O_constant) | |
1430 | { | |
1431 | int x = op->exp.X_add_number; | |
1432 | ||
13761a11 NC |
1433 | if (allow_20bit_values) |
1434 | { | |
1435 | if (x > 0xfffff || x < - (0x7ffff)) | |
1436 | { | |
1437 | as_bad (_("value 0x%x out of extended range."), x); | |
1438 | return 1; | |
1439 | } | |
1440 | } | |
1441 | else if (x > 65535 || x < -32768) | |
2469cfa2 | 1442 | { |
13761a11 | 1443 | as_bad (_("value out of range: 0x%x"), x); |
b18c562e | 1444 | return 1; |
2469cfa2 | 1445 | } |
b18c562e NC |
1446 | |
1447 | if (x == 0) | |
2469cfa2 | 1448 | { |
b18c562e NC |
1449 | op->mode = OP_REG; |
1450 | op->am = 2; | |
1451 | op->ol = 0; | |
1452 | return 0; | |
2469cfa2 NC |
1453 | } |
1454 | } | |
b18c562e NC |
1455 | else if (op->exp.X_op == O_symbol) |
1456 | ; | |
2469cfa2 NC |
1457 | else |
1458 | { | |
79cf5950 | 1459 | /* Redundant (yet) check. */ |
b18c562e NC |
1460 | if (op->exp.X_op == O_register) |
1461 | as_bad | |
1462 | (_("Registers cannot be used as a prefix of indexed expression [%s]"), l); | |
1463 | else | |
1464 | as_bad (_("unknown expression in operand %s"), l); | |
1465 | return 1; | |
2469cfa2 | 1466 | } |
2469cfa2 | 1467 | |
b18c562e | 1468 | return 0; |
2469cfa2 | 1469 | } |
b18c562e | 1470 | while (0); |
2469cfa2 | 1471 | |
13761a11 NC |
1472 | /* Possibly register mode 'mov r1,r2'. */ |
1473 | if ((op->reg = check_reg (l)) != -1) | |
b18c562e | 1474 | { |
13761a11 NC |
1475 | op->mode = OP_REG; |
1476 | op->am = 0; | |
1477 | op->ol = 0; | |
1478 | return 0; | |
b18c562e | 1479 | } |
b18c562e NC |
1480 | |
1481 | /* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */ | |
1482 | do | |
1483 | { | |
b18c562e NC |
1484 | op->mode = OP_EXP; |
1485 | op->reg = 0; /* PC relative... be careful. */ | |
13761a11 NC |
1486 | /* An expression starting with a minus sign is a constant, not an address. */ |
1487 | op->am = (*l == '-' ? 3 : 1); | |
b18c562e | 1488 | op->ol = 1; |
00b32ff2 | 1489 | op->vshift = 0; |
b18c562e NC |
1490 | __tl = l; |
1491 | parse_exp (__tl, &(op->exp)); | |
1492 | return 0; | |
1493 | } | |
1494 | while (0); | |
1495 | ||
1496 | /* Unreachable. */ | |
1497 | as_bad (_("unknown addressing mode for operand %s"), l); | |
1498 | return 1; | |
2469cfa2 NC |
1499 | } |
1500 | ||
b18c562e | 1501 | |
2469cfa2 | 1502 | static int |
13761a11 NC |
1503 | msp430_dstoperand (struct msp430_operand_s * op, |
1504 | char * l, | |
1505 | int bin, | |
1506 | bfd_boolean allow_20bit_values, | |
1507 | bfd_boolean constants_allowed) | |
2469cfa2 NC |
1508 | { |
1509 | int dummy; | |
13761a11 NC |
1510 | int ret = msp430_srcoperand (op, l, bin, & dummy, |
1511 | allow_20bit_values, | |
1512 | constants_allowed); | |
b18c562e | 1513 | |
2469cfa2 NC |
1514 | if (ret) |
1515 | return ret; | |
1516 | ||
1517 | if (op->am == 2) | |
1518 | { | |
1519 | char *__tl = "0"; | |
1520 | ||
1521 | op->mode = OP_EXP; | |
1522 | op->am = 1; | |
1523 | op->ol = 1; | |
00b32ff2 | 1524 | op->vshift = 0; |
2469cfa2 | 1525 | parse_exp (__tl, &(op->exp)); |
b18c562e | 1526 | |
2469cfa2 NC |
1527 | if (op->exp.X_op != O_constant || op->exp.X_add_number != 0) |
1528 | { | |
1529 | as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"), | |
1530 | op->reg, op->reg); | |
1531 | return 1; | |
1532 | } | |
1533 | return 0; | |
1534 | } | |
1535 | ||
1536 | if (op->am > 1) | |
1537 | { | |
1538 | as_bad (_ | |
1539 | ("this addressing mode is not applicable for destination operand")); | |
1540 | return 1; | |
1541 | } | |
1542 | return 0; | |
1543 | } | |
1544 | ||
13761a11 NC |
1545 | /* Attempt to encode a MOVA instruction with the given operands. |
1546 | Returns the length of the encoded instruction if successful | |
1547 | or 0 upon failure. If the encoding fails, an error message | |
1548 | will be returned if a pointer is provided. */ | |
1549 | ||
1550 | static int | |
1551 | try_encode_mova (bfd_boolean imm_op, | |
1552 | int bin, | |
1553 | struct msp430_operand_s * op1, | |
1554 | struct msp430_operand_s * op2, | |
1555 | const char ** error_message_return) | |
1556 | { | |
1557 | short ZEROS = 0; | |
1558 | char *frag; | |
1559 | int where; | |
1560 | ||
1561 | /* Only a restricted subset of the normal MSP430 addressing modes | |
1562 | are supported here, so check for the ones that are allowed. */ | |
1563 | if (imm_op) | |
1564 | { | |
1565 | if (op1->mode == OP_EXP) | |
1566 | { | |
1567 | if (op2->mode != OP_REG) | |
1568 | { | |
1569 | if (error_message_return != NULL) | |
1570 | * error_message_return = _("expected register as second argument of %s"); | |
1571 | return 0; | |
1572 | } | |
1573 | ||
1574 | if (op1->am == 3) | |
1575 | { | |
1576 | /* MOVA #imm20, Rdst. */ | |
1577 | bin |= 0x80 | op2->reg; | |
1578 | frag = frag_more (4); | |
1579 | where = frag - frag_now->fr_literal; | |
1580 | if (op1->exp.X_op == O_constant) | |
1581 | { | |
1582 | bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8; | |
1583 | bfd_putl16 ((bfd_vma) bin, frag); | |
1584 | bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2); | |
1585 | } | |
1586 | else | |
1587 | { | |
1588 | bfd_putl16 ((bfd_vma) bin, frag); | |
1589 | fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE, | |
1590 | BFD_RELOC_MSP430X_ABS20_ADR_SRC); | |
1591 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); | |
1592 | } | |
1593 | ||
1594 | return 4; | |
1595 | } | |
1596 | else if (op1->am == 1) | |
1597 | { | |
1598 | /* MOVA z16(Rsrc), Rdst. */ | |
1599 | bin |= 0x30 | (op1->reg << 8) | op2->reg; | |
1600 | frag = frag_more (4); | |
1601 | where = frag - frag_now->fr_literal; | |
1602 | bfd_putl16 ((bfd_vma) bin, frag); | |
1603 | if (op1->exp.X_op == O_constant) | |
1604 | { | |
1605 | if (op1->exp.X_add_number > 0xffff | |
1606 | || op1->exp.X_add_number < -(0x7fff)) | |
1607 | { | |
1608 | if (error_message_return != NULL) | |
1609 | * error_message_return = _("index value too big for %s"); | |
1610 | return 0; | |
1611 | } | |
1612 | bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2); | |
1613 | } | |
1614 | else | |
1615 | { | |
1616 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); | |
1617 | fix_new_exp (frag_now, where + 2, 2, &(op1->exp), FALSE, | |
1618 | op1->reg == 0 ? | |
1619 | BFD_RELOC_MSP430X_PCR16 : | |
1620 | BFD_RELOC_MSP430X_ABS16); | |
1621 | } | |
1622 | return 4; | |
1623 | } | |
1624 | ||
1625 | if (error_message_return != NULL) | |
1626 | * error_message_return = _("unexpected addressing mode for %s"); | |
1627 | return 0; | |
1628 | } | |
1629 | else if (op1->am == 0) | |
1630 | { | |
1631 | /* MOVA Rsrc, ... */ | |
1632 | if (op2->mode == OP_REG) | |
1633 | { | |
1634 | bin |= 0xc0 | (op1->reg << 8) | op2->reg; | |
1635 | frag = frag_more (2); | |
1636 | where = frag - frag_now->fr_literal; | |
1637 | bfd_putl16 ((bfd_vma) bin, frag); | |
1638 | return 2; | |
1639 | } | |
1640 | else if (op2->am == 1) | |
1641 | { | |
1642 | if (op2->reg == 2) | |
1643 | { | |
1644 | /* MOVA Rsrc, &abs20. */ | |
1645 | bin |= 0x60 | (op1->reg << 8); | |
1646 | frag = frag_more (4); | |
1647 | where = frag - frag_now->fr_literal; | |
1648 | if (op2->exp.X_op == O_constant) | |
1649 | { | |
1650 | bin |= (op2->exp.X_add_number >> 16) & 0xf; | |
1651 | bfd_putl16 ((bfd_vma) bin, frag); | |
1652 | bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2); | |
1653 | } | |
1654 | else | |
1655 | { | |
1656 | bfd_putl16 ((bfd_vma) bin, frag); | |
1657 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); | |
1658 | fix_new_exp (frag_now, where, 4, &(op2->exp), FALSE, | |
1659 | BFD_RELOC_MSP430X_ABS20_ADR_DST); | |
1660 | } | |
1661 | return 4; | |
1662 | } | |
1663 | ||
1664 | /* MOVA Rsrc, z16(Rdst). */ | |
1665 | bin |= 0x70 | (op1->reg << 8) | op2->reg; | |
1666 | frag = frag_more (4); | |
1667 | where = frag - frag_now->fr_literal; | |
1668 | bfd_putl16 ((bfd_vma) bin, frag); | |
1669 | if (op2->exp.X_op == O_constant) | |
1670 | { | |
1671 | if (op2->exp.X_add_number > 0xffff | |
1672 | || op2->exp.X_add_number < -(0x7fff)) | |
1673 | { | |
1674 | if (error_message_return != NULL) | |
1675 | * error_message_return = _("index value too big for %s"); | |
1676 | return 0; | |
1677 | } | |
1678 | bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2); | |
1679 | } | |
1680 | else | |
1681 | { | |
1682 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); | |
1683 | fix_new_exp (frag_now, where + 2, 2, &(op2->exp), FALSE, | |
1684 | op2->reg == 0 ? | |
1685 | BFD_RELOC_MSP430X_PCR16 : | |
1686 | BFD_RELOC_MSP430X_ABS16); | |
1687 | } | |
1688 | return 4; | |
1689 | } | |
1690 | ||
1691 | if (error_message_return != NULL) | |
1692 | * error_message_return = _("unexpected addressing mode for %s"); | |
1693 | return 0; | |
1694 | } | |
1695 | } | |
1696 | ||
1697 | /* imm_op == FALSE. */ | |
1698 | ||
1699 | if (op1->reg == 2 && op1->am == 1 && op1->mode == OP_EXP) | |
1700 | { | |
1701 | /* MOVA &abs20, Rdst. */ | |
1702 | if (op2->mode != OP_REG) | |
1703 | { | |
1704 | if (error_message_return != NULL) | |
1705 | * error_message_return = _("expected register as second argument of %s"); | |
1706 | return 0; | |
1707 | } | |
1708 | ||
1709 | if (op2->reg == 2 || op2->reg == 3) | |
1710 | { | |
1711 | if (error_message_return != NULL) | |
1712 | * error_message_return = _("constant generator destination register found in %s"); | |
1713 | return 0; | |
1714 | } | |
1715 | ||
1716 | bin |= 0x20 | op2->reg; | |
1717 | frag = frag_more (4); | |
1718 | where = frag - frag_now->fr_literal; | |
1719 | if (op1->exp.X_op == O_constant) | |
1720 | { | |
1721 | bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8; | |
1722 | bfd_putl16 ((bfd_vma) bin, frag); | |
1723 | bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2); | |
1724 | } | |
1725 | else | |
1726 | { | |
1727 | bfd_putl16 ((bfd_vma) bin, frag); | |
1728 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); | |
1729 | fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE, | |
1730 | BFD_RELOC_MSP430X_ABS20_ADR_SRC); | |
1731 | } | |
1732 | return 4; | |
1733 | } | |
1734 | else if (op1->mode == OP_REG) | |
1735 | { | |
1736 | if (op1->am == 3) | |
1737 | { | |
1738 | /* MOVA @Rsrc+, Rdst. */ | |
1739 | if (op2->mode != OP_REG) | |
1740 | { | |
1741 | if (error_message_return != NULL) | |
1742 | * error_message_return = _("expected register as second argument of %s"); | |
1743 | return 0; | |
1744 | } | |
1745 | ||
1746 | if (op2->reg == 2 || op2->reg == 3) | |
1747 | { | |
1748 | if (error_message_return != NULL) | |
1749 | * error_message_return = _("constant generator destination register found in %s"); | |
1750 | return 0; | |
1751 | } | |
1752 | ||
1753 | if (op1->reg == 2 || op1->reg == 3) | |
1754 | { | |
1755 | if (error_message_return != NULL) | |
1756 | * error_message_return = _("constant generator source register found in %s"); | |
1757 | return 0; | |
1758 | } | |
1759 | ||
1760 | bin |= 0x10 | (op1->reg << 8) | op2->reg; | |
1761 | frag = frag_more (2); | |
1762 | where = frag - frag_now->fr_literal; | |
1763 | bfd_putl16 ((bfd_vma) bin, frag); | |
1764 | return 2; | |
1765 | } | |
1766 | else if (op1->am == 2) | |
1767 | { | |
1768 | /* MOVA @Rsrc,Rdst */ | |
1769 | if (op2->mode != OP_REG) | |
1770 | { | |
1771 | if (error_message_return != NULL) | |
1772 | * error_message_return = _("expected register as second argument of %s"); | |
1773 | return 0; | |
1774 | } | |
1775 | ||
1776 | if (op2->reg == 2 || op2->reg == 3) | |
1777 | { | |
1778 | if (error_message_return != NULL) | |
1779 | * error_message_return = _("constant generator destination register found in %s"); | |
1780 | return 0; | |
1781 | } | |
1782 | ||
1783 | if (op1->reg == 2 || op1->reg == 3) | |
1784 | { | |
1785 | if (error_message_return != NULL) | |
1786 | * error_message_return = _("constant generator source register found in %s"); | |
1787 | return 0; | |
1788 | } | |
1789 | ||
1790 | bin |= (op1->reg << 8) | op2->reg; | |
1791 | frag = frag_more (2); | |
1792 | where = frag - frag_now->fr_literal; | |
1793 | bfd_putl16 ((bfd_vma) bin, frag); | |
1794 | return 2; | |
1795 | } | |
1796 | } | |
1797 | ||
1798 | if (error_message_return != NULL) | |
1799 | * error_message_return = _("unexpected addressing mode for %s"); | |
1800 | ||
1801 | return 0; | |
1802 | } | |
1803 | ||
65d7bab5 NC |
1804 | static bfd_boolean check_for_nop = FALSE; |
1805 | ||
638d3803 NC |
1806 | #define is_opcode(NAME) (strcmp (opcode->name, NAME) == 0) |
1807 | ||
b18c562e NC |
1808 | /* Parse instruction operands. |
1809 | Return binary opcode. */ | |
1810 | ||
1811 | static unsigned int | |
1812 | msp430_operands (struct msp430_opcode_s * opcode, char * line) | |
2469cfa2 | 1813 | { |
b18c562e | 1814 | int bin = opcode->bin_opcode; /* Opcode mask. */ |
13761a11 | 1815 | int insn_length = 0; |
b18c562e NC |
1816 | char l1[MAX_OP_LEN], l2[MAX_OP_LEN]; |
1817 | char *frag; | |
1818 | int where; | |
1819 | struct msp430_operand_s op1, op2; | |
1820 | int res = 0; | |
1821 | static short ZEROS = 0; | |
00b32ff2 | 1822 | bfd_boolean byte_op, imm_op; |
13761a11 NC |
1823 | int op_length = 0; |
1824 | int fmt; | |
1825 | int extended = 0x1800; | |
1826 | bfd_boolean extended_op = FALSE; | |
1827 | bfd_boolean addr_op; | |
1828 | const char * error_message; | |
1829 | static signed int repeat_count = 0; | |
1830 | bfd_boolean fix_emitted; | |
65d7bab5 | 1831 | bfd_boolean nop_check_needed = FALSE; |
2469cfa2 | 1832 | |
b18c562e NC |
1833 | /* Opcode is the one from opcodes table |
1834 | line contains something like | |
1835 | [.w] @r2+, 5(R1) | |
1836 | or | |
1837 | .b @r2+, 5(R1). */ | |
2469cfa2 | 1838 | |
00b32ff2 | 1839 | byte_op = FALSE; |
38d77545 NC |
1840 | addr_op = FALSE; |
1841 | if (*line == '.') | |
2469cfa2 | 1842 | { |
38d77545 NC |
1843 | bfd_boolean check = FALSE; |
1844 | ++ line; | |
1845 | ||
1846 | switch (TOLOWER (* line)) | |
1847 | { | |
1848 | case 'b': | |
1849 | /* Byte operation. */ | |
1850 | bin |= BYTE_OPERATION; | |
00b32ff2 | 1851 | byte_op = TRUE; |
38d77545 NC |
1852 | check = TRUE; |
1853 | break; | |
1854 | ||
1855 | case 'a': | |
1856 | /* "Address" ops work on 20-bit values. */ | |
1857 | addr_op = TRUE; | |
1858 | bin |= BYTE_OPERATION; | |
1859 | check = TRUE; | |
1860 | break; | |
1861 | ||
1862 | case 'w': | |
1863 | /* Word operation - this is the default. */ | |
1864 | check = TRUE; | |
1865 | break; | |
1866 | ||
1867 | case 0: | |
1868 | case ' ': | |
1869 | case '\n': | |
1870 | case '\r': | |
1871 | as_warn (_("no size modifier after period, .w assumed")); | |
1872 | break; | |
1873 | ||
1874 | default: | |
1875 | as_bad (_("unrecognised instruction size modifier .%c"), | |
1876 | * line); | |
1877 | return 0; | |
1878 | } | |
1879 | ||
1880 | if (check) | |
1881 | { | |
1882 | ++ line; | |
1883 | ||
1884 | } | |
2469cfa2 NC |
1885 | } |
1886 | ||
38d77545 | 1887 | if (*line && ! ISSPACE (*line)) |
13761a11 | 1888 | { |
38d77545 NC |
1889 | as_bad (_("junk found after instruction: %s.%s"), |
1890 | opcode->name, line); | |
1891 | return 0; | |
13761a11 | 1892 | } |
13761a11 | 1893 | |
38d77545 NC |
1894 | /* Catch the case where the programmer has used a ".a" size modifier on an |
1895 | instruction that does not support it. Look for an alternative extended | |
1896 | instruction that has the same name without the period. Eg: "add.a" | |
1897 | becomes "adda". Although this not an officially supported way of | |
1898 | specifing instruction aliases other MSP430 assemblers allow it. So we | |
1899 | support it for compatibility purposes. */ | |
1900 | if (addr_op && opcode->fmt >= 0) | |
1901 | { | |
1902 | char * old_name = opcode->name; | |
1903 | char real_name[32]; | |
1904 | ||
1905 | sprintf (real_name, "%sa", old_name); | |
1906 | opcode = hash_find (msp430_hash, real_name); | |
1907 | if (opcode == NULL) | |
1908 | { | |
1909 | as_bad (_("instruction %s.a does not exist"), old_name); | |
1910 | return 0; | |
1911 | } | |
1912 | #if 0 /* Enable for debugging. */ | |
1913 | as_warn ("treating %s.a as %s", old_name, real_name); | |
1914 | #endif | |
1915 | addr_op = FALSE; | |
1916 | bin = opcode->bin_opcode; | |
1917 | } | |
2469cfa2 | 1918 | |
13761a11 NC |
1919 | if (opcode->fmt != -1 |
1920 | && opcode->insn_opnumb | |
1921 | && (!*line || *line == '\n')) | |
2469cfa2 | 1922 | { |
b18c562e NC |
1923 | as_bad (_("instruction %s requires %d operand(s)"), |
1924 | opcode->name, opcode->insn_opnumb); | |
1925 | return 0; | |
1926 | } | |
2469cfa2 | 1927 | |
b18c562e NC |
1928 | memset (l1, 0, sizeof (l1)); |
1929 | memset (l2, 0, sizeof (l2)); | |
1930 | memset (&op1, 0, sizeof (op1)); | |
1931 | memset (&op2, 0, sizeof (op2)); | |
2469cfa2 | 1932 | |
00b32ff2 | 1933 | imm_op = FALSE; |
2469cfa2 | 1934 | |
13761a11 NC |
1935 | if ((fmt = opcode->fmt) < 0) |
1936 | { | |
638d3803 | 1937 | if (! target_is_430x ()) |
13761a11 NC |
1938 | { |
1939 | as_bad (_("instruction %s requires MSP430X mcu"), | |
1940 | opcode->name); | |
1941 | return 0; | |
1942 | } | |
638d3803 | 1943 | |
13761a11 NC |
1944 | fmt = (-fmt) - 1; |
1945 | extended_op = TRUE; | |
1946 | } | |
1947 | ||
1948 | if (repeat_count) | |
1949 | { | |
1950 | /* If requested set the extended instruction repeat count. */ | |
1951 | if (extended_op) | |
1952 | { | |
1953 | if (repeat_count > 0) | |
1954 | extended |= (repeat_count - 1); | |
1955 | else | |
1956 | extended |= (1 << 7) | (- repeat_count); | |
1957 | } | |
1958 | else | |
1959 | as_bad (_("unable to repeat %s insn"), opcode->name); | |
1960 | ||
1961 | repeat_count = 0; | |
1962 | } | |
1963 | ||
65d7bab5 NC |
1964 | if (check_for_nop && is_opcode ("nop")) |
1965 | check_for_nop = FALSE; | |
1966 | ||
13761a11 | 1967 | switch (fmt) |
b18c562e NC |
1968 | { |
1969 | case 0: /* Emulated. */ | |
1970 | switch (opcode->insn_opnumb) | |
2469cfa2 | 1971 | { |
b18c562e | 1972 | case 0: |
65d7bab5 NC |
1973 | if (is_opcode ("eint") || is_opcode ("dint")) |
1974 | { | |
1975 | if (check_for_nop) | |
1976 | { | |
1977 | if (warn_interrupt_nops) | |
1978 | { | |
1979 | if (gen_interrupt_nops) | |
1980 | as_warn (_("NOP inserted between two instructions that change interrupt state")); | |
1981 | else | |
1982 | as_warn (_("a NOP might be needed here because of successive changes in interrupt state")); | |
1983 | } | |
1984 | ||
1985 | if (gen_interrupt_nops) | |
1986 | { | |
1987 | /* Emit a NOP between interrupt enable/disable. | |
1988 | See 1.3.4.1 of the MSP430x5xx User Guide. */ | |
1989 | insn_length += 2; | |
1990 | frag = frag_more (2); | |
1991 | bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag); | |
1992 | } | |
1993 | } | |
1994 | ||
1995 | nop_check_needed = TRUE; | |
1996 | } | |
1997 | ||
b18c562e | 1998 | /* Set/clear bits instructions. */ |
13761a11 NC |
1999 | if (extended_op) |
2000 | { | |
2001 | if (!addr_op) | |
2002 | extended |= BYTE_OPERATION; | |
2003 | ||
2004 | /* Emit the extension word. */ | |
2005 | insn_length += 2; | |
65d7bab5 | 2006 | frag = frag_more (2); |
13761a11 NC |
2007 | bfd_putl16 (extended, frag); |
2008 | } | |
638d3803 | 2009 | |
13761a11 | 2010 | insn_length += 2; |
65d7bab5 | 2011 | frag = frag_more (2); |
b18c562e | 2012 | bfd_putl16 ((bfd_vma) bin, frag); |
13761a11 | 2013 | dwarf2_emit_insn (insn_length); |
b18c562e | 2014 | break; |
13761a11 | 2015 | |
b18c562e NC |
2016 | case 1: |
2017 | /* Something which works with destination operand. */ | |
2018 | line = extract_operand (line, l1, sizeof (l1)); | |
13761a11 | 2019 | res = msp430_dstoperand (&op1, l1, opcode->bin_opcode, extended_op, TRUE); |
b18c562e NC |
2020 | if (res) |
2021 | break; | |
2469cfa2 | 2022 | |
65d7bab5 NC |
2023 | bin |= (op1.reg | (op1.am << 7)); |
2024 | ||
2025 | if (is_opcode ("clr") && bin == 0x4302 /* CLR R2*/) | |
2026 | { | |
2027 | if (check_for_nop) | |
2028 | { | |
2029 | if (warn_interrupt_nops) | |
2030 | { | |
2031 | if (gen_interrupt_nops) | |
2032 | as_warn (_("NOP inserted between two instructions that change interrupt state")); | |
2033 | else | |
2034 | as_warn (_("a NOP might be needed here because of successive changes in interrupt state")); | |
2035 | } | |
2036 | ||
2037 | if (gen_interrupt_nops) | |
2038 | { | |
2039 | /* Emit a NOP between interrupt enable/disable. | |
2040 | See 1.3.4.1 of the MSP430x5xx User Guide. */ | |
2041 | insn_length += 2; | |
2042 | frag = frag_more (2); | |
2043 | bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag); | |
2044 | } | |
2045 | } | |
2046 | ||
2047 | nop_check_needed = TRUE; | |
2048 | } | |
2049 | ||
13761a11 | 2050 | /* Compute the entire instruction length, in bytes. */ |
65d7bab5 NC |
2051 | op_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2); |
2052 | insn_length += op_length; | |
2053 | frag = frag_more (op_length); | |
b18c562e | 2054 | where = frag - frag_now->fr_literal; |
38d77545 | 2055 | |
13761a11 | 2056 | if (extended_op) |
2469cfa2 | 2057 | { |
13761a11 NC |
2058 | if (!addr_op) |
2059 | extended |= BYTE_OPERATION; | |
2060 | ||
2061 | if (op1.ol != 0 && ((extended & 0xf) != 0)) | |
2062 | { | |
2063 | as_bad (_("repeat instruction used with non-register mode instruction")); | |
2064 | extended &= ~ 0xf; | |
2065 | } | |
38d77545 | 2066 | |
13761a11 NC |
2067 | if (op1.mode == OP_EXP) |
2068 | { | |
2069 | if (op1.exp.X_op == O_constant) | |
2070 | extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7; | |
2071 | ||
e66c3c25 | 2072 | else if (op1.reg || op1.am == 3) /* Not PC relative. */ |
13761a11 NC |
2073 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, |
2074 | BFD_RELOC_MSP430X_ABS20_EXT_SRC); | |
2075 | else | |
2076 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, | |
2077 | BFD_RELOC_MSP430X_PCR20_EXT_SRC); | |
2078 | } | |
38d77545 | 2079 | |
13761a11 NC |
2080 | /* Emit the extension word. */ |
2081 | bfd_putl16 (extended, frag); | |
2082 | frag += 2; | |
2083 | where += 2; | |
2084 | } | |
2085 | ||
13761a11 NC |
2086 | bfd_putl16 ((bfd_vma) bin, frag); |
2087 | frag += 2; | |
2088 | where += 2; | |
2089 | ||
2090 | if (op1.mode == OP_EXP) | |
2091 | { | |
2092 | if (op1.exp.X_op == O_constant) | |
2093 | { | |
2094 | bfd_putl16 (op1.exp.X_add_number & 0xffff, frag); | |
2095 | } | |
2469cfa2 | 2096 | else |
13761a11 NC |
2097 | { |
2098 | bfd_putl16 ((bfd_vma) ZEROS, frag); | |
2099 | ||
2100 | if (!extended_op) | |
2101 | { | |
2102 | if (op1.reg) | |
2103 | fix_new_exp (frag_now, where, 2, | |
00b32ff2 | 2104 | &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1)); |
13761a11 NC |
2105 | else |
2106 | fix_new_exp (frag_now, where, 2, | |
2107 | &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
2108 | } | |
2109 | } | |
2110 | } | |
2111 | ||
13761a11 | 2112 | dwarf2_emit_insn (insn_length); |
b18c562e | 2113 | break; |
2469cfa2 | 2114 | |
b18c562e | 2115 | case 2: |
13761a11 NC |
2116 | /* Shift instruction. */ |
2117 | line = extract_operand (line, l1, sizeof (l1)); | |
2118 | strncpy (l2, l1, sizeof (l2)); | |
2119 | l2[sizeof (l2) - 1] = '\0'; | |
2120 | res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE); | |
2121 | res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE); | |
2122 | ||
2123 | if (res) | |
2124 | break; /* An error occurred. All warnings were done before. */ | |
2125 | ||
2126 | insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2) + (op2.ol * 2); | |
2127 | frag = frag_more (insn_length); | |
2128 | where = frag - frag_now->fr_literal; | |
2129 | ||
d1706f38 NC |
2130 | if (target_is_430xv2 () |
2131 | && op1.mode == OP_REG | |
38d77545 | 2132 | && op1.reg == 0 |
638d3803 NC |
2133 | && (is_opcode ("rlax") |
2134 | || is_opcode ("rlcx") | |
2135 | || is_opcode ("rla") | |
2136 | || is_opcode ("rlc"))) | |
2137 | { | |
2138 | as_bad (_("%s: attempt to rotate the PC register"), opcode->name); | |
65d7bab5 | 2139 | break; |
638d3803 | 2140 | } |
38d77545 | 2141 | |
13761a11 NC |
2142 | if (extended_op) |
2143 | { | |
2144 | if (!addr_op) | |
2145 | extended |= BYTE_OPERATION; | |
2146 | ||
2147 | if ((op1.ol != 0 || op2.ol != 0) && ((extended & 0xf) != 0)) | |
2148 | { | |
2149 | as_bad (_("repeat instruction used with non-register mode instruction")); | |
2150 | extended &= ~ 0xf; | |
2151 | } | |
38d77545 | 2152 | |
13761a11 NC |
2153 | if (op1.mode == OP_EXP) |
2154 | { | |
2155 | if (op1.exp.X_op == O_constant) | |
2156 | extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7; | |
2157 | ||
e66c3c25 | 2158 | else if (op1.reg || op1.am == 3) /* Not PC relative. */ |
13761a11 NC |
2159 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, |
2160 | BFD_RELOC_MSP430X_ABS20_EXT_SRC); | |
2161 | else | |
2162 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, | |
2163 | BFD_RELOC_MSP430X_PCR20_EXT_SRC); | |
2164 | } | |
2165 | ||
2166 | if (op2.mode == OP_EXP) | |
2167 | { | |
2168 | if (op2.exp.X_op == O_constant) | |
2169 | extended |= (op2.exp.X_add_number >> 16) & 0xf; | |
2170 | ||
2171 | else if (op1.mode == OP_EXP) | |
2172 | fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE, | |
2173 | op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST | |
2174 | : BFD_RELOC_MSP430X_PCR20_EXT_ODST); | |
2175 | else | |
2176 | fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE, | |
2177 | op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST | |
2178 | : BFD_RELOC_MSP430X_PCR20_EXT_DST); | |
2179 | } | |
2180 | ||
2181 | /* Emit the extension word. */ | |
2182 | bfd_putl16 (extended, frag); | |
2183 | frag += 2; | |
2184 | where += 2; | |
2185 | } | |
2186 | ||
2187 | bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7)); | |
2188 | bfd_putl16 ((bfd_vma) bin, frag); | |
2189 | frag += 2; | |
2190 | where += 2; | |
2191 | ||
2192 | if (op1.mode == OP_EXP) | |
2193 | { | |
2194 | if (op1.exp.X_op == O_constant) | |
2195 | { | |
2196 | bfd_putl16 (op1.exp.X_add_number & 0xffff, frag); | |
2197 | } | |
2198 | else | |
2199 | { | |
2200 | bfd_putl16 ((bfd_vma) ZEROS, frag); | |
2201 | ||
2202 | if (!extended_op) | |
2203 | { | |
e66c3c25 | 2204 | if (op1.reg || op1.am == 3) /* Not PC relative. */ |
13761a11 | 2205 | fix_new_exp (frag_now, where, 2, |
00b32ff2 | 2206 | &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1)); |
13761a11 NC |
2207 | else |
2208 | fix_new_exp (frag_now, where, 2, | |
2209 | &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
2210 | } | |
2211 | } | |
2212 | frag += 2; | |
2213 | where += 2; | |
2214 | } | |
2215 | ||
2216 | if (op2.mode == OP_EXP) | |
2217 | { | |
2218 | if (op2.exp.X_op == O_constant) | |
2219 | { | |
2220 | bfd_putl16 (op2.exp.X_add_number & 0xffff, frag); | |
2221 | } | |
2222 | else | |
2223 | { | |
2224 | bfd_putl16 ((bfd_vma) ZEROS, frag); | |
2225 | ||
2226 | if (!extended_op) | |
2227 | { | |
2228 | if (op2.reg) /* Not PC relative. */ | |
2229 | fix_new_exp (frag_now, where, 2, | |
00b32ff2 | 2230 | &(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2)); |
13761a11 NC |
2231 | else |
2232 | fix_new_exp (frag_now, where, 2, | |
2233 | &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
2234 | } | |
2235 | } | |
2236 | } | |
2237 | ||
2238 | dwarf2_emit_insn (insn_length); | |
2239 | break; | |
2240 | ||
2241 | case 3: | |
2242 | /* Branch instruction => mov dst, r0. */ | |
2243 | if (extended_op) | |
2244 | { | |
2245 | as_bad ("Internal error: state 0/3 not coded for extended instructions"); | |
65d7bab5 | 2246 | break; |
13761a11 NC |
2247 | } |
2248 | ||
2249 | line = extract_operand (line, l1, sizeof (l1)); | |
2250 | res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, FALSE); | |
2251 | if (res) | |
2252 | break; | |
2253 | ||
00b32ff2 NC |
2254 | byte_op = FALSE; |
2255 | imm_op = FALSE; | |
13761a11 NC |
2256 | bin |= ((op1.reg << 8) | (op1.am << 4)); |
2257 | op_length = 2 + 2 * op1.ol; | |
2258 | frag = frag_more (op_length); | |
2259 | where = frag - frag_now->fr_literal; | |
2260 | bfd_putl16 ((bfd_vma) bin, frag); | |
2261 | ||
2262 | if (op1.mode == OP_EXP) | |
2263 | { | |
2264 | if (op1.exp.X_op == O_constant) | |
2265 | { | |
2266 | bfd_putl16 (op1.exp.X_add_number & 0xffff, frag + 2); | |
2267 | } | |
2268 | else | |
2269 | { | |
2270 | where += 2; | |
38d77545 | 2271 | |
13761a11 NC |
2272 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); |
2273 | ||
e66c3c25 | 2274 | if (op1.reg || op1.am == 3) |
13761a11 | 2275 | fix_new_exp (frag_now, where, 2, |
00b32ff2 | 2276 | &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1)); |
13761a11 NC |
2277 | else |
2278 | fix_new_exp (frag_now, where, 2, | |
2279 | &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
2280 | } | |
2281 | } | |
2282 | ||
2283 | dwarf2_emit_insn (insn_length + op_length); | |
2284 | break; | |
2285 | ||
2286 | case 4: | |
2287 | /* CALLA instructions. */ | |
2288 | fix_emitted = FALSE; | |
2289 | ||
2290 | line = extract_operand (line, l1, sizeof (l1)); | |
00b32ff2 | 2291 | imm_op = FALSE; |
13761a11 NC |
2292 | |
2293 | res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, | |
2294 | extended_op, FALSE); | |
2295 | if (res) | |
2296 | break; | |
2297 | ||
00b32ff2 | 2298 | byte_op = FALSE; |
13761a11 NC |
2299 | |
2300 | op_length = 2 + 2 * op1.ol; | |
2301 | frag = frag_more (op_length); | |
2302 | where = frag - frag_now->fr_literal; | |
2303 | ||
2304 | if (imm_op) | |
2305 | { | |
2306 | if (op1.am == 3) | |
2307 | { | |
2308 | bin |= 0xb0; | |
2309 | ||
2310 | fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE, | |
2311 | BFD_RELOC_MSP430X_ABS20_ADR_DST); | |
2312 | fix_emitted = TRUE; | |
2313 | } | |
2314 | else if (op1.am == 1) | |
2315 | { | |
2316 | if (op1.reg == 0) | |
2317 | { | |
2318 | bin |= 0x90; | |
2319 | ||
2320 | fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE, | |
2321 | BFD_RELOC_MSP430X_PCR20_CALL); | |
2322 | fix_emitted = TRUE; | |
2323 | } | |
2324 | else | |
2325 | bin |= 0x50 | op1.reg; | |
2326 | } | |
2327 | else if (op1.am == 0) | |
2328 | bin |= 0x40 | op1.reg; | |
2329 | } | |
2330 | else if (op1.am == 1) | |
2331 | { | |
2332 | bin |= 0x80; | |
2333 | ||
2334 | fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE, | |
2335 | BFD_RELOC_MSP430X_ABS20_ADR_DST); | |
2336 | fix_emitted = TRUE; | |
2337 | } | |
2338 | else if (op1.am == 2) | |
2339 | bin |= 0x60 | op1.reg; | |
2340 | else if (op1.am == 3) | |
2341 | bin |= 0x70 | op1.reg; | |
38d77545 | 2342 | |
13761a11 NC |
2343 | bfd_putl16 ((bfd_vma) bin, frag); |
2344 | ||
2345 | if (op1.mode == OP_EXP) | |
2346 | { | |
2347 | if (op1.ol != 1) | |
2348 | { | |
2349 | as_bad ("Internal error: unexpected CALLA instruction length: %d\n", op1.ol); | |
65d7bab5 | 2350 | break; |
13761a11 NC |
2351 | } |
2352 | ||
2353 | bfd_putl16 ((bfd_vma) ZEROS, frag + 2); | |
2354 | ||
2355 | if (! fix_emitted) | |
2356 | fix_new_exp (frag_now, where + 2, 2, | |
2357 | &(op1.exp), FALSE, BFD_RELOC_16); | |
2358 | } | |
2359 | ||
2360 | dwarf2_emit_insn (insn_length + op_length); | |
2361 | break; | |
2362 | ||
2363 | case 5: | |
b18c562e | 2364 | { |
13761a11 NC |
2365 | int n; |
2366 | int reg; | |
2367 | ||
2368 | /* [POP|PUSH]M[.A] #N, Rd */ | |
b18c562e | 2369 | line = extract_operand (line, l1, sizeof (l1)); |
13761a11 | 2370 | line = extract_operand (line, l2, sizeof (l2)); |
2469cfa2 | 2371 | |
13761a11 NC |
2372 | if (*l1 != '#') |
2373 | { | |
638d3803 | 2374 | as_bad (_("expected #n as first argument of %s"), opcode->name); |
65d7bab5 | 2375 | break; |
13761a11 NC |
2376 | } |
2377 | parse_exp (l1 + 1, &(op1.exp)); | |
2378 | if (op1.exp.X_op != O_constant) | |
2379 | { | |
2380 | as_bad (_("expected constant expression for first argument of %s"), | |
2381 | opcode->name); | |
65d7bab5 | 2382 | break; |
13761a11 | 2383 | } |
2469cfa2 | 2384 | |
13761a11 NC |
2385 | if ((reg = check_reg (l2)) == -1) |
2386 | { | |
2387 | as_bad (_("expected register as second argument of %s"), | |
2388 | opcode->name); | |
65d7bab5 | 2389 | break; |
13761a11 | 2390 | } |
2469cfa2 | 2391 | |
13761a11 NC |
2392 | op_length = 2; |
2393 | frag = frag_more (op_length); | |
b18c562e | 2394 | where = frag - frag_now->fr_literal; |
13761a11 NC |
2395 | bin = opcode->bin_opcode; |
2396 | if (! addr_op) | |
2397 | bin |= 0x100; | |
2398 | n = op1.exp.X_add_number; | |
2399 | bin |= (n - 1) << 4; | |
638d3803 | 2400 | if (is_opcode ("pushm")) |
13761a11 NC |
2401 | bin |= reg; |
2402 | else | |
2403 | { | |
2404 | if (reg - n + 1 < 0) | |
2405 | { | |
2406 | as_bad (_("Too many registers popped")); | |
65d7bab5 | 2407 | break; |
13761a11 | 2408 | } |
638d3803 | 2409 | |
65d7bab5 | 2410 | /* CPU21 errata: cannot use POPM to restore the SR register. */ |
d1706f38 | 2411 | if (target_is_430xv2 () |
638d3803 NC |
2412 | && (reg - n + 1 < 3) |
2413 | && reg >= 2 | |
2414 | && is_opcode ("popm")) | |
2415 | { | |
2416 | as_bad (_("Cannot use POPM to restore the SR register")); | |
65d7bab5 | 2417 | break; |
638d3803 NC |
2418 | } |
2419 | ||
13761a11 NC |
2420 | bin |= (reg - n + 1); |
2421 | } | |
2422 | ||
b18c562e | 2423 | bfd_putl16 ((bfd_vma) bin, frag); |
13761a11 NC |
2424 | dwarf2_emit_insn (op_length); |
2425 | break; | |
2426 | } | |
2427 | ||
2428 | case 6: | |
2429 | { | |
2430 | int n; | |
2431 | int reg; | |
2432 | ||
2433 | /* Bit rotation instructions. RRCM, RRAM, RRUM, RLAM. */ | |
2434 | if (extended & 0xff) | |
2435 | { | |
2436 | as_bad (_("repeat count cannot be used with %s"), opcode->name); | |
65d7bab5 | 2437 | break; |
13761a11 NC |
2438 | } |
2439 | ||
2440 | line = extract_operand (line, l1, sizeof (l1)); | |
2441 | line = extract_operand (line, l2, sizeof (l2)); | |
2442 | ||
2443 | if (*l1 != '#') | |
2444 | { | |
2445 | as_bad (_("expected #n as first argument of %s"), opcode->name); | |
65d7bab5 | 2446 | break; |
13761a11 NC |
2447 | } |
2448 | parse_exp (l1 + 1, &(op1.exp)); | |
2449 | if (op1.exp.X_op != O_constant) | |
2450 | { | |
2451 | as_bad (_("expected constant expression for first argument of %s"), | |
2452 | opcode->name); | |
65d7bab5 | 2453 | break; |
13761a11 NC |
2454 | } |
2455 | n = op1.exp.X_add_number; | |
2456 | if (n > 4 || n < 1) | |
b18c562e | 2457 | { |
13761a11 NC |
2458 | as_bad (_("expected first argument of %s to be in the range 1-4"), |
2459 | opcode->name); | |
65d7bab5 | 2460 | break; |
13761a11 | 2461 | } |
b18c562e | 2462 | |
13761a11 NC |
2463 | if ((reg = check_reg (l2)) == -1) |
2464 | { | |
2465 | as_bad (_("expected register as second argument of %s"), | |
2466 | opcode->name); | |
65d7bab5 | 2467 | break; |
b18c562e NC |
2468 | } |
2469 | ||
d1706f38 | 2470 | if (target_is_430xv2 () && reg == 0) |
638d3803 NC |
2471 | { |
2472 | as_bad (_("%s: attempt to rotate the PC register"), opcode->name); | |
65d7bab5 | 2473 | break; |
638d3803 NC |
2474 | } |
2475 | ||
13761a11 NC |
2476 | op_length = 2; |
2477 | frag = frag_more (op_length); | |
2478 | where = frag - frag_now->fr_literal; | |
2479 | ||
2480 | bin = opcode->bin_opcode; | |
2481 | if (! addr_op) | |
2482 | bin |= 0x10; | |
2483 | bin |= (n - 1) << 10; | |
2484 | bin |= reg; | |
2485 | ||
2486 | bfd_putl16 ((bfd_vma) bin, frag); | |
2487 | dwarf2_emit_insn (op_length); | |
2488 | break; | |
2489 | } | |
2490 | ||
2491 | case 7: | |
2492 | { | |
2493 | int reg; | |
2494 | ||
2495 | /* RRUX: Synthetic unsigned right shift of a register by one bit. */ | |
2496 | if (extended & 0xff) | |
b18c562e | 2497 | { |
13761a11 | 2498 | as_bad (_("repeat count cannot be used with %s"), opcode->name); |
65d7bab5 | 2499 | break; |
13761a11 | 2500 | } |
b18c562e | 2501 | |
13761a11 NC |
2502 | line = extract_operand (line, l1, sizeof (l1)); |
2503 | if ((reg = check_reg (l1)) == -1) | |
2504 | { | |
2505 | as_bad (_("expected register as argument of %s"), | |
2506 | opcode->name); | |
65d7bab5 | 2507 | break; |
13761a11 NC |
2508 | } |
2509 | ||
d1706f38 | 2510 | if (target_is_430xv2 () && reg == 0) |
638d3803 NC |
2511 | { |
2512 | as_bad (_("%s: attempt to rotate the PC register"), opcode->name); | |
65d7bab5 | 2513 | break; |
638d3803 NC |
2514 | } |
2515 | ||
13761a11 NC |
2516 | if (byte_op) |
2517 | { | |
2518 | /* Tricky - there is no single instruction that will do this. | |
2519 | Encode as: RRA.B rN { BIC.B #0x80, rN */ | |
2520 | op_length = 6; | |
2521 | frag = frag_more (op_length); | |
2522 | where = frag - frag_now->fr_literal; | |
2523 | bin = 0x1140 | reg; | |
2524 | bfd_putl16 ((bfd_vma) bin, frag); | |
2525 | dwarf2_emit_insn (2); | |
2526 | bin = 0xc070 | reg; | |
2527 | bfd_putl16 ((bfd_vma) bin, frag + 2); | |
2528 | bin = 0x0080; | |
2529 | bfd_putl16 ((bfd_vma) bin, frag + 4); | |
2530 | dwarf2_emit_insn (4); | |
2531 | } | |
2532 | else | |
2533 | { | |
2534 | /* Encode as RRUM[.A] rN. */ | |
2535 | bin = opcode->bin_opcode; | |
2536 | if (! addr_op) | |
2537 | bin |= 0x10; | |
2538 | bin |= reg; | |
2539 | op_length = 2; | |
2540 | frag = frag_more (op_length); | |
2541 | where = frag - frag_now->fr_literal; | |
2542 | bfd_putl16 ((bfd_vma) bin, frag); | |
2543 | dwarf2_emit_insn (op_length); | |
38d77545 | 2544 | } |
b18c562e NC |
2545 | break; |
2546 | } | |
b18c562e | 2547 | |
13761a11 NC |
2548 | case 8: |
2549 | { | |
2550 | bfd_boolean need_reloc = FALSE; | |
2551 | int n; | |
2552 | int reg; | |
2553 | ||
2554 | /* ADDA, CMPA and SUBA address instructions. */ | |
2555 | if (extended & 0xff) | |
2556 | { | |
2557 | as_bad (_("repeat count cannot be used with %s"), opcode->name); | |
65d7bab5 | 2558 | break; |
13761a11 NC |
2559 | } |
2560 | ||
2561 | line = extract_operand (line, l1, sizeof (l1)); | |
2562 | line = extract_operand (line, l2, sizeof (l2)); | |
2563 | ||
2564 | bin = opcode->bin_opcode; | |
2565 | ||
2566 | if (*l1 == '#') | |
2567 | { | |
2568 | parse_exp (l1 + 1, &(op1.exp)); | |
2569 | ||
2570 | if (op1.exp.X_op == O_constant) | |
2571 | { | |
2572 | n = op1.exp.X_add_number; | |
2573 | if (n > 0xfffff || n < - (0x7ffff)) | |
2574 | { | |
2575 | as_bad (_("expected value of first argument of %s to fit into 20-bits"), | |
2576 | opcode->name); | |
65d7bab5 | 2577 | break; |
13761a11 NC |
2578 | } |
2579 | ||
2580 | bin |= ((n >> 16) & 0xf) << 8; | |
2581 | } | |
2582 | else | |
2583 | { | |
2584 | n = 0; | |
2585 | need_reloc = TRUE; | |
2586 | } | |
2587 | ||
2588 | op_length = 4; | |
2589 | } | |
2590 | else | |
2591 | { | |
2592 | if ((n = check_reg (l1)) == -1) | |
2593 | { | |
2594 | as_bad (_("expected register name or constant as first argument of %s"), | |
2595 | opcode->name); | |
65d7bab5 | 2596 | break; |
13761a11 NC |
2597 | } |
2598 | ||
2599 | bin |= (n << 8) | (1 << 6); | |
2600 | op_length = 2; | |
2601 | } | |
2602 | ||
2603 | if ((reg = check_reg (l2)) == -1) | |
2604 | { | |
2605 | as_bad (_("expected register as second argument of %s"), | |
2606 | opcode->name); | |
65d7bab5 | 2607 | break; |
13761a11 NC |
2608 | } |
2609 | ||
2610 | frag = frag_more (op_length); | |
2611 | where = frag - frag_now->fr_literal; | |
2612 | bin |= reg; | |
2613 | if (need_reloc) | |
2614 | fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE, | |
2615 | BFD_RELOC_MSP430X_ABS20_ADR_SRC); | |
2616 | ||
2617 | bfd_putl16 ((bfd_vma) bin, frag); | |
2618 | if (op_length == 4) | |
2619 | bfd_putl16 ((bfd_vma) (n & 0xffff), frag + 2); | |
2620 | dwarf2_emit_insn (op_length); | |
b18c562e | 2621 | break; |
13761a11 | 2622 | } |
38d77545 | 2623 | |
13761a11 | 2624 | case 9: /* MOVA, BRA, RETA. */ |
00b32ff2 | 2625 | imm_op = FALSE; |
13761a11 | 2626 | bin = opcode->bin_opcode; |
b18c562e | 2627 | |
638d3803 | 2628 | if (is_opcode ("reta")) |
13761a11 NC |
2629 | { |
2630 | /* The RETA instruction does not take any arguments. | |
2631 | The implicit first argument is @SP+. | |
2632 | The implicit second argument is PC. */ | |
2633 | op1.mode = OP_REG; | |
2634 | op1.am = 3; | |
2635 | op1.reg = 1; | |
2636 | ||
2637 | op2.mode = OP_REG; | |
2638 | op2.reg = 0; | |
2639 | } | |
2640 | else | |
2641 | { | |
2642 | line = extract_operand (line, l1, sizeof (l1)); | |
2643 | res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, | |
2644 | &imm_op, extended_op, FALSE); | |
b18c562e | 2645 | |
638d3803 | 2646 | if (is_opcode ("bra")) |
13761a11 NC |
2647 | { |
2648 | /* This is the BRA synthetic instruction. | |
2649 | The second argument is always PC. */ | |
2650 | op2.mode = OP_REG; | |
2651 | op2.reg = 0; | |
2652 | } | |
2653 | else | |
2654 | { | |
2655 | line = extract_operand (line, l2, sizeof (l2)); | |
2656 | res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, | |
2657 | extended_op, TRUE); | |
2658 | } | |
38d77545 | 2659 | |
13761a11 NC |
2660 | if (res) |
2661 | break; /* Error occurred. All warnings were done before. */ | |
2662 | } | |
2663 | ||
2664 | /* Only a restricted subset of the normal MSP430 addressing modes | |
2665 | are supported here, so check for the ones that are allowed. */ | |
2666 | if ((op_length = try_encode_mova (imm_op, bin, & op1, & op2, | |
2667 | & error_message)) == 0) | |
2469cfa2 | 2668 | { |
13761a11 | 2669 | as_bad (error_message, opcode->name); |
65d7bab5 | 2670 | break; |
13761a11 NC |
2671 | } |
2672 | dwarf2_emit_insn (op_length); | |
2673 | break; | |
2674 | ||
2675 | case 10: /* RPT */ | |
2676 | line = extract_operand (line, l1, sizeof l1); | |
2677 | /* The RPT instruction only accepted immediates and registers. */ | |
2678 | if (*l1 == '#') | |
2679 | { | |
2680 | parse_exp (l1 + 1, &(op1.exp)); | |
2681 | if (op1.exp.X_op != O_constant) | |
2682 | { | |
2683 | as_bad (_("expected constant value as argument to RPT")); | |
65d7bab5 | 2684 | break; |
13761a11 NC |
2685 | } |
2686 | if (op1.exp.X_add_number < 1 | |
2687 | || op1.exp.X_add_number > (1 << 4)) | |
2688 | { | |
2689 | as_bad (_("expected constant in the range 2..16")); | |
65d7bab5 | 2690 | break; |
13761a11 NC |
2691 | } |
2692 | ||
2693 | /* We silently accept and ignore a repeat count of 1. */ | |
2694 | if (op1.exp.X_add_number > 1) | |
2695 | repeat_count = op1.exp.X_add_number; | |
2696 | } | |
2697 | else | |
2698 | { | |
2699 | int reg; | |
b18c562e | 2700 | |
13761a11 NC |
2701 | if ((reg = check_reg (l1)) != -1) |
2702 | { | |
2703 | if (reg == 0) | |
2704 | as_warn (_("PC used as an argument to RPT")); | |
2705 | else | |
2706 | repeat_count = - reg; | |
2707 | } | |
2469cfa2 | 2708 | else |
13761a11 NC |
2709 | { |
2710 | as_bad (_("expected constant or register name as argument to RPT insn")); | |
65d7bab5 | 2711 | break; |
13761a11 | 2712 | } |
2469cfa2 | 2713 | } |
b18c562e | 2714 | break; |
13761a11 NC |
2715 | |
2716 | default: | |
2717 | as_bad (_("Illegal emulated instruction ")); | |
2718 | break; | |
2469cfa2 | 2719 | } |
b18c562e | 2720 | break; |
2469cfa2 | 2721 | |
b18c562e NC |
2722 | case 1: /* Format 1, double operand. */ |
2723 | line = extract_operand (line, l1, sizeof (l1)); | |
2724 | line = extract_operand (line, l2, sizeof (l2)); | |
13761a11 NC |
2725 | res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE); |
2726 | res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE); | |
2469cfa2 | 2727 | |
b18c562e NC |
2728 | if (res) |
2729 | break; /* Error occurred. All warnings were done before. */ | |
2469cfa2 | 2730 | |
13761a11 | 2731 | if (extended_op |
638d3803 | 2732 | && is_opcode ("movx") |
13761a11 NC |
2733 | && addr_op |
2734 | && msp430_enable_relax) | |
2735 | { | |
2736 | /* This is the MOVX.A instruction. See if we can convert | |
2737 | it into the MOVA instruction instead. This saves 2 bytes. */ | |
2738 | if ((op_length = try_encode_mova (imm_op, 0x0000, & op1, & op2, | |
2739 | NULL)) != 0) | |
2740 | { | |
2741 | dwarf2_emit_insn (op_length); | |
2742 | break; | |
2743 | } | |
2744 | } | |
2745 | ||
65d7bab5 NC |
2746 | bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7)); |
2747 | ||
2748 | if ( (is_opcode ("bic") && bin == 0xc232) | |
2749 | || (is_opcode ("bis") && bin == 0xd232) | |
2750 | || (is_opcode ("mov") && op2.mode == OP_REG && op2.reg == 2)) | |
2751 | { | |
2752 | if (check_for_nop) | |
2753 | { | |
2754 | if (warn_interrupt_nops) | |
2755 | { | |
2756 | if (gen_interrupt_nops) | |
2757 | as_warn (_("NOP inserted between two instructions that change interrupt state")); | |
2758 | else | |
2759 | as_warn (_("a NOP might be needed here because of successive changes in interrupt state")); | |
2760 | } | |
2761 | ||
2762 | if (gen_interrupt_nops) | |
2763 | { | |
2764 | /* Emit a NOP between interrupt enable/disable. | |
2765 | See 1.3.4.1 of the MSP430x5xx User Guide. */ | |
2766 | insn_length += 2; | |
2767 | frag = frag_more (2); | |
2768 | bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag); | |
2769 | } | |
2770 | } | |
2771 | ||
2772 | nop_check_needed = TRUE; | |
2773 | } | |
2774 | ||
13761a11 | 2775 | /* Compute the entire length of the instruction in bytes. */ |
65d7bab5 | 2776 | op_length = (extended_op ? 2 : 0) /* The extension word. */ |
13761a11 NC |
2777 | + 2 /* The opcode */ |
2778 | + (2 * op1.ol) /* The first operand. */ | |
2779 | + (2 * op2.ol); /* The second operand. */ | |
b18c562e | 2780 | |
65d7bab5 NC |
2781 | insn_length += op_length; |
2782 | frag = frag_more (op_length); | |
b18c562e | 2783 | where = frag - frag_now->fr_literal; |
38d77545 | 2784 | |
13761a11 NC |
2785 | if (extended_op) |
2786 | { | |
2787 | if (!addr_op) | |
2788 | extended |= BYTE_OPERATION; | |
2789 | ||
2790 | if ((op1.ol != 0 || op2.ol != 0) && ((extended & 0xf) != 0)) | |
2791 | { | |
2792 | as_bad (_("repeat instruction used with non-register mode instruction")); | |
2793 | extended &= ~ 0xf; | |
2794 | } | |
2795 | ||
2796 | /* If necessary, emit a reloc to update the extension word. */ | |
2797 | if (op1.mode == OP_EXP) | |
2798 | { | |
2799 | if (op1.exp.X_op == O_constant) | |
2800 | extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7; | |
2801 | ||
e66c3c25 | 2802 | else if (op1.reg || op1.am == 3) /* Not PC relative. */ |
13761a11 NC |
2803 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, |
2804 | BFD_RELOC_MSP430X_ABS20_EXT_SRC); | |
2805 | else | |
2806 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, | |
2807 | BFD_RELOC_MSP430X_PCR20_EXT_SRC); | |
2808 | } | |
38d77545 | 2809 | |
13761a11 NC |
2810 | if (op2.mode == OP_EXP) |
2811 | { | |
2812 | if (op2.exp.X_op == O_constant) | |
2813 | extended |= (op2.exp.X_add_number >> 16) & 0xf; | |
2814 | ||
2815 | else if (op1.mode == OP_EXP) | |
2816 | fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE, | |
2817 | op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST | |
2818 | : BFD_RELOC_MSP430X_PCR20_EXT_ODST); | |
38d77545 | 2819 | |
13761a11 NC |
2820 | else |
2821 | fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE, | |
2822 | op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST | |
2823 | : BFD_RELOC_MSP430X_PCR20_EXT_DST); | |
2824 | } | |
2825 | ||
2826 | /* Emit the extension word. */ | |
2827 | bfd_putl16 (extended, frag); | |
2828 | where += 2; | |
2829 | frag += 2; | |
2830 | } | |
2831 | ||
b18c562e | 2832 | bfd_putl16 ((bfd_vma) bin, frag); |
13761a11 NC |
2833 | where += 2; |
2834 | frag += 2; | |
b18c562e NC |
2835 | |
2836 | if (op1.mode == OP_EXP) | |
2469cfa2 | 2837 | { |
13761a11 NC |
2838 | if (op1.exp.X_op == O_constant) |
2839 | { | |
2840 | bfd_putl16 (op1.exp.X_add_number & 0xffff, frag); | |
2841 | } | |
b18c562e | 2842 | else |
13761a11 NC |
2843 | { |
2844 | bfd_putl16 ((bfd_vma) ZEROS, frag); | |
2845 | ||
2846 | if (!extended_op) | |
2847 | { | |
e66c3c25 | 2848 | if (op1.reg || op1.am == 3) /* Not PC relative. */ |
13761a11 | 2849 | fix_new_exp (frag_now, where, 2, |
00b32ff2 | 2850 | &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1)); |
13761a11 NC |
2851 | else |
2852 | fix_new_exp (frag_now, where, 2, | |
2853 | &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
2854 | } | |
2855 | } | |
2856 | ||
2857 | where += 2; | |
2858 | frag += 2; | |
2469cfa2 | 2859 | } |
b18c562e NC |
2860 | |
2861 | if (op2.mode == OP_EXP) | |
2469cfa2 | 2862 | { |
13761a11 NC |
2863 | if (op2.exp.X_op == O_constant) |
2864 | { | |
2865 | bfd_putl16 (op2.exp.X_add_number & 0xffff, frag); | |
2866 | } | |
b18c562e | 2867 | else |
13761a11 NC |
2868 | { |
2869 | bfd_putl16 ((bfd_vma) ZEROS, frag); | |
2870 | ||
2871 | if (!extended_op) | |
2872 | { | |
2873 | if (op2.reg) /* Not PC relative. */ | |
2874 | fix_new_exp (frag_now, where, 2, | |
00b32ff2 | 2875 | &(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2)); |
13761a11 NC |
2876 | else |
2877 | fix_new_exp (frag_now, where, 2, | |
2878 | &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
2879 | } | |
2880 | } | |
2881 | } | |
2882 | ||
13761a11 | 2883 | dwarf2_emit_insn (insn_length); |
b18c562e NC |
2884 | break; |
2885 | ||
2886 | case 2: /* Single-operand mostly instr. */ | |
2887 | if (opcode->insn_opnumb == 0) | |
2469cfa2 | 2888 | { |
b18c562e | 2889 | /* reti instruction. */ |
13761a11 | 2890 | insn_length += 2; |
b18c562e NC |
2891 | frag = frag_more (2); |
2892 | bfd_putl16 ((bfd_vma) bin, frag); | |
13761a11 | 2893 | dwarf2_emit_insn (insn_length); |
b18c562e | 2894 | break; |
2469cfa2 | 2895 | } |
2469cfa2 | 2896 | |
b18c562e | 2897 | line = extract_operand (line, l1, sizeof (l1)); |
13761a11 NC |
2898 | res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, |
2899 | &imm_op, extended_op, TRUE); | |
b18c562e NC |
2900 | if (res) |
2901 | break; /* Error in operand. */ | |
2469cfa2 | 2902 | |
d1706f38 NC |
2903 | if (target_is_430xv2 () |
2904 | && op1.mode == OP_REG | |
38d77545 | 2905 | && op1.reg == 0 |
638d3803 NC |
2906 | && (is_opcode ("rrax") |
2907 | || is_opcode ("rrcx") | |
2908 | || is_opcode ("rra") | |
2909 | || is_opcode ("rrc"))) | |
2910 | { | |
2911 | as_bad (_("%s: attempt to rotate the PC register"), opcode->name); | |
65d7bab5 | 2912 | break; |
638d3803 | 2913 | } |
38d77545 | 2914 | |
13761a11 NC |
2915 | insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2); |
2916 | frag = frag_more (insn_length); | |
b18c562e | 2917 | where = frag - frag_now->fr_literal; |
38d77545 | 2918 | |
13761a11 NC |
2919 | if (extended_op) |
2920 | { | |
638d3803 | 2921 | if (is_opcode ("swpbx") || is_opcode ("sxtx")) |
13761a11 NC |
2922 | { |
2923 | /* These two instructions use a special | |
2924 | encoding of the A/L and B/W bits. */ | |
2925 | bin &= ~ BYTE_OPERATION; | |
2926 | ||
2927 | if (byte_op) | |
2928 | { | |
2929 | as_bad (_("%s instruction does not accept a .b suffix"), | |
2930 | opcode->name); | |
65d7bab5 | 2931 | break; |
13761a11 NC |
2932 | } |
2933 | else if (! addr_op) | |
2934 | extended |= BYTE_OPERATION; | |
2935 | } | |
2936 | else if (! addr_op) | |
2937 | extended |= BYTE_OPERATION; | |
2938 | ||
2939 | if (op1.ol != 0 && ((extended & 0xf) != 0)) | |
2940 | { | |
2941 | as_bad (_("repeat instruction used with non-register mode instruction")); | |
2942 | extended &= ~ 0xf; | |
2943 | } | |
2944 | ||
2945 | if (op1.mode == OP_EXP) | |
2946 | { | |
2947 | if (op1.exp.X_op == O_constant) | |
2948 | extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7; | |
38d77545 | 2949 | |
e66c3c25 | 2950 | else if (op1.reg || op1.am == 3) /* Not PC relative. */ |
13761a11 NC |
2951 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, |
2952 | BFD_RELOC_MSP430X_ABS20_EXT_SRC); | |
2953 | else | |
2954 | fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE, | |
2955 | BFD_RELOC_MSP430X_PCR20_EXT_SRC); | |
2956 | } | |
38d77545 | 2957 | |
13761a11 NC |
2958 | /* Emit the extension word. */ |
2959 | bfd_putl16 (extended, frag); | |
2960 | frag += 2; | |
2961 | where += 2; | |
2962 | } | |
2963 | ||
2964 | bin |= op1.reg | (op1.am << 4); | |
b18c562e | 2965 | bfd_putl16 ((bfd_vma) bin, frag); |
13761a11 NC |
2966 | frag += 2; |
2967 | where += 2; | |
b18c562e NC |
2968 | |
2969 | if (op1.mode == OP_EXP) | |
2469cfa2 | 2970 | { |
13761a11 NC |
2971 | if (op1.exp.X_op == O_constant) |
2972 | { | |
2973 | bfd_putl16 (op1.exp.X_add_number & 0xffff, frag); | |
2974 | } | |
b18c562e | 2975 | else |
13761a11 NC |
2976 | { |
2977 | bfd_putl16 ((bfd_vma) ZEROS, frag); | |
2978 | ||
2979 | if (!extended_op) | |
2980 | { | |
e66c3c25 | 2981 | if (op1.reg || op1.am == 3) /* Not PC relative. */ |
13761a11 | 2982 | fix_new_exp (frag_now, where, 2, |
00b32ff2 | 2983 | &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1)); |
13761a11 NC |
2984 | else |
2985 | fix_new_exp (frag_now, where, 2, | |
2986 | &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); | |
2987 | } | |
2988 | } | |
2469cfa2 | 2989 | } |
13761a11 NC |
2990 | |
2991 | dwarf2_emit_insn (insn_length); | |
b18c562e | 2992 | break; |
2469cfa2 | 2993 | |
b18c562e NC |
2994 | case 3: /* Conditional jumps instructions. */ |
2995 | line = extract_operand (line, l1, sizeof (l1)); | |
2996 | /* l1 is a label. */ | |
2997 | if (l1[0]) | |
2469cfa2 | 2998 | { |
b18c562e NC |
2999 | char *m = l1; |
3000 | expressionS exp; | |
2469cfa2 | 3001 | |
b18c562e NC |
3002 | if (*m == '$') |
3003 | m++; | |
2469cfa2 | 3004 | |
b18c562e | 3005 | parse_exp (m, &exp); |
2469cfa2 | 3006 | |
b18c562e | 3007 | /* In order to handle something like: |
2469cfa2 | 3008 | |
b18c562e NC |
3009 | and #0x8000, r5 |
3010 | tst r5 | |
3011 | jz 4 ; skip next 4 bytes | |
3012 | inv r5 | |
3013 | inc r5 | |
3014 | nop ; will jump here if r5 positive or zero | |
2469cfa2 | 3015 | |
b18c562e | 3016 | jCOND -n ;assumes jump n bytes backward: |
2469cfa2 | 3017 | |
b18c562e NC |
3018 | mov r5,r6 |
3019 | jmp -2 | |
2469cfa2 | 3020 | |
b18c562e NC |
3021 | is equal to: |
3022 | lab: | |
3023 | mov r5,r6 | |
3024 | jmp lab | |
3025 | ||
3026 | jCOND $n ; jump from PC in either direction. */ | |
2469cfa2 | 3027 | |
b18c562e NC |
3028 | if (exp.X_op == O_constant) |
3029 | { | |
3030 | int x = exp.X_add_number; | |
2469cfa2 | 3031 | |
b18c562e NC |
3032 | if (x & 1) |
3033 | { | |
3034 | as_warn (_("Even number required. Rounded to %d"), x + 1); | |
3035 | x++; | |
3036 | } | |
2469cfa2 | 3037 | |
b18c562e NC |
3038 | if ((*l1 == '$' && x > 0) || x < 0) |
3039 | x -= 2; | |
2469cfa2 | 3040 | |
b18c562e NC |
3041 | x >>= 1; |
3042 | ||
3043 | if (x > 512 || x < -511) | |
3044 | { | |
3045 | as_bad (_("Wrong displacement %d"), x << 1); | |
3046 | break; | |
3047 | } | |
3048 | ||
13761a11 NC |
3049 | insn_length += 2; |
3050 | frag = frag_more (2); /* Instr size is 1 word. */ | |
3051 | ||
b18c562e NC |
3052 | bin |= x & 0x3ff; |
3053 | bfd_putl16 ((bfd_vma) bin, frag); | |
3054 | } | |
3055 | else if (exp.X_op == O_symbol && *l1 != '$') | |
2469cfa2 | 3056 | { |
13761a11 NC |
3057 | insn_length += 2; |
3058 | frag = frag_more (2); /* Instr size is 1 word. */ | |
b18c562e NC |
3059 | where = frag - frag_now->fr_literal; |
3060 | fix_new_exp (frag_now, where, 2, | |
3061 | &exp, TRUE, BFD_RELOC_MSP430_10_PCREL); | |
3062 | ||
3063 | bfd_putl16 ((bfd_vma) bin, frag); | |
2469cfa2 | 3064 | } |
b18c562e | 3065 | else if (*l1 == '$') |
2469cfa2 | 3066 | { |
b18c562e | 3067 | as_bad (_("instruction requires label sans '$'")); |
2469cfa2 | 3068 | } |
b18c562e | 3069 | else |
13761a11 NC |
3070 | as_bad (_ |
3071 | ("instruction requires label or value in range -511:512")); | |
3072 | dwarf2_emit_insn (insn_length); | |
2a9a06c1 | 3073 | break; |
2469cfa2 | 3074 | } |
b18c562e NC |
3075 | else |
3076 | { | |
3077 | as_bad (_("instruction requires label")); | |
3078 | break; | |
3079 | } | |
3080 | break; | |
2469cfa2 | 3081 | |
b18c562e | 3082 | case 4: /* Extended jumps. */ |
77592908 DD |
3083 | if (!msp430_enable_polys) |
3084 | { | |
20203fb9 | 3085 | as_bad (_("polymorphs are not enabled. Use -mP option to enable.")); |
77592908 DD |
3086 | break; |
3087 | } | |
638d3803 | 3088 | |
b18c562e NC |
3089 | line = extract_operand (line, l1, sizeof (l1)); |
3090 | if (l1[0]) | |
2469cfa2 | 3091 | { |
b18c562e NC |
3092 | char *m = l1; |
3093 | expressionS exp; | |
2469cfa2 | 3094 | |
b18c562e NC |
3095 | /* Ignore absolute addressing. make it PC relative anyway. */ |
3096 | if (*m == '#' || *m == '$') | |
3097 | m++; | |
2469cfa2 | 3098 | |
b18c562e NC |
3099 | parse_exp (m, & exp); |
3100 | if (exp.X_op == O_symbol) | |
2469cfa2 | 3101 | { |
b18c562e NC |
3102 | /* Relaxation required. */ |
3103 | struct rcodes_s rc = msp430_rcodes[opcode->insn_opnumb]; | |
3104 | ||
638d3803 | 3105 | if (target_is_430x ()) |
13761a11 NC |
3106 | rc = msp430x_rcodes[opcode->insn_opnumb]; |
3107 | ||
3108 | /* The parameter to dwarf2_emit_insn is actually the offset to | |
3109 | the start of the insn from the fix piece of instruction that | |
3110 | was emitted. Since next fragments may have variable size we | |
3111 | tie debug info to the beginning of the instruction. */ | |
3112 | insn_length += 8; | |
3e470ab5 | 3113 | frag = frag_more (8); |
2a9a06c1 | 3114 | dwarf2_emit_insn (0); |
3e470ab5 DD |
3115 | bfd_putl16 ((bfd_vma) rc.sop, frag); |
3116 | frag = frag_variant (rs_machine_dependent, 8, 2, | |
13761a11 NC |
3117 | /* Wild guess. */ |
3118 | ENCODE_RELAX (rc.lpos, STATE_BITS10), | |
b18c562e NC |
3119 | exp.X_add_symbol, |
3120 | 0, /* Offset is zero if jump dist less than 1K. */ | |
3121 | (char *) frag); | |
3122 | break; | |
2469cfa2 NC |
3123 | } |
3124 | } | |
b18c562e NC |
3125 | |
3126 | as_bad (_("instruction requires label")); | |
3127 | break; | |
3128 | ||
3129 | case 5: /* Emulated extended branches. */ | |
77592908 DD |
3130 | if (!msp430_enable_polys) |
3131 | { | |
20203fb9 | 3132 | as_bad (_("polymorphs are not enabled. Use -mP option to enable.")); |
77592908 DD |
3133 | break; |
3134 | } | |
b18c562e NC |
3135 | line = extract_operand (line, l1, sizeof (l1)); |
3136 | if (l1[0]) | |
2469cfa2 | 3137 | { |
b18c562e NC |
3138 | char * m = l1; |
3139 | expressionS exp; | |
3140 | ||
3141 | /* Ignore absolute addressing. make it PC relative anyway. */ | |
3142 | if (*m == '#' || *m == '$') | |
3143 | m++; | |
3144 | ||
3145 | parse_exp (m, & exp); | |
3146 | if (exp.X_op == O_symbol) | |
3147 | { | |
3148 | /* Relaxation required. */ | |
3149 | struct hcodes_s hc = msp430_hcodes[opcode->insn_opnumb]; | |
3150 | ||
638d3803 | 3151 | if (target_is_430x ()) |
13761a11 NC |
3152 | hc = msp430x_hcodes[opcode->insn_opnumb]; |
3153 | ||
3154 | insn_length += 8; | |
3e470ab5 | 3155 | frag = frag_more (8); |
2a9a06c1 | 3156 | dwarf2_emit_insn (0); |
3e470ab5 DD |
3157 | bfd_putl16 ((bfd_vma) hc.op0, frag); |
3158 | bfd_putl16 ((bfd_vma) hc.op1, frag+2); | |
3159 | ||
3160 | frag = frag_variant (rs_machine_dependent, 8, 2, | |
b18c562e NC |
3161 | ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10), /* Wild guess. */ |
3162 | exp.X_add_symbol, | |
3163 | 0, /* Offset is zero if jump dist less than 1K. */ | |
3164 | (char *) frag); | |
3165 | break; | |
3166 | } | |
2469cfa2 NC |
3167 | } |
3168 | ||
b18c562e NC |
3169 | as_bad (_("instruction requires label")); |
3170 | break; | |
2469cfa2 | 3171 | |
b18c562e | 3172 | default: |
79cf5950 | 3173 | as_bad (_("Illegal instruction or not implemented opcode.")); |
b18c562e | 3174 | } |
2469cfa2 | 3175 | |
b18c562e | 3176 | input_line_pointer = line; |
65d7bab5 | 3177 | check_for_nop = nop_check_needed; |
b18c562e NC |
3178 | return 0; |
3179 | } | |
2469cfa2 | 3180 | |
b18c562e NC |
3181 | void |
3182 | md_assemble (char * str) | |
3183 | { | |
3184 | struct msp430_opcode_s * opcode; | |
3185 | char cmd[32]; | |
3186 | unsigned int i = 0; | |
2469cfa2 | 3187 | |
b18c562e | 3188 | str = skip_space (str); /* Skip leading spaces. */ |
64a81db0 | 3189 | str = extract_cmd (str, cmd, sizeof (cmd) - 1); |
2469cfa2 | 3190 | |
64a81db0 | 3191 | while (cmd[i]) |
b18c562e NC |
3192 | { |
3193 | char a = TOLOWER (cmd[i]); | |
3194 | cmd[i] = a; | |
3195 | i++; | |
2469cfa2 | 3196 | } |
2469cfa2 | 3197 | |
b18c562e | 3198 | if (!cmd[0]) |
2469cfa2 | 3199 | { |
b18c562e NC |
3200 | as_bad (_("can't find opcode ")); |
3201 | return; | |
3202 | } | |
2469cfa2 | 3203 | |
b18c562e | 3204 | opcode = (struct msp430_opcode_s *) hash_find (msp430_hash, cmd); |
2469cfa2 | 3205 | |
b18c562e NC |
3206 | if (opcode == NULL) |
3207 | { | |
3208 | as_bad (_("unknown opcode `%s'"), cmd); | |
3209 | return; | |
2469cfa2 | 3210 | } |
2469cfa2 | 3211 | |
b18c562e NC |
3212 | { |
3213 | char *__t = input_line_pointer; | |
2469cfa2 | 3214 | |
b18c562e NC |
3215 | msp430_operands (opcode, str); |
3216 | input_line_pointer = __t; | |
3217 | } | |
3218 | } | |
2469cfa2 NC |
3219 | |
3220 | /* GAS will call this function for each section at the end of the assembly, | |
3221 | to permit the CPU backend to adjust the alignment of a section. */ | |
3222 | ||
3223 | valueT | |
b18c562e | 3224 | md_section_align (asection * seg, valueT addr) |
2469cfa2 NC |
3225 | { |
3226 | int align = bfd_get_section_alignment (stdoutput, seg); | |
3227 | ||
3228 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
3229 | } | |
3230 | ||
3231 | /* If you define this macro, it should return the offset between the | |
3232 | address of a PC relative fixup and the position from which the PC | |
3233 | relative adjustment should be made. On many processors, the base | |
3234 | of a PC relative instruction is the next instruction, so this | |
3235 | macro would return the length of an instruction. */ | |
3236 | ||
3237 | long | |
b18c562e | 3238 | md_pcrel_from_section (fixS * fixp, segT sec) |
2469cfa2 NC |
3239 | { |
3240 | if (fixp->fx_addsy != (symbolS *) NULL | |
3241 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
3242 | || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
3243 | return 0; | |
3244 | ||
3245 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
3246 | } | |
3247 | ||
77592908 DD |
3248 | /* Replaces standard TC_FORCE_RELOCATION_LOCAL. |
3249 | Now it handles the situation when relocations | |
13761a11 | 3250 | have to be passed to linker. */ |
77592908 | 3251 | int |
13761a11 | 3252 | msp430_force_relocation_local (fixS *fixp) |
77592908 | 3253 | { |
13761a11 NC |
3254 | if (fixp->fx_r_type == BFD_RELOC_MSP430_10_PCREL) |
3255 | return 1; | |
13761a11 NC |
3256 | if (fixp->fx_pcrel) |
3257 | return 1; | |
77592908 DD |
3258 | if (msp430_enable_polys |
3259 | && !msp430_enable_relax) | |
3260 | return 1; | |
13761a11 NC |
3261 | |
3262 | return (!fixp->fx_pcrel | |
3263 | || generic_force_reloc (fixp)); | |
77592908 DD |
3264 | } |
3265 | ||
3266 | ||
2469cfa2 NC |
3267 | /* GAS will call this for each fixup. It should store the correct |
3268 | value in the object file. */ | |
2469cfa2 | 3269 | void |
55cf6793 | 3270 | md_apply_fix (fixS * fixp, valueT * valuep, segT seg) |
2469cfa2 | 3271 | { |
b18c562e | 3272 | unsigned char * where; |
2469cfa2 NC |
3273 | unsigned long insn; |
3274 | long value; | |
3275 | ||
3276 | if (fixp->fx_addsy == (symbolS *) NULL) | |
3277 | { | |
3278 | value = *valuep; | |
3279 | fixp->fx_done = 1; | |
3280 | } | |
3281 | else if (fixp->fx_pcrel) | |
3282 | { | |
3283 | segT s = S_GET_SEGMENT (fixp->fx_addsy); | |
3284 | ||
3285 | if (fixp->fx_addsy && (s == seg || s == absolute_section)) | |
3286 | { | |
18af0b39 NC |
3287 | /* FIXME: We can appear here only in case if we perform a pc |
3288 | relative jump to the label which is i) global, ii) locally | |
3289 | defined or this is a jump to an absolute symbol. | |
3290 | If this is an absolute symbol -- everything is OK. | |
3291 | If this is a global label, we've got a symbol value defined | |
3292 | twice: | |
3293 | 1. S_GET_VALUE (fixp->fx_addsy) will contain a symbol offset | |
3294 | from this section start | |
3295 | 2. *valuep will contain the real offset from jump insn to the | |
3296 | label | |
3297 | So, the result of S_GET_VALUE (fixp->fx_addsy) + (* valuep); | |
3298 | will be incorrect. Therefore remove s_get_value. */ | |
3299 | value = /* S_GET_VALUE (fixp->fx_addsy) + */ * valuep; | |
2469cfa2 NC |
3300 | fixp->fx_done = 1; |
3301 | } | |
3302 | else | |
3303 | value = *valuep; | |
3304 | } | |
3305 | else | |
3306 | { | |
3307 | value = fixp->fx_offset; | |
3308 | ||
3309 | if (fixp->fx_subsy != (symbolS *) NULL) | |
3310 | { | |
3311 | if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) | |
3312 | { | |
3313 | value -= S_GET_VALUE (fixp->fx_subsy); | |
3314 | fixp->fx_done = 1; | |
3315 | } | |
2469cfa2 NC |
3316 | } |
3317 | } | |
3318 | ||
77592908 DD |
3319 | fixp->fx_no_overflow = 1; |
3320 | ||
38d77545 | 3321 | /* If polymorphs are enabled and relax disabled. |
13761a11 | 3322 | do not kill any relocs and pass them to linker. */ |
38d77545 | 3323 | if (msp430_enable_polys |
77592908 | 3324 | && !msp430_enable_relax) |
2469cfa2 | 3325 | { |
e66c3c25 NC |
3326 | if (!fixp->fx_addsy |
3327 | || S_GET_SEGMENT (fixp->fx_addsy) == absolute_section) | |
79cf5950 | 3328 | fixp->fx_done = 1; /* It is ok to kill 'abs' reloc. */ |
77592908 DD |
3329 | else |
3330 | fixp->fx_done = 0; | |
2469cfa2 NC |
3331 | } |
3332 | ||
3333 | if (fixp->fx_done) | |
3334 | { | |
3335 | /* Fetch the instruction, insert the fully resolved operand | |
8cd5b113 | 3336 | value, and stuff the instruction back again. */ |
2132e3a3 | 3337 | where = (unsigned char *) fixp->fx_frag->fr_literal + fixp->fx_where; |
2469cfa2 NC |
3338 | |
3339 | insn = bfd_getl16 (where); | |
3340 | ||
3341 | switch (fixp->fx_r_type) | |
3342 | { | |
3343 | case BFD_RELOC_MSP430_10_PCREL: | |
3344 | if (value & 1) | |
3345 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3346 | _("odd address operand: %ld"), value); | |
3347 | ||
3348 | /* Jumps are in words. */ | |
3349 | value >>= 1; | |
3350 | --value; /* Correct PC. */ | |
3351 | ||
3352 | if (value < -512 || value > 511) | |
3353 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3354 | _("operand out of range: %ld"), value); | |
3355 | ||
3356 | value &= 0x3ff; /* get rid of extended sign */ | |
3357 | bfd_putl16 ((bfd_vma) (value | insn), where); | |
3358 | break; | |
3359 | ||
13761a11 | 3360 | case BFD_RELOC_MSP430X_PCR16: |
b18c562e | 3361 | case BFD_RELOC_MSP430_RL_PCREL: |
2469cfa2 NC |
3362 | case BFD_RELOC_MSP430_16_PCREL: |
3363 | if (value & 1) | |
3364 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3365 | _("odd address operand: %ld"), value); | |
13761a11 | 3366 | /* Fall through. */ |
2469cfa2 NC |
3367 | |
3368 | case BFD_RELOC_MSP430_16_PCREL_BYTE: | |
3369 | /* Nothing to be corrected here. */ | |
3370 | if (value < -32768 || value > 65536) | |
3371 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3372 | _("operand out of range: %ld"), value); | |
13761a11 | 3373 | /* Fall through. */ |
2469cfa2 | 3374 | |
13761a11 NC |
3375 | case BFD_RELOC_MSP430X_ABS16: |
3376 | case BFD_RELOC_MSP430_16: | |
3377 | case BFD_RELOC_16: | |
3378 | case BFD_RELOC_MSP430_16_BYTE: | |
2469cfa2 NC |
3379 | value &= 0xffff; /* Get rid of extended sign. */ |
3380 | bfd_putl16 ((bfd_vma) value, where); | |
3381 | break; | |
3382 | ||
00b32ff2 NC |
3383 | case BFD_RELOC_MSP430_ABS_HI16: |
3384 | value >>= 16; | |
3385 | value &= 0xffff; /* Get rid of extended sign. */ | |
3386 | bfd_putl16 ((bfd_vma) value, where); | |
3387 | break; | |
3388 | ||
2469cfa2 NC |
3389 | case BFD_RELOC_32: |
3390 | bfd_putl16 ((bfd_vma) value, where); | |
3391 | break; | |
3392 | ||
13761a11 NC |
3393 | case BFD_RELOC_MSP430_ABS8: |
3394 | case BFD_RELOC_8: | |
3395 | bfd_put_8 (NULL, (bfd_vma) value, where); | |
3396 | break; | |
3397 | ||
3398 | case BFD_RELOC_MSP430X_ABS20_EXT_SRC: | |
3399 | case BFD_RELOC_MSP430X_PCR20_EXT_SRC: | |
3400 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4); | |
38d77545 | 3401 | value >>= 16; |
13761a11 NC |
3402 | bfd_putl16 ((bfd_vma) (((value & 0xf) << 7) | insn), where); |
3403 | break; | |
3404 | ||
3405 | case BFD_RELOC_MSP430X_ABS20_ADR_SRC: | |
3406 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2); | |
38d77545 | 3407 | value >>= 16; |
13761a11 NC |
3408 | bfd_putl16 ((bfd_vma) (((value & 0xf) << 8) | insn), where); |
3409 | break; | |
3410 | ||
3411 | case BFD_RELOC_MSP430X_ABS20_EXT_ODST: | |
3412 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6); | |
3413 | value >>= 16; | |
3414 | bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where); | |
3415 | break; | |
3416 | ||
3417 | case BFD_RELOC_MSP430X_PCR20_CALL: | |
3418 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2); | |
3419 | value >>= 16; | |
3420 | bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where); | |
3421 | break; | |
3422 | ||
3423 | case BFD_RELOC_MSP430X_ABS20_EXT_DST: | |
3424 | case BFD_RELOC_MSP430X_PCR20_EXT_DST: | |
3425 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4); | |
3426 | value >>= 16; | |
3427 | bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where); | |
3428 | break; | |
3429 | ||
3430 | case BFD_RELOC_MSP430X_PCR20_EXT_ODST: | |
3431 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6); | |
3432 | value >>= 16; | |
3433 | bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where); | |
3434 | break; | |
3435 | ||
3436 | case BFD_RELOC_MSP430X_ABS20_ADR_DST: | |
3437 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2); | |
3438 | value >>= 16; | |
3439 | bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where); | |
2469cfa2 | 3440 | break; |
38d77545 | 3441 | |
2469cfa2 NC |
3442 | default: |
3443 | as_fatal (_("line %d: unknown relocation type: 0x%x"), | |
3444 | fixp->fx_line, fixp->fx_r_type); | |
3445 | break; | |
3446 | } | |
3447 | } | |
3448 | else | |
3449 | { | |
3450 | fixp->fx_addnumber = value; | |
3451 | } | |
2469cfa2 NC |
3452 | } |
3453 | ||
13761a11 NC |
3454 | static bfd_boolean |
3455 | S_IS_GAS_LOCAL (symbolS * s) | |
3456 | { | |
3457 | const char * name; | |
3458 | unsigned int len; | |
3459 | ||
3460 | if (s == NULL) | |
3461 | return FALSE; | |
3462 | name = S_GET_NAME (s); | |
3463 | len = strlen (name) - 1; | |
38d77545 | 3464 | |
13761a11 NC |
3465 | return name[len] == 1 || name[len] == 2; |
3466 | } | |
3467 | ||
7be1c489 AM |
3468 | /* GAS will call this to generate a reloc, passing the resulting reloc |
3469 | to `bfd_install_relocation'. This currently works poorly, as | |
3470 | `bfd_install_relocation' often does the wrong thing, and instances of | |
3471 | `tc_gen_reloc' have been written to work around the problems, which | |
3472 | in turns makes it difficult to fix `bfd_install_relocation'. */ | |
2469cfa2 NC |
3473 | |
3474 | /* If while processing a fixup, a reloc really needs to be created | |
3475 | then it is done here. */ | |
3476 | ||
13761a11 | 3477 | arelent ** |
b18c562e | 3478 | tc_gen_reloc (asection * seg ATTRIBUTE_UNUSED, fixS * fixp) |
2469cfa2 | 3479 | { |
13761a11 NC |
3480 | static arelent * no_relocs = NULL; |
3481 | static arelent * relocs[MAX_RELOC_EXPANSION + 1]; | |
3482 | arelent *reloc; | |
2469cfa2 | 3483 | |
b18c562e | 3484 | reloc = xmalloc (sizeof (arelent)); |
2469cfa2 NC |
3485 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3486 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
13761a11 | 3487 | |
2469cfa2 NC |
3488 | if (reloc->howto == (reloc_howto_type *) NULL) |
3489 | { | |
3490 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3491 | _("reloc %d not supported by object file format"), | |
3492 | (int) fixp->fx_r_type); | |
13761a11 NC |
3493 | free (reloc); |
3494 | return & no_relocs; | |
3495 | } | |
3496 | ||
3497 | relocs[0] = reloc; | |
3498 | relocs[1] = NULL; | |
3499 | ||
3500 | if (fixp->fx_subsy | |
3501 | && S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) | |
3502 | { | |
3503 | fixp->fx_offset -= S_GET_VALUE (fixp->fx_subsy); | |
3504 | fixp->fx_subsy = NULL; | |
2469cfa2 NC |
3505 | } |
3506 | ||
13761a11 NC |
3507 | if (fixp->fx_addsy && fixp->fx_subsy) |
3508 | { | |
3509 | asection *asec, *ssec; | |
3510 | ||
3511 | asec = S_GET_SEGMENT (fixp->fx_addsy); | |
3512 | ssec = S_GET_SEGMENT (fixp->fx_subsy); | |
3513 | ||
3514 | /* If we have a difference between two different, non-absolute symbols | |
3515 | we must generate two relocs (one for each symbol) and allow the | |
3516 | linker to resolve them - relaxation may change the distances between | |
3517 | symbols, even local symbols defined in the same section. | |
3518 | ||
3519 | Unfortunately we cannot do this with assembler generated local labels | |
3520 | because there can be multiple incarnations of the same label, with | |
3521 | exactly the same name, in any given section and the linker will have | |
3522 | no way to identify the correct one. Instead we just have to hope | |
3523 | that no relaxtion will occur between the local label and the other | |
3524 | symbol in the expression. | |
3525 | ||
3526 | Similarly we have to compute differences between symbols in the .eh_frame | |
3527 | section as the linker is not smart enough to apply relocations there | |
3528 | before attempting to process it. */ | |
3529 | if ((ssec != absolute_section || asec != absolute_section) | |
3530 | && (fixp->fx_addsy != fixp->fx_subsy) | |
3531 | && strcmp (ssec->name, ".eh_frame") != 0 | |
3532 | && ! S_IS_GAS_LOCAL (fixp->fx_addsy) | |
3533 | && ! S_IS_GAS_LOCAL (fixp->fx_subsy)) | |
3534 | { | |
3535 | arelent * reloc2 = xmalloc (sizeof * reloc); | |
2469cfa2 | 3536 | |
13761a11 NC |
3537 | relocs[0] = reloc2; |
3538 | relocs[1] = reloc; | |
2469cfa2 | 3539 | |
13761a11 NC |
3540 | reloc2->address = reloc->address; |
3541 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, | |
3542 | BFD_RELOC_MSP430_SYM_DIFF); | |
3543 | reloc2->addend = - S_GET_VALUE (fixp->fx_subsy); | |
3544 | ||
3545 | if (ssec == absolute_section) | |
3546 | reloc2->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr; | |
3547 | else | |
3548 | { | |
3549 | reloc2->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
3550 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy); | |
3551 | } | |
3552 | ||
38d77545 | 3553 | reloc->addend = fixp->fx_offset; |
13761a11 NC |
3554 | if (asec == absolute_section) |
3555 | { | |
3556 | reloc->addend += S_GET_VALUE (fixp->fx_addsy); | |
3557 | reloc->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr; | |
3558 | } | |
3559 | else | |
3560 | { | |
3561 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
3562 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
3563 | } | |
3564 | ||
3565 | fixp->fx_pcrel = 0; | |
3566 | fixp->fx_done = 1; | |
3567 | return relocs; | |
3568 | } | |
3569 | else | |
3570 | { | |
3571 | char *fixpos = fixp->fx_where + fixp->fx_frag->fr_literal; | |
3572 | ||
3573 | reloc->addend = (S_GET_VALUE (fixp->fx_addsy) | |
3574 | - S_GET_VALUE (fixp->fx_subsy) + fixp->fx_offset); | |
3575 | ||
3576 | switch (fixp->fx_r_type) | |
3577 | { | |
3578 | case BFD_RELOC_8: | |
3579 | md_number_to_chars (fixpos, reloc->addend, 1); | |
3580 | break; | |
3581 | ||
3582 | case BFD_RELOC_16: | |
3583 | md_number_to_chars (fixpos, reloc->addend, 2); | |
3584 | break; | |
3585 | ||
3586 | case BFD_RELOC_24: | |
3587 | md_number_to_chars (fixpos, reloc->addend, 3); | |
3588 | break; | |
3589 | ||
3590 | case BFD_RELOC_32: | |
3591 | md_number_to_chars (fixpos, reloc->addend, 4); | |
3592 | break; | |
3593 | ||
3594 | default: | |
3595 | reloc->sym_ptr_ptr | |
3596 | = (asymbol **) bfd_abs_section_ptr->symbol_ptr_ptr; | |
3597 | return relocs; | |
3598 | } | |
3599 | ||
3600 | free (reloc); | |
3601 | return & no_relocs; | |
3602 | } | |
3603 | } | |
3604 | else | |
3605 | { | |
3606 | #if 0 | |
3607 | if (fixp->fx_r_type == BFD_RELOC_MSP430X_ABS16 | |
3608 | && S_GET_SEGMENT (fixp->fx_addsy) == absolute_section) | |
3609 | { | |
3610 | bfd_vma amount = S_GET_VALUE (fixp->fx_addsy); | |
3611 | char *fixpos = fixp->fx_where + fixp->fx_frag->fr_literal; | |
3612 | ||
3613 | md_number_to_chars (fixpos, amount, 2); | |
3614 | free (reloc); | |
3615 | return & no_relocs; | |
3616 | } | |
3617 | #endif | |
3618 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
3619 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
3620 | reloc->addend = fixp->fx_offset; | |
3621 | ||
3622 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
3623 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3624 | reloc->address = fixp->fx_offset; | |
3625 | } | |
3626 | ||
3627 | return relocs; | |
2469cfa2 NC |
3628 | } |
3629 | ||
b18c562e NC |
3630 | int |
3631 | md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED, | |
3632 | asection * segment_type ATTRIBUTE_UNUSED) | |
3633 | { | |
3634 | if (fragP->fr_symbol && S_GET_SEGMENT (fragP->fr_symbol) == segment_type) | |
3635 | { | |
3636 | /* This is a jump -> pcrel mode. Nothing to do much here. | |
3637 | Return value == 2. */ | |
3638 | fragP->fr_subtype = | |
3639 | ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_BITS10); | |
3640 | } | |
3641 | else if (fragP->fr_symbol) | |
3642 | { | |
3643 | /* Its got a segment, but its not ours. Even if fr_symbol is in | |
79cf5950 | 3644 | an absolute segment, we don't know a displacement until we link |
b18c562e NC |
3645 | object files. So it will always be long. This also applies to |
3646 | labels in a subsegment of current. Liker may relax it to short | |
3647 | jump later. Return value == 8. */ | |
3648 | fragP->fr_subtype = | |
3649 | ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_WORD); | |
3650 | } | |
3651 | else | |
3652 | { | |
3653 | /* We know the abs value. may be it is a jump to fixed address. | |
79cf5950 | 3654 | Impossible in our case, cause all constants already handled. */ |
b18c562e NC |
3655 | fragP->fr_subtype = |
3656 | ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_UNDEF); | |
3657 | } | |
2469cfa2 | 3658 | |
b18c562e NC |
3659 | return md_relax_table[fragP->fr_subtype].rlx_length; |
3660 | } | |
3661 | ||
3662 | void | |
3663 | md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, | |
3664 | asection * sec ATTRIBUTE_UNUSED, | |
3665 | fragS * fragP) | |
2469cfa2 | 3666 | { |
b18c562e NC |
3667 | char * where = 0; |
3668 | int rela = -1; | |
3669 | int i; | |
3670 | struct rcodes_s * cc = NULL; | |
3671 | struct hcodes_s * hc = NULL; | |
3672 | ||
3673 | switch (fragP->fr_subtype) | |
3674 | { | |
3675 | case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_BITS10): | |
3676 | case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_BITS10): | |
3677 | case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_BITS10): | |
3678 | /* We do not have to convert anything here. | |
3679 | Just apply a fix. */ | |
3680 | rela = BFD_RELOC_MSP430_10_PCREL; | |
3681 | break; | |
3682 | ||
3683 | case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_WORD): | |
3684 | case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_UNDEF): | |
3685 | /* Convert uncond branch jmp lab -> br lab. */ | |
638d3803 | 3686 | if (target_is_430x ()) |
13761a11 | 3687 | cc = msp430x_rcodes + 7; |
638d3803 NC |
3688 | else |
3689 | cc = msp430_rcodes + 7; | |
b18c562e NC |
3690 | where = fragP->fr_literal + fragP->fr_fix; |
3691 | bfd_putl16 (cc->lop0, where); | |
3692 | rela = BFD_RELOC_MSP430_RL_PCREL; | |
3693 | fragP->fr_fix += 2; | |
3694 | break; | |
3695 | ||
3696 | case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_WORD): | |
3697 | case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_UNDEF): | |
3698 | { | |
3699 | /* Other simple branches. */ | |
3700 | int insn = bfd_getl16 (fragP->fr_opcode); | |
3701 | ||
3702 | insn &= 0xffff; | |
3703 | /* Find actual instruction. */ | |
638d3803 | 3704 | if (target_is_430x ()) |
13761a11 NC |
3705 | { |
3706 | for (i = 0; i < 7 && !cc; i++) | |
3707 | if (msp430x_rcodes[i].sop == insn) | |
3708 | cc = msp430x_rcodes + i; | |
3709 | } | |
3710 | else | |
3711 | { | |
3712 | for (i = 0; i < 7 && !cc; i++) | |
3713 | if (msp430_rcodes[i].sop == insn) | |
3714 | cc = & msp430_rcodes[i]; | |
3715 | } | |
3716 | ||
b18c562e NC |
3717 | if (!cc || !cc->name) |
3718 | as_fatal (_("internal inconsistency problem in %s: insn %04lx"), | |
3719 | __FUNCTION__, (long) insn); | |
3720 | where = fragP->fr_literal + fragP->fr_fix; | |
3721 | bfd_putl16 (cc->lop0, where); | |
3722 | bfd_putl16 (cc->lop1, where + 2); | |
3723 | rela = BFD_RELOC_MSP430_RL_PCREL; | |
3724 | fragP->fr_fix += 4; | |
3725 | } | |
3726 | break; | |
3727 | ||
3728 | case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_WORD): | |
3729 | case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_UNDEF): | |
638d3803 | 3730 | if (target_is_430x ()) |
13761a11 | 3731 | cc = msp430x_rcodes + 6; |
638d3803 NC |
3732 | else |
3733 | cc = msp430_rcodes + 6; | |
b18c562e NC |
3734 | where = fragP->fr_literal + fragP->fr_fix; |
3735 | bfd_putl16 (cc->lop0, where); | |
3736 | bfd_putl16 (cc->lop1, where + 2); | |
3737 | bfd_putl16 (cc->lop2, where + 4); | |
3738 | rela = BFD_RELOC_MSP430_RL_PCREL; | |
3739 | fragP->fr_fix += 6; | |
3740 | break; | |
3741 | ||
3742 | case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10): | |
3743 | { | |
3744 | int insn = bfd_getl16 (fragP->fr_opcode + 2); | |
3745 | ||
3746 | insn &= 0xffff; | |
638d3803 | 3747 | if (target_is_430x ()) |
13761a11 NC |
3748 | { |
3749 | for (i = 0; i < 4 && !hc; i++) | |
3750 | if (msp430x_hcodes[i].op1 == insn) | |
3751 | hc = msp430x_hcodes + i; | |
3752 | } | |
3753 | else | |
3754 | { | |
3755 | for (i = 0; i < 4 && !hc; i++) | |
3756 | if (msp430_hcodes[i].op1 == insn) | |
3757 | hc = &msp430_hcodes[i]; | |
3758 | } | |
b18c562e NC |
3759 | if (!hc || !hc->name) |
3760 | as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"), | |
3761 | __FUNCTION__, (long) insn); | |
3762 | rela = BFD_RELOC_MSP430_10_PCREL; | |
3763 | /* Apply a fix for a first label if necessary. | |
3764 | another fix will be applied to the next word of insn anyway. */ | |
3765 | if (hc->tlab == 2) | |
3766 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, | |
13761a11 | 3767 | fragP->fr_offset, TRUE, rela); |
b18c562e NC |
3768 | fragP->fr_fix += 2; |
3769 | } | |
3770 | ||
3771 | break; | |
3772 | ||
3773 | case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_WORD): | |
3774 | case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_UNDEF): | |
3775 | { | |
3776 | int insn = bfd_getl16 (fragP->fr_opcode + 2); | |
3777 | ||
3778 | insn &= 0xffff; | |
638d3803 | 3779 | if (target_is_430x ()) |
13761a11 NC |
3780 | { |
3781 | for (i = 0; i < 4 && !hc; i++) | |
3782 | if (msp430x_hcodes[i].op1 == insn) | |
3783 | hc = msp430x_hcodes + i; | |
3784 | } | |
3785 | else | |
3786 | { | |
3787 | for (i = 0; i < 4 && !hc; i++) | |
3788 | if (msp430_hcodes[i].op1 == insn) | |
3789 | hc = & msp430_hcodes[i]; | |
3790 | } | |
b18c562e NC |
3791 | if (!hc || !hc->name) |
3792 | as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"), | |
3793 | __FUNCTION__, (long) insn); | |
3794 | rela = BFD_RELOC_MSP430_RL_PCREL; | |
3795 | where = fragP->fr_literal + fragP->fr_fix; | |
3796 | bfd_putl16 (hc->lop0, where); | |
3797 | bfd_putl16 (hc->lop1, where + 2); | |
3798 | bfd_putl16 (hc->lop2, where + 4); | |
3799 | fragP->fr_fix += 6; | |
3800 | } | |
3801 | break; | |
3802 | ||
3803 | default: | |
3804 | as_fatal (_("internal inconsistency problem in %s: %lx"), | |
3805 | __FUNCTION__, (long) fragP->fr_subtype); | |
3806 | break; | |
3807 | } | |
3808 | ||
3809 | /* Now apply fix. */ | |
3810 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, | |
3811 | fragP->fr_offset, TRUE, rela); | |
3812 | /* Just fixed 2 bytes. */ | |
3813 | fragP->fr_fix += 2; | |
2469cfa2 NC |
3814 | } |
3815 | ||
b18c562e NC |
3816 | /* Relax fragment. Mostly stolen from hc11 and mcore |
3817 | which arches I think I know. */ | |
2469cfa2 | 3818 | |
b18c562e NC |
3819 | long |
3820 | msp430_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS * fragP, | |
3821 | long stretch ATTRIBUTE_UNUSED) | |
2469cfa2 | 3822 | { |
b18c562e NC |
3823 | long growth; |
3824 | offsetT aim = 0; | |
3825 | symbolS *symbolP; | |
3826 | const relax_typeS *this_type; | |
3827 | const relax_typeS *start_type; | |
3828 | relax_substateT next_state; | |
3829 | relax_substateT this_state; | |
3830 | const relax_typeS *table = md_relax_table; | |
3831 | ||
3832 | /* Nothing to be done if the frag has already max size. */ | |
3833 | if (RELAX_STATE (fragP->fr_subtype) == STATE_UNDEF | |
3834 | || RELAX_STATE (fragP->fr_subtype) == STATE_WORD) | |
3835 | return 0; | |
3836 | ||
3837 | if (RELAX_STATE (fragP->fr_subtype) == STATE_BITS10) | |
3838 | { | |
3839 | symbolP = fragP->fr_symbol; | |
3840 | if (symbol_resolved_p (symbolP)) | |
3841 | as_fatal (_("internal inconsistency problem in %s: resolved symbol"), | |
3842 | __FUNCTION__); | |
3843 | /* We know the offset. calculate a distance. */ | |
3844 | aim = S_GET_VALUE (symbolP) - fragP->fr_address - fragP->fr_fix; | |
3845 | } | |
3846 | ||
77592908 DD |
3847 | if (!msp430_enable_relax) |
3848 | { | |
3849 | /* Relaxation is not enabled. So, make all jump as long ones | |
13761a11 | 3850 | by setting 'aim' to quite high value. */ |
77592908 DD |
3851 | aim = 0x7fff; |
3852 | } | |
38d77545 | 3853 | |
b18c562e NC |
3854 | this_state = fragP->fr_subtype; |
3855 | start_type = this_type = table + this_state; | |
3856 | ||
3857 | if (aim < 0) | |
3858 | { | |
3859 | /* Look backwards. */ | |
3860 | for (next_state = this_type->rlx_more; next_state;) | |
3e470ab5 | 3861 | if (aim >= this_type->rlx_backward || !this_type->rlx_backward) |
b18c562e NC |
3862 | next_state = 0; |
3863 | else | |
3864 | { | |
3865 | /* Grow to next state. */ | |
3866 | this_state = next_state; | |
3867 | this_type = table + this_state; | |
3868 | next_state = this_type->rlx_more; | |
3869 | } | |
3870 | } | |
3871 | else | |
3872 | { | |
3873 | /* Look forwards. */ | |
3874 | for (next_state = this_type->rlx_more; next_state;) | |
3e470ab5 | 3875 | if (aim <= this_type->rlx_forward || !this_type->rlx_forward) |
b18c562e NC |
3876 | next_state = 0; |
3877 | else | |
3878 | { | |
3879 | /* Grow to next state. */ | |
3880 | this_state = next_state; | |
3881 | this_type = table + this_state; | |
3882 | next_state = this_type->rlx_more; | |
3883 | } | |
3884 | } | |
3885 | ||
3886 | growth = this_type->rlx_length - start_type->rlx_length; | |
3887 | if (growth != 0) | |
3888 | fragP->fr_subtype = this_state; | |
3889 | return growth; | |
2469cfa2 | 3890 | } |
13761a11 NC |
3891 | |
3892 | /* Return FALSE if the fixup in fixp should be left alone and not | |
3893 | adjusted. We return FALSE here so that linker relaxation will | |
3894 | work. */ | |
3895 | ||
3896 | bfd_boolean | |
3897 | msp430_fix_adjustable (struct fix *fixp ATTRIBUTE_UNUSED) | |
3898 | { | |
3899 | /* If the symbol is in a non-code section then it should be OK. */ | |
3900 | if (fixp->fx_addsy | |
3901 | && ((S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_CODE) == 0)) | |
3902 | return TRUE; | |
38d77545 | 3903 | |
13761a11 NC |
3904 | return FALSE; |
3905 | } | |
3906 | ||
3907 | /* Set the contents of the .MSP430.attributes section. */ | |
3908 | ||
3909 | void | |
3910 | msp430_md_end (void) | |
3911 | { | |
65d7bab5 NC |
3912 | if (check_for_nop == TRUE && warn_interrupt_nops) |
3913 | as_warn ("assembly finished with the last instruction changing interrupt state - a NOP might be needed"); | |
3914 | ||
13761a11 | 3915 | bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_ISA, |
638d3803 | 3916 | target_is_430x () ? 2 : 1); |
13761a11 NC |
3917 | |
3918 | bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_Code_Model, | |
3919 | large_model ? 2 : 1); | |
3920 | ||
3921 | bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_Data_Model, | |
3922 | large_model ? 2 : 1); | |
3923 | } | |
3924 | ||
3925 | /* Returns FALSE if there is a msp430 specific reason why the | |
3926 | subtraction of two same-section symbols cannot be computed by | |
3927 | the assembler. */ | |
3928 | ||
3929 | bfd_boolean | |
3930 | msp430_allow_local_subtract (expressionS * left, | |
3931 | expressionS * right, | |
3932 | segT section) | |
3933 | { | |
3934 | /* If the symbols are not in a code section then they are OK. */ | |
3935 | if ((section->flags & SEC_CODE) == 0) | |
3936 | return TRUE; | |
3937 | ||
3938 | if (S_IS_GAS_LOCAL (left->X_add_symbol) || S_IS_GAS_LOCAL (right->X_add_symbol)) | |
3939 | return TRUE; | |
3940 | ||
3941 | if (left->X_add_symbol == right->X_add_symbol) | |
3942 | return TRUE; | |
3943 | ||
3944 | /* We have to assume that there may be instructions between the | |
3945 | two symbols and that relaxation may increase the distance between | |
3946 | them. */ | |
3947 | return FALSE; | |
3948 | } |