Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000) |
b3adc24a | 2 | Copyright (C) 1994-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support. |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
20 | 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
252b5132 | 24 | #include "subsegs.h" |
75e21f08 | 25 | #include "dw2gencfi.h" |
252b5132 RH |
26 | #include "opcode/ppc.h" |
27 | ||
28 | #ifdef OBJ_ELF | |
29 | #include "elf/ppc.h" | |
ee67d69a | 30 | #include "elf/ppc64.h" |
5d6f4f16 | 31 | #include "dwarf2dbg.h" |
252b5132 RH |
32 | #endif |
33 | ||
34 | #ifdef TE_PE | |
35 | #include "coff/pe.h" | |
36 | #endif | |
37 | ||
85645aed TG |
38 | #ifdef OBJ_XCOFF |
39 | #include "coff/xcoff.h" | |
40 | #include "libxcoff.h" | |
41 | #endif | |
42 | ||
252b5132 RH |
43 | /* This is the assembler for the PowerPC or POWER (RS/6000) chips. */ |
44 | ||
45 | /* Tell the main code what the endianness is. */ | |
46 | extern int target_big_endian; | |
47 | ||
48 | /* Whether or not, we've set target_big_endian. */ | |
49 | static int set_target_endian = 0; | |
50 | ||
51 | /* Whether to use user friendly register names. */ | |
52 | #ifndef TARGET_REG_NAMES_P | |
53 | #ifdef TE_PE | |
b34976b6 | 54 | #define TARGET_REG_NAMES_P TRUE |
252b5132 | 55 | #else |
b34976b6 | 56 | #define TARGET_REG_NAMES_P FALSE |
252b5132 RH |
57 | #endif |
58 | #endif | |
59 | ||
0baf16f2 AM |
60 | /* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST, |
61 | HIGHESTA. */ | |
62 | ||
63 | /* #lo(value) denotes the least significant 16 bits of the indicated. */ | |
64 | #define PPC_LO(v) ((v) & 0xffff) | |
65 | ||
66 | /* #hi(value) denotes bits 16 through 31 of the indicated value. */ | |
67 | #define PPC_HI(v) (((v) >> 16) & 0xffff) | |
68 | ||
69 | /* #ha(value) denotes the high adjusted value: bits 16 through 31 of | |
70 | the indicated value, compensating for #lo() being treated as a | |
71 | signed number. */ | |
15c1449b | 72 | #define PPC_HA(v) PPC_HI ((v) + 0x8000) |
0baf16f2 AM |
73 | |
74 | /* #higher(value) denotes bits 32 through 47 of the indicated value. */ | |
2a98c3a6 | 75 | #define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff) |
0baf16f2 AM |
76 | |
77 | /* #highera(value) denotes bits 32 through 47 of the indicated value, | |
78 | compensating for #lo() being treated as a signed number. */ | |
15c1449b | 79 | #define PPC_HIGHERA(v) PPC_HIGHER ((v) + 0x8000) |
0baf16f2 AM |
80 | |
81 | /* #highest(value) denotes bits 48 through 63 of the indicated value. */ | |
2a98c3a6 | 82 | #define PPC_HIGHEST(v) (((v) >> 24 >> 24) & 0xffff) |
0baf16f2 AM |
83 | |
84 | /* #highesta(value) denotes bits 48 through 63 of the indicated value, | |
15c1449b AM |
85 | compensating for #lo being treated as a signed number. */ |
86 | #define PPC_HIGHESTA(v) PPC_HIGHEST ((v) + 0x8000) | |
0baf16f2 | 87 | |
f9c6b907 AM |
88 | #define SEX16(val) (((val) ^ 0x8000) - 0x8000) |
89 | ||
90 | /* For the time being on ppc64, don't report overflow on @h and @ha | |
91 | applied to constants. */ | |
92 | #define REPORT_OVERFLOW_HI 0 | |
0baf16f2 | 93 | |
b34976b6 | 94 | static bfd_boolean reg_names_p = TARGET_REG_NAMES_P; |
252b5132 | 95 | |
98027b10 AM |
96 | static void ppc_macro (char *, const struct powerpc_macro *); |
97 | static void ppc_byte (int); | |
0baf16f2 AM |
98 | |
99 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) | |
98027b10 AM |
100 | static void ppc_tc (int); |
101 | static void ppc_machine (int); | |
0baf16f2 | 102 | #endif |
252b5132 RH |
103 | |
104 | #ifdef OBJ_XCOFF | |
98027b10 AM |
105 | static void ppc_comm (int); |
106 | static void ppc_bb (int); | |
107 | static void ppc_bc (int); | |
108 | static void ppc_bf (int); | |
109 | static void ppc_biei (int); | |
110 | static void ppc_bs (int); | |
111 | static void ppc_eb (int); | |
112 | static void ppc_ec (int); | |
113 | static void ppc_ef (int); | |
114 | static void ppc_es (int); | |
115 | static void ppc_csect (int); | |
85645aed | 116 | static void ppc_dwsect (int); |
98027b10 AM |
117 | static void ppc_change_csect (symbolS *, offsetT); |
118 | static void ppc_function (int); | |
119 | static void ppc_extern (int); | |
120 | static void ppc_lglobl (int); | |
c865e45b | 121 | static void ppc_ref (int); |
98027b10 AM |
122 | static void ppc_section (int); |
123 | static void ppc_named_section (int); | |
124 | static void ppc_stabx (int); | |
125 | static void ppc_rename (int); | |
126 | static void ppc_toc (int); | |
127 | static void ppc_xcoff_cons (int); | |
128 | static void ppc_vbyte (int); | |
252b5132 RH |
129 | #endif |
130 | ||
131 | #ifdef OBJ_ELF | |
98027b10 AM |
132 | static void ppc_elf_rdata (int); |
133 | static void ppc_elf_lcomm (int); | |
6911b7dc | 134 | static void ppc_elf_localentry (int); |
ee67d69a | 135 | static void ppc_elf_abiversion (int); |
005d79fd | 136 | static void ppc_elf_gnu_attribute (int); |
252b5132 RH |
137 | #endif |
138 | ||
139 | #ifdef TE_PE | |
98027b10 AM |
140 | static void ppc_previous (int); |
141 | static void ppc_pdata (int); | |
142 | static void ppc_ydata (int); | |
143 | static void ppc_reldata (int); | |
144 | static void ppc_rdata (int); | |
145 | static void ppc_ualong (int); | |
146 | static void ppc_znop (int); | |
147 | static void ppc_pe_comm (int); | |
148 | static void ppc_pe_section (int); | |
149 | static void ppc_pe_function (int); | |
150 | static void ppc_pe_tocd (int); | |
252b5132 RH |
151 | #endif |
152 | \f | |
153 | /* Generic assembler global variables which must be defined by all | |
154 | targets. */ | |
155 | ||
156 | #ifdef OBJ_ELF | |
157 | /* This string holds the chars that always start a comment. If the | |
158 | pre-processor is disabled, these aren't very useful. The macro | |
159 | tc_comment_chars points to this. We use this, rather than the | |
160 | usual comment_chars, so that we can switch for Solaris conventions. */ | |
161 | static const char ppc_solaris_comment_chars[] = "#!"; | |
162 | static const char ppc_eabi_comment_chars[] = "#"; | |
163 | ||
164 | #ifdef TARGET_SOLARIS_COMMENT | |
165 | const char *ppc_comment_chars = ppc_solaris_comment_chars; | |
166 | #else | |
167 | const char *ppc_comment_chars = ppc_eabi_comment_chars; | |
168 | #endif | |
169 | #else | |
170 | const char comment_chars[] = "#"; | |
171 | #endif | |
172 | ||
173 | /* Characters which start a comment at the beginning of a line. */ | |
174 | const char line_comment_chars[] = "#"; | |
175 | ||
176 | /* Characters which may be used to separate multiple commands on a | |
177 | single line. */ | |
178 | const char line_separator_chars[] = ";"; | |
179 | ||
180 | /* Characters which are used to indicate an exponent in a floating | |
181 | point number. */ | |
182 | const char EXP_CHARS[] = "eE"; | |
183 | ||
184 | /* Characters which mean that a number is a floating point constant, | |
185 | as in 0d1.0. */ | |
186 | const char FLT_CHARS[] = "dD"; | |
5ce8663f | 187 | |
5e02f92e | 188 | /* Anything that can start an operand needs to be mentioned here, |
ac805826 | 189 | to stop the input scrubber eating whitespace. */ |
5e02f92e | 190 | const char ppc_symbol_chars[] = "%["; |
75e21f08 JJ |
191 | |
192 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
193 | int ppc_cie_data_alignment; | |
783de163 | 194 | |
8fbf7334 JL |
195 | /* The dwarf2 minimum instruction length. */ |
196 | int ppc_dwarf2_line_min_insn_length; | |
197 | ||
cef4f754 AM |
198 | /* More than this number of nops in an alignment op gets a branch |
199 | instead. */ | |
200 | unsigned long nop_limit = 4; | |
201 | ||
783de163 AM |
202 | /* The type of processor we are assembling for. This is one or more |
203 | of the PPC_OPCODE flags defined in opcode/ppc.h. */ | |
fa452fa6 | 204 | ppc_cpu_t ppc_cpu = 0; |
776fc418 | 205 | ppc_cpu_t sticky = 0; |
01efc3af | 206 | |
ee67d69a AM |
207 | /* Value for ELF e_flags EF_PPC64_ABI. */ |
208 | unsigned int ppc_abiversion = 0; | |
209 | ||
05f7541e | 210 | #ifdef OBJ_ELF |
01efc3af | 211 | /* Flags set on encountering toc relocs. */ |
4f2a7b51 | 212 | static enum { |
01efc3af AM |
213 | has_large_toc_reloc = 1, |
214 | has_small_toc_reloc = 2 | |
215 | } toc_reloc_types; | |
05f7541e | 216 | #endif |
bf7279d5 AM |
217 | |
218 | /* Warn on emitting data to code sections. */ | |
219 | int warn_476; | |
0f873fd5 | 220 | uint64_t last_insn; |
bf7279d5 AM |
221 | segT last_seg; |
222 | subsegT last_subseg; | |
252b5132 RH |
223 | \f |
224 | /* The target specific pseudo-ops which we support. */ | |
225 | ||
226 | const pseudo_typeS md_pseudo_table[] = | |
227 | { | |
228 | /* Pseudo-ops which must be overridden. */ | |
229 | { "byte", ppc_byte, 0 }, | |
230 | ||
231 | #ifdef OBJ_XCOFF | |
232 | /* Pseudo-ops specific to the RS/6000 XCOFF format. Some of these | |
233 | legitimately belong in the obj-*.c file. However, XCOFF is based | |
234 | on COFF, and is only implemented for the RS/6000. We just use | |
235 | obj-coff.c, and add what we need here. */ | |
236 | { "comm", ppc_comm, 0 }, | |
237 | { "lcomm", ppc_comm, 1 }, | |
238 | { "bb", ppc_bb, 0 }, | |
239 | { "bc", ppc_bc, 0 }, | |
240 | { "bf", ppc_bf, 0 }, | |
241 | { "bi", ppc_biei, 0 }, | |
242 | { "bs", ppc_bs, 0 }, | |
243 | { "csect", ppc_csect, 0 }, | |
85645aed | 244 | { "dwsect", ppc_dwsect, 0 }, |
252b5132 RH |
245 | { "data", ppc_section, 'd' }, |
246 | { "eb", ppc_eb, 0 }, | |
247 | { "ec", ppc_ec, 0 }, | |
248 | { "ef", ppc_ef, 0 }, | |
249 | { "ei", ppc_biei, 1 }, | |
250 | { "es", ppc_es, 0 }, | |
251 | { "extern", ppc_extern, 0 }, | |
252 | { "function", ppc_function, 0 }, | |
253 | { "lglobl", ppc_lglobl, 0 }, | |
c865e45b | 254 | { "ref", ppc_ref, 0 }, |
252b5132 RH |
255 | { "rename", ppc_rename, 0 }, |
256 | { "section", ppc_named_section, 0 }, | |
257 | { "stabx", ppc_stabx, 0 }, | |
258 | { "text", ppc_section, 't' }, | |
259 | { "toc", ppc_toc, 0 }, | |
260 | { "long", ppc_xcoff_cons, 2 }, | |
7f6d05e8 | 261 | { "llong", ppc_xcoff_cons, 3 }, |
252b5132 RH |
262 | { "word", ppc_xcoff_cons, 1 }, |
263 | { "short", ppc_xcoff_cons, 1 }, | |
264 | { "vbyte", ppc_vbyte, 0 }, | |
265 | #endif | |
266 | ||
267 | #ifdef OBJ_ELF | |
62ebcb5c | 268 | { "llong", cons, 8 }, |
252b5132 RH |
269 | { "rdata", ppc_elf_rdata, 0 }, |
270 | { "rodata", ppc_elf_rdata, 0 }, | |
271 | { "lcomm", ppc_elf_lcomm, 0 }, | |
6911b7dc | 272 | { "localentry", ppc_elf_localentry, 0 }, |
ee67d69a | 273 | { "abiversion", ppc_elf_abiversion, 0 }, |
005d79fd | 274 | { "gnu_attribute", ppc_elf_gnu_attribute, 0}, |
252b5132 RH |
275 | #endif |
276 | ||
277 | #ifdef TE_PE | |
99a814a1 | 278 | /* Pseudo-ops specific to the Windows NT PowerPC PE (coff) format. */ |
252b5132 RH |
279 | { "previous", ppc_previous, 0 }, |
280 | { "pdata", ppc_pdata, 0 }, | |
281 | { "ydata", ppc_ydata, 0 }, | |
282 | { "reldata", ppc_reldata, 0 }, | |
283 | { "rdata", ppc_rdata, 0 }, | |
284 | { "ualong", ppc_ualong, 0 }, | |
285 | { "znop", ppc_znop, 0 }, | |
286 | { "comm", ppc_pe_comm, 0 }, | |
287 | { "lcomm", ppc_pe_comm, 1 }, | |
288 | { "section", ppc_pe_section, 0 }, | |
289 | { "function", ppc_pe_function,0 }, | |
290 | { "tocd", ppc_pe_tocd, 0 }, | |
291 | #endif | |
292 | ||
0baf16f2 | 293 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 | 294 | { "tc", ppc_tc, 0 }, |
0baf16f2 AM |
295 | { "machine", ppc_machine, 0 }, |
296 | #endif | |
252b5132 RH |
297 | |
298 | { NULL, NULL, 0 } | |
299 | }; | |
300 | ||
301 | \f | |
99a814a1 AM |
302 | /* Predefined register names if -mregnames (or default for Windows NT). |
303 | In general, there are lots of them, in an attempt to be compatible | |
304 | with a number of other Windows NT assemblers. */ | |
252b5132 RH |
305 | |
306 | /* Structure to hold information about predefined registers. */ | |
307 | struct pd_reg | |
308 | { | |
e0471c16 | 309 | const char *name; |
7e0de605 AM |
310 | unsigned short value; |
311 | unsigned short flags; | |
252b5132 RH |
312 | }; |
313 | ||
314 | /* List of registers that are pre-defined: | |
315 | ||
316 | Each general register has predefined names of the form: | |
317 | 1. r<reg_num> which has the value <reg_num>. | |
318 | 2. r.<reg_num> which has the value <reg_num>. | |
319 | ||
252b5132 RH |
320 | Each floating point register has predefined names of the form: |
321 | 1. f<reg_num> which has the value <reg_num>. | |
322 | 2. f.<reg_num> which has the value <reg_num>. | |
323 | ||
7a899fff C |
324 | Each vector unit register has predefined names of the form: |
325 | 1. v<reg_num> which has the value <reg_num>. | |
326 | 2. v.<reg_num> which has the value <reg_num>. | |
327 | ||
252b5132 RH |
328 | Each condition register has predefined names of the form: |
329 | 1. cr<reg_num> which has the value <reg_num>. | |
330 | 2. cr.<reg_num> which has the value <reg_num>. | |
331 | ||
332 | There are individual registers as well: | |
333 | sp or r.sp has the value 1 | |
334 | rtoc or r.toc has the value 2 | |
252b5132 RH |
335 | xer has the value 1 |
336 | lr has the value 8 | |
337 | ctr has the value 9 | |
252b5132 RH |
338 | dar has the value 19 |
339 | dsisr has the value 18 | |
340 | dec has the value 22 | |
341 | sdr1 has the value 25 | |
342 | srr0 has the value 26 | |
343 | srr1 has the value 27 | |
344 | ||
81d4177b | 345 | The table is sorted. Suitable for searching by a binary search. */ |
252b5132 RH |
346 | |
347 | static const struct pd_reg pre_defined_registers[] = | |
348 | { | |
aa3c112f AM |
349 | /* VSX accumulators. */ |
350 | { "a0", 0, PPC_OPERAND_ACC }, | |
351 | { "a1", 1, PPC_OPERAND_ACC }, | |
352 | { "a2", 2, PPC_OPERAND_ACC }, | |
353 | { "a3", 3, PPC_OPERAND_ACC }, | |
354 | { "a4", 4, PPC_OPERAND_ACC }, | |
355 | { "a5", 5, PPC_OPERAND_ACC }, | |
356 | { "a6", 6, PPC_OPERAND_ACC }, | |
357 | { "a7", 7, PPC_OPERAND_ACC }, | |
358 | ||
7e0de605 AM |
359 | /* Condition Registers */ |
360 | { "cr.0", 0, PPC_OPERAND_CR_REG }, | |
361 | { "cr.1", 1, PPC_OPERAND_CR_REG }, | |
362 | { "cr.2", 2, PPC_OPERAND_CR_REG }, | |
363 | { "cr.3", 3, PPC_OPERAND_CR_REG }, | |
364 | { "cr.4", 4, PPC_OPERAND_CR_REG }, | |
365 | { "cr.5", 5, PPC_OPERAND_CR_REG }, | |
366 | { "cr.6", 6, PPC_OPERAND_CR_REG }, | |
367 | { "cr.7", 7, PPC_OPERAND_CR_REG }, | |
368 | ||
369 | { "cr0", 0, PPC_OPERAND_CR_REG }, | |
370 | { "cr1", 1, PPC_OPERAND_CR_REG }, | |
371 | { "cr2", 2, PPC_OPERAND_CR_REG }, | |
372 | { "cr3", 3, PPC_OPERAND_CR_REG }, | |
373 | { "cr4", 4, PPC_OPERAND_CR_REG }, | |
374 | { "cr5", 5, PPC_OPERAND_CR_REG }, | |
375 | { "cr6", 6, PPC_OPERAND_CR_REG }, | |
376 | { "cr7", 7, PPC_OPERAND_CR_REG }, | |
377 | ||
378 | { "ctr", 9, PPC_OPERAND_SPR }, | |
379 | { "dar", 19, PPC_OPERAND_SPR }, | |
380 | { "dec", 22, PPC_OPERAND_SPR }, | |
381 | { "dsisr", 18, PPC_OPERAND_SPR }, | |
382 | ||
383 | /* Floating point registers */ | |
384 | { "f.0", 0, PPC_OPERAND_FPR }, | |
385 | { "f.1", 1, PPC_OPERAND_FPR }, | |
386 | { "f.10", 10, PPC_OPERAND_FPR }, | |
387 | { "f.11", 11, PPC_OPERAND_FPR }, | |
388 | { "f.12", 12, PPC_OPERAND_FPR }, | |
389 | { "f.13", 13, PPC_OPERAND_FPR }, | |
390 | { "f.14", 14, PPC_OPERAND_FPR }, | |
391 | { "f.15", 15, PPC_OPERAND_FPR }, | |
392 | { "f.16", 16, PPC_OPERAND_FPR }, | |
393 | { "f.17", 17, PPC_OPERAND_FPR }, | |
394 | { "f.18", 18, PPC_OPERAND_FPR }, | |
395 | { "f.19", 19, PPC_OPERAND_FPR }, | |
396 | { "f.2", 2, PPC_OPERAND_FPR }, | |
397 | { "f.20", 20, PPC_OPERAND_FPR }, | |
398 | { "f.21", 21, PPC_OPERAND_FPR }, | |
399 | { "f.22", 22, PPC_OPERAND_FPR }, | |
400 | { "f.23", 23, PPC_OPERAND_FPR }, | |
401 | { "f.24", 24, PPC_OPERAND_FPR }, | |
402 | { "f.25", 25, PPC_OPERAND_FPR }, | |
403 | { "f.26", 26, PPC_OPERAND_FPR }, | |
404 | { "f.27", 27, PPC_OPERAND_FPR }, | |
405 | { "f.28", 28, PPC_OPERAND_FPR }, | |
406 | { "f.29", 29, PPC_OPERAND_FPR }, | |
407 | { "f.3", 3, PPC_OPERAND_FPR }, | |
408 | { "f.30", 30, PPC_OPERAND_FPR }, | |
409 | { "f.31", 31, PPC_OPERAND_FPR }, | |
410 | { "f.32", 32, PPC_OPERAND_VSR }, | |
411 | { "f.33", 33, PPC_OPERAND_VSR }, | |
412 | { "f.34", 34, PPC_OPERAND_VSR }, | |
413 | { "f.35", 35, PPC_OPERAND_VSR }, | |
414 | { "f.36", 36, PPC_OPERAND_VSR }, | |
415 | { "f.37", 37, PPC_OPERAND_VSR }, | |
416 | { "f.38", 38, PPC_OPERAND_VSR }, | |
417 | { "f.39", 39, PPC_OPERAND_VSR }, | |
418 | { "f.4", 4, PPC_OPERAND_FPR }, | |
419 | { "f.40", 40, PPC_OPERAND_VSR }, | |
420 | { "f.41", 41, PPC_OPERAND_VSR }, | |
421 | { "f.42", 42, PPC_OPERAND_VSR }, | |
422 | { "f.43", 43, PPC_OPERAND_VSR }, | |
423 | { "f.44", 44, PPC_OPERAND_VSR }, | |
424 | { "f.45", 45, PPC_OPERAND_VSR }, | |
425 | { "f.46", 46, PPC_OPERAND_VSR }, | |
426 | { "f.47", 47, PPC_OPERAND_VSR }, | |
427 | { "f.48", 48, PPC_OPERAND_VSR }, | |
428 | { "f.49", 49, PPC_OPERAND_VSR }, | |
429 | { "f.5", 5, PPC_OPERAND_FPR }, | |
430 | { "f.50", 50, PPC_OPERAND_VSR }, | |
431 | { "f.51", 51, PPC_OPERAND_VSR }, | |
432 | { "f.52", 52, PPC_OPERAND_VSR }, | |
433 | { "f.53", 53, PPC_OPERAND_VSR }, | |
434 | { "f.54", 54, PPC_OPERAND_VSR }, | |
435 | { "f.55", 55, PPC_OPERAND_VSR }, | |
436 | { "f.56", 56, PPC_OPERAND_VSR }, | |
437 | { "f.57", 57, PPC_OPERAND_VSR }, | |
438 | { "f.58", 58, PPC_OPERAND_VSR }, | |
439 | { "f.59", 59, PPC_OPERAND_VSR }, | |
440 | { "f.6", 6, PPC_OPERAND_FPR }, | |
441 | { "f.60", 60, PPC_OPERAND_VSR }, | |
442 | { "f.61", 61, PPC_OPERAND_VSR }, | |
443 | { "f.62", 62, PPC_OPERAND_VSR }, | |
444 | { "f.63", 63, PPC_OPERAND_VSR }, | |
445 | { "f.7", 7, PPC_OPERAND_FPR }, | |
446 | { "f.8", 8, PPC_OPERAND_FPR }, | |
447 | { "f.9", 9, PPC_OPERAND_FPR }, | |
448 | ||
449 | { "f0", 0, PPC_OPERAND_FPR }, | |
450 | { "f1", 1, PPC_OPERAND_FPR }, | |
451 | { "f10", 10, PPC_OPERAND_FPR }, | |
452 | { "f11", 11, PPC_OPERAND_FPR }, | |
453 | { "f12", 12, PPC_OPERAND_FPR }, | |
454 | { "f13", 13, PPC_OPERAND_FPR }, | |
455 | { "f14", 14, PPC_OPERAND_FPR }, | |
456 | { "f15", 15, PPC_OPERAND_FPR }, | |
457 | { "f16", 16, PPC_OPERAND_FPR }, | |
458 | { "f17", 17, PPC_OPERAND_FPR }, | |
459 | { "f18", 18, PPC_OPERAND_FPR }, | |
460 | { "f19", 19, PPC_OPERAND_FPR }, | |
461 | { "f2", 2, PPC_OPERAND_FPR }, | |
462 | { "f20", 20, PPC_OPERAND_FPR }, | |
463 | { "f21", 21, PPC_OPERAND_FPR }, | |
464 | { "f22", 22, PPC_OPERAND_FPR }, | |
465 | { "f23", 23, PPC_OPERAND_FPR }, | |
466 | { "f24", 24, PPC_OPERAND_FPR }, | |
467 | { "f25", 25, PPC_OPERAND_FPR }, | |
468 | { "f26", 26, PPC_OPERAND_FPR }, | |
469 | { "f27", 27, PPC_OPERAND_FPR }, | |
470 | { "f28", 28, PPC_OPERAND_FPR }, | |
471 | { "f29", 29, PPC_OPERAND_FPR }, | |
472 | { "f3", 3, PPC_OPERAND_FPR }, | |
473 | { "f30", 30, PPC_OPERAND_FPR }, | |
474 | { "f31", 31, PPC_OPERAND_FPR }, | |
475 | { "f32", 32, PPC_OPERAND_VSR }, | |
476 | { "f33", 33, PPC_OPERAND_VSR }, | |
477 | { "f34", 34, PPC_OPERAND_VSR }, | |
478 | { "f35", 35, PPC_OPERAND_VSR }, | |
479 | { "f36", 36, PPC_OPERAND_VSR }, | |
480 | { "f37", 37, PPC_OPERAND_VSR }, | |
481 | { "f38", 38, PPC_OPERAND_VSR }, | |
482 | { "f39", 39, PPC_OPERAND_VSR }, | |
483 | { "f4", 4, PPC_OPERAND_FPR }, | |
484 | { "f40", 40, PPC_OPERAND_VSR }, | |
485 | { "f41", 41, PPC_OPERAND_VSR }, | |
486 | { "f42", 42, PPC_OPERAND_VSR }, | |
487 | { "f43", 43, PPC_OPERAND_VSR }, | |
488 | { "f44", 44, PPC_OPERAND_VSR }, | |
489 | { "f45", 45, PPC_OPERAND_VSR }, | |
490 | { "f46", 46, PPC_OPERAND_VSR }, | |
491 | { "f47", 47, PPC_OPERAND_VSR }, | |
492 | { "f48", 48, PPC_OPERAND_VSR }, | |
493 | { "f49", 49, PPC_OPERAND_VSR }, | |
494 | { "f5", 5, PPC_OPERAND_FPR }, | |
495 | { "f50", 50, PPC_OPERAND_VSR }, | |
496 | { "f51", 51, PPC_OPERAND_VSR }, | |
497 | { "f52", 52, PPC_OPERAND_VSR }, | |
498 | { "f53", 53, PPC_OPERAND_VSR }, | |
499 | { "f54", 54, PPC_OPERAND_VSR }, | |
500 | { "f55", 55, PPC_OPERAND_VSR }, | |
501 | { "f56", 56, PPC_OPERAND_VSR }, | |
502 | { "f57", 57, PPC_OPERAND_VSR }, | |
503 | { "f58", 58, PPC_OPERAND_VSR }, | |
504 | { "f59", 59, PPC_OPERAND_VSR }, | |
505 | { "f6", 6, PPC_OPERAND_FPR }, | |
506 | { "f60", 60, PPC_OPERAND_VSR }, | |
507 | { "f61", 61, PPC_OPERAND_VSR }, | |
508 | { "f62", 62, PPC_OPERAND_VSR }, | |
509 | { "f63", 63, PPC_OPERAND_VSR }, | |
510 | { "f7", 7, PPC_OPERAND_FPR }, | |
511 | { "f8", 8, PPC_OPERAND_FPR }, | |
512 | { "f9", 9, PPC_OPERAND_FPR }, | |
252b5132 | 513 | |
c3d65c1c | 514 | /* Quantization registers used with pair single instructions. */ |
7e0de605 AM |
515 | { "gqr.0", 0, PPC_OPERAND_GQR }, |
516 | { "gqr.1", 1, PPC_OPERAND_GQR }, | |
517 | { "gqr.2", 2, PPC_OPERAND_GQR }, | |
518 | { "gqr.3", 3, PPC_OPERAND_GQR }, | |
519 | { "gqr.4", 4, PPC_OPERAND_GQR }, | |
520 | { "gqr.5", 5, PPC_OPERAND_GQR }, | |
521 | { "gqr.6", 6, PPC_OPERAND_GQR }, | |
522 | { "gqr.7", 7, PPC_OPERAND_GQR }, | |
523 | { "gqr0", 0, PPC_OPERAND_GQR }, | |
524 | { "gqr1", 1, PPC_OPERAND_GQR }, | |
525 | { "gqr2", 2, PPC_OPERAND_GQR }, | |
526 | { "gqr3", 3, PPC_OPERAND_GQR }, | |
527 | { "gqr4", 4, PPC_OPERAND_GQR }, | |
528 | { "gqr5", 5, PPC_OPERAND_GQR }, | |
529 | { "gqr6", 6, PPC_OPERAND_GQR }, | |
530 | { "gqr7", 7, PPC_OPERAND_GQR }, | |
531 | ||
532 | { "lr", 8, PPC_OPERAND_SPR }, | |
533 | ||
534 | /* General Purpose Registers */ | |
535 | { "r.0", 0, PPC_OPERAND_GPR }, | |
536 | { "r.1", 1, PPC_OPERAND_GPR }, | |
537 | { "r.10", 10, PPC_OPERAND_GPR }, | |
538 | { "r.11", 11, PPC_OPERAND_GPR }, | |
539 | { "r.12", 12, PPC_OPERAND_GPR }, | |
540 | { "r.13", 13, PPC_OPERAND_GPR }, | |
541 | { "r.14", 14, PPC_OPERAND_GPR }, | |
542 | { "r.15", 15, PPC_OPERAND_GPR }, | |
543 | { "r.16", 16, PPC_OPERAND_GPR }, | |
544 | { "r.17", 17, PPC_OPERAND_GPR }, | |
545 | { "r.18", 18, PPC_OPERAND_GPR }, | |
546 | { "r.19", 19, PPC_OPERAND_GPR }, | |
547 | { "r.2", 2, PPC_OPERAND_GPR }, | |
548 | { "r.20", 20, PPC_OPERAND_GPR }, | |
549 | { "r.21", 21, PPC_OPERAND_GPR }, | |
550 | { "r.22", 22, PPC_OPERAND_GPR }, | |
551 | { "r.23", 23, PPC_OPERAND_GPR }, | |
552 | { "r.24", 24, PPC_OPERAND_GPR }, | |
553 | { "r.25", 25, PPC_OPERAND_GPR }, | |
554 | { "r.26", 26, PPC_OPERAND_GPR }, | |
555 | { "r.27", 27, PPC_OPERAND_GPR }, | |
556 | { "r.28", 28, PPC_OPERAND_GPR }, | |
557 | { "r.29", 29, PPC_OPERAND_GPR }, | |
558 | { "r.3", 3, PPC_OPERAND_GPR }, | |
559 | { "r.30", 30, PPC_OPERAND_GPR }, | |
560 | { "r.31", 31, PPC_OPERAND_GPR }, | |
561 | { "r.4", 4, PPC_OPERAND_GPR }, | |
562 | { "r.5", 5, PPC_OPERAND_GPR }, | |
563 | { "r.6", 6, PPC_OPERAND_GPR }, | |
564 | { "r.7", 7, PPC_OPERAND_GPR }, | |
565 | { "r.8", 8, PPC_OPERAND_GPR }, | |
566 | { "r.9", 9, PPC_OPERAND_GPR }, | |
567 | ||
568 | { "r.sp", 1, PPC_OPERAND_GPR }, | |
569 | ||
570 | { "r.toc", 2, PPC_OPERAND_GPR }, | |
571 | ||
572 | { "r0", 0, PPC_OPERAND_GPR }, | |
573 | { "r1", 1, PPC_OPERAND_GPR }, | |
574 | { "r10", 10, PPC_OPERAND_GPR }, | |
575 | { "r11", 11, PPC_OPERAND_GPR }, | |
576 | { "r12", 12, PPC_OPERAND_GPR }, | |
577 | { "r13", 13, PPC_OPERAND_GPR }, | |
578 | { "r14", 14, PPC_OPERAND_GPR }, | |
579 | { "r15", 15, PPC_OPERAND_GPR }, | |
580 | { "r16", 16, PPC_OPERAND_GPR }, | |
581 | { "r17", 17, PPC_OPERAND_GPR }, | |
582 | { "r18", 18, PPC_OPERAND_GPR }, | |
583 | { "r19", 19, PPC_OPERAND_GPR }, | |
584 | { "r2", 2, PPC_OPERAND_GPR }, | |
585 | { "r20", 20, PPC_OPERAND_GPR }, | |
586 | { "r21", 21, PPC_OPERAND_GPR }, | |
587 | { "r22", 22, PPC_OPERAND_GPR }, | |
588 | { "r23", 23, PPC_OPERAND_GPR }, | |
589 | { "r24", 24, PPC_OPERAND_GPR }, | |
590 | { "r25", 25, PPC_OPERAND_GPR }, | |
591 | { "r26", 26, PPC_OPERAND_GPR }, | |
592 | { "r27", 27, PPC_OPERAND_GPR }, | |
593 | { "r28", 28, PPC_OPERAND_GPR }, | |
594 | { "r29", 29, PPC_OPERAND_GPR }, | |
595 | { "r3", 3, PPC_OPERAND_GPR }, | |
596 | { "r30", 30, PPC_OPERAND_GPR }, | |
597 | { "r31", 31, PPC_OPERAND_GPR }, | |
598 | { "r4", 4, PPC_OPERAND_GPR }, | |
599 | { "r5", 5, PPC_OPERAND_GPR }, | |
600 | { "r6", 6, PPC_OPERAND_GPR }, | |
601 | { "r7", 7, PPC_OPERAND_GPR }, | |
602 | { "r8", 8, PPC_OPERAND_GPR }, | |
603 | { "r9", 9, PPC_OPERAND_GPR }, | |
604 | ||
605 | { "rtoc", 2, PPC_OPERAND_GPR }, | |
606 | ||
607 | { "sdr1", 25, PPC_OPERAND_SPR }, | |
608 | ||
609 | { "sp", 1, PPC_OPERAND_GPR }, | |
610 | ||
611 | { "srr0", 26, PPC_OPERAND_SPR }, | |
612 | { "srr1", 27, PPC_OPERAND_SPR }, | |
613 | ||
614 | /* Vector (Altivec/VMX) registers */ | |
615 | { "v.0", 0, PPC_OPERAND_VR }, | |
616 | { "v.1", 1, PPC_OPERAND_VR }, | |
617 | { "v.10", 10, PPC_OPERAND_VR }, | |
618 | { "v.11", 11, PPC_OPERAND_VR }, | |
619 | { "v.12", 12, PPC_OPERAND_VR }, | |
620 | { "v.13", 13, PPC_OPERAND_VR }, | |
621 | { "v.14", 14, PPC_OPERAND_VR }, | |
622 | { "v.15", 15, PPC_OPERAND_VR }, | |
623 | { "v.16", 16, PPC_OPERAND_VR }, | |
624 | { "v.17", 17, PPC_OPERAND_VR }, | |
625 | { "v.18", 18, PPC_OPERAND_VR }, | |
626 | { "v.19", 19, PPC_OPERAND_VR }, | |
627 | { "v.2", 2, PPC_OPERAND_VR }, | |
628 | { "v.20", 20, PPC_OPERAND_VR }, | |
629 | { "v.21", 21, PPC_OPERAND_VR }, | |
630 | { "v.22", 22, PPC_OPERAND_VR }, | |
631 | { "v.23", 23, PPC_OPERAND_VR }, | |
632 | { "v.24", 24, PPC_OPERAND_VR }, | |
633 | { "v.25", 25, PPC_OPERAND_VR }, | |
634 | { "v.26", 26, PPC_OPERAND_VR }, | |
635 | { "v.27", 27, PPC_OPERAND_VR }, | |
636 | { "v.28", 28, PPC_OPERAND_VR }, | |
637 | { "v.29", 29, PPC_OPERAND_VR }, | |
638 | { "v.3", 3, PPC_OPERAND_VR }, | |
639 | { "v.30", 30, PPC_OPERAND_VR }, | |
640 | { "v.31", 31, PPC_OPERAND_VR }, | |
641 | { "v.4", 4, PPC_OPERAND_VR }, | |
642 | { "v.5", 5, PPC_OPERAND_VR }, | |
643 | { "v.6", 6, PPC_OPERAND_VR }, | |
644 | { "v.7", 7, PPC_OPERAND_VR }, | |
645 | { "v.8", 8, PPC_OPERAND_VR }, | |
646 | { "v.9", 9, PPC_OPERAND_VR }, | |
647 | ||
648 | { "v0", 0, PPC_OPERAND_VR }, | |
649 | { "v1", 1, PPC_OPERAND_VR }, | |
650 | { "v10", 10, PPC_OPERAND_VR }, | |
651 | { "v11", 11, PPC_OPERAND_VR }, | |
652 | { "v12", 12, PPC_OPERAND_VR }, | |
653 | { "v13", 13, PPC_OPERAND_VR }, | |
654 | { "v14", 14, PPC_OPERAND_VR }, | |
655 | { "v15", 15, PPC_OPERAND_VR }, | |
656 | { "v16", 16, PPC_OPERAND_VR }, | |
657 | { "v17", 17, PPC_OPERAND_VR }, | |
658 | { "v18", 18, PPC_OPERAND_VR }, | |
659 | { "v19", 19, PPC_OPERAND_VR }, | |
660 | { "v2", 2, PPC_OPERAND_VR }, | |
661 | { "v20", 20, PPC_OPERAND_VR }, | |
662 | { "v21", 21, PPC_OPERAND_VR }, | |
663 | { "v22", 22, PPC_OPERAND_VR }, | |
664 | { "v23", 23, PPC_OPERAND_VR }, | |
665 | { "v24", 24, PPC_OPERAND_VR }, | |
666 | { "v25", 25, PPC_OPERAND_VR }, | |
667 | { "v26", 26, PPC_OPERAND_VR }, | |
668 | { "v27", 27, PPC_OPERAND_VR }, | |
669 | { "v28", 28, PPC_OPERAND_VR }, | |
670 | { "v29", 29, PPC_OPERAND_VR }, | |
671 | { "v3", 3, PPC_OPERAND_VR }, | |
672 | { "v30", 30, PPC_OPERAND_VR }, | |
673 | { "v31", 31, PPC_OPERAND_VR }, | |
674 | { "v4", 4, PPC_OPERAND_VR }, | |
675 | { "v5", 5, PPC_OPERAND_VR }, | |
676 | { "v6", 6, PPC_OPERAND_VR }, | |
677 | { "v7", 7, PPC_OPERAND_VR }, | |
678 | { "v8", 8, PPC_OPERAND_VR }, | |
679 | { "v9", 9, PPC_OPERAND_VR }, | |
680 | ||
681 | /* Vector Scalar (VSX) registers (ISA 2.06). */ | |
682 | { "vs.0", 0, PPC_OPERAND_VSR }, | |
683 | { "vs.1", 1, PPC_OPERAND_VSR }, | |
684 | { "vs.10", 10, PPC_OPERAND_VSR }, | |
685 | { "vs.11", 11, PPC_OPERAND_VSR }, | |
686 | { "vs.12", 12, PPC_OPERAND_VSR }, | |
687 | { "vs.13", 13, PPC_OPERAND_VSR }, | |
688 | { "vs.14", 14, PPC_OPERAND_VSR }, | |
689 | { "vs.15", 15, PPC_OPERAND_VSR }, | |
690 | { "vs.16", 16, PPC_OPERAND_VSR }, | |
691 | { "vs.17", 17, PPC_OPERAND_VSR }, | |
692 | { "vs.18", 18, PPC_OPERAND_VSR }, | |
693 | { "vs.19", 19, PPC_OPERAND_VSR }, | |
694 | { "vs.2", 2, PPC_OPERAND_VSR }, | |
695 | { "vs.20", 20, PPC_OPERAND_VSR }, | |
696 | { "vs.21", 21, PPC_OPERAND_VSR }, | |
697 | { "vs.22", 22, PPC_OPERAND_VSR }, | |
698 | { "vs.23", 23, PPC_OPERAND_VSR }, | |
699 | { "vs.24", 24, PPC_OPERAND_VSR }, | |
700 | { "vs.25", 25, PPC_OPERAND_VSR }, | |
701 | { "vs.26", 26, PPC_OPERAND_VSR }, | |
702 | { "vs.27", 27, PPC_OPERAND_VSR }, | |
703 | { "vs.28", 28, PPC_OPERAND_VSR }, | |
704 | { "vs.29", 29, PPC_OPERAND_VSR }, | |
705 | { "vs.3", 3, PPC_OPERAND_VSR }, | |
706 | { "vs.30", 30, PPC_OPERAND_VSR }, | |
707 | { "vs.31", 31, PPC_OPERAND_VSR }, | |
708 | { "vs.32", 32, PPC_OPERAND_VSR }, | |
709 | { "vs.33", 33, PPC_OPERAND_VSR }, | |
710 | { "vs.34", 34, PPC_OPERAND_VSR }, | |
711 | { "vs.35", 35, PPC_OPERAND_VSR }, | |
712 | { "vs.36", 36, PPC_OPERAND_VSR }, | |
713 | { "vs.37", 37, PPC_OPERAND_VSR }, | |
714 | { "vs.38", 38, PPC_OPERAND_VSR }, | |
715 | { "vs.39", 39, PPC_OPERAND_VSR }, | |
716 | { "vs.4", 4, PPC_OPERAND_VSR }, | |
717 | { "vs.40", 40, PPC_OPERAND_VSR }, | |
718 | { "vs.41", 41, PPC_OPERAND_VSR }, | |
719 | { "vs.42", 42, PPC_OPERAND_VSR }, | |
720 | { "vs.43", 43, PPC_OPERAND_VSR }, | |
721 | { "vs.44", 44, PPC_OPERAND_VSR }, | |
722 | { "vs.45", 45, PPC_OPERAND_VSR }, | |
723 | { "vs.46", 46, PPC_OPERAND_VSR }, | |
724 | { "vs.47", 47, PPC_OPERAND_VSR }, | |
725 | { "vs.48", 48, PPC_OPERAND_VSR }, | |
726 | { "vs.49", 49, PPC_OPERAND_VSR }, | |
727 | { "vs.5", 5, PPC_OPERAND_VSR }, | |
728 | { "vs.50", 50, PPC_OPERAND_VSR }, | |
729 | { "vs.51", 51, PPC_OPERAND_VSR }, | |
730 | { "vs.52", 52, PPC_OPERAND_VSR }, | |
731 | { "vs.53", 53, PPC_OPERAND_VSR }, | |
732 | { "vs.54", 54, PPC_OPERAND_VSR }, | |
733 | { "vs.55", 55, PPC_OPERAND_VSR }, | |
734 | { "vs.56", 56, PPC_OPERAND_VSR }, | |
735 | { "vs.57", 57, PPC_OPERAND_VSR }, | |
736 | { "vs.58", 58, PPC_OPERAND_VSR }, | |
737 | { "vs.59", 59, PPC_OPERAND_VSR }, | |
738 | { "vs.6", 6, PPC_OPERAND_VSR }, | |
739 | { "vs.60", 60, PPC_OPERAND_VSR }, | |
740 | { "vs.61", 61, PPC_OPERAND_VSR }, | |
741 | { "vs.62", 62, PPC_OPERAND_VSR }, | |
742 | { "vs.63", 63, PPC_OPERAND_VSR }, | |
743 | { "vs.7", 7, PPC_OPERAND_VSR }, | |
744 | { "vs.8", 8, PPC_OPERAND_VSR }, | |
745 | { "vs.9", 9, PPC_OPERAND_VSR }, | |
746 | ||
747 | { "vs0", 0, PPC_OPERAND_VSR }, | |
748 | { "vs1", 1, PPC_OPERAND_VSR }, | |
749 | { "vs10", 10, PPC_OPERAND_VSR }, | |
750 | { "vs11", 11, PPC_OPERAND_VSR }, | |
751 | { "vs12", 12, PPC_OPERAND_VSR }, | |
752 | { "vs13", 13, PPC_OPERAND_VSR }, | |
753 | { "vs14", 14, PPC_OPERAND_VSR }, | |
754 | { "vs15", 15, PPC_OPERAND_VSR }, | |
755 | { "vs16", 16, PPC_OPERAND_VSR }, | |
756 | { "vs17", 17, PPC_OPERAND_VSR }, | |
757 | { "vs18", 18, PPC_OPERAND_VSR }, | |
758 | { "vs19", 19, PPC_OPERAND_VSR }, | |
759 | { "vs2", 2, PPC_OPERAND_VSR }, | |
760 | { "vs20", 20, PPC_OPERAND_VSR }, | |
761 | { "vs21", 21, PPC_OPERAND_VSR }, | |
762 | { "vs22", 22, PPC_OPERAND_VSR }, | |
763 | { "vs23", 23, PPC_OPERAND_VSR }, | |
764 | { "vs24", 24, PPC_OPERAND_VSR }, | |
765 | { "vs25", 25, PPC_OPERAND_VSR }, | |
766 | { "vs26", 26, PPC_OPERAND_VSR }, | |
767 | { "vs27", 27, PPC_OPERAND_VSR }, | |
768 | { "vs28", 28, PPC_OPERAND_VSR }, | |
769 | { "vs29", 29, PPC_OPERAND_VSR }, | |
770 | { "vs3", 3, PPC_OPERAND_VSR }, | |
771 | { "vs30", 30, PPC_OPERAND_VSR }, | |
772 | { "vs31", 31, PPC_OPERAND_VSR }, | |
773 | { "vs32", 32, PPC_OPERAND_VSR }, | |
774 | { "vs33", 33, PPC_OPERAND_VSR }, | |
775 | { "vs34", 34, PPC_OPERAND_VSR }, | |
776 | { "vs35", 35, PPC_OPERAND_VSR }, | |
777 | { "vs36", 36, PPC_OPERAND_VSR }, | |
778 | { "vs37", 37, PPC_OPERAND_VSR }, | |
779 | { "vs38", 38, PPC_OPERAND_VSR }, | |
780 | { "vs39", 39, PPC_OPERAND_VSR }, | |
781 | { "vs4", 4, PPC_OPERAND_VSR }, | |
782 | { "vs40", 40, PPC_OPERAND_VSR }, | |
783 | { "vs41", 41, PPC_OPERAND_VSR }, | |
784 | { "vs42", 42, PPC_OPERAND_VSR }, | |
785 | { "vs43", 43, PPC_OPERAND_VSR }, | |
786 | { "vs44", 44, PPC_OPERAND_VSR }, | |
787 | { "vs45", 45, PPC_OPERAND_VSR }, | |
788 | { "vs46", 46, PPC_OPERAND_VSR }, | |
789 | { "vs47", 47, PPC_OPERAND_VSR }, | |
790 | { "vs48", 48, PPC_OPERAND_VSR }, | |
791 | { "vs49", 49, PPC_OPERAND_VSR }, | |
792 | { "vs5", 5, PPC_OPERAND_VSR }, | |
793 | { "vs50", 50, PPC_OPERAND_VSR }, | |
794 | { "vs51", 51, PPC_OPERAND_VSR }, | |
795 | { "vs52", 52, PPC_OPERAND_VSR }, | |
796 | { "vs53", 53, PPC_OPERAND_VSR }, | |
797 | { "vs54", 54, PPC_OPERAND_VSR }, | |
798 | { "vs55", 55, PPC_OPERAND_VSR }, | |
799 | { "vs56", 56, PPC_OPERAND_VSR }, | |
800 | { "vs57", 57, PPC_OPERAND_VSR }, | |
801 | { "vs58", 58, PPC_OPERAND_VSR }, | |
802 | { "vs59", 59, PPC_OPERAND_VSR }, | |
803 | { "vs6", 6, PPC_OPERAND_VSR }, | |
804 | { "vs60", 60, PPC_OPERAND_VSR }, | |
805 | { "vs61", 61, PPC_OPERAND_VSR }, | |
806 | { "vs62", 62, PPC_OPERAND_VSR }, | |
807 | { "vs63", 63, PPC_OPERAND_VSR }, | |
808 | { "vs7", 7, PPC_OPERAND_VSR }, | |
809 | { "vs8", 8, PPC_OPERAND_VSR }, | |
810 | { "vs9", 9, PPC_OPERAND_VSR }, | |
811 | ||
812 | { "xer", 1, PPC_OPERAND_SPR } | |
252b5132 RH |
813 | }; |
814 | ||
bc805888 | 815 | #define REG_NAME_CNT (sizeof (pre_defined_registers) / sizeof (struct pd_reg)) |
252b5132 RH |
816 | |
817 | /* Given NAME, find the register number associated with that name, return | |
818 | the integer value associated with the given name or -1 on failure. */ | |
819 | ||
7e0de605 | 820 | static const struct pd_reg * |
98027b10 | 821 | reg_name_search (const struct pd_reg *regs, int regcount, const char *name) |
252b5132 RH |
822 | { |
823 | int middle, low, high; | |
824 | int cmp; | |
825 | ||
826 | low = 0; | |
827 | high = regcount - 1; | |
828 | ||
829 | do | |
830 | { | |
831 | middle = (low + high) / 2; | |
832 | cmp = strcasecmp (name, regs[middle].name); | |
833 | if (cmp < 0) | |
834 | high = middle - 1; | |
835 | else if (cmp > 0) | |
836 | low = middle + 1; | |
837 | else | |
7e0de605 | 838 | return ®s[middle]; |
252b5132 RH |
839 | } |
840 | while (low <= high); | |
841 | ||
7e0de605 | 842 | return NULL; |
252b5132 RH |
843 | } |
844 | ||
845 | /* | |
99a814a1 | 846 | * Summary of register_name. |
252b5132 RH |
847 | * |
848 | * in: Input_line_pointer points to 1st char of operand. | |
849 | * | |
850 | * out: A expressionS. | |
851 | * The operand may have been a register: in this case, X_op == O_register, | |
852 | * X_add_number is set to the register number, and truth is returned. | |
853 | * Input_line_pointer->(next non-blank) char after operand, or is in its | |
854 | * original state. | |
855 | */ | |
856 | ||
b34976b6 | 857 | static bfd_boolean |
98027b10 | 858 | register_name (expressionS *expressionP) |
252b5132 | 859 | { |
7e0de605 | 860 | const struct pd_reg *reg; |
252b5132 RH |
861 | char *name; |
862 | char *start; | |
863 | char c; | |
864 | ||
99a814a1 | 865 | /* Find the spelling of the operand. */ |
252b5132 | 866 | start = name = input_line_pointer; |
3882b010 | 867 | if (name[0] == '%' && ISALPHA (name[1])) |
252b5132 RH |
868 | name = ++input_line_pointer; |
869 | ||
3882b010 | 870 | else if (!reg_names_p || !ISALPHA (name[0])) |
b34976b6 | 871 | return FALSE; |
252b5132 | 872 | |
d02603dc | 873 | c = get_symbol_name (&name); |
7e0de605 | 874 | reg = reg_name_search (pre_defined_registers, REG_NAME_CNT, name); |
252b5132 | 875 | |
468cced8 AM |
876 | /* Put back the delimiting char. */ |
877 | *input_line_pointer = c; | |
878 | ||
99a814a1 | 879 | /* Look to see if it's in the register table. */ |
7e0de605 | 880 | if (reg != NULL) |
252b5132 RH |
881 | { |
882 | expressionP->X_op = O_register; | |
7e0de605 AM |
883 | expressionP->X_add_number = reg->value; |
884 | expressionP->X_md = reg->flags; | |
81d4177b | 885 | |
99a814a1 | 886 | /* Make the rest nice. */ |
252b5132 RH |
887 | expressionP->X_add_symbol = NULL; |
888 | expressionP->X_op_symbol = NULL; | |
b34976b6 | 889 | return TRUE; |
252b5132 | 890 | } |
468cced8 AM |
891 | |
892 | /* Reset the line as if we had not done anything. */ | |
893 | input_line_pointer = start; | |
b34976b6 | 894 | return FALSE; |
252b5132 RH |
895 | } |
896 | \f | |
897 | /* This function is called for each symbol seen in an expression. It | |
898 | handles the special parsing which PowerPC assemblers are supposed | |
899 | to use for condition codes. */ | |
900 | ||
901 | /* Whether to do the special parsing. */ | |
b34976b6 | 902 | static bfd_boolean cr_operand; |
252b5132 RH |
903 | |
904 | /* Names to recognize in a condition code. This table is sorted. */ | |
905 | static const struct pd_reg cr_names[] = | |
906 | { | |
7e0de605 AM |
907 | { "cr0", 0, PPC_OPERAND_CR_REG }, |
908 | { "cr1", 1, PPC_OPERAND_CR_REG }, | |
909 | { "cr2", 2, PPC_OPERAND_CR_REG }, | |
910 | { "cr3", 3, PPC_OPERAND_CR_REG }, | |
911 | { "cr4", 4, PPC_OPERAND_CR_REG }, | |
912 | { "cr5", 5, PPC_OPERAND_CR_REG }, | |
913 | { "cr6", 6, PPC_OPERAND_CR_REG }, | |
914 | { "cr7", 7, PPC_OPERAND_CR_REG }, | |
915 | { "eq", 2, PPC_OPERAND_CR_BIT }, | |
916 | { "gt", 1, PPC_OPERAND_CR_BIT }, | |
917 | { "lt", 0, PPC_OPERAND_CR_BIT }, | |
918 | { "so", 3, PPC_OPERAND_CR_BIT }, | |
919 | { "un", 3, PPC_OPERAND_CR_BIT } | |
252b5132 RH |
920 | }; |
921 | ||
922 | /* Parsing function. This returns non-zero if it recognized an | |
923 | expression. */ | |
924 | ||
925 | int | |
91d6fa6a | 926 | ppc_parse_name (const char *name, expressionS *exp) |
252b5132 | 927 | { |
7e0de605 | 928 | const struct pd_reg *reg; |
252b5132 RH |
929 | |
930 | if (! cr_operand) | |
931 | return 0; | |
932 | ||
13abbae3 AM |
933 | if (*name == '%') |
934 | ++name; | |
7e0de605 | 935 | reg = reg_name_search (cr_names, sizeof cr_names / sizeof cr_names[0], |
252b5132 | 936 | name); |
7e0de605 | 937 | if (reg == NULL) |
252b5132 RH |
938 | return 0; |
939 | ||
7e0de605 AM |
940 | exp->X_op = O_register; |
941 | exp->X_add_number = reg->value; | |
942 | exp->X_md = reg->flags; | |
252b5132 RH |
943 | |
944 | return 1; | |
945 | } | |
7e0de605 AM |
946 | |
947 | /* Propagate X_md and check register expressions. This is to support | |
948 | condition codes like 4*cr5+eq. */ | |
949 | ||
950 | int | |
951 | ppc_optimize_expr (expressionS *left, operatorT op, expressionS *right) | |
952 | { | |
953 | /* Accept 4*cr<n> and cr<n>*4. */ | |
954 | if (op == O_multiply | |
955 | && ((right->X_op == O_register | |
956 | && right->X_md == PPC_OPERAND_CR_REG | |
957 | && left->X_op == O_constant | |
958 | && left->X_add_number == 4) | |
959 | || (left->X_op == O_register | |
960 | && left->X_md == PPC_OPERAND_CR_REG | |
961 | && right->X_op == O_constant | |
962 | && right->X_add_number == 4))) | |
963 | { | |
964 | left->X_op = O_register; | |
965 | left->X_md = PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT; | |
966 | left->X_add_number *= right->X_add_number; | |
967 | return 1; | |
968 | } | |
969 | ||
970 | /* Accept the above plus <cr bit>, and <cr bit> plus the above. */ | |
971 | if (right->X_op == O_register | |
972 | && left->X_op == O_register | |
973 | && op == O_add | |
974 | && ((right->X_md == PPC_OPERAND_CR_BIT | |
975 | && left->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT)) | |
976 | || (right->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT) | |
977 | && left->X_md == PPC_OPERAND_CR_BIT))) | |
978 | { | |
979 | left->X_md = PPC_OPERAND_CR_BIT; | |
980 | right->X_op = O_constant; | |
981 | return 0; | |
982 | } | |
983 | ||
984 | /* Accept reg +/- constant. */ | |
985 | if (left->X_op == O_register | |
986 | && !((op == O_add || op == O_subtract) && right->X_op == O_constant)) | |
ece5dcc1 | 987 | as_warn (_("invalid register expression")); |
7e0de605 AM |
988 | |
989 | /* Accept constant + reg. */ | |
990 | if (right->X_op == O_register) | |
991 | { | |
992 | if (op == O_add && left->X_op == O_constant) | |
993 | left->X_md = right->X_md; | |
994 | else | |
ece5dcc1 | 995 | as_warn (_("invalid register expression")); |
7e0de605 AM |
996 | } |
997 | ||
998 | return 0; | |
999 | } | |
252b5132 RH |
1000 | \f |
1001 | /* Local variables. */ | |
1002 | ||
2b3c4602 AM |
1003 | /* Whether to target xcoff64/elf64. */ |
1004 | static unsigned int ppc_obj64 = BFD_DEFAULT_TARGET_SIZE == 64; | |
7f6d05e8 | 1005 | |
252b5132 RH |
1006 | /* Opcode hash table. */ |
1007 | static struct hash_control *ppc_hash; | |
1008 | ||
1009 | /* Macro hash table. */ | |
1010 | static struct hash_control *ppc_macro_hash; | |
1011 | ||
1012 | #ifdef OBJ_ELF | |
99a814a1 | 1013 | /* What type of shared library support to use. */ |
5d6f4f16 | 1014 | static enum { SHLIB_NONE, SHLIB_PIC, SHLIB_MRELOCATABLE } shlib = SHLIB_NONE; |
252b5132 | 1015 | |
99a814a1 | 1016 | /* Flags to set in the elf header. */ |
252b5132 RH |
1017 | static flagword ppc_flags = 0; |
1018 | ||
1019 | /* Whether this is Solaris or not. */ | |
1020 | #ifdef TARGET_SOLARIS_COMMENT | |
b34976b6 | 1021 | #define SOLARIS_P TRUE |
252b5132 | 1022 | #else |
b34976b6 | 1023 | #define SOLARIS_P FALSE |
252b5132 RH |
1024 | #endif |
1025 | ||
b34976b6 | 1026 | static bfd_boolean msolaris = SOLARIS_P; |
252b5132 RH |
1027 | #endif |
1028 | ||
1029 | #ifdef OBJ_XCOFF | |
1030 | ||
1031 | /* The RS/6000 assembler uses the .csect pseudo-op to generate code | |
1032 | using a bunch of different sections. These assembler sections, | |
1033 | however, are all encompassed within the .text or .data sections of | |
1034 | the final output file. We handle this by using different | |
1035 | subsegments within these main segments. */ | |
1036 | ||
1037 | /* Next subsegment to allocate within the .text segment. */ | |
1038 | static subsegT ppc_text_subsegment = 2; | |
1039 | ||
1040 | /* Linked list of csects in the text section. */ | |
1041 | static symbolS *ppc_text_csects; | |
1042 | ||
1043 | /* Next subsegment to allocate within the .data segment. */ | |
1044 | static subsegT ppc_data_subsegment = 2; | |
1045 | ||
1046 | /* Linked list of csects in the data section. */ | |
1047 | static symbolS *ppc_data_csects; | |
1048 | ||
1049 | /* The current csect. */ | |
1050 | static symbolS *ppc_current_csect; | |
1051 | ||
1052 | /* The RS/6000 assembler uses a TOC which holds addresses of functions | |
1053 | and variables. Symbols are put in the TOC with the .tc pseudo-op. | |
1054 | A special relocation is used when accessing TOC entries. We handle | |
1055 | the TOC as a subsegment within the .data segment. We set it up if | |
1056 | we see a .toc pseudo-op, and save the csect symbol here. */ | |
1057 | static symbolS *ppc_toc_csect; | |
1058 | ||
1059 | /* The first frag in the TOC subsegment. */ | |
1060 | static fragS *ppc_toc_frag; | |
1061 | ||
1062 | /* The first frag in the first subsegment after the TOC in the .data | |
1063 | segment. NULL if there are no subsegments after the TOC. */ | |
1064 | static fragS *ppc_after_toc_frag; | |
1065 | ||
1066 | /* The current static block. */ | |
1067 | static symbolS *ppc_current_block; | |
1068 | ||
1069 | /* The COFF debugging section; set by md_begin. This is not the | |
1070 | .debug section, but is instead the secret BFD section which will | |
1071 | cause BFD to set the section number of a symbol to N_DEBUG. */ | |
1072 | static asection *ppc_coff_debug_section; | |
1073 | ||
85645aed TG |
1074 | /* Structure to set the length field of the dwarf sections. */ |
1075 | struct dw_subsection { | |
1076 | /* Subsections are simply linked. */ | |
1077 | struct dw_subsection *link; | |
1078 | ||
1079 | /* The subsection number. */ | |
1080 | subsegT subseg; | |
1081 | ||
1082 | /* Expression to compute the length of the section. */ | |
1083 | expressionS end_exp; | |
1084 | }; | |
1085 | ||
1086 | static struct dw_section { | |
1087 | /* Corresponding section. */ | |
1088 | segT sect; | |
1089 | ||
1090 | /* Simply linked list of subsections with a label. */ | |
1091 | struct dw_subsection *list_subseg; | |
1092 | ||
1093 | /* The anonymous subsection. */ | |
1094 | struct dw_subsection *anon_subseg; | |
1095 | } dw_sections[XCOFF_DWSECT_NBR_NAMES]; | |
252b5132 RH |
1096 | #endif /* OBJ_XCOFF */ |
1097 | ||
1098 | #ifdef TE_PE | |
1099 | ||
1100 | /* Various sections that we need for PE coff support. */ | |
1101 | static segT ydata_section; | |
1102 | static segT pdata_section; | |
1103 | static segT reldata_section; | |
1104 | static segT rdata_section; | |
1105 | static segT tocdata_section; | |
1106 | ||
81d4177b | 1107 | /* The current section and the previous section. See ppc_previous. */ |
252b5132 RH |
1108 | static segT ppc_previous_section; |
1109 | static segT ppc_current_section; | |
1110 | ||
1111 | #endif /* TE_PE */ | |
1112 | ||
1113 | #ifdef OBJ_ELF | |
1114 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */ | |
6a0c61b7 EZ |
1115 | unsigned long *ppc_apuinfo_list; |
1116 | unsigned int ppc_apuinfo_num; | |
1117 | unsigned int ppc_apuinfo_num_alloc; | |
252b5132 RH |
1118 | #endif /* OBJ_ELF */ |
1119 | \f | |
1120 | #ifdef OBJ_ELF | |
15c1449b | 1121 | const char *const md_shortopts = "b:l:usm:K:VQ:"; |
252b5132 | 1122 | #else |
15c1449b | 1123 | const char *const md_shortopts = "um:"; |
252b5132 | 1124 | #endif |
cef4f754 | 1125 | #define OPTION_NOPS (OPTION_MD_BASE + 0) |
15c1449b | 1126 | const struct option md_longopts[] = { |
cef4f754 | 1127 | {"nops", required_argument, NULL, OPTION_NOPS}, |
bf7279d5 AM |
1128 | {"ppc476-workaround", no_argument, &warn_476, 1}, |
1129 | {"no-ppc476-workaround", no_argument, &warn_476, 0}, | |
252b5132 RH |
1130 | {NULL, no_argument, NULL, 0} |
1131 | }; | |
15c1449b | 1132 | const size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
1133 | |
1134 | int | |
17b9d67d | 1135 | md_parse_option (int c, const char *arg) |
252b5132 | 1136 | { |
69fe9ce5 AM |
1137 | ppc_cpu_t new_cpu; |
1138 | ||
252b5132 RH |
1139 | switch (c) |
1140 | { | |
1141 | case 'u': | |
1142 | /* -u means that any undefined symbols should be treated as | |
1143 | external, which is the default for gas anyhow. */ | |
1144 | break; | |
1145 | ||
1146 | #ifdef OBJ_ELF | |
1147 | case 'l': | |
1148 | /* Solaris as takes -le (presumably for little endian). For completeness | |
99a814a1 | 1149 | sake, recognize -be also. */ |
252b5132 RH |
1150 | if (strcmp (arg, "e") == 0) |
1151 | { | |
1152 | target_big_endian = 0; | |
1153 | set_target_endian = 1; | |
b9c361e0 | 1154 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1155 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1156 | } |
1157 | else | |
1158 | return 0; | |
1159 | ||
1160 | break; | |
1161 | ||
1162 | case 'b': | |
1163 | if (strcmp (arg, "e") == 0) | |
1164 | { | |
1165 | target_big_endian = 1; | |
1166 | set_target_endian = 1; | |
1167 | } | |
1168 | else | |
1169 | return 0; | |
1170 | ||
1171 | break; | |
1172 | ||
1173 | case 'K': | |
99a814a1 | 1174 | /* Recognize -K PIC. */ |
252b5132 RH |
1175 | if (strcmp (arg, "PIC") == 0 || strcmp (arg, "pic") == 0) |
1176 | { | |
1177 | shlib = SHLIB_PIC; | |
1178 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; | |
1179 | } | |
1180 | else | |
1181 | return 0; | |
1182 | ||
1183 | break; | |
1184 | #endif | |
1185 | ||
7f6d05e8 CP |
1186 | /* a64 and a32 determine whether to use XCOFF64 or XCOFF32. */ |
1187 | case 'a': | |
1188 | if (strcmp (arg, "64") == 0) | |
2a98c3a6 AM |
1189 | { |
1190 | #ifdef BFD64 | |
1191 | ppc_obj64 = 1; | |
d6ed37ed AM |
1192 | if (ppc_cpu & PPC_OPCODE_VLE) |
1193 | as_bad (_("the use of -mvle requires -a32.")); | |
2a98c3a6 AM |
1194 | #else |
1195 | as_fatal (_("%s unsupported"), "-a64"); | |
1196 | #endif | |
1197 | } | |
7f6d05e8 | 1198 | else if (strcmp (arg, "32") == 0) |
2b3c4602 | 1199 | ppc_obj64 = 0; |
7f6d05e8 CP |
1200 | else |
1201 | return 0; | |
1202 | break; | |
81d4177b | 1203 | |
252b5132 | 1204 | case 'm': |
776fc418 | 1205 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, arg); |
52be03fd AM |
1206 | /* "raw" is only valid for the disassembler. */ |
1207 | if (new_cpu != 0 && (new_cpu & PPC_OPCODE_RAW) == 0) | |
b9c361e0 JL |
1208 | { |
1209 | ppc_cpu = new_cpu; | |
d6ed37ed AM |
1210 | if (strcmp (arg, "vle") == 0) |
1211 | { | |
1212 | if (set_target_endian && target_big_endian == 0) | |
1213 | as_bad (_("the use of -mvle requires big endian.")); | |
1214 | if (ppc_obj64) | |
1215 | as_bad (_("the use of -mvle requires -a32.")); | |
1216 | } | |
b9c361e0 | 1217 | } |
252b5132 | 1218 | |
83eef883 AFB |
1219 | else if (strcmp (arg, "no-vle") == 0) |
1220 | { | |
1221 | sticky &= ~PPC_OPCODE_VLE; | |
1222 | ||
1223 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, "booke"); | |
1224 | new_cpu &= ~PPC_OPCODE_VLE; | |
1225 | ||
1226 | ppc_cpu = new_cpu; | |
1227 | } | |
1228 | ||
252b5132 | 1229 | else if (strcmp (arg, "regnames") == 0) |
b34976b6 | 1230 | reg_names_p = TRUE; |
252b5132 RH |
1231 | |
1232 | else if (strcmp (arg, "no-regnames") == 0) | |
b34976b6 | 1233 | reg_names_p = FALSE; |
252b5132 RH |
1234 | |
1235 | #ifdef OBJ_ELF | |
99a814a1 AM |
1236 | /* -mrelocatable/-mrelocatable-lib -- warn about initializations |
1237 | that require relocation. */ | |
252b5132 RH |
1238 | else if (strcmp (arg, "relocatable") == 0) |
1239 | { | |
5d6f4f16 | 1240 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1241 | ppc_flags |= EF_PPC_RELOCATABLE; |
1242 | } | |
1243 | ||
1244 | else if (strcmp (arg, "relocatable-lib") == 0) | |
1245 | { | |
5d6f4f16 | 1246 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1247 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; |
1248 | } | |
1249 | ||
99a814a1 | 1250 | /* -memb, set embedded bit. */ |
252b5132 RH |
1251 | else if (strcmp (arg, "emb") == 0) |
1252 | ppc_flags |= EF_PPC_EMB; | |
1253 | ||
cc643b88 | 1254 | /* -mlittle/-mbig set the endianness. */ |
99a814a1 AM |
1255 | else if (strcmp (arg, "little") == 0 |
1256 | || strcmp (arg, "little-endian") == 0) | |
252b5132 RH |
1257 | { |
1258 | target_big_endian = 0; | |
1259 | set_target_endian = 1; | |
b9c361e0 | 1260 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1261 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1262 | } |
1263 | ||
1264 | else if (strcmp (arg, "big") == 0 || strcmp (arg, "big-endian") == 0) | |
1265 | { | |
1266 | target_big_endian = 1; | |
1267 | set_target_endian = 1; | |
1268 | } | |
1269 | ||
1270 | else if (strcmp (arg, "solaris") == 0) | |
1271 | { | |
b34976b6 | 1272 | msolaris = TRUE; |
252b5132 RH |
1273 | ppc_comment_chars = ppc_solaris_comment_chars; |
1274 | } | |
1275 | ||
1276 | else if (strcmp (arg, "no-solaris") == 0) | |
1277 | { | |
b34976b6 | 1278 | msolaris = FALSE; |
252b5132 RH |
1279 | ppc_comment_chars = ppc_eabi_comment_chars; |
1280 | } | |
74081948 AF |
1281 | else if (strcmp (arg, "spe2") == 0) |
1282 | { | |
1283 | ppc_cpu |= PPC_OPCODE_SPE2; | |
1284 | } | |
252b5132 RH |
1285 | #endif |
1286 | else | |
1287 | { | |
1288 | as_bad (_("invalid switch -m%s"), arg); | |
1289 | return 0; | |
1290 | } | |
1291 | break; | |
1292 | ||
1293 | #ifdef OBJ_ELF | |
1294 | /* -V: SVR4 argument to print version ID. */ | |
1295 | case 'V': | |
1296 | print_version_id (); | |
1297 | break; | |
1298 | ||
1299 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
1300 | should be emitted or not. FIXME: Not implemented. */ | |
1301 | case 'Q': | |
1302 | break; | |
1303 | ||
1304 | /* Solaris takes -s to specify that .stabs go in a .stabs section, | |
1305 | rather than .stabs.excl, which is ignored by the linker. | |
1306 | FIXME: Not implemented. */ | |
1307 | case 's': | |
1308 | if (arg) | |
1309 | return 0; | |
1310 | ||
1311 | break; | |
1312 | #endif | |
1313 | ||
cef4f754 AM |
1314 | case OPTION_NOPS: |
1315 | { | |
1316 | char *end; | |
1317 | nop_limit = strtoul (optarg, &end, 0); | |
1318 | if (*end) | |
1319 | as_bad (_("--nops needs a numeric argument")); | |
1320 | } | |
1321 | break; | |
85645aed | 1322 | |
bf7279d5 AM |
1323 | case 0: |
1324 | break; | |
1325 | ||
252b5132 RH |
1326 | default: |
1327 | return 0; | |
1328 | } | |
1329 | ||
1330 | return 1; | |
1331 | } | |
1332 | ||
5f63875b AM |
1333 | static int |
1334 | is_ppc64_target (const bfd_target *targ, void *data ATTRIBUTE_UNUSED) | |
1335 | { | |
1336 | switch (targ->flavour) | |
1337 | { | |
1338 | #ifdef OBJ_ELF | |
1339 | case bfd_target_elf_flavour: | |
1340 | return strncmp (targ->name, "elf64-powerpc", 13) == 0; | |
1341 | #endif | |
1342 | #ifdef OBJ_XCOFF | |
1343 | case bfd_target_xcoff_flavour: | |
1344 | return (strcmp (targ->name, "aixcoff64-rs6000") == 0 | |
1345 | || strcmp (targ->name, "aix5coff64-rs6000") == 0); | |
1346 | #endif | |
1347 | default: | |
1348 | return 0; | |
1349 | } | |
1350 | } | |
1351 | ||
252b5132 | 1352 | void |
98027b10 | 1353 | md_show_usage (FILE *stream) |
252b5132 | 1354 | { |
bc805888 | 1355 | fprintf (stream, _("\ |
5f63875b AM |
1356 | PowerPC options:\n")); |
1357 | fprintf (stream, _("\ | |
1358 | -a32 generate ELF32/XCOFF32\n")); | |
1359 | if (bfd_iterate_over_targets (is_ppc64_target, NULL)) | |
1360 | fprintf (stream, _("\ | |
1361 | -a64 generate ELF64/XCOFF64\n")); | |
1362 | fprintf (stream, _("\ | |
1363 | -u ignored\n")); | |
1364 | fprintf (stream, _("\ | |
1365 | -mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n")); | |
1366 | fprintf (stream, _("\ | |
1367 | -mpwr generate code for POWER (RIOS1)\n")); | |
1368 | fprintf (stream, _("\ | |
1369 | -m601 generate code for PowerPC 601\n")); | |
1370 | fprintf (stream, _("\ | |
418c1742 | 1371 | -mppc, -mppc32, -m603, -m604\n\ |
5f63875b AM |
1372 | generate code for PowerPC 603/604\n")); |
1373 | fprintf (stream, _("\ | |
1374 | -m403 generate code for PowerPC 403\n")); | |
1375 | fprintf (stream, _("\ | |
1376 | -m405 generate code for PowerPC 405\n")); | |
1377 | fprintf (stream, _("\ | |
1378 | -m440 generate code for PowerPC 440\n")); | |
1379 | fprintf (stream, _("\ | |
1380 | -m464 generate code for PowerPC 464\n")); | |
1381 | fprintf (stream, _("\ | |
1382 | -m476 generate code for PowerPC 476\n")); | |
1383 | fprintf (stream, _("\ | |
f5c120c5 | 1384 | -m7400, -m7410, -m7450, -m7455\n\ |
5f63875b AM |
1385 | generate code for PowerPC 7400/7410/7450/7455\n")); |
1386 | fprintf (stream, _("\ | |
fa758a70 | 1387 | -m750cl, -mgekko, -mbroadway\n\ |
5f63875b AM |
1388 | generate code for PowerPC 750cl/Gekko/Broadway\n")); |
1389 | fprintf (stream, _("\ | |
ef5a96d5 | 1390 | -m821, -m850, -m860 generate code for PowerPC 821/850/860\n")); |
df12615d | 1391 | fprintf (stream, _("\ |
5f63875b AM |
1392 | -mppc64, -m620 generate code for PowerPC 620/625/630\n")); |
1393 | fprintf (stream, _("\ | |
1394 | -mppc64bridge generate code for PowerPC 64, including bridge insns\n")); | |
1395 | fprintf (stream, _("\ | |
1396 | -mbooke generate code for 32-bit PowerPC BookE\n")); | |
1397 | fprintf (stream, _("\ | |
1398 | -ma2 generate code for A2 architecture\n")); | |
1399 | fprintf (stream, _("\ | |
1400 | -mpower4, -mpwr4 generate code for Power4 architecture\n")); | |
1401 | fprintf (stream, _("\ | |
cdc51b07 | 1402 | -mpower5, -mpwr5, -mpwr5x\n\ |
5f63875b AM |
1403 | generate code for Power5 architecture\n")); |
1404 | fprintf (stream, _("\ | |
1405 | -mpower6, -mpwr6 generate code for Power6 architecture\n")); | |
1406 | fprintf (stream, _("\ | |
1407 | -mpower7, -mpwr7 generate code for Power7 architecture\n")); | |
1408 | fprintf (stream, _("\ | |
1409 | -mpower8, -mpwr8 generate code for Power8 architecture\n")); | |
1410 | fprintf (stream, _("\ | |
1411 | -mpower9, -mpwr9 generate code for Power9 architecture\n")); | |
1412 | fprintf (stream, _("\ | |
1424c35d AM |
1413 | -mpower10, -mpwr10 generate code for Power10 architecture\n")); |
1414 | fprintf (stream, _("\ | |
5f63875b AM |
1415 | -mcell generate code for Cell Broadband Engine architecture\n")); |
1416 | fprintf (stream, _("\ | |
1417 | -mcom generate code for Power/PowerPC common instructions\n")); | |
1418 | fprintf (stream, _("\ | |
ce3d2015 | 1419 | -many generate code for any architecture (PWR/PWRX/PPC)\n")); |
6a0c61b7 | 1420 | fprintf (stream, _("\ |
5f63875b AM |
1421 | -maltivec generate code for AltiVec\n")); |
1422 | fprintf (stream, _("\ | |
1423 | -mvsx generate code for Vector-Scalar (VSX) instructions\n")); | |
1424 | fprintf (stream, _("\ | |
1425 | -me300 generate code for PowerPC e300 family\n")); | |
1426 | fprintf (stream, _("\ | |
1427 | -me500, -me500x2 generate code for Motorola e500 core complex\n")); | |
1428 | fprintf (stream, _("\ | |
1429 | -me500mc, generate code for Freescale e500mc core complex\n")); | |
1430 | fprintf (stream, _("\ | |
1431 | -me500mc64, generate code for Freescale e500mc64 core complex\n")); | |
1432 | fprintf (stream, _("\ | |
1433 | -me5500, generate code for Freescale e5500 core complex\n")); | |
1434 | fprintf (stream, _("\ | |
1435 | -me6500, generate code for Freescale e6500 core complex\n")); | |
1436 | fprintf (stream, _("\ | |
1437 | -mspe generate code for Motorola SPE instructions\n")); | |
1438 | fprintf (stream, _("\ | |
1439 | -mspe2 generate code for Freescale SPE2 instructions\n")); | |
1440 | fprintf (stream, _("\ | |
1441 | -mvle generate code for Freescale VLE instructions\n")); | |
1442 | fprintf (stream, _("\ | |
1443 | -mtitan generate code for AppliedMicro Titan core complex\n")); | |
1444 | fprintf (stream, _("\ | |
1445 | -mregnames Allow symbolic names for registers\n")); | |
1446 | fprintf (stream, _("\ | |
ce3d2015 | 1447 | -mno-regnames Do not allow symbolic names for registers\n")); |
252b5132 | 1448 | #ifdef OBJ_ELF |
bc805888 | 1449 | fprintf (stream, _("\ |
5f63875b AM |
1450 | -mrelocatable support for GCC's -mrelocatble option\n")); |
1451 | fprintf (stream, _("\ | |
1452 | -mrelocatable-lib support for GCC's -mrelocatble-lib option\n")); | |
1453 | fprintf (stream, _("\ | |
1454 | -memb set PPC_EMB bit in ELF flags\n")); | |
1455 | fprintf (stream, _("\ | |
b8b738ac | 1456 | -mlittle, -mlittle-endian, -le\n\ |
5f63875b AM |
1457 | generate code for a little endian machine\n")); |
1458 | fprintf (stream, _("\ | |
b8b738ac | 1459 | -mbig, -mbig-endian, -be\n\ |
5f63875b AM |
1460 | generate code for a big endian machine\n")); |
1461 | fprintf (stream, _("\ | |
1462 | -msolaris generate code for Solaris\n")); | |
1463 | fprintf (stream, _("\ | |
1464 | -mno-solaris do not generate code for Solaris\n")); | |
1465 | fprintf (stream, _("\ | |
1466 | -K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n")); | |
1467 | fprintf (stream, _("\ | |
1468 | -V print assembler version number\n")); | |
1469 | fprintf (stream, _("\ | |
ce3d2015 | 1470 | -Qy, -Qn ignored\n")); |
252b5132 | 1471 | #endif |
cef4f754 | 1472 | fprintf (stream, _("\ |
5f63875b AM |
1473 | -nops=count when aligning, more than COUNT nops uses a branch\n")); |
1474 | fprintf (stream, _("\ | |
bf7279d5 | 1475 | -ppc476-workaround warn if emitting data to code sections\n")); |
252b5132 RH |
1476 | } |
1477 | \f | |
1478 | /* Set ppc_cpu if it is not already set. */ | |
1479 | ||
1480 | static void | |
98027b10 | 1481 | ppc_set_cpu (void) |
252b5132 RH |
1482 | { |
1483 | const char *default_os = TARGET_OS; | |
1484 | const char *default_cpu = TARGET_CPU; | |
1485 | ||
7102e95e | 1486 | if ((ppc_cpu & ~(ppc_cpu_t) PPC_OPCODE_ANY) == 0) |
252b5132 | 1487 | { |
2a98c3a6 | 1488 | if (ppc_obj64) |
f2ab4b42 PB |
1489 | if (target_big_endian) |
1490 | ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64; | |
1491 | else | |
1492 | /* The minimum supported cpu for 64-bit little-endian is power8. */ | |
1493 | ppc_cpu |= ppc_parse_cpu (ppc_cpu, &sticky, "power8"); | |
2a98c3a6 AM |
1494 | else if (strncmp (default_os, "aix", 3) == 0 |
1495 | && default_os[3] >= '4' && default_os[3] <= '9') | |
bdc70b4a | 1496 | ppc_cpu |= PPC_OPCODE_COMMON; |
252b5132 | 1497 | else if (strncmp (default_os, "aix3", 4) == 0) |
bdc70b4a | 1498 | ppc_cpu |= PPC_OPCODE_POWER; |
252b5132 | 1499 | else if (strcmp (default_cpu, "rs6000") == 0) |
bdc70b4a | 1500 | ppc_cpu |= PPC_OPCODE_POWER; |
0baf16f2 | 1501 | else if (strncmp (default_cpu, "powerpc", 7) == 0) |
bdc70b4a | 1502 | ppc_cpu |= PPC_OPCODE_PPC; |
252b5132 | 1503 | else |
d6ed37ed | 1504 | as_fatal (_("unknown default cpu = %s, os = %s"), |
99a814a1 | 1505 | default_cpu, default_os); |
252b5132 RH |
1506 | } |
1507 | } | |
1508 | ||
9232bbb0 AM |
1509 | /* Figure out the BFD architecture to use. This function and ppc_mach |
1510 | are called well before md_begin, when the output file is opened. */ | |
252b5132 RH |
1511 | |
1512 | enum bfd_architecture | |
98027b10 | 1513 | ppc_arch (void) |
252b5132 RH |
1514 | { |
1515 | const char *default_cpu = TARGET_CPU; | |
1516 | ppc_set_cpu (); | |
1517 | ||
1518 | if ((ppc_cpu & PPC_OPCODE_PPC) != 0) | |
1519 | return bfd_arch_powerpc; | |
b9c361e0 JL |
1520 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
1521 | return bfd_arch_powerpc; | |
1522 | if ((ppc_cpu & PPC_OPCODE_POWER) != 0) | |
252b5132 | 1523 | return bfd_arch_rs6000; |
b9c361e0 | 1524 | if ((ppc_cpu & (PPC_OPCODE_COMMON | PPC_OPCODE_ANY)) != 0) |
252b5132 RH |
1525 | { |
1526 | if (strcmp (default_cpu, "rs6000") == 0) | |
1527 | return bfd_arch_rs6000; | |
0baf16f2 | 1528 | else if (strncmp (default_cpu, "powerpc", 7) == 0) |
252b5132 RH |
1529 | return bfd_arch_powerpc; |
1530 | } | |
1531 | ||
d6ed37ed | 1532 | as_fatal (_("neither Power nor PowerPC opcodes were selected.")); |
252b5132 RH |
1533 | return bfd_arch_unknown; |
1534 | } | |
1535 | ||
7f6d05e8 | 1536 | unsigned long |
98027b10 | 1537 | ppc_mach (void) |
7f6d05e8 | 1538 | { |
2a98c3a6 AM |
1539 | if (ppc_obj64) |
1540 | return bfd_mach_ppc64; | |
1541 | else if (ppc_arch () == bfd_arch_rs6000) | |
1542 | return bfd_mach_rs6k; | |
ce3d2015 AM |
1543 | else if (ppc_cpu & PPC_OPCODE_TITAN) |
1544 | return bfd_mach_ppc_titan; | |
b9c361e0 JL |
1545 | else if (ppc_cpu & PPC_OPCODE_VLE) |
1546 | return bfd_mach_ppc_vle; | |
2a98c3a6 AM |
1547 | else |
1548 | return bfd_mach_ppc; | |
7f6d05e8 CP |
1549 | } |
1550 | ||
e0471c16 | 1551 | extern const char* |
98027b10 | 1552 | ppc_target_format (void) |
7f6d05e8 CP |
1553 | { |
1554 | #ifdef OBJ_COFF | |
1555 | #ifdef TE_PE | |
99a814a1 | 1556 | return target_big_endian ? "pe-powerpc" : "pe-powerpcle"; |
7f6d05e8 | 1557 | #elif TE_POWERMAC |
0baf16f2 | 1558 | return "xcoff-powermac"; |
7f6d05e8 | 1559 | #else |
eb1e0e80 | 1560 | # ifdef TE_AIX5 |
edc1d652 | 1561 | return (ppc_obj64 ? "aix5coff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1562 | # else |
edc1d652 | 1563 | return (ppc_obj64 ? "aixcoff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1564 | # endif |
7f6d05e8 | 1565 | #endif |
7f6d05e8 CP |
1566 | #endif |
1567 | #ifdef OBJ_ELF | |
edc1d652 AM |
1568 | # ifdef TE_FreeBSD |
1569 | return (ppc_obj64 ? "elf64-powerpc-freebsd" : "elf32-powerpc-freebsd"); | |
1570 | # elif defined (TE_VXWORKS) | |
9d8504b1 PB |
1571 | return "elf32-powerpc-vxworks"; |
1572 | # else | |
0baf16f2 | 1573 | return (target_big_endian |
2b3c4602 AM |
1574 | ? (ppc_obj64 ? "elf64-powerpc" : "elf32-powerpc") |
1575 | : (ppc_obj64 ? "elf64-powerpcle" : "elf32-powerpcle")); | |
9d8504b1 | 1576 | # endif |
7f6d05e8 CP |
1577 | #endif |
1578 | } | |
1579 | ||
b9c361e0 JL |
1580 | /* Validate one entry in powerpc_opcodes[] or vle_opcodes[]. |
1581 | Return TRUE if there's a problem, otherwise FALSE. */ | |
1582 | ||
1583 | static bfd_boolean | |
1584 | insn_validate (const struct powerpc_opcode *op) | |
1585 | { | |
1586 | const unsigned char *o; | |
0f873fd5 | 1587 | uint64_t omask = op->mask; |
b9c361e0 JL |
1588 | |
1589 | /* The mask had better not trim off opcode bits. */ | |
1590 | if ((op->opcode & omask) != op->opcode) | |
1591 | { | |
1592 | as_bad (_("mask trims opcode bits for %s"), op->name); | |
1593 | return TRUE; | |
1594 | } | |
1595 | ||
1596 | /* The operands must not overlap the opcode or each other. */ | |
1597 | for (o = op->operands; *o; ++o) | |
1598 | { | |
2eac3da1 | 1599 | bfd_boolean optional = FALSE; |
b9c361e0 JL |
1600 | if (*o >= num_powerpc_operands) |
1601 | { | |
1602 | as_bad (_("operand index error for %s"), op->name); | |
1603 | return TRUE; | |
1604 | } | |
1605 | else | |
1606 | { | |
71553718 | 1607 | uint64_t mask; |
b9c361e0 | 1608 | const struct powerpc_operand *operand = &powerpc_operands[*o]; |
71553718 | 1609 | if (operand->shift == (int) PPC_OPSHIFT_INV) |
b9c361e0 | 1610 | { |
71553718 AM |
1611 | const char *errmsg; |
1612 | int64_t val; | |
1613 | ||
1614 | errmsg = NULL; | |
1615 | val = -1; | |
1616 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
1617 | val = -val; | |
1618 | else if ((operand->flags & PPC_OPERAND_PLUS1) != 0) | |
1619 | val += 1; | |
1620 | mask = (*operand->insert) (0, val, ppc_cpu, &errmsg); | |
b9c361e0 | 1621 | } |
71553718 AM |
1622 | else if (operand->shift >= 0) |
1623 | mask = operand->bitm << operand->shift; | |
1624 | else | |
1625 | mask = operand->bitm >> -operand->shift; | |
1626 | if (omask & mask) | |
1627 | { | |
1628 | as_bad (_("operand %d overlap in %s"), | |
1629 | (int) (o - op->operands), op->name); | |
1630 | return TRUE; | |
1631 | } | |
1632 | omask |= mask; | |
2eac3da1 AM |
1633 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) |
1634 | optional = TRUE; | |
1635 | else if (optional) | |
1636 | { | |
1637 | as_bad (_("non-optional operand %d follows optional operand in %s"), | |
1638 | (int) (o - op->operands), op->name); | |
1639 | return TRUE; | |
1640 | } | |
b9c361e0 JL |
1641 | } |
1642 | } | |
1643 | return FALSE; | |
1644 | } | |
1645 | ||
69c040df | 1646 | /* Insert opcodes and macros into hash tables. Called at startup and |
1fe532cf | 1647 | for .machine pseudo. */ |
252b5132 | 1648 | |
69c040df AM |
1649 | static void |
1650 | ppc_setup_opcodes (void) | |
252b5132 | 1651 | { |
98027b10 | 1652 | const struct powerpc_opcode *op; |
252b5132 RH |
1653 | const struct powerpc_opcode *op_end; |
1654 | const struct powerpc_macro *macro; | |
1655 | const struct powerpc_macro *macro_end; | |
b84bf58a | 1656 | bfd_boolean bad_insn = FALSE; |
252b5132 | 1657 | |
69c040df AM |
1658 | if (ppc_hash != NULL) |
1659 | hash_die (ppc_hash); | |
1660 | if (ppc_macro_hash != NULL) | |
1661 | hash_die (ppc_macro_hash); | |
252b5132 RH |
1662 | |
1663 | /* Insert the opcodes into a hash table. */ | |
1664 | ppc_hash = hash_new (); | |
1665 | ||
c43a438d | 1666 | if (ENABLE_CHECKING) |
b84bf58a | 1667 | { |
c43a438d | 1668 | unsigned int i; |
b84bf58a | 1669 | |
3b8b57a9 AM |
1670 | /* An index into powerpc_operands is stored in struct fix |
1671 | fx_pcrel_adjust which is 8 bits wide. */ | |
1672 | gas_assert (num_powerpc_operands < 256); | |
1673 | ||
c43a438d AM |
1674 | /* Check operand masks. Code here and in the disassembler assumes |
1675 | all the 1's in the mask are contiguous. */ | |
1676 | for (i = 0; i < num_powerpc_operands; ++i) | |
b84bf58a | 1677 | { |
0f873fd5 PB |
1678 | uint64_t mask = powerpc_operands[i].bitm; |
1679 | uint64_t right_bit; | |
c43a438d AM |
1680 | unsigned int j; |
1681 | ||
1682 | right_bit = mask & -mask; | |
1683 | mask += right_bit; | |
1684 | right_bit = mask & -mask; | |
1685 | if (mask != right_bit) | |
1686 | { | |
1687 | as_bad (_("powerpc_operands[%d].bitm invalid"), i); | |
1688 | bad_insn = TRUE; | |
1689 | } | |
1690 | for (j = i + 1; j < num_powerpc_operands; ++j) | |
1691 | if (memcmp (&powerpc_operands[i], &powerpc_operands[j], | |
1692 | sizeof (powerpc_operands[0])) == 0) | |
1693 | { | |
1694 | as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"), | |
1695 | j, i); | |
1696 | bad_insn = TRUE; | |
1697 | } | |
b84bf58a AM |
1698 | } |
1699 | } | |
1700 | ||
252b5132 RH |
1701 | op_end = powerpc_opcodes + powerpc_num_opcodes; |
1702 | for (op = powerpc_opcodes; op < op_end; op++) | |
1703 | { | |
c43a438d | 1704 | if (ENABLE_CHECKING) |
b84bf58a | 1705 | { |
2ceb7719 | 1706 | unsigned int new_opcode = PPC_OP (op[0].opcode); |
b9c361e0 JL |
1707 | |
1708 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1709 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1710 | op->name, (unsigned int) (op - powerpc_opcodes), | |
1711 | new_opcode, (unsigned long long) op->opcode, | |
1712 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 JL |
1713 | #endif |
1714 | ||
2ceb7719 PB |
1715 | /* The major opcodes had better be sorted. Code in the disassembler |
1716 | assumes the insns are sorted according to major opcode. */ | |
1717 | if (op != powerpc_opcodes | |
1718 | && new_opcode < PPC_OP (op[-1].opcode)) | |
1719 | { | |
1720 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1721 | bad_insn = TRUE; | |
8dbcd839 | 1722 | } |
2ceb7719 | 1723 | |
14b57c7c AM |
1724 | if ((op->flags & PPC_OPCODE_VLE) != 0) |
1725 | { | |
1726 | as_bad (_("%s is enabled by vle flag"), op->name); | |
1727 | bad_insn = TRUE; | |
1728 | } | |
1729 | if (PPC_OP (op->opcode) != 4 | |
1730 | && PPC_OP (op->opcode) != 31 | |
1731 | && (op->deprecated & PPC_OPCODE_VLE) == 0) | |
1732 | { | |
1733 | as_bad (_("%s not disabled by vle flag"), op->name); | |
1734 | bad_insn = TRUE; | |
1735 | } | |
b9c361e0 JL |
1736 | bad_insn |= insn_validate (op); |
1737 | } | |
c43a438d | 1738 | |
b9c361e0 JL |
1739 | if ((ppc_cpu & op->flags) != 0 |
1740 | && !(ppc_cpu & op->deprecated)) | |
1741 | { | |
1742 | const char *retval; | |
1743 | ||
1744 | retval = hash_insert (ppc_hash, op->name, (void *) op); | |
1745 | if (retval != NULL) | |
c43a438d | 1746 | { |
b9c361e0 | 1747 | as_bad (_("duplicate instruction %s"), |
c43a438d AM |
1748 | op->name); |
1749 | bad_insn = TRUE; | |
1750 | } | |
b9c361e0 JL |
1751 | } |
1752 | } | |
c43a438d | 1753 | |
b9c361e0 JL |
1754 | if ((ppc_cpu & PPC_OPCODE_ANY) != 0) |
1755 | for (op = powerpc_opcodes; op < op_end; op++) | |
1756 | hash_insert (ppc_hash, op->name, (void *) op); | |
1757 | ||
dd7efa79 PB |
1758 | op_end = prefix_opcodes + prefix_num_opcodes; |
1759 | for (op = prefix_opcodes; op < op_end; op++) | |
1760 | { | |
1761 | if (ENABLE_CHECKING) | |
1762 | { | |
1763 | unsigned int new_opcode = PPC_PREFIX_SEG (op[0].opcode); | |
1764 | ||
1765 | #ifdef PRINT_OPCODE_TABLE | |
1766 | printf ("%-14s\t#%04u\tmajor op/2: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", | |
1767 | op->name, (unsigned int) (op - prefix_opcodes), | |
1768 | new_opcode, (unsigned long long) op->opcode, | |
1769 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
1770 | #endif | |
1771 | ||
1772 | /* The major opcodes had better be sorted. Code in the disassembler | |
1773 | assumes the insns are sorted according to major opcode. */ | |
1774 | if (op != prefix_opcodes | |
1775 | && new_opcode < PPC_PREFIX_SEG (op[-1].opcode)) | |
1776 | { | |
1777 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1778 | bad_insn = TRUE; | |
1779 | } | |
1780 | bad_insn |= insn_validate (op); | |
1781 | } | |
1782 | ||
1783 | if ((ppc_cpu & op->flags) != 0 | |
1784 | && !(ppc_cpu & op->deprecated)) | |
1785 | { | |
1786 | const char *retval; | |
1787 | ||
1788 | retval = hash_insert (ppc_hash, op->name, (void *) op); | |
1789 | if (retval != NULL) | |
1790 | { | |
1791 | as_bad (_("duplicate instruction %s"), | |
1792 | op->name); | |
1793 | bad_insn = TRUE; | |
1794 | } | |
1795 | } | |
1796 | } | |
1797 | ||
1798 | if ((ppc_cpu & PPC_OPCODE_ANY) != 0) | |
1799 | for (op = prefix_opcodes; op < op_end; op++) | |
1800 | hash_insert (ppc_hash, op->name, (void *) op); | |
1801 | ||
b9c361e0 JL |
1802 | op_end = vle_opcodes + vle_num_opcodes; |
1803 | for (op = vle_opcodes; op < op_end; op++) | |
1804 | { | |
1805 | if (ENABLE_CHECKING) | |
1806 | { | |
2ceb7719 | 1807 | unsigned new_seg = VLE_OP_TO_SEG (VLE_OP (op[0].opcode, op[0].mask)); |
b9c361e0 JL |
1808 | |
1809 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1810 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1811 | op->name, (unsigned int) (op - vle_opcodes), | |
1812 | (unsigned int) new_seg, (unsigned long long) op->opcode, | |
1813 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 | 1814 | #endif |
2ceb7719 PB |
1815 | |
1816 | /* The major opcodes had better be sorted. Code in the disassembler | |
1817 | assumes the insns are sorted according to major opcode. */ | |
1818 | if (op != vle_opcodes | |
1819 | && new_seg < VLE_OP_TO_SEG (VLE_OP (op[-1].opcode, op[-1].mask))) | |
1820 | { | |
1821 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1822 | bad_insn = TRUE; | |
b9c361e0 JL |
1823 | } |
1824 | ||
1825 | bad_insn |= insn_validate (op); | |
c43a438d | 1826 | } |
252b5132 | 1827 | |
bdc70b4a | 1828 | if ((ppc_cpu & op->flags) != 0 |
1cb0a767 | 1829 | && !(ppc_cpu & op->deprecated)) |
252b5132 RH |
1830 | { |
1831 | const char *retval; | |
1832 | ||
98027b10 | 1833 | retval = hash_insert (ppc_hash, op->name, (void *) op); |
69c040df | 1834 | if (retval != NULL) |
252b5132 | 1835 | { |
b84bf58a | 1836 | as_bad (_("duplicate instruction %s"), |
99a814a1 | 1837 | op->name); |
b84bf58a | 1838 | bad_insn = TRUE; |
252b5132 RH |
1839 | } |
1840 | } | |
1841 | } | |
1842 | ||
74081948 AF |
1843 | /* SPE2 instructions */ |
1844 | if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2) | |
1845 | { | |
1846 | op_end = spe2_opcodes + spe2_num_opcodes; | |
1847 | for (op = spe2_opcodes; op < op_end; op++) | |
1848 | { | |
1849 | if (ENABLE_CHECKING) | |
1850 | { | |
1851 | if (op != spe2_opcodes) | |
1852 | { | |
1853 | unsigned old_seg, new_seg; | |
1854 | ||
1855 | old_seg = VLE_OP (op[-1].opcode, op[-1].mask); | |
1856 | old_seg = VLE_OP_TO_SEG (old_seg); | |
1857 | new_seg = VLE_OP (op[0].opcode, op[0].mask); | |
1858 | new_seg = VLE_OP_TO_SEG (new_seg); | |
1859 | ||
1860 | /* The major opcodes had better be sorted. Code in the | |
1861 | disassembler assumes the insns are sorted according to | |
1862 | major opcode. */ | |
1863 | if (new_seg < old_seg) | |
1864 | { | |
1865 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
1866 | bad_insn = TRUE; | |
1867 | } | |
1868 | } | |
1869 | ||
1870 | bad_insn |= insn_validate (op); | |
1871 | } | |
1872 | ||
1873 | if ((ppc_cpu & op->flags) != 0 && !(ppc_cpu & op->deprecated)) | |
1874 | { | |
1875 | const char *retval; | |
1876 | ||
1877 | retval = hash_insert (ppc_hash, op->name, (void *) op); | |
1878 | if (retval != NULL) | |
1879 | { | |
1880 | as_bad (_("duplicate instruction %s"), | |
1881 | op->name); | |
1882 | bad_insn = TRUE; | |
1883 | } | |
1884 | } | |
1885 | } | |
1886 | ||
1887 | for (op = spe2_opcodes; op < op_end; op++) | |
1888 | hash_insert (ppc_hash, op->name, (void *) op); | |
1889 | } | |
1890 | ||
252b5132 RH |
1891 | /* Insert the macros into a hash table. */ |
1892 | ppc_macro_hash = hash_new (); | |
1893 | ||
1894 | macro_end = powerpc_macros + powerpc_num_macros; | |
1895 | for (macro = powerpc_macros; macro < macro_end; macro++) | |
1896 | { | |
33740db9 | 1897 | if ((macro->flags & ppc_cpu) != 0 || (ppc_cpu & PPC_OPCODE_ANY) != 0) |
252b5132 RH |
1898 | { |
1899 | const char *retval; | |
1900 | ||
98027b10 | 1901 | retval = hash_insert (ppc_macro_hash, macro->name, (void *) macro); |
252b5132 RH |
1902 | if (retval != (const char *) NULL) |
1903 | { | |
b84bf58a AM |
1904 | as_bad (_("duplicate macro %s"), macro->name); |
1905 | bad_insn = TRUE; | |
252b5132 RH |
1906 | } |
1907 | } | |
1908 | } | |
1909 | ||
b84bf58a | 1910 | if (bad_insn) |
252b5132 | 1911 | abort (); |
69c040df AM |
1912 | } |
1913 | ||
1914 | /* This function is called when the assembler starts up. It is called | |
1915 | after the options have been parsed and the output file has been | |
1916 | opened. */ | |
1917 | ||
1918 | void | |
98027b10 | 1919 | md_begin (void) |
69c040df AM |
1920 | { |
1921 | ppc_set_cpu (); | |
1922 | ||
1923 | ppc_cie_data_alignment = ppc_obj64 ? -8 : -4; | |
8fbf7334 | 1924 | ppc_dwarf2_line_min_insn_length = (ppc_cpu & PPC_OPCODE_VLE) ? 2 : 4; |
69c040df AM |
1925 | |
1926 | #ifdef OBJ_ELF | |
1927 | /* Set the ELF flags if desired. */ | |
1928 | if (ppc_flags && !msolaris) | |
1929 | bfd_set_private_flags (stdoutput, ppc_flags); | |
1930 | #endif | |
1931 | ||
1932 | ppc_setup_opcodes (); | |
252b5132 | 1933 | |
67c1ffbe | 1934 | /* Tell the main code what the endianness is if it is not overridden |
99a814a1 | 1935 | by the user. */ |
252b5132 RH |
1936 | if (!set_target_endian) |
1937 | { | |
1938 | set_target_endian = 1; | |
1939 | target_big_endian = PPC_BIG_ENDIAN; | |
1940 | } | |
1941 | ||
1942 | #ifdef OBJ_XCOFF | |
1943 | ppc_coff_debug_section = coff_section_from_bfd_index (stdoutput, N_DEBUG); | |
1944 | ||
1945 | /* Create dummy symbols to serve as initial csects. This forces the | |
1946 | text csects to precede the data csects. These symbols will not | |
1947 | be output. */ | |
1948 | ppc_text_csects = symbol_make ("dummy\001"); | |
809ffe0d | 1949 | symbol_get_tc (ppc_text_csects)->within = ppc_text_csects; |
252b5132 | 1950 | ppc_data_csects = symbol_make ("dummy\001"); |
809ffe0d | 1951 | symbol_get_tc (ppc_data_csects)->within = ppc_data_csects; |
252b5132 RH |
1952 | #endif |
1953 | ||
1954 | #ifdef TE_PE | |
1955 | ||
1956 | ppc_current_section = text_section; | |
81d4177b | 1957 | ppc_previous_section = 0; |
252b5132 RH |
1958 | |
1959 | #endif | |
1960 | } | |
1961 | ||
6a0c61b7 | 1962 | void |
98027b10 | 1963 | ppc_cleanup (void) |
6a0c61b7 | 1964 | { |
dc1d03fc | 1965 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
1966 | if (ppc_apuinfo_list == NULL) |
1967 | return; | |
1968 | ||
1969 | /* Ok, so write the section info out. We have this layout: | |
1970 | ||
1971 | byte data what | |
1972 | ---- ---- ---- | |
1973 | 0 8 length of "APUinfo\0" | |
1974 | 4 (n*4) number of APU's (4 bytes each) | |
1975 | 8 2 note type 2 | |
1976 | 12 "APUinfo\0" name | |
1977 | 20 APU#1 first APU's info | |
1978 | 24 APU#2 second APU's info | |
1979 | ... ... | |
1980 | */ | |
1981 | { | |
1982 | char *p; | |
1983 | asection *seg = now_seg; | |
1984 | subsegT subseg = now_subseg; | |
1985 | asection *apuinfo_secp = (asection *) NULL; | |
49181a6a | 1986 | unsigned int i; |
6a0c61b7 EZ |
1987 | |
1988 | /* Create the .PPC.EMB.apuinfo section. */ | |
14b57c7c | 1989 | apuinfo_secp = subseg_new (APUINFO_SECTION_NAME, 0); |
fd361982 | 1990 | bfd_set_section_flags (apuinfo_secp, SEC_HAS_CONTENTS | SEC_READONLY); |
6a0c61b7 EZ |
1991 | |
1992 | p = frag_more (4); | |
1993 | md_number_to_chars (p, (valueT) 8, 4); | |
1994 | ||
1995 | p = frag_more (4); | |
e98d298c | 1996 | md_number_to_chars (p, (valueT) ppc_apuinfo_num * 4, 4); |
6a0c61b7 EZ |
1997 | |
1998 | p = frag_more (4); | |
1999 | md_number_to_chars (p, (valueT) 2, 4); | |
2000 | ||
2001 | p = frag_more (8); | |
14b57c7c | 2002 | strcpy (p, APUINFO_LABEL); |
6a0c61b7 EZ |
2003 | |
2004 | for (i = 0; i < ppc_apuinfo_num; i++) | |
2005 | { | |
b34976b6 AM |
2006 | p = frag_more (4); |
2007 | md_number_to_chars (p, (valueT) ppc_apuinfo_list[i], 4); | |
6a0c61b7 EZ |
2008 | } |
2009 | ||
2010 | frag_align (2, 0, 0); | |
2011 | ||
2012 | /* We probably can't restore the current segment, for there likely | |
2013 | isn't one yet... */ | |
2014 | if (seg && subseg) | |
2015 | subseg_set (seg, subseg); | |
2016 | } | |
dc1d03fc | 2017 | #endif |
6a0c61b7 EZ |
2018 | } |
2019 | ||
252b5132 RH |
2020 | /* Insert an operand value into an instruction. */ |
2021 | ||
0f873fd5 PB |
2022 | static uint64_t |
2023 | ppc_insert_operand (uint64_t insn, | |
a1867a27 | 2024 | const struct powerpc_operand *operand, |
0f873fd5 | 2025 | int64_t val, |
91d6fa6a | 2026 | ppc_cpu_t cpu, |
3b4dbbbf | 2027 | const char *file, |
a1867a27 | 2028 | unsigned int line) |
252b5132 | 2029 | { |
0f873fd5 | 2030 | int64_t min, max, right; |
eb42fac1 | 2031 | |
b84bf58a AM |
2032 | max = operand->bitm; |
2033 | right = max & -max; | |
2034 | min = 0; | |
2035 | ||
a47622ac | 2036 | if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0) |
252b5132 | 2037 | { |
a255f00a AM |
2038 | /* Extend the allowed range for addis to [-32768, 65535]. |
2039 | Similarly for cmpli and some VLE high part insns. For 64-bit | |
2040 | it would be good to disable this for signed fields since the | |
a47622ac AM |
2041 | value is sign extended into the high 32 bits of the register. |
2042 | If the value is, say, an address, then we might care about | |
2043 | the high bits. However, gcc as of 2014-06 uses unsigned | |
2044 | values when loading the high part of 64-bit constants using | |
a255f00a AM |
2045 | lis. */ |
2046 | min = ~(max >> 1) & -right; | |
a47622ac AM |
2047 | } |
2048 | else if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
2049 | { | |
2050 | max = (max >> 1) & -right; | |
931774a9 | 2051 | min = ~max & -right; |
b84bf58a | 2052 | } |
252b5132 | 2053 | |
b84bf58a | 2054 | if ((operand->flags & PPC_OPERAND_PLUS1) != 0) |
3896c469 | 2055 | max++; |
252b5132 | 2056 | |
b84bf58a | 2057 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) |
a1867a27 | 2058 | { |
0f873fd5 | 2059 | int64_t tmp = min; |
a1867a27 AM |
2060 | min = -max; |
2061 | max = -tmp; | |
2062 | } | |
b84bf58a | 2063 | |
a1867a27 AM |
2064 | if (min <= max) |
2065 | { | |
2066 | /* Some people write constants with the sign extension done by | |
2067 | hand but only up to 32 bits. This shouldn't really be valid, | |
2068 | but, to permit this code to assemble on a 64-bit host, we | |
2069 | sign extend the 32-bit value to 64 bits if so doing makes the | |
8acf1435 PB |
2070 | value valid. We only do this for operands that are 32-bits or |
2071 | smaller. */ | |
a1867a27 | 2072 | if (val > max |
8acf1435 | 2073 | && (operand->bitm & ~0xffffffffULL) == 0 |
0f873fd5 PB |
2074 | && (val - (1LL << 32)) >= min |
2075 | && (val - (1LL << 32)) <= max | |
2076 | && ((val - (1LL << 32)) & (right - 1)) == 0) | |
2077 | val = val - (1LL << 32); | |
a1867a27 AM |
2078 | |
2079 | /* Similarly, people write expressions like ~(1<<15), and expect | |
2080 | this to be OK for a 32-bit unsigned value. */ | |
2081 | else if (val < min | |
8acf1435 | 2082 | && (operand->bitm & ~0xffffffffULL) == 0 |
0f873fd5 PB |
2083 | && (val + (1LL << 32)) >= min |
2084 | && (val + (1LL << 32)) <= max | |
2085 | && ((val + (1LL << 32)) & (right - 1)) == 0) | |
2086 | val = val + (1LL << 32); | |
a1867a27 AM |
2087 | |
2088 | else if (val < min | |
2089 | || val > max | |
2090 | || (val & (right - 1)) != 0) | |
2091 | as_bad_value_out_of_range (_("operand"), val, min, max, file, line); | |
2092 | } | |
b84bf58a | 2093 | |
252b5132 RH |
2094 | if (operand->insert) |
2095 | { | |
2096 | const char *errmsg; | |
2097 | ||
2098 | errmsg = NULL; | |
0f873fd5 | 2099 | insn = (*operand->insert) (insn, val, cpu, &errmsg); |
252b5132 | 2100 | if (errmsg != (const char *) NULL) |
ee2c9aa9 | 2101 | as_bad_where (file, line, "%s", errmsg); |
252b5132 | 2102 | } |
b9c361e0 | 2103 | else if (operand->shift >= 0) |
0f873fd5 | 2104 | insn |= (val & operand->bitm) << operand->shift; |
b9c361e0 | 2105 | else |
0f873fd5 | 2106 | insn |= (val & operand->bitm) >> -operand->shift; |
252b5132 RH |
2107 | |
2108 | return insn; | |
2109 | } | |
2110 | ||
2111 | \f | |
2112 | #ifdef OBJ_ELF | |
2113 | /* Parse @got, etc. and return the desired relocation. */ | |
2114 | static bfd_reloc_code_real_type | |
98027b10 | 2115 | ppc_elf_suffix (char **str_p, expressionS *exp_p) |
252b5132 RH |
2116 | { |
2117 | struct map_bfd { | |
e0471c16 | 2118 | const char *string; |
b7d7dc63 AM |
2119 | unsigned int length : 8; |
2120 | unsigned int valid32 : 1; | |
2121 | unsigned int valid64 : 1; | |
2122 | unsigned int reloc; | |
252b5132 RH |
2123 | }; |
2124 | ||
2125 | char ident[20]; | |
2126 | char *str = *str_p; | |
2127 | char *str2; | |
2128 | int ch; | |
2129 | int len; | |
15c1449b | 2130 | const struct map_bfd *ptr; |
252b5132 | 2131 | |
b7d7dc63 AM |
2132 | #define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc } |
2133 | #define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc } | |
2134 | #define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc } | |
252b5132 | 2135 | |
15c1449b | 2136 | static const struct map_bfd mapping[] = { |
b7d7dc63 AM |
2137 | MAP ("l", BFD_RELOC_LO16), |
2138 | MAP ("h", BFD_RELOC_HI16), | |
2139 | MAP ("ha", BFD_RELOC_HI16_S), | |
2140 | MAP ("brtaken", BFD_RELOC_PPC_B16_BRTAKEN), | |
2141 | MAP ("brntaken", BFD_RELOC_PPC_B16_BRNTAKEN), | |
2142 | MAP ("got", BFD_RELOC_16_GOTOFF), | |
2143 | MAP ("got@l", BFD_RELOC_LO16_GOTOFF), | |
2144 | MAP ("got@h", BFD_RELOC_HI16_GOTOFF), | |
2145 | MAP ("got@ha", BFD_RELOC_HI16_S_GOTOFF), | |
2146 | MAP ("plt@l", BFD_RELOC_LO16_PLTOFF), | |
2147 | MAP ("plt@h", BFD_RELOC_HI16_PLTOFF), | |
2148 | MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF), | |
2149 | MAP ("copy", BFD_RELOC_PPC_COPY), | |
2150 | MAP ("globdat", BFD_RELOC_PPC_GLOB_DAT), | |
2151 | MAP ("sectoff", BFD_RELOC_16_BASEREL), | |
2152 | MAP ("sectoff@l", BFD_RELOC_LO16_BASEREL), | |
2153 | MAP ("sectoff@h", BFD_RELOC_HI16_BASEREL), | |
2154 | MAP ("sectoff@ha", BFD_RELOC_HI16_S_BASEREL), | |
2155 | MAP ("tls", BFD_RELOC_PPC_TLS), | |
2156 | MAP ("dtpmod", BFD_RELOC_PPC_DTPMOD), | |
2157 | MAP ("dtprel", BFD_RELOC_PPC_DTPREL), | |
2158 | MAP ("dtprel@l", BFD_RELOC_PPC_DTPREL16_LO), | |
2159 | MAP ("dtprel@h", BFD_RELOC_PPC_DTPREL16_HI), | |
2160 | MAP ("dtprel@ha", BFD_RELOC_PPC_DTPREL16_HA), | |
2161 | MAP ("tprel", BFD_RELOC_PPC_TPREL), | |
2162 | MAP ("tprel@l", BFD_RELOC_PPC_TPREL16_LO), | |
2163 | MAP ("tprel@h", BFD_RELOC_PPC_TPREL16_HI), | |
2164 | MAP ("tprel@ha", BFD_RELOC_PPC_TPREL16_HA), | |
2165 | MAP ("got@tlsgd", BFD_RELOC_PPC_GOT_TLSGD16), | |
2166 | MAP ("got@tlsgd@l", BFD_RELOC_PPC_GOT_TLSGD16_LO), | |
2167 | MAP ("got@tlsgd@h", BFD_RELOC_PPC_GOT_TLSGD16_HI), | |
2168 | MAP ("got@tlsgd@ha", BFD_RELOC_PPC_GOT_TLSGD16_HA), | |
2169 | MAP ("got@tlsld", BFD_RELOC_PPC_GOT_TLSLD16), | |
2170 | MAP ("got@tlsld@l", BFD_RELOC_PPC_GOT_TLSLD16_LO), | |
2171 | MAP ("got@tlsld@h", BFD_RELOC_PPC_GOT_TLSLD16_HI), | |
2172 | MAP ("got@tlsld@ha", BFD_RELOC_PPC_GOT_TLSLD16_HA), | |
2173 | MAP ("got@dtprel", BFD_RELOC_PPC_GOT_DTPREL16), | |
2174 | MAP ("got@dtprel@l", BFD_RELOC_PPC_GOT_DTPREL16_LO), | |
2175 | MAP ("got@dtprel@h", BFD_RELOC_PPC_GOT_DTPREL16_HI), | |
2176 | MAP ("got@dtprel@ha", BFD_RELOC_PPC_GOT_DTPREL16_HA), | |
2177 | MAP ("got@tprel", BFD_RELOC_PPC_GOT_TPREL16), | |
2178 | MAP ("got@tprel@l", BFD_RELOC_PPC_GOT_TPREL16_LO), | |
2179 | MAP ("got@tprel@h", BFD_RELOC_PPC_GOT_TPREL16_HI), | |
2180 | MAP ("got@tprel@ha", BFD_RELOC_PPC_GOT_TPREL16_HA), | |
2181 | MAP32 ("fixup", BFD_RELOC_CTOR), | |
2182 | MAP32 ("plt", BFD_RELOC_24_PLT_PCREL), | |
2183 | MAP32 ("pltrel24", BFD_RELOC_24_PLT_PCREL), | |
2184 | MAP32 ("local24pc", BFD_RELOC_PPC_LOCAL24PC), | |
2185 | MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC), | |
2186 | MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL), | |
2187 | MAP32 ("sdarel", BFD_RELOC_GPREL16), | |
b9c361e0 JL |
2188 | MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A), |
2189 | MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A), | |
2190 | MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A), | |
b7d7dc63 AM |
2191 | MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32), |
2192 | MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16), | |
2193 | MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO), | |
2194 | MAP32 ("naddr@h", BFD_RELOC_PPC_EMB_NADDR16_HI), | |
2195 | MAP32 ("naddr@ha", BFD_RELOC_PPC_EMB_NADDR16_HA), | |
2196 | MAP32 ("sdai16", BFD_RELOC_PPC_EMB_SDAI16), | |
2197 | MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL), | |
2198 | MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16), | |
2199 | MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21), | |
b9c361e0 | 2200 | MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO), |
b7d7dc63 AM |
2201 | MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF), |
2202 | MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16), | |
2203 | MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO), | |
2204 | MAP32 ("relsect@h", BFD_RELOC_PPC_EMB_RELST_HI), | |
2205 | MAP32 ("relsect@ha", BFD_RELOC_PPC_EMB_RELST_HA), | |
2206 | MAP32 ("bitfld", BFD_RELOC_PPC_EMB_BIT_FLD), | |
2207 | MAP32 ("relsda", BFD_RELOC_PPC_EMB_RELSDA), | |
2208 | MAP32 ("xgot", BFD_RELOC_PPC_TOC16), | |
f9c6b907 AM |
2209 | MAP64 ("high", BFD_RELOC_PPC64_ADDR16_HIGH), |
2210 | MAP64 ("higha", BFD_RELOC_PPC64_ADDR16_HIGHA), | |
b7d7dc63 AM |
2211 | MAP64 ("higher", BFD_RELOC_PPC64_HIGHER), |
2212 | MAP64 ("highera", BFD_RELOC_PPC64_HIGHER_S), | |
2213 | MAP64 ("highest", BFD_RELOC_PPC64_HIGHEST), | |
2214 | MAP64 ("highesta", BFD_RELOC_PPC64_HIGHEST_S), | |
2215 | MAP64 ("tocbase", BFD_RELOC_PPC64_TOC), | |
2216 | MAP64 ("toc", BFD_RELOC_PPC_TOC16), | |
2217 | MAP64 ("toc@l", BFD_RELOC_PPC64_TOC16_LO), | |
2218 | MAP64 ("toc@h", BFD_RELOC_PPC64_TOC16_HI), | |
2219 | MAP64 ("toc@ha", BFD_RELOC_PPC64_TOC16_HA), | |
f9c6b907 AM |
2220 | MAP64 ("dtprel@high", BFD_RELOC_PPC64_DTPREL16_HIGH), |
2221 | MAP64 ("dtprel@higha", BFD_RELOC_PPC64_DTPREL16_HIGHA), | |
b7d7dc63 AM |
2222 | MAP64 ("dtprel@higher", BFD_RELOC_PPC64_DTPREL16_HIGHER), |
2223 | MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA), | |
2224 | MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST), | |
2225 | MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA), | |
45965137 | 2226 | MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL), |
f9c6b907 AM |
2227 | MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH), |
2228 | MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA), | |
b7d7dc63 AM |
2229 | MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER), |
2230 | MAP64 ("tprel@highera", BFD_RELOC_PPC64_TPREL16_HIGHERA), | |
2231 | MAP64 ("tprel@highest", BFD_RELOC_PPC64_TPREL16_HIGHEST), | |
2232 | MAP64 ("tprel@highesta", BFD_RELOC_PPC64_TPREL16_HIGHESTA), | |
05d0e962 | 2233 | MAP64 ("notoc", BFD_RELOC_PPC64_REL24_NOTOC), |
5663e321 AM |
2234 | MAP64 ("pcrel", BFD_RELOC_PPC64_PCREL34), |
2235 | MAP64 ("got@pcrel", BFD_RELOC_PPC64_GOT_PCREL34), | |
2236 | MAP64 ("plt@pcrel", BFD_RELOC_PPC64_PLT_PCREL34), | |
c213164a | 2237 | MAP64 ("tls@pcrel", BFD_RELOC_PPC64_TLS_PCREL), |
87c69f97 AM |
2238 | MAP64 ("got@tlsgd@pcrel", BFD_RELOC_PPC64_GOT_TLSGD_PCREL34), |
2239 | MAP64 ("got@tlsld@pcrel", BFD_RELOC_PPC64_GOT_TLSLD_PCREL34), | |
2240 | MAP64 ("got@tprel@pcrel", BFD_RELOC_PPC64_GOT_TPREL_PCREL34), | |
2241 | MAP64 ("got@dtprel@pcrel", BFD_RELOC_PPC64_GOT_DTPREL_PCREL34), | |
5663e321 AM |
2242 | MAP64 ("higher34", BFD_RELOC_PPC64_ADDR16_HIGHER34), |
2243 | MAP64 ("highera34", BFD_RELOC_PPC64_ADDR16_HIGHERA34), | |
2244 | MAP64 ("highest34", BFD_RELOC_PPC64_ADDR16_HIGHEST34), | |
2245 | MAP64 ("highesta34", BFD_RELOC_PPC64_ADDR16_HIGHESTA34), | |
62ebcb5c | 2246 | { (char *) 0, 0, 0, 0, BFD_RELOC_NONE } |
252b5132 RH |
2247 | }; |
2248 | ||
2249 | if (*str++ != '@') | |
62ebcb5c | 2250 | return BFD_RELOC_NONE; |
252b5132 RH |
2251 | |
2252 | for (ch = *str, str2 = ident; | |
2253 | (str2 < ident + sizeof (ident) - 1 | |
3882b010 | 2254 | && (ISALNUM (ch) || ch == '@')); |
252b5132 RH |
2255 | ch = *++str) |
2256 | { | |
3882b010 | 2257 | *str2++ = TOLOWER (ch); |
252b5132 RH |
2258 | } |
2259 | ||
2260 | *str2 = '\0'; | |
2261 | len = str2 - ident; | |
2262 | ||
2263 | ch = ident[0]; | |
2264 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
2265 | if (ch == ptr->string[0] | |
2266 | && len == ptr->length | |
b7d7dc63 AM |
2267 | && memcmp (ident, ptr->string, ptr->length) == 0 |
2268 | && (ppc_obj64 ? ptr->valid64 : ptr->valid32)) | |
252b5132 | 2269 | { |
15c1449b AM |
2270 | int reloc = ptr->reloc; |
2271 | ||
727fc41e AM |
2272 | if (!ppc_obj64 && exp_p->X_add_number != 0) |
2273 | { | |
2274 | switch (reloc) | |
2275 | { | |
2276 | case BFD_RELOC_16_GOTOFF: | |
2277 | case BFD_RELOC_LO16_GOTOFF: | |
2278 | case BFD_RELOC_HI16_GOTOFF: | |
2279 | case BFD_RELOC_HI16_S_GOTOFF: | |
e47d413a AM |
2280 | as_warn (_("symbol+offset@%s means symbol@%s+offset"), |
2281 | ptr->string, ptr->string); | |
727fc41e AM |
2282 | break; |
2283 | ||
2284 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
2285 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
2286 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
2287 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
2288 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
2289 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
2290 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
2291 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
2292 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
2293 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
2294 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
2295 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
2296 | case BFD_RELOC_PPC_GOT_TPREL16: | |
2297 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
2298 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
2299 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
e47d413a | 2300 | as_bad (_("symbol+offset@%s not supported"), ptr->string); |
727fc41e AM |
2301 | break; |
2302 | } | |
2303 | } | |
5f6db75a AM |
2304 | |
2305 | /* Now check for identifier@suffix+constant. */ | |
2306 | if (*str == '-' || *str == '+') | |
252b5132 | 2307 | { |
5f6db75a AM |
2308 | char *orig_line = input_line_pointer; |
2309 | expressionS new_exp; | |
2310 | ||
2311 | input_line_pointer = str; | |
2312 | expression (&new_exp); | |
2313 | if (new_exp.X_op == O_constant) | |
252b5132 | 2314 | { |
5f6db75a AM |
2315 | exp_p->X_add_number += new_exp.X_add_number; |
2316 | str = input_line_pointer; | |
252b5132 | 2317 | } |
5f6db75a AM |
2318 | |
2319 | if (&input_line_pointer != str_p) | |
2320 | input_line_pointer = orig_line; | |
252b5132 | 2321 | } |
252b5132 | 2322 | *str_p = str; |
0baf16f2 | 2323 | |
2b3c4602 | 2324 | if (reloc == (int) BFD_RELOC_PPC64_TOC |
9f2b53d7 AM |
2325 | && exp_p->X_op == O_symbol |
2326 | && strcmp (S_GET_NAME (exp_p->X_add_symbol), ".TOC.") == 0) | |
0baf16f2 | 2327 | { |
9f2b53d7 AM |
2328 | /* Change the symbol so that the dummy .TOC. symbol can be |
2329 | omitted from the object file. */ | |
0baf16f2 AM |
2330 | exp_p->X_add_symbol = &abs_symbol; |
2331 | } | |
2332 | ||
15c1449b | 2333 | return (bfd_reloc_code_real_type) reloc; |
252b5132 RH |
2334 | } |
2335 | ||
62ebcb5c | 2336 | return BFD_RELOC_NONE; |
252b5132 RH |
2337 | } |
2338 | ||
62ebcb5c | 2339 | /* Support @got, etc. on constants emitted via .short, .int etc. */ |
99a814a1 | 2340 | |
62ebcb5c AM |
2341 | bfd_reloc_code_real_type |
2342 | ppc_elf_parse_cons (expressionS *exp, unsigned int nbytes) | |
2343 | { | |
2344 | expression (exp); | |
2345 | if (nbytes >= 2 && *input_line_pointer == '@') | |
2346 | return ppc_elf_suffix (&input_line_pointer, exp); | |
2347 | return BFD_RELOC_NONE; | |
252b5132 RH |
2348 | } |
2349 | ||
bf7279d5 AM |
2350 | /* Warn when emitting data to code sections, unless we are emitting |
2351 | a relocation that ld --ppc476-workaround uses to recognise data | |
2352 | *and* there was an unconditional branch prior to the data. */ | |
2353 | ||
2354 | void | |
2355 | ppc_elf_cons_fix_check (expressionS *exp ATTRIBUTE_UNUSED, | |
2356 | unsigned int nbytes, fixS *fix) | |
2357 | { | |
2358 | if (warn_476 | |
2359 | && (now_seg->flags & SEC_CODE) != 0 | |
2360 | && (nbytes != 4 | |
2361 | || fix == NULL | |
2362 | || !(fix->fx_r_type == BFD_RELOC_32 | |
2363 | || fix->fx_r_type == BFD_RELOC_CTOR | |
2364 | || fix->fx_r_type == BFD_RELOC_32_PCREL) | |
2365 | || !(last_seg == now_seg && last_subseg == now_subseg) | |
2366 | || !((last_insn & (0x3f << 26)) == (18u << 26) | |
2367 | || ((last_insn & (0x3f << 26)) == (16u << 26) | |
2368 | && (last_insn & (0x14 << 21)) == (0x14 << 21)) | |
2369 | || ((last_insn & (0x3f << 26)) == (19u << 26) | |
2370 | && (last_insn & (0x3ff << 1)) == (16u << 1) | |
2371 | && (last_insn & (0x14 << 21)) == (0x14 << 21))))) | |
2372 | { | |
2373 | /* Flag that we've warned. */ | |
2374 | if (fix != NULL) | |
2375 | fix->fx_tcbit = 1; | |
2376 | ||
2377 | as_warn (_("data in executable section")); | |
2378 | } | |
2379 | } | |
2380 | ||
252b5132 RH |
2381 | /* Solaris pseduo op to change to the .rodata section. */ |
2382 | static void | |
98027b10 | 2383 | ppc_elf_rdata (int xxx) |
252b5132 RH |
2384 | { |
2385 | char *save_line = input_line_pointer; | |
2386 | static char section[] = ".rodata\n"; | |
2387 | ||
99a814a1 | 2388 | /* Just pretend this is .section .rodata */ |
252b5132 RH |
2389 | input_line_pointer = section; |
2390 | obj_elf_section (xxx); | |
2391 | ||
2392 | input_line_pointer = save_line; | |
2393 | } | |
2394 | ||
99a814a1 | 2395 | /* Pseudo op to make file scope bss items. */ |
252b5132 | 2396 | static void |
98027b10 | 2397 | ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED) |
252b5132 | 2398 | { |
98027b10 AM |
2399 | char *name; |
2400 | char c; | |
2401 | char *p; | |
252b5132 | 2402 | offsetT size; |
98027b10 | 2403 | symbolS *symbolP; |
252b5132 RH |
2404 | offsetT align; |
2405 | segT old_sec; | |
2406 | int old_subsec; | |
2407 | char *pfrag; | |
2408 | int align2; | |
2409 | ||
d02603dc | 2410 | c = get_symbol_name (&name); |
252b5132 | 2411 | |
d02603dc | 2412 | /* Just after name is now '\0'. */ |
252b5132 RH |
2413 | p = input_line_pointer; |
2414 | *p = c; | |
d02603dc | 2415 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
2416 | if (*input_line_pointer != ',') |
2417 | { | |
d6ed37ed | 2418 | as_bad (_("expected comma after symbol-name: rest of line ignored.")); |
252b5132 RH |
2419 | ignore_rest_of_line (); |
2420 | return; | |
2421 | } | |
2422 | ||
2423 | input_line_pointer++; /* skip ',' */ | |
2424 | if ((size = get_absolute_expression ()) < 0) | |
2425 | { | |
2426 | as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size); | |
2427 | ignore_rest_of_line (); | |
2428 | return; | |
2429 | } | |
2430 | ||
2431 | /* The third argument to .lcomm is the alignment. */ | |
2432 | if (*input_line_pointer != ',') | |
2433 | align = 8; | |
2434 | else | |
2435 | { | |
2436 | ++input_line_pointer; | |
2437 | align = get_absolute_expression (); | |
2438 | if (align <= 0) | |
2439 | { | |
2440 | as_warn (_("ignoring bad alignment")); | |
2441 | align = 8; | |
2442 | } | |
2443 | } | |
2444 | ||
2445 | *p = 0; | |
2446 | symbolP = symbol_find_or_make (name); | |
2447 | *p = c; | |
2448 | ||
2449 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
2450 | { | |
d6ed37ed | 2451 | as_bad (_("ignoring attempt to re-define symbol `%s'."), |
252b5132 RH |
2452 | S_GET_NAME (symbolP)); |
2453 | ignore_rest_of_line (); | |
2454 | return; | |
2455 | } | |
2456 | ||
2457 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
2458 | { | |
d6ed37ed | 2459 | as_bad (_("length of .lcomm \"%s\" is already %ld. Not changed to %ld."), |
252b5132 RH |
2460 | S_GET_NAME (symbolP), |
2461 | (long) S_GET_VALUE (symbolP), | |
2462 | (long) size); | |
2463 | ||
2464 | ignore_rest_of_line (); | |
2465 | return; | |
2466 | } | |
2467 | ||
99a814a1 | 2468 | /* Allocate_bss. */ |
252b5132 RH |
2469 | old_sec = now_seg; |
2470 | old_subsec = now_subseg; | |
2471 | if (align) | |
2472 | { | |
99a814a1 | 2473 | /* Convert to a power of 2 alignment. */ |
252b5132 RH |
2474 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2); |
2475 | if (align != 1) | |
2476 | { | |
d6ed37ed | 2477 | as_bad (_("common alignment not a power of 2")); |
252b5132 RH |
2478 | ignore_rest_of_line (); |
2479 | return; | |
2480 | } | |
2481 | } | |
2482 | else | |
2483 | align2 = 0; | |
2484 | ||
2485 | record_alignment (bss_section, align2); | |
cbe02d4f | 2486 | subseg_set (bss_section, 1); |
252b5132 RH |
2487 | if (align2) |
2488 | frag_align (align2, 0, 0); | |
2489 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
2490 | symbol_get_frag (symbolP)->fr_symbol = 0; |
2491 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
2492 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
2493 | (char *) 0); | |
2494 | *pfrag = 0; | |
2495 | S_SET_SIZE (symbolP, size); | |
2496 | S_SET_SEGMENT (symbolP, bss_section); | |
2497 | subseg_set (old_sec, old_subsec); | |
2498 | demand_empty_rest_of_line (); | |
2499 | } | |
2500 | ||
6911b7dc AM |
2501 | /* Pseudo op to set symbol local entry point. */ |
2502 | static void | |
2503 | ppc_elf_localentry (int ignore ATTRIBUTE_UNUSED) | |
2504 | { | |
d02603dc NC |
2505 | char *name; |
2506 | char c = get_symbol_name (&name); | |
6911b7dc AM |
2507 | char *p; |
2508 | expressionS exp; | |
2509 | symbolS *sym; | |
2510 | asymbol *bfdsym; | |
2511 | elf_symbol_type *elfsym; | |
2512 | ||
2513 | p = input_line_pointer; | |
2514 | *p = c; | |
d02603dc | 2515 | SKIP_WHITESPACE_AFTER_NAME (); |
6911b7dc AM |
2516 | if (*input_line_pointer != ',') |
2517 | { | |
2518 | *p = 0; | |
2519 | as_bad (_("expected comma after name `%s' in .localentry directive"), | |
2520 | name); | |
2521 | *p = c; | |
2522 | ignore_rest_of_line (); | |
2523 | return; | |
2524 | } | |
2525 | input_line_pointer++; | |
2526 | expression (&exp); | |
2527 | if (exp.X_op == O_absent) | |
2528 | { | |
2529 | as_bad (_("missing expression in .localentry directive")); | |
2530 | exp.X_op = O_constant; | |
2531 | exp.X_add_number = 0; | |
2532 | } | |
2533 | *p = 0; | |
2534 | sym = symbol_find_or_make (name); | |
2535 | *p = c; | |
2536 | ||
2537 | if (resolve_expression (&exp) | |
2538 | && exp.X_op == O_constant) | |
2539 | { | |
33cb30a1 | 2540 | unsigned int encoded, ok; |
6911b7dc | 2541 | |
33cb30a1 AM |
2542 | ok = 1; |
2543 | if (exp.X_add_number == 1 || exp.X_add_number == 7) | |
2544 | encoded = exp.X_add_number << STO_PPC64_LOCAL_BIT; | |
6911b7dc | 2545 | else |
33cb30a1 AM |
2546 | { |
2547 | encoded = PPC64_SET_LOCAL_ENTRY_OFFSET (exp.X_add_number); | |
2548 | if (exp.X_add_number != (offsetT) PPC64_LOCAL_ENTRY_OFFSET (encoded)) | |
2549 | { | |
2550 | as_bad (_(".localentry expression for `%s' " | |
2551 | "is not a valid power of 2"), S_GET_NAME (sym)); | |
2552 | ok = 0; | |
2553 | } | |
2554 | } | |
2555 | if (ok) | |
6911b7dc AM |
2556 | { |
2557 | bfdsym = symbol_get_bfdsym (sym); | |
2558 | elfsym = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym); | |
2559 | gas_assert (elfsym); | |
2560 | elfsym->internal_elf_sym.st_other &= ~STO_PPC64_LOCAL_MASK; | |
2561 | elfsym->internal_elf_sym.st_other |= encoded; | |
2562 | if (ppc_abiversion == 0) | |
2563 | ppc_abiversion = 2; | |
2564 | } | |
2565 | } | |
2566 | else | |
2567 | as_bad (_(".localentry expression for `%s' " | |
2568 | "does not evaluate to a constant"), S_GET_NAME (sym)); | |
2569 | ||
2570 | demand_empty_rest_of_line (); | |
2571 | } | |
2572 | ||
ee67d69a AM |
2573 | /* Pseudo op to set ABI version. */ |
2574 | static void | |
2575 | ppc_elf_abiversion (int ignore ATTRIBUTE_UNUSED) | |
2576 | { | |
2577 | expressionS exp; | |
2578 | ||
2579 | expression (&exp); | |
2580 | if (exp.X_op == O_absent) | |
2581 | { | |
2582 | as_bad (_("missing expression in .abiversion directive")); | |
2583 | exp.X_op = O_constant; | |
2584 | exp.X_add_number = 0; | |
2585 | } | |
2586 | ||
2587 | if (resolve_expression (&exp) | |
2588 | && exp.X_op == O_constant) | |
2589 | ppc_abiversion = exp.X_add_number; | |
2590 | else | |
2591 | as_bad (_(".abiversion expression does not evaluate to a constant")); | |
2592 | demand_empty_rest_of_line (); | |
2593 | } | |
2594 | ||
005d79fd AM |
2595 | /* Parse a .gnu_attribute directive. */ |
2596 | static void | |
2597 | ppc_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED) | |
2598 | { | |
2599 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU); | |
2600 | ||
2601 | /* Check validity of defined powerpc tags. */ | |
2602 | if (tag == Tag_GNU_Power_ABI_FP | |
2603 | || tag == Tag_GNU_Power_ABI_Vector | |
2604 | || tag == Tag_GNU_Power_ABI_Struct_Return) | |
2605 | { | |
2606 | unsigned int val; | |
2607 | ||
2608 | val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag); | |
2609 | ||
2610 | if ((tag == Tag_GNU_Power_ABI_FP && val > 15) | |
2611 | || (tag == Tag_GNU_Power_ABI_Vector && val > 3) | |
2612 | || (tag == Tag_GNU_Power_ABI_Struct_Return && val > 2)) | |
2613 | as_warn (_("unknown .gnu_attribute value")); | |
2614 | } | |
2615 | } | |
2616 | ||
ee67d69a AM |
2617 | /* Set ABI version in output file. */ |
2618 | void | |
2619 | ppc_elf_end (void) | |
2620 | { | |
2621 | if (ppc_obj64 && ppc_abiversion != 0) | |
2622 | { | |
2623 | elf_elfheader (stdoutput)->e_flags &= ~EF_PPC64_ABI; | |
2624 | elf_elfheader (stdoutput)->e_flags |= ppc_abiversion & EF_PPC64_ABI; | |
2625 | } | |
22f72c48 AM |
2626 | /* Any selection of opcodes based on ppc_cpu after gas has finished |
2627 | parsing the file is invalid. md_apply_fix and ppc_handle_align | |
2628 | must select opcodes based on the machine in force at the point | |
2629 | where the fixup or alignment frag was created, not the machine in | |
2630 | force at the end of file. */ | |
2631 | ppc_cpu = 0; | |
ee67d69a AM |
2632 | } |
2633 | ||
252b5132 RH |
2634 | /* Validate any relocations emitted for -mrelocatable, possibly adding |
2635 | fixups for word relocations in writable segments, so we can adjust | |
2636 | them at runtime. */ | |
2637 | static void | |
98027b10 | 2638 | ppc_elf_validate_fix (fixS *fixp, segT seg) |
252b5132 RH |
2639 | { |
2640 | if (fixp->fx_done || fixp->fx_pcrel) | |
2641 | return; | |
2642 | ||
2643 | switch (shlib) | |
2644 | { | |
2645 | case SHLIB_NONE: | |
2646 | case SHLIB_PIC: | |
2647 | return; | |
2648 | ||
5d6f4f16 | 2649 | case SHLIB_MRELOCATABLE: |
62ebcb5c | 2650 | if (fixp->fx_r_type != BFD_RELOC_16_GOTOFF |
252b5132 RH |
2651 | && fixp->fx_r_type != BFD_RELOC_HI16_GOTOFF |
2652 | && fixp->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
2653 | && fixp->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
1cfc59d5 | 2654 | && fixp->fx_r_type != BFD_RELOC_16_BASEREL |
252b5132 RH |
2655 | && fixp->fx_r_type != BFD_RELOC_LO16_BASEREL |
2656 | && fixp->fx_r_type != BFD_RELOC_HI16_BASEREL | |
2657 | && fixp->fx_r_type != BFD_RELOC_HI16_S_BASEREL | |
e138127a | 2658 | && (seg->flags & SEC_LOAD) != 0 |
252b5132 RH |
2659 | && strcmp (segment_name (seg), ".got2") != 0 |
2660 | && strcmp (segment_name (seg), ".dtors") != 0 | |
2661 | && strcmp (segment_name (seg), ".ctors") != 0 | |
2662 | && strcmp (segment_name (seg), ".fixup") != 0 | |
252b5132 RH |
2663 | && strcmp (segment_name (seg), ".gcc_except_table") != 0 |
2664 | && strcmp (segment_name (seg), ".eh_frame") != 0 | |
2665 | && strcmp (segment_name (seg), ".ex_shared") != 0) | |
2666 | { | |
2667 | if ((seg->flags & (SEC_READONLY | SEC_CODE)) != 0 | |
2668 | || fixp->fx_r_type != BFD_RELOC_CTOR) | |
2669 | { | |
2670 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d6ed37ed | 2671 | _("relocation cannot be done when using -mrelocatable")); |
252b5132 RH |
2672 | } |
2673 | } | |
2674 | return; | |
2675 | } | |
2676 | } | |
0baf16f2 | 2677 | |
7e8d4ab4 AM |
2678 | /* Prevent elf_frob_file_before_adjust removing a weak undefined |
2679 | function descriptor sym if the corresponding code sym is used. */ | |
2680 | ||
2681 | void | |
98027b10 | 2682 | ppc_frob_file_before_adjust (void) |
0baf16f2 | 2683 | { |
7e8d4ab4 | 2684 | symbolS *symp; |
9232bbb0 | 2685 | asection *toc; |
0baf16f2 | 2686 | |
7e8d4ab4 AM |
2687 | if (!ppc_obj64) |
2688 | return; | |
2689 | ||
2690 | for (symp = symbol_rootP; symp; symp = symbol_next (symp)) | |
0baf16f2 | 2691 | { |
7e8d4ab4 AM |
2692 | const char *name; |
2693 | char *dotname; | |
2694 | symbolS *dotsym; | |
7e8d4ab4 AM |
2695 | |
2696 | name = S_GET_NAME (symp); | |
2697 | if (name[0] == '.') | |
2698 | continue; | |
2699 | ||
2700 | if (! S_IS_WEAK (symp) | |
2701 | || S_IS_DEFINED (symp)) | |
2702 | continue; | |
2703 | ||
a44e2901 | 2704 | dotname = concat (".", name, (char *) NULL); |
461b725f | 2705 | dotsym = symbol_find_noref (dotname, 1); |
7e8d4ab4 AM |
2706 | free (dotname); |
2707 | if (dotsym != NULL && (symbol_used_p (dotsym) | |
2708 | || symbol_used_in_reloc_p (dotsym))) | |
670ec21d NC |
2709 | symbol_mark_used (symp); |
2710 | ||
0baf16f2 AM |
2711 | } |
2712 | ||
9232bbb0 AM |
2713 | toc = bfd_get_section_by_name (stdoutput, ".toc"); |
2714 | if (toc != NULL | |
01efc3af | 2715 | && toc_reloc_types != has_large_toc_reloc |
fd361982 | 2716 | && bfd_section_size (toc) > 0x10000) |
9232bbb0 | 2717 | as_warn (_("TOC section size exceeds 64k")); |
a38a07e0 AM |
2718 | } |
2719 | ||
2720 | /* .TOC. used in an opd entry as .TOC.@tocbase doesn't need to be | |
2721 | emitted. Other uses of .TOC. will cause the symbol to be marked | |
2722 | with BSF_KEEP in md_apply_fix. */ | |
9232bbb0 | 2723 | |
a38a07e0 AM |
2724 | void |
2725 | ppc_elf_adjust_symtab (void) | |
2726 | { | |
2727 | if (ppc_obj64) | |
2728 | { | |
2729 | symbolS *symp; | |
2730 | symp = symbol_find (".TOC."); | |
2731 | if (symp != NULL) | |
2732 | { | |
2733 | asymbol *bsym = symbol_get_bfdsym (symp); | |
2734 | if ((bsym->flags & BSF_KEEP) == 0) | |
2735 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
a38a07e0 AM |
2736 | } |
2737 | } | |
0baf16f2 | 2738 | } |
252b5132 RH |
2739 | #endif /* OBJ_ELF */ |
2740 | \f | |
2741 | #ifdef TE_PE | |
2742 | ||
2743 | /* | |
99a814a1 | 2744 | * Summary of parse_toc_entry. |
252b5132 RH |
2745 | * |
2746 | * in: Input_line_pointer points to the '[' in one of: | |
2747 | * | |
2748 | * [toc] [tocv] [toc32] [toc64] | |
2749 | * | |
2750 | * Anything else is an error of one kind or another. | |
2751 | * | |
81d4177b | 2752 | * out: |
252b5132 RH |
2753 | * return value: success or failure |
2754 | * toc_kind: kind of toc reference | |
2755 | * input_line_pointer: | |
2756 | * success: first char after the ']' | |
2757 | * failure: unchanged | |
2758 | * | |
2759 | * settings: | |
2760 | * | |
2761 | * [toc] - rv == success, toc_kind = default_toc | |
2762 | * [tocv] - rv == success, toc_kind = data_in_toc | |
2763 | * [toc32] - rv == success, toc_kind = must_be_32 | |
2764 | * [toc64] - rv == success, toc_kind = must_be_64 | |
2765 | * | |
2766 | */ | |
2767 | ||
81d4177b KH |
2768 | enum toc_size_qualifier |
2769 | { | |
252b5132 RH |
2770 | default_toc, /* The toc cell constructed should be the system default size */ |
2771 | data_in_toc, /* This is a direct reference to a toc cell */ | |
2772 | must_be_32, /* The toc cell constructed must be 32 bits wide */ | |
2773 | must_be_64 /* The toc cell constructed must be 64 bits wide */ | |
2774 | }; | |
2775 | ||
2776 | static int | |
98027b10 | 2777 | parse_toc_entry (enum toc_size_qualifier *toc_kind) |
252b5132 RH |
2778 | { |
2779 | char *start; | |
2780 | char *toc_spec; | |
2781 | char c; | |
2782 | enum toc_size_qualifier t; | |
2783 | ||
99a814a1 | 2784 | /* Save the input_line_pointer. */ |
252b5132 RH |
2785 | start = input_line_pointer; |
2786 | ||
99a814a1 | 2787 | /* Skip over the '[' , and whitespace. */ |
252b5132 RH |
2788 | ++input_line_pointer; |
2789 | SKIP_WHITESPACE (); | |
81d4177b | 2790 | |
99a814a1 | 2791 | /* Find the spelling of the operand. */ |
d02603dc | 2792 | c = get_symbol_name (&toc_spec); |
252b5132 | 2793 | |
99a814a1 | 2794 | if (strcmp (toc_spec, "toc") == 0) |
252b5132 RH |
2795 | { |
2796 | t = default_toc; | |
2797 | } | |
99a814a1 | 2798 | else if (strcmp (toc_spec, "tocv") == 0) |
252b5132 RH |
2799 | { |
2800 | t = data_in_toc; | |
2801 | } | |
99a814a1 | 2802 | else if (strcmp (toc_spec, "toc32") == 0) |
252b5132 RH |
2803 | { |
2804 | t = must_be_32; | |
2805 | } | |
99a814a1 | 2806 | else if (strcmp (toc_spec, "toc64") == 0) |
252b5132 RH |
2807 | { |
2808 | t = must_be_64; | |
2809 | } | |
2810 | else | |
2811 | { | |
2812 | as_bad (_("syntax error: invalid toc specifier `%s'"), toc_spec); | |
99a814a1 AM |
2813 | *input_line_pointer = c; |
2814 | input_line_pointer = start; | |
252b5132 RH |
2815 | return 0; |
2816 | } | |
2817 | ||
99a814a1 AM |
2818 | /* Now find the ']'. */ |
2819 | *input_line_pointer = c; | |
252b5132 | 2820 | |
d02603dc | 2821 | SKIP_WHITESPACE_AFTER_NAME (); /* leading whitespace could be there. */ |
81d4177b | 2822 | c = *input_line_pointer++; /* input_line_pointer->past char in c. */ |
252b5132 RH |
2823 | |
2824 | if (c != ']') | |
2825 | { | |
2826 | as_bad (_("syntax error: expected `]', found `%c'"), c); | |
99a814a1 | 2827 | input_line_pointer = start; |
252b5132 RH |
2828 | return 0; |
2829 | } | |
2830 | ||
99a814a1 | 2831 | *toc_kind = t; |
252b5132 RH |
2832 | return 1; |
2833 | } | |
2834 | #endif | |
3b8b57a9 | 2835 | |
3e60bf4d | 2836 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
3b8b57a9 AM |
2837 | /* See whether a symbol is in the TOC section. */ |
2838 | ||
2839 | static int | |
2840 | ppc_is_toc_sym (symbolS *sym) | |
2841 | { | |
3e60bf4d | 2842 | #ifdef OBJ_XCOFF |
9f6e76f4 TG |
2843 | return (symbol_get_tc (sym)->symbol_class == XMC_TC |
2844 | || symbol_get_tc (sym)->symbol_class == XMC_TC0); | |
f50c47f1 | 2845 | #endif |
3e60bf4d AM |
2846 | #ifdef OBJ_ELF |
2847 | const char *sname = segment_name (S_GET_SEGMENT (sym)); | |
2848 | if (ppc_obj64) | |
2849 | return strcmp (sname, ".toc") == 0; | |
2850 | else | |
2851 | return strcmp (sname, ".got") == 0; | |
2852 | #endif | |
2853 | } | |
2854 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ | |
252b5132 RH |
2855 | \f |
2856 | ||
dc1d03fc | 2857 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
2858 | #define APUID(a,v) ((((a) & 0xffff) << 16) | ((v) & 0xffff)) |
2859 | static void | |
98027b10 | 2860 | ppc_apuinfo_section_add (unsigned int apu, unsigned int version) |
6a0c61b7 EZ |
2861 | { |
2862 | unsigned int i; | |
2863 | ||
2864 | /* Check we don't already exist. */ | |
2865 | for (i = 0; i < ppc_apuinfo_num; i++) | |
dc1d03fc | 2866 | if (ppc_apuinfo_list[i] == APUID (apu, version)) |
6a0c61b7 | 2867 | return; |
b34976b6 | 2868 | |
6a0c61b7 EZ |
2869 | if (ppc_apuinfo_num == ppc_apuinfo_num_alloc) |
2870 | { | |
2871 | if (ppc_apuinfo_num_alloc == 0) | |
2872 | { | |
2873 | ppc_apuinfo_num_alloc = 4; | |
325801bd | 2874 | ppc_apuinfo_list = XNEWVEC (unsigned long, ppc_apuinfo_num_alloc); |
6a0c61b7 EZ |
2875 | } |
2876 | else | |
2877 | { | |
2878 | ppc_apuinfo_num_alloc += 4; | |
325801bd TS |
2879 | ppc_apuinfo_list = XRESIZEVEC (unsigned long, ppc_apuinfo_list, |
2880 | ppc_apuinfo_num_alloc); | |
6a0c61b7 EZ |
2881 | } |
2882 | } | |
dc1d03fc | 2883 | ppc_apuinfo_list[ppc_apuinfo_num++] = APUID (apu, version); |
6a0c61b7 EZ |
2884 | } |
2885 | #undef APUID | |
dc1d03fc | 2886 | #endif |
6a0c61b7 | 2887 | \f |
dd7efa79 PB |
2888 | /* Various frobbings of labels and their addresses. */ |
2889 | ||
2890 | /* Symbols labelling the current insn. */ | |
2891 | struct insn_label_list | |
2892 | { | |
2893 | struct insn_label_list *next; | |
2894 | symbolS *label; | |
2895 | }; | |
2896 | ||
2897 | static struct insn_label_list *insn_labels; | |
2898 | static struct insn_label_list *free_insn_labels; | |
2899 | ||
2900 | static void | |
2901 | ppc_record_label (symbolS *sym) | |
2902 | { | |
2903 | struct insn_label_list *l; | |
2904 | ||
2905 | if (free_insn_labels == NULL) | |
2906 | l = XNEW (struct insn_label_list); | |
2907 | else | |
2908 | { | |
2909 | l = free_insn_labels; | |
2910 | free_insn_labels = l->next; | |
2911 | } | |
2912 | ||
2913 | l->label = sym; | |
2914 | l->next = insn_labels; | |
2915 | insn_labels = l; | |
2916 | } | |
2917 | ||
2918 | static void | |
2919 | ppc_clear_labels (void) | |
2920 | { | |
2921 | while (insn_labels != NULL) | |
2922 | { | |
2923 | struct insn_label_list *l = insn_labels; | |
2924 | insn_labels = l->next; | |
2925 | l->next = free_insn_labels; | |
2926 | free_insn_labels = l; | |
2927 | } | |
2928 | } | |
2929 | ||
2930 | void | |
2931 | ppc_start_line_hook (void) | |
2932 | { | |
2933 | ppc_clear_labels (); | |
2934 | } | |
2935 | ||
2936 | void | |
2937 | ppc_new_dot_label (symbolS *sym) | |
2938 | { | |
2939 | ppc_record_label (sym); | |
2940 | #ifdef OBJ_XCOFF | |
2941 | /* Anchor this label to the current csect for relocations. */ | |
2942 | symbol_get_tc (sym)->within = ppc_current_csect; | |
2943 | #endif | |
2944 | } | |
2945 | ||
2946 | void | |
2947 | ppc_frob_label (symbolS *sym) | |
2948 | { | |
2949 | ppc_record_label (sym); | |
2950 | ||
2951 | #ifdef OBJ_XCOFF | |
2952 | /* Set the class of a label based on where it is defined. This handles | |
2953 | symbols without suffixes. Also, move the symbol so that it follows | |
2954 | the csect symbol. */ | |
2955 | if (ppc_current_csect != (symbolS *) NULL) | |
2956 | { | |
2957 | if (symbol_get_tc (sym)->symbol_class == -1) | |
2958 | symbol_get_tc (sym)->symbol_class = symbol_get_tc (ppc_current_csect)->symbol_class; | |
2959 | ||
2960 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
2961 | symbol_append (sym, symbol_get_tc (ppc_current_csect)->within, | |
2962 | &symbol_rootP, &symbol_lastP); | |
2963 | symbol_get_tc (ppc_current_csect)->within = sym; | |
2964 | symbol_get_tc (sym)->within = ppc_current_csect; | |
2965 | } | |
2966 | #endif | |
2967 | ||
2968 | #ifdef OBJ_ELF | |
2969 | dwarf2_emit_label (sym); | |
2970 | #endif | |
2971 | } | |
6a0c61b7 | 2972 | |
252b5132 RH |
2973 | /* We need to keep a list of fixups. We can't simply generate them as |
2974 | we go, because that would require us to first create the frag, and | |
2975 | that would screw up references to ``.''. */ | |
2976 | ||
2977 | struct ppc_fixup | |
2978 | { | |
2979 | expressionS exp; | |
2980 | int opindex; | |
2981 | bfd_reloc_code_real_type reloc; | |
2982 | }; | |
2983 | ||
2984 | #define MAX_INSN_FIXUPS (5) | |
2985 | ||
0e2779e9 AM |
2986 | /* Return the field size operated on by RELOC, and whether it is |
2987 | pc-relative in PC_RELATIVE. */ | |
2988 | ||
2989 | static unsigned int | |
2990 | fixup_size (bfd_reloc_code_real_type reloc, bfd_boolean *pc_relative) | |
2991 | { | |
2992 | unsigned int size = 0; | |
2993 | bfd_boolean pcrel = FALSE; | |
2994 | ||
2995 | switch (reloc) | |
2996 | { | |
2997 | /* This switch statement must handle all BFD_RELOC values | |
2998 | possible in instruction fixups. As is, it handles all | |
2999 | BFD_RELOC values used in bfd/elf64-ppc.c, bfd/elf32-ppc.c, | |
3000 | bfd/coff-ppc, bfd/coff-rs6000.c and bfd/coff64-rs6000.c. | |
3001 | Overkill since data and marker relocs need not be handled | |
3002 | here, but this way we can be sure a needed fixup reloc isn't | |
3003 | accidentally omitted. */ | |
3004 | case BFD_RELOC_PPC_EMB_MRKREF: | |
3005 | case BFD_RELOC_VTABLE_ENTRY: | |
3006 | case BFD_RELOC_VTABLE_INHERIT: | |
3007 | break; | |
3008 | ||
3009 | case BFD_RELOC_8: | |
3010 | size = 1; | |
3011 | break; | |
3012 | ||
3013 | case BFD_RELOC_16: | |
3014 | case BFD_RELOC_16_BASEREL: | |
3015 | case BFD_RELOC_16_GOTOFF: | |
3016 | case BFD_RELOC_GPREL16: | |
3017 | case BFD_RELOC_HI16: | |
3018 | case BFD_RELOC_HI16_BASEREL: | |
3019 | case BFD_RELOC_HI16_GOTOFF: | |
3020 | case BFD_RELOC_HI16_PLTOFF: | |
3021 | case BFD_RELOC_HI16_S: | |
3022 | case BFD_RELOC_HI16_S_BASEREL: | |
3023 | case BFD_RELOC_HI16_S_GOTOFF: | |
3024 | case BFD_RELOC_HI16_S_PLTOFF: | |
3025 | case BFD_RELOC_LO16: | |
3026 | case BFD_RELOC_LO16_BASEREL: | |
3027 | case BFD_RELOC_LO16_GOTOFF: | |
3028 | case BFD_RELOC_LO16_PLTOFF: | |
3029 | case BFD_RELOC_PPC64_ADDR16_DS: | |
3030 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
3031 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
5663e321 AM |
3032 | case BFD_RELOC_PPC64_ADDR16_HIGHER34: |
3033 | case BFD_RELOC_PPC64_ADDR16_HIGHERA34: | |
3034 | case BFD_RELOC_PPC64_ADDR16_HIGHEST34: | |
3035 | case BFD_RELOC_PPC64_ADDR16_HIGHESTA34: | |
0e2779e9 AM |
3036 | case BFD_RELOC_PPC64_ADDR16_LO_DS: |
3037 | case BFD_RELOC_PPC64_DTPREL16_DS: | |
3038 | case BFD_RELOC_PPC64_DTPREL16_HIGH: | |
3039 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
3040 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
3041 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
3042 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
3043 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
3044 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
3045 | case BFD_RELOC_PPC64_GOT16_DS: | |
3046 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
3047 | case BFD_RELOC_PPC64_HIGHER: | |
3048 | case BFD_RELOC_PPC64_HIGHER_S: | |
3049 | case BFD_RELOC_PPC64_HIGHEST: | |
3050 | case BFD_RELOC_PPC64_HIGHEST_S: | |
3051 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
3052 | case BFD_RELOC_PPC64_PLTGOT16: | |
3053 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
3054 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
3055 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
3056 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
3057 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
3058 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
3059 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
3060 | case BFD_RELOC_PPC64_TOC16_DS: | |
3061 | case BFD_RELOC_PPC64_TOC16_HA: | |
3062 | case BFD_RELOC_PPC64_TOC16_HI: | |
3063 | case BFD_RELOC_PPC64_TOC16_LO: | |
3064 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
3065 | case BFD_RELOC_PPC64_TPREL16_DS: | |
3066 | case BFD_RELOC_PPC64_TPREL16_HIGH: | |
3067 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
3068 | case BFD_RELOC_PPC64_TPREL16_HIGHER: | |
3069 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
3070 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
3071 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
3072 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
3073 | #ifdef OBJ_XCOFF | |
3074 | case BFD_RELOC_PPC_BA16: | |
3075 | #endif | |
3076 | case BFD_RELOC_PPC_DTPREL16: | |
3077 | case BFD_RELOC_PPC_DTPREL16_HA: | |
3078 | case BFD_RELOC_PPC_DTPREL16_HI: | |
3079 | case BFD_RELOC_PPC_DTPREL16_LO: | |
3080 | case BFD_RELOC_PPC_EMB_NADDR16: | |
3081 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
3082 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
3083 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
3084 | case BFD_RELOC_PPC_EMB_RELSDA: | |
3085 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
3086 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
3087 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
3088 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
3089 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
3090 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
3091 | case BFD_RELOC_PPC_EMB_SDAI16: | |
3092 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
3093 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
3094 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
3095 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
3096 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
3097 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
3098 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
3099 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
3100 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
3101 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
3102 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
3103 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
3104 | case BFD_RELOC_PPC_GOT_TPREL16: | |
3105 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
3106 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
3107 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
3108 | case BFD_RELOC_PPC_TOC16: | |
3109 | case BFD_RELOC_PPC_TPREL16: | |
3110 | case BFD_RELOC_PPC_TPREL16_HA: | |
3111 | case BFD_RELOC_PPC_TPREL16_HI: | |
3112 | case BFD_RELOC_PPC_TPREL16_LO: | |
3113 | size = 2; | |
3114 | break; | |
3115 | ||
3116 | case BFD_RELOC_16_PCREL: | |
3117 | case BFD_RELOC_HI16_PCREL: | |
3118 | case BFD_RELOC_HI16_S_PCREL: | |
3119 | case BFD_RELOC_LO16_PCREL: | |
3120 | case BFD_RELOC_PPC64_REL16_HIGH: | |
3121 | case BFD_RELOC_PPC64_REL16_HIGHA: | |
3122 | case BFD_RELOC_PPC64_REL16_HIGHER: | |
5663e321 | 3123 | case BFD_RELOC_PPC64_REL16_HIGHER34: |
0e2779e9 | 3124 | case BFD_RELOC_PPC64_REL16_HIGHERA: |
5663e321 | 3125 | case BFD_RELOC_PPC64_REL16_HIGHERA34: |
0e2779e9 | 3126 | case BFD_RELOC_PPC64_REL16_HIGHEST: |
5663e321 | 3127 | case BFD_RELOC_PPC64_REL16_HIGHEST34: |
0e2779e9 | 3128 | case BFD_RELOC_PPC64_REL16_HIGHESTA: |
5663e321 | 3129 | case BFD_RELOC_PPC64_REL16_HIGHESTA34: |
0e2779e9 AM |
3130 | #ifdef OBJ_XCOFF |
3131 | case BFD_RELOC_PPC_B16: | |
3132 | #endif | |
3133 | case BFD_RELOC_PPC_VLE_REL8: | |
3134 | size = 2; | |
3135 | pcrel = TRUE; | |
3136 | break; | |
3137 | ||
3138 | case BFD_RELOC_16_GOT_PCREL: /* coff reloc, bad name re size. */ | |
3139 | case BFD_RELOC_32: | |
3140 | case BFD_RELOC_32_GOTOFF: | |
3141 | case BFD_RELOC_32_PLTOFF: | |
3142 | #ifdef OBJ_XCOFF | |
3143 | case BFD_RELOC_CTOR: | |
3144 | #endif | |
3145 | case BFD_RELOC_PPC64_ENTRY: | |
3146 | case BFD_RELOC_PPC_16DX_HA: | |
3147 | #ifndef OBJ_XCOFF | |
3148 | case BFD_RELOC_PPC_BA16: | |
3149 | #endif | |
3150 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
3151 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
3152 | case BFD_RELOC_PPC_BA26: | |
3153 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
3154 | case BFD_RELOC_PPC_EMB_NADDR32: | |
3155 | case BFD_RELOC_PPC_EMB_SDA21: | |
3156 | case BFD_RELOC_PPC_TLS: | |
3157 | case BFD_RELOC_PPC_TLSGD: | |
3158 | case BFD_RELOC_PPC_TLSLD: | |
3159 | case BFD_RELOC_PPC_VLE_HA16A: | |
3160 | case BFD_RELOC_PPC_VLE_HA16D: | |
3161 | case BFD_RELOC_PPC_VLE_HI16A: | |
3162 | case BFD_RELOC_PPC_VLE_HI16D: | |
3163 | case BFD_RELOC_PPC_VLE_LO16A: | |
3164 | case BFD_RELOC_PPC_VLE_LO16D: | |
3165 | case BFD_RELOC_PPC_VLE_SDA21: | |
3166 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
3167 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
3168 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
3169 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
3170 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
3171 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
3172 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
c213164a | 3173 | case BFD_RELOC_PPC64_TLS_PCREL: |
0e2779e9 AM |
3174 | case BFD_RELOC_RVA: |
3175 | size = 4; | |
3176 | break; | |
3177 | ||
3178 | case BFD_RELOC_24_PLT_PCREL: | |
3179 | case BFD_RELOC_32_PCREL: | |
3180 | case BFD_RELOC_32_PLT_PCREL: | |
3181 | case BFD_RELOC_PPC64_REL24_NOTOC: | |
3182 | #ifndef OBJ_XCOFF | |
3183 | case BFD_RELOC_PPC_B16: | |
3184 | #endif | |
3185 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
3186 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
3187 | case BFD_RELOC_PPC_B26: | |
3188 | case BFD_RELOC_PPC_LOCAL24PC: | |
3189 | case BFD_RELOC_PPC_REL16DX_HA: | |
3190 | case BFD_RELOC_PPC_VLE_REL15: | |
3191 | case BFD_RELOC_PPC_VLE_REL24: | |
3192 | size = 4; | |
3193 | pcrel = TRUE; | |
3194 | break; | |
3195 | ||
3196 | #ifndef OBJ_XCOFF | |
3197 | case BFD_RELOC_CTOR: | |
3198 | #endif | |
3199 | case BFD_RELOC_PPC_COPY: | |
3200 | case BFD_RELOC_PPC_DTPMOD: | |
3201 | case BFD_RELOC_PPC_DTPREL: | |
3202 | case BFD_RELOC_PPC_GLOB_DAT: | |
3203 | case BFD_RELOC_PPC_TPREL: | |
3204 | size = ppc_obj64 ? 8 : 4; | |
3205 | break; | |
3206 | ||
3207 | case BFD_RELOC_64: | |
3208 | case BFD_RELOC_64_PLTOFF: | |
3209 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
5663e321 AM |
3210 | case BFD_RELOC_PPC64_D28: |
3211 | case BFD_RELOC_PPC64_D34: | |
3212 | case BFD_RELOC_PPC64_D34_LO: | |
3213 | case BFD_RELOC_PPC64_D34_HI30: | |
3214 | case BFD_RELOC_PPC64_D34_HA30: | |
c213164a AM |
3215 | case BFD_RELOC_PPC64_TPREL34: |
3216 | case BFD_RELOC_PPC64_DTPREL34: | |
0e2779e9 AM |
3217 | case BFD_RELOC_PPC64_TOC: |
3218 | size = 8; | |
3219 | break; | |
3220 | ||
3221 | case BFD_RELOC_64_PCREL: | |
3222 | case BFD_RELOC_64_PLT_PCREL: | |
5663e321 | 3223 | case BFD_RELOC_PPC64_GOT_PCREL34: |
87c69f97 AM |
3224 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
3225 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
3226 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
3227 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
5663e321 AM |
3228 | case BFD_RELOC_PPC64_PCREL28: |
3229 | case BFD_RELOC_PPC64_PCREL34: | |
3230 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
0e2779e9 AM |
3231 | size = 8; |
3232 | pcrel = TRUE; | |
3233 | break; | |
3234 | ||
3235 | default: | |
3236 | abort (); | |
3237 | } | |
3238 | ||
3239 | if (ENABLE_CHECKING) | |
3240 | { | |
3241 | reloc_howto_type *reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
3242 | if (reloc_howto != NULL | |
3243 | && (size != bfd_get_reloc_size (reloc_howto) | |
3244 | || pcrel != reloc_howto->pc_relative)) | |
3245 | { | |
3246 | as_bad (_("%s howto doesn't match size/pcrel in gas"), | |
3247 | reloc_howto->name); | |
3248 | abort (); | |
3249 | } | |
3250 | } | |
3251 | *pc_relative = pcrel; | |
3252 | return size; | |
3253 | } | |
3254 | ||
a894d76a | 3255 | #ifdef OBJ_ELF |
160eba93 AM |
3256 | /* If we have parsed a call to __tls_get_addr, parse an argument like |
3257 | (gd0@tlsgd). *STR is the leading parenthesis on entry. If an arg | |
3258 | is successfully parsed, *STR is updated past the trailing | |
3259 | parenthesis and trailing white space, and *TLS_FIX contains the | |
3260 | reloc and arg expression. */ | |
3261 | ||
3262 | static int | |
3263 | parse_tls_arg (char **str, const expressionS *exp, struct ppc_fixup *tls_fix) | |
3264 | { | |
3265 | const char *sym_name = S_GET_NAME (exp->X_add_symbol); | |
3266 | if (sym_name[0] == '.') | |
3267 | ++sym_name; | |
3268 | ||
3269 | tls_fix->reloc = BFD_RELOC_NONE; | |
9e7028aa AM |
3270 | if (strncasecmp (sym_name, "__tls_get_addr", 14) == 0 |
3271 | && (sym_name[14] == 0 | |
3272 | || strcasecmp (sym_name + 14, "_desc") == 0 | |
3273 | || strcasecmp (sym_name + 14, "_opt") == 0)) | |
160eba93 AM |
3274 | { |
3275 | char *hold = input_line_pointer; | |
3276 | input_line_pointer = *str + 1; | |
3277 | expression (&tls_fix->exp); | |
3278 | if (tls_fix->exp.X_op == O_symbol) | |
3279 | { | |
3280 | if (strncasecmp (input_line_pointer, "@tlsgd)", 7) == 0) | |
3281 | tls_fix->reloc = BFD_RELOC_PPC_TLSGD; | |
3282 | else if (strncasecmp (input_line_pointer, "@tlsld)", 7) == 0) | |
3283 | tls_fix->reloc = BFD_RELOC_PPC_TLSLD; | |
3284 | if (tls_fix->reloc != BFD_RELOC_NONE) | |
3285 | { | |
3286 | input_line_pointer += 7; | |
3287 | SKIP_WHITESPACE (); | |
3288 | *str = input_line_pointer; | |
3289 | } | |
3290 | } | |
3291 | input_line_pointer = hold; | |
3292 | } | |
3293 | return tls_fix->reloc != BFD_RELOC_NONE; | |
3294 | } | |
a894d76a | 3295 | #endif |
160eba93 | 3296 | |
252b5132 RH |
3297 | /* This routine is called for each instruction to be assembled. */ |
3298 | ||
3299 | void | |
98027b10 | 3300 | md_assemble (char *str) |
252b5132 RH |
3301 | { |
3302 | char *s; | |
3303 | const struct powerpc_opcode *opcode; | |
0f873fd5 | 3304 | uint64_t insn; |
252b5132 | 3305 | const unsigned char *opindex_ptr; |
252b5132 RH |
3306 | int need_paren; |
3307 | int next_opindex; | |
3308 | struct ppc_fixup fixups[MAX_INSN_FIXUPS]; | |
3309 | int fc; | |
3310 | char *f; | |
a9479dc0 | 3311 | int addr_mask; |
252b5132 | 3312 | int i; |
b9c361e0 | 3313 | unsigned int insn_length; |
252b5132 RH |
3314 | |
3315 | /* Get the opcode. */ | |
3882b010 | 3316 | for (s = str; *s != '\0' && ! ISSPACE (*s); s++) |
252b5132 RH |
3317 | ; |
3318 | if (*s != '\0') | |
3319 | *s++ = '\0'; | |
3320 | ||
3321 | /* Look up the opcode in the hash table. */ | |
3322 | opcode = (const struct powerpc_opcode *) hash_find (ppc_hash, str); | |
3323 | if (opcode == (const struct powerpc_opcode *) NULL) | |
3324 | { | |
3325 | const struct powerpc_macro *macro; | |
3326 | ||
3327 | macro = (const struct powerpc_macro *) hash_find (ppc_macro_hash, str); | |
3328 | if (macro == (const struct powerpc_macro *) NULL) | |
d6ed37ed | 3329 | as_bad (_("unrecognized opcode: `%s'"), str); |
252b5132 RH |
3330 | else |
3331 | ppc_macro (s, macro); | |
3332 | ||
dd7efa79 | 3333 | ppc_clear_labels (); |
252b5132 RH |
3334 | return; |
3335 | } | |
3336 | ||
3337 | insn = opcode->opcode; | |
3338 | ||
3339 | str = s; | |
3882b010 | 3340 | while (ISSPACE (*str)) |
252b5132 RH |
3341 | ++str; |
3342 | ||
3343 | /* PowerPC operands are just expressions. The only real issue is | |
9cf7e568 AM |
3344 | that a few operand types are optional. If an instruction has |
3345 | multiple optional operands and one is omitted, then all optional | |
3346 | operands past the first omitted one must also be omitted. */ | |
3347 | int num_optional_operands = 0; | |
3348 | int num_optional_provided = 0; | |
252b5132 RH |
3349 | |
3350 | /* Gather the operands. */ | |
3351 | need_paren = 0; | |
3352 | next_opindex = 0; | |
3353 | fc = 0; | |
3354 | for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) | |
3355 | { | |
3356 | const struct powerpc_operand *operand; | |
3357 | const char *errmsg; | |
3358 | char *hold; | |
3359 | expressionS ex; | |
3360 | char endc; | |
3361 | ||
3362 | if (next_opindex == 0) | |
3363 | operand = &powerpc_operands[*opindex_ptr]; | |
3364 | else | |
3365 | { | |
3366 | operand = &powerpc_operands[next_opindex]; | |
3367 | next_opindex = 0; | |
3368 | } | |
252b5132 RH |
3369 | errmsg = NULL; |
3370 | ||
252b5132 | 3371 | /* If this is an optional operand, and we are skipping it, just |
9cf7e568 | 3372 | insert the default value, usually a zero. */ |
252b5132 | 3373 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 |
9cf7e568 | 3374 | && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)) |
252b5132 | 3375 | { |
9cf7e568 AM |
3376 | if (num_optional_operands == 0) |
3377 | { | |
3378 | const unsigned char *optr; | |
3379 | int total = 0; | |
3380 | int provided = 0; | |
3381 | int omitted; | |
3382 | ||
3383 | s = str; | |
3384 | for (optr = opindex_ptr; *optr != 0; optr++) | |
3385 | { | |
3386 | const struct powerpc_operand *op; | |
3387 | op = &powerpc_operands[*optr]; | |
3388 | ||
3389 | ++total; | |
3390 | ||
3391 | if ((op->flags & PPC_OPERAND_OPTIONAL) != 0 | |
3392 | && !((op->flags & PPC_OPERAND_OPTIONAL32) != 0 | |
3393 | && ppc_obj64)) | |
3394 | ++num_optional_operands; | |
3395 | ||
3396 | if (s != NULL && *s != '\0') | |
3397 | { | |
3398 | ++provided; | |
3399 | ||
3400 | /* Look for the start of the next operand. */ | |
3401 | if ((op->flags & PPC_OPERAND_PARENS) != 0) | |
3402 | s = strpbrk (s, "(,"); | |
3403 | else | |
3404 | s = strchr (s, ','); | |
3405 | ||
3406 | if (s != NULL) | |
3407 | ++s; | |
3408 | } | |
3409 | } | |
3410 | omitted = total - provided; | |
3411 | num_optional_provided = num_optional_operands - omitted; | |
3412 | } | |
3413 | if (--num_optional_provided < 0) | |
252b5132 | 3414 | { |
9cf7e568 AM |
3415 | int64_t val = ppc_optional_operand_value (operand, insn, ppc_cpu, |
3416 | num_optional_provided); | |
3417 | if (operand->insert) | |
3418 | { | |
3419 | insn = (*operand->insert) (insn, val, ppc_cpu, &errmsg); | |
3420 | if (errmsg != (const char *) NULL) | |
3421 | as_bad ("%s", errmsg); | |
3422 | } | |
3423 | else if (operand->shift >= 0) | |
3424 | insn |= (val & operand->bitm) << operand->shift; | |
3425 | else | |
3426 | insn |= (val & operand->bitm) >> -operand->shift; | |
3427 | ||
3428 | if ((operand->flags & PPC_OPERAND_NEXT) != 0) | |
3429 | next_opindex = *opindex_ptr + 1; | |
3430 | continue; | |
252b5132 | 3431 | } |
252b5132 RH |
3432 | } |
3433 | ||
3434 | /* Gather the operand. */ | |
3435 | hold = input_line_pointer; | |
3436 | input_line_pointer = str; | |
3437 | ||
3438 | #ifdef TE_PE | |
81d4177b | 3439 | if (*input_line_pointer == '[') |
252b5132 RH |
3440 | { |
3441 | /* We are expecting something like the second argument here: | |
99a814a1 AM |
3442 | * |
3443 | * lwz r4,[toc].GS.0.static_int(rtoc) | |
3444 | * ^^^^^^^^^^^^^^^^^^^^^^^^^^^ | |
3445 | * The argument following the `]' must be a symbol name, and the | |
3446 | * register must be the toc register: 'rtoc' or '2' | |
3447 | * | |
3448 | * The effect is to 0 as the displacement field | |
3449 | * in the instruction, and issue an IMAGE_REL_PPC_TOCREL16 (or | |
3450 | * the appropriate variation) reloc against it based on the symbol. | |
3451 | * The linker will build the toc, and insert the resolved toc offset. | |
3452 | * | |
3453 | * Note: | |
3454 | * o The size of the toc entry is currently assumed to be | |
3455 | * 32 bits. This should not be assumed to be a hard coded | |
3456 | * number. | |
3457 | * o In an effort to cope with a change from 32 to 64 bits, | |
3458 | * there are also toc entries that are specified to be | |
3459 | * either 32 or 64 bits: | |
3460 | * lwz r4,[toc32].GS.0.static_int(rtoc) | |
3461 | * lwz r4,[toc64].GS.0.static_int(rtoc) | |
3462 | * These demand toc entries of the specified size, and the | |
3463 | * instruction probably requires it. | |
3464 | */ | |
252b5132 RH |
3465 | |
3466 | int valid_toc; | |
3467 | enum toc_size_qualifier toc_kind; | |
3468 | bfd_reloc_code_real_type toc_reloc; | |
3469 | ||
99a814a1 AM |
3470 | /* Go parse off the [tocXX] part. */ |
3471 | valid_toc = parse_toc_entry (&toc_kind); | |
252b5132 | 3472 | |
81d4177b | 3473 | if (!valid_toc) |
252b5132 | 3474 | { |
a5840dce AM |
3475 | ignore_rest_of_line (); |
3476 | break; | |
252b5132 RH |
3477 | } |
3478 | ||
99a814a1 AM |
3479 | /* Now get the symbol following the ']'. */ |
3480 | expression (&ex); | |
252b5132 RH |
3481 | |
3482 | switch (toc_kind) | |
3483 | { | |
3484 | case default_toc: | |
99a814a1 AM |
3485 | /* In this case, we may not have seen the symbol yet, |
3486 | since it is allowed to appear on a .extern or .globl | |
3487 | or just be a label in the .data section. */ | |
252b5132 RH |
3488 | toc_reloc = BFD_RELOC_PPC_TOC16; |
3489 | break; | |
3490 | case data_in_toc: | |
99a814a1 AM |
3491 | /* 1. The symbol must be defined and either in the toc |
3492 | section, or a global. | |
3493 | 2. The reloc generated must have the TOCDEFN flag set | |
3494 | in upper bit mess of the reloc type. | |
3495 | FIXME: It's a little confusing what the tocv | |
3496 | qualifier can be used for. At the very least, I've | |
3497 | seen three uses, only one of which I'm sure I can | |
3498 | explain. */ | |
81d4177b KH |
3499 | if (ex.X_op == O_symbol) |
3500 | { | |
9c2799c2 | 3501 | gas_assert (ex.X_add_symbol != NULL); |
fed9b18a ILT |
3502 | if (symbol_get_bfdsym (ex.X_add_symbol)->section |
3503 | != tocdata_section) | |
252b5132 | 3504 | { |
99a814a1 | 3505 | as_bad (_("[tocv] symbol is not a toc symbol")); |
252b5132 RH |
3506 | } |
3507 | } | |
3508 | ||
3509 | toc_reloc = BFD_RELOC_PPC_TOC16; | |
3510 | break; | |
3511 | case must_be_32: | |
99a814a1 AM |
3512 | /* FIXME: these next two specifically specify 32/64 bit |
3513 | toc entries. We don't support them today. Is this | |
3514 | the right way to say that? */ | |
62ebcb5c | 3515 | toc_reloc = BFD_RELOC_NONE; |
d6ed37ed | 3516 | as_bad (_("unimplemented toc32 expression modifier")); |
252b5132 RH |
3517 | break; |
3518 | case must_be_64: | |
99a814a1 | 3519 | /* FIXME: see above. */ |
62ebcb5c | 3520 | toc_reloc = BFD_RELOC_NONE; |
d6ed37ed | 3521 | as_bad (_("unimplemented toc64 expression modifier")); |
252b5132 RH |
3522 | break; |
3523 | default: | |
bc805888 | 3524 | fprintf (stderr, |
99a814a1 AM |
3525 | _("Unexpected return value [%d] from parse_toc_entry!\n"), |
3526 | toc_kind); | |
bc805888 | 3527 | abort (); |
252b5132 RH |
3528 | break; |
3529 | } | |
3530 | ||
3531 | /* We need to generate a fixup for this expression. */ | |
3532 | if (fc >= MAX_INSN_FIXUPS) | |
3533 | as_fatal (_("too many fixups")); | |
3534 | ||
3535 | fixups[fc].reloc = toc_reloc; | |
3536 | fixups[fc].exp = ex; | |
3537 | fixups[fc].opindex = *opindex_ptr; | |
3538 | ++fc; | |
3539 | ||
99a814a1 AM |
3540 | /* Ok. We've set up the fixup for the instruction. Now make it |
3541 | look like the constant 0 was found here. */ | |
252b5132 RH |
3542 | ex.X_unsigned = 1; |
3543 | ex.X_op = O_constant; | |
3544 | ex.X_add_number = 0; | |
3545 | ex.X_add_symbol = NULL; | |
3546 | ex.X_op_symbol = NULL; | |
3547 | } | |
3548 | ||
3549 | else | |
3550 | #endif /* TE_PE */ | |
3551 | { | |
b9c361e0 JL |
3552 | if ((reg_names_p |
3553 | && (((operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
3554 | || ((operand->flags & PPC_OPERAND_CR_REG) != 0))) | |
2ad068be | 3555 | || !register_name (&ex)) |
252b5132 | 3556 | { |
13abbae3 AM |
3557 | char save_lex = lex_type['%']; |
3558 | ||
b9c361e0 JL |
3559 | if (((operand->flags & PPC_OPERAND_CR_REG) != 0) |
3560 | || (operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
13abbae3 AM |
3561 | { |
3562 | cr_operand = TRUE; | |
3563 | lex_type['%'] |= LEX_BEGIN_NAME; | |
3564 | } | |
252b5132 | 3565 | expression (&ex); |
b34976b6 | 3566 | cr_operand = FALSE; |
13abbae3 | 3567 | lex_type['%'] = save_lex; |
252b5132 RH |
3568 | } |
3569 | } | |
3570 | ||
3571 | str = input_line_pointer; | |
3572 | input_line_pointer = hold; | |
3573 | ||
3574 | if (ex.X_op == O_illegal) | |
3575 | as_bad (_("illegal operand")); | |
3576 | else if (ex.X_op == O_absent) | |
3577 | as_bad (_("missing operand")); | |
3578 | else if (ex.X_op == O_register) | |
3579 | { | |
7e0de605 AM |
3580 | if ((ex.X_md |
3581 | & ~operand->flags | |
3582 | & (PPC_OPERAND_GPR | PPC_OPERAND_FPR | PPC_OPERAND_VR | |
3583 | | PPC_OPERAND_VSR | PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG | |
aa3c112f | 3584 | | PPC_OPERAND_SPR | PPC_OPERAND_GQR | PPC_OPERAND_ACC)) != 0 |
7e0de605 AM |
3585 | && !((ex.X_md & PPC_OPERAND_GPR) != 0 |
3586 | && ex.X_add_number != 0 | |
3587 | && (operand->flags & PPC_OPERAND_GPR_0) != 0)) | |
ece5dcc1 | 3588 | as_warn (_("invalid register expression")); |
4b1c0f7e | 3589 | insn = ppc_insert_operand (insn, operand, ex.X_add_number, |
783de163 | 3590 | ppc_cpu, (char *) NULL, 0); |
252b5132 RH |
3591 | } |
3592 | else if (ex.X_op == O_constant) | |
3593 | { | |
3594 | #ifdef OBJ_ELF | |
81d4177b | 3595 | /* Allow @HA, @L, @H on constants. */ |
3b8b57a9 | 3596 | bfd_reloc_code_real_type reloc; |
252b5132 RH |
3597 | char *orig_str = str; |
3598 | ||
62ebcb5c | 3599 | if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE) |
252b5132 RH |
3600 | switch (reloc) |
3601 | { | |
3602 | default: | |
3603 | str = orig_str; | |
3604 | break; | |
3605 | ||
3606 | case BFD_RELOC_LO16: | |
f9c6b907 AM |
3607 | ex.X_add_number &= 0xffff; |
3608 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
0baf16f2 | 3609 | ex.X_add_number = SEX16 (ex.X_add_number); |
252b5132 RH |
3610 | break; |
3611 | ||
3612 | case BFD_RELOC_HI16: | |
f9c6b907 AM |
3613 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3614 | { | |
3615 | /* PowerPC64 @h is tested for overflow. */ | |
3616 | ex.X_add_number = (addressT) ex.X_add_number >> 16; | |
3617 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3618 | { | |
3619 | addressT sign = (((addressT) -1 >> 16) + 1) >> 1; | |
3620 | ex.X_add_number | |
3621 | = ((addressT) ex.X_add_number ^ sign) - sign; | |
3622 | } | |
3623 | break; | |
3624 | } | |
2b0f3761 | 3625 | /* Fallthru */ |
f9c6b907 AM |
3626 | |
3627 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
3628 | ex.X_add_number = PPC_HI (ex.X_add_number); | |
3629 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3630 | ex.X_add_number = SEX16 (ex.X_add_number); | |
252b5132 RH |
3631 | break; |
3632 | ||
3633 | case BFD_RELOC_HI16_S: | |
f9c6b907 AM |
3634 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3635 | { | |
3636 | /* PowerPC64 @ha is tested for overflow. */ | |
3637 | ex.X_add_number | |
3638 | = ((addressT) ex.X_add_number + 0x8000) >> 16; | |
3639 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3640 | { | |
3641 | addressT sign = (((addressT) -1 >> 16) + 1) >> 1; | |
3642 | ex.X_add_number | |
3643 | = ((addressT) ex.X_add_number ^ sign) - sign; | |
3644 | } | |
3645 | break; | |
3646 | } | |
2b0f3761 | 3647 | /* Fallthru */ |
f9c6b907 AM |
3648 | |
3649 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
3650 | ex.X_add_number = PPC_HA (ex.X_add_number); | |
3651 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3652 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 AM |
3653 | break; |
3654 | ||
0baf16f2 | 3655 | case BFD_RELOC_PPC64_HIGHER: |
f9c6b907 AM |
3656 | ex.X_add_number = PPC_HIGHER (ex.X_add_number); |
3657 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3658 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 AM |
3659 | break; |
3660 | ||
3661 | case BFD_RELOC_PPC64_HIGHER_S: | |
f9c6b907 AM |
3662 | ex.X_add_number = PPC_HIGHERA (ex.X_add_number); |
3663 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3664 | ex.X_add_number = SEX16 (ex.X_add_number); | |
252b5132 | 3665 | break; |
0baf16f2 AM |
3666 | |
3667 | case BFD_RELOC_PPC64_HIGHEST: | |
f9c6b907 AM |
3668 | ex.X_add_number = PPC_HIGHEST (ex.X_add_number); |
3669 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3670 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 AM |
3671 | break; |
3672 | ||
3673 | case BFD_RELOC_PPC64_HIGHEST_S: | |
f9c6b907 AM |
3674 | ex.X_add_number = PPC_HIGHESTA (ex.X_add_number); |
3675 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
3676 | ex.X_add_number = SEX16 (ex.X_add_number); | |
0baf16f2 | 3677 | break; |
252b5132 | 3678 | } |
0baf16f2 | 3679 | #endif /* OBJ_ELF */ |
252b5132 | 3680 | insn = ppc_insert_operand (insn, operand, ex.X_add_number, |
783de163 | 3681 | ppc_cpu, (char *) NULL, 0); |
252b5132 | 3682 | } |
727fc41e | 3683 | else |
252b5132 | 3684 | { |
62ebcb5c | 3685 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
3b8b57a9 | 3686 | #ifdef OBJ_ELF |
160eba93 AM |
3687 | /* Look for a __tls_get_addr arg using the insane old syntax. */ |
3688 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
3689 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
cdba85ec | 3690 | { |
160eba93 AM |
3691 | fixups[fc].opindex = *opindex_ptr; |
3692 | ++fc; | |
252b5132 RH |
3693 | } |
3694 | ||
62ebcb5c | 3695 | if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE) |
0baf16f2 | 3696 | { |
b9c361e0 JL |
3697 | /* If VLE-mode convert LO/HI/HA relocations. */ |
3698 | if (opcode->flags & PPC_OPCODE_VLE) | |
3699 | { | |
0f873fd5 | 3700 | uint64_t tmp_insn = insn & opcode->mask; |
3739860c | 3701 | |
08dc996f | 3702 | int use_a_reloc = (tmp_insn == E_OR2I_INSN |
b9c361e0 JL |
3703 | || tmp_insn == E_AND2I_DOT_INSN |
3704 | || tmp_insn == E_OR2IS_INSN | |
bb6bf75e | 3705 | || tmp_insn == E_LI_INSN |
b9c361e0 JL |
3706 | || tmp_insn == E_LIS_INSN |
3707 | || tmp_insn == E_AND2IS_DOT_INSN); | |
3708 | ||
3709 | ||
08dc996f | 3710 | int use_d_reloc = (tmp_insn == E_ADD2I_DOT_INSN |
b9c361e0 JL |
3711 | || tmp_insn == E_ADD2IS_INSN |
3712 | || tmp_insn == E_CMP16I_INSN | |
3713 | || tmp_insn == E_MULL2I_INSN | |
3714 | || tmp_insn == E_CMPL16I_INSN | |
3715 | || tmp_insn == E_CMPH16I_INSN | |
3716 | || tmp_insn == E_CMPHL16I_INSN); | |
3717 | ||
3718 | switch (reloc) | |
3719 | { | |
3720 | default: | |
3721 | break; | |
3722 | ||
3723 | case BFD_RELOC_PPC_EMB_SDA21: | |
3724 | reloc = BFD_RELOC_PPC_VLE_SDA21; | |
3725 | break; | |
3726 | ||
3727 | case BFD_RELOC_LO16: | |
3728 | if (use_d_reloc) | |
3729 | reloc = BFD_RELOC_PPC_VLE_LO16D; | |
3730 | else if (use_a_reloc) | |
3731 | reloc = BFD_RELOC_PPC_VLE_LO16A; | |
3732 | break; | |
3733 | ||
3734 | case BFD_RELOC_HI16: | |
3735 | if (use_d_reloc) | |
3736 | reloc = BFD_RELOC_PPC_VLE_HI16D; | |
3737 | else if (use_a_reloc) | |
3738 | reloc = BFD_RELOC_PPC_VLE_HI16A; | |
3739 | break; | |
3739860c | 3740 | |
b9c361e0 JL |
3741 | case BFD_RELOC_HI16_S: |
3742 | if (use_d_reloc) | |
3743 | reloc = BFD_RELOC_PPC_VLE_HA16D; | |
3744 | else if (use_a_reloc) | |
3745 | reloc = BFD_RELOC_PPC_VLE_HA16A; | |
3746 | break; | |
3747 | ||
3748 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
3749 | if (use_d_reloc) | |
3750 | reloc = BFD_RELOC_PPC_VLE_SDAREL_LO16D; | |
3751 | break; | |
3752 | ||
3753 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
3754 | if (use_d_reloc) | |
3755 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HI16D; | |
3756 | break; | |
3757 | ||
3758 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
3759 | if (use_d_reloc) | |
3760 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HA16D; | |
3761 | break; | |
3762 | } | |
3763 | } | |
bb6bf75e AM |
3764 | |
3765 | /* TLS and other tweaks. */ | |
3766 | switch (reloc) | |
3767 | { | |
3768 | default: | |
3769 | break; | |
3770 | ||
3771 | case BFD_RELOC_PPC_TLS: | |
c213164a | 3772 | case BFD_RELOC_PPC64_TLS_PCREL: |
bb6bf75e AM |
3773 | if (!_bfd_elf_ppc_at_tls_transform (opcode->opcode, 0)) |
3774 | as_bad (_("@tls may not be used with \"%s\" operands"), | |
3775 | opcode->name); | |
3776 | else if (operand->shift != 11) | |
3777 | as_bad (_("@tls may only be used in last operand")); | |
3778 | else | |
3779 | insn = ppc_insert_operand (insn, operand, | |
3780 | ppc_obj64 ? 13 : 2, | |
3781 | ppc_cpu, (char *) NULL, 0); | |
3782 | break; | |
3783 | ||
3784 | /* We'll only use the 32 (or 64) bit form of these relocations | |
c213164a | 3785 | in constants. Instructions get the 16 or 34 bit form. */ |
bb6bf75e | 3786 | case BFD_RELOC_PPC_DTPREL: |
c213164a AM |
3787 | if (operand->bitm == 0x3ffffffffULL) |
3788 | reloc = BFD_RELOC_PPC64_DTPREL34; | |
3789 | else | |
3790 | reloc = BFD_RELOC_PPC_DTPREL16; | |
bb6bf75e AM |
3791 | break; |
3792 | ||
3793 | case BFD_RELOC_PPC_TPREL: | |
c213164a AM |
3794 | if (operand->bitm == 0x3ffffffffULL) |
3795 | reloc = BFD_RELOC_PPC64_TPREL34; | |
3796 | else | |
3797 | reloc = BFD_RELOC_PPC_TPREL16; | |
bb6bf75e AM |
3798 | break; |
3799 | ||
5663e321 AM |
3800 | case BFD_RELOC_PPC64_PCREL34: |
3801 | if (operand->bitm == 0xfffffffULL) | |
3802 | { | |
3803 | reloc = BFD_RELOC_PPC64_PCREL28; | |
3804 | break; | |
3805 | } | |
3806 | /* Fall through. */ | |
3807 | case BFD_RELOC_PPC64_GOT_PCREL34: | |
3808 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
87c69f97 AM |
3809 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
3810 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
3811 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
3812 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
5663e321 | 3813 | if (operand->bitm != 0x3ffffffffULL |
bb6bf75e | 3814 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) |
5663e321 AM |
3815 | as_warn (_("%s unsupported on this instruction"), "@pcrel"); |
3816 | break; | |
3817 | ||
3818 | case BFD_RELOC_LO16: | |
3819 | if (operand->bitm == 0x3ffffffffULL | |
3820 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3821 | reloc = BFD_RELOC_PPC64_D34_LO; | |
3822 | else if ((operand->bitm | 0xf) != 0xffff | |
3823 | || operand->shift != 0 | |
3824 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
bb6bf75e AM |
3825 | as_warn (_("%s unsupported on this instruction"), "@l"); |
3826 | break; | |
3827 | ||
3828 | case BFD_RELOC_HI16: | |
5663e321 AM |
3829 | if (operand->bitm == 0x3ffffffffULL |
3830 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3831 | reloc = BFD_RELOC_PPC64_D34_HI30; | |
3832 | else if (operand->bitm != 0xffff | |
3833 | || operand->shift != 0 | |
3834 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
bb6bf75e AM |
3835 | as_warn (_("%s unsupported on this instruction"), "@h"); |
3836 | break; | |
3837 | ||
3838 | case BFD_RELOC_HI16_S: | |
5663e321 AM |
3839 | if (operand->bitm == 0x3ffffffffULL |
3840 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3841 | reloc = BFD_RELOC_PPC64_D34_HA30; | |
3842 | else if (operand->bitm == 0xffff | |
3843 | && operand->shift == (int) PPC_OPSHIFT_INV | |
3844 | && opcode->opcode == (19 << 26) + (2 << 1)) | |
bb6bf75e AM |
3845 | /* addpcis. */ |
3846 | reloc = BFD_RELOC_PPC_16DX_HA; | |
3847 | else if (operand->bitm != 0xffff | |
3848 | || operand->shift != 0 | |
3849 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
3850 | as_warn (_("%s unsupported on this instruction"), "@ha"); | |
3851 | } | |
0baf16f2 | 3852 | } |
3b8b57a9 AM |
3853 | #endif /* OBJ_ELF */ |
3854 | ||
62ebcb5c | 3855 | if (reloc != BFD_RELOC_NONE) |
3b8b57a9 AM |
3856 | ; |
3857 | /* Determine a BFD reloc value based on the operand information. | |
3858 | We are only prepared to turn a few of the operands into | |
3859 | relocs. */ | |
a0593ad9 AM |
3860 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3861 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3862 | && operand->bitm == 0x3fffffc |
3863 | && operand->shift == 0) | |
3864 | reloc = BFD_RELOC_PPC_B26; | |
a0593ad9 AM |
3865 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3866 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3867 | && operand->bitm == 0xfffc |
3868 | && operand->shift == 0) | |
3869 | reloc = BFD_RELOC_PPC_B16; | |
3870 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3871 | && operand->bitm == 0x1fe | |
3872 | && operand->shift == -1) | |
3873 | reloc = BFD_RELOC_PPC_VLE_REL8; | |
3874 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3875 | && operand->bitm == 0xfffe | |
3876 | && operand->shift == 0) | |
3877 | reloc = BFD_RELOC_PPC_VLE_REL15; | |
3878 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3879 | && operand->bitm == 0x1fffffe | |
3880 | && operand->shift == 0) | |
3881 | reloc = BFD_RELOC_PPC_VLE_REL24; | |
a0593ad9 | 3882 | else if ((operand->flags & PPC_OPERAND_NEGATIVE) == 0 |
3b8b57a9 AM |
3883 | && (operand->bitm & 0xfff0) == 0xfff0 |
3884 | && operand->shift == 0) | |
3885 | { | |
f50c47f1 | 3886 | reloc = BFD_RELOC_16; |
3e60bf4d | 3887 | #if defined OBJ_XCOFF || defined OBJ_ELF |
f50c47f1 | 3888 | /* Note: the symbol may be not yet defined. */ |
a0593ad9 AM |
3889 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
3890 | && ppc_is_toc_sym (ex.X_add_symbol)) | |
3e60bf4d AM |
3891 | { |
3892 | reloc = BFD_RELOC_PPC_TOC16; | |
3893 | #ifdef OBJ_ELF | |
3894 | as_warn (_("assuming %s on symbol"), | |
3895 | ppc_obj64 ? "@toc" : "@xgot"); | |
3896 | #endif | |
3897 | } | |
3b8b57a9 | 3898 | #endif |
3b8b57a9 | 3899 | } |
5663e321 AM |
3900 | else if (operand->bitm == 0x3ffffffffULL) |
3901 | reloc = BFD_RELOC_PPC64_D34; | |
3902 | else if (operand->bitm == 0xfffffffULL) | |
3903 | reloc = BFD_RELOC_PPC64_D28; | |
a0593ad9 AM |
3904 | |
3905 | /* For the absolute forms of branches, convert the PC | |
3906 | relative form back into the absolute. */ | |
3907 | if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) | |
3908 | { | |
3909 | switch (reloc) | |
3910 | { | |
3911 | case BFD_RELOC_PPC_B26: | |
3912 | reloc = BFD_RELOC_PPC_BA26; | |
3913 | break; | |
3914 | case BFD_RELOC_PPC_B16: | |
3915 | reloc = BFD_RELOC_PPC_BA16; | |
3916 | break; | |
3917 | #ifdef OBJ_ELF | |
3918 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
3919 | reloc = BFD_RELOC_PPC_BA16_BRTAKEN; | |
3920 | break; | |
3921 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
3922 | reloc = BFD_RELOC_PPC_BA16_BRNTAKEN; | |
3923 | break; | |
3924 | #endif | |
3925 | default: | |
3926 | break; | |
3927 | } | |
3928 | } | |
3929 | ||
3930 | #ifdef OBJ_ELF | |
3931 | switch (reloc) | |
3932 | { | |
3933 | case BFD_RELOC_PPC_TOC16: | |
3934 | toc_reloc_types |= has_small_toc_reloc; | |
3935 | break; | |
3936 | case BFD_RELOC_PPC64_TOC16_LO: | |
3937 | case BFD_RELOC_PPC64_TOC16_HI: | |
3938 | case BFD_RELOC_PPC64_TOC16_HA: | |
3939 | toc_reloc_types |= has_large_toc_reloc; | |
3940 | break; | |
3941 | default: | |
3942 | break; | |
3943 | } | |
3944 | ||
3945 | if (ppc_obj64 | |
3946 | && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0) | |
3947 | { | |
3948 | switch (reloc) | |
3949 | { | |
3950 | case BFD_RELOC_16: | |
3951 | reloc = BFD_RELOC_PPC64_ADDR16_DS; | |
3952 | break; | |
5663e321 | 3953 | |
a0593ad9 AM |
3954 | case BFD_RELOC_LO16: |
3955 | reloc = BFD_RELOC_PPC64_ADDR16_LO_DS; | |
3956 | break; | |
5663e321 | 3957 | |
a0593ad9 AM |
3958 | case BFD_RELOC_16_GOTOFF: |
3959 | reloc = BFD_RELOC_PPC64_GOT16_DS; | |
3960 | break; | |
5663e321 | 3961 | |
a0593ad9 AM |
3962 | case BFD_RELOC_LO16_GOTOFF: |
3963 | reloc = BFD_RELOC_PPC64_GOT16_LO_DS; | |
3964 | break; | |
5663e321 | 3965 | |
a0593ad9 AM |
3966 | case BFD_RELOC_LO16_PLTOFF: |
3967 | reloc = BFD_RELOC_PPC64_PLT16_LO_DS; | |
3968 | break; | |
5663e321 | 3969 | |
a0593ad9 AM |
3970 | case BFD_RELOC_16_BASEREL: |
3971 | reloc = BFD_RELOC_PPC64_SECTOFF_DS; | |
3972 | break; | |
5663e321 | 3973 | |
a0593ad9 AM |
3974 | case BFD_RELOC_LO16_BASEREL: |
3975 | reloc = BFD_RELOC_PPC64_SECTOFF_LO_DS; | |
3976 | break; | |
5663e321 | 3977 | |
a0593ad9 AM |
3978 | case BFD_RELOC_PPC_TOC16: |
3979 | reloc = BFD_RELOC_PPC64_TOC16_DS; | |
3980 | break; | |
5663e321 | 3981 | |
a0593ad9 AM |
3982 | case BFD_RELOC_PPC64_TOC16_LO: |
3983 | reloc = BFD_RELOC_PPC64_TOC16_LO_DS; | |
3984 | break; | |
5663e321 | 3985 | |
a0593ad9 AM |
3986 | case BFD_RELOC_PPC64_PLTGOT16: |
3987 | reloc = BFD_RELOC_PPC64_PLTGOT16_DS; | |
3988 | break; | |
5663e321 | 3989 | |
a0593ad9 AM |
3990 | case BFD_RELOC_PPC64_PLTGOT16_LO: |
3991 | reloc = BFD_RELOC_PPC64_PLTGOT16_LO_DS; | |
3992 | break; | |
5663e321 | 3993 | |
a0593ad9 AM |
3994 | case BFD_RELOC_PPC_DTPREL16: |
3995 | reloc = BFD_RELOC_PPC64_DTPREL16_DS; | |
3996 | break; | |
5663e321 | 3997 | |
a0593ad9 AM |
3998 | case BFD_RELOC_PPC_DTPREL16_LO: |
3999 | reloc = BFD_RELOC_PPC64_DTPREL16_LO_DS; | |
4000 | break; | |
5663e321 | 4001 | |
a0593ad9 AM |
4002 | case BFD_RELOC_PPC_TPREL16: |
4003 | reloc = BFD_RELOC_PPC64_TPREL16_DS; | |
4004 | break; | |
5663e321 | 4005 | |
a0593ad9 AM |
4006 | case BFD_RELOC_PPC_TPREL16_LO: |
4007 | reloc = BFD_RELOC_PPC64_TPREL16_LO_DS; | |
4008 | break; | |
5663e321 | 4009 | |
a0593ad9 AM |
4010 | case BFD_RELOC_PPC_GOT_DTPREL16: |
4011 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
4012 | case BFD_RELOC_PPC_GOT_TPREL16: | |
4013 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
4014 | break; | |
5663e321 | 4015 | |
a0593ad9 AM |
4016 | default: |
4017 | as_bad (_("unsupported relocation for DS offset field")); | |
4018 | break; | |
4019 | } | |
4020 | } | |
160eba93 AM |
4021 | |
4022 | /* Look for a __tls_get_addr arg after any __tls_get_addr | |
4023 | modifiers like @plt. This fixup must be emitted before | |
4024 | the usual call fixup. */ | |
4025 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
4026 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
4027 | { | |
4028 | fixups[fc].opindex = *opindex_ptr; | |
4029 | ++fc; | |
4030 | } | |
a0593ad9 | 4031 | #endif |
0baf16f2 | 4032 | |
252b5132 RH |
4033 | /* We need to generate a fixup for this expression. */ |
4034 | if (fc >= MAX_INSN_FIXUPS) | |
4035 | as_fatal (_("too many fixups")); | |
4036 | fixups[fc].exp = ex; | |
727fc41e | 4037 | fixups[fc].opindex = *opindex_ptr; |
252b5132 RH |
4038 | fixups[fc].reloc = reloc; |
4039 | ++fc; | |
4040 | } | |
252b5132 RH |
4041 | |
4042 | if (need_paren) | |
4043 | { | |
4044 | endc = ')'; | |
4045 | need_paren = 0; | |
c3d65c1c BE |
4046 | /* If expecting more operands, then we want to see "),". */ |
4047 | if (*str == endc && opindex_ptr[1] != 0) | |
4048 | { | |
4049 | do | |
4050 | ++str; | |
4051 | while (ISSPACE (*str)); | |
4052 | endc = ','; | |
4053 | } | |
252b5132 RH |
4054 | } |
4055 | else if ((operand->flags & PPC_OPERAND_PARENS) != 0) | |
9cf7e568 | 4056 | endc = '('; |
252b5132 RH |
4057 | else |
4058 | endc = ','; | |
4059 | ||
4060 | /* The call to expression should have advanced str past any | |
4061 | whitespace. */ | |
9cf7e568 | 4062 | if (*str == endc) |
252b5132 | 4063 | { |
9cf7e568 AM |
4064 | ++str; |
4065 | if (endc == '(') | |
4066 | need_paren = 1; | |
4067 | } | |
4068 | else if (*str != '\0') | |
4069 | { | |
4070 | as_bad (_("syntax error; found `%c', expected `%c'"), *str, endc); | |
4071 | break; | |
4072 | } | |
4073 | else if (endc == ')') | |
4074 | { | |
4075 | as_bad (_("syntax error; end of line, expected `%c'"), endc); | |
252b5132 RH |
4076 | break; |
4077 | } | |
252b5132 RH |
4078 | } |
4079 | ||
3882b010 | 4080 | while (ISSPACE (*str)) |
252b5132 RH |
4081 | ++str; |
4082 | ||
4083 | if (*str != '\0') | |
4084 | as_bad (_("junk at end of line: `%s'"), str); | |
4085 | ||
dc1d03fc | 4086 | #ifdef OBJ_ELF |
b9c361e0 | 4087 | /* Do we need/want an APUinfo section? */ |
4faf939a JM |
4088 | if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_VLE)) != 0 |
4089 | && !ppc_obj64) | |
6a0c61b7 EZ |
4090 | { |
4091 | /* These are all version "1". */ | |
4092 | if (opcode->flags & PPC_OPCODE_SPE) | |
b34976b6 | 4093 | ppc_apuinfo_section_add (PPC_APUINFO_SPE, 1); |
6a0c61b7 | 4094 | if (opcode->flags & PPC_OPCODE_ISEL) |
b34976b6 | 4095 | ppc_apuinfo_section_add (PPC_APUINFO_ISEL, 1); |
6a0c61b7 | 4096 | if (opcode->flags & PPC_OPCODE_EFS) |
b34976b6 | 4097 | ppc_apuinfo_section_add (PPC_APUINFO_EFS, 1); |
6a0c61b7 | 4098 | if (opcode->flags & PPC_OPCODE_BRLOCK) |
b34976b6 | 4099 | ppc_apuinfo_section_add (PPC_APUINFO_BRLOCK, 1); |
6a0c61b7 | 4100 | if (opcode->flags & PPC_OPCODE_PMR) |
b34976b6 | 4101 | ppc_apuinfo_section_add (PPC_APUINFO_PMR, 1); |
6a0c61b7 | 4102 | if (opcode->flags & PPC_OPCODE_CACHELCK) |
b34976b6 | 4103 | ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK, 1); |
6a0c61b7 | 4104 | if (opcode->flags & PPC_OPCODE_RFMCI) |
b34976b6 | 4105 | ppc_apuinfo_section_add (PPC_APUINFO_RFMCI, 1); |
fbd94057 MR |
4106 | /* Only set the VLE flag if the instruction has been pulled via |
4107 | the VLE instruction set. This way the flag is guaranteed to | |
4108 | be set for VLE-only instructions or for VLE-only processors, | |
4109 | however it'll remain clear for dual-mode instructions on | |
4110 | dual-mode and, more importantly, standard-mode processors. */ | |
4111 | if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE) | |
f7d69005 AM |
4112 | { |
4113 | ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1); | |
4114 | if (elf_section_data (now_seg) != NULL) | |
4115 | elf_section_data (now_seg)->this_hdr.sh_flags |= SHF_PPC_VLE; | |
4116 | } | |
6a0c61b7 | 4117 | } |
dc1d03fc | 4118 | #endif |
6a0c61b7 | 4119 | |
252b5132 | 4120 | /* Write out the instruction. */ |
a9479dc0 AM |
4121 | |
4122 | addr_mask = 3; | |
f7d69005 | 4123 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
a9479dc0 AM |
4124 | /* All instructions can start on a 2 byte boundary for VLE. */ |
4125 | addr_mask = 1; | |
4126 | ||
4127 | if (frag_now->insn_addr != addr_mask) | |
b9c361e0 | 4128 | { |
a9479dc0 AM |
4129 | /* Don't emit instructions to a frag started for data, or for a |
4130 | CPU differing in VLE mode. Data is allowed to be misaligned, | |
4131 | and it's possible to start a new frag in the middle of | |
4132 | misaligned data. */ | |
4133 | frag_wane (frag_now); | |
4134 | frag_new (0); | |
b9c361e0 | 4135 | } |
a9479dc0 AM |
4136 | |
4137 | /* Check that insns within the frag are aligned. ppc_frag_check | |
4138 | will ensure that the frag start address is aligned. */ | |
4139 | if ((frag_now_fix () & addr_mask) != 0) | |
4140 | as_bad (_("instruction address is not a multiple of %d"), addr_mask + 1); | |
4141 | ||
dd7efa79 | 4142 | /* Differentiate between two, four, and eight byte insns. */ |
a9479dc0 AM |
4143 | insn_length = 4; |
4144 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn)) | |
4145 | insn_length = 2; | |
7c1f4227 | 4146 | else if ((opcode->flags & PPC_OPCODE_POWER10) != 0 |
dd7efa79 PB |
4147 | && PPC_PREFIX_P (insn)) |
4148 | { | |
4149 | struct insn_label_list *l; | |
4150 | ||
4151 | insn_length = 8; | |
4152 | ||
4153 | /* 8-byte prefix instructions are not allowed to cross 64-byte | |
4154 | boundaries. */ | |
4155 | frag_align_code (6, 4); | |
4156 | record_alignment (now_seg, 6); | |
4157 | ||
4158 | /* Update "dot" in any expressions used by this instruction, and | |
4159 | a label attached to the instruction. By "attached" we mean | |
4160 | on the same source line as the instruction and without any | |
4161 | intervening semicolons. */ | |
4162 | dot_value = frag_now_fix (); | |
4163 | dot_frag = frag_now; | |
4164 | for (l = insn_labels; l != NULL; l = l->next) | |
4165 | { | |
4166 | symbol_set_frag (l->label, dot_frag); | |
4167 | S_SET_VALUE (l->label, dot_value); | |
4168 | } | |
4169 | } | |
4170 | ||
4171 | ppc_clear_labels (); | |
a9479dc0 | 4172 | |
b9c361e0 | 4173 | f = frag_more (insn_length); |
a9479dc0 | 4174 | frag_now->insn_addr = addr_mask; |
dd7efa79 PB |
4175 | |
4176 | /* The prefix part of an 8-byte instruction always occupies the lower | |
4177 | addressed word in a doubleword, regardless of endianness. */ | |
4178 | if (!target_big_endian && insn_length == 8) | |
4179 | { | |
4180 | md_number_to_chars (f, PPC_GET_PREFIX (insn), 4); | |
4181 | md_number_to_chars (f + 4, PPC_GET_SUFFIX (insn), 4); | |
4182 | } | |
4183 | else | |
4184 | md_number_to_chars (f, insn, insn_length); | |
4185 | ||
bf7279d5 AM |
4186 | last_insn = insn; |
4187 | last_seg = now_seg; | |
4188 | last_subseg = now_subseg; | |
252b5132 | 4189 | |
5d6f4f16 | 4190 | #ifdef OBJ_ELF |
b9c361e0 | 4191 | dwarf2_emit_insn (insn_length); |
5d6f4f16 GK |
4192 | #endif |
4193 | ||
3b8b57a9 | 4194 | /* Create any fixups. */ |
252b5132 RH |
4195 | for (i = 0; i < fc; i++) |
4196 | { | |
3b8b57a9 | 4197 | fixS *fixP; |
62ebcb5c | 4198 | if (fixups[i].reloc != BFD_RELOC_NONE) |
252b5132 | 4199 | { |
0e2779e9 AM |
4200 | bfd_boolean pcrel; |
4201 | unsigned int size = fixup_size (fixups[i].reloc, &pcrel); | |
4202 | int offset = target_big_endian ? (insn_length - size) : 0; | |
252b5132 | 4203 | |
99a814a1 AM |
4204 | fixP = fix_new_exp (frag_now, |
4205 | f - frag_now->fr_literal + offset, | |
4206 | size, | |
4207 | &fixups[i].exp, | |
0e2779e9 | 4208 | pcrel, |
252b5132 | 4209 | fixups[i].reloc); |
252b5132 RH |
4210 | } |
4211 | else | |
727fc41e AM |
4212 | { |
4213 | const struct powerpc_operand *operand; | |
4214 | ||
4215 | operand = &powerpc_operands[fixups[i].opindex]; | |
3b8b57a9 AM |
4216 | fixP = fix_new_exp (frag_now, |
4217 | f - frag_now->fr_literal, | |
4218 | insn_length, | |
4219 | &fixups[i].exp, | |
4220 | (operand->flags & PPC_OPERAND_RELATIVE) != 0, | |
62ebcb5c | 4221 | BFD_RELOC_NONE); |
727fc41e | 4222 | } |
3b8b57a9 | 4223 | fixP->fx_pcrel_adjust = fixups[i].opindex; |
252b5132 RH |
4224 | } |
4225 | } | |
4226 | ||
4227 | /* Handle a macro. Gather all the operands, transform them as | |
4228 | described by the macro, and call md_assemble recursively. All the | |
4229 | operands are separated by commas; we don't accept parentheses | |
4230 | around operands here. */ | |
4231 | ||
4232 | static void | |
98027b10 | 4233 | ppc_macro (char *str, const struct powerpc_macro *macro) |
252b5132 RH |
4234 | { |
4235 | char *operands[10]; | |
4236 | unsigned int count; | |
4237 | char *s; | |
4238 | unsigned int len; | |
4239 | const char *format; | |
db557034 | 4240 | unsigned int arg; |
252b5132 RH |
4241 | char *send; |
4242 | char *complete; | |
4243 | ||
4244 | /* Gather the users operands into the operands array. */ | |
4245 | count = 0; | |
4246 | s = str; | |
4247 | while (1) | |
4248 | { | |
4249 | if (count >= sizeof operands / sizeof operands[0]) | |
4250 | break; | |
4251 | operands[count++] = s; | |
4252 | s = strchr (s, ','); | |
4253 | if (s == (char *) NULL) | |
4254 | break; | |
4255 | *s++ = '\0'; | |
81d4177b | 4256 | } |
252b5132 RH |
4257 | |
4258 | if (count != macro->operands) | |
4259 | { | |
4260 | as_bad (_("wrong number of operands")); | |
4261 | return; | |
4262 | } | |
4263 | ||
4264 | /* Work out how large the string must be (the size is unbounded | |
4265 | because it includes user input). */ | |
4266 | len = 0; | |
4267 | format = macro->format; | |
4268 | while (*format != '\0') | |
4269 | { | |
4270 | if (*format != '%') | |
4271 | { | |
4272 | ++len; | |
4273 | ++format; | |
4274 | } | |
4275 | else | |
4276 | { | |
4277 | arg = strtol (format + 1, &send, 10); | |
db557034 | 4278 | know (send != format && arg < count); |
252b5132 RH |
4279 | len += strlen (operands[arg]); |
4280 | format = send; | |
4281 | } | |
4282 | } | |
4283 | ||
4284 | /* Put the string together. */ | |
325801bd | 4285 | complete = s = XNEWVEC (char, len + 1); |
252b5132 RH |
4286 | format = macro->format; |
4287 | while (*format != '\0') | |
4288 | { | |
4289 | if (*format != '%') | |
4290 | *s++ = *format++; | |
4291 | else | |
4292 | { | |
4293 | arg = strtol (format + 1, &send, 10); | |
4294 | strcpy (s, operands[arg]); | |
4295 | s += strlen (s); | |
4296 | format = send; | |
4297 | } | |
4298 | } | |
4299 | *s = '\0'; | |
4300 | ||
4301 | /* Assemble the constructed instruction. */ | |
4302 | md_assemble (complete); | |
e1fa0163 | 4303 | free (complete); |
81d4177b | 4304 | } |
252b5132 RH |
4305 | \f |
4306 | #ifdef OBJ_ELF | |
18ae9cc1 | 4307 | /* For ELF, add support for SHT_ORDERED. */ |
252b5132 RH |
4308 | |
4309 | int | |
98027b10 | 4310 | ppc_section_type (char *str, size_t len) |
252b5132 | 4311 | { |
9de8d8f1 RH |
4312 | if (len == 7 && strncmp (str, "ordered", 7) == 0) |
4313 | return SHT_ORDERED; | |
252b5132 | 4314 | |
9de8d8f1 | 4315 | return -1; |
252b5132 RH |
4316 | } |
4317 | ||
4318 | int | |
1239de13 | 4319 | ppc_section_flags (flagword flags, bfd_vma attr ATTRIBUTE_UNUSED, int type) |
252b5132 RH |
4320 | { |
4321 | if (type == SHT_ORDERED) | |
4322 | flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES; | |
4323 | ||
252b5132 RH |
4324 | return flags; |
4325 | } | |
83eef883 AFB |
4326 | |
4327 | bfd_vma | |
4328 | ppc_elf_section_letter (int letter, const char **ptrmsg) | |
4329 | { | |
4330 | if (letter == 'v') | |
4331 | return SHF_PPC_VLE; | |
4332 | ||
4333 | *ptrmsg = _("bad .section directive: want a,e,v,w,x,M,S,G,T in string"); | |
4334 | return -1; | |
4335 | } | |
252b5132 RH |
4336 | #endif /* OBJ_ELF */ |
4337 | ||
4338 | \f | |
4339 | /* Pseudo-op handling. */ | |
4340 | ||
4341 | /* The .byte pseudo-op. This is similar to the normal .byte | |
4342 | pseudo-op, but it can also take a single ASCII string. */ | |
4343 | ||
4344 | static void | |
98027b10 | 4345 | ppc_byte (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 4346 | { |
bf7279d5 AM |
4347 | int count = 0; |
4348 | ||
252b5132 RH |
4349 | if (*input_line_pointer != '\"') |
4350 | { | |
4351 | cons (1); | |
4352 | return; | |
4353 | } | |
4354 | ||
4355 | /* Gather characters. A real double quote is doubled. Unusual | |
4356 | characters are not permitted. */ | |
4357 | ++input_line_pointer; | |
4358 | while (1) | |
4359 | { | |
4360 | char c; | |
4361 | ||
4362 | c = *input_line_pointer++; | |
4363 | ||
4364 | if (c == '\"') | |
4365 | { | |
4366 | if (*input_line_pointer != '\"') | |
4367 | break; | |
4368 | ++input_line_pointer; | |
4369 | } | |
4370 | ||
4371 | FRAG_APPEND_1_CHAR (c); | |
bf7279d5 | 4372 | ++count; |
252b5132 RH |
4373 | } |
4374 | ||
bf7279d5 AM |
4375 | if (warn_476 && count != 0 && (now_seg->flags & SEC_CODE) != 0) |
4376 | as_warn (_("data in executable section")); | |
252b5132 RH |
4377 | demand_empty_rest_of_line (); |
4378 | } | |
4379 | \f | |
4380 | #ifdef OBJ_XCOFF | |
4381 | ||
4382 | /* XCOFF specific pseudo-op handling. */ | |
4383 | ||
4384 | /* This is set if we are creating a .stabx symbol, since we don't want | |
4385 | to handle symbol suffixes for such symbols. */ | |
b34976b6 | 4386 | static bfd_boolean ppc_stab_symbol; |
252b5132 RH |
4387 | |
4388 | /* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common | |
4389 | symbols in the .bss segment as though they were local common | |
67c1ffbe | 4390 | symbols, and uses a different smclas. The native Aix 4.3.3 assembler |
1ad63b2f | 4391 | aligns .comm and .lcomm to 4 bytes. */ |
252b5132 RH |
4392 | |
4393 | static void | |
98027b10 | 4394 | ppc_comm (int lcomm) |
252b5132 RH |
4395 | { |
4396 | asection *current_seg = now_seg; | |
4397 | subsegT current_subseg = now_subseg; | |
4398 | char *name; | |
4399 | char endc; | |
4400 | char *end_name; | |
4401 | offsetT size; | |
4402 | offsetT align; | |
4403 | symbolS *lcomm_sym = NULL; | |
4404 | symbolS *sym; | |
4405 | char *pfrag; | |
4406 | ||
d02603dc | 4407 | endc = get_symbol_name (&name); |
252b5132 | 4408 | end_name = input_line_pointer; |
d02603dc | 4409 | (void) restore_line_pointer (endc); |
252b5132 RH |
4410 | |
4411 | if (*input_line_pointer != ',') | |
4412 | { | |
4413 | as_bad (_("missing size")); | |
4414 | ignore_rest_of_line (); | |
4415 | return; | |
4416 | } | |
4417 | ++input_line_pointer; | |
4418 | ||
4419 | size = get_absolute_expression (); | |
4420 | if (size < 0) | |
4421 | { | |
4422 | as_bad (_("negative size")); | |
4423 | ignore_rest_of_line (); | |
4424 | return; | |
4425 | } | |
4426 | ||
4427 | if (! lcomm) | |
4428 | { | |
4429 | /* The third argument to .comm is the alignment. */ | |
4430 | if (*input_line_pointer != ',') | |
1ad63b2f | 4431 | align = 2; |
252b5132 RH |
4432 | else |
4433 | { | |
4434 | ++input_line_pointer; | |
4435 | align = get_absolute_expression (); | |
4436 | if (align <= 0) | |
4437 | { | |
4438 | as_warn (_("ignoring bad alignment")); | |
1ad63b2f | 4439 | align = 2; |
252b5132 RH |
4440 | } |
4441 | } | |
4442 | } | |
4443 | else | |
4444 | { | |
4445 | char *lcomm_name; | |
4446 | char lcomm_endc; | |
4447 | ||
252b5132 RH |
4448 | /* The third argument to .lcomm appears to be the real local |
4449 | common symbol to create. References to the symbol named in | |
4450 | the first argument are turned into references to the third | |
4451 | argument. */ | |
4452 | if (*input_line_pointer != ',') | |
4453 | { | |
4454 | as_bad (_("missing real symbol name")); | |
4455 | ignore_rest_of_line (); | |
4456 | return; | |
4457 | } | |
4458 | ++input_line_pointer; | |
4459 | ||
d02603dc | 4460 | lcomm_endc = get_symbol_name (&lcomm_name); |
81d4177b | 4461 | |
252b5132 RH |
4462 | lcomm_sym = symbol_find_or_make (lcomm_name); |
4463 | ||
d02603dc | 4464 | (void) restore_line_pointer (lcomm_endc); |
3c02c47f DE |
4465 | |
4466 | /* The fourth argument to .lcomm is the alignment. */ | |
4467 | if (*input_line_pointer != ',') | |
4468 | { | |
4469 | if (size <= 4) | |
4470 | align = 2; | |
4471 | else | |
4472 | align = 3; | |
4473 | } | |
4474 | else | |
4475 | { | |
4476 | ++input_line_pointer; | |
4477 | align = get_absolute_expression (); | |
4478 | if (align <= 0) | |
4479 | { | |
4480 | as_warn (_("ignoring bad alignment")); | |
4481 | align = 2; | |
4482 | } | |
4483 | } | |
252b5132 RH |
4484 | } |
4485 | ||
4486 | *end_name = '\0'; | |
4487 | sym = symbol_find_or_make (name); | |
4488 | *end_name = endc; | |
4489 | ||
4490 | if (S_IS_DEFINED (sym) | |
4491 | || S_GET_VALUE (sym) != 0) | |
4492 | { | |
4493 | as_bad (_("attempt to redefine symbol")); | |
4494 | ignore_rest_of_line (); | |
4495 | return; | |
4496 | } | |
81d4177b | 4497 | |
252b5132 | 4498 | record_alignment (bss_section, align); |
81d4177b | 4499 | |
252b5132 RH |
4500 | if (! lcomm |
4501 | || ! S_IS_DEFINED (lcomm_sym)) | |
4502 | { | |
4503 | symbolS *def_sym; | |
4504 | offsetT def_size; | |
4505 | ||
4506 | if (! lcomm) | |
4507 | { | |
4508 | def_sym = sym; | |
4509 | def_size = size; | |
4510 | S_SET_EXTERNAL (sym); | |
4511 | } | |
4512 | else | |
4513 | { | |
809ffe0d | 4514 | symbol_get_tc (lcomm_sym)->output = 1; |
252b5132 RH |
4515 | def_sym = lcomm_sym; |
4516 | def_size = 0; | |
4517 | } | |
4518 | ||
4519 | subseg_set (bss_section, 1); | |
4520 | frag_align (align, 0, 0); | |
81d4177b | 4521 | |
809ffe0d | 4522 | symbol_set_frag (def_sym, frag_now); |
252b5132 RH |
4523 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, def_sym, |
4524 | def_size, (char *) NULL); | |
4525 | *pfrag = 0; | |
4526 | S_SET_SEGMENT (def_sym, bss_section); | |
809ffe0d | 4527 | symbol_get_tc (def_sym)->align = align; |
252b5132 RH |
4528 | } |
4529 | else if (lcomm) | |
4530 | { | |
4531 | /* Align the size of lcomm_sym. */ | |
809ffe0d ILT |
4532 | symbol_get_frag (lcomm_sym)->fr_offset = |
4533 | ((symbol_get_frag (lcomm_sym)->fr_offset + (1 << align) - 1) | |
252b5132 | 4534 | &~ ((1 << align) - 1)); |
809ffe0d ILT |
4535 | if (align > symbol_get_tc (lcomm_sym)->align) |
4536 | symbol_get_tc (lcomm_sym)->align = align; | |
252b5132 RH |
4537 | } |
4538 | ||
4539 | if (lcomm) | |
4540 | { | |
4541 | /* Make sym an offset from lcomm_sym. */ | |
4542 | S_SET_SEGMENT (sym, bss_section); | |
809ffe0d ILT |
4543 | symbol_set_frag (sym, symbol_get_frag (lcomm_sym)); |
4544 | S_SET_VALUE (sym, symbol_get_frag (lcomm_sym)->fr_offset); | |
4545 | symbol_get_frag (lcomm_sym)->fr_offset += size; | |
252b5132 RH |
4546 | } |
4547 | ||
4548 | subseg_set (current_seg, current_subseg); | |
4549 | ||
4550 | demand_empty_rest_of_line (); | |
4551 | } | |
4552 | ||
4553 | /* The .csect pseudo-op. This switches us into a different | |
4554 | subsegment. The first argument is a symbol whose value is the | |
4555 | start of the .csect. In COFF, csect symbols get special aux | |
4556 | entries defined by the x_csect field of union internal_auxent. The | |
4557 | optional second argument is the alignment (the default is 2). */ | |
4558 | ||
4559 | static void | |
98027b10 | 4560 | ppc_csect (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4561 | { |
4562 | char *name; | |
4563 | char endc; | |
4564 | symbolS *sym; | |
931e13a6 | 4565 | offsetT align; |
252b5132 | 4566 | |
d02603dc | 4567 | endc = get_symbol_name (&name); |
81d4177b | 4568 | |
252b5132 RH |
4569 | sym = symbol_find_or_make (name); |
4570 | ||
d02603dc | 4571 | (void) restore_line_pointer (endc); |
252b5132 RH |
4572 | |
4573 | if (S_GET_NAME (sym)[0] == '\0') | |
4574 | { | |
4575 | /* An unnamed csect is assumed to be [PR]. */ | |
96d56e9f | 4576 | symbol_get_tc (sym)->symbol_class = XMC_PR; |
252b5132 RH |
4577 | } |
4578 | ||
931e13a6 | 4579 | align = 2; |
252b5132 RH |
4580 | if (*input_line_pointer == ',') |
4581 | { | |
4582 | ++input_line_pointer; | |
931e13a6 | 4583 | align = get_absolute_expression (); |
252b5132 RH |
4584 | } |
4585 | ||
931e13a6 AM |
4586 | ppc_change_csect (sym, align); |
4587 | ||
252b5132 RH |
4588 | demand_empty_rest_of_line (); |
4589 | } | |
4590 | ||
4591 | /* Change to a different csect. */ | |
4592 | ||
4593 | static void | |
98027b10 | 4594 | ppc_change_csect (symbolS *sym, offsetT align) |
252b5132 RH |
4595 | { |
4596 | if (S_IS_DEFINED (sym)) | |
809ffe0d | 4597 | subseg_set (S_GET_SEGMENT (sym), symbol_get_tc (sym)->subseg); |
252b5132 RH |
4598 | else |
4599 | { | |
4600 | symbolS **list_ptr; | |
4601 | int after_toc; | |
4602 | int hold_chunksize; | |
4603 | symbolS *list; | |
931e13a6 AM |
4604 | int is_code; |
4605 | segT sec; | |
252b5132 RH |
4606 | |
4607 | /* This is a new csect. We need to look at the symbol class to | |
4608 | figure out whether it should go in the text section or the | |
4609 | data section. */ | |
4610 | after_toc = 0; | |
931e13a6 | 4611 | is_code = 0; |
96d56e9f | 4612 | switch (symbol_get_tc (sym)->symbol_class) |
252b5132 RH |
4613 | { |
4614 | case XMC_PR: | |
4615 | case XMC_RO: | |
4616 | case XMC_DB: | |
4617 | case XMC_GL: | |
4618 | case XMC_XO: | |
4619 | case XMC_SV: | |
4620 | case XMC_TI: | |
4621 | case XMC_TB: | |
4622 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 4623 | symbol_get_tc (sym)->subseg = ppc_text_subsegment; |
252b5132 RH |
4624 | ++ppc_text_subsegment; |
4625 | list_ptr = &ppc_text_csects; | |
931e13a6 | 4626 | is_code = 1; |
252b5132 RH |
4627 | break; |
4628 | case XMC_RW: | |
4629 | case XMC_TC0: | |
4630 | case XMC_TC: | |
4631 | case XMC_DS: | |
4632 | case XMC_UA: | |
4633 | case XMC_BS: | |
4634 | case XMC_UC: | |
4635 | if (ppc_toc_csect != NULL | |
809ffe0d ILT |
4636 | && (symbol_get_tc (ppc_toc_csect)->subseg + 1 |
4637 | == ppc_data_subsegment)) | |
252b5132 RH |
4638 | after_toc = 1; |
4639 | S_SET_SEGMENT (sym, data_section); | |
809ffe0d | 4640 | symbol_get_tc (sym)->subseg = ppc_data_subsegment; |
252b5132 RH |
4641 | ++ppc_data_subsegment; |
4642 | list_ptr = &ppc_data_csects; | |
4643 | break; | |
4644 | default: | |
4645 | abort (); | |
4646 | } | |
4647 | ||
4648 | /* We set the obstack chunk size to a small value before | |
99a814a1 AM |
4649 | changing subsegments, so that we don't use a lot of memory |
4650 | space for what may be a small section. */ | |
252b5132 RH |
4651 | hold_chunksize = chunksize; |
4652 | chunksize = 64; | |
4653 | ||
931e13a6 AM |
4654 | sec = subseg_new (segment_name (S_GET_SEGMENT (sym)), |
4655 | symbol_get_tc (sym)->subseg); | |
252b5132 RH |
4656 | |
4657 | chunksize = hold_chunksize; | |
4658 | ||
4659 | if (after_toc) | |
4660 | ppc_after_toc_frag = frag_now; | |
4661 | ||
931e13a6 AM |
4662 | record_alignment (sec, align); |
4663 | if (is_code) | |
4664 | frag_align_code (align, 0); | |
4665 | else | |
4666 | frag_align (align, 0, 0); | |
4667 | ||
809ffe0d | 4668 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
4669 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
4670 | ||
931e13a6 | 4671 | symbol_get_tc (sym)->align = align; |
809ffe0d ILT |
4672 | symbol_get_tc (sym)->output = 1; |
4673 | symbol_get_tc (sym)->within = sym; | |
81d4177b | 4674 | |
252b5132 | 4675 | for (list = *list_ptr; |
809ffe0d ILT |
4676 | symbol_get_tc (list)->next != (symbolS *) NULL; |
4677 | list = symbol_get_tc (list)->next) | |
252b5132 | 4678 | ; |
809ffe0d | 4679 | symbol_get_tc (list)->next = sym; |
81d4177b | 4680 | |
252b5132 | 4681 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); |
809ffe0d ILT |
4682 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
4683 | &symbol_lastP); | |
252b5132 RH |
4684 | } |
4685 | ||
4686 | ppc_current_csect = sym; | |
4687 | } | |
4688 | ||
85645aed TG |
4689 | static void |
4690 | ppc_change_debug_section (unsigned int idx, subsegT subseg) | |
4691 | { | |
4692 | segT sec; | |
4693 | flagword oldflags; | |
4694 | const struct xcoff_dwsect_name *dw = &xcoff_dwsect_names[idx]; | |
4695 | ||
4696 | sec = subseg_new (dw->name, subseg); | |
fd361982 | 4697 | oldflags = bfd_section_flags (sec); |
85645aed TG |
4698 | if (oldflags == SEC_NO_FLAGS) |
4699 | { | |
4700 | /* Just created section. */ | |
4701 | gas_assert (dw_sections[idx].sect == NULL); | |
4702 | ||
fd361982 AM |
4703 | bfd_set_section_flags (sec, SEC_DEBUGGING); |
4704 | bfd_set_section_alignment (sec, 0); | |
85645aed TG |
4705 | dw_sections[idx].sect = sec; |
4706 | } | |
4707 | ||
4708 | /* Not anymore in a csect. */ | |
4709 | ppc_current_csect = NULL; | |
4710 | } | |
4711 | ||
4712 | /* The .dwsect pseudo-op. Defines a DWARF section. Syntax is: | |
4713 | .dwsect flag [, opt-label ] | |
4714 | */ | |
4715 | ||
4716 | static void | |
4717 | ppc_dwsect (int ignore ATTRIBUTE_UNUSED) | |
4718 | { | |
16de26a6 | 4719 | valueT flag; |
85645aed TG |
4720 | symbolS *opt_label; |
4721 | const struct xcoff_dwsect_name *dw; | |
4722 | struct dw_subsection *subseg; | |
4723 | struct dw_section *dws; | |
4724 | int i; | |
4725 | ||
4726 | /* Find section. */ | |
4727 | flag = get_absolute_expression (); | |
4728 | dw = NULL; | |
4729 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
4730 | if (xcoff_dwsect_names[i].flag == flag) | |
4731 | { | |
4732 | dw = &xcoff_dwsect_names[i]; | |
4733 | break; | |
4734 | } | |
4735 | ||
4736 | /* Parse opt-label. */ | |
4737 | if (*input_line_pointer == ',') | |
4738 | { | |
d02603dc | 4739 | char *label; |
85645aed TG |
4740 | char c; |
4741 | ||
4742 | ++input_line_pointer; | |
4743 | ||
d02603dc | 4744 | c = get_symbol_name (&label); |
85645aed | 4745 | opt_label = symbol_find_or_make (label); |
d02603dc | 4746 | (void) restore_line_pointer (c); |
85645aed TG |
4747 | } |
4748 | else | |
4749 | opt_label = NULL; | |
4750 | ||
4751 | demand_empty_rest_of_line (); | |
4752 | ||
4753 | /* Return now in case of unknown subsection. */ | |
4754 | if (dw == NULL) | |
4755 | { | |
d6ed37ed | 4756 | as_bad (_("no known dwarf XCOFF section for flag 0x%08x\n"), |
85645aed TG |
4757 | (unsigned)flag); |
4758 | return; | |
4759 | } | |
4760 | ||
4761 | /* Find the subsection. */ | |
4762 | dws = &dw_sections[i]; | |
4763 | subseg = NULL; | |
4764 | if (opt_label != NULL && S_IS_DEFINED (opt_label)) | |
4765 | { | |
4766 | /* Sanity check (note that in theory S_GET_SEGMENT mustn't be null). */ | |
4767 | if (dws->sect == NULL || S_GET_SEGMENT (opt_label) != dws->sect) | |
4768 | { | |
4769 | as_bad (_("label %s was not defined in this dwarf section"), | |
4770 | S_GET_NAME (opt_label)); | |
4771 | subseg = dws->anon_subseg; | |
4772 | opt_label = NULL; | |
4773 | } | |
4774 | else | |
4775 | subseg = symbol_get_tc (opt_label)->u.dw; | |
4776 | } | |
4777 | ||
4778 | if (subseg != NULL) | |
4779 | { | |
4780 | /* Switch to the subsection. */ | |
4781 | ppc_change_debug_section (i, subseg->subseg); | |
4782 | } | |
4783 | else | |
4784 | { | |
4785 | /* Create a new dw subsection. */ | |
325801bd | 4786 | subseg = XNEW (struct dw_subsection); |
85645aed TG |
4787 | |
4788 | if (opt_label == NULL) | |
4789 | { | |
4790 | /* The anonymous one. */ | |
4791 | subseg->subseg = 0; | |
4792 | subseg->link = NULL; | |
4793 | dws->anon_subseg = subseg; | |
4794 | } | |
4795 | else | |
4796 | { | |
4797 | /* A named one. */ | |
4798 | if (dws->list_subseg != NULL) | |
4799 | subseg->subseg = dws->list_subseg->subseg + 1; | |
4800 | else | |
4801 | subseg->subseg = 1; | |
4802 | ||
4803 | subseg->link = dws->list_subseg; | |
4804 | dws->list_subseg = subseg; | |
4805 | symbol_get_tc (opt_label)->u.dw = subseg; | |
4806 | } | |
4807 | ||
4808 | ppc_change_debug_section (i, subseg->subseg); | |
4809 | ||
4810 | if (dw->def_size) | |
4811 | { | |
4812 | /* Add the length field. */ | |
4813 | expressionS *exp = &subseg->end_exp; | |
4814 | int sz; | |
4815 | ||
4816 | if (opt_label != NULL) | |
4817 | symbol_set_value_now (opt_label); | |
4818 | ||
4819 | /* Add the length field. Note that according to the AIX assembler | |
4820 | manual, the size of the length field is 4 for powerpc32 but | |
4821 | 12 for powerpc64. */ | |
4822 | if (ppc_obj64) | |
4823 | { | |
4824 | /* Write the 64bit marker. */ | |
4825 | md_number_to_chars (frag_more (4), -1, 4); | |
4826 | } | |
4827 | ||
4828 | exp->X_op = O_subtract; | |
4829 | exp->X_op_symbol = symbol_temp_new_now (); | |
4830 | exp->X_add_symbol = symbol_temp_make (); | |
4831 | ||
4832 | sz = ppc_obj64 ? 8 : 4; | |
4833 | exp->X_add_number = -sz; | |
4834 | emit_expr (exp, sz); | |
4835 | } | |
4836 | } | |
4837 | } | |
4838 | ||
252b5132 RH |
4839 | /* This function handles the .text and .data pseudo-ops. These |
4840 | pseudo-ops aren't really used by XCOFF; we implement them for the | |
4841 | convenience of people who aren't used to XCOFF. */ | |
4842 | ||
4843 | static void | |
98027b10 | 4844 | ppc_section (int type) |
252b5132 RH |
4845 | { |
4846 | const char *name; | |
4847 | symbolS *sym; | |
4848 | ||
4849 | if (type == 't') | |
4850 | name = ".text[PR]"; | |
4851 | else if (type == 'd') | |
4852 | name = ".data[RW]"; | |
4853 | else | |
4854 | abort (); | |
4855 | ||
4856 | sym = symbol_find_or_make (name); | |
4857 | ||
931e13a6 | 4858 | ppc_change_csect (sym, 2); |
252b5132 RH |
4859 | |
4860 | demand_empty_rest_of_line (); | |
4861 | } | |
4862 | ||
4863 | /* This function handles the .section pseudo-op. This is mostly to | |
4864 | give an error, since XCOFF only supports .text, .data and .bss, but | |
4865 | we do permit the user to name the text or data section. */ | |
4866 | ||
4867 | static void | |
98027b10 | 4868 | ppc_named_section (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4869 | { |
4870 | char *user_name; | |
4871 | const char *real_name; | |
4872 | char c; | |
4873 | symbolS *sym; | |
4874 | ||
d02603dc | 4875 | c = get_symbol_name (&user_name); |
252b5132 RH |
4876 | |
4877 | if (strcmp (user_name, ".text") == 0) | |
4878 | real_name = ".text[PR]"; | |
4879 | else if (strcmp (user_name, ".data") == 0) | |
4880 | real_name = ".data[RW]"; | |
4881 | else | |
4882 | { | |
d6ed37ed | 4883 | as_bad (_("the XCOFF file format does not support arbitrary sections")); |
d02603dc | 4884 | (void) restore_line_pointer (c); |
252b5132 RH |
4885 | ignore_rest_of_line (); |
4886 | return; | |
4887 | } | |
4888 | ||
d02603dc | 4889 | (void) restore_line_pointer (c); |
252b5132 RH |
4890 | |
4891 | sym = symbol_find_or_make (real_name); | |
4892 | ||
931e13a6 | 4893 | ppc_change_csect (sym, 2); |
252b5132 RH |
4894 | |
4895 | demand_empty_rest_of_line (); | |
4896 | } | |
4897 | ||
4898 | /* The .extern pseudo-op. We create an undefined symbol. */ | |
4899 | ||
4900 | static void | |
98027b10 | 4901 | ppc_extern (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4902 | { |
4903 | char *name; | |
4904 | char endc; | |
4905 | ||
d02603dc | 4906 | endc = get_symbol_name (&name); |
252b5132 RH |
4907 | |
4908 | (void) symbol_find_or_make (name); | |
4909 | ||
d02603dc | 4910 | (void) restore_line_pointer (endc); |
252b5132 RH |
4911 | |
4912 | demand_empty_rest_of_line (); | |
4913 | } | |
4914 | ||
4915 | /* The .lglobl pseudo-op. Keep the symbol in the symbol table. */ | |
4916 | ||
4917 | static void | |
98027b10 | 4918 | ppc_lglobl (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4919 | { |
4920 | char *name; | |
4921 | char endc; | |
4922 | symbolS *sym; | |
4923 | ||
d02603dc | 4924 | endc = get_symbol_name (&name); |
252b5132 RH |
4925 | |
4926 | sym = symbol_find_or_make (name); | |
4927 | ||
d02603dc | 4928 | (void) restore_line_pointer (endc); |
252b5132 | 4929 | |
809ffe0d | 4930 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
4931 | |
4932 | demand_empty_rest_of_line (); | |
4933 | } | |
4934 | ||
c865e45b RS |
4935 | /* The .ref pseudo-op. It takes a list of symbol names and inserts R_REF |
4936 | relocations at the beginning of the current csect. | |
4937 | ||
4938 | (In principle, there's no reason why the relocations _have_ to be at | |
4939 | the beginning. Anywhere in the csect would do. However, inserting | |
33eaf5de | 4940 | at the beginning is what the native assembler does, and it helps to |
c865e45b RS |
4941 | deal with cases where the .ref statements follow the section contents.) |
4942 | ||
4943 | ??? .refs don't work for empty .csects. However, the native assembler | |
4944 | doesn't report an error in this case, and neither yet do we. */ | |
4945 | ||
4946 | static void | |
4947 | ppc_ref (int ignore ATTRIBUTE_UNUSED) | |
4948 | { | |
4949 | char *name; | |
4950 | char c; | |
4951 | ||
4952 | if (ppc_current_csect == NULL) | |
4953 | { | |
4954 | as_bad (_(".ref outside .csect")); | |
4955 | ignore_rest_of_line (); | |
4956 | return; | |
4957 | } | |
4958 | ||
4959 | do | |
4960 | { | |
d02603dc | 4961 | c = get_symbol_name (&name); |
c865e45b RS |
4962 | |
4963 | fix_at_start (symbol_get_frag (ppc_current_csect), 0, | |
4964 | symbol_find_or_make (name), 0, FALSE, BFD_RELOC_NONE); | |
4965 | ||
4966 | *input_line_pointer = c; | |
d02603dc | 4967 | SKIP_WHITESPACE_AFTER_NAME (); |
c865e45b RS |
4968 | c = *input_line_pointer; |
4969 | if (c == ',') | |
4970 | { | |
4971 | input_line_pointer++; | |
4972 | SKIP_WHITESPACE (); | |
4973 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
4974 | { | |
4975 | as_bad (_("missing symbol name")); | |
4976 | ignore_rest_of_line (); | |
4977 | return; | |
4978 | } | |
4979 | } | |
4980 | } | |
4981 | while (c == ','); | |
4982 | ||
4983 | demand_empty_rest_of_line (); | |
4984 | } | |
4985 | ||
252b5132 RH |
4986 | /* The .rename pseudo-op. The RS/6000 assembler can rename symbols, |
4987 | although I don't know why it bothers. */ | |
4988 | ||
4989 | static void | |
98027b10 | 4990 | ppc_rename (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4991 | { |
4992 | char *name; | |
4993 | char endc; | |
4994 | symbolS *sym; | |
4995 | int len; | |
4996 | ||
d02603dc | 4997 | endc = get_symbol_name (&name); |
252b5132 RH |
4998 | |
4999 | sym = symbol_find_or_make (name); | |
5000 | ||
d02603dc | 5001 | (void) restore_line_pointer (endc); |
252b5132 RH |
5002 | |
5003 | if (*input_line_pointer != ',') | |
5004 | { | |
5005 | as_bad (_("missing rename string")); | |
5006 | ignore_rest_of_line (); | |
5007 | return; | |
5008 | } | |
5009 | ++input_line_pointer; | |
5010 | ||
809ffe0d | 5011 | symbol_get_tc (sym)->real_name = demand_copy_C_string (&len); |
252b5132 RH |
5012 | |
5013 | demand_empty_rest_of_line (); | |
5014 | } | |
5015 | ||
5016 | /* The .stabx pseudo-op. This is similar to a normal .stabs | |
5017 | pseudo-op, but slightly different. A sample is | |
5018 | .stabx "main:F-1",.main,142,0 | |
5019 | The first argument is the symbol name to create. The second is the | |
5020 | value, and the third is the storage class. The fourth seems to be | |
5021 | always zero, and I am assuming it is the type. */ | |
5022 | ||
5023 | static void | |
98027b10 | 5024 | ppc_stabx (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5025 | { |
5026 | char *name; | |
5027 | int len; | |
5028 | symbolS *sym; | |
5029 | expressionS exp; | |
5030 | ||
5031 | name = demand_copy_C_string (&len); | |
5032 | ||
5033 | if (*input_line_pointer != ',') | |
5034 | { | |
5035 | as_bad (_("missing value")); | |
5036 | return; | |
5037 | } | |
5038 | ++input_line_pointer; | |
5039 | ||
b34976b6 | 5040 | ppc_stab_symbol = TRUE; |
252b5132 | 5041 | sym = symbol_make (name); |
b34976b6 | 5042 | ppc_stab_symbol = FALSE; |
252b5132 | 5043 | |
809ffe0d | 5044 | symbol_get_tc (sym)->real_name = name; |
252b5132 RH |
5045 | |
5046 | (void) expression (&exp); | |
5047 | ||
5048 | switch (exp.X_op) | |
5049 | { | |
5050 | case O_illegal: | |
5051 | case O_absent: | |
5052 | case O_big: | |
5053 | as_bad (_("illegal .stabx expression; zero assumed")); | |
5054 | exp.X_add_number = 0; | |
5055 | /* Fall through. */ | |
5056 | case O_constant: | |
5057 | S_SET_VALUE (sym, (valueT) exp.X_add_number); | |
809ffe0d | 5058 | symbol_set_frag (sym, &zero_address_frag); |
252b5132 RH |
5059 | break; |
5060 | ||
5061 | case O_symbol: | |
5062 | if (S_GET_SEGMENT (exp.X_add_symbol) == undefined_section) | |
809ffe0d | 5063 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
5064 | else |
5065 | { | |
5066 | S_SET_VALUE (sym, | |
5067 | exp.X_add_number + S_GET_VALUE (exp.X_add_symbol)); | |
809ffe0d | 5068 | symbol_set_frag (sym, symbol_get_frag (exp.X_add_symbol)); |
252b5132 RH |
5069 | } |
5070 | break; | |
5071 | ||
5072 | default: | |
5073 | /* The value is some complex expression. This will probably | |
99a814a1 AM |
5074 | fail at some later point, but this is probably the right |
5075 | thing to do here. */ | |
809ffe0d | 5076 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
5077 | break; |
5078 | } | |
5079 | ||
5080 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5081 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5082 | |
5083 | if (*input_line_pointer != ',') | |
5084 | { | |
5085 | as_bad (_("missing class")); | |
5086 | return; | |
5087 | } | |
5088 | ++input_line_pointer; | |
5089 | ||
5090 | S_SET_STORAGE_CLASS (sym, get_absolute_expression ()); | |
5091 | ||
5092 | if (*input_line_pointer != ',') | |
5093 | { | |
5094 | as_bad (_("missing type")); | |
5095 | return; | |
5096 | } | |
5097 | ++input_line_pointer; | |
5098 | ||
5099 | S_SET_DATA_TYPE (sym, get_absolute_expression ()); | |
5100 | ||
809ffe0d | 5101 | symbol_get_tc (sym)->output = 1; |
252b5132 | 5102 | |
c734e7e3 TG |
5103 | if (S_GET_STORAGE_CLASS (sym) == C_STSYM) |
5104 | { | |
5105 | /* In this case : | |
252b5132 | 5106 | |
c734e7e3 TG |
5107 | .bs name |
5108 | .stabx "z",arrays_,133,0 | |
5109 | .es | |
99a814a1 | 5110 | |
c734e7e3 | 5111 | .comm arrays_,13768,3 |
99a814a1 | 5112 | |
c734e7e3 TG |
5113 | resolve_symbol_value will copy the exp's "within" into sym's when the |
5114 | offset is 0. Since this seems to be corner case problem, | |
5115 | only do the correction for storage class C_STSYM. A better solution | |
5116 | would be to have the tc field updated in ppc_symbol_new_hook. */ | |
99a814a1 | 5117 | |
c734e7e3 TG |
5118 | if (exp.X_op == O_symbol) |
5119 | { | |
5120 | if (ppc_current_block == NULL) | |
5121 | as_bad (_(".stabx of storage class stsym must be within .bs/.es")); | |
99a814a1 | 5122 | |
c734e7e3 TG |
5123 | symbol_get_tc (sym)->within = ppc_current_block; |
5124 | symbol_get_tc (exp.X_add_symbol)->within = ppc_current_block; | |
5125 | } | |
5126 | } | |
99a814a1 | 5127 | |
252b5132 RH |
5128 | if (exp.X_op != O_symbol |
5129 | || ! S_IS_EXTERNAL (exp.X_add_symbol) | |
5130 | || S_GET_SEGMENT (exp.X_add_symbol) != bss_section) | |
5131 | ppc_frob_label (sym); | |
5132 | else | |
5133 | { | |
5134 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
5135 | symbol_append (sym, exp.X_add_symbol, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
5136 | if (symbol_get_tc (ppc_current_csect)->within == exp.X_add_symbol) |
5137 | symbol_get_tc (ppc_current_csect)->within = sym; | |
252b5132 RH |
5138 | } |
5139 | ||
5140 | demand_empty_rest_of_line (); | |
5141 | } | |
5142 | ||
5143 | /* The .function pseudo-op. This takes several arguments. The first | |
5144 | argument seems to be the external name of the symbol. The second | |
67c1ffbe | 5145 | argument seems to be the label for the start of the function. gcc |
252b5132 RH |
5146 | uses the same name for both. I have no idea what the third and |
5147 | fourth arguments are meant to be. The optional fifth argument is | |
5148 | an expression for the size of the function. In COFF this symbol | |
5149 | gets an aux entry like that used for a csect. */ | |
5150 | ||
5151 | static void | |
98027b10 | 5152 | ppc_function (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5153 | { |
5154 | char *name; | |
5155 | char endc; | |
5156 | char *s; | |
5157 | symbolS *ext_sym; | |
5158 | symbolS *lab_sym; | |
5159 | ||
d02603dc | 5160 | endc = get_symbol_name (&name); |
252b5132 RH |
5161 | |
5162 | /* Ignore any [PR] suffix. */ | |
5163 | name = ppc_canonicalize_symbol_name (name); | |
5164 | s = strchr (name, '['); | |
5165 | if (s != (char *) NULL | |
5166 | && strcmp (s + 1, "PR]") == 0) | |
5167 | *s = '\0'; | |
5168 | ||
5169 | ext_sym = symbol_find_or_make (name); | |
5170 | ||
d02603dc | 5171 | (void) restore_line_pointer (endc); |
252b5132 RH |
5172 | |
5173 | if (*input_line_pointer != ',') | |
5174 | { | |
5175 | as_bad (_("missing symbol name")); | |
5176 | ignore_rest_of_line (); | |
5177 | return; | |
5178 | } | |
5179 | ++input_line_pointer; | |
5180 | ||
d02603dc | 5181 | endc = get_symbol_name (&name); |
252b5132 RH |
5182 | |
5183 | lab_sym = symbol_find_or_make (name); | |
5184 | ||
d02603dc | 5185 | (void) restore_line_pointer (endc); |
252b5132 RH |
5186 | |
5187 | if (ext_sym != lab_sym) | |
5188 | { | |
809ffe0d ILT |
5189 | expressionS exp; |
5190 | ||
5191 | exp.X_op = O_symbol; | |
5192 | exp.X_add_symbol = lab_sym; | |
5193 | exp.X_op_symbol = NULL; | |
5194 | exp.X_add_number = 0; | |
5195 | exp.X_unsigned = 0; | |
5196 | symbol_set_value_expression (ext_sym, &exp); | |
252b5132 RH |
5197 | } |
5198 | ||
96d56e9f NC |
5199 | if (symbol_get_tc (ext_sym)->symbol_class == -1) |
5200 | symbol_get_tc (ext_sym)->symbol_class = XMC_PR; | |
809ffe0d | 5201 | symbol_get_tc (ext_sym)->output = 1; |
252b5132 RH |
5202 | |
5203 | if (*input_line_pointer == ',') | |
5204 | { | |
91d6fa6a | 5205 | expressionS exp; |
252b5132 RH |
5206 | |
5207 | /* Ignore the third argument. */ | |
5208 | ++input_line_pointer; | |
91d6fa6a | 5209 | expression (& exp); |
252b5132 RH |
5210 | if (*input_line_pointer == ',') |
5211 | { | |
5212 | /* Ignore the fourth argument. */ | |
5213 | ++input_line_pointer; | |
91d6fa6a | 5214 | expression (& exp); |
252b5132 RH |
5215 | if (*input_line_pointer == ',') |
5216 | { | |
5217 | /* The fifth argument is the function size. */ | |
5218 | ++input_line_pointer; | |
85645aed TG |
5219 | symbol_get_tc (ext_sym)->u.size = symbol_new |
5220 | ("L0\001", absolute_section,(valueT) 0, &zero_address_frag); | |
5221 | pseudo_set (symbol_get_tc (ext_sym)->u.size); | |
252b5132 RH |
5222 | } |
5223 | } | |
5224 | } | |
5225 | ||
5226 | S_SET_DATA_TYPE (ext_sym, DT_FCN << N_BTSHFT); | |
5227 | SF_SET_FUNCTION (ext_sym); | |
5228 | SF_SET_PROCESS (ext_sym); | |
5229 | coff_add_linesym (ext_sym); | |
5230 | ||
5231 | demand_empty_rest_of_line (); | |
5232 | } | |
5233 | ||
5234 | /* The .bf pseudo-op. This is just like a COFF C_FCN symbol named | |
8642cce8 TR |
5235 | ".bf". If the pseudo op .bi was seen before .bf, patch the .bi sym |
5236 | with the correct line number */ | |
5d6255fe | 5237 | |
8642cce8 | 5238 | static symbolS *saved_bi_sym = 0; |
252b5132 RH |
5239 | |
5240 | static void | |
98027b10 | 5241 | ppc_bf (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5242 | { |
5243 | symbolS *sym; | |
5244 | ||
5245 | sym = symbol_make (".bf"); | |
5246 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5247 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5248 | S_SET_VALUE (sym, frag_now_fix ()); |
5249 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
5250 | ||
5251 | coff_line_base = get_absolute_expression (); | |
5252 | ||
5253 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5254 | SA_SET_SYM_LNNO (sym, coff_line_base); | |
5255 | ||
8642cce8 | 5256 | /* Line number for bi. */ |
5d6255fe | 5257 | if (saved_bi_sym) |
8642cce8 TR |
5258 | { |
5259 | S_SET_VALUE (saved_bi_sym, coff_n_line_nos); | |
5260 | saved_bi_sym = 0; | |
5261 | } | |
5d6255fe | 5262 | |
8642cce8 | 5263 | |
809ffe0d | 5264 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5265 | |
5266 | ppc_frob_label (sym); | |
5267 | ||
5268 | demand_empty_rest_of_line (); | |
5269 | } | |
5270 | ||
5271 | /* The .ef pseudo-op. This is just like a COFF C_FCN symbol named | |
5272 | ".ef", except that the line number is absolute, not relative to the | |
5273 | most recent ".bf" symbol. */ | |
5274 | ||
5275 | static void | |
98027b10 | 5276 | ppc_ef (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5277 | { |
5278 | symbolS *sym; | |
5279 | ||
5280 | sym = symbol_make (".ef"); | |
5281 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5282 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5283 | S_SET_VALUE (sym, frag_now_fix ()); |
5284 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
5285 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5286 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 5287 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5288 | |
5289 | ppc_frob_label (sym); | |
5290 | ||
5291 | demand_empty_rest_of_line (); | |
5292 | } | |
5293 | ||
5294 | /* The .bi and .ei pseudo-ops. These take a string argument and | |
5295 | generates a C_BINCL or C_EINCL symbol, which goes at the start of | |
8642cce8 TR |
5296 | the symbol list. The value of .bi will be know when the next .bf |
5297 | is encountered. */ | |
252b5132 RH |
5298 | |
5299 | static void | |
98027b10 | 5300 | ppc_biei (int ei) |
252b5132 RH |
5301 | { |
5302 | static symbolS *last_biei; | |
5303 | ||
5304 | char *name; | |
5305 | int len; | |
5306 | symbolS *sym; | |
5307 | symbolS *look; | |
5308 | ||
5309 | name = demand_copy_C_string (&len); | |
5310 | ||
5311 | /* The value of these symbols is actually file offset. Here we set | |
5312 | the value to the index into the line number entries. In | |
5313 | ppc_frob_symbols we set the fix_line field, which will cause BFD | |
5314 | to do the right thing. */ | |
5315 | ||
5316 | sym = symbol_make (name); | |
5317 | /* obj-coff.c currently only handles line numbers correctly in the | |
5318 | .text section. */ | |
5319 | S_SET_SEGMENT (sym, text_section); | |
5320 | S_SET_VALUE (sym, coff_n_line_nos); | |
809ffe0d | 5321 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5322 | |
5323 | S_SET_STORAGE_CLASS (sym, ei ? C_EINCL : C_BINCL); | |
809ffe0d | 5324 | symbol_get_tc (sym)->output = 1; |
81d4177b | 5325 | |
8642cce8 | 5326 | /* Save bi. */ |
5d6255fe | 5327 | if (ei) |
8642cce8 TR |
5328 | saved_bi_sym = 0; |
5329 | else | |
5330 | saved_bi_sym = sym; | |
5331 | ||
252b5132 RH |
5332 | for (look = last_biei ? last_biei : symbol_rootP; |
5333 | (look != (symbolS *) NULL | |
5334 | && (S_GET_STORAGE_CLASS (look) == C_FILE | |
5335 | || S_GET_STORAGE_CLASS (look) == C_BINCL | |
5336 | || S_GET_STORAGE_CLASS (look) == C_EINCL)); | |
5337 | look = symbol_next (look)) | |
5338 | ; | |
5339 | if (look != (symbolS *) NULL) | |
5340 | { | |
5341 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
5342 | symbol_insert (sym, look, &symbol_rootP, &symbol_lastP); | |
5343 | last_biei = sym; | |
5344 | } | |
5345 | ||
5346 | demand_empty_rest_of_line (); | |
5347 | } | |
5348 | ||
5349 | /* The .bs pseudo-op. This generates a C_BSTAT symbol named ".bs". | |
5350 | There is one argument, which is a csect symbol. The value of the | |
5351 | .bs symbol is the index of this csect symbol. */ | |
5352 | ||
5353 | static void | |
98027b10 | 5354 | ppc_bs (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5355 | { |
5356 | char *name; | |
5357 | char endc; | |
5358 | symbolS *csect; | |
5359 | symbolS *sym; | |
5360 | ||
5361 | if (ppc_current_block != NULL) | |
5362 | as_bad (_("nested .bs blocks")); | |
5363 | ||
d02603dc | 5364 | endc = get_symbol_name (&name); |
252b5132 RH |
5365 | |
5366 | csect = symbol_find_or_make (name); | |
5367 | ||
d02603dc | 5368 | (void) restore_line_pointer (endc); |
252b5132 RH |
5369 | |
5370 | sym = symbol_make (".bs"); | |
5371 | S_SET_SEGMENT (sym, now_seg); | |
5372 | S_SET_STORAGE_CLASS (sym, C_BSTAT); | |
809ffe0d ILT |
5373 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5374 | symbol_get_tc (sym)->output = 1; | |
252b5132 | 5375 | |
809ffe0d | 5376 | symbol_get_tc (sym)->within = csect; |
252b5132 RH |
5377 | |
5378 | ppc_frob_label (sym); | |
5379 | ||
5380 | ppc_current_block = sym; | |
5381 | ||
5382 | demand_empty_rest_of_line (); | |
5383 | } | |
5384 | ||
5385 | /* The .es pseudo-op. Generate a C_ESTART symbol named .es. */ | |
5386 | ||
5387 | static void | |
98027b10 | 5388 | ppc_es (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5389 | { |
5390 | symbolS *sym; | |
5391 | ||
5392 | if (ppc_current_block == NULL) | |
5393 | as_bad (_(".es without preceding .bs")); | |
5394 | ||
5395 | sym = symbol_make (".es"); | |
5396 | S_SET_SEGMENT (sym, now_seg); | |
5397 | S_SET_STORAGE_CLASS (sym, C_ESTAT); | |
809ffe0d ILT |
5398 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5399 | symbol_get_tc (sym)->output = 1; | |
252b5132 RH |
5400 | |
5401 | ppc_frob_label (sym); | |
5402 | ||
5403 | ppc_current_block = NULL; | |
5404 | ||
5405 | demand_empty_rest_of_line (); | |
5406 | } | |
5407 | ||
5408 | /* The .bb pseudo-op. Generate a C_BLOCK symbol named .bb, with a | |
5409 | line number. */ | |
5410 | ||
5411 | static void | |
98027b10 | 5412 | ppc_bb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5413 | { |
5414 | symbolS *sym; | |
5415 | ||
5416 | sym = symbol_make (".bb"); | |
5417 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5418 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5419 | S_SET_VALUE (sym, frag_now_fix ()); |
5420 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5421 | ||
5422 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5423 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
5424 | ||
809ffe0d | 5425 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5426 | |
5427 | SF_SET_PROCESS (sym); | |
5428 | ||
5429 | ppc_frob_label (sym); | |
5430 | ||
5431 | demand_empty_rest_of_line (); | |
5432 | } | |
5433 | ||
5434 | /* The .eb pseudo-op. Generate a C_BLOCK symbol named .eb, with a | |
5435 | line number. */ | |
5436 | ||
5437 | static void | |
98027b10 | 5438 | ppc_eb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5439 | { |
5440 | symbolS *sym; | |
5441 | ||
5442 | sym = symbol_make (".eb"); | |
5443 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5444 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5445 | S_SET_VALUE (sym, frag_now_fix ()); |
5446 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5447 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5448 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 5449 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5450 | |
5451 | SF_SET_PROCESS (sym); | |
5452 | ||
5453 | ppc_frob_label (sym); | |
5454 | ||
5455 | demand_empty_rest_of_line (); | |
5456 | } | |
5457 | ||
5458 | /* The .bc pseudo-op. This just creates a C_BCOMM symbol with a | |
5459 | specified name. */ | |
5460 | ||
5461 | static void | |
98027b10 | 5462 | ppc_bc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5463 | { |
5464 | char *name; | |
5465 | int len; | |
5466 | symbolS *sym; | |
5467 | ||
5468 | name = demand_copy_C_string (&len); | |
5469 | sym = symbol_make (name); | |
5470 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5471 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5472 | S_SET_STORAGE_CLASS (sym, C_BCOMM); |
5473 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5474 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5475 | |
5476 | ppc_frob_label (sym); | |
5477 | ||
5478 | demand_empty_rest_of_line (); | |
5479 | } | |
5480 | ||
5481 | /* The .ec pseudo-op. This just creates a C_ECOMM symbol. */ | |
5482 | ||
5483 | static void | |
98027b10 | 5484 | ppc_ec (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5485 | { |
5486 | symbolS *sym; | |
5487 | ||
5488 | sym = symbol_make (".ec"); | |
5489 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5490 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5491 | S_SET_STORAGE_CLASS (sym, C_ECOMM); |
5492 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5493 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5494 | |
5495 | ppc_frob_label (sym); | |
5496 | ||
5497 | demand_empty_rest_of_line (); | |
5498 | } | |
5499 | ||
5500 | /* The .toc pseudo-op. Switch to the .toc subsegment. */ | |
5501 | ||
5502 | static void | |
98027b10 | 5503 | ppc_toc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5504 | { |
5505 | if (ppc_toc_csect != (symbolS *) NULL) | |
809ffe0d | 5506 | subseg_set (data_section, symbol_get_tc (ppc_toc_csect)->subseg); |
252b5132 RH |
5507 | else |
5508 | { | |
5509 | subsegT subseg; | |
5510 | symbolS *sym; | |
5511 | symbolS *list; | |
81d4177b | 5512 | |
252b5132 RH |
5513 | subseg = ppc_data_subsegment; |
5514 | ++ppc_data_subsegment; | |
5515 | ||
5516 | subseg_new (segment_name (data_section), subseg); | |
5517 | ppc_toc_frag = frag_now; | |
5518 | ||
5519 | sym = symbol_find_or_make ("TOC[TC0]"); | |
809ffe0d | 5520 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5521 | S_SET_SEGMENT (sym, data_section); |
5522 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
809ffe0d ILT |
5523 | symbol_get_tc (sym)->subseg = subseg; |
5524 | symbol_get_tc (sym)->output = 1; | |
5525 | symbol_get_tc (sym)->within = sym; | |
252b5132 RH |
5526 | |
5527 | ppc_toc_csect = sym; | |
81d4177b | 5528 | |
252b5132 | 5529 | for (list = ppc_data_csects; |
809ffe0d ILT |
5530 | symbol_get_tc (list)->next != (symbolS *) NULL; |
5531 | list = symbol_get_tc (list)->next) | |
252b5132 | 5532 | ; |
809ffe0d | 5533 | symbol_get_tc (list)->next = sym; |
252b5132 RH |
5534 | |
5535 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
5536 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
5537 | &symbol_lastP); | |
252b5132 RH |
5538 | } |
5539 | ||
5540 | ppc_current_csect = ppc_toc_csect; | |
5541 | ||
5542 | demand_empty_rest_of_line (); | |
5543 | } | |
5544 | ||
5545 | /* The AIX assembler automatically aligns the operands of a .long or | |
5546 | .short pseudo-op, and we want to be compatible. */ | |
5547 | ||
5548 | static void | |
98027b10 | 5549 | ppc_xcoff_cons (int log_size) |
252b5132 RH |
5550 | { |
5551 | frag_align (log_size, 0, 0); | |
5552 | record_alignment (now_seg, log_size); | |
5553 | cons (1 << log_size); | |
5554 | } | |
5555 | ||
5556 | static void | |
98027b10 | 5557 | ppc_vbyte (int dummy ATTRIBUTE_UNUSED) |
252b5132 RH |
5558 | { |
5559 | expressionS exp; | |
5560 | int byte_count; | |
5561 | ||
5562 | (void) expression (&exp); | |
5563 | ||
5564 | if (exp.X_op != O_constant) | |
5565 | { | |
5566 | as_bad (_("non-constant byte count")); | |
5567 | return; | |
5568 | } | |
5569 | ||
5570 | byte_count = exp.X_add_number; | |
5571 | ||
5572 | if (*input_line_pointer != ',') | |
5573 | { | |
5574 | as_bad (_("missing value")); | |
5575 | return; | |
5576 | } | |
5577 | ||
5578 | ++input_line_pointer; | |
5579 | cons (byte_count); | |
5580 | } | |
5581 | ||
85645aed TG |
5582 | void |
5583 | ppc_xcoff_end (void) | |
5584 | { | |
5585 | int i; | |
5586 | ||
5587 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
5588 | { | |
5589 | struct dw_section *dws = &dw_sections[i]; | |
5590 | struct dw_subsection *dwss; | |
5591 | ||
5592 | if (dws->anon_subseg) | |
5593 | { | |
5594 | dwss = dws->anon_subseg; | |
5595 | dwss->link = dws->list_subseg; | |
5596 | } | |
5597 | else | |
5598 | dwss = dws->list_subseg; | |
5599 | ||
5600 | for (; dwss != NULL; dwss = dwss->link) | |
5601 | if (dwss->end_exp.X_add_symbol != NULL) | |
5602 | { | |
5603 | subseg_set (dws->sect, dwss->subseg); | |
5604 | symbol_set_value_now (dwss->end_exp.X_add_symbol); | |
5605 | } | |
5606 | } | |
22f72c48 | 5607 | ppc_cpu = 0; |
85645aed TG |
5608 | } |
5609 | ||
252b5132 | 5610 | #endif /* OBJ_XCOFF */ |
0baf16f2 | 5611 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 RH |
5612 | \f |
5613 | /* The .tc pseudo-op. This is used when generating either XCOFF or | |
5614 | ELF. This takes two or more arguments. | |
5615 | ||
5616 | When generating XCOFF output, the first argument is the name to | |
5617 | give to this location in the toc; this will be a symbol with class | |
0baf16f2 | 5618 | TC. The rest of the arguments are N-byte values to actually put at |
252b5132 | 5619 | this location in the TOC; often there is just one more argument, a |
1049f94e | 5620 | relocatable symbol reference. The size of the value to store |
0baf16f2 AM |
5621 | depends on target word size. A 32-bit target uses 4-byte values, a |
5622 | 64-bit target uses 8-byte values. | |
252b5132 RH |
5623 | |
5624 | When not generating XCOFF output, the arguments are the same, but | |
5625 | the first argument is simply ignored. */ | |
5626 | ||
5627 | static void | |
98027b10 | 5628 | ppc_tc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5629 | { |
5630 | #ifdef OBJ_XCOFF | |
5631 | ||
5632 | /* Define the TOC symbol name. */ | |
5633 | { | |
5634 | char *name; | |
5635 | char endc; | |
5636 | symbolS *sym; | |
5637 | ||
5638 | if (ppc_toc_csect == (symbolS *) NULL | |
5639 | || ppc_toc_csect != ppc_current_csect) | |
5640 | { | |
5641 | as_bad (_(".tc not in .toc section")); | |
5642 | ignore_rest_of_line (); | |
5643 | return; | |
5644 | } | |
5645 | ||
d02603dc | 5646 | endc = get_symbol_name (&name); |
252b5132 RH |
5647 | |
5648 | sym = symbol_find_or_make (name); | |
5649 | ||
d02603dc | 5650 | (void) restore_line_pointer (endc); |
252b5132 RH |
5651 | |
5652 | if (S_IS_DEFINED (sym)) | |
5653 | { | |
5654 | symbolS *label; | |
5655 | ||
809ffe0d | 5656 | label = symbol_get_tc (ppc_current_csect)->within; |
96d56e9f | 5657 | if (symbol_get_tc (label)->symbol_class != XMC_TC0) |
252b5132 RH |
5658 | { |
5659 | as_bad (_(".tc with no label")); | |
5660 | ignore_rest_of_line (); | |
5661 | return; | |
5662 | } | |
5663 | ||
5664 | S_SET_SEGMENT (label, S_GET_SEGMENT (sym)); | |
809ffe0d | 5665 | symbol_set_frag (label, symbol_get_frag (sym)); |
252b5132 RH |
5666 | S_SET_VALUE (label, S_GET_VALUE (sym)); |
5667 | ||
5668 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5669 | ++input_line_pointer; | |
5670 | ||
5671 | return; | |
5672 | } | |
5673 | ||
5674 | S_SET_SEGMENT (sym, now_seg); | |
809ffe0d | 5675 | symbol_set_frag (sym, frag_now); |
252b5132 | 5676 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
96d56e9f | 5677 | symbol_get_tc (sym)->symbol_class = XMC_TC; |
809ffe0d | 5678 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5679 | |
5680 | ppc_frob_label (sym); | |
5681 | } | |
5682 | ||
0baf16f2 AM |
5683 | #endif /* OBJ_XCOFF */ |
5684 | #ifdef OBJ_ELF | |
9c7977b3 | 5685 | int align; |
252b5132 RH |
5686 | |
5687 | /* Skip the TOC symbol name. */ | |
5688 | while (is_part_of_name (*input_line_pointer) | |
d13d4015 | 5689 | || *input_line_pointer == ' ' |
252b5132 RH |
5690 | || *input_line_pointer == '[' |
5691 | || *input_line_pointer == ']' | |
5692 | || *input_line_pointer == '{' | |
5693 | || *input_line_pointer == '}') | |
5694 | ++input_line_pointer; | |
5695 | ||
0baf16f2 | 5696 | /* Align to a four/eight byte boundary. */ |
2b3c4602 | 5697 | align = ppc_obj64 ? 3 : 2; |
9c7977b3 AM |
5698 | frag_align (align, 0, 0); |
5699 | record_alignment (now_seg, align); | |
0baf16f2 | 5700 | #endif /* OBJ_ELF */ |
252b5132 RH |
5701 | |
5702 | if (*input_line_pointer != ',') | |
5703 | demand_empty_rest_of_line (); | |
5704 | else | |
5705 | { | |
5706 | ++input_line_pointer; | |
2b3c4602 | 5707 | cons (ppc_obj64 ? 8 : 4); |
252b5132 RH |
5708 | } |
5709 | } | |
0baf16f2 AM |
5710 | |
5711 | /* Pseudo-op .machine. */ | |
0baf16f2 AM |
5712 | |
5713 | static void | |
98027b10 | 5714 | ppc_machine (int ignore ATTRIBUTE_UNUSED) |
0baf16f2 | 5715 | { |
d02603dc | 5716 | char c; |
69c040df AM |
5717 | char *cpu_string; |
5718 | #define MAX_HISTORY 100 | |
fa452fa6 | 5719 | static ppc_cpu_t *cpu_history; |
69c040df AM |
5720 | static int curr_hist; |
5721 | ||
5722 | SKIP_WHITESPACE (); | |
5723 | ||
d02603dc NC |
5724 | c = get_symbol_name (&cpu_string); |
5725 | cpu_string = xstrdup (cpu_string); | |
5726 | (void) restore_line_pointer (c); | |
69c040df AM |
5727 | |
5728 | if (cpu_string != NULL) | |
5729 | { | |
fa452fa6 | 5730 | ppc_cpu_t old_cpu = ppc_cpu; |
69fe9ce5 | 5731 | ppc_cpu_t new_cpu; |
69c040df AM |
5732 | char *p; |
5733 | ||
5734 | for (p = cpu_string; *p != 0; p++) | |
5735 | *p = TOLOWER (*p); | |
5736 | ||
5737 | if (strcmp (cpu_string, "push") == 0) | |
5738 | { | |
5739 | if (cpu_history == NULL) | |
325801bd | 5740 | cpu_history = XNEWVEC (ppc_cpu_t, MAX_HISTORY); |
69c040df AM |
5741 | |
5742 | if (curr_hist >= MAX_HISTORY) | |
5743 | as_bad (_(".machine stack overflow")); | |
5744 | else | |
5745 | cpu_history[curr_hist++] = ppc_cpu; | |
5746 | } | |
5747 | else if (strcmp (cpu_string, "pop") == 0) | |
5748 | { | |
5749 | if (curr_hist <= 0) | |
5750 | as_bad (_(".machine stack underflow")); | |
5751 | else | |
5752 | ppc_cpu = cpu_history[--curr_hist]; | |
5753 | } | |
776fc418 | 5754 | else if ((new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, cpu_string)) != 0) |
69fe9ce5 | 5755 | ppc_cpu = new_cpu; |
69c040df AM |
5756 | else |
5757 | as_bad (_("invalid machine `%s'"), cpu_string); | |
5758 | ||
5759 | if (ppc_cpu != old_cpu) | |
5760 | ppc_setup_opcodes (); | |
5761 | } | |
5762 | ||
5763 | demand_empty_rest_of_line (); | |
0baf16f2 | 5764 | } |
0baf16f2 | 5765 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ |
252b5132 RH |
5766 | \f |
5767 | #ifdef TE_PE | |
5768 | ||
99a814a1 | 5769 | /* Pseudo-ops specific to the Windows NT PowerPC PE (coff) format. */ |
252b5132 RH |
5770 | |
5771 | /* Set the current section. */ | |
5772 | static void | |
98027b10 | 5773 | ppc_set_current_section (segT new) |
252b5132 RH |
5774 | { |
5775 | ppc_previous_section = ppc_current_section; | |
5776 | ppc_current_section = new; | |
5777 | } | |
5778 | ||
5779 | /* pseudo-op: .previous | |
5780 | behaviour: toggles the current section with the previous section. | |
5781 | errors: None | |
99a814a1 AM |
5782 | warnings: "No previous section" */ |
5783 | ||
252b5132 | 5784 | static void |
98027b10 | 5785 | ppc_previous (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5786 | { |
81d4177b | 5787 | if (ppc_previous_section == NULL) |
252b5132 | 5788 | { |
d6ed37ed | 5789 | as_warn (_("no previous section to return to, ignored.")); |
252b5132 RH |
5790 | return; |
5791 | } | |
5792 | ||
99a814a1 | 5793 | subseg_set (ppc_previous_section, 0); |
252b5132 | 5794 | |
99a814a1 | 5795 | ppc_set_current_section (ppc_previous_section); |
252b5132 RH |
5796 | } |
5797 | ||
5798 | /* pseudo-op: .pdata | |
5799 | behaviour: predefined read only data section | |
b34976b6 | 5800 | double word aligned |
252b5132 RH |
5801 | errors: None |
5802 | warnings: None | |
5803 | initial: .section .pdata "adr3" | |
b34976b6 | 5804 | a - don't know -- maybe a misprint |
252b5132 RH |
5805 | d - initialized data |
5806 | r - readable | |
5807 | 3 - double word aligned (that would be 4 byte boundary) | |
5808 | ||
5809 | commentary: | |
5810 | Tag index tables (also known as the function table) for exception | |
99a814a1 | 5811 | handling, debugging, etc. */ |
252b5132 | 5812 | |
252b5132 | 5813 | static void |
98027b10 | 5814 | ppc_pdata (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5815 | { |
81d4177b | 5816 | if (pdata_section == 0) |
252b5132 RH |
5817 | { |
5818 | pdata_section = subseg_new (".pdata", 0); | |
81d4177b | 5819 | |
fd361982 AM |
5820 | bfd_set_section_flags (pdata_section, (SEC_ALLOC | SEC_LOAD | SEC_RELOC |
5821 | | SEC_READONLY | SEC_DATA)); | |
81d4177b | 5822 | |
fd361982 | 5823 | bfd_set_section_alignment (pdata_section, 2); |
252b5132 RH |
5824 | } |
5825 | else | |
5826 | { | |
99a814a1 | 5827 | pdata_section = subseg_new (".pdata", 0); |
252b5132 | 5828 | } |
99a814a1 | 5829 | ppc_set_current_section (pdata_section); |
252b5132 RH |
5830 | } |
5831 | ||
5832 | /* pseudo-op: .ydata | |
5833 | behaviour: predefined read only data section | |
b34976b6 | 5834 | double word aligned |
252b5132 RH |
5835 | errors: None |
5836 | warnings: None | |
5837 | initial: .section .ydata "drw3" | |
b34976b6 | 5838 | a - don't know -- maybe a misprint |
252b5132 RH |
5839 | d - initialized data |
5840 | r - readable | |
5841 | 3 - double word aligned (that would be 4 byte boundary) | |
5842 | commentary: | |
5843 | Tag tables (also known as the scope table) for exception handling, | |
99a814a1 AM |
5844 | debugging, etc. */ |
5845 | ||
252b5132 | 5846 | static void |
98027b10 | 5847 | ppc_ydata (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5848 | { |
81d4177b | 5849 | if (ydata_section == 0) |
252b5132 RH |
5850 | { |
5851 | ydata_section = subseg_new (".ydata", 0); | |
fd361982 AM |
5852 | bfd_set_section_flags (ydata_section, (SEC_ALLOC | SEC_LOAD | SEC_RELOC |
5853 | | SEC_READONLY | SEC_DATA )); | |
252b5132 | 5854 | |
fd361982 | 5855 | bfd_set_section_alignment (ydata_section, 3); |
252b5132 RH |
5856 | } |
5857 | else | |
5858 | { | |
5859 | ydata_section = subseg_new (".ydata", 0); | |
5860 | } | |
99a814a1 | 5861 | ppc_set_current_section (ydata_section); |
252b5132 RH |
5862 | } |
5863 | ||
5864 | /* pseudo-op: .reldata | |
5865 | behaviour: predefined read write data section | |
b34976b6 | 5866 | double word aligned (4-byte) |
252b5132 RH |
5867 | FIXME: relocation is applied to it |
5868 | FIXME: what's the difference between this and .data? | |
5869 | errors: None | |
5870 | warnings: None | |
5871 | initial: .section .reldata "drw3" | |
5872 | d - initialized data | |
5873 | r - readable | |
33eaf5de | 5874 | w - writable |
252b5132 RH |
5875 | 3 - double word aligned (that would be 8 byte boundary) |
5876 | ||
5877 | commentary: | |
5878 | Like .data, but intended to hold data subject to relocation, such as | |
99a814a1 AM |
5879 | function descriptors, etc. */ |
5880 | ||
252b5132 | 5881 | static void |
98027b10 | 5882 | ppc_reldata (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5883 | { |
5884 | if (reldata_section == 0) | |
5885 | { | |
5886 | reldata_section = subseg_new (".reldata", 0); | |
5887 | ||
fd361982 AM |
5888 | bfd_set_section_flags (reldata_section, (SEC_ALLOC | SEC_LOAD | SEC_RELOC |
5889 | | SEC_DATA)); | |
252b5132 | 5890 | |
fd361982 | 5891 | bfd_set_section_alignment (reldata_section, 2); |
252b5132 RH |
5892 | } |
5893 | else | |
5894 | { | |
5895 | reldata_section = subseg_new (".reldata", 0); | |
5896 | } | |
99a814a1 | 5897 | ppc_set_current_section (reldata_section); |
252b5132 RH |
5898 | } |
5899 | ||
5900 | /* pseudo-op: .rdata | |
5901 | behaviour: predefined read only data section | |
b34976b6 | 5902 | double word aligned |
252b5132 RH |
5903 | errors: None |
5904 | warnings: None | |
5905 | initial: .section .rdata "dr3" | |
5906 | d - initialized data | |
5907 | r - readable | |
99a814a1 AM |
5908 | 3 - double word aligned (that would be 4 byte boundary) */ |
5909 | ||
252b5132 | 5910 | static void |
98027b10 | 5911 | ppc_rdata (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5912 | { |
5913 | if (rdata_section == 0) | |
5914 | { | |
5915 | rdata_section = subseg_new (".rdata", 0); | |
fd361982 AM |
5916 | bfd_set_section_flags (rdata_section, (SEC_ALLOC | SEC_LOAD | SEC_RELOC |
5917 | | SEC_READONLY | SEC_DATA )); | |
252b5132 | 5918 | |
fd361982 | 5919 | bfd_set_section_alignment (rdata_section, 2); |
252b5132 RH |
5920 | } |
5921 | else | |
5922 | { | |
5923 | rdata_section = subseg_new (".rdata", 0); | |
5924 | } | |
99a814a1 | 5925 | ppc_set_current_section (rdata_section); |
252b5132 RH |
5926 | } |
5927 | ||
5928 | /* pseudo-op: .ualong | |
81d4177b | 5929 | behaviour: much like .int, with the exception that no alignment is |
b34976b6 | 5930 | performed. |
252b5132 RH |
5931 | FIXME: test the alignment statement |
5932 | errors: None | |
99a814a1 AM |
5933 | warnings: None */ |
5934 | ||
252b5132 | 5935 | static void |
98027b10 | 5936 | ppc_ualong (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 5937 | { |
99a814a1 AM |
5938 | /* Try for long. */ |
5939 | cons (4); | |
252b5132 RH |
5940 | } |
5941 | ||
5942 | /* pseudo-op: .znop <symbol name> | |
5943 | behaviour: Issue a nop instruction | |
b34976b6 | 5944 | Issue a IMAGE_REL_PPC_IFGLUE relocation against it, using |
252b5132 RH |
5945 | the supplied symbol name. |
5946 | errors: None | |
99a814a1 AM |
5947 | warnings: Missing symbol name */ |
5948 | ||
252b5132 | 5949 | static void |
98027b10 | 5950 | ppc_znop (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5951 | { |
5952 | unsigned long insn; | |
5953 | const struct powerpc_opcode *opcode; | |
252b5132 | 5954 | char *f; |
252b5132 | 5955 | symbolS *sym; |
252b5132 RH |
5956 | char *symbol_name; |
5957 | char c; | |
5958 | char *name; | |
252b5132 | 5959 | |
99a814a1 | 5960 | /* Strip out the symbol name. */ |
d02603dc | 5961 | c = get_symbol_name (&symbol_name); |
252b5132 | 5962 | |
a44e2901 | 5963 | name = xstrdup (symbol_name); |
252b5132 RH |
5964 | |
5965 | sym = symbol_find_or_make (name); | |
5966 | ||
5967 | *input_line_pointer = c; | |
5968 | ||
d02603dc | 5969 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
5970 | |
5971 | /* Look up the opcode in the hash table. */ | |
5972 | opcode = (const struct powerpc_opcode *) hash_find (ppc_hash, "nop"); | |
5973 | ||
99a814a1 | 5974 | /* Stick in the nop. */ |
252b5132 RH |
5975 | insn = opcode->opcode; |
5976 | ||
5977 | /* Write out the instruction. */ | |
5978 | f = frag_more (4); | |
5979 | md_number_to_chars (f, insn, 4); | |
5980 | fix_new (frag_now, | |
5981 | f - frag_now->fr_literal, | |
5982 | 4, | |
5983 | sym, | |
5984 | 0, | |
5985 | 0, | |
5986 | BFD_RELOC_16_GOT_PCREL); | |
5987 | ||
5988 | } | |
5989 | ||
81d4177b KH |
5990 | /* pseudo-op: |
5991 | behaviour: | |
5992 | errors: | |
99a814a1 AM |
5993 | warnings: */ |
5994 | ||
252b5132 | 5995 | static void |
98027b10 | 5996 | ppc_pe_comm (int lcomm) |
252b5132 | 5997 | { |
98027b10 AM |
5998 | char *name; |
5999 | char c; | |
6000 | char *p; | |
252b5132 | 6001 | offsetT temp; |
98027b10 | 6002 | symbolS *symbolP; |
252b5132 RH |
6003 | offsetT align; |
6004 | ||
d02603dc | 6005 | c = get_symbol_name (&name); |
252b5132 | 6006 | |
99a814a1 | 6007 | /* just after name is now '\0'. */ |
252b5132 RH |
6008 | p = input_line_pointer; |
6009 | *p = c; | |
d02603dc | 6010 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
6011 | if (*input_line_pointer != ',') |
6012 | { | |
d6ed37ed | 6013 | as_bad (_("expected comma after symbol-name: rest of line ignored.")); |
252b5132 RH |
6014 | ignore_rest_of_line (); |
6015 | return; | |
6016 | } | |
6017 | ||
6018 | input_line_pointer++; /* skip ',' */ | |
6019 | if ((temp = get_absolute_expression ()) < 0) | |
6020 | { | |
6021 | as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) temp); | |
6022 | ignore_rest_of_line (); | |
6023 | return; | |
6024 | } | |
6025 | ||
6026 | if (! lcomm) | |
6027 | { | |
6028 | /* The third argument to .comm is the alignment. */ | |
6029 | if (*input_line_pointer != ',') | |
6030 | align = 3; | |
6031 | else | |
6032 | { | |
6033 | ++input_line_pointer; | |
6034 | align = get_absolute_expression (); | |
6035 | if (align <= 0) | |
6036 | { | |
6037 | as_warn (_("ignoring bad alignment")); | |
6038 | align = 3; | |
6039 | } | |
6040 | } | |
6041 | } | |
6042 | ||
6043 | *p = 0; | |
6044 | symbolP = symbol_find_or_make (name); | |
6045 | ||
6046 | *p = c; | |
6047 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
6048 | { | |
d6ed37ed | 6049 | as_bad (_("ignoring attempt to re-define symbol `%s'."), |
252b5132 RH |
6050 | S_GET_NAME (symbolP)); |
6051 | ignore_rest_of_line (); | |
6052 | return; | |
6053 | } | |
6054 | ||
6055 | if (S_GET_VALUE (symbolP)) | |
6056 | { | |
6057 | if (S_GET_VALUE (symbolP) != (valueT) temp) | |
d6ed37ed | 6058 | as_bad (_("length of .comm \"%s\" is already %ld. Not changed to %ld."), |
252b5132 RH |
6059 | S_GET_NAME (symbolP), |
6060 | (long) S_GET_VALUE (symbolP), | |
6061 | (long) temp); | |
6062 | } | |
6063 | else | |
6064 | { | |
6065 | S_SET_VALUE (symbolP, (valueT) temp); | |
6066 | S_SET_EXTERNAL (symbolP); | |
86ebace2 | 6067 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); |
252b5132 RH |
6068 | } |
6069 | ||
6070 | demand_empty_rest_of_line (); | |
6071 | } | |
6072 | ||
6073 | /* | |
6074 | * implement the .section pseudo op: | |
6075 | * .section name {, "flags"} | |
6076 | * ^ ^ | |
6077 | * | +--- optional flags: 'b' for bss | |
6078 | * | 'i' for info | |
6079 | * +-- section name 'l' for lib | |
6080 | * 'n' for noload | |
6081 | * 'o' for over | |
6082 | * 'w' for data | |
6083 | * 'd' (apparently m88k for data) | |
6084 | * 'x' for text | |
6085 | * But if the argument is not a quoted string, treat it as a | |
6086 | * subsegment number. | |
6087 | * | |
6088 | * FIXME: this is a copy of the section processing from obj-coff.c, with | |
6089 | * additions/changes for the moto-pas assembler support. There are three | |
6090 | * categories: | |
6091 | * | |
81d4177b | 6092 | * FIXME: I just noticed this. This doesn't work at all really. It it |
252b5132 RH |
6093 | * setting bits that bfd probably neither understands or uses. The |
6094 | * correct approach (?) will have to incorporate extra fields attached | |
6095 | * to the section to hold the system specific stuff. (krk) | |
6096 | * | |
6097 | * Section Contents: | |
6098 | * 'a' - unknown - referred to in documentation, but no definition supplied | |
6099 | * 'c' - section has code | |
6100 | * 'd' - section has initialized data | |
6101 | * 'u' - section has uninitialized data | |
6102 | * 'i' - section contains directives (info) | |
6103 | * 'n' - section can be discarded | |
6104 | * 'R' - remove section at link time | |
6105 | * | |
6106 | * Section Protection: | |
6107 | * 'r' - section is readable | |
33eaf5de | 6108 | * 'w' - section is writable |
252b5132 RH |
6109 | * 'x' - section is executable |
6110 | * 's' - section is sharable | |
6111 | * | |
6112 | * Section Alignment: | |
6113 | * '0' - align to byte boundary | |
33eaf5de | 6114 | * '1' - align to halfword boundary |
252b5132 RH |
6115 | * '2' - align to word boundary |
6116 | * '3' - align to doubleword boundary | |
6117 | * '4' - align to quadword boundary | |
6118 | * '5' - align to 32 byte boundary | |
6119 | * '6' - align to 64 byte boundary | |
6120 | * | |
6121 | */ | |
6122 | ||
6123 | void | |
98027b10 | 6124 | ppc_pe_section (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 6125 | { |
99a814a1 | 6126 | /* Strip out the section name. */ |
252b5132 RH |
6127 | char *section_name; |
6128 | char c; | |
6129 | char *name; | |
6130 | unsigned int exp; | |
6131 | flagword flags; | |
6132 | segT sec; | |
6133 | int align; | |
6134 | ||
d02603dc | 6135 | c = get_symbol_name (§ion_name); |
252b5132 | 6136 | |
a44e2901 | 6137 | name = xstrdup (section_name); |
252b5132 RH |
6138 | |
6139 | *input_line_pointer = c; | |
6140 | ||
d02603dc | 6141 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
6142 | |
6143 | exp = 0; | |
6144 | flags = SEC_NO_FLAGS; | |
6145 | ||
6146 | if (strcmp (name, ".idata$2") == 0) | |
6147 | { | |
6148 | align = 0; | |
6149 | } | |
6150 | else if (strcmp (name, ".idata$3") == 0) | |
6151 | { | |
6152 | align = 0; | |
6153 | } | |
6154 | else if (strcmp (name, ".idata$4") == 0) | |
6155 | { | |
6156 | align = 2; | |
6157 | } | |
6158 | else if (strcmp (name, ".idata$5") == 0) | |
6159 | { | |
6160 | align = 2; | |
6161 | } | |
6162 | else if (strcmp (name, ".idata$6") == 0) | |
6163 | { | |
6164 | align = 1; | |
6165 | } | |
6166 | else | |
99a814a1 AM |
6167 | /* Default alignment to 16 byte boundary. */ |
6168 | align = 4; | |
252b5132 RH |
6169 | |
6170 | if (*input_line_pointer == ',') | |
6171 | { | |
6172 | ++input_line_pointer; | |
6173 | SKIP_WHITESPACE (); | |
6174 | if (*input_line_pointer != '"') | |
6175 | exp = get_absolute_expression (); | |
6176 | else | |
6177 | { | |
6178 | ++input_line_pointer; | |
6179 | while (*input_line_pointer != '"' | |
6180 | && ! is_end_of_line[(unsigned char) *input_line_pointer]) | |
6181 | { | |
6182 | switch (*input_line_pointer) | |
6183 | { | |
6184 | /* Section Contents */ | |
6185 | case 'a': /* unknown */ | |
d6ed37ed | 6186 | as_bad (_("unsupported section attribute -- 'a'")); |
252b5132 RH |
6187 | break; |
6188 | case 'c': /* code section */ | |
81d4177b | 6189 | flags |= SEC_CODE; |
252b5132 RH |
6190 | break; |
6191 | case 'd': /* section has initialized data */ | |
6192 | flags |= SEC_DATA; | |
6193 | break; | |
6194 | case 'u': /* section has uninitialized data */ | |
6195 | /* FIXME: This is IMAGE_SCN_CNT_UNINITIALIZED_DATA | |
6196 | in winnt.h */ | |
6197 | flags |= SEC_ROM; | |
6198 | break; | |
6199 | case 'i': /* section contains directives (info) */ | |
6200 | /* FIXME: This is IMAGE_SCN_LNK_INFO | |
6201 | in winnt.h */ | |
6202 | flags |= SEC_HAS_CONTENTS; | |
6203 | break; | |
6204 | case 'n': /* section can be discarded */ | |
81d4177b | 6205 | flags &=~ SEC_LOAD; |
252b5132 RH |
6206 | break; |
6207 | case 'R': /* Remove section at link time */ | |
6208 | flags |= SEC_NEVER_LOAD; | |
6209 | break; | |
8d452c78 | 6210 | #if IFLICT_BRAIN_DAMAGE |
252b5132 RH |
6211 | /* Section Protection */ |
6212 | case 'r': /* section is readable */ | |
6213 | flags |= IMAGE_SCN_MEM_READ; | |
6214 | break; | |
33eaf5de | 6215 | case 'w': /* section is writable */ |
252b5132 RH |
6216 | flags |= IMAGE_SCN_MEM_WRITE; |
6217 | break; | |
6218 | case 'x': /* section is executable */ | |
6219 | flags |= IMAGE_SCN_MEM_EXECUTE; | |
6220 | break; | |
6221 | case 's': /* section is sharable */ | |
6222 | flags |= IMAGE_SCN_MEM_SHARED; | |
6223 | break; | |
6224 | ||
6225 | /* Section Alignment */ | |
6226 | case '0': /* align to byte boundary */ | |
6227 | flags |= IMAGE_SCN_ALIGN_1BYTES; | |
6228 | align = 0; | |
6229 | break; | |
6230 | case '1': /* align to halfword boundary */ | |
6231 | flags |= IMAGE_SCN_ALIGN_2BYTES; | |
6232 | align = 1; | |
6233 | break; | |
6234 | case '2': /* align to word boundary */ | |
6235 | flags |= IMAGE_SCN_ALIGN_4BYTES; | |
6236 | align = 2; | |
6237 | break; | |
6238 | case '3': /* align to doubleword boundary */ | |
6239 | flags |= IMAGE_SCN_ALIGN_8BYTES; | |
6240 | align = 3; | |
6241 | break; | |
6242 | case '4': /* align to quadword boundary */ | |
6243 | flags |= IMAGE_SCN_ALIGN_16BYTES; | |
6244 | align = 4; | |
6245 | break; | |
6246 | case '5': /* align to 32 byte boundary */ | |
6247 | flags |= IMAGE_SCN_ALIGN_32BYTES; | |
6248 | align = 5; | |
6249 | break; | |
6250 | case '6': /* align to 64 byte boundary */ | |
6251 | flags |= IMAGE_SCN_ALIGN_64BYTES; | |
6252 | align = 6; | |
6253 | break; | |
8d452c78 | 6254 | #endif |
252b5132 | 6255 | default: |
99a814a1 AM |
6256 | as_bad (_("unknown section attribute '%c'"), |
6257 | *input_line_pointer); | |
252b5132 RH |
6258 | break; |
6259 | } | |
6260 | ++input_line_pointer; | |
6261 | } | |
6262 | if (*input_line_pointer == '"') | |
6263 | ++input_line_pointer; | |
6264 | } | |
6265 | } | |
6266 | ||
6267 | sec = subseg_new (name, (subsegT) exp); | |
6268 | ||
99a814a1 | 6269 | ppc_set_current_section (sec); |
252b5132 RH |
6270 | |
6271 | if (flags != SEC_NO_FLAGS) | |
6272 | { | |
fd361982 | 6273 | if (!bfd_set_section_flags (sec, flags)) |
252b5132 | 6274 | as_bad (_("error setting flags for \"%s\": %s"), |
fd361982 | 6275 | bfd_section_name (sec), |
252b5132 RH |
6276 | bfd_errmsg (bfd_get_error ())); |
6277 | } | |
6278 | ||
fd361982 | 6279 | bfd_set_section_alignment (sec, align); |
252b5132 RH |
6280 | } |
6281 | ||
6282 | static void | |
98027b10 | 6283 | ppc_pe_function (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6284 | { |
6285 | char *name; | |
6286 | char endc; | |
6287 | symbolS *ext_sym; | |
6288 | ||
d02603dc | 6289 | endc = get_symbol_name (&name); |
252b5132 RH |
6290 | |
6291 | ext_sym = symbol_find_or_make (name); | |
6292 | ||
d02603dc | 6293 | (void) restore_line_pointer (endc); |
252b5132 RH |
6294 | |
6295 | S_SET_DATA_TYPE (ext_sym, DT_FCN << N_BTSHFT); | |
6296 | SF_SET_FUNCTION (ext_sym); | |
6297 | SF_SET_PROCESS (ext_sym); | |
6298 | coff_add_linesym (ext_sym); | |
6299 | ||
6300 | demand_empty_rest_of_line (); | |
6301 | } | |
6302 | ||
6303 | static void | |
98027b10 | 6304 | ppc_pe_tocd (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
6305 | { |
6306 | if (tocdata_section == 0) | |
6307 | { | |
6308 | tocdata_section = subseg_new (".tocd", 0); | |
99a814a1 | 6309 | /* FIXME: section flags won't work. */ |
fd361982 AM |
6310 | bfd_set_section_flags (tocdata_section, (SEC_ALLOC | SEC_LOAD | SEC_RELOC |
6311 | | SEC_READONLY | SEC_DATA)); | |
252b5132 | 6312 | |
fd361982 | 6313 | bfd_set_section_alignment (tocdata_section, 2); |
252b5132 RH |
6314 | } |
6315 | else | |
6316 | { | |
6317 | rdata_section = subseg_new (".tocd", 0); | |
6318 | } | |
6319 | ||
99a814a1 | 6320 | ppc_set_current_section (tocdata_section); |
252b5132 RH |
6321 | |
6322 | demand_empty_rest_of_line (); | |
6323 | } | |
6324 | ||
6325 | /* Don't adjust TOC relocs to use the section symbol. */ | |
6326 | ||
6327 | int | |
98027b10 | 6328 | ppc_pe_fix_adjustable (fixS *fix) |
252b5132 RH |
6329 | { |
6330 | return fix->fx_r_type != BFD_RELOC_PPC_TOC16; | |
6331 | } | |
6332 | ||
6333 | #endif | |
6334 | \f | |
6335 | #ifdef OBJ_XCOFF | |
6336 | ||
6337 | /* XCOFF specific symbol and file handling. */ | |
6338 | ||
6339 | /* Canonicalize the symbol name. We use the to force the suffix, if | |
6340 | any, to use square brackets, and to be in upper case. */ | |
6341 | ||
6342 | char * | |
98027b10 | 6343 | ppc_canonicalize_symbol_name (char *name) |
252b5132 RH |
6344 | { |
6345 | char *s; | |
6346 | ||
6347 | if (ppc_stab_symbol) | |
6348 | return name; | |
6349 | ||
6350 | for (s = name; *s != '\0' && *s != '{' && *s != '['; s++) | |
6351 | ; | |
6352 | if (*s != '\0') | |
6353 | { | |
6354 | char brac; | |
6355 | ||
6356 | if (*s == '[') | |
6357 | brac = ']'; | |
6358 | else | |
6359 | { | |
6360 | *s = '['; | |
6361 | brac = '}'; | |
6362 | } | |
6363 | ||
6364 | for (s++; *s != '\0' && *s != brac; s++) | |
3882b010 | 6365 | *s = TOUPPER (*s); |
252b5132 RH |
6366 | |
6367 | if (*s == '\0' || s[1] != '\0') | |
6368 | as_bad (_("bad symbol suffix")); | |
6369 | ||
6370 | *s = ']'; | |
6371 | } | |
6372 | ||
6373 | return name; | |
6374 | } | |
6375 | ||
6376 | /* Set the class of a symbol based on the suffix, if any. This is | |
6377 | called whenever a new symbol is created. */ | |
6378 | ||
6379 | void | |
98027b10 | 6380 | ppc_symbol_new_hook (symbolS *sym) |
252b5132 | 6381 | { |
809ffe0d | 6382 | struct ppc_tc_sy *tc; |
252b5132 RH |
6383 | const char *s; |
6384 | ||
809ffe0d ILT |
6385 | tc = symbol_get_tc (sym); |
6386 | tc->next = NULL; | |
6387 | tc->output = 0; | |
96d56e9f | 6388 | tc->symbol_class = -1; |
809ffe0d ILT |
6389 | tc->real_name = NULL; |
6390 | tc->subseg = 0; | |
6391 | tc->align = 0; | |
85645aed TG |
6392 | tc->u.size = NULL; |
6393 | tc->u.dw = NULL; | |
809ffe0d | 6394 | tc->within = NULL; |
252b5132 RH |
6395 | |
6396 | if (ppc_stab_symbol) | |
6397 | return; | |
6398 | ||
6399 | s = strchr (S_GET_NAME (sym), '['); | |
6400 | if (s == (const char *) NULL) | |
6401 | { | |
6402 | /* There is no suffix. */ | |
6403 | return; | |
6404 | } | |
6405 | ||
6406 | ++s; | |
6407 | ||
6408 | switch (s[0]) | |
6409 | { | |
6410 | case 'B': | |
6411 | if (strcmp (s, "BS]") == 0) | |
96d56e9f | 6412 | tc->symbol_class = XMC_BS; |
252b5132 RH |
6413 | break; |
6414 | case 'D': | |
6415 | if (strcmp (s, "DB]") == 0) | |
96d56e9f | 6416 | tc->symbol_class = XMC_DB; |
252b5132 | 6417 | else if (strcmp (s, "DS]") == 0) |
96d56e9f | 6418 | tc->symbol_class = XMC_DS; |
252b5132 RH |
6419 | break; |
6420 | case 'G': | |
6421 | if (strcmp (s, "GL]") == 0) | |
96d56e9f | 6422 | tc->symbol_class = XMC_GL; |
252b5132 RH |
6423 | break; |
6424 | case 'P': | |
6425 | if (strcmp (s, "PR]") == 0) | |
96d56e9f | 6426 | tc->symbol_class = XMC_PR; |
252b5132 RH |
6427 | break; |
6428 | case 'R': | |
6429 | if (strcmp (s, "RO]") == 0) | |
96d56e9f | 6430 | tc->symbol_class = XMC_RO; |
252b5132 | 6431 | else if (strcmp (s, "RW]") == 0) |
96d56e9f | 6432 | tc->symbol_class = XMC_RW; |
252b5132 RH |
6433 | break; |
6434 | case 'S': | |
6435 | if (strcmp (s, "SV]") == 0) | |
96d56e9f | 6436 | tc->symbol_class = XMC_SV; |
252b5132 RH |
6437 | break; |
6438 | case 'T': | |
6439 | if (strcmp (s, "TC]") == 0) | |
96d56e9f | 6440 | tc->symbol_class = XMC_TC; |
252b5132 | 6441 | else if (strcmp (s, "TI]") == 0) |
96d56e9f | 6442 | tc->symbol_class = XMC_TI; |
252b5132 | 6443 | else if (strcmp (s, "TB]") == 0) |
96d56e9f | 6444 | tc->symbol_class = XMC_TB; |
252b5132 | 6445 | else if (strcmp (s, "TC0]") == 0 || strcmp (s, "T0]") == 0) |
96d56e9f | 6446 | tc->symbol_class = XMC_TC0; |
252b5132 RH |
6447 | break; |
6448 | case 'U': | |
6449 | if (strcmp (s, "UA]") == 0) | |
96d56e9f | 6450 | tc->symbol_class = XMC_UA; |
252b5132 | 6451 | else if (strcmp (s, "UC]") == 0) |
96d56e9f | 6452 | tc->symbol_class = XMC_UC; |
252b5132 RH |
6453 | break; |
6454 | case 'X': | |
6455 | if (strcmp (s, "XO]") == 0) | |
96d56e9f | 6456 | tc->symbol_class = XMC_XO; |
252b5132 RH |
6457 | break; |
6458 | } | |
6459 | ||
96d56e9f | 6460 | if (tc->symbol_class == -1) |
d6ed37ed | 6461 | as_bad (_("unrecognized symbol suffix")); |
252b5132 RH |
6462 | } |
6463 | ||
252b5132 RH |
6464 | /* This variable is set by ppc_frob_symbol if any absolute symbols are |
6465 | seen. It tells ppc_adjust_symtab whether it needs to look through | |
6466 | the symbols. */ | |
6467 | ||
b34976b6 | 6468 | static bfd_boolean ppc_saw_abs; |
252b5132 RH |
6469 | |
6470 | /* Change the name of a symbol just before writing it out. Set the | |
6471 | real name if the .rename pseudo-op was used. Otherwise, remove any | |
6472 | class suffix. Return 1 if the symbol should not be included in the | |
6473 | symbol table. */ | |
6474 | ||
6475 | int | |
98027b10 | 6476 | ppc_frob_symbol (symbolS *sym) |
252b5132 RH |
6477 | { |
6478 | static symbolS *ppc_last_function; | |
6479 | static symbolS *set_end; | |
6480 | ||
6481 | /* Discard symbols that should not be included in the output symbol | |
6482 | table. */ | |
809ffe0d ILT |
6483 | if (! symbol_used_in_reloc_p (sym) |
6484 | && ((symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) != 0 | |
670ec21d | 6485 | || (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 6486 | && ! symbol_get_tc (sym)->output |
252b5132 RH |
6487 | && S_GET_STORAGE_CLASS (sym) != C_FILE))) |
6488 | return 1; | |
6489 | ||
a161fe53 AM |
6490 | /* This one will disappear anyway. Don't make a csect sym for it. */ |
6491 | if (sym == abs_section_sym) | |
6492 | return 1; | |
6493 | ||
809ffe0d ILT |
6494 | if (symbol_get_tc (sym)->real_name != (char *) NULL) |
6495 | S_SET_NAME (sym, symbol_get_tc (sym)->real_name); | |
252b5132 RH |
6496 | else |
6497 | { | |
6498 | const char *name; | |
6499 | const char *s; | |
6500 | ||
6501 | name = S_GET_NAME (sym); | |
6502 | s = strchr (name, '['); | |
6503 | if (s != (char *) NULL) | |
6504 | { | |
6505 | unsigned int len; | |
6506 | char *snew; | |
6507 | ||
6508 | len = s - name; | |
a44e2901 | 6509 | snew = xstrndup (name, len); |
252b5132 RH |
6510 | |
6511 | S_SET_NAME (sym, snew); | |
6512 | } | |
6513 | } | |
6514 | ||
6515 | if (set_end != (symbolS *) NULL) | |
6516 | { | |
6517 | SA_SET_SYM_ENDNDX (set_end, sym); | |
6518 | set_end = NULL; | |
6519 | } | |
6520 | ||
6521 | if (SF_GET_FUNCTION (sym)) | |
6522 | { | |
6523 | if (ppc_last_function != (symbolS *) NULL) | |
6524 | as_bad (_("two .function pseudo-ops with no intervening .ef")); | |
6525 | ppc_last_function = sym; | |
85645aed | 6526 | if (symbol_get_tc (sym)->u.size != (symbolS *) NULL) |
252b5132 | 6527 | { |
85645aed | 6528 | resolve_symbol_value (symbol_get_tc (sym)->u.size); |
809ffe0d | 6529 | SA_SET_SYM_FSIZE (sym, |
85645aed | 6530 | (long) S_GET_VALUE (symbol_get_tc (sym)->u.size)); |
252b5132 RH |
6531 | } |
6532 | } | |
6533 | else if (S_GET_STORAGE_CLASS (sym) == C_FCN | |
6534 | && strcmp (S_GET_NAME (sym), ".ef") == 0) | |
6535 | { | |
6536 | if (ppc_last_function == (symbolS *) NULL) | |
6537 | as_bad (_(".ef with no preceding .function")); | |
6538 | else | |
6539 | { | |
6540 | set_end = ppc_last_function; | |
6541 | ppc_last_function = NULL; | |
6542 | ||
6543 | /* We don't have a C_EFCN symbol, but we need to force the | |
6544 | COFF backend to believe that it has seen one. */ | |
6545 | coff_last_function = NULL; | |
6546 | } | |
6547 | } | |
6548 | ||
670ec21d | 6549 | if (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 6550 | && (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) == 0 |
252b5132 RH |
6551 | && S_GET_STORAGE_CLASS (sym) != C_FILE |
6552 | && S_GET_STORAGE_CLASS (sym) != C_FCN | |
6553 | && S_GET_STORAGE_CLASS (sym) != C_BLOCK | |
6554 | && S_GET_STORAGE_CLASS (sym) != C_BSTAT | |
6555 | && S_GET_STORAGE_CLASS (sym) != C_ESTAT | |
6556 | && S_GET_STORAGE_CLASS (sym) != C_BINCL | |
6557 | && S_GET_STORAGE_CLASS (sym) != C_EINCL | |
6558 | && S_GET_SEGMENT (sym) != ppc_coff_debug_section) | |
6559 | S_SET_STORAGE_CLASS (sym, C_HIDEXT); | |
6560 | ||
6561 | if (S_GET_STORAGE_CLASS (sym) == C_EXT | |
8602d4fe | 6562 | || S_GET_STORAGE_CLASS (sym) == C_AIX_WEAKEXT |
252b5132 RH |
6563 | || S_GET_STORAGE_CLASS (sym) == C_HIDEXT) |
6564 | { | |
6565 | int i; | |
6566 | union internal_auxent *a; | |
6567 | ||
6568 | /* Create a csect aux. */ | |
6569 | i = S_GET_NUMBER_AUXILIARY (sym); | |
6570 | S_SET_NUMBER_AUXILIARY (sym, i + 1); | |
809ffe0d | 6571 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].u.auxent; |
96d56e9f | 6572 | if (symbol_get_tc (sym)->symbol_class == XMC_TC0) |
252b5132 RH |
6573 | { |
6574 | /* This is the TOC table. */ | |
6575 | know (strcmp (S_GET_NAME (sym), "TOC") == 0); | |
6576 | a->x_csect.x_scnlen.l = 0; | |
6577 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
6578 | } | |
809ffe0d | 6579 | else if (symbol_get_tc (sym)->subseg != 0) |
252b5132 RH |
6580 | { |
6581 | /* This is a csect symbol. x_scnlen is the size of the | |
6582 | csect. */ | |
809ffe0d | 6583 | if (symbol_get_tc (sym)->next == (symbolS *) NULL) |
fd361982 | 6584 | a->x_csect.x_scnlen.l = (bfd_section_size (S_GET_SEGMENT (sym)) |
252b5132 RH |
6585 | - S_GET_VALUE (sym)); |
6586 | else | |
6587 | { | |
6386f3a7 | 6588 | resolve_symbol_value (symbol_get_tc (sym)->next); |
809ffe0d | 6589 | a->x_csect.x_scnlen.l = (S_GET_VALUE (symbol_get_tc (sym)->next) |
252b5132 RH |
6590 | - S_GET_VALUE (sym)); |
6591 | } | |
809ffe0d | 6592 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_SD; |
252b5132 RH |
6593 | } |
6594 | else if (S_GET_SEGMENT (sym) == bss_section) | |
6595 | { | |
6596 | /* This is a common symbol. */ | |
809ffe0d ILT |
6597 | a->x_csect.x_scnlen.l = symbol_get_frag (sym)->fr_offset; |
6598 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_CM; | |
252b5132 | 6599 | if (S_IS_EXTERNAL (sym)) |
96d56e9f | 6600 | symbol_get_tc (sym)->symbol_class = XMC_RW; |
252b5132 | 6601 | else |
96d56e9f | 6602 | symbol_get_tc (sym)->symbol_class = XMC_BS; |
252b5132 RH |
6603 | } |
6604 | else if (S_GET_SEGMENT (sym) == absolute_section) | |
6605 | { | |
6606 | /* This is an absolute symbol. The csect will be created by | |
99a814a1 | 6607 | ppc_adjust_symtab. */ |
b34976b6 | 6608 | ppc_saw_abs = TRUE; |
252b5132 | 6609 | a->x_csect.x_smtyp = XTY_LD; |
96d56e9f NC |
6610 | if (symbol_get_tc (sym)->symbol_class == -1) |
6611 | symbol_get_tc (sym)->symbol_class = XMC_XO; | |
252b5132 RH |
6612 | } |
6613 | else if (! S_IS_DEFINED (sym)) | |
6614 | { | |
6615 | /* This is an external symbol. */ | |
6616 | a->x_csect.x_scnlen.l = 0; | |
6617 | a->x_csect.x_smtyp = XTY_ER; | |
6618 | } | |
96d56e9f | 6619 | else if (symbol_get_tc (sym)->symbol_class == XMC_TC) |
252b5132 RH |
6620 | { |
6621 | symbolS *next; | |
6622 | ||
6623 | /* This is a TOC definition. x_scnlen is the size of the | |
6624 | TOC entry. */ | |
6625 | next = symbol_next (sym); | |
96d56e9f | 6626 | while (symbol_get_tc (next)->symbol_class == XMC_TC0) |
252b5132 RH |
6627 | next = symbol_next (next); |
6628 | if (next == (symbolS *) NULL | |
96d56e9f | 6629 | || symbol_get_tc (next)->symbol_class != XMC_TC) |
252b5132 RH |
6630 | { |
6631 | if (ppc_after_toc_frag == (fragS *) NULL) | |
fd361982 | 6632 | a->x_csect.x_scnlen.l = (bfd_section_size (data_section) |
252b5132 RH |
6633 | - S_GET_VALUE (sym)); |
6634 | else | |
6635 | a->x_csect.x_scnlen.l = (ppc_after_toc_frag->fr_address | |
6636 | - S_GET_VALUE (sym)); | |
6637 | } | |
6638 | else | |
6639 | { | |
6386f3a7 | 6640 | resolve_symbol_value (next); |
252b5132 RH |
6641 | a->x_csect.x_scnlen.l = (S_GET_VALUE (next) |
6642 | - S_GET_VALUE (sym)); | |
6643 | } | |
6644 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
6645 | } | |
6646 | else | |
6647 | { | |
6648 | symbolS *csect; | |
6649 | ||
6650 | /* This is a normal symbol definition. x_scnlen is the | |
6651 | symbol index of the containing csect. */ | |
6652 | if (S_GET_SEGMENT (sym) == text_section) | |
6653 | csect = ppc_text_csects; | |
6654 | else if (S_GET_SEGMENT (sym) == data_section) | |
6655 | csect = ppc_data_csects; | |
6656 | else | |
6657 | abort (); | |
6658 | ||
6659 | /* Skip the initial dummy symbol. */ | |
809ffe0d | 6660 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
6661 | |
6662 | if (csect == (symbolS *) NULL) | |
6663 | { | |
6664 | as_warn (_("warning: symbol %s has no csect"), S_GET_NAME (sym)); | |
6665 | a->x_csect.x_scnlen.l = 0; | |
6666 | } | |
6667 | else | |
6668 | { | |
809ffe0d | 6669 | while (symbol_get_tc (csect)->next != (symbolS *) NULL) |
252b5132 | 6670 | { |
6386f3a7 | 6671 | resolve_symbol_value (symbol_get_tc (csect)->next); |
809ffe0d ILT |
6672 | if (S_GET_VALUE (symbol_get_tc (csect)->next) |
6673 | > S_GET_VALUE (sym)) | |
252b5132 | 6674 | break; |
809ffe0d | 6675 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
6676 | } |
6677 | ||
809ffe0d ILT |
6678 | a->x_csect.x_scnlen.p = |
6679 | coffsymbol (symbol_get_bfdsym (csect))->native; | |
6680 | coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].fix_scnlen = | |
6681 | 1; | |
252b5132 RH |
6682 | } |
6683 | a->x_csect.x_smtyp = XTY_LD; | |
6684 | } | |
81d4177b | 6685 | |
252b5132 RH |
6686 | a->x_csect.x_parmhash = 0; |
6687 | a->x_csect.x_snhash = 0; | |
96d56e9f | 6688 | if (symbol_get_tc (sym)->symbol_class == -1) |
252b5132 RH |
6689 | a->x_csect.x_smclas = XMC_PR; |
6690 | else | |
96d56e9f | 6691 | a->x_csect.x_smclas = symbol_get_tc (sym)->symbol_class; |
252b5132 RH |
6692 | a->x_csect.x_stab = 0; |
6693 | a->x_csect.x_snstab = 0; | |
6694 | ||
6695 | /* Don't let the COFF backend resort these symbols. */ | |
809ffe0d | 6696 | symbol_get_bfdsym (sym)->flags |= BSF_NOT_AT_END; |
252b5132 RH |
6697 | } |
6698 | else if (S_GET_STORAGE_CLASS (sym) == C_BSTAT) | |
6699 | { | |
6700 | /* We want the value to be the symbol index of the referenced | |
6701 | csect symbol. BFD will do that for us if we set the right | |
6702 | flags. */ | |
b782de16 AM |
6703 | asymbol *bsym = symbol_get_bfdsym (symbol_get_tc (sym)->within); |
6704 | combined_entry_type *c = coffsymbol (bsym)->native; | |
6705 | ||
6706 | S_SET_VALUE (sym, (valueT) (size_t) c); | |
809ffe0d | 6707 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_value = 1; |
252b5132 RH |
6708 | } |
6709 | else if (S_GET_STORAGE_CLASS (sym) == C_STSYM) | |
6710 | { | |
6711 | symbolS *block; | |
c734e7e3 | 6712 | valueT base; |
252b5132 | 6713 | |
809ffe0d | 6714 | block = symbol_get_tc (sym)->within; |
c734e7e3 TG |
6715 | if (block) |
6716 | { | |
6717 | /* The value is the offset from the enclosing csect. */ | |
6718 | symbolS *csect; | |
6719 | ||
6720 | csect = symbol_get_tc (block)->within; | |
6721 | resolve_symbol_value (csect); | |
6722 | base = S_GET_VALUE (csect); | |
6723 | } | |
6724 | else | |
6725 | base = 0; | |
6726 | ||
6727 | S_SET_VALUE (sym, S_GET_VALUE (sym) - base); | |
252b5132 RH |
6728 | } |
6729 | else if (S_GET_STORAGE_CLASS (sym) == C_BINCL | |
6730 | || S_GET_STORAGE_CLASS (sym) == C_EINCL) | |
6731 | { | |
6732 | /* We want the value to be a file offset into the line numbers. | |
99a814a1 AM |
6733 | BFD will do that for us if we set the right flags. We have |
6734 | already set the value correctly. */ | |
809ffe0d | 6735 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_line = 1; |
252b5132 RH |
6736 | } |
6737 | ||
6738 | return 0; | |
6739 | } | |
6740 | ||
6741 | /* Adjust the symbol table. This creates csect symbols for all | |
6742 | absolute symbols. */ | |
6743 | ||
6744 | void | |
98027b10 | 6745 | ppc_adjust_symtab (void) |
252b5132 RH |
6746 | { |
6747 | symbolS *sym; | |
6748 | ||
6749 | if (! ppc_saw_abs) | |
6750 | return; | |
6751 | ||
6752 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
6753 | { | |
6754 | symbolS *csect; | |
6755 | int i; | |
6756 | union internal_auxent *a; | |
6757 | ||
6758 | if (S_GET_SEGMENT (sym) != absolute_section) | |
6759 | continue; | |
6760 | ||
6761 | csect = symbol_create (".abs[XO]", absolute_section, | |
6762 | S_GET_VALUE (sym), &zero_address_frag); | |
809ffe0d | 6763 | symbol_get_bfdsym (csect)->value = S_GET_VALUE (sym); |
252b5132 RH |
6764 | S_SET_STORAGE_CLASS (csect, C_HIDEXT); |
6765 | i = S_GET_NUMBER_AUXILIARY (csect); | |
6766 | S_SET_NUMBER_AUXILIARY (csect, i + 1); | |
809ffe0d | 6767 | a = &coffsymbol (symbol_get_bfdsym (csect))->native[i + 1].u.auxent; |
252b5132 RH |
6768 | a->x_csect.x_scnlen.l = 0; |
6769 | a->x_csect.x_smtyp = XTY_SD; | |
6770 | a->x_csect.x_parmhash = 0; | |
6771 | a->x_csect.x_snhash = 0; | |
6772 | a->x_csect.x_smclas = XMC_XO; | |
6773 | a->x_csect.x_stab = 0; | |
6774 | a->x_csect.x_snstab = 0; | |
6775 | ||
6776 | symbol_insert (csect, sym, &symbol_rootP, &symbol_lastP); | |
6777 | ||
6778 | i = S_GET_NUMBER_AUXILIARY (sym); | |
809ffe0d ILT |
6779 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i].u.auxent; |
6780 | a->x_csect.x_scnlen.p = coffsymbol (symbol_get_bfdsym (csect))->native; | |
6781 | coffsymbol (symbol_get_bfdsym (sym))->native[i].fix_scnlen = 1; | |
252b5132 RH |
6782 | } |
6783 | ||
b34976b6 | 6784 | ppc_saw_abs = FALSE; |
252b5132 RH |
6785 | } |
6786 | ||
6787 | /* Set the VMA for a section. This is called on all the sections in | |
6788 | turn. */ | |
6789 | ||
6790 | void | |
98027b10 | 6791 | ppc_frob_section (asection *sec) |
252b5132 | 6792 | { |
931e13a6 | 6793 | static bfd_vma vma = 0; |
252b5132 | 6794 | |
85645aed | 6795 | /* Dwarf sections start at 0. */ |
fd361982 | 6796 | if (bfd_section_flags (sec) & SEC_DEBUGGING) |
85645aed TG |
6797 | return; |
6798 | ||
931e13a6 | 6799 | vma = md_section_align (sec, vma); |
fd361982 AM |
6800 | bfd_set_section_vma (sec, vma); |
6801 | vma += bfd_section_size (sec); | |
252b5132 RH |
6802 | } |
6803 | ||
6804 | #endif /* OBJ_XCOFF */ | |
6805 | \f | |
6d4af3c2 | 6806 | const char * |
98027b10 | 6807 | md_atof (int type, char *litp, int *sizep) |
252b5132 | 6808 | { |
499ac353 | 6809 | return ieee_md_atof (type, litp, sizep, target_big_endian); |
252b5132 RH |
6810 | } |
6811 | ||
6812 | /* Write a value out to the object file, using the appropriate | |
6813 | endianness. */ | |
6814 | ||
6815 | void | |
98027b10 | 6816 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
6817 | { |
6818 | if (target_big_endian) | |
6819 | number_to_chars_bigendian (buf, val, n); | |
6820 | else | |
6821 | number_to_chars_littleendian (buf, val, n); | |
6822 | } | |
6823 | ||
6824 | /* Align a section (I don't know why this is machine dependent). */ | |
6825 | ||
6826 | valueT | |
3aeeedbb | 6827 | md_section_align (asection *seg ATTRIBUTE_UNUSED, valueT addr) |
252b5132 | 6828 | { |
3aeeedbb AM |
6829 | #ifdef OBJ_ELF |
6830 | return addr; | |
6831 | #else | |
fd361982 | 6832 | int align = bfd_section_alignment (seg); |
252b5132 | 6833 | |
8d3842cd | 6834 | return ((addr + (1 << align) - 1) & -(1 << align)); |
3aeeedbb | 6835 | #endif |
252b5132 RH |
6836 | } |
6837 | ||
6838 | /* We don't have any form of relaxing. */ | |
6839 | ||
6840 | int | |
98027b10 AM |
6841 | md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, |
6842 | asection *seg ATTRIBUTE_UNUSED) | |
252b5132 RH |
6843 | { |
6844 | abort (); | |
6845 | return 0; | |
6846 | } | |
6847 | ||
6848 | /* Convert a machine dependent frag. We never generate these. */ | |
6849 | ||
6850 | void | |
98027b10 AM |
6851 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
6852 | asection *sec ATTRIBUTE_UNUSED, | |
6853 | fragS *fragp ATTRIBUTE_UNUSED) | |
252b5132 RH |
6854 | { |
6855 | abort (); | |
6856 | } | |
6857 | ||
6858 | /* We have no need to default values of symbols. */ | |
6859 | ||
252b5132 | 6860 | symbolS * |
98027b10 | 6861 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
6862 | { |
6863 | return 0; | |
6864 | } | |
6865 | \f | |
6866 | /* Functions concerning relocs. */ | |
6867 | ||
6868 | /* The location from which a PC relative jump should be calculated, | |
6869 | given a PC relative reloc. */ | |
6870 | ||
6871 | long | |
98027b10 | 6872 | md_pcrel_from_section (fixS *fixp, segT sec ATTRIBUTE_UNUSED) |
252b5132 RH |
6873 | { |
6874 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
6875 | } | |
6876 | ||
6877 | #ifdef OBJ_XCOFF | |
6878 | ||
6879 | /* This is called to see whether a fixup should be adjusted to use a | |
6880 | section symbol. We take the opportunity to change a fixup against | |
6881 | a symbol in the TOC subsegment into a reloc against the | |
6882 | corresponding .tc symbol. */ | |
6883 | ||
6884 | int | |
98027b10 | 6885 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 6886 | { |
b782de16 AM |
6887 | valueT val = resolve_symbol_value (fix->fx_addsy); |
6888 | segT symseg = S_GET_SEGMENT (fix->fx_addsy); | |
6889 | TC_SYMFIELD_TYPE *tc; | |
6890 | ||
6891 | if (symseg == absolute_section) | |
6892 | return 0; | |
252b5132 | 6893 | |
85645aed | 6894 | /* Always adjust symbols in debugging sections. */ |
fd361982 | 6895 | if (bfd_section_flags (symseg) & SEC_DEBUGGING) |
85645aed TG |
6896 | return 1; |
6897 | ||
252b5132 | 6898 | if (ppc_toc_csect != (symbolS *) NULL |
252b5132 | 6899 | && fix->fx_addsy != ppc_toc_csect |
b782de16 | 6900 | && symseg == data_section |
252b5132 RH |
6901 | && val >= ppc_toc_frag->fr_address |
6902 | && (ppc_after_toc_frag == (fragS *) NULL | |
6903 | || val < ppc_after_toc_frag->fr_address)) | |
6904 | { | |
6905 | symbolS *sy; | |
6906 | ||
6907 | for (sy = symbol_next (ppc_toc_csect); | |
6908 | sy != (symbolS *) NULL; | |
6909 | sy = symbol_next (sy)) | |
6910 | { | |
b782de16 AM |
6911 | TC_SYMFIELD_TYPE *sy_tc = symbol_get_tc (sy); |
6912 | ||
96d56e9f | 6913 | if (sy_tc->symbol_class == XMC_TC0) |
252b5132 | 6914 | continue; |
96d56e9f | 6915 | if (sy_tc->symbol_class != XMC_TC) |
252b5132 | 6916 | break; |
b782de16 | 6917 | if (val == resolve_symbol_value (sy)) |
252b5132 RH |
6918 | { |
6919 | fix->fx_addsy = sy; | |
6920 | fix->fx_addnumber = val - ppc_toc_frag->fr_address; | |
6921 | return 0; | |
6922 | } | |
6923 | } | |
6924 | ||
6925 | as_bad_where (fix->fx_file, fix->fx_line, | |
6926 | _("symbol in .toc does not match any .tc")); | |
6927 | } | |
6928 | ||
6929 | /* Possibly adjust the reloc to be against the csect. */ | |
b782de16 AM |
6930 | tc = symbol_get_tc (fix->fx_addsy); |
6931 | if (tc->subseg == 0 | |
96d56e9f NC |
6932 | && tc->symbol_class != XMC_TC0 |
6933 | && tc->symbol_class != XMC_TC | |
b782de16 | 6934 | && symseg != bss_section |
252b5132 | 6935 | /* Don't adjust if this is a reloc in the toc section. */ |
b782de16 | 6936 | && (symseg != data_section |
252b5132 RH |
6937 | || ppc_toc_csect == NULL |
6938 | || val < ppc_toc_frag->fr_address | |
6939 | || (ppc_after_toc_frag != NULL | |
6940 | && val >= ppc_after_toc_frag->fr_address))) | |
6941 | { | |
2fb4b302 | 6942 | symbolS *csect = tc->within; |
252b5132 | 6943 | |
2fb4b302 TG |
6944 | /* If the symbol was not declared by a label (eg: a section symbol), |
6945 | use the section instead of the csect. This doesn't happen in | |
6946 | normal AIX assembly code. */ | |
6947 | if (csect == NULL) | |
6948 | csect = seg_info (symseg)->sym; | |
252b5132 | 6949 | |
2fb4b302 TG |
6950 | fix->fx_offset += val - symbol_get_frag (csect)->fr_address; |
6951 | fix->fx_addsy = csect; | |
252b5132 | 6952 | |
b782de16 | 6953 | return 0; |
252b5132 RH |
6954 | } |
6955 | ||
6956 | /* Adjust a reloc against a .lcomm symbol to be against the base | |
6957 | .lcomm. */ | |
b782de16 | 6958 | if (symseg == bss_section |
252b5132 RH |
6959 | && ! S_IS_EXTERNAL (fix->fx_addsy)) |
6960 | { | |
b782de16 AM |
6961 | symbolS *sy = symbol_get_frag (fix->fx_addsy)->fr_symbol; |
6962 | ||
6963 | fix->fx_offset += val - resolve_symbol_value (sy); | |
6964 | fix->fx_addsy = sy; | |
252b5132 RH |
6965 | } |
6966 | ||
6967 | return 0; | |
6968 | } | |
6969 | ||
6970 | /* A reloc from one csect to another must be kept. The assembler | |
6971 | will, of course, keep relocs between sections, and it will keep | |
6972 | absolute relocs, but we need to force it to keep PC relative relocs | |
6973 | between two csects in the same section. */ | |
6974 | ||
6975 | int | |
98027b10 | 6976 | ppc_force_relocation (fixS *fix) |
252b5132 RH |
6977 | { |
6978 | /* At this point fix->fx_addsy should already have been converted to | |
6979 | a csect symbol. If the csect does not include the fragment, then | |
6980 | we need to force the relocation. */ | |
6981 | if (fix->fx_pcrel | |
6982 | && fix->fx_addsy != NULL | |
809ffe0d ILT |
6983 | && symbol_get_tc (fix->fx_addsy)->subseg != 0 |
6984 | && ((symbol_get_frag (fix->fx_addsy)->fr_address | |
6985 | > fix->fx_frag->fr_address) | |
6986 | || (symbol_get_tc (fix->fx_addsy)->next != NULL | |
6987 | && (symbol_get_frag (symbol_get_tc (fix->fx_addsy)->next)->fr_address | |
252b5132 RH |
6988 | <= fix->fx_frag->fr_address)))) |
6989 | return 1; | |
6990 | ||
ae6063d4 | 6991 | return generic_force_reloc (fix); |
252b5132 | 6992 | } |
252b5132 RH |
6993 | #endif /* OBJ_XCOFF */ |
6994 | ||
0baf16f2 | 6995 | #ifdef OBJ_ELF |
a161fe53 AM |
6996 | /* If this function returns non-zero, it guarantees that a relocation |
6997 | will be emitted for a fixup. */ | |
6998 | ||
6999 | int | |
98027b10 | 7000 | ppc_force_relocation (fixS *fix) |
a161fe53 AM |
7001 | { |
7002 | /* Branch prediction relocations must force a relocation, as must | |
7003 | the vtable description relocs. */ | |
7004 | switch (fix->fx_r_type) | |
7005 | { | |
7006 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
7007 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
7008 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
7009 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
c744ecf2 | 7010 | case BFD_RELOC_24_PLT_PCREL: |
a161fe53 | 7011 | case BFD_RELOC_PPC64_TOC: |
a161fe53 | 7012 | return 1; |
6911b7dc AM |
7013 | case BFD_RELOC_PPC_B26: |
7014 | case BFD_RELOC_PPC_BA26: | |
7015 | case BFD_RELOC_PPC_B16: | |
7016 | case BFD_RELOC_PPC_BA16: | |
05d0e962 | 7017 | case BFD_RELOC_PPC64_REL24_NOTOC: |
6911b7dc AM |
7018 | /* All branch fixups targeting a localentry symbol must |
7019 | force a relocation. */ | |
7020 | if (fix->fx_addsy) | |
7021 | { | |
7022 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
7023 | elf_symbol_type *elfsym | |
7024 | = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym); | |
7025 | gas_assert (elfsym); | |
7026 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
7027 | return 1; | |
7028 | } | |
7029 | break; | |
a161fe53 AM |
7030 | default: |
7031 | break; | |
7032 | } | |
7033 | ||
cdba85ec | 7034 | if (fix->fx_r_type >= BFD_RELOC_PPC_TLS |
c213164a | 7035 | && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL) |
cdba85ec AM |
7036 | return 1; |
7037 | ||
ae6063d4 | 7038 | return generic_force_reloc (fix); |
a161fe53 AM |
7039 | } |
7040 | ||
0baf16f2 | 7041 | int |
98027b10 | 7042 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 7043 | { |
6911b7dc AM |
7044 | switch (fix->fx_r_type) |
7045 | { | |
7046 | /* All branch fixups targeting a localentry symbol must | |
7047 | continue using the symbol. */ | |
7048 | case BFD_RELOC_PPC_B26: | |
7049 | case BFD_RELOC_PPC_BA26: | |
7050 | case BFD_RELOC_PPC_B16: | |
7051 | case BFD_RELOC_PPC_BA16: | |
7052 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
7053 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
7054 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
7055 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
05d0e962 | 7056 | case BFD_RELOC_PPC64_REL24_NOTOC: |
6911b7dc AM |
7057 | if (fix->fx_addsy) |
7058 | { | |
7059 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
7060 | elf_symbol_type *elfsym | |
7061 | = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym); | |
7062 | gas_assert (elfsym); | |
7063 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
7064 | return 0; | |
7065 | } | |
7066 | break; | |
7067 | default: | |
7068 | break; | |
7069 | } | |
7070 | ||
0baf16f2 AM |
7071 | return (fix->fx_r_type != BFD_RELOC_16_GOTOFF |
7072 | && fix->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
7073 | && fix->fx_r_type != BFD_RELOC_HI16_GOTOFF | |
7074 | && fix->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
cc9edbf3 AM |
7075 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_DS |
7076 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_LO_DS | |
334d91b9 AM |
7077 | && fix->fx_r_type != BFD_RELOC_16_GOT_PCREL |
7078 | && fix->fx_r_type != BFD_RELOC_32_GOTOFF | |
5663e321 | 7079 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT_PCREL34 |
334d91b9 AM |
7080 | && fix->fx_r_type != BFD_RELOC_24_PLT_PCREL |
7081 | && fix->fx_r_type != BFD_RELOC_32_PLTOFF | |
7082 | && fix->fx_r_type != BFD_RELOC_32_PLT_PCREL | |
7083 | && fix->fx_r_type != BFD_RELOC_LO16_PLTOFF | |
7084 | && fix->fx_r_type != BFD_RELOC_HI16_PLTOFF | |
7085 | && fix->fx_r_type != BFD_RELOC_HI16_S_PLTOFF | |
7086 | && fix->fx_r_type != BFD_RELOC_64_PLTOFF | |
7087 | && fix->fx_r_type != BFD_RELOC_64_PLT_PCREL | |
7088 | && fix->fx_r_type != BFD_RELOC_PPC64_PLT16_LO_DS | |
5663e321 | 7089 | && fix->fx_r_type != BFD_RELOC_PPC64_PLT_PCREL34 |
334d91b9 AM |
7090 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16 |
7091 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO | |
7092 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HI | |
7093 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HA | |
7094 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_DS | |
7095 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO_DS | |
0baf16f2 | 7096 | && fix->fx_r_type != BFD_RELOC_GPREL16 |
334d91b9 AM |
7097 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_LO16A |
7098 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HI16A | |
7099 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HA16A | |
0baf16f2 AM |
7100 | && fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT |
7101 | && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY | |
cdba85ec | 7102 | && !(fix->fx_r_type >= BFD_RELOC_PPC_TLS |
c213164a | 7103 | && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL)); |
252b5132 | 7104 | } |
0baf16f2 | 7105 | #endif |
252b5132 | 7106 | |
b9c361e0 JL |
7107 | void |
7108 | ppc_frag_check (struct frag *fragP) | |
7109 | { | |
a9479dc0 AM |
7110 | if ((fragP->fr_address & fragP->insn_addr) != 0) |
7111 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
7112 | _("instruction address is not a multiple of %d"), | |
7113 | fragP->insn_addr + 1); | |
b9c361e0 JL |
7114 | } |
7115 | ||
22f72c48 AM |
7116 | /* rs_align_code frag handling. */ |
7117 | ||
7118 | enum ppc_nop_encoding_for_rs_align_code | |
7119 | { | |
7120 | PPC_NOP_VANILLA, | |
7121 | PPC_NOP_VLE, | |
7122 | PPC_NOP_GROUP_P6, | |
7123 | PPC_NOP_GROUP_P7 | |
7124 | }; | |
7125 | ||
7126 | unsigned int | |
7127 | ppc_nop_select (void) | |
7128 | { | |
7129 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) | |
7130 | return PPC_NOP_VLE; | |
7131 | if ((ppc_cpu & (PPC_OPCODE_POWER9 | PPC_OPCODE_E500MC)) == 0) | |
7132 | { | |
7133 | if ((ppc_cpu & PPC_OPCODE_POWER7) != 0) | |
7134 | return PPC_NOP_GROUP_P7; | |
7135 | if ((ppc_cpu & PPC_OPCODE_POWER6) != 0) | |
7136 | return PPC_NOP_GROUP_P6; | |
7137 | } | |
7138 | return PPC_NOP_VANILLA; | |
7139 | } | |
3aeeedbb AM |
7140 | |
7141 | void | |
7142 | ppc_handle_align (struct frag *fragP) | |
7143 | { | |
7144 | valueT count = (fragP->fr_next->fr_address | |
7145 | - (fragP->fr_address + fragP->fr_fix)); | |
22f72c48 AM |
7146 | char *dest = fragP->fr_literal + fragP->fr_fix; |
7147 | enum ppc_nop_encoding_for_rs_align_code nop_select = *dest & 0xff; | |
7148 | ||
7149 | /* Pad with zeros if not inserting a whole number of instructions. | |
7150 | We could pad with zeros up to an instruction boundary then follow | |
7151 | with nops but odd counts indicate data in an executable section | |
7152 | so padding with zeros is most appropriate. */ | |
7153 | if (count == 0 | |
de626965 | 7154 | || (nop_select == PPC_NOP_VLE ? (count & 1) != 0 : (count & 3) != 0)) |
22f72c48 AM |
7155 | { |
7156 | *dest = 0; | |
7157 | return; | |
7158 | } | |
3aeeedbb | 7159 | |
22f72c48 | 7160 | if (nop_select == PPC_NOP_VLE) |
b9c361e0 | 7161 | { |
b9c361e0 JL |
7162 | |
7163 | fragP->fr_var = 2; | |
7164 | md_number_to_chars (dest, 0x4400, 2); | |
7165 | } | |
22f72c48 | 7166 | else |
3aeeedbb | 7167 | { |
3aeeedbb | 7168 | fragP->fr_var = 4; |
cef4f754 AM |
7169 | |
7170 | if (count > 4 * nop_limit && count < 0x2000000) | |
7171 | { | |
7172 | struct frag *rest; | |
7173 | ||
7174 | /* Make a branch, then follow with nops. Insert another | |
7175 | frag to handle the nops. */ | |
7176 | md_number_to_chars (dest, 0x48000000 + count, 4); | |
7177 | count -= 4; | |
7178 | if (count == 0) | |
7179 | return; | |
7180 | ||
7181 | rest = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
7182 | memcpy (rest, fragP, SIZEOF_STRUCT_FRAG); | |
7183 | fragP->fr_next = rest; | |
7184 | fragP = rest; | |
7185 | rest->fr_address += rest->fr_fix + 4; | |
7186 | rest->fr_fix = 0; | |
7187 | /* If we leave the next frag as rs_align_code we'll come here | |
7188 | again, resulting in a bunch of branches rather than a | |
7189 | branch followed by nops. */ | |
7190 | rest->fr_type = rs_align; | |
7191 | dest = rest->fr_literal; | |
7192 | } | |
7193 | ||
3aeeedbb AM |
7194 | md_number_to_chars (dest, 0x60000000, 4); |
7195 | ||
22f72c48 | 7196 | if (nop_select >= PPC_NOP_GROUP_P6) |
3aeeedbb | 7197 | { |
3fea0c3b AM |
7198 | /* For power6, power7, and power8, we want the last nop to |
7199 | be a group terminating one. Do this by inserting an | |
7200 | rs_fill frag immediately after this one, with its address | |
7201 | set to the last nop location. This will automatically | |
7202 | reduce the number of nops in the current frag by one. */ | |
3aeeedbb AM |
7203 | if (count > 4) |
7204 | { | |
7205 | struct frag *group_nop = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
7206 | ||
7207 | memcpy (group_nop, fragP, SIZEOF_STRUCT_FRAG); | |
7208 | group_nop->fr_address = group_nop->fr_next->fr_address - 4; | |
7209 | group_nop->fr_fix = 0; | |
7210 | group_nop->fr_offset = 1; | |
7211 | group_nop->fr_type = rs_fill; | |
7212 | fragP->fr_next = group_nop; | |
7213 | dest = group_nop->fr_literal; | |
7214 | } | |
7215 | ||
22f72c48 | 7216 | if (nop_select == PPC_NOP_GROUP_P6) |
42240548 PB |
7217 | /* power6 group terminating nop: "ori 1,1,0". */ |
7218 | md_number_to_chars (dest, 0x60210000, 4); | |
22f72c48 AM |
7219 | else |
7220 | /* power7/power8 group terminating nop: "ori 2,2,0". */ | |
7221 | md_number_to_chars (dest, 0x60420000, 4); | |
3aeeedbb AM |
7222 | } |
7223 | } | |
7224 | } | |
7225 | ||
252b5132 | 7226 | /* Apply a fixup to the object code. This is called for all the |
3b8b57a9 | 7227 | fixups we generated by the calls to fix_new_exp, above. */ |
252b5132 | 7228 | |
94f592af | 7229 | void |
62ebcb5c | 7230 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
252b5132 | 7231 | { |
94f592af | 7232 | valueT value = * valP; |
5656a981 AM |
7233 | offsetT fieldval; |
7234 | const struct powerpc_operand *operand; | |
252b5132 RH |
7235 | |
7236 | #ifdef OBJ_ELF | |
94f592af | 7237 | if (fixP->fx_addsy != NULL) |
252b5132 | 7238 | { |
a161fe53 | 7239 | /* Hack around bfd_install_relocation brain damage. */ |
94f592af NC |
7240 | if (fixP->fx_pcrel) |
7241 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
a680de9a PB |
7242 | |
7243 | if (fixP->fx_addsy == abs_section_sym) | |
7244 | fixP->fx_done = 1; | |
252b5132 RH |
7245 | } |
7246 | else | |
94f592af | 7247 | fixP->fx_done = 1; |
252b5132 | 7248 | #else |
a161fe53 | 7249 | /* FIXME FIXME FIXME: The value we are passed in *valP includes |
7be1c489 AM |
7250 | the symbol values. If we are doing this relocation the code in |
7251 | write.c is going to call bfd_install_relocation, which is also | |
7252 | going to use the symbol value. That means that if the reloc is | |
7253 | fully resolved we want to use *valP since bfd_install_relocation is | |
7254 | not being used. | |
9f0eb232 RS |
7255 | However, if the reloc is not fully resolved we do not want to |
7256 | use *valP, and must use fx_offset instead. If the relocation | |
7257 | is PC-relative, we then need to re-apply md_pcrel_from_section | |
7258 | to this new relocation value. */ | |
94f592af NC |
7259 | if (fixP->fx_addsy == (symbolS *) NULL) |
7260 | fixP->fx_done = 1; | |
7261 | ||
252b5132 | 7262 | else |
9f0eb232 RS |
7263 | { |
7264 | value = fixP->fx_offset; | |
7265 | if (fixP->fx_pcrel) | |
7266 | value -= md_pcrel_from_section (fixP, seg); | |
7267 | } | |
a161fe53 AM |
7268 | #endif |
7269 | ||
7ba71655 AM |
7270 | /* We are only able to convert some relocs to pc-relative. */ |
7271 | if (fixP->fx_pcrel) | |
7272 | { | |
7273 | switch (fixP->fx_r_type) | |
7274 | { | |
4a969973 AM |
7275 | case BFD_RELOC_64: |
7276 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
7277 | break; | |
7278 | ||
7279 | case BFD_RELOC_32: | |
7280 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
7281 | break; | |
7282 | ||
7283 | case BFD_RELOC_16: | |
7284 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
7285 | break; | |
7286 | ||
7ba71655 AM |
7287 | case BFD_RELOC_LO16: |
7288 | fixP->fx_r_type = BFD_RELOC_LO16_PCREL; | |
7289 | break; | |
7290 | ||
7291 | case BFD_RELOC_HI16: | |
7292 | fixP->fx_r_type = BFD_RELOC_HI16_PCREL; | |
7293 | break; | |
7294 | ||
7295 | case BFD_RELOC_HI16_S: | |
7296 | fixP->fx_r_type = BFD_RELOC_HI16_S_PCREL; | |
7297 | break; | |
7298 | ||
4a969973 AM |
7299 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
7300 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGH; | |
7ba71655 AM |
7301 | break; |
7302 | ||
4a969973 AM |
7303 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
7304 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHA; | |
7ba71655 AM |
7305 | break; |
7306 | ||
4a969973 AM |
7307 | case BFD_RELOC_PPC64_HIGHER: |
7308 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER; | |
7309 | break; | |
7310 | ||
7311 | case BFD_RELOC_PPC64_HIGHER_S: | |
7312 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA; | |
7313 | break; | |
7314 | ||
7315 | case BFD_RELOC_PPC64_HIGHEST: | |
7316 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST; | |
7317 | break; | |
7318 | ||
7319 | case BFD_RELOC_PPC64_HIGHEST_S: | |
7320 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA; | |
7ba71655 AM |
7321 | break; |
7322 | ||
5663e321 AM |
7323 | case BFD_RELOC_PPC64_ADDR16_HIGHER34: |
7324 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER34; | |
7325 | break; | |
7326 | ||
7327 | case BFD_RELOC_PPC64_ADDR16_HIGHERA34: | |
7328 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA34; | |
7329 | break; | |
7330 | ||
7331 | case BFD_RELOC_PPC64_ADDR16_HIGHEST34: | |
7332 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST34; | |
7333 | break; | |
7334 | ||
7335 | case BFD_RELOC_PPC64_ADDR16_HIGHESTA34: | |
7336 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA34; | |
7337 | break; | |
7338 | ||
7ba71655 AM |
7339 | case BFD_RELOC_PPC_16DX_HA: |
7340 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
7341 | break; | |
7342 | ||
5663e321 AM |
7343 | case BFD_RELOC_PPC64_D34: |
7344 | fixP->fx_r_type = BFD_RELOC_PPC64_PCREL34; | |
7345 | break; | |
7346 | ||
7347 | case BFD_RELOC_PPC64_D28: | |
7348 | fixP->fx_r_type = BFD_RELOC_PPC64_PCREL28; | |
7349 | break; | |
7350 | ||
7ba71655 AM |
7351 | default: |
7352 | break; | |
7353 | } | |
7354 | } | |
7355 | else if (!fixP->fx_done | |
7356 | && fixP->fx_r_type == BFD_RELOC_PPC_16DX_HA) | |
252b5132 | 7357 | { |
7ba71655 AM |
7358 | /* addpcis is relative to next insn address. */ |
7359 | value -= 4; | |
7360 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
7361 | fixP->fx_pcrel = 1; | |
252b5132 | 7362 | } |
252b5132 | 7363 | |
5656a981 | 7364 | operand = NULL; |
3b8b57a9 | 7365 | if (fixP->fx_pcrel_adjust != 0) |
252b5132 | 7366 | { |
5656a981 | 7367 | /* This is a fixup on an instruction. */ |
3b8b57a9 | 7368 | int opindex = fixP->fx_pcrel_adjust & 0xff; |
252b5132 | 7369 | |
5656a981 | 7370 | operand = &powerpc_operands[opindex]; |
252b5132 | 7371 | #ifdef OBJ_XCOFF |
0baf16f2 AM |
7372 | /* An instruction like `lwz 9,sym(30)' when `sym' is not a TOC symbol |
7373 | does not generate a reloc. It uses the offset of `sym' within its | |
7374 | csect. Other usages, such as `.long sym', generate relocs. This | |
7375 | is the documented behaviour of non-TOC symbols. */ | |
252b5132 | 7376 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
b84bf58a | 7377 | && (operand->bitm & 0xfff0) == 0xfff0 |
252b5132 | 7378 | && operand->shift == 0 |
2b3c4602 | 7379 | && (operand->insert == NULL || ppc_obj64) |
94f592af NC |
7380 | && fixP->fx_addsy != NULL |
7381 | && symbol_get_tc (fixP->fx_addsy)->subseg != 0 | |
96d56e9f NC |
7382 | && symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TC |
7383 | && symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TC0 | |
94f592af | 7384 | && S_GET_SEGMENT (fixP->fx_addsy) != bss_section) |
252b5132 | 7385 | { |
94f592af NC |
7386 | value = fixP->fx_offset; |
7387 | fixP->fx_done = 1; | |
252b5132 | 7388 | } |
ac21e7da TG |
7389 | |
7390 | /* During parsing of instructions, a TOC16 reloc is generated for | |
7391 | instructions such as 'lwz RT,SYM(RB)' if SYM is a symbol defined | |
7392 | in the toc. But at parse time, SYM may be not yet defined, so | |
7393 | check again here. */ | |
7394 | if (fixP->fx_r_type == BFD_RELOC_16 | |
7395 | && fixP->fx_addsy != NULL | |
7396 | && ppc_is_toc_sym (fixP->fx_addsy)) | |
7397 | fixP->fx_r_type = BFD_RELOC_PPC_TOC16; | |
252b5132 | 7398 | #endif |
5656a981 AM |
7399 | } |
7400 | ||
7401 | /* Calculate value to be stored in field. */ | |
7402 | fieldval = value; | |
7403 | switch (fixP->fx_r_type) | |
7404 | { | |
1ec2d25e | 7405 | #ifdef OBJ_ELF |
5656a981 AM |
7406 | case BFD_RELOC_PPC64_ADDR16_LO_DS: |
7407 | case BFD_RELOC_PPC_VLE_LO16A: | |
7408 | case BFD_RELOC_PPC_VLE_LO16D: | |
1ec2d25e | 7409 | #endif |
5656a981 AM |
7410 | case BFD_RELOC_LO16: |
7411 | case BFD_RELOC_LO16_PCREL: | |
7412 | fieldval = value & 0xffff; | |
7413 | sign_extend_16: | |
7414 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
f9c6b907 | 7415 | fieldval = SEX16 (fieldval); |
5656a981 AM |
7416 | fixP->fx_no_overflow = 1; |
7417 | break; | |
3c9d25f4 | 7418 | |
f9c6b907 AM |
7419 | case BFD_RELOC_HI16: |
7420 | case BFD_RELOC_HI16_PCREL: | |
5656a981 | 7421 | #ifdef OBJ_ELF |
f9c6b907 AM |
7422 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
7423 | { | |
7424 | fieldval = value >> 16; | |
7425 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
7426 | { | |
7427 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
7428 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
7429 | } | |
7430 | break; | |
7431 | } | |
2b0f3761 | 7432 | /* Fallthru */ |
f9c6b907 | 7433 | |
5656a981 AM |
7434 | case BFD_RELOC_PPC_VLE_HI16A: |
7435 | case BFD_RELOC_PPC_VLE_HI16D: | |
f9c6b907 | 7436 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
5656a981 | 7437 | #endif |
5656a981 AM |
7438 | fieldval = PPC_HI (value); |
7439 | goto sign_extend_16; | |
0baf16f2 | 7440 | |
f9c6b907 AM |
7441 | case BFD_RELOC_HI16_S: |
7442 | case BFD_RELOC_HI16_S_PCREL: | |
7ba71655 | 7443 | case BFD_RELOC_PPC_16DX_HA: |
a680de9a | 7444 | case BFD_RELOC_PPC_REL16DX_HA: |
5656a981 | 7445 | #ifdef OBJ_ELF |
f9c6b907 AM |
7446 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
7447 | { | |
7448 | fieldval = (value + 0x8000) >> 16; | |
7449 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
7450 | { | |
7451 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
7452 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
7453 | } | |
7454 | break; | |
7455 | } | |
2b0f3761 | 7456 | /* Fallthru */ |
f9c6b907 | 7457 | |
5656a981 AM |
7458 | case BFD_RELOC_PPC_VLE_HA16A: |
7459 | case BFD_RELOC_PPC_VLE_HA16D: | |
f9c6b907 | 7460 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
5656a981 | 7461 | #endif |
5656a981 AM |
7462 | fieldval = PPC_HA (value); |
7463 | goto sign_extend_16; | |
0baf16f2 | 7464 | |
3b8b57a9 | 7465 | #ifdef OBJ_ELF |
5656a981 AM |
7466 | case BFD_RELOC_PPC64_HIGHER: |
7467 | fieldval = PPC_HIGHER (value); | |
7468 | goto sign_extend_16; | |
252b5132 | 7469 | |
5656a981 AM |
7470 | case BFD_RELOC_PPC64_HIGHER_S: |
7471 | fieldval = PPC_HIGHERA (value); | |
7472 | goto sign_extend_16; | |
0baf16f2 | 7473 | |
5656a981 AM |
7474 | case BFD_RELOC_PPC64_HIGHEST: |
7475 | fieldval = PPC_HIGHEST (value); | |
7476 | goto sign_extend_16; | |
0baf16f2 | 7477 | |
5656a981 AM |
7478 | case BFD_RELOC_PPC64_HIGHEST_S: |
7479 | fieldval = PPC_HIGHESTA (value); | |
7480 | goto sign_extend_16; | |
7481 | #endif | |
7482 | ||
7483 | default: | |
7484 | break; | |
7485 | } | |
7486 | ||
7487 | if (operand != NULL) | |
7488 | { | |
7489 | /* Handle relocs in an insn. */ | |
5656a981 AM |
7490 | switch (fixP->fx_r_type) |
7491 | { | |
7fa9fcb6 | 7492 | #ifdef OBJ_ELF |
3b8b57a9 AM |
7493 | /* The following relocs can't be calculated by the assembler. |
7494 | Leave the field zero. */ | |
cdba85ec AM |
7495 | case BFD_RELOC_PPC_TPREL16: |
7496 | case BFD_RELOC_PPC_TPREL16_LO: | |
7497 | case BFD_RELOC_PPC_TPREL16_HI: | |
7498 | case BFD_RELOC_PPC_TPREL16_HA: | |
cdba85ec AM |
7499 | case BFD_RELOC_PPC_DTPREL16: |
7500 | case BFD_RELOC_PPC_DTPREL16_LO: | |
7501 | case BFD_RELOC_PPC_DTPREL16_HI: | |
7502 | case BFD_RELOC_PPC_DTPREL16_HA: | |
cdba85ec AM |
7503 | case BFD_RELOC_PPC_GOT_TLSGD16: |
7504 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
7505 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
7506 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
7507 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
7508 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
7509 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
7510 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
7511 | case BFD_RELOC_PPC_GOT_TPREL16: | |
7512 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
7513 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
7514 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
7515 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
7516 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
7517 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
7518 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
7519 | case BFD_RELOC_PPC64_TPREL16_DS: | |
7520 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
f9c6b907 AM |
7521 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
7522 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
cdba85ec AM |
7523 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
7524 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
7525 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
7526 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
f9c6b907 AM |
7527 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
7528 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
cdba85ec AM |
7529 | case BFD_RELOC_PPC64_DTPREL16_DS: |
7530 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
7531 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
7532 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
7533 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
7534 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
c213164a AM |
7535 | case BFD_RELOC_PPC64_TPREL34: |
7536 | case BFD_RELOC_PPC64_DTPREL34: | |
87c69f97 AM |
7537 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
7538 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
7539 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
7540 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
3b8b57a9 | 7541 | gas_assert (fixP->fx_addsy != NULL); |
7c1d0959 | 7542 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
3b8b57a9 | 7543 | fieldval = 0; |
cdba85ec | 7544 | break; |
3b8b57a9 AM |
7545 | |
7546 | /* These also should leave the field zero for the same | |
7547 | reason. Note that older versions of gas wrote values | |
7548 | here. If we want to go back to the old behaviour, then | |
7549 | all _LO and _LO_DS cases will need to be treated like | |
7550 | BFD_RELOC_LO16_PCREL above. Similarly for _HI etc. */ | |
7551 | case BFD_RELOC_16_GOTOFF: | |
7552 | case BFD_RELOC_LO16_GOTOFF: | |
7553 | case BFD_RELOC_HI16_GOTOFF: | |
7554 | case BFD_RELOC_HI16_S_GOTOFF: | |
7555 | case BFD_RELOC_LO16_PLTOFF: | |
7556 | case BFD_RELOC_HI16_PLTOFF: | |
7557 | case BFD_RELOC_HI16_S_PLTOFF: | |
7558 | case BFD_RELOC_GPREL16: | |
7559 | case BFD_RELOC_16_BASEREL: | |
7560 | case BFD_RELOC_LO16_BASEREL: | |
7561 | case BFD_RELOC_HI16_BASEREL: | |
7562 | case BFD_RELOC_HI16_S_BASEREL: | |
7563 | case BFD_RELOC_PPC_TOC16: | |
7564 | case BFD_RELOC_PPC64_TOC16_LO: | |
7565 | case BFD_RELOC_PPC64_TOC16_HI: | |
7566 | case BFD_RELOC_PPC64_TOC16_HA: | |
7567 | case BFD_RELOC_PPC64_PLTGOT16: | |
7568 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
7569 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
7570 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
7571 | case BFD_RELOC_PPC64_GOT16_DS: | |
7572 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
7573 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
7574 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
7575 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
7576 | case BFD_RELOC_PPC64_TOC16_DS: | |
7577 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
7578 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
7579 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
7580 | case BFD_RELOC_PPC_EMB_NADDR16: | |
7581 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
7582 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
7583 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
7584 | case BFD_RELOC_PPC_EMB_SDAI16: | |
7585 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
7586 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
252b5132 | 7587 | case BFD_RELOC_PPC_EMB_SDA21: |
3b8b57a9 AM |
7588 | case BFD_RELOC_PPC_EMB_MRKREF: |
7589 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
7590 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
7591 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
7592 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
7593 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
7594 | case BFD_RELOC_PPC_EMB_RELSDA: | |
7595 | case BFD_RELOC_PPC_VLE_SDA21: | |
7596 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
7597 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
7598 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
7599 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
7600 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
7601 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
7602 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
5663e321 AM |
7603 | case BFD_RELOC_PPC64_GOT_PCREL34: |
7604 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
3b8b57a9 | 7605 | gas_assert (fixP->fx_addsy != NULL); |
2b0f3761 | 7606 | /* Fallthru */ |
3b8b57a9 AM |
7607 | |
7608 | case BFD_RELOC_PPC_TLS: | |
7609 | case BFD_RELOC_PPC_TLSGD: | |
7610 | case BFD_RELOC_PPC_TLSLD: | |
c213164a | 7611 | case BFD_RELOC_PPC64_TLS_PCREL: |
3b8b57a9 | 7612 | fieldval = 0; |
3b8b57a9 | 7613 | break; |
7fa9fcb6 TG |
7614 | #endif |
7615 | ||
7616 | #ifdef OBJ_XCOFF | |
7617 | case BFD_RELOC_PPC_B16: | |
7618 | /* Adjust the offset to the instruction boundary. */ | |
7619 | fieldval += 2; | |
7620 | break; | |
7621 | #endif | |
252b5132 | 7622 | |
f728387b AM |
7623 | case BFD_RELOC_VTABLE_INHERIT: |
7624 | case BFD_RELOC_VTABLE_ENTRY: | |
7625 | case BFD_RELOC_PPC_DTPMOD: | |
7626 | case BFD_RELOC_PPC_TPREL: | |
7627 | case BFD_RELOC_PPC_DTPREL: | |
7628 | case BFD_RELOC_PPC_COPY: | |
7629 | case BFD_RELOC_PPC_GLOB_DAT: | |
7630 | case BFD_RELOC_32_PLT_PCREL: | |
7631 | case BFD_RELOC_PPC_EMB_NADDR32: | |
7632 | case BFD_RELOC_PPC64_TOC: | |
7633 | case BFD_RELOC_CTOR: | |
7634 | case BFD_RELOC_32: | |
7635 | case BFD_RELOC_32_PCREL: | |
7636 | case BFD_RELOC_RVA: | |
7637 | case BFD_RELOC_64: | |
7638 | case BFD_RELOC_64_PCREL: | |
7639 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
7640 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7641 | _("%s unsupported as instruction fixup"), | |
7642 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
7643 | fixP->fx_done = 1; | |
7644 | return; | |
7645 | ||
3b8b57a9 | 7646 | default: |
252b5132 | 7647 | break; |
3b8b57a9 | 7648 | } |
252b5132 | 7649 | |
3b8b57a9 AM |
7650 | #ifdef OBJ_ELF |
7651 | /* powerpc uses RELA style relocs, so if emitting a reloc the field | |
7652 | contents can stay at zero. */ | |
7653 | #define APPLY_RELOC fixP->fx_done | |
7654 | #else | |
7655 | #define APPLY_RELOC 1 | |
7656 | #endif | |
5663e321 AM |
7657 | /* We need to call the insert function even when fieldval is |
7658 | zero if the insert function would translate that zero to a | |
7659 | bit pattern other than all zeros. */ | |
3b8b57a9 AM |
7660 | if ((fieldval != 0 && APPLY_RELOC) || operand->insert != NULL) |
7661 | { | |
5663e321 | 7662 | uint64_t insn; |
487b24d8 AM |
7663 | unsigned char *where; |
7664 | ||
3b8b57a9 AM |
7665 | /* Fetch the instruction, insert the fully resolved operand |
7666 | value, and stuff the instruction back again. */ | |
487b24d8 | 7667 | where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
3b8b57a9 | 7668 | if (target_big_endian) |
31a91399 | 7669 | { |
5663e321 | 7670 | if (fixP->fx_size < 4) |
487b24d8 | 7671 | insn = bfd_getb16 (where); |
5663e321 AM |
7672 | else |
7673 | { | |
7674 | insn = bfd_getb32 (where); | |
7675 | if (fixP->fx_size > 4) | |
7676 | insn = insn << 32 | bfd_getb32 (where + 4); | |
7677 | } | |
31a91399 NC |
7678 | } |
7679 | else | |
3b8b57a9 | 7680 | { |
5663e321 | 7681 | if (fixP->fx_size < 4) |
487b24d8 | 7682 | insn = bfd_getl16 (where); |
5663e321 AM |
7683 | else |
7684 | { | |
7685 | insn = bfd_getl32 (where); | |
7686 | if (fixP->fx_size > 4) | |
7687 | insn = insn << 32 | bfd_getl32 (where + 4); | |
7688 | } | |
3b8b57a9 AM |
7689 | } |
7690 | insn = ppc_insert_operand (insn, operand, fieldval, | |
7691 | fixP->tc_fix_data.ppc_cpu, | |
7692 | fixP->fx_file, fixP->fx_line); | |
7693 | if (target_big_endian) | |
7694 | { | |
5663e321 | 7695 | if (fixP->fx_size < 4) |
487b24d8 | 7696 | bfd_putb16 (insn, where); |
5663e321 AM |
7697 | else |
7698 | { | |
7699 | if (fixP->fx_size > 4) | |
7700 | { | |
7701 | bfd_putb32 (insn, where + 4); | |
7702 | insn >>= 32; | |
7703 | } | |
7704 | bfd_putb32 (insn, where); | |
7705 | } | |
3b8b57a9 AM |
7706 | } |
7707 | else | |
7708 | { | |
5663e321 | 7709 | if (fixP->fx_size < 4) |
487b24d8 | 7710 | bfd_putl16 (insn, where); |
5663e321 AM |
7711 | else |
7712 | { | |
7713 | if (fixP->fx_size > 4) | |
7714 | { | |
7715 | bfd_putl32 (insn, where + 4); | |
7716 | insn >>= 32; | |
7717 | } | |
7718 | bfd_putl32 (insn, where); | |
7719 | } | |
3b8b57a9 AM |
7720 | } |
7721 | } | |
7722 | ||
7723 | if (fixP->fx_done) | |
7724 | /* Nothing else to do here. */ | |
7725 | return; | |
7726 | ||
7727 | gas_assert (fixP->fx_addsy != NULL); | |
62ebcb5c | 7728 | if (fixP->fx_r_type == BFD_RELOC_NONE) |
3b8b57a9 | 7729 | { |
3b4dbbbf | 7730 | const char *sfile; |
3b8b57a9 AM |
7731 | unsigned int sline; |
7732 | ||
7733 | /* Use expr_symbol_where to see if this is an expression | |
7734 | symbol. */ | |
7735 | if (expr_symbol_where (fixP->fx_addsy, &sfile, &sline)) | |
7736 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7737 | _("unresolved expression that must be resolved")); | |
7738 | else | |
7739 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7740 | _("unsupported relocation against %s"), | |
7741 | S_GET_NAME (fixP->fx_addsy)); | |
7742 | fixP->fx_done = 1; | |
7743 | return; | |
7744 | } | |
7745 | } | |
7746 | else | |
7747 | { | |
7748 | /* Handle relocs in data. */ | |
7749 | switch (fixP->fx_r_type) | |
7750 | { | |
252b5132 | 7751 | case BFD_RELOC_VTABLE_INHERIT: |
94f592af NC |
7752 | if (fixP->fx_addsy |
7753 | && !S_IS_DEFINED (fixP->fx_addsy) | |
7754 | && !S_IS_WEAK (fixP->fx_addsy)) | |
7755 | S_SET_WEAK (fixP->fx_addsy); | |
2b0f3761 | 7756 | /* Fallthru */ |
252b5132 RH |
7757 | |
7758 | case BFD_RELOC_VTABLE_ENTRY: | |
94f592af | 7759 | fixP->fx_done = 0; |
252b5132 RH |
7760 | break; |
7761 | ||
0baf16f2 | 7762 | #ifdef OBJ_ELF |
3b8b57a9 AM |
7763 | /* These can appear with @l etc. in data. */ |
7764 | case BFD_RELOC_LO16: | |
3b8b57a9 | 7765 | case BFD_RELOC_LO16_PCREL: |
3b8b57a9 | 7766 | case BFD_RELOC_HI16: |
3b8b57a9 | 7767 | case BFD_RELOC_HI16_PCREL: |
3b8b57a9 | 7768 | case BFD_RELOC_HI16_S: |
3b8b57a9 | 7769 | case BFD_RELOC_HI16_S_PCREL: |
3b8b57a9 | 7770 | case BFD_RELOC_PPC64_HIGHER: |
3b8b57a9 | 7771 | case BFD_RELOC_PPC64_HIGHER_S: |
3b8b57a9 | 7772 | case BFD_RELOC_PPC64_HIGHEST: |
3b8b57a9 | 7773 | case BFD_RELOC_PPC64_HIGHEST_S: |
f9c6b907 AM |
7774 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
7775 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
45965137 | 7776 | case BFD_RELOC_PPC64_ADDR64_LOCAL: |
3b8b57a9 AM |
7777 | break; |
7778 | ||
7779 | case BFD_RELOC_PPC_DTPMOD: | |
7780 | case BFD_RELOC_PPC_TPREL: | |
7781 | case BFD_RELOC_PPC_DTPREL: | |
7782 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7783 | break; | |
7784 | ||
7785 | /* Just punt all of these to the linker. */ | |
7786 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
7787 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
7788 | case BFD_RELOC_16_GOTOFF: | |
7789 | case BFD_RELOC_LO16_GOTOFF: | |
7790 | case BFD_RELOC_HI16_GOTOFF: | |
7791 | case BFD_RELOC_HI16_S_GOTOFF: | |
7792 | case BFD_RELOC_LO16_PLTOFF: | |
7793 | case BFD_RELOC_HI16_PLTOFF: | |
7794 | case BFD_RELOC_HI16_S_PLTOFF: | |
7795 | case BFD_RELOC_PPC_COPY: | |
7796 | case BFD_RELOC_PPC_GLOB_DAT: | |
7797 | case BFD_RELOC_16_BASEREL: | |
7798 | case BFD_RELOC_LO16_BASEREL: | |
7799 | case BFD_RELOC_HI16_BASEREL: | |
7800 | case BFD_RELOC_HI16_S_BASEREL: | |
7801 | case BFD_RELOC_PPC_TLS: | |
7802 | case BFD_RELOC_PPC_DTPREL16_LO: | |
7803 | case BFD_RELOC_PPC_DTPREL16_HI: | |
7804 | case BFD_RELOC_PPC_DTPREL16_HA: | |
7805 | case BFD_RELOC_PPC_TPREL16_LO: | |
7806 | case BFD_RELOC_PPC_TPREL16_HI: | |
7807 | case BFD_RELOC_PPC_TPREL16_HA: | |
7808 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
7809 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
7810 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
7811 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
7812 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
7813 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
7814 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
7815 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
7816 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
7817 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
7818 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
7819 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
7820 | case BFD_RELOC_PPC_GOT_TPREL16: | |
7821 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
7822 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
7823 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
7824 | case BFD_RELOC_24_PLT_PCREL: | |
7825 | case BFD_RELOC_PPC_LOCAL24PC: | |
7826 | case BFD_RELOC_32_PLT_PCREL: | |
7827 | case BFD_RELOC_GPREL16: | |
7828 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
7829 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
7830 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
7831 | case BFD_RELOC_PPC_EMB_NADDR32: | |
7832 | case BFD_RELOC_PPC_EMB_NADDR16: | |
7833 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
7834 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
7835 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
7836 | case BFD_RELOC_PPC_EMB_SDAI16: | |
7837 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
7838 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
7839 | case BFD_RELOC_PPC_EMB_SDA21: | |
7840 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
7841 | case BFD_RELOC_PPC_EMB_MRKREF: | |
7842 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
7843 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
7844 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
7845 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
7846 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
7847 | case BFD_RELOC_PPC_EMB_RELSDA: | |
0baf16f2 | 7848 | case BFD_RELOC_PPC64_TOC: |
3b8b57a9 AM |
7849 | case BFD_RELOC_PPC_TOC16: |
7850 | case BFD_RELOC_PPC64_TOC16_LO: | |
7851 | case BFD_RELOC_PPC64_TOC16_HI: | |
7852 | case BFD_RELOC_PPC64_TOC16_HA: | |
f9c6b907 AM |
7853 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
7854 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
3b8b57a9 AM |
7855 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: |
7856 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
7857 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
7858 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
f9c6b907 AM |
7859 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
7860 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
3b8b57a9 AM |
7861 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
7862 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
7863 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
7864 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
c213164a | 7865 | case BFD_RELOC_PPC64_TLS_PCREL: |
94f592af | 7866 | fixP->fx_done = 0; |
0baf16f2 | 7867 | break; |
0baf16f2 | 7868 | #endif |
3b8b57a9 AM |
7869 | |
7870 | #ifdef OBJ_XCOFF | |
7871 | case BFD_RELOC_NONE: | |
3b8b57a9 | 7872 | #endif |
5656a981 AM |
7873 | case BFD_RELOC_CTOR: |
7874 | case BFD_RELOC_32: | |
7875 | case BFD_RELOC_32_PCREL: | |
7876 | case BFD_RELOC_RVA: | |
7877 | case BFD_RELOC_64: | |
7878 | case BFD_RELOC_64_PCREL: | |
7879 | case BFD_RELOC_16: | |
7880 | case BFD_RELOC_16_PCREL: | |
7881 | case BFD_RELOC_8: | |
7882 | break; | |
3b8b57a9 | 7883 | |
252b5132 | 7884 | default: |
bc805888 | 7885 | fprintf (stderr, |
94f592af | 7886 | _("Gas failure, reloc value %d\n"), fixP->fx_r_type); |
99a814a1 | 7887 | fflush (stderr); |
252b5132 RH |
7888 | abort (); |
7889 | } | |
46b596ff | 7890 | |
5656a981 | 7891 | if (fixP->fx_size && APPLY_RELOC) |
46b596ff | 7892 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
5656a981 | 7893 | fieldval, fixP->fx_size); |
bf7279d5 AM |
7894 | if (warn_476 |
7895 | && (seg->flags & SEC_CODE) != 0 | |
7896 | && fixP->fx_size == 4 | |
7897 | && fixP->fx_done | |
7898 | && !fixP->fx_tcbit | |
7899 | && (fixP->fx_r_type == BFD_RELOC_32 | |
7900 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
7901 | || fixP->fx_r_type == BFD_RELOC_32_PCREL)) | |
7902 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
7903 | _("data in executable section")); | |
5656a981 AM |
7904 | } |
7905 | ||
252b5132 | 7906 | #ifdef OBJ_ELF |
3b8b57a9 | 7907 | ppc_elf_validate_fix (fixP, seg); |
94f592af | 7908 | fixP->fx_addnumber = value; |
4e6935a6 AM |
7909 | |
7910 | /* PowerPC uses RELA relocs, ie. the reloc addend is stored separately | |
7911 | from the section contents. If we are going to be emitting a reloc | |
7912 | then the section contents are immaterial, so don't warn if they | |
7913 | happen to overflow. Leave such warnings to ld. */ | |
7914 | if (!fixP->fx_done) | |
a38a07e0 AM |
7915 | { |
7916 | fixP->fx_no_overflow = 1; | |
7917 | ||
7918 | /* Arrange to emit .TOC. as a normal symbol if used in anything | |
7919 | but .TOC.@tocbase. */ | |
7920 | if (ppc_obj64 | |
7921 | && fixP->fx_r_type != BFD_RELOC_PPC64_TOC | |
7922 | && fixP->fx_addsy != NULL | |
7923 | && strcmp (S_GET_NAME (fixP->fx_addsy), ".TOC.") == 0) | |
7924 | symbol_get_bfdsym (fixP->fx_addsy)->flags |= BSF_KEEP; | |
7925 | } | |
252b5132 | 7926 | #else |
94f592af NC |
7927 | if (fixP->fx_r_type != BFD_RELOC_PPC_TOC16) |
7928 | fixP->fx_addnumber = 0; | |
252b5132 RH |
7929 | else |
7930 | { | |
7931 | #ifdef TE_PE | |
94f592af | 7932 | fixP->fx_addnumber = 0; |
252b5132 | 7933 | #else |
8edcbfcd TG |
7934 | /* We want to use the offset within the toc, not the actual VMA |
7935 | of the symbol. */ | |
fd361982 AM |
7936 | fixP->fx_addnumber = (- bfd_section_vma (S_GET_SEGMENT (fixP->fx_addsy)) |
7937 | - S_GET_VALUE (ppc_toc_csect)); | |
ac21e7da TG |
7938 | /* Set *valP to avoid errors. */ |
7939 | *valP = value; | |
252b5132 RH |
7940 | #endif |
7941 | } | |
7942 | #endif | |
252b5132 RH |
7943 | } |
7944 | ||
7945 | /* Generate a reloc for a fixup. */ | |
7946 | ||
7947 | arelent * | |
98027b10 | 7948 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
7949 | { |
7950 | arelent *reloc; | |
7951 | ||
325801bd | 7952 | reloc = XNEW (arelent); |
252b5132 | 7953 | |
325801bd | 7954 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
49309057 | 7955 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 | 7956 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
c213164a AM |
7957 | /* BFD_RELOC_PPC64_TLS_PCREL generates R_PPC64_TLS with an odd r_offset. */ |
7958 | if (fixp->fx_r_type == BFD_RELOC_PPC64_TLS_PCREL) | |
7959 | reloc->address++; | |
252b5132 RH |
7960 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
7961 | if (reloc->howto == (reloc_howto_type *) NULL) | |
7962 | { | |
7963 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
99a814a1 AM |
7964 | _("reloc %d not supported by object file format"), |
7965 | (int) fixp->fx_r_type); | |
252b5132 RH |
7966 | return NULL; |
7967 | } | |
7968 | reloc->addend = fixp->fx_addnumber; | |
7969 | ||
7970 | return reloc; | |
7971 | } | |
75e21f08 JJ |
7972 | |
7973 | void | |
98027b10 | 7974 | ppc_cfi_frame_initial_instructions (void) |
75e21f08 JJ |
7975 | { |
7976 | cfi_add_CFA_def_cfa (1, 0); | |
7977 | } | |
7978 | ||
7979 | int | |
1df69f4f | 7980 | tc_ppc_regname_to_dw2regnum (char *regname) |
75e21f08 JJ |
7981 | { |
7982 | unsigned int regnum = -1; | |
7983 | unsigned int i; | |
7984 | const char *p; | |
7985 | char *q; | |
e0471c16 | 7986 | static struct { const char *name; int dw2regnum; } regnames[] = |
75e21f08 JJ |
7987 | { |
7988 | { "sp", 1 }, { "r.sp", 1 }, { "rtoc", 2 }, { "r.toc", 2 }, | |
7989 | { "mq", 64 }, { "lr", 65 }, { "ctr", 66 }, { "ap", 67 }, | |
80f846b6 | 7990 | { "cr", 70 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 }, |
75e21f08 JJ |
7991 | { "spe_acc", 111 }, { "spefscr", 112 } |
7992 | }; | |
7993 | ||
7994 | for (i = 0; i < ARRAY_SIZE (regnames); ++i) | |
7995 | if (strcmp (regnames[i].name, regname) == 0) | |
7996 | return regnames[i].dw2regnum; | |
7997 | ||
7998 | if (regname[0] == 'r' || regname[0] == 'f' || regname[0] == 'v') | |
7999 | { | |
8000 | p = regname + 1 + (regname[1] == '.'); | |
8001 | regnum = strtoul (p, &q, 10); | |
8002 | if (p == q || *q || regnum >= 32) | |
8003 | return -1; | |
8004 | if (regname[0] == 'f') | |
b7d7dc63 | 8005 | regnum += 32; |
75e21f08 | 8006 | else if (regname[0] == 'v') |
b7d7dc63 | 8007 | regnum += 77; |
75e21f08 JJ |
8008 | } |
8009 | else if (regname[0] == 'c' && regname[1] == 'r') | |
8010 | { | |
8011 | p = regname + 2 + (regname[2] == '.'); | |
8012 | if (p[0] < '0' || p[0] > '7' || p[1]) | |
b7d7dc63 | 8013 | return -1; |
75e21f08 JJ |
8014 | regnum = p[0] - '0' + 68; |
8015 | } | |
8016 | return regnum; | |
8017 | } |