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Port dw2gencfi.c to str_htab.
[deliverable/binutils-gdb.git] / gas / config / tc-ppc.c
CommitLineData
252b5132 1/* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
b3adc24a 2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
252b5132
RH		 3 Written by Ian Lance Taylor, Cygnus Support.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
ec2655a6 9 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
252b5132 21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132 24#include "subsegs.h"
75e21f08 25#include "dw2gencfi.h"
252b5132
RH		 26#include "opcode/ppc.h"
27
28#ifdef OBJ_ELF
29#include "elf/ppc.h"
ee67d69a 30#include "elf/ppc64.h"
5d6f4f16 31#include "dwarf2dbg.h"
252b5132
RH		 32#endif
33
85645aed
TG		 34#ifdef OBJ_XCOFF
35#include "coff/xcoff.h"
36#include "libxcoff.h"
37#endif
38
252b5132
RH		 39/* This is the assembler for the PowerPC or POWER (RS/6000) chips. */
40
41/* Tell the main code what the endianness is. */
42extern int target_big_endian;
43
44/* Whether or not, we've set target_big_endian. */
45static int set_target_endian = 0;
46
47/* Whether to use user friendly register names. */
48#ifndef TARGET_REG_NAMES_P
b34976b6 49#define TARGET_REG_NAMES_P FALSE
252b5132 50#endif
252b5132 51
0baf16f2
AM		 52/* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST,
53 HIGHESTA. */
54
55/* #lo(value) denotes the least significant 16 bits of the indicated. */
56#define PPC_LO(v) ((v) & 0xffff)
57
58/* #hi(value) denotes bits 16 through 31 of the indicated value. */
59#define PPC_HI(v) (((v) >> 16) & 0xffff)
60
61/* #ha(value) denotes the high adjusted value: bits 16 through 31 of
62 the indicated value, compensating for #lo() being treated as a
63 signed number. */
15c1449b 64#define PPC_HA(v) PPC_HI ((v) + 0x8000)
0baf16f2
AM		 65
66/* #higher(value) denotes bits 32 through 47 of the indicated value. */
2a98c3a6 67#define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff)
0baf16f2
AM		 68
69/* #highera(value) denotes bits 32 through 47 of the indicated value,
70 compensating for #lo() being treated as a signed number. */
15c1449b 71#define PPC_HIGHERA(v) PPC_HIGHER ((v) + 0x8000)
0baf16f2
AM		 72
73/* #highest(value) denotes bits 48 through 63 of the indicated value. */
2a98c3a6 74#define PPC_HIGHEST(v) (((v) >> 24 >> 24) & 0xffff)
0baf16f2
AM		 75
76/* #highesta(value) denotes bits 48 through 63 of the indicated value,
15c1449b
AM		 77 compensating for #lo being treated as a signed number. */
78#define PPC_HIGHESTA(v) PPC_HIGHEST ((v) + 0x8000)
0baf16f2 79
f9c6b907
AM		 80#define SEX16(val) (((val) ^ 0x8000) - 0x8000)
81
82/* For the time being on ppc64, don't report overflow on @h and @ha
83 applied to constants. */
84#define REPORT_OVERFLOW_HI 0
0baf16f2 85
b34976b6 86static bfd_boolean reg_names_p = TARGET_REG_NAMES_P;
252b5132 87
98027b10
AM		 88static void ppc_macro (char *, const struct powerpc_macro *);
89static void ppc_byte (int);
0baf16f2
AM		 90
91#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
98027b10
AM		 92static void ppc_tc (int);
93static void ppc_machine (int);
0baf16f2 94#endif
252b5132
RH		 95
96#ifdef OBJ_XCOFF
98027b10
AM		 97static void ppc_comm (int);
98static void ppc_bb (int);
99static void ppc_bc (int);
100static void ppc_bf (int);
101static void ppc_biei (int);
102static void ppc_bs (int);
103static void ppc_eb (int);
104static void ppc_ec (int);
105static void ppc_ef (int);
106static void ppc_es (int);
107static void ppc_csect (int);
85645aed 108static void ppc_dwsect (int);
98027b10
AM		 109static void ppc_change_csect (symbolS *, offsetT);
110static void ppc_function (int);
111static void ppc_extern (int);
112static void ppc_lglobl (int);
c865e45b 113static void ppc_ref (int);
98027b10
AM		 114static void ppc_section (int);
115static void ppc_named_section (int);
116static void ppc_stabx (int);
117static void ppc_rename (int);
118static void ppc_toc (int);
119static void ppc_xcoff_cons (int);
120static void ppc_vbyte (int);
252b5132
RH		 121#endif
122
123#ifdef OBJ_ELF
98027b10
AM		 124static void ppc_elf_rdata (int);
125static void ppc_elf_lcomm (int);
6911b7dc 126static void ppc_elf_localentry (int);
ee67d69a 127static void ppc_elf_abiversion (int);
005d79fd 128static void ppc_elf_gnu_attribute (int);
252b5132 129#endif
252b5132
RH		 130\f
131/* Generic assembler global variables which must be defined by all
132 targets. */
133
134#ifdef OBJ_ELF
135/* This string holds the chars that always start a comment. If the
136 pre-processor is disabled, these aren't very useful. The macro
137 tc_comment_chars points to this. We use this, rather than the
138 usual comment_chars, so that we can switch for Solaris conventions. */
139static const char ppc_solaris_comment_chars[] = "#!";
140static const char ppc_eabi_comment_chars[] = "#";
141
142#ifdef TARGET_SOLARIS_COMMENT
143const char *ppc_comment_chars = ppc_solaris_comment_chars;
144#else
145const char *ppc_comment_chars = ppc_eabi_comment_chars;
146#endif
147#else
148const char comment_chars[] = "#";
149#endif
150
151/* Characters which start a comment at the beginning of a line. */
152const char line_comment_chars[] = "#";
153
154/* Characters which may be used to separate multiple commands on a
155 single line. */
156const char line_separator_chars[] = ";";
157
158/* Characters which are used to indicate an exponent in a floating
159 point number. */
160const char EXP_CHARS[] = "eE";
161
162/* Characters which mean that a number is a floating point constant,
163 as in 0d1.0. */
164const char FLT_CHARS[] = "dD";
5ce8663f 165
5e02f92e 166/* Anything that can start an operand needs to be mentioned here,
ac805826 167 to stop the input scrubber eating whitespace. */
5e02f92e 168const char ppc_symbol_chars[] = "%[";
75e21f08
JJ		 169
170/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
171int ppc_cie_data_alignment;
783de163 172
8fbf7334
JL		 173/* The dwarf2 minimum instruction length. */
174int ppc_dwarf2_line_min_insn_length;
175
cef4f754
AM		 176/* More than this number of nops in an alignment op gets a branch
177 instead. */
178unsigned long nop_limit = 4;
179
783de163
AM		 180/* The type of processor we are assembling for. This is one or more
181 of the PPC_OPCODE flags defined in opcode/ppc.h. */
fa452fa6 182ppc_cpu_t ppc_cpu = 0;
776fc418 183ppc_cpu_t sticky = 0;
01efc3af 184
ee67d69a
AM		 185/* Value for ELF e_flags EF_PPC64_ABI. */
186unsigned int ppc_abiversion = 0;
187
05f7541e 188#ifdef OBJ_ELF
01efc3af 189/* Flags set on encountering toc relocs. */
4f2a7b51 190static enum {
01efc3af
AM		 191 has_large_toc_reloc = 1,
192 has_small_toc_reloc = 2
193} toc_reloc_types;
05f7541e 194#endif
bf7279d5
AM		 195
196/* Warn on emitting data to code sections. */
197int warn_476;
0f873fd5 198uint64_t last_insn;
bf7279d5
AM		 199segT last_seg;
200subsegT last_subseg;
252b5132
RH		 201\f
202/* The target specific pseudo-ops which we support. */
203
204const pseudo_typeS md_pseudo_table[] =
205{
206 /* Pseudo-ops which must be overridden. */
207 { "byte", ppc_byte, 0 },
208
209#ifdef OBJ_XCOFF
210 /* Pseudo-ops specific to the RS/6000 XCOFF format. Some of these
211 legitimately belong in the obj-*.c file. However, XCOFF is based
212 on COFF, and is only implemented for the RS/6000. We just use
213 obj-coff.c, and add what we need here. */
214 { "comm", ppc_comm, 0 },
215 { "lcomm", ppc_comm, 1 },
216 { "bb", ppc_bb, 0 },
217 { "bc", ppc_bc, 0 },
218 { "bf", ppc_bf, 0 },
219 { "bi", ppc_biei, 0 },
220 { "bs", ppc_bs, 0 },
221 { "csect", ppc_csect, 0 },
85645aed 222 { "dwsect", ppc_dwsect, 0 },
252b5132
RH		 223 { "data", ppc_section, 'd' },
224 { "eb", ppc_eb, 0 },
225 { "ec", ppc_ec, 0 },
226 { "ef", ppc_ef, 0 },
227 { "ei", ppc_biei, 1 },
228 { "es", ppc_es, 0 },
229 { "extern", ppc_extern, 0 },
230 { "function", ppc_function, 0 },
231 { "lglobl", ppc_lglobl, 0 },
c865e45b 232 { "ref", ppc_ref, 0 },
252b5132
RH		 233 { "rename", ppc_rename, 0 },
234 { "section", ppc_named_section, 0 },
235 { "stabx", ppc_stabx, 0 },
236 { "text", ppc_section, 't' },
237 { "toc", ppc_toc, 0 },
238 { "long", ppc_xcoff_cons, 2 },
7f6d05e8 239 { "llong", ppc_xcoff_cons, 3 },
252b5132
RH		 240 { "word", ppc_xcoff_cons, 1 },
241 { "short", ppc_xcoff_cons, 1 },
242 { "vbyte", ppc_vbyte, 0 },
243#endif
244
245#ifdef OBJ_ELF
62ebcb5c 246 { "llong", cons, 8 },
252b5132
RH		 247 { "rdata", ppc_elf_rdata, 0 },
248 { "rodata", ppc_elf_rdata, 0 },
249 { "lcomm", ppc_elf_lcomm, 0 },
6911b7dc 250 { "localentry", ppc_elf_localentry, 0 },
ee67d69a 251 { "abiversion", ppc_elf_abiversion, 0 },
005d79fd 252 { "gnu_attribute", ppc_elf_gnu_attribute, 0},
252b5132
RH		 253#endif
254
0baf16f2 255#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
252b5132 256 { "tc", ppc_tc, 0 },
0baf16f2
AM		 257 { "machine", ppc_machine, 0 },
258#endif
252b5132
RH		 259
260 { NULL, NULL, 0 }
261};
262
263\f
99a814a1
AM		 264/* Predefined register names if -mregnames (or default for Windows NT).
265 In general, there are lots of them, in an attempt to be compatible
266 with a number of other Windows NT assemblers. */
252b5132
RH		 267
268/* Structure to hold information about predefined registers. */
269struct pd_reg
270 {
e0471c16 271 const char *name;
7e0de605
AM		 272 unsigned short value;
273 unsigned short flags;
252b5132
RH		 274 };
275
276/* List of registers that are pre-defined:
277
278 Each general register has predefined names of the form:
279 1. r<reg_num> which has the value <reg_num>.
280 2. r.<reg_num> which has the value <reg_num>.
281
252b5132
RH		 282 Each floating point register has predefined names of the form:
283 1. f<reg_num> which has the value <reg_num>.
284 2. f.<reg_num> which has the value <reg_num>.
285
7a899fff
C		 286 Each vector unit register has predefined names of the form:
287 1. v<reg_num> which has the value <reg_num>.
288 2. v.<reg_num> which has the value <reg_num>.
289
252b5132
RH		 290 Each condition register has predefined names of the form:
291 1. cr<reg_num> which has the value <reg_num>.
292 2. cr.<reg_num> which has the value <reg_num>.
293
294 There are individual registers as well:
295 sp or r.sp has the value 1
296 rtoc or r.toc has the value 2
252b5132
RH		 297 xer has the value 1
298 lr has the value 8
299 ctr has the value 9
252b5132
RH		 300 dar has the value 19
301 dsisr has the value 18
302 dec has the value 22
303 sdr1 has the value 25
304 srr0 has the value 26
305 srr1 has the value 27
306
81d4177b 307 The table is sorted. Suitable for searching by a binary search. */
252b5132
RH		 308
309static const struct pd_reg pre_defined_registers[] =
310{
aa3c112f
AM		 311 /* VSX accumulators. */
312 { "a0", 0, PPC_OPERAND_ACC },
313 { "a1", 1, PPC_OPERAND_ACC },
314 { "a2", 2, PPC_OPERAND_ACC },
315 { "a3", 3, PPC_OPERAND_ACC },
316 { "a4", 4, PPC_OPERAND_ACC },
317 { "a5", 5, PPC_OPERAND_ACC },
318 { "a6", 6, PPC_OPERAND_ACC },
319 { "a7", 7, PPC_OPERAND_ACC },
320
7e0de605
AM		 321 /* Condition Registers */
322 { "cr.0", 0, PPC_OPERAND_CR_REG },
323 { "cr.1", 1, PPC_OPERAND_CR_REG },
324 { "cr.2", 2, PPC_OPERAND_CR_REG },
325 { "cr.3", 3, PPC_OPERAND_CR_REG },
326 { "cr.4", 4, PPC_OPERAND_CR_REG },
327 { "cr.5", 5, PPC_OPERAND_CR_REG },
328 { "cr.6", 6, PPC_OPERAND_CR_REG },
329 { "cr.7", 7, PPC_OPERAND_CR_REG },
330
331 { "cr0", 0, PPC_OPERAND_CR_REG },
332 { "cr1", 1, PPC_OPERAND_CR_REG },
333 { "cr2", 2, PPC_OPERAND_CR_REG },
334 { "cr3", 3, PPC_OPERAND_CR_REG },
335 { "cr4", 4, PPC_OPERAND_CR_REG },
336 { "cr5", 5, PPC_OPERAND_CR_REG },
337 { "cr6", 6, PPC_OPERAND_CR_REG },
338 { "cr7", 7, PPC_OPERAND_CR_REG },
339
340 { "ctr", 9, PPC_OPERAND_SPR },
341 { "dar", 19, PPC_OPERAND_SPR },
342 { "dec", 22, PPC_OPERAND_SPR },
343 { "dsisr", 18, PPC_OPERAND_SPR },
344
345 /* Floating point registers */
346 { "f.0", 0, PPC_OPERAND_FPR },
347 { "f.1", 1, PPC_OPERAND_FPR },
348 { "f.10", 10, PPC_OPERAND_FPR },
349 { "f.11", 11, PPC_OPERAND_FPR },
350 { "f.12", 12, PPC_OPERAND_FPR },
351 { "f.13", 13, PPC_OPERAND_FPR },
352 { "f.14", 14, PPC_OPERAND_FPR },
353 { "f.15", 15, PPC_OPERAND_FPR },
354 { "f.16", 16, PPC_OPERAND_FPR },
355 { "f.17", 17, PPC_OPERAND_FPR },
356 { "f.18", 18, PPC_OPERAND_FPR },
357 { "f.19", 19, PPC_OPERAND_FPR },
358 { "f.2", 2, PPC_OPERAND_FPR },
359 { "f.20", 20, PPC_OPERAND_FPR },
360 { "f.21", 21, PPC_OPERAND_FPR },
361 { "f.22", 22, PPC_OPERAND_FPR },
362 { "f.23", 23, PPC_OPERAND_FPR },
363 { "f.24", 24, PPC_OPERAND_FPR },
364 { "f.25", 25, PPC_OPERAND_FPR },
365 { "f.26", 26, PPC_OPERAND_FPR },
366 { "f.27", 27, PPC_OPERAND_FPR },
367 { "f.28", 28, PPC_OPERAND_FPR },
368 { "f.29", 29, PPC_OPERAND_FPR },
369 { "f.3", 3, PPC_OPERAND_FPR },
370 { "f.30", 30, PPC_OPERAND_FPR },
371 { "f.31", 31, PPC_OPERAND_FPR },
372 { "f.32", 32, PPC_OPERAND_VSR },
373 { "f.33", 33, PPC_OPERAND_VSR },
374 { "f.34", 34, PPC_OPERAND_VSR },
375 { "f.35", 35, PPC_OPERAND_VSR },
376 { "f.36", 36, PPC_OPERAND_VSR },
377 { "f.37", 37, PPC_OPERAND_VSR },
378 { "f.38", 38, PPC_OPERAND_VSR },
379 { "f.39", 39, PPC_OPERAND_VSR },
380 { "f.4", 4, PPC_OPERAND_FPR },
381 { "f.40", 40, PPC_OPERAND_VSR },
382 { "f.41", 41, PPC_OPERAND_VSR },
383 { "f.42", 42, PPC_OPERAND_VSR },
384 { "f.43", 43, PPC_OPERAND_VSR },
385 { "f.44", 44, PPC_OPERAND_VSR },
386 { "f.45", 45, PPC_OPERAND_VSR },
387 { "f.46", 46, PPC_OPERAND_VSR },
388 { "f.47", 47, PPC_OPERAND_VSR },
389 { "f.48", 48, PPC_OPERAND_VSR },
390 { "f.49", 49, PPC_OPERAND_VSR },
391 { "f.5", 5, PPC_OPERAND_FPR },
392 { "f.50", 50, PPC_OPERAND_VSR },
393 { "f.51", 51, PPC_OPERAND_VSR },
394 { "f.52", 52, PPC_OPERAND_VSR },
395 { "f.53", 53, PPC_OPERAND_VSR },
396 { "f.54", 54, PPC_OPERAND_VSR },
397 { "f.55", 55, PPC_OPERAND_VSR },
398 { "f.56", 56, PPC_OPERAND_VSR },
399 { "f.57", 57, PPC_OPERAND_VSR },
400 { "f.58", 58, PPC_OPERAND_VSR },
401 { "f.59", 59, PPC_OPERAND_VSR },
402 { "f.6", 6, PPC_OPERAND_FPR },
403 { "f.60", 60, PPC_OPERAND_VSR },
404 { "f.61", 61, PPC_OPERAND_VSR },
405 { "f.62", 62, PPC_OPERAND_VSR },
406 { "f.63", 63, PPC_OPERAND_VSR },
407 { "f.7", 7, PPC_OPERAND_FPR },
408 { "f.8", 8, PPC_OPERAND_FPR },
409 { "f.9", 9, PPC_OPERAND_FPR },
410
411 { "f0", 0, PPC_OPERAND_FPR },
412 { "f1", 1, PPC_OPERAND_FPR },
413 { "f10", 10, PPC_OPERAND_FPR },
414 { "f11", 11, PPC_OPERAND_FPR },
415 { "f12", 12, PPC_OPERAND_FPR },
416 { "f13", 13, PPC_OPERAND_FPR },
417 { "f14", 14, PPC_OPERAND_FPR },
418 { "f15", 15, PPC_OPERAND_FPR },
419 { "f16", 16, PPC_OPERAND_FPR },
420 { "f17", 17, PPC_OPERAND_FPR },
421 { "f18", 18, PPC_OPERAND_FPR },
422 { "f19", 19, PPC_OPERAND_FPR },
423 { "f2", 2, PPC_OPERAND_FPR },
424 { "f20", 20, PPC_OPERAND_FPR },
425 { "f21", 21, PPC_OPERAND_FPR },
426 { "f22", 22, PPC_OPERAND_FPR },
427 { "f23", 23, PPC_OPERAND_FPR },
428 { "f24", 24, PPC_OPERAND_FPR },
429 { "f25", 25, PPC_OPERAND_FPR },
430 { "f26", 26, PPC_OPERAND_FPR },
431 { "f27", 27, PPC_OPERAND_FPR },
432 { "f28", 28, PPC_OPERAND_FPR },
433 { "f29", 29, PPC_OPERAND_FPR },
434 { "f3", 3, PPC_OPERAND_FPR },
435 { "f30", 30, PPC_OPERAND_FPR },
436 { "f31", 31, PPC_OPERAND_FPR },
437 { "f32", 32, PPC_OPERAND_VSR },
438 { "f33", 33, PPC_OPERAND_VSR },
439 { "f34", 34, PPC_OPERAND_VSR },
440 { "f35", 35, PPC_OPERAND_VSR },
441 { "f36", 36, PPC_OPERAND_VSR },
442 { "f37", 37, PPC_OPERAND_VSR },
443 { "f38", 38, PPC_OPERAND_VSR },
444 { "f39", 39, PPC_OPERAND_VSR },
445 { "f4", 4, PPC_OPERAND_FPR },
446 { "f40", 40, PPC_OPERAND_VSR },
447 { "f41", 41, PPC_OPERAND_VSR },
448 { "f42", 42, PPC_OPERAND_VSR },
449 { "f43", 43, PPC_OPERAND_VSR },
450 { "f44", 44, PPC_OPERAND_VSR },
451 { "f45", 45, PPC_OPERAND_VSR },
452 { "f46", 46, PPC_OPERAND_VSR },
453 { "f47", 47, PPC_OPERAND_VSR },
454 { "f48", 48, PPC_OPERAND_VSR },
455 { "f49", 49, PPC_OPERAND_VSR },
456 { "f5", 5, PPC_OPERAND_FPR },
457 { "f50", 50, PPC_OPERAND_VSR },
458 { "f51", 51, PPC_OPERAND_VSR },
459 { "f52", 52, PPC_OPERAND_VSR },
460 { "f53", 53, PPC_OPERAND_VSR },
461 { "f54", 54, PPC_OPERAND_VSR },
462 { "f55", 55, PPC_OPERAND_VSR },
463 { "f56", 56, PPC_OPERAND_VSR },
464 { "f57", 57, PPC_OPERAND_VSR },
465 { "f58", 58, PPC_OPERAND_VSR },
466 { "f59", 59, PPC_OPERAND_VSR },
467 { "f6", 6, PPC_OPERAND_FPR },
468 { "f60", 60, PPC_OPERAND_VSR },
469 { "f61", 61, PPC_OPERAND_VSR },
470 { "f62", 62, PPC_OPERAND_VSR },
471 { "f63", 63, PPC_OPERAND_VSR },
472 { "f7", 7, PPC_OPERAND_FPR },
473 { "f8", 8, PPC_OPERAND_FPR },
474 { "f9", 9, PPC_OPERAND_FPR },
252b5132 475
c3d65c1c 476 /* Quantization registers used with pair single instructions. */
7e0de605
AM		 477 { "gqr.0", 0, PPC_OPERAND_GQR },
478 { "gqr.1", 1, PPC_OPERAND_GQR },
479 { "gqr.2", 2, PPC_OPERAND_GQR },
480 { "gqr.3", 3, PPC_OPERAND_GQR },
481 { "gqr.4", 4, PPC_OPERAND_GQR },
482 { "gqr.5", 5, PPC_OPERAND_GQR },
483 { "gqr.6", 6, PPC_OPERAND_GQR },
484 { "gqr.7", 7, PPC_OPERAND_GQR },
485 { "gqr0", 0, PPC_OPERAND_GQR },
486 { "gqr1", 1, PPC_OPERAND_GQR },
487 { "gqr2", 2, PPC_OPERAND_GQR },
488 { "gqr3", 3, PPC_OPERAND_GQR },
489 { "gqr4", 4, PPC_OPERAND_GQR },
490 { "gqr5", 5, PPC_OPERAND_GQR },
491 { "gqr6", 6, PPC_OPERAND_GQR },
492 { "gqr7", 7, PPC_OPERAND_GQR },
493
494 { "lr", 8, PPC_OPERAND_SPR },
495
496 /* General Purpose Registers */
497 { "r.0", 0, PPC_OPERAND_GPR },
498 { "r.1", 1, PPC_OPERAND_GPR },
499 { "r.10", 10, PPC_OPERAND_GPR },
500 { "r.11", 11, PPC_OPERAND_GPR },
501 { "r.12", 12, PPC_OPERAND_GPR },
502 { "r.13", 13, PPC_OPERAND_GPR },
503 { "r.14", 14, PPC_OPERAND_GPR },
504 { "r.15", 15, PPC_OPERAND_GPR },
505 { "r.16", 16, PPC_OPERAND_GPR },
506 { "r.17", 17, PPC_OPERAND_GPR },
507 { "r.18", 18, PPC_OPERAND_GPR },
508 { "r.19", 19, PPC_OPERAND_GPR },
509 { "r.2", 2, PPC_OPERAND_GPR },
510 { "r.20", 20, PPC_OPERAND_GPR },
511 { "r.21", 21, PPC_OPERAND_GPR },
512 { "r.22", 22, PPC_OPERAND_GPR },
513 { "r.23", 23, PPC_OPERAND_GPR },
514 { "r.24", 24, PPC_OPERAND_GPR },
515 { "r.25", 25, PPC_OPERAND_GPR },
516 { "r.26", 26, PPC_OPERAND_GPR },
517 { "r.27", 27, PPC_OPERAND_GPR },
518 { "r.28", 28, PPC_OPERAND_GPR },
519 { "r.29", 29, PPC_OPERAND_GPR },
520 { "r.3", 3, PPC_OPERAND_GPR },
521 { "r.30", 30, PPC_OPERAND_GPR },
522 { "r.31", 31, PPC_OPERAND_GPR },
523 { "r.4", 4, PPC_OPERAND_GPR },
524 { "r.5", 5, PPC_OPERAND_GPR },
525 { "r.6", 6, PPC_OPERAND_GPR },
526 { "r.7", 7, PPC_OPERAND_GPR },
527 { "r.8", 8, PPC_OPERAND_GPR },
528 { "r.9", 9, PPC_OPERAND_GPR },
529
530 { "r.sp", 1, PPC_OPERAND_GPR },
531
532 { "r.toc", 2, PPC_OPERAND_GPR },
533
534 { "r0", 0, PPC_OPERAND_GPR },
535 { "r1", 1, PPC_OPERAND_GPR },
536 { "r10", 10, PPC_OPERAND_GPR },
537 { "r11", 11, PPC_OPERAND_GPR },
538 { "r12", 12, PPC_OPERAND_GPR },
539 { "r13", 13, PPC_OPERAND_GPR },
540 { "r14", 14, PPC_OPERAND_GPR },
541 { "r15", 15, PPC_OPERAND_GPR },
542 { "r16", 16, PPC_OPERAND_GPR },
543 { "r17", 17, PPC_OPERAND_GPR },
544 { "r18", 18, PPC_OPERAND_GPR },
545 { "r19", 19, PPC_OPERAND_GPR },
546 { "r2", 2, PPC_OPERAND_GPR },
547 { "r20", 20, PPC_OPERAND_GPR },
548 { "r21", 21, PPC_OPERAND_GPR },
549 { "r22", 22, PPC_OPERAND_GPR },
550 { "r23", 23, PPC_OPERAND_GPR },
551 { "r24", 24, PPC_OPERAND_GPR },
552 { "r25", 25, PPC_OPERAND_GPR },
553 { "r26", 26, PPC_OPERAND_GPR },
554 { "r27", 27, PPC_OPERAND_GPR },
555 { "r28", 28, PPC_OPERAND_GPR },
556 { "r29", 29, PPC_OPERAND_GPR },
557 { "r3", 3, PPC_OPERAND_GPR },
558 { "r30", 30, PPC_OPERAND_GPR },
559 { "r31", 31, PPC_OPERAND_GPR },
560 { "r4", 4, PPC_OPERAND_GPR },
561 { "r5", 5, PPC_OPERAND_GPR },
562 { "r6", 6, PPC_OPERAND_GPR },
563 { "r7", 7, PPC_OPERAND_GPR },
564 { "r8", 8, PPC_OPERAND_GPR },
565 { "r9", 9, PPC_OPERAND_GPR },
566
567 { "rtoc", 2, PPC_OPERAND_GPR },
568
569 { "sdr1", 25, PPC_OPERAND_SPR },
570
571 { "sp", 1, PPC_OPERAND_GPR },
572
573 { "srr0", 26, PPC_OPERAND_SPR },
574 { "srr1", 27, PPC_OPERAND_SPR },
575
576 /* Vector (Altivec/VMX) registers */
577 { "v.0", 0, PPC_OPERAND_VR },
578 { "v.1", 1, PPC_OPERAND_VR },
579 { "v.10", 10, PPC_OPERAND_VR },
580 { "v.11", 11, PPC_OPERAND_VR },
581 { "v.12", 12, PPC_OPERAND_VR },
582 { "v.13", 13, PPC_OPERAND_VR },
583 { "v.14", 14, PPC_OPERAND_VR },
584 { "v.15", 15, PPC_OPERAND_VR },
585 { "v.16", 16, PPC_OPERAND_VR },
586 { "v.17", 17, PPC_OPERAND_VR },
587 { "v.18", 18, PPC_OPERAND_VR },
588 { "v.19", 19, PPC_OPERAND_VR },
589 { "v.2", 2, PPC_OPERAND_VR },
590 { "v.20", 20, PPC_OPERAND_VR },
591 { "v.21", 21, PPC_OPERAND_VR },
592 { "v.22", 22, PPC_OPERAND_VR },
593 { "v.23", 23, PPC_OPERAND_VR },
594 { "v.24", 24, PPC_OPERAND_VR },
595 { "v.25", 25, PPC_OPERAND_VR },
596 { "v.26", 26, PPC_OPERAND_VR },
597 { "v.27", 27, PPC_OPERAND_VR },
598 { "v.28", 28, PPC_OPERAND_VR },
599 { "v.29", 29, PPC_OPERAND_VR },
600 { "v.3", 3, PPC_OPERAND_VR },
601 { "v.30", 30, PPC_OPERAND_VR },
602 { "v.31", 31, PPC_OPERAND_VR },
603 { "v.4", 4, PPC_OPERAND_VR },
604 { "v.5", 5, PPC_OPERAND_VR },
605 { "v.6", 6, PPC_OPERAND_VR },
606 { "v.7", 7, PPC_OPERAND_VR },
607 { "v.8", 8, PPC_OPERAND_VR },
608 { "v.9", 9, PPC_OPERAND_VR },
609
610 { "v0", 0, PPC_OPERAND_VR },
611 { "v1", 1, PPC_OPERAND_VR },
612 { "v10", 10, PPC_OPERAND_VR },
613 { "v11", 11, PPC_OPERAND_VR },
614 { "v12", 12, PPC_OPERAND_VR },
615 { "v13", 13, PPC_OPERAND_VR },
616 { "v14", 14, PPC_OPERAND_VR },
617 { "v15", 15, PPC_OPERAND_VR },
618 { "v16", 16, PPC_OPERAND_VR },
619 { "v17", 17, PPC_OPERAND_VR },
620 { "v18", 18, PPC_OPERAND_VR },
621 { "v19", 19, PPC_OPERAND_VR },
622 { "v2", 2, PPC_OPERAND_VR },
623 { "v20", 20, PPC_OPERAND_VR },
624 { "v21", 21, PPC_OPERAND_VR },
625 { "v22", 22, PPC_OPERAND_VR },
626 { "v23", 23, PPC_OPERAND_VR },
627 { "v24", 24, PPC_OPERAND_VR },
628 { "v25", 25, PPC_OPERAND_VR },
629 { "v26", 26, PPC_OPERAND_VR },
630 { "v27", 27, PPC_OPERAND_VR },
631 { "v28", 28, PPC_OPERAND_VR },
632 { "v29", 29, PPC_OPERAND_VR },
633 { "v3", 3, PPC_OPERAND_VR },
634 { "v30", 30, PPC_OPERAND_VR },
635 { "v31", 31, PPC_OPERAND_VR },
636 { "v4", 4, PPC_OPERAND_VR },
637 { "v5", 5, PPC_OPERAND_VR },
638 { "v6", 6, PPC_OPERAND_VR },
639 { "v7", 7, PPC_OPERAND_VR },
640 { "v8", 8, PPC_OPERAND_VR },
641 { "v9", 9, PPC_OPERAND_VR },
642
643 /* Vector Scalar (VSX) registers (ISA 2.06). */
644 { "vs.0", 0, PPC_OPERAND_VSR },
645 { "vs.1", 1, PPC_OPERAND_VSR },
646 { "vs.10", 10, PPC_OPERAND_VSR },
647 { "vs.11", 11, PPC_OPERAND_VSR },
648 { "vs.12", 12, PPC_OPERAND_VSR },
649 { "vs.13", 13, PPC_OPERAND_VSR },
650 { "vs.14", 14, PPC_OPERAND_VSR },
651 { "vs.15", 15, PPC_OPERAND_VSR },
652 { "vs.16", 16, PPC_OPERAND_VSR },
653 { "vs.17", 17, PPC_OPERAND_VSR },
654 { "vs.18", 18, PPC_OPERAND_VSR },
655 { "vs.19", 19, PPC_OPERAND_VSR },
656 { "vs.2", 2, PPC_OPERAND_VSR },
657 { "vs.20", 20, PPC_OPERAND_VSR },
658 { "vs.21", 21, PPC_OPERAND_VSR },
659 { "vs.22", 22, PPC_OPERAND_VSR },
660 { "vs.23", 23, PPC_OPERAND_VSR },
661 { "vs.24", 24, PPC_OPERAND_VSR },
662 { "vs.25", 25, PPC_OPERAND_VSR },
663 { "vs.26", 26, PPC_OPERAND_VSR },
664 { "vs.27", 27, PPC_OPERAND_VSR },
665 { "vs.28", 28, PPC_OPERAND_VSR },
666 { "vs.29", 29, PPC_OPERAND_VSR },
667 { "vs.3", 3, PPC_OPERAND_VSR },
668 { "vs.30", 30, PPC_OPERAND_VSR },
669 { "vs.31", 31, PPC_OPERAND_VSR },
670 { "vs.32", 32, PPC_OPERAND_VSR },
671 { "vs.33", 33, PPC_OPERAND_VSR },
672 { "vs.34", 34, PPC_OPERAND_VSR },
673 { "vs.35", 35, PPC_OPERAND_VSR },
674 { "vs.36", 36, PPC_OPERAND_VSR },
675 { "vs.37", 37, PPC_OPERAND_VSR },
676 { "vs.38", 38, PPC_OPERAND_VSR },
677 { "vs.39", 39, PPC_OPERAND_VSR },
678 { "vs.4", 4, PPC_OPERAND_VSR },
679 { "vs.40", 40, PPC_OPERAND_VSR },
680 { "vs.41", 41, PPC_OPERAND_VSR },
681 { "vs.42", 42, PPC_OPERAND_VSR },
682 { "vs.43", 43, PPC_OPERAND_VSR },
683 { "vs.44", 44, PPC_OPERAND_VSR },
684 { "vs.45", 45, PPC_OPERAND_VSR },
685 { "vs.46", 46, PPC_OPERAND_VSR },
686 { "vs.47", 47, PPC_OPERAND_VSR },
687 { "vs.48", 48, PPC_OPERAND_VSR },
688 { "vs.49", 49, PPC_OPERAND_VSR },
689 { "vs.5", 5, PPC_OPERAND_VSR },
690 { "vs.50", 50, PPC_OPERAND_VSR },
691 { "vs.51", 51, PPC_OPERAND_VSR },
692 { "vs.52", 52, PPC_OPERAND_VSR },
693 { "vs.53", 53, PPC_OPERAND_VSR },
694 { "vs.54", 54, PPC_OPERAND_VSR },
695 { "vs.55", 55, PPC_OPERAND_VSR },
696 { "vs.56", 56, PPC_OPERAND_VSR },
697 { "vs.57", 57, PPC_OPERAND_VSR },
698 { "vs.58", 58, PPC_OPERAND_VSR },
699 { "vs.59", 59, PPC_OPERAND_VSR },
700 { "vs.6", 6, PPC_OPERAND_VSR },
701 { "vs.60", 60, PPC_OPERAND_VSR },
702 { "vs.61", 61, PPC_OPERAND_VSR },
703 { "vs.62", 62, PPC_OPERAND_VSR },
704 { "vs.63", 63, PPC_OPERAND_VSR },
705 { "vs.7", 7, PPC_OPERAND_VSR },
706 { "vs.8", 8, PPC_OPERAND_VSR },
707 { "vs.9", 9, PPC_OPERAND_VSR },
708
709 { "vs0", 0, PPC_OPERAND_VSR },
710 { "vs1", 1, PPC_OPERAND_VSR },
711 { "vs10", 10, PPC_OPERAND_VSR },
712 { "vs11", 11, PPC_OPERAND_VSR },
713 { "vs12", 12, PPC_OPERAND_VSR },
714 { "vs13", 13, PPC_OPERAND_VSR },
715 { "vs14", 14, PPC_OPERAND_VSR },
716 { "vs15", 15, PPC_OPERAND_VSR },
717 { "vs16", 16, PPC_OPERAND_VSR },
718 { "vs17", 17, PPC_OPERAND_VSR },
719 { "vs18", 18, PPC_OPERAND_VSR },
720 { "vs19", 19, PPC_OPERAND_VSR },
721 { "vs2", 2, PPC_OPERAND_VSR },
722 { "vs20", 20, PPC_OPERAND_VSR },
723 { "vs21", 21, PPC_OPERAND_VSR },
724 { "vs22", 22, PPC_OPERAND_VSR },
725 { "vs23", 23, PPC_OPERAND_VSR },
726 { "vs24", 24, PPC_OPERAND_VSR },
727 { "vs25", 25, PPC_OPERAND_VSR },
728 { "vs26", 26, PPC_OPERAND_VSR },
729 { "vs27", 27, PPC_OPERAND_VSR },
730 { "vs28", 28, PPC_OPERAND_VSR },
731 { "vs29", 29, PPC_OPERAND_VSR },
732 { "vs3", 3, PPC_OPERAND_VSR },
733 { "vs30", 30, PPC_OPERAND_VSR },
734 { "vs31", 31, PPC_OPERAND_VSR },
735 { "vs32", 32, PPC_OPERAND_VSR },
736 { "vs33", 33, PPC_OPERAND_VSR },
737 { "vs34", 34, PPC_OPERAND_VSR },
738 { "vs35", 35, PPC_OPERAND_VSR },
739 { "vs36", 36, PPC_OPERAND_VSR },
740 { "vs37", 37, PPC_OPERAND_VSR },
741 { "vs38", 38, PPC_OPERAND_VSR },
742 { "vs39", 39, PPC_OPERAND_VSR },
743 { "vs4", 4, PPC_OPERAND_VSR },
744 { "vs40", 40, PPC_OPERAND_VSR },
745 { "vs41", 41, PPC_OPERAND_VSR },
746 { "vs42", 42, PPC_OPERAND_VSR },
747 { "vs43", 43, PPC_OPERAND_VSR },
748 { "vs44", 44, PPC_OPERAND_VSR },
749 { "vs45", 45, PPC_OPERAND_VSR },
750 { "vs46", 46, PPC_OPERAND_VSR },
751 { "vs47", 47, PPC_OPERAND_VSR },
752 { "vs48", 48, PPC_OPERAND_VSR },
753 { "vs49", 49, PPC_OPERAND_VSR },
754 { "vs5", 5, PPC_OPERAND_VSR },
755 { "vs50", 50, PPC_OPERAND_VSR },
756 { "vs51", 51, PPC_OPERAND_VSR },
757 { "vs52", 52, PPC_OPERAND_VSR },
758 { "vs53", 53, PPC_OPERAND_VSR },
759 { "vs54", 54, PPC_OPERAND_VSR },
760 { "vs55", 55, PPC_OPERAND_VSR },
761 { "vs56", 56, PPC_OPERAND_VSR },
762 { "vs57", 57, PPC_OPERAND_VSR },
763 { "vs58", 58, PPC_OPERAND_VSR },
764 { "vs59", 59, PPC_OPERAND_VSR },
765 { "vs6", 6, PPC_OPERAND_VSR },
766 { "vs60", 60, PPC_OPERAND_VSR },
767 { "vs61", 61, PPC_OPERAND_VSR },
768 { "vs62", 62, PPC_OPERAND_VSR },
769 { "vs63", 63, PPC_OPERAND_VSR },
770 { "vs7", 7, PPC_OPERAND_VSR },
771 { "vs8", 8, PPC_OPERAND_VSR },
772 { "vs9", 9, PPC_OPERAND_VSR },
773
774 { "xer", 1, PPC_OPERAND_SPR }
252b5132
RH		 775};
776
bc805888 777#define REG_NAME_CNT (sizeof (pre_defined_registers) / sizeof (struct pd_reg))
252b5132
RH		 778
779/* Given NAME, find the register number associated with that name, return
780 the integer value associated with the given name or -1 on failure. */
781
7e0de605 782static const struct pd_reg *
98027b10 783reg_name_search (const struct pd_reg *regs, int regcount, const char *name)
252b5132
RH		 784{
785 int middle, low, high;
786 int cmp;
787
788 low = 0;
789 high = regcount - 1;
790
791 do
792 {
793 middle = (low + high) / 2;
794 cmp = strcasecmp (name, regs[middle].name);
795 if (cmp < 0)
796 high = middle - 1;
797 else if (cmp > 0)
798 low = middle + 1;
799 else
7e0de605 800 return &regs[middle];
252b5132
RH		 801 }
802 while (low <= high);
803
7e0de605 804 return NULL;
252b5132
RH		 805}
806
807/*
99a814a1 808 * Summary of register_name.
252b5132
RH		 809 *
810 * in: Input_line_pointer points to 1st char of operand.
811 *
812 * out: A expressionS.
813 * The operand may have been a register: in this case, X_op == O_register,
814 * X_add_number is set to the register number, and truth is returned.
815 * Input_line_pointer->(next non-blank) char after operand, or is in its
816 * original state.
817 */
818
b34976b6 819static bfd_boolean
98027b10 820register_name (expressionS *expressionP)
252b5132 821{
7e0de605 822 const struct pd_reg *reg;
252b5132
RH		 823 char *name;
824 char *start;
825 char c;
826
99a814a1 827 /* Find the spelling of the operand. */
252b5132 828 start = name = input_line_pointer;
3882b010 829 if (name[0] == '%' && ISALPHA (name[1]))
252b5132
RH		 830 name = ++input_line_pointer;
831
3882b010 832 else if (!reg_names_p || !ISALPHA (name[0]))
b34976b6 833 return FALSE;
252b5132 834
d02603dc 835 c = get_symbol_name (&name);
7e0de605 836 reg = reg_name_search (pre_defined_registers, REG_NAME_CNT, name);
252b5132 837
468cced8
AM		 838 /* Put back the delimiting char. */
839 *input_line_pointer = c;
840
99a814a1 841 /* Look to see if it's in the register table. */
7e0de605 842 if (reg != NULL)
252b5132
RH		 843 {
844 expressionP->X_op = O_register;
7e0de605
AM		 845 expressionP->X_add_number = reg->value;
846 expressionP->X_md = reg->flags;
81d4177b 847
99a814a1 848 /* Make the rest nice. */
252b5132
RH		 849 expressionP->X_add_symbol = NULL;
850 expressionP->X_op_symbol = NULL;
b34976b6 851 return TRUE;
252b5132 852 }
468cced8
AM		 853
854 /* Reset the line as if we had not done anything. */
855 input_line_pointer = start;
b34976b6 856 return FALSE;
252b5132
RH		 857}
858\f
859/* This function is called for each symbol seen in an expression. It
860 handles the special parsing which PowerPC assemblers are supposed
861 to use for condition codes. */
862
863/* Whether to do the special parsing. */
b34976b6 864static bfd_boolean cr_operand;
252b5132
RH		 865
866/* Names to recognize in a condition code. This table is sorted. */
867static const struct pd_reg cr_names[] =
868{
7e0de605
AM		 869 { "cr0", 0, PPC_OPERAND_CR_REG },
870 { "cr1", 1, PPC_OPERAND_CR_REG },
871 { "cr2", 2, PPC_OPERAND_CR_REG },
872 { "cr3", 3, PPC_OPERAND_CR_REG },
873 { "cr4", 4, PPC_OPERAND_CR_REG },
874 { "cr5", 5, PPC_OPERAND_CR_REG },
875 { "cr6", 6, PPC_OPERAND_CR_REG },
876 { "cr7", 7, PPC_OPERAND_CR_REG },
877 { "eq", 2, PPC_OPERAND_CR_BIT },
878 { "gt", 1, PPC_OPERAND_CR_BIT },
879 { "lt", 0, PPC_OPERAND_CR_BIT },
880 { "so", 3, PPC_OPERAND_CR_BIT },
881 { "un", 3, PPC_OPERAND_CR_BIT }
252b5132
RH		 882};
883
884/* Parsing function. This returns non-zero if it recognized an
885 expression. */
886
887int
91d6fa6a 888ppc_parse_name (const char *name, expressionS *exp)
252b5132 889{
7e0de605 890 const struct pd_reg *reg;
252b5132
RH		 891
892 if (! cr_operand)
893 return 0;
894
13abbae3
AM		 895 if (*name == '%')
896 ++name;
7e0de605 897 reg = reg_name_search (cr_names, sizeof cr_names / sizeof cr_names[0],
252b5132 898 name);
7e0de605 899 if (reg == NULL)
252b5132
RH		 900 return 0;
901
7e0de605
AM		 902 exp->X_op = O_register;
903 exp->X_add_number = reg->value;
904 exp->X_md = reg->flags;
252b5132
RH		 905
906 return 1;
907}
7e0de605
AM		 908
909/* Propagate X_md and check register expressions. This is to support
910 condition codes like 4*cr5+eq. */
911
912int
913ppc_optimize_expr (expressionS *left, operatorT op, expressionS *right)
914{
915 /* Accept 4*cr<n> and cr<n>*4. */
916 if (op == O_multiply
917 && ((right->X_op == O_register
918 && right->X_md == PPC_OPERAND_CR_REG
919 && left->X_op == O_constant
920 && left->X_add_number == 4)
921 || (left->X_op == O_register
922 && left->X_md == PPC_OPERAND_CR_REG
923 && right->X_op == O_constant
924 && right->X_add_number == 4)))
925 {
926 left->X_op = O_register;
927 left->X_md = PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT;
928 left->X_add_number *= right->X_add_number;
929 return 1;
930 }
931
932 /* Accept the above plus <cr bit>, and <cr bit> plus the above. */
933 if (right->X_op == O_register
934 && left->X_op == O_register
935 && op == O_add
936 && ((right->X_md == PPC_OPERAND_CR_BIT
937 && left->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT))
938 || (right->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT)
939 && left->X_md == PPC_OPERAND_CR_BIT)))
940 {
941 left->X_md = PPC_OPERAND_CR_BIT;
942 right->X_op = O_constant;
943 return 0;
944 }
945
946 /* Accept reg +/- constant. */
947 if (left->X_op == O_register
948 && !((op == O_add || op == O_subtract) && right->X_op == O_constant))
ece5dcc1 949 as_warn (_("invalid register expression"));
7e0de605
AM		 950
951 /* Accept constant + reg. */
952 if (right->X_op == O_register)
953 {
954 if (op == O_add && left->X_op == O_constant)
955 left->X_md = right->X_md;
956 else
ece5dcc1 957 as_warn (_("invalid register expression"));
7e0de605
AM		 958 }
959
960 return 0;
961}
252b5132
RH		 962\f
963/* Local variables. */
964
2b3c4602
AM		 965/* Whether to target xcoff64/elf64. */
966static unsigned int ppc_obj64 = BFD_DEFAULT_TARGET_SIZE == 64;
7f6d05e8 967
252b5132
RH		 968/* Opcode hash table. */
969static struct hash_control *ppc_hash;
970
971/* Macro hash table. */
972static struct hash_control *ppc_macro_hash;
973
974#ifdef OBJ_ELF
99a814a1 975/* What type of shared library support to use. */
5d6f4f16 976static enum { SHLIB_NONE, SHLIB_PIC, SHLIB_MRELOCATABLE } shlib = SHLIB_NONE;
252b5132 977
99a814a1 978/* Flags to set in the elf header. */
252b5132
RH		 979static flagword ppc_flags = 0;
980
981/* Whether this is Solaris or not. */
982#ifdef TARGET_SOLARIS_COMMENT
b34976b6 983#define SOLARIS_P TRUE
252b5132 984#else
b34976b6 985#define SOLARIS_P FALSE
252b5132
RH		 986#endif
987
b34976b6 988static bfd_boolean msolaris = SOLARIS_P;
252b5132
RH		 989#endif
990
991#ifdef OBJ_XCOFF
992
993/* The RS/6000 assembler uses the .csect pseudo-op to generate code
994 using a bunch of different sections. These assembler sections,
995 however, are all encompassed within the .text or .data sections of
996 the final output file. We handle this by using different
997 subsegments within these main segments. */
998
999/* Next subsegment to allocate within the .text segment. */
1000static subsegT ppc_text_subsegment = 2;
1001
1002/* Linked list of csects in the text section. */
1003static symbolS *ppc_text_csects;
1004
1005/* Next subsegment to allocate within the .data segment. */
1006static subsegT ppc_data_subsegment = 2;
1007
1008/* Linked list of csects in the data section. */
1009static symbolS *ppc_data_csects;
1010
1011/* The current csect. */
1012static symbolS *ppc_current_csect;
1013
1014/* The RS/6000 assembler uses a TOC which holds addresses of functions
1015 and variables. Symbols are put in the TOC with the .tc pseudo-op.
1016 A special relocation is used when accessing TOC entries. We handle
1017 the TOC as a subsegment within the .data segment. We set it up if
1018 we see a .toc pseudo-op, and save the csect symbol here. */
1019static symbolS *ppc_toc_csect;
1020
1021/* The first frag in the TOC subsegment. */
1022static fragS *ppc_toc_frag;
1023
1024/* The first frag in the first subsegment after the TOC in the .data
1025 segment. NULL if there are no subsegments after the TOC. */
1026static fragS *ppc_after_toc_frag;
1027
1028/* The current static block. */
1029static symbolS *ppc_current_block;
1030
1031/* The COFF debugging section; set by md_begin. This is not the
1032 .debug section, but is instead the secret BFD section which will
1033 cause BFD to set the section number of a symbol to N_DEBUG. */
1034static asection *ppc_coff_debug_section;
1035
85645aed
TG		 1036/* Structure to set the length field of the dwarf sections. */
1037struct dw_subsection {
1038 /* Subsections are simply linked. */
1039 struct dw_subsection *link;
1040
1041 /* The subsection number. */
1042 subsegT subseg;
1043
1044 /* Expression to compute the length of the section. */
1045 expressionS end_exp;
1046};
1047
1048static struct dw_section {
1049 /* Corresponding section. */
1050 segT sect;
1051
1052 /* Simply linked list of subsections with a label. */
1053 struct dw_subsection *list_subseg;
1054
1055 /* The anonymous subsection. */
1056 struct dw_subsection *anon_subseg;
1057} dw_sections[XCOFF_DWSECT_NBR_NAMES];
252b5132
RH		 1058#endif /* OBJ_XCOFF */
1059
252b5132
RH		 1060#ifdef OBJ_ELF
1061symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */
6a0c61b7
EZ		 1062unsigned long *ppc_apuinfo_list;
1063unsigned int ppc_apuinfo_num;
1064unsigned int ppc_apuinfo_num_alloc;
252b5132
RH		 1065#endif /* OBJ_ELF */
1066\f
1067#ifdef OBJ_ELF
15c1449b 1068const char *const md_shortopts = "b:l:usm:K:VQ:";
252b5132 1069#else
15c1449b 1070const char *const md_shortopts = "um:";
252b5132 1071#endif
cef4f754 1072#define OPTION_NOPS (OPTION_MD_BASE + 0)
15c1449b 1073const struct option md_longopts[] = {
cef4f754 1074 {"nops", required_argument, NULL, OPTION_NOPS},
bf7279d5
AM		 1075 {"ppc476-workaround", no_argument, &warn_476, 1},
1076 {"no-ppc476-workaround", no_argument, &warn_476, 0},
252b5132
RH		 1077 {NULL, no_argument, NULL, 0}
1078};
15c1449b 1079const size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 1080
1081int
17b9d67d 1082md_parse_option (int c, const char *arg)
252b5132 1083{
69fe9ce5
AM		 1084 ppc_cpu_t new_cpu;
1085
252b5132
RH		 1086 switch (c)
1087 {
1088 case 'u':
1089 /* -u means that any undefined symbols should be treated as
1090 external, which is the default for gas anyhow. */
1091 break;
1092
1093#ifdef OBJ_ELF
1094 case 'l':
1095 /* Solaris as takes -le (presumably for little endian). For completeness
99a814a1 1096 sake, recognize -be also. */
252b5132
RH		 1097 if (strcmp (arg, "e") == 0)
1098 {
1099 target_big_endian = 0;
1100 set_target_endian = 1;
b9c361e0 1101 if (ppc_cpu & PPC_OPCODE_VLE)
d6ed37ed 1102 as_bad (_("the use of -mvle requires big endian."));
252b5132
RH		 1103 }
1104 else
1105 return 0;
1106
1107 break;
1108
1109 case 'b':
1110 if (strcmp (arg, "e") == 0)
1111 {
1112 target_big_endian = 1;
1113 set_target_endian = 1;
1114 }
1115 else
1116 return 0;
1117
1118 break;
1119
1120 case 'K':
99a814a1 1121 /* Recognize -K PIC. */
252b5132
RH		 1122 if (strcmp (arg, "PIC") == 0 || strcmp (arg, "pic") == 0)
1123 {
1124 shlib = SHLIB_PIC;
1125 ppc_flags |= EF_PPC_RELOCATABLE_LIB;
1126 }
1127 else
1128 return 0;
1129
1130 break;
1131#endif
1132
7f6d05e8
CP		 1133 /* a64 and a32 determine whether to use XCOFF64 or XCOFF32. */
1134 case 'a':
1135 if (strcmp (arg, "64") == 0)
2a98c3a6
AM		 1136 {
1137#ifdef BFD64
1138 ppc_obj64 = 1;
d6ed37ed
AM		 1139 if (ppc_cpu & PPC_OPCODE_VLE)
1140 as_bad (_("the use of -mvle requires -a32."));
2a98c3a6
AM		 1141#else
1142 as_fatal (_("%s unsupported"), "-a64");
1143#endif
1144 }
7f6d05e8 1145 else if (strcmp (arg, "32") == 0)
2b3c4602 1146 ppc_obj64 = 0;
7f6d05e8
CP		 1147 else
1148 return 0;
1149 break;
81d4177b 1150
252b5132 1151 case 'm':
776fc418 1152 new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, arg);
52be03fd
AM		 1153 /* "raw" is only valid for the disassembler. */
1154 if (new_cpu != 0 && (new_cpu & PPC_OPCODE_RAW) == 0)
b9c361e0
JL		 1155 {
1156 ppc_cpu = new_cpu;
d6ed37ed
AM		 1157 if (strcmp (arg, "vle") == 0)
1158 {
1159 if (set_target_endian && target_big_endian == 0)
1160 as_bad (_("the use of -mvle requires big endian."));
1161 if (ppc_obj64)
1162 as_bad (_("the use of -mvle requires -a32."));
1163 }
b9c361e0 1164 }
252b5132 1165
83eef883
AFB		 1166 else if (strcmp (arg, "no-vle") == 0)
1167 {
1168 sticky &= ~PPC_OPCODE_VLE;
1169
1170 new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, "booke");
1171 new_cpu &= ~PPC_OPCODE_VLE;
1172
1173 ppc_cpu = new_cpu;
1174 }
1175
252b5132 1176 else if (strcmp (arg, "regnames") == 0)
b34976b6 1177 reg_names_p = TRUE;
252b5132
RH		 1178
1179 else if (strcmp (arg, "no-regnames") == 0)
b34976b6 1180 reg_names_p = FALSE;
252b5132
RH		 1181
1182#ifdef OBJ_ELF
99a814a1
AM		 1183 /* -mrelocatable/-mrelocatable-lib -- warn about initializations
1184 that require relocation. */
252b5132
RH		 1185 else if (strcmp (arg, "relocatable") == 0)
1186 {
5d6f4f16 1187 shlib = SHLIB_MRELOCATABLE;
252b5132
RH		 1188 ppc_flags |= EF_PPC_RELOCATABLE;
1189 }
1190
1191 else if (strcmp (arg, "relocatable-lib") == 0)
1192 {
5d6f4f16 1193 shlib = SHLIB_MRELOCATABLE;
252b5132
RH		 1194 ppc_flags |= EF_PPC_RELOCATABLE_LIB;
1195 }
1196
99a814a1 1197 /* -memb, set embedded bit. */
252b5132
RH		 1198 else if (strcmp (arg, "emb") == 0)
1199 ppc_flags |= EF_PPC_EMB;
1200
cc643b88 1201 /* -mlittle/-mbig set the endianness. */
99a814a1
AM		 1202 else if (strcmp (arg, "little") == 0
1203 || strcmp (arg, "little-endian") == 0)
252b5132
RH		 1204 {
1205 target_big_endian = 0;
1206 set_target_endian = 1;
b9c361e0 1207 if (ppc_cpu & PPC_OPCODE_VLE)
d6ed37ed 1208 as_bad (_("the use of -mvle requires big endian."));
252b5132
RH		 1209 }
1210
1211 else if (strcmp (arg, "big") == 0 || strcmp (arg, "big-endian") == 0)
1212 {
1213 target_big_endian = 1;
1214 set_target_endian = 1;
1215 }
1216
1217 else if (strcmp (arg, "solaris") == 0)
1218 {
b34976b6 1219 msolaris = TRUE;
252b5132
RH		 1220 ppc_comment_chars = ppc_solaris_comment_chars;
1221 }
1222
1223 else if (strcmp (arg, "no-solaris") == 0)
1224 {
b34976b6 1225 msolaris = FALSE;
252b5132
RH		 1226 ppc_comment_chars = ppc_eabi_comment_chars;
1227 }
74081948
AF		 1228 else if (strcmp (arg, "spe2") == 0)
1229 {
1230 ppc_cpu |= PPC_OPCODE_SPE2;
1231 }
252b5132
RH		 1232#endif
1233 else
1234 {
1235 as_bad (_("invalid switch -m%s"), arg);
1236 return 0;
1237 }
1238 break;
1239
1240#ifdef OBJ_ELF
1241 /* -V: SVR4 argument to print version ID. */
1242 case 'V':
1243 print_version_id ();
1244 break;
1245
1246 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
1247 should be emitted or not. FIXME: Not implemented. */
1248 case 'Q':
1249 break;
1250
1251 /* Solaris takes -s to specify that .stabs go in a .stabs section,
1252 rather than .stabs.excl, which is ignored by the linker.
1253 FIXME: Not implemented. */
1254 case 's':
1255 if (arg)
1256 return 0;
1257
1258 break;
1259#endif
1260
cef4f754
AM		 1261 case OPTION_NOPS:
1262 {
1263 char *end;
1264 nop_limit = strtoul (optarg, &end, 0);
1265 if (*end)
1266 as_bad (_("--nops needs a numeric argument"));
1267 }
1268 break;
85645aed 1269
bf7279d5
AM		 1270 case 0:
1271 break;
1272
252b5132
RH		 1273 default:
1274 return 0;
1275 }
1276
1277 return 1;
1278}
1279
5f63875b
AM		 1280static int
1281is_ppc64_target (const bfd_target *targ, void *data ATTRIBUTE_UNUSED)
1282{
1283 switch (targ->flavour)
1284 {
1285#ifdef OBJ_ELF
1286 case bfd_target_elf_flavour:
1287 return strncmp (targ->name, "elf64-powerpc", 13) == 0;
1288#endif
1289#ifdef OBJ_XCOFF
1290 case bfd_target_xcoff_flavour:
1291 return (strcmp (targ->name, "aixcoff64-rs6000") == 0
1292 || strcmp (targ->name, "aix5coff64-rs6000") == 0);
1293#endif
1294 default:
1295 return 0;
1296 }
1297}
1298
252b5132 1299void
98027b10 1300md_show_usage (FILE *stream)
252b5132 1301{
bc805888 1302 fprintf (stream, _("\
5f63875b
AM		 1303PowerPC options:\n"));
1304 fprintf (stream, _("\
1305-a32 generate ELF32/XCOFF32\n"));
1306 if (bfd_iterate_over_targets (is_ppc64_target, NULL))
1307 fprintf (stream, _("\
1308-a64 generate ELF64/XCOFF64\n"));
1309 fprintf (stream, _("\
1310-u ignored\n"));
1311 fprintf (stream, _("\
1312-mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n"));
1313 fprintf (stream, _("\
1314-mpwr generate code for POWER (RIOS1)\n"));
1315 fprintf (stream, _("\
1316-m601 generate code for PowerPC 601\n"));
1317 fprintf (stream, _("\
418c1742 1318-mppc, -mppc32, -m603, -m604\n\
5f63875b
AM		 1319 generate code for PowerPC 603/604\n"));
1320 fprintf (stream, _("\
1321-m403 generate code for PowerPC 403\n"));
1322 fprintf (stream, _("\
1323-m405 generate code for PowerPC 405\n"));
1324 fprintf (stream, _("\
1325-m440 generate code for PowerPC 440\n"));
1326 fprintf (stream, _("\
1327-m464 generate code for PowerPC 464\n"));
1328 fprintf (stream, _("\
1329-m476 generate code for PowerPC 476\n"));
1330 fprintf (stream, _("\
f5c120c5 1331-m7400, -m7410, -m7450, -m7455\n\
5f63875b
AM		 1332 generate code for PowerPC 7400/7410/7450/7455\n"));
1333 fprintf (stream, _("\
fa758a70 1334-m750cl, -mgekko, -mbroadway\n\
5f63875b
AM		 1335 generate code for PowerPC 750cl/Gekko/Broadway\n"));
1336 fprintf (stream, _("\
ef5a96d5 1337-m821, -m850, -m860 generate code for PowerPC 821/850/860\n"));
df12615d 1338 fprintf (stream, _("\
5f63875b
AM		 1339-mppc64, -m620 generate code for PowerPC 620/625/630\n"));
1340 fprintf (stream, _("\
1341-mppc64bridge generate code for PowerPC 64, including bridge insns\n"));
1342 fprintf (stream, _("\
1343-mbooke generate code for 32-bit PowerPC BookE\n"));
1344 fprintf (stream, _("\
1345-ma2 generate code for A2 architecture\n"));
1346 fprintf (stream, _("\
1347-mpower4, -mpwr4 generate code for Power4 architecture\n"));
1348 fprintf (stream, _("\
cdc51b07 1349-mpower5, -mpwr5, -mpwr5x\n\
5f63875b
AM		 1350 generate code for Power5 architecture\n"));
1351 fprintf (stream, _("\
1352-mpower6, -mpwr6 generate code for Power6 architecture\n"));
1353 fprintf (stream, _("\
1354-mpower7, -mpwr7 generate code for Power7 architecture\n"));
1355 fprintf (stream, _("\
1356-mpower8, -mpwr8 generate code for Power8 architecture\n"));
1357 fprintf (stream, _("\
1358-mpower9, -mpwr9 generate code for Power9 architecture\n"));
1359 fprintf (stream, _("\
1424c35d
AM		 1360-mpower10, -mpwr10 generate code for Power10 architecture\n"));
1361 fprintf (stream, _("\
5f63875b
AM		 1362-mcell generate code for Cell Broadband Engine architecture\n"));
1363 fprintf (stream, _("\
1364-mcom generate code for Power/PowerPC common instructions\n"));
1365 fprintf (stream, _("\
ce3d2015 1366-many generate code for any architecture (PWR/PWRX/PPC)\n"));
6a0c61b7 1367 fprintf (stream, _("\
5f63875b
AM		 1368-maltivec generate code for AltiVec\n"));
1369 fprintf (stream, _("\
1370-mvsx generate code for Vector-Scalar (VSX) instructions\n"));
1371 fprintf (stream, _("\
1372-me300 generate code for PowerPC e300 family\n"));
1373 fprintf (stream, _("\
1374-me500, -me500x2 generate code for Motorola e500 core complex\n"));
1375 fprintf (stream, _("\
1376-me500mc, generate code for Freescale e500mc core complex\n"));
1377 fprintf (stream, _("\
1378-me500mc64, generate code for Freescale e500mc64 core complex\n"));
1379 fprintf (stream, _("\
1380-me5500, generate code for Freescale e5500 core complex\n"));
1381 fprintf (stream, _("\
1382-me6500, generate code for Freescale e6500 core complex\n"));
1383 fprintf (stream, _("\
1384-mspe generate code for Motorola SPE instructions\n"));
1385 fprintf (stream, _("\
1386-mspe2 generate code for Freescale SPE2 instructions\n"));
1387 fprintf (stream, _("\
1388-mvle generate code for Freescale VLE instructions\n"));
1389 fprintf (stream, _("\
1390-mtitan generate code for AppliedMicro Titan core complex\n"));
1391 fprintf (stream, _("\
1392-mregnames Allow symbolic names for registers\n"));
1393 fprintf (stream, _("\
ce3d2015 1394-mno-regnames Do not allow symbolic names for registers\n"));
252b5132 1395#ifdef OBJ_ELF
bc805888 1396 fprintf (stream, _("\
5f63875b
AM		 1397-mrelocatable support for GCC's -mrelocatble option\n"));
1398 fprintf (stream, _("\
1399-mrelocatable-lib support for GCC's -mrelocatble-lib option\n"));
1400 fprintf (stream, _("\
1401-memb set PPC_EMB bit in ELF flags\n"));
1402 fprintf (stream, _("\
b8b738ac 1403-mlittle, -mlittle-endian, -le\n\
5f63875b
AM		 1404 generate code for a little endian machine\n"));
1405 fprintf (stream, _("\
b8b738ac 1406-mbig, -mbig-endian, -be\n\
5f63875b
AM		 1407 generate code for a big endian machine\n"));
1408 fprintf (stream, _("\
1409-msolaris generate code for Solaris\n"));
1410 fprintf (stream, _("\
1411-mno-solaris do not generate code for Solaris\n"));
1412 fprintf (stream, _("\
1413-K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n"));
1414 fprintf (stream, _("\
1415-V print assembler version number\n"));
1416 fprintf (stream, _("\
ce3d2015 1417-Qy, -Qn ignored\n"));
252b5132 1418#endif
cef4f754 1419 fprintf (stream, _("\
5f63875b
AM		 1420-nops=count when aligning, more than COUNT nops uses a branch\n"));
1421 fprintf (stream, _("\
bf7279d5 1422-ppc476-workaround warn if emitting data to code sections\n"));
252b5132
RH		 1423}
1424\f
1425/* Set ppc_cpu if it is not already set. */
1426
1427static void
98027b10 1428ppc_set_cpu (void)
252b5132
RH		 1429{
1430 const char *default_os = TARGET_OS;
1431 const char *default_cpu = TARGET_CPU;
1432
7102e95e 1433 if ((ppc_cpu & ~(ppc_cpu_t) PPC_OPCODE_ANY) == 0)
252b5132 1434 {
2a98c3a6 1435 if (ppc_obj64)
f2ab4b42
PB		 1436 if (target_big_endian)
1437 ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64;
1438 else
1439 /* The minimum supported cpu for 64-bit little-endian is power8. */
1440 ppc_cpu |= ppc_parse_cpu (ppc_cpu, &sticky, "power8");
2a98c3a6
AM		 1441 else if (strncmp (default_os, "aix", 3) == 0
1442 && default_os[3] >= '4' && default_os[3] <= '9')
bdc70b4a 1443 ppc_cpu |= PPC_OPCODE_COMMON;
252b5132 1444 else if (strncmp (default_os, "aix3", 4) == 0)
bdc70b4a 1445 ppc_cpu |= PPC_OPCODE_POWER;
252b5132 1446 else if (strcmp (default_cpu, "rs6000") == 0)
bdc70b4a 1447 ppc_cpu |= PPC_OPCODE_POWER;
0baf16f2 1448 else if (strncmp (default_cpu, "powerpc", 7) == 0)
bdc70b4a 1449 ppc_cpu |= PPC_OPCODE_PPC;
252b5132 1450 else
d6ed37ed 1451 as_fatal (_("unknown default cpu = %s, os = %s"),
99a814a1 1452 default_cpu, default_os);
252b5132
RH		 1453 }
1454}
1455
9232bbb0
AM		 1456/* Figure out the BFD architecture to use. This function and ppc_mach
1457 are called well before md_begin, when the output file is opened. */
252b5132
RH		 1458
1459enum bfd_architecture
98027b10 1460ppc_arch (void)
252b5132
RH		 1461{
1462 const char *default_cpu = TARGET_CPU;
1463 ppc_set_cpu ();
1464
1465 if ((ppc_cpu & PPC_OPCODE_PPC) != 0)
1466 return bfd_arch_powerpc;
b9c361e0
JL		 1467 if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
1468 return bfd_arch_powerpc;
1469 if ((ppc_cpu & PPC_OPCODE_POWER) != 0)
252b5132 1470 return bfd_arch_rs6000;
b9c361e0 1471 if ((ppc_cpu & (PPC_OPCODE_COMMON | PPC_OPCODE_ANY)) != 0)
252b5132
RH		 1472 {
1473 if (strcmp (default_cpu, "rs6000") == 0)
1474 return bfd_arch_rs6000;
0baf16f2 1475 else if (strncmp (default_cpu, "powerpc", 7) == 0)
252b5132
RH		 1476 return bfd_arch_powerpc;
1477 }
1478
d6ed37ed 1479 as_fatal (_("neither Power nor PowerPC opcodes were selected."));
252b5132
RH		 1480 return bfd_arch_unknown;
1481}
1482
7f6d05e8 1483unsigned long
98027b10 1484ppc_mach (void)
7f6d05e8 1485{
2a98c3a6
AM		 1486 if (ppc_obj64)
1487 return bfd_mach_ppc64;
1488 else if (ppc_arch () == bfd_arch_rs6000)
1489 return bfd_mach_rs6k;
ce3d2015
AM		 1490 else if (ppc_cpu & PPC_OPCODE_TITAN)
1491 return bfd_mach_ppc_titan;
b9c361e0
JL		 1492 else if (ppc_cpu & PPC_OPCODE_VLE)
1493 return bfd_mach_ppc_vle;
2a98c3a6
AM		 1494 else
1495 return bfd_mach_ppc;
7f6d05e8
CP		 1496}
1497
e0471c16 1498extern const char*
98027b10 1499ppc_target_format (void)
7f6d05e8
CP		 1500{
1501#ifdef OBJ_COFF
fe49679d 1502#if TE_POWERMAC
0baf16f2 1503 return "xcoff-powermac";
7f6d05e8 1504#else
eb1e0e80 1505# ifdef TE_AIX5
edc1d652 1506 return (ppc_obj64 ? "aix5coff64-rs6000" : "aixcoff-rs6000");
eb1e0e80 1507# else
edc1d652 1508 return (ppc_obj64 ? "aixcoff64-rs6000" : "aixcoff-rs6000");
eb1e0e80 1509# endif
7f6d05e8 1510#endif
7f6d05e8
CP		 1511#endif
1512#ifdef OBJ_ELF
edc1d652
AM		 1513# ifdef TE_FreeBSD
1514 return (ppc_obj64 ? "elf64-powerpc-freebsd" : "elf32-powerpc-freebsd");
1515# elif defined (TE_VXWORKS)
9d8504b1
PB		 1516 return "elf32-powerpc-vxworks";
1517# else
0baf16f2 1518 return (target_big_endian
2b3c4602
AM		 1519 ? (ppc_obj64 ? "elf64-powerpc" : "elf32-powerpc")
1520 : (ppc_obj64 ? "elf64-powerpcle" : "elf32-powerpcle"));
9d8504b1 1521# endif
7f6d05e8
CP		 1522#endif
1523}
1524
b9c361e0
JL		 1525/* Validate one entry in powerpc_opcodes[] or vle_opcodes[].
1526 Return TRUE if there's a problem, otherwise FALSE. */
1527
1528static bfd_boolean
1529insn_validate (const struct powerpc_opcode *op)
1530{
1531 const unsigned char *o;
0f873fd5 1532 uint64_t omask = op->mask;
b9c361e0
JL		 1533
1534 /* The mask had better not trim off opcode bits. */
1535 if ((op->opcode & omask) != op->opcode)
1536 {
1537 as_bad (_("mask trims opcode bits for %s"), op->name);
1538 return TRUE;
1539 }
1540
1541 /* The operands must not overlap the opcode or each other. */
1542 for (o = op->operands; *o; ++o)
1543 {
2eac3da1 1544 bfd_boolean optional = FALSE;
b9c361e0
JL		 1545 if (*o >= num_powerpc_operands)
1546 {
1547 as_bad (_("operand index error for %s"), op->name);
1548 return TRUE;
1549 }
1550 else
1551 {
71553718 1552 uint64_t mask;
b9c361e0 1553 const struct powerpc_operand *operand = &powerpc_operands[*o];
71553718 1554 if (operand->shift == (int) PPC_OPSHIFT_INV)
b9c361e0 1555 {
71553718
AM		 1556 const char *errmsg;
1557 int64_t val;
1558
1559 errmsg = NULL;
1560 val = -1;
1561 if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0)
1562 val = -val;
1563 else if ((operand->flags & PPC_OPERAND_PLUS1) != 0)
1564 val += 1;
1565 mask = (*operand->insert) (0, val, ppc_cpu, &errmsg);
b9c361e0 1566 }
71553718
AM		 1567 else if (operand->shift >= 0)
1568 mask = operand->bitm << operand->shift;
1569 else
1570 mask = operand->bitm >> -operand->shift;
1571 if (omask & mask)
1572 {
1573 as_bad (_("operand %d overlap in %s"),
1574 (int) (o - op->operands), op->name);
1575 return TRUE;
1576 }
1577 omask |= mask;
2eac3da1
AM		 1578 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
1579 optional = TRUE;
1580 else if (optional)
1581 {
1582 as_bad (_("non-optional operand %d follows optional operand in %s"),
1583 (int) (o - op->operands), op->name);
1584 return TRUE;
1585 }
b9c361e0
JL		 1586 }
1587 }
1588 return FALSE;
1589}
1590
69c040df 1591/* Insert opcodes and macros into hash tables. Called at startup and
1fe532cf 1592 for .machine pseudo. */
252b5132 1593
69c040df
AM		 1594static void
1595ppc_setup_opcodes (void)
252b5132 1596{
98027b10 1597 const struct powerpc_opcode *op;
252b5132
RH		 1598 const struct powerpc_opcode *op_end;
1599 const struct powerpc_macro *macro;
1600 const struct powerpc_macro *macro_end;
b84bf58a 1601 bfd_boolean bad_insn = FALSE;
252b5132 1602
69c040df
AM		 1603 if (ppc_hash != NULL)
1604 hash_die (ppc_hash);
1605 if (ppc_macro_hash != NULL)
1606 hash_die (ppc_macro_hash);
252b5132
RH		 1607
1608 /* Insert the opcodes into a hash table. */
1609 ppc_hash = hash_new ();
1610
c43a438d 1611 if (ENABLE_CHECKING)
b84bf58a 1612 {
c43a438d 1613 unsigned int i;
b84bf58a 1614
3b8b57a9
AM		 1615 /* An index into powerpc_operands is stored in struct fix
1616 fx_pcrel_adjust which is 8 bits wide. */
1617 gas_assert (num_powerpc_operands < 256);
1618
c43a438d
AM		 1619 /* Check operand masks. Code here and in the disassembler assumes
1620 all the 1's in the mask are contiguous. */
1621 for (i = 0; i < num_powerpc_operands; ++i)
b84bf58a 1622 {
0f873fd5
PB		 1623 uint64_t mask = powerpc_operands[i].bitm;
1624 uint64_t right_bit;
c43a438d
AM		 1625 unsigned int j;
1626
1627 right_bit = mask & -mask;
1628 mask += right_bit;
1629 right_bit = mask & -mask;
1630 if (mask != right_bit)
1631 {
1632 as_bad (_("powerpc_operands[%d].bitm invalid"), i);
1633 bad_insn = TRUE;
1634 }
1635 for (j = i + 1; j < num_powerpc_operands; ++j)
1636 if (memcmp (&powerpc_operands[i], &powerpc_operands[j],
1637 sizeof (powerpc_operands[0])) == 0)
1638 {
1639 as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"),
1640 j, i);
1641 bad_insn = TRUE;
1642 }
b84bf58a
AM		 1643 }
1644 }
1645
252b5132
RH		 1646 op_end = powerpc_opcodes + powerpc_num_opcodes;
1647 for (op = powerpc_opcodes; op < op_end; op++)
1648 {
c43a438d 1649 if (ENABLE_CHECKING)
b84bf58a 1650 {
2ceb7719 1651 unsigned int new_opcode = PPC_OP (op[0].opcode);
b9c361e0
JL		 1652
1653#ifdef PRINT_OPCODE_TABLE
2ceb7719
PB		 1654 printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1655 op->name, (unsigned int) (op - powerpc_opcodes),
1656 new_opcode, (unsigned long long) op->opcode,
1657 (unsigned long long) op->mask, (unsigned long long) op->flags);
b9c361e0
JL		 1658#endif
1659
2ceb7719
PB		 1660 /* The major opcodes had better be sorted. Code in the disassembler
1661 assumes the insns are sorted according to major opcode. */
1662 if (op != powerpc_opcodes
1663 && new_opcode < PPC_OP (op[-1].opcode))
1664 {
1665 as_bad (_("major opcode is not sorted for %s"), op->name);
1666 bad_insn = TRUE;
8dbcd839 1667 }
2ceb7719 1668
14b57c7c
AM		 1669 if ((op->flags & PPC_OPCODE_VLE) != 0)
1670 {
1671 as_bad (_("%s is enabled by vle flag"), op->name);
1672 bad_insn = TRUE;
1673 }
1674 if (PPC_OP (op->opcode) != 4
1675 && PPC_OP (op->opcode) != 31
1676 && (op->deprecated & PPC_OPCODE_VLE) == 0)
1677 {
1678 as_bad (_("%s not disabled by vle flag"), op->name);
1679 bad_insn = TRUE;
1680 }
b9c361e0
JL		 1681 bad_insn |= insn_validate (op);
1682 }
c43a438d 1683
b9c361e0
JL		 1684 if ((ppc_cpu & op->flags) != 0
1685 && !(ppc_cpu & op->deprecated))
1686 {
1687 const char *retval;
1688
1689 retval = hash_insert (ppc_hash, op->name, (void *) op);
1690 if (retval != NULL)
c43a438d 1691 {
b9c361e0 1692 as_bad (_("duplicate instruction %s"),
c43a438d
AM		 1693 op->name);
1694 bad_insn = TRUE;
1695 }
b9c361e0
JL		 1696 }
1697 }
c43a438d 1698
b9c361e0
JL		 1699 if ((ppc_cpu & PPC_OPCODE_ANY) != 0)
1700 for (op = powerpc_opcodes; op < op_end; op++)
1701 hash_insert (ppc_hash, op->name, (void *) op);
1702
dd7efa79
PB		 1703 op_end = prefix_opcodes + prefix_num_opcodes;
1704 for (op = prefix_opcodes; op < op_end; op++)
1705 {
1706 if (ENABLE_CHECKING)
1707 {
1708 unsigned int new_opcode = PPC_PREFIX_SEG (op[0].opcode);
1709
1710#ifdef PRINT_OPCODE_TABLE
1711 printf ("%-14s\t#%04u\tmajor op/2: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1712 op->name, (unsigned int) (op - prefix_opcodes),
1713 new_opcode, (unsigned long long) op->opcode,
1714 (unsigned long long) op->mask, (unsigned long long) op->flags);
1715#endif
1716
1717 /* The major opcodes had better be sorted. Code in the disassembler
1718 assumes the insns are sorted according to major opcode. */
1719 if (op != prefix_opcodes
1720 && new_opcode < PPC_PREFIX_SEG (op[-1].opcode))
1721 {
1722 as_bad (_("major opcode is not sorted for %s"), op->name);
1723 bad_insn = TRUE;
1724 }
1725 bad_insn |= insn_validate (op);
1726 }
1727
1728 if ((ppc_cpu & op->flags) != 0
1729 && !(ppc_cpu & op->deprecated))
1730 {
1731 const char *retval;
1732
1733 retval = hash_insert (ppc_hash, op->name, (void *) op);
1734 if (retval != NULL)
1735 {
1736 as_bad (_("duplicate instruction %s"),
1737 op->name);
1738 bad_insn = TRUE;
1739 }
1740 }
1741 }
1742
1743 if ((ppc_cpu & PPC_OPCODE_ANY) != 0)
1744 for (op = prefix_opcodes; op < op_end; op++)
1745 hash_insert (ppc_hash, op->name, (void *) op);
1746
b9c361e0
JL		 1747 op_end = vle_opcodes + vle_num_opcodes;
1748 for (op = vle_opcodes; op < op_end; op++)
1749 {
1750 if (ENABLE_CHECKING)
1751 {
2ceb7719 1752 unsigned new_seg = VLE_OP_TO_SEG (VLE_OP (op[0].opcode, op[0].mask));
b9c361e0
JL		 1753
1754#ifdef PRINT_OPCODE_TABLE
2ceb7719
PB		 1755 printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1756 op->name, (unsigned int) (op - vle_opcodes),
1757 (unsigned int) new_seg, (unsigned long long) op->opcode,
1758 (unsigned long long) op->mask, (unsigned long long) op->flags);
b9c361e0 1759#endif
2ceb7719
PB		 1760
1761 /* The major opcodes had better be sorted. Code in the disassembler
1762 assumes the insns are sorted according to major opcode. */
1763 if (op != vle_opcodes
1764 && new_seg < VLE_OP_TO_SEG (VLE_OP (op[-1].opcode, op[-1].mask)))
1765 {
1766 as_bad (_("major opcode is not sorted for %s"), op->name);
1767 bad_insn = TRUE;
b9c361e0
JL		 1768 }
1769
1770 bad_insn |= insn_validate (op);
c43a438d 1771 }
252b5132 1772
bdc70b4a 1773 if ((ppc_cpu & op->flags) != 0
1cb0a767 1774 && !(ppc_cpu & op->deprecated))
252b5132
RH		 1775 {
1776 const char *retval;
1777
98027b10 1778 retval = hash_insert (ppc_hash, op->name, (void *) op);
69c040df 1779 if (retval != NULL)
252b5132 1780 {
b84bf58a 1781 as_bad (_("duplicate instruction %s"),
99a814a1 1782 op->name);
b84bf58a 1783 bad_insn = TRUE;
252b5132
RH		 1784 }
1785 }
1786 }
1787
74081948
AF		 1788 /* SPE2 instructions */
1789 if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2)
1790 {
1791 op_end = spe2_opcodes + spe2_num_opcodes;
1792 for (op = spe2_opcodes; op < op_end; op++)
1793 {
1794 if (ENABLE_CHECKING)
1795 {
1796 if (op != spe2_opcodes)
1797 {
1798 unsigned old_seg, new_seg;
1799
1800 old_seg = VLE_OP (op[-1].opcode, op[-1].mask);
1801 old_seg = VLE_OP_TO_SEG (old_seg);
1802 new_seg = VLE_OP (op[0].opcode, op[0].mask);
1803 new_seg = VLE_OP_TO_SEG (new_seg);
1804
1805 /* The major opcodes had better be sorted. Code in the
1806 disassembler assumes the insns are sorted according to
1807 major opcode. */
1808 if (new_seg < old_seg)
1809 {
1810 as_bad (_("major opcode is not sorted for %s"), op->name);
1811 bad_insn = TRUE;
1812 }
1813 }
1814
1815 bad_insn |= insn_validate (op);
1816 }
1817
1818 if ((ppc_cpu & op->flags) != 0 && !(ppc_cpu & op->deprecated))
1819 {
1820 const char *retval;
1821
1822 retval = hash_insert (ppc_hash, op->name, (void *) op);
1823 if (retval != NULL)
1824 {
1825 as_bad (_("duplicate instruction %s"),
1826 op->name);
1827 bad_insn = TRUE;
1828 }
1829 }
1830 }
1831
1832 for (op = spe2_opcodes; op < op_end; op++)
1833 hash_insert (ppc_hash, op->name, (void *) op);
1834 }
1835
252b5132
RH		 1836 /* Insert the macros into a hash table. */
1837 ppc_macro_hash = hash_new ();
1838
1839 macro_end = powerpc_macros + powerpc_num_macros;
1840 for (macro = powerpc_macros; macro < macro_end; macro++)
1841 {
33740db9 1842 if ((macro->flags & ppc_cpu) != 0 || (ppc_cpu & PPC_OPCODE_ANY) != 0)
252b5132
RH		 1843 {
1844 const char *retval;
1845
98027b10 1846 retval = hash_insert (ppc_macro_hash, macro->name, (void *) macro);
252b5132
RH		 1847 if (retval != (const char *) NULL)
1848 {
b84bf58a
AM		 1849 as_bad (_("duplicate macro %s"), macro->name);
1850 bad_insn = TRUE;
252b5132
RH		 1851 }
1852 }
1853 }
1854
b84bf58a 1855 if (bad_insn)
252b5132 1856 abort ();
69c040df
AM		 1857}
1858
1859/* This function is called when the assembler starts up. It is called
1860 after the options have been parsed and the output file has been
1861 opened. */
1862
1863void
98027b10 1864md_begin (void)
69c040df
AM		 1865{
1866 ppc_set_cpu ();
1867
1868 ppc_cie_data_alignment = ppc_obj64 ? -8 : -4;
8fbf7334 1869 ppc_dwarf2_line_min_insn_length = (ppc_cpu & PPC_OPCODE_VLE) ? 2 : 4;
69c040df
AM		 1870
1871#ifdef OBJ_ELF
1872 /* Set the ELF flags if desired. */
1873 if (ppc_flags && !msolaris)
1874 bfd_set_private_flags (stdoutput, ppc_flags);
1875#endif
1876
1877 ppc_setup_opcodes ();
252b5132 1878
67c1ffbe 1879 /* Tell the main code what the endianness is if it is not overridden
99a814a1 1880 by the user. */
252b5132
RH		 1881 if (!set_target_endian)
1882 {
1883 set_target_endian = 1;
1884 target_big_endian = PPC_BIG_ENDIAN;
1885 }
1886
1887#ifdef OBJ_XCOFF
1888 ppc_coff_debug_section = coff_section_from_bfd_index (stdoutput, N_DEBUG);
1889
1890 /* Create dummy symbols to serve as initial csects. This forces the
1891 text csects to precede the data csects. These symbols will not
1892 be output. */
1893 ppc_text_csects = symbol_make ("dummy\001");
809ffe0d 1894 symbol_get_tc (ppc_text_csects)->within = ppc_text_csects;
252b5132 1895 ppc_data_csects = symbol_make ("dummy\001");
809ffe0d 1896 symbol_get_tc (ppc_data_csects)->within = ppc_data_csects;
252b5132 1897#endif
252b5132
RH		 1898}
1899
6a0c61b7 1900void
98027b10 1901ppc_cleanup (void)
6a0c61b7 1902{
dc1d03fc 1903#ifdef OBJ_ELF
6a0c61b7
EZ		 1904 if (ppc_apuinfo_list == NULL)
1905 return;
1906
1907 /* Ok, so write the section info out. We have this layout:
1908
1909 byte data what
1910 ---- ---- ----
1911 0 8 length of "APUinfo\0"
1912 4 (n*4) number of APU's (4 bytes each)
1913 8 2 note type 2
1914 12 "APUinfo\0" name
1915 20 APU#1 first APU's info
1916 24 APU#2 second APU's info
1917 ... ...
1918 */
1919 {
1920 char *p;
1921 asection *seg = now_seg;
1922 subsegT subseg = now_subseg;
1923 asection *apuinfo_secp = (asection *) NULL;
49181a6a 1924 unsigned int i;
6a0c61b7
EZ		 1925
1926 /* Create the .PPC.EMB.apuinfo section. */
14b57c7c 1927 apuinfo_secp = subseg_new (APUINFO_SECTION_NAME, 0);
fd361982 1928 bfd_set_section_flags (apuinfo_secp, SEC_HAS_CONTENTS | SEC_READONLY);
6a0c61b7
EZ		 1929
1930 p = frag_more (4);
1931 md_number_to_chars (p, (valueT) 8, 4);
1932
1933 p = frag_more (4);
e98d298c 1934 md_number_to_chars (p, (valueT) ppc_apuinfo_num * 4, 4);
6a0c61b7
EZ		 1935
1936 p = frag_more (4);
1937 md_number_to_chars (p, (valueT) 2, 4);
1938
1939 p = frag_more (8);
14b57c7c 1940 strcpy (p, APUINFO_LABEL);
6a0c61b7
EZ		 1941
1942 for (i = 0; i < ppc_apuinfo_num; i++)
1943 {
b34976b6
AM		 1944 p = frag_more (4);
1945 md_number_to_chars (p, (valueT) ppc_apuinfo_list[i], 4);
6a0c61b7
EZ		 1946 }
1947
1948 frag_align (2, 0, 0);
1949
1950 /* We probably can't restore the current segment, for there likely
1951 isn't one yet... */
1952 if (seg && subseg)
1953 subseg_set (seg, subseg);
1954 }
dc1d03fc 1955#endif
6a0c61b7
EZ		 1956}
1957
252b5132
RH		 1958/* Insert an operand value into an instruction. */
1959
0f873fd5
PB		 1960static uint64_t
1961ppc_insert_operand (uint64_t insn,
a1867a27 1962 const struct powerpc_operand *operand,
0f873fd5 1963 int64_t val,
91d6fa6a 1964 ppc_cpu_t cpu,
3b4dbbbf 1965 const char *file,
a1867a27 1966 unsigned int line)
252b5132 1967{
0f873fd5 1968 int64_t min, max, right;
eb42fac1 1969
b84bf58a
AM		 1970 max = operand->bitm;
1971 right = max & -max;
1972 min = 0;
1973
a47622ac 1974 if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0)
252b5132 1975 {
a255f00a
AM		 1976 /* Extend the allowed range for addis to [-32768, 65535].
1977 Similarly for cmpli and some VLE high part insns. For 64-bit
1978 it would be good to disable this for signed fields since the
a47622ac
AM		 1979 value is sign extended into the high 32 bits of the register.
1980 If the value is, say, an address, then we might care about
1981 the high bits. However, gcc as of 2014-06 uses unsigned
1982 values when loading the high part of 64-bit constants using
a255f00a
AM		 1983 lis. */
1984 min = ~(max >> 1) & -right;
a47622ac
AM		 1985 }
1986 else if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
1987 {
1988 max = (max >> 1) & -right;
931774a9 1989 min = ~max & -right;
b84bf58a 1990 }
252b5132 1991
b84bf58a 1992 if ((operand->flags & PPC_OPERAND_PLUS1) != 0)
3896c469 1993 max++;
252b5132 1994
b84bf58a 1995 if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0)
a1867a27 1996 {
0f873fd5 1997 int64_t tmp = min;
a1867a27
AM		 1998 min = -max;
1999 max = -tmp;
2000 }
b84bf58a 2001
a1867a27
AM		 2002 if (min <= max)
2003 {
2004 /* Some people write constants with the sign extension done by
2005 hand but only up to 32 bits. This shouldn't really be valid,
2006 but, to permit this code to assemble on a 64-bit host, we
2007 sign extend the 32-bit value to 64 bits if so doing makes the
8acf1435
PB		 2008 value valid. We only do this for operands that are 32-bits or
2009 smaller. */
a1867a27 2010 if (val > max
8acf1435 2011 && (operand->bitm & ~0xffffffffULL) == 0
0f873fd5
PB		 2012 && (val - (1LL << 32)) >= min
2013 && (val - (1LL << 32)) <= max
2014 && ((val - (1LL << 32)) & (right - 1)) == 0)
2015 val = val - (1LL << 32);
a1867a27
AM		 2016
2017 /* Similarly, people write expressions like ~(1<<15), and expect
2018 this to be OK for a 32-bit unsigned value. */
2019 else if (val < min
8acf1435 2020 && (operand->bitm & ~0xffffffffULL) == 0
0f873fd5
PB		 2021 && (val + (1LL << 32)) >= min
2022 && (val + (1LL << 32)) <= max
2023 && ((val + (1LL << 32)) & (right - 1)) == 0)
2024 val = val + (1LL << 32);
a1867a27
AM		 2025
2026 else if (val < min
2027 || val > max
2028 || (val & (right - 1)) != 0)
2029 as_bad_value_out_of_range (_("operand"), val, min, max, file, line);
2030 }
b84bf58a 2031
252b5132
RH		 2032 if (operand->insert)
2033 {
2034 const char *errmsg;
2035
2036 errmsg = NULL;
0f873fd5 2037 insn = (*operand->insert) (insn, val, cpu, &errmsg);
252b5132 2038 if (errmsg != (const char *) NULL)
ee2c9aa9 2039 as_bad_where (file, line, "%s", errmsg);
252b5132 2040 }
b9c361e0 2041 else if (operand->shift >= 0)
0f873fd5 2042 insn |= (val & operand->bitm) << operand->shift;
b9c361e0 2043 else
0f873fd5 2044 insn |= (val & operand->bitm) >> -operand->shift;
252b5132
RH		 2045
2046 return insn;
2047}
2048
2049\f
2050#ifdef OBJ_ELF
2051/* Parse @got, etc. and return the desired relocation. */
2052static bfd_reloc_code_real_type
98027b10 2053ppc_elf_suffix (char **str_p, expressionS *exp_p)
252b5132
RH		 2054{
2055 struct map_bfd {
e0471c16 2056 const char *string;
b7d7dc63
AM		 2057 unsigned int length : 8;
2058 unsigned int valid32 : 1;
2059 unsigned int valid64 : 1;
2060 unsigned int reloc;
252b5132
RH		 2061 };
2062
2063 char ident[20];
2064 char *str = *str_p;
2065 char *str2;
2066 int ch;
2067 int len;
15c1449b 2068 const struct map_bfd *ptr;
252b5132 2069
b7d7dc63
AM		 2070#define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc }
2071#define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc }
2072#define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc }
252b5132 2073
15c1449b 2074 static const struct map_bfd mapping[] = {
b7d7dc63
AM		 2075 MAP ("l", BFD_RELOC_LO16),
2076 MAP ("h", BFD_RELOC_HI16),
2077 MAP ("ha", BFD_RELOC_HI16_S),
2078 MAP ("brtaken", BFD_RELOC_PPC_B16_BRTAKEN),
2079 MAP ("brntaken", BFD_RELOC_PPC_B16_BRNTAKEN),
2080 MAP ("got", BFD_RELOC_16_GOTOFF),
2081 MAP ("got@l", BFD_RELOC_LO16_GOTOFF),
2082 MAP ("got@h", BFD_RELOC_HI16_GOTOFF),
2083 MAP ("got@ha", BFD_RELOC_HI16_S_GOTOFF),
2084 MAP ("plt@l", BFD_RELOC_LO16_PLTOFF),
2085 MAP ("plt@h", BFD_RELOC_HI16_PLTOFF),
2086 MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF),
2087 MAP ("copy", BFD_RELOC_PPC_COPY),
2088 MAP ("globdat", BFD_RELOC_PPC_GLOB_DAT),
2089 MAP ("sectoff", BFD_RELOC_16_BASEREL),
2090 MAP ("sectoff@l", BFD_RELOC_LO16_BASEREL),
2091 MAP ("sectoff@h", BFD_RELOC_HI16_BASEREL),
2092 MAP ("sectoff@ha", BFD_RELOC_HI16_S_BASEREL),
2093 MAP ("tls", BFD_RELOC_PPC_TLS),
2094 MAP ("dtpmod", BFD_RELOC_PPC_DTPMOD),
2095 MAP ("dtprel", BFD_RELOC_PPC_DTPREL),
2096 MAP ("dtprel@l", BFD_RELOC_PPC_DTPREL16_LO),
2097 MAP ("dtprel@h", BFD_RELOC_PPC_DTPREL16_HI),
2098 MAP ("dtprel@ha", BFD_RELOC_PPC_DTPREL16_HA),
2099 MAP ("tprel", BFD_RELOC_PPC_TPREL),
2100 MAP ("tprel@l", BFD_RELOC_PPC_TPREL16_LO),
2101 MAP ("tprel@h", BFD_RELOC_PPC_TPREL16_HI),
2102 MAP ("tprel@ha", BFD_RELOC_PPC_TPREL16_HA),
2103 MAP ("got@tlsgd", BFD_RELOC_PPC_GOT_TLSGD16),
2104 MAP ("got@tlsgd@l", BFD_RELOC_PPC_GOT_TLSGD16_LO),
2105 MAP ("got@tlsgd@h", BFD_RELOC_PPC_GOT_TLSGD16_HI),
2106 MAP ("got@tlsgd@ha", BFD_RELOC_PPC_GOT_TLSGD16_HA),
2107 MAP ("got@tlsld", BFD_RELOC_PPC_GOT_TLSLD16),
2108 MAP ("got@tlsld@l", BFD_RELOC_PPC_GOT_TLSLD16_LO),
2109 MAP ("got@tlsld@h", BFD_RELOC_PPC_GOT_TLSLD16_HI),
2110 MAP ("got@tlsld@ha", BFD_RELOC_PPC_GOT_TLSLD16_HA),
2111 MAP ("got@dtprel", BFD_RELOC_PPC_GOT_DTPREL16),
2112 MAP ("got@dtprel@l", BFD_RELOC_PPC_GOT_DTPREL16_LO),
2113 MAP ("got@dtprel@h", BFD_RELOC_PPC_GOT_DTPREL16_HI),
2114 MAP ("got@dtprel@ha", BFD_RELOC_PPC_GOT_DTPREL16_HA),
2115 MAP ("got@tprel", BFD_RELOC_PPC_GOT_TPREL16),
2116 MAP ("got@tprel@l", BFD_RELOC_PPC_GOT_TPREL16_LO),
2117 MAP ("got@tprel@h", BFD_RELOC_PPC_GOT_TPREL16_HI),
2118 MAP ("got@tprel@ha", BFD_RELOC_PPC_GOT_TPREL16_HA),
2119 MAP32 ("fixup", BFD_RELOC_CTOR),
2120 MAP32 ("plt", BFD_RELOC_24_PLT_PCREL),
2121 MAP32 ("pltrel24", BFD_RELOC_24_PLT_PCREL),
2122 MAP32 ("local24pc", BFD_RELOC_PPC_LOCAL24PC),
2123 MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC),
2124 MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL),
2125 MAP32 ("sdarel", BFD_RELOC_GPREL16),
b9c361e0
JL		 2126 MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A),
2127 MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A),
2128 MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A),
b7d7dc63
AM		 2129 MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32),
2130 MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16),
2131 MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO),
2132 MAP32 ("naddr@h", BFD_RELOC_PPC_EMB_NADDR16_HI),
2133 MAP32 ("naddr@ha", BFD_RELOC_PPC_EMB_NADDR16_HA),
2134 MAP32 ("sdai16", BFD_RELOC_PPC_EMB_SDAI16),
2135 MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL),
2136 MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16),
2137 MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21),
b9c361e0 2138 MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO),
b7d7dc63
AM		 2139 MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF),
2140 MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16),
2141 MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO),
2142 MAP32 ("relsect@h", BFD_RELOC_PPC_EMB_RELST_HI),
2143 MAP32 ("relsect@ha", BFD_RELOC_PPC_EMB_RELST_HA),
2144 MAP32 ("bitfld", BFD_RELOC_PPC_EMB_BIT_FLD),
2145 MAP32 ("relsda", BFD_RELOC_PPC_EMB_RELSDA),
2146 MAP32 ("xgot", BFD_RELOC_PPC_TOC16),
f9c6b907
AM		 2147 MAP64 ("high", BFD_RELOC_PPC64_ADDR16_HIGH),
2148 MAP64 ("higha", BFD_RELOC_PPC64_ADDR16_HIGHA),
b7d7dc63
AM		 2149 MAP64 ("higher", BFD_RELOC_PPC64_HIGHER),
2150 MAP64 ("highera", BFD_RELOC_PPC64_HIGHER_S),
2151 MAP64 ("highest", BFD_RELOC_PPC64_HIGHEST),
2152 MAP64 ("highesta", BFD_RELOC_PPC64_HIGHEST_S),
2153 MAP64 ("tocbase", BFD_RELOC_PPC64_TOC),
2154 MAP64 ("toc", BFD_RELOC_PPC_TOC16),
2155 MAP64 ("toc@l", BFD_RELOC_PPC64_TOC16_LO),
2156 MAP64 ("toc@h", BFD_RELOC_PPC64_TOC16_HI),
2157 MAP64 ("toc@ha", BFD_RELOC_PPC64_TOC16_HA),
f9c6b907
AM		 2158 MAP64 ("dtprel@high", BFD_RELOC_PPC64_DTPREL16_HIGH),
2159 MAP64 ("dtprel@higha", BFD_RELOC_PPC64_DTPREL16_HIGHA),
b7d7dc63
AM		 2160 MAP64 ("dtprel@higher", BFD_RELOC_PPC64_DTPREL16_HIGHER),
2161 MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA),
2162 MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST),
2163 MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA),
45965137 2164 MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL),
f9c6b907
AM		 2165 MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH),
2166 MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA),
b7d7dc63
AM		 2167 MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER),
2168 MAP64 ("tprel@highera", BFD_RELOC_PPC64_TPREL16_HIGHERA),
2169 MAP64 ("tprel@highest", BFD_RELOC_PPC64_TPREL16_HIGHEST),
2170 MAP64 ("tprel@highesta", BFD_RELOC_PPC64_TPREL16_HIGHESTA),
05d0e962 2171 MAP64 ("notoc", BFD_RELOC_PPC64_REL24_NOTOC),
5663e321
AM		 2172 MAP64 ("pcrel", BFD_RELOC_PPC64_PCREL34),
2173 MAP64 ("got@pcrel", BFD_RELOC_PPC64_GOT_PCREL34),
2174 MAP64 ("plt@pcrel", BFD_RELOC_PPC64_PLT_PCREL34),
c213164a 2175 MAP64 ("tls@pcrel", BFD_RELOC_PPC64_TLS_PCREL),
87c69f97
AM		 2176 MAP64 ("got@tlsgd@pcrel", BFD_RELOC_PPC64_GOT_TLSGD_PCREL34),
2177 MAP64 ("got@tlsld@pcrel", BFD_RELOC_PPC64_GOT_TLSLD_PCREL34),
2178 MAP64 ("got@tprel@pcrel", BFD_RELOC_PPC64_GOT_TPREL_PCREL34),
2179 MAP64 ("got@dtprel@pcrel", BFD_RELOC_PPC64_GOT_DTPREL_PCREL34),
5663e321
AM		 2180 MAP64 ("higher34", BFD_RELOC_PPC64_ADDR16_HIGHER34),
2181 MAP64 ("highera34", BFD_RELOC_PPC64_ADDR16_HIGHERA34),
2182 MAP64 ("highest34", BFD_RELOC_PPC64_ADDR16_HIGHEST34),
2183 MAP64 ("highesta34", BFD_RELOC_PPC64_ADDR16_HIGHESTA34),
62ebcb5c 2184 { (char *) 0, 0, 0, 0, BFD_RELOC_NONE }
252b5132
RH		 2185 };
2186
2187 if (*str++ != '@')
62ebcb5c 2188 return BFD_RELOC_NONE;
252b5132
RH		 2189
2190 for (ch = *str, str2 = ident;
2191 (str2 < ident + sizeof (ident) - 1
3882b010 2192 && (ISALNUM (ch) || ch == '@'));
252b5132
RH		 2193 ch = *++str)
2194 {
3882b010 2195 *str2++ = TOLOWER (ch);
252b5132
RH		 2196 }
2197
2198 *str2 = '\0';
2199 len = str2 - ident;
2200
2201 ch = ident[0];
2202 for (ptr = &mapping[0]; ptr->length > 0; ptr++)
2203 if (ch == ptr->string[0]
2204 && len == ptr->length
b7d7dc63
AM		 2205 && memcmp (ident, ptr->string, ptr->length) == 0
2206 && (ppc_obj64 ? ptr->valid64 : ptr->valid32))
252b5132 2207 {
15c1449b
AM		 2208 int reloc = ptr->reloc;
2209
727fc41e
AM		 2210 if (!ppc_obj64 && exp_p->X_add_number != 0)
2211 {
2212 switch (reloc)
2213 {
2214 case BFD_RELOC_16_GOTOFF:
2215 case BFD_RELOC_LO16_GOTOFF:
2216 case BFD_RELOC_HI16_GOTOFF:
2217 case BFD_RELOC_HI16_S_GOTOFF:
e47d413a
AM		 2218 as_warn (_("symbol+offset@%s means symbol@%s+offset"),
2219 ptr->string, ptr->string);
727fc41e
AM		 2220 break;
2221
2222 case BFD_RELOC_PPC_GOT_TLSGD16:
2223 case BFD_RELOC_PPC_GOT_TLSGD16_LO:
2224 case BFD_RELOC_PPC_GOT_TLSGD16_HI:
2225 case BFD_RELOC_PPC_GOT_TLSGD16_HA:
2226 case BFD_RELOC_PPC_GOT_TLSLD16:
2227 case BFD_RELOC_PPC_GOT_TLSLD16_LO:
2228 case BFD_RELOC_PPC_GOT_TLSLD16_HI:
2229 case BFD_RELOC_PPC_GOT_TLSLD16_HA:
2230 case BFD_RELOC_PPC_GOT_DTPREL16:
2231 case BFD_RELOC_PPC_GOT_DTPREL16_LO:
2232 case BFD_RELOC_PPC_GOT_DTPREL16_HI:
2233 case BFD_RELOC_PPC_GOT_DTPREL16_HA:
2234 case BFD_RELOC_PPC_GOT_TPREL16:
2235 case BFD_RELOC_PPC_GOT_TPREL16_LO:
2236 case BFD_RELOC_PPC_GOT_TPREL16_HI:
2237 case BFD_RELOC_PPC_GOT_TPREL16_HA:
e47d413a 2238 as_bad (_("symbol+offset@%s not supported"), ptr->string);
727fc41e
AM		 2239 break;
2240 }
2241 }
5f6db75a
AM		 2242
2243 /* Now check for identifier@suffix+constant. */
2244 if (*str == '-' || *str == '+')
252b5132 2245 {
5f6db75a
AM		 2246 char *orig_line = input_line_pointer;
2247 expressionS new_exp;
2248
2249 input_line_pointer = str;
2250 expression (&new_exp);
2251 if (new_exp.X_op == O_constant)
252b5132 2252 {
5f6db75a
AM		 2253 exp_p->X_add_number += new_exp.X_add_number;
2254 str = input_line_pointer;
252b5132 2255 }
5f6db75a
AM		 2256
2257 if (&input_line_pointer != str_p)
2258 input_line_pointer = orig_line;
252b5132 2259 }
252b5132 2260 *str_p = str;
0baf16f2 2261
2b3c4602 2262 if (reloc == (int) BFD_RELOC_PPC64_TOC
9f2b53d7
AM		 2263 && exp_p->X_op == O_symbol
2264 && strcmp (S_GET_NAME (exp_p->X_add_symbol), ".TOC.") == 0)
0baf16f2 2265 {
9f2b53d7
AM		 2266 /* Change the symbol so that the dummy .TOC. symbol can be
2267 omitted from the object file. */
0baf16f2
AM		 2268 exp_p->X_add_symbol = &abs_symbol;
2269 }
2270
15c1449b 2271 return (bfd_reloc_code_real_type) reloc;
252b5132
RH		 2272 }
2273
62ebcb5c 2274 return BFD_RELOC_NONE;
252b5132
RH		 2275}
2276
62ebcb5c 2277/* Support @got, etc. on constants emitted via .short, .int etc. */
99a814a1 2278
62ebcb5c
AM		 2279bfd_reloc_code_real_type
2280ppc_elf_parse_cons (expressionS *exp, unsigned int nbytes)
2281{
2282 expression (exp);
2283 if (nbytes >= 2 && *input_line_pointer == '@')
2284 return ppc_elf_suffix (&input_line_pointer, exp);
2285 return BFD_RELOC_NONE;
252b5132
RH		 2286}
2287
bf7279d5
AM		 2288/* Warn when emitting data to code sections, unless we are emitting
2289 a relocation that ld --ppc476-workaround uses to recognise data
2290 *and* there was an unconditional branch prior to the data. */
2291
2292void
2293ppc_elf_cons_fix_check (expressionS *exp ATTRIBUTE_UNUSED,
2294 unsigned int nbytes, fixS *fix)
2295{
2296 if (warn_476
2297 && (now_seg->flags & SEC_CODE) != 0
2298 && (nbytes != 4
2299 || fix == NULL
2300 || !(fix->fx_r_type == BFD_RELOC_32
2301 || fix->fx_r_type == BFD_RELOC_CTOR
2302 || fix->fx_r_type == BFD_RELOC_32_PCREL)
2303 || !(last_seg == now_seg && last_subseg == now_subseg)
2304 || !((last_insn & (0x3f << 26)) == (18u << 26)
2305 || ((last_insn & (0x3f << 26)) == (16u << 26)
2306 && (last_insn & (0x14 << 21)) == (0x14 << 21))
2307 || ((last_insn & (0x3f << 26)) == (19u << 26)
2308 && (last_insn & (0x3ff << 1)) == (16u << 1)
2309 && (last_insn & (0x14 << 21)) == (0x14 << 21)))))
2310 {
2311 /* Flag that we've warned. */
2312 if (fix != NULL)
2313 fix->fx_tcbit = 1;
2314
2315 as_warn (_("data in executable section"));
2316 }
2317}
2318
252b5132
RH		 2319/* Solaris pseduo op to change to the .rodata section. */
2320static void
98027b10 2321ppc_elf_rdata (int xxx)
252b5132
RH		 2322{
2323 char *save_line = input_line_pointer;
2324 static char section[] = ".rodata\n";
2325
99a814a1 2326 /* Just pretend this is .section .rodata */
252b5132
RH		 2327 input_line_pointer = section;
2328 obj_elf_section (xxx);
2329
2330 input_line_pointer = save_line;
2331}
2332
99a814a1 2333/* Pseudo op to make file scope bss items. */
252b5132 2334static void
98027b10 2335ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED)
252b5132 2336{
98027b10
AM		 2337 char *name;
2338 char c;
2339 char *p;
252b5132 2340 offsetT size;
98027b10 2341 symbolS *symbolP;
252b5132
RH		 2342 offsetT align;
2343 segT old_sec;
2344 int old_subsec;
2345 char *pfrag;
2346 int align2;
2347
d02603dc 2348 c = get_symbol_name (&name);
252b5132 2349
d02603dc 2350 /* Just after name is now '\0'. */
252b5132
RH		 2351 p = input_line_pointer;
2352 *p = c;
d02603dc 2353 SKIP_WHITESPACE_AFTER_NAME ();
252b5132
RH		 2354 if (*input_line_pointer != ',')
2355 {
d6ed37ed 2356 as_bad (_("expected comma after symbol-name: rest of line ignored."));
252b5132
RH		 2357 ignore_rest_of_line ();
2358 return;
2359 }
2360
2361 input_line_pointer++; /* skip ',' */
2362 if ((size = get_absolute_expression ()) < 0)
2363 {
2364 as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size);
2365 ignore_rest_of_line ();
2366 return;
2367 }
2368
2369 /* The third argument to .lcomm is the alignment. */
2370 if (*input_line_pointer != ',')
2371 align = 8;
2372 else
2373 {
2374 ++input_line_pointer;
2375 align = get_absolute_expression ();
2376 if (align <= 0)
2377 {
2378 as_warn (_("ignoring bad alignment"));
2379 align = 8;
2380 }
2381 }
2382
2383 *p = 0;
2384 symbolP = symbol_find_or_make (name);
2385 *p = c;
2386
2387 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
2388 {
d6ed37ed 2389 as_bad (_("ignoring attempt to re-define symbol `%s'."),
252b5132
RH		 2390 S_GET_NAME (symbolP));
2391 ignore_rest_of_line ();
2392 return;
2393 }
2394
2395 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
2396 {
d6ed37ed 2397 as_bad (_("length of .lcomm \"%s\" is already %ld. Not changed to %ld."),
252b5132
RH		 2398 S_GET_NAME (symbolP),
2399 (long) S_GET_VALUE (symbolP),
2400 (long) size);
2401
2402 ignore_rest_of_line ();
2403 return;
2404 }
2405
99a814a1 2406 /* Allocate_bss. */
252b5132
RH		 2407 old_sec = now_seg;
2408 old_subsec = now_subseg;
2409 if (align)
2410 {
99a814a1 2411 /* Convert to a power of 2 alignment. */
252b5132
RH		 2412 for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2);
2413 if (align != 1)
2414 {
d6ed37ed 2415 as_bad (_("common alignment not a power of 2"));
252b5132
RH		 2416 ignore_rest_of_line ();
2417 return;
2418 }
2419 }
2420 else
2421 align2 = 0;
2422
2423 record_alignment (bss_section, align2);
cbe02d4f 2424 subseg_set (bss_section, 1);
252b5132
RH		 2425 if (align2)
2426 frag_align (align2, 0, 0);
2427 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057
ILT		 2428 symbol_get_frag (symbolP)->fr_symbol = 0;
2429 symbol_set_frag (symbolP, frag_now);
252b5132
RH		 2430 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
2431 (char *) 0);
2432 *pfrag = 0;
2433 S_SET_SIZE (symbolP, size);
2434 S_SET_SEGMENT (symbolP, bss_section);
2435 subseg_set (old_sec, old_subsec);
2436 demand_empty_rest_of_line ();
2437}
2438
6911b7dc
AM		 2439/* Pseudo op to set symbol local entry point. */
2440static void
2441ppc_elf_localentry (int ignore ATTRIBUTE_UNUSED)
2442{
d02603dc
NC		 2443 char *name;
2444 char c = get_symbol_name (&name);
6911b7dc
AM		 2445 char *p;
2446 expressionS exp;
2447 symbolS *sym;
2448 asymbol *bfdsym;
2449 elf_symbol_type *elfsym;
2450
2451 p = input_line_pointer;
2452 *p = c;
d02603dc 2453 SKIP_WHITESPACE_AFTER_NAME ();
6911b7dc
AM		 2454 if (*input_line_pointer != ',')
2455 {
2456 *p = 0;
2457 as_bad (_("expected comma after name `%s' in .localentry directive"),
2458 name);
2459 *p = c;
2460 ignore_rest_of_line ();
2461 return;
2462 }
2463 input_line_pointer++;
2464 expression (&exp);
2465 if (exp.X_op == O_absent)
2466 {
2467 as_bad (_("missing expression in .localentry directive"));
2468 exp.X_op = O_constant;
2469 exp.X_add_number = 0;
2470 }
2471 *p = 0;
2472 sym = symbol_find_or_make (name);
2473 *p = c;
2474
2475 if (resolve_expression (&exp)
2476 && exp.X_op == O_constant)
2477 {
33cb30a1 2478 unsigned int encoded, ok;
6911b7dc 2479
33cb30a1
AM		 2480 ok = 1;
2481 if (exp.X_add_number == 1 || exp.X_add_number == 7)
2482 encoded = exp.X_add_number << STO_PPC64_LOCAL_BIT;
6911b7dc 2483 else
33cb30a1
AM		 2484 {
2485 encoded = PPC64_SET_LOCAL_ENTRY_OFFSET (exp.X_add_number);
2486 if (exp.X_add_number != (offsetT) PPC64_LOCAL_ENTRY_OFFSET (encoded))
2487 {
2488 as_bad (_(".localentry expression for `%s' "
2489 "is not a valid power of 2"), S_GET_NAME (sym));
2490 ok = 0;
2491 }
2492 }
2493 if (ok)
6911b7dc
AM		 2494 {
2495 bfdsym = symbol_get_bfdsym (sym);
2496 elfsym = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym);
2497 gas_assert (elfsym);
2498 elfsym->internal_elf_sym.st_other &= ~STO_PPC64_LOCAL_MASK;
2499 elfsym->internal_elf_sym.st_other |= encoded;
2500 if (ppc_abiversion == 0)
2501 ppc_abiversion = 2;
2502 }
2503 }
2504 else
2505 as_bad (_(".localentry expression for `%s' "
2506 "does not evaluate to a constant"), S_GET_NAME (sym));
2507
2508 demand_empty_rest_of_line ();
2509}
2510
ee67d69a
AM		 2511/* Pseudo op to set ABI version. */
2512static void
2513ppc_elf_abiversion (int ignore ATTRIBUTE_UNUSED)
2514{
2515 expressionS exp;
2516
2517 expression (&exp);
2518 if (exp.X_op == O_absent)
2519 {
2520 as_bad (_("missing expression in .abiversion directive"));
2521 exp.X_op = O_constant;
2522 exp.X_add_number = 0;
2523 }
2524
2525 if (resolve_expression (&exp)
2526 && exp.X_op == O_constant)
2527 ppc_abiversion = exp.X_add_number;
2528 else
2529 as_bad (_(".abiversion expression does not evaluate to a constant"));
2530 demand_empty_rest_of_line ();
2531}
2532
005d79fd
AM		 2533/* Parse a .gnu_attribute directive. */
2534static void
2535ppc_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED)
2536{
2537 int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU);
2538
2539 /* Check validity of defined powerpc tags. */
2540 if (tag == Tag_GNU_Power_ABI_FP
2541 || tag == Tag_GNU_Power_ABI_Vector
2542 || tag == Tag_GNU_Power_ABI_Struct_Return)
2543 {
2544 unsigned int val;
2545
2546 val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag);
2547
2548 if ((tag == Tag_GNU_Power_ABI_FP && val > 15)
2549 || (tag == Tag_GNU_Power_ABI_Vector && val > 3)
2550 || (tag == Tag_GNU_Power_ABI_Struct_Return && val > 2))
2551 as_warn (_("unknown .gnu_attribute value"));
2552 }
2553}
2554
ee67d69a
AM		 2555/* Set ABI version in output file. */
2556void
2557ppc_elf_end (void)
2558{
2559 if (ppc_obj64 && ppc_abiversion != 0)
2560 {
2561 elf_elfheader (stdoutput)->e_flags &= ~EF_PPC64_ABI;
2562 elf_elfheader (stdoutput)->e_flags |= ppc_abiversion & EF_PPC64_ABI;
2563 }
22f72c48
AM		 2564 /* Any selection of opcodes based on ppc_cpu after gas has finished
2565 parsing the file is invalid. md_apply_fix and ppc_handle_align
2566 must select opcodes based on the machine in force at the point
2567 where the fixup or alignment frag was created, not the machine in
2568 force at the end of file. */
2569 ppc_cpu = 0;
ee67d69a
AM		 2570}
2571
252b5132
RH		 2572/* Validate any relocations emitted for -mrelocatable, possibly adding
2573 fixups for word relocations in writable segments, so we can adjust
2574 them at runtime. */
2575static void
98027b10 2576ppc_elf_validate_fix (fixS *fixp, segT seg)
252b5132
RH		 2577{
2578 if (fixp->fx_done || fixp->fx_pcrel)
2579 return;
2580
2581 switch (shlib)
2582 {
2583 case SHLIB_NONE:
2584 case SHLIB_PIC:
2585 return;
2586
5d6f4f16 2587 case SHLIB_MRELOCATABLE:
62ebcb5c 2588 if (fixp->fx_r_type != BFD_RELOC_16_GOTOFF
252b5132
RH		 2589 && fixp->fx_r_type != BFD_RELOC_HI16_GOTOFF
2590 && fixp->fx_r_type != BFD_RELOC_LO16_GOTOFF
2591 && fixp->fx_r_type != BFD_RELOC_HI16_S_GOTOFF
1cfc59d5 2592 && fixp->fx_r_type != BFD_RELOC_16_BASEREL
252b5132
RH		 2593 && fixp->fx_r_type != BFD_RELOC_LO16_BASEREL
2594 && fixp->fx_r_type != BFD_RELOC_HI16_BASEREL
2595 && fixp->fx_r_type != BFD_RELOC_HI16_S_BASEREL
e138127a 2596 && (seg->flags & SEC_LOAD) != 0
252b5132
RH		 2597 && strcmp (segment_name (seg), ".got2") != 0
2598 && strcmp (segment_name (seg), ".dtors") != 0
2599 && strcmp (segment_name (seg), ".ctors") != 0
2600 && strcmp (segment_name (seg), ".fixup") != 0
252b5132
RH		 2601 && strcmp (segment_name (seg), ".gcc_except_table") != 0
2602 && strcmp (segment_name (seg), ".eh_frame") != 0
2603 && strcmp (segment_name (seg), ".ex_shared") != 0)
2604 {
2605 if ((seg->flags & (SEC_READONLY | SEC_CODE)) != 0
2606 || fixp->fx_r_type != BFD_RELOC_CTOR)
2607 {
2608 as_bad_where (fixp->fx_file, fixp->fx_line,
d6ed37ed 2609 _("relocation cannot be done when using -mrelocatable"));
252b5132
RH		 2610 }
2611 }
2612 return;
2613 }
2614}
0baf16f2 2615
7e8d4ab4
AM		 2616/* Prevent elf_frob_file_before_adjust removing a weak undefined
2617 function descriptor sym if the corresponding code sym is used. */
2618
2619void
98027b10 2620ppc_frob_file_before_adjust (void)
0baf16f2 2621{
7e8d4ab4 2622 symbolS *symp;
9232bbb0 2623 asection *toc;
0baf16f2 2624
7e8d4ab4
AM		 2625 if (!ppc_obj64)
2626 return;
2627
2628 for (symp = symbol_rootP; symp; symp = symbol_next (symp))
0baf16f2 2629 {
7e8d4ab4
AM		 2630 const char *name;
2631 char *dotname;
2632 symbolS *dotsym;
7e8d4ab4
AM		 2633
2634 name = S_GET_NAME (symp);
2635 if (name[0] == '.')
2636 continue;
2637
2638 if (! S_IS_WEAK (symp)
2639 || S_IS_DEFINED (symp))
2640 continue;
2641
a44e2901 2642 dotname = concat (".", name, (char *) NULL);
461b725f 2643 dotsym = symbol_find_noref (dotname, 1);
7e8d4ab4
AM		 2644 free (dotname);
2645 if (dotsym != NULL && (symbol_used_p (dotsym)
2646 || symbol_used_in_reloc_p (dotsym)))
670ec21d
NC		 2647 symbol_mark_used (symp);
2648
0baf16f2
AM		 2649 }
2650
9232bbb0
AM		 2651 toc = bfd_get_section_by_name (stdoutput, ".toc");
2652 if (toc != NULL
01efc3af 2653 && toc_reloc_types != has_large_toc_reloc
fd361982 2654 && bfd_section_size (toc) > 0x10000)
9232bbb0 2655 as_warn (_("TOC section size exceeds 64k"));
a38a07e0
AM		 2656}
2657
2658/* .TOC. used in an opd entry as .TOC.@tocbase doesn't need to be
2659 emitted. Other uses of .TOC. will cause the symbol to be marked
2660 with BSF_KEEP in md_apply_fix. */
9232bbb0 2661
a38a07e0
AM		 2662void
2663ppc_elf_adjust_symtab (void)
2664{
2665 if (ppc_obj64)
2666 {
2667 symbolS *symp;
2668 symp = symbol_find (".TOC.");
2669 if (symp != NULL)
2670 {
2671 asymbol *bsym = symbol_get_bfdsym (symp);
2672 if ((bsym->flags & BSF_KEEP) == 0)
2673 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
a38a07e0
AM		 2674 }
2675 }
0baf16f2 2676}
252b5132
RH		 2677#endif /* OBJ_ELF */
2678\f
3e60bf4d 2679#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
3b8b57a9
AM		 2680/* See whether a symbol is in the TOC section. */
2681
2682static int
2683ppc_is_toc_sym (symbolS *sym)
2684{
3e60bf4d 2685#ifdef OBJ_XCOFF
9f6e76f4
TG		 2686 return (symbol_get_tc (sym)->symbol_class == XMC_TC
2687 || symbol_get_tc (sym)->symbol_class == XMC_TC0);
f50c47f1 2688#endif
3e60bf4d
AM		 2689#ifdef OBJ_ELF
2690 const char *sname = segment_name (S_GET_SEGMENT (sym));
2691 if (ppc_obj64)
2692 return strcmp (sname, ".toc") == 0;
2693 else
2694 return strcmp (sname, ".got") == 0;
2695#endif
2696}
2697#endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
252b5132
RH		 2698\f
2699
dc1d03fc 2700#ifdef OBJ_ELF
6a0c61b7
EZ		 2701#define APUID(a,v) ((((a) & 0xffff) << 16) | ((v) & 0xffff))
2702static void
98027b10 2703ppc_apuinfo_section_add (unsigned int apu, unsigned int version)
6a0c61b7
EZ		 2704{
2705 unsigned int i;
2706
2707 /* Check we don't already exist. */
2708 for (i = 0; i < ppc_apuinfo_num; i++)
dc1d03fc 2709 if (ppc_apuinfo_list[i] == APUID (apu, version))
6a0c61b7 2710 return;
b34976b6 2711
6a0c61b7
EZ		 2712 if (ppc_apuinfo_num == ppc_apuinfo_num_alloc)
2713 {
2714 if (ppc_apuinfo_num_alloc == 0)
2715 {
2716 ppc_apuinfo_num_alloc = 4;
325801bd 2717 ppc_apuinfo_list = XNEWVEC (unsigned long, ppc_apuinfo_num_alloc);
6a0c61b7
EZ		 2718 }
2719 else
2720 {
2721 ppc_apuinfo_num_alloc += 4;
325801bd
TS		 2722 ppc_apuinfo_list = XRESIZEVEC (unsigned long, ppc_apuinfo_list,
2723 ppc_apuinfo_num_alloc);
6a0c61b7
EZ		 2724 }
2725 }
dc1d03fc 2726 ppc_apuinfo_list[ppc_apuinfo_num++] = APUID (apu, version);
6a0c61b7
EZ		 2727}
2728#undef APUID
dc1d03fc 2729#endif
6a0c61b7 2730\f
dd7efa79
PB		 2731/* Various frobbings of labels and their addresses. */
2732
2733/* Symbols labelling the current insn. */
2734struct insn_label_list
2735{
2736 struct insn_label_list *next;
2737 symbolS *label;
2738};
2739
2740static struct insn_label_list *insn_labels;
2741static struct insn_label_list *free_insn_labels;
2742
2743static void
2744ppc_record_label (symbolS *sym)
2745{
2746 struct insn_label_list *l;
2747
2748 if (free_insn_labels == NULL)
2749 l = XNEW (struct insn_label_list);
2750 else
2751 {
2752 l = free_insn_labels;
2753 free_insn_labels = l->next;
2754 }
2755
2756 l->label = sym;
2757 l->next = insn_labels;
2758 insn_labels = l;
2759}
2760
2761static void
2762ppc_clear_labels (void)
2763{
2764 while (insn_labels != NULL)
2765 {
2766 struct insn_label_list *l = insn_labels;
2767 insn_labels = l->next;
2768 l->next = free_insn_labels;
2769 free_insn_labels = l;
2770 }
2771}
2772
2773void
2774ppc_start_line_hook (void)
2775{
2776 ppc_clear_labels ();
2777}
2778
2779void
2780ppc_new_dot_label (symbolS *sym)
2781{
2782 ppc_record_label (sym);
2783#ifdef OBJ_XCOFF
2784 /* Anchor this label to the current csect for relocations. */
2785 symbol_get_tc (sym)->within = ppc_current_csect;
2786#endif
2787}
2788
2789void
2790ppc_frob_label (symbolS *sym)
2791{
2792 ppc_record_label (sym);
2793
2794#ifdef OBJ_XCOFF
2795 /* Set the class of a label based on where it is defined. This handles
2796 symbols without suffixes. Also, move the symbol so that it follows
2797 the csect symbol. */
2798 if (ppc_current_csect != (symbolS *) NULL)
2799 {
2800 if (symbol_get_tc (sym)->symbol_class == -1)
2801 symbol_get_tc (sym)->symbol_class = symbol_get_tc (ppc_current_csect)->symbol_class;
2802
2803 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
2804 symbol_append (sym, symbol_get_tc (ppc_current_csect)->within,
2805 &symbol_rootP, &symbol_lastP);
2806 symbol_get_tc (ppc_current_csect)->within = sym;
2807 symbol_get_tc (sym)->within = ppc_current_csect;
2808 }
2809#endif
2810
2811#ifdef OBJ_ELF
2812 dwarf2_emit_label (sym);
2813#endif
2814}
6a0c61b7 2815
252b5132
RH		 2816/* We need to keep a list of fixups. We can't simply generate them as
2817 we go, because that would require us to first create the frag, and
2818 that would screw up references to ``.''. */
2819
2820struct ppc_fixup
2821{
2822 expressionS exp;
2823 int opindex;
2824 bfd_reloc_code_real_type reloc;
2825};
2826
2827#define MAX_INSN_FIXUPS (5)
2828
0e2779e9
AM		 2829/* Return the field size operated on by RELOC, and whether it is
2830 pc-relative in PC_RELATIVE. */
2831
2832static unsigned int
2833fixup_size (bfd_reloc_code_real_type reloc, bfd_boolean *pc_relative)
2834{
2835 unsigned int size = 0;
2836 bfd_boolean pcrel = FALSE;
2837
2838 switch (reloc)
2839 {
2840 /* This switch statement must handle all BFD_RELOC values
2841 possible in instruction fixups. As is, it handles all
2842 BFD_RELOC values used in bfd/elf64-ppc.c, bfd/elf32-ppc.c,
fe49679d 2843 bfd/coff-rs6000.c and bfd/coff64-rs6000.c.
0e2779e9
AM		 2844 Overkill since data and marker relocs need not be handled
2845 here, but this way we can be sure a needed fixup reloc isn't
2846 accidentally omitted. */
2847 case BFD_RELOC_PPC_EMB_MRKREF:
2848 case BFD_RELOC_VTABLE_ENTRY:
2849 case BFD_RELOC_VTABLE_INHERIT:
2850 break;
2851
2852 case BFD_RELOC_8:
2853 size = 1;
2854 break;
2855
2856 case BFD_RELOC_16:
2857 case BFD_RELOC_16_BASEREL:
2858 case BFD_RELOC_16_GOTOFF:
2859 case BFD_RELOC_GPREL16:
2860 case BFD_RELOC_HI16:
2861 case BFD_RELOC_HI16_BASEREL:
2862 case BFD_RELOC_HI16_GOTOFF:
2863 case BFD_RELOC_HI16_PLTOFF:
2864 case BFD_RELOC_HI16_S:
2865 case BFD_RELOC_HI16_S_BASEREL:
2866 case BFD_RELOC_HI16_S_GOTOFF:
2867 case BFD_RELOC_HI16_S_PLTOFF:
2868 case BFD_RELOC_LO16:
2869 case BFD_RELOC_LO16_BASEREL:
2870 case BFD_RELOC_LO16_GOTOFF:
2871 case BFD_RELOC_LO16_PLTOFF:
2872 case BFD_RELOC_PPC64_ADDR16_DS:
2873 case BFD_RELOC_PPC64_ADDR16_HIGH:
2874 case BFD_RELOC_PPC64_ADDR16_HIGHA:
5663e321
AM		 2875 case BFD_RELOC_PPC64_ADDR16_HIGHER34:
2876 case BFD_RELOC_PPC64_ADDR16_HIGHERA34:
2877 case BFD_RELOC_PPC64_ADDR16_HIGHEST34:
2878 case BFD_RELOC_PPC64_ADDR16_HIGHESTA34:
0e2779e9
AM		 2879 case BFD_RELOC_PPC64_ADDR16_LO_DS:
2880 case BFD_RELOC_PPC64_DTPREL16_DS:
2881 case BFD_RELOC_PPC64_DTPREL16_HIGH:
2882 case BFD_RELOC_PPC64_DTPREL16_HIGHA:
2883 case BFD_RELOC_PPC64_DTPREL16_HIGHER:
2884 case BFD_RELOC_PPC64_DTPREL16_HIGHERA:
2885 case BFD_RELOC_PPC64_DTPREL16_HIGHEST:
2886 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA:
2887 case BFD_RELOC_PPC64_DTPREL16_LO_DS:
2888 case BFD_RELOC_PPC64_GOT16_DS:
2889 case BFD_RELOC_PPC64_GOT16_LO_DS:
2890 case BFD_RELOC_PPC64_HIGHER:
2891 case BFD_RELOC_PPC64_HIGHER_S:
2892 case BFD_RELOC_PPC64_HIGHEST:
2893 case BFD_RELOC_PPC64_HIGHEST_S:
2894 case BFD_RELOC_PPC64_PLT16_LO_DS:
2895 case BFD_RELOC_PPC64_PLTGOT16:
2896 case BFD_RELOC_PPC64_PLTGOT16_DS:
2897 case BFD_RELOC_PPC64_PLTGOT16_HA:
2898 case BFD_RELOC_PPC64_PLTGOT16_HI:
2899 case BFD_RELOC_PPC64_PLTGOT16_LO:
2900 case BFD_RELOC_PPC64_PLTGOT16_LO_DS:
2901 case BFD_RELOC_PPC64_SECTOFF_DS:
2902 case BFD_RELOC_PPC64_SECTOFF_LO_DS:
2903 case BFD_RELOC_PPC64_TOC16_DS:
2904 case BFD_RELOC_PPC64_TOC16_HA:
2905 case BFD_RELOC_PPC64_TOC16_HI:
2906 case BFD_RELOC_PPC64_TOC16_LO:
2907 case BFD_RELOC_PPC64_TOC16_LO_DS:
2908 case BFD_RELOC_PPC64_TPREL16_DS:
2909 case BFD_RELOC_PPC64_TPREL16_HIGH:
2910 case BFD_RELOC_PPC64_TPREL16_HIGHA:
2911 case BFD_RELOC_PPC64_TPREL16_HIGHER:
2912 case BFD_RELOC_PPC64_TPREL16_HIGHERA:
2913 case BFD_RELOC_PPC64_TPREL16_HIGHEST:
2914 case BFD_RELOC_PPC64_TPREL16_HIGHESTA:
2915 case BFD_RELOC_PPC64_TPREL16_LO_DS:
2916#ifdef OBJ_XCOFF
2917 case BFD_RELOC_PPC_BA16:
2918#endif
2919 case BFD_RELOC_PPC_DTPREL16:
2920 case BFD_RELOC_PPC_DTPREL16_HA:
2921 case BFD_RELOC_PPC_DTPREL16_HI:
2922 case BFD_RELOC_PPC_DTPREL16_LO:
2923 case BFD_RELOC_PPC_EMB_NADDR16:
2924 case BFD_RELOC_PPC_EMB_NADDR16_HA:
2925 case BFD_RELOC_PPC_EMB_NADDR16_HI:
2926 case BFD_RELOC_PPC_EMB_NADDR16_LO:
2927 case BFD_RELOC_PPC_EMB_RELSDA:
2928 case BFD_RELOC_PPC_EMB_RELSEC16:
2929 case BFD_RELOC_PPC_EMB_RELST_LO:
2930 case BFD_RELOC_PPC_EMB_RELST_HI:
2931 case BFD_RELOC_PPC_EMB_RELST_HA:
2932 case BFD_RELOC_PPC_EMB_SDA2I16:
2933 case BFD_RELOC_PPC_EMB_SDA2REL:
2934 case BFD_RELOC_PPC_EMB_SDAI16:
2935 case BFD_RELOC_PPC_GOT_DTPREL16:
2936 case BFD_RELOC_PPC_GOT_DTPREL16_HA:
2937 case BFD_RELOC_PPC_GOT_DTPREL16_HI:
2938 case BFD_RELOC_PPC_GOT_DTPREL16_LO:
2939 case BFD_RELOC_PPC_GOT_TLSGD16:
2940 case BFD_RELOC_PPC_GOT_TLSGD16_HA:
2941 case BFD_RELOC_PPC_GOT_TLSGD16_HI:
2942 case BFD_RELOC_PPC_GOT_TLSGD16_LO:
2943 case BFD_RELOC_PPC_GOT_TLSLD16:
2944 case BFD_RELOC_PPC_GOT_TLSLD16_HA:
2945 case BFD_RELOC_PPC_GOT_TLSLD16_HI:
2946 case BFD_RELOC_PPC_GOT_TLSLD16_LO:
2947 case BFD_RELOC_PPC_GOT_TPREL16:
2948 case BFD_RELOC_PPC_GOT_TPREL16_HA:
2949 case BFD_RELOC_PPC_GOT_TPREL16_HI:
2950 case BFD_RELOC_PPC_GOT_TPREL16_LO:
2951 case BFD_RELOC_PPC_TOC16:
2952 case BFD_RELOC_PPC_TPREL16:
2953 case BFD_RELOC_PPC_TPREL16_HA:
2954 case BFD_RELOC_PPC_TPREL16_HI:
2955 case BFD_RELOC_PPC_TPREL16_LO:
2956 size = 2;
2957 break;
2958
2959 case BFD_RELOC_16_PCREL:
2960 case BFD_RELOC_HI16_PCREL:
2961 case BFD_RELOC_HI16_S_PCREL:
2962 case BFD_RELOC_LO16_PCREL:
2963 case BFD_RELOC_PPC64_REL16_HIGH:
2964 case BFD_RELOC_PPC64_REL16_HIGHA:
2965 case BFD_RELOC_PPC64_REL16_HIGHER:
5663e321 2966 case BFD_RELOC_PPC64_REL16_HIGHER34:
0e2779e9 2967 case BFD_RELOC_PPC64_REL16_HIGHERA:
5663e321 2968 case BFD_RELOC_PPC64_REL16_HIGHERA34:
0e2779e9 2969 case BFD_RELOC_PPC64_REL16_HIGHEST:
5663e321 2970 case BFD_RELOC_PPC64_REL16_HIGHEST34:
0e2779e9 2971 case BFD_RELOC_PPC64_REL16_HIGHESTA:
5663e321 2972 case BFD_RELOC_PPC64_REL16_HIGHESTA34:
0e2779e9
AM		 2973#ifdef OBJ_XCOFF
2974 case BFD_RELOC_PPC_B16:
2975#endif
2976 case BFD_RELOC_PPC_VLE_REL8:
2977 size = 2;
2978 pcrel = TRUE;
2979 break;
2980
0e2779e9 2981 case BFD_RELOC_32:
0e2779e9
AM		 2982 case BFD_RELOC_32_PLTOFF:
2983#ifdef OBJ_XCOFF
2984 case BFD_RELOC_CTOR:
2985#endif
2986 case BFD_RELOC_PPC64_ENTRY:
2987 case BFD_RELOC_PPC_16DX_HA:
2988#ifndef OBJ_XCOFF
2989 case BFD_RELOC_PPC_BA16:
2990#endif
2991 case BFD_RELOC_PPC_BA16_BRNTAKEN:
2992 case BFD_RELOC_PPC_BA16_BRTAKEN:
2993 case BFD_RELOC_PPC_BA26:
2994 case BFD_RELOC_PPC_EMB_BIT_FLD:
2995 case BFD_RELOC_PPC_EMB_NADDR32:
2996 case BFD_RELOC_PPC_EMB_SDA21:
2997 case BFD_RELOC_PPC_TLS:
2998 case BFD_RELOC_PPC_TLSGD:
2999 case BFD_RELOC_PPC_TLSLD:
3000 case BFD_RELOC_PPC_VLE_HA16A:
3001 case BFD_RELOC_PPC_VLE_HA16D:
3002 case BFD_RELOC_PPC_VLE_HI16A:
3003 case BFD_RELOC_PPC_VLE_HI16D:
3004 case BFD_RELOC_PPC_VLE_LO16A:
3005 case BFD_RELOC_PPC_VLE_LO16D:
3006 case BFD_RELOC_PPC_VLE_SDA21:
3007 case BFD_RELOC_PPC_VLE_SDA21_LO:
3008 case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
3009 case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
3010 case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
3011 case BFD_RELOC_PPC_VLE_SDAREL_HI16D:
3012 case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
3013 case BFD_RELOC_PPC_VLE_SDAREL_LO16D:
c213164a 3014 case BFD_RELOC_PPC64_TLS_PCREL:
0e2779e9
AM		 3015 case BFD_RELOC_RVA:
3016 size = 4;
3017 break;
3018
3019 case BFD_RELOC_24_PLT_PCREL:
3020 case BFD_RELOC_32_PCREL:
3021 case BFD_RELOC_32_PLT_PCREL:
3022 case BFD_RELOC_PPC64_REL24_NOTOC:
3023#ifndef OBJ_XCOFF
3024 case BFD_RELOC_PPC_B16:
3025#endif
3026 case BFD_RELOC_PPC_B16_BRNTAKEN:
3027 case BFD_RELOC_PPC_B16_BRTAKEN:
3028 case BFD_RELOC_PPC_B26:
3029 case BFD_RELOC_PPC_LOCAL24PC:
3030 case BFD_RELOC_PPC_REL16DX_HA:
3031 case BFD_RELOC_PPC_VLE_REL15:
3032 case BFD_RELOC_PPC_VLE_REL24:
3033 size = 4;
3034 pcrel = TRUE;
3035 break;
3036
3037#ifndef OBJ_XCOFF
3038 case BFD_RELOC_CTOR:
3039#endif
3040 case BFD_RELOC_PPC_COPY:
3041 case BFD_RELOC_PPC_DTPMOD:
3042 case BFD_RELOC_PPC_DTPREL:
3043 case BFD_RELOC_PPC_GLOB_DAT:
3044 case BFD_RELOC_PPC_TPREL:
3045 size = ppc_obj64 ? 8 : 4;
3046 break;
3047
3048 case BFD_RELOC_64:
3049 case BFD_RELOC_64_PLTOFF:
3050 case BFD_RELOC_PPC64_ADDR64_LOCAL:
5663e321
AM		 3051 case BFD_RELOC_PPC64_D28:
3052 case BFD_RELOC_PPC64_D34:
3053 case BFD_RELOC_PPC64_D34_LO:
3054 case BFD_RELOC_PPC64_D34_HI30:
3055 case BFD_RELOC_PPC64_D34_HA30:
c213164a
AM		 3056 case BFD_RELOC_PPC64_TPREL34:
3057 case BFD_RELOC_PPC64_DTPREL34:
0e2779e9
AM		 3058 case BFD_RELOC_PPC64_TOC:
3059 size = 8;
3060 break;
3061
3062 case BFD_RELOC_64_PCREL:
3063 case BFD_RELOC_64_PLT_PCREL:
5663e321 3064 case BFD_RELOC_PPC64_GOT_PCREL34:
87c69f97
AM		 3065 case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34:
3066 case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34:
3067 case BFD_RELOC_PPC64_GOT_TPREL_PCREL34:
3068 case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34:
5663e321
AM		 3069 case BFD_RELOC_PPC64_PCREL28:
3070 case BFD_RELOC_PPC64_PCREL34:
3071 case BFD_RELOC_PPC64_PLT_PCREL34:
0e2779e9
AM		 3072 size = 8;
3073 pcrel = TRUE;
3074 break;
3075
3076 default:
3077 abort ();
3078 }
3079
3080 if (ENABLE_CHECKING)
3081 {
3082 reloc_howto_type *reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
3083 if (reloc_howto != NULL
3084 && (size != bfd_get_reloc_size (reloc_howto)
3085 || pcrel != reloc_howto->pc_relative))
3086 {
3087 as_bad (_("%s howto doesn't match size/pcrel in gas"),
3088 reloc_howto->name);
3089 abort ();
3090 }
3091 }
3092 *pc_relative = pcrel;
3093 return size;
3094}
3095
a894d76a 3096#ifdef OBJ_ELF
160eba93
AM		 3097/* If we have parsed a call to __tls_get_addr, parse an argument like
3098 (gd0@tlsgd). *STR is the leading parenthesis on entry. If an arg
3099 is successfully parsed, *STR is updated past the trailing
3100 parenthesis and trailing white space, and *TLS_FIX contains the
3101 reloc and arg expression. */
3102
3103static int
3104parse_tls_arg (char **str, const expressionS *exp, struct ppc_fixup *tls_fix)
3105{
3106 const char *sym_name = S_GET_NAME (exp->X_add_symbol);
3107 if (sym_name[0] == '.')
3108 ++sym_name;
3109
3110 tls_fix->reloc = BFD_RELOC_NONE;
9e7028aa
AM		 3111 if (strncasecmp (sym_name, "__tls_get_addr", 14) == 0
3112 && (sym_name[14] == 0
3113 || strcasecmp (sym_name + 14, "_desc") == 0
3114 || strcasecmp (sym_name + 14, "_opt") == 0))
160eba93
AM		 3115 {
3116 char *hold = input_line_pointer;
3117 input_line_pointer = *str + 1;
3118 expression (&tls_fix->exp);
3119 if (tls_fix->exp.X_op == O_symbol)
3120 {
3121 if (strncasecmp (input_line_pointer, "@tlsgd)", 7) == 0)
3122 tls_fix->reloc = BFD_RELOC_PPC_TLSGD;
3123 else if (strncasecmp (input_line_pointer, "@tlsld)", 7) == 0)
3124 tls_fix->reloc = BFD_RELOC_PPC_TLSLD;
3125 if (tls_fix->reloc != BFD_RELOC_NONE)
3126 {
3127 input_line_pointer += 7;
3128 SKIP_WHITESPACE ();
3129 *str = input_line_pointer;
3130 }
3131 }
3132 input_line_pointer = hold;
3133 }
3134 return tls_fix->reloc != BFD_RELOC_NONE;
3135}
a894d76a 3136#endif
160eba93 3137
252b5132
RH		 3138/* This routine is called for each instruction to be assembled. */
3139
3140void
98027b10 3141md_assemble (char *str)
252b5132
RH		 3142{
3143 char *s;
3144 const struct powerpc_opcode *opcode;
0f873fd5 3145 uint64_t insn;
252b5132 3146 const unsigned char *opindex_ptr;
252b5132
RH		 3147 int need_paren;
3148 int next_opindex;
3149 struct ppc_fixup fixups[MAX_INSN_FIXUPS];
3150 int fc;
3151 char *f;
a9479dc0 3152 int addr_mask;
252b5132 3153 int i;
b9c361e0 3154 unsigned int insn_length;
252b5132
RH		 3155
3156 /* Get the opcode. */
3882b010 3157 for (s = str; *s != '\0' && ! ISSPACE (*s); s++)
252b5132
RH		 3158 ;
3159 if (*s != '\0')
3160 *s++ = '\0';
3161
3162 /* Look up the opcode in the hash table. */
3163 opcode = (const struct powerpc_opcode *) hash_find (ppc_hash, str);
3164 if (opcode == (const struct powerpc_opcode *) NULL)
3165 {
3166 const struct powerpc_macro *macro;
3167
3168 macro = (const struct powerpc_macro *) hash_find (ppc_macro_hash, str);
3169 if (macro == (const struct powerpc_macro *) NULL)
d6ed37ed 3170 as_bad (_("unrecognized opcode: `%s'"), str);
252b5132
RH		 3171 else
3172 ppc_macro (s, macro);
3173
dd7efa79 3174 ppc_clear_labels ();
252b5132
RH		 3175 return;
3176 }
3177
3178 insn = opcode->opcode;
86c0f617
AM		 3179 if (!target_big_endian
3180 && ((insn & ~(1 << 26)) == 46u << 26
3181 || (insn & ~(0xc0 << 1)) == (31u << 26 | 533 << 1)))
3182 {
3183 /* lmw, stmw, lswi, lswx, stswi, stswx */
3184 as_bad (_("`%s' invalid when little-endian"), str);
3185 ppc_clear_labels ();
3186 return;
3187 }
252b5132
RH		 3188
3189 str = s;
3882b010 3190 while (ISSPACE (*str))
252b5132
RH		 3191 ++str;
3192
3193 /* PowerPC operands are just expressions. The only real issue is
9cf7e568
AM		 3194 that a few operand types are optional. If an instruction has
3195 multiple optional operands and one is omitted, then all optional
3196 operands past the first omitted one must also be omitted. */
3197 int num_optional_operands = 0;
3198 int num_optional_provided = 0;
252b5132
RH		 3199
3200 /* Gather the operands. */
3201 need_paren = 0;
3202 next_opindex = 0;
3203 fc = 0;
3204 for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
3205 {
3206 const struct powerpc_operand *operand;
3207 const char *errmsg;
3208 char *hold;
3209 expressionS ex;
3210 char endc;
3211
3212 if (next_opindex == 0)
3213 operand = &powerpc_operands[*opindex_ptr];
3214 else
3215 {
3216 operand = &powerpc_operands[next_opindex];
3217 next_opindex = 0;
3218 }
252b5132
RH		 3219 errmsg = NULL;
3220
252b5132 3221 /* If this is an optional operand, and we are skipping it, just
9cf7e568 3222 insert the default value, usually a zero. */
252b5132 3223 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
9cf7e568 3224 && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64))
252b5132 3225 {
9cf7e568
AM		 3226 if (num_optional_operands == 0)
3227 {
3228 const unsigned char *optr;
3229 int total = 0;
3230 int provided = 0;
3231 int omitted;
3232
3233 s = str;
3234 for (optr = opindex_ptr; *optr != 0; optr++)
3235 {
3236 const struct powerpc_operand *op;
3237 op = &powerpc_operands[*optr];
3238
3239 ++total;
3240
3241 if ((op->flags & PPC_OPERAND_OPTIONAL) != 0
3242 && !((op->flags & PPC_OPERAND_OPTIONAL32) != 0
3243 && ppc_obj64))
3244 ++num_optional_operands;
3245
3246 if (s != NULL && *s != '\0')
3247 {
3248 ++provided;
3249
3250 /* Look for the start of the next operand. */
3251 if ((op->flags & PPC_OPERAND_PARENS) != 0)
3252 s = strpbrk (s, "(,");
3253 else
3254 s = strchr (s, ',');
3255
3256 if (s != NULL)
3257 ++s;
3258 }
3259 }
3260 omitted = total - provided;
3261 num_optional_provided = num_optional_operands - omitted;
3262 }
3263 if (--num_optional_provided < 0)
252b5132 3264 {
9cf7e568
AM		 3265 int64_t val = ppc_optional_operand_value (operand, insn, ppc_cpu,
3266 num_optional_provided);
3267 if (operand->insert)
3268 {
3269 insn = (*operand->insert) (insn, val, ppc_cpu, &errmsg);
3270 if (errmsg != (const char *) NULL)
3271 as_bad ("%s", errmsg);
3272 }
3273 else if (operand->shift >= 0)
3274 insn |= (val & operand->bitm) << operand->shift;
3275 else
3276 insn |= (val & operand->bitm) >> -operand->shift;
3277
3278 if ((operand->flags & PPC_OPERAND_NEXT) != 0)
3279 next_opindex = *opindex_ptr + 1;
3280 continue;
252b5132 3281 }
252b5132
RH		 3282 }
3283
3284 /* Gather the operand. */
3285 hold = input_line_pointer;
3286 input_line_pointer = str;
3287
fe49679d
AM		 3288 if ((reg_names_p
3289 && (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
3290 || ((operand->flags & PPC_OPERAND_CR_REG) != 0)))
3291 || !register_name (&ex))
252b5132 3292 {
fe49679d 3293 char save_lex = lex_type['%'];
252b5132 3294
fe49679d
AM		 3295 if (((operand->flags & PPC_OPERAND_CR_REG) != 0)
3296 || (operand->flags & PPC_OPERAND_CR_BIT) != 0)
252b5132 3297 {
fe49679d
AM		 3298 cr_operand = TRUE;
3299 lex_type['%'] |= LEX_BEGIN_NAME;
252b5132 3300 }
fe49679d
AM		 3301 expression (&ex);
3302 cr_operand = FALSE;
3303 lex_type['%'] = save_lex;
252b5132
RH		 3304 }
3305
3306 str = input_line_pointer;
3307 input_line_pointer = hold;
3308
3309 if (ex.X_op == O_illegal)
3310 as_bad (_("illegal operand"));
3311 else if (ex.X_op == O_absent)
3312 as_bad (_("missing operand"));
3313 else if (ex.X_op == O_register)
3314 {
7e0de605
AM		 3315 if ((ex.X_md
3316 & ~operand->flags
3317 & (PPC_OPERAND_GPR | PPC_OPERAND_FPR | PPC_OPERAND_VR
3318 | PPC_OPERAND_VSR | PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG
aa3c112f 3319 | PPC_OPERAND_SPR | PPC_OPERAND_GQR | PPC_OPERAND_ACC)) != 0
7e0de605
AM		 3320 && !((ex.X_md & PPC_OPERAND_GPR) != 0
3321 && ex.X_add_number != 0
3322 && (operand->flags & PPC_OPERAND_GPR_0) != 0))
ece5dcc1 3323 as_warn (_("invalid register expression"));
4b1c0f7e 3324 insn = ppc_insert_operand (insn, operand, ex.X_add_number,
783de163 3325 ppc_cpu, (char *) NULL, 0);
252b5132
RH		 3326 }
3327 else if (ex.X_op == O_constant)
3328 {
3329#ifdef OBJ_ELF
81d4177b 3330 /* Allow @HA, @L, @H on constants. */
3b8b57a9 3331 bfd_reloc_code_real_type reloc;
252b5132
RH		 3332 char *orig_str = str;
3333
62ebcb5c 3334 if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE)
252b5132
RH		 3335 switch (reloc)
3336 {
3337 default:
3338 str = orig_str;
3339 break;
3340
3341 case BFD_RELOC_LO16:
f9c6b907
AM		 3342 ex.X_add_number &= 0xffff;
3343 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
0baf16f2 3344 ex.X_add_number = SEX16 (ex.X_add_number);
252b5132
RH		 3345 break;
3346
3347 case BFD_RELOC_HI16:
f9c6b907
AM		 3348 if (REPORT_OVERFLOW_HI && ppc_obj64)
3349 {
3350 /* PowerPC64 @h is tested for overflow. */
3351 ex.X_add_number = (addressT) ex.X_add_number >> 16;
3352 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3353 {
3354 addressT sign = (((addressT) -1 >> 16) + 1) >> 1;
3355 ex.X_add_number
3356 = ((addressT) ex.X_add_number ^ sign) - sign;
3357 }
3358 break;
3359 }
2b0f3761 3360 /* Fallthru */
f9c6b907
AM		 3361
3362 case BFD_RELOC_PPC64_ADDR16_HIGH:
3363 ex.X_add_number = PPC_HI (ex.X_add_number);
3364 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3365 ex.X_add_number = SEX16 (ex.X_add_number);
252b5132
RH		 3366 break;
3367
3368 case BFD_RELOC_HI16_S:
f9c6b907
AM		 3369 if (REPORT_OVERFLOW_HI && ppc_obj64)
3370 {
3371 /* PowerPC64 @ha is tested for overflow. */
3372 ex.X_add_number
3373 = ((addressT) ex.X_add_number + 0x8000) >> 16;
3374 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3375 {
3376 addressT sign = (((addressT) -1 >> 16) + 1) >> 1;
3377 ex.X_add_number
3378 = ((addressT) ex.X_add_number ^ sign) - sign;
3379 }
3380 break;
3381 }
2b0f3761 3382 /* Fallthru */
f9c6b907
AM		 3383
3384 case BFD_RELOC_PPC64_ADDR16_HIGHA:
3385 ex.X_add_number = PPC_HA (ex.X_add_number);
3386 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3387 ex.X_add_number = SEX16 (ex.X_add_number);
0baf16f2
AM		 3388 break;
3389
0baf16f2 3390 case BFD_RELOC_PPC64_HIGHER:
f9c6b907
AM		 3391 ex.X_add_number = PPC_HIGHER (ex.X_add_number);
3392 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3393 ex.X_add_number = SEX16 (ex.X_add_number);
0baf16f2
AM		 3394 break;
3395
3396 case BFD_RELOC_PPC64_HIGHER_S:
f9c6b907
AM		 3397 ex.X_add_number = PPC_HIGHERA (ex.X_add_number);
3398 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3399 ex.X_add_number = SEX16 (ex.X_add_number);
252b5132 3400 break;
0baf16f2
AM		 3401
3402 case BFD_RELOC_PPC64_HIGHEST:
f9c6b907
AM		 3403 ex.X_add_number = PPC_HIGHEST (ex.X_add_number);
3404 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3405 ex.X_add_number = SEX16 (ex.X_add_number);
0baf16f2
AM		 3406 break;
3407
3408 case BFD_RELOC_PPC64_HIGHEST_S:
f9c6b907
AM		 3409 ex.X_add_number = PPC_HIGHESTA (ex.X_add_number);
3410 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3411 ex.X_add_number = SEX16 (ex.X_add_number);
0baf16f2 3412 break;
252b5132 3413 }
0baf16f2 3414#endif /* OBJ_ELF */
252b5132 3415 insn = ppc_insert_operand (insn, operand, ex.X_add_number,
783de163 3416 ppc_cpu, (char *) NULL, 0);
252b5132 3417 }
727fc41e 3418 else
252b5132 3419 {
62ebcb5c 3420 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
3b8b57a9 3421#ifdef OBJ_ELF
160eba93
AM		 3422 /* Look for a __tls_get_addr arg using the insane old syntax. */
3423 if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS
3424 && parse_tls_arg (&str, &ex, &fixups[fc]))
cdba85ec 3425 {
160eba93
AM		 3426 fixups[fc].opindex = *opindex_ptr;
3427 ++fc;
252b5132
RH		 3428 }
3429
62ebcb5c 3430 if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE)
0baf16f2 3431 {
b9c361e0
JL		 3432 /* If VLE-mode convert LO/HI/HA relocations. */
3433 if (opcode->flags & PPC_OPCODE_VLE)
3434 {
0f873fd5 3435 uint64_t tmp_insn = insn & opcode->mask;
3739860c 3436
08dc996f 3437 int use_a_reloc = (tmp_insn == E_OR2I_INSN
b9c361e0
JL		 3438 || tmp_insn == E_AND2I_DOT_INSN
3439 || tmp_insn == E_OR2IS_INSN
bb6bf75e 3440 || tmp_insn == E_LI_INSN
b9c361e0
JL		 3441 || tmp_insn == E_LIS_INSN
3442 || tmp_insn == E_AND2IS_DOT_INSN);
3443
3444
08dc996f 3445 int use_d_reloc = (tmp_insn == E_ADD2I_DOT_INSN
b9c361e0
JL		 3446 || tmp_insn == E_ADD2IS_INSN
3447 || tmp_insn == E_CMP16I_INSN
3448 || tmp_insn == E_MULL2I_INSN
3449 || tmp_insn == E_CMPL16I_INSN
3450 || tmp_insn == E_CMPH16I_INSN
3451 || tmp_insn == E_CMPHL16I_INSN);
3452
3453 switch (reloc)
3454 {
3455 default:
3456 break;
3457
3458 case BFD_RELOC_PPC_EMB_SDA21:
3459 reloc = BFD_RELOC_PPC_VLE_SDA21;
3460 break;
3461
3462 case BFD_RELOC_LO16:
3463 if (use_d_reloc)
3464 reloc = BFD_RELOC_PPC_VLE_LO16D;
3465 else if (use_a_reloc)
3466 reloc = BFD_RELOC_PPC_VLE_LO16A;
3467 break;
3468
3469 case BFD_RELOC_HI16:
3470 if (use_d_reloc)
3471 reloc = BFD_RELOC_PPC_VLE_HI16D;
3472 else if (use_a_reloc)
3473 reloc = BFD_RELOC_PPC_VLE_HI16A;
3474 break;
3739860c 3475
b9c361e0
JL		 3476 case BFD_RELOC_HI16_S:
3477 if (use_d_reloc)
3478 reloc = BFD_RELOC_PPC_VLE_HA16D;
3479 else if (use_a_reloc)
3480 reloc = BFD_RELOC_PPC_VLE_HA16A;
3481 break;
3482
3483 case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
3484 if (use_d_reloc)
3485 reloc = BFD_RELOC_PPC_VLE_SDAREL_LO16D;
3486 break;
3487
3488 case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
3489 if (use_d_reloc)
3490 reloc = BFD_RELOC_PPC_VLE_SDAREL_HI16D;
3491 break;
3492
3493 case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
3494 if (use_d_reloc)
3495 reloc = BFD_RELOC_PPC_VLE_SDAREL_HA16D;
3496 break;
3497 }
3498 }
bb6bf75e
AM		 3499
3500 /* TLS and other tweaks. */
3501 switch (reloc)
3502 {
3503 default:
3504 break;
3505
3506 case BFD_RELOC_PPC_TLS:
c213164a 3507 case BFD_RELOC_PPC64_TLS_PCREL:
bb6bf75e
AM		 3508 if (!_bfd_elf_ppc_at_tls_transform (opcode->opcode, 0))
3509 as_bad (_("@tls may not be used with \"%s\" operands"),
3510 opcode->name);
3511 else if (operand->shift != 11)
3512 as_bad (_("@tls may only be used in last operand"));
3513 else
3514 insn = ppc_insert_operand (insn, operand,
3515 ppc_obj64 ? 13 : 2,
3516 ppc_cpu, (char *) NULL, 0);
3517 break;
3518
3519 /* We'll only use the 32 (or 64) bit form of these relocations
c213164a 3520 in constants. Instructions get the 16 or 34 bit form. */
bb6bf75e 3521 case BFD_RELOC_PPC_DTPREL:
c213164a
AM		 3522 if (operand->bitm == 0x3ffffffffULL)
3523 reloc = BFD_RELOC_PPC64_DTPREL34;
3524 else
3525 reloc = BFD_RELOC_PPC_DTPREL16;
bb6bf75e
AM		 3526 break;
3527
3528 case BFD_RELOC_PPC_TPREL:
c213164a
AM		 3529 if (operand->bitm == 0x3ffffffffULL)
3530 reloc = BFD_RELOC_PPC64_TPREL34;
3531 else
3532 reloc = BFD_RELOC_PPC_TPREL16;
bb6bf75e
AM		 3533 break;
3534
5663e321
AM		 3535 case BFD_RELOC_PPC64_PCREL34:
3536 if (operand->bitm == 0xfffffffULL)
3537 {
3538 reloc = BFD_RELOC_PPC64_PCREL28;
3539 break;
3540 }
3541 /* Fall through. */
3542 case BFD_RELOC_PPC64_GOT_PCREL34:
3543 case BFD_RELOC_PPC64_PLT_PCREL34:
87c69f97
AM		 3544 case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34:
3545 case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34:
3546 case BFD_RELOC_PPC64_GOT_TPREL_PCREL34:
3547 case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34:
5663e321 3548 if (operand->bitm != 0x3ffffffffULL
bb6bf75e 3549 || (operand->flags & PPC_OPERAND_NEGATIVE) != 0)
5663e321
AM		 3550 as_warn (_("%s unsupported on this instruction"), "@pcrel");
3551 break;
3552
3553 case BFD_RELOC_LO16:
3554 if (operand->bitm == 0x3ffffffffULL
3555 && (operand->flags & PPC_OPERAND_NEGATIVE) == 0)
3556 reloc = BFD_RELOC_PPC64_D34_LO;
3557 else if ((operand->bitm | 0xf) != 0xffff
3558 || operand->shift != 0
3559 || (operand->flags & PPC_OPERAND_NEGATIVE) != 0)
bb6bf75e
AM		 3560 as_warn (_("%s unsupported on this instruction"), "@l");
3561 break;
3562
3563 case BFD_RELOC_HI16:
5663e321
AM		 3564 if (operand->bitm == 0x3ffffffffULL
3565 && (operand->flags & PPC_OPERAND_NEGATIVE) == 0)
3566 reloc = BFD_RELOC_PPC64_D34_HI30;
3567 else if (operand->bitm != 0xffff
3568 || operand->shift != 0
3569 || (operand->flags & PPC_OPERAND_NEGATIVE) != 0)
bb6bf75e
AM		 3570 as_warn (_("%s unsupported on this instruction"), "@h");
3571 break;
3572
3573 case BFD_RELOC_HI16_S:
5663e321
AM		 3574 if (operand->bitm == 0x3ffffffffULL
3575 && (operand->flags & PPC_OPERAND_NEGATIVE) == 0)
3576 reloc = BFD_RELOC_PPC64_D34_HA30;
3577 else if (operand->bitm == 0xffff
3578 && operand->shift == (int) PPC_OPSHIFT_INV
3579 && opcode->opcode == (19 << 26) + (2 << 1))
bb6bf75e
AM		 3580 /* addpcis. */
3581 reloc = BFD_RELOC_PPC_16DX_HA;
3582 else if (operand->bitm != 0xffff
3583 || operand->shift != 0
3584 || (operand->flags & PPC_OPERAND_NEGATIVE) != 0)
3585 as_warn (_("%s unsupported on this instruction"), "@ha");
3586 }
0baf16f2 3587 }
3b8b57a9
AM		 3588#endif /* OBJ_ELF */
3589
62ebcb5c 3590 if (reloc != BFD_RELOC_NONE)
3b8b57a9
AM		 3591 ;
3592 /* Determine a BFD reloc value based on the operand information.
3593 We are only prepared to turn a few of the operands into
3594 relocs. */
a0593ad9
AM		 3595 else if ((operand->flags & (PPC_OPERAND_RELATIVE
3596 | PPC_OPERAND_ABSOLUTE)) != 0
3b8b57a9
AM		 3597 && operand->bitm == 0x3fffffc
3598 && operand->shift == 0)
3599 reloc = BFD_RELOC_PPC_B26;
a0593ad9
AM		 3600 else if ((operand->flags & (PPC_OPERAND_RELATIVE
3601 | PPC_OPERAND_ABSOLUTE)) != 0
3b8b57a9
AM		 3602 && operand->bitm == 0xfffc
3603 && operand->shift == 0)
3604 reloc = BFD_RELOC_PPC_B16;
3605 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
3606 && operand->bitm == 0x1fe
3607 && operand->shift == -1)
3608 reloc = BFD_RELOC_PPC_VLE_REL8;
3609 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
3610 && operand->bitm == 0xfffe
3611 && operand->shift == 0)
3612 reloc = BFD_RELOC_PPC_VLE_REL15;
3613 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
3614 && operand->bitm == 0x1fffffe
3615 && operand->shift == 0)
3616 reloc = BFD_RELOC_PPC_VLE_REL24;
a0593ad9 3617 else if ((operand->flags & PPC_OPERAND_NEGATIVE) == 0
3b8b57a9
AM		 3618 && (operand->bitm & 0xfff0) == 0xfff0
3619 && operand->shift == 0)
3620 {
f50c47f1 3621 reloc = BFD_RELOC_16;
3e60bf4d 3622#if defined OBJ_XCOFF || defined OBJ_ELF
f50c47f1 3623 /* Note: the symbol may be not yet defined. */
a0593ad9
AM		 3624 if ((operand->flags & PPC_OPERAND_PARENS) != 0
3625 && ppc_is_toc_sym (ex.X_add_symbol))
3e60bf4d
AM		 3626 {
3627 reloc = BFD_RELOC_PPC_TOC16;
3628#ifdef OBJ_ELF
3629 as_warn (_("assuming %s on symbol"),
3630 ppc_obj64 ? "@toc" : "@xgot");
3631#endif
3632 }
3b8b57a9 3633#endif
3b8b57a9 3634 }
5663e321
AM		 3635 else if (operand->bitm == 0x3ffffffffULL)
3636 reloc = BFD_RELOC_PPC64_D34;
3637 else if (operand->bitm == 0xfffffffULL)
3638 reloc = BFD_RELOC_PPC64_D28;
a0593ad9
AM		 3639
3640 /* For the absolute forms of branches, convert the PC
3641 relative form back into the absolute. */
3642 if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
3643 {
3644 switch (reloc)
3645 {
3646 case BFD_RELOC_PPC_B26:
3647 reloc = BFD_RELOC_PPC_BA26;
3648 break;
3649 case BFD_RELOC_PPC_B16:
3650 reloc = BFD_RELOC_PPC_BA16;
3651 break;
3652#ifdef OBJ_ELF
3653 case BFD_RELOC_PPC_B16_BRTAKEN:
3654 reloc = BFD_RELOC_PPC_BA16_BRTAKEN;
3655 break;
3656 case BFD_RELOC_PPC_B16_BRNTAKEN:
3657 reloc = BFD_RELOC_PPC_BA16_BRNTAKEN;
3658 break;
3659#endif
3660 default:
3661 break;
3662 }
3663 }
3664
3665#ifdef OBJ_ELF
3666 switch (reloc)
3667 {
3668 case BFD_RELOC_PPC_TOC16:
3669 toc_reloc_types |= has_small_toc_reloc;
3670 break;
3671 case BFD_RELOC_PPC64_TOC16_LO:
3672 case BFD_RELOC_PPC64_TOC16_HI:
3673 case BFD_RELOC_PPC64_TOC16_HA:
3674 toc_reloc_types |= has_large_toc_reloc;
3675 break;
3676 default:
3677 break;
3678 }
3679
3680 if (ppc_obj64
3681 && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0)
3682 {
3683 switch (reloc)
3684 {
3685 case BFD_RELOC_16:
3686 reloc = BFD_RELOC_PPC64_ADDR16_DS;
3687 break;
5663e321 3688
a0593ad9
AM		 3689 case BFD_RELOC_LO16:
3690 reloc = BFD_RELOC_PPC64_ADDR16_LO_DS;
3691 break;
5663e321 3692
a0593ad9
AM		 3693 case BFD_RELOC_16_GOTOFF:
3694 reloc = BFD_RELOC_PPC64_GOT16_DS;
3695 break;
5663e321 3696
a0593ad9
AM		 3697 case BFD_RELOC_LO16_GOTOFF:
3698 reloc = BFD_RELOC_PPC64_GOT16_LO_DS;
3699 break;
5663e321 3700
a0593ad9
AM		 3701 case BFD_RELOC_LO16_PLTOFF:
3702 reloc = BFD_RELOC_PPC64_PLT16_LO_DS;
3703 break;
5663e321 3704
a0593ad9
AM		 3705 case BFD_RELOC_16_BASEREL:
3706 reloc = BFD_RELOC_PPC64_SECTOFF_DS;
3707 break;
5663e321 3708
a0593ad9
AM		 3709 case BFD_RELOC_LO16_BASEREL:
3710 reloc = BFD_RELOC_PPC64_SECTOFF_LO_DS;
3711 break;
5663e321 3712
a0593ad9
AM		 3713 case BFD_RELOC_PPC_TOC16:
3714 reloc = BFD_RELOC_PPC64_TOC16_DS;
3715 break;
5663e321 3716
a0593ad9
AM		 3717 case BFD_RELOC_PPC64_TOC16_LO:
3718 reloc = BFD_RELOC_PPC64_TOC16_LO_DS;
3719 break;
5663e321 3720
a0593ad9
AM		 3721 case BFD_RELOC_PPC64_PLTGOT16:
3722 reloc = BFD_RELOC_PPC64_PLTGOT16_DS;
3723 break;
5663e321 3724
a0593ad9
AM		 3725 case BFD_RELOC_PPC64_PLTGOT16_LO:
3726 reloc = BFD_RELOC_PPC64_PLTGOT16_LO_DS;
3727 break;
5663e321 3728
a0593ad9
AM		 3729 case BFD_RELOC_PPC_DTPREL16:
3730 reloc = BFD_RELOC_PPC64_DTPREL16_DS;
3731 break;
5663e321 3732
a0593ad9
AM		 3733 case BFD_RELOC_PPC_DTPREL16_LO:
3734 reloc = BFD_RELOC_PPC64_DTPREL16_LO_DS;
3735 break;
5663e321 3736
a0593ad9
AM		 3737 case BFD_RELOC_PPC_TPREL16:
3738 reloc = BFD_RELOC_PPC64_TPREL16_DS;
3739 break;
5663e321 3740
a0593ad9
AM		 3741 case BFD_RELOC_PPC_TPREL16_LO:
3742 reloc = BFD_RELOC_PPC64_TPREL16_LO_DS;
3743 break;
5663e321 3744
a0593ad9
AM		 3745 case BFD_RELOC_PPC_GOT_DTPREL16:
3746 case BFD_RELOC_PPC_GOT_DTPREL16_LO:
3747 case BFD_RELOC_PPC_GOT_TPREL16:
3748 case BFD_RELOC_PPC_GOT_TPREL16_LO:
3749 break;
5663e321 3750
a0593ad9
AM		 3751 default:
3752 as_bad (_("unsupported relocation for DS offset field"));
3753 break;
3754 }
3755 }
160eba93
AM		 3756
3757 /* Look for a __tls_get_addr arg after any __tls_get_addr
3758 modifiers like @plt. This fixup must be emitted before
3759 the usual call fixup. */
3760 if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS
3761 && parse_tls_arg (&str, &ex, &fixups[fc]))
3762 {
3763 fixups[fc].opindex = *opindex_ptr;
3764 ++fc;
3765 }
a0593ad9 3766#endif
0baf16f2 3767
252b5132
RH		 3768 /* We need to generate a fixup for this expression. */
3769 if (fc >= MAX_INSN_FIXUPS)
3770 as_fatal (_("too many fixups"));
3771 fixups[fc].exp = ex;
727fc41e 3772 fixups[fc].opindex = *opindex_ptr;
252b5132
RH		 3773 fixups[fc].reloc = reloc;
3774 ++fc;
3775 }
252b5132
RH		 3776
3777 if (need_paren)
3778 {
3779 endc = ')';
3780 need_paren = 0;
c3d65c1c
BE		 3781 /* If expecting more operands, then we want to see "),". */
3782 if (*str == endc && opindex_ptr[1] != 0)
3783 {
3784 do
3785 ++str;
3786 while (ISSPACE (*str));
3787 endc = ',';
3788 }
252b5132
RH		 3789 }
3790 else if ((operand->flags & PPC_OPERAND_PARENS) != 0)
9cf7e568 3791 endc = '(';
252b5132
RH		 3792 else
3793 endc = ',';
3794
3795 /* The call to expression should have advanced str past any
3796 whitespace. */
9cf7e568 3797 if (*str == endc)
252b5132 3798 {
9cf7e568
AM		 3799 ++str;
3800 if (endc == '(')
3801 need_paren = 1;
3802 }
3803 else if (*str != '\0')
3804 {
3805 as_bad (_("syntax error; found `%c', expected `%c'"), *str, endc);
3806 break;
3807 }
3808 else if (endc == ')')
3809 {
3810 as_bad (_("syntax error; end of line, expected `%c'"), endc);
252b5132
RH		 3811 break;
3812 }
252b5132
RH		 3813 }
3814
3882b010 3815 while (ISSPACE (*str))
252b5132
RH		 3816 ++str;
3817
3818 if (*str != '\0')
3819 as_bad (_("junk at end of line: `%s'"), str);
3820
dc1d03fc 3821#ifdef OBJ_ELF
b9c361e0 3822 /* Do we need/want an APUinfo section? */
4faf939a
JM		 3823 if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_VLE)) != 0
3824 && !ppc_obj64)
6a0c61b7
EZ		 3825 {
3826 /* These are all version "1". */
3827 if (opcode->flags & PPC_OPCODE_SPE)
b34976b6 3828 ppc_apuinfo_section_add (PPC_APUINFO_SPE, 1);
6a0c61b7 3829 if (opcode->flags & PPC_OPCODE_ISEL)
b34976b6 3830 ppc_apuinfo_section_add (PPC_APUINFO_ISEL, 1);
6a0c61b7 3831 if (opcode->flags & PPC_OPCODE_EFS)
b34976b6 3832 ppc_apuinfo_section_add (PPC_APUINFO_EFS, 1);
6a0c61b7 3833 if (opcode->flags & PPC_OPCODE_BRLOCK)
b34976b6 3834 ppc_apuinfo_section_add (PPC_APUINFO_BRLOCK, 1);
6a0c61b7 3835 if (opcode->flags & PPC_OPCODE_PMR)
b34976b6 3836 ppc_apuinfo_section_add (PPC_APUINFO_PMR, 1);
6a0c61b7 3837 if (opcode->flags & PPC_OPCODE_CACHELCK)
b34976b6 3838 ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK, 1);
6a0c61b7 3839 if (opcode->flags & PPC_OPCODE_RFMCI)
b34976b6 3840 ppc_apuinfo_section_add (PPC_APUINFO_RFMCI, 1);
fbd94057
MR		 3841 /* Only set the VLE flag if the instruction has been pulled via
3842 the VLE instruction set. This way the flag is guaranteed to
3843 be set for VLE-only instructions or for VLE-only processors,
3844 however it'll remain clear for dual-mode instructions on
3845 dual-mode and, more importantly, standard-mode processors. */
3846 if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE)
f7d69005
AM		 3847 {
3848 ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1);
3849 if (elf_section_data (now_seg) != NULL)
3850 elf_section_data (now_seg)->this_hdr.sh_flags |= SHF_PPC_VLE;
3851 }
6a0c61b7 3852 }
dc1d03fc 3853#endif
6a0c61b7 3854
252b5132 3855 /* Write out the instruction. */
a9479dc0
AM		 3856
3857 addr_mask = 3;
f7d69005 3858 if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
a9479dc0
AM		 3859 /* All instructions can start on a 2 byte boundary for VLE. */
3860 addr_mask = 1;
3861
3862 if (frag_now->insn_addr != addr_mask)
b9c361e0 3863 {
a9479dc0
AM		 3864 /* Don't emit instructions to a frag started for data, or for a
3865 CPU differing in VLE mode. Data is allowed to be misaligned,
3866 and it's possible to start a new frag in the middle of
3867 misaligned data. */
3868 frag_wane (frag_now);
3869 frag_new (0);
b9c361e0 3870 }
a9479dc0
AM		 3871
3872 /* Check that insns within the frag are aligned. ppc_frag_check
3873 will ensure that the frag start address is aligned. */
3874 if ((frag_now_fix () & addr_mask) != 0)
3875 as_bad (_("instruction address is not a multiple of %d"), addr_mask + 1);
3876
dd7efa79 3877 /* Differentiate between two, four, and eight byte insns. */
a9479dc0
AM		 3878 insn_length = 4;
3879 if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn))
3880 insn_length = 2;
7c1f4227 3881 else if ((opcode->flags & PPC_OPCODE_POWER10) != 0
dd7efa79
PB		 3882 && PPC_PREFIX_P (insn))
3883 {
3884 struct insn_label_list *l;
3885
3886 insn_length = 8;
3887
3888 /* 8-byte prefix instructions are not allowed to cross 64-byte
3889 boundaries. */
3890 frag_align_code (6, 4);
3891 record_alignment (now_seg, 6);
3892
3893 /* Update "dot" in any expressions used by this instruction, and
3894 a label attached to the instruction. By "attached" we mean
3895 on the same source line as the instruction and without any
3896 intervening semicolons. */
3897 dot_value = frag_now_fix ();
3898 dot_frag = frag_now;
3899 for (l = insn_labels; l != NULL; l = l->next)
3900 {
3901 symbol_set_frag (l->label, dot_frag);
3902 S_SET_VALUE (l->label, dot_value);
3903 }
3904 }
3905
3906 ppc_clear_labels ();
a9479dc0 3907
b9c361e0 3908 f = frag_more (insn_length);
a9479dc0 3909 frag_now->insn_addr = addr_mask;
dd7efa79
PB		 3910
3911 /* The prefix part of an 8-byte instruction always occupies the lower
3912 addressed word in a doubleword, regardless of endianness. */
3913 if (!target_big_endian && insn_length == 8)
3914 {
3915 md_number_to_chars (f, PPC_GET_PREFIX (insn), 4);
3916 md_number_to_chars (f + 4, PPC_GET_SUFFIX (insn), 4);
3917 }
3918 else
3919 md_number_to_chars (f, insn, insn_length);
3920
bf7279d5
AM		 3921 last_insn = insn;
3922 last_seg = now_seg;
3923 last_subseg = now_subseg;
252b5132 3924
5d6f4f16 3925#ifdef OBJ_ELF
b9c361e0 3926 dwarf2_emit_insn (insn_length);
5d6f4f16
GK		 3927#endif
3928
3b8b57a9 3929 /* Create any fixups. */
252b5132
RH		 3930 for (i = 0; i < fc; i++)
3931 {
3b8b57a9 3932 fixS *fixP;
62ebcb5c 3933 if (fixups[i].reloc != BFD_RELOC_NONE)
252b5132 3934 {
0e2779e9
AM		 3935 bfd_boolean pcrel;
3936 unsigned int size = fixup_size (fixups[i].reloc, &pcrel);
3937 int offset = target_big_endian ? (insn_length - size) : 0;
252b5132 3938
99a814a1
AM		 3939 fixP = fix_new_exp (frag_now,
3940 f - frag_now->fr_literal + offset,
3941 size,
3942 &fixups[i].exp,
0e2779e9 3943 pcrel,
252b5132 3944 fixups[i].reloc);
252b5132
RH		 3945 }
3946 else
727fc41e
AM		 3947 {
3948 const struct powerpc_operand *operand;
3949
3950 operand = &powerpc_operands[fixups[i].opindex];
3b8b57a9
AM		 3951 fixP = fix_new_exp (frag_now,
3952 f - frag_now->fr_literal,
3953 insn_length,
3954 &fixups[i].exp,
3955 (operand->flags & PPC_OPERAND_RELATIVE) != 0,
62ebcb5c 3956 BFD_RELOC_NONE);
727fc41e 3957 }
3b8b57a9 3958 fixP->fx_pcrel_adjust = fixups[i].opindex;
252b5132
RH		 3959 }
3960}
3961
3962/* Handle a macro. Gather all the operands, transform them as
3963 described by the macro, and call md_assemble recursively. All the
3964 operands are separated by commas; we don't accept parentheses
3965 around operands here. */
3966
3967static void
98027b10 3968ppc_macro (char *str, const struct powerpc_macro *macro)
252b5132
RH		 3969{
3970 char *operands[10];
3971 unsigned int count;
3972 char *s;
3973 unsigned int len;
3974 const char *format;
db557034 3975 unsigned int arg;
252b5132
RH		 3976 char *send;
3977 char *complete;
3978
3979 /* Gather the users operands into the operands array. */
3980 count = 0;
3981 s = str;
3982 while (1)
3983 {
3984 if (count >= sizeof operands / sizeof operands[0])
3985 break;
3986 operands[count++] = s;
3987 s = strchr (s, ',');
3988 if (s == (char *) NULL)
3989 break;
3990 *s++ = '\0';
81d4177b 3991 }
252b5132
RH		 3992
3993 if (count != macro->operands)
3994 {
3995 as_bad (_("wrong number of operands"));
3996 return;
3997 }
3998
3999 /* Work out how large the string must be (the size is unbounded
4000 because it includes user input). */
4001 len = 0;
4002 format = macro->format;
4003 while (*format != '\0')
4004 {
4005 if (*format != '%')
4006 {
4007 ++len;
4008 ++format;
4009 }
4010 else
4011 {
4012 arg = strtol (format + 1, &send, 10);
db557034 4013 know (send != format && arg < count);
252b5132
RH		 4014 len += strlen (operands[arg]);
4015 format = send;
4016 }
4017 }
4018
4019 /* Put the string together. */
325801bd 4020 complete = s = XNEWVEC (char, len + 1);
252b5132
RH		 4021 format = macro->format;
4022 while (*format != '\0')
4023 {
4024 if (*format != '%')
4025 *s++ = *format++;
4026 else
4027 {
4028 arg = strtol (format + 1, &send, 10);
4029 strcpy (s, operands[arg]);
4030 s += strlen (s);
4031 format = send;
4032 }
4033 }
4034 *s = '\0';
4035
4036 /* Assemble the constructed instruction. */
4037 md_assemble (complete);
e1fa0163 4038 free (complete);
81d4177b 4039}
252b5132
RH		 4040\f
4041#ifdef OBJ_ELF
18ae9cc1 4042/* For ELF, add support for SHT_ORDERED. */
252b5132
RH		 4043
4044int
98027b10 4045ppc_section_type (char *str, size_t len)
252b5132 4046{
9de8d8f1
RH		 4047 if (len == 7 && strncmp (str, "ordered", 7) == 0)
4048 return SHT_ORDERED;
252b5132 4049
9de8d8f1 4050 return -1;
252b5132
RH		 4051}
4052
4053int
1239de13 4054ppc_section_flags (flagword flags, bfd_vma attr ATTRIBUTE_UNUSED, int type)
252b5132
RH		 4055{
4056 if (type == SHT_ORDERED)
4057 flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES;
4058
252b5132
RH		 4059 return flags;
4060}
83eef883
AFB		 4061
4062bfd_vma
4063ppc_elf_section_letter (int letter, const char **ptrmsg)
4064{
4065 if (letter == 'v')
4066 return SHF_PPC_VLE;
4067
4068 *ptrmsg = _("bad .section directive: want a,e,v,w,x,M,S,G,T in string");
4069 return -1;
4070}
252b5132
RH		 4071#endif /* OBJ_ELF */
4072
4073\f
4074/* Pseudo-op handling. */
4075
4076/* The .byte pseudo-op. This is similar to the normal .byte
4077 pseudo-op, but it can also take a single ASCII string. */
4078
4079static void
98027b10 4080ppc_byte (int ignore ATTRIBUTE_UNUSED)
252b5132 4081{
bf7279d5
AM		 4082 int count = 0;
4083
252b5132
RH		 4084 if (*input_line_pointer != '\"')
4085 {
4086 cons (1);
4087 return;
4088 }
4089
4090 /* Gather characters. A real double quote is doubled. Unusual
4091 characters are not permitted. */
4092 ++input_line_pointer;
4093 while (1)
4094 {
4095 char c;
4096
4097 c = *input_line_pointer++;
4098
4099 if (c == '\"')
4100 {
4101 if (*input_line_pointer != '\"')
4102 break;
4103 ++input_line_pointer;
4104 }
4105
4106 FRAG_APPEND_1_CHAR (c);
bf7279d5 4107 ++count;
252b5132
RH		 4108 }
4109
bf7279d5
AM		 4110 if (warn_476 && count != 0 && (now_seg->flags & SEC_CODE) != 0)
4111 as_warn (_("data in executable section"));
252b5132
RH		 4112 demand_empty_rest_of_line ();
4113}
4114\f
4115#ifdef OBJ_XCOFF
4116
4117/* XCOFF specific pseudo-op handling. */
4118
4119/* This is set if we are creating a .stabx symbol, since we don't want
4120 to handle symbol suffixes for such symbols. */
b34976b6 4121static bfd_boolean ppc_stab_symbol;
252b5132
RH		 4122
4123/* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common
4124 symbols in the .bss segment as though they were local common
67c1ffbe 4125 symbols, and uses a different smclas. The native Aix 4.3.3 assembler
1ad63b2f 4126 aligns .comm and .lcomm to 4 bytes. */
252b5132
RH		 4127
4128static void
98027b10 4129ppc_comm (int lcomm)
252b5132
RH		 4130{
4131 asection *current_seg = now_seg;
4132 subsegT current_subseg = now_subseg;
4133 char *name;
4134 char endc;
4135 char *end_name;
4136 offsetT size;
4137 offsetT align;
4138 symbolS *lcomm_sym = NULL;
4139 symbolS *sym;
4140 char *pfrag;
4141
d02603dc 4142 endc = get_symbol_name (&name);
252b5132 4143 end_name = input_line_pointer;
d02603dc 4144 (void) restore_line_pointer (endc);
252b5132
RH		 4145
4146 if (*input_line_pointer != ',')
4147 {
4148 as_bad (_("missing size"));
4149 ignore_rest_of_line ();
4150 return;
4151 }
4152 ++input_line_pointer;
4153
4154 size = get_absolute_expression ();
4155 if (size < 0)
4156 {
4157 as_bad (_("negative size"));
4158 ignore_rest_of_line ();
4159 return;
4160 }
4161
4162 if (! lcomm)
4163 {
4164 /* The third argument to .comm is the alignment. */
4165 if (*input_line_pointer != ',')
1ad63b2f 4166 align = 2;
252b5132
RH		 4167 else
4168 {
4169 ++input_line_pointer;
4170 align = get_absolute_expression ();
4171 if (align <= 0)
4172 {
4173 as_warn (_("ignoring bad alignment"));
1ad63b2f 4174 align = 2;
252b5132
RH		 4175 }
4176 }
4177 }
4178 else
4179 {
4180 char *lcomm_name;
4181 char lcomm_endc;
4182
252b5132
RH		 4183 /* The third argument to .lcomm appears to be the real local
4184 common symbol to create. References to the symbol named in
4185 the first argument are turned into references to the third
4186 argument. */
4187 if (*input_line_pointer != ',')
4188 {
4189 as_bad (_("missing real symbol name"));
4190 ignore_rest_of_line ();
4191 return;
4192 }
4193 ++input_line_pointer;
4194
d02603dc 4195 lcomm_endc = get_symbol_name (&lcomm_name);
81d4177b 4196
252b5132
RH		 4197 lcomm_sym = symbol_find_or_make (lcomm_name);
4198
d02603dc 4199 (void) restore_line_pointer (lcomm_endc);
3c02c47f
DE		 4200
4201 /* The fourth argument to .lcomm is the alignment. */
4202 if (*input_line_pointer != ',')
4203 {
4204 if (size <= 4)
4205 align = 2;
4206 else
4207 align = 3;
4208 }
4209 else
4210 {
4211 ++input_line_pointer;
4212 align = get_absolute_expression ();
4213 if (align <= 0)
4214 {
4215 as_warn (_("ignoring bad alignment"));
4216 align = 2;
4217 }
4218 }
252b5132
RH		 4219 }
4220
4221 *end_name = '\0';
4222 sym = symbol_find_or_make (name);
4223 *end_name = endc;
4224
4225 if (S_IS_DEFINED (sym)
4226 || S_GET_VALUE (sym) != 0)
4227 {
4228 as_bad (_("attempt to redefine symbol"));
4229 ignore_rest_of_line ();
4230 return;
4231 }
81d4177b 4232
252b5132 4233 record_alignment (bss_section, align);
81d4177b 4234
252b5132
RH		 4235 if (! lcomm
4236 || ! S_IS_DEFINED (lcomm_sym))
4237 {
4238 symbolS *def_sym;
4239 offsetT def_size;
4240
4241 if (! lcomm)
4242 {
4243 def_sym = sym;
4244 def_size = size;
4245 S_SET_EXTERNAL (sym);
4246 }
4247 else
4248 {
809ffe0d 4249 symbol_get_tc (lcomm_sym)->output = 1;
252b5132
RH		 4250 def_sym = lcomm_sym;
4251 def_size = 0;
4252 }
4253
4254 subseg_set (bss_section, 1);
4255 frag_align (align, 0, 0);
81d4177b 4256
809ffe0d 4257 symbol_set_frag (def_sym, frag_now);
252b5132
RH		 4258 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, def_sym,
4259 def_size, (char *) NULL);
4260 *pfrag = 0;
4261 S_SET_SEGMENT (def_sym, bss_section);
809ffe0d 4262 symbol_get_tc (def_sym)->align = align;
252b5132
RH		 4263 }
4264 else if (lcomm)
4265 {
4266 /* Align the size of lcomm_sym. */
809ffe0d
ILT		 4267 symbol_get_frag (lcomm_sym)->fr_offset =
4268 ((symbol_get_frag (lcomm_sym)->fr_offset + (1 << align) - 1)
252b5132 4269 &~ ((1 << align) - 1));
809ffe0d
ILT		 4270 if (align > symbol_get_tc (lcomm_sym)->align)
4271 symbol_get_tc (lcomm_sym)->align = align;
252b5132
RH		 4272 }
4273
4274 if (lcomm)
4275 {
4276 /* Make sym an offset from lcomm_sym. */
4277 S_SET_SEGMENT (sym, bss_section);
809ffe0d
ILT		 4278 symbol_set_frag (sym, symbol_get_frag (lcomm_sym));
4279 S_SET_VALUE (sym, symbol_get_frag (lcomm_sym)->fr_offset);
4280 symbol_get_frag (lcomm_sym)->fr_offset += size;
252b5132
RH		 4281 }
4282
4283 subseg_set (current_seg, current_subseg);
4284
4285 demand_empty_rest_of_line ();
4286}
4287
4288/* The .csect pseudo-op. This switches us into a different
4289 subsegment. The first argument is a symbol whose value is the
4290 start of the .csect. In COFF, csect symbols get special aux
4291 entries defined by the x_csect field of union internal_auxent. The
4292 optional second argument is the alignment (the default is 2). */
4293
4294static void
98027b10 4295ppc_csect (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 4296{
4297 char *name;
4298 char endc;
4299 symbolS *sym;
931e13a6 4300 offsetT align;
252b5132 4301
d02603dc 4302 endc = get_symbol_name (&name);
81d4177b 4303
252b5132
RH		 4304 sym = symbol_find_or_make (name);
4305
d02603dc 4306 (void) restore_line_pointer (endc);
252b5132
RH		 4307
4308 if (S_GET_NAME (sym)[0] == '\0')
4309 {
4310 /* An unnamed csect is assumed to be [PR]. */
96d56e9f 4311 symbol_get_tc (sym)->symbol_class = XMC_PR;
252b5132
RH		 4312 }
4313
931e13a6 4314 align = 2;
252b5132
RH		 4315 if (*input_line_pointer == ',')
4316 {
4317 ++input_line_pointer;
931e13a6 4318 align = get_absolute_expression ();
252b5132
RH		 4319 }
4320
931e13a6
AM		 4321 ppc_change_csect (sym, align);
4322
252b5132
RH		 4323 demand_empty_rest_of_line ();
4324}
4325
4326/* Change to a different csect. */
4327
4328static void
98027b10 4329ppc_change_csect (symbolS *sym, offsetT align)
252b5132
RH		 4330{
4331 if (S_IS_DEFINED (sym))
809ffe0d 4332 subseg_set (S_GET_SEGMENT (sym), symbol_get_tc (sym)->subseg);
252b5132
RH		 4333 else
4334 {
4335 symbolS **list_ptr;
4336 int after_toc;
4337 int hold_chunksize;
4338 symbolS *list;
931e13a6
AM		 4339 int is_code;
4340 segT sec;
252b5132
RH		 4341
4342 /* This is a new csect. We need to look at the symbol class to
4343 figure out whether it should go in the text section or the
4344 data section. */
4345 after_toc = 0;
931e13a6 4346 is_code = 0;
96d56e9f 4347 switch (symbol_get_tc (sym)->symbol_class)
252b5132
RH		 4348 {
4349 case XMC_PR:
4350 case XMC_RO:
4351 case XMC_DB:
4352 case XMC_GL:
4353 case XMC_XO:
4354 case XMC_SV:
4355 case XMC_TI:
4356 case XMC_TB:
4357 S_SET_SEGMENT (sym, text_section);
809ffe0d 4358 symbol_get_tc (sym)->subseg = ppc_text_subsegment;
252b5132
RH		 4359 ++ppc_text_subsegment;
4360 list_ptr = &ppc_text_csects;
931e13a6 4361 is_code = 1;
252b5132
RH		 4362 break;
4363 case XMC_RW:
4364 case XMC_TC0:
4365 case XMC_TC:
4366 case XMC_DS:
4367 case XMC_UA:
4368 case XMC_BS:
4369 case XMC_UC:
4370 if (ppc_toc_csect != NULL
809ffe0d
ILT		 4371 && (symbol_get_tc (ppc_toc_csect)->subseg + 1
4372 == ppc_data_subsegment))
252b5132
RH		 4373 after_toc = 1;
4374 S_SET_SEGMENT (sym, data_section);
809ffe0d 4375 symbol_get_tc (sym)->subseg = ppc_data_subsegment;
252b5132
RH		 4376 ++ppc_data_subsegment;
4377 list_ptr = &ppc_data_csects;
4378 break;
4379 default:
4380 abort ();
4381 }
4382
4383 /* We set the obstack chunk size to a small value before
99a814a1
AM		 4384 changing subsegments, so that we don't use a lot of memory
4385 space for what may be a small section. */
252b5132
RH		 4386 hold_chunksize = chunksize;
4387 chunksize = 64;
4388
931e13a6
AM		 4389 sec = subseg_new (segment_name (S_GET_SEGMENT (sym)),
4390 symbol_get_tc (sym)->subseg);
252b5132
RH		 4391
4392 chunksize = hold_chunksize;
4393
4394 if (after_toc)
4395 ppc_after_toc_frag = frag_now;
4396
931e13a6
AM		 4397 record_alignment (sec, align);
4398 if (is_code)
4399 frag_align_code (align, 0);
4400 else
4401 frag_align (align, 0, 0);
4402
809ffe0d 4403 symbol_set_frag (sym, frag_now);
252b5132
RH		 4404 S_SET_VALUE (sym, (valueT) frag_now_fix ());
4405
931e13a6 4406 symbol_get_tc (sym)->align = align;
809ffe0d
ILT		 4407 symbol_get_tc (sym)->output = 1;
4408 symbol_get_tc (sym)->within = sym;
81d4177b 4409
252b5132 4410 for (list = *list_ptr;
809ffe0d
ILT		 4411 symbol_get_tc (list)->next != (symbolS *) NULL;
4412 list = symbol_get_tc (list)->next)
252b5132 4413 ;
809ffe0d 4414 symbol_get_tc (list)->next = sym;
81d4177b 4415
252b5132 4416 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
809ffe0d
ILT		 4417 symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP,
4418 &symbol_lastP);
252b5132
RH		 4419 }
4420
4421 ppc_current_csect = sym;
4422}
4423
85645aed
TG		 4424static void
4425ppc_change_debug_section (unsigned int idx, subsegT subseg)
4426{
4427 segT sec;
4428 flagword oldflags;
4429 const struct xcoff_dwsect_name *dw = &xcoff_dwsect_names[idx];
4430
4431 sec = subseg_new (dw->name, subseg);
fd361982 4432 oldflags = bfd_section_flags (sec);
85645aed
TG		 4433 if (oldflags == SEC_NO_FLAGS)
4434 {
4435 /* Just created section. */
4436 gas_assert (dw_sections[idx].sect == NULL);
4437
fd361982
AM		 4438 bfd_set_section_flags (sec, SEC_DEBUGGING);
4439 bfd_set_section_alignment (sec, 0);
85645aed
TG		 4440 dw_sections[idx].sect = sec;
4441 }
4442
4443 /* Not anymore in a csect. */
4444 ppc_current_csect = NULL;
4445}
4446
4447/* The .dwsect pseudo-op. Defines a DWARF section. Syntax is:
4448 .dwsect flag [, opt-label ]
4449*/
4450
4451static void
4452ppc_dwsect (int ignore ATTRIBUTE_UNUSED)
4453{
16de26a6 4454 valueT flag;
85645aed
TG		 4455 symbolS *opt_label;
4456 const struct xcoff_dwsect_name *dw;
4457 struct dw_subsection *subseg;
4458 struct dw_section *dws;
4459 int i;
4460
4461 /* Find section. */
4462 flag = get_absolute_expression ();
4463 dw = NULL;
4464 for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++)
4465 if (xcoff_dwsect_names[i].flag == flag)
4466 {
4467 dw = &xcoff_dwsect_names[i];
4468 break;
4469 }
4470
4471 /* Parse opt-label. */
4472 if (*input_line_pointer == ',')
4473 {
d02603dc 4474 char *label;
85645aed
TG		 4475 char c;
4476
4477 ++input_line_pointer;
4478
d02603dc 4479 c = get_symbol_name (&label);
85645aed 4480 opt_label = symbol_find_or_make (label);
d02603dc 4481 (void) restore_line_pointer (c);
85645aed
TG		 4482 }
4483 else
4484 opt_label = NULL;
4485
4486 demand_empty_rest_of_line ();
4487
4488 /* Return now in case of unknown subsection. */
4489 if (dw == NULL)
4490 {
d6ed37ed 4491 as_bad (_("no known dwarf XCOFF section for flag 0x%08x\n"),
85645aed
TG		 4492 (unsigned)flag);
4493 return;
4494 }
4495
4496 /* Find the subsection. */
4497 dws = &dw_sections[i];
4498 subseg = NULL;
4499 if (opt_label != NULL && S_IS_DEFINED (opt_label))
4500 {
4501 /* Sanity check (note that in theory S_GET_SEGMENT mustn't be null). */
4502 if (dws->sect == NULL || S_GET_SEGMENT (opt_label) != dws->sect)
4503 {
4504 as_bad (_("label %s was not defined in this dwarf section"),
4505 S_GET_NAME (opt_label));
4506 subseg = dws->anon_subseg;
4507 opt_label = NULL;
4508 }
4509 else
4510 subseg = symbol_get_tc (opt_label)->u.dw;
4511 }
4512
4513 if (subseg != NULL)
4514 {
4515 /* Switch to the subsection. */
4516 ppc_change_debug_section (i, subseg->subseg);
4517 }
4518 else
4519 {
4520 /* Create a new dw subsection. */
325801bd 4521 subseg = XNEW (struct dw_subsection);
85645aed
TG		 4522
4523 if (opt_label == NULL)
4524 {
4525 /* The anonymous one. */
4526 subseg->subseg = 0;
4527 subseg->link = NULL;
4528 dws->anon_subseg = subseg;
4529 }
4530 else
4531 {
4532 /* A named one. */
4533 if (dws->list_subseg != NULL)
4534 subseg->subseg = dws->list_subseg->subseg + 1;
4535 else
4536 subseg->subseg = 1;
4537
4538 subseg->link = dws->list_subseg;
4539 dws->list_subseg = subseg;
4540 symbol_get_tc (opt_label)->u.dw = subseg;
4541 }
4542
4543 ppc_change_debug_section (i, subseg->subseg);
4544
4545 if (dw->def_size)
4546 {
4547 /* Add the length field. */
4548 expressionS *exp = &subseg->end_exp;
4549 int sz;
4550
4551 if (opt_label != NULL)
4552 symbol_set_value_now (opt_label);
4553
4554 /* Add the length field. Note that according to the AIX assembler
4555 manual, the size of the length field is 4 for powerpc32 but
4556 12 for powerpc64. */
4557 if (ppc_obj64)
4558 {
4559 /* Write the 64bit marker. */
4560 md_number_to_chars (frag_more (4), -1, 4);
4561 }
4562
4563 exp->X_op = O_subtract;
4564 exp->X_op_symbol = symbol_temp_new_now ();
4565 exp->X_add_symbol = symbol_temp_make ();
4566
4567 sz = ppc_obj64 ? 8 : 4;
4568 exp->X_add_number = -sz;
4569 emit_expr (exp, sz);
4570 }
4571 }
4572}
4573
252b5132
RH		 4574/* This function handles the .text and .data pseudo-ops. These
4575 pseudo-ops aren't really used by XCOFF; we implement them for the
4576 convenience of people who aren't used to XCOFF. */
4577
4578static void
98027b10 4579ppc_section (int type)
252b5132
RH		 4580{
4581 const char *name;
4582 symbolS *sym;
4583
4584 if (type == 't')
4585 name = ".text[PR]";
4586 else if (type == 'd')
4587 name = ".data[RW]";
4588 else
4589 abort ();
4590
4591 sym = symbol_find_or_make (name);
4592
931e13a6 4593 ppc_change_csect (sym, 2);
252b5132
RH		 4594
4595 demand_empty_rest_of_line ();
4596}
4597
4598/* This function handles the .section pseudo-op. This is mostly to
4599 give an error, since XCOFF only supports .text, .data and .bss, but
4600 we do permit the user to name the text or data section. */
4601
4602static void
98027b10 4603ppc_named_section (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 4604{
4605 char *user_name;
4606 const char *real_name;
4607 char c;
4608 symbolS *sym;
4609
d02603dc 4610 c = get_symbol_name (&user_name);
252b5132
RH		 4611
4612 if (strcmp (user_name, ".text") == 0)
4613 real_name = ".text[PR]";
4614 else if (strcmp (user_name, ".data") == 0)
4615 real_name = ".data[RW]";
4616 else
4617 {
d6ed37ed 4618 as_bad (_("the XCOFF file format does not support arbitrary sections"));
d02603dc 4619 (void) restore_line_pointer (c);
252b5132
RH		 4620 ignore_rest_of_line ();
4621 return;
4622 }
4623
d02603dc 4624 (void) restore_line_pointer (c);
252b5132
RH		 4625
4626 sym = symbol_find_or_make (real_name);
4627
931e13a6 4628 ppc_change_csect (sym, 2);
252b5132
RH		 4629
4630 demand_empty_rest_of_line ();
4631}
4632
4633/* The .extern pseudo-op. We create an undefined symbol. */
4634
4635static void
98027b10 4636ppc_extern (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 4637{
4638 char *name;
4639 char endc;
4640
d02603dc 4641 endc = get_symbol_name (&name);
252b5132
RH		 4642
4643 (void) symbol_find_or_make (name);
4644
d02603dc 4645 (void) restore_line_pointer (endc);
252b5132
RH		 4646
4647 demand_empty_rest_of_line ();
4648}
4649
4650/* The .lglobl pseudo-op. Keep the symbol in the symbol table. */
4651
4652static void
98027b10 4653ppc_lglobl (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 4654{
4655 char *name;
4656 char endc;
4657 symbolS *sym;
4658
d02603dc 4659 endc = get_symbol_name (&name);
252b5132
RH		 4660
4661 sym = symbol_find_or_make (name);
4662
d02603dc 4663 (void) restore_line_pointer (endc);
252b5132 4664
809ffe0d 4665 symbol_get_tc (sym)->output = 1;
252b5132
RH		 4666
4667 demand_empty_rest_of_line ();
4668}
4669
c865e45b
RS		 4670/* The .ref pseudo-op. It takes a list of symbol names and inserts R_REF
4671 relocations at the beginning of the current csect.
4672
4673 (In principle, there's no reason why the relocations _have_ to be at
4674 the beginning. Anywhere in the csect would do. However, inserting
33eaf5de 4675 at the beginning is what the native assembler does, and it helps to
c865e45b
RS		 4676 deal with cases where the .ref statements follow the section contents.)
4677
4678 ??? .refs don't work for empty .csects. However, the native assembler
4679 doesn't report an error in this case, and neither yet do we. */
4680
4681static void
4682ppc_ref (int ignore ATTRIBUTE_UNUSED)
4683{
4684 char *name;
4685 char c;
4686
4687 if (ppc_current_csect == NULL)
4688 {
4689 as_bad (_(".ref outside .csect"));
4690 ignore_rest_of_line ();
4691 return;
4692 }
4693
4694 do
4695 {
d02603dc 4696 c = get_symbol_name (&name);
c865e45b
RS		 4697
4698 fix_at_start (symbol_get_frag (ppc_current_csect), 0,
4699 symbol_find_or_make (name), 0, FALSE, BFD_RELOC_NONE);
4700
4701 *input_line_pointer = c;
d02603dc 4702 SKIP_WHITESPACE_AFTER_NAME ();
c865e45b
RS		 4703 c = *input_line_pointer;
4704 if (c == ',')
4705 {
4706 input_line_pointer++;
4707 SKIP_WHITESPACE ();
4708 if (is_end_of_line[(unsigned char) *input_line_pointer])
4709 {
4710 as_bad (_("missing symbol name"));
4711 ignore_rest_of_line ();
4712 return;
4713 }
4714 }
4715 }
4716 while (c == ',');
4717
4718 demand_empty_rest_of_line ();
4719}
4720
252b5132
RH		 4721/* The .rename pseudo-op. The RS/6000 assembler can rename symbols,
4722 although I don't know why it bothers. */
4723
4724static void
98027b10 4725ppc_rename (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 4726{
4727 char *name;
4728 char endc;
4729 symbolS *sym;
4730 int len;
4731
d02603dc 4732 endc = get_symbol_name (&name);
252b5132
RH		 4733
4734 sym = symbol_find_or_make (name);
4735
d02603dc 4736 (void) restore_line_pointer (endc);
252b5132
RH		 4737
4738 if (*input_line_pointer != ',')
4739 {
4740 as_bad (_("missing rename string"));
4741 ignore_rest_of_line ();
4742 return;
4743 }
4744 ++input_line_pointer;
4745
809ffe0d 4746 symbol_get_tc (sym)->real_name = demand_copy_C_string (&len);
252b5132
RH		 4747
4748 demand_empty_rest_of_line ();
4749}
4750
4751/* The .stabx pseudo-op. This is similar to a normal .stabs
4752 pseudo-op, but slightly different. A sample is
4753 .stabx "main:F-1",.main,142,0
4754 The first argument is the symbol name to create. The second is the
4755 value, and the third is the storage class. The fourth seems to be
4756 always zero, and I am assuming it is the type. */
4757
4758static void
98027b10 4759ppc_stabx (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 4760{
4761 char *name;
4762 int len;
4763 symbolS *sym;
4764 expressionS exp;
4765
4766 name = demand_copy_C_string (&len);
4767
4768 if (*input_line_pointer != ',')
4769 {
4770 as_bad (_("missing value"));
4771 return;
4772 }
4773 ++input_line_pointer;
4774
b34976b6 4775 ppc_stab_symbol = TRUE;
252b5132 4776 sym = symbol_make (name);
b34976b6 4777 ppc_stab_symbol = FALSE;
252b5132 4778
809ffe0d 4779 symbol_get_tc (sym)->real_name = name;
252b5132
RH		 4780
4781 (void) expression (&exp);
4782
4783 switch (exp.X_op)
4784 {
4785 case O_illegal:
4786 case O_absent:
4787 case O_big:
4788 as_bad (_("illegal .stabx expression; zero assumed"));
4789 exp.X_add_number = 0;
4790 /* Fall through. */
4791 case O_constant:
4792 S_SET_VALUE (sym, (valueT) exp.X_add_number);
809ffe0d 4793 symbol_set_frag (sym, &zero_address_frag);
252b5132
RH		 4794 break;
4795
4796 case O_symbol:
4797 if (S_GET_SEGMENT (exp.X_add_symbol) == undefined_section)
809ffe0d 4798 symbol_set_value_expression (sym, &exp);
252b5132
RH		 4799 else
4800 {
4801 S_SET_VALUE (sym,
4802 exp.X_add_number + S_GET_VALUE (exp.X_add_symbol));
809ffe0d 4803 symbol_set_frag (sym, symbol_get_frag (exp.X_add_symbol));
252b5132
RH		 4804 }
4805 break;
4806
4807 default:
4808 /* The value is some complex expression. This will probably
99a814a1
AM		 4809 fail at some later point, but this is probably the right
4810 thing to do here. */
809ffe0d 4811 symbol_set_value_expression (sym, &exp);
252b5132
RH		 4812 break;
4813 }
4814
4815 S_SET_SEGMENT (sym, ppc_coff_debug_section);
809ffe0d 4816 symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
252b5132
RH		 4817
4818 if (*input_line_pointer != ',')
4819 {
4820 as_bad (_("missing class"));
4821 return;
4822 }
4823 ++input_line_pointer;
4824
4825 S_SET_STORAGE_CLASS (sym, get_absolute_expression ());
4826
4827 if (*input_line_pointer != ',')
4828 {
4829 as_bad (_("missing type"));
4830 return;
4831 }
4832 ++input_line_pointer;
4833
4834 S_SET_DATA_TYPE (sym, get_absolute_expression ());
4835
809ffe0d 4836 symbol_get_tc (sym)->output = 1;
252b5132 4837
c734e7e3
TG		 4838 if (S_GET_STORAGE_CLASS (sym) == C_STSYM)
4839 {
4840 /* In this case :
252b5132 4841
c734e7e3
TG		 4842 .bs name
4843 .stabx "z",arrays_,133,0
4844 .es
99a814a1 4845
c734e7e3 4846 .comm arrays_,13768,3
99a814a1 4847
c734e7e3
TG		 4848 resolve_symbol_value will copy the exp's "within" into sym's when the
4849 offset is 0. Since this seems to be corner case problem,
4850 only do the correction for storage class C_STSYM. A better solution
4851 would be to have the tc field updated in ppc_symbol_new_hook. */
99a814a1 4852
c734e7e3
TG		 4853 if (exp.X_op == O_symbol)
4854 {
4855 if (ppc_current_block == NULL)
4856 as_bad (_(".stabx of storage class stsym must be within .bs/.es"));
99a814a1 4857
c734e7e3
TG		 4858 symbol_get_tc (sym)->within = ppc_current_block;
4859 symbol_get_tc (exp.X_add_symbol)->within = ppc_current_block;
4860 }
4861 }
99a814a1 4862
252b5132
RH		 4863 if (exp.X_op != O_symbol
4864 || ! S_IS_EXTERNAL (exp.X_add_symbol)
4865 || S_GET_SEGMENT (exp.X_add_symbol) != bss_section)
4866 ppc_frob_label (sym);
4867 else
4868 {
4869 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4870 symbol_append (sym, exp.X_add_symbol, &symbol_rootP, &symbol_lastP);
809ffe0d
ILT		 4871 if (symbol_get_tc (ppc_current_csect)->within == exp.X_add_symbol)
4872 symbol_get_tc (ppc_current_csect)->within = sym;
252b5132
RH		 4873 }
4874
4875 demand_empty_rest_of_line ();
4876}
4877
4878/* The .function pseudo-op. This takes several arguments. The first
4879 argument seems to be the external name of the symbol. The second
67c1ffbe 4880 argument seems to be the label for the start of the function. gcc
252b5132
RH		 4881 uses the same name for both. I have no idea what the third and
4882 fourth arguments are meant to be. The optional fifth argument is
4883 an expression for the size of the function. In COFF this symbol
4884 gets an aux entry like that used for a csect. */
4885
4886static void
98027b10 4887ppc_function (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 4888{
4889 char *name;
4890 char endc;
4891 char *s;
4892 symbolS *ext_sym;
4893 symbolS *lab_sym;
4894
d02603dc 4895 endc = get_symbol_name (&name);
252b5132
RH		 4896
4897 /* Ignore any [PR] suffix. */
4898 name = ppc_canonicalize_symbol_name (name);
4899 s = strchr (name, '[');
4900 if (s != (char *) NULL
4901 && strcmp (s + 1, "PR]") == 0)
4902 *s = '\0';
4903
4904 ext_sym = symbol_find_or_make (name);
4905
d02603dc 4906 (void) restore_line_pointer (endc);
252b5132
RH		 4907
4908 if (*input_line_pointer != ',')
4909 {
4910 as_bad (_("missing symbol name"));
4911 ignore_rest_of_line ();
4912 return;
4913 }
4914 ++input_line_pointer;
4915
d02603dc 4916 endc = get_symbol_name (&name);
252b5132
RH		 4917
4918 lab_sym = symbol_find_or_make (name);
4919
d02603dc 4920 (void) restore_line_pointer (endc);
252b5132
RH		 4921
4922 if (ext_sym != lab_sym)
4923 {
809ffe0d
ILT		 4924 expressionS exp;
4925
4926 exp.X_op = O_symbol;
4927 exp.X_add_symbol = lab_sym;
4928 exp.X_op_symbol = NULL;
4929 exp.X_add_number = 0;
4930 exp.X_unsigned = 0;
4931 symbol_set_value_expression (ext_sym, &exp);
252b5132
RH		 4932 }
4933
96d56e9f
NC		 4934 if (symbol_get_tc (ext_sym)->symbol_class == -1)
4935 symbol_get_tc (ext_sym)->symbol_class = XMC_PR;
809ffe0d 4936 symbol_get_tc (ext_sym)->output = 1;
252b5132
RH		 4937
4938 if (*input_line_pointer == ',')
4939 {
91d6fa6a 4940 expressionS exp;
252b5132
RH		 4941
4942 /* Ignore the third argument. */
4943 ++input_line_pointer;
91d6fa6a 4944 expression (& exp);
252b5132
RH		 4945 if (*input_line_pointer == ',')
4946 {
4947 /* Ignore the fourth argument. */
4948 ++input_line_pointer;
91d6fa6a 4949 expression (& exp);
252b5132
RH		 4950 if (*input_line_pointer == ',')
4951 {
4952 /* The fifth argument is the function size. */
4953 ++input_line_pointer;
85645aed
TG		 4954 symbol_get_tc (ext_sym)->u.size = symbol_new
4955 ("L0\001", absolute_section,(valueT) 0, &zero_address_frag);
4956 pseudo_set (symbol_get_tc (ext_sym)->u.size);
252b5132
RH		 4957 }
4958 }
4959 }
4960
4961 S_SET_DATA_TYPE (ext_sym, DT_FCN << N_BTSHFT);
4962 SF_SET_FUNCTION (ext_sym);
4963 SF_SET_PROCESS (ext_sym);
4964 coff_add_linesym (ext_sym);
4965
4966 demand_empty_rest_of_line ();
4967}
4968
4969/* The .bf pseudo-op. This is just like a COFF C_FCN symbol named
8642cce8
TR		 4970 ".bf". If the pseudo op .bi was seen before .bf, patch the .bi sym
4971 with the correct line number */
5d6255fe 4972
8642cce8 4973static symbolS *saved_bi_sym = 0;
252b5132
RH		 4974
4975static void
98027b10 4976ppc_bf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 4977{
4978 symbolS *sym;
4979
4980 sym = symbol_make (".bf");
4981 S_SET_SEGMENT (sym, text_section);
809ffe0d 4982 symbol_set_frag (sym, frag_now);
252b5132
RH		 4983 S_SET_VALUE (sym, frag_now_fix ());
4984 S_SET_STORAGE_CLASS (sym, C_FCN);
4985
4986 coff_line_base = get_absolute_expression ();
4987
4988 S_SET_NUMBER_AUXILIARY (sym, 1);
4989 SA_SET_SYM_LNNO (sym, coff_line_base);
4990
8642cce8 4991 /* Line number for bi. */
5d6255fe 4992 if (saved_bi_sym)
8642cce8
TR		 4993 {
4994 S_SET_VALUE (saved_bi_sym, coff_n_line_nos);
4995 saved_bi_sym = 0;
4996 }
5d6255fe 4997
8642cce8 4998
809ffe0d 4999 symbol_get_tc (sym)->output = 1;
252b5132
RH		 5000
5001 ppc_frob_label (sym);
5002
5003 demand_empty_rest_of_line ();
5004}
5005
5006/* The .ef pseudo-op. This is just like a COFF C_FCN symbol named
5007 ".ef", except that the line number is absolute, not relative to the
5008 most recent ".bf" symbol. */
5009
5010static void
98027b10 5011ppc_ef (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5012{
5013 symbolS *sym;
5014
5015 sym = symbol_make (".ef");
5016 S_SET_SEGMENT (sym, text_section);
809ffe0d 5017 symbol_set_frag (sym, frag_now);
252b5132
RH		 5018 S_SET_VALUE (sym, frag_now_fix ());
5019 S_SET_STORAGE_CLASS (sym, C_FCN);
5020 S_SET_NUMBER_AUXILIARY (sym, 1);
5021 SA_SET_SYM_LNNO (sym, get_absolute_expression ());
809ffe0d 5022 symbol_get_tc (sym)->output = 1;
252b5132
RH		 5023
5024 ppc_frob_label (sym);
5025
5026 demand_empty_rest_of_line ();
5027}
5028
5029/* The .bi and .ei pseudo-ops. These take a string argument and
5030 generates a C_BINCL or C_EINCL symbol, which goes at the start of
8642cce8
TR		 5031 the symbol list. The value of .bi will be know when the next .bf
5032 is encountered. */
252b5132
RH		 5033
5034static void
98027b10 5035ppc_biei (int ei)
252b5132
RH		 5036{
5037 static symbolS *last_biei;
5038
5039 char *name;
5040 int len;
5041 symbolS *sym;
5042 symbolS *look;
5043
5044 name = demand_copy_C_string (&len);
5045
5046 /* The value of these symbols is actually file offset. Here we set
5047 the value to the index into the line number entries. In
5048 ppc_frob_symbols we set the fix_line field, which will cause BFD
5049 to do the right thing. */
5050
5051 sym = symbol_make (name);
5052 /* obj-coff.c currently only handles line numbers correctly in the
5053 .text section. */
5054 S_SET_SEGMENT (sym, text_section);
5055 S_SET_VALUE (sym, coff_n_line_nos);
809ffe0d 5056 symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
252b5132
RH		 5057
5058 S_SET_STORAGE_CLASS (sym, ei ? C_EINCL : C_BINCL);
809ffe0d 5059 symbol_get_tc (sym)->output = 1;
81d4177b 5060
8642cce8 5061 /* Save bi. */
5d6255fe 5062 if (ei)
8642cce8
TR		 5063 saved_bi_sym = 0;
5064 else
5065 saved_bi_sym = sym;
5066
252b5132
RH		 5067 for (look = last_biei ? last_biei : symbol_rootP;
5068 (look != (symbolS *) NULL
5069 && (S_GET_STORAGE_CLASS (look) == C_FILE
5070 || S_GET_STORAGE_CLASS (look) == C_BINCL
5071 || S_GET_STORAGE_CLASS (look) == C_EINCL));
5072 look = symbol_next (look))
5073 ;
5074 if (look != (symbolS *) NULL)
5075 {
5076 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
5077 symbol_insert (sym, look, &symbol_rootP, &symbol_lastP);
5078 last_biei = sym;
5079 }
5080
5081 demand_empty_rest_of_line ();
5082}
5083
5084/* The .bs pseudo-op. This generates a C_BSTAT symbol named ".bs".
5085 There is one argument, which is a csect symbol. The value of the
5086 .bs symbol is the index of this csect symbol. */
5087
5088static void
98027b10 5089ppc_bs (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5090{
5091 char *name;
5092 char endc;
5093 symbolS *csect;
5094 symbolS *sym;
5095
5096 if (ppc_current_block != NULL)
5097 as_bad (_("nested .bs blocks"));
5098
d02603dc 5099 endc = get_symbol_name (&name);
252b5132
RH		 5100
5101 csect = symbol_find_or_make (name);
5102
d02603dc 5103 (void) restore_line_pointer (endc);
252b5132
RH		 5104
5105 sym = symbol_make (".bs");
5106 S_SET_SEGMENT (sym, now_seg);
5107 S_SET_STORAGE_CLASS (sym, C_BSTAT);
809ffe0d
ILT		 5108 symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
5109 symbol_get_tc (sym)->output = 1;
252b5132 5110
809ffe0d 5111 symbol_get_tc (sym)->within = csect;
252b5132
RH		 5112
5113 ppc_frob_label (sym);
5114
5115 ppc_current_block = sym;
5116
5117 demand_empty_rest_of_line ();
5118}
5119
5120/* The .es pseudo-op. Generate a C_ESTART symbol named .es. */
5121
5122static void
98027b10 5123ppc_es (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5124{
5125 symbolS *sym;
5126
5127 if (ppc_current_block == NULL)
5128 as_bad (_(".es without preceding .bs"));
5129
5130 sym = symbol_make (".es");
5131 S_SET_SEGMENT (sym, now_seg);
5132 S_SET_STORAGE_CLASS (sym, C_ESTAT);
809ffe0d
ILT		 5133 symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
5134 symbol_get_tc (sym)->output = 1;
252b5132
RH		 5135
5136 ppc_frob_label (sym);
5137
5138 ppc_current_block = NULL;
5139
5140 demand_empty_rest_of_line ();
5141}
5142
5143/* The .bb pseudo-op. Generate a C_BLOCK symbol named .bb, with a
5144 line number. */
5145
5146static void
98027b10 5147ppc_bb (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5148{
5149 symbolS *sym;
5150
5151 sym = symbol_make (".bb");
5152 S_SET_SEGMENT (sym, text_section);
809ffe0d 5153 symbol_set_frag (sym, frag_now);
252b5132
RH		 5154 S_SET_VALUE (sym, frag_now_fix ());
5155 S_SET_STORAGE_CLASS (sym, C_BLOCK);
5156
5157 S_SET_NUMBER_AUXILIARY (sym, 1);
5158 SA_SET_SYM_LNNO (sym, get_absolute_expression ());
5159
809ffe0d 5160 symbol_get_tc (sym)->output = 1;
252b5132
RH		 5161
5162 SF_SET_PROCESS (sym);
5163
5164 ppc_frob_label (sym);
5165
5166 demand_empty_rest_of_line ();
5167}
5168
5169/* The .eb pseudo-op. Generate a C_BLOCK symbol named .eb, with a
5170 line number. */
5171
5172static void
98027b10 5173ppc_eb (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5174{
5175 symbolS *sym;
5176
5177 sym = symbol_make (".eb");
5178 S_SET_SEGMENT (sym, text_section);
809ffe0d 5179 symbol_set_frag (sym, frag_now);
252b5132
RH		 5180 S_SET_VALUE (sym, frag_now_fix ());
5181 S_SET_STORAGE_CLASS (sym, C_BLOCK);
5182 S_SET_NUMBER_AUXILIARY (sym, 1);
5183 SA_SET_SYM_LNNO (sym, get_absolute_expression ());
809ffe0d 5184 symbol_get_tc (sym)->output = 1;
252b5132
RH		 5185
5186 SF_SET_PROCESS (sym);
5187
5188 ppc_frob_label (sym);
5189
5190 demand_empty_rest_of_line ();
5191}
5192
5193/* The .bc pseudo-op. This just creates a C_BCOMM symbol with a
5194 specified name. */
5195
5196static void
98027b10 5197ppc_bc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5198{
5199 char *name;
5200 int len;
5201 symbolS *sym;
5202
5203 name = demand_copy_C_string (&len);
5204 sym = symbol_make (name);
5205 S_SET_SEGMENT (sym, ppc_coff_debug_section);
809ffe0d 5206 symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
252b5132
RH		 5207 S_SET_STORAGE_CLASS (sym, C_BCOMM);
5208 S_SET_VALUE (sym, 0);
809ffe0d 5209 symbol_get_tc (sym)->output = 1;
252b5132
RH		 5210
5211 ppc_frob_label (sym);
5212
5213 demand_empty_rest_of_line ();
5214}
5215
5216/* The .ec pseudo-op. This just creates a C_ECOMM symbol. */
5217
5218static void
98027b10 5219ppc_ec (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5220{
5221 symbolS *sym;
5222
5223 sym = symbol_make (".ec");
5224 S_SET_SEGMENT (sym, ppc_coff_debug_section);
809ffe0d 5225 symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
252b5132
RH		 5226 S_SET_STORAGE_CLASS (sym, C_ECOMM);
5227 S_SET_VALUE (sym, 0);
809ffe0d 5228 symbol_get_tc (sym)->output = 1;
252b5132
RH		 5229
5230 ppc_frob_label (sym);
5231
5232 demand_empty_rest_of_line ();
5233}
5234
5235/* The .toc pseudo-op. Switch to the .toc subsegment. */
5236
5237static void
98027b10 5238ppc_toc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5239{
5240 if (ppc_toc_csect != (symbolS *) NULL)
809ffe0d 5241 subseg_set (data_section, symbol_get_tc (ppc_toc_csect)->subseg);
252b5132
RH		 5242 else
5243 {
5244 subsegT subseg;
5245 symbolS *sym;
5246 symbolS *list;
81d4177b 5247
252b5132
RH		 5248 subseg = ppc_data_subsegment;
5249 ++ppc_data_subsegment;
5250
5251 subseg_new (segment_name (data_section), subseg);
5252 ppc_toc_frag = frag_now;
5253
5254 sym = symbol_find_or_make ("TOC[TC0]");
809ffe0d 5255 symbol_set_frag (sym, frag_now);
252b5132
RH		 5256 S_SET_SEGMENT (sym, data_section);
5257 S_SET_VALUE (sym, (valueT) frag_now_fix ());
809ffe0d
ILT		 5258 symbol_get_tc (sym)->subseg = subseg;
5259 symbol_get_tc (sym)->output = 1;
5260 symbol_get_tc (sym)->within = sym;
252b5132
RH		 5261
5262 ppc_toc_csect = sym;
81d4177b 5263
252b5132 5264 for (list = ppc_data_csects;
809ffe0d
ILT		 5265 symbol_get_tc (list)->next != (symbolS *) NULL;
5266 list = symbol_get_tc (list)->next)
252b5132 5267 ;
809ffe0d 5268 symbol_get_tc (list)->next = sym;
252b5132
RH		 5269
5270 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
809ffe0d
ILT		 5271 symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP,
5272 &symbol_lastP);
252b5132
RH		 5273 }
5274
5275 ppc_current_csect = ppc_toc_csect;
5276
5277 demand_empty_rest_of_line ();
5278}
5279
5280/* The AIX assembler automatically aligns the operands of a .long or
5281 .short pseudo-op, and we want to be compatible. */
5282
5283static void
98027b10 5284ppc_xcoff_cons (int log_size)
252b5132
RH		 5285{
5286 frag_align (log_size, 0, 0);
5287 record_alignment (now_seg, log_size);
5288 cons (1 << log_size);
5289}
5290
5291static void
98027b10 5292ppc_vbyte (int dummy ATTRIBUTE_UNUSED)
252b5132
RH		 5293{
5294 expressionS exp;
5295 int byte_count;
5296
5297 (void) expression (&exp);
5298
5299 if (exp.X_op != O_constant)
5300 {
5301 as_bad (_("non-constant byte count"));
5302 return;
5303 }
5304
5305 byte_count = exp.X_add_number;
5306
5307 if (*input_line_pointer != ',')
5308 {
5309 as_bad (_("missing value"));
5310 return;
5311 }
5312
5313 ++input_line_pointer;
5314 cons (byte_count);
5315}
5316
85645aed
TG		 5317void
5318ppc_xcoff_end (void)
5319{
5320 int i;
5321
5322 for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++)
5323 {
5324 struct dw_section *dws = &dw_sections[i];
5325 struct dw_subsection *dwss;
5326
5327 if (dws->anon_subseg)
5328 {
5329 dwss = dws->anon_subseg;
5330 dwss->link = dws->list_subseg;
5331 }
5332 else
5333 dwss = dws->list_subseg;
5334
5335 for (; dwss != NULL; dwss = dwss->link)
5336 if (dwss->end_exp.X_add_symbol != NULL)
5337 {
5338 subseg_set (dws->sect, dwss->subseg);
5339 symbol_set_value_now (dwss->end_exp.X_add_symbol);
5340 }
5341 }
22f72c48 5342 ppc_cpu = 0;
85645aed
TG		 5343}
5344
252b5132 5345#endif /* OBJ_XCOFF */
0baf16f2 5346#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
252b5132
RH		 5347\f
5348/* The .tc pseudo-op. This is used when generating either XCOFF or
5349 ELF. This takes two or more arguments.
5350
5351 When generating XCOFF output, the first argument is the name to
5352 give to this location in the toc; this will be a symbol with class
0baf16f2 5353 TC. The rest of the arguments are N-byte values to actually put at
252b5132 5354 this location in the TOC; often there is just one more argument, a
1049f94e 5355 relocatable symbol reference. The size of the value to store
0baf16f2
AM		 5356 depends on target word size. A 32-bit target uses 4-byte values, a
5357 64-bit target uses 8-byte values.
252b5132
RH		 5358
5359 When not generating XCOFF output, the arguments are the same, but
5360 the first argument is simply ignored. */
5361
5362static void
98027b10 5363ppc_tc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5364{
5365#ifdef OBJ_XCOFF
5366
5367 /* Define the TOC symbol name. */
5368 {
5369 char *name;
5370 char endc;
5371 symbolS *sym;
5372
5373 if (ppc_toc_csect == (symbolS *) NULL
5374 || ppc_toc_csect != ppc_current_csect)
5375 {
5376 as_bad (_(".tc not in .toc section"));
5377 ignore_rest_of_line ();
5378 return;
5379 }
5380
d02603dc 5381 endc = get_symbol_name (&name);
252b5132
RH		 5382
5383 sym = symbol_find_or_make (name);
5384
d02603dc 5385 (void) restore_line_pointer (endc);
252b5132
RH		 5386
5387 if (S_IS_DEFINED (sym))
5388 {
5389 symbolS *label;
5390
809ffe0d 5391 label = symbol_get_tc (ppc_current_csect)->within;
96d56e9f 5392 if (symbol_get_tc (label)->symbol_class != XMC_TC0)
252b5132
RH		 5393 {
5394 as_bad (_(".tc with no label"));
5395 ignore_rest_of_line ();
5396 return;
5397 }
5398
5399 S_SET_SEGMENT (label, S_GET_SEGMENT (sym));
809ffe0d 5400 symbol_set_frag (label, symbol_get_frag (sym));
252b5132
RH		 5401 S_SET_VALUE (label, S_GET_VALUE (sym));
5402
5403 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5404 ++input_line_pointer;
5405
5406 return;
5407 }
5408
5409 S_SET_SEGMENT (sym, now_seg);
809ffe0d 5410 symbol_set_frag (sym, frag_now);
252b5132 5411 S_SET_VALUE (sym, (valueT) frag_now_fix ());
96d56e9f 5412 symbol_get_tc (sym)->symbol_class = XMC_TC;
809ffe0d 5413 symbol_get_tc (sym)->output = 1;
252b5132
RH		 5414
5415 ppc_frob_label (sym);
5416 }
5417
0baf16f2
AM		 5418#endif /* OBJ_XCOFF */
5419#ifdef OBJ_ELF
9c7977b3 5420 int align;
252b5132
RH		 5421
5422 /* Skip the TOC symbol name. */
5423 while (is_part_of_name (*input_line_pointer)
d13d4015 5424 || *input_line_pointer == ' '
252b5132
RH		 5425 || *input_line_pointer == '['
5426 || *input_line_pointer == ']'
5427 || *input_line_pointer == '{'
5428 || *input_line_pointer == '}')
5429 ++input_line_pointer;
5430
0baf16f2 5431 /* Align to a four/eight byte boundary. */
2b3c4602 5432 align = ppc_obj64 ? 3 : 2;
9c7977b3
AM		 5433 frag_align (align, 0, 0);
5434 record_alignment (now_seg, align);
0baf16f2 5435#endif /* OBJ_ELF */
252b5132
RH		 5436
5437 if (*input_line_pointer != ',')
5438 demand_empty_rest_of_line ();
5439 else
5440 {
5441 ++input_line_pointer;
2b3c4602 5442 cons (ppc_obj64 ? 8 : 4);
252b5132
RH		 5443 }
5444}
0baf16f2
AM		 5445
5446/* Pseudo-op .machine. */
0baf16f2
AM		 5447
5448static void
98027b10 5449ppc_machine (int ignore ATTRIBUTE_UNUSED)
0baf16f2 5450{
d02603dc 5451 char c;
69c040df
AM		 5452 char *cpu_string;
5453#define MAX_HISTORY 100
fa452fa6 5454 static ppc_cpu_t *cpu_history;
69c040df
AM		 5455 static int curr_hist;
5456
5457 SKIP_WHITESPACE ();
5458
d02603dc
NC		 5459 c = get_symbol_name (&cpu_string);
5460 cpu_string = xstrdup (cpu_string);
5461 (void) restore_line_pointer (c);
69c040df
AM		 5462
5463 if (cpu_string != NULL)
5464 {
fa452fa6 5465 ppc_cpu_t old_cpu = ppc_cpu;
69fe9ce5 5466 ppc_cpu_t new_cpu;
69c040df
AM		 5467 char *p;
5468
5469 for (p = cpu_string; *p != 0; p++)
5470 *p = TOLOWER (*p);
5471
5472 if (strcmp (cpu_string, "push") == 0)
5473 {
5474 if (cpu_history == NULL)
325801bd 5475 cpu_history = XNEWVEC (ppc_cpu_t, MAX_HISTORY);
69c040df
AM		 5476
5477 if (curr_hist >= MAX_HISTORY)
5478 as_bad (_(".machine stack overflow"));
5479 else
5480 cpu_history[curr_hist++] = ppc_cpu;
5481 }
5482 else if (strcmp (cpu_string, "pop") == 0)
5483 {
5484 if (curr_hist <= 0)
5485 as_bad (_(".machine stack underflow"));
5486 else
5487 ppc_cpu = cpu_history[--curr_hist];
5488 }
776fc418 5489 else if ((new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, cpu_string)) != 0)
69fe9ce5 5490 ppc_cpu = new_cpu;
69c040df
AM		 5491 else
5492 as_bad (_("invalid machine `%s'"), cpu_string);
5493
5494 if (ppc_cpu != old_cpu)
5495 ppc_setup_opcodes ();
5496 }
5497
5498 demand_empty_rest_of_line ();
0baf16f2 5499}
0baf16f2 5500#endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
252b5132 5501\f
252b5132
RH		 5502#ifdef OBJ_XCOFF
5503
5504/* XCOFF specific symbol and file handling. */
5505
5506/* Canonicalize the symbol name. We use the to force the suffix, if
5507 any, to use square brackets, and to be in upper case. */
5508
5509char *
98027b10 5510ppc_canonicalize_symbol_name (char *name)
252b5132
RH		 5511{
5512 char *s;
5513
5514 if (ppc_stab_symbol)
5515 return name;
5516
5517 for (s = name; *s != '\0' && *s != '{' && *s != '['; s++)
5518 ;
5519 if (*s != '\0')
5520 {
5521 char brac;
5522
5523 if (*s == '[')
5524 brac = ']';
5525 else
5526 {
5527 *s = '[';
5528 brac = '}';
5529 }
5530
5531 for (s++; *s != '\0' && *s != brac; s++)
3882b010 5532 *s = TOUPPER (*s);
252b5132
RH		 5533
5534 if (*s == '\0' || s[1] != '\0')
5535 as_bad (_("bad symbol suffix"));
5536
5537 *s = ']';
5538 }
5539
5540 return name;
5541}
5542
5543/* Set the class of a symbol based on the suffix, if any. This is
5544 called whenever a new symbol is created. */
5545
5546void
98027b10 5547ppc_symbol_new_hook (symbolS *sym)
252b5132 5548{
809ffe0d 5549 struct ppc_tc_sy *tc;
252b5132
RH		 5550 const char *s;
5551
809ffe0d
ILT		 5552 tc = symbol_get_tc (sym);
5553 tc->next = NULL;
5554 tc->output = 0;
96d56e9f 5555 tc->symbol_class = -1;
809ffe0d
ILT		 5556 tc->real_name = NULL;
5557 tc->subseg = 0;
5558 tc->align = 0;
85645aed
TG		 5559 tc->u.size = NULL;
5560 tc->u.dw = NULL;
809ffe0d 5561 tc->within = NULL;
252b5132
RH		 5562
5563 if (ppc_stab_symbol)
5564 return;
5565
5566 s = strchr (S_GET_NAME (sym), '[');
5567 if (s == (const char *) NULL)
5568 {
5569 /* There is no suffix. */
5570 return;
5571 }
5572
5573 ++s;
5574
5575 switch (s[0])
5576 {
5577 case 'B':
5578 if (strcmp (s, "BS]") == 0)
96d56e9f 5579 tc->symbol_class = XMC_BS;
252b5132
RH		 5580 break;
5581 case 'D':
5582 if (strcmp (s, "DB]") == 0)
96d56e9f 5583 tc->symbol_class = XMC_DB;
252b5132 5584 else if (strcmp (s, "DS]") == 0)
96d56e9f 5585 tc->symbol_class = XMC_DS;
252b5132
RH		 5586 break;
5587 case 'G':
5588 if (strcmp (s, "GL]") == 0)
96d56e9f 5589 tc->symbol_class = XMC_GL;
252b5132
RH		 5590 break;
5591 case 'P':
5592 if (strcmp (s, "PR]") == 0)
96d56e9f 5593 tc->symbol_class = XMC_PR;
252b5132
RH		 5594 break;
5595 case 'R':
5596 if (strcmp (s, "RO]") == 0)
96d56e9f 5597 tc->symbol_class = XMC_RO;
252b5132 5598 else if (strcmp (s, "RW]") == 0)
96d56e9f 5599 tc->symbol_class = XMC_RW;
252b5132
RH		 5600 break;
5601 case 'S':
5602 if (strcmp (s, "SV]") == 0)
96d56e9f 5603 tc->symbol_class = XMC_SV;
252b5132
RH		 5604 break;
5605 case 'T':
5606 if (strcmp (s, "TC]") == 0)
96d56e9f 5607 tc->symbol_class = XMC_TC;
252b5132 5608 else if (strcmp (s, "TI]") == 0)
96d56e9f 5609 tc->symbol_class = XMC_TI;
252b5132 5610 else if (strcmp (s, "TB]") == 0)
96d56e9f 5611 tc->symbol_class = XMC_TB;
252b5132 5612 else if (strcmp (s, "TC0]") == 0 || strcmp (s, "T0]") == 0)
96d56e9f 5613 tc->symbol_class = XMC_TC0;
252b5132
RH		 5614 break;
5615 case 'U':
5616 if (strcmp (s, "UA]") == 0)
96d56e9f 5617 tc->symbol_class = XMC_UA;
252b5132 5618 else if (strcmp (s, "UC]") == 0)
96d56e9f 5619 tc->symbol_class = XMC_UC;
252b5132
RH		 5620 break;
5621 case 'X':
5622 if (strcmp (s, "XO]") == 0)
96d56e9f 5623 tc->symbol_class = XMC_XO;
252b5132
RH		 5624 break;
5625 }
5626
96d56e9f 5627 if (tc->symbol_class == -1)
d6ed37ed 5628 as_bad (_("unrecognized symbol suffix"));
252b5132
RH		 5629}
5630
252b5132
RH		 5631/* This variable is set by ppc_frob_symbol if any absolute symbols are
5632 seen. It tells ppc_adjust_symtab whether it needs to look through
5633 the symbols. */
5634
b34976b6 5635static bfd_boolean ppc_saw_abs;
252b5132
RH		 5636
5637/* Change the name of a symbol just before writing it out. Set the
5638 real name if the .rename pseudo-op was used. Otherwise, remove any
5639 class suffix. Return 1 if the symbol should not be included in the
5640 symbol table. */
5641
5642int
98027b10 5643ppc_frob_symbol (symbolS *sym)
252b5132
RH		 5644{
5645 static symbolS *ppc_last_function;
5646 static symbolS *set_end;
5647
5648 /* Discard symbols that should not be included in the output symbol
5649 table. */
809ffe0d
ILT		 5650 if (! symbol_used_in_reloc_p (sym)
5651 && ((symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) != 0
670ec21d 5652 || (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym))
809ffe0d 5653 && ! symbol_get_tc (sym)->output
252b5132
RH		 5654 && S_GET_STORAGE_CLASS (sym) != C_FILE)))
5655 return 1;
5656
a161fe53
AM		 5657 /* This one will disappear anyway. Don't make a csect sym for it. */
5658 if (sym == abs_section_sym)
5659 return 1;
5660
809ffe0d
ILT		 5661 if (symbol_get_tc (sym)->real_name != (char *) NULL)
5662 S_SET_NAME (sym, symbol_get_tc (sym)->real_name);
252b5132
RH		 5663 else
5664 {
5665 const char *name;
5666 const char *s;
5667
5668 name = S_GET_NAME (sym);
5669 s = strchr (name, '[');
5670 if (s != (char *) NULL)
5671 {
5672 unsigned int len;
5673 char *snew;
5674
5675 len = s - name;
a44e2901 5676 snew = xstrndup (name, len);
252b5132
RH		 5677
5678 S_SET_NAME (sym, snew);
5679 }
5680 }
5681
5682 if (set_end != (symbolS *) NULL)
5683 {
5684 SA_SET_SYM_ENDNDX (set_end, sym);
5685 set_end = NULL;
5686 }
5687
5688 if (SF_GET_FUNCTION (sym))
5689 {
5690 if (ppc_last_function != (symbolS *) NULL)
5691 as_bad (_("two .function pseudo-ops with no intervening .ef"));
5692 ppc_last_function = sym;
85645aed 5693 if (symbol_get_tc (sym)->u.size != (symbolS *) NULL)
252b5132 5694 {
85645aed 5695 resolve_symbol_value (symbol_get_tc (sym)->u.size);
809ffe0d 5696 SA_SET_SYM_FSIZE (sym,
85645aed 5697 (long) S_GET_VALUE (symbol_get_tc (sym)->u.size));
252b5132
RH		 5698 }
5699 }
5700 else if (S_GET_STORAGE_CLASS (sym) == C_FCN
5701 && strcmp (S_GET_NAME (sym), ".ef") == 0)
5702 {
5703 if (ppc_last_function == (symbolS *) NULL)
5704 as_bad (_(".ef with no preceding .function"));
5705 else
5706 {
5707 set_end = ppc_last_function;
5708 ppc_last_function = NULL;
5709
5710 /* We don't have a C_EFCN symbol, but we need to force the
5711 COFF backend to believe that it has seen one. */
5712 coff_last_function = NULL;
5713 }
5714 }
5715
670ec21d 5716 if (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym))
809ffe0d 5717 && (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) == 0
252b5132
RH		 5718 && S_GET_STORAGE_CLASS (sym) != C_FILE
5719 && S_GET_STORAGE_CLASS (sym) != C_FCN
5720 && S_GET_STORAGE_CLASS (sym) != C_BLOCK
5721 && S_GET_STORAGE_CLASS (sym) != C_BSTAT
5722 && S_GET_STORAGE_CLASS (sym) != C_ESTAT
5723 && S_GET_STORAGE_CLASS (sym) != C_BINCL
5724 && S_GET_STORAGE_CLASS (sym) != C_EINCL
5725 && S_GET_SEGMENT (sym) != ppc_coff_debug_section)
5726 S_SET_STORAGE_CLASS (sym, C_HIDEXT);
5727
5728 if (S_GET_STORAGE_CLASS (sym) == C_EXT
8602d4fe 5729 || S_GET_STORAGE_CLASS (sym) == C_AIX_WEAKEXT
252b5132
RH		 5730 || S_GET_STORAGE_CLASS (sym) == C_HIDEXT)
5731 {
5732 int i;
5733 union internal_auxent *a;
5734
5735 /* Create a csect aux. */
5736 i = S_GET_NUMBER_AUXILIARY (sym);
5737 S_SET_NUMBER_AUXILIARY (sym, i + 1);
809ffe0d 5738 a = &coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].u.auxent;
96d56e9f 5739 if (symbol_get_tc (sym)->symbol_class == XMC_TC0)
252b5132
RH		 5740 {
5741 /* This is the TOC table. */
5742 know (strcmp (S_GET_NAME (sym), "TOC") == 0);
5743 a->x_csect.x_scnlen.l = 0;
5744 a->x_csect.x_smtyp = (2 << 3) | XTY_SD;
5745 }
809ffe0d 5746 else if (symbol_get_tc (sym)->subseg != 0)
252b5132
RH		 5747 {
5748 /* This is a csect symbol. x_scnlen is the size of the
5749 csect. */
809ffe0d 5750 if (symbol_get_tc (sym)->next == (symbolS *) NULL)
fd361982 5751 a->x_csect.x_scnlen.l = (bfd_section_size (S_GET_SEGMENT (sym))
252b5132
RH		 5752 - S_GET_VALUE (sym));
5753 else
5754 {
6386f3a7 5755 resolve_symbol_value (symbol_get_tc (sym)->next);
809ffe0d 5756 a->x_csect.x_scnlen.l = (S_GET_VALUE (symbol_get_tc (sym)->next)
252b5132
RH		 5757 - S_GET_VALUE (sym));
5758 }
809ffe0d 5759 a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_SD;
252b5132
RH		 5760 }
5761 else if (S_GET_SEGMENT (sym) == bss_section)
5762 {
5763 /* This is a common symbol. */
809ffe0d
ILT		 5764 a->x_csect.x_scnlen.l = symbol_get_frag (sym)->fr_offset;
5765 a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_CM;
252b5132 5766 if (S_IS_EXTERNAL (sym))
96d56e9f 5767 symbol_get_tc (sym)->symbol_class = XMC_RW;
252b5132 5768 else
96d56e9f 5769 symbol_get_tc (sym)->symbol_class = XMC_BS;
252b5132
RH		 5770 }
5771 else if (S_GET_SEGMENT (sym) == absolute_section)
5772 {
5773 /* This is an absolute symbol. The csect will be created by
99a814a1 5774 ppc_adjust_symtab. */
b34976b6 5775 ppc_saw_abs = TRUE;
252b5132 5776 a->x_csect.x_smtyp = XTY_LD;
96d56e9f
NC		 5777 if (symbol_get_tc (sym)->symbol_class == -1)
5778 symbol_get_tc (sym)->symbol_class = XMC_XO;
252b5132
RH		 5779 }
5780 else if (! S_IS_DEFINED (sym))
5781 {
5782 /* This is an external symbol. */
5783 a->x_csect.x_scnlen.l = 0;
5784 a->x_csect.x_smtyp = XTY_ER;
5785 }
96d56e9f 5786 else if (symbol_get_tc (sym)->symbol_class == XMC_TC)
252b5132
RH		 5787 {
5788 symbolS *next;
5789
5790 /* This is a TOC definition. x_scnlen is the size of the
5791 TOC entry. */
5792 next = symbol_next (sym);
96d56e9f 5793 while (symbol_get_tc (next)->symbol_class == XMC_TC0)
252b5132
RH		 5794 next = symbol_next (next);
5795 if (next == (symbolS *) NULL
96d56e9f 5796 || symbol_get_tc (next)->symbol_class != XMC_TC)
252b5132
RH		 5797 {
5798 if (ppc_after_toc_frag == (fragS *) NULL)
fd361982 5799 a->x_csect.x_scnlen.l = (bfd_section_size (data_section)
252b5132
RH		 5800 - S_GET_VALUE (sym));
5801 else
5802 a->x_csect.x_scnlen.l = (ppc_after_toc_frag->fr_address
5803 - S_GET_VALUE (sym));
5804 }
5805 else
5806 {
6386f3a7 5807 resolve_symbol_value (next);
252b5132
RH		 5808 a->x_csect.x_scnlen.l = (S_GET_VALUE (next)
5809 - S_GET_VALUE (sym));
5810 }
5811 a->x_csect.x_smtyp = (2 << 3) | XTY_SD;
5812 }
5813 else
5814 {
5815 symbolS *csect;
5816
5817 /* This is a normal symbol definition. x_scnlen is the
5818 symbol index of the containing csect. */
5819 if (S_GET_SEGMENT (sym) == text_section)
5820 csect = ppc_text_csects;
5821 else if (S_GET_SEGMENT (sym) == data_section)
5822 csect = ppc_data_csects;
5823 else
5824 abort ();
5825
5826 /* Skip the initial dummy symbol. */
809ffe0d 5827 csect = symbol_get_tc (csect)->next;
252b5132
RH		 5828
5829 if (csect == (symbolS *) NULL)
5830 {
5831 as_warn (_("warning: symbol %s has no csect"), S_GET_NAME (sym));
5832 a->x_csect.x_scnlen.l = 0;
5833 }
5834 else
5835 {
809ffe0d 5836 while (symbol_get_tc (csect)->next != (symbolS *) NULL)
252b5132 5837 {
6386f3a7 5838 resolve_symbol_value (symbol_get_tc (csect)->next);
809ffe0d
ILT		 5839 if (S_GET_VALUE (symbol_get_tc (csect)->next)
5840 > S_GET_VALUE (sym))
252b5132 5841 break;
809ffe0d 5842 csect = symbol_get_tc (csect)->next;
252b5132
RH		 5843 }
5844
809ffe0d
ILT		 5845 a->x_csect.x_scnlen.p =
5846 coffsymbol (symbol_get_bfdsym (csect))->native;
5847 coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].fix_scnlen =
5848 1;
252b5132
RH		 5849 }
5850 a->x_csect.x_smtyp = XTY_LD;
5851 }
81d4177b 5852
252b5132
RH		 5853 a->x_csect.x_parmhash = 0;
5854 a->x_csect.x_snhash = 0;
96d56e9f 5855 if (symbol_get_tc (sym)->symbol_class == -1)
252b5132
RH		 5856 a->x_csect.x_smclas = XMC_PR;
5857 else
96d56e9f 5858 a->x_csect.x_smclas = symbol_get_tc (sym)->symbol_class;
252b5132
RH		 5859 a->x_csect.x_stab = 0;
5860 a->x_csect.x_snstab = 0;
5861
5862 /* Don't let the COFF backend resort these symbols. */
809ffe0d 5863 symbol_get_bfdsym (sym)->flags |= BSF_NOT_AT_END;
252b5132
RH		 5864 }
5865 else if (S_GET_STORAGE_CLASS (sym) == C_BSTAT)
5866 {
5867 /* We want the value to be the symbol index of the referenced
5868 csect symbol. BFD will do that for us if we set the right
5869 flags. */
b782de16
AM		 5870 asymbol *bsym = symbol_get_bfdsym (symbol_get_tc (sym)->within);
5871 combined_entry_type *c = coffsymbol (bsym)->native;
5872
5873 S_SET_VALUE (sym, (valueT) (size_t) c);
809ffe0d 5874 coffsymbol (symbol_get_bfdsym (sym))->native->fix_value = 1;
252b5132
RH		 5875 }
5876 else if (S_GET_STORAGE_CLASS (sym) == C_STSYM)
5877 {
5878 symbolS *block;
c734e7e3 5879 valueT base;
252b5132 5880
809ffe0d 5881 block = symbol_get_tc (sym)->within;
c734e7e3
TG		 5882 if (block)
5883 {
5884 /* The value is the offset from the enclosing csect. */
5885 symbolS *csect;
5886
5887 csect = symbol_get_tc (block)->within;
5888 resolve_symbol_value (csect);
5889 base = S_GET_VALUE (csect);
5890 }
5891 else
5892 base = 0;
5893
5894 S_SET_VALUE (sym, S_GET_VALUE (sym) - base);
252b5132
RH		 5895 }
5896 else if (S_GET_STORAGE_CLASS (sym) == C_BINCL
5897 || S_GET_STORAGE_CLASS (sym) == C_EINCL)
5898 {
5899 /* We want the value to be a file offset into the line numbers.
99a814a1
AM		 5900 BFD will do that for us if we set the right flags. We have
5901 already set the value correctly. */
809ffe0d 5902 coffsymbol (symbol_get_bfdsym (sym))->native->fix_line = 1;
252b5132
RH		 5903 }
5904
5905 return 0;
5906}
5907
5908/* Adjust the symbol table. This creates csect symbols for all
5909 absolute symbols. */
5910
5911void
98027b10 5912ppc_adjust_symtab (void)
252b5132
RH		 5913{
5914 symbolS *sym;
5915
5916 if (! ppc_saw_abs)
5917 return;
5918
5919 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
5920 {
5921 symbolS *csect;
5922 int i;
5923 union internal_auxent *a;
5924
5925 if (S_GET_SEGMENT (sym) != absolute_section)
5926 continue;
5927
5928 csect = symbol_create (".abs[XO]", absolute_section,
5929 S_GET_VALUE (sym), &zero_address_frag);
809ffe0d 5930 symbol_get_bfdsym (csect)->value = S_GET_VALUE (sym);
252b5132
RH		 5931 S_SET_STORAGE_CLASS (csect, C_HIDEXT);
5932 i = S_GET_NUMBER_AUXILIARY (csect);
5933 S_SET_NUMBER_AUXILIARY (csect, i + 1);
809ffe0d 5934 a = &coffsymbol (symbol_get_bfdsym (csect))->native[i + 1].u.auxent;
252b5132
RH		 5935 a->x_csect.x_scnlen.l = 0;
5936 a->x_csect.x_smtyp = XTY_SD;
5937 a->x_csect.x_parmhash = 0;
5938 a->x_csect.x_snhash = 0;
5939 a->x_csect.x_smclas = XMC_XO;
5940 a->x_csect.x_stab = 0;
5941 a->x_csect.x_snstab = 0;
5942
5943 symbol_insert (csect, sym, &symbol_rootP, &symbol_lastP);
5944
5945 i = S_GET_NUMBER_AUXILIARY (sym);
809ffe0d
ILT		 5946 a = &coffsymbol (symbol_get_bfdsym (sym))->native[i].u.auxent;
5947 a->x_csect.x_scnlen.p = coffsymbol (symbol_get_bfdsym (csect))->native;
5948 coffsymbol (symbol_get_bfdsym (sym))->native[i].fix_scnlen = 1;
252b5132
RH		 5949 }
5950
b34976b6 5951 ppc_saw_abs = FALSE;
252b5132
RH		 5952}
5953
5954/* Set the VMA for a section. This is called on all the sections in
5955 turn. */
5956
5957void
98027b10 5958ppc_frob_section (asection *sec)
252b5132 5959{
931e13a6 5960 static bfd_vma vma = 0;
252b5132 5961
85645aed 5962 /* Dwarf sections start at 0. */
fd361982 5963 if (bfd_section_flags (sec) & SEC_DEBUGGING)
85645aed
TG		 5964 return;
5965
931e13a6 5966 vma = md_section_align (sec, vma);
fd361982
AM		 5967 bfd_set_section_vma (sec, vma);
5968 vma += bfd_section_size (sec);
252b5132
RH		 5969}
5970
5971#endif /* OBJ_XCOFF */
5972\f
6d4af3c2 5973const char *
98027b10 5974md_atof (int type, char *litp, int *sizep)
252b5132 5975{
499ac353 5976 return ieee_md_atof (type, litp, sizep, target_big_endian);
252b5132
RH		 5977}
5978
5979/* Write a value out to the object file, using the appropriate
5980 endianness. */
5981
5982void
98027b10 5983md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 5984{
5985 if (target_big_endian)
5986 number_to_chars_bigendian (buf, val, n);
5987 else
5988 number_to_chars_littleendian (buf, val, n);
5989}
5990
5991/* Align a section (I don't know why this is machine dependent). */
5992
5993valueT
3aeeedbb 5994md_section_align (asection *seg ATTRIBUTE_UNUSED, valueT addr)
252b5132 5995{
3aeeedbb
AM		 5996#ifdef OBJ_ELF
5997 return addr;
5998#else
fd361982 5999 int align = bfd_section_alignment (seg);
252b5132 6000
8d3842cd 6001 return ((addr + (1 << align) - 1) & -(1 << align));
3aeeedbb 6002#endif
252b5132
RH		 6003}
6004
6005/* We don't have any form of relaxing. */
6006
6007int
98027b10
AM		 6008md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
6009 asection *seg ATTRIBUTE_UNUSED)
252b5132
RH		 6010{
6011 abort ();
6012 return 0;
6013}
6014
6015/* Convert a machine dependent frag. We never generate these. */
6016
6017void
98027b10
AM		 6018md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
6019 asection *sec ATTRIBUTE_UNUSED,
6020 fragS *fragp ATTRIBUTE_UNUSED)
252b5132
RH		 6021{
6022 abort ();
6023}
6024
6025/* We have no need to default values of symbols. */
6026
252b5132 6027symbolS *
98027b10 6028md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 6029{
6030 return 0;
6031}
6032\f
6033/* Functions concerning relocs. */
6034
6035/* The location from which a PC relative jump should be calculated,
6036 given a PC relative reloc. */
6037
6038long
98027b10 6039md_pcrel_from_section (fixS *fixp, segT sec ATTRIBUTE_UNUSED)
252b5132
RH		 6040{
6041 return fixp->fx_frag->fr_address + fixp->fx_where;
6042}
6043
6044#ifdef OBJ_XCOFF
6045
6046/* This is called to see whether a fixup should be adjusted to use a
6047 section symbol. We take the opportunity to change a fixup against
6048 a symbol in the TOC subsegment into a reloc against the
6049 corresponding .tc symbol. */
6050
6051int
98027b10 6052ppc_fix_adjustable (fixS *fix)
252b5132 6053{
b782de16
AM		 6054 valueT val = resolve_symbol_value (fix->fx_addsy);
6055 segT symseg = S_GET_SEGMENT (fix->fx_addsy);
6056 TC_SYMFIELD_TYPE *tc;
6057
6058 if (symseg == absolute_section)
6059 return 0;
252b5132 6060
85645aed 6061 /* Always adjust symbols in debugging sections. */
fd361982 6062 if (bfd_section_flags (symseg) & SEC_DEBUGGING)
85645aed
TG		 6063 return 1;
6064
252b5132 6065 if (ppc_toc_csect != (symbolS *) NULL
252b5132 6066 && fix->fx_addsy != ppc_toc_csect
b782de16 6067 && symseg == data_section
252b5132
RH		 6068 && val >= ppc_toc_frag->fr_address
6069 && (ppc_after_toc_frag == (fragS *) NULL
6070 || val < ppc_after_toc_frag->fr_address))
6071 {
6072 symbolS *sy;
6073
6074 for (sy = symbol_next (ppc_toc_csect);
6075 sy != (symbolS *) NULL;
6076 sy = symbol_next (sy))
6077 {
b782de16
AM		 6078 TC_SYMFIELD_TYPE *sy_tc = symbol_get_tc (sy);
6079
96d56e9f 6080 if (sy_tc->symbol_class == XMC_TC0)
252b5132 6081 continue;
96d56e9f 6082 if (sy_tc->symbol_class != XMC_TC)
252b5132 6083 break;
b782de16 6084 if (val == resolve_symbol_value (sy))
252b5132
RH		 6085 {
6086 fix->fx_addsy = sy;
6087 fix->fx_addnumber = val - ppc_toc_frag->fr_address;
6088 return 0;
6089 }
6090 }
6091
6092 as_bad_where (fix->fx_file, fix->fx_line,
6093 _("symbol in .toc does not match any .tc"));
6094 }
6095
6096 /* Possibly adjust the reloc to be against the csect. */
b782de16
AM		 6097 tc = symbol_get_tc (fix->fx_addsy);
6098 if (tc->subseg == 0
96d56e9f
NC		 6099 && tc->symbol_class != XMC_TC0
6100 && tc->symbol_class != XMC_TC
b782de16 6101 && symseg != bss_section
252b5132 6102 /* Don't adjust if this is a reloc in the toc section. */
b782de16 6103 && (symseg != data_section
252b5132
RH		 6104 || ppc_toc_csect == NULL
6105 || val < ppc_toc_frag->fr_address
6106 || (ppc_after_toc_frag != NULL
6107 && val >= ppc_after_toc_frag->fr_address)))
6108 {
2fb4b302 6109 symbolS *csect = tc->within;
252b5132 6110
2fb4b302
TG		 6111 /* If the symbol was not declared by a label (eg: a section symbol),
6112 use the section instead of the csect. This doesn't happen in
6113 normal AIX assembly code. */
6114 if (csect == NULL)
6115 csect = seg_info (symseg)->sym;
252b5132 6116
2fb4b302
TG		 6117 fix->fx_offset += val - symbol_get_frag (csect)->fr_address;
6118 fix->fx_addsy = csect;
252b5132 6119
b782de16 6120 return 0;
252b5132
RH		 6121 }
6122
6123 /* Adjust a reloc against a .lcomm symbol to be against the base
6124 .lcomm. */
b782de16 6125 if (symseg == bss_section
252b5132
RH		 6126 && ! S_IS_EXTERNAL (fix->fx_addsy))
6127 {
b782de16
AM		 6128 symbolS *sy = symbol_get_frag (fix->fx_addsy)->fr_symbol;
6129
6130 fix->fx_offset += val - resolve_symbol_value (sy);
6131 fix->fx_addsy = sy;
252b5132
RH		 6132 }
6133
6134 return 0;
6135}
6136
6137/* A reloc from one csect to another must be kept. The assembler
6138 will, of course, keep relocs between sections, and it will keep
6139 absolute relocs, but we need to force it to keep PC relative relocs
6140 between two csects in the same section. */
6141
6142int
98027b10 6143ppc_force_relocation (fixS *fix)
252b5132
RH		 6144{
6145 /* At this point fix->fx_addsy should already have been converted to
6146 a csect symbol. If the csect does not include the fragment, then
6147 we need to force the relocation. */
6148 if (fix->fx_pcrel
6149 && fix->fx_addsy != NULL
809ffe0d
ILT		 6150 && symbol_get_tc (fix->fx_addsy)->subseg != 0
6151 && ((symbol_get_frag (fix->fx_addsy)->fr_address
6152 > fix->fx_frag->fr_address)
6153 || (symbol_get_tc (fix->fx_addsy)->next != NULL
6154 && (symbol_get_frag (symbol_get_tc (fix->fx_addsy)->next)->fr_address
252b5132
RH		 6155 <= fix->fx_frag->fr_address))))
6156 return 1;
6157
ae6063d4 6158 return generic_force_reloc (fix);
252b5132 6159}
252b5132
RH		 6160#endif /* OBJ_XCOFF */
6161
0baf16f2 6162#ifdef OBJ_ELF
a161fe53
AM		 6163/* If this function returns non-zero, it guarantees that a relocation
6164 will be emitted for a fixup. */
6165
6166int
98027b10 6167ppc_force_relocation (fixS *fix)
a161fe53
AM		 6168{
6169 /* Branch prediction relocations must force a relocation, as must
6170 the vtable description relocs. */
6171 switch (fix->fx_r_type)
6172 {
6173 case BFD_RELOC_PPC_B16_BRTAKEN:
6174 case BFD_RELOC_PPC_B16_BRNTAKEN:
6175 case BFD_RELOC_PPC_BA16_BRTAKEN:
6176 case BFD_RELOC_PPC_BA16_BRNTAKEN:
c744ecf2 6177 case BFD_RELOC_24_PLT_PCREL:
a161fe53 6178 case BFD_RELOC_PPC64_TOC:
a161fe53 6179 return 1;
6911b7dc
AM		 6180 case BFD_RELOC_PPC_B26:
6181 case BFD_RELOC_PPC_BA26:
6182 case BFD_RELOC_PPC_B16:
6183 case BFD_RELOC_PPC_BA16:
05d0e962 6184 case BFD_RELOC_PPC64_REL24_NOTOC:
6911b7dc
AM		 6185 /* All branch fixups targeting a localentry symbol must
6186 force a relocation. */
6187 if (fix->fx_addsy)
6188 {
6189 asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy);
6190 elf_symbol_type *elfsym
6191 = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym);
6192 gas_assert (elfsym);
6193 if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0)
6194 return 1;
6195 }
6196 break;
a161fe53
AM		 6197 default:
6198 break;
6199 }
6200
cdba85ec 6201 if (fix->fx_r_type >= BFD_RELOC_PPC_TLS
c213164a 6202 && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL)
cdba85ec
AM		 6203 return 1;
6204
ae6063d4 6205 return generic_force_reloc (fix);
a161fe53
AM		 6206}
6207
0baf16f2 6208int
98027b10 6209ppc_fix_adjustable (fixS *fix)
252b5132 6210{
6911b7dc
AM		 6211 switch (fix->fx_r_type)
6212 {
6213 /* All branch fixups targeting a localentry symbol must
6214 continue using the symbol. */
6215 case BFD_RELOC_PPC_B26:
6216 case BFD_RELOC_PPC_BA26:
6217 case BFD_RELOC_PPC_B16:
6218 case BFD_RELOC_PPC_BA16:
6219 case BFD_RELOC_PPC_B16_BRTAKEN:
6220 case BFD_RELOC_PPC_B16_BRNTAKEN:
6221 case BFD_RELOC_PPC_BA16_BRTAKEN:
6222 case BFD_RELOC_PPC_BA16_BRNTAKEN:
05d0e962 6223 case BFD_RELOC_PPC64_REL24_NOTOC:
6911b7dc
AM		 6224 if (fix->fx_addsy)
6225 {
6226 asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy);
6227 elf_symbol_type *elfsym
6228 = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym);
6229 gas_assert (elfsym);
6230 if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0)
6231 return 0;
6232 }
6233 break;
6234 default:
6235 break;
6236 }
6237
0baf16f2
AM		 6238 return (fix->fx_r_type != BFD_RELOC_16_GOTOFF
6239 && fix->fx_r_type != BFD_RELOC_LO16_GOTOFF
6240 && fix->fx_r_type != BFD_RELOC_HI16_GOTOFF
6241 && fix->fx_r_type != BFD_RELOC_HI16_S_GOTOFF
cc9edbf3
AM		 6242 && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_DS
6243 && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_LO_DS
5663e321 6244 && fix->fx_r_type != BFD_RELOC_PPC64_GOT_PCREL34
334d91b9
AM		 6245 && fix->fx_r_type != BFD_RELOC_24_PLT_PCREL
6246 && fix->fx_r_type != BFD_RELOC_32_PLTOFF
6247 && fix->fx_r_type != BFD_RELOC_32_PLT_PCREL
6248 && fix->fx_r_type != BFD_RELOC_LO16_PLTOFF
6249 && fix->fx_r_type != BFD_RELOC_HI16_PLTOFF
6250 && fix->fx_r_type != BFD_RELOC_HI16_S_PLTOFF
6251 && fix->fx_r_type != BFD_RELOC_64_PLTOFF
6252 && fix->fx_r_type != BFD_RELOC_64_PLT_PCREL
6253 && fix->fx_r_type != BFD_RELOC_PPC64_PLT16_LO_DS
5663e321 6254 && fix->fx_r_type != BFD_RELOC_PPC64_PLT_PCREL34
334d91b9
AM		 6255 && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16
6256 && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO
6257 && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HI
6258 && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HA
6259 && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_DS
6260 && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO_DS
0baf16f2 6261 && fix->fx_r_type != BFD_RELOC_GPREL16
334d91b9
AM		 6262 && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_LO16A
6263 && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HI16A
6264 && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HA16A
0baf16f2
AM		 6265 && fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT
6266 && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY
cdba85ec 6267 && !(fix->fx_r_type >= BFD_RELOC_PPC_TLS
c213164a 6268 && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL));
252b5132 6269}
0baf16f2 6270#endif
252b5132 6271
b9c361e0
JL		 6272void
6273ppc_frag_check (struct frag *fragP)
6274{
a9479dc0
AM		 6275 if ((fragP->fr_address & fragP->insn_addr) != 0)
6276 as_bad_where (fragP->fr_file, fragP->fr_line,
6277 _("instruction address is not a multiple of %d"),
6278 fragP->insn_addr + 1);
b9c361e0
JL		 6279}
6280
22f72c48
AM		 6281/* rs_align_code frag handling. */
6282
6283enum ppc_nop_encoding_for_rs_align_code
6284{
6285 PPC_NOP_VANILLA,
6286 PPC_NOP_VLE,
6287 PPC_NOP_GROUP_P6,
6288 PPC_NOP_GROUP_P7
6289};
6290
6291unsigned int
6292ppc_nop_select (void)
6293{
6294 if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
6295 return PPC_NOP_VLE;
6296 if ((ppc_cpu & (PPC_OPCODE_POWER9 | PPC_OPCODE_E500MC)) == 0)
6297 {
6298 if ((ppc_cpu & PPC_OPCODE_POWER7) != 0)
6299 return PPC_NOP_GROUP_P7;
6300 if ((ppc_cpu & PPC_OPCODE_POWER6) != 0)
6301 return PPC_NOP_GROUP_P6;
6302 }
6303 return PPC_NOP_VANILLA;
6304}
3aeeedbb
AM		 6305
6306void
6307ppc_handle_align (struct frag *fragP)
6308{
6309 valueT count = (fragP->fr_next->fr_address
6310 - (fragP->fr_address + fragP->fr_fix));
22f72c48
AM		 6311 char *dest = fragP->fr_literal + fragP->fr_fix;
6312 enum ppc_nop_encoding_for_rs_align_code nop_select = *dest & 0xff;
6313
6314 /* Pad with zeros if not inserting a whole number of instructions.
6315 We could pad with zeros up to an instruction boundary then follow
6316 with nops but odd counts indicate data in an executable section
6317 so padding with zeros is most appropriate. */
6318 if (count == 0
de626965 6319 || (nop_select == PPC_NOP_VLE ? (count & 1) != 0 : (count & 3) != 0))
22f72c48
AM		 6320 {
6321 *dest = 0;
6322 return;
6323 }
3aeeedbb 6324
22f72c48 6325 if (nop_select == PPC_NOP_VLE)
b9c361e0 6326 {
b9c361e0
JL		 6327
6328 fragP->fr_var = 2;
6329 md_number_to_chars (dest, 0x4400, 2);
6330 }
22f72c48 6331 else
3aeeedbb 6332 {
3aeeedbb 6333 fragP->fr_var = 4;
cef4f754
AM		 6334
6335 if (count > 4 * nop_limit && count < 0x2000000)
6336 {
6337 struct frag *rest;
6338
6339 /* Make a branch, then follow with nops. Insert another
6340 frag to handle the nops. */
6341 md_number_to_chars (dest, 0x48000000 + count, 4);
6342 count -= 4;
6343 if (count == 0)
6344 return;
6345
6346 rest = xmalloc (SIZEOF_STRUCT_FRAG + 4);
6347 memcpy (rest, fragP, SIZEOF_STRUCT_FRAG);
6348 fragP->fr_next = rest;
6349 fragP = rest;
6350 rest->fr_address += rest->fr_fix + 4;
6351 rest->fr_fix = 0;
6352 /* If we leave the next frag as rs_align_code we'll come here
6353 again, resulting in a bunch of branches rather than a
6354 branch followed by nops. */
6355 rest->fr_type = rs_align;
6356 dest = rest->fr_literal;
6357 }
6358
3aeeedbb
AM		 6359 md_number_to_chars (dest, 0x60000000, 4);
6360
22f72c48 6361 if (nop_select >= PPC_NOP_GROUP_P6)
3aeeedbb 6362 {
3fea0c3b
AM		 6363 /* For power6, power7, and power8, we want the last nop to
6364 be a group terminating one. Do this by inserting an
6365 rs_fill frag immediately after this one, with its address
6366 set to the last nop location. This will automatically
6367 reduce the number of nops in the current frag by one. */
3aeeedbb
AM		 6368 if (count > 4)
6369 {
6370 struct frag *group_nop = xmalloc (SIZEOF_STRUCT_FRAG + 4);
6371
6372 memcpy (group_nop, fragP, SIZEOF_STRUCT_FRAG);
6373 group_nop->fr_address = group_nop->fr_next->fr_address - 4;
6374 group_nop->fr_fix = 0;
6375 group_nop->fr_offset = 1;
6376 group_nop->fr_type = rs_fill;
6377 fragP->fr_next = group_nop;
6378 dest = group_nop->fr_literal;
6379 }
6380
22f72c48 6381 if (nop_select == PPC_NOP_GROUP_P6)
42240548
PB		 6382 /* power6 group terminating nop: "ori 1,1,0". */
6383 md_number_to_chars (dest, 0x60210000, 4);
22f72c48
AM		 6384 else
6385 /* power7/power8 group terminating nop: "ori 2,2,0". */
6386 md_number_to_chars (dest, 0x60420000, 4);
3aeeedbb
AM		 6387 }
6388 }
6389}
6390
252b5132 6391/* Apply a fixup to the object code. This is called for all the
3b8b57a9 6392 fixups we generated by the calls to fix_new_exp, above. */
252b5132 6393
94f592af 6394void
62ebcb5c 6395md_apply_fix (fixS *fixP, valueT *valP, segT seg)
252b5132 6396{
94f592af 6397 valueT value = * valP;
5656a981
AM		 6398 offsetT fieldval;
6399 const struct powerpc_operand *operand;
252b5132
RH		 6400
6401#ifdef OBJ_ELF
94f592af 6402 if (fixP->fx_addsy != NULL)
252b5132 6403 {
a161fe53 6404 /* Hack around bfd_install_relocation brain damage. */
94f592af
NC		 6405 if (fixP->fx_pcrel)
6406 value += fixP->fx_frag->fr_address + fixP->fx_where;
a680de9a
PB		 6407
6408 if (fixP->fx_addsy == abs_section_sym)
6409 fixP->fx_done = 1;
252b5132
RH		 6410 }
6411 else
94f592af 6412 fixP->fx_done = 1;
252b5132 6413#else
a161fe53 6414 /* FIXME FIXME FIXME: The value we are passed in *valP includes
7be1c489
AM		 6415 the symbol values. If we are doing this relocation the code in
6416 write.c is going to call bfd_install_relocation, which is also
6417 going to use the symbol value. That means that if the reloc is
6418 fully resolved we want to use *valP since bfd_install_relocation is
6419 not being used.
9f0eb232
RS		 6420 However, if the reloc is not fully resolved we do not want to
6421 use *valP, and must use fx_offset instead. If the relocation
6422 is PC-relative, we then need to re-apply md_pcrel_from_section
6423 to this new relocation value. */
94f592af
NC		 6424 if (fixP->fx_addsy == (symbolS *) NULL)
6425 fixP->fx_done = 1;
6426
252b5132 6427 else
9f0eb232
RS		 6428 {
6429 value = fixP->fx_offset;
6430 if (fixP->fx_pcrel)
6431 value -= md_pcrel_from_section (fixP, seg);
6432 }
a161fe53
AM		 6433#endif
6434
7ba71655
AM		 6435 /* We are only able to convert some relocs to pc-relative. */
6436 if (fixP->fx_pcrel)
6437 {
6438 switch (fixP->fx_r_type)
6439 {
4a969973
AM		 6440 case BFD_RELOC_64:
6441 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6442 break;
6443
6444 case BFD_RELOC_32:
6445 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6446 break;
6447
6448 case BFD_RELOC_16:
6449 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6450 break;
6451
7ba71655
AM		 6452 case BFD_RELOC_LO16:
6453 fixP->fx_r_type = BFD_RELOC_LO16_PCREL;
6454 break;
6455
6456 case BFD_RELOC_HI16:
6457 fixP->fx_r_type = BFD_RELOC_HI16_PCREL;
6458 break;
6459
6460 case BFD_RELOC_HI16_S:
6461 fixP->fx_r_type = BFD_RELOC_HI16_S_PCREL;
6462 break;
6463
4a969973
AM		 6464 case BFD_RELOC_PPC64_ADDR16_HIGH:
6465 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGH;
7ba71655
AM		 6466 break;
6467
4a969973
AM		 6468 case BFD_RELOC_PPC64_ADDR16_HIGHA:
6469 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHA;
7ba71655
AM		 6470 break;
6471
4a969973
AM		 6472 case BFD_RELOC_PPC64_HIGHER:
6473 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER;
6474 break;
6475
6476 case BFD_RELOC_PPC64_HIGHER_S:
6477 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA;
6478 break;
6479
6480 case BFD_RELOC_PPC64_HIGHEST:
6481 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST;
6482 break;
6483
6484 case BFD_RELOC_PPC64_HIGHEST_S:
6485 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA;
7ba71655
AM		 6486 break;
6487
5663e321
AM		 6488 case BFD_RELOC_PPC64_ADDR16_HIGHER34:
6489 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER34;
6490 break;
6491
6492 case BFD_RELOC_PPC64_ADDR16_HIGHERA34:
6493 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA34;
6494 break;
6495
6496 case BFD_RELOC_PPC64_ADDR16_HIGHEST34:
6497 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST34;
6498 break;
6499
6500 case BFD_RELOC_PPC64_ADDR16_HIGHESTA34:
6501 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA34;
6502 break;
6503
7ba71655
AM		 6504 case BFD_RELOC_PPC_16DX_HA:
6505 fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA;
6506 break;
6507
5663e321
AM		 6508 case BFD_RELOC_PPC64_D34:
6509 fixP->fx_r_type = BFD_RELOC_PPC64_PCREL34;
6510 break;
6511
6512 case BFD_RELOC_PPC64_D28:
6513 fixP->fx_r_type = BFD_RELOC_PPC64_PCREL28;
6514 break;
6515
7ba71655
AM		 6516 default:
6517 break;
6518 }
6519 }
6520 else if (!fixP->fx_done
6521 && fixP->fx_r_type == BFD_RELOC_PPC_16DX_HA)
252b5132 6522 {
7ba71655
AM		 6523 /* addpcis is relative to next insn address. */
6524 value -= 4;
6525 fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA;
6526 fixP->fx_pcrel = 1;
252b5132 6527 }
252b5132 6528
5656a981 6529 operand = NULL;
3b8b57a9 6530 if (fixP->fx_pcrel_adjust != 0)
252b5132 6531 {
5656a981 6532 /* This is a fixup on an instruction. */
3b8b57a9 6533 int opindex = fixP->fx_pcrel_adjust & 0xff;
252b5132 6534
5656a981 6535 operand = &powerpc_operands[opindex];
252b5132 6536#ifdef OBJ_XCOFF
0baf16f2
AM		 6537 /* An instruction like `lwz 9,sym(30)' when `sym' is not a TOC symbol
6538 does not generate a reloc. It uses the offset of `sym' within its
6539 csect. Other usages, such as `.long sym', generate relocs. This
6540 is the documented behaviour of non-TOC symbols. */
252b5132 6541 if ((operand->flags & PPC_OPERAND_PARENS) != 0
b84bf58a 6542 && (operand->bitm & 0xfff0) == 0xfff0
252b5132 6543 && operand->shift == 0
2b3c4602 6544 && (operand->insert == NULL || ppc_obj64)
94f592af
NC		 6545 && fixP->fx_addsy != NULL
6546 && symbol_get_tc (fixP->fx_addsy)->subseg != 0
96d56e9f
NC		 6547 && symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TC
6548 && symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TC0
94f592af 6549 && S_GET_SEGMENT (fixP->fx_addsy) != bss_section)
252b5132 6550 {
94f592af
NC		 6551 value = fixP->fx_offset;
6552 fixP->fx_done = 1;
252b5132 6553 }
ac21e7da
TG		 6554
6555 /* During parsing of instructions, a TOC16 reloc is generated for
6556 instructions such as 'lwz RT,SYM(RB)' if SYM is a symbol defined
6557 in the toc. But at parse time, SYM may be not yet defined, so
6558 check again here. */
6559 if (fixP->fx_r_type == BFD_RELOC_16
6560 && fixP->fx_addsy != NULL
6561 && ppc_is_toc_sym (fixP->fx_addsy))
6562 fixP->fx_r_type = BFD_RELOC_PPC_TOC16;
252b5132 6563#endif
5656a981
AM		 6564 }
6565
6566 /* Calculate value to be stored in field. */
6567 fieldval = value;
6568 switch (fixP->fx_r_type)
6569 {
1ec2d25e 6570#ifdef OBJ_ELF
5656a981
AM		 6571 case BFD_RELOC_PPC64_ADDR16_LO_DS:
6572 case BFD_RELOC_PPC_VLE_LO16A:
6573 case BFD_RELOC_PPC_VLE_LO16D:
1ec2d25e 6574#endif
5656a981
AM		 6575 case BFD_RELOC_LO16:
6576 case BFD_RELOC_LO16_PCREL:
6577 fieldval = value & 0xffff;
6578 sign_extend_16:
6579 if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0)
f9c6b907 6580 fieldval = SEX16 (fieldval);
5656a981
AM		 6581 fixP->fx_no_overflow = 1;
6582 break;
3c9d25f4 6583
f9c6b907
AM		 6584 case BFD_RELOC_HI16:
6585 case BFD_RELOC_HI16_PCREL:
5656a981 6586#ifdef OBJ_ELF
f9c6b907
AM		 6587 if (REPORT_OVERFLOW_HI && ppc_obj64)
6588 {
6589 fieldval = value >> 16;
6590 if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0)
6591 {
6592 valueT sign = (((valueT) -1 >> 16) + 1) >> 1;
6593 fieldval = ((valueT) fieldval ^ sign) - sign;
6594 }
6595 break;
6596 }
2b0f3761 6597 /* Fallthru */
f9c6b907 6598
5656a981
AM		 6599 case BFD_RELOC_PPC_VLE_HI16A:
6600 case BFD_RELOC_PPC_VLE_HI16D:
f9c6b907 6601 case BFD_RELOC_PPC64_ADDR16_HIGH:
5656a981 6602#endif
5656a981
AM		 6603 fieldval = PPC_HI (value);
6604 goto sign_extend_16;
0baf16f2 6605
f9c6b907
AM		 6606 case BFD_RELOC_HI16_S:
6607 case BFD_RELOC_HI16_S_PCREL:
7ba71655 6608 case BFD_RELOC_PPC_16DX_HA:
a680de9a 6609 case BFD_RELOC_PPC_REL16DX_HA:
5656a981 6610#ifdef OBJ_ELF
f9c6b907
AM		 6611 if (REPORT_OVERFLOW_HI && ppc_obj64)
6612 {
6613 fieldval = (value + 0x8000) >> 16;
6614 if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0)
6615 {
6616 valueT sign = (((valueT) -1 >> 16) + 1) >> 1;
6617 fieldval = ((valueT) fieldval ^ sign) - sign;
6618 }
6619 break;
6620 }
2b0f3761 6621 /* Fallthru */
f9c6b907 6622
5656a981
AM		 6623 case BFD_RELOC_PPC_VLE_HA16A:
6624 case BFD_RELOC_PPC_VLE_HA16D:
f9c6b907 6625 case BFD_RELOC_PPC64_ADDR16_HIGHA:
5656a981 6626#endif
5656a981
AM		 6627 fieldval = PPC_HA (value);
6628 goto sign_extend_16;
0baf16f2 6629
3b8b57a9 6630#ifdef OBJ_ELF
5656a981
AM		 6631 case BFD_RELOC_PPC64_HIGHER:
6632 fieldval = PPC_HIGHER (value);
6633 goto sign_extend_16;
252b5132 6634
5656a981
AM		 6635 case BFD_RELOC_PPC64_HIGHER_S:
6636 fieldval = PPC_HIGHERA (value);
6637 goto sign_extend_16;
0baf16f2 6638
5656a981
AM		 6639 case BFD_RELOC_PPC64_HIGHEST:
6640 fieldval = PPC_HIGHEST (value);
6641 goto sign_extend_16;
0baf16f2 6642
5656a981
AM		 6643 case BFD_RELOC_PPC64_HIGHEST_S:
6644 fieldval = PPC_HIGHESTA (value);
6645 goto sign_extend_16;
6646#endif
6647
6648 default:
6649 break;
6650 }
6651
6652 if (operand != NULL)
6653 {
6654 /* Handle relocs in an insn. */
5656a981
AM		 6655 switch (fixP->fx_r_type)
6656 {
7fa9fcb6 6657#ifdef OBJ_ELF
3b8b57a9
AM		 6658 /* The following relocs can't be calculated by the assembler.
6659 Leave the field zero. */
cdba85ec
AM		 6660 case BFD_RELOC_PPC_TPREL16:
6661 case BFD_RELOC_PPC_TPREL16_LO:
6662 case BFD_RELOC_PPC_TPREL16_HI:
6663 case BFD_RELOC_PPC_TPREL16_HA:
cdba85ec
AM		 6664 case BFD_RELOC_PPC_DTPREL16:
6665 case BFD_RELOC_PPC_DTPREL16_LO:
6666 case BFD_RELOC_PPC_DTPREL16_HI:
6667 case BFD_RELOC_PPC_DTPREL16_HA:
cdba85ec
AM		 6668 case BFD_RELOC_PPC_GOT_TLSGD16:
6669 case BFD_RELOC_PPC_GOT_TLSGD16_LO:
6670 case BFD_RELOC_PPC_GOT_TLSGD16_HI:
6671 case BFD_RELOC_PPC_GOT_TLSGD16_HA:
6672 case BFD_RELOC_PPC_GOT_TLSLD16:
6673 case BFD_RELOC_PPC_GOT_TLSLD16_LO:
6674 case BFD_RELOC_PPC_GOT_TLSLD16_HI:
6675 case BFD_RELOC_PPC_GOT_TLSLD16_HA:
6676 case BFD_RELOC_PPC_GOT_TPREL16:
6677 case BFD_RELOC_PPC_GOT_TPREL16_LO:
6678 case BFD_RELOC_PPC_GOT_TPREL16_HI:
6679 case BFD_RELOC_PPC_GOT_TPREL16_HA:
6680 case BFD_RELOC_PPC_GOT_DTPREL16:
6681 case BFD_RELOC_PPC_GOT_DTPREL16_LO:
6682 case BFD_RELOC_PPC_GOT_DTPREL16_HI:
6683 case BFD_RELOC_PPC_GOT_DTPREL16_HA:
6684 case BFD_RELOC_PPC64_TPREL16_DS:
6685 case BFD_RELOC_PPC64_TPREL16_LO_DS:
f9c6b907
AM		 6686 case BFD_RELOC_PPC64_TPREL16_HIGH:
6687 case BFD_RELOC_PPC64_TPREL16_HIGHA:
cdba85ec
AM		 6688 case BFD_RELOC_PPC64_TPREL16_HIGHER:
6689 case BFD_RELOC_PPC64_TPREL16_HIGHERA:
6690 case BFD_RELOC_PPC64_TPREL16_HIGHEST:
6691 case BFD_RELOC_PPC64_TPREL16_HIGHESTA:
f9c6b907
AM		 6692 case BFD_RELOC_PPC64_DTPREL16_HIGH:
6693 case BFD_RELOC_PPC64_DTPREL16_HIGHA:
cdba85ec
AM		 6694 case BFD_RELOC_PPC64_DTPREL16_DS:
6695 case BFD_RELOC_PPC64_DTPREL16_LO_DS:
6696 case BFD_RELOC_PPC64_DTPREL16_HIGHER:
6697 case BFD_RELOC_PPC64_DTPREL16_HIGHERA:
6698 case BFD_RELOC_PPC64_DTPREL16_HIGHEST:
6699 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA:
c213164a
AM		 6700 case BFD_RELOC_PPC64_TPREL34:
6701 case BFD_RELOC_PPC64_DTPREL34:
87c69f97
AM		 6702 case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34:
6703 case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34:
6704 case BFD_RELOC_PPC64_GOT_TPREL_PCREL34:
6705 case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34:
3b8b57a9 6706 gas_assert (fixP->fx_addsy != NULL);
7c1d0959 6707 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3b8b57a9 6708 fieldval = 0;
cdba85ec 6709 break;
3b8b57a9
AM		 6710
6711 /* These also should leave the field zero for the same
6712 reason. Note that older versions of gas wrote values
6713 here. If we want to go back to the old behaviour, then
6714 all _LO and _LO_DS cases will need to be treated like
6715 BFD_RELOC_LO16_PCREL above. Similarly for _HI etc. */
6716 case BFD_RELOC_16_GOTOFF:
6717 case BFD_RELOC_LO16_GOTOFF:
6718 case BFD_RELOC_HI16_GOTOFF:
6719 case BFD_RELOC_HI16_S_GOTOFF:
6720 case BFD_RELOC_LO16_PLTOFF:
6721 case BFD_RELOC_HI16_PLTOFF:
6722 case BFD_RELOC_HI16_S_PLTOFF:
6723 case BFD_RELOC_GPREL16:
6724 case BFD_RELOC_16_BASEREL:
6725 case BFD_RELOC_LO16_BASEREL:
6726 case BFD_RELOC_HI16_BASEREL:
6727 case BFD_RELOC_HI16_S_BASEREL:
6728 case BFD_RELOC_PPC_TOC16:
6729 case BFD_RELOC_PPC64_TOC16_LO:
6730 case BFD_RELOC_PPC64_TOC16_HI:
6731 case BFD_RELOC_PPC64_TOC16_HA:
6732 case BFD_RELOC_PPC64_PLTGOT16:
6733 case BFD_RELOC_PPC64_PLTGOT16_LO:
6734 case BFD_RELOC_PPC64_PLTGOT16_HI:
6735 case BFD_RELOC_PPC64_PLTGOT16_HA:
6736 case BFD_RELOC_PPC64_GOT16_DS:
6737 case BFD_RELOC_PPC64_GOT16_LO_DS:
6738 case BFD_RELOC_PPC64_PLT16_LO_DS:
6739 case BFD_RELOC_PPC64_SECTOFF_DS:
6740 case BFD_RELOC_PPC64_SECTOFF_LO_DS:
6741 case BFD_RELOC_PPC64_TOC16_DS:
6742 case BFD_RELOC_PPC64_TOC16_LO_DS:
6743 case BFD_RELOC_PPC64_PLTGOT16_DS:
6744 case BFD_RELOC_PPC64_PLTGOT16_LO_DS:
6745 case BFD_RELOC_PPC_EMB_NADDR16:
6746 case BFD_RELOC_PPC_EMB_NADDR16_LO:
6747 case BFD_RELOC_PPC_EMB_NADDR16_HI:
6748 case BFD_RELOC_PPC_EMB_NADDR16_HA:
6749 case BFD_RELOC_PPC_EMB_SDAI16:
6750 case BFD_RELOC_PPC_EMB_SDA2I16:
6751 case BFD_RELOC_PPC_EMB_SDA2REL:
252b5132 6752 case BFD_RELOC_PPC_EMB_SDA21:
3b8b57a9
AM		 6753 case BFD_RELOC_PPC_EMB_MRKREF:
6754 case BFD_RELOC_PPC_EMB_RELSEC16:
6755 case BFD_RELOC_PPC_EMB_RELST_LO:
6756 case BFD_RELOC_PPC_EMB_RELST_HI:
6757 case BFD_RELOC_PPC_EMB_RELST_HA:
6758 case BFD_RELOC_PPC_EMB_BIT_FLD:
6759 case BFD_RELOC_PPC_EMB_RELSDA:
6760 case BFD_RELOC_PPC_VLE_SDA21:
6761 case BFD_RELOC_PPC_VLE_SDA21_LO:
6762 case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
6763 case BFD_RELOC_PPC_VLE_SDAREL_LO16D:
6764 case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
6765 case BFD_RELOC_PPC_VLE_SDAREL_HI16D:
6766 case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
6767 case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
5663e321
AM		 6768 case BFD_RELOC_PPC64_GOT_PCREL34:
6769 case BFD_RELOC_PPC64_PLT_PCREL34:
3b8b57a9 6770 gas_assert (fixP->fx_addsy != NULL);
2b0f3761 6771 /* Fallthru */
3b8b57a9
AM		 6772
6773 case BFD_RELOC_PPC_TLS:
6774 case BFD_RELOC_PPC_TLSGD:
6775 case BFD_RELOC_PPC_TLSLD:
c213164a 6776 case BFD_RELOC_PPC64_TLS_PCREL:
3b8b57a9 6777 fieldval = 0;
3b8b57a9 6778 break;
7fa9fcb6
TG		 6779#endif
6780
6781#ifdef OBJ_XCOFF
6782 case BFD_RELOC_PPC_B16:
6783 /* Adjust the offset to the instruction boundary. */
6784 fieldval += 2;
6785 break;
6786#endif
252b5132 6787
f728387b
AM		 6788 case BFD_RELOC_VTABLE_INHERIT:
6789 case BFD_RELOC_VTABLE_ENTRY:
6790 case BFD_RELOC_PPC_DTPMOD:
6791 case BFD_RELOC_PPC_TPREL:
6792 case BFD_RELOC_PPC_DTPREL:
6793 case BFD_RELOC_PPC_COPY:
6794 case BFD_RELOC_PPC_GLOB_DAT:
6795 case BFD_RELOC_32_PLT_PCREL:
6796 case BFD_RELOC_PPC_EMB_NADDR32:
6797 case BFD_RELOC_PPC64_TOC:
6798 case BFD_RELOC_CTOR:
6799 case BFD_RELOC_32:
6800 case BFD_RELOC_32_PCREL:
6801 case BFD_RELOC_RVA:
6802 case BFD_RELOC_64:
6803 case BFD_RELOC_64_PCREL:
6804 case BFD_RELOC_PPC64_ADDR64_LOCAL:
6805 as_bad_where (fixP->fx_file, fixP->fx_line,
6806 _("%s unsupported as instruction fixup"),
6807 bfd_get_reloc_code_name (fixP->fx_r_type));
6808 fixP->fx_done = 1;
6809 return;
6810
3b8b57a9 6811 default:
252b5132 6812 break;
3b8b57a9 6813 }
252b5132 6814
3b8b57a9
AM		 6815#ifdef OBJ_ELF
6816/* powerpc uses RELA style relocs, so if emitting a reloc the field
6817 contents can stay at zero. */
6818#define APPLY_RELOC fixP->fx_done
6819#else
6820#define APPLY_RELOC 1
6821#endif
5663e321
AM		 6822 /* We need to call the insert function even when fieldval is
6823 zero if the insert function would translate that zero to a
6824 bit pattern other than all zeros. */
3b8b57a9
AM		 6825 if ((fieldval != 0 && APPLY_RELOC) || operand->insert != NULL)
6826 {
5663e321 6827 uint64_t insn;
487b24d8
AM		 6828 unsigned char *where;
6829
3b8b57a9
AM		 6830 /* Fetch the instruction, insert the fully resolved operand
6831 value, and stuff the instruction back again. */
487b24d8 6832 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
3b8b57a9 6833 if (target_big_endian)
31a91399 6834 {
5663e321 6835 if (fixP->fx_size < 4)
487b24d8 6836 insn = bfd_getb16 (where);
5663e321
AM		 6837 else
6838 {
6839 insn = bfd_getb32 (where);
6840 if (fixP->fx_size > 4)
6841 insn = insn << 32 | bfd_getb32 (where + 4);
6842 }
31a91399
NC		 6843 }
6844 else
3b8b57a9 6845 {
5663e321 6846 if (fixP->fx_size < 4)
487b24d8 6847 insn = bfd_getl16 (where);
5663e321
AM		 6848 else
6849 {
6850 insn = bfd_getl32 (where);
6851 if (fixP->fx_size > 4)
6852 insn = insn << 32 | bfd_getl32 (where + 4);
6853 }
3b8b57a9
AM		 6854 }
6855 insn = ppc_insert_operand (insn, operand, fieldval,
6856 fixP->tc_fix_data.ppc_cpu,
6857 fixP->fx_file, fixP->fx_line);
6858 if (target_big_endian)
6859 {
5663e321 6860 if (fixP->fx_size < 4)
487b24d8 6861 bfd_putb16 (insn, where);
5663e321
AM		 6862 else
6863 {
6864 if (fixP->fx_size > 4)
6865 {
6866 bfd_putb32 (insn, where + 4);
6867 insn >>= 32;
6868 }
6869 bfd_putb32 (insn, where);
6870 }
3b8b57a9
AM		 6871 }
6872 else
6873 {
5663e321 6874 if (fixP->fx_size < 4)
487b24d8 6875 bfd_putl16 (insn, where);
5663e321
AM		 6876 else
6877 {
6878 if (fixP->fx_size > 4)
6879 {
6880 bfd_putl32 (insn, where + 4);
6881 insn >>= 32;
6882 }
6883 bfd_putl32 (insn, where);
6884 }
3b8b57a9
AM		 6885 }
6886 }
6887
6888 if (fixP->fx_done)
6889 /* Nothing else to do here. */
6890 return;
6891
6892 gas_assert (fixP->fx_addsy != NULL);
62ebcb5c 6893 if (fixP->fx_r_type == BFD_RELOC_NONE)
3b8b57a9 6894 {
3b4dbbbf 6895 const char *sfile;
3b8b57a9
AM		 6896 unsigned int sline;
6897
6898 /* Use expr_symbol_where to see if this is an expression
6899 symbol. */
6900 if (expr_symbol_where (fixP->fx_addsy, &sfile, &sline))
6901 as_bad_where (fixP->fx_file, fixP->fx_line,
6902 _("unresolved expression that must be resolved"));
6903 else
6904 as_bad_where (fixP->fx_file, fixP->fx_line,
6905 _("unsupported relocation against %s"),
6906 S_GET_NAME (fixP->fx_addsy));
6907 fixP->fx_done = 1;
6908 return;
6909 }
6910 }
6911 else
6912 {
6913 /* Handle relocs in data. */
6914 switch (fixP->fx_r_type)
6915 {
252b5132 6916 case BFD_RELOC_VTABLE_INHERIT:
94f592af
NC		 6917 if (fixP->fx_addsy
6918 && !S_IS_DEFINED (fixP->fx_addsy)
6919 && !S_IS_WEAK (fixP->fx_addsy))
6920 S_SET_WEAK (fixP->fx_addsy);
2b0f3761 6921 /* Fallthru */
252b5132
RH		 6922
6923 case BFD_RELOC_VTABLE_ENTRY:
94f592af 6924 fixP->fx_done = 0;
252b5132
RH		 6925 break;
6926
0baf16f2 6927#ifdef OBJ_ELF
3b8b57a9
AM		 6928 /* These can appear with @l etc. in data. */
6929 case BFD_RELOC_LO16:
3b8b57a9 6930 case BFD_RELOC_LO16_PCREL:
3b8b57a9 6931 case BFD_RELOC_HI16:
3b8b57a9 6932 case BFD_RELOC_HI16_PCREL:
3b8b57a9 6933 case BFD_RELOC_HI16_S:
3b8b57a9 6934 case BFD_RELOC_HI16_S_PCREL:
3b8b57a9 6935 case BFD_RELOC_PPC64_HIGHER:
3b8b57a9 6936 case BFD_RELOC_PPC64_HIGHER_S:
3b8b57a9 6937 case BFD_RELOC_PPC64_HIGHEST:
3b8b57a9 6938 case BFD_RELOC_PPC64_HIGHEST_S:
f9c6b907
AM		 6939 case BFD_RELOC_PPC64_ADDR16_HIGH:
6940 case BFD_RELOC_PPC64_ADDR16_HIGHA:
45965137 6941 case BFD_RELOC_PPC64_ADDR64_LOCAL:
3b8b57a9
AM		 6942 break;
6943
6944 case BFD_RELOC_PPC_DTPMOD:
6945 case BFD_RELOC_PPC_TPREL:
6946 case BFD_RELOC_PPC_DTPREL:
6947 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6948 break;
6949
6950 /* Just punt all of these to the linker. */
6951 case BFD_RELOC_PPC_B16_BRTAKEN:
6952 case BFD_RELOC_PPC_B16_BRNTAKEN:
6953 case BFD_RELOC_16_GOTOFF:
6954 case BFD_RELOC_LO16_GOTOFF:
6955 case BFD_RELOC_HI16_GOTOFF:
6956 case BFD_RELOC_HI16_S_GOTOFF:
6957 case BFD_RELOC_LO16_PLTOFF:
6958 case BFD_RELOC_HI16_PLTOFF:
6959 case BFD_RELOC_HI16_S_PLTOFF:
6960 case BFD_RELOC_PPC_COPY:
6961 case BFD_RELOC_PPC_GLOB_DAT:
6962 case BFD_RELOC_16_BASEREL:
6963 case BFD_RELOC_LO16_BASEREL:
6964 case BFD_RELOC_HI16_BASEREL:
6965 case BFD_RELOC_HI16_S_BASEREL:
6966 case BFD_RELOC_PPC_TLS:
6967 case BFD_RELOC_PPC_DTPREL16_LO:
6968 case BFD_RELOC_PPC_DTPREL16_HI:
6969 case BFD_RELOC_PPC_DTPREL16_HA:
6970 case BFD_RELOC_PPC_TPREL16_LO:
6971 case BFD_RELOC_PPC_TPREL16_HI:
6972 case BFD_RELOC_PPC_TPREL16_HA:
6973 case BFD_RELOC_PPC_GOT_TLSGD16:
6974 case BFD_RELOC_PPC_GOT_TLSGD16_LO:
6975 case BFD_RELOC_PPC_GOT_TLSGD16_HI:
6976 case BFD_RELOC_PPC_GOT_TLSGD16_HA:
6977 case BFD_RELOC_PPC_GOT_TLSLD16:
6978 case BFD_RELOC_PPC_GOT_TLSLD16_LO:
6979 case BFD_RELOC_PPC_GOT_TLSLD16_HI:
6980 case BFD_RELOC_PPC_GOT_TLSLD16_HA:
6981 case BFD_RELOC_PPC_GOT_DTPREL16:
6982 case BFD_RELOC_PPC_GOT_DTPREL16_LO:
6983 case BFD_RELOC_PPC_GOT_DTPREL16_HI:
6984 case BFD_RELOC_PPC_GOT_DTPREL16_HA:
6985 case BFD_RELOC_PPC_GOT_TPREL16:
6986 case BFD_RELOC_PPC_GOT_TPREL16_LO:
6987 case BFD_RELOC_PPC_GOT_TPREL16_HI:
6988 case BFD_RELOC_PPC_GOT_TPREL16_HA:
6989 case BFD_RELOC_24_PLT_PCREL:
6990 case BFD_RELOC_PPC_LOCAL24PC:
6991 case BFD_RELOC_32_PLT_PCREL:
6992 case BFD_RELOC_GPREL16:
6993 case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
6994 case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
6995 case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
6996 case BFD_RELOC_PPC_EMB_NADDR32:
6997 case BFD_RELOC_PPC_EMB_NADDR16:
6998 case BFD_RELOC_PPC_EMB_NADDR16_LO:
6999 case BFD_RELOC_PPC_EMB_NADDR16_HI:
7000 case BFD_RELOC_PPC_EMB_NADDR16_HA:
7001 case BFD_RELOC_PPC_EMB_SDAI16:
7002 case BFD_RELOC_PPC_EMB_SDA2REL:
7003 case BFD_RELOC_PPC_EMB_SDA2I16:
7004 case BFD_RELOC_PPC_EMB_SDA21:
7005 case BFD_RELOC_PPC_VLE_SDA21_LO:
7006 case BFD_RELOC_PPC_EMB_MRKREF:
7007 case BFD_RELOC_PPC_EMB_RELSEC16:
7008 case BFD_RELOC_PPC_EMB_RELST_LO:
7009 case BFD_RELOC_PPC_EMB_RELST_HI:
7010 case BFD_RELOC_PPC_EMB_RELST_HA:
7011 case BFD_RELOC_PPC_EMB_BIT_FLD:
7012 case BFD_RELOC_PPC_EMB_RELSDA:
0baf16f2 7013 case BFD_RELOC_PPC64_TOC:
3b8b57a9
AM		 7014 case BFD_RELOC_PPC_TOC16:
7015 case BFD_RELOC_PPC64_TOC16_LO:
7016 case BFD_RELOC_PPC64_TOC16_HI:
7017 case BFD_RELOC_PPC64_TOC16_HA:
f9c6b907
AM		 7018 case BFD_RELOC_PPC64_DTPREL16_HIGH:
7019 case BFD_RELOC_PPC64_DTPREL16_HIGHA:
3b8b57a9
AM		 7020 case BFD_RELOC_PPC64_DTPREL16_HIGHER:
7021 case BFD_RELOC_PPC64_DTPREL16_HIGHERA:
7022 case BFD_RELOC_PPC64_DTPREL16_HIGHEST:
7023 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA:
f9c6b907
AM		 7024 case BFD_RELOC_PPC64_TPREL16_HIGH:
7025 case BFD_RELOC_PPC64_TPREL16_HIGHA:
3b8b57a9
AM		 7026 case BFD_RELOC_PPC64_TPREL16_HIGHER:
7027 case BFD_RELOC_PPC64_TPREL16_HIGHERA:
7028 case BFD_RELOC_PPC64_TPREL16_HIGHEST:
7029 case BFD_RELOC_PPC64_TPREL16_HIGHESTA:
c213164a 7030 case BFD_RELOC_PPC64_TLS_PCREL:
94f592af 7031 fixP->fx_done = 0;
0baf16f2 7032 break;
0baf16f2 7033#endif
3b8b57a9
AM		 7034
7035#ifdef OBJ_XCOFF
7036 case BFD_RELOC_NONE:
3b8b57a9 7037#endif
5656a981
AM		 7038 case BFD_RELOC_CTOR:
7039 case BFD_RELOC_32:
7040 case BFD_RELOC_32_PCREL:
7041 case BFD_RELOC_RVA:
7042 case BFD_RELOC_64:
7043 case BFD_RELOC_64_PCREL:
7044 case BFD_RELOC_16:
7045 case BFD_RELOC_16_PCREL:
7046 case BFD_RELOC_8:
7047 break;
3b8b57a9 7048
252b5132 7049 default:
bc805888 7050 fprintf (stderr,
94f592af 7051 _("Gas failure, reloc value %d\n"), fixP->fx_r_type);
99a814a1 7052 fflush (stderr);
252b5132
RH		 7053 abort ();
7054 }
46b596ff 7055
5656a981 7056 if (fixP->fx_size && APPLY_RELOC)
46b596ff 7057 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
5656a981 7058 fieldval, fixP->fx_size);
bf7279d5
AM		 7059 if (warn_476
7060 && (seg->flags & SEC_CODE) != 0
7061 && fixP->fx_size == 4
7062 && fixP->fx_done
7063 && !fixP->fx_tcbit
7064 && (fixP->fx_r_type == BFD_RELOC_32
7065 || fixP->fx_r_type == BFD_RELOC_CTOR
7066 || fixP->fx_r_type == BFD_RELOC_32_PCREL))
7067 as_warn_where (fixP->fx_file, fixP->fx_line,
7068 _("data in executable section"));
5656a981
AM		 7069 }
7070
252b5132 7071#ifdef OBJ_ELF
3b8b57a9 7072 ppc_elf_validate_fix (fixP, seg);
94f592af 7073 fixP->fx_addnumber = value;
4e6935a6
AM		 7074
7075 /* PowerPC uses RELA relocs, ie. the reloc addend is stored separately
7076 from the section contents. If we are going to be emitting a reloc
7077 then the section contents are immaterial, so don't warn if they
7078 happen to overflow. Leave such warnings to ld. */
7079 if (!fixP->fx_done)
a38a07e0
AM		 7080 {
7081 fixP->fx_no_overflow = 1;
7082
7083 /* Arrange to emit .TOC. as a normal symbol if used in anything
7084 but .TOC.@tocbase. */
7085 if (ppc_obj64
7086 && fixP->fx_r_type != BFD_RELOC_PPC64_TOC
7087 && fixP->fx_addsy != NULL
7088 && strcmp (S_GET_NAME (fixP->fx_addsy), ".TOC.") == 0)
7089 symbol_get_bfdsym (fixP->fx_addsy)->flags |= BSF_KEEP;
7090 }
252b5132 7091#else
94f592af
NC		 7092 if (fixP->fx_r_type != BFD_RELOC_PPC_TOC16)
7093 fixP->fx_addnumber = 0;
252b5132
RH		 7094 else
7095 {
8edcbfcd
TG		 7096 /* We want to use the offset within the toc, not the actual VMA
7097 of the symbol. */
fd361982
AM		 7098 fixP->fx_addnumber = (- bfd_section_vma (S_GET_SEGMENT (fixP->fx_addsy))
7099 - S_GET_VALUE (ppc_toc_csect));
ac21e7da
TG		 7100 /* Set *valP to avoid errors. */
7101 *valP = value;
252b5132
RH		 7102 }
7103#endif
252b5132
RH		 7104}
7105
7106/* Generate a reloc for a fixup. */
7107
7108arelent *
98027b10 7109tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 7110{
7111 arelent *reloc;
7112
325801bd 7113 reloc = XNEW (arelent);
252b5132 7114
325801bd 7115 reloc->sym_ptr_ptr = XNEW (asymbol *);
49309057 7116 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132 7117 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
c213164a
AM		 7118 /* BFD_RELOC_PPC64_TLS_PCREL generates R_PPC64_TLS with an odd r_offset. */
7119 if (fixp->fx_r_type == BFD_RELOC_PPC64_TLS_PCREL)
7120 reloc->address++;
252b5132
RH		 7121 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
7122 if (reloc->howto == (reloc_howto_type *) NULL)
7123 {
7124 as_bad_where (fixp->fx_file, fixp->fx_line,
99a814a1
AM		 7125 _("reloc %d not supported by object file format"),
7126 (int) fixp->fx_r_type);
252b5132
RH		 7127 return NULL;
7128 }
7129 reloc->addend = fixp->fx_addnumber;
7130
7131 return reloc;
7132}
75e21f08
JJ		 7133
7134void
98027b10 7135ppc_cfi_frame_initial_instructions (void)
75e21f08
JJ		 7136{
7137 cfi_add_CFA_def_cfa (1, 0);
7138}
7139
7140int
1df69f4f 7141tc_ppc_regname_to_dw2regnum (char *regname)
75e21f08
JJ		 7142{
7143 unsigned int regnum = -1;
7144 unsigned int i;
7145 const char *p;
7146 char *q;
e0471c16 7147 static struct { const char *name; int dw2regnum; } regnames[] =
75e21f08
JJ		 7148 {
7149 { "sp", 1 }, { "r.sp", 1 }, { "rtoc", 2 }, { "r.toc", 2 },
7150 { "mq", 64 }, { "lr", 65 }, { "ctr", 66 }, { "ap", 67 },
80f846b6 7151 { "cr", 70 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 },
75e21f08
JJ		 7152 { "spe_acc", 111 }, { "spefscr", 112 }
7153 };
7154
7155 for (i = 0; i < ARRAY_SIZE (regnames); ++i)
7156 if (strcmp (regnames[i].name, regname) == 0)
7157 return regnames[i].dw2regnum;
7158
7159 if (regname[0] == 'r' || regname[0] == 'f' || regname[0] == 'v')
7160 {
7161 p = regname + 1 + (regname[1] == '.');
7162 regnum = strtoul (p, &q, 10);
7163 if (p == q || *q || regnum >= 32)
7164 return -1;
7165 if (regname[0] == 'f')
b7d7dc63 7166 regnum += 32;
75e21f08 7167 else if (regname[0] == 'v')
b7d7dc63 7168 regnum += 77;
75e21f08
JJ		 7169 }
7170 else if (regname[0] == 'c' && regname[1] == 'r')
7171 {
7172 p = regname + 2 + (regname[2] == '.');
7173 if (p[0] < '0' || p[0] > '7' || p[1])
b7d7dc63 7174 return -1;
75e21f08
JJ		 7175 regnum = p[0] - '0' + 68;
7176 }
7177 return regnum;
7178}
GDB Binutils - Deliverables
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