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e23eba97 | 1 | /* tc-riscv.c -- RISC-V assembler |
2571583a | 2 | Copyright (C) 2011-2017 Free Software Foundation, Inc. |
e23eba97 NC |
3 | |
4 | Contributed by Andrew Waterman (andrew@sifive.com). | |
5 | Based on MIPS target. | |
6 | ||
7 | This file is part of GAS. | |
8 | ||
9 | GAS is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GAS is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; see the file COPYING3. If not, | |
21 | see <http://www.gnu.org/licenses/>. */ | |
22 | ||
23 | #include "as.h" | |
24 | #include "config.h" | |
25 | #include "subsegs.h" | |
26 | #include "safe-ctype.h" | |
27 | ||
28 | #include "itbl-ops.h" | |
29 | #include "dwarf2dbg.h" | |
30 | #include "dw2gencfi.h" | |
1d65abb5 | 31 | #include "struc-symbol.h" |
e23eba97 NC |
32 | |
33 | #include "elf/riscv.h" | |
34 | #include "opcode/riscv.h" | |
35 | ||
36 | #include <stdint.h> | |
37 | ||
38 | /* Information about an instruction, including its format, operands | |
39 | and fixups. */ | |
40 | struct riscv_cl_insn | |
41 | { | |
42 | /* The opcode's entry in riscv_opcodes. */ | |
43 | const struct riscv_opcode *insn_mo; | |
44 | ||
45 | /* The encoded instruction bits. */ | |
46 | insn_t insn_opcode; | |
47 | ||
48 | /* The frag that contains the instruction. */ | |
49 | struct frag *frag; | |
50 | ||
51 | /* The offset into FRAG of the first instruction byte. */ | |
52 | long where; | |
53 | ||
54 | /* The relocs associated with the instruction, if any. */ | |
55 | fixS *fixp; | |
56 | }; | |
57 | ||
58 | #ifndef DEFAULT_ARCH | |
59 | #define DEFAULT_ARCH "riscv64" | |
60 | #endif | |
61 | ||
62 | static const char default_arch[] = DEFAULT_ARCH; | |
63 | ||
2922d21d AW |
64 | static unsigned xlen = 0; /* width of an x-register */ |
65 | static unsigned abi_xlen = 0; /* width of a pointer in the ABI */ | |
e23eba97 | 66 | |
2922d21d | 67 | #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw") |
e23eba97 NC |
68 | #define ADD32_INSN (xlen == 64 ? "addiw" : "addi") |
69 | ||
70 | static unsigned elf_flags = 0; | |
71 | ||
72 | /* This is the set of options which the .option pseudo-op may modify. */ | |
73 | ||
74 | struct riscv_set_options | |
75 | { | |
76 | int pic; /* Generate position-independent code. */ | |
77 | int rvc; /* Generate RVC code. */ | |
45f76423 | 78 | int relax; /* Emit relocs the linker is allowed to relax. */ |
e23eba97 NC |
79 | }; |
80 | ||
81 | static struct riscv_set_options riscv_opts = | |
82 | { | |
83 | 0, /* pic */ | |
84 | 0, /* rvc */ | |
45f76423 | 85 | 1, /* relax */ |
e23eba97 NC |
86 | }; |
87 | ||
88 | static void | |
89 | riscv_set_rvc (bfd_boolean rvc_value) | |
90 | { | |
91 | if (rvc_value) | |
92 | elf_flags |= EF_RISCV_RVC; | |
93 | ||
94 | riscv_opts.rvc = rvc_value; | |
95 | } | |
96 | ||
97 | struct riscv_subset | |
98 | { | |
99 | const char *name; | |
100 | ||
101 | struct riscv_subset *next; | |
102 | }; | |
103 | ||
104 | static struct riscv_subset *riscv_subsets; | |
105 | ||
106 | static bfd_boolean | |
107 | riscv_subset_supports (const char *feature) | |
108 | { | |
109 | struct riscv_subset *s; | |
110 | char *p; | |
111 | unsigned xlen_required = strtoul (feature, &p, 10); | |
112 | ||
113 | if (xlen_required && xlen != xlen_required) | |
114 | return FALSE; | |
115 | ||
116 | for (s = riscv_subsets; s != NULL; s = s->next) | |
117 | if (strcasecmp (s->name, p) == 0) | |
118 | return TRUE; | |
119 | ||
120 | return FALSE; | |
121 | } | |
122 | ||
123 | static void | |
124 | riscv_add_subset (const char *subset) | |
125 | { | |
126 | struct riscv_subset *s = xmalloc (sizeof *s); | |
127 | ||
128 | s->name = xstrdup (subset); | |
129 | s->next = riscv_subsets; | |
130 | riscv_subsets = s; | |
131 | } | |
132 | ||
2922d21d | 133 | /* Set which ISA and extensions are available. */ |
e23eba97 | 134 | |
e23eba97 | 135 | static void |
2922d21d | 136 | riscv_set_arch (const char *s) |
e23eba97 | 137 | { |
2922d21d | 138 | const char *all_subsets = "imafdc"; |
e23eba97 | 139 | const char *extension = NULL; |
2922d21d | 140 | const char *p = s; |
e23eba97 | 141 | |
2922d21d | 142 | if (strncmp (p, "rv32", 4) == 0) |
e23eba97 NC |
143 | { |
144 | xlen = 32; | |
145 | p += 4; | |
146 | } | |
2922d21d | 147 | else if (strncmp (p, "rv64", 4) == 0) |
e23eba97 NC |
148 | { |
149 | xlen = 64; | |
150 | p += 4; | |
151 | } | |
2922d21d AW |
152 | else |
153 | as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s); | |
e23eba97 | 154 | |
2922d21d | 155 | switch (*p) |
e23eba97 | 156 | { |
2922d21d | 157 | case 'i': |
e23eba97 NC |
158 | break; |
159 | ||
2922d21d | 160 | case 'g': |
e23eba97 | 161 | p++; |
2922d21d | 162 | for ( ; *all_subsets != 'c'; all_subsets++) |
e23eba97 | 163 | { |
2922d21d | 164 | const char subset[] = {*all_subsets, '\0'}; |
e23eba97 NC |
165 | riscv_add_subset (subset); |
166 | } | |
167 | break; | |
168 | ||
169 | default: | |
2922d21d | 170 | as_fatal ("-march=%s: first ISA subset must be `i' or `g'", s); |
e23eba97 NC |
171 | } |
172 | ||
173 | while (*p) | |
174 | { | |
2922d21d | 175 | if (*p == 'x') |
e23eba97 NC |
176 | { |
177 | char *subset = xstrdup (p), *q = subset; | |
178 | ||
179 | while (*++q != '\0' && *q != '_') | |
180 | ; | |
181 | *q = '\0'; | |
182 | ||
183 | if (extension) | |
2922d21d AW |
184 | as_fatal ("-march=%s: only one non-standard extension is supported" |
185 | " (found `%s' and `%s')", s, extension, subset); | |
e23eba97 NC |
186 | extension = subset; |
187 | riscv_add_subset (subset); | |
188 | p += strlen (subset); | |
189 | free (subset); | |
190 | } | |
191 | else if (*p == '_') | |
192 | p++; | |
193 | else if ((all_subsets = strchr (all_subsets, *p)) != NULL) | |
194 | { | |
195 | const char subset[] = {*p, 0}; | |
196 | riscv_add_subset (subset); | |
e23eba97 NC |
197 | all_subsets++; |
198 | p++; | |
199 | } | |
cc917fd9 KC |
200 | else if (*p == 'q') |
201 | { | |
202 | const char subset[] = {*p, 0}; | |
203 | riscv_add_subset (subset); | |
204 | p++; | |
205 | } | |
e23eba97 | 206 | else |
2922d21d | 207 | as_fatal ("-march=%s: unsupported ISA subset `%c'", s, *p); |
e23eba97 NC |
208 | } |
209 | } | |
210 | ||
211 | /* Handle of the OPCODE hash table. */ | |
212 | static struct hash_control *op_hash = NULL; | |
213 | ||
214 | /* This array holds the chars that always start a comment. If the | |
215 | pre-processor is disabled, these aren't very useful */ | |
216 | const char comment_chars[] = "#"; | |
217 | ||
218 | /* This array holds the chars that only start a comment at the beginning of | |
219 | a line. If the line seems to have the form '# 123 filename' | |
220 | .line and .file directives will appear in the pre-processed output */ | |
221 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
222 | first line of the input file. This is because the compiler outputs | |
223 | #NO_APP at the beginning of its output. */ | |
224 | /* Also note that C style comments are always supported. */ | |
225 | const char line_comment_chars[] = "#"; | |
226 | ||
227 | /* This array holds machine specific line separator characters. */ | |
228 | const char line_separator_chars[] = ";"; | |
229 | ||
230 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
231 | const char EXP_CHARS[] = "eE"; | |
232 | ||
233 | /* Chars that mean this number is a floating point constant */ | |
234 | /* As in 0f12.456 */ | |
235 | /* or 0d1.2345e12 */ | |
236 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
237 | ||
238 | /* Macros for encoding relaxation state for RVC branches and far jumps. */ | |
239 | #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \ | |
240 | ((relax_substateT) \ | |
241 | (0xc0000000 \ | |
242 | | ((uncond) ? 1 : 0) \ | |
243 | | ((rvc) ? 2 : 0) \ | |
244 | | ((length) << 2))) | |
245 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) | |
246 | #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF) | |
247 | #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0) | |
248 | #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0) | |
249 | ||
250 | /* Is the given value a sign-extended 32-bit value? */ | |
251 | #define IS_SEXT_32BIT_NUM(x) \ | |
252 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
253 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
254 | ||
255 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ | |
256 | #define IS_ZEXT_32BIT_NUM(x) \ | |
257 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
258 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
259 | ||
260 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
261 | INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */ | |
262 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
263 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
264 | ||
265 | /* Determine if an instruction matches an opcode. */ | |
266 | #define OPCODE_MATCHES(OPCODE, OP) \ | |
267 | (((OPCODE) & MASK_##OP) == MATCH_##OP) | |
268 | ||
269 | static char *expr_end; | |
270 | ||
271 | /* The default target format to use. */ | |
272 | ||
273 | const char * | |
274 | riscv_target_format (void) | |
275 | { | |
276 | return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; | |
277 | } | |
278 | ||
279 | /* Return the length of instruction INSN. */ | |
280 | ||
281 | static inline unsigned int | |
282 | insn_length (const struct riscv_cl_insn *insn) | |
283 | { | |
284 | return riscv_insn_length (insn->insn_opcode); | |
285 | } | |
286 | ||
287 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
288 | ||
289 | static void | |
290 | create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) | |
291 | { | |
292 | insn->insn_mo = mo; | |
293 | insn->insn_opcode = mo->match; | |
294 | insn->frag = NULL; | |
295 | insn->where = 0; | |
296 | insn->fixp = NULL; | |
297 | } | |
298 | ||
299 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
300 | ||
301 | static void | |
302 | install_insn (const struct riscv_cl_insn *insn) | |
303 | { | |
304 | char *f = insn->frag->fr_literal + insn->where; | |
305 | md_number_to_chars (f, insn->insn_opcode, insn_length (insn)); | |
306 | } | |
307 | ||
308 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
309 | and install the opcode in the new location. */ | |
310 | ||
311 | static void | |
312 | move_insn (struct riscv_cl_insn *insn, fragS *frag, long where) | |
313 | { | |
314 | insn->frag = frag; | |
315 | insn->where = where; | |
316 | if (insn->fixp != NULL) | |
317 | { | |
318 | insn->fixp->fx_frag = frag; | |
319 | insn->fixp->fx_where = where; | |
320 | } | |
321 | install_insn (insn); | |
322 | } | |
323 | ||
324 | /* Add INSN to the end of the output. */ | |
325 | ||
326 | static void | |
327 | add_fixed_insn (struct riscv_cl_insn *insn) | |
328 | { | |
329 | char *f = frag_more (insn_length (insn)); | |
330 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
331 | } | |
332 | ||
333 | static void | |
334 | add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var, | |
335 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
336 | { | |
337 | frag_grow (max_chars); | |
338 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
339 | frag_var (rs_machine_dependent, max_chars, var, | |
340 | subtype, symbol, offset, NULL); | |
341 | } | |
342 | ||
343 | /* Compute the length of a branch sequence, and adjust the stored length | |
344 | accordingly. If FRAGP is NULL, the worst-case length is returned. */ | |
345 | ||
346 | static unsigned | |
347 | relaxed_branch_length (fragS *fragp, asection *sec, int update) | |
348 | { | |
349 | int jump, rvc, length = 8; | |
350 | ||
351 | if (!fragp) | |
352 | return length; | |
353 | ||
354 | jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype); | |
355 | rvc = RELAX_BRANCH_RVC (fragp->fr_subtype); | |
356 | length = RELAX_BRANCH_LENGTH (fragp->fr_subtype); | |
357 | ||
358 | /* Assume jumps are in range; the linker will catch any that aren't. */ | |
359 | length = jump ? 4 : 8; | |
360 | ||
361 | if (fragp->fr_symbol != NULL | |
362 | && S_IS_DEFINED (fragp->fr_symbol) | |
01156111 | 363 | && !S_IS_WEAK (fragp->fr_symbol) |
e23eba97 NC |
364 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
365 | { | |
366 | offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
367 | bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH; | |
368 | val -= fragp->fr_address + fragp->fr_fix; | |
369 | ||
370 | if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range) | |
371 | length = 2; | |
372 | else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH) | |
373 | length = 4; | |
374 | else if (!jump && rvc) | |
375 | length = 6; | |
376 | } | |
377 | ||
378 | if (update) | |
379 | fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length); | |
380 | ||
381 | return length; | |
382 | } | |
383 | ||
384 | struct regname | |
385 | { | |
386 | const char *name; | |
387 | unsigned int num; | |
388 | }; | |
389 | ||
390 | enum reg_class | |
391 | { | |
392 | RCLASS_GPR, | |
393 | RCLASS_FPR, | |
394 | RCLASS_CSR, | |
395 | RCLASS_MAX | |
396 | }; | |
397 | ||
398 | static struct hash_control *reg_names_hash = NULL; | |
399 | ||
400 | #define ENCODE_REG_HASH(cls, n) \ | |
401 | ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1)) | |
402 | #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX) | |
403 | #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX) | |
404 | ||
405 | static void | |
406 | hash_reg_name (enum reg_class class, const char *name, unsigned n) | |
407 | { | |
408 | void *hash = ENCODE_REG_HASH (class, n); | |
409 | const char *retval = hash_insert (reg_names_hash, name, hash); | |
410 | ||
411 | if (retval != NULL) | |
412 | as_fatal (_("internal error: can't hash `%s': %s"), name, retval); | |
413 | } | |
414 | ||
415 | static void | |
416 | hash_reg_names (enum reg_class class, const char * const names[], unsigned n) | |
417 | { | |
418 | unsigned i; | |
419 | ||
420 | for (i = 0; i < n; i++) | |
421 | hash_reg_name (class, names[i], i); | |
422 | } | |
423 | ||
424 | static unsigned int | |
425 | reg_lookup_internal (const char *s, enum reg_class class) | |
426 | { | |
427 | struct regname *r = (struct regname *) hash_find (reg_names_hash, s); | |
428 | ||
429 | if (r == NULL || DECODE_REG_CLASS (r) != class) | |
430 | return -1; | |
431 | return DECODE_REG_NUM (r); | |
432 | } | |
433 | ||
434 | static bfd_boolean | |
435 | reg_lookup (char **s, enum reg_class class, unsigned int *regnop) | |
436 | { | |
437 | char *e; | |
438 | char save_c; | |
439 | int reg = -1; | |
440 | ||
441 | /* Find end of name. */ | |
442 | e = *s; | |
443 | if (is_name_beginner (*e)) | |
444 | ++e; | |
445 | while (is_part_of_name (*e)) | |
446 | ++e; | |
447 | ||
448 | /* Terminate name. */ | |
449 | save_c = *e; | |
450 | *e = '\0'; | |
451 | ||
452 | /* Look for the register. Advance to next token if one was recognized. */ | |
453 | if ((reg = reg_lookup_internal (*s, class)) >= 0) | |
454 | *s = e; | |
455 | ||
456 | *e = save_c; | |
457 | if (regnop) | |
458 | *regnop = reg; | |
459 | return reg >= 0; | |
460 | } | |
461 | ||
462 | static bfd_boolean | |
463 | arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) | |
464 | { | |
465 | const char *p = strchr (*s, ','); | |
466 | size_t i, len = p ? (size_t)(p - *s) : strlen (*s); | |
467 | ||
468 | for (i = 0; i < size; i++) | |
469 | if (array[i] != NULL && strncmp (array[i], *s, len) == 0) | |
470 | { | |
471 | *regnop = i; | |
472 | *s += len; | |
473 | return TRUE; | |
474 | } | |
475 | ||
476 | return FALSE; | |
477 | } | |
478 | ||
479 | /* For consistency checking, verify that all bits are specified either | |
480 | by the match/mask part of the instruction definition, or by the | |
481 | operand list. */ | |
482 | static bfd_boolean | |
483 | validate_riscv_insn (const struct riscv_opcode *opc) | |
484 | { | |
485 | const char *p = opc->args; | |
486 | char c; | |
487 | insn_t used_bits = opc->mask; | |
488 | int insn_width = 8 * riscv_insn_length (opc->match); | |
489 | insn_t required_bits = ~0ULL >> (64 - insn_width); | |
490 | ||
491 | if ((used_bits & opc->match) != (opc->match & required_bits)) | |
492 | { | |
493 | as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"), | |
494 | opc->name, opc->args); | |
495 | return FALSE; | |
496 | } | |
497 | ||
498 | #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) | |
499 | while (*p) | |
500 | switch (c = *p++) | |
501 | { | |
502 | case 'C': /* RVC */ | |
503 | switch (c = *p++) | |
504 | { | |
1d65abb5 | 505 | case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break; |
e23eba97 NC |
506 | case 'c': break; /* RS1, constrained to equal sp */ |
507 | case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break; | |
1d65abb5 AW |
508 | case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break; |
509 | case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break; | |
510 | case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break; | |
511 | case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break; | |
512 | case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break; | |
513 | case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break; | |
e23eba97 NC |
514 | case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; |
515 | case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; | |
1d65abb5 AW |
516 | case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break; |
517 | case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break; | |
e23eba97 NC |
518 | case 'w': break; /* RS1S, constrained to equal RD */ |
519 | case 'x': break; /* RS2S, constrained to equal RD */ | |
1d65abb5 AW |
520 | case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break; |
521 | case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break; | |
522 | case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break; | |
523 | case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break; | |
e23eba97 NC |
524 | case 'U': break; /* RS1, constrained to equal RD */ |
525 | case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; | |
1d65abb5 AW |
526 | case '<': used_bits |= ENCODE_RVC_IMM (-1U); break; |
527 | case '>': used_bits |= ENCODE_RVC_IMM (-1U); break; | |
e23eba97 NC |
528 | case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; |
529 | case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; | |
530 | default: | |
531 | as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"), | |
532 | c, opc->name, opc->args); | |
533 | return FALSE; | |
534 | } | |
535 | break; | |
536 | case ',': break; | |
537 | case '(': break; | |
538 | case ')': break; | |
539 | case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break; | |
540 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
541 | case 'A': break; | |
542 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
543 | case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
544 | case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; | |
545 | case 'I': break; | |
546 | case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; | |
547 | case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
548 | case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */ | |
549 | case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; | |
550 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
551 | case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; | |
552 | case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
553 | case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; | |
554 | case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; | |
555 | case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break; | |
556 | case 'o': | |
1d65abb5 AW |
557 | case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; |
558 | case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break; | |
559 | case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break; | |
560 | case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; | |
561 | case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; | |
e23eba97 NC |
562 | case '[': break; |
563 | case ']': break; | |
564 | case '0': break; | |
565 | default: | |
566 | as_bad (_("internal: bad RISC-V opcode " | |
567 | "(unknown operand type `%c'): %s %s"), | |
568 | c, opc->name, opc->args); | |
569 | return FALSE; | |
570 | } | |
571 | #undef USE_BITS | |
572 | if (used_bits != required_bits) | |
573 | { | |
574 | as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"), | |
575 | ~(unsigned long)(used_bits & required_bits), | |
576 | opc->name, opc->args); | |
577 | return FALSE; | |
578 | } | |
579 | return TRUE; | |
580 | } | |
581 | ||
582 | struct percent_op_match | |
583 | { | |
584 | const char *str; | |
585 | bfd_reloc_code_real_type reloc; | |
586 | }; | |
587 | ||
588 | /* This function is called once, at assembler startup time. It should set up | |
589 | all the tables, etc. that the MD part of the assembler will need. */ | |
590 | ||
591 | void | |
592 | md_begin (void) | |
593 | { | |
594 | int i = 0; | |
2922d21d | 595 | unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; |
e23eba97 | 596 | |
2922d21d | 597 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) |
e23eba97 NC |
598 | as_warn (_("Could not set architecture and machine")); |
599 | ||
600 | op_hash = hash_new (); | |
601 | ||
602 | while (riscv_opcodes[i].name) | |
603 | { | |
604 | const char *name = riscv_opcodes[i].name; | |
605 | const char *hash_error = | |
606 | hash_insert (op_hash, name, (void *) &riscv_opcodes[i]); | |
607 | ||
608 | if (hash_error) | |
609 | { | |
610 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
611 | riscv_opcodes[i].name, hash_error); | |
612 | /* Probably a memory allocation problem? Give up now. */ | |
613 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
614 | } | |
615 | ||
616 | do | |
617 | { | |
618 | if (riscv_opcodes[i].pinfo != INSN_MACRO) | |
619 | { | |
620 | if (!validate_riscv_insn (&riscv_opcodes[i])) | |
621 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
622 | } | |
623 | ++i; | |
624 | } | |
625 | while (riscv_opcodes[i].name && !strcmp (riscv_opcodes[i].name, name)); | |
626 | } | |
627 | ||
628 | reg_names_hash = hash_new (); | |
629 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR); | |
630 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR); | |
631 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR); | |
632 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); | |
633 | ||
634 | #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num); | |
635 | #include "opcode/riscv-opc.h" | |
636 | #undef DECLARE_CSR | |
637 | ||
638 | /* Set the default alignment for the text section. */ | |
639 | record_alignment (text_section, riscv_opts.rvc ? 1 : 2); | |
640 | } | |
641 | ||
45f76423 AW |
642 | static insn_t |
643 | riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value) | |
644 | { | |
645 | switch (reloc_type) | |
646 | { | |
647 | case BFD_RELOC_32: | |
648 | return value; | |
649 | ||
650 | case BFD_RELOC_RISCV_HI20: | |
651 | return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)); | |
652 | ||
653 | case BFD_RELOC_RISCV_LO12_S: | |
654 | return ENCODE_STYPE_IMM (value); | |
655 | ||
656 | case BFD_RELOC_RISCV_LO12_I: | |
657 | return ENCODE_ITYPE_IMM (value); | |
658 | ||
659 | default: | |
660 | abort (); | |
661 | } | |
662 | } | |
663 | ||
e23eba97 NC |
664 | /* Output an instruction. IP is the instruction information. |
665 | ADDRESS_EXPR is an operand of the instruction to be used with | |
666 | RELOC_TYPE. */ | |
667 | ||
668 | static void | |
669 | append_insn (struct riscv_cl_insn *ip, expressionS *address_expr, | |
670 | bfd_reloc_code_real_type reloc_type) | |
671 | { | |
672 | dwarf2_emit_insn (0); | |
673 | ||
674 | if (reloc_type != BFD_RELOC_UNUSED) | |
675 | { | |
676 | reloc_howto_type *howto; | |
677 | ||
1d65abb5 | 678 | gas_assert (address_expr); |
e23eba97 NC |
679 | if (reloc_type == BFD_RELOC_12_PCREL |
680 | || reloc_type == BFD_RELOC_RISCV_JMP) | |
681 | { | |
682 | int j = reloc_type == BFD_RELOC_RISCV_JMP; | |
683 | int best_case = riscv_insn_length (ip->insn_opcode); | |
684 | unsigned worst_case = relaxed_branch_length (NULL, NULL, 0); | |
685 | add_relaxed_insn (ip, worst_case, best_case, | |
686 | RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case), | |
687 | address_expr->X_add_symbol, | |
688 | address_expr->X_add_number); | |
689 | return; | |
690 | } | |
45f76423 | 691 | else |
e23eba97 | 692 | { |
45f76423 AW |
693 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type); |
694 | if (howto == NULL) | |
695 | as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type); | |
e23eba97 | 696 | |
45f76423 AW |
697 | ip->fixp = fix_new_exp (ip->frag, ip->where, |
698 | bfd_get_reloc_size (howto), | |
699 | address_expr, FALSE, reloc_type); | |
e23eba97 | 700 | |
45f76423 | 701 | ip->fixp->fx_tcbit = riscv_opts.relax; |
e23eba97 | 702 | } |
e23eba97 NC |
703 | } |
704 | ||
e23eba97 NC |
705 | add_fixed_insn (ip); |
706 | install_insn (ip); | |
707 | } | |
708 | ||
709 | /* Build an instruction created by a macro expansion. This is passed | |
710 | a pointer to the count of instructions created so far, an | |
711 | expression, the name of the instruction to build, an operand format | |
712 | string, and corresponding arguments. */ | |
713 | ||
714 | static void | |
715 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) | |
716 | { | |
717 | const struct riscv_opcode *mo; | |
718 | struct riscv_cl_insn insn; | |
719 | bfd_reloc_code_real_type r; | |
720 | va_list args; | |
721 | ||
722 | va_start (args, fmt); | |
723 | ||
724 | r = BFD_RELOC_UNUSED; | |
725 | mo = (struct riscv_opcode *) hash_find (op_hash, name); | |
726 | gas_assert (mo); | |
727 | ||
728 | /* Find a non-RVC variant of the instruction. append_insn will compress | |
729 | it if possible. */ | |
730 | while (riscv_insn_length (mo->match) < 4) | |
731 | mo++; | |
732 | gas_assert (strcmp (name, mo->name) == 0); | |
733 | ||
734 | create_insn (&insn, mo); | |
735 | for (;;) | |
736 | { | |
737 | switch (*fmt++) | |
738 | { | |
739 | case 'd': | |
740 | INSERT_OPERAND (RD, insn, va_arg (args, int)); | |
741 | continue; | |
742 | ||
743 | case 's': | |
744 | INSERT_OPERAND (RS1, insn, va_arg (args, int)); | |
745 | continue; | |
746 | ||
747 | case 't': | |
748 | INSERT_OPERAND (RS2, insn, va_arg (args, int)); | |
749 | continue; | |
750 | ||
751 | case '>': | |
752 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); | |
753 | continue; | |
754 | ||
755 | case 'j': | |
756 | case 'u': | |
757 | case 'q': | |
758 | gas_assert (ep != NULL); | |
759 | r = va_arg (args, int); | |
760 | continue; | |
761 | ||
762 | case '\0': | |
763 | break; | |
764 | case ',': | |
765 | continue; | |
766 | default: | |
767 | as_fatal (_("internal error: invalid macro")); | |
768 | } | |
769 | break; | |
770 | } | |
771 | va_end (args); | |
772 | gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
773 | ||
774 | append_insn (&insn, ep, r); | |
775 | } | |
776 | ||
777 | /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits | |
778 | unset. */ | |
779 | static void | |
780 | normalize_constant_expr (expressionS *ex) | |
781 | { | |
782 | if (xlen > 32) | |
783 | return; | |
784 | if ((ex->X_op == O_constant || ex->X_op == O_symbol) | |
785 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
786 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
787 | - 0x80000000); | |
788 | } | |
789 | ||
790 | /* Fail if an expression is not a constant. */ | |
791 | ||
792 | static void | |
793 | check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex) | |
794 | { | |
795 | if (ex->X_op == O_big) | |
796 | as_bad (_("unsupported large constant")); | |
797 | else if (ex->X_op != O_constant) | |
798 | as_bad (_("Instruction %s requires absolute expression"), | |
799 | ip->insn_mo->name); | |
800 | normalize_constant_expr (ex); | |
801 | } | |
802 | ||
803 | static symbolS * | |
804 | make_internal_label (void) | |
805 | { | |
806 | return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, | |
1d65abb5 | 807 | (valueT) frag_now_fix (), frag_now); |
e23eba97 NC |
808 | } |
809 | ||
810 | /* Load an entry from the GOT. */ | |
811 | static void | |
812 | pcrel_access (int destreg, int tempreg, expressionS *ep, | |
813 | const char *lo_insn, const char *lo_pattern, | |
814 | bfd_reloc_code_real_type hi_reloc, | |
815 | bfd_reloc_code_real_type lo_reloc) | |
816 | { | |
817 | expressionS ep2; | |
818 | ep2.X_op = O_symbol; | |
819 | ep2.X_add_symbol = make_internal_label (); | |
820 | ep2.X_add_number = 0; | |
821 | ||
822 | macro_build (ep, "auipc", "d,u", tempreg, hi_reloc); | |
823 | macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc); | |
824 | } | |
825 | ||
826 | static void | |
827 | pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn, | |
828 | bfd_reloc_code_real_type hi_reloc, | |
829 | bfd_reloc_code_real_type lo_reloc) | |
830 | { | |
831 | pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc); | |
832 | } | |
833 | ||
834 | static void | |
835 | pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn, | |
836 | bfd_reloc_code_real_type hi_reloc, | |
837 | bfd_reloc_code_real_type lo_reloc) | |
838 | { | |
839 | pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc); | |
840 | } | |
841 | ||
842 | /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */ | |
843 | static void | |
844 | riscv_call (int destreg, int tempreg, expressionS *ep, | |
845 | bfd_reloc_code_real_type reloc) | |
846 | { | |
847 | macro_build (ep, "auipc", "d,u", tempreg, reloc); | |
848 | macro_build (NULL, "jalr", "d,s", destreg, tempreg); | |
849 | } | |
850 | ||
851 | /* Load an integer constant into a register. */ | |
852 | ||
853 | static void | |
854 | load_const (int reg, expressionS *ep) | |
855 | { | |
856 | int shift = RISCV_IMM_BITS; | |
857 | expressionS upper = *ep, lower = *ep; | |
858 | lower.X_add_number = (int32_t) ep->X_add_number << (32-shift) >> (32-shift); | |
859 | upper.X_add_number -= lower.X_add_number; | |
860 | ||
861 | if (ep->X_op != O_constant) | |
862 | { | |
863 | as_bad (_("unsupported large constant")); | |
864 | return; | |
865 | } | |
866 | ||
1d65abb5 | 867 | if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number)) |
e23eba97 NC |
868 | { |
869 | /* Reduce to a signed 32-bit constant using SLLI and ADDI. */ | |
870 | while (((upper.X_add_number >> shift) & 1) == 0) | |
871 | shift++; | |
872 | ||
873 | upper.X_add_number = (int64_t) upper.X_add_number >> shift; | |
1d65abb5 | 874 | load_const (reg, &upper); |
e23eba97 NC |
875 | |
876 | macro_build (NULL, "slli", "d,s,>", reg, reg, shift); | |
877 | if (lower.X_add_number != 0) | |
878 | macro_build (&lower, "addi", "d,s,j", reg, reg, BFD_RELOC_RISCV_LO12_I); | |
879 | } | |
880 | else | |
881 | { | |
882 | /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */ | |
883 | int hi_reg = 0; | |
884 | ||
885 | if (upper.X_add_number != 0) | |
886 | { | |
887 | macro_build (ep, "lui", "d,u", reg, BFD_RELOC_RISCV_HI20); | |
888 | hi_reg = reg; | |
889 | } | |
890 | ||
891 | if (lower.X_add_number != 0 || hi_reg == 0) | |
892 | macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg, | |
893 | BFD_RELOC_RISCV_LO12_I); | |
894 | } | |
895 | } | |
896 | ||
897 | /* Expand RISC-V assembly macros into one or more instructions. */ | |
898 | static void | |
899 | macro (struct riscv_cl_insn *ip, expressionS *imm_expr, | |
900 | bfd_reloc_code_real_type *imm_reloc) | |
901 | { | |
902 | int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD; | |
903 | int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1; | |
904 | int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; | |
905 | int mask = ip->insn_mo->mask; | |
906 | ||
907 | switch (mask) | |
908 | { | |
909 | case M_LI: | |
910 | load_const (rd, imm_expr); | |
911 | break; | |
912 | ||
913 | case M_LA: | |
914 | case M_LLA: | |
915 | /* Load the address of a symbol into a register. */ | |
916 | if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number)) | |
917 | as_bad (_("offset too large")); | |
918 | ||
919 | if (imm_expr->X_op == O_constant) | |
920 | load_const (rd, imm_expr); | |
921 | else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */ | |
922 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, | |
923 | BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
924 | else /* Local PIC symbol, or any non-PIC symbol */ | |
925 | pcrel_load (rd, rd, imm_expr, "addi", | |
926 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
927 | break; | |
928 | ||
929 | case M_LA_TLS_GD: | |
930 | pcrel_load (rd, rd, imm_expr, "addi", | |
931 | BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
932 | break; | |
933 | ||
934 | case M_LA_TLS_IE: | |
935 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, | |
936 | BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
937 | break; | |
938 | ||
939 | case M_LB: | |
940 | pcrel_load (rd, rd, imm_expr, "lb", | |
941 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
942 | break; | |
943 | ||
944 | case M_LBU: | |
945 | pcrel_load (rd, rd, imm_expr, "lbu", | |
946 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
947 | break; | |
948 | ||
949 | case M_LH: | |
950 | pcrel_load (rd, rd, imm_expr, "lh", | |
951 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
952 | break; | |
953 | ||
954 | case M_LHU: | |
955 | pcrel_load (rd, rd, imm_expr, "lhu", | |
956 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
957 | break; | |
958 | ||
959 | case M_LW: | |
960 | pcrel_load (rd, rd, imm_expr, "lw", | |
961 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
962 | break; | |
963 | ||
964 | case M_LWU: | |
965 | pcrel_load (rd, rd, imm_expr, "lwu", | |
966 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
967 | break; | |
968 | ||
969 | case M_LD: | |
970 | pcrel_load (rd, rd, imm_expr, "ld", | |
971 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
972 | break; | |
973 | ||
974 | case M_FLW: | |
975 | pcrel_load (rd, rs1, imm_expr, "flw", | |
976 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
977 | break; | |
978 | ||
979 | case M_FLD: | |
980 | pcrel_load (rd, rs1, imm_expr, "fld", | |
981 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
982 | break; | |
983 | ||
984 | case M_SB: | |
985 | pcrel_store (rs2, rs1, imm_expr, "sb", | |
986 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
987 | break; | |
988 | ||
989 | case M_SH: | |
990 | pcrel_store (rs2, rs1, imm_expr, "sh", | |
991 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
992 | break; | |
993 | ||
994 | case M_SW: | |
995 | pcrel_store (rs2, rs1, imm_expr, "sw", | |
996 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
997 | break; | |
998 | ||
999 | case M_SD: | |
1000 | pcrel_store (rs2, rs1, imm_expr, "sd", | |
1001 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1002 | break; | |
1003 | ||
1004 | case M_FSW: | |
1005 | pcrel_store (rs2, rs1, imm_expr, "fsw", | |
1006 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1007 | break; | |
1008 | ||
1009 | case M_FSD: | |
1010 | pcrel_store (rs2, rs1, imm_expr, "fsd", | |
1011 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1012 | break; | |
1013 | ||
1014 | case M_CALL: | |
1015 | riscv_call (rd, rs1, imm_expr, *imm_reloc); | |
1016 | break; | |
1017 | ||
1018 | default: | |
1019 | as_bad (_("Macro %s not implemented"), ip->insn_mo->name); | |
1020 | break; | |
1021 | } | |
1022 | } | |
1023 | ||
1024 | static const struct percent_op_match percent_op_utype[] = | |
1025 | { | |
1026 | {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, | |
1027 | {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, | |
1028 | {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, | |
1029 | {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, | |
1030 | {"%hi", BFD_RELOC_RISCV_HI20}, | |
1031 | {0, 0} | |
1032 | }; | |
1033 | ||
1034 | static const struct percent_op_match percent_op_itype[] = | |
1035 | { | |
1036 | {"%lo", BFD_RELOC_RISCV_LO12_I}, | |
1037 | {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, | |
1038 | {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, | |
1039 | {0, 0} | |
1040 | }; | |
1041 | ||
1042 | static const struct percent_op_match percent_op_stype[] = | |
1043 | { | |
1044 | {"%lo", BFD_RELOC_RISCV_LO12_S}, | |
1045 | {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S}, | |
1046 | {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S}, | |
1047 | {0, 0} | |
1048 | }; | |
1049 | ||
1050 | static const struct percent_op_match percent_op_rtype[] = | |
1051 | { | |
1052 | {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, | |
1053 | {0, 0} | |
1054 | }; | |
1055 | ||
1056 | /* Return true if *STR points to a relocation operator. When returning true, | |
1057 | move *STR over the operator and store its relocation code in *RELOC. | |
1058 | Leave both *STR and *RELOC alone when returning false. */ | |
1059 | ||
1060 | static bfd_boolean | |
1061 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc, | |
1062 | const struct percent_op_match *percent_op) | |
1063 | { | |
1064 | for ( ; percent_op->str; percent_op++) | |
1065 | if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0) | |
1066 | { | |
1067 | int len = strlen (percent_op->str); | |
1068 | ||
1069 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
1070 | continue; | |
1071 | ||
1072 | *str += strlen (percent_op->str); | |
1073 | *reloc = percent_op->reloc; | |
1074 | ||
1075 | /* Check whether the output BFD supports this relocation. | |
1076 | If not, issue an error and fall back on something safe. */ | |
45f76423 AW |
1077 | if (*reloc != BFD_RELOC_UNUSED |
1078 | && !bfd_reloc_type_lookup (stdoutput, *reloc)) | |
e23eba97 NC |
1079 | { |
1080 | as_bad ("relocation %s isn't supported by the current ABI", | |
1081 | percent_op->str); | |
1082 | *reloc = BFD_RELOC_UNUSED; | |
1083 | } | |
1084 | return TRUE; | |
1085 | } | |
1086 | return FALSE; | |
1087 | } | |
1088 | ||
1089 | static void | |
1090 | my_getExpression (expressionS *ep, char *str) | |
1091 | { | |
1092 | char *save_in; | |
1093 | ||
1094 | save_in = input_line_pointer; | |
1095 | input_line_pointer = str; | |
1096 | expression (ep); | |
1097 | expr_end = input_line_pointer; | |
1098 | input_line_pointer = save_in; | |
1099 | } | |
1100 | ||
1101 | /* Parse string STR as a 16-bit relocatable operand. Store the | |
1102 | expression in *EP and the relocation, if any, in RELOC. | |
1103 | Return the number of relocation operators used (0 or 1). | |
1104 | ||
1105 | On exit, EXPR_END points to the first character after the expression. */ | |
1106 | ||
1107 | static size_t | |
1108 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, | |
1109 | char *str, const struct percent_op_match *percent_op) | |
1110 | { | |
1111 | size_t reloc_index; | |
1112 | unsigned crux_depth, str_depth, regno; | |
1113 | char *crux; | |
1114 | ||
1115 | /* First, check for integer registers. */ | |
1116 | if (reg_lookup (&str, RCLASS_GPR, ®no)) | |
1117 | { | |
1118 | ep->X_op = O_register; | |
1119 | ep->X_add_number = regno; | |
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | /* Search for the start of the main expression. | |
1124 | End the loop with CRUX pointing to the start | |
1125 | of the main expression and with CRUX_DEPTH containing the number | |
1126 | of open brackets at that point. */ | |
1127 | reloc_index = -1; | |
1128 | str_depth = 0; | |
1129 | do | |
1130 | { | |
1131 | reloc_index++; | |
1132 | crux = str; | |
1133 | crux_depth = str_depth; | |
1134 | ||
1135 | /* Skip over whitespace and brackets, keeping count of the number | |
1136 | of brackets. */ | |
1137 | while (*str == ' ' || *str == '\t' || *str == '(') | |
1138 | if (*str++ == '(') | |
1139 | str_depth++; | |
1140 | } | |
1141 | while (*str == '%' | |
1142 | && reloc_index < 1 | |
1143 | && parse_relocation (&str, reloc, percent_op)); | |
1144 | ||
1145 | my_getExpression (ep, crux); | |
1146 | str = expr_end; | |
1147 | ||
1148 | /* Match every open bracket. */ | |
1149 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) | |
1150 | if (*str++ == ')') | |
1151 | crux_depth--; | |
1152 | ||
1153 | if (crux_depth > 0) | |
1154 | as_bad ("unclosed '('"); | |
1155 | ||
1156 | expr_end = str; | |
1157 | ||
1158 | return reloc_index; | |
1159 | } | |
1160 | ||
1161 | /* This routine assembles an instruction into its binary format. As a | |
1162 | side effect, it sets the global variable imm_reloc to the type of | |
1163 | relocation to do if one of the operands is an address expression. */ | |
1164 | ||
1165 | static const char * | |
1166 | riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, | |
1167 | bfd_reloc_code_real_type *imm_reloc) | |
1168 | { | |
1169 | char *s; | |
1170 | const char *args; | |
1171 | char c = 0; | |
1172 | struct riscv_opcode *insn; | |
1173 | char *argsStart; | |
1174 | unsigned int regno; | |
1175 | char save_c = 0; | |
1176 | int argnum; | |
1177 | const struct percent_op_match *p; | |
1178 | const char *error = "unrecognized opcode"; | |
1179 | ||
1180 | /* Parse the name of the instruction. Terminate the string if whitespace | |
1181 | is found so that hash_find only sees the name part of the string. */ | |
1182 | for (s = str; *s != '\0'; ++s) | |
1183 | if (ISSPACE (*s)) | |
1184 | { | |
1185 | save_c = *s; | |
1186 | *s++ = '\0'; | |
1187 | break; | |
1188 | } | |
1189 | ||
1190 | insn = (struct riscv_opcode *) hash_find (op_hash, str); | |
1191 | ||
1192 | argsStart = s; | |
1193 | for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++) | |
1194 | { | |
1195 | if (!riscv_subset_supports (insn->subset)) | |
1196 | continue; | |
1197 | ||
1198 | create_insn (ip, insn); | |
1199 | argnum = 1; | |
1200 | ||
1201 | imm_expr->X_op = O_absent; | |
1202 | *imm_reloc = BFD_RELOC_UNUSED; | |
1203 | p = percent_op_itype; | |
1204 | ||
1205 | for (args = insn->args;; ++args) | |
1206 | { | |
1207 | s += strspn (s, " \t"); | |
1208 | switch (*args) | |
1209 | { | |
1210 | case '\0': /* End of args. */ | |
1211 | if (insn->pinfo != INSN_MACRO) | |
1212 | { | |
1213 | if (!insn->match_func (insn, ip->insn_opcode)) | |
1214 | break; | |
1215 | if (riscv_insn_length (insn->match) == 2 && !riscv_opts.rvc) | |
1216 | break; | |
1217 | } | |
1218 | if (*s != '\0') | |
1219 | break; | |
1220 | /* Successful assembly. */ | |
1221 | error = NULL; | |
1222 | goto out; | |
1223 | ||
1224 | case 'C': /* RVC */ | |
1225 | switch (*++args) | |
1226 | { | |
1227 | case 's': /* RS1 x8-x15 */ | |
1228 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1229 | || !(regno >= 8 && regno <= 15)) | |
1230 | break; | |
1231 | INSERT_OPERAND (CRS1S, *ip, regno % 8); | |
1232 | continue; | |
1233 | case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */ | |
1234 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1235 | || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno) | |
1236 | break; | |
1237 | continue; | |
1238 | case 't': /* RS2 x8-x15 */ | |
1239 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1240 | || !(regno >= 8 && regno <= 15)) | |
1241 | break; | |
1242 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
1243 | continue; | |
1244 | case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */ | |
1245 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1246 | || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno) | |
1247 | break; | |
1248 | continue; | |
1249 | case 'U': /* RS1, constrained to equal RD. */ | |
1250 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1251 | || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno) | |
1252 | break; | |
1253 | continue; | |
1254 | case 'V': /* RS2 */ | |
1255 | if (!reg_lookup (&s, RCLASS_GPR, ®no)) | |
1256 | break; | |
1257 | INSERT_OPERAND (CRS2, *ip, regno); | |
1258 | continue; | |
1259 | case 'c': /* RS1, constrained to equal sp. */ | |
1260 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1261 | || regno != X_SP) | |
1262 | break; | |
1263 | continue; | |
1264 | case '>': | |
1265 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1266 | || imm_expr->X_op != O_constant | |
1267 | || imm_expr->X_add_number <= 0 | |
1268 | || imm_expr->X_add_number >= 64) | |
1269 | break; | |
1270 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1271 | rvc_imm_done: | |
1272 | s = expr_end; | |
1273 | imm_expr->X_op = O_absent; | |
1274 | continue; | |
1275 | case '<': | |
1276 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1277 | || imm_expr->X_op != O_constant | |
1278 | || !VALID_RVC_IMM (imm_expr->X_add_number) | |
1279 | || imm_expr->X_add_number <= 0 | |
1280 | || imm_expr->X_add_number >= 32) | |
1281 | break; | |
1282 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1283 | goto rvc_imm_done; | |
1284 | case 'i': | |
1285 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1286 | || imm_expr->X_op != O_constant | |
1287 | || imm_expr->X_add_number == 0 | |
1288 | || !VALID_RVC_SIMM3 (imm_expr->X_add_number)) | |
1289 | break; | |
1290 | ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number); | |
1291 | goto rvc_imm_done; | |
1292 | case 'j': | |
1293 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1294 | || imm_expr->X_op != O_constant | |
1295 | || imm_expr->X_add_number == 0 | |
1296 | || !VALID_RVC_IMM (imm_expr->X_add_number)) | |
1297 | break; | |
1298 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1299 | goto rvc_imm_done; | |
1300 | case 'k': | |
1301 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1302 | || imm_expr->X_op != O_constant | |
1303 | || !VALID_RVC_LW_IMM (imm_expr->X_add_number)) | |
1304 | break; | |
1305 | ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number); | |
1306 | goto rvc_imm_done; | |
1307 | case 'l': | |
1308 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1309 | || imm_expr->X_op != O_constant | |
1310 | || !VALID_RVC_LD_IMM (imm_expr->X_add_number)) | |
1311 | break; | |
1312 | ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number); | |
1313 | goto rvc_imm_done; | |
1314 | case 'm': | |
1315 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1316 | || imm_expr->X_op != O_constant | |
1317 | || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number)) | |
1318 | break; | |
1319 | ip->insn_opcode |= | |
1320 | ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number); | |
1321 | goto rvc_imm_done; | |
1322 | case 'n': | |
1323 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1324 | || imm_expr->X_op != O_constant | |
1325 | || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number)) | |
1326 | break; | |
1327 | ip->insn_opcode |= | |
1328 | ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number); | |
1329 | goto rvc_imm_done; | |
1330 | case 'K': | |
1331 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1332 | || imm_expr->X_op != O_constant | |
1333 | || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number) | |
1334 | || imm_expr->X_add_number == 0) | |
1335 | break; | |
1336 | ip->insn_opcode |= | |
1337 | ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number); | |
1338 | goto rvc_imm_done; | |
1339 | case 'L': | |
1340 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1341 | || imm_expr->X_op != O_constant | |
1342 | || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number) | |
1343 | || imm_expr->X_add_number == 0) | |
1344 | break; | |
1345 | ip->insn_opcode |= | |
1346 | ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number); | |
1347 | goto rvc_imm_done; | |
1348 | case 'M': | |
1349 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1350 | || imm_expr->X_op != O_constant | |
1351 | || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number)) | |
1352 | break; | |
1353 | ip->insn_opcode |= | |
1354 | ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number); | |
1355 | goto rvc_imm_done; | |
1356 | case 'N': | |
1357 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1358 | || imm_expr->X_op != O_constant | |
1359 | || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number)) | |
1360 | break; | |
1361 | ip->insn_opcode |= | |
1362 | ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number); | |
1363 | goto rvc_imm_done; | |
1364 | case 'u': | |
1365 | p = percent_op_utype; | |
1366 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p)) | |
1367 | break; | |
1368 | rvc_lui: | |
1369 | if (imm_expr->X_op != O_constant | |
1370 | || imm_expr->X_add_number <= 0 | |
1371 | || imm_expr->X_add_number >= RISCV_BIGIMM_REACH | |
1372 | || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2 | |
1373 | && (imm_expr->X_add_number < | |
1374 | RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2))) | |
1375 | break; | |
1376 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1377 | goto rvc_imm_done; | |
1378 | case 'v': | |
1379 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1380 | || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1)) | |
1381 | || ((int32_t)imm_expr->X_add_number | |
1382 | != imm_expr->X_add_number)) | |
1383 | break; | |
1384 | imm_expr->X_add_number = | |
1385 | ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS; | |
1386 | goto rvc_lui; | |
1387 | case 'p': | |
1388 | goto branch; | |
1389 | case 'a': | |
1390 | goto jump; | |
1391 | case 'D': /* Floating-point RS2 x8-x15. */ | |
1392 | if (!reg_lookup (&s, RCLASS_FPR, ®no) | |
1393 | || !(regno >= 8 && regno <= 15)) | |
1394 | break; | |
1395 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
1396 | continue; | |
1397 | case 'T': /* Floating-point RS2. */ | |
1398 | if (!reg_lookup (&s, RCLASS_FPR, ®no)) | |
1399 | break; | |
1400 | INSERT_OPERAND (CRS2, *ip, regno); | |
1401 | continue; | |
1402 | default: | |
1403 | as_bad (_("bad RVC field specifier 'C%c'\n"), *args); | |
1404 | } | |
1405 | break; | |
1406 | ||
1407 | case ',': | |
1408 | ++argnum; | |
1409 | if (*s++ == *args) | |
1410 | continue; | |
1411 | s--; | |
1412 | break; | |
1413 | ||
1414 | case '(': | |
1415 | case ')': | |
1416 | case '[': | |
1417 | case ']': | |
1418 | if (*s++ == *args) | |
1419 | continue; | |
1420 | break; | |
1421 | ||
1422 | case '<': /* Shift amount, 0 - 31. */ | |
1423 | my_getExpression (imm_expr, s); | |
1424 | check_absolute_expr (ip, imm_expr); | |
1425 | if ((unsigned long) imm_expr->X_add_number > 31) | |
1426 | as_warn (_("Improper shift amount (%lu)"), | |
1427 | (unsigned long) imm_expr->X_add_number); | |
1428 | INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number); | |
1429 | imm_expr->X_op = O_absent; | |
1430 | s = expr_end; | |
1431 | continue; | |
1432 | ||
1433 | case '>': /* Shift amount, 0 - (XLEN-1). */ | |
1434 | my_getExpression (imm_expr, s); | |
1435 | check_absolute_expr (ip, imm_expr); | |
1436 | if ((unsigned long) imm_expr->X_add_number >= xlen) | |
1437 | as_warn (_("Improper shift amount (%lu)"), | |
1438 | (unsigned long) imm_expr->X_add_number); | |
1439 | INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number); | |
1440 | imm_expr->X_op = O_absent; | |
1441 | s = expr_end; | |
1442 | continue; | |
1443 | ||
1444 | case 'Z': /* CSRRxI immediate. */ | |
1445 | my_getExpression (imm_expr, s); | |
1446 | check_absolute_expr (ip, imm_expr); | |
1447 | if ((unsigned long) imm_expr->X_add_number > 31) | |
1448 | as_warn (_("Improper CSRxI immediate (%lu)"), | |
1449 | (unsigned long) imm_expr->X_add_number); | |
1450 | INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number); | |
1451 | imm_expr->X_op = O_absent; | |
1452 | s = expr_end; | |
1453 | continue; | |
1454 | ||
1455 | case 'E': /* Control register. */ | |
1456 | if (reg_lookup (&s, RCLASS_CSR, ®no)) | |
1457 | INSERT_OPERAND (CSR, *ip, regno); | |
1458 | else | |
1459 | { | |
1460 | my_getExpression (imm_expr, s); | |
1461 | check_absolute_expr (ip, imm_expr); | |
1462 | if ((unsigned long) imm_expr->X_add_number > 0xfff) | |
1d65abb5 AW |
1463 | as_warn (_("Improper CSR address (%lu)"), |
1464 | (unsigned long) imm_expr->X_add_number); | |
e23eba97 NC |
1465 | INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number); |
1466 | imm_expr->X_op = O_absent; | |
1467 | s = expr_end; | |
1468 | } | |
1469 | continue; | |
1470 | ||
1471 | case 'm': /* Rounding mode. */ | |
1472 | if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), ®no)) | |
1473 | { | |
1474 | INSERT_OPERAND (RM, *ip, regno); | |
1475 | continue; | |
1476 | } | |
1477 | break; | |
1478 | ||
1479 | case 'P': | |
1480 | case 'Q': /* Fence predecessor/successor. */ | |
1481 | if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ), | |
1482 | ®no)) | |
1483 | { | |
1484 | if (*args == 'P') | |
1485 | INSERT_OPERAND (PRED, *ip, regno); | |
1486 | else | |
1487 | INSERT_OPERAND (SUCC, *ip, regno); | |
1488 | continue; | |
1489 | } | |
1490 | break; | |
1491 | ||
1492 | case 'd': /* Destination register. */ | |
1493 | case 's': /* Source register. */ | |
1494 | case 't': /* Target register. */ | |
1495 | if (reg_lookup (&s, RCLASS_GPR, ®no)) | |
1496 | { | |
1497 | c = *args; | |
1498 | if (*s == ' ') | |
1499 | ++s; | |
1500 | ||
1501 | /* Now that we have assembled one operand, we use the args | |
1502 | string to figure out where it goes in the instruction. */ | |
1503 | switch (c) | |
1504 | { | |
1505 | case 's': | |
1506 | INSERT_OPERAND (RS1, *ip, regno); | |
1507 | break; | |
1508 | case 'd': | |
1509 | INSERT_OPERAND (RD, *ip, regno); | |
1510 | break; | |
1511 | case 't': | |
1512 | INSERT_OPERAND (RS2, *ip, regno); | |
1513 | break; | |
1514 | } | |
1515 | continue; | |
1516 | } | |
1517 | break; | |
1518 | ||
1519 | case 'D': /* Floating point rd. */ | |
1520 | case 'S': /* Floating point rs1. */ | |
1521 | case 'T': /* Floating point rs2. */ | |
1522 | case 'U': /* Floating point rs1 and rs2. */ | |
1523 | case 'R': /* Floating point rs3. */ | |
1524 | if (reg_lookup (&s, RCLASS_FPR, ®no)) | |
1525 | { | |
1526 | c = *args; | |
1527 | if (*s == ' ') | |
1528 | ++s; | |
1529 | switch (c) | |
1530 | { | |
1531 | case 'D': | |
1532 | INSERT_OPERAND (RD, *ip, regno); | |
1533 | break; | |
1534 | case 'S': | |
1535 | INSERT_OPERAND (RS1, *ip, regno); | |
1536 | break; | |
1537 | case 'U': | |
1538 | INSERT_OPERAND (RS1, *ip, regno); | |
1539 | /* fallthru */ | |
1540 | case 'T': | |
1541 | INSERT_OPERAND (RS2, *ip, regno); | |
1542 | break; | |
1543 | case 'R': | |
1544 | INSERT_OPERAND (RS3, *ip, regno); | |
1545 | break; | |
1546 | } | |
1547 | continue; | |
1548 | } | |
1549 | ||
1550 | break; | |
1551 | ||
1552 | case 'I': | |
1553 | my_getExpression (imm_expr, s); | |
1554 | if (imm_expr->X_op != O_big | |
1555 | && imm_expr->X_op != O_constant) | |
1556 | break; | |
1557 | normalize_constant_expr (imm_expr); | |
1558 | s = expr_end; | |
1559 | continue; | |
1560 | ||
1561 | case 'A': | |
1562 | my_getExpression (imm_expr, s); | |
1563 | normalize_constant_expr (imm_expr); | |
1564 | /* The 'A' format specifier must be a symbol. */ | |
1565 | if (imm_expr->X_op != O_symbol) | |
1566 | break; | |
1567 | *imm_reloc = BFD_RELOC_32; | |
1568 | s = expr_end; | |
1569 | continue; | |
1570 | ||
1571 | case 'j': /* Sign-extended immediate. */ | |
1572 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; | |
1573 | p = percent_op_itype; | |
1574 | goto alu_op; | |
1575 | case 'q': /* Store displacement. */ | |
1576 | p = percent_op_stype; | |
1577 | *imm_reloc = BFD_RELOC_RISCV_LO12_S; | |
1578 | goto load_store; | |
1579 | case 'o': /* Load displacement. */ | |
1580 | p = percent_op_itype; | |
1581 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; | |
1582 | goto load_store; | |
1583 | case '0': /* AMO "displacement," which must be zero. */ | |
1584 | p = percent_op_rtype; | |
1585 | *imm_reloc = BFD_RELOC_UNUSED; | |
1586 | load_store: | |
1587 | /* Check whether there is only a single bracketed expression | |
1588 | left. If so, it must be the base register and the | |
1589 | constant must be zero. */ | |
1590 | imm_expr->X_op = O_constant; | |
1591 | imm_expr->X_add_number = 0; | |
1592 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
1593 | continue; | |
1594 | alu_op: | |
1595 | /* If this value won't fit into a 16 bit offset, then go | |
1596 | find a macro that will generate the 32 bit offset | |
1597 | code pattern. */ | |
1598 | if (!my_getSmallExpression (imm_expr, imm_reloc, s, p)) | |
1599 | { | |
1600 | normalize_constant_expr (imm_expr); | |
1601 | if (imm_expr->X_op != O_constant | |
1602 | || (*args == '0' && imm_expr->X_add_number != 0) | |
1603 | || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2 | |
1604 | || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2) | |
1605 | break; | |
1606 | } | |
1607 | ||
1608 | s = expr_end; | |
1609 | continue; | |
1610 | ||
1611 | case 'p': /* PC-relative offset. */ | |
1612 | branch: | |
1613 | *imm_reloc = BFD_RELOC_12_PCREL; | |
1614 | my_getExpression (imm_expr, s); | |
1615 | s = expr_end; | |
1616 | continue; | |
1617 | ||
1618 | case 'u': /* Upper 20 bits. */ | |
1619 | p = percent_op_utype; | |
1620 | if (!my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1621 | && imm_expr->X_op == O_constant) | |
1622 | { | |
1623 | if (imm_expr->X_add_number < 0 | |
1624 | || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH) | |
1625 | as_bad (_("lui expression not in range 0..1048575")); | |
1626 | ||
1627 | *imm_reloc = BFD_RELOC_RISCV_HI20; | |
1628 | imm_expr->X_add_number <<= RISCV_IMM_BITS; | |
1629 | } | |
1630 | s = expr_end; | |
1631 | continue; | |
1632 | ||
1633 | case 'a': /* 20-bit PC-relative offset. */ | |
1634 | jump: | |
1635 | my_getExpression (imm_expr, s); | |
1636 | s = expr_end; | |
1637 | *imm_reloc = BFD_RELOC_RISCV_JMP; | |
1638 | continue; | |
1639 | ||
1640 | case 'c': | |
1641 | my_getExpression (imm_expr, s); | |
1642 | s = expr_end; | |
1643 | if (strcmp (s, "@plt") == 0) | |
1644 | { | |
1645 | *imm_reloc = BFD_RELOC_RISCV_CALL_PLT; | |
1646 | s += 4; | |
1647 | } | |
1648 | else | |
1649 | *imm_reloc = BFD_RELOC_RISCV_CALL; | |
1650 | continue; | |
1651 | ||
1652 | default: | |
1653 | as_fatal (_("internal error: bad argument type %c"), *args); | |
1654 | } | |
1655 | break; | |
1656 | } | |
1657 | s = argsStart; | |
1658 | error = _("illegal operands"); | |
1659 | } | |
1660 | ||
1661 | out: | |
1662 | /* Restore the character we might have clobbered above. */ | |
1663 | if (save_c) | |
1664 | *(argsStart - 1) = save_c; | |
1665 | ||
1666 | return error; | |
1667 | } | |
1668 | ||
1669 | void | |
1670 | md_assemble (char *str) | |
1671 | { | |
1672 | struct riscv_cl_insn insn; | |
1673 | expressionS imm_expr; | |
1674 | bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; | |
1675 | ||
1676 | const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc); | |
1677 | ||
1678 | if (error) | |
1679 | { | |
1680 | as_bad ("%s `%s'", error, str); | |
1681 | return; | |
1682 | } | |
1683 | ||
1684 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1685 | macro (&insn, &imm_expr, &imm_reloc); | |
1686 | else | |
1687 | append_insn (&insn, &imm_expr, imm_reloc); | |
1688 | } | |
1689 | ||
1690 | const char * | |
1691 | md_atof (int type, char *litP, int *sizeP) | |
1692 | { | |
1693 | return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN); | |
1694 | } | |
1695 | ||
1696 | void | |
1697 | md_number_to_chars (char *buf, valueT val, int n) | |
1698 | { | |
1699 | number_to_chars_littleendian (buf, val, n); | |
1700 | } | |
1701 | ||
1702 | const char *md_shortopts = "O::g::G:"; | |
1703 | ||
1704 | enum options | |
1705 | { | |
2922d21d | 1706 | OPTION_MARCH = OPTION_MD_BASE, |
e23eba97 NC |
1707 | OPTION_PIC, |
1708 | OPTION_NO_PIC, | |
2922d21d | 1709 | OPTION_MABI, |
e23eba97 NC |
1710 | OPTION_END_OF_ENUM |
1711 | }; | |
1712 | ||
1713 | struct option md_longopts[] = | |
1714 | { | |
e23eba97 NC |
1715 | {"march", required_argument, NULL, OPTION_MARCH}, |
1716 | {"fPIC", no_argument, NULL, OPTION_PIC}, | |
1717 | {"fpic", no_argument, NULL, OPTION_PIC}, | |
1718 | {"fno-pic", no_argument, NULL, OPTION_NO_PIC}, | |
2922d21d | 1719 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e23eba97 NC |
1720 | |
1721 | {NULL, no_argument, NULL, 0} | |
1722 | }; | |
1723 | size_t md_longopts_size = sizeof (md_longopts); | |
1724 | ||
2922d21d AW |
1725 | enum float_abi { |
1726 | FLOAT_ABI_DEFAULT = -1, | |
1727 | FLOAT_ABI_SOFT, | |
1728 | FLOAT_ABI_SINGLE, | |
1729 | FLOAT_ABI_DOUBLE, | |
1730 | FLOAT_ABI_QUAD | |
e23eba97 | 1731 | }; |
2922d21d AW |
1732 | static enum float_abi float_abi = FLOAT_ABI_DEFAULT; |
1733 | ||
1734 | static void | |
1735 | riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi) | |
1736 | { | |
1737 | abi_xlen = new_xlen; | |
1738 | float_abi = new_float_abi; | |
1739 | } | |
e23eba97 NC |
1740 | |
1741 | int | |
1742 | md_parse_option (int c, const char *arg) | |
1743 | { | |
1744 | switch (c) | |
1745 | { | |
e23eba97 NC |
1746 | case OPTION_MARCH: |
1747 | riscv_set_arch (arg); | |
1748 | break; | |
1749 | ||
1750 | case OPTION_NO_PIC: | |
1751 | riscv_opts.pic = FALSE; | |
1752 | break; | |
1753 | ||
1754 | case OPTION_PIC: | |
1755 | riscv_opts.pic = TRUE; | |
1756 | break; | |
1757 | ||
2922d21d AW |
1758 | case OPTION_MABI: |
1759 | if (strcmp (arg, "ilp32") == 0) | |
1760 | riscv_set_abi (32, FLOAT_ABI_SOFT); | |
1761 | else if (strcmp (arg, "ilp32f") == 0) | |
1762 | riscv_set_abi (32, FLOAT_ABI_SINGLE); | |
1763 | else if (strcmp (arg, "ilp32d") == 0) | |
1764 | riscv_set_abi (32, FLOAT_ABI_DOUBLE); | |
1765 | else if (strcmp (arg, "ilp32q") == 0) | |
1766 | riscv_set_abi (32, FLOAT_ABI_QUAD); | |
1767 | else if (strcmp (arg, "lp64") == 0) | |
1768 | riscv_set_abi (64, FLOAT_ABI_SOFT); | |
1769 | else if (strcmp (arg, "lp64f") == 0) | |
1770 | riscv_set_abi (64, FLOAT_ABI_SINGLE); | |
1771 | else if (strcmp (arg, "lp64d") == 0) | |
1772 | riscv_set_abi (64, FLOAT_ABI_DOUBLE); | |
1773 | else if (strcmp (arg, "lp64q") == 0) | |
1774 | riscv_set_abi (64, FLOAT_ABI_QUAD); | |
1775 | else | |
1776 | return 0; | |
1777 | break; | |
1778 | ||
e23eba97 NC |
1779 | default: |
1780 | return 0; | |
1781 | } | |
1782 | ||
1783 | return 1; | |
1784 | } | |
1785 | ||
1786 | void | |
1787 | riscv_after_parse_args (void) | |
1788 | { | |
e23eba97 NC |
1789 | if (xlen == 0) |
1790 | { | |
1791 | if (strcmp (default_arch, "riscv32") == 0) | |
1792 | xlen = 32; | |
1793 | else if (strcmp (default_arch, "riscv64") == 0) | |
1794 | xlen = 64; | |
1795 | else | |
1796 | as_bad ("unknown default architecture `%s'", default_arch); | |
1797 | } | |
2922d21d AW |
1798 | |
1799 | if (riscv_subsets == NULL) | |
1800 | riscv_set_arch (xlen == 64 ? "rv64g" : "rv32g"); | |
1801 | ||
1802 | /* Add the RVC extension, regardless of -march, to support .option rvc. */ | |
1803 | if (riscv_subset_supports ("c")) | |
1804 | riscv_set_rvc (TRUE); | |
1805 | else | |
1806 | riscv_add_subset ("c"); | |
1807 | ||
1808 | /* Infer ABI from ISA if not specified on command line. */ | |
1809 | if (abi_xlen == 0) | |
1810 | abi_xlen = xlen; | |
1811 | else if (abi_xlen > xlen) | |
1812 | as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen); | |
1813 | else if (abi_xlen < xlen) | |
1814 | as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); | |
1815 | ||
1816 | if (float_abi == FLOAT_ABI_DEFAULT) | |
1817 | { | |
1818 | struct riscv_subset *subset; | |
1819 | ||
1820 | /* Assume soft-float unless D extension is present. */ | |
1821 | float_abi = FLOAT_ABI_SOFT; | |
1822 | ||
1823 | for (subset = riscv_subsets; subset != NULL; subset = subset->next) | |
cc917fd9 KC |
1824 | { |
1825 | if (strcasecmp (subset->name, "D") == 0) | |
1826 | float_abi = FLOAT_ABI_DOUBLE; | |
1827 | if (strcasecmp (subset->name, "Q") == 0) | |
1828 | float_abi = FLOAT_ABI_QUAD; | |
1829 | } | |
2922d21d AW |
1830 | } |
1831 | ||
1832 | /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */ | |
1833 | elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1)); | |
e23eba97 NC |
1834 | } |
1835 | ||
1836 | long | |
1837 | md_pcrel_from (fixS *fixP) | |
1838 | { | |
1839 | return fixP->fx_where + fixP->fx_frag->fr_address; | |
1840 | } | |
1841 | ||
1842 | /* Apply a fixup to the object file. */ | |
1843 | ||
1844 | void | |
1845 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) | |
1846 | { | |
45f76423 | 1847 | unsigned int subtype; |
e23eba97 | 1848 | bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
45f76423 | 1849 | bfd_boolean relaxable = FALSE; |
e23eba97 NC |
1850 | |
1851 | /* Remember value for tc_gen_reloc. */ | |
1852 | fixP->fx_addnumber = *valP; | |
1853 | ||
1854 | switch (fixP->fx_r_type) | |
1855 | { | |
e23eba97 NC |
1856 | case BFD_RELOC_RISCV_HI20: |
1857 | case BFD_RELOC_RISCV_LO12_I: | |
1858 | case BFD_RELOC_RISCV_LO12_S: | |
45f76423 AW |
1859 | bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP) |
1860 | | bfd_getl32 (buf), buf); | |
a5ec5e3f AW |
1861 | if (fixP->fx_addsy == NULL) |
1862 | fixP->fx_done = TRUE; | |
45f76423 AW |
1863 | relaxable = TRUE; |
1864 | break; | |
1865 | ||
1866 | case BFD_RELOC_RISCV_GOT_HI20: | |
1867 | case BFD_RELOC_RISCV_PCREL_HI20: | |
e23eba97 NC |
1868 | case BFD_RELOC_RISCV_ADD8: |
1869 | case BFD_RELOC_RISCV_ADD16: | |
1870 | case BFD_RELOC_RISCV_ADD32: | |
1871 | case BFD_RELOC_RISCV_ADD64: | |
45f76423 | 1872 | case BFD_RELOC_RISCV_SUB6: |
e23eba97 NC |
1873 | case BFD_RELOC_RISCV_SUB8: |
1874 | case BFD_RELOC_RISCV_SUB16: | |
1875 | case BFD_RELOC_RISCV_SUB32: | |
1876 | case BFD_RELOC_RISCV_SUB64: | |
45f76423 AW |
1877 | case BFD_RELOC_RISCV_RELAX: |
1878 | break; | |
1879 | ||
1880 | case BFD_RELOC_RISCV_TPREL_HI20: | |
1881 | case BFD_RELOC_RISCV_TPREL_LO12_I: | |
1882 | case BFD_RELOC_RISCV_TPREL_LO12_S: | |
1883 | case BFD_RELOC_RISCV_TPREL_ADD: | |
1884 | relaxable = TRUE; | |
1885 | /* Fall through. */ | |
1886 | ||
1887 | case BFD_RELOC_RISCV_TLS_GOT_HI20: | |
1888 | case BFD_RELOC_RISCV_TLS_GD_HI20: | |
1889 | case BFD_RELOC_RISCV_TLS_DTPREL32: | |
1890 | case BFD_RELOC_RISCV_TLS_DTPREL64: | |
e294484e AW |
1891 | if (fixP->fx_addsy != NULL) |
1892 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
1893 | else | |
1894 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1895 | _("TLS relocation against a constant")); | |
e23eba97 NC |
1896 | break; |
1897 | ||
1898 | case BFD_RELOC_64: | |
1899 | case BFD_RELOC_32: | |
1900 | case BFD_RELOC_16: | |
1901 | case BFD_RELOC_8: | |
45f76423 | 1902 | case BFD_RELOC_RISCV_CFA: |
e23eba97 NC |
1903 | if (fixP->fx_addsy && fixP->fx_subsy) |
1904 | { | |
1905 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
1906 | fixP->fx_next->fx_addsy = fixP->fx_subsy; | |
1907 | fixP->fx_next->fx_subsy = NULL; | |
1908 | fixP->fx_next->fx_offset = 0; | |
1909 | fixP->fx_subsy = NULL; | |
1910 | ||
1911 | switch (fixP->fx_r_type) | |
1912 | { | |
1913 | case BFD_RELOC_64: | |
1914 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD64; | |
1915 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64; | |
1916 | break; | |
1917 | ||
1918 | case BFD_RELOC_32: | |
1919 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD32; | |
1920 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
1921 | break; | |
1922 | ||
1923 | case BFD_RELOC_16: | |
1924 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD16; | |
1925 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
1926 | break; | |
1927 | ||
1928 | case BFD_RELOC_8: | |
1929 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD8; | |
1930 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
073808ed | 1931 | break; |
e23eba97 | 1932 | |
45f76423 AW |
1933 | case BFD_RELOC_RISCV_CFA: |
1934 | /* Load the byte to get the subtype. */ | |
1935 | subtype = bfd_get_8 (NULL, &fixP->fx_frag->fr_literal[fixP->fx_where]); | |
1936 | switch (subtype) | |
1937 | { | |
1938 | case DW_CFA_advance_loc1: | |
1939 | fixP->fx_where++; | |
1940 | fixP->fx_next->fx_where++; | |
1941 | fixP->fx_r_type = BFD_RELOC_RISCV_SET8; | |
1942 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
1943 | break; | |
1944 | ||
1945 | case DW_CFA_advance_loc2: | |
1946 | fixP->fx_size = 2; | |
1947 | fixP->fx_where++; | |
1948 | fixP->fx_next->fx_size = 2; | |
1949 | fixP->fx_next->fx_where++; | |
1950 | fixP->fx_r_type = BFD_RELOC_RISCV_SET16; | |
1951 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
1952 | break; | |
1953 | ||
1954 | case DW_CFA_advance_loc4: | |
1955 | fixP->fx_size = 4; | |
1956 | fixP->fx_where++; | |
1957 | fixP->fx_next->fx_size = 4; | |
1958 | fixP->fx_next->fx_where++; | |
1959 | fixP->fx_r_type = BFD_RELOC_RISCV_SET32; | |
1960 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
1961 | break; | |
1962 | ||
1963 | default: | |
1964 | if (subtype < 0x80 && (subtype & 0x40)) | |
1965 | { | |
1966 | /* DW_CFA_advance_loc */ | |
1967 | fixP->fx_r_type = BFD_RELOC_RISCV_SET6; | |
1968 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6; | |
1969 | } | |
1970 | else | |
1971 | as_fatal (_("internal error: bad CFA value #%d"), subtype); | |
1972 | break; | |
1973 | } | |
1974 | break; | |
1975 | ||
e23eba97 NC |
1976 | default: |
1977 | /* This case is unreachable. */ | |
1978 | abort (); | |
1979 | } | |
1980 | } | |
1981 | /* Fall through. */ | |
1982 | ||
1983 | case BFD_RELOC_RVA: | |
1984 | /* If we are deleting this reloc entry, we must fill in the | |
1985 | value now. This can happen if we have a .word which is not | |
1986 | resolved when it appears but is later defined. */ | |
1987 | if (fixP->fx_addsy == NULL) | |
1988 | { | |
1989 | gas_assert (fixP->fx_size <= sizeof (valueT)); | |
1990 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); | |
1991 | fixP->fx_done = 1; | |
1992 | } | |
1993 | break; | |
1994 | ||
1995 | case BFD_RELOC_RISCV_JMP: | |
1996 | if (fixP->fx_addsy) | |
1997 | { | |
1998 | /* Fill in a tentative value to improve objdump readability. */ | |
1999 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2000 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2001 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf); | |
2002 | } | |
2003 | break; | |
2004 | ||
2005 | case BFD_RELOC_12_PCREL: | |
2006 | if (fixP->fx_addsy) | |
2007 | { | |
2008 | /* Fill in a tentative value to improve objdump readability. */ | |
2009 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2010 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2011 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf); | |
2012 | } | |
2013 | break; | |
2014 | ||
2015 | case BFD_RELOC_RISCV_RVC_BRANCH: | |
2016 | if (fixP->fx_addsy) | |
2017 | { | |
2018 | /* Fill in a tentative value to improve objdump readability. */ | |
2019 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2020 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2021 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf); | |
2022 | } | |
2023 | break; | |
2024 | ||
2025 | case BFD_RELOC_RISCV_RVC_JUMP: | |
2026 | if (fixP->fx_addsy) | |
2027 | { | |
2028 | /* Fill in a tentative value to improve objdump readability. */ | |
2029 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2030 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2031 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf); | |
2032 | } | |
2033 | break; | |
2034 | ||
e23eba97 NC |
2035 | case BFD_RELOC_RISCV_CALL: |
2036 | case BFD_RELOC_RISCV_CALL_PLT: | |
45f76423 AW |
2037 | relaxable = TRUE; |
2038 | break; | |
2039 | ||
2040 | case BFD_RELOC_RISCV_PCREL_LO12_S: | |
2041 | case BFD_RELOC_RISCV_PCREL_LO12_I: | |
e23eba97 NC |
2042 | case BFD_RELOC_RISCV_ALIGN: |
2043 | break; | |
2044 | ||
2045 | default: | |
2046 | /* We ignore generic BFD relocations we don't know about. */ | |
2047 | if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL) | |
2048 | as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type); | |
2049 | } | |
45f76423 | 2050 | |
e294484e AW |
2051 | if (fixP->fx_subsy != NULL) |
2052 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2053 | _("unsupported symbol subtraction")); | |
2054 | ||
45f76423 AW |
2055 | /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */ |
2056 | if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL) | |
2057 | { | |
2058 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
2059 | fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL; | |
2060 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX; | |
2061 | } | |
2062 | } | |
2063 | ||
2064 | /* Because the value of .cfi_remember_state may changed after relaxation, | |
2065 | we insert a fix to relocate it again in link-time. */ | |
2066 | ||
2067 | void | |
2068 | riscv_pre_output_hook (void) | |
2069 | { | |
2070 | const frchainS *frch; | |
2071 | const asection *s; | |
2072 | ||
2073 | for (s = stdoutput->sections; s; s = s->next) | |
2074 | for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next) | |
2075 | { | |
2076 | const fragS *frag; | |
2077 | ||
2078 | for (frag = frch->frch_root; frag; frag = frag->fr_next) | |
2079 | { | |
2080 | if (frag->fr_type == rs_cfa) | |
2081 | { | |
ad5bc882 | 2082 | fragS *loc4_frag; |
45f76423 AW |
2083 | expressionS exp; |
2084 | ||
2085 | symbolS *add_symbol = frag->fr_symbol->sy_value.X_add_symbol; | |
2086 | symbolS *op_symbol = frag->fr_symbol->sy_value.X_op_symbol; | |
2087 | ||
2088 | exp.X_op = O_subtract; | |
2089 | exp.X_add_symbol = add_symbol; | |
2090 | exp.X_add_number = 0; | |
2091 | exp.X_op_symbol = op_symbol; | |
2092 | ||
2093 | loc4_frag = (fragS *) frag->fr_opcode; | |
2094 | fix_new_exp (loc4_frag, (int) frag->fr_offset, 1, &exp, 0, | |
2095 | BFD_RELOC_RISCV_CFA); | |
2096 | } | |
2097 | } | |
2098 | } | |
e23eba97 NC |
2099 | } |
2100 | ||
45f76423 | 2101 | |
e23eba97 NC |
2102 | /* This structure is used to hold a stack of .option values. */ |
2103 | ||
2104 | struct riscv_option_stack | |
2105 | { | |
2106 | struct riscv_option_stack *next; | |
2107 | struct riscv_set_options options; | |
2108 | }; | |
2109 | ||
2110 | static struct riscv_option_stack *riscv_opts_stack; | |
2111 | ||
2112 | /* Handle the .option pseudo-op. */ | |
2113 | ||
2114 | static void | |
2115 | s_riscv_option (int x ATTRIBUTE_UNUSED) | |
2116 | { | |
2117 | char *name = input_line_pointer, ch; | |
2118 | ||
2119 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2120 | ++input_line_pointer; | |
2121 | ch = *input_line_pointer; | |
2122 | *input_line_pointer = '\0'; | |
2123 | ||
2124 | if (strcmp (name, "rvc") == 0) | |
2125 | riscv_set_rvc (TRUE); | |
2126 | else if (strcmp (name, "norvc") == 0) | |
2127 | riscv_set_rvc (FALSE); | |
2128 | else if (strcmp (name, "pic") == 0) | |
2129 | riscv_opts.pic = TRUE; | |
2130 | else if (strcmp (name, "nopic") == 0) | |
2131 | riscv_opts.pic = FALSE; | |
45f76423 AW |
2132 | else if (strcmp (name, "relax") == 0) |
2133 | riscv_opts.relax = TRUE; | |
2134 | else if (strcmp (name, "norelax") == 0) | |
2135 | riscv_opts.relax = FALSE; | |
e23eba97 NC |
2136 | else if (strcmp (name, "push") == 0) |
2137 | { | |
2138 | struct riscv_option_stack *s; | |
2139 | ||
2140 | s = (struct riscv_option_stack *) xmalloc (sizeof *s); | |
2141 | s->next = riscv_opts_stack; | |
2142 | s->options = riscv_opts; | |
2143 | riscv_opts_stack = s; | |
2144 | } | |
2145 | else if (strcmp (name, "pop") == 0) | |
2146 | { | |
2147 | struct riscv_option_stack *s; | |
2148 | ||
2149 | s = riscv_opts_stack; | |
2150 | if (s == NULL) | |
2151 | as_bad (_(".option pop with no .option push")); | |
2152 | else | |
2153 | { | |
2154 | riscv_opts = s->options; | |
2155 | riscv_opts_stack = s->next; | |
2156 | free (s); | |
2157 | } | |
2158 | } | |
2159 | else | |
2160 | { | |
2161 | as_warn (_("Unrecognized .option directive: %s\n"), name); | |
2162 | } | |
2163 | *input_line_pointer = ch; | |
2164 | demand_empty_rest_of_line (); | |
2165 | } | |
2166 | ||
2167 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate | |
2168 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
2169 | use in DWARF debug information. */ | |
2170 | ||
2171 | static void | |
2172 | s_dtprel (int bytes) | |
2173 | { | |
2174 | expressionS ex; | |
2175 | char *p; | |
2176 | ||
2177 | expression (&ex); | |
2178 | ||
2179 | if (ex.X_op != O_symbol) | |
2180 | { | |
2181 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
2182 | ? ".dtpreldword" | |
2183 | : ".dtprelword")); | |
2184 | ignore_rest_of_line (); | |
2185 | } | |
2186 | ||
2187 | p = frag_more (bytes); | |
2188 | md_number_to_chars (p, 0, bytes); | |
2189 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
2190 | (bytes == 8 | |
2191 | ? BFD_RELOC_RISCV_TLS_DTPREL64 | |
2192 | : BFD_RELOC_RISCV_TLS_DTPREL32)); | |
2193 | ||
2194 | demand_empty_rest_of_line (); | |
2195 | } | |
2196 | ||
2197 | /* Handle the .bss pseudo-op. */ | |
2198 | ||
2199 | static void | |
2200 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
2201 | { | |
2202 | subseg_set (bss_section, 0); | |
2203 | demand_empty_rest_of_line (); | |
2204 | } | |
2205 | ||
e23eba97 | 2206 | static void |
d115ab8e | 2207 | riscv_make_nops (char *buf, bfd_vma bytes) |
e23eba97 | 2208 | { |
d115ab8e | 2209 | bfd_vma i = 0; |
e23eba97 | 2210 | |
e5b737de AW |
2211 | /* RISC-V instructions cannot begin or end on odd addresses, so this case |
2212 | means we are not within a valid instruction sequence. It is thus safe | |
2213 | to use a zero byte, even though that is not a valid instruction. */ | |
2214 | if (bytes % 2 == 1) | |
2215 | buf[i++] = 0; | |
2216 | ||
2217 | /* Use at most one 2-byte NOP. */ | |
2218 | if ((bytes - i) % 4 == 2) | |
e23eba97 | 2219 | { |
e5b737de | 2220 | md_number_to_chars (buf + i, RVC_NOP, 2); |
d115ab8e | 2221 | i += 2; |
e23eba97 NC |
2222 | } |
2223 | ||
e5b737de | 2224 | /* Fill the remainder with 4-byte NOPs. */ |
d115ab8e AW |
2225 | for ( ; i < bytes; i += 4) |
2226 | md_number_to_chars (buf + i, RISCV_NOP, 4); | |
2227 | } | |
e23eba97 | 2228 | |
d115ab8e AW |
2229 | /* Called from md_do_align. Used to create an alignment frag in a |
2230 | code section by emitting a worst-case NOP sequence that the linker | |
2231 | will later relax to the correct number of NOPs. We can't compute | |
2232 | the correct alignment now because of other linker relaxations. */ | |
2233 | ||
2234 | bfd_boolean | |
2235 | riscv_frag_align_code (int n) | |
2236 | { | |
e5b737de AW |
2237 | bfd_vma bytes = (bfd_vma) 1 << n; |
2238 | bfd_vma min_text_alignment_order = riscv_opts.rvc ? 1 : 2; | |
2239 | bfd_vma min_text_alignment = (bfd_vma) 1 << min_text_alignment_order; | |
2240 | ||
2241 | /* First, get back to minimal alignment. */ | |
2242 | frag_align_code (min_text_alignment_order, 0); | |
d115ab8e AW |
2243 | |
2244 | /* When not relaxing, riscv_handle_align handles code alignment. */ | |
2245 | if (!riscv_opts.relax) | |
2246 | return FALSE; | |
e23eba97 | 2247 | |
d115ab8e | 2248 | if (bytes > min_text_alignment) |
e23eba97 | 2249 | { |
d115ab8e | 2250 | bfd_vma worst_case_bytes = bytes - min_text_alignment; |
e23eba97 | 2251 | char *nops = frag_more (worst_case_bytes); |
e23eba97 | 2252 | expressionS ex; |
d115ab8e | 2253 | |
e23eba97 NC |
2254 | ex.X_op = O_constant; |
2255 | ex.X_add_number = worst_case_bytes; | |
2256 | ||
d115ab8e AW |
2257 | riscv_make_nops (nops, worst_case_bytes); |
2258 | ||
e23eba97 NC |
2259 | fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, |
2260 | &ex, FALSE, BFD_RELOC_RISCV_ALIGN); | |
2261 | } | |
e23eba97 | 2262 | |
d115ab8e AW |
2263 | return TRUE; |
2264 | } | |
e23eba97 | 2265 | |
d115ab8e AW |
2266 | /* Implement HANDLE_ALIGN. */ |
2267 | ||
2268 | void | |
2269 | riscv_handle_align (fragS *fragP) | |
2270 | { | |
2271 | switch (fragP->fr_type) | |
2272 | { | |
2273 | case rs_align_code: | |
2274 | /* When relaxing, riscv_frag_align_code handles code alignment. */ | |
2275 | if (!riscv_opts.relax) | |
2276 | { | |
2277 | bfd_signed_vma count = fragP->fr_next->fr_address | |
2278 | - fragP->fr_address - fragP->fr_fix; | |
2279 | ||
2280 | if (count <= 0) | |
2281 | break; | |
2282 | ||
2283 | count &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
2284 | riscv_make_nops (fragP->fr_literal + fragP->fr_fix, count); | |
2285 | fragP->fr_var = count; | |
2286 | } | |
2287 | break; | |
2288 | ||
2289 | default: | |
2290 | break; | |
2291 | } | |
e23eba97 NC |
2292 | } |
2293 | ||
2294 | int | |
2295 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) | |
2296 | { | |
2297 | return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE)); | |
2298 | } | |
2299 | ||
2300 | /* Translate internal representation of relocation info to BFD target | |
2301 | format. */ | |
2302 | ||
2303 | arelent * | |
2304 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) | |
2305 | { | |
2306 | arelent *reloc = (arelent *) xmalloc (sizeof (arelent)); | |
2307 | ||
2308 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
2309 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
2310 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
2311 | reloc->addend = fixp->fx_addnumber; | |
2312 | ||
2313 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
2314 | if (reloc->howto == NULL) | |
2315 | { | |
2316 | if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8) | |
2317 | && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL) | |
2318 | { | |
2319 | /* We don't have R_RISCV_8/16, but for this special case, | |
2320 | we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */ | |
2321 | return reloc; | |
2322 | } | |
2323 | ||
2324 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2325 | _("cannot represent %s relocation in object file"), | |
2326 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
2327 | return NULL; | |
2328 | } | |
2329 | ||
2330 | return reloc; | |
2331 | } | |
2332 | ||
2333 | int | |
2334 | riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) | |
2335 | { | |
2336 | if (RELAX_BRANCH_P (fragp->fr_subtype)) | |
2337 | { | |
2338 | offsetT old_var = fragp->fr_var; | |
2339 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
2340 | return fragp->fr_var - old_var; | |
2341 | } | |
2342 | ||
2343 | return 0; | |
2344 | } | |
2345 | ||
2346 | /* Expand far branches to multi-instruction sequences. */ | |
2347 | ||
2348 | static void | |
2349 | md_convert_frag_branch (fragS *fragp) | |
2350 | { | |
2351 | bfd_byte *buf; | |
2352 | expressionS exp; | |
2353 | fixS *fixp; | |
2354 | insn_t insn; | |
2355 | int rs1, reloc; | |
2356 | ||
2357 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; | |
2358 | ||
2359 | exp.X_op = O_symbol; | |
2360 | exp.X_add_symbol = fragp->fr_symbol; | |
2361 | exp.X_add_number = fragp->fr_offset; | |
2362 | ||
2363 | gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype)); | |
2364 | ||
2365 | if (RELAX_BRANCH_RVC (fragp->fr_subtype)) | |
2366 | { | |
2367 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
2368 | { | |
2369 | case 8: | |
2370 | case 4: | |
2371 | /* Expand the RVC branch into a RISC-V one. */ | |
2372 | insn = bfd_getl16 (buf); | |
2373 | rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S); | |
2374 | if ((insn & MASK_C_J) == MATCH_C_J) | |
2375 | insn = MATCH_JAL; | |
2376 | else if ((insn & MASK_C_JAL) == MATCH_C_JAL) | |
2377 | insn = MATCH_JAL | (X_RA << OP_SH_RD); | |
2378 | else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ) | |
2379 | insn = MATCH_BEQ | (rs1 << OP_SH_RS1); | |
2380 | else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ) | |
2381 | insn = MATCH_BNE | (rs1 << OP_SH_RS1); | |
2382 | else | |
2383 | abort (); | |
2384 | bfd_putl32 (insn, buf); | |
2385 | break; | |
2386 | ||
2387 | case 6: | |
2388 | /* Invert the branch condition. Branch over the jump. */ | |
2389 | insn = bfd_getl16 (buf); | |
2390 | insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ; | |
2391 | insn |= ENCODE_RVC_B_IMM (6); | |
2392 | bfd_putl16 (insn, buf); | |
2393 | buf += 2; | |
2394 | goto jump; | |
2395 | ||
2396 | case 2: | |
2397 | /* Just keep the RVC branch. */ | |
2398 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
2399 | ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH; | |
2400 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
2401 | 2, &exp, FALSE, reloc); | |
2402 | buf += 2; | |
2403 | goto done; | |
2404 | ||
2405 | default: | |
1d65abb5 | 2406 | abort (); |
e23eba97 NC |
2407 | } |
2408 | } | |
2409 | ||
2410 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
2411 | { | |
2412 | case 8: | |
2413 | gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); | |
2414 | ||
2415 | /* Invert the branch condition. Branch over the jump. */ | |
2416 | insn = bfd_getl32 (buf); | |
2417 | insn ^= MATCH_BEQ ^ MATCH_BNE; | |
2418 | insn |= ENCODE_SBTYPE_IMM (8); | |
2419 | md_number_to_chars ((char *) buf, insn, 4); | |
2420 | buf += 4; | |
2421 | ||
2422 | jump: | |
2423 | /* Jump to the target. */ | |
2424 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
2425 | 4, &exp, FALSE, BFD_RELOC_RISCV_JMP); | |
2426 | md_number_to_chars ((char *) buf, MATCH_JAL, 4); | |
2427 | buf += 4; | |
2428 | break; | |
2429 | ||
2430 | case 4: | |
2431 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
2432 | ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL; | |
2433 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
2434 | 4, &exp, FALSE, reloc); | |
2435 | buf += 4; | |
2436 | break; | |
2437 | ||
2438 | default: | |
2439 | abort (); | |
2440 | } | |
2441 | ||
2442 | done: | |
2443 | fixp->fx_file = fragp->fr_file; | |
2444 | fixp->fx_line = fragp->fr_line; | |
2445 | ||
2446 | gas_assert (buf == (bfd_byte *)fragp->fr_literal | |
2447 | + fragp->fr_fix + fragp->fr_var); | |
2448 | ||
2449 | fragp->fr_fix += fragp->fr_var; | |
2450 | } | |
2451 | ||
2452 | /* Relax a machine dependent frag. This returns the amount by which | |
2453 | the current size of the frag should change. */ | |
2454 | ||
2455 | void | |
2456 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, | |
2457 | fragS *fragp) | |
2458 | { | |
2459 | gas_assert (RELAX_BRANCH_P (fragp->fr_subtype)); | |
2460 | md_convert_frag_branch (fragp); | |
2461 | } | |
2462 | ||
2463 | void | |
2464 | md_show_usage (FILE *stream) | |
2465 | { | |
2466 | fprintf (stream, _("\ | |
2467 | RISC-V options:\n\ | |
2468 | -m32 assemble RV32 code\n\ | |
2469 | -m64 assemble RV64 code (default)\n\ | |
2470 | -fpic generate position-independent code\n\ | |
2471 | -fno-pic don't generate position-independent code (default)\n\ | |
2472 | -msoft-float don't use F registers for floating-point values\n\ | |
2473 | -mhard-float use F registers for floating-point values (default)\n\ | |
2474 | -mno-rvc disable the C extension for compressed instructions (default)\n\ | |
2475 | -mrvc enable the C extension for compressed instructions\n\ | |
2476 | -march=ISA set the RISC-V architecture, RV64IMAFD by default\n\ | |
2477 | ")); | |
2478 | } | |
2479 | ||
2480 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
2481 | void | |
2482 | riscv_cfi_frame_initial_instructions (void) | |
2483 | { | |
2484 | cfi_add_CFA_def_cfa_register (X_SP); | |
2485 | } | |
2486 | ||
2487 | int | |
2488 | tc_riscv_regname_to_dw2regnum (char *regname) | |
2489 | { | |
2490 | int reg; | |
2491 | ||
2492 | if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0) | |
2493 | return reg; | |
2494 | ||
2495 | if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0) | |
2496 | return reg + 32; | |
2497 | ||
2498 | as_bad (_("unknown register `%s'"), regname); | |
2499 | return -1; | |
2500 | } | |
2501 | ||
2502 | void | |
2503 | riscv_elf_final_processing (void) | |
2504 | { | |
e23eba97 | 2505 | elf_elfheader (stdoutput)->e_flags |= elf_flags; |
e23eba97 NC |
2506 | } |
2507 | ||
2508 | /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions, | |
2509 | since these directives break relaxation when used with symbol deltas. */ | |
2510 | ||
2511 | static void | |
2512 | s_riscv_leb128 (int sign) | |
2513 | { | |
2514 | expressionS exp; | |
2515 | char *save_in = input_line_pointer; | |
2516 | ||
2517 | expression (&exp); | |
2518 | if (exp.X_op != O_constant) | |
2519 | as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u'); | |
2520 | demand_empty_rest_of_line (); | |
2521 | ||
2522 | input_line_pointer = save_in; | |
2523 | return s_leb128 (sign); | |
2524 | } | |
2525 | ||
2526 | /* Pseudo-op table. */ | |
2527 | ||
2528 | static const pseudo_typeS riscv_pseudo_table[] = | |
2529 | { | |
2530 | /* RISC-V-specific pseudo-ops. */ | |
2531 | {"option", s_riscv_option, 0}, | |
2532 | {"half", cons, 2}, | |
2533 | {"word", cons, 4}, | |
2534 | {"dword", cons, 8}, | |
2535 | {"dtprelword", s_dtprel, 4}, | |
2536 | {"dtpreldword", s_dtprel, 8}, | |
2537 | {"bss", s_bss, 0}, | |
e23eba97 NC |
2538 | {"uleb128", s_riscv_leb128, 0}, |
2539 | {"sleb128", s_riscv_leb128, 1}, | |
2540 | ||
2541 | { NULL, NULL, 0 }, | |
2542 | }; | |
2543 | ||
2544 | void | |
2545 | riscv_pop_insert (void) | |
2546 | { | |
2547 | extern void pop_insert (const pseudo_typeS *); | |
2548 | ||
2549 | pop_insert (riscv_pseudo_table); | |
2550 | } |