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Re: gas/ELF: don't accumulate .type settings
[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
CommitLineData
e23eba97 1/* tc-riscv.c -- RISC-V assembler
82704155 2 Copyright (C) 2011-2019 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
1080bf78 32#include "bfd/elfxx-riscv.h"
e23eba97
NC		 33#include "elf/riscv.h"
34#include "opcode/riscv.h"
35
36#include <stdint.h>
37
38/* Information about an instruction, including its format, operands
39 and fixups. */
40struct riscv_cl_insn
41{
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode *insn_mo;
44
45 /* The encoded instruction bits. */
46 insn_t insn_opcode;
47
48 /* The frag that contains the instruction. */
49 struct frag *frag;
50
51 /* The offset into FRAG of the first instruction byte. */
52 long where;
53
54 /* The relocs associated with the instruction, if any. */
55 fixS *fixp;
56};
57
58#ifndef DEFAULT_ARCH
59#define DEFAULT_ARCH "riscv64"
60#endif
61
2dc8dd17
JW		 62#ifndef DEFAULT_RISCV_ATTR
63#define DEFAULT_RISCV_ATTR 0
64#endif
65
e23eba97
NC		 66static const char default_arch[] = DEFAULT_ARCH;
67
2922d21d
AW		 68static unsigned xlen = 0; /* width of an x-register */
69static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
7f999549 70static bfd_boolean rve_abi = FALSE;
e23eba97 71
2922d21d 72#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
e23eba97
NC		 73#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
74
75static unsigned elf_flags = 0;
76
77/* This is the set of options which the .option pseudo-op may modify. */
78
79struct riscv_set_options
80{
81 int pic; /* Generate position-independent code. */
82 int rvc; /* Generate RVC code. */
7f999549 83 int rve; /* Generate RVE code. */
45f76423 84 int relax; /* Emit relocs the linker is allowed to relax. */
2dc8dd17 85 int arch_attr; /* Emit arch attribute. */
e23eba97
NC		 86};
87
88static struct riscv_set_options riscv_opts =
89{
90 0, /* pic */
91 0, /* rvc */
7f999549 92 0, /* rve */
45f76423 93 1, /* relax */
2dc8dd17 94 DEFAULT_RISCV_ATTR, /* arch_attr */
e23eba97
NC		 95};
96
97static void
98riscv_set_rvc (bfd_boolean rvc_value)
99{
100 if (rvc_value)
101 elf_flags |= EF_RISCV_RVC;
102
103 riscv_opts.rvc = rvc_value;
104}
105
7f999549
JW		 106static void
107riscv_set_rve (bfd_boolean rve_value)
108{
109 riscv_opts.rve = rve_value;
110}
111
1080bf78 112static riscv_subset_list_t riscv_subsets;
e23eba97
NC		 113
114static bfd_boolean
1080bf78 115riscv_subset_supports (const char *feature)
e23eba97 116{
1080bf78
JW		 117 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
118 return TRUE;
e23eba97 119
1080bf78 120 return riscv_lookup_subset (&riscv_subsets, feature) != NULL;
e23eba97
NC		 121}
122
43135d3b 123static bfd_boolean
1080bf78 124riscv_multi_subset_supports (const char *features[])
43135d3b
JW		 125{
126 unsigned i = 0;
127 bfd_boolean supported = TRUE;
128
129 for (;features[i]; ++i)
1080bf78 130 supported = supported && riscv_subset_supports (features[i]);
43135d3b
JW		 131
132 return supported;
133}
134
2922d21d 135/* Set which ISA and extensions are available. */
e23eba97 136
e23eba97 137static void
2922d21d 138riscv_set_arch (const char *s)
e23eba97 139{
1080bf78
JW		 140 riscv_parse_subset_t rps;
141 rps.subset_list = &riscv_subsets;
142 rps.error_handler = as_fatal;
143 rps.xlen = &xlen;
7f999549 144
1080bf78
JW		 145 riscv_release_subset_list (&riscv_subsets);
146 riscv_parse_subset (&rps, s);
e23eba97
NC		 147}
148
149/* Handle of the OPCODE hash table. */
150static struct hash_control *op_hash = NULL;
151
0e35537d
JW		 152/* Handle of the type of .insn hash table. */
153static struct hash_control *insn_type_hash = NULL;
154
e23eba97
NC		 155/* This array holds the chars that always start a comment. If the
156 pre-processor is disabled, these aren't very useful */
157const char comment_chars[] = "#";
158
159/* This array holds the chars that only start a comment at the beginning of
160 a line. If the line seems to have the form '# 123 filename'
161 .line and .file directives will appear in the pre-processed output */
162/* Note that input_file.c hand checks for '#' at the beginning of the
163 first line of the input file. This is because the compiler outputs
164 #NO_APP at the beginning of its output. */
165/* Also note that C style comments are always supported. */
166const char line_comment_chars[] = "#";
167
168/* This array holds machine specific line separator characters. */
169const char line_separator_chars[] = ";";
170
171/* Chars that can be used to separate mant from exp in floating point nums */
172const char EXP_CHARS[] = "eE";
173
174/* Chars that mean this number is a floating point constant */
175/* As in 0f12.456 */
176/* or 0d1.2345e12 */
177const char FLT_CHARS[] = "rRsSfFdDxXpP";
178
2dc8dd17
JW		 179/* Indicate we are already assemble any instructions or not. */
180static bfd_boolean start_assemble = FALSE;
181
182/* Indicate arch attribute is explictly set. */
183static bfd_boolean explicit_arch_attr = FALSE;
184
e23eba97
NC		 185/* Macros for encoding relaxation state for RVC branches and far jumps. */
186#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
187 ((relax_substateT) \
188 (0xc0000000 \
189 | ((uncond) ? 1 : 0) \
190 | ((rvc) ? 2 : 0) \
191 | ((length) << 2)))
192#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
193#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
194#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
195#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
196
197/* Is the given value a sign-extended 32-bit value? */
198#define IS_SEXT_32BIT_NUM(x) \
199 (((x) &~ (offsetT) 0x7fffffff) == 0 \
200 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
201
202/* Is the given value a zero-extended 32-bit value? Or a negated one? */
203#define IS_ZEXT_32BIT_NUM(x) \
204 (((x) &~ (offsetT) 0xffffffff) == 0 \
205 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
206
207/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
208 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
209#define INSERT_OPERAND(FIELD, INSN, VALUE) \
210 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
211
212/* Determine if an instruction matches an opcode. */
213#define OPCODE_MATCHES(OPCODE, OP) \
214 (((OPCODE) & MASK_##OP) == MATCH_##OP)
215
216static char *expr_end;
217
218/* The default target format to use. */
219
220const char *
221riscv_target_format (void)
222{
223 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
224}
225
226/* Return the length of instruction INSN. */
227
228static inline unsigned int
229insn_length (const struct riscv_cl_insn *insn)
230{
231 return riscv_insn_length (insn->insn_opcode);
232}
233
234/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
235
236static void
237create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
238{
239 insn->insn_mo = mo;
240 insn->insn_opcode = mo->match;
241 insn->frag = NULL;
242 insn->where = 0;
243 insn->fixp = NULL;
244}
245
246/* Install INSN at the location specified by its "frag" and "where" fields. */
247
248static void
249install_insn (const struct riscv_cl_insn *insn)
250{
251 char *f = insn->frag->fr_literal + insn->where;
252 md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
253}
254
255/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
256 and install the opcode in the new location. */
257
258static void
259move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
260{
261 insn->frag = frag;
262 insn->where = where;
263 if (insn->fixp != NULL)
264 {
265 insn->fixp->fx_frag = frag;
266 insn->fixp->fx_where = where;
267 }
268 install_insn (insn);
269}
270
271/* Add INSN to the end of the output. */
272
273static void
274add_fixed_insn (struct riscv_cl_insn *insn)
275{
276 char *f = frag_more (insn_length (insn));
277 move_insn (insn, frag_now, f - frag_now->fr_literal);
278}
279
280static void
281add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
282 relax_substateT subtype, symbolS *symbol, offsetT offset)
283{
284 frag_grow (max_chars);
285 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
286 frag_var (rs_machine_dependent, max_chars, var,
287 subtype, symbol, offset, NULL);
288}
289
290/* Compute the length of a branch sequence, and adjust the stored length
291 accordingly. If FRAGP is NULL, the worst-case length is returned. */
292
293static unsigned
294relaxed_branch_length (fragS *fragp, asection *sec, int update)
295{
296 int jump, rvc, length = 8;
297
298 if (!fragp)
299 return length;
300
301 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
302 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
303 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
304
305 /* Assume jumps are in range; the linker will catch any that aren't. */
306 length = jump ? 4 : 8;
307
308 if (fragp->fr_symbol != NULL
309 && S_IS_DEFINED (fragp->fr_symbol)
01156111 310 && !S_IS_WEAK (fragp->fr_symbol)
e23eba97
NC		 311 && sec == S_GET_SEGMENT (fragp->fr_symbol))
312 {
313 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
314 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
315 val -= fragp->fr_address + fragp->fr_fix;
316
317 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
318 length = 2;
319 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
320 length = 4;
321 else if (!jump && rvc)
322 length = 6;
323 }
324
325 if (update)
326 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
327
328 return length;
329}
330
0e35537d
JW		 331/* Information about an opcode name, mnemonics and its value. */
332struct opcode_name_t
333{
334 const char *name;
335 unsigned int val;
336};
337
338/* List for all supported opcode name. */
339static const struct opcode_name_t opcode_name_list[] =
340{
341 {"C0", 0x0},
342 {"C1", 0x1},
343 {"C2", 0x2},
344
345 {"LOAD", 0x03},
346 {"LOAD_FP", 0x07},
347 {"CUSTOM_0", 0x0b},
348 {"MISC_MEM", 0x0f},
349 {"OP_IMM", 0x13},
350 {"AUIPC", 0x17},
351 {"OP_IMM_32", 0x1b},
352 /* 48b 0x1f. */
353
354 {"STORE", 0x23},
355 {"STORE_FP", 0x27},
356 {"CUSTOM_1", 0x2b},
357 {"AMO", 0x2f},
358 {"OP", 0x33},
359 {"LUI", 0x37},
360 {"OP_32", 0x3b},
361 /* 64b 0x3f. */
362
363 {"MADD", 0x43},
364 {"MSUB", 0x47},
365 {"NMADD", 0x4f},
366 {"NMSUB", 0x4b},
367 {"OP_FP", 0x53},
368 /*reserved 0x57. */
369 {"CUSTOM_2", 0x5b},
370 /* 48b 0x5f. */
371
372 {"BRANCH", 0x63},
373 {"JALR", 0x67},
374 /*reserved 0x5b. */
375 {"JAL", 0x6f},
376 {"SYSTEM", 0x73},
377 /*reserved 0x77. */
378 {"CUSTOM_3", 0x7b},
379 /* >80b 0x7f. */
380
381 {NULL, 0}
382};
383
384/* Hash table for lookup opcode name. */
385static struct hash_control *opcode_names_hash = NULL;
386
387/* Initialization for hash table of opcode name. */
388static void
389init_opcode_names_hash (void)
390{
391 const char *retval;
392 const struct opcode_name_t *opcode;
393
394 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
395 {
396 retval = hash_insert (opcode_names_hash, opcode->name, (void *)opcode);
397
398 if (retval != NULL)
399 as_fatal (_("internal error: can't hash `%s': %s"),
400 opcode->name, retval);
401 }
402}
403
404/* Find `s` is a valid opcode name or not,
405 return the opcode name info if found. */
406static const struct opcode_name_t *
407opcode_name_lookup (char **s)
408{
409 char *e;
410 char save_c;
411 struct opcode_name_t *o;
412
413 /* Find end of name. */
414 e = *s;
415 if (is_name_beginner (*e))
416 ++e;
417 while (is_part_of_name (*e))
418 ++e;
419
420 /* Terminate name. */
421 save_c = *e;
422 *e = '\0';
423
424 o = (struct opcode_name_t *) hash_find (opcode_names_hash, *s);
425
426 /* Advance to next token if one was recognized. */
427 if (o)
428 *s = e;
429
430 *e = save_c;
431 expr_end = e;
432
433 return o;
434}
435
e23eba97
NC		 436struct regname
437{
438 const char *name;
439 unsigned int num;
440};
441
442enum reg_class
443{
444 RCLASS_GPR,
445 RCLASS_FPR,
446 RCLASS_CSR,
447 RCLASS_MAX
448};
449
450static struct hash_control *reg_names_hash = NULL;
451
452#define ENCODE_REG_HASH(cls, n) \
453 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
454#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
455#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
456
457static void
458hash_reg_name (enum reg_class class, const char *name, unsigned n)
459{
460 void *hash = ENCODE_REG_HASH (class, n);
461 const char *retval = hash_insert (reg_names_hash, name, hash);
462
463 if (retval != NULL)
464 as_fatal (_("internal error: can't hash `%s': %s"), name, retval);
465}
466
467static void
468hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
469{
470 unsigned i;
471
472 for (i = 0; i < n; i++)
473 hash_reg_name (class, names[i], i);
474}
475
476static unsigned int
477reg_lookup_internal (const char *s, enum reg_class class)
478{
479 struct regname *r = (struct regname *) hash_find (reg_names_hash, s);
480
481 if (r == NULL || DECODE_REG_CLASS (r) != class)
482 return -1;
7f999549
JW		 483
484 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
485 return -1;
486
e23eba97
NC		 487 return DECODE_REG_NUM (r);
488}
489
490static bfd_boolean
491reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
492{
493 char *e;
494 char save_c;
495 int reg = -1;
496
497 /* Find end of name. */
498 e = *s;
499 if (is_name_beginner (*e))
500 ++e;
501 while (is_part_of_name (*e))
502 ++e;
503
504 /* Terminate name. */
505 save_c = *e;
506 *e = '\0';
507
508 /* Look for the register. Advance to next token if one was recognized. */
509 if ((reg = reg_lookup_internal (*s, class)) >= 0)
510 *s = e;
511
512 *e = save_c;
513 if (regnop)
514 *regnop = reg;
515 return reg >= 0;
516}
517
518static bfd_boolean
519arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
520{
521 const char *p = strchr (*s, ',');
522 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
523
bfb218e3
JW		 524 if (len == 0)
525 return FALSE;
526
e23eba97
NC		 527 for (i = 0; i < size; i++)
528 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
529 {
530 *regnop = i;
531 *s += len;
532 return TRUE;
533 }
534
535 return FALSE;
536}
537
538/* For consistency checking, verify that all bits are specified either
539 by the match/mask part of the instruction definition, or by the
0e35537d
JW		 540 operand list.
541
542 `length` could be 0, 4 or 8, 0 for auto detection. */
e23eba97 543static bfd_boolean
0e35537d 544validate_riscv_insn (const struct riscv_opcode *opc, int length)
e23eba97
NC		 545{
546 const char *p = opc->args;
547 char c;
548 insn_t used_bits = opc->mask;
0e35537d
JW		 549 int insn_width;
550 insn_t required_bits;
551
552 if (length == 0)
553 insn_width = 8 * riscv_insn_length (opc->match);
554 else
555 insn_width = 8 * length;
556
557 required_bits = ~0ULL >> (64 - insn_width);
e23eba97
NC		 558
559 if ((used_bits & opc->match) != (opc->match & required_bits))
560 {
561 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
562 opc->name, opc->args);
563 return FALSE;
564 }
565
566#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
567 while (*p)
568 switch (c = *p++)
569 {
570 case 'C': /* RVC */
571 switch (c = *p++)
572 {
1d65abb5 573 case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
e23eba97
NC		 574 case 'c': break; /* RS1, constrained to equal sp */
575 case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
1d65abb5 576 case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
b416fe87 577 case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
1d65abb5
AW		 578 case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
579 case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
580 case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
581 case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
582 case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
e23eba97
NC		 583 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
584 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
1d65abb5
AW		 585 case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
586 case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
e23eba97
NC		 587 case 'w': break; /* RS1S, constrained to equal RD */
588 case 'x': break; /* RS2S, constrained to equal RD */
ca0bc150 589 case 'z': break; /* RS2S, contrained to be x0 */
1d65abb5
AW		 590 case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
591 case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
592 case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
593 case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
e23eba97
NC		 594 case 'U': break; /* RS1, constrained to equal RD */
595 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1d65abb5
AW		 596 case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
597 case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
0e35537d
JW		 598 case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
599 case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
e23eba97
NC		 600 case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
601 case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
0e35537d
JW		 602 case 'F': /* funct */
603 switch (c = *p++)
604 {
4765cd61 605 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
0e35537d
JW		 606 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
607 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
4765cd61 608 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
0e35537d
JW		 609 default:
610 as_bad (_("internal: bad RISC-V opcode"
611 " (unknown operand type `CF%c'): %s %s"),
612 c, opc->name, opc->args);
613 return FALSE;
614 }
615 break;
e23eba97
NC		 616 default:
617 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
618 c, opc->name, opc->args);
619 return FALSE;
620 }
621 break;
622 case ',': break;
623 case '(': break;
624 case ')': break;
625 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
626 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
627 case 'A': break;
628 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
629 case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
630 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
631 case 'I': break;
632 case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
633 case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
634 case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */
635 case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
636 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
637 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
638 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
639 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
0e35537d 640 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
e23eba97
NC		 641 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
642 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
643 case 'o':
1d65abb5
AW		 644 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
645 case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
646 case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
647 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
648 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
e925c834 649 case 'z': break;
e23eba97
NC		 650 case '[': break;
651 case ']': break;
652 case '0': break;
f50fabe4 653 case '1': break;
0e35537d
JW		 654 case 'F': /* funct */
655 switch (c = *p++)
656 {
657 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
658 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
659 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
660 default:
661 as_bad (_("internal: bad RISC-V opcode"
662 " (unknown operand type `F%c'): %s %s"),
663 c, opc->name, opc->args);
664 return FALSE;
665 }
666 break;
667 case 'O': /* opcode */
668 switch (c = *p++)
669 {
670 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
671 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
672 default:
673 as_bad (_("internal: bad RISC-V opcode"
674 " (unknown operand type `F%c'): %s %s"),
675 c, opc->name, opc->args);
676 return FALSE;
677 }
678 break;
e23eba97
NC		 679 default:
680 as_bad (_("internal: bad RISC-V opcode "
681 "(unknown operand type `%c'): %s %s"),
682 c, opc->name, opc->args);
683 return FALSE;
684 }
685#undef USE_BITS
686 if (used_bits != required_bits)
687 {
688 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
689 ~(unsigned long)(used_bits & required_bits),
690 opc->name, opc->args);
691 return FALSE;
692 }
693 return TRUE;
694}
695
696struct percent_op_match
697{
698 const char *str;
699 bfd_reloc_code_real_type reloc;
700};
701
0e35537d
JW		 702/* Common hash table initialization function for
703 instruction and .insn directive. */
704static struct hash_control *
705init_opcode_hash (const struct riscv_opcode *opcodes,
706 bfd_boolean insn_directive_p)
e23eba97
NC		 707{
708 int i = 0;
0e35537d
JW		 709 int length;
710 struct hash_control *hash = hash_new ();
711 while (opcodes[i].name)
e23eba97 712 {
0e35537d 713 const char *name = opcodes[i].name;
e23eba97 714 const char *hash_error =
0e35537d 715 hash_insert (hash, name, (void *) &opcodes[i]);
e23eba97
NC		 716
717 if (hash_error)
718 {
719 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
0e35537d 720 opcodes[i].name, hash_error);
e23eba97
NC		 721 /* Probably a memory allocation problem? Give up now. */
722 as_fatal (_("Broken assembler. No assembly attempted."));
723 }
724
725 do
726 {
0e35537d 727 if (opcodes[i].pinfo != INSN_MACRO)
e23eba97 728 {
0e35537d
JW		 729 if (insn_directive_p)
730 length = ((name[0] == 'c') ? 2 : 4);
731 else
732 length = 0; /* Let assembler determine the length. */
733 if (!validate_riscv_insn (&opcodes[i], length))
e23eba97
NC		 734 as_fatal (_("Broken assembler. No assembly attempted."));
735 }
0e35537d
JW		 736 else
737 gas_assert (!insn_directive_p);
e23eba97
NC		 738 ++i;
739 }
0e35537d 740 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
e23eba97
NC		 741 }
742
0e35537d
JW		 743 return hash;
744}
745
746/* This function is called once, at assembler startup time. It should set up
747 all the tables, etc. that the MD part of the assembler will need. */
748
749void
750md_begin (void)
751{
752 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
753
754 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
755 as_warn (_("Could not set architecture and machine"));
756
757 op_hash = init_opcode_hash (riscv_opcodes, FALSE);
758 insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
759
e23eba97
NC		 760 reg_names_hash = hash_new ();
761 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
762 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
763 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
764 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
765
b9c04e5a
JW		 766 /* Add "fp" as an alias for "s0". */
767 hash_reg_name (RCLASS_GPR, "fp", 8);
768
0e35537d
JW		 769 opcode_names_hash = hash_new ();
770 init_opcode_names_hash ();
771
e23eba97 772#define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
1270b047 773#define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
e23eba97
NC		 774#include "opcode/riscv-opc.h"
775#undef DECLARE_CSR
776
777 /* Set the default alignment for the text section. */
778 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
779}
780
45f76423
AW		 781static insn_t
782riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
783{
784 switch (reloc_type)
785 {
786 case BFD_RELOC_32:
787 return value;
788
789 case BFD_RELOC_RISCV_HI20:
790 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
791
792 case BFD_RELOC_RISCV_LO12_S:
793 return ENCODE_STYPE_IMM (value);
794
795 case BFD_RELOC_RISCV_LO12_I:
796 return ENCODE_ITYPE_IMM (value);
797
798 default:
799 abort ();
800 }
801}
802
e23eba97
NC		 803/* Output an instruction. IP is the instruction information.
804 ADDRESS_EXPR is an operand of the instruction to be used with
805 RELOC_TYPE. */
806
807static void
808append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
809 bfd_reloc_code_real_type reloc_type)
810{
811 dwarf2_emit_insn (0);
812
813 if (reloc_type != BFD_RELOC_UNUSED)
814 {
815 reloc_howto_type *howto;
816
1d65abb5 817 gas_assert (address_expr);
e23eba97
NC		 818 if (reloc_type == BFD_RELOC_12_PCREL
819 || reloc_type == BFD_RELOC_RISCV_JMP)
820 {
821 int j = reloc_type == BFD_RELOC_RISCV_JMP;
822 int best_case = riscv_insn_length (ip->insn_opcode);
823 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
824 add_relaxed_insn (ip, worst_case, best_case,
825 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
826 address_expr->X_add_symbol,
827 address_expr->X_add_number);
828 return;
829 }
45f76423 830 else
e23eba97 831 {
45f76423
AW		 832 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
833 if (howto == NULL)
834 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
e23eba97 835
45f76423
AW		 836 ip->fixp = fix_new_exp (ip->frag, ip->where,
837 bfd_get_reloc_size (howto),
838 address_expr, FALSE, reloc_type);
e23eba97 839
45f76423 840 ip->fixp->fx_tcbit = riscv_opts.relax;
e23eba97 841 }
e23eba97
NC		 842 }
843
e23eba97
NC		 844 add_fixed_insn (ip);
845 install_insn (ip);
f77bb6c5
JW		 846
847 /* We need to start a new frag after any instruction that can be
848 optimized away or compressed by the linker during relaxation, to prevent
849 the assembler from computing static offsets across such an instruction.
850 This is necessary to get correct EH info. */
851 if (reloc_type == BFD_RELOC_RISCV_CALL
852 || reloc_type == BFD_RELOC_RISCV_CALL_PLT
853 || reloc_type == BFD_RELOC_RISCV_HI20
854 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
855 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
856 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
857 {
858 frag_wane (frag_now);
859 frag_new (0);
860 }
e23eba97
NC		 861}
862
863/* Build an instruction created by a macro expansion. This is passed
864 a pointer to the count of instructions created so far, an
865 expression, the name of the instruction to build, an operand format
866 string, and corresponding arguments. */
867
868static void
869macro_build (expressionS *ep, const char *name, const char *fmt, ...)
870{
871 const struct riscv_opcode *mo;
872 struct riscv_cl_insn insn;
873 bfd_reloc_code_real_type r;
874 va_list args;
875
876 va_start (args, fmt);
877
878 r = BFD_RELOC_UNUSED;
879 mo = (struct riscv_opcode *) hash_find (op_hash, name);
880 gas_assert (mo);
881
882 /* Find a non-RVC variant of the instruction. append_insn will compress
883 it if possible. */
884 while (riscv_insn_length (mo->match) < 4)
885 mo++;
886 gas_assert (strcmp (name, mo->name) == 0);
887
888 create_insn (&insn, mo);
889 for (;;)
890 {
891 switch (*fmt++)
892 {
893 case 'd':
894 INSERT_OPERAND (RD, insn, va_arg (args, int));
895 continue;
896
897 case 's':
898 INSERT_OPERAND (RS1, insn, va_arg (args, int));
899 continue;
900
901 case 't':
902 INSERT_OPERAND (RS2, insn, va_arg (args, int));
903 continue;
904
905 case '>':
906 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
907 continue;
908
909 case 'j':
910 case 'u':
911 case 'q':
912 gas_assert (ep != NULL);
913 r = va_arg (args, int);
914 continue;
915
916 case '\0':
917 break;
918 case ',':
919 continue;
920 default:
921 as_fatal (_("internal error: invalid macro"));
922 }
923 break;
924 }
925 va_end (args);
926 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
927
928 append_insn (&insn, ep, r);
929}
930
931/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
932 unset. */
933static void
934normalize_constant_expr (expressionS *ex)
935{
936 if (xlen > 32)
937 return;
938 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
939 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
940 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
941 - 0x80000000);
942}
943
ca2fd32c
JW		 944/* Fail if an expression EX is not a constant. IP is the instruction using EX.
945 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
e23eba97
NC		 946
947static void
ca2fd32c
JW		 948check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
949 bfd_boolean maybe_csr)
e23eba97
NC		 950{
951 if (ex->X_op == O_big)
952 as_bad (_("unsupported large constant"));
ca2fd32c
JW		 953 else if (maybe_csr && ex->X_op == O_symbol)
954 as_bad (_("unknown CSR `%s'"),
955 S_GET_NAME (ex->X_add_symbol));
e23eba97
NC		 956 else if (ex->X_op != O_constant)
957 as_bad (_("Instruction %s requires absolute expression"),
958 ip->insn_mo->name);
959 normalize_constant_expr (ex);
960}
961
962static symbolS *
963make_internal_label (void)
964{
965 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg,
1d65abb5 966 (valueT) frag_now_fix (), frag_now);
e23eba97
NC		 967}
968
969/* Load an entry from the GOT. */
970static void
971pcrel_access (int destreg, int tempreg, expressionS *ep,
972 const char *lo_insn, const char *lo_pattern,
973 bfd_reloc_code_real_type hi_reloc,
974 bfd_reloc_code_real_type lo_reloc)
975{
976 expressionS ep2;
977 ep2.X_op = O_symbol;
978 ep2.X_add_symbol = make_internal_label ();
979 ep2.X_add_number = 0;
980
981 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
982 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
983}
984
985static void
986pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
987 bfd_reloc_code_real_type hi_reloc,
988 bfd_reloc_code_real_type lo_reloc)
989{
990 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
991}
992
993static void
994pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
995 bfd_reloc_code_real_type hi_reloc,
996 bfd_reloc_code_real_type lo_reloc)
997{
998 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
999}
1000
1001/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1002static void
1003riscv_call (int destreg, int tempreg, expressionS *ep,
1004 bfd_reloc_code_real_type reloc)
1005{
1006 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1007 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
1008}
1009
1010/* Load an integer constant into a register. */
1011
1012static void
1013load_const (int reg, expressionS *ep)
1014{
1015 int shift = RISCV_IMM_BITS;
1016 expressionS upper = *ep, lower = *ep;
1017 lower.X_add_number = (int32_t) ep->X_add_number << (32-shift) >> (32-shift);
1018 upper.X_add_number -= lower.X_add_number;
1019
1020 if (ep->X_op != O_constant)
1021 {
1022 as_bad (_("unsupported large constant"));
1023 return;
1024 }
1025
1d65abb5 1026 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
e23eba97
NC		 1027 {
1028 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1029 while (((upper.X_add_number >> shift) & 1) == 0)
1030 shift++;
1031
1032 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1d65abb5 1033 load_const (reg, &upper);
e23eba97
NC		 1034
1035 macro_build (NULL, "slli", "d,s,>", reg, reg, shift);
1036 if (lower.X_add_number != 0)
1037 macro_build (&lower, "addi", "d,s,j", reg, reg, BFD_RELOC_RISCV_LO12_I);
1038 }
1039 else
1040 {
1041 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1042 int hi_reg = 0;
1043
1044 if (upper.X_add_number != 0)
1045 {
1046 macro_build (ep, "lui", "d,u", reg, BFD_RELOC_RISCV_HI20);
1047 hi_reg = reg;
1048 }
1049
1050 if (lower.X_add_number != 0 || hi_reg == 0)
1051 macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg,
1052 BFD_RELOC_RISCV_LO12_I);
1053 }
1054}
1055
1056/* Expand RISC-V assembly macros into one or more instructions. */
1057static void
1058macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1059 bfd_reloc_code_real_type *imm_reloc)
1060{
1061 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1062 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1063 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1064 int mask = ip->insn_mo->mask;
1065
1066 switch (mask)
1067 {
1068 case M_LI:
1069 load_const (rd, imm_expr);
1070 break;
1071
1072 case M_LA:
1073 case M_LLA:
1074 /* Load the address of a symbol into a register. */
1075 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1076 as_bad (_("offset too large"));
1077
1078 if (imm_expr->X_op == O_constant)
1079 load_const (rd, imm_expr);
1080 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */
1081 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1082 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1083 else /* Local PIC symbol, or any non-PIC symbol */
1084 pcrel_load (rd, rd, imm_expr, "addi",
1085 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1086 break;
1087
1088 case M_LA_TLS_GD:
1089 pcrel_load (rd, rd, imm_expr, "addi",
1090 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1091 break;
1092
1093 case M_LA_TLS_IE:
1094 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1095 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1096 break;
1097
1098 case M_LB:
1099 pcrel_load (rd, rd, imm_expr, "lb",
1100 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1101 break;
1102
1103 case M_LBU:
1104 pcrel_load (rd, rd, imm_expr, "lbu",
1105 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1106 break;
1107
1108 case M_LH:
1109 pcrel_load (rd, rd, imm_expr, "lh",
1110 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1111 break;
1112
1113 case M_LHU:
1114 pcrel_load (rd, rd, imm_expr, "lhu",
1115 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1116 break;
1117
1118 case M_LW:
1119 pcrel_load (rd, rd, imm_expr, "lw",
1120 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1121 break;
1122
1123 case M_LWU:
1124 pcrel_load (rd, rd, imm_expr, "lwu",
1125 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1126 break;
1127
1128 case M_LD:
1129 pcrel_load (rd, rd, imm_expr, "ld",
1130 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1131 break;
1132
1133 case M_FLW:
1134 pcrel_load (rd, rs1, imm_expr, "flw",
1135 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1136 break;
1137
1138 case M_FLD:
1139 pcrel_load (rd, rs1, imm_expr, "fld",
1140 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1141 break;
1142
1143 case M_SB:
1144 pcrel_store (rs2, rs1, imm_expr, "sb",
1145 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1146 break;
1147
1148 case M_SH:
1149 pcrel_store (rs2, rs1, imm_expr, "sh",
1150 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1151 break;
1152
1153 case M_SW:
1154 pcrel_store (rs2, rs1, imm_expr, "sw",
1155 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1156 break;
1157
1158 case M_SD:
1159 pcrel_store (rs2, rs1, imm_expr, "sd",
1160 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1161 break;
1162
1163 case M_FSW:
1164 pcrel_store (rs2, rs1, imm_expr, "fsw",
1165 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1166 break;
1167
1168 case M_FSD:
1169 pcrel_store (rs2, rs1, imm_expr, "fsd",
1170 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1171 break;
1172
1173 case M_CALL:
1174 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1175 break;
1176
1177 default:
1178 as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
1179 break;
1180 }
1181}
1182
1183static const struct percent_op_match percent_op_utype[] =
1184{
1185 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1186 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
1187 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1188 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1189 {"%hi", BFD_RELOC_RISCV_HI20},
1190 {0, 0}
1191};
1192
1193static const struct percent_op_match percent_op_itype[] =
1194{
1195 {"%lo", BFD_RELOC_RISCV_LO12_I},
1196 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1197 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1198 {0, 0}
1199};
1200
1201static const struct percent_op_match percent_op_stype[] =
1202{
1203 {"%lo", BFD_RELOC_RISCV_LO12_S},
1204 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1205 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1206 {0, 0}
1207};
1208
1209static const struct percent_op_match percent_op_rtype[] =
1210{
1211 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1212 {0, 0}
1213};
1214
f50fabe4
JW		 1215static const struct percent_op_match percent_op_null[] =
1216{
1217 {0, 0}
1218};
1219
e23eba97
NC		 1220/* Return true if *STR points to a relocation operator. When returning true,
1221 move *STR over the operator and store its relocation code in *RELOC.
1222 Leave both *STR and *RELOC alone when returning false. */
1223
1224static bfd_boolean
1225parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1226 const struct percent_op_match *percent_op)
1227{
1228 for ( ; percent_op->str; percent_op++)
1229 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1230 {
1231 int len = strlen (percent_op->str);
1232
1233 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1234 continue;
1235
1236 *str += strlen (percent_op->str);
1237 *reloc = percent_op->reloc;
1238
1239 /* Check whether the output BFD supports this relocation.
1240 If not, issue an error and fall back on something safe. */
45f76423
AW		 1241 if (*reloc != BFD_RELOC_UNUSED
1242 && !bfd_reloc_type_lookup (stdoutput, *reloc))
e23eba97
NC		 1243 {
1244 as_bad ("relocation %s isn't supported by the current ABI",
1245 percent_op->str);
1246 *reloc = BFD_RELOC_UNUSED;
1247 }
1248 return TRUE;
1249 }
1250 return FALSE;
1251}
1252
1253static void
1254my_getExpression (expressionS *ep, char *str)
1255{
1256 char *save_in;
1257
1258 save_in = input_line_pointer;
1259 input_line_pointer = str;
1260 expression (ep);
1261 expr_end = input_line_pointer;
1262 input_line_pointer = save_in;
1263}
1264
1265/* Parse string STR as a 16-bit relocatable operand. Store the
1266 expression in *EP and the relocation, if any, in RELOC.
1267 Return the number of relocation operators used (0 or 1).
1268
1269 On exit, EXPR_END points to the first character after the expression. */
1270
1271static size_t
1272my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1273 char *str, const struct percent_op_match *percent_op)
1274{
1275 size_t reloc_index;
1276 unsigned crux_depth, str_depth, regno;
1277 char *crux;
1278
8970c022
JW		 1279 /* First, check for integer registers. No callers can accept a reg, but
1280 we need to avoid accidentally creating a useless undefined symbol below,
1281 if this is an instruction pattern that can't match. A glibc build fails
1282 if this is removed. */
e23eba97
NC		 1283 if (reg_lookup (&str, RCLASS_GPR, &regno))
1284 {
1285 ep->X_op = O_register;
1286 ep->X_add_number = regno;
8970c022 1287 expr_end = str;
e23eba97
NC		 1288 return 0;
1289 }
1290
1291 /* Search for the start of the main expression.
1292 End the loop with CRUX pointing to the start
1293 of the main expression and with CRUX_DEPTH containing the number
1294 of open brackets at that point. */
1295 reloc_index = -1;
1296 str_depth = 0;
1297 do
1298 {
1299 reloc_index++;
1300 crux = str;
1301 crux_depth = str_depth;
1302
1303 /* Skip over whitespace and brackets, keeping count of the number
1304 of brackets. */
1305 while (*str == ' ' || *str == '\t' || *str == '(')
1306 if (*str++ == '(')
1307 str_depth++;
1308 }
1309 while (*str == '%'
1310 && reloc_index < 1
1311 && parse_relocation (&str, reloc, percent_op));
1312
1313 my_getExpression (ep, crux);
1314 str = expr_end;
1315
1316 /* Match every open bracket. */
1317 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1318 if (*str++ == ')')
1319 crux_depth--;
1320
1321 if (crux_depth > 0)
1322 as_bad ("unclosed '('");
1323
1324 expr_end = str;
1325
1326 return reloc_index;
1327}
1328
0e35537d
JW		 1329/* Parse opcode name, could be an mnemonics or number. */
1330static size_t
1331my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1332 char *str, const struct percent_op_match *percent_op)
1333{
1334 const struct opcode_name_t *o = opcode_name_lookup (&str);
1335
1336 if (o != NULL)
1337 {
1338 ep->X_op = O_constant;
1339 ep->X_add_number = o->val;
1340 return 0;
1341 }
1342
1343 return my_getSmallExpression (ep, reloc, str, percent_op);
1344}
1345
f0531ed6
JW		 1346/* Detect and handle implicitly zero load-store offsets. For example,
1347 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1348 an implicit offset was detected. */
1349
1350static bfd_boolean
89424b1d 1351riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
f0531ed6
JW		 1352{
1353 /* Check whether there is only a single bracketed expression left.
1354 If so, it must be the base register and the constant must be zero. */
1355 if (*s == '(' && strchr (s + 1, '(') == 0)
1356 {
89424b1d
MR		 1357 ep->X_op = O_constant;
1358 ep->X_add_number = 0;
f0531ed6
JW		 1359 return TRUE;
1360 }
1361
1362 return FALSE;
1363}
1364
e23eba97
NC		 1365/* This routine assembles an instruction into its binary format. As a
1366 side effect, it sets the global variable imm_reloc to the type of
1367 relocation to do if one of the operands is an address expression. */
1368
1369static const char *
1370riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
0e35537d 1371 bfd_reloc_code_real_type *imm_reloc, struct hash_control *hash)
e23eba97
NC		 1372{
1373 char *s;
1374 const char *args;
1375 char c = 0;
1376 struct riscv_opcode *insn;
1377 char *argsStart;
1378 unsigned int regno;
1379 char save_c = 0;
1380 int argnum;
1381 const struct percent_op_match *p;
1382 const char *error = "unrecognized opcode";
1383
1384 /* Parse the name of the instruction. Terminate the string if whitespace
1385 is found so that hash_find only sees the name part of the string. */
1386 for (s = str; *s != '\0'; ++s)
1387 if (ISSPACE (*s))
1388 {
1389 save_c = *s;
1390 *s++ = '\0';
1391 break;
1392 }
1393
0e35537d 1394 insn = (struct riscv_opcode *) hash_find (hash, str);
e23eba97
NC		 1395
1396 argsStart = s;
1397 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1398 {
1080bf78
JW		 1399 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
1400 continue;
1401
1402 if (!riscv_multi_subset_supports (insn->subset))
e23eba97
NC		 1403 continue;
1404
1405 create_insn (ip, insn);
1406 argnum = 1;
1407
1408 imm_expr->X_op = O_absent;
1409 *imm_reloc = BFD_RELOC_UNUSED;
1410 p = percent_op_itype;
1411
1412 for (args = insn->args;; ++args)
1413 {
1414 s += strspn (s, " \t");
1415 switch (*args)
1416 {
1417 case '\0': /* End of args. */
1418 if (insn->pinfo != INSN_MACRO)
1419 {
1420 if (!insn->match_func (insn, ip->insn_opcode))
1421 break;
0e35537d
JW		 1422
1423 /* For .insn, insn->match and insn->mask are 0. */
1424 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
1425 ? ip->insn_opcode
1426 : insn->match) == 2
1427 && !riscv_opts.rvc)
e23eba97
NC		 1428 break;
1429 }
1430 if (*s != '\0')
1431 break;
1432 /* Successful assembly. */
1433 error = NULL;
1434 goto out;
1435
1436 case 'C': /* RVC */
1437 switch (*++args)
1438 {
1439 case 's': /* RS1 x8-x15 */
1440 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1441 || !(regno >= 8 && regno <= 15))
1442 break;
1443 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1444 continue;
1445 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1446 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1447 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
1448 break;
1449 continue;
1450 case 't': /* RS2 x8-x15 */
1451 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1452 || !(regno >= 8 && regno <= 15))
1453 break;
1454 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1455 continue;
1456 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1457 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1458 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
1459 break;
1460 continue;
1461 case 'U': /* RS1, constrained to equal RD. */
1462 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1463 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
1464 break;
1465 continue;
1466 case 'V': /* RS2 */
1467 if (!reg_lookup (&s, RCLASS_GPR, &regno))
1468 break;
1469 INSERT_OPERAND (CRS2, *ip, regno);
1470 continue;
1471 case 'c': /* RS1, constrained to equal sp. */
1472 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1473 || regno != X_SP)
1474 break;
1475 continue;
ca0bc150
JW		 1476 case 'z': /* RS2, contrained to equal x0. */
1477 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1478 || regno != 0)
1479 break;
1480 continue;
e23eba97
NC		 1481 case '>':
1482 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1483 || imm_expr->X_op != O_constant
1484 || imm_expr->X_add_number <= 0
1485 || imm_expr->X_add_number >= 64)
1486 break;
1487 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1488rvc_imm_done:
1489 s = expr_end;
1490 imm_expr->X_op = O_absent;
1491 continue;
1492 case '<':
1493 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1494 || imm_expr->X_op != O_constant
1495 || !VALID_RVC_IMM (imm_expr->X_add_number)
1496 || imm_expr->X_add_number <= 0
1497 || imm_expr->X_add_number >= 32)
1498 break;
1499 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1500 goto rvc_imm_done;
0e35537d
JW		 1501 case '8':
1502 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1503 || imm_expr->X_op != O_constant
1504 || !VALID_RVC_UIMM8 (imm_expr->X_add_number)
1505 || imm_expr->X_add_number < 0
1506 || imm_expr->X_add_number >= 256)
1507 break;
1508 ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
1509 goto rvc_imm_done;
e23eba97
NC		 1510 case 'i':
1511 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1512 || imm_expr->X_op != O_constant
1513 || imm_expr->X_add_number == 0
1514 || !VALID_RVC_SIMM3 (imm_expr->X_add_number))
1515 break;
1516 ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
1517 goto rvc_imm_done;
1518 case 'j':
1519 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1520 || imm_expr->X_op != O_constant
1521 || imm_expr->X_add_number == 0
1522 || !VALID_RVC_IMM (imm_expr->X_add_number))
1523 break;
1524 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1525 goto rvc_imm_done;
1526 case 'k':
f0531ed6
JW		 1527 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1528 continue;
e23eba97
NC		 1529 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1530 || imm_expr->X_op != O_constant
1531 || !VALID_RVC_LW_IMM (imm_expr->X_add_number))
1532 break;
1533 ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
1534 goto rvc_imm_done;
1535 case 'l':
f0531ed6
JW		 1536 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1537 continue;
e23eba97
NC		 1538 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1539 || imm_expr->X_op != O_constant
1540 || !VALID_RVC_LD_IMM (imm_expr->X_add_number))
1541 break;
1542 ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
1543 goto rvc_imm_done;
1544 case 'm':
f0531ed6
JW		 1545 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1546 continue;
e23eba97
NC		 1547 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1548 || imm_expr->X_op != O_constant
1549 || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number))
1550 break;
1551 ip->insn_opcode |=
1552 ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
1553 goto rvc_imm_done;
1554 case 'n':
f0531ed6
JW		 1555 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1556 continue;
e23eba97
NC		 1557 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1558 || imm_expr->X_op != O_constant
1559 || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number))
1560 break;
1561 ip->insn_opcode |=
1562 ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
1563 goto rvc_imm_done;
b416fe87
KC		 1564 case 'o':
1565 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1566 || imm_expr->X_op != O_constant
21a186f2
JW		 1567 /* C.addiw, c.li, and c.andi allow zero immediate.
1568 C.addi allows zero immediate as hint. Otherwise this
1569 is same as 'j'. */
b416fe87
KC		 1570 || !VALID_RVC_IMM (imm_expr->X_add_number))
1571 break;
1572 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1573 goto rvc_imm_done;
e23eba97
NC		 1574 case 'K':
1575 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1576 || imm_expr->X_op != O_constant
1577 || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number)
1578 || imm_expr->X_add_number == 0)
1579 break;
1580 ip->insn_opcode |=
1581 ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
1582 goto rvc_imm_done;
1583 case 'L':
1584 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1585 || imm_expr->X_op != O_constant
1586 || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number)
1587 || imm_expr->X_add_number == 0)
1588 break;
1589 ip->insn_opcode |=
1590 ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
1591 goto rvc_imm_done;
1592 case 'M':
f0531ed6
JW		 1593 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1594 continue;
e23eba97
NC		 1595 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1596 || imm_expr->X_op != O_constant
1597 || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number))
1598 break;
1599 ip->insn_opcode |=
1600 ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
1601 goto rvc_imm_done;
1602 case 'N':
f0531ed6
JW		 1603 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1604 continue;
e23eba97
NC		 1605 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1606 || imm_expr->X_op != O_constant
1607 || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number))
1608 break;
1609 ip->insn_opcode |=
1610 ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
1611 goto rvc_imm_done;
1612 case 'u':
1613 p = percent_op_utype;
1614 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
1615 break;
1616rvc_lui:
1617 if (imm_expr->X_op != O_constant
1618 || imm_expr->X_add_number <= 0
1619 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
1620 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
1621 && (imm_expr->X_add_number <
1622 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
1623 break;
1624 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1625 goto rvc_imm_done;
1626 case 'v':
1627 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1628 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
1629 || ((int32_t)imm_expr->X_add_number
1630 != imm_expr->X_add_number))
1631 break;
1632 imm_expr->X_add_number =
1633 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
1634 goto rvc_lui;
1635 case 'p':
1636 goto branch;
1637 case 'a':
1638 goto jump;
0e35537d
JW		 1639 case 'S': /* Floating-point RS1 x8-x15. */
1640 if (!reg_lookup (&s, RCLASS_FPR, &regno)
1641 || !(regno >= 8 && regno <= 15))
1642 break;
1643 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1644 continue;
e23eba97
NC		 1645 case 'D': /* Floating-point RS2 x8-x15. */
1646 if (!reg_lookup (&s, RCLASS_FPR, &regno)
1647 || !(regno >= 8 && regno <= 15))
1648 break;
1649 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1650 continue;
1651 case 'T': /* Floating-point RS2. */
1652 if (!reg_lookup (&s, RCLASS_FPR, &regno))
1653 break;
1654 INSERT_OPERAND (CRS2, *ip, regno);
1655 continue;
0e35537d
JW		 1656 case 'F':
1657 switch (*++args)
1658 {
4765cd61
JW		 1659 case '6':
1660 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1661 || imm_expr->X_op != O_constant
1662 || imm_expr->X_add_number < 0
1663 || imm_expr->X_add_number >= 64)
1664 {
1665 as_bad (_("bad value for funct6 field, "
1666 "value must be 0...64"));
1667 break;
1668 }
1669
1670 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
1671 imm_expr->X_op = O_absent;
1672 s = expr_end;
1673 continue;
0e35537d
JW		 1674 case '4':
1675 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1676 || imm_expr->X_op != O_constant
1677 || imm_expr->X_add_number < 0
1678 || imm_expr->X_add_number >= 16)
1679 {
1680 as_bad (_("bad value for funct4 field, "
1681 "value must be 0...15"));
1682 break;
1683 }
1684
1685 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
1686 imm_expr->X_op = O_absent;
1687 s = expr_end;
1688 continue;
1689 case '3':
1690 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1691 || imm_expr->X_op != O_constant
1692 || imm_expr->X_add_number < 0
1693 || imm_expr->X_add_number >= 8)
1694 {
1695 as_bad (_("bad value for funct3 field, "
1696 "value must be 0...7"));
1697 break;
1698 }
1699 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
1700 imm_expr->X_op = O_absent;
1701 s = expr_end;
1702 continue;
4765cd61
JW		 1703 case '2':
1704 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1705 || imm_expr->X_op != O_constant
1706 || imm_expr->X_add_number < 0
1707 || imm_expr->X_add_number >= 4)
1708 {
1709 as_bad (_("bad value for funct2 field, "
1710 "value must be 0...3"));
1711 break;
1712 }
1713 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number);
1714 imm_expr->X_op = O_absent;
1715 s = expr_end;
1716 continue;
0e35537d
JW		 1717 default:
1718 as_bad (_("bad compressed FUNCT field"
1719 " specifier 'CF%c'\n"),
1720 *args);
1721 }
1722 break;
1723
e23eba97
NC		 1724 default:
1725 as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
1726 }
1727 break;
1728
1729 case ',':
1730 ++argnum;
1731 if (*s++ == *args)
1732 continue;
1733 s--;
1734 break;
1735
1736 case '(':
1737 case ')':
1738 case '[':
1739 case ']':
1740 if (*s++ == *args)
1741 continue;
1742 break;
1743
1744 case '<': /* Shift amount, 0 - 31. */
1745 my_getExpression (imm_expr, s);
ca2fd32c 1746 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 1747 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 1748 as_bad (_("Improper shift amount (%lu)"),
1749 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 1750 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
1751 imm_expr->X_op = O_absent;
1752 s = expr_end;
1753 continue;
1754
1755 case '>': /* Shift amount, 0 - (XLEN-1). */
1756 my_getExpression (imm_expr, s);
ca2fd32c 1757 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 1758 if ((unsigned long) imm_expr->X_add_number >= xlen)
94f78a77
AW		 1759 as_bad (_("Improper shift amount (%lu)"),
1760 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 1761 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
1762 imm_expr->X_op = O_absent;
1763 s = expr_end;
1764 continue;
1765
1766 case 'Z': /* CSRRxI immediate. */
1767 my_getExpression (imm_expr, s);
ca2fd32c 1768 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 1769 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 1770 as_bad (_("Improper CSRxI immediate (%lu)"),
1771 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 1772 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
1773 imm_expr->X_op = O_absent;
1774 s = expr_end;
1775 continue;
1776
1777 case 'E': /* Control register. */
1778 if (reg_lookup (&s, RCLASS_CSR, &regno))
1779 INSERT_OPERAND (CSR, *ip, regno);
1780 else
1781 {
1782 my_getExpression (imm_expr, s);
ca2fd32c 1783 check_absolute_expr (ip, imm_expr, TRUE);
e23eba97 1784 if ((unsigned long) imm_expr->X_add_number > 0xfff)
94f78a77
AW		 1785 as_bad (_("Improper CSR address (%lu)"),
1786 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 1787 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
1788 imm_expr->X_op = O_absent;
1789 s = expr_end;
1790 }
1791 continue;
1792
1793 case 'm': /* Rounding mode. */
1794 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
1795 {
1796 INSERT_OPERAND (RM, *ip, regno);
1797 continue;
1798 }
1799 break;
1800
1801 case 'P':
1802 case 'Q': /* Fence predecessor/successor. */
1803 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
1804 &regno))
1805 {
1806 if (*args == 'P')
1807 INSERT_OPERAND (PRED, *ip, regno);
1808 else
1809 INSERT_OPERAND (SUCC, *ip, regno);
1810 continue;
1811 }
1812 break;
1813
1814 case 'd': /* Destination register. */
1815 case 's': /* Source register. */
1816 case 't': /* Target register. */
0e35537d 1817 case 'r': /* rs3. */
e23eba97
NC		 1818 if (reg_lookup (&s, RCLASS_GPR, &regno))
1819 {
1820 c = *args;
1821 if (*s == ' ')
1822 ++s;
1823
1824 /* Now that we have assembled one operand, we use the args
1825 string to figure out where it goes in the instruction. */
1826 switch (c)
1827 {
1828 case 's':
1829 INSERT_OPERAND (RS1, *ip, regno);
1830 break;
1831 case 'd':
1832 INSERT_OPERAND (RD, *ip, regno);
1833 break;
1834 case 't':
1835 INSERT_OPERAND (RS2, *ip, regno);
1836 break;
0e35537d
JW		 1837 case 'r':
1838 INSERT_OPERAND (RS3, *ip, regno);
1839 break;
e23eba97
NC		 1840 }
1841 continue;
1842 }
1843 break;
1844
1845 case 'D': /* Floating point rd. */
1846 case 'S': /* Floating point rs1. */
1847 case 'T': /* Floating point rs2. */
1848 case 'U': /* Floating point rs1 and rs2. */
1849 case 'R': /* Floating point rs3. */
1850 if (reg_lookup (&s, RCLASS_FPR, &regno))
1851 {
1852 c = *args;
1853 if (*s == ' ')
1854 ++s;
1855 switch (c)
1856 {
1857 case 'D':
1858 INSERT_OPERAND (RD, *ip, regno);
1859 break;
1860 case 'S':
1861 INSERT_OPERAND (RS1, *ip, regno);
1862 break;
1863 case 'U':
1864 INSERT_OPERAND (RS1, *ip, regno);
1865 /* fallthru */
1866 case 'T':
1867 INSERT_OPERAND (RS2, *ip, regno);
1868 break;
1869 case 'R':
1870 INSERT_OPERAND (RS3, *ip, regno);
1871 break;
1872 }
1873 continue;
1874 }
1875
1876 break;
1877
1878 case 'I':
1879 my_getExpression (imm_expr, s);
1880 if (imm_expr->X_op != O_big
1881 && imm_expr->X_op != O_constant)
1882 break;
1883 normalize_constant_expr (imm_expr);
1884 s = expr_end;
1885 continue;
1886
1887 case 'A':
1888 my_getExpression (imm_expr, s);
1889 normalize_constant_expr (imm_expr);
1890 /* The 'A' format specifier must be a symbol. */
1891 if (imm_expr->X_op != O_symbol)
1892 break;
1893 *imm_reloc = BFD_RELOC_32;
1894 s = expr_end;
1895 continue;
1896
160d1b3d
SH		 1897 case 'B':
1898 my_getExpression (imm_expr, s);
1899 normalize_constant_expr (imm_expr);
1900 /* The 'B' format specifier must be a symbol or a constant. */
1901 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
1902 break;
1903 if (imm_expr->X_op == O_symbol)
1904 *imm_reloc = BFD_RELOC_32;
1905 s = expr_end;
1906 continue;
1907
e23eba97 1908 case 'j': /* Sign-extended immediate. */
e23eba97 1909 p = percent_op_itype;
f50fabe4 1910 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
e23eba97
NC		 1911 goto alu_op;
1912 case 'q': /* Store displacement. */
1913 p = percent_op_stype;
1914 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
1915 goto load_store;
1916 case 'o': /* Load displacement. */
1917 p = percent_op_itype;
1918 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
1919 goto load_store;
f50fabe4 1920 case '1': /* 4-operand add, must be %tprel_add. */
e23eba97 1921 p = percent_op_rtype;
f50fabe4
JW		 1922 goto alu_op;
1923 case '0': /* AMO "displacement," which must be zero. */
1924 p = percent_op_null;
e23eba97 1925load_store:
f0531ed6 1926 if (riscv_handle_implicit_zero_offset (imm_expr, s))
e23eba97
NC		 1927 continue;
1928alu_op:
1929 /* If this value won't fit into a 16 bit offset, then go
1930 find a macro that will generate the 32 bit offset
1931 code pattern. */
1932 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
1933 {
1934 normalize_constant_expr (imm_expr);
1935 if (imm_expr->X_op != O_constant
1936 || (*args == '0' && imm_expr->X_add_number != 0)
f50fabe4 1937 || (*args == '1')
e23eba97
NC		 1938 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
1939 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
1940 break;
1941 }
1942
1943 s = expr_end;
1944 continue;
1945
1946 case 'p': /* PC-relative offset. */
1947branch:
1948 *imm_reloc = BFD_RELOC_12_PCREL;
1949 my_getExpression (imm_expr, s);
1950 s = expr_end;
1951 continue;
1952
1953 case 'u': /* Upper 20 bits. */
1954 p = percent_op_utype;
4288405d 1955 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
e23eba97 1956 {
4288405d
JW		 1957 if (imm_expr->X_op != O_constant)
1958 break;
1959
e23eba97
NC		 1960 if (imm_expr->X_add_number < 0
1961 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
1962 as_bad (_("lui expression not in range 0..1048575"));
1963
1964 *imm_reloc = BFD_RELOC_RISCV_HI20;
1965 imm_expr->X_add_number <<= RISCV_IMM_BITS;
1966 }
1967 s = expr_end;
1968 continue;
1969
1970 case 'a': /* 20-bit PC-relative offset. */
1971jump:
1972 my_getExpression (imm_expr, s);
1973 s = expr_end;
1974 *imm_reloc = BFD_RELOC_RISCV_JMP;
1975 continue;
1976
1977 case 'c':
1978 my_getExpression (imm_expr, s);
1979 s = expr_end;
1980 if (strcmp (s, "@plt") == 0)
1981 {
1982 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
1983 s += 4;
1984 }
1985 else
1986 *imm_reloc = BFD_RELOC_RISCV_CALL;
1987 continue;
0e35537d
JW		 1988 case 'O':
1989 switch (*++args)
1990 {
1991 case '4':
1992 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
1993 || imm_expr->X_op != O_constant
1994 || imm_expr->X_add_number < 0
1995 || imm_expr->X_add_number >= 128
1996 || (imm_expr->X_add_number & 0x3) != 3)
1997 {
1998 as_bad (_("bad value for opcode field, "
1999 "value must be 0...127 and "
2000 "lower 2 bits must be 0x3"));
2001 break;
2002 }
2003
2004 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2005 imm_expr->X_op = O_absent;
2006 s = expr_end;
2007 continue;
2008 case '2':
2009 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2010 || imm_expr->X_op != O_constant
2011 || imm_expr->X_add_number < 0
2012 || imm_expr->X_add_number >= 3)
2013 {
2014 as_bad (_("bad value for opcode field, "
2015 "value must be 0...2"));
2016 break;
2017 }
2018
2019 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2020 imm_expr->X_op = O_absent;
2021 s = expr_end;
2022 continue;
2023 default:
2024 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args);
2025 }
2026 break;
2027
2028 case 'F':
2029 switch (*++args)
2030 {
2031 case '7':
2032 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2033 || imm_expr->X_op != O_constant
2034 || imm_expr->X_add_number < 0
2035 || imm_expr->X_add_number >= 128)
2036 {
2037 as_bad (_("bad value for funct7 field, "
2038 "value must be 0...127"));
2039 break;
2040 }
2041
2042 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2043 imm_expr->X_op = O_absent;
2044 s = expr_end;
2045 continue;
2046 case '3':
2047 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2048 || imm_expr->X_op != O_constant
2049 || imm_expr->X_add_number < 0
2050 || imm_expr->X_add_number >= 8)
2051 {
2052 as_bad (_("bad value for funct3 field, "
2053 "value must be 0...7"));
2054 break;
2055 }
2056
2057 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2058 imm_expr->X_op = O_absent;
2059 s = expr_end;
2060 continue;
2061 case '2':
2062 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2063 || imm_expr->X_op != O_constant
2064 || imm_expr->X_add_number < 0
2065 || imm_expr->X_add_number >= 4)
2066 {
2067 as_bad (_("bad value for funct2 field, "
2068 "value must be 0...3"));
2069 break;
2070 }
2071
2072 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2073 imm_expr->X_op = O_absent;
2074 s = expr_end;
2075 continue;
2076
2077 default:
2078 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args);
2079 }
2080 break;
e23eba97 2081
e925c834
JW		 2082 case 'z':
2083 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2084 || imm_expr->X_op != O_constant
2085 || imm_expr->X_add_number != 0)
2086 break;
2087 s = expr_end;
2088 imm_expr->X_op = O_absent;
2089 continue;
2090
e23eba97
NC		 2091 default:
2092 as_fatal (_("internal error: bad argument type %c"), *args);
2093 }
2094 break;
2095 }
2096 s = argsStart;
2097 error = _("illegal operands");
2098 }
2099
2100out:
2101 /* Restore the character we might have clobbered above. */
2102 if (save_c)
2103 *(argsStart - 1) = save_c;
2104
2105 return error;
2106}
2107
2108void
2109md_assemble (char *str)
2110{
2111 struct riscv_cl_insn insn;
2112 expressionS imm_expr;
2113 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2114
0e35537d 2115 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
e23eba97 2116
2dc8dd17
JW		 2117 start_assemble = TRUE;
2118
e23eba97
NC		 2119 if (error)
2120 {
2121 as_bad ("%s `%s'", error, str);
2122 return;
2123 }
2124
2125 if (insn.insn_mo->pinfo == INSN_MACRO)
2126 macro (&insn, &imm_expr, &imm_reloc);
2127 else
2128 append_insn (&insn, &imm_expr, imm_reloc);
2129}
2130
2131const char *
2132md_atof (int type, char *litP, int *sizeP)
2133{
2134 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2135}
2136
2137void
2138md_number_to_chars (char *buf, valueT val, int n)
2139{
2140 number_to_chars_littleendian (buf, val, n);
2141}
2142
2143const char *md_shortopts = "O::g::G:";
2144
2145enum options
2146{
2922d21d 2147 OPTION_MARCH = OPTION_MD_BASE,
e23eba97
NC		 2148 OPTION_PIC,
2149 OPTION_NO_PIC,
2922d21d 2150 OPTION_MABI,
71060565
JW		 2151 OPTION_RELAX,
2152 OPTION_NO_RELAX,
2dc8dd17
JW		 2153 OPTION_ARCH_ATTR,
2154 OPTION_NO_ARCH_ATTR,
e23eba97
NC		 2155 OPTION_END_OF_ENUM
2156};
2157
2158struct option md_longopts[] =
2159{
e23eba97
NC		 2160 {"march", required_argument, NULL, OPTION_MARCH},
2161 {"fPIC", no_argument, NULL, OPTION_PIC},
2162 {"fpic", no_argument, NULL, OPTION_PIC},
2163 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2922d21d 2164 {"mabi", required_argument, NULL, OPTION_MABI},
71060565
JW		 2165 {"mrelax", no_argument, NULL, OPTION_RELAX},
2166 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2dc8dd17
JW		 2167 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
2168 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
e23eba97
NC		 2169
2170 {NULL, no_argument, NULL, 0}
2171};
2172size_t md_longopts_size = sizeof (md_longopts);
2173
2922d21d
AW		 2174enum float_abi {
2175 FLOAT_ABI_DEFAULT = -1,
2176 FLOAT_ABI_SOFT,
2177 FLOAT_ABI_SINGLE,
2178 FLOAT_ABI_DOUBLE,
2179 FLOAT_ABI_QUAD
e23eba97 2180};
2922d21d
AW		 2181static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
2182
2183static void
7f999549 2184riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
2922d21d
AW		 2185{
2186 abi_xlen = new_xlen;
2187 float_abi = new_float_abi;
7f999549 2188 rve_abi = rve;
2922d21d 2189}
e23eba97
NC		 2190
2191int
2192md_parse_option (int c, const char *arg)
2193{
2194 switch (c)
2195 {
e23eba97
NC		 2196 case OPTION_MARCH:
2197 riscv_set_arch (arg);
2198 break;
2199
2200 case OPTION_NO_PIC:
2201 riscv_opts.pic = FALSE;
2202 break;
2203
2204 case OPTION_PIC:
2205 riscv_opts.pic = TRUE;
2206 break;
2207
2922d21d
AW		 2208 case OPTION_MABI:
2209 if (strcmp (arg, "ilp32") == 0)
7f999549
JW		 2210 riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
2211 else if (strcmp (arg, "ilp32e") == 0)
2212 riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
2922d21d 2213 else if (strcmp (arg, "ilp32f") == 0)
7f999549 2214 riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2215 else if (strcmp (arg, "ilp32d") == 0)
7f999549 2216 riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2217 else if (strcmp (arg, "ilp32q") == 0)
7f999549 2218 riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
2922d21d 2219 else if (strcmp (arg, "lp64") == 0)
7f999549 2220 riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
2922d21d 2221 else if (strcmp (arg, "lp64f") == 0)
7f999549 2222 riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2223 else if (strcmp (arg, "lp64d") == 0)
7f999549 2224 riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2225 else if (strcmp (arg, "lp64q") == 0)
7f999549 2226 riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
2922d21d
AW		 2227 else
2228 return 0;
2229 break;
2230
71060565
JW		 2231 case OPTION_RELAX:
2232 riscv_opts.relax = TRUE;
2233 break;
2234
2235 case OPTION_NO_RELAX:
2236 riscv_opts.relax = FALSE;
2237 break;
2238
2dc8dd17
JW		 2239 case OPTION_ARCH_ATTR:
2240 riscv_opts.arch_attr = TRUE;
2241 break;
2242
2243 case OPTION_NO_ARCH_ATTR:
2244 riscv_opts.arch_attr = FALSE;
2245 break;
2246
e23eba97
NC		 2247 default:
2248 return 0;
2249 }
2250
2251 return 1;
2252}
2253
2254void
2255riscv_after_parse_args (void)
2256{
e23eba97
NC		 2257 if (xlen == 0)
2258 {
2259 if (strcmp (default_arch, "riscv32") == 0)
2260 xlen = 32;
2261 else if (strcmp (default_arch, "riscv64") == 0)
2262 xlen = 64;
2263 else
2264 as_bad ("unknown default architecture `%s'", default_arch);
2265 }
2922d21d 2266
1080bf78 2267 if (riscv_subsets.head == NULL)
2922d21d
AW		 2268 riscv_set_arch (xlen == 64 ? "rv64g" : "rv32g");
2269
2270 /* Add the RVC extension, regardless of -march, to support .option rvc. */
fecb9c46 2271 riscv_set_rvc (FALSE);
1080bf78 2272 if (riscv_subset_supports ("c"))
2922d21d 2273 riscv_set_rvc (TRUE);
2922d21d 2274
7f999549
JW		 2275 /* Enable RVE if specified by the -march option. */
2276 riscv_set_rve (FALSE);
1080bf78 2277 if (riscv_subset_supports ("e"))
7f999549
JW		 2278 riscv_set_rve (TRUE);
2279
2922d21d
AW		 2280 /* Infer ABI from ISA if not specified on command line. */
2281 if (abi_xlen == 0)
2282 abi_xlen = xlen;
2283 else if (abi_xlen > xlen)
2284 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
2285 else if (abi_xlen < xlen)
2286 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
2287
2288 if (float_abi == FLOAT_ABI_DEFAULT)
2289 {
1080bf78 2290 riscv_subset_t *subset;
2922d21d
AW		 2291
2292 /* Assume soft-float unless D extension is present. */
2293 float_abi = FLOAT_ABI_SOFT;
2294
1080bf78 2295 for (subset = riscv_subsets.head; subset != NULL; subset = subset->next)
cc917fd9
KC		 2296 {
2297 if (strcasecmp (subset->name, "D") == 0)
2298 float_abi = FLOAT_ABI_DOUBLE;
2299 if (strcasecmp (subset->name, "Q") == 0)
2300 float_abi = FLOAT_ABI_QUAD;
2301 }
2922d21d
AW		 2302 }
2303
7f999549
JW		 2304 if (rve_abi)
2305 elf_flags |= EF_RISCV_RVE;
2306
2922d21d
AW		 2307 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2308 elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1));
e23eba97
NC		 2309}
2310
2311long
2312md_pcrel_from (fixS *fixP)
2313{
2314 return fixP->fx_where + fixP->fx_frag->fr_address;
2315}
2316
2317/* Apply a fixup to the object file. */
2318
2319void
2320md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2321{
45f76423 2322 unsigned int subtype;
e23eba97 2323 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
45f76423 2324 bfd_boolean relaxable = FALSE;
c1b465c9 2325 offsetT loc;
a6cbf936 2326 segT sub_segment;
e23eba97
NC		 2327
2328 /* Remember value for tc_gen_reloc. */
2329 fixP->fx_addnumber = *valP;
2330
2331 switch (fixP->fx_r_type)
2332 {
e23eba97
NC		 2333 case BFD_RELOC_RISCV_HI20:
2334 case BFD_RELOC_RISCV_LO12_I:
2335 case BFD_RELOC_RISCV_LO12_S:
45f76423
AW		 2336 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2337 | bfd_getl32 (buf), buf);
a5ec5e3f
AW		 2338 if (fixP->fx_addsy == NULL)
2339 fixP->fx_done = TRUE;
45f76423
AW		 2340 relaxable = TRUE;
2341 break;
2342
2343 case BFD_RELOC_RISCV_GOT_HI20:
e23eba97
NC		 2344 case BFD_RELOC_RISCV_ADD8:
2345 case BFD_RELOC_RISCV_ADD16:
2346 case BFD_RELOC_RISCV_ADD32:
2347 case BFD_RELOC_RISCV_ADD64:
45f76423 2348 case BFD_RELOC_RISCV_SUB6:
e23eba97
NC		 2349 case BFD_RELOC_RISCV_SUB8:
2350 case BFD_RELOC_RISCV_SUB16:
2351 case BFD_RELOC_RISCV_SUB32:
2352 case BFD_RELOC_RISCV_SUB64:
45f76423
AW		 2353 case BFD_RELOC_RISCV_RELAX:
2354 break;
2355
2356 case BFD_RELOC_RISCV_TPREL_HI20:
2357 case BFD_RELOC_RISCV_TPREL_LO12_I:
2358 case BFD_RELOC_RISCV_TPREL_LO12_S:
2359 case BFD_RELOC_RISCV_TPREL_ADD:
2360 relaxable = TRUE;
2361 /* Fall through. */
2362
2363 case BFD_RELOC_RISCV_TLS_GOT_HI20:
2364 case BFD_RELOC_RISCV_TLS_GD_HI20:
2365 case BFD_RELOC_RISCV_TLS_DTPREL32:
2366 case BFD_RELOC_RISCV_TLS_DTPREL64:
e294484e
AW		 2367 if (fixP->fx_addsy != NULL)
2368 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2369 else
2370 as_bad_where (fixP->fx_file, fixP->fx_line,
2371 _("TLS relocation against a constant"));
e23eba97
NC		 2372 break;
2373
e23eba97 2374 case BFD_RELOC_32:
a6cbf936
KLC		 2375 /* Use pc-relative relocation for FDE initial location.
2376 The symbol address in .eh_frame may be adjusted in
2377 _bfd_elf_discard_section_eh_frame, and the content of
2378 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2379 Therefore, we cannot insert a relocation whose addend symbol is
2380 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2381 if (fixP->fx_addsy && fixP->fx_subsy
2382 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
2383 && strcmp (sub_segment->name, ".eh_frame") == 0
2384 && S_GET_VALUE (fixP->fx_subsy)
2385 == fixP->fx_frag->fr_address + fixP->fx_where)
2386 {
2387 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
2388 fixP->fx_subsy = NULL;
2389 break;
2390 }
2391 /* Fall through. */
2392 case BFD_RELOC_64:
e23eba97
NC		 2393 case BFD_RELOC_16:
2394 case BFD_RELOC_8:
45f76423 2395 case BFD_RELOC_RISCV_CFA:
e23eba97
NC		 2396 if (fixP->fx_addsy && fixP->fx_subsy)
2397 {
2398 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2399 fixP->fx_next->fx_addsy = fixP->fx_subsy;
2400 fixP->fx_next->fx_subsy = NULL;
2401 fixP->fx_next->fx_offset = 0;
2402 fixP->fx_subsy = NULL;
2403
2404 switch (fixP->fx_r_type)
2405 {
2406 case BFD_RELOC_64:
2407 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
2408 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
2409 break;
2410
2411 case BFD_RELOC_32:
2412 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
2413 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2414 break;
2415
2416 case BFD_RELOC_16:
2417 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
2418 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2419 break;
2420
2421 case BFD_RELOC_8:
2422 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
2423 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
073808ed 2424 break;
e23eba97 2425
45f76423
AW		 2426 case BFD_RELOC_RISCV_CFA:
2427 /* Load the byte to get the subtype. */
c1b465c9
KLC		 2428 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
2429 loc = fixP->fx_frag->fr_fix - (subtype & 7);
45f76423
AW		 2430 switch (subtype)
2431 {
2432 case DW_CFA_advance_loc1:
c1b465c9
KLC		 2433 fixP->fx_where = loc + 1;
2434 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2435 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
2436 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
2437 break;
2438
2439 case DW_CFA_advance_loc2:
2440 fixP->fx_size = 2;
45f76423 2441 fixP->fx_next->fx_size = 2;
c1b465c9
KLC		 2442 fixP->fx_where = loc + 1;
2443 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2444 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
2445 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2446 break;
2447
2448 case DW_CFA_advance_loc4:
2449 fixP->fx_size = 4;
45f76423 2450 fixP->fx_next->fx_size = 4;
c1b465c9
KLC		 2451 fixP->fx_where = loc;
2452 fixP->fx_next->fx_where = loc;
45f76423
AW		 2453 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
2454 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2455 break;
2456
2457 default:
2458 if (subtype < 0x80 && (subtype & 0x40))
2459 {
2460 /* DW_CFA_advance_loc */
2aece2ba
KLC		 2461 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
2462 fixP->fx_next->fx_frag = fixP->fx_frag;
45f76423
AW		 2463 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
2464 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
2465 }
2466 else
2467 as_fatal (_("internal error: bad CFA value #%d"), subtype);
2468 break;
2469 }
2470 break;
2471
e23eba97
NC		 2472 default:
2473 /* This case is unreachable. */
2474 abort ();
2475 }
2476 }
2477 /* Fall through. */
2478
2479 case BFD_RELOC_RVA:
2480 /* If we are deleting this reloc entry, we must fill in the
2481 value now. This can happen if we have a .word which is not
2482 resolved when it appears but is later defined. */
2483 if (fixP->fx_addsy == NULL)
2484 {
2485 gas_assert (fixP->fx_size <= sizeof (valueT));
2486 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
2487 fixP->fx_done = 1;
2488 }
2489 break;
2490
2491 case BFD_RELOC_RISCV_JMP:
2492 if (fixP->fx_addsy)
2493 {
2494 /* Fill in a tentative value to improve objdump readability. */
2495 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2496 bfd_vma delta = target - md_pcrel_from (fixP);
2497 bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
2498 }
2499 break;
2500
2501 case BFD_RELOC_12_PCREL:
2502 if (fixP->fx_addsy)
2503 {
2504 /* Fill in a tentative value to improve objdump readability. */
2505 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2506 bfd_vma delta = target - md_pcrel_from (fixP);
2507 bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
2508 }
2509 break;
2510
2511 case BFD_RELOC_RISCV_RVC_BRANCH:
2512 if (fixP->fx_addsy)
2513 {
2514 /* Fill in a tentative value to improve objdump readability. */
2515 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2516 bfd_vma delta = target - md_pcrel_from (fixP);
2517 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
2518 }
2519 break;
2520
2521 case BFD_RELOC_RISCV_RVC_JUMP:
2522 if (fixP->fx_addsy)
2523 {
2524 /* Fill in a tentative value to improve objdump readability. */
2525 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2526 bfd_vma delta = target - md_pcrel_from (fixP);
2527 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
2528 }
2529 break;
2530
e23eba97
NC		 2531 case BFD_RELOC_RISCV_CALL:
2532 case BFD_RELOC_RISCV_CALL_PLT:
45f76423
AW		 2533 relaxable = TRUE;
2534 break;
2535
9d06997a 2536 case BFD_RELOC_RISCV_PCREL_HI20:
45f76423
AW		 2537 case BFD_RELOC_RISCV_PCREL_LO12_S:
2538 case BFD_RELOC_RISCV_PCREL_LO12_I:
9d06997a
PD		 2539 relaxable = riscv_opts.relax;
2540 break;
2541
e23eba97
NC		 2542 case BFD_RELOC_RISCV_ALIGN:
2543 break;
2544
2545 default:
2546 /* We ignore generic BFD relocations we don't know about. */
2547 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
2548 as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type);
2549 }
45f76423 2550
e294484e
AW		 2551 if (fixP->fx_subsy != NULL)
2552 as_bad_where (fixP->fx_file, fixP->fx_line,
2553 _("unsupported symbol subtraction"));
2554
45f76423
AW		 2555 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2556 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
2557 {
2558 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2559 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
2560 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
2561 }
2562}
2563
2564/* Because the value of .cfi_remember_state may changed after relaxation,
2565 we insert a fix to relocate it again in link-time. */
2566
2567void
2568riscv_pre_output_hook (void)
2569{
2570 const frchainS *frch;
2571 const asection *s;
2572
2573 for (s = stdoutput->sections; s; s = s->next)
2574 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
2575 {
7cb7b948 2576 fragS *frag;
45f76423
AW		 2577
2578 for (frag = frch->frch_root; frag; frag = frag->fr_next)
2579 {
2580 if (frag->fr_type == rs_cfa)
2581 {
45f76423 2582 expressionS exp;
8d1015a8 2583 expressionS *symval;
45f76423 2584
8d1015a8 2585 symval = symbol_get_value_expression (frag->fr_symbol);
45f76423 2586 exp.X_op = O_subtract;
8d1015a8 2587 exp.X_add_symbol = symval->X_add_symbol;
45f76423 2588 exp.X_add_number = 0;
8d1015a8 2589 exp.X_op_symbol = symval->X_op_symbol;
45f76423 2590
c1b465c9 2591 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
45f76423
AW		 2592 BFD_RELOC_RISCV_CFA);
2593 }
2594 }
2595 }
e23eba97
NC		 2596}
2597
45f76423 2598
e23eba97
NC		 2599/* This structure is used to hold a stack of .option values. */
2600
2601struct riscv_option_stack
2602{
2603 struct riscv_option_stack *next;
2604 struct riscv_set_options options;
2605};
2606
2607static struct riscv_option_stack *riscv_opts_stack;
2608
2609/* Handle the .option pseudo-op. */
2610
2611static void
2612s_riscv_option (int x ATTRIBUTE_UNUSED)
2613{
2614 char *name = input_line_pointer, ch;
2615
2616 while (!is_end_of_line[(unsigned char) *input_line_pointer])
2617 ++input_line_pointer;
2618 ch = *input_line_pointer;
2619 *input_line_pointer = '\0';
2620
2621 if (strcmp (name, "rvc") == 0)
2622 riscv_set_rvc (TRUE);
2623 else if (strcmp (name, "norvc") == 0)
2624 riscv_set_rvc (FALSE);
2625 else if (strcmp (name, "pic") == 0)
2626 riscv_opts.pic = TRUE;
2627 else if (strcmp (name, "nopic") == 0)
2628 riscv_opts.pic = FALSE;
45f76423
AW		 2629 else if (strcmp (name, "relax") == 0)
2630 riscv_opts.relax = TRUE;
2631 else if (strcmp (name, "norelax") == 0)
2632 riscv_opts.relax = FALSE;
e23eba97
NC		 2633 else if (strcmp (name, "push") == 0)
2634 {
2635 struct riscv_option_stack *s;
2636
2637 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
2638 s->next = riscv_opts_stack;
2639 s->options = riscv_opts;
2640 riscv_opts_stack = s;
2641 }
2642 else if (strcmp (name, "pop") == 0)
2643 {
2644 struct riscv_option_stack *s;
2645
2646 s = riscv_opts_stack;
2647 if (s == NULL)
2648 as_bad (_(".option pop with no .option push"));
2649 else
2650 {
2651 riscv_opts = s->options;
2652 riscv_opts_stack = s->next;
2653 free (s);
2654 }
2655 }
2656 else
2657 {
2658 as_warn (_("Unrecognized .option directive: %s\n"), name);
2659 }
2660 *input_line_pointer = ch;
2661 demand_empty_rest_of_line ();
2662}
2663
2664/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2665 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2666 use in DWARF debug information. */
2667
2668static void
2669s_dtprel (int bytes)
2670{
2671 expressionS ex;
2672 char *p;
2673
2674 expression (&ex);
2675
2676 if (ex.X_op != O_symbol)
2677 {
2678 as_bad (_("Unsupported use of %s"), (bytes == 8
2679 ? ".dtpreldword"
2680 : ".dtprelword"));
2681 ignore_rest_of_line ();
2682 }
2683
2684 p = frag_more (bytes);
2685 md_number_to_chars (p, 0, bytes);
2686 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
2687 (bytes == 8
2688 ? BFD_RELOC_RISCV_TLS_DTPREL64
2689 : BFD_RELOC_RISCV_TLS_DTPREL32));
2690
2691 demand_empty_rest_of_line ();
2692}
2693
2694/* Handle the .bss pseudo-op. */
2695
2696static void
2697s_bss (int ignore ATTRIBUTE_UNUSED)
2698{
2699 subseg_set (bss_section, 0);
2700 demand_empty_rest_of_line ();
2701}
2702
e23eba97 2703static void
d115ab8e 2704riscv_make_nops (char *buf, bfd_vma bytes)
e23eba97 2705{
d115ab8e 2706 bfd_vma i = 0;
e23eba97 2707
e5b737de
AW		 2708 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2709 means we are not within a valid instruction sequence. It is thus safe
2710 to use a zero byte, even though that is not a valid instruction. */
2711 if (bytes % 2 == 1)
2712 buf[i++] = 0;
2713
2714 /* Use at most one 2-byte NOP. */
2715 if ((bytes - i) % 4 == 2)
e23eba97 2716 {
e5b737de 2717 md_number_to_chars (buf + i, RVC_NOP, 2);
d115ab8e 2718 i += 2;
e23eba97
NC		 2719 }
2720
e5b737de 2721 /* Fill the remainder with 4-byte NOPs. */
d115ab8e
AW		 2722 for ( ; i < bytes; i += 4)
2723 md_number_to_chars (buf + i, RISCV_NOP, 4);
2724}
e23eba97 2725
d115ab8e
AW		 2726/* Called from md_do_align. Used to create an alignment frag in a
2727 code section by emitting a worst-case NOP sequence that the linker
2728 will later relax to the correct number of NOPs. We can't compute
2729 the correct alignment now because of other linker relaxations. */
2730
2731bfd_boolean
2732riscv_frag_align_code (int n)
2733{
e5b737de 2734 bfd_vma bytes = (bfd_vma) 1 << n;
36877bfb
JW		 2735 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
2736 bfd_vma worst_case_bytes = bytes - insn_alignment;
2737 char *nops;
ed0816bd 2738 expressionS ex;
d115ab8e 2739
36877bfb
JW		 2740 /* If we are moving to a smaller alignment than the instruction size, then no
2741 alignment is required. */
2742 if (bytes <= insn_alignment)
2743 return TRUE;
2744
d115ab8e
AW		 2745 /* When not relaxing, riscv_handle_align handles code alignment. */
2746 if (!riscv_opts.relax)
2747 return FALSE;
e23eba97 2748
e80ae190
JW		 2749 nops = frag_more (worst_case_bytes);
2750
ed0816bd
PD		 2751 ex.X_op = O_constant;
2752 ex.X_add_number = worst_case_bytes;
d115ab8e 2753
ed0816bd 2754 riscv_make_nops (nops, worst_case_bytes);
e23eba97 2755
ed0816bd
PD		 2756 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
2757 &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
e23eba97 2758
d115ab8e
AW		 2759 return TRUE;
2760}
e23eba97 2761
d115ab8e
AW		 2762/* Implement HANDLE_ALIGN. */
2763
2764void
2765riscv_handle_align (fragS *fragP)
2766{
2767 switch (fragP->fr_type)
2768 {
2769 case rs_align_code:
2770 /* When relaxing, riscv_frag_align_code handles code alignment. */
2771 if (!riscv_opts.relax)
2772 {
e80ae190
JW		 2773 bfd_signed_vma bytes = (fragP->fr_next->fr_address
2774 - fragP->fr_address - fragP->fr_fix);
2775 /* We have 4 byte uncompressed nops. */
2776 bfd_signed_vma size = 4;
2777 bfd_signed_vma excess = bytes % size;
2778 char *p = fragP->fr_literal + fragP->fr_fix;
2779
2780 if (bytes <= 0)
d115ab8e
AW		 2781 break;
2782
e80ae190
JW		 2783 /* Insert zeros or compressed nops to get 4 byte alignment. */
2784 if (excess)
2785 {
2786 riscv_make_nops (p, excess);
2787 fragP->fr_fix += excess;
2788 p += excess;
2789 }
2790
2791 /* Insert variable number of 4 byte uncompressed nops. */
2792 riscv_make_nops (p, size);
2793 fragP->fr_var = size;
d115ab8e
AW		 2794 }
2795 break;
2796
2797 default:
2798 break;
2799 }
e23eba97
NC		 2800}
2801
2802int
2803md_estimate_size_before_relax (fragS *fragp, asection *segtype)
2804{
2805 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
2806}
2807
2808/* Translate internal representation of relocation info to BFD target
2809 format. */
2810
2811arelent *
2812tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
2813{
2814 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
2815
2816 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
2817 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
2818 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
2819 reloc->addend = fixp->fx_addnumber;
2820
2821 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
2822 if (reloc->howto == NULL)
2823 {
2824 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
2825 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
2826 {
2827 /* We don't have R_RISCV_8/16, but for this special case,
2828 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2829 return reloc;
2830 }
2831
2832 as_bad_where (fixp->fx_file, fixp->fx_line,
2833 _("cannot represent %s relocation in object file"),
2834 bfd_get_reloc_code_name (fixp->fx_r_type));
2835 return NULL;
2836 }
2837
2838 return reloc;
2839}
2840
2841int
2842riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
2843{
2844 if (RELAX_BRANCH_P (fragp->fr_subtype))
2845 {
2846 offsetT old_var = fragp->fr_var;
2847 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
2848 return fragp->fr_var - old_var;
2849 }
2850
2851 return 0;
2852}
2853
2854/* Expand far branches to multi-instruction sequences. */
2855
2856static void
2857md_convert_frag_branch (fragS *fragp)
2858{
2859 bfd_byte *buf;
2860 expressionS exp;
2861 fixS *fixp;
2862 insn_t insn;
2863 int rs1, reloc;
2864
2865 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
2866
2867 exp.X_op = O_symbol;
2868 exp.X_add_symbol = fragp->fr_symbol;
2869 exp.X_add_number = fragp->fr_offset;
2870
2871 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
2872
2873 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
2874 {
2875 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
2876 {
2877 case 8:
2878 case 4:
2879 /* Expand the RVC branch into a RISC-V one. */
2880 insn = bfd_getl16 (buf);
2881 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
2882 if ((insn & MASK_C_J) == MATCH_C_J)
2883 insn = MATCH_JAL;
2884 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
2885 insn = MATCH_JAL | (X_RA << OP_SH_RD);
2886 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
2887 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
2888 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
2889 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
2890 else
2891 abort ();
2892 bfd_putl32 (insn, buf);
2893 break;
2894
2895 case 6:
2896 /* Invert the branch condition. Branch over the jump. */
2897 insn = bfd_getl16 (buf);
2898 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
2899 insn |= ENCODE_RVC_B_IMM (6);
2900 bfd_putl16 (insn, buf);
2901 buf += 2;
2902 goto jump;
2903
2904 case 2:
2905 /* Just keep the RVC branch. */
2906 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
2907 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
2908 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
2909 2, &exp, FALSE, reloc);
2910 buf += 2;
2911 goto done;
2912
2913 default:
1d65abb5 2914 abort ();
e23eba97
NC		 2915 }
2916 }
2917
2918 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
2919 {
2920 case 8:
2921 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
2922
2923 /* Invert the branch condition. Branch over the jump. */
2924 insn = bfd_getl32 (buf);
2925 insn ^= MATCH_BEQ ^ MATCH_BNE;
2926 insn |= ENCODE_SBTYPE_IMM (8);
2927 md_number_to_chars ((char *) buf, insn, 4);
2928 buf += 4;
2929
2930jump:
2931 /* Jump to the target. */
2932 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
2933 4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
2934 md_number_to_chars ((char *) buf, MATCH_JAL, 4);
2935 buf += 4;
2936 break;
2937
2938 case 4:
2939 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
2940 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
2941 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
2942 4, &exp, FALSE, reloc);
2943 buf += 4;
2944 break;
2945
2946 default:
2947 abort ();
2948 }
2949
2950done:
2951 fixp->fx_file = fragp->fr_file;
2952 fixp->fx_line = fragp->fr_line;
2953
2954 gas_assert (buf == (bfd_byte *)fragp->fr_literal
2955 + fragp->fr_fix + fragp->fr_var);
2956
2957 fragp->fr_fix += fragp->fr_var;
2958}
2959
2960/* Relax a machine dependent frag. This returns the amount by which
2961 the current size of the frag should change. */
2962
2963void
2964md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
2965 fragS *fragp)
2966{
2967 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
2968 md_convert_frag_branch (fragp);
2969}
2970
2971void
2972md_show_usage (FILE *stream)
2973{
2974 fprintf (stream, _("\
2975RISC-V options:\n\
e23eba97
NC		 2976 -fpic generate position-independent code\n\
2977 -fno-pic don't generate position-independent code (default)\n\
19683c04
PD		 2978 -march=ISA set the RISC-V architecture\n\
2979 -mabi=ABI set the RISC-V ABI\n\
71060565
JW		 2980 -mrelax enable relax (default)\n\
2981 -mno-relax disable relax\n\
2dc8dd17
JW		 2982 -march-attr generate RISC-V arch attribute\n\
2983 -mno-arch-attr don't generate RISC-V arch attribute\n\
e23eba97
NC		 2984"));
2985}
2986
2987/* Standard calling conventions leave the CFA at SP on entry. */
2988void
2989riscv_cfi_frame_initial_instructions (void)
2990{
2991 cfi_add_CFA_def_cfa_register (X_SP);
2992}
2993
2994int
2995tc_riscv_regname_to_dw2regnum (char *regname)
2996{
2997 int reg;
2998
2999 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3000 return reg;
3001
3002 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3003 return reg + 32;
3004
3005 as_bad (_("unknown register `%s'"), regname);
3006 return -1;
3007}
3008
3009void
3010riscv_elf_final_processing (void)
3011{
e23eba97 3012 elf_elfheader (stdoutput)->e_flags |= elf_flags;
e23eba97
NC		 3013}
3014
3015/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3016 since these directives break relaxation when used with symbol deltas. */
3017
3018static void
3019s_riscv_leb128 (int sign)
3020{
3021 expressionS exp;
3022 char *save_in = input_line_pointer;
3023
3024 expression (&exp);
3025 if (exp.X_op != O_constant)
3026 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3027 demand_empty_rest_of_line ();
3028
3029 input_line_pointer = save_in;
3030 return s_leb128 (sign);
3031}
3032
0e35537d
JW		 3033/* Parse the .insn directive. */
3034
3035static void
3036s_riscv_insn (int x ATTRIBUTE_UNUSED)
3037{
3038 char *str = input_line_pointer;
3039 struct riscv_cl_insn insn;
3040 expressionS imm_expr;
3041 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3042 char save_c;
3043
3044 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3045 ++input_line_pointer;
3046
3047 save_c = *input_line_pointer;
3048 *input_line_pointer = '\0';
3049
3050 const char *error = riscv_ip (str, &insn, &imm_expr,
3051 &imm_reloc, insn_type_hash);
3052
3053 if (error)
3054 {
3055 as_bad ("%s `%s'", error, str);
3056 }
3057 else
3058 {
3059 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3060 append_insn (&insn, &imm_expr, imm_reloc);
3061 }
3062
3063 *input_line_pointer = save_c;
3064 demand_empty_rest_of_line ();
3065}
3066
2dc8dd17
JW		 3067/* Update arch attributes. */
3068
3069static void
3070riscv_write_out_arch_attr (void)
3071{
3072 const char *arch_str = riscv_arch_str (xlen, &riscv_subsets);
3073
3074 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
3075
3076 xfree ((void *)arch_str);
3077}
3078
3079/* Add the default contents for the .riscv.attributes section. */
3080
3081static void
3082riscv_set_public_attributes (void)
3083{
3084 if (riscv_opts.arch_attr || explicit_arch_attr)
3085 /* Re-write arch attribute to normalize the arch string. */
3086 riscv_write_out_arch_attr ();
3087}
3088
3089/* Called after all assembly has been done. */
3090
3091void
3092riscv_md_end (void)
3093{
3094 riscv_set_public_attributes ();
3095}
3096
3097/* Given a symbolic attribute NAME, return the proper integer value.
3098 Returns -1 if the attribute is not known. */
3099
3100int
3101riscv_convert_symbolic_attribute (const char *name)
3102{
3103 static const struct
3104 {
3105 const char * name;
3106 const int tag;
3107 }
3108 attribute_table[] =
3109 {
3110 /* When you modify this table you should
3111 also modify the list in doc/c-riscv.texi. */
3112#define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3113 T(arch),
3114 T(priv_spec),
3115 T(priv_spec_minor),
3116 T(priv_spec_revision),
3117 T(unaligned_access),
3118 T(stack_align),
3119#undef T
3120 };
3121
3122 unsigned int i;
3123
3124 if (name == NULL)
3125 return -1;
3126
3127 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
3128 if (strcmp (name, attribute_table[i].name) == 0)
3129 return attribute_table[i].tag;
3130
3131 return -1;
3132}
3133
3134/* Parse a .attribute directive. */
3135
3136static void
3137s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
3138{
3139 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
3140
3141 if (tag == Tag_RISCV_arch)
3142 {
3143 unsigned old_xlen = xlen;
3144
3145 explicit_arch_attr = TRUE;
3146 obj_attribute *attr;
3147 attr = elf_known_obj_attributes_proc (stdoutput);
3148 if (!start_assemble)
3149 riscv_set_arch (attr[Tag_RISCV_arch].s);
3150 else
3151 as_fatal (_(".attribute arch must set before any instructions"));
3152
3153 if (old_xlen != xlen)
3154 {
3155 /* We must re-init bfd again if xlen is changed. */
3156 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
3157 bfd_find_target (riscv_target_format (), stdoutput);
3158
3159 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
3160 as_warn (_("Could not set architecture and machine"));
3161 }
3162 }
3163}
3164
e23eba97
NC		 3165/* Pseudo-op table. */
3166
3167static const pseudo_typeS riscv_pseudo_table[] =
3168{
3169 /* RISC-V-specific pseudo-ops. */
3170 {"option", s_riscv_option, 0},
3171 {"half", cons, 2},
3172 {"word", cons, 4},
3173 {"dword", cons, 8},
3174 {"dtprelword", s_dtprel, 4},
3175 {"dtpreldword", s_dtprel, 8},
3176 {"bss", s_bss, 0},
e23eba97
NC		 3177 {"uleb128", s_riscv_leb128, 0},
3178 {"sleb128", s_riscv_leb128, 1},
0e35537d 3179 {"insn", s_riscv_insn, 0},
2dc8dd17 3180 {"attribute", s_riscv_attribute, 0},
e23eba97
NC		 3181
3182 { NULL, NULL, 0 },
3183};
3184
3185void
3186riscv_pop_insert (void)
3187{
3188 extern void pop_insert (const pseudo_typeS *);
3189
3190 pop_insert (riscv_pseudo_table);
3191}
GDB Binutils - Deliverables
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