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e23eba97 | 1 | /* tc-riscv.c -- RISC-V assembler |
219d1afa | 2 | Copyright (C) 2011-2018 Free Software Foundation, Inc. |
e23eba97 NC |
3 | |
4 | Contributed by Andrew Waterman (andrew@sifive.com). | |
5 | Based on MIPS target. | |
6 | ||
7 | This file is part of GAS. | |
8 | ||
9 | GAS is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GAS is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; see the file COPYING3. If not, | |
21 | see <http://www.gnu.org/licenses/>. */ | |
22 | ||
23 | #include "as.h" | |
24 | #include "config.h" | |
25 | #include "subsegs.h" | |
26 | #include "safe-ctype.h" | |
27 | ||
28 | #include "itbl-ops.h" | |
29 | #include "dwarf2dbg.h" | |
30 | #include "dw2gencfi.h" | |
31 | ||
1080bf78 | 32 | #include "bfd/elfxx-riscv.h" |
e23eba97 NC |
33 | #include "elf/riscv.h" |
34 | #include "opcode/riscv.h" | |
35 | ||
36 | #include <stdint.h> | |
37 | ||
38 | /* Information about an instruction, including its format, operands | |
39 | and fixups. */ | |
40 | struct riscv_cl_insn | |
41 | { | |
42 | /* The opcode's entry in riscv_opcodes. */ | |
43 | const struct riscv_opcode *insn_mo; | |
44 | ||
45 | /* The encoded instruction bits. */ | |
46 | insn_t insn_opcode; | |
47 | ||
48 | /* The frag that contains the instruction. */ | |
49 | struct frag *frag; | |
50 | ||
51 | /* The offset into FRAG of the first instruction byte. */ | |
52 | long where; | |
53 | ||
54 | /* The relocs associated with the instruction, if any. */ | |
55 | fixS *fixp; | |
56 | }; | |
57 | ||
58 | #ifndef DEFAULT_ARCH | |
59 | #define DEFAULT_ARCH "riscv64" | |
60 | #endif | |
61 | ||
62 | static const char default_arch[] = DEFAULT_ARCH; | |
63 | ||
2922d21d AW |
64 | static unsigned xlen = 0; /* width of an x-register */ |
65 | static unsigned abi_xlen = 0; /* width of a pointer in the ABI */ | |
7f999549 | 66 | static bfd_boolean rve_abi = FALSE; |
e23eba97 | 67 | |
2922d21d | 68 | #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw") |
e23eba97 NC |
69 | #define ADD32_INSN (xlen == 64 ? "addiw" : "addi") |
70 | ||
71 | static unsigned elf_flags = 0; | |
72 | ||
73 | /* This is the set of options which the .option pseudo-op may modify. */ | |
74 | ||
75 | struct riscv_set_options | |
76 | { | |
77 | int pic; /* Generate position-independent code. */ | |
78 | int rvc; /* Generate RVC code. */ | |
7f999549 | 79 | int rve; /* Generate RVE code. */ |
45f76423 | 80 | int relax; /* Emit relocs the linker is allowed to relax. */ |
e23eba97 NC |
81 | }; |
82 | ||
83 | static struct riscv_set_options riscv_opts = | |
84 | { | |
85 | 0, /* pic */ | |
86 | 0, /* rvc */ | |
7f999549 | 87 | 0, /* rve */ |
45f76423 | 88 | 1, /* relax */ |
e23eba97 NC |
89 | }; |
90 | ||
91 | static void | |
92 | riscv_set_rvc (bfd_boolean rvc_value) | |
93 | { | |
94 | if (rvc_value) | |
95 | elf_flags |= EF_RISCV_RVC; | |
96 | ||
97 | riscv_opts.rvc = rvc_value; | |
98 | } | |
99 | ||
7f999549 JW |
100 | static void |
101 | riscv_set_rve (bfd_boolean rve_value) | |
102 | { | |
103 | riscv_opts.rve = rve_value; | |
104 | } | |
105 | ||
1080bf78 | 106 | static riscv_subset_list_t riscv_subsets; |
e23eba97 NC |
107 | |
108 | static bfd_boolean | |
1080bf78 | 109 | riscv_subset_supports (const char *feature) |
e23eba97 | 110 | { |
1080bf78 JW |
111 | if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0)) |
112 | return TRUE; | |
e23eba97 | 113 | |
1080bf78 | 114 | return riscv_lookup_subset (&riscv_subsets, feature) != NULL; |
e23eba97 NC |
115 | } |
116 | ||
43135d3b | 117 | static bfd_boolean |
1080bf78 | 118 | riscv_multi_subset_supports (const char *features[]) |
43135d3b JW |
119 | { |
120 | unsigned i = 0; | |
121 | bfd_boolean supported = TRUE; | |
122 | ||
123 | for (;features[i]; ++i) | |
1080bf78 | 124 | supported = supported && riscv_subset_supports (features[i]); |
43135d3b JW |
125 | |
126 | return supported; | |
127 | } | |
128 | ||
2922d21d | 129 | /* Set which ISA and extensions are available. */ |
e23eba97 | 130 | |
e23eba97 | 131 | static void |
2922d21d | 132 | riscv_set_arch (const char *s) |
e23eba97 | 133 | { |
1080bf78 JW |
134 | riscv_parse_subset_t rps; |
135 | rps.subset_list = &riscv_subsets; | |
136 | rps.error_handler = as_fatal; | |
137 | rps.xlen = &xlen; | |
7f999549 | 138 | |
1080bf78 JW |
139 | riscv_release_subset_list (&riscv_subsets); |
140 | riscv_parse_subset (&rps, s); | |
e23eba97 NC |
141 | } |
142 | ||
143 | /* Handle of the OPCODE hash table. */ | |
144 | static struct hash_control *op_hash = NULL; | |
145 | ||
0e35537d JW |
146 | /* Handle of the type of .insn hash table. */ |
147 | static struct hash_control *insn_type_hash = NULL; | |
148 | ||
e23eba97 NC |
149 | /* This array holds the chars that always start a comment. If the |
150 | pre-processor is disabled, these aren't very useful */ | |
151 | const char comment_chars[] = "#"; | |
152 | ||
153 | /* This array holds the chars that only start a comment at the beginning of | |
154 | a line. If the line seems to have the form '# 123 filename' | |
155 | .line and .file directives will appear in the pre-processed output */ | |
156 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
157 | first line of the input file. This is because the compiler outputs | |
158 | #NO_APP at the beginning of its output. */ | |
159 | /* Also note that C style comments are always supported. */ | |
160 | const char line_comment_chars[] = "#"; | |
161 | ||
162 | /* This array holds machine specific line separator characters. */ | |
163 | const char line_separator_chars[] = ";"; | |
164 | ||
165 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
166 | const char EXP_CHARS[] = "eE"; | |
167 | ||
168 | /* Chars that mean this number is a floating point constant */ | |
169 | /* As in 0f12.456 */ | |
170 | /* or 0d1.2345e12 */ | |
171 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
172 | ||
173 | /* Macros for encoding relaxation state for RVC branches and far jumps. */ | |
174 | #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \ | |
175 | ((relax_substateT) \ | |
176 | (0xc0000000 \ | |
177 | | ((uncond) ? 1 : 0) \ | |
178 | | ((rvc) ? 2 : 0) \ | |
179 | | ((length) << 2))) | |
180 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) | |
181 | #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF) | |
182 | #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0) | |
183 | #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0) | |
184 | ||
185 | /* Is the given value a sign-extended 32-bit value? */ | |
186 | #define IS_SEXT_32BIT_NUM(x) \ | |
187 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
188 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
189 | ||
190 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ | |
191 | #define IS_ZEXT_32BIT_NUM(x) \ | |
192 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
193 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
194 | ||
195 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
196 | INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */ | |
197 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
198 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
199 | ||
200 | /* Determine if an instruction matches an opcode. */ | |
201 | #define OPCODE_MATCHES(OPCODE, OP) \ | |
202 | (((OPCODE) & MASK_##OP) == MATCH_##OP) | |
203 | ||
204 | static char *expr_end; | |
205 | ||
206 | /* The default target format to use. */ | |
207 | ||
208 | const char * | |
209 | riscv_target_format (void) | |
210 | { | |
211 | return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; | |
212 | } | |
213 | ||
214 | /* Return the length of instruction INSN. */ | |
215 | ||
216 | static inline unsigned int | |
217 | insn_length (const struct riscv_cl_insn *insn) | |
218 | { | |
219 | return riscv_insn_length (insn->insn_opcode); | |
220 | } | |
221 | ||
222 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
223 | ||
224 | static void | |
225 | create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) | |
226 | { | |
227 | insn->insn_mo = mo; | |
228 | insn->insn_opcode = mo->match; | |
229 | insn->frag = NULL; | |
230 | insn->where = 0; | |
231 | insn->fixp = NULL; | |
232 | } | |
233 | ||
234 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
235 | ||
236 | static void | |
237 | install_insn (const struct riscv_cl_insn *insn) | |
238 | { | |
239 | char *f = insn->frag->fr_literal + insn->where; | |
240 | md_number_to_chars (f, insn->insn_opcode, insn_length (insn)); | |
241 | } | |
242 | ||
243 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
244 | and install the opcode in the new location. */ | |
245 | ||
246 | static void | |
247 | move_insn (struct riscv_cl_insn *insn, fragS *frag, long where) | |
248 | { | |
249 | insn->frag = frag; | |
250 | insn->where = where; | |
251 | if (insn->fixp != NULL) | |
252 | { | |
253 | insn->fixp->fx_frag = frag; | |
254 | insn->fixp->fx_where = where; | |
255 | } | |
256 | install_insn (insn); | |
257 | } | |
258 | ||
259 | /* Add INSN to the end of the output. */ | |
260 | ||
261 | static void | |
262 | add_fixed_insn (struct riscv_cl_insn *insn) | |
263 | { | |
264 | char *f = frag_more (insn_length (insn)); | |
265 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
266 | } | |
267 | ||
268 | static void | |
269 | add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var, | |
270 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
271 | { | |
272 | frag_grow (max_chars); | |
273 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
274 | frag_var (rs_machine_dependent, max_chars, var, | |
275 | subtype, symbol, offset, NULL); | |
276 | } | |
277 | ||
278 | /* Compute the length of a branch sequence, and adjust the stored length | |
279 | accordingly. If FRAGP is NULL, the worst-case length is returned. */ | |
280 | ||
281 | static unsigned | |
282 | relaxed_branch_length (fragS *fragp, asection *sec, int update) | |
283 | { | |
284 | int jump, rvc, length = 8; | |
285 | ||
286 | if (!fragp) | |
287 | return length; | |
288 | ||
289 | jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype); | |
290 | rvc = RELAX_BRANCH_RVC (fragp->fr_subtype); | |
291 | length = RELAX_BRANCH_LENGTH (fragp->fr_subtype); | |
292 | ||
293 | /* Assume jumps are in range; the linker will catch any that aren't. */ | |
294 | length = jump ? 4 : 8; | |
295 | ||
296 | if (fragp->fr_symbol != NULL | |
297 | && S_IS_DEFINED (fragp->fr_symbol) | |
01156111 | 298 | && !S_IS_WEAK (fragp->fr_symbol) |
e23eba97 NC |
299 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
300 | { | |
301 | offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
302 | bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH; | |
303 | val -= fragp->fr_address + fragp->fr_fix; | |
304 | ||
305 | if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range) | |
306 | length = 2; | |
307 | else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH) | |
308 | length = 4; | |
309 | else if (!jump && rvc) | |
310 | length = 6; | |
311 | } | |
312 | ||
313 | if (update) | |
314 | fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length); | |
315 | ||
316 | return length; | |
317 | } | |
318 | ||
0e35537d JW |
319 | /* Information about an opcode name, mnemonics and its value. */ |
320 | struct opcode_name_t | |
321 | { | |
322 | const char *name; | |
323 | unsigned int val; | |
324 | }; | |
325 | ||
326 | /* List for all supported opcode name. */ | |
327 | static const struct opcode_name_t opcode_name_list[] = | |
328 | { | |
329 | {"C0", 0x0}, | |
330 | {"C1", 0x1}, | |
331 | {"C2", 0x2}, | |
332 | ||
333 | {"LOAD", 0x03}, | |
334 | {"LOAD_FP", 0x07}, | |
335 | {"CUSTOM_0", 0x0b}, | |
336 | {"MISC_MEM", 0x0f}, | |
337 | {"OP_IMM", 0x13}, | |
338 | {"AUIPC", 0x17}, | |
339 | {"OP_IMM_32", 0x1b}, | |
340 | /* 48b 0x1f. */ | |
341 | ||
342 | {"STORE", 0x23}, | |
343 | {"STORE_FP", 0x27}, | |
344 | {"CUSTOM_1", 0x2b}, | |
345 | {"AMO", 0x2f}, | |
346 | {"OP", 0x33}, | |
347 | {"LUI", 0x37}, | |
348 | {"OP_32", 0x3b}, | |
349 | /* 64b 0x3f. */ | |
350 | ||
351 | {"MADD", 0x43}, | |
352 | {"MSUB", 0x47}, | |
353 | {"NMADD", 0x4f}, | |
354 | {"NMSUB", 0x4b}, | |
355 | {"OP_FP", 0x53}, | |
356 | /*reserved 0x57. */ | |
357 | {"CUSTOM_2", 0x5b}, | |
358 | /* 48b 0x5f. */ | |
359 | ||
360 | {"BRANCH", 0x63}, | |
361 | {"JALR", 0x67}, | |
362 | /*reserved 0x5b. */ | |
363 | {"JAL", 0x6f}, | |
364 | {"SYSTEM", 0x73}, | |
365 | /*reserved 0x77. */ | |
366 | {"CUSTOM_3", 0x7b}, | |
367 | /* >80b 0x7f. */ | |
368 | ||
369 | {NULL, 0} | |
370 | }; | |
371 | ||
372 | /* Hash table for lookup opcode name. */ | |
373 | static struct hash_control *opcode_names_hash = NULL; | |
374 | ||
375 | /* Initialization for hash table of opcode name. */ | |
376 | static void | |
377 | init_opcode_names_hash (void) | |
378 | { | |
379 | const char *retval; | |
380 | const struct opcode_name_t *opcode; | |
381 | ||
382 | for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode) | |
383 | { | |
384 | retval = hash_insert (opcode_names_hash, opcode->name, (void *)opcode); | |
385 | ||
386 | if (retval != NULL) | |
387 | as_fatal (_("internal error: can't hash `%s': %s"), | |
388 | opcode->name, retval); | |
389 | } | |
390 | } | |
391 | ||
392 | /* Find `s` is a valid opcode name or not, | |
393 | return the opcode name info if found. */ | |
394 | static const struct opcode_name_t * | |
395 | opcode_name_lookup (char **s) | |
396 | { | |
397 | char *e; | |
398 | char save_c; | |
399 | struct opcode_name_t *o; | |
400 | ||
401 | /* Find end of name. */ | |
402 | e = *s; | |
403 | if (is_name_beginner (*e)) | |
404 | ++e; | |
405 | while (is_part_of_name (*e)) | |
406 | ++e; | |
407 | ||
408 | /* Terminate name. */ | |
409 | save_c = *e; | |
410 | *e = '\0'; | |
411 | ||
412 | o = (struct opcode_name_t *) hash_find (opcode_names_hash, *s); | |
413 | ||
414 | /* Advance to next token if one was recognized. */ | |
415 | if (o) | |
416 | *s = e; | |
417 | ||
418 | *e = save_c; | |
419 | expr_end = e; | |
420 | ||
421 | return o; | |
422 | } | |
423 | ||
e23eba97 NC |
424 | struct regname |
425 | { | |
426 | const char *name; | |
427 | unsigned int num; | |
428 | }; | |
429 | ||
430 | enum reg_class | |
431 | { | |
432 | RCLASS_GPR, | |
433 | RCLASS_FPR, | |
434 | RCLASS_CSR, | |
435 | RCLASS_MAX | |
436 | }; | |
437 | ||
438 | static struct hash_control *reg_names_hash = NULL; | |
439 | ||
440 | #define ENCODE_REG_HASH(cls, n) \ | |
441 | ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1)) | |
442 | #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX) | |
443 | #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX) | |
444 | ||
445 | static void | |
446 | hash_reg_name (enum reg_class class, const char *name, unsigned n) | |
447 | { | |
448 | void *hash = ENCODE_REG_HASH (class, n); | |
449 | const char *retval = hash_insert (reg_names_hash, name, hash); | |
450 | ||
451 | if (retval != NULL) | |
452 | as_fatal (_("internal error: can't hash `%s': %s"), name, retval); | |
453 | } | |
454 | ||
455 | static void | |
456 | hash_reg_names (enum reg_class class, const char * const names[], unsigned n) | |
457 | { | |
458 | unsigned i; | |
459 | ||
460 | for (i = 0; i < n; i++) | |
461 | hash_reg_name (class, names[i], i); | |
462 | } | |
463 | ||
464 | static unsigned int | |
465 | reg_lookup_internal (const char *s, enum reg_class class) | |
466 | { | |
467 | struct regname *r = (struct regname *) hash_find (reg_names_hash, s); | |
468 | ||
469 | if (r == NULL || DECODE_REG_CLASS (r) != class) | |
470 | return -1; | |
7f999549 JW |
471 | |
472 | if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15) | |
473 | return -1; | |
474 | ||
e23eba97 NC |
475 | return DECODE_REG_NUM (r); |
476 | } | |
477 | ||
478 | static bfd_boolean | |
479 | reg_lookup (char **s, enum reg_class class, unsigned int *regnop) | |
480 | { | |
481 | char *e; | |
482 | char save_c; | |
483 | int reg = -1; | |
484 | ||
485 | /* Find end of name. */ | |
486 | e = *s; | |
487 | if (is_name_beginner (*e)) | |
488 | ++e; | |
489 | while (is_part_of_name (*e)) | |
490 | ++e; | |
491 | ||
492 | /* Terminate name. */ | |
493 | save_c = *e; | |
494 | *e = '\0'; | |
495 | ||
496 | /* Look for the register. Advance to next token if one was recognized. */ | |
497 | if ((reg = reg_lookup_internal (*s, class)) >= 0) | |
498 | *s = e; | |
499 | ||
500 | *e = save_c; | |
501 | if (regnop) | |
502 | *regnop = reg; | |
503 | return reg >= 0; | |
504 | } | |
505 | ||
506 | static bfd_boolean | |
507 | arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) | |
508 | { | |
509 | const char *p = strchr (*s, ','); | |
510 | size_t i, len = p ? (size_t)(p - *s) : strlen (*s); | |
511 | ||
bfb218e3 JW |
512 | if (len == 0) |
513 | return FALSE; | |
514 | ||
e23eba97 NC |
515 | for (i = 0; i < size; i++) |
516 | if (array[i] != NULL && strncmp (array[i], *s, len) == 0) | |
517 | { | |
518 | *regnop = i; | |
519 | *s += len; | |
520 | return TRUE; | |
521 | } | |
522 | ||
523 | return FALSE; | |
524 | } | |
525 | ||
526 | /* For consistency checking, verify that all bits are specified either | |
527 | by the match/mask part of the instruction definition, or by the | |
0e35537d JW |
528 | operand list. |
529 | ||
530 | `length` could be 0, 4 or 8, 0 for auto detection. */ | |
e23eba97 | 531 | static bfd_boolean |
0e35537d | 532 | validate_riscv_insn (const struct riscv_opcode *opc, int length) |
e23eba97 NC |
533 | { |
534 | const char *p = opc->args; | |
535 | char c; | |
536 | insn_t used_bits = opc->mask; | |
0e35537d JW |
537 | int insn_width; |
538 | insn_t required_bits; | |
539 | ||
540 | if (length == 0) | |
541 | insn_width = 8 * riscv_insn_length (opc->match); | |
542 | else | |
543 | insn_width = 8 * length; | |
544 | ||
545 | required_bits = ~0ULL >> (64 - insn_width); | |
e23eba97 NC |
546 | |
547 | if ((used_bits & opc->match) != (opc->match & required_bits)) | |
548 | { | |
549 | as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"), | |
550 | opc->name, opc->args); | |
551 | return FALSE; | |
552 | } | |
553 | ||
554 | #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) | |
555 | while (*p) | |
556 | switch (c = *p++) | |
557 | { | |
558 | case 'C': /* RVC */ | |
559 | switch (c = *p++) | |
560 | { | |
1d65abb5 | 561 | case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break; |
e23eba97 NC |
562 | case 'c': break; /* RS1, constrained to equal sp */ |
563 | case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break; | |
1d65abb5 | 564 | case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break; |
b416fe87 | 565 | case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break; |
1d65abb5 AW |
566 | case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break; |
567 | case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break; | |
568 | case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break; | |
569 | case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break; | |
570 | case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break; | |
e23eba97 NC |
571 | case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; |
572 | case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; | |
1d65abb5 AW |
573 | case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break; |
574 | case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break; | |
e23eba97 NC |
575 | case 'w': break; /* RS1S, constrained to equal RD */ |
576 | case 'x': break; /* RS2S, constrained to equal RD */ | |
1d65abb5 AW |
577 | case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break; |
578 | case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break; | |
579 | case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break; | |
580 | case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break; | |
e23eba97 NC |
581 | case 'U': break; /* RS1, constrained to equal RD */ |
582 | case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; | |
1d65abb5 AW |
583 | case '<': used_bits |= ENCODE_RVC_IMM (-1U); break; |
584 | case '>': used_bits |= ENCODE_RVC_IMM (-1U); break; | |
0e35537d JW |
585 | case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break; |
586 | case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; | |
e23eba97 NC |
587 | case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; |
588 | case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; | |
0e35537d JW |
589 | case 'F': /* funct */ |
590 | switch (c = *p++) | |
591 | { | |
4765cd61 | 592 | case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break; |
0e35537d JW |
593 | case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break; |
594 | case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break; | |
4765cd61 | 595 | case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break; |
0e35537d JW |
596 | default: |
597 | as_bad (_("internal: bad RISC-V opcode" | |
598 | " (unknown operand type `CF%c'): %s %s"), | |
599 | c, opc->name, opc->args); | |
600 | return FALSE; | |
601 | } | |
602 | break; | |
e23eba97 NC |
603 | default: |
604 | as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"), | |
605 | c, opc->name, opc->args); | |
606 | return FALSE; | |
607 | } | |
608 | break; | |
609 | case ',': break; | |
610 | case '(': break; | |
611 | case ')': break; | |
612 | case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break; | |
613 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
614 | case 'A': break; | |
615 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
616 | case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
617 | case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; | |
618 | case 'I': break; | |
619 | case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; | |
620 | case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
621 | case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */ | |
622 | case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; | |
623 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
624 | case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; | |
625 | case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
626 | case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; | |
0e35537d | 627 | case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; |
e23eba97 NC |
628 | case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; |
629 | case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break; | |
630 | case 'o': | |
1d65abb5 AW |
631 | case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; |
632 | case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break; | |
633 | case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break; | |
634 | case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; | |
635 | case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; | |
e925c834 | 636 | case 'z': break; |
e23eba97 NC |
637 | case '[': break; |
638 | case ']': break; | |
639 | case '0': break; | |
0e35537d JW |
640 | case 'F': /* funct */ |
641 | switch (c = *p++) | |
642 | { | |
643 | case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break; | |
644 | case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break; | |
645 | case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break; | |
646 | default: | |
647 | as_bad (_("internal: bad RISC-V opcode" | |
648 | " (unknown operand type `F%c'): %s %s"), | |
649 | c, opc->name, opc->args); | |
650 | return FALSE; | |
651 | } | |
652 | break; | |
653 | case 'O': /* opcode */ | |
654 | switch (c = *p++) | |
655 | { | |
656 | case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break; | |
657 | case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break; | |
658 | default: | |
659 | as_bad (_("internal: bad RISC-V opcode" | |
660 | " (unknown operand type `F%c'): %s %s"), | |
661 | c, opc->name, opc->args); | |
662 | return FALSE; | |
663 | } | |
664 | break; | |
e23eba97 NC |
665 | default: |
666 | as_bad (_("internal: bad RISC-V opcode " | |
667 | "(unknown operand type `%c'): %s %s"), | |
668 | c, opc->name, opc->args); | |
669 | return FALSE; | |
670 | } | |
671 | #undef USE_BITS | |
672 | if (used_bits != required_bits) | |
673 | { | |
674 | as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"), | |
675 | ~(unsigned long)(used_bits & required_bits), | |
676 | opc->name, opc->args); | |
677 | return FALSE; | |
678 | } | |
679 | return TRUE; | |
680 | } | |
681 | ||
682 | struct percent_op_match | |
683 | { | |
684 | const char *str; | |
685 | bfd_reloc_code_real_type reloc; | |
686 | }; | |
687 | ||
0e35537d JW |
688 | /* Common hash table initialization function for |
689 | instruction and .insn directive. */ | |
690 | static struct hash_control * | |
691 | init_opcode_hash (const struct riscv_opcode *opcodes, | |
692 | bfd_boolean insn_directive_p) | |
e23eba97 NC |
693 | { |
694 | int i = 0; | |
0e35537d JW |
695 | int length; |
696 | struct hash_control *hash = hash_new (); | |
697 | while (opcodes[i].name) | |
e23eba97 | 698 | { |
0e35537d | 699 | const char *name = opcodes[i].name; |
e23eba97 | 700 | const char *hash_error = |
0e35537d | 701 | hash_insert (hash, name, (void *) &opcodes[i]); |
e23eba97 NC |
702 | |
703 | if (hash_error) | |
704 | { | |
705 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
0e35537d | 706 | opcodes[i].name, hash_error); |
e23eba97 NC |
707 | /* Probably a memory allocation problem? Give up now. */ |
708 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
709 | } | |
710 | ||
711 | do | |
712 | { | |
0e35537d | 713 | if (opcodes[i].pinfo != INSN_MACRO) |
e23eba97 | 714 | { |
0e35537d JW |
715 | if (insn_directive_p) |
716 | length = ((name[0] == 'c') ? 2 : 4); | |
717 | else | |
718 | length = 0; /* Let assembler determine the length. */ | |
719 | if (!validate_riscv_insn (&opcodes[i], length)) | |
e23eba97 NC |
720 | as_fatal (_("Broken assembler. No assembly attempted.")); |
721 | } | |
0e35537d JW |
722 | else |
723 | gas_assert (!insn_directive_p); | |
e23eba97 NC |
724 | ++i; |
725 | } | |
0e35537d | 726 | while (opcodes[i].name && !strcmp (opcodes[i].name, name)); |
e23eba97 NC |
727 | } |
728 | ||
0e35537d JW |
729 | return hash; |
730 | } | |
731 | ||
732 | /* This function is called once, at assembler startup time. It should set up | |
733 | all the tables, etc. that the MD part of the assembler will need. */ | |
734 | ||
735 | void | |
736 | md_begin (void) | |
737 | { | |
738 | unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; | |
739 | ||
740 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) | |
741 | as_warn (_("Could not set architecture and machine")); | |
742 | ||
743 | op_hash = init_opcode_hash (riscv_opcodes, FALSE); | |
744 | insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE); | |
745 | ||
e23eba97 NC |
746 | reg_names_hash = hash_new (); |
747 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR); | |
748 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR); | |
749 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR); | |
750 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); | |
751 | ||
b9c04e5a JW |
752 | /* Add "fp" as an alias for "s0". */ |
753 | hash_reg_name (RCLASS_GPR, "fp", 8); | |
754 | ||
0e35537d JW |
755 | opcode_names_hash = hash_new (); |
756 | init_opcode_names_hash (); | |
757 | ||
e23eba97 | 758 | #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num); |
1270b047 | 759 | #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num); |
e23eba97 NC |
760 | #include "opcode/riscv-opc.h" |
761 | #undef DECLARE_CSR | |
762 | ||
763 | /* Set the default alignment for the text section. */ | |
764 | record_alignment (text_section, riscv_opts.rvc ? 1 : 2); | |
765 | } | |
766 | ||
45f76423 AW |
767 | static insn_t |
768 | riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value) | |
769 | { | |
770 | switch (reloc_type) | |
771 | { | |
772 | case BFD_RELOC_32: | |
773 | return value; | |
774 | ||
775 | case BFD_RELOC_RISCV_HI20: | |
776 | return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)); | |
777 | ||
778 | case BFD_RELOC_RISCV_LO12_S: | |
779 | return ENCODE_STYPE_IMM (value); | |
780 | ||
781 | case BFD_RELOC_RISCV_LO12_I: | |
782 | return ENCODE_ITYPE_IMM (value); | |
783 | ||
784 | default: | |
785 | abort (); | |
786 | } | |
787 | } | |
788 | ||
e23eba97 NC |
789 | /* Output an instruction. IP is the instruction information. |
790 | ADDRESS_EXPR is an operand of the instruction to be used with | |
791 | RELOC_TYPE. */ | |
792 | ||
793 | static void | |
794 | append_insn (struct riscv_cl_insn *ip, expressionS *address_expr, | |
795 | bfd_reloc_code_real_type reloc_type) | |
796 | { | |
797 | dwarf2_emit_insn (0); | |
798 | ||
799 | if (reloc_type != BFD_RELOC_UNUSED) | |
800 | { | |
801 | reloc_howto_type *howto; | |
802 | ||
1d65abb5 | 803 | gas_assert (address_expr); |
e23eba97 NC |
804 | if (reloc_type == BFD_RELOC_12_PCREL |
805 | || reloc_type == BFD_RELOC_RISCV_JMP) | |
806 | { | |
807 | int j = reloc_type == BFD_RELOC_RISCV_JMP; | |
808 | int best_case = riscv_insn_length (ip->insn_opcode); | |
809 | unsigned worst_case = relaxed_branch_length (NULL, NULL, 0); | |
810 | add_relaxed_insn (ip, worst_case, best_case, | |
811 | RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case), | |
812 | address_expr->X_add_symbol, | |
813 | address_expr->X_add_number); | |
814 | return; | |
815 | } | |
45f76423 | 816 | else |
e23eba97 | 817 | { |
45f76423 AW |
818 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type); |
819 | if (howto == NULL) | |
820 | as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type); | |
e23eba97 | 821 | |
45f76423 AW |
822 | ip->fixp = fix_new_exp (ip->frag, ip->where, |
823 | bfd_get_reloc_size (howto), | |
824 | address_expr, FALSE, reloc_type); | |
e23eba97 | 825 | |
45f76423 | 826 | ip->fixp->fx_tcbit = riscv_opts.relax; |
e23eba97 | 827 | } |
e23eba97 NC |
828 | } |
829 | ||
e23eba97 NC |
830 | add_fixed_insn (ip); |
831 | install_insn (ip); | |
f77bb6c5 JW |
832 | |
833 | /* We need to start a new frag after any instruction that can be | |
834 | optimized away or compressed by the linker during relaxation, to prevent | |
835 | the assembler from computing static offsets across such an instruction. | |
836 | This is necessary to get correct EH info. */ | |
837 | if (reloc_type == BFD_RELOC_RISCV_CALL | |
838 | || reloc_type == BFD_RELOC_RISCV_CALL_PLT | |
839 | || reloc_type == BFD_RELOC_RISCV_HI20 | |
840 | || reloc_type == BFD_RELOC_RISCV_PCREL_HI20 | |
841 | || reloc_type == BFD_RELOC_RISCV_TPREL_HI20 | |
842 | || reloc_type == BFD_RELOC_RISCV_TPREL_ADD) | |
843 | { | |
844 | frag_wane (frag_now); | |
845 | frag_new (0); | |
846 | } | |
e23eba97 NC |
847 | } |
848 | ||
849 | /* Build an instruction created by a macro expansion. This is passed | |
850 | a pointer to the count of instructions created so far, an | |
851 | expression, the name of the instruction to build, an operand format | |
852 | string, and corresponding arguments. */ | |
853 | ||
854 | static void | |
855 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) | |
856 | { | |
857 | const struct riscv_opcode *mo; | |
858 | struct riscv_cl_insn insn; | |
859 | bfd_reloc_code_real_type r; | |
860 | va_list args; | |
861 | ||
862 | va_start (args, fmt); | |
863 | ||
864 | r = BFD_RELOC_UNUSED; | |
865 | mo = (struct riscv_opcode *) hash_find (op_hash, name); | |
866 | gas_assert (mo); | |
867 | ||
868 | /* Find a non-RVC variant of the instruction. append_insn will compress | |
869 | it if possible. */ | |
870 | while (riscv_insn_length (mo->match) < 4) | |
871 | mo++; | |
872 | gas_assert (strcmp (name, mo->name) == 0); | |
873 | ||
874 | create_insn (&insn, mo); | |
875 | for (;;) | |
876 | { | |
877 | switch (*fmt++) | |
878 | { | |
879 | case 'd': | |
880 | INSERT_OPERAND (RD, insn, va_arg (args, int)); | |
881 | continue; | |
882 | ||
883 | case 's': | |
884 | INSERT_OPERAND (RS1, insn, va_arg (args, int)); | |
885 | continue; | |
886 | ||
887 | case 't': | |
888 | INSERT_OPERAND (RS2, insn, va_arg (args, int)); | |
889 | continue; | |
890 | ||
891 | case '>': | |
892 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); | |
893 | continue; | |
894 | ||
895 | case 'j': | |
896 | case 'u': | |
897 | case 'q': | |
898 | gas_assert (ep != NULL); | |
899 | r = va_arg (args, int); | |
900 | continue; | |
901 | ||
902 | case '\0': | |
903 | break; | |
904 | case ',': | |
905 | continue; | |
906 | default: | |
907 | as_fatal (_("internal error: invalid macro")); | |
908 | } | |
909 | break; | |
910 | } | |
911 | va_end (args); | |
912 | gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
913 | ||
914 | append_insn (&insn, ep, r); | |
915 | } | |
916 | ||
917 | /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits | |
918 | unset. */ | |
919 | static void | |
920 | normalize_constant_expr (expressionS *ex) | |
921 | { | |
922 | if (xlen > 32) | |
923 | return; | |
924 | if ((ex->X_op == O_constant || ex->X_op == O_symbol) | |
925 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
926 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
927 | - 0x80000000); | |
928 | } | |
929 | ||
ca2fd32c JW |
930 | /* Fail if an expression EX is not a constant. IP is the instruction using EX. |
931 | MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */ | |
e23eba97 NC |
932 | |
933 | static void | |
ca2fd32c JW |
934 | check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex, |
935 | bfd_boolean maybe_csr) | |
e23eba97 NC |
936 | { |
937 | if (ex->X_op == O_big) | |
938 | as_bad (_("unsupported large constant")); | |
ca2fd32c JW |
939 | else if (maybe_csr && ex->X_op == O_symbol) |
940 | as_bad (_("unknown CSR `%s'"), | |
941 | S_GET_NAME (ex->X_add_symbol)); | |
e23eba97 NC |
942 | else if (ex->X_op != O_constant) |
943 | as_bad (_("Instruction %s requires absolute expression"), | |
944 | ip->insn_mo->name); | |
945 | normalize_constant_expr (ex); | |
946 | } | |
947 | ||
948 | static symbolS * | |
949 | make_internal_label (void) | |
950 | { | |
951 | return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, | |
1d65abb5 | 952 | (valueT) frag_now_fix (), frag_now); |
e23eba97 NC |
953 | } |
954 | ||
955 | /* Load an entry from the GOT. */ | |
956 | static void | |
957 | pcrel_access (int destreg, int tempreg, expressionS *ep, | |
958 | const char *lo_insn, const char *lo_pattern, | |
959 | bfd_reloc_code_real_type hi_reloc, | |
960 | bfd_reloc_code_real_type lo_reloc) | |
961 | { | |
962 | expressionS ep2; | |
963 | ep2.X_op = O_symbol; | |
964 | ep2.X_add_symbol = make_internal_label (); | |
965 | ep2.X_add_number = 0; | |
966 | ||
967 | macro_build (ep, "auipc", "d,u", tempreg, hi_reloc); | |
968 | macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc); | |
969 | } | |
970 | ||
971 | static void | |
972 | pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn, | |
973 | bfd_reloc_code_real_type hi_reloc, | |
974 | bfd_reloc_code_real_type lo_reloc) | |
975 | { | |
976 | pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc); | |
977 | } | |
978 | ||
979 | static void | |
980 | pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn, | |
981 | bfd_reloc_code_real_type hi_reloc, | |
982 | bfd_reloc_code_real_type lo_reloc) | |
983 | { | |
984 | pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc); | |
985 | } | |
986 | ||
987 | /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */ | |
988 | static void | |
989 | riscv_call (int destreg, int tempreg, expressionS *ep, | |
990 | bfd_reloc_code_real_type reloc) | |
991 | { | |
992 | macro_build (ep, "auipc", "d,u", tempreg, reloc); | |
993 | macro_build (NULL, "jalr", "d,s", destreg, tempreg); | |
994 | } | |
995 | ||
996 | /* Load an integer constant into a register. */ | |
997 | ||
998 | static void | |
999 | load_const (int reg, expressionS *ep) | |
1000 | { | |
1001 | int shift = RISCV_IMM_BITS; | |
1002 | expressionS upper = *ep, lower = *ep; | |
1003 | lower.X_add_number = (int32_t) ep->X_add_number << (32-shift) >> (32-shift); | |
1004 | upper.X_add_number -= lower.X_add_number; | |
1005 | ||
1006 | if (ep->X_op != O_constant) | |
1007 | { | |
1008 | as_bad (_("unsupported large constant")); | |
1009 | return; | |
1010 | } | |
1011 | ||
1d65abb5 | 1012 | if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number)) |
e23eba97 NC |
1013 | { |
1014 | /* Reduce to a signed 32-bit constant using SLLI and ADDI. */ | |
1015 | while (((upper.X_add_number >> shift) & 1) == 0) | |
1016 | shift++; | |
1017 | ||
1018 | upper.X_add_number = (int64_t) upper.X_add_number >> shift; | |
1d65abb5 | 1019 | load_const (reg, &upper); |
e23eba97 NC |
1020 | |
1021 | macro_build (NULL, "slli", "d,s,>", reg, reg, shift); | |
1022 | if (lower.X_add_number != 0) | |
1023 | macro_build (&lower, "addi", "d,s,j", reg, reg, BFD_RELOC_RISCV_LO12_I); | |
1024 | } | |
1025 | else | |
1026 | { | |
1027 | /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */ | |
1028 | int hi_reg = 0; | |
1029 | ||
1030 | if (upper.X_add_number != 0) | |
1031 | { | |
1032 | macro_build (ep, "lui", "d,u", reg, BFD_RELOC_RISCV_HI20); | |
1033 | hi_reg = reg; | |
1034 | } | |
1035 | ||
1036 | if (lower.X_add_number != 0 || hi_reg == 0) | |
1037 | macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg, | |
1038 | BFD_RELOC_RISCV_LO12_I); | |
1039 | } | |
1040 | } | |
1041 | ||
1042 | /* Expand RISC-V assembly macros into one or more instructions. */ | |
1043 | static void | |
1044 | macro (struct riscv_cl_insn *ip, expressionS *imm_expr, | |
1045 | bfd_reloc_code_real_type *imm_reloc) | |
1046 | { | |
1047 | int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD; | |
1048 | int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1; | |
1049 | int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; | |
1050 | int mask = ip->insn_mo->mask; | |
1051 | ||
1052 | switch (mask) | |
1053 | { | |
1054 | case M_LI: | |
1055 | load_const (rd, imm_expr); | |
1056 | break; | |
1057 | ||
1058 | case M_LA: | |
1059 | case M_LLA: | |
1060 | /* Load the address of a symbol into a register. */ | |
1061 | if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number)) | |
1062 | as_bad (_("offset too large")); | |
1063 | ||
1064 | if (imm_expr->X_op == O_constant) | |
1065 | load_const (rd, imm_expr); | |
1066 | else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */ | |
1067 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, | |
1068 | BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1069 | else /* Local PIC symbol, or any non-PIC symbol */ | |
1070 | pcrel_load (rd, rd, imm_expr, "addi", | |
1071 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1072 | break; | |
1073 | ||
1074 | case M_LA_TLS_GD: | |
1075 | pcrel_load (rd, rd, imm_expr, "addi", | |
1076 | BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1077 | break; | |
1078 | ||
1079 | case M_LA_TLS_IE: | |
1080 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, | |
1081 | BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1082 | break; | |
1083 | ||
1084 | case M_LB: | |
1085 | pcrel_load (rd, rd, imm_expr, "lb", | |
1086 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1087 | break; | |
1088 | ||
1089 | case M_LBU: | |
1090 | pcrel_load (rd, rd, imm_expr, "lbu", | |
1091 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1092 | break; | |
1093 | ||
1094 | case M_LH: | |
1095 | pcrel_load (rd, rd, imm_expr, "lh", | |
1096 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1097 | break; | |
1098 | ||
1099 | case M_LHU: | |
1100 | pcrel_load (rd, rd, imm_expr, "lhu", | |
1101 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1102 | break; | |
1103 | ||
1104 | case M_LW: | |
1105 | pcrel_load (rd, rd, imm_expr, "lw", | |
1106 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1107 | break; | |
1108 | ||
1109 | case M_LWU: | |
1110 | pcrel_load (rd, rd, imm_expr, "lwu", | |
1111 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1112 | break; | |
1113 | ||
1114 | case M_LD: | |
1115 | pcrel_load (rd, rd, imm_expr, "ld", | |
1116 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1117 | break; | |
1118 | ||
1119 | case M_FLW: | |
1120 | pcrel_load (rd, rs1, imm_expr, "flw", | |
1121 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1122 | break; | |
1123 | ||
1124 | case M_FLD: | |
1125 | pcrel_load (rd, rs1, imm_expr, "fld", | |
1126 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
1127 | break; | |
1128 | ||
1129 | case M_SB: | |
1130 | pcrel_store (rs2, rs1, imm_expr, "sb", | |
1131 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1132 | break; | |
1133 | ||
1134 | case M_SH: | |
1135 | pcrel_store (rs2, rs1, imm_expr, "sh", | |
1136 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1137 | break; | |
1138 | ||
1139 | case M_SW: | |
1140 | pcrel_store (rs2, rs1, imm_expr, "sw", | |
1141 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1142 | break; | |
1143 | ||
1144 | case M_SD: | |
1145 | pcrel_store (rs2, rs1, imm_expr, "sd", | |
1146 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1147 | break; | |
1148 | ||
1149 | case M_FSW: | |
1150 | pcrel_store (rs2, rs1, imm_expr, "fsw", | |
1151 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1152 | break; | |
1153 | ||
1154 | case M_FSD: | |
1155 | pcrel_store (rs2, rs1, imm_expr, "fsd", | |
1156 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
1157 | break; | |
1158 | ||
1159 | case M_CALL: | |
1160 | riscv_call (rd, rs1, imm_expr, *imm_reloc); | |
1161 | break; | |
1162 | ||
1163 | default: | |
1164 | as_bad (_("Macro %s not implemented"), ip->insn_mo->name); | |
1165 | break; | |
1166 | } | |
1167 | } | |
1168 | ||
1169 | static const struct percent_op_match percent_op_utype[] = | |
1170 | { | |
1171 | {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, | |
1172 | {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, | |
1173 | {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, | |
1174 | {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, | |
1175 | {"%hi", BFD_RELOC_RISCV_HI20}, | |
1176 | {0, 0} | |
1177 | }; | |
1178 | ||
1179 | static const struct percent_op_match percent_op_itype[] = | |
1180 | { | |
1181 | {"%lo", BFD_RELOC_RISCV_LO12_I}, | |
1182 | {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, | |
1183 | {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, | |
1184 | {0, 0} | |
1185 | }; | |
1186 | ||
1187 | static const struct percent_op_match percent_op_stype[] = | |
1188 | { | |
1189 | {"%lo", BFD_RELOC_RISCV_LO12_S}, | |
1190 | {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S}, | |
1191 | {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S}, | |
1192 | {0, 0} | |
1193 | }; | |
1194 | ||
1195 | static const struct percent_op_match percent_op_rtype[] = | |
1196 | { | |
1197 | {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, | |
1198 | {0, 0} | |
1199 | }; | |
1200 | ||
1201 | /* Return true if *STR points to a relocation operator. When returning true, | |
1202 | move *STR over the operator and store its relocation code in *RELOC. | |
1203 | Leave both *STR and *RELOC alone when returning false. */ | |
1204 | ||
1205 | static bfd_boolean | |
1206 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc, | |
1207 | const struct percent_op_match *percent_op) | |
1208 | { | |
1209 | for ( ; percent_op->str; percent_op++) | |
1210 | if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0) | |
1211 | { | |
1212 | int len = strlen (percent_op->str); | |
1213 | ||
1214 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
1215 | continue; | |
1216 | ||
1217 | *str += strlen (percent_op->str); | |
1218 | *reloc = percent_op->reloc; | |
1219 | ||
1220 | /* Check whether the output BFD supports this relocation. | |
1221 | If not, issue an error and fall back on something safe. */ | |
45f76423 AW |
1222 | if (*reloc != BFD_RELOC_UNUSED |
1223 | && !bfd_reloc_type_lookup (stdoutput, *reloc)) | |
e23eba97 NC |
1224 | { |
1225 | as_bad ("relocation %s isn't supported by the current ABI", | |
1226 | percent_op->str); | |
1227 | *reloc = BFD_RELOC_UNUSED; | |
1228 | } | |
1229 | return TRUE; | |
1230 | } | |
1231 | return FALSE; | |
1232 | } | |
1233 | ||
1234 | static void | |
1235 | my_getExpression (expressionS *ep, char *str) | |
1236 | { | |
1237 | char *save_in; | |
1238 | ||
1239 | save_in = input_line_pointer; | |
1240 | input_line_pointer = str; | |
1241 | expression (ep); | |
1242 | expr_end = input_line_pointer; | |
1243 | input_line_pointer = save_in; | |
1244 | } | |
1245 | ||
1246 | /* Parse string STR as a 16-bit relocatable operand. Store the | |
1247 | expression in *EP and the relocation, if any, in RELOC. | |
1248 | Return the number of relocation operators used (0 or 1). | |
1249 | ||
1250 | On exit, EXPR_END points to the first character after the expression. */ | |
1251 | ||
1252 | static size_t | |
1253 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, | |
1254 | char *str, const struct percent_op_match *percent_op) | |
1255 | { | |
1256 | size_t reloc_index; | |
1257 | unsigned crux_depth, str_depth, regno; | |
1258 | char *crux; | |
1259 | ||
1260 | /* First, check for integer registers. */ | |
1261 | if (reg_lookup (&str, RCLASS_GPR, ®no)) | |
1262 | { | |
1263 | ep->X_op = O_register; | |
1264 | ep->X_add_number = regno; | |
1265 | return 0; | |
1266 | } | |
1267 | ||
1268 | /* Search for the start of the main expression. | |
1269 | End the loop with CRUX pointing to the start | |
1270 | of the main expression and with CRUX_DEPTH containing the number | |
1271 | of open brackets at that point. */ | |
1272 | reloc_index = -1; | |
1273 | str_depth = 0; | |
1274 | do | |
1275 | { | |
1276 | reloc_index++; | |
1277 | crux = str; | |
1278 | crux_depth = str_depth; | |
1279 | ||
1280 | /* Skip over whitespace and brackets, keeping count of the number | |
1281 | of brackets. */ | |
1282 | while (*str == ' ' || *str == '\t' || *str == '(') | |
1283 | if (*str++ == '(') | |
1284 | str_depth++; | |
1285 | } | |
1286 | while (*str == '%' | |
1287 | && reloc_index < 1 | |
1288 | && parse_relocation (&str, reloc, percent_op)); | |
1289 | ||
1290 | my_getExpression (ep, crux); | |
1291 | str = expr_end; | |
1292 | ||
1293 | /* Match every open bracket. */ | |
1294 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) | |
1295 | if (*str++ == ')') | |
1296 | crux_depth--; | |
1297 | ||
1298 | if (crux_depth > 0) | |
1299 | as_bad ("unclosed '('"); | |
1300 | ||
1301 | expr_end = str; | |
1302 | ||
1303 | return reloc_index; | |
1304 | } | |
1305 | ||
0e35537d JW |
1306 | /* Parse opcode name, could be an mnemonics or number. */ |
1307 | static size_t | |
1308 | my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, | |
1309 | char *str, const struct percent_op_match *percent_op) | |
1310 | { | |
1311 | const struct opcode_name_t *o = opcode_name_lookup (&str); | |
1312 | ||
1313 | if (o != NULL) | |
1314 | { | |
1315 | ep->X_op = O_constant; | |
1316 | ep->X_add_number = o->val; | |
1317 | return 0; | |
1318 | } | |
1319 | ||
1320 | return my_getSmallExpression (ep, reloc, str, percent_op); | |
1321 | } | |
1322 | ||
f0531ed6 JW |
1323 | /* Detect and handle implicitly zero load-store offsets. For example, |
1324 | "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such | |
1325 | an implicit offset was detected. */ | |
1326 | ||
1327 | static bfd_boolean | |
89424b1d | 1328 | riscv_handle_implicit_zero_offset (expressionS *ep, const char *s) |
f0531ed6 JW |
1329 | { |
1330 | /* Check whether there is only a single bracketed expression left. | |
1331 | If so, it must be the base register and the constant must be zero. */ | |
1332 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
1333 | { | |
89424b1d MR |
1334 | ep->X_op = O_constant; |
1335 | ep->X_add_number = 0; | |
f0531ed6 JW |
1336 | return TRUE; |
1337 | } | |
1338 | ||
1339 | return FALSE; | |
1340 | } | |
1341 | ||
e23eba97 NC |
1342 | /* This routine assembles an instruction into its binary format. As a |
1343 | side effect, it sets the global variable imm_reloc to the type of | |
1344 | relocation to do if one of the operands is an address expression. */ | |
1345 | ||
1346 | static const char * | |
1347 | riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, | |
0e35537d | 1348 | bfd_reloc_code_real_type *imm_reloc, struct hash_control *hash) |
e23eba97 NC |
1349 | { |
1350 | char *s; | |
1351 | const char *args; | |
1352 | char c = 0; | |
1353 | struct riscv_opcode *insn; | |
1354 | char *argsStart; | |
1355 | unsigned int regno; | |
1356 | char save_c = 0; | |
1357 | int argnum; | |
1358 | const struct percent_op_match *p; | |
1359 | const char *error = "unrecognized opcode"; | |
1360 | ||
1361 | /* Parse the name of the instruction. Terminate the string if whitespace | |
1362 | is found so that hash_find only sees the name part of the string. */ | |
1363 | for (s = str; *s != '\0'; ++s) | |
1364 | if (ISSPACE (*s)) | |
1365 | { | |
1366 | save_c = *s; | |
1367 | *s++ = '\0'; | |
1368 | break; | |
1369 | } | |
1370 | ||
0e35537d | 1371 | insn = (struct riscv_opcode *) hash_find (hash, str); |
e23eba97 NC |
1372 | |
1373 | argsStart = s; | |
1374 | for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++) | |
1375 | { | |
1080bf78 JW |
1376 | if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement)) |
1377 | continue; | |
1378 | ||
1379 | if (!riscv_multi_subset_supports (insn->subset)) | |
e23eba97 NC |
1380 | continue; |
1381 | ||
1382 | create_insn (ip, insn); | |
1383 | argnum = 1; | |
1384 | ||
1385 | imm_expr->X_op = O_absent; | |
1386 | *imm_reloc = BFD_RELOC_UNUSED; | |
1387 | p = percent_op_itype; | |
1388 | ||
1389 | for (args = insn->args;; ++args) | |
1390 | { | |
1391 | s += strspn (s, " \t"); | |
1392 | switch (*args) | |
1393 | { | |
1394 | case '\0': /* End of args. */ | |
1395 | if (insn->pinfo != INSN_MACRO) | |
1396 | { | |
1397 | if (!insn->match_func (insn, ip->insn_opcode)) | |
1398 | break; | |
0e35537d JW |
1399 | |
1400 | /* For .insn, insn->match and insn->mask are 0. */ | |
1401 | if (riscv_insn_length ((insn->match == 0 && insn->mask == 0) | |
1402 | ? ip->insn_opcode | |
1403 | : insn->match) == 2 | |
1404 | && !riscv_opts.rvc) | |
e23eba97 NC |
1405 | break; |
1406 | } | |
1407 | if (*s != '\0') | |
1408 | break; | |
1409 | /* Successful assembly. */ | |
1410 | error = NULL; | |
1411 | goto out; | |
1412 | ||
1413 | case 'C': /* RVC */ | |
1414 | switch (*++args) | |
1415 | { | |
1416 | case 's': /* RS1 x8-x15 */ | |
1417 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1418 | || !(regno >= 8 && regno <= 15)) | |
1419 | break; | |
1420 | INSERT_OPERAND (CRS1S, *ip, regno % 8); | |
1421 | continue; | |
1422 | case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */ | |
1423 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1424 | || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno) | |
1425 | break; | |
1426 | continue; | |
1427 | case 't': /* RS2 x8-x15 */ | |
1428 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1429 | || !(regno >= 8 && regno <= 15)) | |
1430 | break; | |
1431 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
1432 | continue; | |
1433 | case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */ | |
1434 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1435 | || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno) | |
1436 | break; | |
1437 | continue; | |
1438 | case 'U': /* RS1, constrained to equal RD. */ | |
1439 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1440 | || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno) | |
1441 | break; | |
1442 | continue; | |
1443 | case 'V': /* RS2 */ | |
1444 | if (!reg_lookup (&s, RCLASS_GPR, ®no)) | |
1445 | break; | |
1446 | INSERT_OPERAND (CRS2, *ip, regno); | |
1447 | continue; | |
1448 | case 'c': /* RS1, constrained to equal sp. */ | |
1449 | if (!reg_lookup (&s, RCLASS_GPR, ®no) | |
1450 | || regno != X_SP) | |
1451 | break; | |
1452 | continue; | |
1453 | case '>': | |
1454 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1455 | || imm_expr->X_op != O_constant | |
1456 | || imm_expr->X_add_number <= 0 | |
1457 | || imm_expr->X_add_number >= 64) | |
1458 | break; | |
1459 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1460 | rvc_imm_done: | |
1461 | s = expr_end; | |
1462 | imm_expr->X_op = O_absent; | |
1463 | continue; | |
1464 | case '<': | |
1465 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1466 | || imm_expr->X_op != O_constant | |
1467 | || !VALID_RVC_IMM (imm_expr->X_add_number) | |
1468 | || imm_expr->X_add_number <= 0 | |
1469 | || imm_expr->X_add_number >= 32) | |
1470 | break; | |
1471 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1472 | goto rvc_imm_done; | |
0e35537d JW |
1473 | case '8': |
1474 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1475 | || imm_expr->X_op != O_constant | |
1476 | || !VALID_RVC_UIMM8 (imm_expr->X_add_number) | |
1477 | || imm_expr->X_add_number < 0 | |
1478 | || imm_expr->X_add_number >= 256) | |
1479 | break; | |
1480 | ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number); | |
1481 | goto rvc_imm_done; | |
e23eba97 NC |
1482 | case 'i': |
1483 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1484 | || imm_expr->X_op != O_constant | |
1485 | || imm_expr->X_add_number == 0 | |
1486 | || !VALID_RVC_SIMM3 (imm_expr->X_add_number)) | |
1487 | break; | |
1488 | ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number); | |
1489 | goto rvc_imm_done; | |
1490 | case 'j': | |
1491 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1492 | || imm_expr->X_op != O_constant | |
1493 | || imm_expr->X_add_number == 0 | |
1494 | || !VALID_RVC_IMM (imm_expr->X_add_number)) | |
1495 | break; | |
1496 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1497 | goto rvc_imm_done; | |
1498 | case 'k': | |
f0531ed6 JW |
1499 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1500 | continue; | |
e23eba97 NC |
1501 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1502 | || imm_expr->X_op != O_constant | |
1503 | || !VALID_RVC_LW_IMM (imm_expr->X_add_number)) | |
1504 | break; | |
1505 | ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number); | |
1506 | goto rvc_imm_done; | |
1507 | case 'l': | |
f0531ed6 JW |
1508 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1509 | continue; | |
e23eba97 NC |
1510 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1511 | || imm_expr->X_op != O_constant | |
1512 | || !VALID_RVC_LD_IMM (imm_expr->X_add_number)) | |
1513 | break; | |
1514 | ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number); | |
1515 | goto rvc_imm_done; | |
1516 | case 'm': | |
f0531ed6 JW |
1517 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1518 | continue; | |
e23eba97 NC |
1519 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1520 | || imm_expr->X_op != O_constant | |
1521 | || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number)) | |
1522 | break; | |
1523 | ip->insn_opcode |= | |
1524 | ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number); | |
1525 | goto rvc_imm_done; | |
1526 | case 'n': | |
f0531ed6 JW |
1527 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1528 | continue; | |
e23eba97 NC |
1529 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1530 | || imm_expr->X_op != O_constant | |
1531 | || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number)) | |
1532 | break; | |
1533 | ip->insn_opcode |= | |
1534 | ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number); | |
1535 | goto rvc_imm_done; | |
b416fe87 KC |
1536 | case 'o': |
1537 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1538 | || imm_expr->X_op != O_constant | |
21a186f2 JW |
1539 | /* C.addiw, c.li, and c.andi allow zero immediate. |
1540 | C.addi allows zero immediate as hint. Otherwise this | |
1541 | is same as 'j'. */ | |
b416fe87 KC |
1542 | || !VALID_RVC_IMM (imm_expr->X_add_number)) |
1543 | break; | |
1544 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1545 | goto rvc_imm_done; | |
e23eba97 NC |
1546 | case 'K': |
1547 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1548 | || imm_expr->X_op != O_constant | |
1549 | || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number) | |
1550 | || imm_expr->X_add_number == 0) | |
1551 | break; | |
1552 | ip->insn_opcode |= | |
1553 | ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number); | |
1554 | goto rvc_imm_done; | |
1555 | case 'L': | |
1556 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1557 | || imm_expr->X_op != O_constant | |
1558 | || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number) | |
1559 | || imm_expr->X_add_number == 0) | |
1560 | break; | |
1561 | ip->insn_opcode |= | |
1562 | ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number); | |
1563 | goto rvc_imm_done; | |
1564 | case 'M': | |
f0531ed6 JW |
1565 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1566 | continue; | |
e23eba97 NC |
1567 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1568 | || imm_expr->X_op != O_constant | |
1569 | || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number)) | |
1570 | break; | |
1571 | ip->insn_opcode |= | |
1572 | ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number); | |
1573 | goto rvc_imm_done; | |
1574 | case 'N': | |
f0531ed6 JW |
1575 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
1576 | continue; | |
e23eba97 NC |
1577 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) |
1578 | || imm_expr->X_op != O_constant | |
1579 | || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number)) | |
1580 | break; | |
1581 | ip->insn_opcode |= | |
1582 | ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number); | |
1583 | goto rvc_imm_done; | |
1584 | case 'u': | |
1585 | p = percent_op_utype; | |
1586 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p)) | |
1587 | break; | |
1588 | rvc_lui: | |
1589 | if (imm_expr->X_op != O_constant | |
1590 | || imm_expr->X_add_number <= 0 | |
1591 | || imm_expr->X_add_number >= RISCV_BIGIMM_REACH | |
1592 | || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2 | |
1593 | && (imm_expr->X_add_number < | |
1594 | RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2))) | |
1595 | break; | |
1596 | ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); | |
1597 | goto rvc_imm_done; | |
1598 | case 'v': | |
1599 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1600 | || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1)) | |
1601 | || ((int32_t)imm_expr->X_add_number | |
1602 | != imm_expr->X_add_number)) | |
1603 | break; | |
1604 | imm_expr->X_add_number = | |
1605 | ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS; | |
1606 | goto rvc_lui; | |
1607 | case 'p': | |
1608 | goto branch; | |
1609 | case 'a': | |
1610 | goto jump; | |
0e35537d JW |
1611 | case 'S': /* Floating-point RS1 x8-x15. */ |
1612 | if (!reg_lookup (&s, RCLASS_FPR, ®no) | |
1613 | || !(regno >= 8 && regno <= 15)) | |
1614 | break; | |
1615 | INSERT_OPERAND (CRS1S, *ip, regno % 8); | |
1616 | continue; | |
e23eba97 NC |
1617 | case 'D': /* Floating-point RS2 x8-x15. */ |
1618 | if (!reg_lookup (&s, RCLASS_FPR, ®no) | |
1619 | || !(regno >= 8 && regno <= 15)) | |
1620 | break; | |
1621 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
1622 | continue; | |
1623 | case 'T': /* Floating-point RS2. */ | |
1624 | if (!reg_lookup (&s, RCLASS_FPR, ®no)) | |
1625 | break; | |
1626 | INSERT_OPERAND (CRS2, *ip, regno); | |
1627 | continue; | |
0e35537d JW |
1628 | case 'F': |
1629 | switch (*++args) | |
1630 | { | |
4765cd61 JW |
1631 | case '6': |
1632 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1633 | || imm_expr->X_op != O_constant | |
1634 | || imm_expr->X_add_number < 0 | |
1635 | || imm_expr->X_add_number >= 64) | |
1636 | { | |
1637 | as_bad (_("bad value for funct6 field, " | |
1638 | "value must be 0...64")); | |
1639 | break; | |
1640 | } | |
1641 | ||
1642 | INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number); | |
1643 | imm_expr->X_op = O_absent; | |
1644 | s = expr_end; | |
1645 | continue; | |
0e35537d JW |
1646 | case '4': |
1647 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1648 | || imm_expr->X_op != O_constant | |
1649 | || imm_expr->X_add_number < 0 | |
1650 | || imm_expr->X_add_number >= 16) | |
1651 | { | |
1652 | as_bad (_("bad value for funct4 field, " | |
1653 | "value must be 0...15")); | |
1654 | break; | |
1655 | } | |
1656 | ||
1657 | INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number); | |
1658 | imm_expr->X_op = O_absent; | |
1659 | s = expr_end; | |
1660 | continue; | |
1661 | case '3': | |
1662 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1663 | || imm_expr->X_op != O_constant | |
1664 | || imm_expr->X_add_number < 0 | |
1665 | || imm_expr->X_add_number >= 8) | |
1666 | { | |
1667 | as_bad (_("bad value for funct3 field, " | |
1668 | "value must be 0...7")); | |
1669 | break; | |
1670 | } | |
1671 | INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number); | |
1672 | imm_expr->X_op = O_absent; | |
1673 | s = expr_end; | |
1674 | continue; | |
4765cd61 JW |
1675 | case '2': |
1676 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1677 | || imm_expr->X_op != O_constant | |
1678 | || imm_expr->X_add_number < 0 | |
1679 | || imm_expr->X_add_number >= 4) | |
1680 | { | |
1681 | as_bad (_("bad value for funct2 field, " | |
1682 | "value must be 0...3")); | |
1683 | break; | |
1684 | } | |
1685 | INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number); | |
1686 | imm_expr->X_op = O_absent; | |
1687 | s = expr_end; | |
1688 | continue; | |
0e35537d JW |
1689 | default: |
1690 | as_bad (_("bad compressed FUNCT field" | |
1691 | " specifier 'CF%c'\n"), | |
1692 | *args); | |
1693 | } | |
1694 | break; | |
1695 | ||
e23eba97 NC |
1696 | default: |
1697 | as_bad (_("bad RVC field specifier 'C%c'\n"), *args); | |
1698 | } | |
1699 | break; | |
1700 | ||
1701 | case ',': | |
1702 | ++argnum; | |
1703 | if (*s++ == *args) | |
1704 | continue; | |
1705 | s--; | |
1706 | break; | |
1707 | ||
1708 | case '(': | |
1709 | case ')': | |
1710 | case '[': | |
1711 | case ']': | |
1712 | if (*s++ == *args) | |
1713 | continue; | |
1714 | break; | |
1715 | ||
1716 | case '<': /* Shift amount, 0 - 31. */ | |
1717 | my_getExpression (imm_expr, s); | |
ca2fd32c | 1718 | check_absolute_expr (ip, imm_expr, FALSE); |
e23eba97 | 1719 | if ((unsigned long) imm_expr->X_add_number > 31) |
94f78a77 AW |
1720 | as_bad (_("Improper shift amount (%lu)"), |
1721 | (unsigned long) imm_expr->X_add_number); | |
e23eba97 NC |
1722 | INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number); |
1723 | imm_expr->X_op = O_absent; | |
1724 | s = expr_end; | |
1725 | continue; | |
1726 | ||
1727 | case '>': /* Shift amount, 0 - (XLEN-1). */ | |
1728 | my_getExpression (imm_expr, s); | |
ca2fd32c | 1729 | check_absolute_expr (ip, imm_expr, FALSE); |
e23eba97 | 1730 | if ((unsigned long) imm_expr->X_add_number >= xlen) |
94f78a77 AW |
1731 | as_bad (_("Improper shift amount (%lu)"), |
1732 | (unsigned long) imm_expr->X_add_number); | |
e23eba97 NC |
1733 | INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number); |
1734 | imm_expr->X_op = O_absent; | |
1735 | s = expr_end; | |
1736 | continue; | |
1737 | ||
1738 | case 'Z': /* CSRRxI immediate. */ | |
1739 | my_getExpression (imm_expr, s); | |
ca2fd32c | 1740 | check_absolute_expr (ip, imm_expr, FALSE); |
e23eba97 | 1741 | if ((unsigned long) imm_expr->X_add_number > 31) |
94f78a77 AW |
1742 | as_bad (_("Improper CSRxI immediate (%lu)"), |
1743 | (unsigned long) imm_expr->X_add_number); | |
e23eba97 NC |
1744 | INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number); |
1745 | imm_expr->X_op = O_absent; | |
1746 | s = expr_end; | |
1747 | continue; | |
1748 | ||
1749 | case 'E': /* Control register. */ | |
1750 | if (reg_lookup (&s, RCLASS_CSR, ®no)) | |
1751 | INSERT_OPERAND (CSR, *ip, regno); | |
1752 | else | |
1753 | { | |
1754 | my_getExpression (imm_expr, s); | |
ca2fd32c | 1755 | check_absolute_expr (ip, imm_expr, TRUE); |
e23eba97 | 1756 | if ((unsigned long) imm_expr->X_add_number > 0xfff) |
94f78a77 AW |
1757 | as_bad (_("Improper CSR address (%lu)"), |
1758 | (unsigned long) imm_expr->X_add_number); | |
e23eba97 NC |
1759 | INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number); |
1760 | imm_expr->X_op = O_absent; | |
1761 | s = expr_end; | |
1762 | } | |
1763 | continue; | |
1764 | ||
1765 | case 'm': /* Rounding mode. */ | |
1766 | if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), ®no)) | |
1767 | { | |
1768 | INSERT_OPERAND (RM, *ip, regno); | |
1769 | continue; | |
1770 | } | |
1771 | break; | |
1772 | ||
1773 | case 'P': | |
1774 | case 'Q': /* Fence predecessor/successor. */ | |
1775 | if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ), | |
1776 | ®no)) | |
1777 | { | |
1778 | if (*args == 'P') | |
1779 | INSERT_OPERAND (PRED, *ip, regno); | |
1780 | else | |
1781 | INSERT_OPERAND (SUCC, *ip, regno); | |
1782 | continue; | |
1783 | } | |
1784 | break; | |
1785 | ||
1786 | case 'd': /* Destination register. */ | |
1787 | case 's': /* Source register. */ | |
1788 | case 't': /* Target register. */ | |
0e35537d | 1789 | case 'r': /* rs3. */ |
e23eba97 NC |
1790 | if (reg_lookup (&s, RCLASS_GPR, ®no)) |
1791 | { | |
1792 | c = *args; | |
1793 | if (*s == ' ') | |
1794 | ++s; | |
1795 | ||
1796 | /* Now that we have assembled one operand, we use the args | |
1797 | string to figure out where it goes in the instruction. */ | |
1798 | switch (c) | |
1799 | { | |
1800 | case 's': | |
1801 | INSERT_OPERAND (RS1, *ip, regno); | |
1802 | break; | |
1803 | case 'd': | |
1804 | INSERT_OPERAND (RD, *ip, regno); | |
1805 | break; | |
1806 | case 't': | |
1807 | INSERT_OPERAND (RS2, *ip, regno); | |
1808 | break; | |
0e35537d JW |
1809 | case 'r': |
1810 | INSERT_OPERAND (RS3, *ip, regno); | |
1811 | break; | |
e23eba97 NC |
1812 | } |
1813 | continue; | |
1814 | } | |
1815 | break; | |
1816 | ||
1817 | case 'D': /* Floating point rd. */ | |
1818 | case 'S': /* Floating point rs1. */ | |
1819 | case 'T': /* Floating point rs2. */ | |
1820 | case 'U': /* Floating point rs1 and rs2. */ | |
1821 | case 'R': /* Floating point rs3. */ | |
1822 | if (reg_lookup (&s, RCLASS_FPR, ®no)) | |
1823 | { | |
1824 | c = *args; | |
1825 | if (*s == ' ') | |
1826 | ++s; | |
1827 | switch (c) | |
1828 | { | |
1829 | case 'D': | |
1830 | INSERT_OPERAND (RD, *ip, regno); | |
1831 | break; | |
1832 | case 'S': | |
1833 | INSERT_OPERAND (RS1, *ip, regno); | |
1834 | break; | |
1835 | case 'U': | |
1836 | INSERT_OPERAND (RS1, *ip, regno); | |
1837 | /* fallthru */ | |
1838 | case 'T': | |
1839 | INSERT_OPERAND (RS2, *ip, regno); | |
1840 | break; | |
1841 | case 'R': | |
1842 | INSERT_OPERAND (RS3, *ip, regno); | |
1843 | break; | |
1844 | } | |
1845 | continue; | |
1846 | } | |
1847 | ||
1848 | break; | |
1849 | ||
1850 | case 'I': | |
1851 | my_getExpression (imm_expr, s); | |
1852 | if (imm_expr->X_op != O_big | |
1853 | && imm_expr->X_op != O_constant) | |
1854 | break; | |
1855 | normalize_constant_expr (imm_expr); | |
1856 | s = expr_end; | |
1857 | continue; | |
1858 | ||
1859 | case 'A': | |
1860 | my_getExpression (imm_expr, s); | |
1861 | normalize_constant_expr (imm_expr); | |
1862 | /* The 'A' format specifier must be a symbol. */ | |
1863 | if (imm_expr->X_op != O_symbol) | |
1864 | break; | |
1865 | *imm_reloc = BFD_RELOC_32; | |
1866 | s = expr_end; | |
1867 | continue; | |
1868 | ||
160d1b3d SH |
1869 | case 'B': |
1870 | my_getExpression (imm_expr, s); | |
1871 | normalize_constant_expr (imm_expr); | |
1872 | /* The 'B' format specifier must be a symbol or a constant. */ | |
1873 | if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant) | |
1874 | break; | |
1875 | if (imm_expr->X_op == O_symbol) | |
1876 | *imm_reloc = BFD_RELOC_32; | |
1877 | s = expr_end; | |
1878 | continue; | |
1879 | ||
e23eba97 NC |
1880 | case 'j': /* Sign-extended immediate. */ |
1881 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; | |
1882 | p = percent_op_itype; | |
1883 | goto alu_op; | |
1884 | case 'q': /* Store displacement. */ | |
1885 | p = percent_op_stype; | |
1886 | *imm_reloc = BFD_RELOC_RISCV_LO12_S; | |
1887 | goto load_store; | |
1888 | case 'o': /* Load displacement. */ | |
1889 | p = percent_op_itype; | |
1890 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; | |
1891 | goto load_store; | |
1892 | case '0': /* AMO "displacement," which must be zero. */ | |
1893 | p = percent_op_rtype; | |
1894 | *imm_reloc = BFD_RELOC_UNUSED; | |
1895 | load_store: | |
f0531ed6 | 1896 | if (riscv_handle_implicit_zero_offset (imm_expr, s)) |
e23eba97 NC |
1897 | continue; |
1898 | alu_op: | |
1899 | /* If this value won't fit into a 16 bit offset, then go | |
1900 | find a macro that will generate the 32 bit offset | |
1901 | code pattern. */ | |
1902 | if (!my_getSmallExpression (imm_expr, imm_reloc, s, p)) | |
1903 | { | |
1904 | normalize_constant_expr (imm_expr); | |
1905 | if (imm_expr->X_op != O_constant | |
1906 | || (*args == '0' && imm_expr->X_add_number != 0) | |
1907 | || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2 | |
1908 | || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2) | |
1909 | break; | |
1910 | } | |
1911 | ||
1912 | s = expr_end; | |
1913 | continue; | |
1914 | ||
1915 | case 'p': /* PC-relative offset. */ | |
1916 | branch: | |
1917 | *imm_reloc = BFD_RELOC_12_PCREL; | |
1918 | my_getExpression (imm_expr, s); | |
1919 | s = expr_end; | |
1920 | continue; | |
1921 | ||
1922 | case 'u': /* Upper 20 bits. */ | |
1923 | p = percent_op_utype; | |
1924 | if (!my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
1925 | && imm_expr->X_op == O_constant) | |
1926 | { | |
1927 | if (imm_expr->X_add_number < 0 | |
1928 | || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH) | |
1929 | as_bad (_("lui expression not in range 0..1048575")); | |
1930 | ||
1931 | *imm_reloc = BFD_RELOC_RISCV_HI20; | |
1932 | imm_expr->X_add_number <<= RISCV_IMM_BITS; | |
1933 | } | |
1934 | s = expr_end; | |
1935 | continue; | |
1936 | ||
1937 | case 'a': /* 20-bit PC-relative offset. */ | |
1938 | jump: | |
1939 | my_getExpression (imm_expr, s); | |
1940 | s = expr_end; | |
1941 | *imm_reloc = BFD_RELOC_RISCV_JMP; | |
1942 | continue; | |
1943 | ||
1944 | case 'c': | |
1945 | my_getExpression (imm_expr, s); | |
1946 | s = expr_end; | |
1947 | if (strcmp (s, "@plt") == 0) | |
1948 | { | |
1949 | *imm_reloc = BFD_RELOC_RISCV_CALL_PLT; | |
1950 | s += 4; | |
1951 | } | |
1952 | else | |
1953 | *imm_reloc = BFD_RELOC_RISCV_CALL; | |
1954 | continue; | |
0e35537d JW |
1955 | case 'O': |
1956 | switch (*++args) | |
1957 | { | |
1958 | case '4': | |
1959 | if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p) | |
1960 | || imm_expr->X_op != O_constant | |
1961 | || imm_expr->X_add_number < 0 | |
1962 | || imm_expr->X_add_number >= 128 | |
1963 | || (imm_expr->X_add_number & 0x3) != 3) | |
1964 | { | |
1965 | as_bad (_("bad value for opcode field, " | |
1966 | "value must be 0...127 and " | |
1967 | "lower 2 bits must be 0x3")); | |
1968 | break; | |
1969 | } | |
1970 | ||
1971 | INSERT_OPERAND (OP, *ip, imm_expr->X_add_number); | |
1972 | imm_expr->X_op = O_absent; | |
1973 | s = expr_end; | |
1974 | continue; | |
1975 | case '2': | |
1976 | if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p) | |
1977 | || imm_expr->X_op != O_constant | |
1978 | || imm_expr->X_add_number < 0 | |
1979 | || imm_expr->X_add_number >= 3) | |
1980 | { | |
1981 | as_bad (_("bad value for opcode field, " | |
1982 | "value must be 0...2")); | |
1983 | break; | |
1984 | } | |
1985 | ||
1986 | INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number); | |
1987 | imm_expr->X_op = O_absent; | |
1988 | s = expr_end; | |
1989 | continue; | |
1990 | default: | |
1991 | as_bad (_("bad Opcode field specifier 'O%c'\n"), *args); | |
1992 | } | |
1993 | break; | |
1994 | ||
1995 | case 'F': | |
1996 | switch (*++args) | |
1997 | { | |
1998 | case '7': | |
1999 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
2000 | || imm_expr->X_op != O_constant | |
2001 | || imm_expr->X_add_number < 0 | |
2002 | || imm_expr->X_add_number >= 128) | |
2003 | { | |
2004 | as_bad (_("bad value for funct7 field, " | |
2005 | "value must be 0...127")); | |
2006 | break; | |
2007 | } | |
2008 | ||
2009 | INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number); | |
2010 | imm_expr->X_op = O_absent; | |
2011 | s = expr_end; | |
2012 | continue; | |
2013 | case '3': | |
2014 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
2015 | || imm_expr->X_op != O_constant | |
2016 | || imm_expr->X_add_number < 0 | |
2017 | || imm_expr->X_add_number >= 8) | |
2018 | { | |
2019 | as_bad (_("bad value for funct3 field, " | |
2020 | "value must be 0...7")); | |
2021 | break; | |
2022 | } | |
2023 | ||
2024 | INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number); | |
2025 | imm_expr->X_op = O_absent; | |
2026 | s = expr_end; | |
2027 | continue; | |
2028 | case '2': | |
2029 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
2030 | || imm_expr->X_op != O_constant | |
2031 | || imm_expr->X_add_number < 0 | |
2032 | || imm_expr->X_add_number >= 4) | |
2033 | { | |
2034 | as_bad (_("bad value for funct2 field, " | |
2035 | "value must be 0...3")); | |
2036 | break; | |
2037 | } | |
2038 | ||
2039 | INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number); | |
2040 | imm_expr->X_op = O_absent; | |
2041 | s = expr_end; | |
2042 | continue; | |
2043 | ||
2044 | default: | |
2045 | as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args); | |
2046 | } | |
2047 | break; | |
e23eba97 | 2048 | |
e925c834 JW |
2049 | case 'z': |
2050 | if (my_getSmallExpression (imm_expr, imm_reloc, s, p) | |
2051 | || imm_expr->X_op != O_constant | |
2052 | || imm_expr->X_add_number != 0) | |
2053 | break; | |
2054 | s = expr_end; | |
2055 | imm_expr->X_op = O_absent; | |
2056 | continue; | |
2057 | ||
e23eba97 NC |
2058 | default: |
2059 | as_fatal (_("internal error: bad argument type %c"), *args); | |
2060 | } | |
2061 | break; | |
2062 | } | |
2063 | s = argsStart; | |
2064 | error = _("illegal operands"); | |
2065 | } | |
2066 | ||
2067 | out: | |
2068 | /* Restore the character we might have clobbered above. */ | |
2069 | if (save_c) | |
2070 | *(argsStart - 1) = save_c; | |
2071 | ||
2072 | return error; | |
2073 | } | |
2074 | ||
2075 | void | |
2076 | md_assemble (char *str) | |
2077 | { | |
2078 | struct riscv_cl_insn insn; | |
2079 | expressionS imm_expr; | |
2080 | bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; | |
2081 | ||
0e35537d | 2082 | const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash); |
e23eba97 NC |
2083 | |
2084 | if (error) | |
2085 | { | |
2086 | as_bad ("%s `%s'", error, str); | |
2087 | return; | |
2088 | } | |
2089 | ||
2090 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2091 | macro (&insn, &imm_expr, &imm_reloc); | |
2092 | else | |
2093 | append_insn (&insn, &imm_expr, imm_reloc); | |
2094 | } | |
2095 | ||
2096 | const char * | |
2097 | md_atof (int type, char *litP, int *sizeP) | |
2098 | { | |
2099 | return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN); | |
2100 | } | |
2101 | ||
2102 | void | |
2103 | md_number_to_chars (char *buf, valueT val, int n) | |
2104 | { | |
2105 | number_to_chars_littleendian (buf, val, n); | |
2106 | } | |
2107 | ||
2108 | const char *md_shortopts = "O::g::G:"; | |
2109 | ||
2110 | enum options | |
2111 | { | |
2922d21d | 2112 | OPTION_MARCH = OPTION_MD_BASE, |
e23eba97 NC |
2113 | OPTION_PIC, |
2114 | OPTION_NO_PIC, | |
2922d21d | 2115 | OPTION_MABI, |
71060565 JW |
2116 | OPTION_RELAX, |
2117 | OPTION_NO_RELAX, | |
e23eba97 NC |
2118 | OPTION_END_OF_ENUM |
2119 | }; | |
2120 | ||
2121 | struct option md_longopts[] = | |
2122 | { | |
e23eba97 NC |
2123 | {"march", required_argument, NULL, OPTION_MARCH}, |
2124 | {"fPIC", no_argument, NULL, OPTION_PIC}, | |
2125 | {"fpic", no_argument, NULL, OPTION_PIC}, | |
2126 | {"fno-pic", no_argument, NULL, OPTION_NO_PIC}, | |
2922d21d | 2127 | {"mabi", required_argument, NULL, OPTION_MABI}, |
71060565 JW |
2128 | {"mrelax", no_argument, NULL, OPTION_RELAX}, |
2129 | {"mno-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
e23eba97 NC |
2130 | |
2131 | {NULL, no_argument, NULL, 0} | |
2132 | }; | |
2133 | size_t md_longopts_size = sizeof (md_longopts); | |
2134 | ||
2922d21d AW |
2135 | enum float_abi { |
2136 | FLOAT_ABI_DEFAULT = -1, | |
2137 | FLOAT_ABI_SOFT, | |
2138 | FLOAT_ABI_SINGLE, | |
2139 | FLOAT_ABI_DOUBLE, | |
2140 | FLOAT_ABI_QUAD | |
e23eba97 | 2141 | }; |
2922d21d AW |
2142 | static enum float_abi float_abi = FLOAT_ABI_DEFAULT; |
2143 | ||
2144 | static void | |
7f999549 | 2145 | riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve) |
2922d21d AW |
2146 | { |
2147 | abi_xlen = new_xlen; | |
2148 | float_abi = new_float_abi; | |
7f999549 | 2149 | rve_abi = rve; |
2922d21d | 2150 | } |
e23eba97 NC |
2151 | |
2152 | int | |
2153 | md_parse_option (int c, const char *arg) | |
2154 | { | |
2155 | switch (c) | |
2156 | { | |
e23eba97 NC |
2157 | case OPTION_MARCH: |
2158 | riscv_set_arch (arg); | |
2159 | break; | |
2160 | ||
2161 | case OPTION_NO_PIC: | |
2162 | riscv_opts.pic = FALSE; | |
2163 | break; | |
2164 | ||
2165 | case OPTION_PIC: | |
2166 | riscv_opts.pic = TRUE; | |
2167 | break; | |
2168 | ||
2922d21d AW |
2169 | case OPTION_MABI: |
2170 | if (strcmp (arg, "ilp32") == 0) | |
7f999549 JW |
2171 | riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE); |
2172 | else if (strcmp (arg, "ilp32e") == 0) | |
2173 | riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE); | |
2922d21d | 2174 | else if (strcmp (arg, "ilp32f") == 0) |
7f999549 | 2175 | riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE); |
2922d21d | 2176 | else if (strcmp (arg, "ilp32d") == 0) |
7f999549 | 2177 | riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE); |
2922d21d | 2178 | else if (strcmp (arg, "ilp32q") == 0) |
7f999549 | 2179 | riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE); |
2922d21d | 2180 | else if (strcmp (arg, "lp64") == 0) |
7f999549 | 2181 | riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE); |
2922d21d | 2182 | else if (strcmp (arg, "lp64f") == 0) |
7f999549 | 2183 | riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE); |
2922d21d | 2184 | else if (strcmp (arg, "lp64d") == 0) |
7f999549 | 2185 | riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE); |
2922d21d | 2186 | else if (strcmp (arg, "lp64q") == 0) |
7f999549 | 2187 | riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE); |
2922d21d AW |
2188 | else |
2189 | return 0; | |
2190 | break; | |
2191 | ||
71060565 JW |
2192 | case OPTION_RELAX: |
2193 | riscv_opts.relax = TRUE; | |
2194 | break; | |
2195 | ||
2196 | case OPTION_NO_RELAX: | |
2197 | riscv_opts.relax = FALSE; | |
2198 | break; | |
2199 | ||
e23eba97 NC |
2200 | default: |
2201 | return 0; | |
2202 | } | |
2203 | ||
2204 | return 1; | |
2205 | } | |
2206 | ||
2207 | void | |
2208 | riscv_after_parse_args (void) | |
2209 | { | |
e23eba97 NC |
2210 | if (xlen == 0) |
2211 | { | |
2212 | if (strcmp (default_arch, "riscv32") == 0) | |
2213 | xlen = 32; | |
2214 | else if (strcmp (default_arch, "riscv64") == 0) | |
2215 | xlen = 64; | |
2216 | else | |
2217 | as_bad ("unknown default architecture `%s'", default_arch); | |
2218 | } | |
2922d21d | 2219 | |
1080bf78 | 2220 | if (riscv_subsets.head == NULL) |
2922d21d AW |
2221 | riscv_set_arch (xlen == 64 ? "rv64g" : "rv32g"); |
2222 | ||
2223 | /* Add the RVC extension, regardless of -march, to support .option rvc. */ | |
fecb9c46 | 2224 | riscv_set_rvc (FALSE); |
1080bf78 | 2225 | if (riscv_subset_supports ("c")) |
2922d21d | 2226 | riscv_set_rvc (TRUE); |
2922d21d | 2227 | |
7f999549 JW |
2228 | /* Enable RVE if specified by the -march option. */ |
2229 | riscv_set_rve (FALSE); | |
1080bf78 | 2230 | if (riscv_subset_supports ("e")) |
7f999549 JW |
2231 | riscv_set_rve (TRUE); |
2232 | ||
2922d21d AW |
2233 | /* Infer ABI from ISA if not specified on command line. */ |
2234 | if (abi_xlen == 0) | |
2235 | abi_xlen = xlen; | |
2236 | else if (abi_xlen > xlen) | |
2237 | as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen); | |
2238 | else if (abi_xlen < xlen) | |
2239 | as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); | |
2240 | ||
2241 | if (float_abi == FLOAT_ABI_DEFAULT) | |
2242 | { | |
1080bf78 | 2243 | riscv_subset_t *subset; |
2922d21d AW |
2244 | |
2245 | /* Assume soft-float unless D extension is present. */ | |
2246 | float_abi = FLOAT_ABI_SOFT; | |
2247 | ||
1080bf78 | 2248 | for (subset = riscv_subsets.head; subset != NULL; subset = subset->next) |
cc917fd9 KC |
2249 | { |
2250 | if (strcasecmp (subset->name, "D") == 0) | |
2251 | float_abi = FLOAT_ABI_DOUBLE; | |
2252 | if (strcasecmp (subset->name, "Q") == 0) | |
2253 | float_abi = FLOAT_ABI_QUAD; | |
2254 | } | |
2922d21d AW |
2255 | } |
2256 | ||
7f999549 JW |
2257 | if (rve_abi) |
2258 | elf_flags |= EF_RISCV_RVE; | |
2259 | ||
2922d21d AW |
2260 | /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */ |
2261 | elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1)); | |
e23eba97 NC |
2262 | } |
2263 | ||
2264 | long | |
2265 | md_pcrel_from (fixS *fixP) | |
2266 | { | |
2267 | return fixP->fx_where + fixP->fx_frag->fr_address; | |
2268 | } | |
2269 | ||
2270 | /* Apply a fixup to the object file. */ | |
2271 | ||
2272 | void | |
2273 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) | |
2274 | { | |
45f76423 | 2275 | unsigned int subtype; |
e23eba97 | 2276 | bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
45f76423 | 2277 | bfd_boolean relaxable = FALSE; |
c1b465c9 | 2278 | offsetT loc; |
a6cbf936 | 2279 | segT sub_segment; |
e23eba97 NC |
2280 | |
2281 | /* Remember value for tc_gen_reloc. */ | |
2282 | fixP->fx_addnumber = *valP; | |
2283 | ||
2284 | switch (fixP->fx_r_type) | |
2285 | { | |
e23eba97 NC |
2286 | case BFD_RELOC_RISCV_HI20: |
2287 | case BFD_RELOC_RISCV_LO12_I: | |
2288 | case BFD_RELOC_RISCV_LO12_S: | |
45f76423 AW |
2289 | bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP) |
2290 | | bfd_getl32 (buf), buf); | |
a5ec5e3f AW |
2291 | if (fixP->fx_addsy == NULL) |
2292 | fixP->fx_done = TRUE; | |
45f76423 AW |
2293 | relaxable = TRUE; |
2294 | break; | |
2295 | ||
2296 | case BFD_RELOC_RISCV_GOT_HI20: | |
e23eba97 NC |
2297 | case BFD_RELOC_RISCV_ADD8: |
2298 | case BFD_RELOC_RISCV_ADD16: | |
2299 | case BFD_RELOC_RISCV_ADD32: | |
2300 | case BFD_RELOC_RISCV_ADD64: | |
45f76423 | 2301 | case BFD_RELOC_RISCV_SUB6: |
e23eba97 NC |
2302 | case BFD_RELOC_RISCV_SUB8: |
2303 | case BFD_RELOC_RISCV_SUB16: | |
2304 | case BFD_RELOC_RISCV_SUB32: | |
2305 | case BFD_RELOC_RISCV_SUB64: | |
45f76423 AW |
2306 | case BFD_RELOC_RISCV_RELAX: |
2307 | break; | |
2308 | ||
2309 | case BFD_RELOC_RISCV_TPREL_HI20: | |
2310 | case BFD_RELOC_RISCV_TPREL_LO12_I: | |
2311 | case BFD_RELOC_RISCV_TPREL_LO12_S: | |
2312 | case BFD_RELOC_RISCV_TPREL_ADD: | |
2313 | relaxable = TRUE; | |
2314 | /* Fall through. */ | |
2315 | ||
2316 | case BFD_RELOC_RISCV_TLS_GOT_HI20: | |
2317 | case BFD_RELOC_RISCV_TLS_GD_HI20: | |
2318 | case BFD_RELOC_RISCV_TLS_DTPREL32: | |
2319 | case BFD_RELOC_RISCV_TLS_DTPREL64: | |
e294484e AW |
2320 | if (fixP->fx_addsy != NULL) |
2321 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
2322 | else | |
2323 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2324 | _("TLS relocation against a constant")); | |
e23eba97 NC |
2325 | break; |
2326 | ||
e23eba97 | 2327 | case BFD_RELOC_32: |
a6cbf936 KLC |
2328 | /* Use pc-relative relocation for FDE initial location. |
2329 | The symbol address in .eh_frame may be adjusted in | |
2330 | _bfd_elf_discard_section_eh_frame, and the content of | |
2331 | .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame. | |
2332 | Therefore, we cannot insert a relocation whose addend symbol is | |
2333 | in .eh_frame. Othrewise, the value may be adjusted twice.*/ | |
2334 | if (fixP->fx_addsy && fixP->fx_subsy | |
2335 | && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy)) | |
2336 | && strcmp (sub_segment->name, ".eh_frame") == 0 | |
2337 | && S_GET_VALUE (fixP->fx_subsy) | |
2338 | == fixP->fx_frag->fr_address + fixP->fx_where) | |
2339 | { | |
2340 | fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL; | |
2341 | fixP->fx_subsy = NULL; | |
2342 | break; | |
2343 | } | |
2344 | /* Fall through. */ | |
2345 | case BFD_RELOC_64: | |
e23eba97 NC |
2346 | case BFD_RELOC_16: |
2347 | case BFD_RELOC_8: | |
45f76423 | 2348 | case BFD_RELOC_RISCV_CFA: |
e23eba97 NC |
2349 | if (fixP->fx_addsy && fixP->fx_subsy) |
2350 | { | |
2351 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
2352 | fixP->fx_next->fx_addsy = fixP->fx_subsy; | |
2353 | fixP->fx_next->fx_subsy = NULL; | |
2354 | fixP->fx_next->fx_offset = 0; | |
2355 | fixP->fx_subsy = NULL; | |
2356 | ||
2357 | switch (fixP->fx_r_type) | |
2358 | { | |
2359 | case BFD_RELOC_64: | |
2360 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD64; | |
2361 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64; | |
2362 | break; | |
2363 | ||
2364 | case BFD_RELOC_32: | |
2365 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD32; | |
2366 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
2367 | break; | |
2368 | ||
2369 | case BFD_RELOC_16: | |
2370 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD16; | |
2371 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
2372 | break; | |
2373 | ||
2374 | case BFD_RELOC_8: | |
2375 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD8; | |
2376 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
073808ed | 2377 | break; |
e23eba97 | 2378 | |
45f76423 AW |
2379 | case BFD_RELOC_RISCV_CFA: |
2380 | /* Load the byte to get the subtype. */ | |
c1b465c9 KLC |
2381 | subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]); |
2382 | loc = fixP->fx_frag->fr_fix - (subtype & 7); | |
45f76423 AW |
2383 | switch (subtype) |
2384 | { | |
2385 | case DW_CFA_advance_loc1: | |
c1b465c9 KLC |
2386 | fixP->fx_where = loc + 1; |
2387 | fixP->fx_next->fx_where = loc + 1; | |
45f76423 AW |
2388 | fixP->fx_r_type = BFD_RELOC_RISCV_SET8; |
2389 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
2390 | break; | |
2391 | ||
2392 | case DW_CFA_advance_loc2: | |
2393 | fixP->fx_size = 2; | |
45f76423 | 2394 | fixP->fx_next->fx_size = 2; |
c1b465c9 KLC |
2395 | fixP->fx_where = loc + 1; |
2396 | fixP->fx_next->fx_where = loc + 1; | |
45f76423 AW |
2397 | fixP->fx_r_type = BFD_RELOC_RISCV_SET16; |
2398 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
2399 | break; | |
2400 | ||
2401 | case DW_CFA_advance_loc4: | |
2402 | fixP->fx_size = 4; | |
45f76423 | 2403 | fixP->fx_next->fx_size = 4; |
c1b465c9 KLC |
2404 | fixP->fx_where = loc; |
2405 | fixP->fx_next->fx_where = loc; | |
45f76423 AW |
2406 | fixP->fx_r_type = BFD_RELOC_RISCV_SET32; |
2407 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
2408 | break; | |
2409 | ||
2410 | default: | |
2411 | if (subtype < 0x80 && (subtype & 0x40)) | |
2412 | { | |
2413 | /* DW_CFA_advance_loc */ | |
2aece2ba KLC |
2414 | fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode; |
2415 | fixP->fx_next->fx_frag = fixP->fx_frag; | |
45f76423 AW |
2416 | fixP->fx_r_type = BFD_RELOC_RISCV_SET6; |
2417 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6; | |
2418 | } | |
2419 | else | |
2420 | as_fatal (_("internal error: bad CFA value #%d"), subtype); | |
2421 | break; | |
2422 | } | |
2423 | break; | |
2424 | ||
e23eba97 NC |
2425 | default: |
2426 | /* This case is unreachable. */ | |
2427 | abort (); | |
2428 | } | |
2429 | } | |
2430 | /* Fall through. */ | |
2431 | ||
2432 | case BFD_RELOC_RVA: | |
2433 | /* If we are deleting this reloc entry, we must fill in the | |
2434 | value now. This can happen if we have a .word which is not | |
2435 | resolved when it appears but is later defined. */ | |
2436 | if (fixP->fx_addsy == NULL) | |
2437 | { | |
2438 | gas_assert (fixP->fx_size <= sizeof (valueT)); | |
2439 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); | |
2440 | fixP->fx_done = 1; | |
2441 | } | |
2442 | break; | |
2443 | ||
2444 | case BFD_RELOC_RISCV_JMP: | |
2445 | if (fixP->fx_addsy) | |
2446 | { | |
2447 | /* Fill in a tentative value to improve objdump readability. */ | |
2448 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2449 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2450 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf); | |
2451 | } | |
2452 | break; | |
2453 | ||
2454 | case BFD_RELOC_12_PCREL: | |
2455 | if (fixP->fx_addsy) | |
2456 | { | |
2457 | /* Fill in a tentative value to improve objdump readability. */ | |
2458 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2459 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2460 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf); | |
2461 | } | |
2462 | break; | |
2463 | ||
2464 | case BFD_RELOC_RISCV_RVC_BRANCH: | |
2465 | if (fixP->fx_addsy) | |
2466 | { | |
2467 | /* Fill in a tentative value to improve objdump readability. */ | |
2468 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2469 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2470 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf); | |
2471 | } | |
2472 | break; | |
2473 | ||
2474 | case BFD_RELOC_RISCV_RVC_JUMP: | |
2475 | if (fixP->fx_addsy) | |
2476 | { | |
2477 | /* Fill in a tentative value to improve objdump readability. */ | |
2478 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
2479 | bfd_vma delta = target - md_pcrel_from (fixP); | |
2480 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf); | |
2481 | } | |
2482 | break; | |
2483 | ||
e23eba97 NC |
2484 | case BFD_RELOC_RISCV_CALL: |
2485 | case BFD_RELOC_RISCV_CALL_PLT: | |
45f76423 AW |
2486 | relaxable = TRUE; |
2487 | break; | |
2488 | ||
9d06997a | 2489 | case BFD_RELOC_RISCV_PCREL_HI20: |
45f76423 AW |
2490 | case BFD_RELOC_RISCV_PCREL_LO12_S: |
2491 | case BFD_RELOC_RISCV_PCREL_LO12_I: | |
9d06997a PD |
2492 | relaxable = riscv_opts.relax; |
2493 | break; | |
2494 | ||
e23eba97 NC |
2495 | case BFD_RELOC_RISCV_ALIGN: |
2496 | break; | |
2497 | ||
2498 | default: | |
2499 | /* We ignore generic BFD relocations we don't know about. */ | |
2500 | if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL) | |
2501 | as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type); | |
2502 | } | |
45f76423 | 2503 | |
e294484e AW |
2504 | if (fixP->fx_subsy != NULL) |
2505 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2506 | _("unsupported symbol subtraction")); | |
2507 | ||
45f76423 AW |
2508 | /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */ |
2509 | if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL) | |
2510 | { | |
2511 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
2512 | fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL; | |
2513 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX; | |
2514 | } | |
2515 | } | |
2516 | ||
2517 | /* Because the value of .cfi_remember_state may changed after relaxation, | |
2518 | we insert a fix to relocate it again in link-time. */ | |
2519 | ||
2520 | void | |
2521 | riscv_pre_output_hook (void) | |
2522 | { | |
2523 | const frchainS *frch; | |
2524 | const asection *s; | |
2525 | ||
2526 | for (s = stdoutput->sections; s; s = s->next) | |
2527 | for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next) | |
2528 | { | |
7cb7b948 | 2529 | fragS *frag; |
45f76423 AW |
2530 | |
2531 | for (frag = frch->frch_root; frag; frag = frag->fr_next) | |
2532 | { | |
2533 | if (frag->fr_type == rs_cfa) | |
2534 | { | |
45f76423 | 2535 | expressionS exp; |
8d1015a8 | 2536 | expressionS *symval; |
45f76423 | 2537 | |
8d1015a8 | 2538 | symval = symbol_get_value_expression (frag->fr_symbol); |
45f76423 | 2539 | exp.X_op = O_subtract; |
8d1015a8 | 2540 | exp.X_add_symbol = symval->X_add_symbol; |
45f76423 | 2541 | exp.X_add_number = 0; |
8d1015a8 | 2542 | exp.X_op_symbol = symval->X_op_symbol; |
45f76423 | 2543 | |
c1b465c9 | 2544 | fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0, |
45f76423 AW |
2545 | BFD_RELOC_RISCV_CFA); |
2546 | } | |
2547 | } | |
2548 | } | |
e23eba97 NC |
2549 | } |
2550 | ||
45f76423 | 2551 | |
e23eba97 NC |
2552 | /* This structure is used to hold a stack of .option values. */ |
2553 | ||
2554 | struct riscv_option_stack | |
2555 | { | |
2556 | struct riscv_option_stack *next; | |
2557 | struct riscv_set_options options; | |
2558 | }; | |
2559 | ||
2560 | static struct riscv_option_stack *riscv_opts_stack; | |
2561 | ||
2562 | /* Handle the .option pseudo-op. */ | |
2563 | ||
2564 | static void | |
2565 | s_riscv_option (int x ATTRIBUTE_UNUSED) | |
2566 | { | |
2567 | char *name = input_line_pointer, ch; | |
2568 | ||
2569 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2570 | ++input_line_pointer; | |
2571 | ch = *input_line_pointer; | |
2572 | *input_line_pointer = '\0'; | |
2573 | ||
2574 | if (strcmp (name, "rvc") == 0) | |
2575 | riscv_set_rvc (TRUE); | |
2576 | else if (strcmp (name, "norvc") == 0) | |
2577 | riscv_set_rvc (FALSE); | |
2578 | else if (strcmp (name, "pic") == 0) | |
2579 | riscv_opts.pic = TRUE; | |
2580 | else if (strcmp (name, "nopic") == 0) | |
2581 | riscv_opts.pic = FALSE; | |
45f76423 AW |
2582 | else if (strcmp (name, "relax") == 0) |
2583 | riscv_opts.relax = TRUE; | |
2584 | else if (strcmp (name, "norelax") == 0) | |
2585 | riscv_opts.relax = FALSE; | |
e23eba97 NC |
2586 | else if (strcmp (name, "push") == 0) |
2587 | { | |
2588 | struct riscv_option_stack *s; | |
2589 | ||
2590 | s = (struct riscv_option_stack *) xmalloc (sizeof *s); | |
2591 | s->next = riscv_opts_stack; | |
2592 | s->options = riscv_opts; | |
2593 | riscv_opts_stack = s; | |
2594 | } | |
2595 | else if (strcmp (name, "pop") == 0) | |
2596 | { | |
2597 | struct riscv_option_stack *s; | |
2598 | ||
2599 | s = riscv_opts_stack; | |
2600 | if (s == NULL) | |
2601 | as_bad (_(".option pop with no .option push")); | |
2602 | else | |
2603 | { | |
2604 | riscv_opts = s->options; | |
2605 | riscv_opts_stack = s->next; | |
2606 | free (s); | |
2607 | } | |
2608 | } | |
2609 | else | |
2610 | { | |
2611 | as_warn (_("Unrecognized .option directive: %s\n"), name); | |
2612 | } | |
2613 | *input_line_pointer = ch; | |
2614 | demand_empty_rest_of_line (); | |
2615 | } | |
2616 | ||
2617 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate | |
2618 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
2619 | use in DWARF debug information. */ | |
2620 | ||
2621 | static void | |
2622 | s_dtprel (int bytes) | |
2623 | { | |
2624 | expressionS ex; | |
2625 | char *p; | |
2626 | ||
2627 | expression (&ex); | |
2628 | ||
2629 | if (ex.X_op != O_symbol) | |
2630 | { | |
2631 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
2632 | ? ".dtpreldword" | |
2633 | : ".dtprelword")); | |
2634 | ignore_rest_of_line (); | |
2635 | } | |
2636 | ||
2637 | p = frag_more (bytes); | |
2638 | md_number_to_chars (p, 0, bytes); | |
2639 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
2640 | (bytes == 8 | |
2641 | ? BFD_RELOC_RISCV_TLS_DTPREL64 | |
2642 | : BFD_RELOC_RISCV_TLS_DTPREL32)); | |
2643 | ||
2644 | demand_empty_rest_of_line (); | |
2645 | } | |
2646 | ||
2647 | /* Handle the .bss pseudo-op. */ | |
2648 | ||
2649 | static void | |
2650 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
2651 | { | |
2652 | subseg_set (bss_section, 0); | |
2653 | demand_empty_rest_of_line (); | |
2654 | } | |
2655 | ||
e23eba97 | 2656 | static void |
d115ab8e | 2657 | riscv_make_nops (char *buf, bfd_vma bytes) |
e23eba97 | 2658 | { |
d115ab8e | 2659 | bfd_vma i = 0; |
e23eba97 | 2660 | |
e5b737de AW |
2661 | /* RISC-V instructions cannot begin or end on odd addresses, so this case |
2662 | means we are not within a valid instruction sequence. It is thus safe | |
2663 | to use a zero byte, even though that is not a valid instruction. */ | |
2664 | if (bytes % 2 == 1) | |
2665 | buf[i++] = 0; | |
2666 | ||
2667 | /* Use at most one 2-byte NOP. */ | |
2668 | if ((bytes - i) % 4 == 2) | |
e23eba97 | 2669 | { |
e5b737de | 2670 | md_number_to_chars (buf + i, RVC_NOP, 2); |
d115ab8e | 2671 | i += 2; |
e23eba97 NC |
2672 | } |
2673 | ||
e5b737de | 2674 | /* Fill the remainder with 4-byte NOPs. */ |
d115ab8e AW |
2675 | for ( ; i < bytes; i += 4) |
2676 | md_number_to_chars (buf + i, RISCV_NOP, 4); | |
2677 | } | |
e23eba97 | 2678 | |
d115ab8e AW |
2679 | /* Called from md_do_align. Used to create an alignment frag in a |
2680 | code section by emitting a worst-case NOP sequence that the linker | |
2681 | will later relax to the correct number of NOPs. We can't compute | |
2682 | the correct alignment now because of other linker relaxations. */ | |
2683 | ||
2684 | bfd_boolean | |
2685 | riscv_frag_align_code (int n) | |
2686 | { | |
e5b737de | 2687 | bfd_vma bytes = (bfd_vma) 1 << n; |
36877bfb JW |
2688 | bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4; |
2689 | bfd_vma worst_case_bytes = bytes - insn_alignment; | |
2690 | char *nops; | |
ed0816bd | 2691 | expressionS ex; |
d115ab8e | 2692 | |
36877bfb JW |
2693 | /* If we are moving to a smaller alignment than the instruction size, then no |
2694 | alignment is required. */ | |
2695 | if (bytes <= insn_alignment) | |
2696 | return TRUE; | |
2697 | ||
d115ab8e AW |
2698 | /* When not relaxing, riscv_handle_align handles code alignment. */ |
2699 | if (!riscv_opts.relax) | |
2700 | return FALSE; | |
e23eba97 | 2701 | |
e80ae190 JW |
2702 | nops = frag_more (worst_case_bytes); |
2703 | ||
ed0816bd PD |
2704 | ex.X_op = O_constant; |
2705 | ex.X_add_number = worst_case_bytes; | |
d115ab8e | 2706 | |
ed0816bd | 2707 | riscv_make_nops (nops, worst_case_bytes); |
e23eba97 | 2708 | |
ed0816bd PD |
2709 | fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, |
2710 | &ex, FALSE, BFD_RELOC_RISCV_ALIGN); | |
e23eba97 | 2711 | |
d115ab8e AW |
2712 | return TRUE; |
2713 | } | |
e23eba97 | 2714 | |
d115ab8e AW |
2715 | /* Implement HANDLE_ALIGN. */ |
2716 | ||
2717 | void | |
2718 | riscv_handle_align (fragS *fragP) | |
2719 | { | |
2720 | switch (fragP->fr_type) | |
2721 | { | |
2722 | case rs_align_code: | |
2723 | /* When relaxing, riscv_frag_align_code handles code alignment. */ | |
2724 | if (!riscv_opts.relax) | |
2725 | { | |
e80ae190 JW |
2726 | bfd_signed_vma bytes = (fragP->fr_next->fr_address |
2727 | - fragP->fr_address - fragP->fr_fix); | |
2728 | /* We have 4 byte uncompressed nops. */ | |
2729 | bfd_signed_vma size = 4; | |
2730 | bfd_signed_vma excess = bytes % size; | |
2731 | char *p = fragP->fr_literal + fragP->fr_fix; | |
2732 | ||
2733 | if (bytes <= 0) | |
d115ab8e AW |
2734 | break; |
2735 | ||
e80ae190 JW |
2736 | /* Insert zeros or compressed nops to get 4 byte alignment. */ |
2737 | if (excess) | |
2738 | { | |
2739 | riscv_make_nops (p, excess); | |
2740 | fragP->fr_fix += excess; | |
2741 | p += excess; | |
2742 | } | |
2743 | ||
2744 | /* Insert variable number of 4 byte uncompressed nops. */ | |
2745 | riscv_make_nops (p, size); | |
2746 | fragP->fr_var = size; | |
d115ab8e AW |
2747 | } |
2748 | break; | |
2749 | ||
2750 | default: | |
2751 | break; | |
2752 | } | |
e23eba97 NC |
2753 | } |
2754 | ||
2755 | int | |
2756 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) | |
2757 | { | |
2758 | return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE)); | |
2759 | } | |
2760 | ||
2761 | /* Translate internal representation of relocation info to BFD target | |
2762 | format. */ | |
2763 | ||
2764 | arelent * | |
2765 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) | |
2766 | { | |
2767 | arelent *reloc = (arelent *) xmalloc (sizeof (arelent)); | |
2768 | ||
2769 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
2770 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
2771 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
2772 | reloc->addend = fixp->fx_addnumber; | |
2773 | ||
2774 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
2775 | if (reloc->howto == NULL) | |
2776 | { | |
2777 | if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8) | |
2778 | && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL) | |
2779 | { | |
2780 | /* We don't have R_RISCV_8/16, but for this special case, | |
2781 | we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */ | |
2782 | return reloc; | |
2783 | } | |
2784 | ||
2785 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2786 | _("cannot represent %s relocation in object file"), | |
2787 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
2788 | return NULL; | |
2789 | } | |
2790 | ||
2791 | return reloc; | |
2792 | } | |
2793 | ||
2794 | int | |
2795 | riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) | |
2796 | { | |
2797 | if (RELAX_BRANCH_P (fragp->fr_subtype)) | |
2798 | { | |
2799 | offsetT old_var = fragp->fr_var; | |
2800 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
2801 | return fragp->fr_var - old_var; | |
2802 | } | |
2803 | ||
2804 | return 0; | |
2805 | } | |
2806 | ||
2807 | /* Expand far branches to multi-instruction sequences. */ | |
2808 | ||
2809 | static void | |
2810 | md_convert_frag_branch (fragS *fragp) | |
2811 | { | |
2812 | bfd_byte *buf; | |
2813 | expressionS exp; | |
2814 | fixS *fixp; | |
2815 | insn_t insn; | |
2816 | int rs1, reloc; | |
2817 | ||
2818 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; | |
2819 | ||
2820 | exp.X_op = O_symbol; | |
2821 | exp.X_add_symbol = fragp->fr_symbol; | |
2822 | exp.X_add_number = fragp->fr_offset; | |
2823 | ||
2824 | gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype)); | |
2825 | ||
2826 | if (RELAX_BRANCH_RVC (fragp->fr_subtype)) | |
2827 | { | |
2828 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
2829 | { | |
2830 | case 8: | |
2831 | case 4: | |
2832 | /* Expand the RVC branch into a RISC-V one. */ | |
2833 | insn = bfd_getl16 (buf); | |
2834 | rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S); | |
2835 | if ((insn & MASK_C_J) == MATCH_C_J) | |
2836 | insn = MATCH_JAL; | |
2837 | else if ((insn & MASK_C_JAL) == MATCH_C_JAL) | |
2838 | insn = MATCH_JAL | (X_RA << OP_SH_RD); | |
2839 | else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ) | |
2840 | insn = MATCH_BEQ | (rs1 << OP_SH_RS1); | |
2841 | else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ) | |
2842 | insn = MATCH_BNE | (rs1 << OP_SH_RS1); | |
2843 | else | |
2844 | abort (); | |
2845 | bfd_putl32 (insn, buf); | |
2846 | break; | |
2847 | ||
2848 | case 6: | |
2849 | /* Invert the branch condition. Branch over the jump. */ | |
2850 | insn = bfd_getl16 (buf); | |
2851 | insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ; | |
2852 | insn |= ENCODE_RVC_B_IMM (6); | |
2853 | bfd_putl16 (insn, buf); | |
2854 | buf += 2; | |
2855 | goto jump; | |
2856 | ||
2857 | case 2: | |
2858 | /* Just keep the RVC branch. */ | |
2859 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
2860 | ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH; | |
2861 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
2862 | 2, &exp, FALSE, reloc); | |
2863 | buf += 2; | |
2864 | goto done; | |
2865 | ||
2866 | default: | |
1d65abb5 | 2867 | abort (); |
e23eba97 NC |
2868 | } |
2869 | } | |
2870 | ||
2871 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
2872 | { | |
2873 | case 8: | |
2874 | gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); | |
2875 | ||
2876 | /* Invert the branch condition. Branch over the jump. */ | |
2877 | insn = bfd_getl32 (buf); | |
2878 | insn ^= MATCH_BEQ ^ MATCH_BNE; | |
2879 | insn |= ENCODE_SBTYPE_IMM (8); | |
2880 | md_number_to_chars ((char *) buf, insn, 4); | |
2881 | buf += 4; | |
2882 | ||
2883 | jump: | |
2884 | /* Jump to the target. */ | |
2885 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
2886 | 4, &exp, FALSE, BFD_RELOC_RISCV_JMP); | |
2887 | md_number_to_chars ((char *) buf, MATCH_JAL, 4); | |
2888 | buf += 4; | |
2889 | break; | |
2890 | ||
2891 | case 4: | |
2892 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
2893 | ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL; | |
2894 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
2895 | 4, &exp, FALSE, reloc); | |
2896 | buf += 4; | |
2897 | break; | |
2898 | ||
2899 | default: | |
2900 | abort (); | |
2901 | } | |
2902 | ||
2903 | done: | |
2904 | fixp->fx_file = fragp->fr_file; | |
2905 | fixp->fx_line = fragp->fr_line; | |
2906 | ||
2907 | gas_assert (buf == (bfd_byte *)fragp->fr_literal | |
2908 | + fragp->fr_fix + fragp->fr_var); | |
2909 | ||
2910 | fragp->fr_fix += fragp->fr_var; | |
2911 | } | |
2912 | ||
2913 | /* Relax a machine dependent frag. This returns the amount by which | |
2914 | the current size of the frag should change. */ | |
2915 | ||
2916 | void | |
2917 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, | |
2918 | fragS *fragp) | |
2919 | { | |
2920 | gas_assert (RELAX_BRANCH_P (fragp->fr_subtype)); | |
2921 | md_convert_frag_branch (fragp); | |
2922 | } | |
2923 | ||
2924 | void | |
2925 | md_show_usage (FILE *stream) | |
2926 | { | |
2927 | fprintf (stream, _("\ | |
2928 | RISC-V options:\n\ | |
e23eba97 NC |
2929 | -fpic generate position-independent code\n\ |
2930 | -fno-pic don't generate position-independent code (default)\n\ | |
19683c04 PD |
2931 | -march=ISA set the RISC-V architecture\n\ |
2932 | -mabi=ABI set the RISC-V ABI\n\ | |
71060565 JW |
2933 | -mrelax enable relax (default)\n\ |
2934 | -mno-relax disable relax\n\ | |
e23eba97 NC |
2935 | ")); |
2936 | } | |
2937 | ||
2938 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
2939 | void | |
2940 | riscv_cfi_frame_initial_instructions (void) | |
2941 | { | |
2942 | cfi_add_CFA_def_cfa_register (X_SP); | |
2943 | } | |
2944 | ||
2945 | int | |
2946 | tc_riscv_regname_to_dw2regnum (char *regname) | |
2947 | { | |
2948 | int reg; | |
2949 | ||
2950 | if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0) | |
2951 | return reg; | |
2952 | ||
2953 | if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0) | |
2954 | return reg + 32; | |
2955 | ||
2956 | as_bad (_("unknown register `%s'"), regname); | |
2957 | return -1; | |
2958 | } | |
2959 | ||
2960 | void | |
2961 | riscv_elf_final_processing (void) | |
2962 | { | |
e23eba97 | 2963 | elf_elfheader (stdoutput)->e_flags |= elf_flags; |
e23eba97 NC |
2964 | } |
2965 | ||
2966 | /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions, | |
2967 | since these directives break relaxation when used with symbol deltas. */ | |
2968 | ||
2969 | static void | |
2970 | s_riscv_leb128 (int sign) | |
2971 | { | |
2972 | expressionS exp; | |
2973 | char *save_in = input_line_pointer; | |
2974 | ||
2975 | expression (&exp); | |
2976 | if (exp.X_op != O_constant) | |
2977 | as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u'); | |
2978 | demand_empty_rest_of_line (); | |
2979 | ||
2980 | input_line_pointer = save_in; | |
2981 | return s_leb128 (sign); | |
2982 | } | |
2983 | ||
0e35537d JW |
2984 | /* Parse the .insn directive. */ |
2985 | ||
2986 | static void | |
2987 | s_riscv_insn (int x ATTRIBUTE_UNUSED) | |
2988 | { | |
2989 | char *str = input_line_pointer; | |
2990 | struct riscv_cl_insn insn; | |
2991 | expressionS imm_expr; | |
2992 | bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; | |
2993 | char save_c; | |
2994 | ||
2995 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2996 | ++input_line_pointer; | |
2997 | ||
2998 | save_c = *input_line_pointer; | |
2999 | *input_line_pointer = '\0'; | |
3000 | ||
3001 | const char *error = riscv_ip (str, &insn, &imm_expr, | |
3002 | &imm_reloc, insn_type_hash); | |
3003 | ||
3004 | if (error) | |
3005 | { | |
3006 | as_bad ("%s `%s'", error, str); | |
3007 | } | |
3008 | else | |
3009 | { | |
3010 | gas_assert (insn.insn_mo->pinfo != INSN_MACRO); | |
3011 | append_insn (&insn, &imm_expr, imm_reloc); | |
3012 | } | |
3013 | ||
3014 | *input_line_pointer = save_c; | |
3015 | demand_empty_rest_of_line (); | |
3016 | } | |
3017 | ||
e23eba97 NC |
3018 | /* Pseudo-op table. */ |
3019 | ||
3020 | static const pseudo_typeS riscv_pseudo_table[] = | |
3021 | { | |
3022 | /* RISC-V-specific pseudo-ops. */ | |
3023 | {"option", s_riscv_option, 0}, | |
3024 | {"half", cons, 2}, | |
3025 | {"word", cons, 4}, | |
3026 | {"dword", cons, 8}, | |
3027 | {"dtprelword", s_dtprel, 4}, | |
3028 | {"dtpreldword", s_dtprel, 8}, | |
3029 | {"bss", s_bss, 0}, | |
e23eba97 NC |
3030 | {"uleb128", s_riscv_leb128, 0}, |
3031 | {"sleb128", s_riscv_leb128, 1}, | |
0e35537d | 3032 | {"insn", s_riscv_insn, 0}, |
e23eba97 NC |
3033 | |
3034 | { NULL, NULL, 0 }, | |
3035 | }; | |
3036 | ||
3037 | void | |
3038 | riscv_pop_insert (void) | |
3039 | { | |
3040 | extern void pop_insert (const pseudo_typeS *); | |
3041 | ||
3042 | pop_insert (riscv_pseudo_table); | |
3043 | } |