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RISC-V: Dump CSR according to the elf privileged spec attributes.
[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
CommitLineData
e23eba97 1/* tc-riscv.c -- RISC-V assembler
b3adc24a 2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
1080bf78 32#include "bfd/elfxx-riscv.h"
e23eba97
NC		 33#include "elf/riscv.h"
34#include "opcode/riscv.h"
35
36#include <stdint.h>
37
38/* Information about an instruction, including its format, operands
39 and fixups. */
40struct riscv_cl_insn
41{
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode *insn_mo;
44
45 /* The encoded instruction bits. */
46 insn_t insn_opcode;
47
48 /* The frag that contains the instruction. */
49 struct frag *frag;
50
51 /* The offset into FRAG of the first instruction byte. */
52 long where;
53
54 /* The relocs associated with the instruction, if any. */
55 fixS *fixp;
56};
57
58#ifndef DEFAULT_ARCH
59#define DEFAULT_ARCH "riscv64"
60#endif
61
2dc8dd17
JW		 62#ifndef DEFAULT_RISCV_ATTR
63#define DEFAULT_RISCV_ATTR 0
64#endif
65
8f595e9b
NC		 66/* Let riscv_after_parse_args set the default value according to xlen. */
67
68#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
70#endif
71
72/* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
77
78#ifndef DEFAULT_RISCV_ISA_SPEC
79#define DEFAULT_RISCV_ISA_SPEC "2.2"
80#endif
81
82#ifndef DEFAULT_RISCV_PRIV_SPEC
83#define DEFAULT_RISCV_PRIV_SPEC "1.11"
84#endif
85
e23eba97 86static const char default_arch[] = DEFAULT_ARCH;
8f595e9b
NC		 87static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
88static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
89static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
e23eba97 90
2922d21d
AW		 91static unsigned xlen = 0; /* width of an x-register */
92static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
7f999549 93static bfd_boolean rve_abi = FALSE;
6e1605e4
NC		 94enum float_abi {
95 FLOAT_ABI_DEFAULT = -1,
96 FLOAT_ABI_SOFT,
97 FLOAT_ABI_SINGLE,
98 FLOAT_ABI_DOUBLE,
99 FLOAT_ABI_QUAD
100};
101static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
e23eba97 102
2922d21d 103#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
e23eba97
NC		 104#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
105
106static unsigned elf_flags = 0;
107
8f595e9b
NC		 108/* Set the default_isa_spec. Return 0 if the input spec string isn't
109 supported. Otherwise, return 1. */
110
111static int
112riscv_set_default_isa_spec (const char *s)
113{
114 enum riscv_isa_spec_class class;
115 if (!riscv_get_isa_spec_class (s, &class))
116 {
117 as_bad ("Unknown default ISA spec `%s' set by "
118 "-misa-spec or --with-isa-spec", s);
119 return 0;
120 }
121 else
122 default_isa_spec = class;
123 return 1;
124}
125
126/* Set the default_priv_spec, assembler will find the suitable CSR address
127 according to default_priv_spec. We will try to check priv attributes if
128 the input string is NULL. Return 0 if the input priv spec string isn't
129 supported. Otherwise, return 1. */
130
131static int
132riscv_set_default_priv_spec (const char *s)
133{
134 enum riscv_priv_spec_class class;
135 unsigned major, minor, revision;
136 obj_attribute *attr;
8f595e9b
NC		 137
138 /* Find the corresponding priv spec class. */
139 if (riscv_get_priv_spec_class (s, &class))
140 {
141 default_priv_spec = class;
142 return 1;
143 }
144
145 if (s != NULL)
146 {
147 as_bad (_("Unknown default privilege spec `%s' set by "
148 "-mpriv-spec or --with-priv-spec"), s);
149 return 0;
150 }
151
152 /* Try to set the default_priv_spec according to the priv attributes. */
153 attr = elf_known_obj_attributes_proc (stdoutput);
154 major = (unsigned) attr[Tag_RISCV_priv_spec].i;
155 minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
156 revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
157
39ff0b81
NC		 158 if (riscv_get_priv_spec_class_from_numbers (major,
159 minor,
160 revision,
161 &class))
8f595e9b 162 {
39ff0b81
NC		 163 /* The priv attributes setting 0.0.0 is meaningless. We should have set
164 the default_priv_spec by md_parse_option and riscv_after_parse_args,
165 so just skip the following setting. */
166 if (class == PRIV_SPEC_CLASS_NONE)
167 return 1;
8f595e9b 168
8f595e9b 169 default_priv_spec = class;
8f595e9b
NC		 170 return 1;
171 }
172
173 /* Still can not find the priv spec class. */
ddc73fa9 174 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
8f595e9b 175 "privilege attributes"), major, minor, revision);
8f595e9b
NC		 176 return 0;
177}
178
e23eba97
NC		 179/* This is the set of options which the .option pseudo-op may modify. */
180
181struct riscv_set_options
182{
183 int pic; /* Generate position-independent code. */
184 int rvc; /* Generate RVC code. */
7f999549 185 int rve; /* Generate RVE code. */
45f76423 186 int relax; /* Emit relocs the linker is allowed to relax. */
2dc8dd17 187 int arch_attr; /* Emit arch attribute. */
2ca89224 188 int csr_check; /* Enable the CSR checking. */
e23eba97
NC		 189};
190
191static struct riscv_set_options riscv_opts =
192{
193 0, /* pic */
194 0, /* rvc */
7f999549 195 0, /* rve */
45f76423 196 1, /* relax */
2dc8dd17 197 DEFAULT_RISCV_ATTR, /* arch_attr */
2ca89224 198 0. /* csr_check */
e23eba97
NC		 199};
200
201static void
202riscv_set_rvc (bfd_boolean rvc_value)
203{
204 if (rvc_value)
205 elf_flags |= EF_RISCV_RVC;
206
207 riscv_opts.rvc = rvc_value;
208}
209
7f999549
JW		 210static void
211riscv_set_rve (bfd_boolean rve_value)
212{
213 riscv_opts.rve = rve_value;
214}
215
1080bf78 216static riscv_subset_list_t riscv_subsets;
e23eba97
NC		 217
218static bfd_boolean
1080bf78 219riscv_subset_supports (const char *feature)
e23eba97 220{
dfe92496
NC		 221 struct riscv_subset_t *subset;
222
1080bf78
JW		 223 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
224 return TRUE;
e23eba97 225
dfe92496 226 return riscv_lookup_subset (&riscv_subsets, feature, &subset);
e23eba97
NC		 227}
228
43135d3b 229static bfd_boolean
7e9ad3a3 230riscv_multi_subset_supports (enum riscv_insn_class insn_class)
43135d3b 231{
7e9ad3a3
JW		 232 switch (insn_class)
233 {
234 case INSN_CLASS_I: return riscv_subset_supports ("i");
235 case INSN_CLASS_C: return riscv_subset_supports ("c");
236 case INSN_CLASS_A: return riscv_subset_supports ("a");
237 case INSN_CLASS_M: return riscv_subset_supports ("m");
238 case INSN_CLASS_F: return riscv_subset_supports ("f");
239 case INSN_CLASS_D: return riscv_subset_supports ("d");
729a5353 240 case INSN_CLASS_Q: return riscv_subset_supports ("q");
7e9ad3a3
JW		 241
242 case INSN_CLASS_F_AND_C:
729a5353
NC		 243 return (riscv_subset_supports ("f")
244 && riscv_subset_supports ("c"));
245 case INSN_CLASS_D_AND_C:
246 return (riscv_subset_supports ("d")
247 && riscv_subset_supports ("c"));
43135d3b 248
729a5353
NC		 249 case INSN_CLASS_ZICSR:
250 return riscv_subset_supports ("zicsr");
251 case INSN_CLASS_ZIFENCEI:
252 return riscv_subset_supports ("zifencei");
43135d3b 253
7e9ad3a3
JW		 254 default:
255 as_fatal ("Unreachable");
256 return FALSE;
257 }
43135d3b
JW		 258}
259
8f595e9b 260/* Handle of the extension with version hash table. */
629310ab 261static htab_t ext_version_hash = NULL;
8f595e9b 262
629310ab 263static htab_t
8f595e9b
NC		 264init_ext_version_hash (const struct riscv_ext_version *table)
265{
266 int i = 0;
629310ab 267 htab_t hash = str_htab_create ();
8f595e9b
NC		 268
269 while (table[i].name)
270 {
271 const char *name = table[i].name;
fe0e921f
AM		 272 if (str_hash_insert (hash, name, &table[i], 0) != NULL)
273 as_fatal (_("duplicate %s"), name);
8f595e9b
NC		 274
275 i++;
276 while (table[i].name
277 && strcmp (table[i].name, name) == 0)
278 i++;
279 }
280
281 return hash;
282}
283
284static void
285riscv_get_default_ext_version (const char *name,
7ef19aa6
NC		 286 int *major_version,
287 int *minor_version)
8f595e9b
NC		 288{
289 struct riscv_ext_version *ext;
290
8f595e9b
NC		 291 if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
292 return;
293
629310ab 294 ext = (struct riscv_ext_version *) str_hash_find (ext_version_hash, name);
8f595e9b 295 while (ext
7ef19aa6
NC		 296 && ext->name
297 && strcmp (ext->name, name) == 0)
8f595e9b
NC		 298 {
299 if (ext->isa_spec_class == default_isa_spec)
7ef19aa6
NC		 300 {
301 *major_version = ext->major_version;
302 *minor_version = ext->minor_version;
303 return;
304 }
8f595e9b
NC		 305 ext++;
306 }
307}
308
2922d21d 309/* Set which ISA and extensions are available. */
e23eba97 310
e23eba97 311static void
2922d21d 312riscv_set_arch (const char *s)
e23eba97 313{
1080bf78
JW		 314 riscv_parse_subset_t rps;
315 rps.subset_list = &riscv_subsets;
7ef19aa6 316 rps.error_handler = as_bad;
1080bf78 317 rps.xlen = &xlen;
8f595e9b
NC		 318 rps.get_default_version = riscv_get_default_ext_version;
319
320 if (s == NULL)
321 return;
7f999549 322
1080bf78
JW		 323 riscv_release_subset_list (&riscv_subsets);
324 riscv_parse_subset (&rps, s);
e23eba97
NC		 325}
326
6e1605e4
NC		 327/* Indicate -mabi= option is explictly set. */
328static bfd_boolean explicit_mabi = FALSE;
329
330static void
331riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
332{
333 abi_xlen = new_xlen;
334 float_abi = new_float_abi;
335 rve_abi = rve;
336}
337
338/* If the -mabi option isn't set, then we set the abi according to the arch
339 string. Otherwise, check if there are conflicts between architecture
340 and abi setting. */
341
342static void
343riscv_set_abi_by_arch (void)
344{
345 if (!explicit_mabi)
346 {
347 if (riscv_subset_supports ("q"))
348 riscv_set_abi (xlen, FLOAT_ABI_QUAD, FALSE);
349 else if (riscv_subset_supports ("d"))
350 riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, FALSE);
351 else
352 riscv_set_abi (xlen, FLOAT_ABI_SOFT, FALSE);
353 }
354 else
355 {
356 gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT);
357 if (abi_xlen > xlen)
358 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
359 else if (abi_xlen < xlen)
360 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
361 }
362
363 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
364 elf_flags &= ~EF_RISCV_FLOAT_ABI;
365 elf_flags |= float_abi << 1;
366
367 if (rve_abi)
368 elf_flags |= EF_RISCV_RVE;
369}
370
e23eba97 371/* Handle of the OPCODE hash table. */
629310ab 372static htab_t op_hash = NULL;
e23eba97 373
0e35537d 374/* Handle of the type of .insn hash table. */
629310ab 375static htab_t insn_type_hash = NULL;
0e35537d 376
e23eba97
NC		 377/* This array holds the chars that always start a comment. If the
378 pre-processor is disabled, these aren't very useful */
379const char comment_chars[] = "#";
380
381/* This array holds the chars that only start a comment at the beginning of
382 a line. If the line seems to have the form '# 123 filename'
383 .line and .file directives will appear in the pre-processed output */
384/* Note that input_file.c hand checks for '#' at the beginning of the
385 first line of the input file. This is because the compiler outputs
386 #NO_APP at the beginning of its output. */
387/* Also note that C style comments are always supported. */
388const char line_comment_chars[] = "#";
389
390/* This array holds machine specific line separator characters. */
391const char line_separator_chars[] = ";";
392
393/* Chars that can be used to separate mant from exp in floating point nums */
394const char EXP_CHARS[] = "eE";
395
396/* Chars that mean this number is a floating point constant */
397/* As in 0f12.456 */
398/* or 0d1.2345e12 */
399const char FLT_CHARS[] = "rRsSfFdDxXpP";
400
2dc8dd17
JW		 401/* Indicate we are already assemble any instructions or not. */
402static bfd_boolean start_assemble = FALSE;
403
8f595e9b
NC		 404/* Indicate ELF attributes are explictly set. */
405static bfd_boolean explicit_attr = FALSE;
2dc8dd17 406
1a79004f
NC		 407/* Indicate CSR or priv instructions are explictly used. */
408static bfd_boolean explicit_priv_attr = FALSE;
3fc6c3dc 409
e23eba97
NC		 410/* Macros for encoding relaxation state for RVC branches and far jumps. */
411#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
412 ((relax_substateT) \
413 (0xc0000000 \
414 | ((uncond) ? 1 : 0) \
415 | ((rvc) ? 2 : 0) \
416 | ((length) << 2)))
417#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
418#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
419#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
420#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
421
422/* Is the given value a sign-extended 32-bit value? */
423#define IS_SEXT_32BIT_NUM(x) \
424 (((x) &~ (offsetT) 0x7fffffff) == 0 \
425 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
426
427/* Is the given value a zero-extended 32-bit value? Or a negated one? */
428#define IS_ZEXT_32BIT_NUM(x) \
429 (((x) &~ (offsetT) 0xffffffff) == 0 \
430 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
431
432/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
433 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
434#define INSERT_OPERAND(FIELD, INSN, VALUE) \
435 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
436
437/* Determine if an instruction matches an opcode. */
438#define OPCODE_MATCHES(OPCODE, OP) \
439 (((OPCODE) & MASK_##OP) == MATCH_##OP)
440
441static char *expr_end;
442
443/* The default target format to use. */
444
445const char *
446riscv_target_format (void)
447{
448 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
449}
450
451/* Return the length of instruction INSN. */
452
453static inline unsigned int
454insn_length (const struct riscv_cl_insn *insn)
455{
456 return riscv_insn_length (insn->insn_opcode);
457}
458
459/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
460
461static void
462create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
463{
464 insn->insn_mo = mo;
465 insn->insn_opcode = mo->match;
466 insn->frag = NULL;
467 insn->where = 0;
468 insn->fixp = NULL;
469}
470
471/* Install INSN at the location specified by its "frag" and "where" fields. */
472
473static void
474install_insn (const struct riscv_cl_insn *insn)
475{
476 char *f = insn->frag->fr_literal + insn->where;
477 md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
478}
479
480/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
481 and install the opcode in the new location. */
482
483static void
484move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
485{
486 insn->frag = frag;
487 insn->where = where;
488 if (insn->fixp != NULL)
489 {
490 insn->fixp->fx_frag = frag;
491 insn->fixp->fx_where = where;
492 }
493 install_insn (insn);
494}
495
496/* Add INSN to the end of the output. */
497
498static void
499add_fixed_insn (struct riscv_cl_insn *insn)
500{
501 char *f = frag_more (insn_length (insn));
502 move_insn (insn, frag_now, f - frag_now->fr_literal);
503}
504
505static void
506add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
507 relax_substateT subtype, symbolS *symbol, offsetT offset)
508{
509 frag_grow (max_chars);
510 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
511 frag_var (rs_machine_dependent, max_chars, var,
512 subtype, symbol, offset, NULL);
513}
514
515/* Compute the length of a branch sequence, and adjust the stored length
516 accordingly. If FRAGP is NULL, the worst-case length is returned. */
517
518static unsigned
519relaxed_branch_length (fragS *fragp, asection *sec, int update)
520{
521 int jump, rvc, length = 8;
522
523 if (!fragp)
524 return length;
525
526 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
527 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
528 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
529
530 /* Assume jumps are in range; the linker will catch any that aren't. */
531 length = jump ? 4 : 8;
532
533 if (fragp->fr_symbol != NULL
534 && S_IS_DEFINED (fragp->fr_symbol)
01156111 535 && !S_IS_WEAK (fragp->fr_symbol)
e23eba97
NC		 536 && sec == S_GET_SEGMENT (fragp->fr_symbol))
537 {
538 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
539 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
540 val -= fragp->fr_address + fragp->fr_fix;
541
542 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
543 length = 2;
544 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
545 length = 4;
546 else if (!jump && rvc)
547 length = 6;
548 }
549
550 if (update)
551 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
552
553 return length;
554}
555
0e35537d
JW		 556/* Information about an opcode name, mnemonics and its value. */
557struct opcode_name_t
558{
559 const char *name;
560 unsigned int val;
561};
562
563/* List for all supported opcode name. */
564static const struct opcode_name_t opcode_name_list[] =
565{
566 {"C0", 0x0},
567 {"C1", 0x1},
568 {"C2", 0x2},
569
570 {"LOAD", 0x03},
571 {"LOAD_FP", 0x07},
572 {"CUSTOM_0", 0x0b},
573 {"MISC_MEM", 0x0f},
574 {"OP_IMM", 0x13},
575 {"AUIPC", 0x17},
576 {"OP_IMM_32", 0x1b},
577 /* 48b 0x1f. */
578
579 {"STORE", 0x23},
580 {"STORE_FP", 0x27},
581 {"CUSTOM_1", 0x2b},
582 {"AMO", 0x2f},
583 {"OP", 0x33},
584 {"LUI", 0x37},
585 {"OP_32", 0x3b},
586 /* 64b 0x3f. */
587
588 {"MADD", 0x43},
589 {"MSUB", 0x47},
590 {"NMADD", 0x4f},
591 {"NMSUB", 0x4b},
592 {"OP_FP", 0x53},
593 /*reserved 0x57. */
594 {"CUSTOM_2", 0x5b},
595 /* 48b 0x5f. */
596
597 {"BRANCH", 0x63},
598 {"JALR", 0x67},
599 /*reserved 0x5b. */
600 {"JAL", 0x6f},
601 {"SYSTEM", 0x73},
602 /*reserved 0x77. */
603 {"CUSTOM_3", 0x7b},
604 /* >80b 0x7f. */
605
606 {NULL, 0}
607};
608
609/* Hash table for lookup opcode name. */
629310ab 610static htab_t opcode_names_hash = NULL;
0e35537d
JW		 611
612/* Initialization for hash table of opcode name. */
613static void
614init_opcode_names_hash (void)
615{
0e35537d
JW		 616 const struct opcode_name_t *opcode;
617
618 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
fe0e921f
AM		 619 if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL)
620 as_fatal (_("duplicate %s"), opcode->name);
0e35537d
JW		 621}
622
623/* Find `s` is a valid opcode name or not,
624 return the opcode name info if found. */
625static const struct opcode_name_t *
626opcode_name_lookup (char **s)
627{
628 char *e;
629 char save_c;
630 struct opcode_name_t *o;
631
632 /* Find end of name. */
633 e = *s;
634 if (is_name_beginner (*e))
635 ++e;
636 while (is_part_of_name (*e))
637 ++e;
638
639 /* Terminate name. */
640 save_c = *e;
641 *e = '\0';
642
629310ab 643 o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s);
0e35537d
JW		 644
645 /* Advance to next token if one was recognized. */
646 if (o)
647 *s = e;
648
649 *e = save_c;
650 expr_end = e;
651
652 return o;
653}
654
e23eba97
NC		 655enum reg_class
656{
657 RCLASS_GPR,
658 RCLASS_FPR,
8f595e9b
NC		 659 RCLASS_MAX,
660
661 RCLASS_CSR
e23eba97
NC		 662};
663
629310ab
ML		 664static htab_t reg_names_hash = NULL;
665static htab_t csr_extra_hash = NULL;
e23eba97
NC		 666
667#define ENCODE_REG_HASH(cls, n) \
668 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
669#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
670#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
671
672static void
673hash_reg_name (enum reg_class class, const char *name, unsigned n)
674{
675 void *hash = ENCODE_REG_HASH (class, n);
fe0e921f
AM		 676 if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL)
677 as_fatal (_("duplicate %s"), name);
e23eba97
NC		 678}
679
680static void
681hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
682{
683 unsigned i;
684
685 for (i = 0; i < n; i++)
686 hash_reg_name (class, names[i], i);
687}
688
8f595e9b
NC		 689/* Init hash table csr_extra_hash to handle CSR. */
690static void
691riscv_init_csr_hash (const char *name,
692 unsigned address,
693 enum riscv_csr_class class,
694 enum riscv_priv_spec_class define_version,
695 enum riscv_priv_spec_class abort_version)
696{
697 struct riscv_csr_extra *entry, *pre_entry;
8f595e9b
NC		 698 bfd_boolean need_enrty = TRUE;
699
700 pre_entry = NULL;
629310ab 701 entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
8f595e9b
NC		 702 while (need_enrty && entry != NULL)
703 {
704 if (entry->csr_class == class
705 && entry->address == address
706 && entry->define_version == define_version
707 && entry->abort_version == abort_version)
708 need_enrty = FALSE;
709 pre_entry = entry;
710 entry = entry->next;
711 }
712
713 /* Duplicate setting for the CSR, just return and do nothing. */
714 if (!need_enrty)
715 return;
bd0cf5a6 716
8f595e9b
NC		 717 entry = XNEW (struct riscv_csr_extra);
718 entry->csr_class = class;
719 entry->address = address;
720 entry->define_version = define_version;
721 entry->abort_version = abort_version;
5c505568 722 entry->next = NULL;
8f595e9b
NC		 723
724 /* If the CSR hasn't been inserted in the hash table, then insert it.
725 Otherwise, attach the extra information to the entry which is already
726 in the hash table. */
727 if (pre_entry == NULL)
fe0e921f 728 str_hash_insert (csr_extra_hash, name, entry, 0);
8f595e9b
NC		 729 else
730 pre_entry->next = entry;
731}
bd0cf5a6 732
08ccfccf
NC		 733/* Return the suitable CSR address after checking the ISA dependency and
734 priv spec versions. */
bd0cf5a6 735
08ccfccf
NC		 736static unsigned int
737riscv_csr_address (const char *csr_name,
738 struct riscv_csr_extra *entry)
bd0cf5a6 739{
08ccfccf
NC		 740 struct riscv_csr_extra *saved_entry = entry;
741 enum riscv_csr_class csr_class = entry->csr_class;
742 bfd_boolean need_check_version = TRUE;
8f595e9b
NC		 743 bfd_boolean result = TRUE;
744
8f595e9b 745 switch (csr_class)
bd0cf5a6 746 {
8f595e9b
NC		 747 case CSR_CLASS_I:
748 result = riscv_subset_supports ("i");
749 break;
08ccfccf
NC		 750 case CSR_CLASS_I_32:
751 result = (xlen == 32 && riscv_subset_supports ("i"));
752 break;
8f595e9b
NC		 753 case CSR_CLASS_F:
754 result = riscv_subset_supports ("f");
08ccfccf 755 need_check_version = FALSE;
8f595e9b 756 break;
08ccfccf
NC		 757 case CSR_CLASS_DEBUG:
758 need_check_version = FALSE;
8f595e9b
NC		 759 break;
760 default:
761 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
bd0cf5a6
NC		 762 }
763
08ccfccf
NC		 764 /* Don't report the ISA conflict when -mcsr-check isn't set. */
765 if (riscv_opts.csr_check && !result)
766 as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name);
8f595e9b
NC		 767
768 while (entry != NULL)
bd0cf5a6 769 {
08ccfccf
NC		 770 if (!need_check_version
771 || (default_priv_spec >= entry->define_version
772 && default_priv_spec < entry->abort_version))
8f595e9b
NC		 773 {
774 /* Find the suitable CSR according to the specific version. */
08ccfccf 775 return entry->address;
8f595e9b
NC		 776 }
777 entry = entry->next;
778 }
bd0cf5a6 779
8f595e9b
NC		 780 /* We can not find the suitable CSR address according to the privilege
781 version. Therefore, we use the last defined value. Report the warning
782 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
783 otherwise, you may get the unexpected CSR address. */
784 if (riscv_opts.csr_check)
785 {
786 const char *priv_name = riscv_get_priv_spec_name (default_priv_spec);
787
788 if (priv_name != NULL)
789 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
790 csr_name, priv_name);
bd0cf5a6 791 }
08ccfccf
NC		 792
793 return saved_entry->address;
bd0cf5a6
NC		 794}
795
8f595e9b
NC		 796/* Once the CSR is defined, including the old privilege spec, then we call
797 riscv_csr_class_check and riscv_csr_version_check to do the further checking
798 and get the corresponding address. Return -1 if the CSR is never been
799 defined. Otherwise, return the address. */
bd0cf5a6 800
8f595e9b 801static unsigned int
bd0cf5a6
NC		 802reg_csr_lookup_internal (const char *s)
803{
804 struct riscv_csr_extra *r =
629310ab 805 (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s);
bd0cf5a6
NC		 806
807 if (r == NULL)
8f595e9b 808 return -1U;
bd0cf5a6 809
8f595e9b
NC		 810 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
811 the CSR was defined, but isn't allowed for the current ISA setting or
812 the privilege spec. If the CSR is never been defined, then assembler
813 will regard it as a "Unknown CSR" and report error. If user use number
814 to set the CSR, but over the range (> 0xfff), then assembler will report
815 "Improper CSR" error for it. */
08ccfccf 816 return riscv_csr_address (s, r);
bd0cf5a6
NC		 817}
818
e23eba97
NC		 819static unsigned int
820reg_lookup_internal (const char *s, enum reg_class class)
821{
8f595e9b
NC		 822 void *r;
823
824 if (class == RCLASS_CSR)
825 return reg_csr_lookup_internal (s);
e23eba97 826
629310ab 827 r = str_hash_find (reg_names_hash, s);
e23eba97
NC		 828 if (r == NULL || DECODE_REG_CLASS (r) != class)
829 return -1;
7f999549
JW		 830
831 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
832 return -1;
833
e23eba97
NC		 834 return DECODE_REG_NUM (r);
835}
836
837static bfd_boolean
838reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
839{
840 char *e;
841 char save_c;
842 int reg = -1;
843
844 /* Find end of name. */
845 e = *s;
846 if (is_name_beginner (*e))
847 ++e;
848 while (is_part_of_name (*e))
849 ++e;
850
851 /* Terminate name. */
852 save_c = *e;
853 *e = '\0';
854
855 /* Look for the register. Advance to next token if one was recognized. */
856 if ((reg = reg_lookup_internal (*s, class)) >= 0)
857 *s = e;
858
859 *e = save_c;
860 if (regnop)
861 *regnop = reg;
862 return reg >= 0;
863}
864
865static bfd_boolean
866arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
867{
868 const char *p = strchr (*s, ',');
869 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
870
bfb218e3
JW		 871 if (len == 0)
872 return FALSE;
873
e23eba97
NC		 874 for (i = 0; i < size; i++)
875 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
876 {
877 *regnop = i;
878 *s += len;
879 return TRUE;
880 }
881
882 return FALSE;
883}
884
885/* For consistency checking, verify that all bits are specified either
886 by the match/mask part of the instruction definition, or by the
0e35537d
JW		 887 operand list.
888
889 `length` could be 0, 4 or 8, 0 for auto detection. */
e23eba97 890static bfd_boolean
0e35537d 891validate_riscv_insn (const struct riscv_opcode *opc, int length)
e23eba97
NC		 892{
893 const char *p = opc->args;
894 char c;
895 insn_t used_bits = opc->mask;
0e35537d
JW		 896 int insn_width;
897 insn_t required_bits;
898
899 if (length == 0)
900 insn_width = 8 * riscv_insn_length (opc->match);
901 else
902 insn_width = 8 * length;
903
904 required_bits = ~0ULL >> (64 - insn_width);
e23eba97
NC		 905
906 if ((used_bits & opc->match) != (opc->match & required_bits))
907 {
908 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
909 opc->name, opc->args);
910 return FALSE;
911 }
912
913#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
914 while (*p)
915 switch (c = *p++)
916 {
917 case 'C': /* RVC */
918 switch (c = *p++)
919 {
1d65abb5 920 case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
e23eba97
NC		 921 case 'c': break; /* RS1, constrained to equal sp */
922 case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
1d65abb5 923 case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
b416fe87 924 case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
1d65abb5
AW		 925 case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
926 case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
927 case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
928 case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
929 case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
e23eba97
NC		 930 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
931 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
1d65abb5
AW		 932 case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
933 case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
e23eba97
NC		 934 case 'w': break; /* RS1S, constrained to equal RD */
935 case 'x': break; /* RS2S, constrained to equal RD */
ca0bc150 936 case 'z': break; /* RS2S, contrained to be x0 */
1d65abb5
AW		 937 case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
938 case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
939 case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
940 case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
e23eba97
NC		 941 case 'U': break; /* RS1, constrained to equal RD */
942 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1d65abb5
AW		 943 case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
944 case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
0e35537d
JW		 945 case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
946 case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
e23eba97
NC		 947 case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
948 case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
0e35537d
JW		 949 case 'F': /* funct */
950 switch (c = *p++)
951 {
4765cd61 952 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
0e35537d
JW		 953 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
954 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
4765cd61 955 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
0e35537d
JW		 956 default:
957 as_bad (_("internal: bad RISC-V opcode"
958 " (unknown operand type `CF%c'): %s %s"),
959 c, opc->name, opc->args);
960 return FALSE;
961 }
962 break;
e23eba97
NC		 963 default:
964 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
965 c, opc->name, opc->args);
966 return FALSE;
967 }
968 break;
969 case ',': break;
970 case '(': break;
971 case ')': break;
972 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
973 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
974 case 'A': break;
975 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
976 case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
977 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
978 case 'I': break;
979 case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
980 case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
981 case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */
982 case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
983 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
984 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
985 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
986 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
0e35537d 987 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
e23eba97
NC		 988 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
989 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
990 case 'o':
1d65abb5
AW		 991 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
992 case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
993 case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
994 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
995 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
e925c834 996 case 'z': break;
e23eba97
NC		 997 case '[': break;
998 case ']': break;
999 case '0': break;
f50fabe4 1000 case '1': break;
0e35537d
JW		 1001 case 'F': /* funct */
1002 switch (c = *p++)
1003 {
1004 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
1005 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
1006 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
1007 default:
1008 as_bad (_("internal: bad RISC-V opcode"
1009 " (unknown operand type `F%c'): %s %s"),
1010 c, opc->name, opc->args);
1011 return FALSE;
1012 }
1013 break;
1014 case 'O': /* opcode */
1015 switch (c = *p++)
1016 {
1017 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
1018 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
1019 default:
1020 as_bad (_("internal: bad RISC-V opcode"
1021 " (unknown operand type `F%c'): %s %s"),
1022 c, opc->name, opc->args);
1023 return FALSE;
1024 }
1025 break;
e23eba97
NC		 1026 default:
1027 as_bad (_("internal: bad RISC-V opcode "
1028 "(unknown operand type `%c'): %s %s"),
1029 c, opc->name, opc->args);
1030 return FALSE;
1031 }
1032#undef USE_BITS
1033 if (used_bits != required_bits)
1034 {
1035 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1036 ~(unsigned long)(used_bits & required_bits),
1037 opc->name, opc->args);
1038 return FALSE;
1039 }
1040 return TRUE;
1041}
1042
1043struct percent_op_match
1044{
1045 const char *str;
1046 bfd_reloc_code_real_type reloc;
1047};
1048
0e35537d
JW		 1049/* Common hash table initialization function for
1050 instruction and .insn directive. */
629310ab 1051static htab_t
0e35537d
JW		 1052init_opcode_hash (const struct riscv_opcode *opcodes,
1053 bfd_boolean insn_directive_p)
e23eba97
NC		 1054{
1055 int i = 0;
0e35537d 1056 int length;
629310ab 1057 htab_t hash = str_htab_create ();
0e35537d 1058 while (opcodes[i].name)
e23eba97 1059 {
0e35537d 1060 const char *name = opcodes[i].name;
fe0e921f
AM		 1061 if (str_hash_insert (hash, name, &opcodes[i], 0) != NULL)
1062 as_fatal (_("duplicate %s"), name);
e23eba97
NC		 1063
1064 do
1065 {
0e35537d 1066 if (opcodes[i].pinfo != INSN_MACRO)
e23eba97 1067 {
0e35537d
JW		 1068 if (insn_directive_p)
1069 length = ((name[0] == 'c') ? 2 : 4);
1070 else
1071 length = 0; /* Let assembler determine the length. */
1072 if (!validate_riscv_insn (&opcodes[i], length))
e23eba97
NC		 1073 as_fatal (_("Broken assembler. No assembly attempted."));
1074 }
0e35537d
JW		 1075 else
1076 gas_assert (!insn_directive_p);
e23eba97
NC		 1077 ++i;
1078 }
0e35537d 1079 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
e23eba97
NC		 1080 }
1081
0e35537d
JW		 1082 return hash;
1083}
1084
1085/* This function is called once, at assembler startup time. It should set up
1086 all the tables, etc. that the MD part of the assembler will need. */
1087
1088void
1089md_begin (void)
1090{
1091 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
1092
1093 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
1094 as_warn (_("Could not set architecture and machine"));
1095
1096 op_hash = init_opcode_hash (riscv_opcodes, FALSE);
1097 insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
1098
629310ab 1099 reg_names_hash = str_htab_create ();
e23eba97
NC		 1100 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
1101 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
1102 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
1103 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
b9c04e5a
JW		 1104 /* Add "fp" as an alias for "s0". */
1105 hash_reg_name (RCLASS_GPR, "fp", 8);
1106
bd0cf5a6 1107 /* Create and insert CSR hash tables. */
629310ab 1108 csr_extra_hash = str_htab_create ();
8f595e9b
NC		 1109#define DECLARE_CSR(name, num, class, define_version, abort_version) \
1110 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1111#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1112 DECLARE_CSR(name, num, class, define_version, abort_version);
e23eba97
NC		 1113#include "opcode/riscv-opc.h"
1114#undef DECLARE_CSR
1115
629310ab 1116 opcode_names_hash = str_htab_create ();
bd0cf5a6
NC		 1117 init_opcode_names_hash ();
1118
e23eba97
NC		 1119 /* Set the default alignment for the text section. */
1120 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
1121}
1122
45f76423
AW		 1123static insn_t
1124riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
1125{
1126 switch (reloc_type)
1127 {
1128 case BFD_RELOC_32:
1129 return value;
1130
1131 case BFD_RELOC_RISCV_HI20:
1132 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
1133
1134 case BFD_RELOC_RISCV_LO12_S:
1135 return ENCODE_STYPE_IMM (value);
1136
1137 case BFD_RELOC_RISCV_LO12_I:
1138 return ENCODE_ITYPE_IMM (value);
1139
1140 default:
1141 abort ();
1142 }
1143}
1144
e23eba97
NC		 1145/* Output an instruction. IP is the instruction information.
1146 ADDRESS_EXPR is an operand of the instruction to be used with
1147 RELOC_TYPE. */
1148
1149static void
1150append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
1151 bfd_reloc_code_real_type reloc_type)
1152{
1153 dwarf2_emit_insn (0);
1154
1155 if (reloc_type != BFD_RELOC_UNUSED)
1156 {
1157 reloc_howto_type *howto;
1158
1d65abb5 1159 gas_assert (address_expr);
e23eba97
NC		 1160 if (reloc_type == BFD_RELOC_12_PCREL
1161 || reloc_type == BFD_RELOC_RISCV_JMP)
1162 {
1163 int j = reloc_type == BFD_RELOC_RISCV_JMP;
1164 int best_case = riscv_insn_length (ip->insn_opcode);
1165 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
743f5cfc
JW		 1166
1167 if (now_seg == absolute_section)
1168 {
1169 as_bad (_("relaxable branches not supported in absolute section"));
1170 return;
1171 }
1172
e23eba97
NC		 1173 add_relaxed_insn (ip, worst_case, best_case,
1174 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
1175 address_expr->X_add_symbol,
1176 address_expr->X_add_number);
1177 return;
1178 }
45f76423 1179 else
e23eba97 1180 {
45f76423
AW		 1181 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
1182 if (howto == NULL)
1183 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
e23eba97 1184
45f76423
AW		 1185 ip->fixp = fix_new_exp (ip->frag, ip->where,
1186 bfd_get_reloc_size (howto),
1187 address_expr, FALSE, reloc_type);
e23eba97 1188
45f76423 1189 ip->fixp->fx_tcbit = riscv_opts.relax;
e23eba97 1190 }
e23eba97
NC		 1191 }
1192
e23eba97
NC		 1193 add_fixed_insn (ip);
1194 install_insn (ip);
f77bb6c5
JW		 1195
1196 /* We need to start a new frag after any instruction that can be
1197 optimized away or compressed by the linker during relaxation, to prevent
1198 the assembler from computing static offsets across such an instruction.
1199 This is necessary to get correct EH info. */
b1b11e92 1200 if (reloc_type == BFD_RELOC_RISCV_HI20
f77bb6c5
JW		 1201 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
1202 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
1203 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
1204 {
1205 frag_wane (frag_now);
1206 frag_new (0);
1207 }
e23eba97
NC		 1208}
1209
1210/* Build an instruction created by a macro expansion. This is passed
1211 a pointer to the count of instructions created so far, an
1212 expression, the name of the instruction to build, an operand format
1213 string, and corresponding arguments. */
1214
1215static void
1216macro_build (expressionS *ep, const char *name, const char *fmt, ...)
1217{
1218 const struct riscv_opcode *mo;
1219 struct riscv_cl_insn insn;
1220 bfd_reloc_code_real_type r;
1221 va_list args;
1222
1223 va_start (args, fmt);
1224
1225 r = BFD_RELOC_UNUSED;
629310ab 1226 mo = (struct riscv_opcode *) str_hash_find (op_hash, name);
e23eba97
NC		 1227 gas_assert (mo);
1228
1229 /* Find a non-RVC variant of the instruction. append_insn will compress
1230 it if possible. */
1231 while (riscv_insn_length (mo->match) < 4)
1232 mo++;
1233 gas_assert (strcmp (name, mo->name) == 0);
1234
1235 create_insn (&insn, mo);
1236 for (;;)
1237 {
1238 switch (*fmt++)
1239 {
1240 case 'd':
1241 INSERT_OPERAND (RD, insn, va_arg (args, int));
1242 continue;
1243
1244 case 's':
1245 INSERT_OPERAND (RS1, insn, va_arg (args, int));
1246 continue;
1247
1248 case 't':
1249 INSERT_OPERAND (RS2, insn, va_arg (args, int));
1250 continue;
1251
1252 case '>':
1253 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
1254 continue;
1255
1256 case 'j':
1257 case 'u':
1258 case 'q':
1259 gas_assert (ep != NULL);
1260 r = va_arg (args, int);
1261 continue;
1262
1263 case '\0':
1264 break;
1265 case ',':
1266 continue;
1267 default:
1268 as_fatal (_("internal error: invalid macro"));
1269 }
1270 break;
1271 }
1272 va_end (args);
1273 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1274
1275 append_insn (&insn, ep, r);
1276}
1277
db3b6ecc
KC		 1278/* Build an instruction created by a macro expansion. Like md_assemble but
1279 accept a printf-style format string and arguments. */
1280
1281static void
1282md_assemblef (const char *format, ...)
1283{
1284 char *buf = NULL;
1285 va_list ap;
1286 int r;
1287
1288 va_start (ap, format);
1289
1290 r = vasprintf (&buf, format, ap);
1291
1292 if (r < 0)
1293 as_fatal (_("internal error: vasprintf failed"));
1294
1295 md_assemble (buf);
1296 free(buf);
1297
1298 va_end (ap);
1299}
1300
e23eba97
NC		 1301/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1302 unset. */
1303static void
1304normalize_constant_expr (expressionS *ex)
1305{
1306 if (xlen > 32)
1307 return;
1308 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1309 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1310 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1311 - 0x80000000);
1312}
1313
ca2fd32c
JW		 1314/* Fail if an expression EX is not a constant. IP is the instruction using EX.
1315 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
e23eba97
NC		 1316
1317static void
ca2fd32c
JW		 1318check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
1319 bfd_boolean maybe_csr)
e23eba97
NC		 1320{
1321 if (ex->X_op == O_big)
1322 as_bad (_("unsupported large constant"));
ca2fd32c
JW		 1323 else if (maybe_csr && ex->X_op == O_symbol)
1324 as_bad (_("unknown CSR `%s'"),
1325 S_GET_NAME (ex->X_add_symbol));
e23eba97
NC		 1326 else if (ex->X_op != O_constant)
1327 as_bad (_("Instruction %s requires absolute expression"),
1328 ip->insn_mo->name);
1329 normalize_constant_expr (ex);
1330}
1331
1332static symbolS *
1333make_internal_label (void)
1334{
e01e1cee
AM		 1335 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now,
1336 frag_now_fix ());
e23eba97
NC		 1337}
1338
1339/* Load an entry from the GOT. */
1340static void
1341pcrel_access (int destreg, int tempreg, expressionS *ep,
1342 const char *lo_insn, const char *lo_pattern,
1343 bfd_reloc_code_real_type hi_reloc,
1344 bfd_reloc_code_real_type lo_reloc)
1345{
1346 expressionS ep2;
1347 ep2.X_op = O_symbol;
1348 ep2.X_add_symbol = make_internal_label ();
1349 ep2.X_add_number = 0;
1350
1351 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1352 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1353}
1354
1355static void
1356pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1357 bfd_reloc_code_real_type hi_reloc,
1358 bfd_reloc_code_real_type lo_reloc)
1359{
1360 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1361}
1362
1363static void
1364pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1365 bfd_reloc_code_real_type hi_reloc,
1366 bfd_reloc_code_real_type lo_reloc)
1367{
1368 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1369}
1370
1371/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1372static void
1373riscv_call (int destreg, int tempreg, expressionS *ep,
1374 bfd_reloc_code_real_type reloc)
1375{
b1b11e92
AM		 1376 /* Ensure the jalr is emitted to the same frag as the auipc. */
1377 frag_grow (8);
e23eba97
NC		 1378 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1379 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
b1b11e92
AM		 1380 /* See comment at end of append_insn. */
1381 frag_wane (frag_now);
1382 frag_new (0);
e23eba97
NC		 1383}
1384
1385/* Load an integer constant into a register. */
1386
1387static void
1388load_const (int reg, expressionS *ep)
1389{
1390 int shift = RISCV_IMM_BITS;
4f7cc141 1391 bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1);
e23eba97 1392 expressionS upper = *ep, lower = *ep;
4f7cc141 1393 lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign;
e23eba97
NC		 1394 upper.X_add_number -= lower.X_add_number;
1395
1396 if (ep->X_op != O_constant)
1397 {
1398 as_bad (_("unsupported large constant"));
1399 return;
1400 }
1401
1d65abb5 1402 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
e23eba97
NC		 1403 {
1404 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1405 while (((upper.X_add_number >> shift) & 1) == 0)
1406 shift++;
1407
1408 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1d65abb5 1409 load_const (reg, &upper);
e23eba97 1410
db3b6ecc 1411 md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift);
e23eba97 1412 if (lower.X_add_number != 0)
db3b6ecc
KC		 1413 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg,
1414 lower.X_add_number);
e23eba97
NC		 1415 }
1416 else
1417 {
1418 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1419 int hi_reg = 0;
1420
1421 if (upper.X_add_number != 0)
1422 {
db3b6ecc
KC		 1423 /* Discard low part and zero-extend upper immediate. */
1424 upper_imm = ((uint32_t)upper.X_add_number >> shift);
1425
1426 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm);
e23eba97
NC		 1427 hi_reg = reg;
1428 }
1429
1430 if (lower.X_add_number != 0 || hi_reg == 0)
db3b6ecc
KC		 1431 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg,
1432 lower.X_add_number);
e23eba97
NC		 1433 }
1434}
1435
1436/* Expand RISC-V assembly macros into one or more instructions. */
1437static void
1438macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1439 bfd_reloc_code_real_type *imm_reloc)
1440{
1441 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1442 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1443 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1444 int mask = ip->insn_mo->mask;
1445
1446 switch (mask)
1447 {
1448 case M_LI:
1449 load_const (rd, imm_expr);
1450 break;
1451
1452 case M_LA:
1453 case M_LLA:
1454 /* Load the address of a symbol into a register. */
1455 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1456 as_bad (_("offset too large"));
1457
1458 if (imm_expr->X_op == O_constant)
1459 load_const (rd, imm_expr);
1460 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */
1461 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1462 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1463 else /* Local PIC symbol, or any non-PIC symbol */
1464 pcrel_load (rd, rd, imm_expr, "addi",
1465 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1466 break;
1467
1468 case M_LA_TLS_GD:
1469 pcrel_load (rd, rd, imm_expr, "addi",
1470 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1471 break;
1472
1473 case M_LA_TLS_IE:
1474 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1475 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1476 break;
1477
1478 case M_LB:
1479 pcrel_load (rd, rd, imm_expr, "lb",
1480 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1481 break;
1482
1483 case M_LBU:
1484 pcrel_load (rd, rd, imm_expr, "lbu",
1485 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1486 break;
1487
1488 case M_LH:
1489 pcrel_load (rd, rd, imm_expr, "lh",
1490 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1491 break;
1492
1493 case M_LHU:
1494 pcrel_load (rd, rd, imm_expr, "lhu",
1495 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1496 break;
1497
1498 case M_LW:
1499 pcrel_load (rd, rd, imm_expr, "lw",
1500 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1501 break;
1502
1503 case M_LWU:
1504 pcrel_load (rd, rd, imm_expr, "lwu",
1505 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1506 break;
1507
1508 case M_LD:
1509 pcrel_load (rd, rd, imm_expr, "ld",
1510 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1511 break;
1512
1513 case M_FLW:
1514 pcrel_load (rd, rs1, imm_expr, "flw",
1515 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1516 break;
1517
1518 case M_FLD:
1519 pcrel_load (rd, rs1, imm_expr, "fld",
1520 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1521 break;
1522
1523 case M_SB:
1524 pcrel_store (rs2, rs1, imm_expr, "sb",
1525 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1526 break;
1527
1528 case M_SH:
1529 pcrel_store (rs2, rs1, imm_expr, "sh",
1530 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1531 break;
1532
1533 case M_SW:
1534 pcrel_store (rs2, rs1, imm_expr, "sw",
1535 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1536 break;
1537
1538 case M_SD:
1539 pcrel_store (rs2, rs1, imm_expr, "sd",
1540 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1541 break;
1542
1543 case M_FSW:
1544 pcrel_store (rs2, rs1, imm_expr, "fsw",
1545 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1546 break;
1547
1548 case M_FSD:
1549 pcrel_store (rs2, rs1, imm_expr, "fsd",
1550 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1551 break;
1552
1553 case M_CALL:
1554 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1555 break;
1556
1557 default:
1558 as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
1559 break;
1560 }
1561}
1562
1563static const struct percent_op_match percent_op_utype[] =
1564{
1565 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1566 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
dee35d02 1567 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
e23eba97
NC		 1568 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1569 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1570 {"%hi", BFD_RELOC_RISCV_HI20},
1571 {0, 0}
1572};
1573
1574static const struct percent_op_match percent_op_itype[] =
1575{
1576 {"%lo", BFD_RELOC_RISCV_LO12_I},
1577 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1578 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1579 {0, 0}
1580};
1581
1582static const struct percent_op_match percent_op_stype[] =
1583{
1584 {"%lo", BFD_RELOC_RISCV_LO12_S},
1585 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1586 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1587 {0, 0}
1588};
1589
1590static const struct percent_op_match percent_op_rtype[] =
1591{
1592 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1593 {0, 0}
1594};
1595
f50fabe4
JW		 1596static const struct percent_op_match percent_op_null[] =
1597{
1598 {0, 0}
1599};
1600
e23eba97
NC		 1601/* Return true if *STR points to a relocation operator. When returning true,
1602 move *STR over the operator and store its relocation code in *RELOC.
1603 Leave both *STR and *RELOC alone when returning false. */
1604
1605static bfd_boolean
1606parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1607 const struct percent_op_match *percent_op)
1608{
1609 for ( ; percent_op->str; percent_op++)
1610 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1611 {
1612 int len = strlen (percent_op->str);
1613
1614 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1615 continue;
1616
1617 *str += strlen (percent_op->str);
1618 *reloc = percent_op->reloc;
1619
1620 /* Check whether the output BFD supports this relocation.
1621 If not, issue an error and fall back on something safe. */
45f76423
AW		 1622 if (*reloc != BFD_RELOC_UNUSED
1623 && !bfd_reloc_type_lookup (stdoutput, *reloc))
e23eba97
NC		 1624 {
1625 as_bad ("relocation %s isn't supported by the current ABI",
1626 percent_op->str);
1627 *reloc = BFD_RELOC_UNUSED;
1628 }
1629 return TRUE;
1630 }
1631 return FALSE;
1632}
1633
1634static void
1635my_getExpression (expressionS *ep, char *str)
1636{
1637 char *save_in;
1638
1639 save_in = input_line_pointer;
1640 input_line_pointer = str;
1641 expression (ep);
1642 expr_end = input_line_pointer;
1643 input_line_pointer = save_in;
1644}
1645
1646/* Parse string STR as a 16-bit relocatable operand. Store the
1647 expression in *EP and the relocation, if any, in RELOC.
1648 Return the number of relocation operators used (0 or 1).
1649
1650 On exit, EXPR_END points to the first character after the expression. */
1651
1652static size_t
1653my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1654 char *str, const struct percent_op_match *percent_op)
1655{
1656 size_t reloc_index;
1657 unsigned crux_depth, str_depth, regno;
1658 char *crux;
1659
8970c022
JW		 1660 /* First, check for integer registers. No callers can accept a reg, but
1661 we need to avoid accidentally creating a useless undefined symbol below,
1662 if this is an instruction pattern that can't match. A glibc build fails
1663 if this is removed. */
e23eba97
NC		 1664 if (reg_lookup (&str, RCLASS_GPR, &regno))
1665 {
1666 ep->X_op = O_register;
1667 ep->X_add_number = regno;
8970c022 1668 expr_end = str;
e23eba97
NC		 1669 return 0;
1670 }
1671
1672 /* Search for the start of the main expression.
1673 End the loop with CRUX pointing to the start
1674 of the main expression and with CRUX_DEPTH containing the number
1675 of open brackets at that point. */
1676 reloc_index = -1;
1677 str_depth = 0;
1678 do
1679 {
1680 reloc_index++;
1681 crux = str;
1682 crux_depth = str_depth;
1683
1684 /* Skip over whitespace and brackets, keeping count of the number
1685 of brackets. */
1686 while (*str == ' ' || *str == '\t' || *str == '(')
1687 if (*str++ == '(')
1688 str_depth++;
1689 }
1690 while (*str == '%'
1691 && reloc_index < 1
1692 && parse_relocation (&str, reloc, percent_op));
1693
1694 my_getExpression (ep, crux);
1695 str = expr_end;
1696
1697 /* Match every open bracket. */
1698 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1699 if (*str++ == ')')
1700 crux_depth--;
1701
1702 if (crux_depth > 0)
1703 as_bad ("unclosed '('");
1704
1705 expr_end = str;
1706
1707 return reloc_index;
1708}
1709
0e35537d
JW		 1710/* Parse opcode name, could be an mnemonics or number. */
1711static size_t
1712my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1713 char *str, const struct percent_op_match *percent_op)
1714{
1715 const struct opcode_name_t *o = opcode_name_lookup (&str);
1716
1717 if (o != NULL)
1718 {
1719 ep->X_op = O_constant;
1720 ep->X_add_number = o->val;
1721 return 0;
1722 }
1723
1724 return my_getSmallExpression (ep, reloc, str, percent_op);
1725}
1726
f0531ed6
JW		 1727/* Detect and handle implicitly zero load-store offsets. For example,
1728 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1729 an implicit offset was detected. */
1730
1731static bfd_boolean
89424b1d 1732riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
f0531ed6
JW		 1733{
1734 /* Check whether there is only a single bracketed expression left.
1735 If so, it must be the base register and the constant must be zero. */
1736 if (*s == '(' && strchr (s + 1, '(') == 0)
1737 {
89424b1d
MR		 1738 ep->X_op = O_constant;
1739 ep->X_add_number = 0;
f0531ed6
JW		 1740 return TRUE;
1741 }
1742
1743 return FALSE;
1744}
1745
54b2aec1
NC		 1746/* All RISC-V CSR instructions belong to one of these classes. */
1747
1748enum csr_insn_type
1749{
1750 INSN_NOT_CSR,
1751 INSN_CSRRW,
1752 INSN_CSRRS,
1753 INSN_CSRRC
1754};
1755
1756/* Return which CSR instruction is checking. */
1757
1758static enum csr_insn_type
1759riscv_csr_insn_type (insn_t insn)
1760{
1761 if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
1762 || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
1763 return INSN_CSRRW;
1764 else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
1765 || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
1766 return INSN_CSRRS;
1767 else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
1768 || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
1769 return INSN_CSRRC;
1770 else
1771 return INSN_NOT_CSR;
1772}
1773
1774/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1775 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1776 CSR address is 0x3. */
1777
1778static bfd_boolean
1779riscv_csr_read_only_check (insn_t insn)
1780{
1781 int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
1782 int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
1783 int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
1784 enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
1785
1786 if (readonly
1787 && (((csr_insn == INSN_CSRRS
1788 || csr_insn == INSN_CSRRC)
1789 && rs1 != 0)
1790 || csr_insn == INSN_CSRRW))
1791 return FALSE;
1792
1793 return TRUE;
1794}
1795
1a79004f
NC		 1796/* Return True if it is a privileged instruction. Otherwise, return FALSE.
1797
1798 uret is actually a N-ext instruction. So it is better to regard it as
1799 an user instruction rather than the priv instruction.
1800
1801 hret is used to return from traps in H-mode. H-mode is removed since
1802 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1803 Therefore, hret should be controlled by the hypervisor spec rather than
1804 priv spec in the future.
1805
1806 dret is defined in the debug spec, so it should be checked in the future,
1807 too. */
1808
1809static bfd_boolean
1810riscv_is_priv_insn (insn_t insn)
1811{
1812 return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
1813 || ((insn ^ MATCH_MRET) & MASK_MRET) == 0
1814 || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0
1815 || ((insn ^ MATCH_WFI) & MASK_WFI) == 0
1816 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1817 check it here to keep the compatible. Maybe we should issue warning
1818 if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
1819 We already have a similar check for CSR, but not yet for instructions.
1820 It would be good if we could check the spec versions both for CSR and
1821 instructions, but not here. */
1822 || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
1823}
1824
e23eba97
NC		 1825/* This routine assembles an instruction into its binary format. As a
1826 side effect, it sets the global variable imm_reloc to the type of
1827 relocation to do if one of the operands is an address expression. */
1828
1829static const char *
1830riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
629310ab 1831 bfd_reloc_code_real_type *imm_reloc, htab_t hash)
e23eba97
NC		 1832{
1833 char *s;
1834 const char *args;
1835 char c = 0;
1836 struct riscv_opcode *insn;
1837 char *argsStart;
1838 unsigned int regno;
1839 char save_c = 0;
1840 int argnum;
1841 const struct percent_op_match *p;
1842 const char *error = "unrecognized opcode";
54b2aec1
NC		 1843 /* Indicate we are assembling instruction with CSR. */
1844 bfd_boolean insn_with_csr = FALSE;
e23eba97
NC		 1845
1846 /* Parse the name of the instruction. Terminate the string if whitespace
629310ab 1847 is found so that str_hash_find only sees the name part of the string. */
e23eba97
NC		 1848 for (s = str; *s != '\0'; ++s)
1849 if (ISSPACE (*s))
1850 {
1851 save_c = *s;
1852 *s++ = '\0';
1853 break;
1854 }
1855
629310ab 1856 insn = (struct riscv_opcode *) str_hash_find (hash, str);
e23eba97
NC		 1857
1858 argsStart = s;
1859 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1860 {
1080bf78
JW		 1861 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
1862 continue;
1863
7e9ad3a3 1864 if (!riscv_multi_subset_supports (insn->insn_class))
e23eba97
NC		 1865 continue;
1866
1867 create_insn (ip, insn);
1868 argnum = 1;
1869
1870 imm_expr->X_op = O_absent;
1871 *imm_reloc = BFD_RELOC_UNUSED;
1872 p = percent_op_itype;
1873
1874 for (args = insn->args;; ++args)
1875 {
1876 s += strspn (s, " \t");
1877 switch (*args)
1878 {
1879 case '\0': /* End of args. */
1880 if (insn->pinfo != INSN_MACRO)
1881 {
1882 if (!insn->match_func (insn, ip->insn_opcode))
1883 break;
0e35537d
JW		 1884
1885 /* For .insn, insn->match and insn->mask are 0. */
1886 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
1887 ? ip->insn_opcode
1888 : insn->match) == 2
1889 && !riscv_opts.rvc)
e23eba97 1890 break;
54b2aec1 1891
1a79004f
NC		 1892 if (riscv_is_priv_insn (ip->insn_opcode))
1893 explicit_priv_attr = TRUE;
1894
54b2aec1
NC		 1895 /* Check if we write a read-only CSR by the CSR
1896 instruction. */
1897 if (insn_with_csr
1898 && riscv_opts.csr_check
1899 && !riscv_csr_read_only_check (ip->insn_opcode))
1900 {
1901 /* Restore the character in advance, since we want to
1902 report the detailed warning message here. */
1903 if (save_c)
1904 *(argsStart - 1) = save_c;
1905 as_warn (_("Read-only CSR is written `%s'"), str);
1906 insn_with_csr = FALSE;
1907 }
e23eba97
NC		 1908 }
1909 if (*s != '\0')
1910 break;
1911 /* Successful assembly. */
1912 error = NULL;
54b2aec1 1913 insn_with_csr = FALSE;
e23eba97
NC		 1914 goto out;
1915
1916 case 'C': /* RVC */
1917 switch (*++args)
1918 {
1919 case 's': /* RS1 x8-x15 */
1920 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1921 || !(regno >= 8 && regno <= 15))
1922 break;
1923 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1924 continue;
1925 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1926 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1927 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
1928 break;
1929 continue;
1930 case 't': /* RS2 x8-x15 */
1931 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1932 || !(regno >= 8 && regno <= 15))
1933 break;
1934 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1935 continue;
1936 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1937 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1938 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
1939 break;
1940 continue;
1941 case 'U': /* RS1, constrained to equal RD. */
1942 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1943 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
1944 break;
1945 continue;
1946 case 'V': /* RS2 */
1947 if (!reg_lookup (&s, RCLASS_GPR, &regno))
1948 break;
1949 INSERT_OPERAND (CRS2, *ip, regno);
1950 continue;
1951 case 'c': /* RS1, constrained to equal sp. */
1952 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1953 || regno != X_SP)
1954 break;
1955 continue;
ca0bc150
JW		 1956 case 'z': /* RS2, contrained to equal x0. */
1957 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1958 || regno != 0)
1959 break;
1960 continue;
e23eba97
NC		 1961 case '>':
1962 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1963 || imm_expr->X_op != O_constant
1964 || imm_expr->X_add_number <= 0
1965 || imm_expr->X_add_number >= 64)
1966 break;
1967 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
dc1e8a47 1968 rvc_imm_done:
e23eba97
NC		 1969 s = expr_end;
1970 imm_expr->X_op = O_absent;
1971 continue;
1972 case '<':
1973 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1974 || imm_expr->X_op != O_constant
e23eba97 1975 || imm_expr->X_add_number <= 0
169ec512
AM		 1976 || imm_expr->X_add_number >= 32
1977 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1978 break;
1979 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1980 goto rvc_imm_done;
0e35537d
JW		 1981 case '8':
1982 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1983 || imm_expr->X_op != O_constant
0e35537d 1984 || imm_expr->X_add_number < 0
169ec512
AM		 1985 || imm_expr->X_add_number >= 256
1986 || !VALID_RVC_UIMM8 ((valueT) imm_expr->X_add_number))
0e35537d
JW		 1987 break;
1988 ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
1989 goto rvc_imm_done;
e23eba97
NC		 1990 case 'i':
1991 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1992 || imm_expr->X_op != O_constant
1993 || imm_expr->X_add_number == 0
169ec512 1994 || !VALID_RVC_SIMM3 ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1995 break;
1996 ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
1997 goto rvc_imm_done;
1998 case 'j':
1999 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2000 || imm_expr->X_op != O_constant
2001 || imm_expr->X_add_number == 0
169ec512 2002 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2003 break;
2004 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2005 goto rvc_imm_done;
2006 case 'k':
f0531ed6
JW		 2007 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2008 continue;
e23eba97
NC		 2009 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2010 || imm_expr->X_op != O_constant
169ec512 2011 || !VALID_RVC_LW_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2012 break;
2013 ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
2014 goto rvc_imm_done;
2015 case 'l':
f0531ed6
JW		 2016 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2017 continue;
e23eba97
NC		 2018 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2019 || imm_expr->X_op != O_constant
169ec512 2020 || !VALID_RVC_LD_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2021 break;
2022 ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
2023 goto rvc_imm_done;
2024 case 'm':
f0531ed6
JW		 2025 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2026 continue;
e23eba97
NC		 2027 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2028 || imm_expr->X_op != O_constant
169ec512 2029 || !VALID_RVC_LWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2030 break;
2031 ip->insn_opcode |=
2032 ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
2033 goto rvc_imm_done;
2034 case 'n':
f0531ed6
JW		 2035 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2036 continue;
e23eba97
NC		 2037 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2038 || imm_expr->X_op != O_constant
169ec512 2039 || !VALID_RVC_LDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2040 break;
2041 ip->insn_opcode |=
2042 ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
2043 goto rvc_imm_done;
b416fe87
KC		 2044 case 'o':
2045 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2046 || imm_expr->X_op != O_constant
21a186f2
JW		 2047 /* C.addiw, c.li, and c.andi allow zero immediate.
2048 C.addi allows zero immediate as hint. Otherwise this
2049 is same as 'j'. */
169ec512 2050 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
b416fe87
KC		 2051 break;
2052 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2053 goto rvc_imm_done;
e23eba97
NC		 2054 case 'K':
2055 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2056 || imm_expr->X_op != O_constant
169ec512
AM		 2057 || imm_expr->X_add_number == 0
2058 || !VALID_RVC_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2059 break;
2060 ip->insn_opcode |=
2061 ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
2062 goto rvc_imm_done;
2063 case 'L':
2064 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2065 || imm_expr->X_op != O_constant
169ec512
AM		 2066 || imm_expr->X_add_number == 0
2067 || !VALID_RVC_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2068 break;
2069 ip->insn_opcode |=
2070 ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
2071 goto rvc_imm_done;
2072 case 'M':
f0531ed6
JW		 2073 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2074 continue;
e23eba97
NC		 2075 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2076 || imm_expr->X_op != O_constant
169ec512 2077 || !VALID_RVC_SWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2078 break;
2079 ip->insn_opcode |=
2080 ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
2081 goto rvc_imm_done;
2082 case 'N':
f0531ed6
JW		 2083 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2084 continue;
e23eba97
NC		 2085 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2086 || imm_expr->X_op != O_constant
169ec512 2087 || !VALID_RVC_SDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2088 break;
2089 ip->insn_opcode |=
2090 ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
2091 goto rvc_imm_done;
2092 case 'u':
2093 p = percent_op_utype;
2094 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
2095 break;
dc1e8a47 2096 rvc_lui:
e23eba97
NC		 2097 if (imm_expr->X_op != O_constant
2098 || imm_expr->X_add_number <= 0
2099 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
2100 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
2101 && (imm_expr->X_add_number <
2102 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
2103 break;
2104 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2105 goto rvc_imm_done;
2106 case 'v':
2107 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2108 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
2109 || ((int32_t)imm_expr->X_add_number
2110 != imm_expr->X_add_number))
2111 break;
2112 imm_expr->X_add_number =
2113 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
2114 goto rvc_lui;
2115 case 'p':
2116 goto branch;
2117 case 'a':
2118 goto jump;
0e35537d
JW		 2119 case 'S': /* Floating-point RS1 x8-x15. */
2120 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2121 || !(regno >= 8 && regno <= 15))
2122 break;
2123 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2124 continue;
e23eba97
NC		 2125 case 'D': /* Floating-point RS2 x8-x15. */
2126 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2127 || !(regno >= 8 && regno <= 15))
2128 break;
2129 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2130 continue;
2131 case 'T': /* Floating-point RS2. */
2132 if (!reg_lookup (&s, RCLASS_FPR, &regno))
2133 break;
2134 INSERT_OPERAND (CRS2, *ip, regno);
2135 continue;
0e35537d
JW		 2136 case 'F':
2137 switch (*++args)
2138 {
4765cd61
JW		 2139 case '6':
2140 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2141 || imm_expr->X_op != O_constant
2142 || imm_expr->X_add_number < 0
2143 || imm_expr->X_add_number >= 64)
2144 {
2145 as_bad (_("bad value for funct6 field, "
2146 "value must be 0...64"));
2147 break;
2148 }
2149
2150 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
2151 imm_expr->X_op = O_absent;
2152 s = expr_end;
2153 continue;
0e35537d
JW		 2154 case '4':
2155 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2156 || imm_expr->X_op != O_constant
2157 || imm_expr->X_add_number < 0
2158 || imm_expr->X_add_number >= 16)
2159 {
2160 as_bad (_("bad value for funct4 field, "
2161 "value must be 0...15"));
2162 break;
2163 }
2164
2165 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
2166 imm_expr->X_op = O_absent;
2167 s = expr_end;
2168 continue;
2169 case '3':
2170 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2171 || imm_expr->X_op != O_constant
2172 || imm_expr->X_add_number < 0
2173 || imm_expr->X_add_number >= 8)
2174 {
2175 as_bad (_("bad value for funct3 field, "
2176 "value must be 0...7"));
2177 break;
2178 }
2179 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
2180 imm_expr->X_op = O_absent;
2181 s = expr_end;
2182 continue;
4765cd61
JW		 2183 case '2':
2184 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2185 || imm_expr->X_op != O_constant
2186 || imm_expr->X_add_number < 0
2187 || imm_expr->X_add_number >= 4)
2188 {
2189 as_bad (_("bad value for funct2 field, "
2190 "value must be 0...3"));
2191 break;
2192 }
2193 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number);
2194 imm_expr->X_op = O_absent;
2195 s = expr_end;
2196 continue;
0e35537d
JW		 2197 default:
2198 as_bad (_("bad compressed FUNCT field"
2199 " specifier 'CF%c'\n"),
2200 *args);
2201 }
2202 break;
2203
e23eba97
NC		 2204 default:
2205 as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
2206 }
2207 break;
2208
2209 case ',':
2210 ++argnum;
2211 if (*s++ == *args)
2212 continue;
2213 s--;
2214 break;
2215
2216 case '(':
2217 case ')':
2218 case '[':
2219 case ']':
2220 if (*s++ == *args)
2221 continue;
2222 break;
2223
2224 case '<': /* Shift amount, 0 - 31. */
2225 my_getExpression (imm_expr, s);
ca2fd32c 2226 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2227 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2228 as_bad (_("Improper shift amount (%lu)"),
2229 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2230 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
2231 imm_expr->X_op = O_absent;
2232 s = expr_end;
2233 continue;
2234
2235 case '>': /* Shift amount, 0 - (XLEN-1). */
2236 my_getExpression (imm_expr, s);
ca2fd32c 2237 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2238 if ((unsigned long) imm_expr->X_add_number >= xlen)
94f78a77
AW		 2239 as_bad (_("Improper shift amount (%lu)"),
2240 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2241 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
2242 imm_expr->X_op = O_absent;
2243 s = expr_end;
2244 continue;
2245
2246 case 'Z': /* CSRRxI immediate. */
2247 my_getExpression (imm_expr, s);
ca2fd32c 2248 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2249 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2250 as_bad (_("Improper CSRxI immediate (%lu)"),
2251 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2252 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
2253 imm_expr->X_op = O_absent;
2254 s = expr_end;
2255 continue;
2256
2257 case 'E': /* Control register. */
54b2aec1 2258 insn_with_csr = TRUE;
1a79004f 2259 explicit_priv_attr = TRUE;
e23eba97
NC		 2260 if (reg_lookup (&s, RCLASS_CSR, &regno))
2261 INSERT_OPERAND (CSR, *ip, regno);
2262 else
2263 {
2264 my_getExpression (imm_expr, s);
ca2fd32c 2265 check_absolute_expr (ip, imm_expr, TRUE);
e23eba97 2266 if ((unsigned long) imm_expr->X_add_number > 0xfff)
94f78a77
AW		 2267 as_bad (_("Improper CSR address (%lu)"),
2268 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2269 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
2270 imm_expr->X_op = O_absent;
2271 s = expr_end;
2272 }
2273 continue;
2274
2275 case 'm': /* Rounding mode. */
2276 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
2277 {
2278 INSERT_OPERAND (RM, *ip, regno);
2279 continue;
2280 }
2281 break;
2282
2283 case 'P':
2284 case 'Q': /* Fence predecessor/successor. */
2285 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
2286 &regno))
2287 {
2288 if (*args == 'P')
2289 INSERT_OPERAND (PRED, *ip, regno);
2290 else
2291 INSERT_OPERAND (SUCC, *ip, regno);
2292 continue;
2293 }
2294 break;
2295
2296 case 'd': /* Destination register. */
2297 case 's': /* Source register. */
2298 case 't': /* Target register. */
0e35537d 2299 case 'r': /* rs3. */
e23eba97
NC		 2300 if (reg_lookup (&s, RCLASS_GPR, &regno))
2301 {
2302 c = *args;
2303 if (*s == ' ')
2304 ++s;
2305
2306 /* Now that we have assembled one operand, we use the args
2307 string to figure out where it goes in the instruction. */
2308 switch (c)
2309 {
2310 case 's':
2311 INSERT_OPERAND (RS1, *ip, regno);
2312 break;
2313 case 'd':
2314 INSERT_OPERAND (RD, *ip, regno);
2315 break;
2316 case 't':
2317 INSERT_OPERAND (RS2, *ip, regno);
2318 break;
0e35537d
JW		 2319 case 'r':
2320 INSERT_OPERAND (RS3, *ip, regno);
2321 break;
e23eba97
NC		 2322 }
2323 continue;
2324 }
2325 break;
2326
2327 case 'D': /* Floating point rd. */
2328 case 'S': /* Floating point rs1. */
2329 case 'T': /* Floating point rs2. */
2330 case 'U': /* Floating point rs1 and rs2. */
2331 case 'R': /* Floating point rs3. */
2332 if (reg_lookup (&s, RCLASS_FPR, &regno))
2333 {
2334 c = *args;
2335 if (*s == ' ')
2336 ++s;
2337 switch (c)
2338 {
2339 case 'D':
2340 INSERT_OPERAND (RD, *ip, regno);
2341 break;
2342 case 'S':
2343 INSERT_OPERAND (RS1, *ip, regno);
2344 break;
2345 case 'U':
2346 INSERT_OPERAND (RS1, *ip, regno);
2347 /* fallthru */
2348 case 'T':
2349 INSERT_OPERAND (RS2, *ip, regno);
2350 break;
2351 case 'R':
2352 INSERT_OPERAND (RS3, *ip, regno);
2353 break;
2354 }
2355 continue;
2356 }
2357
2358 break;
2359
2360 case 'I':
2361 my_getExpression (imm_expr, s);
2362 if (imm_expr->X_op != O_big
2363 && imm_expr->X_op != O_constant)
2364 break;
2365 normalize_constant_expr (imm_expr);
2366 s = expr_end;
2367 continue;
2368
2369 case 'A':
2370 my_getExpression (imm_expr, s);
2371 normalize_constant_expr (imm_expr);
2372 /* The 'A' format specifier must be a symbol. */
2373 if (imm_expr->X_op != O_symbol)
2374 break;
2375 *imm_reloc = BFD_RELOC_32;
2376 s = expr_end;
2377 continue;
2378
160d1b3d
SH		 2379 case 'B':
2380 my_getExpression (imm_expr, s);
2381 normalize_constant_expr (imm_expr);
2382 /* The 'B' format specifier must be a symbol or a constant. */
2383 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
2384 break;
2385 if (imm_expr->X_op == O_symbol)
2386 *imm_reloc = BFD_RELOC_32;
2387 s = expr_end;
2388 continue;
2389
e23eba97 2390 case 'j': /* Sign-extended immediate. */
e23eba97 2391 p = percent_op_itype;
f50fabe4 2392 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
e23eba97
NC		 2393 goto alu_op;
2394 case 'q': /* Store displacement. */
2395 p = percent_op_stype;
2396 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
2397 goto load_store;
2398 case 'o': /* Load displacement. */
2399 p = percent_op_itype;
2400 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
2401 goto load_store;
f50fabe4 2402 case '1': /* 4-operand add, must be %tprel_add. */
e23eba97 2403 p = percent_op_rtype;
f50fabe4
JW		 2404 goto alu_op;
2405 case '0': /* AMO "displacement," which must be zero. */
2406 p = percent_op_null;
dc1e8a47 2407 load_store:
f0531ed6 2408 if (riscv_handle_implicit_zero_offset (imm_expr, s))
e23eba97 2409 continue;
dc1e8a47 2410 alu_op:
e23eba97
NC		 2411 /* If this value won't fit into a 16 bit offset, then go
2412 find a macro that will generate the 32 bit offset
2413 code pattern. */
2414 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
2415 {
2416 normalize_constant_expr (imm_expr);
2417 if (imm_expr->X_op != O_constant
2418 || (*args == '0' && imm_expr->X_add_number != 0)
f50fabe4 2419 || (*args == '1')
e23eba97
NC		 2420 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
2421 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
2422 break;
2423 }
2424
2425 s = expr_end;
2426 continue;
2427
2428 case 'p': /* PC-relative offset. */
dc1e8a47 2429 branch:
e23eba97
NC		 2430 *imm_reloc = BFD_RELOC_12_PCREL;
2431 my_getExpression (imm_expr, s);
2432 s = expr_end;
2433 continue;
2434
2435 case 'u': /* Upper 20 bits. */
2436 p = percent_op_utype;
4288405d 2437 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
e23eba97 2438 {
4288405d
JW		 2439 if (imm_expr->X_op != O_constant)
2440 break;
2441
e23eba97
NC		 2442 if (imm_expr->X_add_number < 0
2443 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
2444 as_bad (_("lui expression not in range 0..1048575"));
2445
2446 *imm_reloc = BFD_RELOC_RISCV_HI20;
2447 imm_expr->X_add_number <<= RISCV_IMM_BITS;
2448 }
2449 s = expr_end;
2450 continue;
2451
2452 case 'a': /* 20-bit PC-relative offset. */
dc1e8a47 2453 jump:
e23eba97
NC		 2454 my_getExpression (imm_expr, s);
2455 s = expr_end;
2456 *imm_reloc = BFD_RELOC_RISCV_JMP;
2457 continue;
2458
2459 case 'c':
2460 my_getExpression (imm_expr, s);
2461 s = expr_end;
2462 if (strcmp (s, "@plt") == 0)
2463 {
2464 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2465 s += 4;
2466 }
2467 else
2468 *imm_reloc = BFD_RELOC_RISCV_CALL;
2469 continue;
0e35537d
JW		 2470 case 'O':
2471 switch (*++args)
2472 {
2473 case '4':
2474 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2475 || imm_expr->X_op != O_constant
2476 || imm_expr->X_add_number < 0
2477 || imm_expr->X_add_number >= 128
2478 || (imm_expr->X_add_number & 0x3) != 3)
2479 {
2480 as_bad (_("bad value for opcode field, "
2481 "value must be 0...127 and "
2482 "lower 2 bits must be 0x3"));
2483 break;
2484 }
2485
2486 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2487 imm_expr->X_op = O_absent;
2488 s = expr_end;
2489 continue;
2490 case '2':
2491 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2492 || imm_expr->X_op != O_constant
2493 || imm_expr->X_add_number < 0
2494 || imm_expr->X_add_number >= 3)
2495 {
2496 as_bad (_("bad value for opcode field, "
2497 "value must be 0...2"));
2498 break;
2499 }
2500
2501 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2502 imm_expr->X_op = O_absent;
2503 s = expr_end;
2504 continue;
2505 default:
2506 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args);
2507 }
2508 break;
2509
2510 case 'F':
2511 switch (*++args)
2512 {
2513 case '7':
2514 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2515 || imm_expr->X_op != O_constant
2516 || imm_expr->X_add_number < 0
2517 || imm_expr->X_add_number >= 128)
2518 {
2519 as_bad (_("bad value for funct7 field, "
2520 "value must be 0...127"));
2521 break;
2522 }
2523
2524 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2525 imm_expr->X_op = O_absent;
2526 s = expr_end;
2527 continue;
2528 case '3':
2529 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2530 || imm_expr->X_op != O_constant
2531 || imm_expr->X_add_number < 0
2532 || imm_expr->X_add_number >= 8)
2533 {
2534 as_bad (_("bad value for funct3 field, "
2535 "value must be 0...7"));
2536 break;
2537 }
2538
2539 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2540 imm_expr->X_op = O_absent;
2541 s = expr_end;
2542 continue;
2543 case '2':
2544 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2545 || imm_expr->X_op != O_constant
2546 || imm_expr->X_add_number < 0
2547 || imm_expr->X_add_number >= 4)
2548 {
2549 as_bad (_("bad value for funct2 field, "
2550 "value must be 0...3"));
2551 break;
2552 }
2553
2554 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2555 imm_expr->X_op = O_absent;
2556 s = expr_end;
2557 continue;
2558
2559 default:
2560 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args);
2561 }
2562 break;
e23eba97 2563
e925c834
JW		 2564 case 'z':
2565 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2566 || imm_expr->X_op != O_constant
2567 || imm_expr->X_add_number != 0)
2568 break;
2569 s = expr_end;
2570 imm_expr->X_op = O_absent;
2571 continue;
2572
e23eba97
NC		 2573 default:
2574 as_fatal (_("internal error: bad argument type %c"), *args);
2575 }
2576 break;
2577 }
2578 s = argsStart;
2579 error = _("illegal operands");
54b2aec1 2580 insn_with_csr = FALSE;
e23eba97
NC		 2581 }
2582
dc1e8a47 2583 out:
e23eba97
NC		 2584 /* Restore the character we might have clobbered above. */
2585 if (save_c)
2586 *(argsStart - 1) = save_c;
2587
2588 return error;
2589}
2590
2591void
2592md_assemble (char *str)
2593{
2594 struct riscv_cl_insn insn;
2595 expressionS imm_expr;
2596 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2597
8f595e9b
NC		 2598 /* The arch and priv attributes should be set before assembling. */
2599 if (!start_assemble)
2600 {
2601 start_assemble = TRUE;
6e1605e4 2602 riscv_set_abi_by_arch ();
e23eba97 2603
8f595e9b
NC		 2604 /* Set the default_priv_spec according to the priv attributes. */
2605 if (!riscv_set_default_priv_spec (NULL))
2606 return;
2607 }
2608
2609 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
2dc8dd17 2610
e23eba97
NC		 2611 if (error)
2612 {
2613 as_bad ("%s `%s'", error, str);
2614 return;
2615 }
2616
2617 if (insn.insn_mo->pinfo == INSN_MACRO)
2618 macro (&insn, &imm_expr, &imm_reloc);
2619 else
2620 append_insn (&insn, &imm_expr, imm_reloc);
2621}
2622
2623const char *
2624md_atof (int type, char *litP, int *sizeP)
2625{
2626 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2627}
2628
2629void
2630md_number_to_chars (char *buf, valueT val, int n)
2631{
2632 number_to_chars_littleendian (buf, val, n);
2633}
2634
2635const char *md_shortopts = "O::g::G:";
2636
2637enum options
2638{
2922d21d 2639 OPTION_MARCH = OPTION_MD_BASE,
e23eba97
NC		 2640 OPTION_PIC,
2641 OPTION_NO_PIC,
2922d21d 2642 OPTION_MABI,
71060565
JW		 2643 OPTION_RELAX,
2644 OPTION_NO_RELAX,
2dc8dd17
JW		 2645 OPTION_ARCH_ATTR,
2646 OPTION_NO_ARCH_ATTR,
2ca89224
NC		 2647 OPTION_CSR_CHECK,
2648 OPTION_NO_CSR_CHECK,
8f595e9b
NC		 2649 OPTION_MISA_SPEC,
2650 OPTION_MPRIV_SPEC,
e23eba97
NC		 2651 OPTION_END_OF_ENUM
2652};
2653
2654struct option md_longopts[] =
2655{
e23eba97
NC		 2656 {"march", required_argument, NULL, OPTION_MARCH},
2657 {"fPIC", no_argument, NULL, OPTION_PIC},
2658 {"fpic", no_argument, NULL, OPTION_PIC},
2659 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2922d21d 2660 {"mabi", required_argument, NULL, OPTION_MABI},
71060565
JW		 2661 {"mrelax", no_argument, NULL, OPTION_RELAX},
2662 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2dc8dd17
JW		 2663 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
2664 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
2ca89224
NC		 2665 {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
2666 {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
8f595e9b
NC		 2667 {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
2668 {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
e23eba97
NC		 2669
2670 {NULL, no_argument, NULL, 0}
2671};
2672size_t md_longopts_size = sizeof (md_longopts);
2673
e23eba97
NC		 2674int
2675md_parse_option (int c, const char *arg)
2676{
2677 switch (c)
2678 {
e23eba97 2679 case OPTION_MARCH:
8f595e9b
NC		 2680 /* riscv_after_parse_args will call riscv_set_arch to parse
2681 the architecture. */
2682 default_arch_with_ext = arg;
e23eba97
NC		 2683 break;
2684
2685 case OPTION_NO_PIC:
2686 riscv_opts.pic = FALSE;
2687 break;
2688
2689 case OPTION_PIC:
2690 riscv_opts.pic = TRUE;
2691 break;
2692
2922d21d
AW		 2693 case OPTION_MABI:
2694 if (strcmp (arg, "ilp32") == 0)
7f999549
JW		 2695 riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
2696 else if (strcmp (arg, "ilp32e") == 0)
2697 riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
2922d21d 2698 else if (strcmp (arg, "ilp32f") == 0)
7f999549 2699 riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2700 else if (strcmp (arg, "ilp32d") == 0)
7f999549 2701 riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2702 else if (strcmp (arg, "ilp32q") == 0)
7f999549 2703 riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
2922d21d 2704 else if (strcmp (arg, "lp64") == 0)
7f999549 2705 riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
2922d21d 2706 else if (strcmp (arg, "lp64f") == 0)
7f999549 2707 riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2708 else if (strcmp (arg, "lp64d") == 0)
7f999549 2709 riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2710 else if (strcmp (arg, "lp64q") == 0)
7f999549 2711 riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
2922d21d
AW		 2712 else
2713 return 0;
6e1605e4 2714 explicit_mabi = TRUE;
2922d21d
AW		 2715 break;
2716
71060565
JW		 2717 case OPTION_RELAX:
2718 riscv_opts.relax = TRUE;
2719 break;
2720
2721 case OPTION_NO_RELAX:
2722 riscv_opts.relax = FALSE;
2723 break;
2724
2dc8dd17
JW		 2725 case OPTION_ARCH_ATTR:
2726 riscv_opts.arch_attr = TRUE;
2727 break;
2728
2729 case OPTION_NO_ARCH_ATTR:
2730 riscv_opts.arch_attr = FALSE;
2731 break;
2732
2ca89224
NC		 2733 case OPTION_CSR_CHECK:
2734 riscv_opts.csr_check = TRUE;
2735 break;
2736
2737 case OPTION_NO_CSR_CHECK:
2738 riscv_opts.csr_check = FALSE;
2739 break;
2740
8f595e9b
NC		 2741 case OPTION_MISA_SPEC:
2742 return riscv_set_default_isa_spec (arg);
2743
2744 case OPTION_MPRIV_SPEC:
2745 return riscv_set_default_priv_spec (arg);
2746
e23eba97
NC		 2747 default:
2748 return 0;
2749 }
2750
2751 return 1;
2752}
2753
2754void
2755riscv_after_parse_args (void)
2756{
8f595e9b
NC		 2757 /* The --with-arch is optional for now, so we have to set the xlen
2758 according to the default_arch, which is set by the --targte, first.
2759 Then, we use the xlen to set the default_arch_with_ext if the
2760 -march and --with-arch are not set. */
e23eba97
NC		 2761 if (xlen == 0)
2762 {
2763 if (strcmp (default_arch, "riscv32") == 0)
2764 xlen = 32;
2765 else if (strcmp (default_arch, "riscv64") == 0)
2766 xlen = 64;
2767 else
2768 as_bad ("unknown default architecture `%s'", default_arch);
2769 }
8f595e9b
NC		 2770 if (default_arch_with_ext == NULL)
2771 default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
2772
2773 /* Initialize the hash table for extensions with default version. */
2774 ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
2775
2776 /* If the -misa-spec isn't set, then we set the default ISA spec according
2777 to DEFAULT_RISCV_ISA_SPEC. */
2778 if (default_isa_spec == ISA_SPEC_CLASS_NONE)
2779 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
2922d21d 2780
8f595e9b
NC		 2781 /* Set the architecture according to -march or or --with-arch. */
2782 riscv_set_arch (default_arch_with_ext);
2922d21d
AW		 2783
2784 /* Add the RVC extension, regardless of -march, to support .option rvc. */
fecb9c46 2785 riscv_set_rvc (FALSE);
1080bf78 2786 if (riscv_subset_supports ("c"))
2922d21d 2787 riscv_set_rvc (TRUE);
2922d21d 2788
7f999549
JW		 2789 /* Enable RVE if specified by the -march option. */
2790 riscv_set_rve (FALSE);
1080bf78 2791 if (riscv_subset_supports ("e"))
7f999549
JW		 2792 riscv_set_rve (TRUE);
2793
8f595e9b
NC		 2794 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2795 according to DEFAULT_PRIV_SPEC. */
2796 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
2797 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
2798
0ac2b354
AB		 2799 /* If the CIE to be produced has not been overridden on the command line,
2800 then produce version 3 by default. This allows us to use the full
2801 range of registers in a .cfi_return_column directive. */
2802 if (flag_dwarf_cie_version == -1)
2803 flag_dwarf_cie_version = 3;
e23eba97
NC		 2804}
2805
2806long
2807md_pcrel_from (fixS *fixP)
2808{
2809 return fixP->fx_where + fixP->fx_frag->fr_address;
2810}
2811
2812/* Apply a fixup to the object file. */
2813
2814void
2815md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2816{
45f76423 2817 unsigned int subtype;
e23eba97 2818 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
45f76423 2819 bfd_boolean relaxable = FALSE;
c1b465c9 2820 offsetT loc;
a6cbf936 2821 segT sub_segment;
e23eba97
NC		 2822
2823 /* Remember value for tc_gen_reloc. */
2824 fixP->fx_addnumber = *valP;
2825
2826 switch (fixP->fx_r_type)
2827 {
e23eba97
NC		 2828 case BFD_RELOC_RISCV_HI20:
2829 case BFD_RELOC_RISCV_LO12_I:
2830 case BFD_RELOC_RISCV_LO12_S:
45f76423
AW		 2831 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2832 | bfd_getl32 (buf), buf);
a5ec5e3f
AW		 2833 if (fixP->fx_addsy == NULL)
2834 fixP->fx_done = TRUE;
45f76423
AW		 2835 relaxable = TRUE;
2836 break;
2837
2838 case BFD_RELOC_RISCV_GOT_HI20:
e23eba97
NC		 2839 case BFD_RELOC_RISCV_ADD8:
2840 case BFD_RELOC_RISCV_ADD16:
2841 case BFD_RELOC_RISCV_ADD32:
2842 case BFD_RELOC_RISCV_ADD64:
45f76423 2843 case BFD_RELOC_RISCV_SUB6:
e23eba97
NC		 2844 case BFD_RELOC_RISCV_SUB8:
2845 case BFD_RELOC_RISCV_SUB16:
2846 case BFD_RELOC_RISCV_SUB32:
2847 case BFD_RELOC_RISCV_SUB64:
45f76423
AW		 2848 case BFD_RELOC_RISCV_RELAX:
2849 break;
2850
2851 case BFD_RELOC_RISCV_TPREL_HI20:
2852 case BFD_RELOC_RISCV_TPREL_LO12_I:
2853 case BFD_RELOC_RISCV_TPREL_LO12_S:
2854 case BFD_RELOC_RISCV_TPREL_ADD:
2855 relaxable = TRUE;
2856 /* Fall through. */
2857
2858 case BFD_RELOC_RISCV_TLS_GOT_HI20:
2859 case BFD_RELOC_RISCV_TLS_GD_HI20:
2860 case BFD_RELOC_RISCV_TLS_DTPREL32:
2861 case BFD_RELOC_RISCV_TLS_DTPREL64:
e294484e
AW		 2862 if (fixP->fx_addsy != NULL)
2863 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2864 else
2865 as_bad_where (fixP->fx_file, fixP->fx_line,
2866 _("TLS relocation against a constant"));
e23eba97
NC		 2867 break;
2868
e23eba97 2869 case BFD_RELOC_32:
a6cbf936
KLC		 2870 /* Use pc-relative relocation for FDE initial location.
2871 The symbol address in .eh_frame may be adjusted in
2872 _bfd_elf_discard_section_eh_frame, and the content of
2873 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2874 Therefore, we cannot insert a relocation whose addend symbol is
2875 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2876 if (fixP->fx_addsy && fixP->fx_subsy
2877 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
2878 && strcmp (sub_segment->name, ".eh_frame") == 0
2879 && S_GET_VALUE (fixP->fx_subsy)
2880 == fixP->fx_frag->fr_address + fixP->fx_where)
2881 {
2882 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
2883 fixP->fx_subsy = NULL;
2884 break;
2885 }
2886 /* Fall through. */
2887 case BFD_RELOC_64:
e23eba97
NC		 2888 case BFD_RELOC_16:
2889 case BFD_RELOC_8:
45f76423 2890 case BFD_RELOC_RISCV_CFA:
e23eba97
NC		 2891 if (fixP->fx_addsy && fixP->fx_subsy)
2892 {
2893 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2894 fixP->fx_next->fx_addsy = fixP->fx_subsy;
2895 fixP->fx_next->fx_subsy = NULL;
2896 fixP->fx_next->fx_offset = 0;
2897 fixP->fx_subsy = NULL;
2898
2899 switch (fixP->fx_r_type)
2900 {
2901 case BFD_RELOC_64:
2902 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
2903 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
2904 break;
2905
2906 case BFD_RELOC_32:
2907 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
2908 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2909 break;
2910
2911 case BFD_RELOC_16:
2912 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
2913 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2914 break;
2915
2916 case BFD_RELOC_8:
2917 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
2918 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
073808ed 2919 break;
e23eba97 2920
45f76423
AW		 2921 case BFD_RELOC_RISCV_CFA:
2922 /* Load the byte to get the subtype. */
c1b465c9
KLC		 2923 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
2924 loc = fixP->fx_frag->fr_fix - (subtype & 7);
45f76423
AW		 2925 switch (subtype)
2926 {
2927 case DW_CFA_advance_loc1:
c1b465c9
KLC		 2928 fixP->fx_where = loc + 1;
2929 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2930 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
2931 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
2932 break;
2933
2934 case DW_CFA_advance_loc2:
2935 fixP->fx_size = 2;
45f76423 2936 fixP->fx_next->fx_size = 2;
c1b465c9
KLC		 2937 fixP->fx_where = loc + 1;
2938 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2939 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
2940 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2941 break;
2942
2943 case DW_CFA_advance_loc4:
2944 fixP->fx_size = 4;
45f76423 2945 fixP->fx_next->fx_size = 4;
c1b465c9
KLC		 2946 fixP->fx_where = loc;
2947 fixP->fx_next->fx_where = loc;
45f76423
AW		 2948 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
2949 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2950 break;
2951
2952 default:
2953 if (subtype < 0x80 && (subtype & 0x40))
2954 {
2955 /* DW_CFA_advance_loc */
2aece2ba
KLC		 2956 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
2957 fixP->fx_next->fx_frag = fixP->fx_frag;
45f76423
AW		 2958 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
2959 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
2960 }
2961 else
2962 as_fatal (_("internal error: bad CFA value #%d"), subtype);
2963 break;
2964 }
2965 break;
2966
e23eba97
NC		 2967 default:
2968 /* This case is unreachable. */
2969 abort ();
2970 }
2971 }
2972 /* Fall through. */
2973
2974 case BFD_RELOC_RVA:
2975 /* If we are deleting this reloc entry, we must fill in the
2976 value now. This can happen if we have a .word which is not
2977 resolved when it appears but is later defined. */
2978 if (fixP->fx_addsy == NULL)
2979 {
2980 gas_assert (fixP->fx_size <= sizeof (valueT));
2981 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
2982 fixP->fx_done = 1;
2983 }
2984 break;
2985
2986 case BFD_RELOC_RISCV_JMP:
2987 if (fixP->fx_addsy)
2988 {
2989 /* Fill in a tentative value to improve objdump readability. */
2990 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2991 bfd_vma delta = target - md_pcrel_from (fixP);
2992 bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
2993 }
2994 break;
2995
2996 case BFD_RELOC_12_PCREL:
2997 if (fixP->fx_addsy)
2998 {
2999 /* Fill in a tentative value to improve objdump readability. */
3000 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3001 bfd_vma delta = target - md_pcrel_from (fixP);
3002 bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
3003 }
3004 break;
3005
3006 case BFD_RELOC_RISCV_RVC_BRANCH:
3007 if (fixP->fx_addsy)
3008 {
3009 /* Fill in a tentative value to improve objdump readability. */
3010 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3011 bfd_vma delta = target - md_pcrel_from (fixP);
3012 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
3013 }
3014 break;
3015
3016 case BFD_RELOC_RISCV_RVC_JUMP:
3017 if (fixP->fx_addsy)
3018 {
3019 /* Fill in a tentative value to improve objdump readability. */
3020 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3021 bfd_vma delta = target - md_pcrel_from (fixP);
3022 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
3023 }
3024 break;
3025
e23eba97
NC		 3026 case BFD_RELOC_RISCV_CALL:
3027 case BFD_RELOC_RISCV_CALL_PLT:
45f76423
AW		 3028 relaxable = TRUE;
3029 break;
3030
9d06997a 3031 case BFD_RELOC_RISCV_PCREL_HI20:
45f76423
AW		 3032 case BFD_RELOC_RISCV_PCREL_LO12_S:
3033 case BFD_RELOC_RISCV_PCREL_LO12_I:
9d06997a
PD		 3034 relaxable = riscv_opts.relax;
3035 break;
3036
e23eba97
NC		 3037 case BFD_RELOC_RISCV_ALIGN:
3038 break;
3039
3040 default:
3041 /* We ignore generic BFD relocations we don't know about. */
3042 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
3043 as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type);
3044 }
45f76423 3045
e294484e
AW		 3046 if (fixP->fx_subsy != NULL)
3047 as_bad_where (fixP->fx_file, fixP->fx_line,
3048 _("unsupported symbol subtraction"));
3049
45f76423
AW		 3050 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3051 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
3052 {
3053 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3054 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
3055 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
b1b11e92 3056 fixP->fx_next->fx_size = 0;
45f76423
AW		 3057 }
3058}
3059
3060/* Because the value of .cfi_remember_state may changed after relaxation,
3061 we insert a fix to relocate it again in link-time. */
3062
3063void
3064riscv_pre_output_hook (void)
3065{
3066 const frchainS *frch;
72393fd1
JW		 3067 segT s;
3068
3069 /* Save the current segment info. */
3070 segT seg = now_seg;
3071 subsegT subseg = now_subseg;
45f76423
AW		 3072
3073 for (s = stdoutput->sections; s; s = s->next)
3074 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
3075 {
7cb7b948 3076 fragS *frag;
45f76423
AW		 3077
3078 for (frag = frch->frch_root; frag; frag = frag->fr_next)
3079 {
3080 if (frag->fr_type == rs_cfa)
3081 {
45f76423 3082 expressionS exp;
8d1015a8 3083 expressionS *symval;
45f76423 3084
8d1015a8 3085 symval = symbol_get_value_expression (frag->fr_symbol);
45f76423 3086 exp.X_op = O_subtract;
8d1015a8 3087 exp.X_add_symbol = symval->X_add_symbol;
45f76423 3088 exp.X_add_number = 0;
8d1015a8 3089 exp.X_op_symbol = symval->X_op_symbol;
45f76423 3090
72393fd1
JW		 3091 /* We must set the segment before creating a frag after all
3092 frag chains have been chained together. */
3093 subseg_set (s, frch->frch_subseg);
3094
c1b465c9 3095 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
45f76423
AW		 3096 BFD_RELOC_RISCV_CFA);
3097 }
3098 }
3099 }
72393fd1
JW		 3100
3101 /* Restore the original segment info. */
3102 subseg_set (seg, subseg);
e23eba97
NC		 3103}
3104
45f76423 3105
e23eba97
NC		 3106/* This structure is used to hold a stack of .option values. */
3107
3108struct riscv_option_stack
3109{
3110 struct riscv_option_stack *next;
3111 struct riscv_set_options options;
3112};
3113
3114static struct riscv_option_stack *riscv_opts_stack;
3115
3116/* Handle the .option pseudo-op. */
3117
3118static void
3119s_riscv_option (int x ATTRIBUTE_UNUSED)
3120{
3121 char *name = input_line_pointer, ch;
3122
3123 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3124 ++input_line_pointer;
3125 ch = *input_line_pointer;
3126 *input_line_pointer = '\0';
3127
3128 if (strcmp (name, "rvc") == 0)
3129 riscv_set_rvc (TRUE);
3130 else if (strcmp (name, "norvc") == 0)
3131 riscv_set_rvc (FALSE);
3132 else if (strcmp (name, "pic") == 0)
3133 riscv_opts.pic = TRUE;
3134 else if (strcmp (name, "nopic") == 0)
3135 riscv_opts.pic = FALSE;
45f76423
AW		 3136 else if (strcmp (name, "relax") == 0)
3137 riscv_opts.relax = TRUE;
3138 else if (strcmp (name, "norelax") == 0)
3139 riscv_opts.relax = FALSE;
2ca89224
NC		 3140 else if (strcmp (name, "csr-check") == 0)
3141 riscv_opts.csr_check = TRUE;
3142 else if (strcmp (name, "no-csr-check") == 0)
3143 riscv_opts.csr_check = FALSE;
e23eba97
NC		 3144 else if (strcmp (name, "push") == 0)
3145 {
3146 struct riscv_option_stack *s;
3147
3148 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
3149 s->next = riscv_opts_stack;
3150 s->options = riscv_opts;
3151 riscv_opts_stack = s;
3152 }
3153 else if (strcmp (name, "pop") == 0)
3154 {
3155 struct riscv_option_stack *s;
3156
3157 s = riscv_opts_stack;
3158 if (s == NULL)
3159 as_bad (_(".option pop with no .option push"));
3160 else
3161 {
3162 riscv_opts = s->options;
3163 riscv_opts_stack = s->next;
3164 free (s);
3165 }
3166 }
3167 else
3168 {
3169 as_warn (_("Unrecognized .option directive: %s\n"), name);
3170 }
3171 *input_line_pointer = ch;
3172 demand_empty_rest_of_line ();
3173}
3174
3175/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3176 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3177 use in DWARF debug information. */
3178
3179static void
3180s_dtprel (int bytes)
3181{
3182 expressionS ex;
3183 char *p;
3184
3185 expression (&ex);
3186
3187 if (ex.X_op != O_symbol)
3188 {
3189 as_bad (_("Unsupported use of %s"), (bytes == 8
3190 ? ".dtpreldword"
3191 : ".dtprelword"));
3192 ignore_rest_of_line ();
3193 }
3194
3195 p = frag_more (bytes);
3196 md_number_to_chars (p, 0, bytes);
3197 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
3198 (bytes == 8
3199 ? BFD_RELOC_RISCV_TLS_DTPREL64
3200 : BFD_RELOC_RISCV_TLS_DTPREL32));
3201
3202 demand_empty_rest_of_line ();
3203}
3204
3205/* Handle the .bss pseudo-op. */
3206
3207static void
3208s_bss (int ignore ATTRIBUTE_UNUSED)
3209{
3210 subseg_set (bss_section, 0);
3211 demand_empty_rest_of_line ();
3212}
3213
e23eba97 3214static void
d115ab8e 3215riscv_make_nops (char *buf, bfd_vma bytes)
e23eba97 3216{
d115ab8e 3217 bfd_vma i = 0;
e23eba97 3218
e5b737de
AW		 3219 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3220 means we are not within a valid instruction sequence. It is thus safe
3221 to use a zero byte, even though that is not a valid instruction. */
3222 if (bytes % 2 == 1)
3223 buf[i++] = 0;
3224
3225 /* Use at most one 2-byte NOP. */
3226 if ((bytes - i) % 4 == 2)
e23eba97 3227 {
e5b737de 3228 md_number_to_chars (buf + i, RVC_NOP, 2);
d115ab8e 3229 i += 2;
e23eba97
NC		 3230 }
3231
e5b737de 3232 /* Fill the remainder with 4-byte NOPs. */
d115ab8e
AW		 3233 for ( ; i < bytes; i += 4)
3234 md_number_to_chars (buf + i, RISCV_NOP, 4);
3235}
e23eba97 3236
d115ab8e
AW		 3237/* Called from md_do_align. Used to create an alignment frag in a
3238 code section by emitting a worst-case NOP sequence that the linker
3239 will later relax to the correct number of NOPs. We can't compute
3240 the correct alignment now because of other linker relaxations. */
3241
3242bfd_boolean
3243riscv_frag_align_code (int n)
3244{
e5b737de 3245 bfd_vma bytes = (bfd_vma) 1 << n;
36877bfb
JW		 3246 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
3247 bfd_vma worst_case_bytes = bytes - insn_alignment;
3248 char *nops;
ed0816bd 3249 expressionS ex;
d115ab8e 3250
36877bfb
JW		 3251 /* If we are moving to a smaller alignment than the instruction size, then no
3252 alignment is required. */
3253 if (bytes <= insn_alignment)
3254 return TRUE;
3255
d115ab8e
AW		 3256 /* When not relaxing, riscv_handle_align handles code alignment. */
3257 if (!riscv_opts.relax)
3258 return FALSE;
e23eba97 3259
e80ae190
JW		 3260 nops = frag_more (worst_case_bytes);
3261
ed0816bd
PD		 3262 ex.X_op = O_constant;
3263 ex.X_add_number = worst_case_bytes;
d115ab8e 3264
ed0816bd 3265 riscv_make_nops (nops, worst_case_bytes);
e23eba97 3266
ed0816bd
PD		 3267 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
3268 &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
e23eba97 3269
d115ab8e
AW		 3270 return TRUE;
3271}
e23eba97 3272
d115ab8e
AW		 3273/* Implement HANDLE_ALIGN. */
3274
3275void
3276riscv_handle_align (fragS *fragP)
3277{
3278 switch (fragP->fr_type)
3279 {
3280 case rs_align_code:
3281 /* When relaxing, riscv_frag_align_code handles code alignment. */
3282 if (!riscv_opts.relax)
3283 {
e80ae190
JW		 3284 bfd_signed_vma bytes = (fragP->fr_next->fr_address
3285 - fragP->fr_address - fragP->fr_fix);
3286 /* We have 4 byte uncompressed nops. */
3287 bfd_signed_vma size = 4;
3288 bfd_signed_vma excess = bytes % size;
3289 char *p = fragP->fr_literal + fragP->fr_fix;
3290
3291 if (bytes <= 0)
d115ab8e
AW		 3292 break;
3293
e80ae190
JW		 3294 /* Insert zeros or compressed nops to get 4 byte alignment. */
3295 if (excess)
3296 {
3297 riscv_make_nops (p, excess);
3298 fragP->fr_fix += excess;
3299 p += excess;
3300 }
3301
3302 /* Insert variable number of 4 byte uncompressed nops. */
3303 riscv_make_nops (p, size);
3304 fragP->fr_var = size;
d115ab8e
AW		 3305 }
3306 break;
3307
3308 default:
3309 break;
3310 }
e23eba97
NC		 3311}
3312
3313int
3314md_estimate_size_before_relax (fragS *fragp, asection *segtype)
3315{
3316 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
3317}
3318
3319/* Translate internal representation of relocation info to BFD target
3320 format. */
3321
3322arelent *
3323tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3324{
3325 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
3326
3327 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3328 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3329 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3330 reloc->addend = fixp->fx_addnumber;
3331
3332 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3333 if (reloc->howto == NULL)
3334 {
3335 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
3336 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
3337 {
3338 /* We don't have R_RISCV_8/16, but for this special case,
3339 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3340 return reloc;
3341 }
3342
3343 as_bad_where (fixp->fx_file, fixp->fx_line,
3344 _("cannot represent %s relocation in object file"),
3345 bfd_get_reloc_code_name (fixp->fx_r_type));
3346 return NULL;
3347 }
3348
3349 return reloc;
3350}
3351
3352int
3353riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
3354{
3355 if (RELAX_BRANCH_P (fragp->fr_subtype))
3356 {
3357 offsetT old_var = fragp->fr_var;
3358 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
3359 return fragp->fr_var - old_var;
3360 }
3361
3362 return 0;
3363}
3364
3365/* Expand far branches to multi-instruction sequences. */
3366
3367static void
3368md_convert_frag_branch (fragS *fragp)
3369{
3370 bfd_byte *buf;
3371 expressionS exp;
3372 fixS *fixp;
3373 insn_t insn;
3374 int rs1, reloc;
3375
3376 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
3377
3378 exp.X_op = O_symbol;
3379 exp.X_add_symbol = fragp->fr_symbol;
3380 exp.X_add_number = fragp->fr_offset;
3381
3382 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
3383
3384 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
3385 {
3386 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3387 {
3388 case 8:
3389 case 4:
3390 /* Expand the RVC branch into a RISC-V one. */
3391 insn = bfd_getl16 (buf);
3392 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
3393 if ((insn & MASK_C_J) == MATCH_C_J)
3394 insn = MATCH_JAL;
3395 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
3396 insn = MATCH_JAL | (X_RA << OP_SH_RD);
3397 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
3398 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
3399 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
3400 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
3401 else
3402 abort ();
3403 bfd_putl32 (insn, buf);
3404 break;
3405
3406 case 6:
3407 /* Invert the branch condition. Branch over the jump. */
3408 insn = bfd_getl16 (buf);
3409 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
3410 insn |= ENCODE_RVC_B_IMM (6);
3411 bfd_putl16 (insn, buf);
3412 buf += 2;
3413 goto jump;
3414
3415 case 2:
3416 /* Just keep the RVC branch. */
3417 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3418 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
3419 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3420 2, &exp, FALSE, reloc);
3421 buf += 2;
3422 goto done;
3423
3424 default:
1d65abb5 3425 abort ();
e23eba97
NC		 3426 }
3427 }
3428
3429 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3430 {
3431 case 8:
3432 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
3433
3434 /* Invert the branch condition. Branch over the jump. */
3435 insn = bfd_getl32 (buf);
3436 insn ^= MATCH_BEQ ^ MATCH_BNE;
3437 insn |= ENCODE_SBTYPE_IMM (8);
3438 md_number_to_chars ((char *) buf, insn, 4);
3439 buf += 4;
3440
dc1e8a47 3441 jump:
e23eba97
NC		 3442 /* Jump to the target. */
3443 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3444 4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
3445 md_number_to_chars ((char *) buf, MATCH_JAL, 4);
3446 buf += 4;
3447 break;
3448
3449 case 4:
3450 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3451 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
3452 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3453 4, &exp, FALSE, reloc);
3454 buf += 4;
3455 break;
3456
3457 default:
3458 abort ();
3459 }
3460
dc1e8a47 3461 done:
e23eba97
NC		 3462 fixp->fx_file = fragp->fr_file;
3463 fixp->fx_line = fragp->fr_line;
3464
3465 gas_assert (buf == (bfd_byte *)fragp->fr_literal
3466 + fragp->fr_fix + fragp->fr_var);
3467
3468 fragp->fr_fix += fragp->fr_var;
3469}
3470
3471/* Relax a machine dependent frag. This returns the amount by which
3472 the current size of the frag should change. */
3473
3474void
3475md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3476 fragS *fragp)
3477{
3478 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
3479 md_convert_frag_branch (fragp);
3480}
3481
3482void
3483md_show_usage (FILE *stream)
3484{
3485 fprintf (stream, _("\
3486RISC-V options:\n\
8f595e9b
NC		 3487 -fpic generate position-independent code\n\
3488 -fno-pic don't generate position-independent code (default)\n\
3489 -march=ISA set the RISC-V architecture\n\
3490 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3491 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3492 -mabi=ABI set the RISC-V ABI\n\
3493 -mrelax enable relax (default)\n\
3494 -mno-relax disable relax\n\
3495 -march-attr generate RISC-V arch attribute\n\
3496 -mno-arch-attr don't generate RISC-V arch attribute\n\
e23eba97
NC		 3497"));
3498}
3499
3500/* Standard calling conventions leave the CFA at SP on entry. */
3501void
3502riscv_cfi_frame_initial_instructions (void)
3503{
3504 cfi_add_CFA_def_cfa_register (X_SP);
3505}
3506
3507int
3508tc_riscv_regname_to_dw2regnum (char *regname)
3509{
3510 int reg;
3511
3512 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3513 return reg;
3514
3515 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3516 return reg + 32;
3517
4762fe62
AB		 3518 /* CSRs are numbered 4096 -> 8191. */
3519 if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
3520 return reg + 4096;
3521
e23eba97
NC		 3522 as_bad (_("unknown register `%s'"), regname);
3523 return -1;
3524}
3525
3526void
3527riscv_elf_final_processing (void)
3528{
6e1605e4 3529 riscv_set_abi_by_arch ();
e23eba97 3530 elf_elfheader (stdoutput)->e_flags |= elf_flags;
e23eba97
NC		 3531}
3532
3533/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3534 since these directives break relaxation when used with symbol deltas. */
3535
3536static void
3537s_riscv_leb128 (int sign)
3538{
3539 expressionS exp;
3540 char *save_in = input_line_pointer;
3541
3542 expression (&exp);
3543 if (exp.X_op != O_constant)
3544 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3545 demand_empty_rest_of_line ();
3546
3547 input_line_pointer = save_in;
3548 return s_leb128 (sign);
3549}
3550
0e35537d
JW		 3551/* Parse the .insn directive. */
3552
3553static void
3554s_riscv_insn (int x ATTRIBUTE_UNUSED)
3555{
3556 char *str = input_line_pointer;
3557 struct riscv_cl_insn insn;
3558 expressionS imm_expr;
3559 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3560 char save_c;
3561
3562 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3563 ++input_line_pointer;
3564
3565 save_c = *input_line_pointer;
3566 *input_line_pointer = '\0';
3567
3568 const char *error = riscv_ip (str, &insn, &imm_expr,
3569 &imm_reloc, insn_type_hash);
3570
3571 if (error)
3572 {
3573 as_bad ("%s `%s'", error, str);
3574 }
3575 else
3576 {
3577 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3578 append_insn (&insn, &imm_expr, imm_reloc);
3579 }
3580
3581 *input_line_pointer = save_c;
3582 demand_empty_rest_of_line ();
3583}
3584
8f595e9b
NC		 3585/* Update arch and priv attributes. If we don't set the corresponding ELF
3586 attributes, then try to output the default ones. */
2dc8dd17
JW		 3587
3588static void
8f595e9b 3589riscv_write_out_attrs (void)
2dc8dd17 3590{
8f595e9b
NC		 3591 const char *arch_str, *priv_str, *p;
3592 /* versions[0] is major, versions[1] is minor,
3593 and versions[3] is revision. */
3594 unsigned versions[3] = {0}, number = 0;
3595 unsigned int i;
2dc8dd17 3596
8f595e9b
NC		 3597 /* Re-write arch attribute to normalize the arch string. */
3598 arch_str = riscv_arch_str (xlen, &riscv_subsets);
2dc8dd17 3599 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
2dc8dd17 3600 xfree ((void *)arch_str);
8f595e9b
NC		 3601
3602 /* For the file without any instruction, we don't set the default_priv_spec
3603 according to the priv attributes since the md_assemble isn't called.
3604 Call riscv_set_default_priv_spec here for the above case, although
3605 it seems strange. */
3606 if (!start_assemble
3607 && !riscv_set_default_priv_spec (NULL))
3608 return;
3609
1a79004f
NC		 3610 /* If we already have set elf priv attributes, then no need to do anything,
3611 assembler will generate them according to what you set. Otherwise, don't
3612 generate or update them when no CSR and priv instructions are used.
3613 Generate the priv attributes according to default_priv_spec, which can be
3614 set by -mpriv-spec and --with-priv-spec, and be updated by the original
3615 priv attribute sets. */
3616 if (!explicit_priv_attr)
3fc6c3dc
NC		 3617 return;
3618
8f595e9b
NC		 3619 /* Re-write priv attributes by default_priv_spec. */
3620 priv_str = riscv_get_priv_spec_name (default_priv_spec);
3621 p = priv_str;
3622 for (i = 0; *p; ++p)
3623 {
3624 if (*p == '.' && i < 3)
3625 {
3626 versions[i++] = number;
3627 number = 0;
3628 }
3629 else if (ISDIGIT (*p))
3630 number = (number * 10) + (*p - '0');
3631 else
3632 {
3633 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str);
3634 return;
3635 }
3636 }
3637 versions[i] = number;
3638
3639 /* Set the priv attributes. */
3640 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
3641 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
3642 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
2dc8dd17
JW		 3643}
3644
8f595e9b
NC		 3645/* Add the default contents for the .riscv.attributes section. If any
3646 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3647 to update the arch and priv attributes. */
2dc8dd17
JW		 3648
3649static void
3650riscv_set_public_attributes (void)
3651{
8f595e9b
NC		 3652 if (riscv_opts.arch_attr || explicit_attr)
3653 riscv_write_out_attrs ();
2dc8dd17
JW		 3654}
3655
3656/* Called after all assembly has been done. */
3657
3658void
3659riscv_md_end (void)
3660{
3661 riscv_set_public_attributes ();
3662}
3663
3664/* Given a symbolic attribute NAME, return the proper integer value.
3665 Returns -1 if the attribute is not known. */
3666
3667int
3668riscv_convert_symbolic_attribute (const char *name)
3669{
3670 static const struct
3671 {
3672 const char * name;
3673 const int tag;
3674 }
3675 attribute_table[] =
3676 {
3677 /* When you modify this table you should
3678 also modify the list in doc/c-riscv.texi. */
3679#define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3680 T(arch),
3681 T(priv_spec),
3682 T(priv_spec_minor),
3683 T(priv_spec_revision),
3684 T(unaligned_access),
3685 T(stack_align),
3686#undef T
3687 };
3688
3689 unsigned int i;
3690
3691 if (name == NULL)
3692 return -1;
3693
3694 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
3695 if (strcmp (name, attribute_table[i].name) == 0)
3696 return attribute_table[i].tag;
3697
3698 return -1;
3699}
3700
3701/* Parse a .attribute directive. */
3702
3703static void
3704s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
3705{
3706 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
8f595e9b
NC		 3707 unsigned old_xlen;
3708 obj_attribute *attr;
2dc8dd17 3709
8f595e9b
NC		 3710 explicit_attr = TRUE;
3711 switch (tag)
2dc8dd17 3712 {
8f595e9b
NC		 3713 case Tag_RISCV_arch:
3714 old_xlen = xlen;
2dc8dd17
JW		 3715 attr = elf_known_obj_attributes_proc (stdoutput);
3716 if (!start_assemble)
3717 riscv_set_arch (attr[Tag_RISCV_arch].s);
3718 else
3719 as_fatal (_(".attribute arch must set before any instructions"));
3720
3721 if (old_xlen != xlen)
3722 {
3723 /* We must re-init bfd again if xlen is changed. */
3724 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
3725 bfd_find_target (riscv_target_format (), stdoutput);
3726
3727 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
3728 as_warn (_("Could not set architecture and machine"));
3729 }
8f595e9b
NC		 3730 break;
3731
3732 case Tag_RISCV_priv_spec:
3733 case Tag_RISCV_priv_spec_minor:
3734 case Tag_RISCV_priv_spec_revision:
3735 if (start_assemble)
3736 as_fatal (_(".attribute priv spec must set before any instructions"));
3737 break;
3738
3739 default:
3740 break;
2dc8dd17
JW		 3741 }
3742}
3743
e23eba97
NC		 3744/* Pseudo-op table. */
3745
3746static const pseudo_typeS riscv_pseudo_table[] =
3747{
3748 /* RISC-V-specific pseudo-ops. */
3749 {"option", s_riscv_option, 0},
3750 {"half", cons, 2},
3751 {"word", cons, 4},
3752 {"dword", cons, 8},
3753 {"dtprelword", s_dtprel, 4},
3754 {"dtpreldword", s_dtprel, 8},
3755 {"bss", s_bss, 0},
e23eba97
NC		 3756 {"uleb128", s_riscv_leb128, 0},
3757 {"sleb128", s_riscv_leb128, 1},
0e35537d 3758 {"insn", s_riscv_insn, 0},
2dc8dd17 3759 {"attribute", s_riscv_attribute, 0},
e23eba97
NC		 3760
3761 { NULL, NULL, 0 },
3762};
3763
3764void
3765riscv_pop_insert (void)
3766{
3767 extern void pop_insert (const pseudo_typeS *);
3768
3769 pop_insert (riscv_pseudo_table);
3770}
GDB Binutils - Deliverables
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