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amd64-linux-siginfo.c: Adjust include order to avoid gnulib error
[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
CommitLineData
e23eba97 1/* tc-riscv.c -- RISC-V assembler
250d07de 2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
3d73d29e 32#include "bfd/cpu-riscv.h"
1080bf78 33#include "bfd/elfxx-riscv.h"
e23eba97
NC		 34#include "elf/riscv.h"
35#include "opcode/riscv.h"
36
37#include <stdint.h>
38
39/* Information about an instruction, including its format, operands
40 and fixups. */
41struct riscv_cl_insn
42{
43 /* The opcode's entry in riscv_opcodes. */
44 const struct riscv_opcode *insn_mo;
45
46 /* The encoded instruction bits. */
47 insn_t insn_opcode;
48
49 /* The frag that contains the instruction. */
50 struct frag *frag;
51
52 /* The offset into FRAG of the first instruction byte. */
53 long where;
54
55 /* The relocs associated with the instruction, if any. */
56 fixS *fixp;
57};
58
3d73d29e
NC		 59/* All RISC-V CSR belong to one of these classes. */
60enum riscv_csr_class
61{
62 CSR_CLASS_NONE,
63
64 CSR_CLASS_I,
65 CSR_CLASS_I_32, /* rv32 only */
66 CSR_CLASS_F, /* f-ext only */
67 CSR_CLASS_DEBUG /* debug CSR */
68};
69
70/* This structure holds all restricted conditions for a CSR. */
71struct riscv_csr_extra
72{
73 /* Class to which this CSR belongs. Used to decide whether or
74 not this CSR is legal in the current -march context. */
75 enum riscv_csr_class csr_class;
76
77 /* CSR may have differnet numbers in the previous priv spec. */
78 unsigned address;
79
80 /* Record the CSR is defined/valid in which versions. */
81 enum riscv_spec_class define_version;
82
83 /* Record the CSR is aborted/invalid from which versions. If it isn't
84 aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
85 enum riscv_spec_class abort_version;
86
87 /* The CSR may have more than one setting. */
88 struct riscv_csr_extra *next;
89};
90
91/* All standard/Z* extensions defined in all supported ISA spec. */
92struct riscv_ext_version
93{
94 const char *name;
95 enum riscv_spec_class isa_spec_class;
96 int major_version;
97 int minor_version;
98};
99
100static const struct riscv_ext_version ext_version_table[] =
101{
102 {"e", ISA_SPEC_CLASS_20191213, 1, 9},
103 {"e", ISA_SPEC_CLASS_20190608, 1, 9},
104 {"e", ISA_SPEC_CLASS_2P2, 1, 9},
105
106 {"i", ISA_SPEC_CLASS_20191213, 2, 1},
107 {"i", ISA_SPEC_CLASS_20190608, 2, 1},
108 {"i", ISA_SPEC_CLASS_2P2, 2, 0},
109
110 {"m", ISA_SPEC_CLASS_20191213, 2, 0},
111 {"m", ISA_SPEC_CLASS_20190608, 2, 0},
112 {"m", ISA_SPEC_CLASS_2P2, 2, 0},
113
114 {"a", ISA_SPEC_CLASS_20191213, 2, 1},
115 {"a", ISA_SPEC_CLASS_20190608, 2, 0},
116 {"a", ISA_SPEC_CLASS_2P2, 2, 0},
117
118 {"f", ISA_SPEC_CLASS_20191213, 2, 2},
119 {"f", ISA_SPEC_CLASS_20190608, 2, 2},
120 {"f", ISA_SPEC_CLASS_2P2, 2, 0},
121
122 {"d", ISA_SPEC_CLASS_20191213, 2, 2},
123 {"d", ISA_SPEC_CLASS_20190608, 2, 2},
124 {"d", ISA_SPEC_CLASS_2P2, 2, 0},
125
126 {"q", ISA_SPEC_CLASS_20191213, 2, 2},
127 {"q", ISA_SPEC_CLASS_20190608, 2, 2},
128 {"q", ISA_SPEC_CLASS_2P2, 2, 0},
129
130 {"c", ISA_SPEC_CLASS_20191213, 2, 0},
131 {"c", ISA_SPEC_CLASS_20190608, 2, 0},
132 {"c", ISA_SPEC_CLASS_2P2, 2, 0},
133
134 {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
135 {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
136
137 {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
138 {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
139
140 {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
141
142 /* Terminate the list. */
143 {NULL, 0, 0, 0}
144};
145
e23eba97
NC		 146#ifndef DEFAULT_ARCH
147#define DEFAULT_ARCH "riscv64"
148#endif
149
2dc8dd17
JW		 150#ifndef DEFAULT_RISCV_ATTR
151#define DEFAULT_RISCV_ATTR 0
152#endif
153
8f595e9b 154/* Let riscv_after_parse_args set the default value according to xlen. */
8f595e9b
NC		 155#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
156#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
157#endif
158
dcd709e0 159/* Need to sync the version with RISC-V compiler. */
8f595e9b
NC		 160#ifndef DEFAULT_RISCV_ISA_SPEC
161#define DEFAULT_RISCV_ISA_SPEC "2.2"
162#endif
163
164#ifndef DEFAULT_RISCV_PRIV_SPEC
165#define DEFAULT_RISCV_PRIV_SPEC "1.11"
166#endif
167
e23eba97 168static const char default_arch[] = DEFAULT_ARCH;
8f595e9b 169static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
3d73d29e
NC		 170static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
171static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
e23eba97 172
dcd709e0
NC		 173static unsigned xlen = 0; /* The width of an x-register. */
174static unsigned abi_xlen = 0; /* The width of a pointer in the ABI. */
7f999549 175static bfd_boolean rve_abi = FALSE;
1942a048
NC		 176enum float_abi
177{
6e1605e4
NC		 178 FLOAT_ABI_DEFAULT = -1,
179 FLOAT_ABI_SOFT,
180 FLOAT_ABI_SINGLE,
181 FLOAT_ABI_DOUBLE,
182 FLOAT_ABI_QUAD
183};
184static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
e23eba97 185
2922d21d 186#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
e23eba97
NC		 187#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
188
189static unsigned elf_flags = 0;
190
dcd709e0
NC		 191/* Set the default_isa_spec. Return 0 if the spec isn't supported.
192 Otherwise, return 1. */
8f595e9b
NC		 193
194static int
195riscv_set_default_isa_spec (const char *s)
196{
3d73d29e
NC		 197 enum riscv_spec_class class = ISA_SPEC_CLASS_NONE;
198 RISCV_GET_ISA_SPEC_CLASS (s, class);
199 if (class == ISA_SPEC_CLASS_NONE)
8f595e9b 200 {
b800637e
NC		 201 as_bad ("unknown default ISA spec `%s' set by "
202 "-misa-spec or --with-isa-spec", s);
8f595e9b
NC		 203 return 0;
204 }
205 else
206 default_isa_spec = class;
207 return 1;
208}
209
dcd709e0
NC		 210/* Set the default_priv_spec. Find the privileged elf attributes when
211 the input string is NULL. Return 0 if the spec isn't supported.
212 Otherwise, return 1. */
8f595e9b
NC		 213
214static int
215riscv_set_default_priv_spec (const char *s)
216{
3d73d29e 217 enum riscv_spec_class class = PRIV_SPEC_CLASS_NONE;
8f595e9b
NC		 218 unsigned major, minor, revision;
219 obj_attribute *attr;
8f595e9b 220
3d73d29e
NC		 221 RISCV_GET_PRIV_SPEC_CLASS (s, class);
222 if (class != PRIV_SPEC_CLASS_NONE)
8f595e9b
NC		 223 {
224 default_priv_spec = class;
225 return 1;
226 }
227
228 if (s != NULL)
229 {
b800637e
NC		 230 as_bad (_("unknown default privileged spec `%s' set by "
231 "-mpriv-spec or --with-priv-spec"), s);
8f595e9b
NC		 232 return 0;
233 }
234
dcd709e0 235 /* Set the default_priv_spec by the privileged elf attributes. */
8f595e9b
NC		 236 attr = elf_known_obj_attributes_proc (stdoutput);
237 major = (unsigned) attr[Tag_RISCV_priv_spec].i;
238 minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
239 revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
3d73d29e
NC		 240 /* Version 0.0.0 is the default value and meningless. */
241 if (major == 0 && minor == 0 && revision == 0)
242 return 1;
8f595e9b 243
3d73d29e
NC		 244 riscv_get_priv_spec_class_from_numbers (major, minor, revision, &class);
245 if (class != PRIV_SPEC_CLASS_NONE)
246 {
8f595e9b 247 default_priv_spec = class;
8f595e9b
NC		 248 return 1;
249 }
250
dcd709e0 251 /* Still can not find the privileged spec class. */
b800637e
NC		 252 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
253 "privileged elf attributes"), major, minor, revision);
8f595e9b
NC		 254 return 0;
255}
256
e23eba97 257/* This is the set of options which the .option pseudo-op may modify. */
e23eba97
NC		 258struct riscv_set_options
259{
260 int pic; /* Generate position-independent code. */
261 int rvc; /* Generate RVC code. */
7f999549 262 int rve; /* Generate RVE code. */
45f76423 263 int relax; /* Emit relocs the linker is allowed to relax. */
dcd709e0 264 int arch_attr; /* Emit architecture and privileged elf attributes. */
2ca89224 265 int csr_check; /* Enable the CSR checking. */
e23eba97
NC		 266};
267
268static struct riscv_set_options riscv_opts =
269{
dcd709e0
NC		 270 0, /* pic */
271 0, /* rvc */
272 0, /* rve */
273 1, /* relax */
2dc8dd17 274 DEFAULT_RISCV_ATTR, /* arch_attr */
dcd709e0 275 0, /* csr_check */
e23eba97
NC		 276};
277
278static void
279riscv_set_rvc (bfd_boolean rvc_value)
280{
281 if (rvc_value)
282 elf_flags |= EF_RISCV_RVC;
283
284 riscv_opts.rvc = rvc_value;
285}
286
7f999549
JW		 287static void
288riscv_set_rve (bfd_boolean rve_value)
289{
290 riscv_opts.rve = rve_value;
291}
292
1080bf78 293static riscv_subset_list_t riscv_subsets;
e23eba97
NC		 294
295static bfd_boolean
1080bf78 296riscv_subset_supports (const char *feature)
e23eba97 297{
dfe92496
NC		 298 struct riscv_subset_t *subset;
299
1080bf78
JW		 300 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
301 return TRUE;
e23eba97 302
dfe92496 303 return riscv_lookup_subset (&riscv_subsets, feature, &subset);
e23eba97
NC		 304}
305
43135d3b 306static bfd_boolean
7e9ad3a3 307riscv_multi_subset_supports (enum riscv_insn_class insn_class)
43135d3b 308{
7e9ad3a3
JW		 309 switch (insn_class)
310 {
311 case INSN_CLASS_I: return riscv_subset_supports ("i");
312 case INSN_CLASS_C: return riscv_subset_supports ("c");
313 case INSN_CLASS_A: return riscv_subset_supports ("a");
314 case INSN_CLASS_M: return riscv_subset_supports ("m");
315 case INSN_CLASS_F: return riscv_subset_supports ("f");
316 case INSN_CLASS_D: return riscv_subset_supports ("d");
729a5353 317 case INSN_CLASS_Q: return riscv_subset_supports ("q");
7e9ad3a3
JW		 318
319 case INSN_CLASS_F_AND_C:
729a5353
NC		 320 return (riscv_subset_supports ("f")
321 && riscv_subset_supports ("c"));
322 case INSN_CLASS_D_AND_C:
323 return (riscv_subset_supports ("d")
324 && riscv_subset_supports ("c"));
43135d3b 325
729a5353
NC		 326 case INSN_CLASS_ZICSR:
327 return riscv_subset_supports ("zicsr");
328 case INSN_CLASS_ZIFENCEI:
329 return riscv_subset_supports ("zifencei");
aa881ecd
PT		 330 case INSN_CLASS_ZIHINTPAUSE:
331 return riscv_subset_supports ("zihintpause");
43135d3b 332
7e9ad3a3 333 default:
b800637e 334 as_fatal ("internal: unreachable");
7e9ad3a3
JW		 335 return FALSE;
336 }
43135d3b
JW		 337}
338
8f595e9b 339/* Handle of the extension with version hash table. */
629310ab 340static htab_t ext_version_hash = NULL;
8f595e9b 341
629310ab 342static htab_t
3d73d29e 343init_ext_version_hash (void)
8f595e9b 344{
3d73d29e 345 const struct riscv_ext_version *table = ext_version_table;
629310ab 346 htab_t hash = str_htab_create ();
3d73d29e 347 int i = 0;
8f595e9b
NC		 348
349 while (table[i].name)
350 {
351 const char *name = table[i].name;
fe0e921f 352 if (str_hash_insert (hash, name, &table[i], 0) != NULL)
b800637e 353 as_fatal (_("internal: duplicate %s"), name);
8f595e9b
NC		 354
355 i++;
356 while (table[i].name
1942a048 357 && strcmp (table[i].name, name) == 0)
8f595e9b
NC		 358 i++;
359 }
360
361 return hash;
362}
363
364static void
365riscv_get_default_ext_version (const char *name,
7ef19aa6
NC		 366 int *major_version,
367 int *minor_version)
8f595e9b
NC		 368{
369 struct riscv_ext_version *ext;
370
8f595e9b
NC		 371 if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
372 return;
373
629310ab 374 ext = (struct riscv_ext_version *) str_hash_find (ext_version_hash, name);
8f595e9b 375 while (ext
7ef19aa6
NC		 376 && ext->name
377 && strcmp (ext->name, name) == 0)
8f595e9b 378 {
2652cfad
CXW		 379 if (ext->isa_spec_class == ISA_SPEC_CLASS_DRAFT
380 || ext->isa_spec_class == default_isa_spec)
7ef19aa6
NC		 381 {
382 *major_version = ext->major_version;
383 *minor_version = ext->minor_version;
384 return;
385 }
8f595e9b
NC		 386 ext++;
387 }
388}
389
2922d21d 390/* Set which ISA and extensions are available. */
e23eba97 391
e23eba97 392static void
2922d21d 393riscv_set_arch (const char *s)
e23eba97 394{
1080bf78
JW		 395 riscv_parse_subset_t rps;
396 rps.subset_list = &riscv_subsets;
7ef19aa6 397 rps.error_handler = as_bad;
1080bf78 398 rps.xlen = &xlen;
8f595e9b
NC		 399 rps.get_default_version = riscv_get_default_ext_version;
400
401 if (s == NULL)
402 return;
7f999549 403
1080bf78
JW		 404 riscv_release_subset_list (&riscv_subsets);
405 riscv_parse_subset (&rps, s);
e23eba97
NC		 406}
407
dcd709e0 408/* Indicate -mabi option is explictly set. */
6e1605e4
NC		 409static bfd_boolean explicit_mabi = FALSE;
410
411static void
412riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
413{
414 abi_xlen = new_xlen;
415 float_abi = new_float_abi;
416 rve_abi = rve;
417}
418
dcd709e0
NC		 419/* If the -mabi option isn't set, then set the abi according to the
420 ISA string. Otherwise, check if there is any conflict. */
6e1605e4
NC		 421
422static void
423riscv_set_abi_by_arch (void)
424{
425 if (!explicit_mabi)
426 {
427 if (riscv_subset_supports ("q"))
428 riscv_set_abi (xlen, FLOAT_ABI_QUAD, FALSE);
429 else if (riscv_subset_supports ("d"))
430 riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, FALSE);
431 else
432 riscv_set_abi (xlen, FLOAT_ABI_SOFT, FALSE);
433 }
434 else
435 {
436 gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT);
437 if (abi_xlen > xlen)
438 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
439 else if (abi_xlen < xlen)
440 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
441 }
442
443 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
444 elf_flags &= ~EF_RISCV_FLOAT_ABI;
445 elf_flags |= float_abi << 1;
446
447 if (rve_abi)
448 elf_flags |= EF_RISCV_RVE;
449}
450
e23eba97 451/* Handle of the OPCODE hash table. */
629310ab 452static htab_t op_hash = NULL;
e23eba97 453
0e35537d 454/* Handle of the type of .insn hash table. */
629310ab 455static htab_t insn_type_hash = NULL;
0e35537d 456
e23eba97 457/* This array holds the chars that always start a comment. If the
dcd709e0 458 pre-processor is disabled, these aren't very useful. */
e23eba97
NC		 459const char comment_chars[] = "#";
460
461/* This array holds the chars that only start a comment at the beginning of
462 a line. If the line seems to have the form '# 123 filename'
dcd709e0
NC		 463 .line and .file directives will appear in the pre-processed output
464
465 Note that input_file.c hand checks for '#' at the beginning of the
e23eba97 466 first line of the input file. This is because the compiler outputs
dcd709e0
NC		 467 #NO_APP at the beginning of its output.
468
469 Also note that C style comments are always supported. */
e23eba97
NC		 470const char line_comment_chars[] = "#";
471
472/* This array holds machine specific line separator characters. */
473const char line_separator_chars[] = ";";
474
dcd709e0 475/* Chars that can be used to separate mant from exp in floating point nums. */
e23eba97
NC		 476const char EXP_CHARS[] = "eE";
477
dcd709e0
NC		 478/* Chars that mean this number is a floating point constant.
479 As in 0f12.456 or 0d1.2345e12. */
e23eba97
NC		 480const char FLT_CHARS[] = "rRsSfFdDxXpP";
481
2dc8dd17
JW		 482/* Indicate we are already assemble any instructions or not. */
483static bfd_boolean start_assemble = FALSE;
484
f9a6a8f0 485/* Indicate ELF attributes are explicitly set. */
8f595e9b 486static bfd_boolean explicit_attr = FALSE;
2dc8dd17 487
f9a6a8f0 488/* Indicate CSR or priv instructions are explicitly used. */
1a79004f 489static bfd_boolean explicit_priv_attr = FALSE;
3fc6c3dc 490
e23eba97
NC		 491/* Macros for encoding relaxation state for RVC branches and far jumps. */
492#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
493 ((relax_substateT) \
494 (0xc0000000 \
495 | ((uncond) ? 1 : 0) \
496 | ((rvc) ? 2 : 0) \
497 | ((length) << 2)))
498#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
499#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
500#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
501#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
502
503/* Is the given value a sign-extended 32-bit value? */
504#define IS_SEXT_32BIT_NUM(x) \
505 (((x) &~ (offsetT) 0x7fffffff) == 0 \
506 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
507
508/* Is the given value a zero-extended 32-bit value? Or a negated one? */
509#define IS_ZEXT_32BIT_NUM(x) \
510 (((x) &~ (offsetT) 0xffffffff) == 0 \
511 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
512
513/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
514 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
515#define INSERT_OPERAND(FIELD, INSN, VALUE) \
516 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
517
518/* Determine if an instruction matches an opcode. */
519#define OPCODE_MATCHES(OPCODE, OP) \
520 (((OPCODE) & MASK_##OP) == MATCH_##OP)
521
522static char *expr_end;
523
524/* The default target format to use. */
525
526const char *
527riscv_target_format (void)
528{
fbc09e7a
MC		 529 if (target_big_endian)
530 return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv";
531 else
532 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
e23eba97
NC		 533}
534
535/* Return the length of instruction INSN. */
536
537static inline unsigned int
538insn_length (const struct riscv_cl_insn *insn)
539{
540 return riscv_insn_length (insn->insn_opcode);
541}
542
543/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
544
545static void
546create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
547{
548 insn->insn_mo = mo;
549 insn->insn_opcode = mo->match;
550 insn->frag = NULL;
551 insn->where = 0;
552 insn->fixp = NULL;
553}
554
555/* Install INSN at the location specified by its "frag" and "where" fields. */
556
557static void
558install_insn (const struct riscv_cl_insn *insn)
559{
560 char *f = insn->frag->fr_literal + insn->where;
fbc09e7a 561 number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn));
e23eba97
NC		 562}
563
564/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
565 and install the opcode in the new location. */
566
567static void
568move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
569{
570 insn->frag = frag;
571 insn->where = where;
572 if (insn->fixp != NULL)
573 {
574 insn->fixp->fx_frag = frag;
575 insn->fixp->fx_where = where;
576 }
577 install_insn (insn);
578}
579
580/* Add INSN to the end of the output. */
581
582static void
583add_fixed_insn (struct riscv_cl_insn *insn)
584{
585 char *f = frag_more (insn_length (insn));
586 move_insn (insn, frag_now, f - frag_now->fr_literal);
587}
588
589static void
590add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
591 relax_substateT subtype, symbolS *symbol, offsetT offset)
592{
593 frag_grow (max_chars);
594 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
595 frag_var (rs_machine_dependent, max_chars, var,
596 subtype, symbol, offset, NULL);
597}
598
599/* Compute the length of a branch sequence, and adjust the stored length
600 accordingly. If FRAGP is NULL, the worst-case length is returned. */
601
602static unsigned
603relaxed_branch_length (fragS *fragp, asection *sec, int update)
604{
605 int jump, rvc, length = 8;
606
607 if (!fragp)
608 return length;
609
610 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
611 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
612 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
613
614 /* Assume jumps are in range; the linker will catch any that aren't. */
615 length = jump ? 4 : 8;
616
617 if (fragp->fr_symbol != NULL
618 && S_IS_DEFINED (fragp->fr_symbol)
01156111 619 && !S_IS_WEAK (fragp->fr_symbol)
e23eba97
NC		 620 && sec == S_GET_SEGMENT (fragp->fr_symbol))
621 {
622 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
623 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
624 val -= fragp->fr_address + fragp->fr_fix;
625
626 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
627 length = 2;
628 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
629 length = 4;
630 else if (!jump && rvc)
631 length = 6;
632 }
633
634 if (update)
635 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
636
637 return length;
638}
639
0e35537d
JW		 640/* Information about an opcode name, mnemonics and its value. */
641struct opcode_name_t
642{
643 const char *name;
644 unsigned int val;
645};
646
647/* List for all supported opcode name. */
648static const struct opcode_name_t opcode_name_list[] =
649{
650 {"C0", 0x0},
651 {"C1", 0x1},
652 {"C2", 0x2},
653
654 {"LOAD", 0x03},
655 {"LOAD_FP", 0x07},
656 {"CUSTOM_0", 0x0b},
657 {"MISC_MEM", 0x0f},
658 {"OP_IMM", 0x13},
659 {"AUIPC", 0x17},
660 {"OP_IMM_32", 0x1b},
661 /* 48b 0x1f. */
662
663 {"STORE", 0x23},
664 {"STORE_FP", 0x27},
665 {"CUSTOM_1", 0x2b},
666 {"AMO", 0x2f},
667 {"OP", 0x33},
668 {"LUI", 0x37},
669 {"OP_32", 0x3b},
670 /* 64b 0x3f. */
671
672 {"MADD", 0x43},
673 {"MSUB", 0x47},
674 {"NMADD", 0x4f},
675 {"NMSUB", 0x4b},
676 {"OP_FP", 0x53},
677 /*reserved 0x57. */
678 {"CUSTOM_2", 0x5b},
679 /* 48b 0x5f. */
680
681 {"BRANCH", 0x63},
682 {"JALR", 0x67},
683 /*reserved 0x5b. */
684 {"JAL", 0x6f},
685 {"SYSTEM", 0x73},
686 /*reserved 0x77. */
687 {"CUSTOM_3", 0x7b},
688 /* >80b 0x7f. */
689
690 {NULL, 0}
691};
692
693/* Hash table for lookup opcode name. */
629310ab 694static htab_t opcode_names_hash = NULL;
0e35537d
JW		 695
696/* Initialization for hash table of opcode name. */
dcd709e0 697
0e35537d
JW		 698static void
699init_opcode_names_hash (void)
700{
0e35537d
JW		 701 const struct opcode_name_t *opcode;
702
703 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
fe0e921f 704 if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL)
b800637e 705 as_fatal (_("internal: duplicate %s"), opcode->name);
0e35537d
JW		 706}
707
dcd709e0
NC		 708/* Find `s` is a valid opcode name or not, return the opcode name info
709 if found. */
710
0e35537d
JW		 711static const struct opcode_name_t *
712opcode_name_lookup (char **s)
713{
714 char *e;
715 char save_c;
716 struct opcode_name_t *o;
717
718 /* Find end of name. */
719 e = *s;
720 if (is_name_beginner (*e))
721 ++e;
722 while (is_part_of_name (*e))
723 ++e;
724
725 /* Terminate name. */
726 save_c = *e;
727 *e = '\0';
728
629310ab 729 o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s);
0e35537d
JW		 730
731 /* Advance to next token if one was recognized. */
732 if (o)
733 *s = e;
734
735 *e = save_c;
736 expr_end = e;
737
738 return o;
739}
740
e23eba97
NC		 741enum reg_class
742{
743 RCLASS_GPR,
744 RCLASS_FPR,
8f595e9b
NC		 745 RCLASS_MAX,
746
747 RCLASS_CSR
e23eba97
NC		 748};
749
629310ab
ML		 750static htab_t reg_names_hash = NULL;
751static htab_t csr_extra_hash = NULL;
e23eba97
NC		 752
753#define ENCODE_REG_HASH(cls, n) \
754 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
755#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
756#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
757
758static void
759hash_reg_name (enum reg_class class, const char *name, unsigned n)
760{
761 void *hash = ENCODE_REG_HASH (class, n);
fe0e921f 762 if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL)
b800637e 763 as_fatal (_("internal: duplicate %s"), name);
e23eba97
NC		 764}
765
766static void
767hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
768{
769 unsigned i;
770
771 for (i = 0; i < n; i++)
772 hash_reg_name (class, names[i], i);
773}
774
8f595e9b 775/* Init hash table csr_extra_hash to handle CSR. */
dcd709e0 776
8f595e9b
NC		 777static void
778riscv_init_csr_hash (const char *name,
3d73d29e
NC		 779 unsigned address,
780 enum riscv_csr_class class,
781 enum riscv_spec_class define_version,
782 enum riscv_spec_class abort_version)
8f595e9b
NC		 783{
784 struct riscv_csr_extra *entry, *pre_entry;
8f595e9b
NC		 785 bfd_boolean need_enrty = TRUE;
786
787 pre_entry = NULL;
629310ab 788 entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
8f595e9b
NC		 789 while (need_enrty && entry != NULL)
790 {
791 if (entry->csr_class == class
1942a048
NC		 792 && entry->address == address
793 && entry->define_version == define_version
794 && entry->abort_version == abort_version)
795 need_enrty = FALSE;
8f595e9b
NC		 796 pre_entry = entry;
797 entry = entry->next;
798 }
1942a048 799
dcd709e0 800 /* Duplicate CSR. */
8f595e9b
NC		 801 if (!need_enrty)
802 return;
bd0cf5a6 803
8f595e9b
NC		 804 entry = XNEW (struct riscv_csr_extra);
805 entry->csr_class = class;
806 entry->address = address;
807 entry->define_version = define_version;
808 entry->abort_version = abort_version;
5c505568 809 entry->next = NULL;
8f595e9b 810
8f595e9b 811 if (pre_entry == NULL)
fe0e921f 812 str_hash_insert (csr_extra_hash, name, entry, 0);
8f595e9b
NC		 813 else
814 pre_entry->next = entry;
815}
bd0cf5a6 816
dcd709e0
NC		 817/* Return the CSR address after checking the ISA dependency and
818 the privileged spec version.
819
820 There are one warning and two errors for CSR,
821
822 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
823 or the privileged spec, report warning only if -mcsr-check is set.
824 Unknown CSR: the CSR has never been defined, report error.
825 Improper CSR: the CSR number over the range (> 0xfff), report error. */
bd0cf5a6 826
08ccfccf
NC		 827static unsigned int
828riscv_csr_address (const char *csr_name,
829 struct riscv_csr_extra *entry)
bd0cf5a6 830{
08ccfccf
NC		 831 struct riscv_csr_extra *saved_entry = entry;
832 enum riscv_csr_class csr_class = entry->csr_class;
833 bfd_boolean need_check_version = TRUE;
8f595e9b
NC		 834 bfd_boolean result = TRUE;
835
8f595e9b 836 switch (csr_class)
bd0cf5a6 837 {
8f595e9b
NC		 838 case CSR_CLASS_I:
839 result = riscv_subset_supports ("i");
840 break;
08ccfccf
NC		 841 case CSR_CLASS_I_32:
842 result = (xlen == 32 && riscv_subset_supports ("i"));
843 break;
8f595e9b
NC		 844 case CSR_CLASS_F:
845 result = riscv_subset_supports ("f");
08ccfccf 846 need_check_version = FALSE;
8f595e9b 847 break;
08ccfccf
NC		 848 case CSR_CLASS_DEBUG:
849 need_check_version = FALSE;
8f595e9b
NC		 850 break;
851 default:
852 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
bd0cf5a6
NC		 853 }
854
08ccfccf 855 if (riscv_opts.csr_check && !result)
b800637e 856 as_warn (_("invalid CSR `%s' for the current ISA"), csr_name);
8f595e9b
NC		 857
858 while (entry != NULL)
bd0cf5a6 859 {
08ccfccf
NC		 860 if (!need_check_version
861 || (default_priv_spec >= entry->define_version
862 && default_priv_spec < entry->abort_version))
8f595e9b 863 {
dcd709e0 864 /* Find the CSR according to the specific version. */
08ccfccf 865 return entry->address;
8f595e9b
NC		 866 }
867 entry = entry->next;
868 }
bd0cf5a6 869
dcd709e0
NC		 870 /* Can not find the CSR address from the chosen privileged version,
871 so use the newly defined value. */
8f595e9b
NC		 872 if (riscv_opts.csr_check)
873 {
3d73d29e
NC		 874 const char *priv_name = NULL;
875 RISCV_GET_PRIV_SPEC_NAME (priv_name, default_priv_spec);
8f595e9b 876 if (priv_name != NULL)
b800637e 877 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
8f595e9b 878 csr_name, priv_name);
bd0cf5a6 879 }
08ccfccf
NC		 880
881 return saved_entry->address;
bd0cf5a6
NC		 882}
883
dcd709e0
NC		 884/* Return -1 if the CSR has never been defined. Otherwise, return
885 the address. */
bd0cf5a6 886
8f595e9b 887static unsigned int
bd0cf5a6
NC		 888reg_csr_lookup_internal (const char *s)
889{
890 struct riscv_csr_extra *r =
629310ab 891 (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s);
bd0cf5a6
NC		 892
893 if (r == NULL)
8f595e9b 894 return -1U;
bd0cf5a6 895
08ccfccf 896 return riscv_csr_address (s, r);
bd0cf5a6
NC		 897}
898
e23eba97
NC		 899static unsigned int
900reg_lookup_internal (const char *s, enum reg_class class)
901{
8f595e9b
NC		 902 void *r;
903
904 if (class == RCLASS_CSR)
905 return reg_csr_lookup_internal (s);
e23eba97 906
629310ab 907 r = str_hash_find (reg_names_hash, s);
e23eba97
NC		 908 if (r == NULL || DECODE_REG_CLASS (r) != class)
909 return -1;
7f999549
JW		 910
911 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
912 return -1;
913
e23eba97
NC		 914 return DECODE_REG_NUM (r);
915}
916
917static bfd_boolean
918reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
919{
920 char *e;
921 char save_c;
922 int reg = -1;
923
924 /* Find end of name. */
925 e = *s;
926 if (is_name_beginner (*e))
927 ++e;
928 while (is_part_of_name (*e))
929 ++e;
930
931 /* Terminate name. */
932 save_c = *e;
933 *e = '\0';
934
935 /* Look for the register. Advance to next token if one was recognized. */
936 if ((reg = reg_lookup_internal (*s, class)) >= 0)
937 *s = e;
938
939 *e = save_c;
940 if (regnop)
941 *regnop = reg;
942 return reg >= 0;
943}
944
945static bfd_boolean
946arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
947{
948 const char *p = strchr (*s, ',');
949 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
950
bfb218e3
JW		 951 if (len == 0)
952 return FALSE;
953
e23eba97
NC		 954 for (i = 0; i < size; i++)
955 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
956 {
957 *regnop = i;
958 *s += len;
959 return TRUE;
960 }
961
962 return FALSE;
963}
964
965/* For consistency checking, verify that all bits are specified either
966 by the match/mask part of the instruction definition, or by the
dcd709e0 967 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
0e35537d 968
e23eba97 969static bfd_boolean
0e35537d 970validate_riscv_insn (const struct riscv_opcode *opc, int length)
e23eba97
NC		 971{
972 const char *p = opc->args;
973 char c;
974 insn_t used_bits = opc->mask;
0e35537d
JW		 975 int insn_width;
976 insn_t required_bits;
977
978 if (length == 0)
979 insn_width = 8 * riscv_insn_length (opc->match);
980 else
981 insn_width = 8 * length;
982
983 required_bits = ~0ULL >> (64 - insn_width);
e23eba97
NC		 984
985 if ((used_bits & opc->match) != (opc->match & required_bits))
986 {
987 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
988 opc->name, opc->args);
989 return FALSE;
990 }
991
992#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
993 while (*p)
994 switch (c = *p++)
995 {
996 case 'C': /* RVC */
997 switch (c = *p++)
998 {
5a9f5403
NC		 999 case 'U': break; /* CRS1, constrained to equal RD. */
1000 case 'c': break; /* CRS1, constrained to equal sp. */
1001 case 'T': /* CRS2, floating point. */
1002 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1003 case 'S': /* CRS1S, floating point. */
e23eba97 1004 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
5a9f5403
NC		 1005 case 'w': break; /* CRS1S, constrained to equal RD. */
1006 case 'D': /* CRS2S, floating point. */
e23eba97 1007 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
5a9f5403
NC		 1008 case 'x': break; /* CRS2S, constrained to equal RD. */
1009 case 'z': break; /* CRS2S, constrained to be x0. */
1010 case '>': /* CITYPE immediate, compressed shift. */
1011 case 'u': /* CITYPE immediate, compressed lui. */
1012 case 'v': /* CITYPE immediate, li to compressed lui. */
1013 case 'o': /* CITYPE immediate, allow zero. */
1014 case 'j': used_bits |= ENCODE_CITYPE_IMM (-1U); break;
1015 case 'L': used_bits |= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1016 case 'm': used_bits |= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1017 case 'n': used_bits |= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1018 case '6': used_bits |= ENCODE_CSSTYPE_IMM (-1U); break;
1019 case 'M': used_bits |= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1020 case 'N': used_bits |= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1021 case '8': used_bits |= ENCODE_CIWTYPE_IMM (-1U); break;
1022 case 'K': used_bits |= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1023 /* CLTYPE and CSTYPE have the same immediate encoding. */
1024 case '5': used_bits |= ENCODE_CLTYPE_IMM (-1U); break;
1025 case 'k': used_bits |= ENCODE_CLTYPE_LW_IMM (-1U); break;
1026 case 'l': used_bits |= ENCODE_CLTYPE_LD_IMM (-1U); break;
1027 case 'p': used_bits |= ENCODE_CBTYPE_IMM (-1U); break;
1028 case 'a': used_bits |= ENCODE_CJTYPE_IMM (-1U); break;
1029 case 'F': /* Compressed funct for .insn directive. */
0e35537d
JW		 1030 switch (c = *p++)
1031 {
4765cd61 1032 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
0e35537d
JW		 1033 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
1034 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
4765cd61 1035 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
0e35537d 1036 default:
b800637e
NC		 1037 as_bad (_("internal: bad RISC-V opcode "
1038 "(unknown operand type `CF%c'): %s %s"),
0e35537d
JW		 1039 c, opc->name, opc->args);
1040 return FALSE;
1041 }
1042 break;
e23eba97 1043 default:
b800637e
NC		 1044 as_bad (_("internal: bad RISC-V opcode "
1045 "(unknown operand type `C%c'): %s %s"),
e23eba97
NC		 1046 c, opc->name, opc->args);
1047 return FALSE;
1048 }
1049 break;
1050 case ',': break;
1051 case '(': break;
1052 case ')': break;
1942a048
NC		 1053 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
1054 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
5a9f5403
NC		 1055 case 'A': break; /* Macro operand, must be symbol. */
1056 case 'B': break; /* Macro operand, must be symbol or constant. */
1057 case 'I': break; /* Macro operand, must be constant. */
1058 case 'D': /* RD, floating point. */
1942a048 1059 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
5a9f5403
NC		 1060 case 'Z': /* RS1, CSR number. */
1061 case 'S': /* RS1, floating point. */
1942a048 1062 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
5a9f5403
NC		 1063 case 'U': /* RS1 and RS2 are the same, floating point. */
1064 USE_BITS (OP_MASK_RS1, OP_SH_RS1);
1065 /* Fall through. */
1066 case 'T': /* RS2, floating point. */
1942a048 1067 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
5a9f5403
NC		 1068 case 'R': /* RS3, floating point. */
1069 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
1070 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
1071 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
1942a048
NC		 1072 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
1073 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
5a9f5403 1074 case 'o': /* ITYPE immediate, load displacement. */
1d65abb5 1075 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
5a9f5403
NC		 1076 case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
1077 case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
1942a048
NC		 1078 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
1079 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
5a9f5403
NC		 1080 case 'z': break; /* Zero immediate. */
1081 case '[': break; /* Unused operand. */
1082 case ']': break; /* Unused operand. */
1083 case '0': break; /* AMO displacement, must to zero. */
1084 case '1': break; /* Relaxation operand. */
dcd709e0 1085 case 'F': /* Funct for .insn directive. */
0e35537d
JW		 1086 switch (c = *p++)
1087 {
1088 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
1089 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
1090 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
1091 default:
b800637e
NC		 1092 as_bad (_("internal: bad RISC-V opcode "
1093 "(unknown operand type `F%c'): %s %s"),
0e35537d
JW		 1094 c, opc->name, opc->args);
1095 return FALSE;
1096 }
1097 break;
dcd709e0 1098 case 'O': /* Opcode for .insn directive. */
0e35537d
JW		 1099 switch (c = *p++)
1100 {
1101 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
1102 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
1103 default:
b800637e
NC		 1104 as_bad (_("internal: bad RISC-V opcode "
1105 "(unknown operand type `F%c'): %s %s"),
0e35537d
JW		 1106 c, opc->name, opc->args);
1107 return FALSE;
1108 }
1109 break;
e23eba97
NC		 1110 default:
1111 as_bad (_("internal: bad RISC-V opcode "
1112 "(unknown operand type `%c'): %s %s"),
1113 c, opc->name, opc->args);
1114 return FALSE;
1115 }
1116#undef USE_BITS
1117 if (used_bits != required_bits)
1118 {
b800637e
NC		 1119 as_bad (_("internal: bad RISC-V opcode "
1120 "(bits 0x%lx undefined): %s %s"),
e23eba97
NC		 1121 ~(unsigned long)(used_bits & required_bits),
1122 opc->name, opc->args);
1123 return FALSE;
1124 }
1125 return TRUE;
1126}
1127
1128struct percent_op_match
1129{
1130 const char *str;
1131 bfd_reloc_code_real_type reloc;
1132};
1133
dcd709e0
NC		 1134/* Common hash table initialization function for instruction and .insn
1135 directive. */
1136
629310ab 1137static htab_t
0e35537d
JW		 1138init_opcode_hash (const struct riscv_opcode *opcodes,
1139 bfd_boolean insn_directive_p)
e23eba97
NC		 1140{
1141 int i = 0;
0e35537d 1142 int length;
629310ab 1143 htab_t hash = str_htab_create ();
0e35537d 1144 while (opcodes[i].name)
e23eba97 1145 {
0e35537d 1146 const char *name = opcodes[i].name;
fe0e921f 1147 if (str_hash_insert (hash, name, &opcodes[i], 0) != NULL)
b800637e 1148 as_fatal (_("internal: duplicate %s"), name);
e23eba97
NC		 1149
1150 do
1151 {
0e35537d 1152 if (opcodes[i].pinfo != INSN_MACRO)
e23eba97 1153 {
0e35537d
JW		 1154 if (insn_directive_p)
1155 length = ((name[0] == 'c') ? 2 : 4);
1156 else
dcd709e0 1157 length = 0; /* Let assembler determine the length. */
0e35537d 1158 if (!validate_riscv_insn (&opcodes[i], length))
b800637e
NC		 1159 as_fatal (_("internal: broken assembler. "
1160 "No assembly attempted"));
e23eba97 1161 }
0e35537d
JW		 1162 else
1163 gas_assert (!insn_directive_p);
e23eba97
NC		 1164 ++i;
1165 }
0e35537d 1166 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
e23eba97
NC		 1167 }
1168
0e35537d
JW		 1169 return hash;
1170}
1171
1172/* This function is called once, at assembler startup time. It should set up
1173 all the tables, etc. that the MD part of the assembler will need. */
1174
1175void
1176md_begin (void)
1177{
1178 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
1179
1180 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
b800637e 1181 as_warn (_("could not set architecture and machine"));
0e35537d
JW		 1182
1183 op_hash = init_opcode_hash (riscv_opcodes, FALSE);
1184 insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
1185
629310ab 1186 reg_names_hash = str_htab_create ();
e23eba97
NC		 1187 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
1188 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
1189 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
1190 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
b9c04e5a
JW		 1191 /* Add "fp" as an alias for "s0". */
1192 hash_reg_name (RCLASS_GPR, "fp", 8);
1193
bd0cf5a6 1194 /* Create and insert CSR hash tables. */
629310ab 1195 csr_extra_hash = str_htab_create ();
8f595e9b
NC		 1196#define DECLARE_CSR(name, num, class, define_version, abort_version) \
1197 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1198#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1199 DECLARE_CSR(name, num, class, define_version, abort_version);
e23eba97
NC		 1200#include "opcode/riscv-opc.h"
1201#undef DECLARE_CSR
1202
629310ab 1203 opcode_names_hash = str_htab_create ();
bd0cf5a6
NC		 1204 init_opcode_names_hash ();
1205
e23eba97
NC		 1206 /* Set the default alignment for the text section. */
1207 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
1208}
1209
45f76423
AW		 1210static insn_t
1211riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
1212{
1213 switch (reloc_type)
1214 {
1215 case BFD_RELOC_32:
1216 return value;
1217
1218 case BFD_RELOC_RISCV_HI20:
1219 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
1220
1221 case BFD_RELOC_RISCV_LO12_S:
1222 return ENCODE_STYPE_IMM (value);
1223
1224 case BFD_RELOC_RISCV_LO12_I:
1225 return ENCODE_ITYPE_IMM (value);
1226
1227 default:
1228 abort ();
1229 }
1230}
1231
e23eba97
NC		 1232/* Output an instruction. IP is the instruction information.
1233 ADDRESS_EXPR is an operand of the instruction to be used with
1234 RELOC_TYPE. */
1235
1236static void
1237append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
1238 bfd_reloc_code_real_type reloc_type)
1239{
1240 dwarf2_emit_insn (0);
1241
1242 if (reloc_type != BFD_RELOC_UNUSED)
1243 {
1244 reloc_howto_type *howto;
1245
1d65abb5 1246 gas_assert (address_expr);
e23eba97
NC		 1247 if (reloc_type == BFD_RELOC_12_PCREL
1248 || reloc_type == BFD_RELOC_RISCV_JMP)
1249 {
1250 int j = reloc_type == BFD_RELOC_RISCV_JMP;
1251 int best_case = riscv_insn_length (ip->insn_opcode);
1252 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
743f5cfc
JW		 1253
1254 if (now_seg == absolute_section)
1255 {
1256 as_bad (_("relaxable branches not supported in absolute section"));
1257 return;
1258 }
1259
e23eba97
NC		 1260 add_relaxed_insn (ip, worst_case, best_case,
1261 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
1262 address_expr->X_add_symbol,
1263 address_expr->X_add_number);
1264 return;
1265 }
45f76423 1266 else
e23eba97 1267 {
45f76423
AW		 1268 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
1269 if (howto == NULL)
b800637e
NC		 1270 as_bad (_("internal: usupported RISC-V relocation number %d"),
1271 reloc_type);
e23eba97 1272
45f76423
AW		 1273 ip->fixp = fix_new_exp (ip->frag, ip->where,
1274 bfd_get_reloc_size (howto),
1275 address_expr, FALSE, reloc_type);
e23eba97 1276
45f76423 1277 ip->fixp->fx_tcbit = riscv_opts.relax;
e23eba97 1278 }
e23eba97
NC		 1279 }
1280
e23eba97
NC		 1281 add_fixed_insn (ip);
1282 install_insn (ip);
f77bb6c5
JW		 1283
1284 /* We need to start a new frag after any instruction that can be
1285 optimized away or compressed by the linker during relaxation, to prevent
1286 the assembler from computing static offsets across such an instruction.
1287 This is necessary to get correct EH info. */
b1b11e92 1288 if (reloc_type == BFD_RELOC_RISCV_HI20
f77bb6c5
JW		 1289 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
1290 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
1291 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
1292 {
1293 frag_wane (frag_now);
1294 frag_new (0);
1295 }
e23eba97
NC		 1296}
1297
1298/* Build an instruction created by a macro expansion. This is passed
dcd709e0
NC		 1299 a pointer to the count of instructions created so far, an expression,
1300 the name of the instruction to build, an operand format string, and
1301 corresponding arguments. */
e23eba97
NC		 1302
1303static void
1304macro_build (expressionS *ep, const char *name, const char *fmt, ...)
1305{
1306 const struct riscv_opcode *mo;
1307 struct riscv_cl_insn insn;
1308 bfd_reloc_code_real_type r;
1309 va_list args;
1310
1311 va_start (args, fmt);
1312
1313 r = BFD_RELOC_UNUSED;
629310ab 1314 mo = (struct riscv_opcode *) str_hash_find (op_hash, name);
e23eba97
NC		 1315 gas_assert (mo);
1316
1317 /* Find a non-RVC variant of the instruction. append_insn will compress
1318 it if possible. */
1319 while (riscv_insn_length (mo->match) < 4)
1320 mo++;
1321 gas_assert (strcmp (name, mo->name) == 0);
1322
1323 create_insn (&insn, mo);
1324 for (;;)
1325 {
1326 switch (*fmt++)
1327 {
1328 case 'd':
1329 INSERT_OPERAND (RD, insn, va_arg (args, int));
1330 continue;
1331
1332 case 's':
1333 INSERT_OPERAND (RS1, insn, va_arg (args, int));
1334 continue;
1335
1336 case 't':
1337 INSERT_OPERAND (RS2, insn, va_arg (args, int));
1338 continue;
1339
e23eba97
NC		 1340 case 'j':
1341 case 'u':
1342 case 'q':
1343 gas_assert (ep != NULL);
1344 r = va_arg (args, int);
1345 continue;
1346
1347 case '\0':
1348 break;
1349 case ',':
1350 continue;
1351 default:
b800637e 1352 as_fatal (_("internal: invalid macro"));
e23eba97
NC		 1353 }
1354 break;
1355 }
1356 va_end (args);
1357 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1358
1359 append_insn (&insn, ep, r);
1360}
1361
db3b6ecc
KC		 1362/* Build an instruction created by a macro expansion. Like md_assemble but
1363 accept a printf-style format string and arguments. */
1364
1365static void
1366md_assemblef (const char *format, ...)
1367{
1368 char *buf = NULL;
1369 va_list ap;
1370 int r;
1371
1372 va_start (ap, format);
1373
1374 r = vasprintf (&buf, format, ap);
1375
1376 if (r < 0)
b800637e 1377 as_fatal (_("internal: vasprintf failed"));
db3b6ecc
KC		 1378
1379 md_assemble (buf);
1380 free(buf);
1381
1382 va_end (ap);
1383}
1384
e23eba97
NC		 1385/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1386 unset. */
dcd709e0 1387
e23eba97
NC		 1388static void
1389normalize_constant_expr (expressionS *ex)
1390{
1391 if (xlen > 32)
1392 return;
1393 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1394 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1395 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1396 - 0x80000000);
1397}
1398
ca2fd32c
JW		 1399/* Fail if an expression EX is not a constant. IP is the instruction using EX.
1400 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
e23eba97
NC		 1401
1402static void
ca2fd32c
JW		 1403check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
1404 bfd_boolean maybe_csr)
e23eba97
NC		 1405{
1406 if (ex->X_op == O_big)
1407 as_bad (_("unsupported large constant"));
ca2fd32c
JW		 1408 else if (maybe_csr && ex->X_op == O_symbol)
1409 as_bad (_("unknown CSR `%s'"),
1410 S_GET_NAME (ex->X_add_symbol));
e23eba97 1411 else if (ex->X_op != O_constant)
b800637e 1412 as_bad (_("instruction %s requires absolute expression"),
e23eba97
NC		 1413 ip->insn_mo->name);
1414 normalize_constant_expr (ex);
1415}
1416
1417static symbolS *
1418make_internal_label (void)
1419{
e01e1cee
AM		 1420 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now,
1421 frag_now_fix ());
e23eba97
NC		 1422}
1423
1424/* Load an entry from the GOT. */
dcd709e0 1425
e23eba97
NC		 1426static void
1427pcrel_access (int destreg, int tempreg, expressionS *ep,
1428 const char *lo_insn, const char *lo_pattern,
1429 bfd_reloc_code_real_type hi_reloc,
1430 bfd_reloc_code_real_type lo_reloc)
1431{
1432 expressionS ep2;
1433 ep2.X_op = O_symbol;
1434 ep2.X_add_symbol = make_internal_label ();
1435 ep2.X_add_number = 0;
1436
1437 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1438 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1439}
1440
1441static void
1442pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1443 bfd_reloc_code_real_type hi_reloc,
1444 bfd_reloc_code_real_type lo_reloc)
1445{
1446 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1447}
1448
1449static void
1450pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1451 bfd_reloc_code_real_type hi_reloc,
1452 bfd_reloc_code_real_type lo_reloc)
1453{
1454 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1455}
1456
1457/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
dcd709e0 1458
e23eba97
NC		 1459static void
1460riscv_call (int destreg, int tempreg, expressionS *ep,
1461 bfd_reloc_code_real_type reloc)
1462{
b1b11e92
AM		 1463 /* Ensure the jalr is emitted to the same frag as the auipc. */
1464 frag_grow (8);
e23eba97
NC		 1465 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1466 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
b1b11e92
AM		 1467 /* See comment at end of append_insn. */
1468 frag_wane (frag_now);
1469 frag_new (0);
e23eba97
NC		 1470}
1471
1472/* Load an integer constant into a register. */
1473
1474static void
1475load_const (int reg, expressionS *ep)
1476{
1477 int shift = RISCV_IMM_BITS;
4f7cc141 1478 bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1);
e23eba97 1479 expressionS upper = *ep, lower = *ep;
4f7cc141 1480 lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign;
e23eba97
NC		 1481 upper.X_add_number -= lower.X_add_number;
1482
1483 if (ep->X_op != O_constant)
1484 {
1485 as_bad (_("unsupported large constant"));
1486 return;
1487 }
1488
1d65abb5 1489 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
e23eba97
NC		 1490 {
1491 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1492 while (((upper.X_add_number >> shift) & 1) == 0)
1493 shift++;
1494
1495 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1d65abb5 1496 load_const (reg, &upper);
e23eba97 1497
db3b6ecc 1498 md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift);
e23eba97 1499 if (lower.X_add_number != 0)
db3b6ecc
KC		 1500 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg,
1501 lower.X_add_number);
e23eba97
NC		 1502 }
1503 else
1504 {
1505 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1506 int hi_reg = 0;
1507
1508 if (upper.X_add_number != 0)
1509 {
db3b6ecc
KC		 1510 /* Discard low part and zero-extend upper immediate. */
1511 upper_imm = ((uint32_t)upper.X_add_number >> shift);
1512
1513 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm);
e23eba97
NC		 1514 hi_reg = reg;
1515 }
1516
1517 if (lower.X_add_number != 0 || hi_reg == 0)
db3b6ecc
KC		 1518 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg,
1519 lower.X_add_number);
e23eba97
NC		 1520 }
1521}
1522
c2137f55
NC		 1523/* Zero extend and sign extend byte/half-word/word. */
1524
1525static void
1526riscv_ext (int destreg, int srcreg, unsigned shift, bfd_boolean sign)
1527{
1528 if (sign)
1529 {
1530 md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
1531 md_assemblef ("srai x%d, x%d, 0x%x", destreg, destreg, shift);
1532 }
1533 else
1534 {
1535 md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
1536 md_assemblef ("srli x%d, x%d, 0x%x", destreg, destreg, shift);
1537 }
1538}
1539
e23eba97 1540/* Expand RISC-V assembly macros into one or more instructions. */
2652cfad 1541
e23eba97
NC		 1542static void
1543macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1544 bfd_reloc_code_real_type *imm_reloc)
1545{
1546 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1547 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1548 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1549 int mask = ip->insn_mo->mask;
1550
1551 switch (mask)
1552 {
1553 case M_LI:
1554 load_const (rd, imm_expr);
1555 break;
1556
1557 case M_LA:
1558 case M_LLA:
1559 /* Load the address of a symbol into a register. */
1560 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1561 as_bad (_("offset too large"));
1562
1563 if (imm_expr->X_op == O_constant)
1564 load_const (rd, imm_expr);
dcd709e0 1565 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol. */
e23eba97
NC		 1566 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1567 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
dcd709e0 1568 else /* Local PIC symbol, or any non-PIC symbol. */
e23eba97
NC		 1569 pcrel_load (rd, rd, imm_expr, "addi",
1570 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1571 break;
1572
1573 case M_LA_TLS_GD:
1574 pcrel_load (rd, rd, imm_expr, "addi",
1575 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1576 break;
1577
1578 case M_LA_TLS_IE:
1579 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1580 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1581 break;
1582
1583 case M_LB:
1584 pcrel_load (rd, rd, imm_expr, "lb",
1585 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1586 break;
1587
1588 case M_LBU:
1589 pcrel_load (rd, rd, imm_expr, "lbu",
1590 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1591 break;
1592
1593 case M_LH:
1594 pcrel_load (rd, rd, imm_expr, "lh",
1595 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1596 break;
1597
1598 case M_LHU:
1599 pcrel_load (rd, rd, imm_expr, "lhu",
1600 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1601 break;
1602
1603 case M_LW:
1604 pcrel_load (rd, rd, imm_expr, "lw",
1605 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1606 break;
1607
1608 case M_LWU:
1609 pcrel_load (rd, rd, imm_expr, "lwu",
1610 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1611 break;
1612
1613 case M_LD:
1614 pcrel_load (rd, rd, imm_expr, "ld",
1615 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1616 break;
1617
1618 case M_FLW:
1619 pcrel_load (rd, rs1, imm_expr, "flw",
1620 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1621 break;
1622
1623 case M_FLD:
1624 pcrel_load (rd, rs1, imm_expr, "fld",
1625 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1626 break;
1627
1628 case M_SB:
1629 pcrel_store (rs2, rs1, imm_expr, "sb",
1630 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1631 break;
1632
1633 case M_SH:
1634 pcrel_store (rs2, rs1, imm_expr, "sh",
1635 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1636 break;
1637
1638 case M_SW:
1639 pcrel_store (rs2, rs1, imm_expr, "sw",
1640 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1641 break;
1642
1643 case M_SD:
1644 pcrel_store (rs2, rs1, imm_expr, "sd",
1645 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1646 break;
1647
1648 case M_FSW:
1649 pcrel_store (rs2, rs1, imm_expr, "fsw",
1650 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1651 break;
1652
1653 case M_FSD:
1654 pcrel_store (rs2, rs1, imm_expr, "fsd",
1655 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1656 break;
1657
1658 case M_CALL:
1659 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1660 break;
1661
c2137f55
NC		 1662 case M_ZEXTH:
1663 riscv_ext (rd, rs1, xlen - 16, FALSE);
1664 break;
1665
1666 case M_ZEXTW:
1667 riscv_ext (rd, rs1, xlen - 32, FALSE);
1668 break;
1669
1670 case M_SEXTB:
1671 riscv_ext (rd, rs1, xlen - 8, TRUE);
1672 break;
1673
1674 case M_SEXTH:
1675 riscv_ext (rd, rs1, xlen - 16, TRUE);
1676 break;
1677
e23eba97 1678 default:
b800637e 1679 as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name);
e23eba97
NC		 1680 break;
1681 }
1682}
1683
1684static const struct percent_op_match percent_op_utype[] =
1685{
1686 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1687 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
dee35d02 1688 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
e23eba97
NC		 1689 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1690 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1691 {"%hi", BFD_RELOC_RISCV_HI20},
1692 {0, 0}
1693};
1694
1695static const struct percent_op_match percent_op_itype[] =
1696{
1697 {"%lo", BFD_RELOC_RISCV_LO12_I},
1698 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1699 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1700 {0, 0}
1701};
1702
1703static const struct percent_op_match percent_op_stype[] =
1704{
1705 {"%lo", BFD_RELOC_RISCV_LO12_S},
1706 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1707 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1708 {0, 0}
1709};
1710
1711static const struct percent_op_match percent_op_rtype[] =
1712{
1713 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1714 {0, 0}
1715};
1716
f50fabe4
JW		 1717static const struct percent_op_match percent_op_null[] =
1718{
1719 {0, 0}
1720};
1721
e23eba97
NC		 1722/* Return true if *STR points to a relocation operator. When returning true,
1723 move *STR over the operator and store its relocation code in *RELOC.
1724 Leave both *STR and *RELOC alone when returning false. */
1725
1726static bfd_boolean
1727parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1728 const struct percent_op_match *percent_op)
1729{
1730 for ( ; percent_op->str; percent_op++)
1731 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1732 {
1733 int len = strlen (percent_op->str);
1734
1735 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1736 continue;
1737
1738 *str += strlen (percent_op->str);
1739 *reloc = percent_op->reloc;
1740
1741 /* Check whether the output BFD supports this relocation.
1742 If not, issue an error and fall back on something safe. */
45f76423
AW		 1743 if (*reloc != BFD_RELOC_UNUSED
1744 && !bfd_reloc_type_lookup (stdoutput, *reloc))
e23eba97 1745 {
b800637e
NC		 1746 as_bad ("internal: relocation %s isn't supported by the "
1747 "current ABI", percent_op->str);
e23eba97
NC		 1748 *reloc = BFD_RELOC_UNUSED;
1749 }
1750 return TRUE;
1751 }
1752 return FALSE;
1753}
1754
1755static void
1756my_getExpression (expressionS *ep, char *str)
1757{
1758 char *save_in;
1759
1760 save_in = input_line_pointer;
1761 input_line_pointer = str;
1762 expression (ep);
1763 expr_end = input_line_pointer;
1764 input_line_pointer = save_in;
1765}
1766
1767/* Parse string STR as a 16-bit relocatable operand. Store the
1768 expression in *EP and the relocation, if any, in RELOC.
1769 Return the number of relocation operators used (0 or 1).
1770
1771 On exit, EXPR_END points to the first character after the expression. */
1772
1773static size_t
1774my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1775 char *str, const struct percent_op_match *percent_op)
1776{
1777 size_t reloc_index;
1778 unsigned crux_depth, str_depth, regno;
1779 char *crux;
1780
8970c022
JW		 1781 /* First, check for integer registers. No callers can accept a reg, but
1782 we need to avoid accidentally creating a useless undefined symbol below,
1783 if this is an instruction pattern that can't match. A glibc build fails
1784 if this is removed. */
e23eba97
NC		 1785 if (reg_lookup (&str, RCLASS_GPR, &regno))
1786 {
1787 ep->X_op = O_register;
1788 ep->X_add_number = regno;
8970c022 1789 expr_end = str;
e23eba97
NC		 1790 return 0;
1791 }
1792
1793 /* Search for the start of the main expression.
dcd709e0
NC		 1794
1795 End the loop with CRUX pointing to the start of the main expression and
1796 with CRUX_DEPTH containing the number of open brackets at that point. */
e23eba97
NC		 1797 reloc_index = -1;
1798 str_depth = 0;
1799 do
1800 {
1801 reloc_index++;
1802 crux = str;
1803 crux_depth = str_depth;
1804
1805 /* Skip over whitespace and brackets, keeping count of the number
1806 of brackets. */
1807 while (*str == ' ' || *str == '\t' || *str == '(')
1808 if (*str++ == '(')
1809 str_depth++;
1810 }
1811 while (*str == '%'
1812 && reloc_index < 1
1813 && parse_relocation (&str, reloc, percent_op));
1814
1815 my_getExpression (ep, crux);
1816 str = expr_end;
1817
1818 /* Match every open bracket. */
1819 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1820 if (*str++ == ')')
1821 crux_depth--;
1822
1823 if (crux_depth > 0)
1824 as_bad ("unclosed '('");
1825
1826 expr_end = str;
1827
1828 return reloc_index;
1829}
1830
0e35537d 1831/* Parse opcode name, could be an mnemonics or number. */
dcd709e0 1832
0e35537d
JW		 1833static size_t
1834my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1835 char *str, const struct percent_op_match *percent_op)
1836{
1837 const struct opcode_name_t *o = opcode_name_lookup (&str);
1838
1839 if (o != NULL)
1840 {
1841 ep->X_op = O_constant;
1842 ep->X_add_number = o->val;
1843 return 0;
1844 }
1845
1846 return my_getSmallExpression (ep, reloc, str, percent_op);
1847}
1848
f0531ed6
JW		 1849/* Detect and handle implicitly zero load-store offsets. For example,
1850 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1851 an implicit offset was detected. */
1852
1853static bfd_boolean
89424b1d 1854riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
f0531ed6
JW		 1855{
1856 /* Check whether there is only a single bracketed expression left.
1857 If so, it must be the base register and the constant must be zero. */
1858 if (*s == '(' && strchr (s + 1, '(') == 0)
1859 {
89424b1d
MR		 1860 ep->X_op = O_constant;
1861 ep->X_add_number = 0;
f0531ed6
JW		 1862 return TRUE;
1863 }
1864
1865 return FALSE;
1866}
1867
54b2aec1 1868/* All RISC-V CSR instructions belong to one of these classes. */
54b2aec1
NC		 1869enum csr_insn_type
1870{
1871 INSN_NOT_CSR,
1872 INSN_CSRRW,
1873 INSN_CSRRS,
1874 INSN_CSRRC
1875};
1876
1877/* Return which CSR instruction is checking. */
1878
1879static enum csr_insn_type
1880riscv_csr_insn_type (insn_t insn)
1881{
1882 if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
1883 || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
1884 return INSN_CSRRW;
1885 else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
1886 || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
1887 return INSN_CSRRS;
1888 else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
1889 || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
1890 return INSN_CSRRC;
1891 else
1892 return INSN_NOT_CSR;
1893}
1894
1895/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1896 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1897 CSR address is 0x3. */
1898
1899static bfd_boolean
1900riscv_csr_read_only_check (insn_t insn)
1901{
1902 int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
1903 int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
1904 int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
1905 enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
1906
1907 if (readonly
1908 && (((csr_insn == INSN_CSRRS
1909 || csr_insn == INSN_CSRRC)
1910 && rs1 != 0)
1911 || csr_insn == INSN_CSRRW))
1912 return FALSE;
1913
1914 return TRUE;
1915}
1916
1a79004f
NC		 1917/* Return True if it is a privileged instruction. Otherwise, return FALSE.
1918
1919 uret is actually a N-ext instruction. So it is better to regard it as
1920 an user instruction rather than the priv instruction.
1921
1922 hret is used to return from traps in H-mode. H-mode is removed since
1923 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1924 Therefore, hret should be controlled by the hypervisor spec rather than
1925 priv spec in the future.
1926
1927 dret is defined in the debug spec, so it should be checked in the future,
1928 too. */
1929
1930static bfd_boolean
1931riscv_is_priv_insn (insn_t insn)
1932{
1933 return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
1934 || ((insn ^ MATCH_MRET) & MASK_MRET) == 0
1935 || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0
1936 || ((insn ^ MATCH_WFI) & MASK_WFI) == 0
1937 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
dcd709e0 1938 check it here to keep the compatible. */
1a79004f
NC		 1939 || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
1940}
1941
e23eba97
NC		 1942/* This routine assembles an instruction into its binary format. As a
1943 side effect, it sets the global variable imm_reloc to the type of
1944 relocation to do if one of the operands is an address expression. */
1945
1946static const char *
1947riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
629310ab 1948 bfd_reloc_code_real_type *imm_reloc, htab_t hash)
e23eba97
NC		 1949{
1950 char *s;
1951 const char *args;
1952 char c = 0;
1953 struct riscv_opcode *insn;
1954 char *argsStart;
1955 unsigned int regno;
1956 char save_c = 0;
1957 int argnum;
1958 const struct percent_op_match *p;
1959 const char *error = "unrecognized opcode";
54b2aec1
NC		 1960 /* Indicate we are assembling instruction with CSR. */
1961 bfd_boolean insn_with_csr = FALSE;
e23eba97
NC		 1962
1963 /* Parse the name of the instruction. Terminate the string if whitespace
629310ab 1964 is found so that str_hash_find only sees the name part of the string. */
e23eba97
NC		 1965 for (s = str; *s != '\0'; ++s)
1966 if (ISSPACE (*s))
1967 {
1968 save_c = *s;
1969 *s++ = '\0';
1970 break;
1971 }
1972
629310ab 1973 insn = (struct riscv_opcode *) str_hash_find (hash, str);
e23eba97
NC		 1974
1975 argsStart = s;
1976 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1977 {
1080bf78
JW		 1978 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
1979 continue;
1980
7e9ad3a3 1981 if (!riscv_multi_subset_supports (insn->insn_class))
e23eba97
NC		 1982 continue;
1983
1984 create_insn (ip, insn);
1985 argnum = 1;
1986
1987 imm_expr->X_op = O_absent;
1988 *imm_reloc = BFD_RELOC_UNUSED;
1989 p = percent_op_itype;
1990
1991 for (args = insn->args;; ++args)
1992 {
1993 s += strspn (s, " \t");
1994 switch (*args)
1995 {
dcd709e0 1996 case '\0': /* End of args. */
e23eba97
NC		 1997 if (insn->pinfo != INSN_MACRO)
1998 {
1999 if (!insn->match_func (insn, ip->insn_opcode))
2000 break;
0e35537d
JW		 2001
2002 /* For .insn, insn->match and insn->mask are 0. */
2003 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
2004 ? ip->insn_opcode
2005 : insn->match) == 2
2006 && !riscv_opts.rvc)
e23eba97 2007 break;
54b2aec1 2008
1a79004f
NC		 2009 if (riscv_is_priv_insn (ip->insn_opcode))
2010 explicit_priv_attr = TRUE;
2011
54b2aec1
NC		 2012 /* Check if we write a read-only CSR by the CSR
2013 instruction. */
2014 if (insn_with_csr
2015 && riscv_opts.csr_check
2016 && !riscv_csr_read_only_check (ip->insn_opcode))
2017 {
2018 /* Restore the character in advance, since we want to
2019 report the detailed warning message here. */
2020 if (save_c)
2021 *(argsStart - 1) = save_c;
b800637e 2022 as_warn (_("read-only CSR is written `%s'"), str);
54b2aec1
NC		 2023 insn_with_csr = FALSE;
2024 }
e23eba97
NC		 2025 }
2026 if (*s != '\0')
2027 break;
2028 /* Successful assembly. */
2029 error = NULL;
54b2aec1 2030 insn_with_csr = FALSE;
e23eba97
NC		 2031 goto out;
2032
2033 case 'C': /* RVC */
2034 switch (*++args)
2035 {
dcd709e0 2036 case 's': /* RS1 x8-x15. */
e23eba97
NC		 2037 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2038 || !(regno >= 8 && regno <= 15))
2039 break;
2040 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2041 continue;
2042 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2043 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2044 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
2045 break;
2046 continue;
dcd709e0 2047 case 't': /* RS2 x8-x15. */
e23eba97
NC		 2048 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2049 || !(regno >= 8 && regno <= 15))
2050 break;
2051 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2052 continue;
2053 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2054 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2055 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
2056 break;
2057 continue;
2058 case 'U': /* RS1, constrained to equal RD. */
2059 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2060 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
2061 break;
2062 continue;
2063 case 'V': /* RS2 */
2064 if (!reg_lookup (&s, RCLASS_GPR, &regno))
2065 break;
2066 INSERT_OPERAND (CRS2, *ip, regno);
2067 continue;
2068 case 'c': /* RS1, constrained to equal sp. */
2069 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2070 || regno != X_SP)
2071 break;
2072 continue;
dcd709e0 2073 case 'z': /* RS2, constrained to equal x0. */
ca0bc150
JW		 2074 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2075 || regno != 0)
2076 break;
2077 continue;
e23eba97
NC		 2078 case '>':
2079 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2080 || imm_expr->X_op != O_constant
2081 || imm_expr->X_add_number <= 0
2082 || imm_expr->X_add_number >= 64)
2083 break;
5a9f5403 2084 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
dc1e8a47 2085 rvc_imm_done:
e23eba97
NC		 2086 s = expr_end;
2087 imm_expr->X_op = O_absent;
2088 continue;
5a9f5403 2089 case '5':
e23eba97
NC		 2090 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2091 || imm_expr->X_op != O_constant
5a9f5403 2092 || imm_expr->X_add_number < 0
169ec512 2093 || imm_expr->X_add_number >= 32
5a9f5403 2094 || !VALID_CLTYPE_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2095 break;
5a9f5403 2096 ip->insn_opcode |= ENCODE_CLTYPE_IMM (imm_expr->X_add_number);
e23eba97 2097 goto rvc_imm_done;
5a9f5403 2098 case '6':
0e35537d
JW		 2099 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2100 || imm_expr->X_op != O_constant
0e35537d 2101 || imm_expr->X_add_number < 0
5a9f5403
NC		 2102 || imm_expr->X_add_number >= 64
2103 || !VALID_CSSTYPE_IMM ((valueT) imm_expr->X_add_number))
0e35537d 2104 break;
5a9f5403 2105 ip->insn_opcode |= ENCODE_CSSTYPE_IMM (imm_expr->X_add_number);
0e35537d 2106 goto rvc_imm_done;
5a9f5403 2107 case '8':
e23eba97
NC		 2108 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2109 || imm_expr->X_op != O_constant
5a9f5403
NC		 2110 || imm_expr->X_add_number < 0
2111 || imm_expr->X_add_number >= 256
2112 || !VALID_CIWTYPE_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2113 break;
5a9f5403 2114 ip->insn_opcode |= ENCODE_CIWTYPE_IMM (imm_expr->X_add_number);
e23eba97
NC		 2115 goto rvc_imm_done;
2116 case 'j':
2117 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2118 || imm_expr->X_op != O_constant
2119 || imm_expr->X_add_number == 0
5a9f5403 2120 || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2121 break;
5a9f5403 2122 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
e23eba97
NC		 2123 goto rvc_imm_done;
2124 case 'k':
f0531ed6
JW		 2125 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2126 continue;
e23eba97
NC		 2127 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2128 || imm_expr->X_op != O_constant
5a9f5403 2129 || !VALID_CLTYPE_LW_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2130 break;
5a9f5403 2131 ip->insn_opcode |= ENCODE_CLTYPE_LW_IMM (imm_expr->X_add_number);
e23eba97
NC		 2132 goto rvc_imm_done;
2133 case 'l':
f0531ed6
JW		 2134 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2135 continue;
e23eba97
NC		 2136 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2137 || imm_expr->X_op != O_constant
5a9f5403 2138 || !VALID_CLTYPE_LD_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2139 break;
5a9f5403 2140 ip->insn_opcode |= ENCODE_CLTYPE_LD_IMM (imm_expr->X_add_number);
e23eba97
NC		 2141 goto rvc_imm_done;
2142 case 'm':
f0531ed6
JW		 2143 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2144 continue;
e23eba97
NC		 2145 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2146 || imm_expr->X_op != O_constant
5a9f5403 2147 || !VALID_CITYPE_LWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2148 break;
2149 ip->insn_opcode |=
5a9f5403 2150 ENCODE_CITYPE_LWSP_IMM (imm_expr->X_add_number);
e23eba97
NC		 2151 goto rvc_imm_done;
2152 case 'n':
f0531ed6
JW		 2153 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2154 continue;
e23eba97
NC		 2155 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2156 || imm_expr->X_op != O_constant
5a9f5403 2157 || !VALID_CITYPE_LDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2158 break;
2159 ip->insn_opcode |=
5a9f5403 2160 ENCODE_CITYPE_LDSP_IMM (imm_expr->X_add_number);
e23eba97 2161 goto rvc_imm_done;
b416fe87
KC		 2162 case 'o':
2163 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2164 || imm_expr->X_op != O_constant
21a186f2
JW		 2165 /* C.addiw, c.li, and c.andi allow zero immediate.
2166 C.addi allows zero immediate as hint. Otherwise this
2167 is same as 'j'. */
5a9f5403 2168 || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number))
b416fe87 2169 break;
5a9f5403 2170 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
b416fe87 2171 goto rvc_imm_done;
e23eba97
NC		 2172 case 'K':
2173 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2174 || imm_expr->X_op != O_constant
169ec512 2175 || imm_expr->X_add_number == 0
5a9f5403 2176 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2177 break;
2178 ip->insn_opcode |=
5a9f5403 2179 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr->X_add_number);
e23eba97
NC		 2180 goto rvc_imm_done;
2181 case 'L':
2182 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2183 || imm_expr->X_op != O_constant
5a9f5403 2184 || !VALID_CITYPE_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2185 break;
2186 ip->insn_opcode |=
5a9f5403 2187 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr->X_add_number);
e23eba97
NC		 2188 goto rvc_imm_done;
2189 case 'M':
f0531ed6
JW		 2190 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2191 continue;
e23eba97
NC		 2192 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2193 || imm_expr->X_op != O_constant
5a9f5403 2194 || !VALID_CSSTYPE_SWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2195 break;
2196 ip->insn_opcode |=
5a9f5403 2197 ENCODE_CSSTYPE_SWSP_IMM (imm_expr->X_add_number);
e23eba97
NC		 2198 goto rvc_imm_done;
2199 case 'N':
f0531ed6
JW		 2200 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2201 continue;
e23eba97
NC		 2202 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2203 || imm_expr->X_op != O_constant
5a9f5403 2204 || !VALID_CSSTYPE_SDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2205 break;
2206 ip->insn_opcode |=
5a9f5403 2207 ENCODE_CSSTYPE_SDSP_IMM (imm_expr->X_add_number);
e23eba97
NC		 2208 goto rvc_imm_done;
2209 case 'u':
2210 p = percent_op_utype;
2211 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
2212 break;
dc1e8a47 2213 rvc_lui:
e23eba97
NC		 2214 if (imm_expr->X_op != O_constant
2215 || imm_expr->X_add_number <= 0
2216 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
2217 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
2218 && (imm_expr->X_add_number <
2219 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
2220 break;
5a9f5403 2221 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
e23eba97
NC		 2222 goto rvc_imm_done;
2223 case 'v':
2224 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2225 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
2226 || ((int32_t)imm_expr->X_add_number
2227 != imm_expr->X_add_number))
2228 break;
2229 imm_expr->X_add_number =
2230 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
2231 goto rvc_lui;
2232 case 'p':
2233 goto branch;
2234 case 'a':
2235 goto jump;
0e35537d
JW		 2236 case 'S': /* Floating-point RS1 x8-x15. */
2237 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2238 || !(regno >= 8 && regno <= 15))
2239 break;
2240 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2241 continue;
e23eba97
NC		 2242 case 'D': /* Floating-point RS2 x8-x15. */
2243 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2244 || !(regno >= 8 && regno <= 15))
2245 break;
2246 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2247 continue;
2248 case 'T': /* Floating-point RS2. */
2249 if (!reg_lookup (&s, RCLASS_FPR, &regno))
2250 break;
2251 INSERT_OPERAND (CRS2, *ip, regno);
2252 continue;
0e35537d
JW		 2253 case 'F':
2254 switch (*++args)
2255 {
4765cd61
JW		 2256 case '6':
2257 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2258 || imm_expr->X_op != O_constant
2259 || imm_expr->X_add_number < 0
2260 || imm_expr->X_add_number >= 64)
2261 {
b800637e
NC		 2262 as_bad (_("bad value for compressed funct6 "
2263 "field, value must be 0...64"));
4765cd61
JW		 2264 break;
2265 }
4765cd61
JW		 2266 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
2267 imm_expr->X_op = O_absent;
2268 s = expr_end;
2269 continue;
1942a048 2270
0e35537d
JW		 2271 case '4':
2272 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2273 || imm_expr->X_op != O_constant
2274 || imm_expr->X_add_number < 0
2275 || imm_expr->X_add_number >= 16)
2276 {
b800637e
NC		 2277 as_bad (_("bad value for compressed funct4 "
2278 "field, value must be 0...15"));
0e35537d
JW		 2279 break;
2280 }
0e35537d
JW		 2281 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
2282 imm_expr->X_op = O_absent;
2283 s = expr_end;
2284 continue;
1942a048 2285
0e35537d
JW		 2286 case '3':
2287 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2288 || imm_expr->X_op != O_constant
2289 || imm_expr->X_add_number < 0
2290 || imm_expr->X_add_number >= 8)
2291 {
b800637e
NC		 2292 as_bad (_("bad value for compressed funct3 "
2293 "field, value must be 0...7"));
0e35537d
JW		 2294 break;
2295 }
2296 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
2297 imm_expr->X_op = O_absent;
2298 s = expr_end;
2299 continue;
1942a048 2300
4765cd61
JW		 2301 case '2':
2302 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2303 || imm_expr->X_op != O_constant
2304 || imm_expr->X_add_number < 0
2305 || imm_expr->X_add_number >= 4)
2306 {
b800637e
NC		 2307 as_bad (_("bad value for compressed funct2 "
2308 "field, value must be 0...3"));
4765cd61
JW		 2309 break;
2310 }
2311 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number);
2312 imm_expr->X_op = O_absent;
2313 s = expr_end;
2314 continue;
1942a048 2315
0e35537d 2316 default:
b800637e
NC		 2317 as_bad (_("internal: unknown compressed funct "
2318 "field specifier `CF%c'"), *args);
0e35537d
JW		 2319 }
2320 break;
2321
e23eba97 2322 default:
b800637e
NC		 2323 as_bad (_("internal: unknown compressed field "
2324 "specifier `C%c'"), *args);
e23eba97
NC		 2325 }
2326 break;
2327
2328 case ',':
2329 ++argnum;
2330 if (*s++ == *args)
2331 continue;
2332 s--;
2333 break;
2334
2335 case '(':
2336 case ')':
2337 case '[':
2338 case ']':
2339 if (*s++ == *args)
2340 continue;
2341 break;
2342
dcd709e0 2343 case '<': /* Shift amount, 0 - 31. */
e23eba97 2344 my_getExpression (imm_expr, s);
ca2fd32c 2345 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2346 if ((unsigned long) imm_expr->X_add_number > 31)
b800637e 2347 as_bad (_("improper shift amount (%lu)"),
94f78a77 2348 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2349 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
2350 imm_expr->X_op = O_absent;
2351 s = expr_end;
2352 continue;
2353
dcd709e0 2354 case '>': /* Shift amount, 0 - (XLEN-1). */
e23eba97 2355 my_getExpression (imm_expr, s);
ca2fd32c 2356 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2357 if ((unsigned long) imm_expr->X_add_number >= xlen)
b800637e 2358 as_bad (_("improper shift amount (%lu)"),
94f78a77 2359 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2360 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
2361 imm_expr->X_op = O_absent;
2362 s = expr_end;
2363 continue;
2364
dcd709e0 2365 case 'Z': /* CSRRxI immediate. */
e23eba97 2366 my_getExpression (imm_expr, s);
ca2fd32c 2367 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2368 if ((unsigned long) imm_expr->X_add_number > 31)
b800637e 2369 as_bad (_("improper CSRxI immediate (%lu)"),
94f78a77 2370 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2371 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
2372 imm_expr->X_op = O_absent;
2373 s = expr_end;
2374 continue;
2375
dcd709e0 2376 case 'E': /* Control register. */
54b2aec1 2377 insn_with_csr = TRUE;
1a79004f 2378 explicit_priv_attr = TRUE;
e23eba97
NC		 2379 if (reg_lookup (&s, RCLASS_CSR, &regno))
2380 INSERT_OPERAND (CSR, *ip, regno);
2381 else
2382 {
2383 my_getExpression (imm_expr, s);
ca2fd32c 2384 check_absolute_expr (ip, imm_expr, TRUE);
e23eba97 2385 if ((unsigned long) imm_expr->X_add_number > 0xfff)
b800637e 2386 as_bad (_("improper CSR address (%lu)"),
94f78a77 2387 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2388 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
2389 imm_expr->X_op = O_absent;
2390 s = expr_end;
2391 }
2392 continue;
2393
dcd709e0 2394 case 'm': /* Rounding mode. */
e23eba97
NC		 2395 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
2396 {
2397 INSERT_OPERAND (RM, *ip, regno);
2398 continue;
2399 }
2400 break;
2401
2402 case 'P':
dcd709e0 2403 case 'Q': /* Fence predecessor/successor. */
e23eba97
NC		 2404 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
2405 &regno))
2406 {
2407 if (*args == 'P')
2408 INSERT_OPERAND (PRED, *ip, regno);
2409 else
2410 INSERT_OPERAND (SUCC, *ip, regno);
2411 continue;
2412 }
2413 break;
2414
dcd709e0
NC		 2415 case 'd': /* Destination register. */
2416 case 's': /* Source register. */
2417 case 't': /* Target register. */
2418 case 'r': /* RS3 */
e23eba97
NC		 2419 if (reg_lookup (&s, RCLASS_GPR, &regno))
2420 {
2421 c = *args;
2422 if (*s == ' ')
2423 ++s;
2424
2425 /* Now that we have assembled one operand, we use the args
2426 string to figure out where it goes in the instruction. */
2427 switch (c)
2428 {
2429 case 's':
2430 INSERT_OPERAND (RS1, *ip, regno);
2431 break;
2432 case 'd':
2433 INSERT_OPERAND (RD, *ip, regno);
2434 break;
2435 case 't':
2436 INSERT_OPERAND (RS2, *ip, regno);
2437 break;
0e35537d
JW		 2438 case 'r':
2439 INSERT_OPERAND (RS3, *ip, regno);
2440 break;
e23eba97
NC		 2441 }
2442 continue;
2443 }
2444 break;
2445
dcd709e0
NC		 2446 case 'D': /* Floating point RD. */
2447 case 'S': /* Floating point RS1. */
2448 case 'T': /* Floating point RS2. */
2449 case 'U': /* Floating point RS1 and RS2. */
2450 case 'R': /* Floating point RS3. */
e23eba97
NC		 2451 if (reg_lookup (&s, RCLASS_FPR, &regno))
2452 {
2453 c = *args;
2454 if (*s == ' ')
2455 ++s;
2456 switch (c)
2457 {
2458 case 'D':
2459 INSERT_OPERAND (RD, *ip, regno);
2460 break;
2461 case 'S':
2462 INSERT_OPERAND (RS1, *ip, regno);
2463 break;
2464 case 'U':
2465 INSERT_OPERAND (RS1, *ip, regno);
dcd709e0 2466 /* Fall through. */
e23eba97
NC		 2467 case 'T':
2468 INSERT_OPERAND (RS2, *ip, regno);
2469 break;
2470 case 'R':
2471 INSERT_OPERAND (RS3, *ip, regno);
2472 break;
2473 }
2474 continue;
2475 }
e23eba97
NC		 2476 break;
2477
2478 case 'I':
2479 my_getExpression (imm_expr, s);
2480 if (imm_expr->X_op != O_big
2481 && imm_expr->X_op != O_constant)
2482 break;
2483 normalize_constant_expr (imm_expr);
2484 s = expr_end;
2485 continue;
2486
2487 case 'A':
2488 my_getExpression (imm_expr, s);
2489 normalize_constant_expr (imm_expr);
2490 /* The 'A' format specifier must be a symbol. */
2491 if (imm_expr->X_op != O_symbol)
2492 break;
2493 *imm_reloc = BFD_RELOC_32;
2494 s = expr_end;
2495 continue;
2496
160d1b3d
SH		 2497 case 'B':
2498 my_getExpression (imm_expr, s);
2499 normalize_constant_expr (imm_expr);
2500 /* The 'B' format specifier must be a symbol or a constant. */
2501 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
2502 break;
2503 if (imm_expr->X_op == O_symbol)
2504 *imm_reloc = BFD_RELOC_32;
2505 s = expr_end;
2506 continue;
2507
e23eba97 2508 case 'j': /* Sign-extended immediate. */
e23eba97 2509 p = percent_op_itype;
f50fabe4 2510 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
e23eba97
NC		 2511 goto alu_op;
2512 case 'q': /* Store displacement. */
2513 p = percent_op_stype;
2514 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
2515 goto load_store;
2516 case 'o': /* Load displacement. */
2517 p = percent_op_itype;
2518 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
2519 goto load_store;
dcd709e0
NC		 2520 case '1':
2521 /* This is used for TLS, where the fourth operand is
2522 %tprel_add, to get a relocation applied to an add
2523 instruction, for relaxation to use. */
e23eba97 2524 p = percent_op_rtype;
f50fabe4 2525 goto alu_op;
dcd709e0 2526 case '0': /* AMO displacement, which must be zero. */
f50fabe4 2527 p = percent_op_null;
dc1e8a47 2528 load_store:
f0531ed6 2529 if (riscv_handle_implicit_zero_offset (imm_expr, s))
e23eba97 2530 continue;
dc1e8a47 2531 alu_op:
e23eba97
NC		 2532 /* If this value won't fit into a 16 bit offset, then go
2533 find a macro that will generate the 32 bit offset
2534 code pattern. */
2535 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
2536 {
2537 normalize_constant_expr (imm_expr);
2538 if (imm_expr->X_op != O_constant
2539 || (*args == '0' && imm_expr->X_add_number != 0)
f50fabe4 2540 || (*args == '1')
e23eba97
NC		 2541 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
2542 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
2543 break;
2544 }
e23eba97
NC		 2545 s = expr_end;
2546 continue;
2547
dcd709e0 2548 case 'p': /* PC-relative offset. */
dc1e8a47 2549 branch:
e23eba97
NC		 2550 *imm_reloc = BFD_RELOC_12_PCREL;
2551 my_getExpression (imm_expr, s);
2552 s = expr_end;
2553 continue;
2554
dcd709e0 2555 case 'u': /* Upper 20 bits. */
e23eba97 2556 p = percent_op_utype;
4288405d 2557 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
e23eba97 2558 {
4288405d
JW		 2559 if (imm_expr->X_op != O_constant)
2560 break;
2561
e23eba97
NC		 2562 if (imm_expr->X_add_number < 0
2563 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
2564 as_bad (_("lui expression not in range 0..1048575"));
2565
2566 *imm_reloc = BFD_RELOC_RISCV_HI20;
2567 imm_expr->X_add_number <<= RISCV_IMM_BITS;
2568 }
2569 s = expr_end;
2570 continue;
2571
dcd709e0 2572 case 'a': /* 20-bit PC-relative offset. */
dc1e8a47 2573 jump:
e23eba97
NC		 2574 my_getExpression (imm_expr, s);
2575 s = expr_end;
2576 *imm_reloc = BFD_RELOC_RISCV_JMP;
2577 continue;
2578
2579 case 'c':
2580 my_getExpression (imm_expr, s);
2581 s = expr_end;
2582 if (strcmp (s, "@plt") == 0)
2583 {
2584 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2585 s += 4;
2586 }
2587 else
2588 *imm_reloc = BFD_RELOC_RISCV_CALL;
2589 continue;
1942a048 2590
0e35537d
JW		 2591 case 'O':
2592 switch (*++args)
2593 {
2594 case '4':
2595 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2596 || imm_expr->X_op != O_constant
2597 || imm_expr->X_add_number < 0
2598 || imm_expr->X_add_number >= 128
2599 || (imm_expr->X_add_number & 0x3) != 3)
2600 {
2601 as_bad (_("bad value for opcode field, "
2602 "value must be 0...127 and "
2603 "lower 2 bits must be 0x3"));
2604 break;
2605 }
0e35537d
JW		 2606 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2607 imm_expr->X_op = O_absent;
2608 s = expr_end;
2609 continue;
1942a048 2610
0e35537d
JW		 2611 case '2':
2612 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2613 || imm_expr->X_op != O_constant
2614 || imm_expr->X_add_number < 0
2615 || imm_expr->X_add_number >= 3)
2616 {
2617 as_bad (_("bad value for opcode field, "
2618 "value must be 0...2"));
2619 break;
2620 }
0e35537d
JW		 2621 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2622 imm_expr->X_op = O_absent;
2623 s = expr_end;
2624 continue;
1942a048 2625
0e35537d 2626 default:
b800637e
NC		 2627 as_bad (_("internal: unknown opcode field "
2628 "specifier `O%c'"), *args);
0e35537d
JW		 2629 }
2630 break;
2631
2632 case 'F':
2633 switch (*++args)
2634 {
2635 case '7':
2636 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2637 || imm_expr->X_op != O_constant
2638 || imm_expr->X_add_number < 0
2639 || imm_expr->X_add_number >= 128)
2640 {
2641 as_bad (_("bad value for funct7 field, "
2642 "value must be 0...127"));
2643 break;
2644 }
0e35537d
JW		 2645 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2646 imm_expr->X_op = O_absent;
2647 s = expr_end;
2648 continue;
1942a048 2649
0e35537d
JW		 2650 case '3':
2651 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2652 || imm_expr->X_op != O_constant
2653 || imm_expr->X_add_number < 0
2654 || imm_expr->X_add_number >= 8)
2655 {
2656 as_bad (_("bad value for funct3 field, "
2657 "value must be 0...7"));
2658 break;
2659 }
0e35537d
JW		 2660 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2661 imm_expr->X_op = O_absent;
2662 s = expr_end;
2663 continue;
1942a048 2664
0e35537d
JW		 2665 case '2':
2666 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2667 || imm_expr->X_op != O_constant
2668 || imm_expr->X_add_number < 0
2669 || imm_expr->X_add_number >= 4)
2670 {
2671 as_bad (_("bad value for funct2 field, "
2672 "value must be 0...3"));
2673 break;
2674 }
0e35537d
JW		 2675 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2676 imm_expr->X_op = O_absent;
2677 s = expr_end;
2678 continue;
2679
2680 default:
b800637e
NC		 2681 as_bad (_("internal: unknown funct field "
2682 "specifier `F%c'\n"), *args);
0e35537d
JW		 2683 }
2684 break;
e23eba97 2685
e925c834
JW		 2686 case 'z':
2687 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2688 || imm_expr->X_op != O_constant
2689 || imm_expr->X_add_number != 0)
2690 break;
2691 s = expr_end;
2692 imm_expr->X_op = O_absent;
2693 continue;
2694
e23eba97 2695 default:
b800637e 2696 as_fatal (_("internal: unknown argument type `%c'"), *args);
e23eba97
NC		 2697 }
2698 break;
2699 }
2700 s = argsStart;
2701 error = _("illegal operands");
54b2aec1 2702 insn_with_csr = FALSE;
e23eba97
NC		 2703 }
2704
dc1e8a47 2705 out:
e23eba97
NC		 2706 /* Restore the character we might have clobbered above. */
2707 if (save_c)
2708 *(argsStart - 1) = save_c;
2709
2710 return error;
2711}
2712
2713void
2714md_assemble (char *str)
2715{
2716 struct riscv_cl_insn insn;
2717 expressionS imm_expr;
2718 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2719
dcd709e0
NC		 2720 /* The architecture and privileged elf attributes should be set
2721 before assembling. */
8f595e9b
NC		 2722 if (!start_assemble)
2723 {
2724 start_assemble = TRUE;
e23eba97 2725
dcd709e0 2726 riscv_set_abi_by_arch ();
8f595e9b
NC		 2727 if (!riscv_set_default_priv_spec (NULL))
2728 return;
2729 }
2730
2731 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
2dc8dd17 2732
e23eba97
NC		 2733 if (error)
2734 {
2735 as_bad ("%s `%s'", error, str);
2736 return;
2737 }
2738
2739 if (insn.insn_mo->pinfo == INSN_MACRO)
2740 macro (&insn, &imm_expr, &imm_reloc);
2741 else
2742 append_insn (&insn, &imm_expr, imm_reloc);
2743}
2744
2745const char *
2746md_atof (int type, char *litP, int *sizeP)
2747{
2748 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2749}
2750
2751void
2752md_number_to_chars (char *buf, valueT val, int n)
2753{
fbc09e7a
MC		 2754 if (target_big_endian)
2755 number_to_chars_bigendian (buf, val, n);
2756 else
2757 number_to_chars_littleendian (buf, val, n);
e23eba97
NC		 2758}
2759
2760const char *md_shortopts = "O::g::G:";
2761
2762enum options
2763{
2922d21d 2764 OPTION_MARCH = OPTION_MD_BASE,
e23eba97
NC		 2765 OPTION_PIC,
2766 OPTION_NO_PIC,
2922d21d 2767 OPTION_MABI,
71060565
JW		 2768 OPTION_RELAX,
2769 OPTION_NO_RELAX,
2dc8dd17
JW		 2770 OPTION_ARCH_ATTR,
2771 OPTION_NO_ARCH_ATTR,
2ca89224
NC		 2772 OPTION_CSR_CHECK,
2773 OPTION_NO_CSR_CHECK,
8f595e9b
NC		 2774 OPTION_MISA_SPEC,
2775 OPTION_MPRIV_SPEC,
fbc09e7a
MC		 2776 OPTION_BIG_ENDIAN,
2777 OPTION_LITTLE_ENDIAN,
e23eba97
NC		 2778 OPTION_END_OF_ENUM
2779};
2780
2781struct option md_longopts[] =
2782{
e23eba97
NC		 2783 {"march", required_argument, NULL, OPTION_MARCH},
2784 {"fPIC", no_argument, NULL, OPTION_PIC},
2785 {"fpic", no_argument, NULL, OPTION_PIC},
2786 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2922d21d 2787 {"mabi", required_argument, NULL, OPTION_MABI},
71060565
JW		 2788 {"mrelax", no_argument, NULL, OPTION_RELAX},
2789 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2dc8dd17
JW		 2790 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
2791 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
2ca89224
NC		 2792 {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
2793 {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
8f595e9b
NC		 2794 {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
2795 {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
fbc09e7a
MC		 2796 {"mbig-endian", no_argument, NULL, OPTION_BIG_ENDIAN},
2797 {"mlittle-endian", no_argument, NULL, OPTION_LITTLE_ENDIAN},
e23eba97
NC		 2798
2799 {NULL, no_argument, NULL, 0}
2800};
2801size_t md_longopts_size = sizeof (md_longopts);
2802
e23eba97
NC		 2803int
2804md_parse_option (int c, const char *arg)
2805{
2806 switch (c)
2807 {
e23eba97 2808 case OPTION_MARCH:
8f595e9b 2809 default_arch_with_ext = arg;
e23eba97
NC		 2810 break;
2811
2812 case OPTION_NO_PIC:
2813 riscv_opts.pic = FALSE;
2814 break;
2815
2816 case OPTION_PIC:
2817 riscv_opts.pic = TRUE;
2818 break;
2819
2922d21d
AW		 2820 case OPTION_MABI:
2821 if (strcmp (arg, "ilp32") == 0)
7f999549
JW		 2822 riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
2823 else if (strcmp (arg, "ilp32e") == 0)
2824 riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
2922d21d 2825 else if (strcmp (arg, "ilp32f") == 0)
7f999549 2826 riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2827 else if (strcmp (arg, "ilp32d") == 0)
7f999549 2828 riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2829 else if (strcmp (arg, "ilp32q") == 0)
7f999549 2830 riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
2922d21d 2831 else if (strcmp (arg, "lp64") == 0)
7f999549 2832 riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
2922d21d 2833 else if (strcmp (arg, "lp64f") == 0)
7f999549 2834 riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2835 else if (strcmp (arg, "lp64d") == 0)
7f999549 2836 riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2837 else if (strcmp (arg, "lp64q") == 0)
7f999549 2838 riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
2922d21d
AW		 2839 else
2840 return 0;
6e1605e4 2841 explicit_mabi = TRUE;
2922d21d
AW		 2842 break;
2843
71060565
JW		 2844 case OPTION_RELAX:
2845 riscv_opts.relax = TRUE;
2846 break;
2847
2848 case OPTION_NO_RELAX:
2849 riscv_opts.relax = FALSE;
2850 break;
2851
2dc8dd17
JW		 2852 case OPTION_ARCH_ATTR:
2853 riscv_opts.arch_attr = TRUE;
2854 break;
2855
2856 case OPTION_NO_ARCH_ATTR:
2857 riscv_opts.arch_attr = FALSE;
2858 break;
2859
2ca89224
NC		 2860 case OPTION_CSR_CHECK:
2861 riscv_opts.csr_check = TRUE;
2862 break;
2863
2864 case OPTION_NO_CSR_CHECK:
2865 riscv_opts.csr_check = FALSE;
2866 break;
2867
8f595e9b
NC		 2868 case OPTION_MISA_SPEC:
2869 return riscv_set_default_isa_spec (arg);
2870
2871 case OPTION_MPRIV_SPEC:
2872 return riscv_set_default_priv_spec (arg);
2873
fbc09e7a
MC		 2874 case OPTION_BIG_ENDIAN:
2875 target_big_endian = 1;
2876 break;
2877
2878 case OPTION_LITTLE_ENDIAN:
2879 target_big_endian = 0;
2880 break;
2881
e23eba97
NC		 2882 default:
2883 return 0;
2884 }
2885
2886 return 1;
2887}
2888
2889void
2890riscv_after_parse_args (void)
2891{
dcd709e0
NC		 2892 /* The --with-arch is optional for now, so we still need to set the xlen
2893 according to the default_arch, which is set by the --target. */
e23eba97
NC		 2894 if (xlen == 0)
2895 {
2896 if (strcmp (default_arch, "riscv32") == 0)
2897 xlen = 32;
2898 else if (strcmp (default_arch, "riscv64") == 0)
2899 xlen = 64;
2900 else
2901 as_bad ("unknown default architecture `%s'", default_arch);
2902 }
8f595e9b
NC		 2903 if (default_arch_with_ext == NULL)
2904 default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
2905
2906 /* Initialize the hash table for extensions with default version. */
3d73d29e 2907 ext_version_hash = init_ext_version_hash ();
8f595e9b 2908
dcd709e0 2909 /* Set default specs. */
8f595e9b
NC		 2910 if (default_isa_spec == ISA_SPEC_CLASS_NONE)
2911 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
dcd709e0
NC		 2912 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
2913 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
2922d21d 2914
8f595e9b 2915 riscv_set_arch (default_arch_with_ext);
2922d21d
AW		 2916
2917 /* Add the RVC extension, regardless of -march, to support .option rvc. */
fecb9c46 2918 riscv_set_rvc (FALSE);
1080bf78 2919 if (riscv_subset_supports ("c"))
2922d21d 2920 riscv_set_rvc (TRUE);
2922d21d 2921
7f999549
JW		 2922 /* Enable RVE if specified by the -march option. */
2923 riscv_set_rve (FALSE);
1080bf78 2924 if (riscv_subset_supports ("e"))
7f999549
JW		 2925 riscv_set_rve (TRUE);
2926
0ac2b354
AB		 2927 /* If the CIE to be produced has not been overridden on the command line,
2928 then produce version 3 by default. This allows us to use the full
2929 range of registers in a .cfi_return_column directive. */
2930 if (flag_dwarf_cie_version == -1)
2931 flag_dwarf_cie_version = 3;
e23eba97
NC		 2932}
2933
2934long
2935md_pcrel_from (fixS *fixP)
2936{
2937 return fixP->fx_where + fixP->fx_frag->fr_address;
2938}
2939
2940/* Apply a fixup to the object file. */
2941
2942void
2943md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2944{
45f76423 2945 unsigned int subtype;
e23eba97 2946 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
45f76423 2947 bfd_boolean relaxable = FALSE;
c1b465c9 2948 offsetT loc;
a6cbf936 2949 segT sub_segment;
e23eba97
NC		 2950
2951 /* Remember value for tc_gen_reloc. */
2952 fixP->fx_addnumber = *valP;
2953
2954 switch (fixP->fx_r_type)
2955 {
e23eba97
NC		 2956 case BFD_RELOC_RISCV_HI20:
2957 case BFD_RELOC_RISCV_LO12_I:
2958 case BFD_RELOC_RISCV_LO12_S:
45f76423
AW		 2959 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2960 | bfd_getl32 (buf), buf);
a5ec5e3f
AW		 2961 if (fixP->fx_addsy == NULL)
2962 fixP->fx_done = TRUE;
45f76423
AW		 2963 relaxable = TRUE;
2964 break;
2965
2966 case BFD_RELOC_RISCV_GOT_HI20:
e23eba97
NC		 2967 case BFD_RELOC_RISCV_ADD8:
2968 case BFD_RELOC_RISCV_ADD16:
2969 case BFD_RELOC_RISCV_ADD32:
2970 case BFD_RELOC_RISCV_ADD64:
45f76423 2971 case BFD_RELOC_RISCV_SUB6:
e23eba97
NC		 2972 case BFD_RELOC_RISCV_SUB8:
2973 case BFD_RELOC_RISCV_SUB16:
2974 case BFD_RELOC_RISCV_SUB32:
2975 case BFD_RELOC_RISCV_SUB64:
45f76423
AW		 2976 case BFD_RELOC_RISCV_RELAX:
2977 break;
2978
2979 case BFD_RELOC_RISCV_TPREL_HI20:
2980 case BFD_RELOC_RISCV_TPREL_LO12_I:
2981 case BFD_RELOC_RISCV_TPREL_LO12_S:
2982 case BFD_RELOC_RISCV_TPREL_ADD:
2983 relaxable = TRUE;
2984 /* Fall through. */
2985
2986 case BFD_RELOC_RISCV_TLS_GOT_HI20:
2987 case BFD_RELOC_RISCV_TLS_GD_HI20:
2988 case BFD_RELOC_RISCV_TLS_DTPREL32:
2989 case BFD_RELOC_RISCV_TLS_DTPREL64:
e294484e
AW		 2990 if (fixP->fx_addsy != NULL)
2991 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2992 else
2993 as_bad_where (fixP->fx_file, fixP->fx_line,
2994 _("TLS relocation against a constant"));
e23eba97
NC		 2995 break;
2996
e23eba97 2997 case BFD_RELOC_32:
a6cbf936
KLC		 2998 /* Use pc-relative relocation for FDE initial location.
2999 The symbol address in .eh_frame may be adjusted in
3000 _bfd_elf_discard_section_eh_frame, and the content of
3001 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
3002 Therefore, we cannot insert a relocation whose addend symbol is
dcd709e0 3003 in .eh_frame. Othrewise, the value may be adjusted twice. */
a6cbf936
KLC		 3004 if (fixP->fx_addsy && fixP->fx_subsy
3005 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
3006 && strcmp (sub_segment->name, ".eh_frame") == 0
3007 && S_GET_VALUE (fixP->fx_subsy)
3008 == fixP->fx_frag->fr_address + fixP->fx_where)
3009 {
3010 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
3011 fixP->fx_subsy = NULL;
3012 break;
3013 }
3014 /* Fall through. */
3015 case BFD_RELOC_64:
e23eba97
NC		 3016 case BFD_RELOC_16:
3017 case BFD_RELOC_8:
45f76423 3018 case BFD_RELOC_RISCV_CFA:
e23eba97
NC		 3019 if (fixP->fx_addsy && fixP->fx_subsy)
3020 {
3021 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3022 fixP->fx_next->fx_addsy = fixP->fx_subsy;
3023 fixP->fx_next->fx_subsy = NULL;
3024 fixP->fx_next->fx_offset = 0;
3025 fixP->fx_subsy = NULL;
3026
3027 switch (fixP->fx_r_type)
3028 {
3029 case BFD_RELOC_64:
3030 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
3031 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
3032 break;
3033
3034 case BFD_RELOC_32:
3035 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
3036 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
3037 break;
3038
3039 case BFD_RELOC_16:
3040 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
3041 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
3042 break;
3043
3044 case BFD_RELOC_8:
3045 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
3046 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
073808ed 3047 break;
e23eba97 3048
45f76423
AW		 3049 case BFD_RELOC_RISCV_CFA:
3050 /* Load the byte to get the subtype. */
c1b465c9
KLC		 3051 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
3052 loc = fixP->fx_frag->fr_fix - (subtype & 7);
45f76423
AW		 3053 switch (subtype)
3054 {
3055 case DW_CFA_advance_loc1:
c1b465c9
KLC		 3056 fixP->fx_where = loc + 1;
3057 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 3058 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
3059 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
3060 break;
3061
3062 case DW_CFA_advance_loc2:
3063 fixP->fx_size = 2;
45f76423 3064 fixP->fx_next->fx_size = 2;
c1b465c9
KLC		 3065 fixP->fx_where = loc + 1;
3066 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 3067 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
3068 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
3069 break;
3070
3071 case DW_CFA_advance_loc4:
3072 fixP->fx_size = 4;
45f76423 3073 fixP->fx_next->fx_size = 4;
c1b465c9
KLC		 3074 fixP->fx_where = loc;
3075 fixP->fx_next->fx_where = loc;
45f76423
AW		 3076 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
3077 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
3078 break;
3079
3080 default:
3081 if (subtype < 0x80 && (subtype & 0x40))
3082 {
3083 /* DW_CFA_advance_loc */
2aece2ba
KLC		 3084 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
3085 fixP->fx_next->fx_frag = fixP->fx_frag;
45f76423
AW		 3086 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
3087 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
3088 }
3089 else
b800637e 3090 as_fatal (_("internal: bad CFA value #%d"), subtype);
45f76423
AW		 3091 break;
3092 }
3093 break;
3094
e23eba97
NC		 3095 default:
3096 /* This case is unreachable. */
3097 abort ();
3098 }
3099 }
3100 /* Fall through. */
3101
3102 case BFD_RELOC_RVA:
3103 /* If we are deleting this reloc entry, we must fill in the
3104 value now. This can happen if we have a .word which is not
3105 resolved when it appears but is later defined. */
3106 if (fixP->fx_addsy == NULL)
3107 {
3108 gas_assert (fixP->fx_size <= sizeof (valueT));
3109 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
3110 fixP->fx_done = 1;
3111 }
3112 break;
3113
3114 case BFD_RELOC_RISCV_JMP:
3115 if (fixP->fx_addsy)
3116 {
3117 /* Fill in a tentative value to improve objdump readability. */
3118 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3119 bfd_vma delta = target - md_pcrel_from (fixP);
5a9f5403 3120 bfd_putl32 (bfd_getl32 (buf) | ENCODE_JTYPE_IMM (delta), buf);
e23eba97
NC		 3121 }
3122 break;
3123
3124 case BFD_RELOC_12_PCREL:
3125 if (fixP->fx_addsy)
3126 {
3127 /* Fill in a tentative value to improve objdump readability. */
3128 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3129 bfd_vma delta = target - md_pcrel_from (fixP);
5a9f5403 3130 bfd_putl32 (bfd_getl32 (buf) | ENCODE_BTYPE_IMM (delta), buf);
e23eba97
NC		 3131 }
3132 break;
3133
3134 case BFD_RELOC_RISCV_RVC_BRANCH:
3135 if (fixP->fx_addsy)
3136 {
3137 /* Fill in a tentative value to improve objdump readability. */
3138 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3139 bfd_vma delta = target - md_pcrel_from (fixP);
5a9f5403 3140 bfd_putl16 (bfd_getl16 (buf) | ENCODE_CBTYPE_IMM (delta), buf);
e23eba97
NC		 3141 }
3142 break;
3143
3144 case BFD_RELOC_RISCV_RVC_JUMP:
3145 if (fixP->fx_addsy)
3146 {
3147 /* Fill in a tentative value to improve objdump readability. */
3148 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3149 bfd_vma delta = target - md_pcrel_from (fixP);
5a9f5403 3150 bfd_putl16 (bfd_getl16 (buf) | ENCODE_CJTYPE_IMM (delta), buf);
e23eba97
NC		 3151 }
3152 break;
3153
e23eba97
NC		 3154 case BFD_RELOC_RISCV_CALL:
3155 case BFD_RELOC_RISCV_CALL_PLT:
45f76423
AW		 3156 relaxable = TRUE;
3157 break;
3158
9d06997a 3159 case BFD_RELOC_RISCV_PCREL_HI20:
45f76423
AW		 3160 case BFD_RELOC_RISCV_PCREL_LO12_S:
3161 case BFD_RELOC_RISCV_PCREL_LO12_I:
9d06997a
PD		 3162 relaxable = riscv_opts.relax;
3163 break;
3164
e23eba97
NC		 3165 case BFD_RELOC_RISCV_ALIGN:
3166 break;
3167
3168 default:
3169 /* We ignore generic BFD relocations we don't know about. */
3170 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
b800637e 3171 as_fatal (_("internal: bad relocation #%d"), fixP->fx_r_type);
e23eba97 3172 }
45f76423 3173
e294484e
AW		 3174 if (fixP->fx_subsy != NULL)
3175 as_bad_where (fixP->fx_file, fixP->fx_line,
3176 _("unsupported symbol subtraction"));
3177
45f76423
AW		 3178 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3179 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
3180 {
3181 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3182 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
3183 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
b1b11e92 3184 fixP->fx_next->fx_size = 0;
45f76423
AW		 3185 }
3186}
3187
3188/* Because the value of .cfi_remember_state may changed after relaxation,
3189 we insert a fix to relocate it again in link-time. */
3190
3191void
3192riscv_pre_output_hook (void)
3193{
3194 const frchainS *frch;
72393fd1
JW		 3195 segT s;
3196
3197 /* Save the current segment info. */
3198 segT seg = now_seg;
3199 subsegT subseg = now_subseg;
45f76423
AW		 3200
3201 for (s = stdoutput->sections; s; s = s->next)
3202 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
3203 {
7cb7b948 3204 fragS *frag;
45f76423
AW		 3205
3206 for (frag = frch->frch_root; frag; frag = frag->fr_next)
3207 {
3208 if (frag->fr_type == rs_cfa)
3209 {
45f76423 3210 expressionS exp;
8d1015a8 3211 expressionS *symval;
45f76423 3212
8d1015a8 3213 symval = symbol_get_value_expression (frag->fr_symbol);
45f76423 3214 exp.X_op = O_subtract;
8d1015a8 3215 exp.X_add_symbol = symval->X_add_symbol;
45f76423 3216 exp.X_add_number = 0;
8d1015a8 3217 exp.X_op_symbol = symval->X_op_symbol;
45f76423 3218
72393fd1
JW		 3219 /* We must set the segment before creating a frag after all
3220 frag chains have been chained together. */
3221 subseg_set (s, frch->frch_subseg);
3222
c1b465c9 3223 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
45f76423
AW		 3224 BFD_RELOC_RISCV_CFA);
3225 }
3226 }
3227 }
72393fd1
JW		 3228
3229 /* Restore the original segment info. */
3230 subseg_set (seg, subseg);
e23eba97
NC		 3231}
3232
3233/* This structure is used to hold a stack of .option values. */
e23eba97
NC		 3234struct riscv_option_stack
3235{
3236 struct riscv_option_stack *next;
3237 struct riscv_set_options options;
3238};
3239
3240static struct riscv_option_stack *riscv_opts_stack;
3241
3242/* Handle the .option pseudo-op. */
3243
3244static void
3245s_riscv_option (int x ATTRIBUTE_UNUSED)
3246{
3247 char *name = input_line_pointer, ch;
3248
3249 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3250 ++input_line_pointer;
3251 ch = *input_line_pointer;
3252 *input_line_pointer = '\0';
3253
3254 if (strcmp (name, "rvc") == 0)
3255 riscv_set_rvc (TRUE);
3256 else if (strcmp (name, "norvc") == 0)
3257 riscv_set_rvc (FALSE);
3258 else if (strcmp (name, "pic") == 0)
3259 riscv_opts.pic = TRUE;
3260 else if (strcmp (name, "nopic") == 0)
3261 riscv_opts.pic = FALSE;
45f76423
AW		 3262 else if (strcmp (name, "relax") == 0)
3263 riscv_opts.relax = TRUE;
3264 else if (strcmp (name, "norelax") == 0)
3265 riscv_opts.relax = FALSE;
2ca89224
NC		 3266 else if (strcmp (name, "csr-check") == 0)
3267 riscv_opts.csr_check = TRUE;
3268 else if (strcmp (name, "no-csr-check") == 0)
3269 riscv_opts.csr_check = FALSE;
e23eba97
NC		 3270 else if (strcmp (name, "push") == 0)
3271 {
3272 struct riscv_option_stack *s;
3273
3274 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
3275 s->next = riscv_opts_stack;
3276 s->options = riscv_opts;
3277 riscv_opts_stack = s;
3278 }
3279 else if (strcmp (name, "pop") == 0)
3280 {
3281 struct riscv_option_stack *s;
3282
3283 s = riscv_opts_stack;
3284 if (s == NULL)
3285 as_bad (_(".option pop with no .option push"));
3286 else
3287 {
3288 riscv_opts = s->options;
3289 riscv_opts_stack = s->next;
3290 free (s);
3291 }
3292 }
3293 else
3294 {
b800637e 3295 as_warn (_("unrecognized .option directive: %s\n"), name);
e23eba97
NC		 3296 }
3297 *input_line_pointer = ch;
3298 demand_empty_rest_of_line ();
3299}
3300
3301/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3302 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3303 use in DWARF debug information. */
3304
3305static void
3306s_dtprel (int bytes)
3307{
3308 expressionS ex;
3309 char *p;
3310
3311 expression (&ex);
3312
3313 if (ex.X_op != O_symbol)
3314 {
b800637e 3315 as_bad (_("unsupported use of %s"), (bytes == 8
e23eba97
NC		 3316 ? ".dtpreldword"
3317 : ".dtprelword"));
3318 ignore_rest_of_line ();
3319 }
3320
3321 p = frag_more (bytes);
3322 md_number_to_chars (p, 0, bytes);
3323 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
3324 (bytes == 8
3325 ? BFD_RELOC_RISCV_TLS_DTPREL64
3326 : BFD_RELOC_RISCV_TLS_DTPREL32));
3327
3328 demand_empty_rest_of_line ();
3329}
3330
3331/* Handle the .bss pseudo-op. */
3332
3333static void
3334s_bss (int ignore ATTRIBUTE_UNUSED)
3335{
3336 subseg_set (bss_section, 0);
3337 demand_empty_rest_of_line ();
3338}
3339
e23eba97 3340static void
d115ab8e 3341riscv_make_nops (char *buf, bfd_vma bytes)
e23eba97 3342{
d115ab8e 3343 bfd_vma i = 0;
e23eba97 3344
e5b737de
AW		 3345 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3346 means we are not within a valid instruction sequence. It is thus safe
3347 to use a zero byte, even though that is not a valid instruction. */
3348 if (bytes % 2 == 1)
3349 buf[i++] = 0;
3350
3351 /* Use at most one 2-byte NOP. */
3352 if ((bytes - i) % 4 == 2)
e23eba97 3353 {
fbc09e7a 3354 number_to_chars_littleendian (buf + i, RVC_NOP, 2);
d115ab8e 3355 i += 2;
e23eba97
NC		 3356 }
3357
e5b737de 3358 /* Fill the remainder with 4-byte NOPs. */
d115ab8e 3359 for ( ; i < bytes; i += 4)
fbc09e7a 3360 number_to_chars_littleendian (buf + i, RISCV_NOP, 4);
d115ab8e 3361}
e23eba97 3362
d115ab8e
AW		 3363/* Called from md_do_align. Used to create an alignment frag in a
3364 code section by emitting a worst-case NOP sequence that the linker
3365 will later relax to the correct number of NOPs. We can't compute
3366 the correct alignment now because of other linker relaxations. */
3367
3368bfd_boolean
3369riscv_frag_align_code (int n)
3370{
e5b737de 3371 bfd_vma bytes = (bfd_vma) 1 << n;
36877bfb
JW		 3372 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
3373 bfd_vma worst_case_bytes = bytes - insn_alignment;
3374 char *nops;
ed0816bd 3375 expressionS ex;
d115ab8e 3376
36877bfb
JW		 3377 /* If we are moving to a smaller alignment than the instruction size, then no
3378 alignment is required. */
3379 if (bytes <= insn_alignment)
3380 return TRUE;
3381
d115ab8e
AW		 3382 /* When not relaxing, riscv_handle_align handles code alignment. */
3383 if (!riscv_opts.relax)
3384 return FALSE;
e23eba97 3385
e80ae190
JW		 3386 nops = frag_more (worst_case_bytes);
3387
ed0816bd
PD		 3388 ex.X_op = O_constant;
3389 ex.X_add_number = worst_case_bytes;
d115ab8e 3390
ed0816bd 3391 riscv_make_nops (nops, worst_case_bytes);
e23eba97 3392
ed0816bd
PD		 3393 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
3394 &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
e23eba97 3395
d115ab8e
AW		 3396 return TRUE;
3397}
e23eba97 3398
d115ab8e
AW		 3399/* Implement HANDLE_ALIGN. */
3400
3401void
3402riscv_handle_align (fragS *fragP)
3403{
3404 switch (fragP->fr_type)
3405 {
3406 case rs_align_code:
3407 /* When relaxing, riscv_frag_align_code handles code alignment. */
3408 if (!riscv_opts.relax)
3409 {
e80ae190
JW		 3410 bfd_signed_vma bytes = (fragP->fr_next->fr_address
3411 - fragP->fr_address - fragP->fr_fix);
3412 /* We have 4 byte uncompressed nops. */
3413 bfd_signed_vma size = 4;
3414 bfd_signed_vma excess = bytes % size;
3415 char *p = fragP->fr_literal + fragP->fr_fix;
3416
3417 if (bytes <= 0)
d115ab8e
AW		 3418 break;
3419
e80ae190
JW		 3420 /* Insert zeros or compressed nops to get 4 byte alignment. */
3421 if (excess)
3422 {
3423 riscv_make_nops (p, excess);
3424 fragP->fr_fix += excess;
3425 p += excess;
3426 }
3427
3428 /* Insert variable number of 4 byte uncompressed nops. */
3429 riscv_make_nops (p, size);
3430 fragP->fr_var = size;
d115ab8e
AW		 3431 }
3432 break;
3433
3434 default:
3435 break;
3436 }
e23eba97
NC		 3437}
3438
3439int
3440md_estimate_size_before_relax (fragS *fragp, asection *segtype)
3441{
3442 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
3443}
3444
3445/* Translate internal representation of relocation info to BFD target
3446 format. */
3447
3448arelent *
3449tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3450{
3451 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
3452
3453 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3454 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3455 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3456 reloc->addend = fixp->fx_addnumber;
3457
3458 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3459 if (reloc->howto == NULL)
3460 {
3461 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
3462 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
3463 {
3464 /* We don't have R_RISCV_8/16, but for this special case,
3465 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3466 return reloc;
3467 }
3468
3469 as_bad_where (fixp->fx_file, fixp->fx_line,
3470 _("cannot represent %s relocation in object file"),
3471 bfd_get_reloc_code_name (fixp->fx_r_type));
3472 return NULL;
3473 }
3474
3475 return reloc;
3476}
3477
3478int
3479riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
3480{
3481 if (RELAX_BRANCH_P (fragp->fr_subtype))
3482 {
3483 offsetT old_var = fragp->fr_var;
3484 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
3485 return fragp->fr_var - old_var;
3486 }
3487
3488 return 0;
3489}
3490
3491/* Expand far branches to multi-instruction sequences. */
3492
3493static void
3494md_convert_frag_branch (fragS *fragp)
3495{
3496 bfd_byte *buf;
3497 expressionS exp;
3498 fixS *fixp;
3499 insn_t insn;
3500 int rs1, reloc;
3501
3502 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
3503
3504 exp.X_op = O_symbol;
3505 exp.X_add_symbol = fragp->fr_symbol;
3506 exp.X_add_number = fragp->fr_offset;
3507
3508 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
3509
3510 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
3511 {
3512 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3513 {
3514 case 8:
3515 case 4:
3516 /* Expand the RVC branch into a RISC-V one. */
3517 insn = bfd_getl16 (buf);
3518 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
3519 if ((insn & MASK_C_J) == MATCH_C_J)
3520 insn = MATCH_JAL;
3521 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
3522 insn = MATCH_JAL | (X_RA << OP_SH_RD);
3523 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
3524 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
3525 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
3526 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
3527 else
3528 abort ();
3529 bfd_putl32 (insn, buf);
3530 break;
3531
3532 case 6:
3533 /* Invert the branch condition. Branch over the jump. */
3534 insn = bfd_getl16 (buf);
3535 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
5a9f5403 3536 insn |= ENCODE_CBTYPE_IMM (6);
e23eba97
NC		 3537 bfd_putl16 (insn, buf);
3538 buf += 2;
3539 goto jump;
3540
3541 case 2:
3542 /* Just keep the RVC branch. */
3543 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3544 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
3545 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3546 2, &exp, FALSE, reloc);
3547 buf += 2;
3548 goto done;
3549
3550 default:
1d65abb5 3551 abort ();
e23eba97
NC		 3552 }
3553 }
3554
3555 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3556 {
3557 case 8:
3558 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
3559
3560 /* Invert the branch condition. Branch over the jump. */
3561 insn = bfd_getl32 (buf);
3562 insn ^= MATCH_BEQ ^ MATCH_BNE;
5a9f5403 3563 insn |= ENCODE_BTYPE_IMM (8);
fbc09e7a 3564 bfd_putl32 (insn, buf);
e23eba97
NC		 3565 buf += 4;
3566
dc1e8a47 3567 jump:
e23eba97
NC		 3568 /* Jump to the target. */
3569 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3570 4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
fbc09e7a 3571 bfd_putl32 (MATCH_JAL, buf);
e23eba97
NC		 3572 buf += 4;
3573 break;
3574
3575 case 4:
3576 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3577 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
3578 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3579 4, &exp, FALSE, reloc);
3580 buf += 4;
3581 break;
3582
3583 default:
3584 abort ();
3585 }
3586
dc1e8a47 3587 done:
e23eba97
NC		 3588 fixp->fx_file = fragp->fr_file;
3589 fixp->fx_line = fragp->fr_line;
3590
3591 gas_assert (buf == (bfd_byte *)fragp->fr_literal
3592 + fragp->fr_fix + fragp->fr_var);
3593
3594 fragp->fr_fix += fragp->fr_var;
3595}
3596
3597/* Relax a machine dependent frag. This returns the amount by which
3598 the current size of the frag should change. */
3599
3600void
3601md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3602 fragS *fragp)
3603{
3604 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
3605 md_convert_frag_branch (fragp);
3606}
3607
3608void
3609md_show_usage (FILE *stream)
3610{
3611 fprintf (stream, _("\
3612RISC-V options:\n\
8f595e9b
NC		 3613 -fpic generate position-independent code\n\
3614 -fno-pic don't generate position-independent code (default)\n\
3615 -march=ISA set the RISC-V architecture\n\
3616 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3617 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3618 -mabi=ABI set the RISC-V ABI\n\
3619 -mrelax enable relax (default)\n\
3620 -mno-relax disable relax\n\
3621 -march-attr generate RISC-V arch attribute\n\
3622 -mno-arch-attr don't generate RISC-V arch attribute\n\
e23eba97
NC		 3623"));
3624}
3625
3626/* Standard calling conventions leave the CFA at SP on entry. */
dcd709e0 3627
e23eba97
NC		 3628void
3629riscv_cfi_frame_initial_instructions (void)
3630{
3631 cfi_add_CFA_def_cfa_register (X_SP);
3632}
3633
3634int
3635tc_riscv_regname_to_dw2regnum (char *regname)
3636{
3637 int reg;
3638
3639 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3640 return reg;
3641
3642 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3643 return reg + 32;
3644
4762fe62
AB		 3645 /* CSRs are numbered 4096 -> 8191. */
3646 if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
3647 return reg + 4096;
3648
e23eba97
NC		 3649 as_bad (_("unknown register `%s'"), regname);
3650 return -1;
3651}
3652
3653void
3654riscv_elf_final_processing (void)
3655{
6e1605e4 3656 riscv_set_abi_by_arch ();
e23eba97 3657 elf_elfheader (stdoutput)->e_flags |= elf_flags;
e23eba97
NC		 3658}
3659
3660/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3661 since these directives break relaxation when used with symbol deltas. */
3662
3663static void
3664s_riscv_leb128 (int sign)
3665{
3666 expressionS exp;
3667 char *save_in = input_line_pointer;
3668
3669 expression (&exp);
3670 if (exp.X_op != O_constant)
3671 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3672 demand_empty_rest_of_line ();
3673
3674 input_line_pointer = save_in;
3675 return s_leb128 (sign);
3676}
3677
0e35537d
JW		 3678/* Parse the .insn directive. */
3679
3680static void
3681s_riscv_insn (int x ATTRIBUTE_UNUSED)
3682{
3683 char *str = input_line_pointer;
3684 struct riscv_cl_insn insn;
3685 expressionS imm_expr;
3686 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3687 char save_c;
3688
3689 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3690 ++input_line_pointer;
3691
3692 save_c = *input_line_pointer;
3693 *input_line_pointer = '\0';
3694
3695 const char *error = riscv_ip (str, &insn, &imm_expr,
3696 &imm_reloc, insn_type_hash);
3697
3698 if (error)
3699 {
3700 as_bad ("%s `%s'", error, str);
3701 }
3702 else
3703 {
3704 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3705 append_insn (&insn, &imm_expr, imm_reloc);
3706 }
3707
3708 *input_line_pointer = save_c;
3709 demand_empty_rest_of_line ();
3710}
3711
dcd709e0
NC		 3712/* Update architecture and privileged elf attributes. If we don't set
3713 them, then try to output the default ones. */
2dc8dd17
JW		 3714
3715static void
8f595e9b 3716riscv_write_out_attrs (void)
2dc8dd17 3717{
8f595e9b 3718 const char *arch_str, *priv_str, *p;
dcd709e0
NC		 3719 /* versions[0]: major version.
3720 versions[1]: minor version.
3721 versions[2]: revision version. */
8f595e9b
NC		 3722 unsigned versions[3] = {0}, number = 0;
3723 unsigned int i;
2dc8dd17 3724
dcd709e0 3725 /* Re-write architecture elf attribute. */
8f595e9b 3726 arch_str = riscv_arch_str (xlen, &riscv_subsets);
2dc8dd17 3727 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
1942a048 3728 xfree ((void *) arch_str);
8f595e9b
NC		 3729
3730 /* For the file without any instruction, we don't set the default_priv_spec
dcd709e0
NC		 3731 according to the privileged elf attributes since the md_assemble isn't
3732 called. */
8f595e9b
NC		 3733 if (!start_assemble
3734 && !riscv_set_default_priv_spec (NULL))
3735 return;
3736
dcd709e0
NC		 3737 /* If we already have set privileged elf attributes, then no need to do
3738 anything. Otherwise, don't generate or update them when no CSR and
3739 privileged instructions are used. */
1a79004f 3740 if (!explicit_priv_attr)
3fc6c3dc
NC		 3741 return;
3742
3d73d29e 3743 RISCV_GET_PRIV_SPEC_NAME (priv_str, default_priv_spec);
8f595e9b
NC		 3744 p = priv_str;
3745 for (i = 0; *p; ++p)
3746 {
3747 if (*p == '.' && i < 3)
3748 {
3749 versions[i++] = number;
3750 number = 0;
3751 }
3752 else if (ISDIGIT (*p))
3753 number = (number * 10) + (*p - '0');
3754 else
3755 {
b800637e 3756 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str);
8f595e9b
NC		 3757 return;
3758 }
3759 }
3760 versions[i] = number;
3761
dcd709e0 3762 /* Re-write privileged elf attributes. */
8f595e9b
NC		 3763 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
3764 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
3765 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
2dc8dd17
JW		 3766}
3767
dcd709e0 3768/* Add the default contents for the .riscv.attributes section. */
2dc8dd17
JW		 3769
3770static void
3771riscv_set_public_attributes (void)
3772{
8f595e9b
NC		 3773 if (riscv_opts.arch_attr || explicit_attr)
3774 riscv_write_out_attrs ();
2dc8dd17
JW		 3775}
3776
3777/* Called after all assembly has been done. */
3778
3779void
3780riscv_md_end (void)
3781{
3782 riscv_set_public_attributes ();
3783}
3784
3785/* Given a symbolic attribute NAME, return the proper integer value.
3786 Returns -1 if the attribute is not known. */
3787
3788int
3789riscv_convert_symbolic_attribute (const char *name)
3790{
3791 static const struct
3792 {
1942a048
NC		 3793 const char *name;
3794 const int tag;
2dc8dd17
JW		 3795 }
3796 attribute_table[] =
1942a048
NC		 3797 {
3798 /* When you modify this table you should
3799 also modify the list in doc/c-riscv.texi. */
3800#define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3801 T(arch),
3802 T(priv_spec),
3803 T(priv_spec_minor),
3804 T(priv_spec_revision),
3805 T(unaligned_access),
3806 T(stack_align),
2dc8dd17 3807#undef T
1942a048 3808 };
2dc8dd17
JW		 3809
3810 if (name == NULL)
3811 return -1;
3812
1942a048 3813 unsigned int i;
2dc8dd17
JW		 3814 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
3815 if (strcmp (name, attribute_table[i].name) == 0)
3816 return attribute_table[i].tag;
3817
3818 return -1;
3819}
3820
3821/* Parse a .attribute directive. */
3822
3823static void
3824s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
3825{
3826 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
8f595e9b
NC		 3827 unsigned old_xlen;
3828 obj_attribute *attr;
2dc8dd17 3829
8f595e9b
NC		 3830 explicit_attr = TRUE;
3831 switch (tag)
2dc8dd17 3832 {
8f595e9b
NC		 3833 case Tag_RISCV_arch:
3834 old_xlen = xlen;
2dc8dd17
JW		 3835 attr = elf_known_obj_attributes_proc (stdoutput);
3836 if (!start_assemble)
3837 riscv_set_arch (attr[Tag_RISCV_arch].s);
3838 else
b800637e
NC		 3839 as_fatal (_("architecture elf attributes must set before "
3840 "any instructions"));
2dc8dd17
JW		 3841
3842 if (old_xlen != xlen)
3843 {
3844 /* We must re-init bfd again if xlen is changed. */
3845 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
3846 bfd_find_target (riscv_target_format (), stdoutput);
3847
3848 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
b800637e 3849 as_warn (_("could not set architecture and machine"));
2dc8dd17 3850 }
8f595e9b
NC		 3851 break;
3852
3853 case Tag_RISCV_priv_spec:
3854 case Tag_RISCV_priv_spec_minor:
3855 case Tag_RISCV_priv_spec_revision:
3856 if (start_assemble)
b800637e
NC		 3857 as_fatal (_("privileged elf attributes must set before "
3858 "any instructions"));
8f595e9b
NC		 3859 break;
3860
3861 default:
3862 break;
2dc8dd17
JW		 3863 }
3864}
3865
dcd709e0 3866/* RISC-V pseudo-ops table. */
e23eba97
NC		 3867static const pseudo_typeS riscv_pseudo_table[] =
3868{
e23eba97
NC		 3869 {"option", s_riscv_option, 0},
3870 {"half", cons, 2},
3871 {"word", cons, 4},
3872 {"dword", cons, 8},
3873 {"dtprelword", s_dtprel, 4},
3874 {"dtpreldword", s_dtprel, 8},
3875 {"bss", s_bss, 0},
e23eba97
NC		 3876 {"uleb128", s_riscv_leb128, 0},
3877 {"sleb128", s_riscv_leb128, 1},
0e35537d 3878 {"insn", s_riscv_insn, 0},
2dc8dd17 3879 {"attribute", s_riscv_attribute, 0},
e23eba97
NC		 3880
3881 { NULL, NULL, 0 },
3882};
3883
3884void
3885riscv_pop_insert (void)
3886{
3887 extern void pop_insert (const pseudo_typeS *);
3888
3889 pop_insert (riscv_pseudo_table);
3890}
GDB Binutils - Deliverables
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