projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Move struc-symbol.h to symbols.c
[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
CommitLineData
e23eba97 1/* tc-riscv.c -- RISC-V assembler
219d1afa 2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
32#include "elf/riscv.h"
33#include "opcode/riscv.h"
34
35#include <stdint.h>
36
37/* Information about an instruction, including its format, operands
38 and fixups. */
39struct riscv_cl_insn
40{
41 /* The opcode's entry in riscv_opcodes. */
42 const struct riscv_opcode *insn_mo;
43
44 /* The encoded instruction bits. */
45 insn_t insn_opcode;
46
47 /* The frag that contains the instruction. */
48 struct frag *frag;
49
50 /* The offset into FRAG of the first instruction byte. */
51 long where;
52
53 /* The relocs associated with the instruction, if any. */
54 fixS *fixp;
55};
56
57#ifndef DEFAULT_ARCH
58#define DEFAULT_ARCH "riscv64"
59#endif
60
61static const char default_arch[] = DEFAULT_ARCH;
62
2922d21d
AW		 63static unsigned xlen = 0; /* width of an x-register */
64static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
7f999549 65static bfd_boolean rve_abi = FALSE;
e23eba97 66
2922d21d 67#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
e23eba97
NC		 68#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
69
70static unsigned elf_flags = 0;
71
72/* This is the set of options which the .option pseudo-op may modify. */
73
74struct riscv_set_options
75{
76 int pic; /* Generate position-independent code. */
77 int rvc; /* Generate RVC code. */
7f999549 78 int rve; /* Generate RVE code. */
45f76423 79 int relax; /* Emit relocs the linker is allowed to relax. */
e23eba97
NC		 80};
81
82static struct riscv_set_options riscv_opts =
83{
84 0, /* pic */
85 0, /* rvc */
7f999549 86 0, /* rve */
45f76423 87 1, /* relax */
e23eba97
NC		 88};
89
90static void
91riscv_set_rvc (bfd_boolean rvc_value)
92{
93 if (rvc_value)
94 elf_flags |= EF_RISCV_RVC;
95
96 riscv_opts.rvc = rvc_value;
97}
98
7f999549
JW		 99static void
100riscv_set_rve (bfd_boolean rve_value)
101{
102 riscv_opts.rve = rve_value;
103}
104
e23eba97
NC		 105struct riscv_subset
106{
107 const char *name;
108
109 struct riscv_subset *next;
110};
111
112static struct riscv_subset *riscv_subsets;
113
114static bfd_boolean
43135d3b 115riscv_subset_supports (unsigned xlen_required, const char *feature)
e23eba97
NC		 116{
117 struct riscv_subset *s;
e23eba97
NC		 118
119 if (xlen_required && xlen != xlen_required)
120 return FALSE;
121
122 for (s = riscv_subsets; s != NULL; s = s->next)
43135d3b 123 if (strcasecmp (s->name, feature) == 0)
e23eba97
NC		 124 return TRUE;
125
126 return FALSE;
127}
128
43135d3b
JW		 129static bfd_boolean
130riscv_multi_subset_supports (unsigned xlen_required, const char *features[])
131{
132 unsigned i = 0;
133 bfd_boolean supported = TRUE;
134
135 for (;features[i]; ++i)
136 supported = supported && riscv_subset_supports (xlen_required, features[i]);
137
138 return supported;
139}
140
fecb9c46
PD		 141static void
142riscv_clear_subsets (void)
143{
144 while (riscv_subsets != NULL)
145 {
146 struct riscv_subset *next = riscv_subsets->next;
c41cf6fd 147 free ((void *) riscv_subsets->name);
fecb9c46
PD		 148 free (riscv_subsets);
149 riscv_subsets = next;
150 }
151}
152
e23eba97
NC		 153static void
154riscv_add_subset (const char *subset)
155{
156 struct riscv_subset *s = xmalloc (sizeof *s);
157
158 s->name = xstrdup (subset);
159 s->next = riscv_subsets;
160 riscv_subsets = s;
161}
162
2922d21d 163/* Set which ISA and extensions are available. */
e23eba97 164
e23eba97 165static void
2922d21d 166riscv_set_arch (const char *s)
e23eba97 167{
a8086704
AW		 168 const char *all_subsets = "imafdqc";
169 char *extension = NULL;
2922d21d 170 const char *p = s;
e23eba97 171
fecb9c46
PD		 172 riscv_clear_subsets();
173
2922d21d 174 if (strncmp (p, "rv32", 4) == 0)
e23eba97
NC		 175 {
176 xlen = 32;
177 p += 4;
178 }
2922d21d 179 else if (strncmp (p, "rv64", 4) == 0)
e23eba97
NC		 180 {
181 xlen = 64;
182 p += 4;
183 }
2922d21d
AW		 184 else
185 as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s);
e23eba97 186
2922d21d 187 switch (*p)
e23eba97 188 {
2922d21d 189 case 'i':
e23eba97
NC		 190 break;
191
7f999549
JW		 192 case 'e':
193 p++;
194 riscv_add_subset ("e");
195 riscv_add_subset ("i");
196
197 if (xlen > 32)
198 as_fatal ("-march=%s: rv%de is not a valid base ISA", s, xlen);
199
200 break;
201
2922d21d 202 case 'g':
e23eba97 203 p++;
a8086704 204 for ( ; *all_subsets != 'q'; all_subsets++)
e23eba97 205 {
2922d21d 206 const char subset[] = {*all_subsets, '\0'};
e23eba97
NC		 207 riscv_add_subset (subset);
208 }
209 break;
210
211 default:
7f999549 212 as_fatal ("-march=%s: first ISA subset must be `e', `i' or `g'", s);
e23eba97
NC		 213 }
214
215 while (*p)
216 {
2922d21d 217 if (*p == 'x')
e23eba97 218 {
a8086704
AW		 219 char *subset = xstrdup (p);
220 char *q = subset;
e23eba97
NC		 221
222 while (*++q != '\0' && *q != '_')
223 ;
224 *q = '\0';
225
226 if (extension)
2922d21d
AW		 227 as_fatal ("-march=%s: only one non-standard extension is supported"
228 " (found `%s' and `%s')", s, extension, subset);
e23eba97
NC		 229 extension = subset;
230 riscv_add_subset (subset);
231 p += strlen (subset);
e23eba97
NC		 232 }
233 else if (*p == '_')
234 p++;
235 else if ((all_subsets = strchr (all_subsets, *p)) != NULL)
236 {
237 const char subset[] = {*p, 0};
238 riscv_add_subset (subset);
e23eba97
NC		 239 all_subsets++;
240 p++;
241 }
242 else
2922d21d 243 as_fatal ("-march=%s: unsupported ISA subset `%c'", s, *p);
e23eba97 244 }
a8086704 245
43135d3b 246 if (riscv_subset_supports (0, "e") && riscv_subset_supports (0, "f"))
7f999549
JW		 247 as_fatal ("-march=%s: rv32e does not support the `f' extension", s);
248
43135d3b 249 if (riscv_subset_supports (0, "d") && !riscv_subset_supports (0, "f"))
7f999549
JW		 250 as_fatal ("-march=%s: `d' extension requires `f' extension", s);
251
43135d3b 252 if (riscv_subset_supports (0, "q") && !riscv_subset_supports (0, "d"))
7f999549
JW		 253 as_fatal ("-march=%s: `q' extension requires `d' extension", s);
254
43135d3b 255 if (riscv_subset_supports (0, "q") && xlen < 64)
7f999549
JW		 256 as_fatal ("-march=%s: rv32 does not support the `q' extension", s);
257
a8086704 258 free (extension);
e23eba97
NC		 259}
260
261/* Handle of the OPCODE hash table. */
262static struct hash_control *op_hash = NULL;
263
0e35537d
JW		 264/* Handle of the type of .insn hash table. */
265static struct hash_control *insn_type_hash = NULL;
266
e23eba97
NC		 267/* This array holds the chars that always start a comment. If the
268 pre-processor is disabled, these aren't very useful */
269const char comment_chars[] = "#";
270
271/* This array holds the chars that only start a comment at the beginning of
272 a line. If the line seems to have the form '# 123 filename'
273 .line and .file directives will appear in the pre-processed output */
274/* Note that input_file.c hand checks for '#' at the beginning of the
275 first line of the input file. This is because the compiler outputs
276 #NO_APP at the beginning of its output. */
277/* Also note that C style comments are always supported. */
278const char line_comment_chars[] = "#";
279
280/* This array holds machine specific line separator characters. */
281const char line_separator_chars[] = ";";
282
283/* Chars that can be used to separate mant from exp in floating point nums */
284const char EXP_CHARS[] = "eE";
285
286/* Chars that mean this number is a floating point constant */
287/* As in 0f12.456 */
288/* or 0d1.2345e12 */
289const char FLT_CHARS[] = "rRsSfFdDxXpP";
290
291/* Macros for encoding relaxation state for RVC branches and far jumps. */
292#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
293 ((relax_substateT) \
294 (0xc0000000 \
295 | ((uncond) ? 1 : 0) \
296 | ((rvc) ? 2 : 0) \
297 | ((length) << 2)))
298#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
299#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
300#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
301#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
302
303/* Is the given value a sign-extended 32-bit value? */
304#define IS_SEXT_32BIT_NUM(x) \
305 (((x) &~ (offsetT) 0x7fffffff) == 0 \
306 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
307
308/* Is the given value a zero-extended 32-bit value? Or a negated one? */
309#define IS_ZEXT_32BIT_NUM(x) \
310 (((x) &~ (offsetT) 0xffffffff) == 0 \
311 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
312
313/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
314 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
315#define INSERT_OPERAND(FIELD, INSN, VALUE) \
316 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
317
318/* Determine if an instruction matches an opcode. */
319#define OPCODE_MATCHES(OPCODE, OP) \
320 (((OPCODE) & MASK_##OP) == MATCH_##OP)
321
322static char *expr_end;
323
324/* The default target format to use. */
325
326const char *
327riscv_target_format (void)
328{
329 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
330}
331
332/* Return the length of instruction INSN. */
333
334static inline unsigned int
335insn_length (const struct riscv_cl_insn *insn)
336{
337 return riscv_insn_length (insn->insn_opcode);
338}
339
340/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
341
342static void
343create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
344{
345 insn->insn_mo = mo;
346 insn->insn_opcode = mo->match;
347 insn->frag = NULL;
348 insn->where = 0;
349 insn->fixp = NULL;
350}
351
352/* Install INSN at the location specified by its "frag" and "where" fields. */
353
354static void
355install_insn (const struct riscv_cl_insn *insn)
356{
357 char *f = insn->frag->fr_literal + insn->where;
358 md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
359}
360
361/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
362 and install the opcode in the new location. */
363
364static void
365move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
366{
367 insn->frag = frag;
368 insn->where = where;
369 if (insn->fixp != NULL)
370 {
371 insn->fixp->fx_frag = frag;
372 insn->fixp->fx_where = where;
373 }
374 install_insn (insn);
375}
376
377/* Add INSN to the end of the output. */
378
379static void
380add_fixed_insn (struct riscv_cl_insn *insn)
381{
382 char *f = frag_more (insn_length (insn));
383 move_insn (insn, frag_now, f - frag_now->fr_literal);
384}
385
386static void
387add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
388 relax_substateT subtype, symbolS *symbol, offsetT offset)
389{
390 frag_grow (max_chars);
391 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
392 frag_var (rs_machine_dependent, max_chars, var,
393 subtype, symbol, offset, NULL);
394}
395
396/* Compute the length of a branch sequence, and adjust the stored length
397 accordingly. If FRAGP is NULL, the worst-case length is returned. */
398
399static unsigned
400relaxed_branch_length (fragS *fragp, asection *sec, int update)
401{
402 int jump, rvc, length = 8;
403
404 if (!fragp)
405 return length;
406
407 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
408 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
409 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
410
411 /* Assume jumps are in range; the linker will catch any that aren't. */
412 length = jump ? 4 : 8;
413
414 if (fragp->fr_symbol != NULL
415 && S_IS_DEFINED (fragp->fr_symbol)
01156111 416 && !S_IS_WEAK (fragp->fr_symbol)
e23eba97
NC		 417 && sec == S_GET_SEGMENT (fragp->fr_symbol))
418 {
419 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
420 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
421 val -= fragp->fr_address + fragp->fr_fix;
422
423 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
424 length = 2;
425 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
426 length = 4;
427 else if (!jump && rvc)
428 length = 6;
429 }
430
431 if (update)
432 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
433
434 return length;
435}
436
0e35537d
JW		 437/* Information about an opcode name, mnemonics and its value. */
438struct opcode_name_t
439{
440 const char *name;
441 unsigned int val;
442};
443
444/* List for all supported opcode name. */
445static const struct opcode_name_t opcode_name_list[] =
446{
447 {"C0", 0x0},
448 {"C1", 0x1},
449 {"C2", 0x2},
450
451 {"LOAD", 0x03},
452 {"LOAD_FP", 0x07},
453 {"CUSTOM_0", 0x0b},
454 {"MISC_MEM", 0x0f},
455 {"OP_IMM", 0x13},
456 {"AUIPC", 0x17},
457 {"OP_IMM_32", 0x1b},
458 /* 48b 0x1f. */
459
460 {"STORE", 0x23},
461 {"STORE_FP", 0x27},
462 {"CUSTOM_1", 0x2b},
463 {"AMO", 0x2f},
464 {"OP", 0x33},
465 {"LUI", 0x37},
466 {"OP_32", 0x3b},
467 /* 64b 0x3f. */
468
469 {"MADD", 0x43},
470 {"MSUB", 0x47},
471 {"NMADD", 0x4f},
472 {"NMSUB", 0x4b},
473 {"OP_FP", 0x53},
474 /*reserved 0x57. */
475 {"CUSTOM_2", 0x5b},
476 /* 48b 0x5f. */
477
478 {"BRANCH", 0x63},
479 {"JALR", 0x67},
480 /*reserved 0x5b. */
481 {"JAL", 0x6f},
482 {"SYSTEM", 0x73},
483 /*reserved 0x77. */
484 {"CUSTOM_3", 0x7b},
485 /* >80b 0x7f. */
486
487 {NULL, 0}
488};
489
490/* Hash table for lookup opcode name. */
491static struct hash_control *opcode_names_hash = NULL;
492
493/* Initialization for hash table of opcode name. */
494static void
495init_opcode_names_hash (void)
496{
497 const char *retval;
498 const struct opcode_name_t *opcode;
499
500 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
501 {
502 retval = hash_insert (opcode_names_hash, opcode->name, (void *)opcode);
503
504 if (retval != NULL)
505 as_fatal (_("internal error: can't hash `%s': %s"),
506 opcode->name, retval);
507 }
508}
509
510/* Find `s` is a valid opcode name or not,
511 return the opcode name info if found. */
512static const struct opcode_name_t *
513opcode_name_lookup (char **s)
514{
515 char *e;
516 char save_c;
517 struct opcode_name_t *o;
518
519 /* Find end of name. */
520 e = *s;
521 if (is_name_beginner (*e))
522 ++e;
523 while (is_part_of_name (*e))
524 ++e;
525
526 /* Terminate name. */
527 save_c = *e;
528 *e = '\0';
529
530 o = (struct opcode_name_t *) hash_find (opcode_names_hash, *s);
531
532 /* Advance to next token if one was recognized. */
533 if (o)
534 *s = e;
535
536 *e = save_c;
537 expr_end = e;
538
539 return o;
540}
541
e23eba97
NC		 542struct regname
543{
544 const char *name;
545 unsigned int num;
546};
547
548enum reg_class
549{
550 RCLASS_GPR,
551 RCLASS_FPR,
552 RCLASS_CSR,
553 RCLASS_MAX
554};
555
556static struct hash_control *reg_names_hash = NULL;
557
558#define ENCODE_REG_HASH(cls, n) \
559 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
560#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
561#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
562
563static void
564hash_reg_name (enum reg_class class, const char *name, unsigned n)
565{
566 void *hash = ENCODE_REG_HASH (class, n);
567 const char *retval = hash_insert (reg_names_hash, name, hash);
568
569 if (retval != NULL)
570 as_fatal (_("internal error: can't hash `%s': %s"), name, retval);
571}
572
573static void
574hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
575{
576 unsigned i;
577
578 for (i = 0; i < n; i++)
579 hash_reg_name (class, names[i], i);
580}
581
582static unsigned int
583reg_lookup_internal (const char *s, enum reg_class class)
584{
585 struct regname *r = (struct regname *) hash_find (reg_names_hash, s);
586
587 if (r == NULL || DECODE_REG_CLASS (r) != class)
588 return -1;
7f999549
JW		 589
590 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
591 return -1;
592
e23eba97
NC		 593 return DECODE_REG_NUM (r);
594}
595
596static bfd_boolean
597reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
598{
599 char *e;
600 char save_c;
601 int reg = -1;
602
603 /* Find end of name. */
604 e = *s;
605 if (is_name_beginner (*e))
606 ++e;
607 while (is_part_of_name (*e))
608 ++e;
609
610 /* Terminate name. */
611 save_c = *e;
612 *e = '\0';
613
614 /* Look for the register. Advance to next token if one was recognized. */
615 if ((reg = reg_lookup_internal (*s, class)) >= 0)
616 *s = e;
617
618 *e = save_c;
619 if (regnop)
620 *regnop = reg;
621 return reg >= 0;
622}
623
624static bfd_boolean
625arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
626{
627 const char *p = strchr (*s, ',');
628 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
629
bfb218e3
JW		 630 if (len == 0)
631 return FALSE;
632
e23eba97
NC		 633 for (i = 0; i < size; i++)
634 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
635 {
636 *regnop = i;
637 *s += len;
638 return TRUE;
639 }
640
641 return FALSE;
642}
643
644/* For consistency checking, verify that all bits are specified either
645 by the match/mask part of the instruction definition, or by the
0e35537d
JW		 646 operand list.
647
648 `length` could be 0, 4 or 8, 0 for auto detection. */
e23eba97 649static bfd_boolean
0e35537d 650validate_riscv_insn (const struct riscv_opcode *opc, int length)
e23eba97
NC		 651{
652 const char *p = opc->args;
653 char c;
654 insn_t used_bits = opc->mask;
0e35537d
JW		 655 int insn_width;
656 insn_t required_bits;
657
658 if (length == 0)
659 insn_width = 8 * riscv_insn_length (opc->match);
660 else
661 insn_width = 8 * length;
662
663 required_bits = ~0ULL >> (64 - insn_width);
e23eba97
NC		 664
665 if ((used_bits & opc->match) != (opc->match & required_bits))
666 {
667 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
668 opc->name, opc->args);
669 return FALSE;
670 }
671
672#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
673 while (*p)
674 switch (c = *p++)
675 {
676 case 'C': /* RVC */
677 switch (c = *p++)
678 {
1d65abb5 679 case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
e23eba97
NC		 680 case 'c': break; /* RS1, constrained to equal sp */
681 case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
1d65abb5 682 case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
b416fe87 683 case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
1d65abb5
AW		 684 case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
685 case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
686 case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
687 case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
688 case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
e23eba97
NC		 689 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
690 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
1d65abb5
AW		 691 case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
692 case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
e23eba97
NC		 693 case 'w': break; /* RS1S, constrained to equal RD */
694 case 'x': break; /* RS2S, constrained to equal RD */
1d65abb5
AW		 695 case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
696 case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
697 case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
698 case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
e23eba97
NC		 699 case 'U': break; /* RS1, constrained to equal RD */
700 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1d65abb5
AW		 701 case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
702 case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
0e35537d
JW		 703 case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
704 case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
e23eba97
NC		 705 case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
706 case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
0e35537d
JW		 707 case 'F': /* funct */
708 switch (c = *p++)
709 {
710 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
711 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
712 default:
713 as_bad (_("internal: bad RISC-V opcode"
714 " (unknown operand type `CF%c'): %s %s"),
715 c, opc->name, opc->args);
716 return FALSE;
717 }
718 break;
e23eba97
NC		 719 default:
720 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
721 c, opc->name, opc->args);
722 return FALSE;
723 }
724 break;
725 case ',': break;
726 case '(': break;
727 case ')': break;
728 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
729 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
730 case 'A': break;
731 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
732 case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
733 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
734 case 'I': break;
735 case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
736 case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
737 case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */
738 case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
739 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
740 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
741 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
742 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
0e35537d 743 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
e23eba97
NC		 744 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
745 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
746 case 'o':
1d65abb5
AW		 747 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
748 case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
749 case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
750 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
751 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
e925c834 752 case 'z': break;
e23eba97
NC		 753 case '[': break;
754 case ']': break;
755 case '0': break;
0e35537d
JW		 756 case 'F': /* funct */
757 switch (c = *p++)
758 {
759 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
760 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
761 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
762 default:
763 as_bad (_("internal: bad RISC-V opcode"
764 " (unknown operand type `F%c'): %s %s"),
765 c, opc->name, opc->args);
766 return FALSE;
767 }
768 break;
769 case 'O': /* opcode */
770 switch (c = *p++)
771 {
772 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
773 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
774 default:
775 as_bad (_("internal: bad RISC-V opcode"
776 " (unknown operand type `F%c'): %s %s"),
777 c, opc->name, opc->args);
778 return FALSE;
779 }
780 break;
e23eba97
NC		 781 default:
782 as_bad (_("internal: bad RISC-V opcode "
783 "(unknown operand type `%c'): %s %s"),
784 c, opc->name, opc->args);
785 return FALSE;
786 }
787#undef USE_BITS
788 if (used_bits != required_bits)
789 {
790 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
791 ~(unsigned long)(used_bits & required_bits),
792 opc->name, opc->args);
793 return FALSE;
794 }
795 return TRUE;
796}
797
798struct percent_op_match
799{
800 const char *str;
801 bfd_reloc_code_real_type reloc;
802};
803
0e35537d
JW		 804/* Common hash table initialization function for
805 instruction and .insn directive. */
806static struct hash_control *
807init_opcode_hash (const struct riscv_opcode *opcodes,
808 bfd_boolean insn_directive_p)
e23eba97
NC		 809{
810 int i = 0;
0e35537d
JW		 811 int length;
812 struct hash_control *hash = hash_new ();
813 while (opcodes[i].name)
e23eba97 814 {
0e35537d 815 const char *name = opcodes[i].name;
e23eba97 816 const char *hash_error =
0e35537d 817 hash_insert (hash, name, (void *) &opcodes[i]);
e23eba97
NC		 818
819 if (hash_error)
820 {
821 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
0e35537d 822 opcodes[i].name, hash_error);
e23eba97
NC		 823 /* Probably a memory allocation problem? Give up now. */
824 as_fatal (_("Broken assembler. No assembly attempted."));
825 }
826
827 do
828 {
0e35537d 829 if (opcodes[i].pinfo != INSN_MACRO)
e23eba97 830 {
0e35537d
JW		 831 if (insn_directive_p)
832 length = ((name[0] == 'c') ? 2 : 4);
833 else
834 length = 0; /* Let assembler determine the length. */
835 if (!validate_riscv_insn (&opcodes[i], length))
e23eba97
NC		 836 as_fatal (_("Broken assembler. No assembly attempted."));
837 }
0e35537d
JW		 838 else
839 gas_assert (!insn_directive_p);
e23eba97
NC		 840 ++i;
841 }
0e35537d 842 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
e23eba97
NC		 843 }
844
0e35537d
JW		 845 return hash;
846}
847
848/* This function is called once, at assembler startup time. It should set up
849 all the tables, etc. that the MD part of the assembler will need. */
850
851void
852md_begin (void)
853{
854 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
855
856 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
857 as_warn (_("Could not set architecture and machine"));
858
859 op_hash = init_opcode_hash (riscv_opcodes, FALSE);
860 insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
861
e23eba97
NC		 862 reg_names_hash = hash_new ();
863 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
864 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
865 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
866 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
867
b9c04e5a
JW		 868 /* Add "fp" as an alias for "s0". */
869 hash_reg_name (RCLASS_GPR, "fp", 8);
870
0e35537d
JW		 871 opcode_names_hash = hash_new ();
872 init_opcode_names_hash ();
873
e23eba97 874#define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
1270b047 875#define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
e23eba97
NC		 876#include "opcode/riscv-opc.h"
877#undef DECLARE_CSR
878
879 /* Set the default alignment for the text section. */
880 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
881}
882
45f76423
AW		 883static insn_t
884riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
885{
886 switch (reloc_type)
887 {
888 case BFD_RELOC_32:
889 return value;
890
891 case BFD_RELOC_RISCV_HI20:
892 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
893
894 case BFD_RELOC_RISCV_LO12_S:
895 return ENCODE_STYPE_IMM (value);
896
897 case BFD_RELOC_RISCV_LO12_I:
898 return ENCODE_ITYPE_IMM (value);
899
900 default:
901 abort ();
902 }
903}
904
e23eba97
NC		 905/* Output an instruction. IP is the instruction information.
906 ADDRESS_EXPR is an operand of the instruction to be used with
907 RELOC_TYPE. */
908
909static void
910append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
911 bfd_reloc_code_real_type reloc_type)
912{
913 dwarf2_emit_insn (0);
914
915 if (reloc_type != BFD_RELOC_UNUSED)
916 {
917 reloc_howto_type *howto;
918
1d65abb5 919 gas_assert (address_expr);
e23eba97
NC		 920 if (reloc_type == BFD_RELOC_12_PCREL
921 || reloc_type == BFD_RELOC_RISCV_JMP)
922 {
923 int j = reloc_type == BFD_RELOC_RISCV_JMP;
924 int best_case = riscv_insn_length (ip->insn_opcode);
925 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
926 add_relaxed_insn (ip, worst_case, best_case,
927 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
928 address_expr->X_add_symbol,
929 address_expr->X_add_number);
930 return;
931 }
45f76423 932 else
e23eba97 933 {
45f76423
AW		 934 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
935 if (howto == NULL)
936 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
e23eba97 937
45f76423
AW		 938 ip->fixp = fix_new_exp (ip->frag, ip->where,
939 bfd_get_reloc_size (howto),
940 address_expr, FALSE, reloc_type);
e23eba97 941
45f76423 942 ip->fixp->fx_tcbit = riscv_opts.relax;
e23eba97 943 }
e23eba97
NC		 944 }
945
e23eba97
NC		 946 add_fixed_insn (ip);
947 install_insn (ip);
f77bb6c5
JW		 948
949 /* We need to start a new frag after any instruction that can be
950 optimized away or compressed by the linker during relaxation, to prevent
951 the assembler from computing static offsets across such an instruction.
952 This is necessary to get correct EH info. */
953 if (reloc_type == BFD_RELOC_RISCV_CALL
954 || reloc_type == BFD_RELOC_RISCV_CALL_PLT
955 || reloc_type == BFD_RELOC_RISCV_HI20
956 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
957 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
958 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
959 {
960 frag_wane (frag_now);
961 frag_new (0);
962 }
e23eba97
NC		 963}
964
965/* Build an instruction created by a macro expansion. This is passed
966 a pointer to the count of instructions created so far, an
967 expression, the name of the instruction to build, an operand format
968 string, and corresponding arguments. */
969
970static void
971macro_build (expressionS *ep, const char *name, const char *fmt, ...)
972{
973 const struct riscv_opcode *mo;
974 struct riscv_cl_insn insn;
975 bfd_reloc_code_real_type r;
976 va_list args;
977
978 va_start (args, fmt);
979
980 r = BFD_RELOC_UNUSED;
981 mo = (struct riscv_opcode *) hash_find (op_hash, name);
982 gas_assert (mo);
983
984 /* Find a non-RVC variant of the instruction. append_insn will compress
985 it if possible. */
986 while (riscv_insn_length (mo->match) < 4)
987 mo++;
988 gas_assert (strcmp (name, mo->name) == 0);
989
990 create_insn (&insn, mo);
991 for (;;)
992 {
993 switch (*fmt++)
994 {
995 case 'd':
996 INSERT_OPERAND (RD, insn, va_arg (args, int));
997 continue;
998
999 case 's':
1000 INSERT_OPERAND (RS1, insn, va_arg (args, int));
1001 continue;
1002
1003 case 't':
1004 INSERT_OPERAND (RS2, insn, va_arg (args, int));
1005 continue;
1006
1007 case '>':
1008 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
1009 continue;
1010
1011 case 'j':
1012 case 'u':
1013 case 'q':
1014 gas_assert (ep != NULL);
1015 r = va_arg (args, int);
1016 continue;
1017
1018 case '\0':
1019 break;
1020 case ',':
1021 continue;
1022 default:
1023 as_fatal (_("internal error: invalid macro"));
1024 }
1025 break;
1026 }
1027 va_end (args);
1028 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1029
1030 append_insn (&insn, ep, r);
1031}
1032
1033/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1034 unset. */
1035static void
1036normalize_constant_expr (expressionS *ex)
1037{
1038 if (xlen > 32)
1039 return;
1040 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1041 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1042 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1043 - 0x80000000);
1044}
1045
ca2fd32c
JW		 1046/* Fail if an expression EX is not a constant. IP is the instruction using EX.
1047 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
e23eba97
NC		 1048
1049static void
ca2fd32c
JW		 1050check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
1051 bfd_boolean maybe_csr)
e23eba97
NC		 1052{
1053 if (ex->X_op == O_big)
1054 as_bad (_("unsupported large constant"));
ca2fd32c
JW		 1055 else if (maybe_csr && ex->X_op == O_symbol)
1056 as_bad (_("unknown CSR `%s'"),
1057 S_GET_NAME (ex->X_add_symbol));
e23eba97
NC		 1058 else if (ex->X_op != O_constant)
1059 as_bad (_("Instruction %s requires absolute expression"),
1060 ip->insn_mo->name);
1061 normalize_constant_expr (ex);
1062}
1063
1064static symbolS *
1065make_internal_label (void)
1066{
1067 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg,
1d65abb5 1068 (valueT) frag_now_fix (), frag_now);
e23eba97
NC		 1069}
1070
1071/* Load an entry from the GOT. */
1072static void
1073pcrel_access (int destreg, int tempreg, expressionS *ep,
1074 const char *lo_insn, const char *lo_pattern,
1075 bfd_reloc_code_real_type hi_reloc,
1076 bfd_reloc_code_real_type lo_reloc)
1077{
1078 expressionS ep2;
1079 ep2.X_op = O_symbol;
1080 ep2.X_add_symbol = make_internal_label ();
1081 ep2.X_add_number = 0;
1082
1083 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1084 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1085}
1086
1087static void
1088pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1089 bfd_reloc_code_real_type hi_reloc,
1090 bfd_reloc_code_real_type lo_reloc)
1091{
1092 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1093}
1094
1095static void
1096pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1097 bfd_reloc_code_real_type hi_reloc,
1098 bfd_reloc_code_real_type lo_reloc)
1099{
1100 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1101}
1102
1103/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1104static void
1105riscv_call (int destreg, int tempreg, expressionS *ep,
1106 bfd_reloc_code_real_type reloc)
1107{
1108 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1109 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
1110}
1111
1112/* Load an integer constant into a register. */
1113
1114static void
1115load_const (int reg, expressionS *ep)
1116{
1117 int shift = RISCV_IMM_BITS;
1118 expressionS upper = *ep, lower = *ep;
1119 lower.X_add_number = (int32_t) ep->X_add_number << (32-shift) >> (32-shift);
1120 upper.X_add_number -= lower.X_add_number;
1121
1122 if (ep->X_op != O_constant)
1123 {
1124 as_bad (_("unsupported large constant"));
1125 return;
1126 }
1127
1d65abb5 1128 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
e23eba97
NC		 1129 {
1130 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1131 while (((upper.X_add_number >> shift) & 1) == 0)
1132 shift++;
1133
1134 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1d65abb5 1135 load_const (reg, &upper);
e23eba97
NC		 1136
1137 macro_build (NULL, "slli", "d,s,>", reg, reg, shift);
1138 if (lower.X_add_number != 0)
1139 macro_build (&lower, "addi", "d,s,j", reg, reg, BFD_RELOC_RISCV_LO12_I);
1140 }
1141 else
1142 {
1143 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1144 int hi_reg = 0;
1145
1146 if (upper.X_add_number != 0)
1147 {
1148 macro_build (ep, "lui", "d,u", reg, BFD_RELOC_RISCV_HI20);
1149 hi_reg = reg;
1150 }
1151
1152 if (lower.X_add_number != 0 || hi_reg == 0)
1153 macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg,
1154 BFD_RELOC_RISCV_LO12_I);
1155 }
1156}
1157
1158/* Expand RISC-V assembly macros into one or more instructions. */
1159static void
1160macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1161 bfd_reloc_code_real_type *imm_reloc)
1162{
1163 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1164 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1165 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1166 int mask = ip->insn_mo->mask;
1167
1168 switch (mask)
1169 {
1170 case M_LI:
1171 load_const (rd, imm_expr);
1172 break;
1173
1174 case M_LA:
1175 case M_LLA:
1176 /* Load the address of a symbol into a register. */
1177 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1178 as_bad (_("offset too large"));
1179
1180 if (imm_expr->X_op == O_constant)
1181 load_const (rd, imm_expr);
1182 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */
1183 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1184 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1185 else /* Local PIC symbol, or any non-PIC symbol */
1186 pcrel_load (rd, rd, imm_expr, "addi",
1187 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1188 break;
1189
1190 case M_LA_TLS_GD:
1191 pcrel_load (rd, rd, imm_expr, "addi",
1192 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1193 break;
1194
1195 case M_LA_TLS_IE:
1196 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1197 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1198 break;
1199
1200 case M_LB:
1201 pcrel_load (rd, rd, imm_expr, "lb",
1202 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1203 break;
1204
1205 case M_LBU:
1206 pcrel_load (rd, rd, imm_expr, "lbu",
1207 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1208 break;
1209
1210 case M_LH:
1211 pcrel_load (rd, rd, imm_expr, "lh",
1212 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1213 break;
1214
1215 case M_LHU:
1216 pcrel_load (rd, rd, imm_expr, "lhu",
1217 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1218 break;
1219
1220 case M_LW:
1221 pcrel_load (rd, rd, imm_expr, "lw",
1222 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1223 break;
1224
1225 case M_LWU:
1226 pcrel_load (rd, rd, imm_expr, "lwu",
1227 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1228 break;
1229
1230 case M_LD:
1231 pcrel_load (rd, rd, imm_expr, "ld",
1232 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1233 break;
1234
1235 case M_FLW:
1236 pcrel_load (rd, rs1, imm_expr, "flw",
1237 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1238 break;
1239
1240 case M_FLD:
1241 pcrel_load (rd, rs1, imm_expr, "fld",
1242 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1243 break;
1244
1245 case M_SB:
1246 pcrel_store (rs2, rs1, imm_expr, "sb",
1247 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1248 break;
1249
1250 case M_SH:
1251 pcrel_store (rs2, rs1, imm_expr, "sh",
1252 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1253 break;
1254
1255 case M_SW:
1256 pcrel_store (rs2, rs1, imm_expr, "sw",
1257 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1258 break;
1259
1260 case M_SD:
1261 pcrel_store (rs2, rs1, imm_expr, "sd",
1262 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1263 break;
1264
1265 case M_FSW:
1266 pcrel_store (rs2, rs1, imm_expr, "fsw",
1267 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1268 break;
1269
1270 case M_FSD:
1271 pcrel_store (rs2, rs1, imm_expr, "fsd",
1272 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1273 break;
1274
1275 case M_CALL:
1276 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1277 break;
1278
1279 default:
1280 as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
1281 break;
1282 }
1283}
1284
1285static const struct percent_op_match percent_op_utype[] =
1286{
1287 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1288 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
1289 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1290 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1291 {"%hi", BFD_RELOC_RISCV_HI20},
1292 {0, 0}
1293};
1294
1295static const struct percent_op_match percent_op_itype[] =
1296{
1297 {"%lo", BFD_RELOC_RISCV_LO12_I},
1298 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1299 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1300 {0, 0}
1301};
1302
1303static const struct percent_op_match percent_op_stype[] =
1304{
1305 {"%lo", BFD_RELOC_RISCV_LO12_S},
1306 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1307 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1308 {0, 0}
1309};
1310
1311static const struct percent_op_match percent_op_rtype[] =
1312{
1313 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1314 {0, 0}
1315};
1316
1317/* Return true if *STR points to a relocation operator. When returning true,
1318 move *STR over the operator and store its relocation code in *RELOC.
1319 Leave both *STR and *RELOC alone when returning false. */
1320
1321static bfd_boolean
1322parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1323 const struct percent_op_match *percent_op)
1324{
1325 for ( ; percent_op->str; percent_op++)
1326 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1327 {
1328 int len = strlen (percent_op->str);
1329
1330 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1331 continue;
1332
1333 *str += strlen (percent_op->str);
1334 *reloc = percent_op->reloc;
1335
1336 /* Check whether the output BFD supports this relocation.
1337 If not, issue an error and fall back on something safe. */
45f76423
AW		 1338 if (*reloc != BFD_RELOC_UNUSED
1339 && !bfd_reloc_type_lookup (stdoutput, *reloc))
e23eba97
NC		 1340 {
1341 as_bad ("relocation %s isn't supported by the current ABI",
1342 percent_op->str);
1343 *reloc = BFD_RELOC_UNUSED;
1344 }
1345 return TRUE;
1346 }
1347 return FALSE;
1348}
1349
1350static void
1351my_getExpression (expressionS *ep, char *str)
1352{
1353 char *save_in;
1354
1355 save_in = input_line_pointer;
1356 input_line_pointer = str;
1357 expression (ep);
1358 expr_end = input_line_pointer;
1359 input_line_pointer = save_in;
1360}
1361
1362/* Parse string STR as a 16-bit relocatable operand. Store the
1363 expression in *EP and the relocation, if any, in RELOC.
1364 Return the number of relocation operators used (0 or 1).
1365
1366 On exit, EXPR_END points to the first character after the expression. */
1367
1368static size_t
1369my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1370 char *str, const struct percent_op_match *percent_op)
1371{
1372 size_t reloc_index;
1373 unsigned crux_depth, str_depth, regno;
1374 char *crux;
1375
1376 /* First, check for integer registers. */
1377 if (reg_lookup (&str, RCLASS_GPR, &regno))
1378 {
1379 ep->X_op = O_register;
1380 ep->X_add_number = regno;
1381 return 0;
1382 }
1383
1384 /* Search for the start of the main expression.
1385 End the loop with CRUX pointing to the start
1386 of the main expression and with CRUX_DEPTH containing the number
1387 of open brackets at that point. */
1388 reloc_index = -1;
1389 str_depth = 0;
1390 do
1391 {
1392 reloc_index++;
1393 crux = str;
1394 crux_depth = str_depth;
1395
1396 /* Skip over whitespace and brackets, keeping count of the number
1397 of brackets. */
1398 while (*str == ' ' || *str == '\t' || *str == '(')
1399 if (*str++ == '(')
1400 str_depth++;
1401 }
1402 while (*str == '%'
1403 && reloc_index < 1
1404 && parse_relocation (&str, reloc, percent_op));
1405
1406 my_getExpression (ep, crux);
1407 str = expr_end;
1408
1409 /* Match every open bracket. */
1410 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1411 if (*str++ == ')')
1412 crux_depth--;
1413
1414 if (crux_depth > 0)
1415 as_bad ("unclosed '('");
1416
1417 expr_end = str;
1418
1419 return reloc_index;
1420}
1421
0e35537d
JW		 1422/* Parse opcode name, could be an mnemonics or number. */
1423static size_t
1424my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1425 char *str, const struct percent_op_match *percent_op)
1426{
1427 const struct opcode_name_t *o = opcode_name_lookup (&str);
1428
1429 if (o != NULL)
1430 {
1431 ep->X_op = O_constant;
1432 ep->X_add_number = o->val;
1433 return 0;
1434 }
1435
1436 return my_getSmallExpression (ep, reloc, str, percent_op);
1437}
1438
f0531ed6
JW		 1439/* Detect and handle implicitly zero load-store offsets. For example,
1440 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1441 an implicit offset was detected. */
1442
1443static bfd_boolean
89424b1d 1444riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
f0531ed6
JW		 1445{
1446 /* Check whether there is only a single bracketed expression left.
1447 If so, it must be the base register and the constant must be zero. */
1448 if (*s == '(' && strchr (s + 1, '(') == 0)
1449 {
89424b1d
MR		 1450 ep->X_op = O_constant;
1451 ep->X_add_number = 0;
f0531ed6
JW		 1452 return TRUE;
1453 }
1454
1455 return FALSE;
1456}
1457
e23eba97
NC		 1458/* This routine assembles an instruction into its binary format. As a
1459 side effect, it sets the global variable imm_reloc to the type of
1460 relocation to do if one of the operands is an address expression. */
1461
1462static const char *
1463riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
0e35537d 1464 bfd_reloc_code_real_type *imm_reloc, struct hash_control *hash)
e23eba97
NC		 1465{
1466 char *s;
1467 const char *args;
1468 char c = 0;
1469 struct riscv_opcode *insn;
1470 char *argsStart;
1471 unsigned int regno;
1472 char save_c = 0;
1473 int argnum;
1474 const struct percent_op_match *p;
1475 const char *error = "unrecognized opcode";
1476
1477 /* Parse the name of the instruction. Terminate the string if whitespace
1478 is found so that hash_find only sees the name part of the string. */
1479 for (s = str; *s != '\0'; ++s)
1480 if (ISSPACE (*s))
1481 {
1482 save_c = *s;
1483 *s++ = '\0';
1484 break;
1485 }
1486
0e35537d 1487 insn = (struct riscv_opcode *) hash_find (hash, str);
e23eba97
NC		 1488
1489 argsStart = s;
1490 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1491 {
43135d3b 1492 if (!riscv_multi_subset_supports (insn->xlen_requirement, insn->subset))
e23eba97
NC		 1493 continue;
1494
1495 create_insn (ip, insn);
1496 argnum = 1;
1497
1498 imm_expr->X_op = O_absent;
1499 *imm_reloc = BFD_RELOC_UNUSED;
1500 p = percent_op_itype;
1501
1502 for (args = insn->args;; ++args)
1503 {
1504 s += strspn (s, " \t");
1505 switch (*args)
1506 {
1507 case '\0': /* End of args. */
1508 if (insn->pinfo != INSN_MACRO)
1509 {
1510 if (!insn->match_func (insn, ip->insn_opcode))
1511 break;
0e35537d
JW		 1512
1513 /* For .insn, insn->match and insn->mask are 0. */
1514 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
1515 ? ip->insn_opcode
1516 : insn->match) == 2
1517 && !riscv_opts.rvc)
e23eba97
NC		 1518 break;
1519 }
1520 if (*s != '\0')
1521 break;
1522 /* Successful assembly. */
1523 error = NULL;
1524 goto out;
1525
1526 case 'C': /* RVC */
1527 switch (*++args)
1528 {
1529 case 's': /* RS1 x8-x15 */
1530 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1531 || !(regno >= 8 && regno <= 15))
1532 break;
1533 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1534 continue;
1535 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1536 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1537 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
1538 break;
1539 continue;
1540 case 't': /* RS2 x8-x15 */
1541 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1542 || !(regno >= 8 && regno <= 15))
1543 break;
1544 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1545 continue;
1546 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1547 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1548 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
1549 break;
1550 continue;
1551 case 'U': /* RS1, constrained to equal RD. */
1552 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1553 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
1554 break;
1555 continue;
1556 case 'V': /* RS2 */
1557 if (!reg_lookup (&s, RCLASS_GPR, &regno))
1558 break;
1559 INSERT_OPERAND (CRS2, *ip, regno);
1560 continue;
1561 case 'c': /* RS1, constrained to equal sp. */
1562 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1563 || regno != X_SP)
1564 break;
1565 continue;
1566 case '>':
1567 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1568 || imm_expr->X_op != O_constant
1569 || imm_expr->X_add_number <= 0
1570 || imm_expr->X_add_number >= 64)
1571 break;
1572 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1573rvc_imm_done:
1574 s = expr_end;
1575 imm_expr->X_op = O_absent;
1576 continue;
1577 case '<':
1578 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1579 || imm_expr->X_op != O_constant
1580 || !VALID_RVC_IMM (imm_expr->X_add_number)
1581 || imm_expr->X_add_number <= 0
1582 || imm_expr->X_add_number >= 32)
1583 break;
1584 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1585 goto rvc_imm_done;
0e35537d
JW		 1586 case '8':
1587 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1588 || imm_expr->X_op != O_constant
1589 || !VALID_RVC_UIMM8 (imm_expr->X_add_number)
1590 || imm_expr->X_add_number < 0
1591 || imm_expr->X_add_number >= 256)
1592 break;
1593 ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
1594 goto rvc_imm_done;
e23eba97
NC		 1595 case 'i':
1596 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1597 || imm_expr->X_op != O_constant
1598 || imm_expr->X_add_number == 0
1599 || !VALID_RVC_SIMM3 (imm_expr->X_add_number))
1600 break;
1601 ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
1602 goto rvc_imm_done;
1603 case 'j':
1604 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1605 || imm_expr->X_op != O_constant
1606 || imm_expr->X_add_number == 0
1607 || !VALID_RVC_IMM (imm_expr->X_add_number))
1608 break;
1609 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1610 goto rvc_imm_done;
1611 case 'k':
f0531ed6
JW		 1612 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1613 continue;
e23eba97
NC		 1614 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1615 || imm_expr->X_op != O_constant
1616 || !VALID_RVC_LW_IMM (imm_expr->X_add_number))
1617 break;
1618 ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
1619 goto rvc_imm_done;
1620 case 'l':
f0531ed6
JW		 1621 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1622 continue;
e23eba97
NC		 1623 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1624 || imm_expr->X_op != O_constant
1625 || !VALID_RVC_LD_IMM (imm_expr->X_add_number))
1626 break;
1627 ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
1628 goto rvc_imm_done;
1629 case 'm':
f0531ed6
JW		 1630 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1631 continue;
e23eba97
NC		 1632 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1633 || imm_expr->X_op != O_constant
1634 || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number))
1635 break;
1636 ip->insn_opcode |=
1637 ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
1638 goto rvc_imm_done;
1639 case 'n':
f0531ed6
JW		 1640 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1641 continue;
e23eba97
NC		 1642 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1643 || imm_expr->X_op != O_constant
1644 || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number))
1645 break;
1646 ip->insn_opcode |=
1647 ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
1648 goto rvc_imm_done;
b416fe87
KC		 1649 case 'o':
1650 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1651 || imm_expr->X_op != O_constant
21a186f2
JW		 1652 /* C.addiw, c.li, and c.andi allow zero immediate.
1653 C.addi allows zero immediate as hint. Otherwise this
1654 is same as 'j'. */
b416fe87
KC		 1655 || !VALID_RVC_IMM (imm_expr->X_add_number))
1656 break;
1657 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1658 goto rvc_imm_done;
e23eba97
NC		 1659 case 'K':
1660 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1661 || imm_expr->X_op != O_constant
1662 || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number)
1663 || imm_expr->X_add_number == 0)
1664 break;
1665 ip->insn_opcode |=
1666 ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
1667 goto rvc_imm_done;
1668 case 'L':
1669 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1670 || imm_expr->X_op != O_constant
1671 || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number)
1672 || imm_expr->X_add_number == 0)
1673 break;
1674 ip->insn_opcode |=
1675 ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
1676 goto rvc_imm_done;
1677 case 'M':
f0531ed6
JW		 1678 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1679 continue;
e23eba97
NC		 1680 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1681 || imm_expr->X_op != O_constant
1682 || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number))
1683 break;
1684 ip->insn_opcode |=
1685 ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
1686 goto rvc_imm_done;
1687 case 'N':
f0531ed6
JW		 1688 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1689 continue;
e23eba97
NC		 1690 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1691 || imm_expr->X_op != O_constant
1692 || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number))
1693 break;
1694 ip->insn_opcode |=
1695 ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
1696 goto rvc_imm_done;
1697 case 'u':
1698 p = percent_op_utype;
1699 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
1700 break;
1701rvc_lui:
1702 if (imm_expr->X_op != O_constant
1703 || imm_expr->X_add_number <= 0
1704 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
1705 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
1706 && (imm_expr->X_add_number <
1707 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
1708 break;
1709 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1710 goto rvc_imm_done;
1711 case 'v':
1712 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1713 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
1714 || ((int32_t)imm_expr->X_add_number
1715 != imm_expr->X_add_number))
1716 break;
1717 imm_expr->X_add_number =
1718 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
1719 goto rvc_lui;
1720 case 'p':
1721 goto branch;
1722 case 'a':
1723 goto jump;
0e35537d
JW		 1724 case 'S': /* Floating-point RS1 x8-x15. */
1725 if (!reg_lookup (&s, RCLASS_FPR, &regno)
1726 || !(regno >= 8 && regno <= 15))
1727 break;
1728 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1729 continue;
e23eba97
NC		 1730 case 'D': /* Floating-point RS2 x8-x15. */
1731 if (!reg_lookup (&s, RCLASS_FPR, &regno)
1732 || !(regno >= 8 && regno <= 15))
1733 break;
1734 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1735 continue;
1736 case 'T': /* Floating-point RS2. */
1737 if (!reg_lookup (&s, RCLASS_FPR, &regno))
1738 break;
1739 INSERT_OPERAND (CRS2, *ip, regno);
1740 continue;
0e35537d
JW		 1741 case 'F':
1742 switch (*++args)
1743 {
1744 case '4':
1745 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1746 || imm_expr->X_op != O_constant
1747 || imm_expr->X_add_number < 0
1748 || imm_expr->X_add_number >= 16)
1749 {
1750 as_bad (_("bad value for funct4 field, "
1751 "value must be 0...15"));
1752 break;
1753 }
1754
1755 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
1756 imm_expr->X_op = O_absent;
1757 s = expr_end;
1758 continue;
1759 case '3':
1760 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1761 || imm_expr->X_op != O_constant
1762 || imm_expr->X_add_number < 0
1763 || imm_expr->X_add_number >= 8)
1764 {
1765 as_bad (_("bad value for funct3 field, "
1766 "value must be 0...7"));
1767 break;
1768 }
1769 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
1770 imm_expr->X_op = O_absent;
1771 s = expr_end;
1772 continue;
1773 default:
1774 as_bad (_("bad compressed FUNCT field"
1775 " specifier 'CF%c'\n"),
1776 *args);
1777 }
1778 break;
1779
e23eba97
NC		 1780 default:
1781 as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
1782 }
1783 break;
1784
1785 case ',':
1786 ++argnum;
1787 if (*s++ == *args)
1788 continue;
1789 s--;
1790 break;
1791
1792 case '(':
1793 case ')':
1794 case '[':
1795 case ']':
1796 if (*s++ == *args)
1797 continue;
1798 break;
1799
1800 case '<': /* Shift amount, 0 - 31. */
1801 my_getExpression (imm_expr, s);
ca2fd32c 1802 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 1803 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 1804 as_bad (_("Improper shift amount (%lu)"),
1805 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 1806 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
1807 imm_expr->X_op = O_absent;
1808 s = expr_end;
1809 continue;
1810
1811 case '>': /* Shift amount, 0 - (XLEN-1). */
1812 my_getExpression (imm_expr, s);
ca2fd32c 1813 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 1814 if ((unsigned long) imm_expr->X_add_number >= xlen)
94f78a77
AW		 1815 as_bad (_("Improper shift amount (%lu)"),
1816 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 1817 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
1818 imm_expr->X_op = O_absent;
1819 s = expr_end;
1820 continue;
1821
1822 case 'Z': /* CSRRxI immediate. */
1823 my_getExpression (imm_expr, s);
ca2fd32c 1824 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 1825 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 1826 as_bad (_("Improper CSRxI immediate (%lu)"),
1827 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 1828 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
1829 imm_expr->X_op = O_absent;
1830 s = expr_end;
1831 continue;
1832
1833 case 'E': /* Control register. */
1834 if (reg_lookup (&s, RCLASS_CSR, &regno))
1835 INSERT_OPERAND (CSR, *ip, regno);
1836 else
1837 {
1838 my_getExpression (imm_expr, s);
ca2fd32c 1839 check_absolute_expr (ip, imm_expr, TRUE);
e23eba97 1840 if ((unsigned long) imm_expr->X_add_number > 0xfff)
94f78a77
AW		 1841 as_bad (_("Improper CSR address (%lu)"),
1842 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 1843 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
1844 imm_expr->X_op = O_absent;
1845 s = expr_end;
1846 }
1847 continue;
1848
1849 case 'm': /* Rounding mode. */
1850 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
1851 {
1852 INSERT_OPERAND (RM, *ip, regno);
1853 continue;
1854 }
1855 break;
1856
1857 case 'P':
1858 case 'Q': /* Fence predecessor/successor. */
1859 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
1860 &regno))
1861 {
1862 if (*args == 'P')
1863 INSERT_OPERAND (PRED, *ip, regno);
1864 else
1865 INSERT_OPERAND (SUCC, *ip, regno);
1866 continue;
1867 }
1868 break;
1869
1870 case 'd': /* Destination register. */
1871 case 's': /* Source register. */
1872 case 't': /* Target register. */
0e35537d 1873 case 'r': /* rs3. */
e23eba97
NC		 1874 if (reg_lookup (&s, RCLASS_GPR, &regno))
1875 {
1876 c = *args;
1877 if (*s == ' ')
1878 ++s;
1879
1880 /* Now that we have assembled one operand, we use the args
1881 string to figure out where it goes in the instruction. */
1882 switch (c)
1883 {
1884 case 's':
1885 INSERT_OPERAND (RS1, *ip, regno);
1886 break;
1887 case 'd':
1888 INSERT_OPERAND (RD, *ip, regno);
1889 break;
1890 case 't':
1891 INSERT_OPERAND (RS2, *ip, regno);
1892 break;
0e35537d
JW		 1893 case 'r':
1894 INSERT_OPERAND (RS3, *ip, regno);
1895 break;
e23eba97
NC		 1896 }
1897 continue;
1898 }
1899 break;
1900
1901 case 'D': /* Floating point rd. */
1902 case 'S': /* Floating point rs1. */
1903 case 'T': /* Floating point rs2. */
1904 case 'U': /* Floating point rs1 and rs2. */
1905 case 'R': /* Floating point rs3. */
1906 if (reg_lookup (&s, RCLASS_FPR, &regno))
1907 {
1908 c = *args;
1909 if (*s == ' ')
1910 ++s;
1911 switch (c)
1912 {
1913 case 'D':
1914 INSERT_OPERAND (RD, *ip, regno);
1915 break;
1916 case 'S':
1917 INSERT_OPERAND (RS1, *ip, regno);
1918 break;
1919 case 'U':
1920 INSERT_OPERAND (RS1, *ip, regno);
1921 /* fallthru */
1922 case 'T':
1923 INSERT_OPERAND (RS2, *ip, regno);
1924 break;
1925 case 'R':
1926 INSERT_OPERAND (RS3, *ip, regno);
1927 break;
1928 }
1929 continue;
1930 }
1931
1932 break;
1933
1934 case 'I':
1935 my_getExpression (imm_expr, s);
1936 if (imm_expr->X_op != O_big
1937 && imm_expr->X_op != O_constant)
1938 break;
1939 normalize_constant_expr (imm_expr);
1940 s = expr_end;
1941 continue;
1942
1943 case 'A':
1944 my_getExpression (imm_expr, s);
1945 normalize_constant_expr (imm_expr);
1946 /* The 'A' format specifier must be a symbol. */
1947 if (imm_expr->X_op != O_symbol)
1948 break;
1949 *imm_reloc = BFD_RELOC_32;
1950 s = expr_end;
1951 continue;
1952
160d1b3d
SH		 1953 case 'B':
1954 my_getExpression (imm_expr, s);
1955 normalize_constant_expr (imm_expr);
1956 /* The 'B' format specifier must be a symbol or a constant. */
1957 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
1958 break;
1959 if (imm_expr->X_op == O_symbol)
1960 *imm_reloc = BFD_RELOC_32;
1961 s = expr_end;
1962 continue;
1963
e23eba97
NC		 1964 case 'j': /* Sign-extended immediate. */
1965 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
1966 p = percent_op_itype;
1967 goto alu_op;
1968 case 'q': /* Store displacement. */
1969 p = percent_op_stype;
1970 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
1971 goto load_store;
1972 case 'o': /* Load displacement. */
1973 p = percent_op_itype;
1974 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
1975 goto load_store;
1976 case '0': /* AMO "displacement," which must be zero. */
1977 p = percent_op_rtype;
1978 *imm_reloc = BFD_RELOC_UNUSED;
1979load_store:
f0531ed6 1980 if (riscv_handle_implicit_zero_offset (imm_expr, s))
e23eba97
NC		 1981 continue;
1982alu_op:
1983 /* If this value won't fit into a 16 bit offset, then go
1984 find a macro that will generate the 32 bit offset
1985 code pattern. */
1986 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
1987 {
1988 normalize_constant_expr (imm_expr);
1989 if (imm_expr->X_op != O_constant
1990 || (*args == '0' && imm_expr->X_add_number != 0)
1991 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
1992 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
1993 break;
1994 }
1995
1996 s = expr_end;
1997 continue;
1998
1999 case 'p': /* PC-relative offset. */
2000branch:
2001 *imm_reloc = BFD_RELOC_12_PCREL;
2002 my_getExpression (imm_expr, s);
2003 s = expr_end;
2004 continue;
2005
2006 case 'u': /* Upper 20 bits. */
2007 p = percent_op_utype;
2008 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p)
2009 && imm_expr->X_op == O_constant)
2010 {
2011 if (imm_expr->X_add_number < 0
2012 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
2013 as_bad (_("lui expression not in range 0..1048575"));
2014
2015 *imm_reloc = BFD_RELOC_RISCV_HI20;
2016 imm_expr->X_add_number <<= RISCV_IMM_BITS;
2017 }
2018 s = expr_end;
2019 continue;
2020
2021 case 'a': /* 20-bit PC-relative offset. */
2022jump:
2023 my_getExpression (imm_expr, s);
2024 s = expr_end;
2025 *imm_reloc = BFD_RELOC_RISCV_JMP;
2026 continue;
2027
2028 case 'c':
2029 my_getExpression (imm_expr, s);
2030 s = expr_end;
2031 if (strcmp (s, "@plt") == 0)
2032 {
2033 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2034 s += 4;
2035 }
2036 else
2037 *imm_reloc = BFD_RELOC_RISCV_CALL;
2038 continue;
0e35537d
JW		 2039 case 'O':
2040 switch (*++args)
2041 {
2042 case '4':
2043 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2044 || imm_expr->X_op != O_constant
2045 || imm_expr->X_add_number < 0
2046 || imm_expr->X_add_number >= 128
2047 || (imm_expr->X_add_number & 0x3) != 3)
2048 {
2049 as_bad (_("bad value for opcode field, "
2050 "value must be 0...127 and "
2051 "lower 2 bits must be 0x3"));
2052 break;
2053 }
2054
2055 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2056 imm_expr->X_op = O_absent;
2057 s = expr_end;
2058 continue;
2059 case '2':
2060 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2061 || imm_expr->X_op != O_constant
2062 || imm_expr->X_add_number < 0
2063 || imm_expr->X_add_number >= 3)
2064 {
2065 as_bad (_("bad value for opcode field, "
2066 "value must be 0...2"));
2067 break;
2068 }
2069
2070 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2071 imm_expr->X_op = O_absent;
2072 s = expr_end;
2073 continue;
2074 default:
2075 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args);
2076 }
2077 break;
2078
2079 case 'F':
2080 switch (*++args)
2081 {
2082 case '7':
2083 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2084 || imm_expr->X_op != O_constant
2085 || imm_expr->X_add_number < 0
2086 || imm_expr->X_add_number >= 128)
2087 {
2088 as_bad (_("bad value for funct7 field, "
2089 "value must be 0...127"));
2090 break;
2091 }
2092
2093 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2094 imm_expr->X_op = O_absent;
2095 s = expr_end;
2096 continue;
2097 case '3':
2098 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2099 || imm_expr->X_op != O_constant
2100 || imm_expr->X_add_number < 0
2101 || imm_expr->X_add_number >= 8)
2102 {
2103 as_bad (_("bad value for funct3 field, "
2104 "value must be 0...7"));
2105 break;
2106 }
2107
2108 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2109 imm_expr->X_op = O_absent;
2110 s = expr_end;
2111 continue;
2112 case '2':
2113 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2114 || imm_expr->X_op != O_constant
2115 || imm_expr->X_add_number < 0
2116 || imm_expr->X_add_number >= 4)
2117 {
2118 as_bad (_("bad value for funct2 field, "
2119 "value must be 0...3"));
2120 break;
2121 }
2122
2123 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2124 imm_expr->X_op = O_absent;
2125 s = expr_end;
2126 continue;
2127
2128 default:
2129 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args);
2130 }
2131 break;
e23eba97 2132
e925c834
JW		 2133 case 'z':
2134 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2135 || imm_expr->X_op != O_constant
2136 || imm_expr->X_add_number != 0)
2137 break;
2138 s = expr_end;
2139 imm_expr->X_op = O_absent;
2140 continue;
2141
e23eba97
NC		 2142 default:
2143 as_fatal (_("internal error: bad argument type %c"), *args);
2144 }
2145 break;
2146 }
2147 s = argsStart;
2148 error = _("illegal operands");
2149 }
2150
2151out:
2152 /* Restore the character we might have clobbered above. */
2153 if (save_c)
2154 *(argsStart - 1) = save_c;
2155
2156 return error;
2157}
2158
2159void
2160md_assemble (char *str)
2161{
2162 struct riscv_cl_insn insn;
2163 expressionS imm_expr;
2164 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2165
0e35537d 2166 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
e23eba97
NC		 2167
2168 if (error)
2169 {
2170 as_bad ("%s `%s'", error, str);
2171 return;
2172 }
2173
2174 if (insn.insn_mo->pinfo == INSN_MACRO)
2175 macro (&insn, &imm_expr, &imm_reloc);
2176 else
2177 append_insn (&insn, &imm_expr, imm_reloc);
2178}
2179
2180const char *
2181md_atof (int type, char *litP, int *sizeP)
2182{
2183 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2184}
2185
2186void
2187md_number_to_chars (char *buf, valueT val, int n)
2188{
2189 number_to_chars_littleendian (buf, val, n);
2190}
2191
2192const char *md_shortopts = "O::g::G:";
2193
2194enum options
2195{
2922d21d 2196 OPTION_MARCH = OPTION_MD_BASE,
e23eba97
NC		 2197 OPTION_PIC,
2198 OPTION_NO_PIC,
2922d21d 2199 OPTION_MABI,
71060565
JW		 2200 OPTION_RELAX,
2201 OPTION_NO_RELAX,
e23eba97
NC		 2202 OPTION_END_OF_ENUM
2203};
2204
2205struct option md_longopts[] =
2206{
e23eba97
NC		 2207 {"march", required_argument, NULL, OPTION_MARCH},
2208 {"fPIC", no_argument, NULL, OPTION_PIC},
2209 {"fpic", no_argument, NULL, OPTION_PIC},
2210 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2922d21d 2211 {"mabi", required_argument, NULL, OPTION_MABI},
71060565
JW		 2212 {"mrelax", no_argument, NULL, OPTION_RELAX},
2213 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
e23eba97
NC		 2214
2215 {NULL, no_argument, NULL, 0}
2216};
2217size_t md_longopts_size = sizeof (md_longopts);
2218
2922d21d
AW		 2219enum float_abi {
2220 FLOAT_ABI_DEFAULT = -1,
2221 FLOAT_ABI_SOFT,
2222 FLOAT_ABI_SINGLE,
2223 FLOAT_ABI_DOUBLE,
2224 FLOAT_ABI_QUAD
e23eba97 2225};
2922d21d
AW		 2226static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
2227
2228static void
7f999549 2229riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
2922d21d
AW		 2230{
2231 abi_xlen = new_xlen;
2232 float_abi = new_float_abi;
7f999549 2233 rve_abi = rve;
2922d21d 2234}
e23eba97
NC		 2235
2236int
2237md_parse_option (int c, const char *arg)
2238{
2239 switch (c)
2240 {
e23eba97
NC		 2241 case OPTION_MARCH:
2242 riscv_set_arch (arg);
2243 break;
2244
2245 case OPTION_NO_PIC:
2246 riscv_opts.pic = FALSE;
2247 break;
2248
2249 case OPTION_PIC:
2250 riscv_opts.pic = TRUE;
2251 break;
2252
2922d21d
AW		 2253 case OPTION_MABI:
2254 if (strcmp (arg, "ilp32") == 0)
7f999549
JW		 2255 riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
2256 else if (strcmp (arg, "ilp32e") == 0)
2257 riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
2922d21d 2258 else if (strcmp (arg, "ilp32f") == 0)
7f999549 2259 riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2260 else if (strcmp (arg, "ilp32d") == 0)
7f999549 2261 riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2262 else if (strcmp (arg, "ilp32q") == 0)
7f999549 2263 riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
2922d21d 2264 else if (strcmp (arg, "lp64") == 0)
7f999549 2265 riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
2922d21d 2266 else if (strcmp (arg, "lp64f") == 0)
7f999549 2267 riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2268 else if (strcmp (arg, "lp64d") == 0)
7f999549 2269 riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2270 else if (strcmp (arg, "lp64q") == 0)
7f999549 2271 riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
2922d21d
AW		 2272 else
2273 return 0;
2274 break;
2275
71060565
JW		 2276 case OPTION_RELAX:
2277 riscv_opts.relax = TRUE;
2278 break;
2279
2280 case OPTION_NO_RELAX:
2281 riscv_opts.relax = FALSE;
2282 break;
2283
e23eba97
NC		 2284 default:
2285 return 0;
2286 }
2287
2288 return 1;
2289}
2290
2291void
2292riscv_after_parse_args (void)
2293{
e23eba97
NC		 2294 if (xlen == 0)
2295 {
2296 if (strcmp (default_arch, "riscv32") == 0)
2297 xlen = 32;
2298 else if (strcmp (default_arch, "riscv64") == 0)
2299 xlen = 64;
2300 else
2301 as_bad ("unknown default architecture `%s'", default_arch);
2302 }
2922d21d
AW		 2303
2304 if (riscv_subsets == NULL)
2305 riscv_set_arch (xlen == 64 ? "rv64g" : "rv32g");
2306
2307 /* Add the RVC extension, regardless of -march, to support .option rvc. */
fecb9c46 2308 riscv_set_rvc (FALSE);
43135d3b 2309 if (riscv_subset_supports (0, "c"))
2922d21d
AW		 2310 riscv_set_rvc (TRUE);
2311 else
2312 riscv_add_subset ("c");
2313
7f999549
JW		 2314 /* Enable RVE if specified by the -march option. */
2315 riscv_set_rve (FALSE);
43135d3b 2316 if (riscv_subset_supports (0, "e"))
7f999549
JW		 2317 riscv_set_rve (TRUE);
2318
2922d21d
AW		 2319 /* Infer ABI from ISA if not specified on command line. */
2320 if (abi_xlen == 0)
2321 abi_xlen = xlen;
2322 else if (abi_xlen > xlen)
2323 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
2324 else if (abi_xlen < xlen)
2325 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
2326
2327 if (float_abi == FLOAT_ABI_DEFAULT)
2328 {
2329 struct riscv_subset *subset;
2330
2331 /* Assume soft-float unless D extension is present. */
2332 float_abi = FLOAT_ABI_SOFT;
2333
2334 for (subset = riscv_subsets; subset != NULL; subset = subset->next)
cc917fd9
KC		 2335 {
2336 if (strcasecmp (subset->name, "D") == 0)
2337 float_abi = FLOAT_ABI_DOUBLE;
2338 if (strcasecmp (subset->name, "Q") == 0)
2339 float_abi = FLOAT_ABI_QUAD;
2340 }
2922d21d
AW		 2341 }
2342
7f999549
JW		 2343 if (rve_abi)
2344 elf_flags |= EF_RISCV_RVE;
2345
2922d21d
AW		 2346 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2347 elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1));
e23eba97
NC		 2348}
2349
2350long
2351md_pcrel_from (fixS *fixP)
2352{
2353 return fixP->fx_where + fixP->fx_frag->fr_address;
2354}
2355
2356/* Apply a fixup to the object file. */
2357
2358void
2359md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2360{
45f76423 2361 unsigned int subtype;
e23eba97 2362 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
45f76423 2363 bfd_boolean relaxable = FALSE;
c1b465c9 2364 offsetT loc;
a6cbf936 2365 segT sub_segment;
e23eba97
NC		 2366
2367 /* Remember value for tc_gen_reloc. */
2368 fixP->fx_addnumber = *valP;
2369
2370 switch (fixP->fx_r_type)
2371 {
e23eba97
NC		 2372 case BFD_RELOC_RISCV_HI20:
2373 case BFD_RELOC_RISCV_LO12_I:
2374 case BFD_RELOC_RISCV_LO12_S:
45f76423
AW		 2375 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2376 | bfd_getl32 (buf), buf);
a5ec5e3f
AW		 2377 if (fixP->fx_addsy == NULL)
2378 fixP->fx_done = TRUE;
45f76423
AW		 2379 relaxable = TRUE;
2380 break;
2381
2382 case BFD_RELOC_RISCV_GOT_HI20:
e23eba97
NC		 2383 case BFD_RELOC_RISCV_ADD8:
2384 case BFD_RELOC_RISCV_ADD16:
2385 case BFD_RELOC_RISCV_ADD32:
2386 case BFD_RELOC_RISCV_ADD64:
45f76423 2387 case BFD_RELOC_RISCV_SUB6:
e23eba97
NC		 2388 case BFD_RELOC_RISCV_SUB8:
2389 case BFD_RELOC_RISCV_SUB16:
2390 case BFD_RELOC_RISCV_SUB32:
2391 case BFD_RELOC_RISCV_SUB64:
45f76423
AW		 2392 case BFD_RELOC_RISCV_RELAX:
2393 break;
2394
2395 case BFD_RELOC_RISCV_TPREL_HI20:
2396 case BFD_RELOC_RISCV_TPREL_LO12_I:
2397 case BFD_RELOC_RISCV_TPREL_LO12_S:
2398 case BFD_RELOC_RISCV_TPREL_ADD:
2399 relaxable = TRUE;
2400 /* Fall through. */
2401
2402 case BFD_RELOC_RISCV_TLS_GOT_HI20:
2403 case BFD_RELOC_RISCV_TLS_GD_HI20:
2404 case BFD_RELOC_RISCV_TLS_DTPREL32:
2405 case BFD_RELOC_RISCV_TLS_DTPREL64:
e294484e
AW		 2406 if (fixP->fx_addsy != NULL)
2407 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2408 else
2409 as_bad_where (fixP->fx_file, fixP->fx_line,
2410 _("TLS relocation against a constant"));
e23eba97
NC		 2411 break;
2412
e23eba97 2413 case BFD_RELOC_32:
a6cbf936
KLC		 2414 /* Use pc-relative relocation for FDE initial location.
2415 The symbol address in .eh_frame may be adjusted in
2416 _bfd_elf_discard_section_eh_frame, and the content of
2417 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2418 Therefore, we cannot insert a relocation whose addend symbol is
2419 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2420 if (fixP->fx_addsy && fixP->fx_subsy
2421 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
2422 && strcmp (sub_segment->name, ".eh_frame") == 0
2423 && S_GET_VALUE (fixP->fx_subsy)
2424 == fixP->fx_frag->fr_address + fixP->fx_where)
2425 {
2426 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
2427 fixP->fx_subsy = NULL;
2428 break;
2429 }
2430 /* Fall through. */
2431 case BFD_RELOC_64:
e23eba97
NC		 2432 case BFD_RELOC_16:
2433 case BFD_RELOC_8:
45f76423 2434 case BFD_RELOC_RISCV_CFA:
e23eba97
NC		 2435 if (fixP->fx_addsy && fixP->fx_subsy)
2436 {
2437 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2438 fixP->fx_next->fx_addsy = fixP->fx_subsy;
2439 fixP->fx_next->fx_subsy = NULL;
2440 fixP->fx_next->fx_offset = 0;
2441 fixP->fx_subsy = NULL;
2442
2443 switch (fixP->fx_r_type)
2444 {
2445 case BFD_RELOC_64:
2446 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
2447 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
2448 break;
2449
2450 case BFD_RELOC_32:
2451 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
2452 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2453 break;
2454
2455 case BFD_RELOC_16:
2456 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
2457 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2458 break;
2459
2460 case BFD_RELOC_8:
2461 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
2462 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
073808ed 2463 break;
e23eba97 2464
45f76423
AW		 2465 case BFD_RELOC_RISCV_CFA:
2466 /* Load the byte to get the subtype. */
c1b465c9
KLC		 2467 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
2468 loc = fixP->fx_frag->fr_fix - (subtype & 7);
45f76423
AW		 2469 switch (subtype)
2470 {
2471 case DW_CFA_advance_loc1:
c1b465c9
KLC		 2472 fixP->fx_where = loc + 1;
2473 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2474 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
2475 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
2476 break;
2477
2478 case DW_CFA_advance_loc2:
2479 fixP->fx_size = 2;
45f76423 2480 fixP->fx_next->fx_size = 2;
c1b465c9
KLC		 2481 fixP->fx_where = loc + 1;
2482 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2483 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
2484 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2485 break;
2486
2487 case DW_CFA_advance_loc4:
2488 fixP->fx_size = 4;
45f76423 2489 fixP->fx_next->fx_size = 4;
c1b465c9
KLC		 2490 fixP->fx_where = loc;
2491 fixP->fx_next->fx_where = loc;
45f76423
AW		 2492 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
2493 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2494 break;
2495
2496 default:
2497 if (subtype < 0x80 && (subtype & 0x40))
2498 {
2499 /* DW_CFA_advance_loc */
2aece2ba
KLC		 2500 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
2501 fixP->fx_next->fx_frag = fixP->fx_frag;
45f76423
AW		 2502 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
2503 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
2504 }
2505 else
2506 as_fatal (_("internal error: bad CFA value #%d"), subtype);
2507 break;
2508 }
2509 break;
2510
e23eba97
NC		 2511 default:
2512 /* This case is unreachable. */
2513 abort ();
2514 }
2515 }
2516 /* Fall through. */
2517
2518 case BFD_RELOC_RVA:
2519 /* If we are deleting this reloc entry, we must fill in the
2520 value now. This can happen if we have a .word which is not
2521 resolved when it appears but is later defined. */
2522 if (fixP->fx_addsy == NULL)
2523 {
2524 gas_assert (fixP->fx_size <= sizeof (valueT));
2525 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
2526 fixP->fx_done = 1;
2527 }
2528 break;
2529
2530 case BFD_RELOC_RISCV_JMP:
2531 if (fixP->fx_addsy)
2532 {
2533 /* Fill in a tentative value to improve objdump readability. */
2534 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2535 bfd_vma delta = target - md_pcrel_from (fixP);
2536 bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
2537 }
2538 break;
2539
2540 case BFD_RELOC_12_PCREL:
2541 if (fixP->fx_addsy)
2542 {
2543 /* Fill in a tentative value to improve objdump readability. */
2544 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2545 bfd_vma delta = target - md_pcrel_from (fixP);
2546 bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
2547 }
2548 break;
2549
2550 case BFD_RELOC_RISCV_RVC_BRANCH:
2551 if (fixP->fx_addsy)
2552 {
2553 /* Fill in a tentative value to improve objdump readability. */
2554 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2555 bfd_vma delta = target - md_pcrel_from (fixP);
2556 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
2557 }
2558 break;
2559
2560 case BFD_RELOC_RISCV_RVC_JUMP:
2561 if (fixP->fx_addsy)
2562 {
2563 /* Fill in a tentative value to improve objdump readability. */
2564 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2565 bfd_vma delta = target - md_pcrel_from (fixP);
2566 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
2567 }
2568 break;
2569
e23eba97
NC		 2570 case BFD_RELOC_RISCV_CALL:
2571 case BFD_RELOC_RISCV_CALL_PLT:
45f76423
AW		 2572 relaxable = TRUE;
2573 break;
2574
9d06997a 2575 case BFD_RELOC_RISCV_PCREL_HI20:
45f76423
AW		 2576 case BFD_RELOC_RISCV_PCREL_LO12_S:
2577 case BFD_RELOC_RISCV_PCREL_LO12_I:
9d06997a
PD		 2578 relaxable = riscv_opts.relax;
2579 break;
2580
e23eba97
NC		 2581 case BFD_RELOC_RISCV_ALIGN:
2582 break;
2583
2584 default:
2585 /* We ignore generic BFD relocations we don't know about. */
2586 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
2587 as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type);
2588 }
45f76423 2589
e294484e
AW		 2590 if (fixP->fx_subsy != NULL)
2591 as_bad_where (fixP->fx_file, fixP->fx_line,
2592 _("unsupported symbol subtraction"));
2593
45f76423
AW		 2594 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2595 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
2596 {
2597 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2598 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
2599 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
2600 }
2601}
2602
2603/* Because the value of .cfi_remember_state may changed after relaxation,
2604 we insert a fix to relocate it again in link-time. */
2605
2606void
2607riscv_pre_output_hook (void)
2608{
2609 const frchainS *frch;
2610 const asection *s;
2611
2612 for (s = stdoutput->sections; s; s = s->next)
2613 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
2614 {
7cb7b948 2615 fragS *frag;
45f76423
AW		 2616
2617 for (frag = frch->frch_root; frag; frag = frag->fr_next)
2618 {
2619 if (frag->fr_type == rs_cfa)
2620 {
45f76423 2621 expressionS exp;
8d1015a8 2622 expressionS *symval;
45f76423 2623
8d1015a8 2624 symval = symbol_get_value_expression (frag->fr_symbol);
45f76423 2625 exp.X_op = O_subtract;
8d1015a8 2626 exp.X_add_symbol = symval->X_add_symbol;
45f76423 2627 exp.X_add_number = 0;
8d1015a8 2628 exp.X_op_symbol = symval->X_op_symbol;
45f76423 2629
c1b465c9 2630 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
45f76423
AW		 2631 BFD_RELOC_RISCV_CFA);
2632 }
2633 }
2634 }
e23eba97
NC		 2635}
2636
45f76423 2637
e23eba97
NC		 2638/* This structure is used to hold a stack of .option values. */
2639
2640struct riscv_option_stack
2641{
2642 struct riscv_option_stack *next;
2643 struct riscv_set_options options;
2644};
2645
2646static struct riscv_option_stack *riscv_opts_stack;
2647
2648/* Handle the .option pseudo-op. */
2649
2650static void
2651s_riscv_option (int x ATTRIBUTE_UNUSED)
2652{
2653 char *name = input_line_pointer, ch;
2654
2655 while (!is_end_of_line[(unsigned char) *input_line_pointer])
2656 ++input_line_pointer;
2657 ch = *input_line_pointer;
2658 *input_line_pointer = '\0';
2659
2660 if (strcmp (name, "rvc") == 0)
2661 riscv_set_rvc (TRUE);
2662 else if (strcmp (name, "norvc") == 0)
2663 riscv_set_rvc (FALSE);
2664 else if (strcmp (name, "pic") == 0)
2665 riscv_opts.pic = TRUE;
2666 else if (strcmp (name, "nopic") == 0)
2667 riscv_opts.pic = FALSE;
45f76423
AW		 2668 else if (strcmp (name, "relax") == 0)
2669 riscv_opts.relax = TRUE;
2670 else if (strcmp (name, "norelax") == 0)
2671 riscv_opts.relax = FALSE;
e23eba97
NC		 2672 else if (strcmp (name, "push") == 0)
2673 {
2674 struct riscv_option_stack *s;
2675
2676 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
2677 s->next = riscv_opts_stack;
2678 s->options = riscv_opts;
2679 riscv_opts_stack = s;
2680 }
2681 else if (strcmp (name, "pop") == 0)
2682 {
2683 struct riscv_option_stack *s;
2684
2685 s = riscv_opts_stack;
2686 if (s == NULL)
2687 as_bad (_(".option pop with no .option push"));
2688 else
2689 {
2690 riscv_opts = s->options;
2691 riscv_opts_stack = s->next;
2692 free (s);
2693 }
2694 }
2695 else
2696 {
2697 as_warn (_("Unrecognized .option directive: %s\n"), name);
2698 }
2699 *input_line_pointer = ch;
2700 demand_empty_rest_of_line ();
2701}
2702
2703/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2704 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2705 use in DWARF debug information. */
2706
2707static void
2708s_dtprel (int bytes)
2709{
2710 expressionS ex;
2711 char *p;
2712
2713 expression (&ex);
2714
2715 if (ex.X_op != O_symbol)
2716 {
2717 as_bad (_("Unsupported use of %s"), (bytes == 8
2718 ? ".dtpreldword"
2719 : ".dtprelword"));
2720 ignore_rest_of_line ();
2721 }
2722
2723 p = frag_more (bytes);
2724 md_number_to_chars (p, 0, bytes);
2725 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
2726 (bytes == 8
2727 ? BFD_RELOC_RISCV_TLS_DTPREL64
2728 : BFD_RELOC_RISCV_TLS_DTPREL32));
2729
2730 demand_empty_rest_of_line ();
2731}
2732
2733/* Handle the .bss pseudo-op. */
2734
2735static void
2736s_bss (int ignore ATTRIBUTE_UNUSED)
2737{
2738 subseg_set (bss_section, 0);
2739 demand_empty_rest_of_line ();
2740}
2741
e23eba97 2742static void
d115ab8e 2743riscv_make_nops (char *buf, bfd_vma bytes)
e23eba97 2744{
d115ab8e 2745 bfd_vma i = 0;
e23eba97 2746
e5b737de
AW		 2747 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2748 means we are not within a valid instruction sequence. It is thus safe
2749 to use a zero byte, even though that is not a valid instruction. */
2750 if (bytes % 2 == 1)
2751 buf[i++] = 0;
2752
2753 /* Use at most one 2-byte NOP. */
2754 if ((bytes - i) % 4 == 2)
e23eba97 2755 {
e5b737de 2756 md_number_to_chars (buf + i, RVC_NOP, 2);
d115ab8e 2757 i += 2;
e23eba97
NC		 2758 }
2759
e5b737de 2760 /* Fill the remainder with 4-byte NOPs. */
d115ab8e
AW		 2761 for ( ; i < bytes; i += 4)
2762 md_number_to_chars (buf + i, RISCV_NOP, 4);
2763}
e23eba97 2764
d115ab8e
AW		 2765/* Called from md_do_align. Used to create an alignment frag in a
2766 code section by emitting a worst-case NOP sequence that the linker
2767 will later relax to the correct number of NOPs. We can't compute
2768 the correct alignment now because of other linker relaxations. */
2769
2770bfd_boolean
2771riscv_frag_align_code (int n)
2772{
e5b737de 2773 bfd_vma bytes = (bfd_vma) 1 << n;
36877bfb
JW		 2774 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
2775 bfd_vma worst_case_bytes = bytes - insn_alignment;
2776 char *nops;
ed0816bd 2777 expressionS ex;
d115ab8e 2778
36877bfb
JW		 2779 /* If we are moving to a smaller alignment than the instruction size, then no
2780 alignment is required. */
2781 if (bytes <= insn_alignment)
2782 return TRUE;
2783
d115ab8e
AW		 2784 /* When not relaxing, riscv_handle_align handles code alignment. */
2785 if (!riscv_opts.relax)
2786 return FALSE;
e23eba97 2787
e80ae190
JW		 2788 nops = frag_more (worst_case_bytes);
2789
ed0816bd
PD		 2790 ex.X_op = O_constant;
2791 ex.X_add_number = worst_case_bytes;
d115ab8e 2792
ed0816bd 2793 riscv_make_nops (nops, worst_case_bytes);
e23eba97 2794
ed0816bd
PD		 2795 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
2796 &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
e23eba97 2797
d115ab8e
AW		 2798 return TRUE;
2799}
e23eba97 2800
d115ab8e
AW		 2801/* Implement HANDLE_ALIGN. */
2802
2803void
2804riscv_handle_align (fragS *fragP)
2805{
2806 switch (fragP->fr_type)
2807 {
2808 case rs_align_code:
2809 /* When relaxing, riscv_frag_align_code handles code alignment. */
2810 if (!riscv_opts.relax)
2811 {
e80ae190
JW		 2812 bfd_signed_vma bytes = (fragP->fr_next->fr_address
2813 - fragP->fr_address - fragP->fr_fix);
2814 /* We have 4 byte uncompressed nops. */
2815 bfd_signed_vma size = 4;
2816 bfd_signed_vma excess = bytes % size;
2817 char *p = fragP->fr_literal + fragP->fr_fix;
2818
2819 if (bytes <= 0)
d115ab8e
AW		 2820 break;
2821
e80ae190
JW		 2822 /* Insert zeros or compressed nops to get 4 byte alignment. */
2823 if (excess)
2824 {
2825 riscv_make_nops (p, excess);
2826 fragP->fr_fix += excess;
2827 p += excess;
2828 }
2829
2830 /* Insert variable number of 4 byte uncompressed nops. */
2831 riscv_make_nops (p, size);
2832 fragP->fr_var = size;
d115ab8e
AW		 2833 }
2834 break;
2835
2836 default:
2837 break;
2838 }
e23eba97
NC		 2839}
2840
2841int
2842md_estimate_size_before_relax (fragS *fragp, asection *segtype)
2843{
2844 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
2845}
2846
2847/* Translate internal representation of relocation info to BFD target
2848 format. */
2849
2850arelent *
2851tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
2852{
2853 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
2854
2855 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
2856 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
2857 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
2858 reloc->addend = fixp->fx_addnumber;
2859
2860 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
2861 if (reloc->howto == NULL)
2862 {
2863 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
2864 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
2865 {
2866 /* We don't have R_RISCV_8/16, but for this special case,
2867 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2868 return reloc;
2869 }
2870
2871 as_bad_where (fixp->fx_file, fixp->fx_line,
2872 _("cannot represent %s relocation in object file"),
2873 bfd_get_reloc_code_name (fixp->fx_r_type));
2874 return NULL;
2875 }
2876
2877 return reloc;
2878}
2879
2880int
2881riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
2882{
2883 if (RELAX_BRANCH_P (fragp->fr_subtype))
2884 {
2885 offsetT old_var = fragp->fr_var;
2886 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
2887 return fragp->fr_var - old_var;
2888 }
2889
2890 return 0;
2891}
2892
2893/* Expand far branches to multi-instruction sequences. */
2894
2895static void
2896md_convert_frag_branch (fragS *fragp)
2897{
2898 bfd_byte *buf;
2899 expressionS exp;
2900 fixS *fixp;
2901 insn_t insn;
2902 int rs1, reloc;
2903
2904 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
2905
2906 exp.X_op = O_symbol;
2907 exp.X_add_symbol = fragp->fr_symbol;
2908 exp.X_add_number = fragp->fr_offset;
2909
2910 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
2911
2912 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
2913 {
2914 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
2915 {
2916 case 8:
2917 case 4:
2918 /* Expand the RVC branch into a RISC-V one. */
2919 insn = bfd_getl16 (buf);
2920 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
2921 if ((insn & MASK_C_J) == MATCH_C_J)
2922 insn = MATCH_JAL;
2923 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
2924 insn = MATCH_JAL | (X_RA << OP_SH_RD);
2925 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
2926 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
2927 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
2928 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
2929 else
2930 abort ();
2931 bfd_putl32 (insn, buf);
2932 break;
2933
2934 case 6:
2935 /* Invert the branch condition. Branch over the jump. */
2936 insn = bfd_getl16 (buf);
2937 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
2938 insn |= ENCODE_RVC_B_IMM (6);
2939 bfd_putl16 (insn, buf);
2940 buf += 2;
2941 goto jump;
2942
2943 case 2:
2944 /* Just keep the RVC branch. */
2945 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
2946 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
2947 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
2948 2, &exp, FALSE, reloc);
2949 buf += 2;
2950 goto done;
2951
2952 default:
1d65abb5 2953 abort ();
e23eba97
NC		 2954 }
2955 }
2956
2957 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
2958 {
2959 case 8:
2960 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
2961
2962 /* Invert the branch condition. Branch over the jump. */
2963 insn = bfd_getl32 (buf);
2964 insn ^= MATCH_BEQ ^ MATCH_BNE;
2965 insn |= ENCODE_SBTYPE_IMM (8);
2966 md_number_to_chars ((char *) buf, insn, 4);
2967 buf += 4;
2968
2969jump:
2970 /* Jump to the target. */
2971 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
2972 4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
2973 md_number_to_chars ((char *) buf, MATCH_JAL, 4);
2974 buf += 4;
2975 break;
2976
2977 case 4:
2978 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
2979 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
2980 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
2981 4, &exp, FALSE, reloc);
2982 buf += 4;
2983 break;
2984
2985 default:
2986 abort ();
2987 }
2988
2989done:
2990 fixp->fx_file = fragp->fr_file;
2991 fixp->fx_line = fragp->fr_line;
2992
2993 gas_assert (buf == (bfd_byte *)fragp->fr_literal
2994 + fragp->fr_fix + fragp->fr_var);
2995
2996 fragp->fr_fix += fragp->fr_var;
2997}
2998
2999/* Relax a machine dependent frag. This returns the amount by which
3000 the current size of the frag should change. */
3001
3002void
3003md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3004 fragS *fragp)
3005{
3006 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
3007 md_convert_frag_branch (fragp);
3008}
3009
3010void
3011md_show_usage (FILE *stream)
3012{
3013 fprintf (stream, _("\
3014RISC-V options:\n\
e23eba97
NC		 3015 -fpic generate position-independent code\n\
3016 -fno-pic don't generate position-independent code (default)\n\
19683c04
PD		 3017 -march=ISA set the RISC-V architecture\n\
3018 -mabi=ABI set the RISC-V ABI\n\
71060565
JW		 3019 -mrelax enable relax (default)\n\
3020 -mno-relax disable relax\n\
e23eba97
NC		 3021"));
3022}
3023
3024/* Standard calling conventions leave the CFA at SP on entry. */
3025void
3026riscv_cfi_frame_initial_instructions (void)
3027{
3028 cfi_add_CFA_def_cfa_register (X_SP);
3029}
3030
3031int
3032tc_riscv_regname_to_dw2regnum (char *regname)
3033{
3034 int reg;
3035
3036 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3037 return reg;
3038
3039 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3040 return reg + 32;
3041
3042 as_bad (_("unknown register `%s'"), regname);
3043 return -1;
3044}
3045
3046void
3047riscv_elf_final_processing (void)
3048{
e23eba97 3049 elf_elfheader (stdoutput)->e_flags |= elf_flags;
e23eba97
NC		 3050}
3051
3052/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3053 since these directives break relaxation when used with symbol deltas. */
3054
3055static void
3056s_riscv_leb128 (int sign)
3057{
3058 expressionS exp;
3059 char *save_in = input_line_pointer;
3060
3061 expression (&exp);
3062 if (exp.X_op != O_constant)
3063 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3064 demand_empty_rest_of_line ();
3065
3066 input_line_pointer = save_in;
3067 return s_leb128 (sign);
3068}
3069
0e35537d
JW		 3070/* Parse the .insn directive. */
3071
3072static void
3073s_riscv_insn (int x ATTRIBUTE_UNUSED)
3074{
3075 char *str = input_line_pointer;
3076 struct riscv_cl_insn insn;
3077 expressionS imm_expr;
3078 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3079 char save_c;
3080
3081 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3082 ++input_line_pointer;
3083
3084 save_c = *input_line_pointer;
3085 *input_line_pointer = '\0';
3086
3087 const char *error = riscv_ip (str, &insn, &imm_expr,
3088 &imm_reloc, insn_type_hash);
3089
3090 if (error)
3091 {
3092 as_bad ("%s `%s'", error, str);
3093 }
3094 else
3095 {
3096 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3097 append_insn (&insn, &imm_expr, imm_reloc);
3098 }
3099
3100 *input_line_pointer = save_c;
3101 demand_empty_rest_of_line ();
3102}
3103
e23eba97
NC		 3104/* Pseudo-op table. */
3105
3106static const pseudo_typeS riscv_pseudo_table[] =
3107{
3108 /* RISC-V-specific pseudo-ops. */
3109 {"option", s_riscv_option, 0},
3110 {"half", cons, 2},
3111 {"word", cons, 4},
3112 {"dword", cons, 8},
3113 {"dtprelword", s_dtprel, 4},
3114 {"dtpreldword", s_dtprel, 8},
3115 {"bss", s_bss, 0},
e23eba97
NC		 3116 {"uleb128", s_riscv_leb128, 0},
3117 {"sleb128", s_riscv_leb128, 1},
0e35537d 3118 {"insn", s_riscv_insn, 0},
e23eba97
NC		 3119
3120 { NULL, NULL, 0 },
3121};
3122
3123void
3124riscv_pop_insert (void)
3125{
3126 extern void pop_insert (const pseudo_typeS *);
3127
3128 pop_insert (riscv_pseudo_table);
3129}
GDB Binutils - Deliverables
This page took 0.286948 seconds and 4 git commands to generate.