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[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
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e23eba97 1/* tc-riscv.c -- RISC-V assembler
250d07de 2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
3d73d29e 32#include "bfd/cpu-riscv.h"
1080bf78 33#include "bfd/elfxx-riscv.h"
e23eba97
NC		 34#include "elf/riscv.h"
35#include "opcode/riscv.h"
36
37#include <stdint.h>
38
39/* Information about an instruction, including its format, operands
40 and fixups. */
41struct riscv_cl_insn
42{
43 /* The opcode's entry in riscv_opcodes. */
44 const struct riscv_opcode *insn_mo;
45
46 /* The encoded instruction bits. */
47 insn_t insn_opcode;
48
49 /* The frag that contains the instruction. */
50 struct frag *frag;
51
52 /* The offset into FRAG of the first instruction byte. */
53 long where;
54
55 /* The relocs associated with the instruction, if any. */
56 fixS *fixp;
57};
58
3d73d29e
NC		 59/* All RISC-V CSR belong to one of these classes. */
60enum riscv_csr_class
61{
62 CSR_CLASS_NONE,
63
64 CSR_CLASS_I,
65 CSR_CLASS_I_32, /* rv32 only */
66 CSR_CLASS_F, /* f-ext only */
67 CSR_CLASS_DEBUG /* debug CSR */
68};
69
70/* This structure holds all restricted conditions for a CSR. */
71struct riscv_csr_extra
72{
73 /* Class to which this CSR belongs. Used to decide whether or
74 not this CSR is legal in the current -march context. */
75 enum riscv_csr_class csr_class;
76
77 /* CSR may have differnet numbers in the previous priv spec. */
78 unsigned address;
79
80 /* Record the CSR is defined/valid in which versions. */
81 enum riscv_spec_class define_version;
82
83 /* Record the CSR is aborted/invalid from which versions. If it isn't
84 aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
85 enum riscv_spec_class abort_version;
86
87 /* The CSR may have more than one setting. */
88 struct riscv_csr_extra *next;
89};
90
91/* All standard/Z* extensions defined in all supported ISA spec. */
92struct riscv_ext_version
93{
94 const char *name;
95 enum riscv_spec_class isa_spec_class;
96 int major_version;
97 int minor_version;
98};
99
100static const struct riscv_ext_version ext_version_table[] =
101{
102 {"e", ISA_SPEC_CLASS_20191213, 1, 9},
103 {"e", ISA_SPEC_CLASS_20190608, 1, 9},
104 {"e", ISA_SPEC_CLASS_2P2, 1, 9},
105
106 {"i", ISA_SPEC_CLASS_20191213, 2, 1},
107 {"i", ISA_SPEC_CLASS_20190608, 2, 1},
108 {"i", ISA_SPEC_CLASS_2P2, 2, 0},
109
110 {"m", ISA_SPEC_CLASS_20191213, 2, 0},
111 {"m", ISA_SPEC_CLASS_20190608, 2, 0},
112 {"m", ISA_SPEC_CLASS_2P2, 2, 0},
113
114 {"a", ISA_SPEC_CLASS_20191213, 2, 1},
115 {"a", ISA_SPEC_CLASS_20190608, 2, 0},
116 {"a", ISA_SPEC_CLASS_2P2, 2, 0},
117
118 {"f", ISA_SPEC_CLASS_20191213, 2, 2},
119 {"f", ISA_SPEC_CLASS_20190608, 2, 2},
120 {"f", ISA_SPEC_CLASS_2P2, 2, 0},
121
122 {"d", ISA_SPEC_CLASS_20191213, 2, 2},
123 {"d", ISA_SPEC_CLASS_20190608, 2, 2},
124 {"d", ISA_SPEC_CLASS_2P2, 2, 0},
125
126 {"q", ISA_SPEC_CLASS_20191213, 2, 2},
127 {"q", ISA_SPEC_CLASS_20190608, 2, 2},
128 {"q", ISA_SPEC_CLASS_2P2, 2, 0},
129
130 {"c", ISA_SPEC_CLASS_20191213, 2, 0},
131 {"c", ISA_SPEC_CLASS_20190608, 2, 0},
132 {"c", ISA_SPEC_CLASS_2P2, 2, 0},
133
134 {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
135 {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
136
137 {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
138 {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
139
140 {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
141
80d49d6a
KLC		 142 {"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93},
143 {"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
144 {"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},
145
3d73d29e
NC		 146 /* Terminate the list. */
147 {NULL, 0, 0, 0}
148};
149
e23eba97
NC		 150#ifndef DEFAULT_ARCH
151#define DEFAULT_ARCH "riscv64"
152#endif
153
2dc8dd17
JW		 154#ifndef DEFAULT_RISCV_ATTR
155#define DEFAULT_RISCV_ATTR 0
156#endif
157
8f595e9b 158/* Let riscv_after_parse_args set the default value according to xlen. */
8f595e9b
NC		 159#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
160#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
161#endif
162
dcd709e0 163/* Need to sync the version with RISC-V compiler. */
8f595e9b
NC		 164#ifndef DEFAULT_RISCV_ISA_SPEC
165#define DEFAULT_RISCV_ISA_SPEC "2.2"
166#endif
167
168#ifndef DEFAULT_RISCV_PRIV_SPEC
169#define DEFAULT_RISCV_PRIV_SPEC "1.11"
170#endif
171
e23eba97 172static const char default_arch[] = DEFAULT_ARCH;
8f595e9b 173static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
3d73d29e
NC		 174static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
175static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
e23eba97 176
dcd709e0
NC		 177static unsigned xlen = 0; /* The width of an x-register. */
178static unsigned abi_xlen = 0; /* The width of a pointer in the ABI. */
5b7c81bd 179static bool rve_abi = false;
1942a048
NC		 180enum float_abi
181{
6e1605e4
NC		 182 FLOAT_ABI_DEFAULT = -1,
183 FLOAT_ABI_SOFT,
184 FLOAT_ABI_SINGLE,
185 FLOAT_ABI_DOUBLE,
186 FLOAT_ABI_QUAD
187};
188static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
e23eba97 189
2922d21d 190#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
e23eba97
NC		 191#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
192
193static unsigned elf_flags = 0;
194
dcd709e0
NC		 195/* Set the default_isa_spec. Return 0 if the spec isn't supported.
196 Otherwise, return 1. */
8f595e9b
NC		 197
198static int
199riscv_set_default_isa_spec (const char *s)
200{
3d73d29e
NC		 201 enum riscv_spec_class class = ISA_SPEC_CLASS_NONE;
202 RISCV_GET_ISA_SPEC_CLASS (s, class);
203 if (class == ISA_SPEC_CLASS_NONE)
8f595e9b 204 {
b800637e
NC		 205 as_bad ("unknown default ISA spec `%s' set by "
206 "-misa-spec or --with-isa-spec", s);
8f595e9b
NC		 207 return 0;
208 }
209 else
210 default_isa_spec = class;
211 return 1;
212}
213
dcd709e0
NC		 214/* Set the default_priv_spec. Find the privileged elf attributes when
215 the input string is NULL. Return 0 if the spec isn't supported.
216 Otherwise, return 1. */
8f595e9b
NC		 217
218static int
219riscv_set_default_priv_spec (const char *s)
220{
3d73d29e 221 enum riscv_spec_class class = PRIV_SPEC_CLASS_NONE;
8f595e9b
NC		 222 unsigned major, minor, revision;
223 obj_attribute *attr;
8f595e9b 224
3d73d29e
NC		 225 RISCV_GET_PRIV_SPEC_CLASS (s, class);
226 if (class != PRIV_SPEC_CLASS_NONE)
8f595e9b
NC		 227 {
228 default_priv_spec = class;
229 return 1;
230 }
231
232 if (s != NULL)
233 {
b800637e
NC		 234 as_bad (_("unknown default privileged spec `%s' set by "
235 "-mpriv-spec or --with-priv-spec"), s);
8f595e9b
NC		 236 return 0;
237 }
238
dcd709e0 239 /* Set the default_priv_spec by the privileged elf attributes. */
8f595e9b
NC		 240 attr = elf_known_obj_attributes_proc (stdoutput);
241 major = (unsigned) attr[Tag_RISCV_priv_spec].i;
242 minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
243 revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
3d73d29e
NC		 244 /* Version 0.0.0 is the default value and meningless. */
245 if (major == 0 && minor == 0 && revision == 0)
246 return 1;
8f595e9b 247
3d73d29e
NC		 248 riscv_get_priv_spec_class_from_numbers (major, minor, revision, &class);
249 if (class != PRIV_SPEC_CLASS_NONE)
250 {
8f595e9b 251 default_priv_spec = class;
8f595e9b
NC		 252 return 1;
253 }
254
dcd709e0 255 /* Still can not find the privileged spec class. */
b800637e
NC		 256 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
257 "privileged elf attributes"), major, minor, revision);
8f595e9b
NC		 258 return 0;
259}
260
e23eba97 261/* This is the set of options which the .option pseudo-op may modify. */
e23eba97
NC		 262struct riscv_set_options
263{
264 int pic; /* Generate position-independent code. */
265 int rvc; /* Generate RVC code. */
7f999549 266 int rve; /* Generate RVE code. */
45f76423 267 int relax; /* Emit relocs the linker is allowed to relax. */
dcd709e0 268 int arch_attr; /* Emit architecture and privileged elf attributes. */
2ca89224 269 int csr_check; /* Enable the CSR checking. */
e23eba97
NC		 270};
271
272static struct riscv_set_options riscv_opts =
273{
dcd709e0
NC		 274 0, /* pic */
275 0, /* rvc */
276 0, /* rve */
277 1, /* relax */
2dc8dd17 278 DEFAULT_RISCV_ATTR, /* arch_attr */
dcd709e0 279 0, /* csr_check */
e23eba97
NC		 280};
281
282static void
5b7c81bd 283riscv_set_rvc (bool rvc_value)
e23eba97
NC		 284{
285 if (rvc_value)
286 elf_flags |= EF_RISCV_RVC;
287
288 riscv_opts.rvc = rvc_value;
289}
290
7f999549 291static void
5b7c81bd 292riscv_set_rve (bool rve_value)
7f999549
JW		 293{
294 riscv_opts.rve = rve_value;
295}
296
1080bf78 297static riscv_subset_list_t riscv_subsets;
e23eba97 298
5b7c81bd 299static bool
1080bf78 300riscv_subset_supports (const char *feature)
e23eba97 301{
dfe92496
NC		 302 struct riscv_subset_t *subset;
303
1080bf78 304 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
5b7c81bd 305 return true;
e23eba97 306
dfe92496 307 return riscv_lookup_subset (&riscv_subsets, feature, &subset);
e23eba97
NC		 308}
309
5b7c81bd 310static bool
7e9ad3a3 311riscv_multi_subset_supports (enum riscv_insn_class insn_class)
43135d3b 312{
7e9ad3a3
JW		 313 switch (insn_class)
314 {
315 case INSN_CLASS_I: return riscv_subset_supports ("i");
316 case INSN_CLASS_C: return riscv_subset_supports ("c");
317 case INSN_CLASS_A: return riscv_subset_supports ("a");
318 case INSN_CLASS_M: return riscv_subset_supports ("m");
319 case INSN_CLASS_F: return riscv_subset_supports ("f");
320 case INSN_CLASS_D: return riscv_subset_supports ("d");
729a5353 321 case INSN_CLASS_Q: return riscv_subset_supports ("q");
7e9ad3a3
JW		 322
323 case INSN_CLASS_F_AND_C:
729a5353
NC		 324 return (riscv_subset_supports ("f")
325 && riscv_subset_supports ("c"));
326 case INSN_CLASS_D_AND_C:
327 return (riscv_subset_supports ("d")
328 && riscv_subset_supports ("c"));
43135d3b 329
729a5353
NC		 330 case INSN_CLASS_ZICSR:
331 return riscv_subset_supports ("zicsr");
332 case INSN_CLASS_ZIFENCEI:
333 return riscv_subset_supports ("zifencei");
aa881ecd
PT		 334 case INSN_CLASS_ZIHINTPAUSE:
335 return riscv_subset_supports ("zihintpause");
43135d3b 336
80d49d6a
KLC		 337 case INSN_CLASS_ZBB:
338 return riscv_subset_supports ("zbb");
339
340 case INSN_CLASS_ZBA:
341 return riscv_subset_supports ("zba");
342
343 case INSN_CLASS_ZBC:
344 return riscv_subset_supports ("zbc");
345
7e9ad3a3 346 default:
b800637e 347 as_fatal ("internal: unreachable");
5b7c81bd 348 return false;
7e9ad3a3 349 }
43135d3b
JW		 350}
351
8f595e9b 352/* Handle of the extension with version hash table. */
629310ab 353static htab_t ext_version_hash = NULL;
8f595e9b 354
629310ab 355static htab_t
3d73d29e 356init_ext_version_hash (void)
8f595e9b 357{
3d73d29e 358 const struct riscv_ext_version *table = ext_version_table;
629310ab 359 htab_t hash = str_htab_create ();
3d73d29e 360 int i = 0;
8f595e9b
NC		 361
362 while (table[i].name)
363 {
364 const char *name = table[i].name;
fe0e921f 365 if (str_hash_insert (hash, name, &table[i], 0) != NULL)
b800637e 366 as_fatal (_("internal: duplicate %s"), name);
8f595e9b
NC		 367
368 i++;
369 while (table[i].name
1942a048 370 && strcmp (table[i].name, name) == 0)
8f595e9b
NC		 371 i++;
372 }
373
374 return hash;
375}
376
377static void
378riscv_get_default_ext_version (const char *name,
7ef19aa6
NC		 379 int *major_version,
380 int *minor_version)
8f595e9b
NC		 381{
382 struct riscv_ext_version *ext;
383
8f595e9b
NC		 384 if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
385 return;
386
629310ab 387 ext = (struct riscv_ext_version *) str_hash_find (ext_version_hash, name);
8f595e9b 388 while (ext
7ef19aa6
NC		 389 && ext->name
390 && strcmp (ext->name, name) == 0)
8f595e9b 391 {
2652cfad
CXW		 392 if (ext->isa_spec_class == ISA_SPEC_CLASS_DRAFT
393 || ext->isa_spec_class == default_isa_spec)
7ef19aa6
NC		 394 {
395 *major_version = ext->major_version;
396 *minor_version = ext->minor_version;
397 return;
398 }
8f595e9b
NC		 399 ext++;
400 }
401}
402
2922d21d 403/* Set which ISA and extensions are available. */
e23eba97 404
e23eba97 405static void
2922d21d 406riscv_set_arch (const char *s)
e23eba97 407{
1080bf78
JW		 408 riscv_parse_subset_t rps;
409 rps.subset_list = &riscv_subsets;
7ef19aa6 410 rps.error_handler = as_bad;
1080bf78 411 rps.xlen = &xlen;
8f595e9b
NC		 412 rps.get_default_version = riscv_get_default_ext_version;
413
414 if (s == NULL)
415 return;
7f999549 416
1080bf78
JW		 417 riscv_release_subset_list (&riscv_subsets);
418 riscv_parse_subset (&rps, s);
e23eba97
NC		 419}
420
dcd709e0 421/* Indicate -mabi option is explictly set. */
5b7c81bd 422static bool explicit_mabi = false;
6e1605e4
NC		 423
424static void
5b7c81bd 425riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bool rve)
6e1605e4
NC		 426{
427 abi_xlen = new_xlen;
428 float_abi = new_float_abi;
429 rve_abi = rve;
430}
431
dcd709e0
NC		 432/* If the -mabi option isn't set, then set the abi according to the
433 ISA string. Otherwise, check if there is any conflict. */
6e1605e4
NC		 434
435static void
436riscv_set_abi_by_arch (void)
437{
438 if (!explicit_mabi)
439 {
440 if (riscv_subset_supports ("q"))
5b7c81bd 441 riscv_set_abi (xlen, FLOAT_ABI_QUAD, false);
6e1605e4 442 else if (riscv_subset_supports ("d"))
5b7c81bd 443 riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, false);
6e1605e4 444 else
5b7c81bd 445 riscv_set_abi (xlen, FLOAT_ABI_SOFT, false);
6e1605e4
NC		 446 }
447 else
448 {
449 gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT);
450 if (abi_xlen > xlen)
451 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
452 else if (abi_xlen < xlen)
453 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
454 }
455
456 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
457 elf_flags &= ~EF_RISCV_FLOAT_ABI;
458 elf_flags |= float_abi << 1;
459
460 if (rve_abi)
461 elf_flags |= EF_RISCV_RVE;
462}
463
e23eba97 464/* Handle of the OPCODE hash table. */
629310ab 465static htab_t op_hash = NULL;
e23eba97 466
0e35537d 467/* Handle of the type of .insn hash table. */
629310ab 468static htab_t insn_type_hash = NULL;
0e35537d 469
e23eba97 470/* This array holds the chars that always start a comment. If the
dcd709e0 471 pre-processor is disabled, these aren't very useful. */
e23eba97
NC		 472const char comment_chars[] = "#";
473
474/* This array holds the chars that only start a comment at the beginning of
475 a line. If the line seems to have the form '# 123 filename'
dcd709e0
NC		 476 .line and .file directives will appear in the pre-processed output
477
478 Note that input_file.c hand checks for '#' at the beginning of the
e23eba97 479 first line of the input file. This is because the compiler outputs
dcd709e0
NC		 480 #NO_APP at the beginning of its output.
481
482 Also note that C style comments are always supported. */
e23eba97
NC		 483const char line_comment_chars[] = "#";
484
485/* This array holds machine specific line separator characters. */
486const char line_separator_chars[] = ";";
487
dcd709e0 488/* Chars that can be used to separate mant from exp in floating point nums. */
e23eba97
NC		 489const char EXP_CHARS[] = "eE";
490
dcd709e0
NC		 491/* Chars that mean this number is a floating point constant.
492 As in 0f12.456 or 0d1.2345e12. */
e23eba97
NC		 493const char FLT_CHARS[] = "rRsSfFdDxXpP";
494
2dc8dd17 495/* Indicate we are already assemble any instructions or not. */
5b7c81bd 496static bool start_assemble = false;
2dc8dd17 497
f9a6a8f0 498/* Indicate ELF attributes are explicitly set. */
5b7c81bd 499static bool explicit_attr = false;
2dc8dd17 500
f9a6a8f0 501/* Indicate CSR or priv instructions are explicitly used. */
5b7c81bd 502static bool explicit_priv_attr = false;
3fc6c3dc 503
e23eba97
NC		 504/* Macros for encoding relaxation state for RVC branches and far jumps. */
505#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
506 ((relax_substateT) \
507 (0xc0000000 \
508 | ((uncond) ? 1 : 0) \
509 | ((rvc) ? 2 : 0) \
510 | ((length) << 2)))
511#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
512#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
513#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
514#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
515
516/* Is the given value a sign-extended 32-bit value? */
517#define IS_SEXT_32BIT_NUM(x) \
518 (((x) &~ (offsetT) 0x7fffffff) == 0 \
519 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
520
521/* Is the given value a zero-extended 32-bit value? Or a negated one? */
522#define IS_ZEXT_32BIT_NUM(x) \
523 (((x) &~ (offsetT) 0xffffffff) == 0 \
524 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
525
526/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
527 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
528#define INSERT_OPERAND(FIELD, INSN, VALUE) \
529 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
530
531/* Determine if an instruction matches an opcode. */
532#define OPCODE_MATCHES(OPCODE, OP) \
533 (((OPCODE) & MASK_##OP) == MATCH_##OP)
534
535static char *expr_end;
536
537/* The default target format to use. */
538
539const char *
540riscv_target_format (void)
541{
fbc09e7a
MC		 542 if (target_big_endian)
543 return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv";
544 else
545 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
e23eba97
NC		 546}
547
548/* Return the length of instruction INSN. */
549
550static inline unsigned int
551insn_length (const struct riscv_cl_insn *insn)
552{
553 return riscv_insn_length (insn->insn_opcode);
554}
555
556/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
557
558static void
559create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
560{
561 insn->insn_mo = mo;
562 insn->insn_opcode = mo->match;
563 insn->frag = NULL;
564 insn->where = 0;
565 insn->fixp = NULL;
566}
567
568/* Install INSN at the location specified by its "frag" and "where" fields. */
569
570static void
571install_insn (const struct riscv_cl_insn *insn)
572{
573 char *f = insn->frag->fr_literal + insn->where;
fbc09e7a 574 number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn));
e23eba97
NC		 575}
576
577/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
578 and install the opcode in the new location. */
579
580static void
581move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
582{
583 insn->frag = frag;
584 insn->where = where;
585 if (insn->fixp != NULL)
586 {
587 insn->fixp->fx_frag = frag;
588 insn->fixp->fx_where = where;
589 }
590 install_insn (insn);
591}
592
593/* Add INSN to the end of the output. */
594
595static void
596add_fixed_insn (struct riscv_cl_insn *insn)
597{
598 char *f = frag_more (insn_length (insn));
599 move_insn (insn, frag_now, f - frag_now->fr_literal);
600}
601
602static void
603add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
604 relax_substateT subtype, symbolS *symbol, offsetT offset)
605{
606 frag_grow (max_chars);
607 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
608 frag_var (rs_machine_dependent, max_chars, var,
609 subtype, symbol, offset, NULL);
610}
611
612/* Compute the length of a branch sequence, and adjust the stored length
613 accordingly. If FRAGP is NULL, the worst-case length is returned. */
614
615static unsigned
616relaxed_branch_length (fragS *fragp, asection *sec, int update)
617{
618 int jump, rvc, length = 8;
619
620 if (!fragp)
621 return length;
622
623 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
624 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
625 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
626
627 /* Assume jumps are in range; the linker will catch any that aren't. */
628 length = jump ? 4 : 8;
629
630 if (fragp->fr_symbol != NULL
631 && S_IS_DEFINED (fragp->fr_symbol)
01156111 632 && !S_IS_WEAK (fragp->fr_symbol)
e23eba97
NC		 633 && sec == S_GET_SEGMENT (fragp->fr_symbol))
634 {
635 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
636 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
637 val -= fragp->fr_address + fragp->fr_fix;
638
639 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
640 length = 2;
641 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
642 length = 4;
643 else if (!jump && rvc)
644 length = 6;
645 }
646
647 if (update)
648 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
649
650 return length;
651}
652
0e35537d
JW		 653/* Information about an opcode name, mnemonics and its value. */
654struct opcode_name_t
655{
656 const char *name;
657 unsigned int val;
658};
659
660/* List for all supported opcode name. */
661static const struct opcode_name_t opcode_name_list[] =
662{
663 {"C0", 0x0},
664 {"C1", 0x1},
665 {"C2", 0x2},
666
667 {"LOAD", 0x03},
668 {"LOAD_FP", 0x07},
669 {"CUSTOM_0", 0x0b},
670 {"MISC_MEM", 0x0f},
671 {"OP_IMM", 0x13},
672 {"AUIPC", 0x17},
673 {"OP_IMM_32", 0x1b},
674 /* 48b 0x1f. */
675
676 {"STORE", 0x23},
677 {"STORE_FP", 0x27},
678 {"CUSTOM_1", 0x2b},
679 {"AMO", 0x2f},
680 {"OP", 0x33},
681 {"LUI", 0x37},
682 {"OP_32", 0x3b},
683 /* 64b 0x3f. */
684
685 {"MADD", 0x43},
686 {"MSUB", 0x47},
687 {"NMADD", 0x4f},
688 {"NMSUB", 0x4b},
689 {"OP_FP", 0x53},
690 /*reserved 0x57. */
691 {"CUSTOM_2", 0x5b},
692 /* 48b 0x5f. */
693
694 {"BRANCH", 0x63},
695 {"JALR", 0x67},
696 /*reserved 0x5b. */
697 {"JAL", 0x6f},
698 {"SYSTEM", 0x73},
699 /*reserved 0x77. */
700 {"CUSTOM_3", 0x7b},
701 /* >80b 0x7f. */
702
703 {NULL, 0}
704};
705
706/* Hash table for lookup opcode name. */
629310ab 707static htab_t opcode_names_hash = NULL;
0e35537d
JW		 708
709/* Initialization for hash table of opcode name. */
dcd709e0 710
0e35537d
JW		 711static void
712init_opcode_names_hash (void)
713{
0e35537d
JW		 714 const struct opcode_name_t *opcode;
715
716 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
fe0e921f 717 if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL)
b800637e 718 as_fatal (_("internal: duplicate %s"), opcode->name);
0e35537d
JW		 719}
720
dcd709e0
NC		 721/* Find `s` is a valid opcode name or not, return the opcode name info
722 if found. */
723
0e35537d
JW		 724static const struct opcode_name_t *
725opcode_name_lookup (char **s)
726{
727 char *e;
728 char save_c;
729 struct opcode_name_t *o;
730
731 /* Find end of name. */
732 e = *s;
733 if (is_name_beginner (*e))
734 ++e;
735 while (is_part_of_name (*e))
736 ++e;
737
738 /* Terminate name. */
739 save_c = *e;
740 *e = '\0';
741
629310ab 742 o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s);
0e35537d
JW		 743
744 /* Advance to next token if one was recognized. */
745 if (o)
746 *s = e;
747
748 *e = save_c;
749 expr_end = e;
750
751 return o;
752}
753
e23eba97
NC		 754enum reg_class
755{
756 RCLASS_GPR,
757 RCLASS_FPR,
8f595e9b
NC		 758 RCLASS_MAX,
759
760 RCLASS_CSR
e23eba97
NC		 761};
762
629310ab
ML		 763static htab_t reg_names_hash = NULL;
764static htab_t csr_extra_hash = NULL;
e23eba97
NC		 765
766#define ENCODE_REG_HASH(cls, n) \
767 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
768#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
769#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
770
771static void
772hash_reg_name (enum reg_class class, const char *name, unsigned n)
773{
774 void *hash = ENCODE_REG_HASH (class, n);
fe0e921f 775 if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL)
b800637e 776 as_fatal (_("internal: duplicate %s"), name);
e23eba97
NC		 777}
778
779static void
780hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
781{
782 unsigned i;
783
784 for (i = 0; i < n; i++)
785 hash_reg_name (class, names[i], i);
786}
787
8f595e9b 788/* Init hash table csr_extra_hash to handle CSR. */
dcd709e0 789
8f595e9b
NC		 790static void
791riscv_init_csr_hash (const char *name,
3d73d29e
NC		 792 unsigned address,
793 enum riscv_csr_class class,
794 enum riscv_spec_class define_version,
795 enum riscv_spec_class abort_version)
8f595e9b
NC		 796{
797 struct riscv_csr_extra *entry, *pre_entry;
5b7c81bd 798 bool need_enrty = true;
8f595e9b
NC		 799
800 pre_entry = NULL;
629310ab 801 entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
8f595e9b
NC		 802 while (need_enrty && entry != NULL)
803 {
804 if (entry->csr_class == class
1942a048
NC		 805 && entry->address == address
806 && entry->define_version == define_version
807 && entry->abort_version == abort_version)
5b7c81bd 808 need_enrty = false;
8f595e9b
NC		 809 pre_entry = entry;
810 entry = entry->next;
811 }
1942a048 812
dcd709e0 813 /* Duplicate CSR. */
8f595e9b
NC		 814 if (!need_enrty)
815 return;
bd0cf5a6 816
8f595e9b
NC		 817 entry = XNEW (struct riscv_csr_extra);
818 entry->csr_class = class;
819 entry->address = address;
820 entry->define_version = define_version;
821 entry->abort_version = abort_version;
5c505568 822 entry->next = NULL;
8f595e9b 823
8f595e9b 824 if (pre_entry == NULL)
fe0e921f 825 str_hash_insert (csr_extra_hash, name, entry, 0);
8f595e9b
NC		 826 else
827 pre_entry->next = entry;
828}
bd0cf5a6 829
dcd709e0
NC		 830/* Return the CSR address after checking the ISA dependency and
831 the privileged spec version.
832
833 There are one warning and two errors for CSR,
834
835 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
836 or the privileged spec, report warning only if -mcsr-check is set.
837 Unknown CSR: the CSR has never been defined, report error.
838 Improper CSR: the CSR number over the range (> 0xfff), report error. */
bd0cf5a6 839
08ccfccf
NC		 840static unsigned int
841riscv_csr_address (const char *csr_name,
842 struct riscv_csr_extra *entry)
bd0cf5a6 843{
08ccfccf
NC		 844 struct riscv_csr_extra *saved_entry = entry;
845 enum riscv_csr_class csr_class = entry->csr_class;
5b7c81bd
AM		 846 bool need_check_version = true;
847 bool result = true;
8f595e9b 848
8f595e9b 849 switch (csr_class)
bd0cf5a6 850 {
8f595e9b
NC		 851 case CSR_CLASS_I:
852 result = riscv_subset_supports ("i");
853 break;
08ccfccf
NC		 854 case CSR_CLASS_I_32:
855 result = (xlen == 32 && riscv_subset_supports ("i"));
856 break;
8f595e9b
NC		 857 case CSR_CLASS_F:
858 result = riscv_subset_supports ("f");
5b7c81bd 859 need_check_version = false;
8f595e9b 860 break;
08ccfccf 861 case CSR_CLASS_DEBUG:
5b7c81bd 862 need_check_version = false;
8f595e9b
NC		 863 break;
864 default:
865 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
bd0cf5a6
NC		 866 }
867
08ccfccf 868 if (riscv_opts.csr_check && !result)
b800637e 869 as_warn (_("invalid CSR `%s' for the current ISA"), csr_name);
8f595e9b
NC		 870
871 while (entry != NULL)
bd0cf5a6 872 {
08ccfccf
NC		 873 if (!need_check_version
874 || (default_priv_spec >= entry->define_version
875 && default_priv_spec < entry->abort_version))
8f595e9b 876 {
dcd709e0 877 /* Find the CSR according to the specific version. */
08ccfccf 878 return entry->address;
8f595e9b
NC		 879 }
880 entry = entry->next;
881 }
bd0cf5a6 882
dcd709e0
NC		 883 /* Can not find the CSR address from the chosen privileged version,
884 so use the newly defined value. */
8f595e9b
NC		 885 if (riscv_opts.csr_check)
886 {
3d73d29e
NC		 887 const char *priv_name = NULL;
888 RISCV_GET_PRIV_SPEC_NAME (priv_name, default_priv_spec);
8f595e9b 889 if (priv_name != NULL)
b800637e 890 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
8f595e9b 891 csr_name, priv_name);
bd0cf5a6 892 }
08ccfccf
NC		 893
894 return saved_entry->address;
bd0cf5a6
NC		 895}
896
dcd709e0
NC		 897/* Return -1 if the CSR has never been defined. Otherwise, return
898 the address. */
bd0cf5a6 899
8f595e9b 900static unsigned int
bd0cf5a6
NC		 901reg_csr_lookup_internal (const char *s)
902{
903 struct riscv_csr_extra *r =
629310ab 904 (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s);
bd0cf5a6
NC		 905
906 if (r == NULL)
8f595e9b 907 return -1U;
bd0cf5a6 908
08ccfccf 909 return riscv_csr_address (s, r);
bd0cf5a6
NC		 910}
911
e23eba97
NC		 912static unsigned int
913reg_lookup_internal (const char *s, enum reg_class class)
914{
8f595e9b
NC		 915 void *r;
916
917 if (class == RCLASS_CSR)
918 return reg_csr_lookup_internal (s);
e23eba97 919
629310ab 920 r = str_hash_find (reg_names_hash, s);
e23eba97
NC		 921 if (r == NULL || DECODE_REG_CLASS (r) != class)
922 return -1;
7f999549
JW		 923
924 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
925 return -1;
926
e23eba97
NC		 927 return DECODE_REG_NUM (r);
928}
929
5b7c81bd 930static bool
e23eba97
NC		 931reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
932{
933 char *e;
934 char save_c;
935 int reg = -1;
936
937 /* Find end of name. */
938 e = *s;
939 if (is_name_beginner (*e))
940 ++e;
941 while (is_part_of_name (*e))
942 ++e;
943
944 /* Terminate name. */
945 save_c = *e;
946 *e = '\0';
947
948 /* Look for the register. Advance to next token if one was recognized. */
949 if ((reg = reg_lookup_internal (*s, class)) >= 0)
950 *s = e;
951
952 *e = save_c;
953 if (regnop)
954 *regnop = reg;
955 return reg >= 0;
956}
957
5b7c81bd 958static bool
e23eba97
NC		 959arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
960{
961 const char *p = strchr (*s, ',');
962 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
963
bfb218e3 964 if (len == 0)
5b7c81bd 965 return false;
bfb218e3 966
e23eba97
NC		 967 for (i = 0; i < size; i++)
968 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
969 {
970 *regnop = i;
971 *s += len;
5b7c81bd 972 return true;
e23eba97
NC		 973 }
974
5b7c81bd 975 return false;
e23eba97
NC		 976}
977
978/* For consistency checking, verify that all bits are specified either
979 by the match/mask part of the instruction definition, or by the
dcd709e0 980 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
0e35537d 981
5b7c81bd 982static bool
0e35537d 983validate_riscv_insn (const struct riscv_opcode *opc, int length)
e23eba97
NC		 984{
985 const char *p = opc->args;
986 char c;
987 insn_t used_bits = opc->mask;
0e35537d
JW		 988 int insn_width;
989 insn_t required_bits;
990
991 if (length == 0)
992 insn_width = 8 * riscv_insn_length (opc->match);
993 else
994 insn_width = 8 * length;
995
996 required_bits = ~0ULL >> (64 - insn_width);
e23eba97
NC		 997
998 if ((used_bits & opc->match) != (opc->match & required_bits))
999 {
1000 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
1001 opc->name, opc->args);
5b7c81bd 1002 return false;
e23eba97
NC		 1003 }
1004
1005#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
1006 while (*p)
1007 switch (c = *p++)
1008 {
1009 case 'C': /* RVC */
1010 switch (c = *p++)
1011 {
5a9f5403
NC		 1012 case 'U': break; /* CRS1, constrained to equal RD. */
1013 case 'c': break; /* CRS1, constrained to equal sp. */
1014 case 'T': /* CRS2, floating point. */
1015 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1016 case 'S': /* CRS1S, floating point. */
e23eba97 1017 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
5a9f5403
NC		 1018 case 'w': break; /* CRS1S, constrained to equal RD. */
1019 case 'D': /* CRS2S, floating point. */
e23eba97 1020 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
5a9f5403
NC		 1021 case 'x': break; /* CRS2S, constrained to equal RD. */
1022 case 'z': break; /* CRS2S, constrained to be x0. */
1023 case '>': /* CITYPE immediate, compressed shift. */
1024 case 'u': /* CITYPE immediate, compressed lui. */
1025 case 'v': /* CITYPE immediate, li to compressed lui. */
1026 case 'o': /* CITYPE immediate, allow zero. */
1027 case 'j': used_bits |= ENCODE_CITYPE_IMM (-1U); break;
1028 case 'L': used_bits |= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1029 case 'm': used_bits |= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1030 case 'n': used_bits |= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1031 case '6': used_bits |= ENCODE_CSSTYPE_IMM (-1U); break;
1032 case 'M': used_bits |= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1033 case 'N': used_bits |= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1034 case '8': used_bits |= ENCODE_CIWTYPE_IMM (-1U); break;
1035 case 'K': used_bits |= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1036 /* CLTYPE and CSTYPE have the same immediate encoding. */
1037 case '5': used_bits |= ENCODE_CLTYPE_IMM (-1U); break;
1038 case 'k': used_bits |= ENCODE_CLTYPE_LW_IMM (-1U); break;
1039 case 'l': used_bits |= ENCODE_CLTYPE_LD_IMM (-1U); break;
1040 case 'p': used_bits |= ENCODE_CBTYPE_IMM (-1U); break;
1041 case 'a': used_bits |= ENCODE_CJTYPE_IMM (-1U); break;
1042 case 'F': /* Compressed funct for .insn directive. */
0e35537d
JW		 1043 switch (c = *p++)
1044 {
4765cd61 1045 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
0e35537d
JW		 1046 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
1047 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
4765cd61 1048 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
0e35537d 1049 default:
b800637e
NC		 1050 as_bad (_("internal: bad RISC-V opcode "
1051 "(unknown operand type `CF%c'): %s %s"),
0e35537d 1052 c, opc->name, opc->args);
5b7c81bd 1053 return false;
0e35537d
JW		 1054 }
1055 break;
e23eba97 1056 default:
b800637e
NC		 1057 as_bad (_("internal: bad RISC-V opcode "
1058 "(unknown operand type `C%c'): %s %s"),
e23eba97 1059 c, opc->name, opc->args);
5b7c81bd 1060 return false;
e23eba97
NC		 1061 }
1062 break;
1063 case ',': break;
1064 case '(': break;
1065 case ')': break;
1942a048
NC		 1066 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
1067 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
5a9f5403
NC		 1068 case 'A': break; /* Macro operand, must be symbol. */
1069 case 'B': break; /* Macro operand, must be symbol or constant. */
1070 case 'I': break; /* Macro operand, must be constant. */
1071 case 'D': /* RD, floating point. */
1942a048 1072 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
5a9f5403
NC		 1073 case 'Z': /* RS1, CSR number. */
1074 case 'S': /* RS1, floating point. */
1942a048 1075 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
5a9f5403
NC		 1076 case 'U': /* RS1 and RS2 are the same, floating point. */
1077 USE_BITS (OP_MASK_RS1, OP_SH_RS1);
1078 /* Fall through. */
1079 case 'T': /* RS2, floating point. */
1942a048 1080 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
5a9f5403
NC		 1081 case 'R': /* RS3, floating point. */
1082 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
1083 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
1084 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
1942a048
NC		 1085 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
1086 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
5a9f5403 1087 case 'o': /* ITYPE immediate, load displacement. */
1d65abb5 1088 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
5a9f5403
NC		 1089 case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
1090 case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
1942a048
NC		 1091 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
1092 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
5a9f5403
NC		 1093 case 'z': break; /* Zero immediate. */
1094 case '[': break; /* Unused operand. */
1095 case ']': break; /* Unused operand. */
1096 case '0': break; /* AMO displacement, must to zero. */
1097 case '1': break; /* Relaxation operand. */
dcd709e0 1098 case 'F': /* Funct for .insn directive. */
0e35537d
JW		 1099 switch (c = *p++)
1100 {
1101 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
1102 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
1103 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
1104 default:
b800637e
NC		 1105 as_bad (_("internal: bad RISC-V opcode "
1106 "(unknown operand type `F%c'): %s %s"),
0e35537d 1107 c, opc->name, opc->args);
5b7c81bd 1108 return false;
0e35537d
JW		 1109 }
1110 break;
dcd709e0 1111 case 'O': /* Opcode for .insn directive. */
0e35537d
JW		 1112 switch (c = *p++)
1113 {
1114 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
1115 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
1116 default:
b800637e
NC		 1117 as_bad (_("internal: bad RISC-V opcode "
1118 "(unknown operand type `F%c'): %s %s"),
0e35537d 1119 c, opc->name, opc->args);
5b7c81bd 1120 return false;
0e35537d
JW		 1121 }
1122 break;
e23eba97
NC		 1123 default:
1124 as_bad (_("internal: bad RISC-V opcode "
1125 "(unknown operand type `%c'): %s %s"),
1126 c, opc->name, opc->args);
5b7c81bd 1127 return false;
e23eba97
NC		 1128 }
1129#undef USE_BITS
1130 if (used_bits != required_bits)
1131 {
b800637e
NC		 1132 as_bad (_("internal: bad RISC-V opcode "
1133 "(bits 0x%lx undefined): %s %s"),
e23eba97
NC		 1134 ~(unsigned long)(used_bits & required_bits),
1135 opc->name, opc->args);
5b7c81bd 1136 return false;
e23eba97 1137 }
5b7c81bd 1138 return true;
e23eba97
NC		 1139}
1140
1141struct percent_op_match
1142{
1143 const char *str;
1144 bfd_reloc_code_real_type reloc;
1145};
1146
dcd709e0
NC		 1147/* Common hash table initialization function for instruction and .insn
1148 directive. */
1149
629310ab 1150static htab_t
0e35537d 1151init_opcode_hash (const struct riscv_opcode *opcodes,
5b7c81bd 1152 bool insn_directive_p)
e23eba97
NC		 1153{
1154 int i = 0;
0e35537d 1155 int length;
629310ab 1156 htab_t hash = str_htab_create ();
0e35537d 1157 while (opcodes[i].name)
e23eba97 1158 {
0e35537d 1159 const char *name = opcodes[i].name;
fe0e921f 1160 if (str_hash_insert (hash, name, &opcodes[i], 0) != NULL)
b800637e 1161 as_fatal (_("internal: duplicate %s"), name);
e23eba97
NC		 1162
1163 do
1164 {
0e35537d 1165 if (opcodes[i].pinfo != INSN_MACRO)
e23eba97 1166 {
0e35537d
JW		 1167 if (insn_directive_p)
1168 length = ((name[0] == 'c') ? 2 : 4);
1169 else
dcd709e0 1170 length = 0; /* Let assembler determine the length. */
0e35537d 1171 if (!validate_riscv_insn (&opcodes[i], length))
b800637e
NC		 1172 as_fatal (_("internal: broken assembler. "
1173 "No assembly attempted"));
e23eba97 1174 }
0e35537d
JW		 1175 else
1176 gas_assert (!insn_directive_p);
e23eba97
NC		 1177 ++i;
1178 }
0e35537d 1179 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
e23eba97
NC		 1180 }
1181
0e35537d
JW		 1182 return hash;
1183}
1184
1185/* This function is called once, at assembler startup time. It should set up
1186 all the tables, etc. that the MD part of the assembler will need. */
1187
1188void
1189md_begin (void)
1190{
1191 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
1192
1193 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
b800637e 1194 as_warn (_("could not set architecture and machine"));
0e35537d 1195
5b7c81bd
AM		 1196 op_hash = init_opcode_hash (riscv_opcodes, false);
1197 insn_type_hash = init_opcode_hash (riscv_insn_types, true);
0e35537d 1198
629310ab 1199 reg_names_hash = str_htab_create ();
e23eba97
NC		 1200 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
1201 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
1202 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
1203 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
b9c04e5a
JW		 1204 /* Add "fp" as an alias for "s0". */
1205 hash_reg_name (RCLASS_GPR, "fp", 8);
1206
bd0cf5a6 1207 /* Create and insert CSR hash tables. */
629310ab 1208 csr_extra_hash = str_htab_create ();
8f595e9b
NC		 1209#define DECLARE_CSR(name, num, class, define_version, abort_version) \
1210 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1211#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1212 DECLARE_CSR(name, num, class, define_version, abort_version);
e23eba97
NC		 1213#include "opcode/riscv-opc.h"
1214#undef DECLARE_CSR
1215
629310ab 1216 opcode_names_hash = str_htab_create ();
bd0cf5a6
NC		 1217 init_opcode_names_hash ();
1218
e23eba97
NC		 1219 /* Set the default alignment for the text section. */
1220 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
1221}
1222
45f76423
AW		 1223static insn_t
1224riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
1225{
1226 switch (reloc_type)
1227 {
1228 case BFD_RELOC_32:
1229 return value;
1230
1231 case BFD_RELOC_RISCV_HI20:
1232 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
1233
1234 case BFD_RELOC_RISCV_LO12_S:
1235 return ENCODE_STYPE_IMM (value);
1236
1237 case BFD_RELOC_RISCV_LO12_I:
1238 return ENCODE_ITYPE_IMM (value);
1239
1240 default:
1241 abort ();
1242 }
1243}
1244
e23eba97
NC		 1245/* Output an instruction. IP is the instruction information.
1246 ADDRESS_EXPR is an operand of the instruction to be used with
1247 RELOC_TYPE. */
1248
1249static void
1250append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
1251 bfd_reloc_code_real_type reloc_type)
1252{
1253 dwarf2_emit_insn (0);
1254
1255 if (reloc_type != BFD_RELOC_UNUSED)
1256 {
1257 reloc_howto_type *howto;
1258
1d65abb5 1259 gas_assert (address_expr);
e23eba97
NC		 1260 if (reloc_type == BFD_RELOC_12_PCREL
1261 || reloc_type == BFD_RELOC_RISCV_JMP)
1262 {
1263 int j = reloc_type == BFD_RELOC_RISCV_JMP;
1264 int best_case = riscv_insn_length (ip->insn_opcode);
1265 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
743f5cfc
JW		 1266
1267 if (now_seg == absolute_section)
1268 {
1269 as_bad (_("relaxable branches not supported in absolute section"));
1270 return;
1271 }
1272
e23eba97
NC		 1273 add_relaxed_insn (ip, worst_case, best_case,
1274 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
1275 address_expr->X_add_symbol,
1276 address_expr->X_add_number);
1277 return;
1278 }
45f76423 1279 else
e23eba97 1280 {
45f76423
AW		 1281 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
1282 if (howto == NULL)
b800637e
NC		 1283 as_bad (_("internal: usupported RISC-V relocation number %d"),
1284 reloc_type);
e23eba97 1285
45f76423
AW		 1286 ip->fixp = fix_new_exp (ip->frag, ip->where,
1287 bfd_get_reloc_size (howto),
5b7c81bd 1288 address_expr, false, reloc_type);
e23eba97 1289
45f76423 1290 ip->fixp->fx_tcbit = riscv_opts.relax;
e23eba97 1291 }
e23eba97
NC		 1292 }
1293
e23eba97
NC		 1294 add_fixed_insn (ip);
1295 install_insn (ip);
f77bb6c5
JW		 1296
1297 /* We need to start a new frag after any instruction that can be
1298 optimized away or compressed by the linker during relaxation, to prevent
1299 the assembler from computing static offsets across such an instruction.
1300 This is necessary to get correct EH info. */
b1b11e92 1301 if (reloc_type == BFD_RELOC_RISCV_HI20
f77bb6c5
JW		 1302 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
1303 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
1304 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
1305 {
1306 frag_wane (frag_now);
1307 frag_new (0);
1308 }
e23eba97
NC		 1309}
1310
1311/* Build an instruction created by a macro expansion. This is passed
dcd709e0
NC		 1312 a pointer to the count of instructions created so far, an expression,
1313 the name of the instruction to build, an operand format string, and
1314 corresponding arguments. */
e23eba97
NC		 1315
1316static void
1317macro_build (expressionS *ep, const char *name, const char *fmt, ...)
1318{
1319 const struct riscv_opcode *mo;
1320 struct riscv_cl_insn insn;
1321 bfd_reloc_code_real_type r;
1322 va_list args;
1323
1324 va_start (args, fmt);
1325
1326 r = BFD_RELOC_UNUSED;
629310ab 1327 mo = (struct riscv_opcode *) str_hash_find (op_hash, name);
e23eba97
NC		 1328 gas_assert (mo);
1329
1330 /* Find a non-RVC variant of the instruction. append_insn will compress
1331 it if possible. */
1332 while (riscv_insn_length (mo->match) < 4)
1333 mo++;
1334 gas_assert (strcmp (name, mo->name) == 0);
1335
1336 create_insn (&insn, mo);
1337 for (;;)
1338 {
1339 switch (*fmt++)
1340 {
1341 case 'd':
1342 INSERT_OPERAND (RD, insn, va_arg (args, int));
1343 continue;
1344
1345 case 's':
1346 INSERT_OPERAND (RS1, insn, va_arg (args, int));
1347 continue;
1348
1349 case 't':
1350 INSERT_OPERAND (RS2, insn, va_arg (args, int));
1351 continue;
1352
e23eba97
NC		 1353 case 'j':
1354 case 'u':
1355 case 'q':
1356 gas_assert (ep != NULL);
1357 r = va_arg (args, int);
1358 continue;
1359
1360 case '\0':
1361 break;
1362 case ',':
1363 continue;
1364 default:
b800637e 1365 as_fatal (_("internal: invalid macro"));
e23eba97
NC		 1366 }
1367 break;
1368 }
1369 va_end (args);
1370 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1371
1372 append_insn (&insn, ep, r);
1373}
1374
db3b6ecc
KC		 1375/* Build an instruction created by a macro expansion. Like md_assemble but
1376 accept a printf-style format string and arguments. */
1377
1378static void
1379md_assemblef (const char *format, ...)
1380{
1381 char *buf = NULL;
1382 va_list ap;
1383 int r;
1384
1385 va_start (ap, format);
1386
1387 r = vasprintf (&buf, format, ap);
1388
1389 if (r < 0)
b800637e 1390 as_fatal (_("internal: vasprintf failed"));
db3b6ecc
KC		 1391
1392 md_assemble (buf);
1393 free(buf);
1394
1395 va_end (ap);
1396}
1397
e23eba97
NC		 1398/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1399 unset. */
dcd709e0 1400
e23eba97
NC		 1401static void
1402normalize_constant_expr (expressionS *ex)
1403{
1404 if (xlen > 32)
1405 return;
1406 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1407 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1408 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1409 - 0x80000000);
1410}
1411
ca2fd32c
JW		 1412/* Fail if an expression EX is not a constant. IP is the instruction using EX.
1413 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
e23eba97
NC		 1414
1415static void
ca2fd32c 1416check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
5b7c81bd 1417 bool maybe_csr)
e23eba97
NC		 1418{
1419 if (ex->X_op == O_big)
1420 as_bad (_("unsupported large constant"));
ca2fd32c
JW		 1421 else if (maybe_csr && ex->X_op == O_symbol)
1422 as_bad (_("unknown CSR `%s'"),
1423 S_GET_NAME (ex->X_add_symbol));
e23eba97 1424 else if (ex->X_op != O_constant)
b800637e 1425 as_bad (_("instruction %s requires absolute expression"),
e23eba97
NC		 1426 ip->insn_mo->name);
1427 normalize_constant_expr (ex);
1428}
1429
1430static symbolS *
1431make_internal_label (void)
1432{
e01e1cee
AM		 1433 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now,
1434 frag_now_fix ());
e23eba97
NC		 1435}
1436
1437/* Load an entry from the GOT. */
dcd709e0 1438
e23eba97
NC		 1439static void
1440pcrel_access (int destreg, int tempreg, expressionS *ep,
1441 const char *lo_insn, const char *lo_pattern,
1442 bfd_reloc_code_real_type hi_reloc,
1443 bfd_reloc_code_real_type lo_reloc)
1444{
1445 expressionS ep2;
1446 ep2.X_op = O_symbol;
1447 ep2.X_add_symbol = make_internal_label ();
1448 ep2.X_add_number = 0;
1449
1450 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1451 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1452}
1453
1454static void
1455pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1456 bfd_reloc_code_real_type hi_reloc,
1457 bfd_reloc_code_real_type lo_reloc)
1458{
1459 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1460}
1461
1462static void
1463pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1464 bfd_reloc_code_real_type hi_reloc,
1465 bfd_reloc_code_real_type lo_reloc)
1466{
1467 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1468}
1469
1470/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
dcd709e0 1471
e23eba97
NC		 1472static void
1473riscv_call (int destreg, int tempreg, expressionS *ep,
1474 bfd_reloc_code_real_type reloc)
1475{
b1b11e92
AM		 1476 /* Ensure the jalr is emitted to the same frag as the auipc. */
1477 frag_grow (8);
e23eba97
NC		 1478 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1479 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
b1b11e92
AM		 1480 /* See comment at end of append_insn. */
1481 frag_wane (frag_now);
1482 frag_new (0);
e23eba97
NC		 1483}
1484
1485/* Load an integer constant into a register. */
1486
1487static void
1488load_const (int reg, expressionS *ep)
1489{
1490 int shift = RISCV_IMM_BITS;
4f7cc141 1491 bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1);
e23eba97 1492 expressionS upper = *ep, lower = *ep;
4f7cc141 1493 lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign;
e23eba97
NC		 1494 upper.X_add_number -= lower.X_add_number;
1495
1496 if (ep->X_op != O_constant)
1497 {
1498 as_bad (_("unsupported large constant"));
1499 return;
1500 }
1501
1d65abb5 1502 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
e23eba97
NC		 1503 {
1504 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1505 while (((upper.X_add_number >> shift) & 1) == 0)
1506 shift++;
1507
1508 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1d65abb5 1509 load_const (reg, &upper);
e23eba97 1510
db3b6ecc 1511 md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift);
e23eba97 1512 if (lower.X_add_number != 0)
db3b6ecc
KC		 1513 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg,
1514 lower.X_add_number);
e23eba97
NC		 1515 }
1516 else
1517 {
1518 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1519 int hi_reg = 0;
1520
1521 if (upper.X_add_number != 0)
1522 {
db3b6ecc
KC		 1523 /* Discard low part and zero-extend upper immediate. */
1524 upper_imm = ((uint32_t)upper.X_add_number >> shift);
1525
1526 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm);
e23eba97
NC		 1527 hi_reg = reg;
1528 }
1529
1530 if (lower.X_add_number != 0 || hi_reg == 0)
db3b6ecc
KC		 1531 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg,
1532 lower.X_add_number);
e23eba97
NC		 1533 }
1534}
1535
c2137f55
NC		 1536/* Zero extend and sign extend byte/half-word/word. */
1537
1538static void
5b7c81bd 1539riscv_ext (int destreg, int srcreg, unsigned shift, bool sign)
c2137f55
NC		 1540{
1541 if (sign)
1542 {
1543 md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
1544 md_assemblef ("srai x%d, x%d, 0x%x", destreg, destreg, shift);
1545 }
1546 else
1547 {
1548 md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
1549 md_assemblef ("srli x%d, x%d, 0x%x", destreg, destreg, shift);
1550 }
1551}
1552
e23eba97 1553/* Expand RISC-V assembly macros into one or more instructions. */
2652cfad 1554
e23eba97
NC		 1555static void
1556macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1557 bfd_reloc_code_real_type *imm_reloc)
1558{
1559 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1560 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1561 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1562 int mask = ip->insn_mo->mask;
1563
1564 switch (mask)
1565 {
1566 case M_LI:
1567 load_const (rd, imm_expr);
1568 break;
1569
1570 case M_LA:
1571 case M_LLA:
1572 /* Load the address of a symbol into a register. */
1573 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1574 as_bad (_("offset too large"));
1575
1576 if (imm_expr->X_op == O_constant)
1577 load_const (rd, imm_expr);
dcd709e0 1578 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol. */
e23eba97
NC		 1579 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1580 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
dcd709e0 1581 else /* Local PIC symbol, or any non-PIC symbol. */
e23eba97
NC		 1582 pcrel_load (rd, rd, imm_expr, "addi",
1583 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1584 break;
1585
1586 case M_LA_TLS_GD:
1587 pcrel_load (rd, rd, imm_expr, "addi",
1588 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1589 break;
1590
1591 case M_LA_TLS_IE:
1592 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1593 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1594 break;
1595
1596 case M_LB:
1597 pcrel_load (rd, rd, imm_expr, "lb",
1598 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1599 break;
1600
1601 case M_LBU:
1602 pcrel_load (rd, rd, imm_expr, "lbu",
1603 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1604 break;
1605
1606 case M_LH:
1607 pcrel_load (rd, rd, imm_expr, "lh",
1608 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1609 break;
1610
1611 case M_LHU:
1612 pcrel_load (rd, rd, imm_expr, "lhu",
1613 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1614 break;
1615
1616 case M_LW:
1617 pcrel_load (rd, rd, imm_expr, "lw",
1618 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1619 break;
1620
1621 case M_LWU:
1622 pcrel_load (rd, rd, imm_expr, "lwu",
1623 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1624 break;
1625
1626 case M_LD:
1627 pcrel_load (rd, rd, imm_expr, "ld",
1628 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1629 break;
1630
1631 case M_FLW:
1632 pcrel_load (rd, rs1, imm_expr, "flw",
1633 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1634 break;
1635
1636 case M_FLD:
1637 pcrel_load (rd, rs1, imm_expr, "fld",
1638 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1639 break;
1640
1641 case M_SB:
1642 pcrel_store (rs2, rs1, imm_expr, "sb",
1643 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1644 break;
1645
1646 case M_SH:
1647 pcrel_store (rs2, rs1, imm_expr, "sh",
1648 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1649 break;
1650
1651 case M_SW:
1652 pcrel_store (rs2, rs1, imm_expr, "sw",
1653 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1654 break;
1655
1656 case M_SD:
1657 pcrel_store (rs2, rs1, imm_expr, "sd",
1658 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1659 break;
1660
1661 case M_FSW:
1662 pcrel_store (rs2, rs1, imm_expr, "fsw",
1663 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1664 break;
1665
1666 case M_FSD:
1667 pcrel_store (rs2, rs1, imm_expr, "fsd",
1668 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1669 break;
1670
1671 case M_CALL:
1672 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1673 break;
1674
c2137f55 1675 case M_ZEXTH:
5b7c81bd 1676 riscv_ext (rd, rs1, xlen - 16, false);
c2137f55
NC		 1677 break;
1678
1679 case M_ZEXTW:
5b7c81bd 1680 riscv_ext (rd, rs1, xlen - 32, false);
c2137f55
NC		 1681 break;
1682
1683 case M_SEXTB:
5b7c81bd 1684 riscv_ext (rd, rs1, xlen - 8, true);
c2137f55
NC		 1685 break;
1686
1687 case M_SEXTH:
5b7c81bd 1688 riscv_ext (rd, rs1, xlen - 16, true);
c2137f55
NC		 1689 break;
1690
e23eba97 1691 default:
b800637e 1692 as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name);
e23eba97
NC		 1693 break;
1694 }
1695}
1696
1697static const struct percent_op_match percent_op_utype[] =
1698{
1699 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1700 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
dee35d02 1701 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
e23eba97
NC		 1702 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1703 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1704 {"%hi", BFD_RELOC_RISCV_HI20},
1705 {0, 0}
1706};
1707
1708static const struct percent_op_match percent_op_itype[] =
1709{
1710 {"%lo", BFD_RELOC_RISCV_LO12_I},
1711 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1712 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1713 {0, 0}
1714};
1715
1716static const struct percent_op_match percent_op_stype[] =
1717{
1718 {"%lo", BFD_RELOC_RISCV_LO12_S},
1719 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1720 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1721 {0, 0}
1722};
1723
1724static const struct percent_op_match percent_op_rtype[] =
1725{
1726 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1727 {0, 0}
1728};
1729
f50fabe4
JW		 1730static const struct percent_op_match percent_op_null[] =
1731{
1732 {0, 0}
1733};
1734
e23eba97
NC		 1735/* Return true if *STR points to a relocation operator. When returning true,
1736 move *STR over the operator and store its relocation code in *RELOC.
1737 Leave both *STR and *RELOC alone when returning false. */
1738
5b7c81bd 1739static bool
e23eba97
NC		 1740parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1741 const struct percent_op_match *percent_op)
1742{
1743 for ( ; percent_op->str; percent_op++)
1744 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1745 {
1746 int len = strlen (percent_op->str);
1747
1748 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1749 continue;
1750
1751 *str += strlen (percent_op->str);
1752 *reloc = percent_op->reloc;
1753
1754 /* Check whether the output BFD supports this relocation.
1755 If not, issue an error and fall back on something safe. */
45f76423
AW		 1756 if (*reloc != BFD_RELOC_UNUSED
1757 && !bfd_reloc_type_lookup (stdoutput, *reloc))
e23eba97 1758 {
b800637e
NC		 1759 as_bad ("internal: relocation %s isn't supported by the "
1760 "current ABI", percent_op->str);
e23eba97
NC		 1761 *reloc = BFD_RELOC_UNUSED;
1762 }
5b7c81bd 1763 return true;
e23eba97 1764 }
5b7c81bd 1765 return false;
e23eba97
NC		 1766}
1767
1768static void
1769my_getExpression (expressionS *ep, char *str)
1770{
1771 char *save_in;
1772
1773 save_in = input_line_pointer;
1774 input_line_pointer = str;
1775 expression (ep);
1776 expr_end = input_line_pointer;
1777 input_line_pointer = save_in;
1778}
1779
1780/* Parse string STR as a 16-bit relocatable operand. Store the
1781 expression in *EP and the relocation, if any, in RELOC.
1782 Return the number of relocation operators used (0 or 1).
1783
1784 On exit, EXPR_END points to the first character after the expression. */
1785
1786static size_t
1787my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1788 char *str, const struct percent_op_match *percent_op)
1789{
1790 size_t reloc_index;
1791 unsigned crux_depth, str_depth, regno;
1792 char *crux;
1793
8970c022
JW		 1794 /* First, check for integer registers. No callers can accept a reg, but
1795 we need to avoid accidentally creating a useless undefined symbol below,
1796 if this is an instruction pattern that can't match. A glibc build fails
1797 if this is removed. */
e23eba97
NC		 1798 if (reg_lookup (&str, RCLASS_GPR, &regno))
1799 {
1800 ep->X_op = O_register;
1801 ep->X_add_number = regno;
8970c022 1802 expr_end = str;
e23eba97
NC		 1803 return 0;
1804 }
1805
1806 /* Search for the start of the main expression.
dcd709e0
NC		 1807
1808 End the loop with CRUX pointing to the start of the main expression and
1809 with CRUX_DEPTH containing the number of open brackets at that point. */
e23eba97
NC		 1810 reloc_index = -1;
1811 str_depth = 0;
1812 do
1813 {
1814 reloc_index++;
1815 crux = str;
1816 crux_depth = str_depth;
1817
1818 /* Skip over whitespace and brackets, keeping count of the number
1819 of brackets. */
1820 while (*str == ' ' || *str == '\t' || *str == '(')
1821 if (*str++ == '(')
1822 str_depth++;
1823 }
1824 while (*str == '%'
1825 && reloc_index < 1
1826 && parse_relocation (&str, reloc, percent_op));
1827
1828 my_getExpression (ep, crux);
1829 str = expr_end;
1830
1831 /* Match every open bracket. */
1832 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1833 if (*str++ == ')')
1834 crux_depth--;
1835
1836 if (crux_depth > 0)
1837 as_bad ("unclosed '('");
1838
1839 expr_end = str;
1840
1841 return reloc_index;
1842}
1843
0e35537d 1844/* Parse opcode name, could be an mnemonics or number. */
dcd709e0 1845
0e35537d
JW		 1846static size_t
1847my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1848 char *str, const struct percent_op_match *percent_op)
1849{
1850 const struct opcode_name_t *o = opcode_name_lookup (&str);
1851
1852 if (o != NULL)
1853 {
1854 ep->X_op = O_constant;
1855 ep->X_add_number = o->val;
1856 return 0;
1857 }
1858
1859 return my_getSmallExpression (ep, reloc, str, percent_op);
1860}
1861
f0531ed6
JW		 1862/* Detect and handle implicitly zero load-store offsets. For example,
1863 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1864 an implicit offset was detected. */
1865
5b7c81bd 1866static bool
89424b1d 1867riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
f0531ed6
JW		 1868{
1869 /* Check whether there is only a single bracketed expression left.
1870 If so, it must be the base register and the constant must be zero. */
1871 if (*s == '(' && strchr (s + 1, '(') == 0)
1872 {
89424b1d
MR		 1873 ep->X_op = O_constant;
1874 ep->X_add_number = 0;
5b7c81bd 1875 return true;
f0531ed6
JW		 1876 }
1877
5b7c81bd 1878 return false;
f0531ed6
JW		 1879}
1880
54b2aec1 1881/* All RISC-V CSR instructions belong to one of these classes. */
54b2aec1
NC		 1882enum csr_insn_type
1883{
1884 INSN_NOT_CSR,
1885 INSN_CSRRW,
1886 INSN_CSRRS,
1887 INSN_CSRRC
1888};
1889
1890/* Return which CSR instruction is checking. */
1891
1892static enum csr_insn_type
1893riscv_csr_insn_type (insn_t insn)
1894{
1895 if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
1896 || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
1897 return INSN_CSRRW;
1898 else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
1899 || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
1900 return INSN_CSRRS;
1901 else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
1902 || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
1903 return INSN_CSRRC;
1904 else
1905 return INSN_NOT_CSR;
1906}
1907
1908/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1909 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1910 CSR address is 0x3. */
1911
5b7c81bd 1912static bool
54b2aec1
NC		 1913riscv_csr_read_only_check (insn_t insn)
1914{
1915 int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
1916 int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
1917 int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
1918 enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
1919
1920 if (readonly
1921 && (((csr_insn == INSN_CSRRS
1922 || csr_insn == INSN_CSRRC)
1923 && rs1 != 0)
1924 || csr_insn == INSN_CSRRW))
5b7c81bd 1925 return false;
54b2aec1 1926
5b7c81bd 1927 return true;
54b2aec1
NC		 1928}
1929
1a79004f
NC		 1930/* Return True if it is a privileged instruction. Otherwise, return FALSE.
1931
1932 uret is actually a N-ext instruction. So it is better to regard it as
1933 an user instruction rather than the priv instruction.
1934
1935 hret is used to return from traps in H-mode. H-mode is removed since
1936 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1937 Therefore, hret should be controlled by the hypervisor spec rather than
1938 priv spec in the future.
1939
1940 dret is defined in the debug spec, so it should be checked in the future,
1941 too. */
1942
5b7c81bd 1943static bool
1a79004f
NC		 1944riscv_is_priv_insn (insn_t insn)
1945{
1946 return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
1947 || ((insn ^ MATCH_MRET) & MASK_MRET) == 0
1948 || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0
1949 || ((insn ^ MATCH_WFI) & MASK_WFI) == 0
1950 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
dcd709e0 1951 check it here to keep the compatible. */
1a79004f
NC		 1952 || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
1953}
1954
e23eba97
NC		 1955/* This routine assembles an instruction into its binary format. As a
1956 side effect, it sets the global variable imm_reloc to the type of
1957 relocation to do if one of the operands is an address expression. */
1958
1959static const char *
1960riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
629310ab 1961 bfd_reloc_code_real_type *imm_reloc, htab_t hash)
e23eba97
NC		 1962{
1963 char *s;
1964 const char *args;
1965 char c = 0;
1966 struct riscv_opcode *insn;
1967 char *argsStart;
1968 unsigned int regno;
1969 char save_c = 0;
1970 int argnum;
1971 const struct percent_op_match *p;
1972 const char *error = "unrecognized opcode";
54b2aec1 1973 /* Indicate we are assembling instruction with CSR. */
5b7c81bd 1974 bool insn_with_csr = false;
e23eba97
NC		 1975
1976 /* Parse the name of the instruction. Terminate the string if whitespace
629310ab 1977 is found so that str_hash_find only sees the name part of the string. */
e23eba97
NC		 1978 for (s = str; *s != '\0'; ++s)
1979 if (ISSPACE (*s))
1980 {
1981 save_c = *s;
1982 *s++ = '\0';
1983 break;
1984 }
1985
629310ab 1986 insn = (struct riscv_opcode *) str_hash_find (hash, str);
e23eba97
NC		 1987
1988 argsStart = s;
1989 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1990 {
1080bf78
JW		 1991 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
1992 continue;
1993
7e9ad3a3 1994 if (!riscv_multi_subset_supports (insn->insn_class))
e23eba97
NC		 1995 continue;
1996
1997 create_insn (ip, insn);
1998 argnum = 1;
1999
2000 imm_expr->X_op = O_absent;
2001 *imm_reloc = BFD_RELOC_UNUSED;
2002 p = percent_op_itype;
2003
2004 for (args = insn->args;; ++args)
2005 {
2006 s += strspn (s, " \t");
2007 switch (*args)
2008 {
dcd709e0 2009 case '\0': /* End of args. */
e23eba97
NC		 2010 if (insn->pinfo != INSN_MACRO)
2011 {
2012 if (!insn->match_func (insn, ip->insn_opcode))
2013 break;
0e35537d
JW		 2014
2015 /* For .insn, insn->match and insn->mask are 0. */
2016 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
2017 ? ip->insn_opcode
2018 : insn->match) == 2
2019 && !riscv_opts.rvc)
e23eba97 2020 break;
54b2aec1 2021
1a79004f 2022 if (riscv_is_priv_insn (ip->insn_opcode))
5b7c81bd 2023 explicit_priv_attr = true;
1a79004f 2024
54b2aec1
NC		 2025 /* Check if we write a read-only CSR by the CSR
2026 instruction. */
2027 if (insn_with_csr
2028 && riscv_opts.csr_check
2029 && !riscv_csr_read_only_check (ip->insn_opcode))
2030 {
2031 /* Restore the character in advance, since we want to
2032 report the detailed warning message here. */
2033 if (save_c)
2034 *(argsStart - 1) = save_c;
b800637e 2035 as_warn (_("read-only CSR is written `%s'"), str);
5b7c81bd 2036 insn_with_csr = false;
54b2aec1 2037 }
e23eba97
NC		 2038 }
2039 if (*s != '\0')
2040 break;
2041 /* Successful assembly. */
2042 error = NULL;
5b7c81bd 2043 insn_with_csr = false;
e23eba97
NC		 2044 goto out;
2045
2046 case 'C': /* RVC */
2047 switch (*++args)
2048 {
dcd709e0 2049 case 's': /* RS1 x8-x15. */
e23eba97
NC		 2050 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2051 || !(regno >= 8 && regno <= 15))
2052 break;
2053 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2054 continue;
2055 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2056 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2057 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
2058 break;
2059 continue;
dcd709e0 2060 case 't': /* RS2 x8-x15. */
e23eba97
NC		 2061 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2062 || !(regno >= 8 && regno <= 15))
2063 break;
2064 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2065 continue;
2066 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2067 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2068 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
2069 break;
2070 continue;
2071 case 'U': /* RS1, constrained to equal RD. */
2072 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2073 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
2074 break;
2075 continue;
2076 case 'V': /* RS2 */
2077 if (!reg_lookup (&s, RCLASS_GPR, &regno))
2078 break;
2079 INSERT_OPERAND (CRS2, *ip, regno);
2080 continue;
2081 case 'c': /* RS1, constrained to equal sp. */
2082 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2083 || regno != X_SP)
2084 break;
2085 continue;
dcd709e0 2086 case 'z': /* RS2, constrained to equal x0. */
ca0bc150
JW		 2087 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2088 || regno != 0)
2089 break;
2090 continue;
e23eba97
NC		 2091 case '>':
2092 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2093 || imm_expr->X_op != O_constant
2094 || imm_expr->X_add_number <= 0
2095 || imm_expr->X_add_number >= 64)
2096 break;
5a9f5403 2097 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
dc1e8a47 2098 rvc_imm_done:
e23eba97
NC		 2099 s = expr_end;
2100 imm_expr->X_op = O_absent;
2101 continue;
5a9f5403 2102 case '5':
e23eba97
NC		 2103 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2104 || imm_expr->X_op != O_constant
5a9f5403 2105 || imm_expr->X_add_number < 0
169ec512 2106 || imm_expr->X_add_number >= 32
5a9f5403 2107 || !VALID_CLTYPE_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2108 break;
0257c2ff 2109 ip->insn_opcode |= ENCODE_CLTYPE_IMM (imm_expr->X_add_number);
e23eba97 2110 goto rvc_imm_done;
5a9f5403 2111 case '6':
0e35537d
JW		 2112 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2113 || imm_expr->X_op != O_constant
0e35537d 2114 || imm_expr->X_add_number < 0
5a9f5403
NC		 2115 || imm_expr->X_add_number >= 64
2116 || !VALID_CSSTYPE_IMM ((valueT) imm_expr->X_add_number))
0e35537d 2117 break;
0257c2ff 2118 ip->insn_opcode |= ENCODE_CSSTYPE_IMM (imm_expr->X_add_number);
0e35537d 2119 goto rvc_imm_done;
5a9f5403 2120 case '8':
e23eba97
NC		 2121 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2122 || imm_expr->X_op != O_constant
5a9f5403
NC		 2123 || imm_expr->X_add_number < 0
2124 || imm_expr->X_add_number >= 256
2125 || !VALID_CIWTYPE_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2126 break;
0257c2ff 2127 ip->insn_opcode |= ENCODE_CIWTYPE_IMM (imm_expr->X_add_number);
e23eba97
NC		 2128 goto rvc_imm_done;
2129 case 'j':
2130 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2131 || imm_expr->X_op != O_constant
2132 || imm_expr->X_add_number == 0
5a9f5403 2133 || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2134 break;
5a9f5403 2135 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
e23eba97
NC		 2136 goto rvc_imm_done;
2137 case 'k':
f0531ed6
JW		 2138 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2139 continue;
e23eba97
NC		 2140 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2141 || imm_expr->X_op != O_constant
5a9f5403 2142 || !VALID_CLTYPE_LW_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2143 break;
5a9f5403 2144 ip->insn_opcode |= ENCODE_CLTYPE_LW_IMM (imm_expr->X_add_number);
e23eba97
NC		 2145 goto rvc_imm_done;
2146 case 'l':
f0531ed6
JW		 2147 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2148 continue;
e23eba97
NC		 2149 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2150 || imm_expr->X_op != O_constant
5a9f5403 2151 || !VALID_CLTYPE_LD_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2152 break;
5a9f5403 2153 ip->insn_opcode |= ENCODE_CLTYPE_LD_IMM (imm_expr->X_add_number);
e23eba97
NC		 2154 goto rvc_imm_done;
2155 case 'm':
f0531ed6
JW		 2156 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2157 continue;
e23eba97
NC		 2158 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2159 || imm_expr->X_op != O_constant
5a9f5403 2160 || !VALID_CITYPE_LWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2161 break;
2162 ip->insn_opcode |=
5a9f5403 2163 ENCODE_CITYPE_LWSP_IMM (imm_expr->X_add_number);
e23eba97
NC		 2164 goto rvc_imm_done;
2165 case 'n':
f0531ed6
JW		 2166 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2167 continue;
e23eba97
NC		 2168 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2169 || imm_expr->X_op != O_constant
5a9f5403 2170 || !VALID_CITYPE_LDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2171 break;
2172 ip->insn_opcode |=
5a9f5403 2173 ENCODE_CITYPE_LDSP_IMM (imm_expr->X_add_number);
e23eba97 2174 goto rvc_imm_done;
b416fe87
KC		 2175 case 'o':
2176 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2177 || imm_expr->X_op != O_constant
21a186f2
JW		 2178 /* C.addiw, c.li, and c.andi allow zero immediate.
2179 C.addi allows zero immediate as hint. Otherwise this
2180 is same as 'j'. */
5a9f5403 2181 || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number))
b416fe87 2182 break;
5a9f5403 2183 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
b416fe87 2184 goto rvc_imm_done;
e23eba97
NC		 2185 case 'K':
2186 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2187 || imm_expr->X_op != O_constant
169ec512 2188 || imm_expr->X_add_number == 0
5a9f5403 2189 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2190 break;
2191 ip->insn_opcode |=
5a9f5403 2192 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr->X_add_number);
e23eba97
NC		 2193 goto rvc_imm_done;
2194 case 'L':
2195 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2196 || imm_expr->X_op != O_constant
5a9f5403 2197 || !VALID_CITYPE_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2198 break;
2199 ip->insn_opcode |=
5a9f5403 2200 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr->X_add_number);
e23eba97
NC		 2201 goto rvc_imm_done;
2202 case 'M':
f0531ed6
JW		 2203 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2204 continue;
e23eba97
NC		 2205 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2206 || imm_expr->X_op != O_constant
5a9f5403 2207 || !VALID_CSSTYPE_SWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2208 break;
2209 ip->insn_opcode |=
5a9f5403 2210 ENCODE_CSSTYPE_SWSP_IMM (imm_expr->X_add_number);
e23eba97
NC		 2211 goto rvc_imm_done;
2212 case 'N':
f0531ed6
JW		 2213 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2214 continue;
e23eba97
NC		 2215 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2216 || imm_expr->X_op != O_constant
5a9f5403 2217 || !VALID_CSSTYPE_SDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2218 break;
2219 ip->insn_opcode |=
5a9f5403 2220 ENCODE_CSSTYPE_SDSP_IMM (imm_expr->X_add_number);
e23eba97
NC		 2221 goto rvc_imm_done;
2222 case 'u':
2223 p = percent_op_utype;
2224 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
2225 break;
dc1e8a47 2226 rvc_lui:
e23eba97
NC		 2227 if (imm_expr->X_op != O_constant
2228 || imm_expr->X_add_number <= 0
2229 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
2230 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
2231 && (imm_expr->X_add_number <
2232 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
2233 break;
5a9f5403 2234 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
e23eba97
NC		 2235 goto rvc_imm_done;
2236 case 'v':
2237 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2238 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
2239 || ((int32_t)imm_expr->X_add_number
2240 != imm_expr->X_add_number))
2241 break;
2242 imm_expr->X_add_number =
2243 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
2244 goto rvc_lui;
2245 case 'p':
2246 goto branch;
2247 case 'a':
2248 goto jump;
0e35537d
JW		 2249 case 'S': /* Floating-point RS1 x8-x15. */
2250 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2251 || !(regno >= 8 && regno <= 15))
2252 break;
2253 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2254 continue;
e23eba97
NC		 2255 case 'D': /* Floating-point RS2 x8-x15. */
2256 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2257 || !(regno >= 8 && regno <= 15))
2258 break;
2259 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2260 continue;
2261 case 'T': /* Floating-point RS2. */
2262 if (!reg_lookup (&s, RCLASS_FPR, &regno))
2263 break;
2264 INSERT_OPERAND (CRS2, *ip, regno);
2265 continue;
0e35537d
JW		 2266 case 'F':
2267 switch (*++args)
2268 {
4765cd61
JW		 2269 case '6':
2270 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2271 || imm_expr->X_op != O_constant
2272 || imm_expr->X_add_number < 0
2273 || imm_expr->X_add_number >= 64)
2274 {
b800637e
NC		 2275 as_bad (_("bad value for compressed funct6 "
2276 "field, value must be 0...64"));
4765cd61
JW		 2277 break;
2278 }
4765cd61
JW		 2279 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
2280 imm_expr->X_op = O_absent;
2281 s = expr_end;
2282 continue;
1942a048 2283
0e35537d
JW		 2284 case '4':
2285 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2286 || imm_expr->X_op != O_constant
2287 || imm_expr->X_add_number < 0
2288 || imm_expr->X_add_number >= 16)
2289 {
b800637e
NC		 2290 as_bad (_("bad value for compressed funct4 "
2291 "field, value must be 0...15"));
0e35537d
JW		 2292 break;
2293 }
0e35537d
JW		 2294 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
2295 imm_expr->X_op = O_absent;
2296 s = expr_end;
2297 continue;
1942a048 2298
0e35537d
JW		 2299 case '3':
2300 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2301 || imm_expr->X_op != O_constant
2302 || imm_expr->X_add_number < 0
2303 || imm_expr->X_add_number >= 8)
2304 {
b800637e
NC		 2305 as_bad (_("bad value for compressed funct3 "
2306 "field, value must be 0...7"));
0e35537d
JW		 2307 break;
2308 }
2309 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
2310 imm_expr->X_op = O_absent;
2311 s = expr_end;
2312 continue;
1942a048 2313
4765cd61
JW		 2314 case '2':
2315 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2316 || imm_expr->X_op != O_constant
2317 || imm_expr->X_add_number < 0
2318 || imm_expr->X_add_number >= 4)
2319 {
b800637e
NC		 2320 as_bad (_("bad value for compressed funct2 "
2321 "field, value must be 0...3"));
4765cd61
JW		 2322 break;
2323 }
2324 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number);
2325 imm_expr->X_op = O_absent;
2326 s = expr_end;
2327 continue;
1942a048 2328
0e35537d 2329 default:
b800637e
NC		 2330 as_bad (_("internal: unknown compressed funct "
2331 "field specifier `CF%c'"), *args);
0e35537d
JW		 2332 }
2333 break;
2334
e23eba97 2335 default:
b800637e
NC		 2336 as_bad (_("internal: unknown compressed field "
2337 "specifier `C%c'"), *args);
e23eba97
NC		 2338 }
2339 break;
2340
2341 case ',':
2342 ++argnum;
2343 if (*s++ == *args)
2344 continue;
2345 s--;
2346 break;
2347
2348 case '(':
2349 case ')':
2350 case '[':
2351 case ']':
2352 if (*s++ == *args)
2353 continue;
2354 break;
2355
dcd709e0 2356 case '<': /* Shift amount, 0 - 31. */
e23eba97 2357 my_getExpression (imm_expr, s);
5b7c81bd 2358 check_absolute_expr (ip, imm_expr, false);
e23eba97 2359 if ((unsigned long) imm_expr->X_add_number > 31)
b800637e 2360 as_bad (_("improper shift amount (%lu)"),
94f78a77 2361 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2362 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
2363 imm_expr->X_op = O_absent;
2364 s = expr_end;
2365 continue;
2366
dcd709e0 2367 case '>': /* Shift amount, 0 - (XLEN-1). */
e23eba97 2368 my_getExpression (imm_expr, s);
5b7c81bd 2369 check_absolute_expr (ip, imm_expr, false);
e23eba97 2370 if ((unsigned long) imm_expr->X_add_number >= xlen)
b800637e 2371 as_bad (_("improper shift amount (%lu)"),
94f78a77 2372 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2373 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
2374 imm_expr->X_op = O_absent;
2375 s = expr_end;
2376 continue;
2377
dcd709e0 2378 case 'Z': /* CSRRxI immediate. */
e23eba97 2379 my_getExpression (imm_expr, s);
5b7c81bd 2380 check_absolute_expr (ip, imm_expr, false);
e23eba97 2381 if ((unsigned long) imm_expr->X_add_number > 31)
b800637e 2382 as_bad (_("improper CSRxI immediate (%lu)"),
94f78a77 2383 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2384 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
2385 imm_expr->X_op = O_absent;
2386 s = expr_end;
2387 continue;
2388
dcd709e0 2389 case 'E': /* Control register. */
5b7c81bd
AM		 2390 insn_with_csr = true;
2391 explicit_priv_attr = true;
e23eba97
NC		 2392 if (reg_lookup (&s, RCLASS_CSR, &regno))
2393 INSERT_OPERAND (CSR, *ip, regno);
2394 else
2395 {
2396 my_getExpression (imm_expr, s);
5b7c81bd 2397 check_absolute_expr (ip, imm_expr, true);
e23eba97 2398 if ((unsigned long) imm_expr->X_add_number > 0xfff)
b800637e 2399 as_bad (_("improper CSR address (%lu)"),
94f78a77 2400 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2401 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
2402 imm_expr->X_op = O_absent;
2403 s = expr_end;
2404 }
2405 continue;
2406
dcd709e0 2407 case 'm': /* Rounding mode. */
e23eba97
NC		 2408 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
2409 {
2410 INSERT_OPERAND (RM, *ip, regno);
2411 continue;
2412 }
2413 break;
2414
2415 case 'P':
dcd709e0 2416 case 'Q': /* Fence predecessor/successor. */
e23eba97
NC		 2417 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
2418 &regno))
2419 {
2420 if (*args == 'P')
2421 INSERT_OPERAND (PRED, *ip, regno);
2422 else
2423 INSERT_OPERAND (SUCC, *ip, regno);
2424 continue;
2425 }
2426 break;
2427
dcd709e0
NC		 2428 case 'd': /* Destination register. */
2429 case 's': /* Source register. */
2430 case 't': /* Target register. */
2431 case 'r': /* RS3 */
e23eba97
NC		 2432 if (reg_lookup (&s, RCLASS_GPR, &regno))
2433 {
2434 c = *args;
2435 if (*s == ' ')
2436 ++s;
2437
2438 /* Now that we have assembled one operand, we use the args
2439 string to figure out where it goes in the instruction. */
2440 switch (c)
2441 {
2442 case 's':
2443 INSERT_OPERAND (RS1, *ip, regno);
2444 break;
2445 case 'd':
2446 INSERT_OPERAND (RD, *ip, regno);
2447 break;
2448 case 't':
2449 INSERT_OPERAND (RS2, *ip, regno);
2450 break;
0e35537d
JW		 2451 case 'r':
2452 INSERT_OPERAND (RS3, *ip, regno);
2453 break;
e23eba97
NC		 2454 }
2455 continue;
2456 }
2457 break;
2458
dcd709e0
NC		 2459 case 'D': /* Floating point RD. */
2460 case 'S': /* Floating point RS1. */
2461 case 'T': /* Floating point RS2. */
2462 case 'U': /* Floating point RS1 and RS2. */
2463 case 'R': /* Floating point RS3. */
e23eba97
NC		 2464 if (reg_lookup (&s, RCLASS_FPR, &regno))
2465 {
2466 c = *args;
2467 if (*s == ' ')
2468 ++s;
2469 switch (c)
2470 {
2471 case 'D':
2472 INSERT_OPERAND (RD, *ip, regno);
2473 break;
2474 case 'S':
2475 INSERT_OPERAND (RS1, *ip, regno);
2476 break;
2477 case 'U':
2478 INSERT_OPERAND (RS1, *ip, regno);
dcd709e0 2479 /* Fall through. */
e23eba97
NC		 2480 case 'T':
2481 INSERT_OPERAND (RS2, *ip, regno);
2482 break;
2483 case 'R':
2484 INSERT_OPERAND (RS3, *ip, regno);
2485 break;
2486 }
2487 continue;
2488 }
e23eba97
NC		 2489 break;
2490
2491 case 'I':
2492 my_getExpression (imm_expr, s);
2493 if (imm_expr->X_op != O_big
2494 && imm_expr->X_op != O_constant)
2495 break;
2496 normalize_constant_expr (imm_expr);
2497 s = expr_end;
2498 continue;
2499
2500 case 'A':
2501 my_getExpression (imm_expr, s);
2502 normalize_constant_expr (imm_expr);
2503 /* The 'A' format specifier must be a symbol. */
2504 if (imm_expr->X_op != O_symbol)
2505 break;
2506 *imm_reloc = BFD_RELOC_32;
2507 s = expr_end;
2508 continue;
2509
160d1b3d
SH		 2510 case 'B':
2511 my_getExpression (imm_expr, s);
2512 normalize_constant_expr (imm_expr);
2513 /* The 'B' format specifier must be a symbol or a constant. */
2514 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
2515 break;
2516 if (imm_expr->X_op == O_symbol)
2517 *imm_reloc = BFD_RELOC_32;
2518 s = expr_end;
2519 continue;
2520
e23eba97 2521 case 'j': /* Sign-extended immediate. */
e23eba97 2522 p = percent_op_itype;
f50fabe4 2523 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
e23eba97
NC		 2524 goto alu_op;
2525 case 'q': /* Store displacement. */
2526 p = percent_op_stype;
2527 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
2528 goto load_store;
2529 case 'o': /* Load displacement. */
2530 p = percent_op_itype;
2531 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
2532 goto load_store;
dcd709e0
NC		 2533 case '1':
2534 /* This is used for TLS, where the fourth operand is
2535 %tprel_add, to get a relocation applied to an add
2536 instruction, for relaxation to use. */
e23eba97 2537 p = percent_op_rtype;
f50fabe4 2538 goto alu_op;
dcd709e0 2539 case '0': /* AMO displacement, which must be zero. */
f50fabe4 2540 p = percent_op_null;
dc1e8a47 2541 load_store:
f0531ed6 2542 if (riscv_handle_implicit_zero_offset (imm_expr, s))
e23eba97 2543 continue;
dc1e8a47 2544 alu_op:
e23eba97
NC		 2545 /* If this value won't fit into a 16 bit offset, then go
2546 find a macro that will generate the 32 bit offset
2547 code pattern. */
2548 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
2549 {
2550 normalize_constant_expr (imm_expr);
2551 if (imm_expr->X_op != O_constant
2552 || (*args == '0' && imm_expr->X_add_number != 0)
f50fabe4 2553 || (*args == '1')
e23eba97
NC		 2554 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
2555 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
2556 break;
2557 }
e23eba97
NC		 2558 s = expr_end;
2559 continue;
2560
dcd709e0 2561 case 'p': /* PC-relative offset. */
dc1e8a47 2562 branch:
e23eba97
NC		 2563 *imm_reloc = BFD_RELOC_12_PCREL;
2564 my_getExpression (imm_expr, s);
2565 s = expr_end;
2566 continue;
2567
dcd709e0 2568 case 'u': /* Upper 20 bits. */
e23eba97 2569 p = percent_op_utype;
4288405d 2570 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
e23eba97 2571 {
4288405d
JW		 2572 if (imm_expr->X_op != O_constant)
2573 break;
2574
e23eba97
NC		 2575 if (imm_expr->X_add_number < 0
2576 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
2577 as_bad (_("lui expression not in range 0..1048575"));
2578
2579 *imm_reloc = BFD_RELOC_RISCV_HI20;
2580 imm_expr->X_add_number <<= RISCV_IMM_BITS;
2581 }
2582 s = expr_end;
2583 continue;
2584
dcd709e0 2585 case 'a': /* 20-bit PC-relative offset. */
dc1e8a47 2586 jump:
e23eba97
NC		 2587 my_getExpression (imm_expr, s);
2588 s = expr_end;
2589 *imm_reloc = BFD_RELOC_RISCV_JMP;
2590 continue;
2591
2592 case 'c':
2593 my_getExpression (imm_expr, s);
2594 s = expr_end;
2595 if (strcmp (s, "@plt") == 0)
2596 {
2597 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2598 s += 4;
2599 }
2600 else
2601 *imm_reloc = BFD_RELOC_RISCV_CALL;
2602 continue;
1942a048 2603
0e35537d
JW		 2604 case 'O':
2605 switch (*++args)
2606 {
2607 case '4':
2608 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2609 || imm_expr->X_op != O_constant
2610 || imm_expr->X_add_number < 0
2611 || imm_expr->X_add_number >= 128
2612 || (imm_expr->X_add_number & 0x3) != 3)
2613 {
2614 as_bad (_("bad value for opcode field, "
2615 "value must be 0...127 and "
2616 "lower 2 bits must be 0x3"));
2617 break;
2618 }
0e35537d
JW		 2619 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2620 imm_expr->X_op = O_absent;
2621 s = expr_end;
2622 continue;
1942a048 2623
0e35537d
JW		 2624 case '2':
2625 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2626 || imm_expr->X_op != O_constant
2627 || imm_expr->X_add_number < 0
2628 || imm_expr->X_add_number >= 3)
2629 {
2630 as_bad (_("bad value for opcode field, "
2631 "value must be 0...2"));
2632 break;
2633 }
0e35537d
JW		 2634 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2635 imm_expr->X_op = O_absent;
2636 s = expr_end;
2637 continue;
1942a048 2638
0e35537d 2639 default:
b800637e
NC		 2640 as_bad (_("internal: unknown opcode field "
2641 "specifier `O%c'"), *args);
0e35537d
JW		 2642 }
2643 break;
2644
2645 case 'F':
2646 switch (*++args)
2647 {
2648 case '7':
2649 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2650 || imm_expr->X_op != O_constant
2651 || imm_expr->X_add_number < 0
2652 || imm_expr->X_add_number >= 128)
2653 {
2654 as_bad (_("bad value for funct7 field, "
2655 "value must be 0...127"));
2656 break;
2657 }
0e35537d
JW		 2658 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2659 imm_expr->X_op = O_absent;
2660 s = expr_end;
2661 continue;
1942a048 2662
0e35537d
JW		 2663 case '3':
2664 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2665 || imm_expr->X_op != O_constant
2666 || imm_expr->X_add_number < 0
2667 || imm_expr->X_add_number >= 8)
2668 {
2669 as_bad (_("bad value for funct3 field, "
2670 "value must be 0...7"));
2671 break;
2672 }
0e35537d
JW		 2673 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2674 imm_expr->X_op = O_absent;
2675 s = expr_end;
2676 continue;
1942a048 2677
0e35537d
JW		 2678 case '2':
2679 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2680 || imm_expr->X_op != O_constant
2681 || imm_expr->X_add_number < 0
2682 || imm_expr->X_add_number >= 4)
2683 {
2684 as_bad (_("bad value for funct2 field, "
2685 "value must be 0...3"));
2686 break;
2687 }
0e35537d
JW		 2688 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2689 imm_expr->X_op = O_absent;
2690 s = expr_end;
2691 continue;
2692
2693 default:
b800637e
NC		 2694 as_bad (_("internal: unknown funct field "
2695 "specifier `F%c'\n"), *args);
0e35537d
JW		 2696 }
2697 break;
e23eba97 2698
e925c834
JW		 2699 case 'z':
2700 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2701 || imm_expr->X_op != O_constant
2702 || imm_expr->X_add_number != 0)
2703 break;
2704 s = expr_end;
2705 imm_expr->X_op = O_absent;
2706 continue;
2707
e23eba97 2708 default:
b800637e 2709 as_fatal (_("internal: unknown argument type `%c'"), *args);
e23eba97
NC		 2710 }
2711 break;
2712 }
2713 s = argsStart;
2714 error = _("illegal operands");
5b7c81bd 2715 insn_with_csr = false;
e23eba97
NC		 2716 }
2717
dc1e8a47 2718 out:
e23eba97
NC		 2719 /* Restore the character we might have clobbered above. */
2720 if (save_c)
2721 *(argsStart - 1) = save_c;
2722
2723 return error;
2724}
2725
2726void
2727md_assemble (char *str)
2728{
2729 struct riscv_cl_insn insn;
2730 expressionS imm_expr;
2731 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2732
dcd709e0
NC		 2733 /* The architecture and privileged elf attributes should be set
2734 before assembling. */
8f595e9b
NC		 2735 if (!start_assemble)
2736 {
5b7c81bd 2737 start_assemble = true;
e23eba97 2738
dcd709e0 2739 riscv_set_abi_by_arch ();
8f595e9b
NC		 2740 if (!riscv_set_default_priv_spec (NULL))
2741 return;
2742 }
2743
2744 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
2dc8dd17 2745
e23eba97
NC		 2746 if (error)
2747 {
2748 as_bad ("%s `%s'", error, str);
2749 return;
2750 }
2751
2752 if (insn.insn_mo->pinfo == INSN_MACRO)
2753 macro (&insn, &imm_expr, &imm_reloc);
2754 else
2755 append_insn (&insn, &imm_expr, imm_reloc);
2756}
2757
2758const char *
2759md_atof (int type, char *litP, int *sizeP)
2760{
2761 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2762}
2763
2764void
2765md_number_to_chars (char *buf, valueT val, int n)
2766{
fbc09e7a
MC		 2767 if (target_big_endian)
2768 number_to_chars_bigendian (buf, val, n);
2769 else
2770 number_to_chars_littleendian (buf, val, n);
e23eba97
NC		 2771}
2772
2773const char *md_shortopts = "O::g::G:";
2774
2775enum options
2776{
2922d21d 2777 OPTION_MARCH = OPTION_MD_BASE,
e23eba97
NC		 2778 OPTION_PIC,
2779 OPTION_NO_PIC,
2922d21d 2780 OPTION_MABI,
71060565
JW		 2781 OPTION_RELAX,
2782 OPTION_NO_RELAX,
2dc8dd17
JW		 2783 OPTION_ARCH_ATTR,
2784 OPTION_NO_ARCH_ATTR,
2ca89224
NC		 2785 OPTION_CSR_CHECK,
2786 OPTION_NO_CSR_CHECK,
8f595e9b
NC		 2787 OPTION_MISA_SPEC,
2788 OPTION_MPRIV_SPEC,
fbc09e7a
MC		 2789 OPTION_BIG_ENDIAN,
2790 OPTION_LITTLE_ENDIAN,
e23eba97
NC		 2791 OPTION_END_OF_ENUM
2792};
2793
2794struct option md_longopts[] =
2795{
e23eba97
NC		 2796 {"march", required_argument, NULL, OPTION_MARCH},
2797 {"fPIC", no_argument, NULL, OPTION_PIC},
2798 {"fpic", no_argument, NULL, OPTION_PIC},
2799 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2922d21d 2800 {"mabi", required_argument, NULL, OPTION_MABI},
71060565
JW		 2801 {"mrelax", no_argument, NULL, OPTION_RELAX},
2802 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2dc8dd17
JW		 2803 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
2804 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
2ca89224
NC		 2805 {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
2806 {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
8f595e9b
NC		 2807 {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
2808 {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
fbc09e7a
MC		 2809 {"mbig-endian", no_argument, NULL, OPTION_BIG_ENDIAN},
2810 {"mlittle-endian", no_argument, NULL, OPTION_LITTLE_ENDIAN},
e23eba97
NC		 2811
2812 {NULL, no_argument, NULL, 0}
2813};
2814size_t md_longopts_size = sizeof (md_longopts);
2815
e23eba97
NC		 2816int
2817md_parse_option (int c, const char *arg)
2818{
2819 switch (c)
2820 {
e23eba97 2821 case OPTION_MARCH:
8f595e9b 2822 default_arch_with_ext = arg;
e23eba97
NC		 2823 break;
2824
2825 case OPTION_NO_PIC:
5b7c81bd 2826 riscv_opts.pic = false;
e23eba97
NC		 2827 break;
2828
2829 case OPTION_PIC:
5b7c81bd 2830 riscv_opts.pic = true;
e23eba97
NC		 2831 break;
2832
2922d21d
AW		 2833 case OPTION_MABI:
2834 if (strcmp (arg, "ilp32") == 0)
5b7c81bd 2835 riscv_set_abi (32, FLOAT_ABI_SOFT, false);
7f999549 2836 else if (strcmp (arg, "ilp32e") == 0)
5b7c81bd 2837 riscv_set_abi (32, FLOAT_ABI_SOFT, true);
2922d21d 2838 else if (strcmp (arg, "ilp32f") == 0)
5b7c81bd 2839 riscv_set_abi (32, FLOAT_ABI_SINGLE, false);
2922d21d 2840 else if (strcmp (arg, "ilp32d") == 0)
5b7c81bd 2841 riscv_set_abi (32, FLOAT_ABI_DOUBLE, false);
2922d21d 2842 else if (strcmp (arg, "ilp32q") == 0)
5b7c81bd 2843 riscv_set_abi (32, FLOAT_ABI_QUAD, false);
2922d21d 2844 else if (strcmp (arg, "lp64") == 0)
5b7c81bd 2845 riscv_set_abi (64, FLOAT_ABI_SOFT, false);
2922d21d 2846 else if (strcmp (arg, "lp64f") == 0)
5b7c81bd 2847 riscv_set_abi (64, FLOAT_ABI_SINGLE, false);
2922d21d 2848 else if (strcmp (arg, "lp64d") == 0)
5b7c81bd 2849 riscv_set_abi (64, FLOAT_ABI_DOUBLE, false);
2922d21d 2850 else if (strcmp (arg, "lp64q") == 0)
5b7c81bd 2851 riscv_set_abi (64, FLOAT_ABI_QUAD, false);
2922d21d
AW		 2852 else
2853 return 0;
5b7c81bd 2854 explicit_mabi = true;
2922d21d
AW		 2855 break;
2856
71060565 2857 case OPTION_RELAX:
5b7c81bd 2858 riscv_opts.relax = true;
71060565
JW		 2859 break;
2860
2861 case OPTION_NO_RELAX:
5b7c81bd 2862 riscv_opts.relax = false;
71060565
JW		 2863 break;
2864
2dc8dd17 2865 case OPTION_ARCH_ATTR:
5b7c81bd 2866 riscv_opts.arch_attr = true;
2dc8dd17
JW		 2867 break;
2868
2869 case OPTION_NO_ARCH_ATTR:
5b7c81bd 2870 riscv_opts.arch_attr = false;
2dc8dd17
JW		 2871 break;
2872
2ca89224 2873 case OPTION_CSR_CHECK:
5b7c81bd 2874 riscv_opts.csr_check = true;
2ca89224
NC		 2875 break;
2876
2877 case OPTION_NO_CSR_CHECK:
5b7c81bd 2878 riscv_opts.csr_check = false;
2ca89224
NC		 2879 break;
2880
8f595e9b
NC		 2881 case OPTION_MISA_SPEC:
2882 return riscv_set_default_isa_spec (arg);
2883
2884 case OPTION_MPRIV_SPEC:
2885 return riscv_set_default_priv_spec (arg);
2886
fbc09e7a
MC		 2887 case OPTION_BIG_ENDIAN:
2888 target_big_endian = 1;
2889 break;
2890
2891 case OPTION_LITTLE_ENDIAN:
2892 target_big_endian = 0;
2893 break;
2894
e23eba97
NC		 2895 default:
2896 return 0;
2897 }
2898
2899 return 1;
2900}
2901
2902void
2903riscv_after_parse_args (void)
2904{
dcd709e0
NC		 2905 /* The --with-arch is optional for now, so we still need to set the xlen
2906 according to the default_arch, which is set by the --target. */
e23eba97
NC		 2907 if (xlen == 0)
2908 {
2909 if (strcmp (default_arch, "riscv32") == 0)
2910 xlen = 32;
2911 else if (strcmp (default_arch, "riscv64") == 0)
2912 xlen = 64;
2913 else
2914 as_bad ("unknown default architecture `%s'", default_arch);
2915 }
8f595e9b
NC		 2916 if (default_arch_with_ext == NULL)
2917 default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
2918
2919 /* Initialize the hash table for extensions with default version. */
3d73d29e 2920 ext_version_hash = init_ext_version_hash ();
8f595e9b 2921
dcd709e0 2922 /* Set default specs. */
8f595e9b
NC		 2923 if (default_isa_spec == ISA_SPEC_CLASS_NONE)
2924 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
dcd709e0
NC		 2925 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
2926 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
2922d21d 2927
8f595e9b 2928 riscv_set_arch (default_arch_with_ext);
2922d21d
AW		 2929
2930 /* Add the RVC extension, regardless of -march, to support .option rvc. */
5b7c81bd 2931 riscv_set_rvc (false);
1080bf78 2932 if (riscv_subset_supports ("c"))
5b7c81bd 2933 riscv_set_rvc (true);
2922d21d 2934
7f999549 2935 /* Enable RVE if specified by the -march option. */
5b7c81bd 2936 riscv_set_rve (false);
1080bf78 2937 if (riscv_subset_supports ("e"))
5b7c81bd 2938 riscv_set_rve (true);
7f999549 2939
0ac2b354
AB		 2940 /* If the CIE to be produced has not been overridden on the command line,
2941 then produce version 3 by default. This allows us to use the full
2942 range of registers in a .cfi_return_column directive. */
2943 if (flag_dwarf_cie_version == -1)
2944 flag_dwarf_cie_version = 3;
e23eba97
NC		 2945}
2946
2947long
2948md_pcrel_from (fixS *fixP)
2949{
2950 return fixP->fx_where + fixP->fx_frag->fr_address;
2951}
2952
2953/* Apply a fixup to the object file. */
2954
2955void
2956md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2957{
45f76423 2958 unsigned int subtype;
e23eba97 2959 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
5b7c81bd 2960 bool relaxable = false;
c1b465c9 2961 offsetT loc;
a6cbf936 2962 segT sub_segment;
e23eba97
NC		 2963
2964 /* Remember value for tc_gen_reloc. */
2965 fixP->fx_addnumber = *valP;
2966
2967 switch (fixP->fx_r_type)
2968 {
e23eba97
NC		 2969 case BFD_RELOC_RISCV_HI20:
2970 case BFD_RELOC_RISCV_LO12_I:
2971 case BFD_RELOC_RISCV_LO12_S:
45f76423
AW		 2972 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2973 | bfd_getl32 (buf), buf);
a5ec5e3f 2974 if (fixP->fx_addsy == NULL)
5b7c81bd
AM		 2975 fixP->fx_done = true;
2976 relaxable = true;
45f76423
AW		 2977 break;
2978
2979 case BFD_RELOC_RISCV_GOT_HI20:
e23eba97
NC		 2980 case BFD_RELOC_RISCV_ADD8:
2981 case BFD_RELOC_RISCV_ADD16:
2982 case BFD_RELOC_RISCV_ADD32:
2983 case BFD_RELOC_RISCV_ADD64:
45f76423 2984 case BFD_RELOC_RISCV_SUB6:
e23eba97
NC		 2985 case BFD_RELOC_RISCV_SUB8:
2986 case BFD_RELOC_RISCV_SUB16:
2987 case BFD_RELOC_RISCV_SUB32:
2988 case BFD_RELOC_RISCV_SUB64:
45f76423
AW		 2989 case BFD_RELOC_RISCV_RELAX:
2990 break;
2991
2992 case BFD_RELOC_RISCV_TPREL_HI20:
2993 case BFD_RELOC_RISCV_TPREL_LO12_I:
2994 case BFD_RELOC_RISCV_TPREL_LO12_S:
2995 case BFD_RELOC_RISCV_TPREL_ADD:
5b7c81bd 2996 relaxable = true;
45f76423
AW		 2997 /* Fall through. */
2998
2999 case BFD_RELOC_RISCV_TLS_GOT_HI20:
3000 case BFD_RELOC_RISCV_TLS_GD_HI20:
3001 case BFD_RELOC_RISCV_TLS_DTPREL32:
3002 case BFD_RELOC_RISCV_TLS_DTPREL64:
e294484e
AW		 3003 if (fixP->fx_addsy != NULL)
3004 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3005 else
3006 as_bad_where (fixP->fx_file, fixP->fx_line,
3007 _("TLS relocation against a constant"));
e23eba97
NC		 3008 break;
3009
e23eba97 3010 case BFD_RELOC_32:
a6cbf936
KLC		 3011 /* Use pc-relative relocation for FDE initial location.
3012 The symbol address in .eh_frame may be adjusted in
3013 _bfd_elf_discard_section_eh_frame, and the content of
3014 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
3015 Therefore, we cannot insert a relocation whose addend symbol is
dcd709e0 3016 in .eh_frame. Othrewise, the value may be adjusted twice. */
a6cbf936
KLC		 3017 if (fixP->fx_addsy && fixP->fx_subsy
3018 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
3019 && strcmp (sub_segment->name, ".eh_frame") == 0
3020 && S_GET_VALUE (fixP->fx_subsy)
3021 == fixP->fx_frag->fr_address + fixP->fx_where)
3022 {
3023 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
3024 fixP->fx_subsy = NULL;
3025 break;
3026 }
3027 /* Fall through. */
3028 case BFD_RELOC_64:
e23eba97
NC		 3029 case BFD_RELOC_16:
3030 case BFD_RELOC_8:
45f76423 3031 case BFD_RELOC_RISCV_CFA:
e23eba97
NC		 3032 if (fixP->fx_addsy && fixP->fx_subsy)
3033 {
3034 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3035 fixP->fx_next->fx_addsy = fixP->fx_subsy;
3036 fixP->fx_next->fx_subsy = NULL;
3037 fixP->fx_next->fx_offset = 0;
3038 fixP->fx_subsy = NULL;
3039
3040 switch (fixP->fx_r_type)
3041 {
3042 case BFD_RELOC_64:
3043 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
3044 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
3045 break;
3046
3047 case BFD_RELOC_32:
3048 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
3049 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
3050 break;
3051
3052 case BFD_RELOC_16:
3053 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
3054 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
3055 break;
3056
3057 case BFD_RELOC_8:
3058 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
3059 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
073808ed 3060 break;
e23eba97 3061
45f76423
AW		 3062 case BFD_RELOC_RISCV_CFA:
3063 /* Load the byte to get the subtype. */
c1b465c9
KLC		 3064 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
3065 loc = fixP->fx_frag->fr_fix - (subtype & 7);
45f76423
AW		 3066 switch (subtype)
3067 {
3068 case DW_CFA_advance_loc1:
c1b465c9
KLC		 3069 fixP->fx_where = loc + 1;
3070 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 3071 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
3072 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
3073 break;
3074
3075 case DW_CFA_advance_loc2:
3076 fixP->fx_size = 2;
45f76423 3077 fixP->fx_next->fx_size = 2;
c1b465c9
KLC		 3078 fixP->fx_where = loc + 1;
3079 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 3080 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
3081 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
3082 break;
3083
3084 case DW_CFA_advance_loc4:
3085 fixP->fx_size = 4;
45f76423 3086 fixP->fx_next->fx_size = 4;
c1b465c9
KLC		 3087 fixP->fx_where = loc;
3088 fixP->fx_next->fx_where = loc;
45f76423
AW		 3089 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
3090 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
3091 break;
3092
3093 default:
3094 if (subtype < 0x80 && (subtype & 0x40))
3095 {
3096 /* DW_CFA_advance_loc */
2aece2ba
KLC		 3097 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
3098 fixP->fx_next->fx_frag = fixP->fx_frag;
45f76423
AW		 3099 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
3100 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
3101 }
3102 else
b800637e 3103 as_fatal (_("internal: bad CFA value #%d"), subtype);
45f76423
AW		 3104 break;
3105 }
3106 break;
3107
e23eba97
NC		 3108 default:
3109 /* This case is unreachable. */
3110 abort ();
3111 }
3112 }
3113 /* Fall through. */
3114
3115 case BFD_RELOC_RVA:
3116 /* If we are deleting this reloc entry, we must fill in the
3117 value now. This can happen if we have a .word which is not
3118 resolved when it appears but is later defined. */
3119 if (fixP->fx_addsy == NULL)
3120 {
3121 gas_assert (fixP->fx_size <= sizeof (valueT));
3122 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
3123 fixP->fx_done = 1;
3124 }
3125 break;
3126
3127 case BFD_RELOC_RISCV_JMP:
3128 if (fixP->fx_addsy)
3129 {
3130 /* Fill in a tentative value to improve objdump readability. */
3131 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3132 bfd_vma delta = target - md_pcrel_from (fixP);
5a9f5403 3133 bfd_putl32 (bfd_getl32 (buf) | ENCODE_JTYPE_IMM (delta), buf);
e23eba97
NC		 3134 }
3135 break;
3136
3137 case BFD_RELOC_12_PCREL:
3138 if (fixP->fx_addsy)
3139 {
3140 /* Fill in a tentative value to improve objdump readability. */
3141 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3142 bfd_vma delta = target - md_pcrel_from (fixP);
5a9f5403 3143 bfd_putl32 (bfd_getl32 (buf) | ENCODE_BTYPE_IMM (delta), buf);
e23eba97
NC		 3144 }
3145 break;
3146
3147 case BFD_RELOC_RISCV_RVC_BRANCH:
3148 if (fixP->fx_addsy)
3149 {
3150 /* Fill in a tentative value to improve objdump readability. */
3151 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3152 bfd_vma delta = target - md_pcrel_from (fixP);
5a9f5403 3153 bfd_putl16 (bfd_getl16 (buf) | ENCODE_CBTYPE_IMM (delta), buf);
e23eba97
NC		 3154 }
3155 break;
3156
3157 case BFD_RELOC_RISCV_RVC_JUMP:
3158 if (fixP->fx_addsy)
3159 {
3160 /* Fill in a tentative value to improve objdump readability. */
3161 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3162 bfd_vma delta = target - md_pcrel_from (fixP);
5a9f5403 3163 bfd_putl16 (bfd_getl16 (buf) | ENCODE_CJTYPE_IMM (delta), buf);
e23eba97
NC		 3164 }
3165 break;
3166
e23eba97
NC		 3167 case BFD_RELOC_RISCV_CALL:
3168 case BFD_RELOC_RISCV_CALL_PLT:
5b7c81bd 3169 relaxable = true;
45f76423
AW		 3170 break;
3171
9d06997a 3172 case BFD_RELOC_RISCV_PCREL_HI20:
45f76423
AW		 3173 case BFD_RELOC_RISCV_PCREL_LO12_S:
3174 case BFD_RELOC_RISCV_PCREL_LO12_I:
9d06997a
PD		 3175 relaxable = riscv_opts.relax;
3176 break;
3177
e23eba97
NC		 3178 case BFD_RELOC_RISCV_ALIGN:
3179 break;
3180
3181 default:
3182 /* We ignore generic BFD relocations we don't know about. */
3183 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
b800637e 3184 as_fatal (_("internal: bad relocation #%d"), fixP->fx_r_type);
e23eba97 3185 }
45f76423 3186
e294484e
AW		 3187 if (fixP->fx_subsy != NULL)
3188 as_bad_where (fixP->fx_file, fixP->fx_line,
3189 _("unsupported symbol subtraction"));
3190
45f76423
AW		 3191 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3192 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
3193 {
3194 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3195 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
3196 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
b1b11e92 3197 fixP->fx_next->fx_size = 0;
45f76423
AW		 3198 }
3199}
3200
3201/* Because the value of .cfi_remember_state may changed after relaxation,
3202 we insert a fix to relocate it again in link-time. */
3203
3204void
3205riscv_pre_output_hook (void)
3206{
3207 const frchainS *frch;
72393fd1
JW		 3208 segT s;
3209
3210 /* Save the current segment info. */
3211 segT seg = now_seg;
3212 subsegT subseg = now_subseg;
45f76423
AW		 3213
3214 for (s = stdoutput->sections; s; s = s->next)
3215 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
3216 {
7cb7b948 3217 fragS *frag;
45f76423
AW		 3218
3219 for (frag = frch->frch_root; frag; frag = frag->fr_next)
3220 {
3221 if (frag->fr_type == rs_cfa)
3222 {
45f76423 3223 expressionS exp;
8d1015a8 3224 expressionS *symval;
45f76423 3225
8d1015a8 3226 symval = symbol_get_value_expression (frag->fr_symbol);
45f76423 3227 exp.X_op = O_subtract;
8d1015a8 3228 exp.X_add_symbol = symval->X_add_symbol;
45f76423 3229 exp.X_add_number = 0;
8d1015a8 3230 exp.X_op_symbol = symval->X_op_symbol;
45f76423 3231
72393fd1
JW		 3232 /* We must set the segment before creating a frag after all
3233 frag chains have been chained together. */
3234 subseg_set (s, frch->frch_subseg);
3235
c1b465c9 3236 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
45f76423
AW		 3237 BFD_RELOC_RISCV_CFA);
3238 }
3239 }
3240 }
72393fd1
JW		 3241
3242 /* Restore the original segment info. */
3243 subseg_set (seg, subseg);
e23eba97
NC		 3244}
3245
3246/* This structure is used to hold a stack of .option values. */
e23eba97
NC		 3247struct riscv_option_stack
3248{
3249 struct riscv_option_stack *next;
3250 struct riscv_set_options options;
3251};
3252
3253static struct riscv_option_stack *riscv_opts_stack;
3254
3255/* Handle the .option pseudo-op. */
3256
3257static void
3258s_riscv_option (int x ATTRIBUTE_UNUSED)
3259{
3260 char *name = input_line_pointer, ch;
3261
3262 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3263 ++input_line_pointer;
3264 ch = *input_line_pointer;
3265 *input_line_pointer = '\0';
3266
3267 if (strcmp (name, "rvc") == 0)
5b7c81bd 3268 riscv_set_rvc (true);
e23eba97 3269 else if (strcmp (name, "norvc") == 0)
5b7c81bd 3270 riscv_set_rvc (false);
e23eba97 3271 else if (strcmp (name, "pic") == 0)
5b7c81bd 3272 riscv_opts.pic = true;
e23eba97 3273 else if (strcmp (name, "nopic") == 0)
5b7c81bd 3274 riscv_opts.pic = false;
45f76423 3275 else if (strcmp (name, "relax") == 0)
5b7c81bd 3276 riscv_opts.relax = true;
45f76423 3277 else if (strcmp (name, "norelax") == 0)
5b7c81bd 3278 riscv_opts.relax = false;
2ca89224 3279 else if (strcmp (name, "csr-check") == 0)
5b7c81bd 3280 riscv_opts.csr_check = true;
2ca89224 3281 else if (strcmp (name, "no-csr-check") == 0)
5b7c81bd 3282 riscv_opts.csr_check = false;
e23eba97
NC		 3283 else if (strcmp (name, "push") == 0)
3284 {
3285 struct riscv_option_stack *s;
3286
3287 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
3288 s->next = riscv_opts_stack;
3289 s->options = riscv_opts;
3290 riscv_opts_stack = s;
3291 }
3292 else if (strcmp (name, "pop") == 0)
3293 {
3294 struct riscv_option_stack *s;
3295
3296 s = riscv_opts_stack;
3297 if (s == NULL)
3298 as_bad (_(".option pop with no .option push"));
3299 else
3300 {
3301 riscv_opts = s->options;
3302 riscv_opts_stack = s->next;
3303 free (s);
3304 }
3305 }
3306 else
3307 {
b800637e 3308 as_warn (_("unrecognized .option directive: %s\n"), name);
e23eba97
NC		 3309 }
3310 *input_line_pointer = ch;
3311 demand_empty_rest_of_line ();
3312}
3313
3314/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3315 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3316 use in DWARF debug information. */
3317
3318static void
3319s_dtprel (int bytes)
3320{
3321 expressionS ex;
3322 char *p;
3323
3324 expression (&ex);
3325
3326 if (ex.X_op != O_symbol)
3327 {
b800637e 3328 as_bad (_("unsupported use of %s"), (bytes == 8
e23eba97
NC		 3329 ? ".dtpreldword"
3330 : ".dtprelword"));
3331 ignore_rest_of_line ();
3332 }
3333
3334 p = frag_more (bytes);
3335 md_number_to_chars (p, 0, bytes);
5b7c81bd 3336 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false,
e23eba97
NC		 3337 (bytes == 8
3338 ? BFD_RELOC_RISCV_TLS_DTPREL64
3339 : BFD_RELOC_RISCV_TLS_DTPREL32));
3340
3341 demand_empty_rest_of_line ();
3342}
3343
3344/* Handle the .bss pseudo-op. */
3345
3346static void
3347s_bss (int ignore ATTRIBUTE_UNUSED)
3348{
3349 subseg_set (bss_section, 0);
3350 demand_empty_rest_of_line ();
3351}
3352
e23eba97 3353static void
d115ab8e 3354riscv_make_nops (char *buf, bfd_vma bytes)
e23eba97 3355{
d115ab8e 3356 bfd_vma i = 0;
e23eba97 3357
e5b737de
AW		 3358 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3359 means we are not within a valid instruction sequence. It is thus safe
3360 to use a zero byte, even though that is not a valid instruction. */
3361 if (bytes % 2 == 1)
3362 buf[i++] = 0;
3363
3364 /* Use at most one 2-byte NOP. */
3365 if ((bytes - i) % 4 == 2)
e23eba97 3366 {
fbc09e7a 3367 number_to_chars_littleendian (buf + i, RVC_NOP, 2);
d115ab8e 3368 i += 2;
e23eba97
NC		 3369 }
3370
e5b737de 3371 /* Fill the remainder with 4-byte NOPs. */
d115ab8e 3372 for ( ; i < bytes; i += 4)
fbc09e7a 3373 number_to_chars_littleendian (buf + i, RISCV_NOP, 4);
d115ab8e 3374}
e23eba97 3375
d115ab8e
AW		 3376/* Called from md_do_align. Used to create an alignment frag in a
3377 code section by emitting a worst-case NOP sequence that the linker
3378 will later relax to the correct number of NOPs. We can't compute
3379 the correct alignment now because of other linker relaxations. */
3380
5b7c81bd 3381bool
d115ab8e
AW		 3382riscv_frag_align_code (int n)
3383{
e5b737de 3384 bfd_vma bytes = (bfd_vma) 1 << n;
36877bfb
JW		 3385 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
3386 bfd_vma worst_case_bytes = bytes - insn_alignment;
3387 char *nops;
ed0816bd 3388 expressionS ex;
d115ab8e 3389
36877bfb
JW		 3390 /* If we are moving to a smaller alignment than the instruction size, then no
3391 alignment is required. */
3392 if (bytes <= insn_alignment)
5b7c81bd 3393 return true;
36877bfb 3394
d115ab8e
AW		 3395 /* When not relaxing, riscv_handle_align handles code alignment. */
3396 if (!riscv_opts.relax)
5b7c81bd 3397 return false;
e23eba97 3398
e80ae190
JW		 3399 nops = frag_more (worst_case_bytes);
3400
ed0816bd
PD		 3401 ex.X_op = O_constant;
3402 ex.X_add_number = worst_case_bytes;
d115ab8e 3403
ed0816bd 3404 riscv_make_nops (nops, worst_case_bytes);
e23eba97 3405
ed0816bd 3406 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
5b7c81bd 3407 &ex, false, BFD_RELOC_RISCV_ALIGN);
e23eba97 3408
5b7c81bd 3409 return true;
d115ab8e 3410}
e23eba97 3411
d115ab8e
AW		 3412/* Implement HANDLE_ALIGN. */
3413
3414void
3415riscv_handle_align (fragS *fragP)
3416{
3417 switch (fragP->fr_type)
3418 {
3419 case rs_align_code:
3420 /* When relaxing, riscv_frag_align_code handles code alignment. */
3421 if (!riscv_opts.relax)
3422 {
e80ae190
JW		 3423 bfd_signed_vma bytes = (fragP->fr_next->fr_address
3424 - fragP->fr_address - fragP->fr_fix);
3425 /* We have 4 byte uncompressed nops. */
3426 bfd_signed_vma size = 4;
3427 bfd_signed_vma excess = bytes % size;
3428 char *p = fragP->fr_literal + fragP->fr_fix;
3429
3430 if (bytes <= 0)
d115ab8e
AW		 3431 break;
3432
e80ae190
JW		 3433 /* Insert zeros or compressed nops to get 4 byte alignment. */
3434 if (excess)
3435 {
3436 riscv_make_nops (p, excess);
3437 fragP->fr_fix += excess;
3438 p += excess;
3439 }
3440
3441 /* Insert variable number of 4 byte uncompressed nops. */
3442 riscv_make_nops (p, size);
3443 fragP->fr_var = size;
d115ab8e
AW		 3444 }
3445 break;
3446
3447 default:
3448 break;
3449 }
e23eba97
NC		 3450}
3451
3452int
3453md_estimate_size_before_relax (fragS *fragp, asection *segtype)
3454{
5b7c81bd 3455 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, false));
e23eba97
NC		 3456}
3457
3458/* Translate internal representation of relocation info to BFD target
3459 format. */
3460
3461arelent *
3462tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3463{
3464 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
3465
3466 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3467 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3468 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3469 reloc->addend = fixp->fx_addnumber;
3470
3471 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3472 if (reloc->howto == NULL)
3473 {
3474 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
3475 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
3476 {
3477 /* We don't have R_RISCV_8/16, but for this special case,
3478 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3479 return reloc;
3480 }
3481
3482 as_bad_where (fixp->fx_file, fixp->fx_line,
3483 _("cannot represent %s relocation in object file"),
3484 bfd_get_reloc_code_name (fixp->fx_r_type));
3485 return NULL;
3486 }
3487
3488 return reloc;
3489}
3490
3491int
3492riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
3493{
3494 if (RELAX_BRANCH_P (fragp->fr_subtype))
3495 {
3496 offsetT old_var = fragp->fr_var;
5b7c81bd 3497 fragp->fr_var = relaxed_branch_length (fragp, sec, true);
e23eba97
NC		 3498 return fragp->fr_var - old_var;
3499 }
3500
3501 return 0;
3502}
3503
3504/* Expand far branches to multi-instruction sequences. */
3505
3506static void
3507md_convert_frag_branch (fragS *fragp)
3508{
3509 bfd_byte *buf;
3510 expressionS exp;
3511 fixS *fixp;
3512 insn_t insn;
3513 int rs1, reloc;
3514
3515 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
3516
3517 exp.X_op = O_symbol;
3518 exp.X_add_symbol = fragp->fr_symbol;
3519 exp.X_add_number = fragp->fr_offset;
3520
3521 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
3522
3523 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
3524 {
3525 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3526 {
3527 case 8:
3528 case 4:
3529 /* Expand the RVC branch into a RISC-V one. */
3530 insn = bfd_getl16 (buf);
3531 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
3532 if ((insn & MASK_C_J) == MATCH_C_J)
3533 insn = MATCH_JAL;
3534 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
3535 insn = MATCH_JAL | (X_RA << OP_SH_RD);
3536 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
3537 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
3538 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
3539 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
3540 else
3541 abort ();
3542 bfd_putl32 (insn, buf);
3543 break;
3544
3545 case 6:
3546 /* Invert the branch condition. Branch over the jump. */
3547 insn = bfd_getl16 (buf);
3548 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
5a9f5403 3549 insn |= ENCODE_CBTYPE_IMM (6);
e23eba97
NC		 3550 bfd_putl16 (insn, buf);
3551 buf += 2;
3552 goto jump;
3553
3554 case 2:
3555 /* Just keep the RVC branch. */
3556 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3557 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
3558 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
5b7c81bd 3559 2, &exp, false, reloc);
e23eba97
NC		 3560 buf += 2;
3561 goto done;
3562
3563 default:
1d65abb5 3564 abort ();
e23eba97
NC		 3565 }
3566 }
3567
3568 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3569 {
3570 case 8:
3571 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
3572
3573 /* Invert the branch condition. Branch over the jump. */
3574 insn = bfd_getl32 (buf);
3575 insn ^= MATCH_BEQ ^ MATCH_BNE;
5a9f5403 3576 insn |= ENCODE_BTYPE_IMM (8);
fbc09e7a 3577 bfd_putl32 (insn, buf);
e23eba97
NC		 3578 buf += 4;
3579
dc1e8a47 3580 jump:
e23eba97
NC		 3581 /* Jump to the target. */
3582 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
5b7c81bd 3583 4, &exp, false, BFD_RELOC_RISCV_JMP);
fbc09e7a 3584 bfd_putl32 (MATCH_JAL, buf);
e23eba97
NC		 3585 buf += 4;
3586 break;
3587
3588 case 4:
3589 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3590 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
3591 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
5b7c81bd 3592 4, &exp, false, reloc);
e23eba97
NC		 3593 buf += 4;
3594 break;
3595
3596 default:
3597 abort ();
3598 }
3599
dc1e8a47 3600 done:
e23eba97
NC		 3601 fixp->fx_file = fragp->fr_file;
3602 fixp->fx_line = fragp->fr_line;
3603
3604 gas_assert (buf == (bfd_byte *)fragp->fr_literal
3605 + fragp->fr_fix + fragp->fr_var);
3606
3607 fragp->fr_fix += fragp->fr_var;
3608}
3609
3610/* Relax a machine dependent frag. This returns the amount by which
3611 the current size of the frag should change. */
3612
3613void
3614md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3615 fragS *fragp)
3616{
3617 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
3618 md_convert_frag_branch (fragp);
3619}
3620
3621void
3622md_show_usage (FILE *stream)
3623{
3624 fprintf (stream, _("\
3625RISC-V options:\n\
8f595e9b
NC		 3626 -fpic generate position-independent code\n\
3627 -fno-pic don't generate position-independent code (default)\n\
3628 -march=ISA set the RISC-V architecture\n\
3629 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3630 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3631 -mabi=ABI set the RISC-V ABI\n\
3632 -mrelax enable relax (default)\n\
3633 -mno-relax disable relax\n\
3634 -march-attr generate RISC-V arch attribute\n\
3635 -mno-arch-attr don't generate RISC-V arch attribute\n\
e23eba97
NC		 3636"));
3637}
3638
3639/* Standard calling conventions leave the CFA at SP on entry. */
dcd709e0 3640
e23eba97
NC		 3641void
3642riscv_cfi_frame_initial_instructions (void)
3643{
3644 cfi_add_CFA_def_cfa_register (X_SP);
3645}
3646
3647int
3648tc_riscv_regname_to_dw2regnum (char *regname)
3649{
3650 int reg;
3651
3652 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3653 return reg;
3654
3655 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3656 return reg + 32;
3657
4762fe62
AB		 3658 /* CSRs are numbered 4096 -> 8191. */
3659 if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
3660 return reg + 4096;
3661
e23eba97
NC		 3662 as_bad (_("unknown register `%s'"), regname);
3663 return -1;
3664}
3665
3666void
3667riscv_elf_final_processing (void)
3668{
6e1605e4 3669 riscv_set_abi_by_arch ();
e23eba97 3670 elf_elfheader (stdoutput)->e_flags |= elf_flags;
e23eba97
NC		 3671}
3672
3673/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3674 since these directives break relaxation when used with symbol deltas. */
3675
3676static void
3677s_riscv_leb128 (int sign)
3678{
3679 expressionS exp;
3680 char *save_in = input_line_pointer;
3681
3682 expression (&exp);
3683 if (exp.X_op != O_constant)
3684 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3685 demand_empty_rest_of_line ();
3686
3687 input_line_pointer = save_in;
3688 return s_leb128 (sign);
3689}
3690
0e35537d
JW		 3691/* Parse the .insn directive. */
3692
3693static void
3694s_riscv_insn (int x ATTRIBUTE_UNUSED)
3695{
3696 char *str = input_line_pointer;
3697 struct riscv_cl_insn insn;
3698 expressionS imm_expr;
3699 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3700 char save_c;
3701
3702 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3703 ++input_line_pointer;
3704
3705 save_c = *input_line_pointer;
3706 *input_line_pointer = '\0';
3707
3708 const char *error = riscv_ip (str, &insn, &imm_expr,
3709 &imm_reloc, insn_type_hash);
3710
3711 if (error)
3712 {
3713 as_bad ("%s `%s'", error, str);
3714 }
3715 else
3716 {
3717 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3718 append_insn (&insn, &imm_expr, imm_reloc);
3719 }
3720
3721 *input_line_pointer = save_c;
3722 demand_empty_rest_of_line ();
3723}
3724
dcd709e0
NC		 3725/* Update architecture and privileged elf attributes. If we don't set
3726 them, then try to output the default ones. */
2dc8dd17
JW		 3727
3728static void
8f595e9b 3729riscv_write_out_attrs (void)
2dc8dd17 3730{
8f595e9b 3731 const char *arch_str, *priv_str, *p;
dcd709e0
NC		 3732 /* versions[0]: major version.
3733 versions[1]: minor version.
3734 versions[2]: revision version. */
8f595e9b
NC		 3735 unsigned versions[3] = {0}, number = 0;
3736 unsigned int i;
2dc8dd17 3737
dcd709e0 3738 /* Re-write architecture elf attribute. */
8f595e9b 3739 arch_str = riscv_arch_str (xlen, &riscv_subsets);
2dc8dd17 3740 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
1942a048 3741 xfree ((void *) arch_str);
8f595e9b
NC		 3742
3743 /* For the file without any instruction, we don't set the default_priv_spec
dcd709e0
NC		 3744 according to the privileged elf attributes since the md_assemble isn't
3745 called. */
8f595e9b
NC		 3746 if (!start_assemble
3747 && !riscv_set_default_priv_spec (NULL))
3748 return;
3749
dcd709e0
NC		 3750 /* If we already have set privileged elf attributes, then no need to do
3751 anything. Otherwise, don't generate or update them when no CSR and
3752 privileged instructions are used. */
1a79004f 3753 if (!explicit_priv_attr)
3fc6c3dc
NC		 3754 return;
3755
3d73d29e 3756 RISCV_GET_PRIV_SPEC_NAME (priv_str, default_priv_spec);
8f595e9b
NC		 3757 p = priv_str;
3758 for (i = 0; *p; ++p)
3759 {
3760 if (*p == '.' && i < 3)
3761 {
3762 versions[i++] = number;
3763 number = 0;
3764 }
3765 else if (ISDIGIT (*p))
3766 number = (number * 10) + (*p - '0');
3767 else
3768 {
b800637e 3769 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str);
8f595e9b
NC		 3770 return;
3771 }
3772 }
3773 versions[i] = number;
3774
dcd709e0 3775 /* Re-write privileged elf attributes. */
8f595e9b
NC		 3776 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
3777 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
3778 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
2dc8dd17
JW		 3779}
3780
dcd709e0 3781/* Add the default contents for the .riscv.attributes section. */
2dc8dd17
JW		 3782
3783static void
3784riscv_set_public_attributes (void)
3785{
8f595e9b
NC		 3786 if (riscv_opts.arch_attr || explicit_attr)
3787 riscv_write_out_attrs ();
2dc8dd17
JW		 3788}
3789
3790/* Called after all assembly has been done. */
3791
3792void
3793riscv_md_end (void)
3794{
3795 riscv_set_public_attributes ();
3796}
3797
3798/* Given a symbolic attribute NAME, return the proper integer value.
3799 Returns -1 if the attribute is not known. */
3800
3801int
3802riscv_convert_symbolic_attribute (const char *name)
3803{
3804 static const struct
3805 {
1942a048
NC		 3806 const char *name;
3807 const int tag;
2dc8dd17
JW		 3808 }
3809 attribute_table[] =
1942a048
NC		 3810 {
3811 /* When you modify this table you should
3812 also modify the list in doc/c-riscv.texi. */
3813#define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3814 T(arch),
3815 T(priv_spec),
3816 T(priv_spec_minor),
3817 T(priv_spec_revision),
3818 T(unaligned_access),
3819 T(stack_align),
2dc8dd17 3820#undef T
1942a048 3821 };
2dc8dd17
JW		 3822
3823 if (name == NULL)
3824 return -1;
3825
1942a048 3826 unsigned int i;
2dc8dd17
JW		 3827 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
3828 if (strcmp (name, attribute_table[i].name) == 0)
3829 return attribute_table[i].tag;
3830
3831 return -1;
3832}
3833
3834/* Parse a .attribute directive. */
3835
3836static void
3837s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
3838{
3839 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
8f595e9b
NC		 3840 unsigned old_xlen;
3841 obj_attribute *attr;
2dc8dd17 3842
5b7c81bd 3843 explicit_attr = true;
8f595e9b 3844 switch (tag)
2dc8dd17 3845 {
8f595e9b
NC		 3846 case Tag_RISCV_arch:
3847 old_xlen = xlen;
2dc8dd17
JW		 3848 attr = elf_known_obj_attributes_proc (stdoutput);
3849 if (!start_assemble)
3850 riscv_set_arch (attr[Tag_RISCV_arch].s);
3851 else
b800637e
NC		 3852 as_fatal (_("architecture elf attributes must set before "
3853 "any instructions"));
2dc8dd17
JW		 3854
3855 if (old_xlen != xlen)
3856 {
3857 /* We must re-init bfd again if xlen is changed. */
3858 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
3859 bfd_find_target (riscv_target_format (), stdoutput);
3860
3861 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
b800637e 3862 as_warn (_("could not set architecture and machine"));
2dc8dd17 3863 }
8f595e9b
NC		 3864 break;
3865
3866 case Tag_RISCV_priv_spec:
3867 case Tag_RISCV_priv_spec_minor:
3868 case Tag_RISCV_priv_spec_revision:
3869 if (start_assemble)
b800637e
NC		 3870 as_fatal (_("privileged elf attributes must set before "
3871 "any instructions"));
8f595e9b
NC		 3872 break;
3873
3874 default:
3875 break;
2dc8dd17
JW		 3876 }
3877}
3878
dcd709e0 3879/* RISC-V pseudo-ops table. */
e23eba97
NC		 3880static const pseudo_typeS riscv_pseudo_table[] =
3881{
e23eba97
NC		 3882 {"option", s_riscv_option, 0},
3883 {"half", cons, 2},
3884 {"word", cons, 4},
3885 {"dword", cons, 8},
3886 {"dtprelword", s_dtprel, 4},
3887 {"dtpreldword", s_dtprel, 8},
3888 {"bss", s_bss, 0},
e23eba97
NC		 3889 {"uleb128", s_riscv_leb128, 0},
3890 {"sleb128", s_riscv_leb128, 1},
0e35537d 3891 {"insn", s_riscv_insn, 0},
2dc8dd17 3892 {"attribute", s_riscv_attribute, 0},
e23eba97
NC		 3893
3894 { NULL, NULL, 0 },
3895};
3896
3897void
3898riscv_pop_insert (void)
3899{
3900 extern void pop_insert (const pseudo_typeS *);
3901
3902 pop_insert (riscv_pseudo_table);
3903}
GDB Binutils - Deliverables
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