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RISC-V: Error and warning messages tidy.
[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
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e23eba97 1/* tc-riscv.c -- RISC-V assembler
250d07de 2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
1080bf78 32#include "bfd/elfxx-riscv.h"
e23eba97
NC		 33#include "elf/riscv.h"
34#include "opcode/riscv.h"
35
36#include <stdint.h>
37
38/* Information about an instruction, including its format, operands
39 and fixups. */
40struct riscv_cl_insn
41{
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode *insn_mo;
44
45 /* The encoded instruction bits. */
46 insn_t insn_opcode;
47
48 /* The frag that contains the instruction. */
49 struct frag *frag;
50
51 /* The offset into FRAG of the first instruction byte. */
52 long where;
53
54 /* The relocs associated with the instruction, if any. */
55 fixS *fixp;
56};
57
58#ifndef DEFAULT_ARCH
59#define DEFAULT_ARCH "riscv64"
60#endif
61
2dc8dd17
JW		 62#ifndef DEFAULT_RISCV_ATTR
63#define DEFAULT_RISCV_ATTR 0
64#endif
65
8f595e9b 66/* Let riscv_after_parse_args set the default value according to xlen. */
8f595e9b
NC		 67#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
68#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
69#endif
70
dcd709e0 71/* Need to sync the version with RISC-V compiler. */
8f595e9b
NC		 72#ifndef DEFAULT_RISCV_ISA_SPEC
73#define DEFAULT_RISCV_ISA_SPEC "2.2"
74#endif
75
76#ifndef DEFAULT_RISCV_PRIV_SPEC
77#define DEFAULT_RISCV_PRIV_SPEC "1.11"
78#endif
79
e23eba97 80static const char default_arch[] = DEFAULT_ARCH;
8f595e9b
NC		 81static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
82static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
83static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
e23eba97 84
dcd709e0
NC		 85static unsigned xlen = 0; /* The width of an x-register. */
86static unsigned abi_xlen = 0; /* The width of a pointer in the ABI. */
7f999549 87static bfd_boolean rve_abi = FALSE;
6e1605e4
NC		 88enum float_abi {
89 FLOAT_ABI_DEFAULT = -1,
90 FLOAT_ABI_SOFT,
91 FLOAT_ABI_SINGLE,
92 FLOAT_ABI_DOUBLE,
93 FLOAT_ABI_QUAD
94};
95static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
e23eba97 96
2922d21d 97#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
e23eba97
NC		 98#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
99
100static unsigned elf_flags = 0;
101
dcd709e0
NC		 102/* Set the default_isa_spec. Return 0 if the spec isn't supported.
103 Otherwise, return 1. */
8f595e9b
NC		 104
105static int
106riscv_set_default_isa_spec (const char *s)
107{
108 enum riscv_isa_spec_class class;
109 if (!riscv_get_isa_spec_class (s, &class))
110 {
b800637e
NC		 111 as_bad ("unknown default ISA spec `%s' set by "
112 "-misa-spec or --with-isa-spec", s);
8f595e9b
NC		 113 return 0;
114 }
115 else
116 default_isa_spec = class;
117 return 1;
118}
119
dcd709e0
NC		 120/* Set the default_priv_spec. Find the privileged elf attributes when
121 the input string is NULL. Return 0 if the spec isn't supported.
122 Otherwise, return 1. */
8f595e9b
NC		 123
124static int
125riscv_set_default_priv_spec (const char *s)
126{
127 enum riscv_priv_spec_class class;
128 unsigned major, minor, revision;
129 obj_attribute *attr;
8f595e9b 130
8f595e9b
NC		 131 if (riscv_get_priv_spec_class (s, &class))
132 {
133 default_priv_spec = class;
134 return 1;
135 }
136
137 if (s != NULL)
138 {
b800637e
NC		 139 as_bad (_("unknown default privileged spec `%s' set by "
140 "-mpriv-spec or --with-priv-spec"), s);
8f595e9b
NC		 141 return 0;
142 }
143
dcd709e0 144 /* Set the default_priv_spec by the privileged elf attributes. */
8f595e9b
NC		 145 attr = elf_known_obj_attributes_proc (stdoutput);
146 major = (unsigned) attr[Tag_RISCV_priv_spec].i;
147 minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
148 revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
39ff0b81
NC		 149 if (riscv_get_priv_spec_class_from_numbers (major,
150 minor,
151 revision,
152 &class))
8f595e9b 153 {
dcd709e0 154 /* 0.0.0 is meaningless. */
39ff0b81
NC		 155 if (class == PRIV_SPEC_CLASS_NONE)
156 return 1;
8f595e9b 157
8f595e9b 158 default_priv_spec = class;
8f595e9b
NC		 159 return 1;
160 }
161
dcd709e0 162 /* Still can not find the privileged spec class. */
b800637e
NC		 163 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
164 "privileged elf attributes"), major, minor, revision);
8f595e9b
NC		 165 return 0;
166}
167
e23eba97 168/* This is the set of options which the .option pseudo-op may modify. */
e23eba97
NC		 169struct riscv_set_options
170{
171 int pic; /* Generate position-independent code. */
172 int rvc; /* Generate RVC code. */
7f999549 173 int rve; /* Generate RVE code. */
45f76423 174 int relax; /* Emit relocs the linker is allowed to relax. */
dcd709e0 175 int arch_attr; /* Emit architecture and privileged elf attributes. */
2ca89224 176 int csr_check; /* Enable the CSR checking. */
e23eba97
NC		 177};
178
179static struct riscv_set_options riscv_opts =
180{
dcd709e0
NC		 181 0, /* pic */
182 0, /* rvc */
183 0, /* rve */
184 1, /* relax */
2dc8dd17 185 DEFAULT_RISCV_ATTR, /* arch_attr */
dcd709e0 186 0, /* csr_check */
e23eba97
NC		 187};
188
189static void
190riscv_set_rvc (bfd_boolean rvc_value)
191{
192 if (rvc_value)
193 elf_flags |= EF_RISCV_RVC;
194
195 riscv_opts.rvc = rvc_value;
196}
197
7f999549
JW		 198static void
199riscv_set_rve (bfd_boolean rve_value)
200{
201 riscv_opts.rve = rve_value;
202}
203
1080bf78 204static riscv_subset_list_t riscv_subsets;
e23eba97
NC		 205
206static bfd_boolean
1080bf78 207riscv_subset_supports (const char *feature)
e23eba97 208{
dfe92496
NC		 209 struct riscv_subset_t *subset;
210
1080bf78
JW		 211 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
212 return TRUE;
e23eba97 213
dfe92496 214 return riscv_lookup_subset (&riscv_subsets, feature, &subset);
e23eba97
NC		 215}
216
43135d3b 217static bfd_boolean
7e9ad3a3 218riscv_multi_subset_supports (enum riscv_insn_class insn_class)
43135d3b 219{
7e9ad3a3
JW		 220 switch (insn_class)
221 {
222 case INSN_CLASS_I: return riscv_subset_supports ("i");
223 case INSN_CLASS_C: return riscv_subset_supports ("c");
224 case INSN_CLASS_A: return riscv_subset_supports ("a");
225 case INSN_CLASS_M: return riscv_subset_supports ("m");
226 case INSN_CLASS_F: return riscv_subset_supports ("f");
227 case INSN_CLASS_D: return riscv_subset_supports ("d");
729a5353 228 case INSN_CLASS_Q: return riscv_subset_supports ("q");
7e9ad3a3
JW		 229
230 case INSN_CLASS_F_AND_C:
729a5353
NC		 231 return (riscv_subset_supports ("f")
232 && riscv_subset_supports ("c"));
233 case INSN_CLASS_D_AND_C:
234 return (riscv_subset_supports ("d")
235 && riscv_subset_supports ("c"));
43135d3b 236
729a5353
NC		 237 case INSN_CLASS_ZICSR:
238 return riscv_subset_supports ("zicsr");
239 case INSN_CLASS_ZIFENCEI:
240 return riscv_subset_supports ("zifencei");
aa881ecd
PT		 241 case INSN_CLASS_ZIHINTPAUSE:
242 return riscv_subset_supports ("zihintpause");
43135d3b 243
2652cfad
CXW		 244 case INSN_CLASS_ZBA:
245 return riscv_subset_supports ("zba");
246 case INSN_CLASS_ZBB:
247 return riscv_subset_supports ("zbb");
248 case INSN_CLASS_ZBC:
249 return riscv_subset_supports ("zbc");
250 case INSN_CLASS_ZBA_OR_ZBB:
251 return (riscv_subset_supports ("zba")
252 || riscv_subset_supports ("zbb"));
253
7e9ad3a3 254 default:
b800637e 255 as_fatal ("internal: unreachable");
7e9ad3a3
JW		 256 return FALSE;
257 }
43135d3b
JW		 258}
259
8f595e9b 260/* Handle of the extension with version hash table. */
629310ab 261static htab_t ext_version_hash = NULL;
8f595e9b 262
629310ab 263static htab_t
8f595e9b
NC		 264init_ext_version_hash (const struct riscv_ext_version *table)
265{
266 int i = 0;
629310ab 267 htab_t hash = str_htab_create ();
8f595e9b
NC		 268
269 while (table[i].name)
270 {
271 const char *name = table[i].name;
fe0e921f 272 if (str_hash_insert (hash, name, &table[i], 0) != NULL)
b800637e 273 as_fatal (_("internal: duplicate %s"), name);
8f595e9b
NC		 274
275 i++;
276 while (table[i].name
277 && strcmp (table[i].name, name) == 0)
278 i++;
279 }
280
281 return hash;
282}
283
284static void
285riscv_get_default_ext_version (const char *name,
7ef19aa6
NC		 286 int *major_version,
287 int *minor_version)
8f595e9b
NC		 288{
289 struct riscv_ext_version *ext;
290
8f595e9b
NC		 291 if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
292 return;
293
629310ab 294 ext = (struct riscv_ext_version *) str_hash_find (ext_version_hash, name);
8f595e9b 295 while (ext
7ef19aa6
NC		 296 && ext->name
297 && strcmp (ext->name, name) == 0)
8f595e9b 298 {
2652cfad
CXW		 299 if (ext->isa_spec_class == ISA_SPEC_CLASS_DRAFT
300 || ext->isa_spec_class == default_isa_spec)
7ef19aa6
NC		 301 {
302 *major_version = ext->major_version;
303 *minor_version = ext->minor_version;
304 return;
305 }
8f595e9b
NC		 306 ext++;
307 }
308}
309
2922d21d 310/* Set which ISA and extensions are available. */
e23eba97 311
e23eba97 312static void
2922d21d 313riscv_set_arch (const char *s)
e23eba97 314{
1080bf78
JW		 315 riscv_parse_subset_t rps;
316 rps.subset_list = &riscv_subsets;
7ef19aa6 317 rps.error_handler = as_bad;
1080bf78 318 rps.xlen = &xlen;
8f595e9b
NC		 319 rps.get_default_version = riscv_get_default_ext_version;
320
321 if (s == NULL)
322 return;
7f999549 323
1080bf78
JW		 324 riscv_release_subset_list (&riscv_subsets);
325 riscv_parse_subset (&rps, s);
e23eba97
NC		 326}
327
dcd709e0 328/* Indicate -mabi option is explictly set. */
6e1605e4
NC		 329static bfd_boolean explicit_mabi = FALSE;
330
331static void
332riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
333{
334 abi_xlen = new_xlen;
335 float_abi = new_float_abi;
336 rve_abi = rve;
337}
338
dcd709e0
NC		 339/* If the -mabi option isn't set, then set the abi according to the
340 ISA string. Otherwise, check if there is any conflict. */
6e1605e4
NC		 341
342static void
343riscv_set_abi_by_arch (void)
344{
345 if (!explicit_mabi)
346 {
347 if (riscv_subset_supports ("q"))
348 riscv_set_abi (xlen, FLOAT_ABI_QUAD, FALSE);
349 else if (riscv_subset_supports ("d"))
350 riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, FALSE);
351 else
352 riscv_set_abi (xlen, FLOAT_ABI_SOFT, FALSE);
353 }
354 else
355 {
356 gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT);
357 if (abi_xlen > xlen)
358 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
359 else if (abi_xlen < xlen)
360 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
361 }
362
363 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
364 elf_flags &= ~EF_RISCV_FLOAT_ABI;
365 elf_flags |= float_abi << 1;
366
367 if (rve_abi)
368 elf_flags |= EF_RISCV_RVE;
369}
370
e23eba97 371/* Handle of the OPCODE hash table. */
629310ab 372static htab_t op_hash = NULL;
e23eba97 373
0e35537d 374/* Handle of the type of .insn hash table. */
629310ab 375static htab_t insn_type_hash = NULL;
0e35537d 376
e23eba97 377/* This array holds the chars that always start a comment. If the
dcd709e0 378 pre-processor is disabled, these aren't very useful. */
e23eba97
NC		 379const char comment_chars[] = "#";
380
381/* This array holds the chars that only start a comment at the beginning of
382 a line. If the line seems to have the form '# 123 filename'
dcd709e0
NC		 383 .line and .file directives will appear in the pre-processed output
384
385 Note that input_file.c hand checks for '#' at the beginning of the
e23eba97 386 first line of the input file. This is because the compiler outputs
dcd709e0
NC		 387 #NO_APP at the beginning of its output.
388
389 Also note that C style comments are always supported. */
e23eba97
NC		 390const char line_comment_chars[] = "#";
391
392/* This array holds machine specific line separator characters. */
393const char line_separator_chars[] = ";";
394
dcd709e0 395/* Chars that can be used to separate mant from exp in floating point nums. */
e23eba97
NC		 396const char EXP_CHARS[] = "eE";
397
dcd709e0
NC		 398/* Chars that mean this number is a floating point constant.
399 As in 0f12.456 or 0d1.2345e12. */
e23eba97
NC		 400const char FLT_CHARS[] = "rRsSfFdDxXpP";
401
2dc8dd17
JW		 402/* Indicate we are already assemble any instructions or not. */
403static bfd_boolean start_assemble = FALSE;
404
f9a6a8f0 405/* Indicate ELF attributes are explicitly set. */
8f595e9b 406static bfd_boolean explicit_attr = FALSE;
2dc8dd17 407
f9a6a8f0 408/* Indicate CSR or priv instructions are explicitly used. */
1a79004f 409static bfd_boolean explicit_priv_attr = FALSE;
3fc6c3dc 410
e23eba97
NC		 411/* Macros for encoding relaxation state for RVC branches and far jumps. */
412#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
413 ((relax_substateT) \
414 (0xc0000000 \
415 | ((uncond) ? 1 : 0) \
416 | ((rvc) ? 2 : 0) \
417 | ((length) << 2)))
418#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
419#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
420#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
421#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
422
423/* Is the given value a sign-extended 32-bit value? */
424#define IS_SEXT_32BIT_NUM(x) \
425 (((x) &~ (offsetT) 0x7fffffff) == 0 \
426 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
427
428/* Is the given value a zero-extended 32-bit value? Or a negated one? */
429#define IS_ZEXT_32BIT_NUM(x) \
430 (((x) &~ (offsetT) 0xffffffff) == 0 \
431 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
432
433/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
434 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
435#define INSERT_OPERAND(FIELD, INSN, VALUE) \
436 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
437
438/* Determine if an instruction matches an opcode. */
439#define OPCODE_MATCHES(OPCODE, OP) \
440 (((OPCODE) & MASK_##OP) == MATCH_##OP)
441
442static char *expr_end;
443
444/* The default target format to use. */
445
446const char *
447riscv_target_format (void)
448{
fbc09e7a
MC		 449 if (target_big_endian)
450 return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv";
451 else
452 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
e23eba97
NC		 453}
454
455/* Return the length of instruction INSN. */
456
457static inline unsigned int
458insn_length (const struct riscv_cl_insn *insn)
459{
460 return riscv_insn_length (insn->insn_opcode);
461}
462
463/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
464
465static void
466create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
467{
468 insn->insn_mo = mo;
469 insn->insn_opcode = mo->match;
470 insn->frag = NULL;
471 insn->where = 0;
472 insn->fixp = NULL;
473}
474
475/* Install INSN at the location specified by its "frag" and "where" fields. */
476
477static void
478install_insn (const struct riscv_cl_insn *insn)
479{
480 char *f = insn->frag->fr_literal + insn->where;
fbc09e7a 481 number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn));
e23eba97
NC		 482}
483
484/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
485 and install the opcode in the new location. */
486
487static void
488move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
489{
490 insn->frag = frag;
491 insn->where = where;
492 if (insn->fixp != NULL)
493 {
494 insn->fixp->fx_frag = frag;
495 insn->fixp->fx_where = where;
496 }
497 install_insn (insn);
498}
499
500/* Add INSN to the end of the output. */
501
502static void
503add_fixed_insn (struct riscv_cl_insn *insn)
504{
505 char *f = frag_more (insn_length (insn));
506 move_insn (insn, frag_now, f - frag_now->fr_literal);
507}
508
509static void
510add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
511 relax_substateT subtype, symbolS *symbol, offsetT offset)
512{
513 frag_grow (max_chars);
514 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
515 frag_var (rs_machine_dependent, max_chars, var,
516 subtype, symbol, offset, NULL);
517}
518
519/* Compute the length of a branch sequence, and adjust the stored length
520 accordingly. If FRAGP is NULL, the worst-case length is returned. */
521
522static unsigned
523relaxed_branch_length (fragS *fragp, asection *sec, int update)
524{
525 int jump, rvc, length = 8;
526
527 if (!fragp)
528 return length;
529
530 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
531 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
532 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
533
534 /* Assume jumps are in range; the linker will catch any that aren't. */
535 length = jump ? 4 : 8;
536
537 if (fragp->fr_symbol != NULL
538 && S_IS_DEFINED (fragp->fr_symbol)
01156111 539 && !S_IS_WEAK (fragp->fr_symbol)
e23eba97
NC		 540 && sec == S_GET_SEGMENT (fragp->fr_symbol))
541 {
542 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
543 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
544 val -= fragp->fr_address + fragp->fr_fix;
545
546 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
547 length = 2;
548 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
549 length = 4;
550 else if (!jump && rvc)
551 length = 6;
552 }
553
554 if (update)
555 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
556
557 return length;
558}
559
0e35537d
JW		 560/* Information about an opcode name, mnemonics and its value. */
561struct opcode_name_t
562{
563 const char *name;
564 unsigned int val;
565};
566
567/* List for all supported opcode name. */
568static const struct opcode_name_t opcode_name_list[] =
569{
570 {"C0", 0x0},
571 {"C1", 0x1},
572 {"C2", 0x2},
573
574 {"LOAD", 0x03},
575 {"LOAD_FP", 0x07},
576 {"CUSTOM_0", 0x0b},
577 {"MISC_MEM", 0x0f},
578 {"OP_IMM", 0x13},
579 {"AUIPC", 0x17},
580 {"OP_IMM_32", 0x1b},
581 /* 48b 0x1f. */
582
583 {"STORE", 0x23},
584 {"STORE_FP", 0x27},
585 {"CUSTOM_1", 0x2b},
586 {"AMO", 0x2f},
587 {"OP", 0x33},
588 {"LUI", 0x37},
589 {"OP_32", 0x3b},
590 /* 64b 0x3f. */
591
592 {"MADD", 0x43},
593 {"MSUB", 0x47},
594 {"NMADD", 0x4f},
595 {"NMSUB", 0x4b},
596 {"OP_FP", 0x53},
597 /*reserved 0x57. */
598 {"CUSTOM_2", 0x5b},
599 /* 48b 0x5f. */
600
601 {"BRANCH", 0x63},
602 {"JALR", 0x67},
603 /*reserved 0x5b. */
604 {"JAL", 0x6f},
605 {"SYSTEM", 0x73},
606 /*reserved 0x77. */
607 {"CUSTOM_3", 0x7b},
608 /* >80b 0x7f. */
609
610 {NULL, 0}
611};
612
613/* Hash table for lookup opcode name. */
629310ab 614static htab_t opcode_names_hash = NULL;
0e35537d
JW		 615
616/* Initialization for hash table of opcode name. */
dcd709e0 617
0e35537d
JW		 618static void
619init_opcode_names_hash (void)
620{
0e35537d
JW		 621 const struct opcode_name_t *opcode;
622
623 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
fe0e921f 624 if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL)
b800637e 625 as_fatal (_("internal: duplicate %s"), opcode->name);
0e35537d
JW		 626}
627
dcd709e0
NC		 628/* Find `s` is a valid opcode name or not, return the opcode name info
629 if found. */
630
0e35537d
JW		 631static const struct opcode_name_t *
632opcode_name_lookup (char **s)
633{
634 char *e;
635 char save_c;
636 struct opcode_name_t *o;
637
638 /* Find end of name. */
639 e = *s;
640 if (is_name_beginner (*e))
641 ++e;
642 while (is_part_of_name (*e))
643 ++e;
644
645 /* Terminate name. */
646 save_c = *e;
647 *e = '\0';
648
629310ab 649 o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s);
0e35537d
JW		 650
651 /* Advance to next token if one was recognized. */
652 if (o)
653 *s = e;
654
655 *e = save_c;
656 expr_end = e;
657
658 return o;
659}
660
e23eba97
NC		 661enum reg_class
662{
663 RCLASS_GPR,
664 RCLASS_FPR,
8f595e9b
NC		 665 RCLASS_MAX,
666
667 RCLASS_CSR
e23eba97
NC		 668};
669
629310ab
ML		 670static htab_t reg_names_hash = NULL;
671static htab_t csr_extra_hash = NULL;
e23eba97
NC		 672
673#define ENCODE_REG_HASH(cls, n) \
674 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
675#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
676#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
677
678static void
679hash_reg_name (enum reg_class class, const char *name, unsigned n)
680{
681 void *hash = ENCODE_REG_HASH (class, n);
fe0e921f 682 if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL)
b800637e 683 as_fatal (_("internal: duplicate %s"), name);
e23eba97
NC		 684}
685
686static void
687hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
688{
689 unsigned i;
690
691 for (i = 0; i < n; i++)
692 hash_reg_name (class, names[i], i);
693}
694
8f595e9b 695/* Init hash table csr_extra_hash to handle CSR. */
dcd709e0 696
8f595e9b
NC		 697static void
698riscv_init_csr_hash (const char *name,
699 unsigned address,
700 enum riscv_csr_class class,
701 enum riscv_priv_spec_class define_version,
702 enum riscv_priv_spec_class abort_version)
703{
704 struct riscv_csr_extra *entry, *pre_entry;
8f595e9b
NC		 705 bfd_boolean need_enrty = TRUE;
706
707 pre_entry = NULL;
629310ab 708 entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
8f595e9b
NC		 709 while (need_enrty && entry != NULL)
710 {
711 if (entry->csr_class == class
712 && entry->address == address
713 && entry->define_version == define_version
714 && entry->abort_version == abort_version)
715 need_enrty = FALSE;
716 pre_entry = entry;
717 entry = entry->next;
718 }
719
dcd709e0 720 /* Duplicate CSR. */
8f595e9b
NC		 721 if (!need_enrty)
722 return;
bd0cf5a6 723
8f595e9b
NC		 724 entry = XNEW (struct riscv_csr_extra);
725 entry->csr_class = class;
726 entry->address = address;
727 entry->define_version = define_version;
728 entry->abort_version = abort_version;
5c505568 729 entry->next = NULL;
8f595e9b 730
8f595e9b 731 if (pre_entry == NULL)
fe0e921f 732 str_hash_insert (csr_extra_hash, name, entry, 0);
8f595e9b
NC		 733 else
734 pre_entry->next = entry;
735}
bd0cf5a6 736
dcd709e0
NC		 737/* Return the CSR address after checking the ISA dependency and
738 the privileged spec version.
739
740 There are one warning and two errors for CSR,
741
742 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
743 or the privileged spec, report warning only if -mcsr-check is set.
744 Unknown CSR: the CSR has never been defined, report error.
745 Improper CSR: the CSR number over the range (> 0xfff), report error. */
bd0cf5a6 746
08ccfccf
NC		 747static unsigned int
748riscv_csr_address (const char *csr_name,
749 struct riscv_csr_extra *entry)
bd0cf5a6 750{
08ccfccf
NC		 751 struct riscv_csr_extra *saved_entry = entry;
752 enum riscv_csr_class csr_class = entry->csr_class;
753 bfd_boolean need_check_version = TRUE;
8f595e9b
NC		 754 bfd_boolean result = TRUE;
755
8f595e9b 756 switch (csr_class)
bd0cf5a6 757 {
8f595e9b
NC		 758 case CSR_CLASS_I:
759 result = riscv_subset_supports ("i");
760 break;
08ccfccf
NC		 761 case CSR_CLASS_I_32:
762 result = (xlen == 32 && riscv_subset_supports ("i"));
763 break;
8f595e9b
NC		 764 case CSR_CLASS_F:
765 result = riscv_subset_supports ("f");
08ccfccf 766 need_check_version = FALSE;
8f595e9b 767 break;
08ccfccf
NC		 768 case CSR_CLASS_DEBUG:
769 need_check_version = FALSE;
8f595e9b
NC		 770 break;
771 default:
772 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
bd0cf5a6
NC		 773 }
774
08ccfccf 775 if (riscv_opts.csr_check && !result)
b800637e 776 as_warn (_("invalid CSR `%s' for the current ISA"), csr_name);
8f595e9b
NC		 777
778 while (entry != NULL)
bd0cf5a6 779 {
08ccfccf
NC		 780 if (!need_check_version
781 || (default_priv_spec >= entry->define_version
782 && default_priv_spec < entry->abort_version))
8f595e9b 783 {
dcd709e0 784 /* Find the CSR according to the specific version. */
08ccfccf 785 return entry->address;
8f595e9b
NC		 786 }
787 entry = entry->next;
788 }
bd0cf5a6 789
dcd709e0
NC		 790 /* Can not find the CSR address from the chosen privileged version,
791 so use the newly defined value. */
8f595e9b
NC		 792 if (riscv_opts.csr_check)
793 {
794 const char *priv_name = riscv_get_priv_spec_name (default_priv_spec);
795
796 if (priv_name != NULL)
b800637e 797 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
8f595e9b 798 csr_name, priv_name);
bd0cf5a6 799 }
08ccfccf
NC		 800
801 return saved_entry->address;
bd0cf5a6
NC		 802}
803
dcd709e0
NC		 804/* Return -1 if the CSR has never been defined. Otherwise, return
805 the address. */
bd0cf5a6 806
8f595e9b 807static unsigned int
bd0cf5a6
NC		 808reg_csr_lookup_internal (const char *s)
809{
810 struct riscv_csr_extra *r =
629310ab 811 (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s);
bd0cf5a6
NC		 812
813 if (r == NULL)
8f595e9b 814 return -1U;
bd0cf5a6 815
08ccfccf 816 return riscv_csr_address (s, r);
bd0cf5a6
NC		 817}
818
e23eba97
NC		 819static unsigned int
820reg_lookup_internal (const char *s, enum reg_class class)
821{
8f595e9b
NC		 822 void *r;
823
824 if (class == RCLASS_CSR)
825 return reg_csr_lookup_internal (s);
e23eba97 826
629310ab 827 r = str_hash_find (reg_names_hash, s);
e23eba97
NC		 828 if (r == NULL || DECODE_REG_CLASS (r) != class)
829 return -1;
7f999549
JW		 830
831 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
832 return -1;
833
e23eba97
NC		 834 return DECODE_REG_NUM (r);
835}
836
837static bfd_boolean
838reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
839{
840 char *e;
841 char save_c;
842 int reg = -1;
843
844 /* Find end of name. */
845 e = *s;
846 if (is_name_beginner (*e))
847 ++e;
848 while (is_part_of_name (*e))
849 ++e;
850
851 /* Terminate name. */
852 save_c = *e;
853 *e = '\0';
854
855 /* Look for the register. Advance to next token if one was recognized. */
856 if ((reg = reg_lookup_internal (*s, class)) >= 0)
857 *s = e;
858
859 *e = save_c;
860 if (regnop)
861 *regnop = reg;
862 return reg >= 0;
863}
864
865static bfd_boolean
866arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
867{
868 const char *p = strchr (*s, ',');
869 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
870
bfb218e3
JW		 871 if (len == 0)
872 return FALSE;
873
e23eba97
NC		 874 for (i = 0; i < size; i++)
875 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
876 {
877 *regnop = i;
878 *s += len;
879 return TRUE;
880 }
881
882 return FALSE;
883}
884
885/* For consistency checking, verify that all bits are specified either
886 by the match/mask part of the instruction definition, or by the
dcd709e0 887 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
0e35537d 888
e23eba97 889static bfd_boolean
0e35537d 890validate_riscv_insn (const struct riscv_opcode *opc, int length)
e23eba97
NC		 891{
892 const char *p = opc->args;
893 char c;
894 insn_t used_bits = opc->mask;
0e35537d
JW		 895 int insn_width;
896 insn_t required_bits;
897
898 if (length == 0)
899 insn_width = 8 * riscv_insn_length (opc->match);
900 else
901 insn_width = 8 * length;
902
903 required_bits = ~0ULL >> (64 - insn_width);
e23eba97
NC		 904
905 if ((used_bits & opc->match) != (opc->match & required_bits))
906 {
907 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
908 opc->name, opc->args);
909 return FALSE;
910 }
911
912#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
913 while (*p)
914 switch (c = *p++)
915 {
916 case 'C': /* RVC */
917 switch (c = *p++)
918 {
1d65abb5 919 case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
dcd709e0 920 case 'c': break; /* RS1, constrained to equal sp. */
e23eba97 921 case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
1d65abb5 922 case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
b416fe87 923 case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
1d65abb5
AW		 924 case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
925 case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
926 case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
927 case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
928 case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
e23eba97
NC		 929 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
930 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
1d65abb5
AW		 931 case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
932 case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
dcd709e0
NC		 933 case 'w': break; /* RS1S, constrained to equal RD. */
934 case 'x': break; /* RS2S, constrained to equal RD. */
935 case 'z': break; /* RS2S, constrained to be x0. */
1d65abb5
AW		 936 case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
937 case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
938 case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
939 case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
dcd709e0 940 case 'U': break; /* RS1, constrained to equal RD. */
e23eba97 941 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1d65abb5
AW		 942 case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
943 case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
0e35537d
JW		 944 case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
945 case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
e23eba97
NC		 946 case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
947 case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
dcd709e0 948 case 'F': /* RVC funct for .insn directive. */
0e35537d
JW		 949 switch (c = *p++)
950 {
4765cd61 951 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
0e35537d
JW		 952 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
953 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
4765cd61 954 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
0e35537d 955 default:
b800637e
NC		 956 as_bad (_("internal: bad RISC-V opcode "
957 "(unknown operand type `CF%c'): %s %s"),
0e35537d
JW		 958 c, opc->name, opc->args);
959 return FALSE;
960 }
961 break;
e23eba97 962 default:
b800637e
NC		 963 as_bad (_("internal: bad RISC-V opcode "
964 "(unknown operand type `C%c'): %s %s"),
e23eba97
NC		 965 c, opc->name, opc->args);
966 return FALSE;
967 }
968 break;
969 case ',': break;
970 case '(': break;
971 case ')': break;
972 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
973 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
974 case 'A': break;
975 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
976 case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
977 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
978 case 'I': break;
979 case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
980 case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
dcd709e0
NC		 981 case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1);
982 /* Fall through. */
e23eba97
NC		 983 case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
984 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
985 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
986 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
987 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
0e35537d 988 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
e23eba97
NC		 989 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
990 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
991 case 'o':
1d65abb5
AW		 992 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
993 case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
994 case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
995 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
996 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
e925c834 997 case 'z': break;
e23eba97
NC		 998 case '[': break;
999 case ']': break;
1000 case '0': break;
f50fabe4 1001 case '1': break;
dcd709e0 1002 case 'F': /* Funct for .insn directive. */
0e35537d
JW		 1003 switch (c = *p++)
1004 {
1005 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
1006 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
1007 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
1008 default:
b800637e
NC		 1009 as_bad (_("internal: bad RISC-V opcode "
1010 "(unknown operand type `F%c'): %s %s"),
0e35537d
JW		 1011 c, opc->name, opc->args);
1012 return FALSE;
1013 }
1014 break;
dcd709e0 1015 case 'O': /* Opcode for .insn directive. */
0e35537d
JW		 1016 switch (c = *p++)
1017 {
1018 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
1019 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
1020 default:
b800637e
NC		 1021 as_bad (_("internal: bad RISC-V opcode "
1022 "(unknown operand type `F%c'): %s %s"),
0e35537d
JW		 1023 c, opc->name, opc->args);
1024 return FALSE;
1025 }
1026 break;
e23eba97
NC		 1027 default:
1028 as_bad (_("internal: bad RISC-V opcode "
1029 "(unknown operand type `%c'): %s %s"),
1030 c, opc->name, opc->args);
1031 return FALSE;
1032 }
1033#undef USE_BITS
1034 if (used_bits != required_bits)
1035 {
b800637e
NC		 1036 as_bad (_("internal: bad RISC-V opcode "
1037 "(bits 0x%lx undefined): %s %s"),
e23eba97
NC		 1038 ~(unsigned long)(used_bits & required_bits),
1039 opc->name, opc->args);
1040 return FALSE;
1041 }
1042 return TRUE;
1043}
1044
1045struct percent_op_match
1046{
1047 const char *str;
1048 bfd_reloc_code_real_type reloc;
1049};
1050
dcd709e0
NC		 1051/* Common hash table initialization function for instruction and .insn
1052 directive. */
1053
629310ab 1054static htab_t
0e35537d
JW		 1055init_opcode_hash (const struct riscv_opcode *opcodes,
1056 bfd_boolean insn_directive_p)
e23eba97
NC		 1057{
1058 int i = 0;
0e35537d 1059 int length;
629310ab 1060 htab_t hash = str_htab_create ();
0e35537d 1061 while (opcodes[i].name)
e23eba97 1062 {
0e35537d 1063 const char *name = opcodes[i].name;
fe0e921f 1064 if (str_hash_insert (hash, name, &opcodes[i], 0) != NULL)
b800637e 1065 as_fatal (_("internal: duplicate %s"), name);
e23eba97
NC		 1066
1067 do
1068 {
0e35537d 1069 if (opcodes[i].pinfo != INSN_MACRO)
e23eba97 1070 {
0e35537d
JW		 1071 if (insn_directive_p)
1072 length = ((name[0] == 'c') ? 2 : 4);
1073 else
dcd709e0 1074 length = 0; /* Let assembler determine the length. */
0e35537d 1075 if (!validate_riscv_insn (&opcodes[i], length))
b800637e
NC		 1076 as_fatal (_("internal: broken assembler. "
1077 "No assembly attempted"));
e23eba97 1078 }
0e35537d
JW		 1079 else
1080 gas_assert (!insn_directive_p);
e23eba97
NC		 1081 ++i;
1082 }
0e35537d 1083 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
e23eba97
NC		 1084 }
1085
0e35537d
JW		 1086 return hash;
1087}
1088
1089/* This function is called once, at assembler startup time. It should set up
1090 all the tables, etc. that the MD part of the assembler will need. */
1091
1092void
1093md_begin (void)
1094{
1095 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
1096
1097 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
b800637e 1098 as_warn (_("could not set architecture and machine"));
0e35537d
JW		 1099
1100 op_hash = init_opcode_hash (riscv_opcodes, FALSE);
1101 insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
1102
629310ab 1103 reg_names_hash = str_htab_create ();
e23eba97
NC		 1104 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
1105 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
1106 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
1107 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
b9c04e5a
JW		 1108 /* Add "fp" as an alias for "s0". */
1109 hash_reg_name (RCLASS_GPR, "fp", 8);
1110
bd0cf5a6 1111 /* Create and insert CSR hash tables. */
629310ab 1112 csr_extra_hash = str_htab_create ();
8f595e9b
NC		 1113#define DECLARE_CSR(name, num, class, define_version, abort_version) \
1114 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1115#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1116 DECLARE_CSR(name, num, class, define_version, abort_version);
e23eba97
NC		 1117#include "opcode/riscv-opc.h"
1118#undef DECLARE_CSR
1119
629310ab 1120 opcode_names_hash = str_htab_create ();
bd0cf5a6
NC		 1121 init_opcode_names_hash ();
1122
e23eba97
NC		 1123 /* Set the default alignment for the text section. */
1124 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
1125}
1126
45f76423
AW		 1127static insn_t
1128riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
1129{
1130 switch (reloc_type)
1131 {
1132 case BFD_RELOC_32:
1133 return value;
1134
1135 case BFD_RELOC_RISCV_HI20:
1136 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
1137
1138 case BFD_RELOC_RISCV_LO12_S:
1139 return ENCODE_STYPE_IMM (value);
1140
1141 case BFD_RELOC_RISCV_LO12_I:
1142 return ENCODE_ITYPE_IMM (value);
1143
1144 default:
1145 abort ();
1146 }
1147}
1148
e23eba97
NC		 1149/* Output an instruction. IP is the instruction information.
1150 ADDRESS_EXPR is an operand of the instruction to be used with
1151 RELOC_TYPE. */
1152
1153static void
1154append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
1155 bfd_reloc_code_real_type reloc_type)
1156{
1157 dwarf2_emit_insn (0);
1158
1159 if (reloc_type != BFD_RELOC_UNUSED)
1160 {
1161 reloc_howto_type *howto;
1162
1d65abb5 1163 gas_assert (address_expr);
e23eba97
NC		 1164 if (reloc_type == BFD_RELOC_12_PCREL
1165 || reloc_type == BFD_RELOC_RISCV_JMP)
1166 {
1167 int j = reloc_type == BFD_RELOC_RISCV_JMP;
1168 int best_case = riscv_insn_length (ip->insn_opcode);
1169 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
743f5cfc
JW		 1170
1171 if (now_seg == absolute_section)
1172 {
1173 as_bad (_("relaxable branches not supported in absolute section"));
1174 return;
1175 }
1176
e23eba97
NC		 1177 add_relaxed_insn (ip, worst_case, best_case,
1178 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
1179 address_expr->X_add_symbol,
1180 address_expr->X_add_number);
1181 return;
1182 }
45f76423 1183 else
e23eba97 1184 {
45f76423
AW		 1185 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
1186 if (howto == NULL)
b800637e
NC		 1187 as_bad (_("internal: usupported RISC-V relocation number %d"),
1188 reloc_type);
e23eba97 1189
45f76423
AW		 1190 ip->fixp = fix_new_exp (ip->frag, ip->where,
1191 bfd_get_reloc_size (howto),
1192 address_expr, FALSE, reloc_type);
e23eba97 1193
45f76423 1194 ip->fixp->fx_tcbit = riscv_opts.relax;
e23eba97 1195 }
e23eba97
NC		 1196 }
1197
e23eba97
NC		 1198 add_fixed_insn (ip);
1199 install_insn (ip);
f77bb6c5
JW		 1200
1201 /* We need to start a new frag after any instruction that can be
1202 optimized away or compressed by the linker during relaxation, to prevent
1203 the assembler from computing static offsets across such an instruction.
1204 This is necessary to get correct EH info. */
b1b11e92 1205 if (reloc_type == BFD_RELOC_RISCV_HI20
f77bb6c5
JW		 1206 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
1207 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
1208 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
1209 {
1210 frag_wane (frag_now);
1211 frag_new (0);
1212 }
e23eba97
NC		 1213}
1214
1215/* Build an instruction created by a macro expansion. This is passed
dcd709e0
NC		 1216 a pointer to the count of instructions created so far, an expression,
1217 the name of the instruction to build, an operand format string, and
1218 corresponding arguments. */
e23eba97
NC		 1219
1220static void
1221macro_build (expressionS *ep, const char *name, const char *fmt, ...)
1222{
1223 const struct riscv_opcode *mo;
1224 struct riscv_cl_insn insn;
1225 bfd_reloc_code_real_type r;
1226 va_list args;
1227
1228 va_start (args, fmt);
1229
1230 r = BFD_RELOC_UNUSED;
629310ab 1231 mo = (struct riscv_opcode *) str_hash_find (op_hash, name);
e23eba97
NC		 1232 gas_assert (mo);
1233
1234 /* Find a non-RVC variant of the instruction. append_insn will compress
1235 it if possible. */
1236 while (riscv_insn_length (mo->match) < 4)
1237 mo++;
1238 gas_assert (strcmp (name, mo->name) == 0);
1239
1240 create_insn (&insn, mo);
1241 for (;;)
1242 {
1243 switch (*fmt++)
1244 {
1245 case 'd':
1246 INSERT_OPERAND (RD, insn, va_arg (args, int));
1247 continue;
1248
1249 case 's':
1250 INSERT_OPERAND (RS1, insn, va_arg (args, int));
1251 continue;
1252
1253 case 't':
1254 INSERT_OPERAND (RS2, insn, va_arg (args, int));
1255 continue;
1256
1257 case '>':
1258 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
1259 continue;
1260
1261 case 'j':
1262 case 'u':
1263 case 'q':
1264 gas_assert (ep != NULL);
1265 r = va_arg (args, int);
1266 continue;
1267
1268 case '\0':
1269 break;
1270 case ',':
1271 continue;
1272 default:
b800637e 1273 as_fatal (_("internal: invalid macro"));
e23eba97
NC		 1274 }
1275 break;
1276 }
1277 va_end (args);
1278 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1279
1280 append_insn (&insn, ep, r);
1281}
1282
db3b6ecc
KC		 1283/* Build an instruction created by a macro expansion. Like md_assemble but
1284 accept a printf-style format string and arguments. */
1285
1286static void
1287md_assemblef (const char *format, ...)
1288{
1289 char *buf = NULL;
1290 va_list ap;
1291 int r;
1292
1293 va_start (ap, format);
1294
1295 r = vasprintf (&buf, format, ap);
1296
1297 if (r < 0)
b800637e 1298 as_fatal (_("internal: vasprintf failed"));
db3b6ecc
KC		 1299
1300 md_assemble (buf);
1301 free(buf);
1302
1303 va_end (ap);
1304}
1305
e23eba97
NC		 1306/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1307 unset. */
dcd709e0 1308
e23eba97
NC		 1309static void
1310normalize_constant_expr (expressionS *ex)
1311{
1312 if (xlen > 32)
1313 return;
1314 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1315 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1316 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1317 - 0x80000000);
1318}
1319
ca2fd32c
JW		 1320/* Fail if an expression EX is not a constant. IP is the instruction using EX.
1321 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
e23eba97
NC		 1322
1323static void
ca2fd32c
JW		 1324check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
1325 bfd_boolean maybe_csr)
e23eba97
NC		 1326{
1327 if (ex->X_op == O_big)
1328 as_bad (_("unsupported large constant"));
ca2fd32c
JW		 1329 else if (maybe_csr && ex->X_op == O_symbol)
1330 as_bad (_("unknown CSR `%s'"),
1331 S_GET_NAME (ex->X_add_symbol));
e23eba97 1332 else if (ex->X_op != O_constant)
b800637e 1333 as_bad (_("instruction %s requires absolute expression"),
e23eba97
NC		 1334 ip->insn_mo->name);
1335 normalize_constant_expr (ex);
1336}
1337
1338static symbolS *
1339make_internal_label (void)
1340{
e01e1cee
AM		 1341 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now,
1342 frag_now_fix ());
e23eba97
NC		 1343}
1344
1345/* Load an entry from the GOT. */
dcd709e0 1346
e23eba97
NC		 1347static void
1348pcrel_access (int destreg, int tempreg, expressionS *ep,
1349 const char *lo_insn, const char *lo_pattern,
1350 bfd_reloc_code_real_type hi_reloc,
1351 bfd_reloc_code_real_type lo_reloc)
1352{
1353 expressionS ep2;
1354 ep2.X_op = O_symbol;
1355 ep2.X_add_symbol = make_internal_label ();
1356 ep2.X_add_number = 0;
1357
1358 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1359 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1360}
1361
1362static void
1363pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1364 bfd_reloc_code_real_type hi_reloc,
1365 bfd_reloc_code_real_type lo_reloc)
1366{
1367 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1368}
1369
1370static void
1371pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1372 bfd_reloc_code_real_type hi_reloc,
1373 bfd_reloc_code_real_type lo_reloc)
1374{
1375 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1376}
1377
1378/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
dcd709e0 1379
e23eba97
NC		 1380static void
1381riscv_call (int destreg, int tempreg, expressionS *ep,
1382 bfd_reloc_code_real_type reloc)
1383{
b1b11e92
AM		 1384 /* Ensure the jalr is emitted to the same frag as the auipc. */
1385 frag_grow (8);
e23eba97
NC		 1386 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1387 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
b1b11e92
AM		 1388 /* See comment at end of append_insn. */
1389 frag_wane (frag_now);
1390 frag_new (0);
e23eba97
NC		 1391}
1392
1393/* Load an integer constant into a register. */
1394
1395static void
1396load_const (int reg, expressionS *ep)
1397{
1398 int shift = RISCV_IMM_BITS;
4f7cc141 1399 bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1);
e23eba97 1400 expressionS upper = *ep, lower = *ep;
4f7cc141 1401 lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign;
e23eba97
NC		 1402 upper.X_add_number -= lower.X_add_number;
1403
1404 if (ep->X_op != O_constant)
1405 {
1406 as_bad (_("unsupported large constant"));
1407 return;
1408 }
1409
1d65abb5 1410 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
e23eba97
NC		 1411 {
1412 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1413 while (((upper.X_add_number >> shift) & 1) == 0)
1414 shift++;
1415
1416 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1d65abb5 1417 load_const (reg, &upper);
e23eba97 1418
db3b6ecc 1419 md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift);
e23eba97 1420 if (lower.X_add_number != 0)
db3b6ecc
KC		 1421 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg,
1422 lower.X_add_number);
e23eba97
NC		 1423 }
1424 else
1425 {
1426 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1427 int hi_reg = 0;
1428
1429 if (upper.X_add_number != 0)
1430 {
db3b6ecc
KC		 1431 /* Discard low part and zero-extend upper immediate. */
1432 upper_imm = ((uint32_t)upper.X_add_number >> shift);
1433
1434 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm);
e23eba97
NC		 1435 hi_reg = reg;
1436 }
1437
1438 if (lower.X_add_number != 0 || hi_reg == 0)
db3b6ecc
KC		 1439 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg,
1440 lower.X_add_number);
e23eba97
NC		 1441 }
1442}
1443
c2137f55
NC		 1444/* Zero extend and sign extend byte/half-word/word. */
1445
1446static void
1447riscv_ext (int destreg, int srcreg, unsigned shift, bfd_boolean sign)
1448{
1449 if (sign)
1450 {
1451 md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
1452 md_assemblef ("srai x%d, x%d, 0x%x", destreg, destreg, shift);
1453 }
1454 else
1455 {
1456 md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
1457 md_assemblef ("srli x%d, x%d, 0x%x", destreg, destreg, shift);
1458 }
1459}
1460
e23eba97 1461/* Expand RISC-V assembly macros into one or more instructions. */
2652cfad 1462
e23eba97
NC		 1463static void
1464macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1465 bfd_reloc_code_real_type *imm_reloc)
1466{
1467 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1468 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1469 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1470 int mask = ip->insn_mo->mask;
1471
1472 switch (mask)
1473 {
1474 case M_LI:
1475 load_const (rd, imm_expr);
1476 break;
1477
1478 case M_LA:
1479 case M_LLA:
1480 /* Load the address of a symbol into a register. */
1481 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1482 as_bad (_("offset too large"));
1483
1484 if (imm_expr->X_op == O_constant)
1485 load_const (rd, imm_expr);
dcd709e0 1486 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol. */
e23eba97
NC		 1487 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1488 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
dcd709e0 1489 else /* Local PIC symbol, or any non-PIC symbol. */
e23eba97
NC		 1490 pcrel_load (rd, rd, imm_expr, "addi",
1491 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1492 break;
1493
1494 case M_LA_TLS_GD:
1495 pcrel_load (rd, rd, imm_expr, "addi",
1496 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1497 break;
1498
1499 case M_LA_TLS_IE:
1500 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1501 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1502 break;
1503
1504 case M_LB:
1505 pcrel_load (rd, rd, imm_expr, "lb",
1506 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1507 break;
1508
1509 case M_LBU:
1510 pcrel_load (rd, rd, imm_expr, "lbu",
1511 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1512 break;
1513
1514 case M_LH:
1515 pcrel_load (rd, rd, imm_expr, "lh",
1516 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1517 break;
1518
1519 case M_LHU:
1520 pcrel_load (rd, rd, imm_expr, "lhu",
1521 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1522 break;
1523
1524 case M_LW:
1525 pcrel_load (rd, rd, imm_expr, "lw",
1526 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1527 break;
1528
1529 case M_LWU:
1530 pcrel_load (rd, rd, imm_expr, "lwu",
1531 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1532 break;
1533
1534 case M_LD:
1535 pcrel_load (rd, rd, imm_expr, "ld",
1536 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1537 break;
1538
1539 case M_FLW:
1540 pcrel_load (rd, rs1, imm_expr, "flw",
1541 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1542 break;
1543
1544 case M_FLD:
1545 pcrel_load (rd, rs1, imm_expr, "fld",
1546 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1547 break;
1548
1549 case M_SB:
1550 pcrel_store (rs2, rs1, imm_expr, "sb",
1551 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1552 break;
1553
1554 case M_SH:
1555 pcrel_store (rs2, rs1, imm_expr, "sh",
1556 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1557 break;
1558
1559 case M_SW:
1560 pcrel_store (rs2, rs1, imm_expr, "sw",
1561 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1562 break;
1563
1564 case M_SD:
1565 pcrel_store (rs2, rs1, imm_expr, "sd",
1566 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1567 break;
1568
1569 case M_FSW:
1570 pcrel_store (rs2, rs1, imm_expr, "fsw",
1571 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1572 break;
1573
1574 case M_FSD:
1575 pcrel_store (rs2, rs1, imm_expr, "fsd",
1576 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1577 break;
1578
1579 case M_CALL:
1580 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1581 break;
1582
c2137f55
NC		 1583 case M_ZEXTH:
1584 riscv_ext (rd, rs1, xlen - 16, FALSE);
1585 break;
1586
1587 case M_ZEXTW:
1588 riscv_ext (rd, rs1, xlen - 32, FALSE);
1589 break;
1590
1591 case M_SEXTB:
1592 riscv_ext (rd, rs1, xlen - 8, TRUE);
1593 break;
1594
1595 case M_SEXTH:
1596 riscv_ext (rd, rs1, xlen - 16, TRUE);
1597 break;
1598
e23eba97 1599 default:
b800637e 1600 as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name);
e23eba97
NC		 1601 break;
1602 }
1603}
1604
1605static const struct percent_op_match percent_op_utype[] =
1606{
1607 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1608 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
dee35d02 1609 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
e23eba97
NC		 1610 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1611 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1612 {"%hi", BFD_RELOC_RISCV_HI20},
1613 {0, 0}
1614};
1615
1616static const struct percent_op_match percent_op_itype[] =
1617{
1618 {"%lo", BFD_RELOC_RISCV_LO12_I},
1619 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1620 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1621 {0, 0}
1622};
1623
1624static const struct percent_op_match percent_op_stype[] =
1625{
1626 {"%lo", BFD_RELOC_RISCV_LO12_S},
1627 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1628 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1629 {0, 0}
1630};
1631
1632static const struct percent_op_match percent_op_rtype[] =
1633{
1634 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1635 {0, 0}
1636};
1637
f50fabe4
JW		 1638static const struct percent_op_match percent_op_null[] =
1639{
1640 {0, 0}
1641};
1642
e23eba97
NC		 1643/* Return true if *STR points to a relocation operator. When returning true,
1644 move *STR over the operator and store its relocation code in *RELOC.
1645 Leave both *STR and *RELOC alone when returning false. */
1646
1647static bfd_boolean
1648parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1649 const struct percent_op_match *percent_op)
1650{
1651 for ( ; percent_op->str; percent_op++)
1652 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1653 {
1654 int len = strlen (percent_op->str);
1655
1656 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1657 continue;
1658
1659 *str += strlen (percent_op->str);
1660 *reloc = percent_op->reloc;
1661
1662 /* Check whether the output BFD supports this relocation.
1663 If not, issue an error and fall back on something safe. */
45f76423
AW		 1664 if (*reloc != BFD_RELOC_UNUSED
1665 && !bfd_reloc_type_lookup (stdoutput, *reloc))
e23eba97 1666 {
b800637e
NC		 1667 as_bad ("internal: relocation %s isn't supported by the "
1668 "current ABI", percent_op->str);
e23eba97
NC		 1669 *reloc = BFD_RELOC_UNUSED;
1670 }
1671 return TRUE;
1672 }
1673 return FALSE;
1674}
1675
1676static void
1677my_getExpression (expressionS *ep, char *str)
1678{
1679 char *save_in;
1680
1681 save_in = input_line_pointer;
1682 input_line_pointer = str;
1683 expression (ep);
1684 expr_end = input_line_pointer;
1685 input_line_pointer = save_in;
1686}
1687
1688/* Parse string STR as a 16-bit relocatable operand. Store the
1689 expression in *EP and the relocation, if any, in RELOC.
1690 Return the number of relocation operators used (0 or 1).
1691
1692 On exit, EXPR_END points to the first character after the expression. */
1693
1694static size_t
1695my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1696 char *str, const struct percent_op_match *percent_op)
1697{
1698 size_t reloc_index;
1699 unsigned crux_depth, str_depth, regno;
1700 char *crux;
1701
8970c022
JW		 1702 /* First, check for integer registers. No callers can accept a reg, but
1703 we need to avoid accidentally creating a useless undefined symbol below,
1704 if this is an instruction pattern that can't match. A glibc build fails
1705 if this is removed. */
e23eba97
NC		 1706 if (reg_lookup (&str, RCLASS_GPR, &regno))
1707 {
1708 ep->X_op = O_register;
1709 ep->X_add_number = regno;
8970c022 1710 expr_end = str;
e23eba97
NC		 1711 return 0;
1712 }
1713
1714 /* Search for the start of the main expression.
dcd709e0
NC		 1715
1716 End the loop with CRUX pointing to the start of the main expression and
1717 with CRUX_DEPTH containing the number of open brackets at that point. */
e23eba97
NC		 1718 reloc_index = -1;
1719 str_depth = 0;
1720 do
1721 {
1722 reloc_index++;
1723 crux = str;
1724 crux_depth = str_depth;
1725
1726 /* Skip over whitespace and brackets, keeping count of the number
1727 of brackets. */
1728 while (*str == ' ' || *str == '\t' || *str == '(')
1729 if (*str++ == '(')
1730 str_depth++;
1731 }
1732 while (*str == '%'
1733 && reloc_index < 1
1734 && parse_relocation (&str, reloc, percent_op));
1735
1736 my_getExpression (ep, crux);
1737 str = expr_end;
1738
1739 /* Match every open bracket. */
1740 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1741 if (*str++ == ')')
1742 crux_depth--;
1743
1744 if (crux_depth > 0)
1745 as_bad ("unclosed '('");
1746
1747 expr_end = str;
1748
1749 return reloc_index;
1750}
1751
0e35537d 1752/* Parse opcode name, could be an mnemonics or number. */
dcd709e0 1753
0e35537d
JW		 1754static size_t
1755my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1756 char *str, const struct percent_op_match *percent_op)
1757{
1758 const struct opcode_name_t *o = opcode_name_lookup (&str);
1759
1760 if (o != NULL)
1761 {
1762 ep->X_op = O_constant;
1763 ep->X_add_number = o->val;
1764 return 0;
1765 }
1766
1767 return my_getSmallExpression (ep, reloc, str, percent_op);
1768}
1769
f0531ed6
JW		 1770/* Detect and handle implicitly zero load-store offsets. For example,
1771 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1772 an implicit offset was detected. */
1773
1774static bfd_boolean
89424b1d 1775riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
f0531ed6
JW		 1776{
1777 /* Check whether there is only a single bracketed expression left.
1778 If so, it must be the base register and the constant must be zero. */
1779 if (*s == '(' && strchr (s + 1, '(') == 0)
1780 {
89424b1d
MR		 1781 ep->X_op = O_constant;
1782 ep->X_add_number = 0;
f0531ed6
JW		 1783 return TRUE;
1784 }
1785
1786 return FALSE;
1787}
1788
54b2aec1 1789/* All RISC-V CSR instructions belong to one of these classes. */
54b2aec1
NC		 1790enum csr_insn_type
1791{
1792 INSN_NOT_CSR,
1793 INSN_CSRRW,
1794 INSN_CSRRS,
1795 INSN_CSRRC
1796};
1797
1798/* Return which CSR instruction is checking. */
1799
1800static enum csr_insn_type
1801riscv_csr_insn_type (insn_t insn)
1802{
1803 if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
1804 || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
1805 return INSN_CSRRW;
1806 else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
1807 || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
1808 return INSN_CSRRS;
1809 else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
1810 || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
1811 return INSN_CSRRC;
1812 else
1813 return INSN_NOT_CSR;
1814}
1815
1816/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1817 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1818 CSR address is 0x3. */
1819
1820static bfd_boolean
1821riscv_csr_read_only_check (insn_t insn)
1822{
1823 int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
1824 int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
1825 int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
1826 enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
1827
1828 if (readonly
1829 && (((csr_insn == INSN_CSRRS
1830 || csr_insn == INSN_CSRRC)
1831 && rs1 != 0)
1832 || csr_insn == INSN_CSRRW))
1833 return FALSE;
1834
1835 return TRUE;
1836}
1837
1a79004f
NC		 1838/* Return True if it is a privileged instruction. Otherwise, return FALSE.
1839
1840 uret is actually a N-ext instruction. So it is better to regard it as
1841 an user instruction rather than the priv instruction.
1842
1843 hret is used to return from traps in H-mode. H-mode is removed since
1844 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1845 Therefore, hret should be controlled by the hypervisor spec rather than
1846 priv spec in the future.
1847
1848 dret is defined in the debug spec, so it should be checked in the future,
1849 too. */
1850
1851static bfd_boolean
1852riscv_is_priv_insn (insn_t insn)
1853{
1854 return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
1855 || ((insn ^ MATCH_MRET) & MASK_MRET) == 0
1856 || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0
1857 || ((insn ^ MATCH_WFI) & MASK_WFI) == 0
1858 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
dcd709e0 1859 check it here to keep the compatible. */
1a79004f
NC		 1860 || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
1861}
1862
e23eba97
NC		 1863/* This routine assembles an instruction into its binary format. As a
1864 side effect, it sets the global variable imm_reloc to the type of
1865 relocation to do if one of the operands is an address expression. */
1866
1867static const char *
1868riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
629310ab 1869 bfd_reloc_code_real_type *imm_reloc, htab_t hash)
e23eba97
NC		 1870{
1871 char *s;
1872 const char *args;
1873 char c = 0;
1874 struct riscv_opcode *insn;
1875 char *argsStart;
1876 unsigned int regno;
1877 char save_c = 0;
1878 int argnum;
1879 const struct percent_op_match *p;
1880 const char *error = "unrecognized opcode";
54b2aec1
NC		 1881 /* Indicate we are assembling instruction with CSR. */
1882 bfd_boolean insn_with_csr = FALSE;
e23eba97
NC		 1883
1884 /* Parse the name of the instruction. Terminate the string if whitespace
629310ab 1885 is found so that str_hash_find only sees the name part of the string. */
e23eba97
NC		 1886 for (s = str; *s != '\0'; ++s)
1887 if (ISSPACE (*s))
1888 {
1889 save_c = *s;
1890 *s++ = '\0';
1891 break;
1892 }
1893
629310ab 1894 insn = (struct riscv_opcode *) str_hash_find (hash, str);
e23eba97
NC		 1895
1896 argsStart = s;
1897 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1898 {
1080bf78
JW		 1899 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
1900 continue;
1901
7e9ad3a3 1902 if (!riscv_multi_subset_supports (insn->insn_class))
e23eba97
NC		 1903 continue;
1904
1905 create_insn (ip, insn);
1906 argnum = 1;
1907
1908 imm_expr->X_op = O_absent;
1909 *imm_reloc = BFD_RELOC_UNUSED;
1910 p = percent_op_itype;
1911
1912 for (args = insn->args;; ++args)
1913 {
1914 s += strspn (s, " \t");
1915 switch (*args)
1916 {
dcd709e0 1917 case '\0': /* End of args. */
e23eba97
NC		 1918 if (insn->pinfo != INSN_MACRO)
1919 {
1920 if (!insn->match_func (insn, ip->insn_opcode))
1921 break;
0e35537d
JW		 1922
1923 /* For .insn, insn->match and insn->mask are 0. */
1924 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
1925 ? ip->insn_opcode
1926 : insn->match) == 2
1927 && !riscv_opts.rvc)
e23eba97 1928 break;
54b2aec1 1929
1a79004f
NC		 1930 if (riscv_is_priv_insn (ip->insn_opcode))
1931 explicit_priv_attr = TRUE;
1932
54b2aec1
NC		 1933 /* Check if we write a read-only CSR by the CSR
1934 instruction. */
1935 if (insn_with_csr
1936 && riscv_opts.csr_check
1937 && !riscv_csr_read_only_check (ip->insn_opcode))
1938 {
1939 /* Restore the character in advance, since we want to
1940 report the detailed warning message here. */
1941 if (save_c)
1942 *(argsStart - 1) = save_c;
b800637e 1943 as_warn (_("read-only CSR is written `%s'"), str);
54b2aec1
NC		 1944 insn_with_csr = FALSE;
1945 }
e23eba97
NC		 1946 }
1947 if (*s != '\0')
1948 break;
1949 /* Successful assembly. */
1950 error = NULL;
54b2aec1 1951 insn_with_csr = FALSE;
e23eba97
NC		 1952 goto out;
1953
1954 case 'C': /* RVC */
1955 switch (*++args)
1956 {
dcd709e0 1957 case 's': /* RS1 x8-x15. */
e23eba97
NC		 1958 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1959 || !(regno >= 8 && regno <= 15))
1960 break;
1961 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1962 continue;
1963 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1964 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1965 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
1966 break;
1967 continue;
dcd709e0 1968 case 't': /* RS2 x8-x15. */
e23eba97
NC		 1969 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1970 || !(regno >= 8 && regno <= 15))
1971 break;
1972 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1973 continue;
1974 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1975 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1976 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
1977 break;
1978 continue;
1979 case 'U': /* RS1, constrained to equal RD. */
1980 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1981 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
1982 break;
1983 continue;
1984 case 'V': /* RS2 */
1985 if (!reg_lookup (&s, RCLASS_GPR, &regno))
1986 break;
1987 INSERT_OPERAND (CRS2, *ip, regno);
1988 continue;
1989 case 'c': /* RS1, constrained to equal sp. */
1990 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1991 || regno != X_SP)
1992 break;
1993 continue;
dcd709e0 1994 case 'z': /* RS2, constrained to equal x0. */
ca0bc150
JW		 1995 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1996 || regno != 0)
1997 break;
1998 continue;
e23eba97
NC		 1999 case '>':
2000 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2001 || imm_expr->X_op != O_constant
2002 || imm_expr->X_add_number <= 0
2003 || imm_expr->X_add_number >= 64)
2004 break;
2005 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
dc1e8a47 2006 rvc_imm_done:
e23eba97
NC		 2007 s = expr_end;
2008 imm_expr->X_op = O_absent;
2009 continue;
2010 case '<':
2011 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2012 || imm_expr->X_op != O_constant
e23eba97 2013 || imm_expr->X_add_number <= 0
169ec512
AM		 2014 || imm_expr->X_add_number >= 32
2015 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2016 break;
2017 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2018 goto rvc_imm_done;
0e35537d
JW		 2019 case '8':
2020 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2021 || imm_expr->X_op != O_constant
0e35537d 2022 || imm_expr->X_add_number < 0
169ec512
AM		 2023 || imm_expr->X_add_number >= 256
2024 || !VALID_RVC_UIMM8 ((valueT) imm_expr->X_add_number))
0e35537d
JW		 2025 break;
2026 ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
2027 goto rvc_imm_done;
e23eba97
NC		 2028 case 'i':
2029 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2030 || imm_expr->X_op != O_constant
2031 || imm_expr->X_add_number == 0
169ec512 2032 || !VALID_RVC_SIMM3 ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2033 break;
2034 ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
2035 goto rvc_imm_done;
2036 case 'j':
2037 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2038 || imm_expr->X_op != O_constant
2039 || imm_expr->X_add_number == 0
169ec512 2040 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2041 break;
2042 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2043 goto rvc_imm_done;
2044 case 'k':
f0531ed6
JW		 2045 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2046 continue;
e23eba97
NC		 2047 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2048 || imm_expr->X_op != O_constant
169ec512 2049 || !VALID_RVC_LW_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2050 break;
2051 ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
2052 goto rvc_imm_done;
2053 case 'l':
f0531ed6
JW		 2054 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2055 continue;
e23eba97
NC		 2056 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2057 || imm_expr->X_op != O_constant
169ec512 2058 || !VALID_RVC_LD_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2059 break;
2060 ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
2061 goto rvc_imm_done;
2062 case 'm':
f0531ed6
JW		 2063 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2064 continue;
e23eba97
NC		 2065 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2066 || imm_expr->X_op != O_constant
169ec512 2067 || !VALID_RVC_LWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2068 break;
2069 ip->insn_opcode |=
2070 ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
2071 goto rvc_imm_done;
2072 case 'n':
f0531ed6
JW		 2073 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2074 continue;
e23eba97
NC		 2075 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2076 || imm_expr->X_op != O_constant
169ec512 2077 || !VALID_RVC_LDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2078 break;
2079 ip->insn_opcode |=
2080 ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
2081 goto rvc_imm_done;
b416fe87
KC		 2082 case 'o':
2083 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2084 || imm_expr->X_op != O_constant
21a186f2
JW		 2085 /* C.addiw, c.li, and c.andi allow zero immediate.
2086 C.addi allows zero immediate as hint. Otherwise this
2087 is same as 'j'. */
169ec512 2088 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
b416fe87
KC		 2089 break;
2090 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2091 goto rvc_imm_done;
e23eba97
NC		 2092 case 'K':
2093 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2094 || imm_expr->X_op != O_constant
169ec512
AM		 2095 || imm_expr->X_add_number == 0
2096 || !VALID_RVC_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2097 break;
2098 ip->insn_opcode |=
2099 ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
2100 goto rvc_imm_done;
2101 case 'L':
2102 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2103 || imm_expr->X_op != O_constant
169ec512
AM		 2104 || imm_expr->X_add_number == 0
2105 || !VALID_RVC_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2106 break;
2107 ip->insn_opcode |=
2108 ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
2109 goto rvc_imm_done;
2110 case 'M':
f0531ed6
JW		 2111 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2112 continue;
e23eba97
NC		 2113 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2114 || imm_expr->X_op != O_constant
169ec512 2115 || !VALID_RVC_SWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2116 break;
2117 ip->insn_opcode |=
2118 ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
2119 goto rvc_imm_done;
2120 case 'N':
f0531ed6
JW		 2121 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2122 continue;
e23eba97
NC		 2123 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2124 || imm_expr->X_op != O_constant
169ec512 2125 || !VALID_RVC_SDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2126 break;
2127 ip->insn_opcode |=
2128 ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
2129 goto rvc_imm_done;
2130 case 'u':
2131 p = percent_op_utype;
2132 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
2133 break;
dc1e8a47 2134 rvc_lui:
e23eba97
NC		 2135 if (imm_expr->X_op != O_constant
2136 || imm_expr->X_add_number <= 0
2137 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
2138 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
2139 && (imm_expr->X_add_number <
2140 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
2141 break;
2142 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2143 goto rvc_imm_done;
2144 case 'v':
2145 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2146 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
2147 || ((int32_t)imm_expr->X_add_number
2148 != imm_expr->X_add_number))
2149 break;
2150 imm_expr->X_add_number =
2151 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
2152 goto rvc_lui;
2153 case 'p':
2154 goto branch;
2155 case 'a':
2156 goto jump;
0e35537d
JW		 2157 case 'S': /* Floating-point RS1 x8-x15. */
2158 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2159 || !(regno >= 8 && regno <= 15))
2160 break;
2161 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2162 continue;
e23eba97
NC		 2163 case 'D': /* Floating-point RS2 x8-x15. */
2164 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2165 || !(regno >= 8 && regno <= 15))
2166 break;
2167 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2168 continue;
2169 case 'T': /* Floating-point RS2. */
2170 if (!reg_lookup (&s, RCLASS_FPR, &regno))
2171 break;
2172 INSERT_OPERAND (CRS2, *ip, regno);
2173 continue;
0e35537d
JW		 2174 case 'F':
2175 switch (*++args)
2176 {
4765cd61
JW		 2177 case '6':
2178 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2179 || imm_expr->X_op != O_constant
2180 || imm_expr->X_add_number < 0
2181 || imm_expr->X_add_number >= 64)
2182 {
b800637e
NC		 2183 as_bad (_("bad value for compressed funct6 "
2184 "field, value must be 0...64"));
4765cd61
JW		 2185 break;
2186 }
2187
2188 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
2189 imm_expr->X_op = O_absent;
2190 s = expr_end;
2191 continue;
0e35537d
JW		 2192 case '4':
2193 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2194 || imm_expr->X_op != O_constant
2195 || imm_expr->X_add_number < 0
2196 || imm_expr->X_add_number >= 16)
2197 {
b800637e
NC		 2198 as_bad (_("bad value for compressed funct4 "
2199 "field, value must be 0...15"));
0e35537d
JW		 2200 break;
2201 }
2202
2203 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
2204 imm_expr->X_op = O_absent;
2205 s = expr_end;
2206 continue;
2207 case '3':
2208 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2209 || imm_expr->X_op != O_constant
2210 || imm_expr->X_add_number < 0
2211 || imm_expr->X_add_number >= 8)
2212 {
b800637e
NC		 2213 as_bad (_("bad value for compressed funct3 "
2214 "field, value must be 0...7"));
0e35537d
JW		 2215 break;
2216 }
2217 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
2218 imm_expr->X_op = O_absent;
2219 s = expr_end;
2220 continue;
4765cd61
JW		 2221 case '2':
2222 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2223 || imm_expr->X_op != O_constant
2224 || imm_expr->X_add_number < 0
2225 || imm_expr->X_add_number >= 4)
2226 {
b800637e
NC		 2227 as_bad (_("bad value for compressed funct2 "
2228 "field, value must be 0...3"));
4765cd61
JW		 2229 break;
2230 }
2231 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number);
2232 imm_expr->X_op = O_absent;
2233 s = expr_end;
2234 continue;
0e35537d 2235 default:
b800637e
NC		 2236 as_bad (_("internal: unknown compressed funct "
2237 "field specifier `CF%c'"), *args);
0e35537d
JW		 2238 }
2239 break;
2240
e23eba97 2241 default:
b800637e
NC		 2242 as_bad (_("internal: unknown compressed field "
2243 "specifier `C%c'"), *args);
e23eba97
NC		 2244 }
2245 break;
2246
2247 case ',':
2248 ++argnum;
2249 if (*s++ == *args)
2250 continue;
2251 s--;
2252 break;
2253
2254 case '(':
2255 case ')':
2256 case '[':
2257 case ']':
2258 if (*s++ == *args)
2259 continue;
2260 break;
2261
dcd709e0 2262 case '<': /* Shift amount, 0 - 31. */
e23eba97 2263 my_getExpression (imm_expr, s);
ca2fd32c 2264 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2265 if ((unsigned long) imm_expr->X_add_number > 31)
b800637e 2266 as_bad (_("improper shift amount (%lu)"),
94f78a77 2267 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2268 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
2269 imm_expr->X_op = O_absent;
2270 s = expr_end;
2271 continue;
2272
dcd709e0 2273 case '>': /* Shift amount, 0 - (XLEN-1). */
e23eba97 2274 my_getExpression (imm_expr, s);
ca2fd32c 2275 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2276 if ((unsigned long) imm_expr->X_add_number >= xlen)
b800637e 2277 as_bad (_("improper shift amount (%lu)"),
94f78a77 2278 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2279 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
2280 imm_expr->X_op = O_absent;
2281 s = expr_end;
2282 continue;
2283
dcd709e0 2284 case 'Z': /* CSRRxI immediate. */
e23eba97 2285 my_getExpression (imm_expr, s);
ca2fd32c 2286 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2287 if ((unsigned long) imm_expr->X_add_number > 31)
b800637e 2288 as_bad (_("improper CSRxI immediate (%lu)"),
94f78a77 2289 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2290 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
2291 imm_expr->X_op = O_absent;
2292 s = expr_end;
2293 continue;
2294
dcd709e0 2295 case 'E': /* Control register. */
54b2aec1 2296 insn_with_csr = TRUE;
1a79004f 2297 explicit_priv_attr = TRUE;
e23eba97
NC		 2298 if (reg_lookup (&s, RCLASS_CSR, &regno))
2299 INSERT_OPERAND (CSR, *ip, regno);
2300 else
2301 {
2302 my_getExpression (imm_expr, s);
ca2fd32c 2303 check_absolute_expr (ip, imm_expr, TRUE);
e23eba97 2304 if ((unsigned long) imm_expr->X_add_number > 0xfff)
b800637e 2305 as_bad (_("improper CSR address (%lu)"),
94f78a77 2306 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2307 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
2308 imm_expr->X_op = O_absent;
2309 s = expr_end;
2310 }
2311 continue;
2312
dcd709e0 2313 case 'm': /* Rounding mode. */
e23eba97
NC		 2314 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
2315 {
2316 INSERT_OPERAND (RM, *ip, regno);
2317 continue;
2318 }
2319 break;
2320
2321 case 'P':
dcd709e0 2322 case 'Q': /* Fence predecessor/successor. */
e23eba97
NC		 2323 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
2324 &regno))
2325 {
2326 if (*args == 'P')
2327 INSERT_OPERAND (PRED, *ip, regno);
2328 else
2329 INSERT_OPERAND (SUCC, *ip, regno);
2330 continue;
2331 }
2332 break;
2333
dcd709e0
NC		 2334 case 'd': /* Destination register. */
2335 case 's': /* Source register. */
2336 case 't': /* Target register. */
2337 case 'r': /* RS3 */
e23eba97
NC		 2338 if (reg_lookup (&s, RCLASS_GPR, &regno))
2339 {
2340 c = *args;
2341 if (*s == ' ')
2342 ++s;
2343
2344 /* Now that we have assembled one operand, we use the args
2345 string to figure out where it goes in the instruction. */
2346 switch (c)
2347 {
2348 case 's':
2349 INSERT_OPERAND (RS1, *ip, regno);
2350 break;
2351 case 'd':
2352 INSERT_OPERAND (RD, *ip, regno);
2353 break;
2354 case 't':
2355 INSERT_OPERAND (RS2, *ip, regno);
2356 break;
0e35537d
JW		 2357 case 'r':
2358 INSERT_OPERAND (RS3, *ip, regno);
2359 break;
e23eba97
NC		 2360 }
2361 continue;
2362 }
2363 break;
2364
dcd709e0
NC		 2365 case 'D': /* Floating point RD. */
2366 case 'S': /* Floating point RS1. */
2367 case 'T': /* Floating point RS2. */
2368 case 'U': /* Floating point RS1 and RS2. */
2369 case 'R': /* Floating point RS3. */
e23eba97
NC		 2370 if (reg_lookup (&s, RCLASS_FPR, &regno))
2371 {
2372 c = *args;
2373 if (*s == ' ')
2374 ++s;
2375 switch (c)
2376 {
2377 case 'D':
2378 INSERT_OPERAND (RD, *ip, regno);
2379 break;
2380 case 'S':
2381 INSERT_OPERAND (RS1, *ip, regno);
2382 break;
2383 case 'U':
2384 INSERT_OPERAND (RS1, *ip, regno);
dcd709e0 2385 /* Fall through. */
e23eba97
NC		 2386 case 'T':
2387 INSERT_OPERAND (RS2, *ip, regno);
2388 break;
2389 case 'R':
2390 INSERT_OPERAND (RS3, *ip, regno);
2391 break;
2392 }
2393 continue;
2394 }
2395
2396 break;
2397
2398 case 'I':
2399 my_getExpression (imm_expr, s);
2400 if (imm_expr->X_op != O_big
2401 && imm_expr->X_op != O_constant)
2402 break;
2403 normalize_constant_expr (imm_expr);
2404 s = expr_end;
2405 continue;
2406
2407 case 'A':
2408 my_getExpression (imm_expr, s);
2409 normalize_constant_expr (imm_expr);
2410 /* The 'A' format specifier must be a symbol. */
2411 if (imm_expr->X_op != O_symbol)
2412 break;
2413 *imm_reloc = BFD_RELOC_32;
2414 s = expr_end;
2415 continue;
2416
160d1b3d
SH		 2417 case 'B':
2418 my_getExpression (imm_expr, s);
2419 normalize_constant_expr (imm_expr);
2420 /* The 'B' format specifier must be a symbol or a constant. */
2421 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
2422 break;
2423 if (imm_expr->X_op == O_symbol)
2424 *imm_reloc = BFD_RELOC_32;
2425 s = expr_end;
2426 continue;
2427
e23eba97 2428 case 'j': /* Sign-extended immediate. */
e23eba97 2429 p = percent_op_itype;
f50fabe4 2430 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
e23eba97
NC		 2431 goto alu_op;
2432 case 'q': /* Store displacement. */
2433 p = percent_op_stype;
2434 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
2435 goto load_store;
2436 case 'o': /* Load displacement. */
2437 p = percent_op_itype;
2438 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
2439 goto load_store;
dcd709e0
NC		 2440 case '1':
2441 /* This is used for TLS, where the fourth operand is
2442 %tprel_add, to get a relocation applied to an add
2443 instruction, for relaxation to use. */
e23eba97 2444 p = percent_op_rtype;
f50fabe4 2445 goto alu_op;
dcd709e0 2446 case '0': /* AMO displacement, which must be zero. */
f50fabe4 2447 p = percent_op_null;
dc1e8a47 2448 load_store:
f0531ed6 2449 if (riscv_handle_implicit_zero_offset (imm_expr, s))
e23eba97 2450 continue;
dc1e8a47 2451 alu_op:
e23eba97
NC		 2452 /* If this value won't fit into a 16 bit offset, then go
2453 find a macro that will generate the 32 bit offset
2454 code pattern. */
2455 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
2456 {
2457 normalize_constant_expr (imm_expr);
2458 if (imm_expr->X_op != O_constant
2459 || (*args == '0' && imm_expr->X_add_number != 0)
f50fabe4 2460 || (*args == '1')
e23eba97
NC		 2461 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
2462 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
2463 break;
2464 }
2465
2466 s = expr_end;
2467 continue;
2468
dcd709e0 2469 case 'p': /* PC-relative offset. */
dc1e8a47 2470 branch:
e23eba97
NC		 2471 *imm_reloc = BFD_RELOC_12_PCREL;
2472 my_getExpression (imm_expr, s);
2473 s = expr_end;
2474 continue;
2475
dcd709e0 2476 case 'u': /* Upper 20 bits. */
e23eba97 2477 p = percent_op_utype;
4288405d 2478 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
e23eba97 2479 {
4288405d
JW		 2480 if (imm_expr->X_op != O_constant)
2481 break;
2482
e23eba97
NC		 2483 if (imm_expr->X_add_number < 0
2484 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
2485 as_bad (_("lui expression not in range 0..1048575"));
2486
2487 *imm_reloc = BFD_RELOC_RISCV_HI20;
2488 imm_expr->X_add_number <<= RISCV_IMM_BITS;
2489 }
2490 s = expr_end;
2491 continue;
2492
dcd709e0 2493 case 'a': /* 20-bit PC-relative offset. */
dc1e8a47 2494 jump:
e23eba97
NC		 2495 my_getExpression (imm_expr, s);
2496 s = expr_end;
2497 *imm_reloc = BFD_RELOC_RISCV_JMP;
2498 continue;
2499
2500 case 'c':
2501 my_getExpression (imm_expr, s);
2502 s = expr_end;
2503 if (strcmp (s, "@plt") == 0)
2504 {
2505 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2506 s += 4;
2507 }
2508 else
2509 *imm_reloc = BFD_RELOC_RISCV_CALL;
2510 continue;
0e35537d
JW		 2511 case 'O':
2512 switch (*++args)
2513 {
2514 case '4':
2515 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2516 || imm_expr->X_op != O_constant
2517 || imm_expr->X_add_number < 0
2518 || imm_expr->X_add_number >= 128
2519 || (imm_expr->X_add_number & 0x3) != 3)
2520 {
2521 as_bad (_("bad value for opcode field, "
2522 "value must be 0...127 and "
2523 "lower 2 bits must be 0x3"));
2524 break;
2525 }
2526
2527 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2528 imm_expr->X_op = O_absent;
2529 s = expr_end;
2530 continue;
2531 case '2':
2532 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2533 || imm_expr->X_op != O_constant
2534 || imm_expr->X_add_number < 0
2535 || imm_expr->X_add_number >= 3)
2536 {
2537 as_bad (_("bad value for opcode field, "
2538 "value must be 0...2"));
2539 break;
2540 }
2541
2542 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2543 imm_expr->X_op = O_absent;
2544 s = expr_end;
2545 continue;
2546 default:
b800637e
NC		 2547 as_bad (_("internal: unknown opcode field "
2548 "specifier `O%c'"), *args);
0e35537d
JW		 2549 }
2550 break;
2551
2552 case 'F':
2553 switch (*++args)
2554 {
2555 case '7':
2556 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2557 || imm_expr->X_op != O_constant
2558 || imm_expr->X_add_number < 0
2559 || imm_expr->X_add_number >= 128)
2560 {
2561 as_bad (_("bad value for funct7 field, "
2562 "value must be 0...127"));
2563 break;
2564 }
2565
2566 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2567 imm_expr->X_op = O_absent;
2568 s = expr_end;
2569 continue;
2570 case '3':
2571 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2572 || imm_expr->X_op != O_constant
2573 || imm_expr->X_add_number < 0
2574 || imm_expr->X_add_number >= 8)
2575 {
2576 as_bad (_("bad value for funct3 field, "
2577 "value must be 0...7"));
2578 break;
2579 }
2580
2581 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2582 imm_expr->X_op = O_absent;
2583 s = expr_end;
2584 continue;
2585 case '2':
2586 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2587 || imm_expr->X_op != O_constant
2588 || imm_expr->X_add_number < 0
2589 || imm_expr->X_add_number >= 4)
2590 {
2591 as_bad (_("bad value for funct2 field, "
2592 "value must be 0...3"));
2593 break;
2594 }
2595
2596 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2597 imm_expr->X_op = O_absent;
2598 s = expr_end;
2599 continue;
2600
2601 default:
b800637e
NC		 2602 as_bad (_("internal: unknown funct field "
2603 "specifier `F%c'\n"), *args);
0e35537d
JW		 2604 }
2605 break;
e23eba97 2606
e925c834
JW		 2607 case 'z':
2608 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2609 || imm_expr->X_op != O_constant
2610 || imm_expr->X_add_number != 0)
2611 break;
2612 s = expr_end;
2613 imm_expr->X_op = O_absent;
2614 continue;
2615
e23eba97 2616 default:
b800637e 2617 as_fatal (_("internal: unknown argument type `%c'"), *args);
e23eba97
NC		 2618 }
2619 break;
2620 }
2621 s = argsStart;
2622 error = _("illegal operands");
54b2aec1 2623 insn_with_csr = FALSE;
e23eba97
NC		 2624 }
2625
dc1e8a47 2626 out:
e23eba97
NC		 2627 /* Restore the character we might have clobbered above. */
2628 if (save_c)
2629 *(argsStart - 1) = save_c;
2630
2631 return error;
2632}
2633
2634void
2635md_assemble (char *str)
2636{
2637 struct riscv_cl_insn insn;
2638 expressionS imm_expr;
2639 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2640
dcd709e0
NC		 2641 /* The architecture and privileged elf attributes should be set
2642 before assembling. */
8f595e9b
NC		 2643 if (!start_assemble)
2644 {
2645 start_assemble = TRUE;
e23eba97 2646
dcd709e0 2647 riscv_set_abi_by_arch ();
8f595e9b
NC		 2648 if (!riscv_set_default_priv_spec (NULL))
2649 return;
2650 }
2651
2652 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
2dc8dd17 2653
e23eba97
NC		 2654 if (error)
2655 {
2656 as_bad ("%s `%s'", error, str);
2657 return;
2658 }
2659
2660 if (insn.insn_mo->pinfo == INSN_MACRO)
2661 macro (&insn, &imm_expr, &imm_reloc);
2662 else
2663 append_insn (&insn, &imm_expr, imm_reloc);
2664}
2665
2666const char *
2667md_atof (int type, char *litP, int *sizeP)
2668{
2669 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2670}
2671
2672void
2673md_number_to_chars (char *buf, valueT val, int n)
2674{
fbc09e7a
MC		 2675 if (target_big_endian)
2676 number_to_chars_bigendian (buf, val, n);
2677 else
2678 number_to_chars_littleendian (buf, val, n);
e23eba97
NC		 2679}
2680
2681const char *md_shortopts = "O::g::G:";
2682
2683enum options
2684{
2922d21d 2685 OPTION_MARCH = OPTION_MD_BASE,
e23eba97
NC		 2686 OPTION_PIC,
2687 OPTION_NO_PIC,
2922d21d 2688 OPTION_MABI,
71060565
JW		 2689 OPTION_RELAX,
2690 OPTION_NO_RELAX,
2dc8dd17
JW		 2691 OPTION_ARCH_ATTR,
2692 OPTION_NO_ARCH_ATTR,
2ca89224
NC		 2693 OPTION_CSR_CHECK,
2694 OPTION_NO_CSR_CHECK,
8f595e9b
NC		 2695 OPTION_MISA_SPEC,
2696 OPTION_MPRIV_SPEC,
fbc09e7a
MC		 2697 OPTION_BIG_ENDIAN,
2698 OPTION_LITTLE_ENDIAN,
e23eba97
NC		 2699 OPTION_END_OF_ENUM
2700};
2701
2702struct option md_longopts[] =
2703{
e23eba97
NC		 2704 {"march", required_argument, NULL, OPTION_MARCH},
2705 {"fPIC", no_argument, NULL, OPTION_PIC},
2706 {"fpic", no_argument, NULL, OPTION_PIC},
2707 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2922d21d 2708 {"mabi", required_argument, NULL, OPTION_MABI},
71060565
JW		 2709 {"mrelax", no_argument, NULL, OPTION_RELAX},
2710 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2dc8dd17
JW		 2711 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
2712 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
2ca89224
NC		 2713 {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
2714 {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
8f595e9b
NC		 2715 {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
2716 {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
fbc09e7a
MC		 2717 {"mbig-endian", no_argument, NULL, OPTION_BIG_ENDIAN},
2718 {"mlittle-endian", no_argument, NULL, OPTION_LITTLE_ENDIAN},
e23eba97
NC		 2719
2720 {NULL, no_argument, NULL, 0}
2721};
2722size_t md_longopts_size = sizeof (md_longopts);
2723
e23eba97
NC		 2724int
2725md_parse_option (int c, const char *arg)
2726{
2727 switch (c)
2728 {
e23eba97 2729 case OPTION_MARCH:
8f595e9b 2730 default_arch_with_ext = arg;
e23eba97
NC		 2731 break;
2732
2733 case OPTION_NO_PIC:
2734 riscv_opts.pic = FALSE;
2735 break;
2736
2737 case OPTION_PIC:
2738 riscv_opts.pic = TRUE;
2739 break;
2740
2922d21d
AW		 2741 case OPTION_MABI:
2742 if (strcmp (arg, "ilp32") == 0)
7f999549
JW		 2743 riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
2744 else if (strcmp (arg, "ilp32e") == 0)
2745 riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
2922d21d 2746 else if (strcmp (arg, "ilp32f") == 0)
7f999549 2747 riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2748 else if (strcmp (arg, "ilp32d") == 0)
7f999549 2749 riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2750 else if (strcmp (arg, "ilp32q") == 0)
7f999549 2751 riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
2922d21d 2752 else if (strcmp (arg, "lp64") == 0)
7f999549 2753 riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
2922d21d 2754 else if (strcmp (arg, "lp64f") == 0)
7f999549 2755 riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2756 else if (strcmp (arg, "lp64d") == 0)
7f999549 2757 riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2758 else if (strcmp (arg, "lp64q") == 0)
7f999549 2759 riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
2922d21d
AW		 2760 else
2761 return 0;
6e1605e4 2762 explicit_mabi = TRUE;
2922d21d
AW		 2763 break;
2764
71060565
JW		 2765 case OPTION_RELAX:
2766 riscv_opts.relax = TRUE;
2767 break;
2768
2769 case OPTION_NO_RELAX:
2770 riscv_opts.relax = FALSE;
2771 break;
2772
2dc8dd17
JW		 2773 case OPTION_ARCH_ATTR:
2774 riscv_opts.arch_attr = TRUE;
2775 break;
2776
2777 case OPTION_NO_ARCH_ATTR:
2778 riscv_opts.arch_attr = FALSE;
2779 break;
2780
2ca89224
NC		 2781 case OPTION_CSR_CHECK:
2782 riscv_opts.csr_check = TRUE;
2783 break;
2784
2785 case OPTION_NO_CSR_CHECK:
2786 riscv_opts.csr_check = FALSE;
2787 break;
2788
8f595e9b
NC		 2789 case OPTION_MISA_SPEC:
2790 return riscv_set_default_isa_spec (arg);
2791
2792 case OPTION_MPRIV_SPEC:
2793 return riscv_set_default_priv_spec (arg);
2794
fbc09e7a
MC		 2795 case OPTION_BIG_ENDIAN:
2796 target_big_endian = 1;
2797 break;
2798
2799 case OPTION_LITTLE_ENDIAN:
2800 target_big_endian = 0;
2801 break;
2802
e23eba97
NC		 2803 default:
2804 return 0;
2805 }
2806
2807 return 1;
2808}
2809
2810void
2811riscv_after_parse_args (void)
2812{
dcd709e0
NC		 2813 /* The --with-arch is optional for now, so we still need to set the xlen
2814 according to the default_arch, which is set by the --target. */
e23eba97
NC		 2815 if (xlen == 0)
2816 {
2817 if (strcmp (default_arch, "riscv32") == 0)
2818 xlen = 32;
2819 else if (strcmp (default_arch, "riscv64") == 0)
2820 xlen = 64;
2821 else
2822 as_bad ("unknown default architecture `%s'", default_arch);
2823 }
8f595e9b
NC		 2824 if (default_arch_with_ext == NULL)
2825 default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
2826
2827 /* Initialize the hash table for extensions with default version. */
2828 ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
2829
dcd709e0 2830 /* Set default specs. */
8f595e9b
NC		 2831 if (default_isa_spec == ISA_SPEC_CLASS_NONE)
2832 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
dcd709e0
NC		 2833 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
2834 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
2922d21d 2835
8f595e9b 2836 riscv_set_arch (default_arch_with_ext);
2922d21d
AW		 2837
2838 /* Add the RVC extension, regardless of -march, to support .option rvc. */
fecb9c46 2839 riscv_set_rvc (FALSE);
1080bf78 2840 if (riscv_subset_supports ("c"))
2922d21d 2841 riscv_set_rvc (TRUE);
2922d21d 2842
7f999549
JW		 2843 /* Enable RVE if specified by the -march option. */
2844 riscv_set_rve (FALSE);
1080bf78 2845 if (riscv_subset_supports ("e"))
7f999549
JW		 2846 riscv_set_rve (TRUE);
2847
0ac2b354
AB		 2848 /* If the CIE to be produced has not been overridden on the command line,
2849 then produce version 3 by default. This allows us to use the full
2850 range of registers in a .cfi_return_column directive. */
2851 if (flag_dwarf_cie_version == -1)
2852 flag_dwarf_cie_version = 3;
e23eba97
NC		 2853}
2854
2855long
2856md_pcrel_from (fixS *fixP)
2857{
2858 return fixP->fx_where + fixP->fx_frag->fr_address;
2859}
2860
2861/* Apply a fixup to the object file. */
2862
2863void
2864md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2865{
45f76423 2866 unsigned int subtype;
e23eba97 2867 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
45f76423 2868 bfd_boolean relaxable = FALSE;
c1b465c9 2869 offsetT loc;
a6cbf936 2870 segT sub_segment;
e23eba97
NC		 2871
2872 /* Remember value for tc_gen_reloc. */
2873 fixP->fx_addnumber = *valP;
2874
2875 switch (fixP->fx_r_type)
2876 {
e23eba97
NC		 2877 case BFD_RELOC_RISCV_HI20:
2878 case BFD_RELOC_RISCV_LO12_I:
2879 case BFD_RELOC_RISCV_LO12_S:
45f76423
AW		 2880 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2881 | bfd_getl32 (buf), buf);
a5ec5e3f
AW		 2882 if (fixP->fx_addsy == NULL)
2883 fixP->fx_done = TRUE;
45f76423
AW		 2884 relaxable = TRUE;
2885 break;
2886
2887 case BFD_RELOC_RISCV_GOT_HI20:
e23eba97
NC		 2888 case BFD_RELOC_RISCV_ADD8:
2889 case BFD_RELOC_RISCV_ADD16:
2890 case BFD_RELOC_RISCV_ADD32:
2891 case BFD_RELOC_RISCV_ADD64:
45f76423 2892 case BFD_RELOC_RISCV_SUB6:
e23eba97
NC		 2893 case BFD_RELOC_RISCV_SUB8:
2894 case BFD_RELOC_RISCV_SUB16:
2895 case BFD_RELOC_RISCV_SUB32:
2896 case BFD_RELOC_RISCV_SUB64:
45f76423
AW		 2897 case BFD_RELOC_RISCV_RELAX:
2898 break;
2899
2900 case BFD_RELOC_RISCV_TPREL_HI20:
2901 case BFD_RELOC_RISCV_TPREL_LO12_I:
2902 case BFD_RELOC_RISCV_TPREL_LO12_S:
2903 case BFD_RELOC_RISCV_TPREL_ADD:
2904 relaxable = TRUE;
2905 /* Fall through. */
2906
2907 case BFD_RELOC_RISCV_TLS_GOT_HI20:
2908 case BFD_RELOC_RISCV_TLS_GD_HI20:
2909 case BFD_RELOC_RISCV_TLS_DTPREL32:
2910 case BFD_RELOC_RISCV_TLS_DTPREL64:
e294484e
AW		 2911 if (fixP->fx_addsy != NULL)
2912 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2913 else
2914 as_bad_where (fixP->fx_file, fixP->fx_line,
2915 _("TLS relocation against a constant"));
e23eba97
NC		 2916 break;
2917
e23eba97 2918 case BFD_RELOC_32:
a6cbf936
KLC		 2919 /* Use pc-relative relocation for FDE initial location.
2920 The symbol address in .eh_frame may be adjusted in
2921 _bfd_elf_discard_section_eh_frame, and the content of
2922 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2923 Therefore, we cannot insert a relocation whose addend symbol is
dcd709e0 2924 in .eh_frame. Othrewise, the value may be adjusted twice. */
a6cbf936
KLC		 2925 if (fixP->fx_addsy && fixP->fx_subsy
2926 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
2927 && strcmp (sub_segment->name, ".eh_frame") == 0
2928 && S_GET_VALUE (fixP->fx_subsy)
2929 == fixP->fx_frag->fr_address + fixP->fx_where)
2930 {
2931 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
2932 fixP->fx_subsy = NULL;
2933 break;
2934 }
2935 /* Fall through. */
2936 case BFD_RELOC_64:
e23eba97
NC		 2937 case BFD_RELOC_16:
2938 case BFD_RELOC_8:
45f76423 2939 case BFD_RELOC_RISCV_CFA:
e23eba97
NC		 2940 if (fixP->fx_addsy && fixP->fx_subsy)
2941 {
2942 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2943 fixP->fx_next->fx_addsy = fixP->fx_subsy;
2944 fixP->fx_next->fx_subsy = NULL;
2945 fixP->fx_next->fx_offset = 0;
2946 fixP->fx_subsy = NULL;
2947
2948 switch (fixP->fx_r_type)
2949 {
2950 case BFD_RELOC_64:
2951 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
2952 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
2953 break;
2954
2955 case BFD_RELOC_32:
2956 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
2957 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2958 break;
2959
2960 case BFD_RELOC_16:
2961 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
2962 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2963 break;
2964
2965 case BFD_RELOC_8:
2966 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
2967 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
073808ed 2968 break;
e23eba97 2969
45f76423
AW		 2970 case BFD_RELOC_RISCV_CFA:
2971 /* Load the byte to get the subtype. */
c1b465c9
KLC		 2972 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
2973 loc = fixP->fx_frag->fr_fix - (subtype & 7);
45f76423
AW		 2974 switch (subtype)
2975 {
2976 case DW_CFA_advance_loc1:
c1b465c9
KLC		 2977 fixP->fx_where = loc + 1;
2978 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2979 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
2980 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
2981 break;
2982
2983 case DW_CFA_advance_loc2:
2984 fixP->fx_size = 2;
45f76423 2985 fixP->fx_next->fx_size = 2;
c1b465c9
KLC		 2986 fixP->fx_where = loc + 1;
2987 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2988 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
2989 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2990 break;
2991
2992 case DW_CFA_advance_loc4:
2993 fixP->fx_size = 4;
45f76423 2994 fixP->fx_next->fx_size = 4;
c1b465c9
KLC		 2995 fixP->fx_where = loc;
2996 fixP->fx_next->fx_where = loc;
45f76423
AW		 2997 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
2998 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2999 break;
3000
3001 default:
3002 if (subtype < 0x80 && (subtype & 0x40))
3003 {
3004 /* DW_CFA_advance_loc */
2aece2ba
KLC		 3005 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
3006 fixP->fx_next->fx_frag = fixP->fx_frag;
45f76423
AW		 3007 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
3008 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
3009 }
3010 else
b800637e 3011 as_fatal (_("internal: bad CFA value #%d"), subtype);
45f76423
AW		 3012 break;
3013 }
3014 break;
3015
e23eba97
NC		 3016 default:
3017 /* This case is unreachable. */
3018 abort ();
3019 }
3020 }
3021 /* Fall through. */
3022
3023 case BFD_RELOC_RVA:
3024 /* If we are deleting this reloc entry, we must fill in the
3025 value now. This can happen if we have a .word which is not
3026 resolved when it appears but is later defined. */
3027 if (fixP->fx_addsy == NULL)
3028 {
3029 gas_assert (fixP->fx_size <= sizeof (valueT));
3030 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
3031 fixP->fx_done = 1;
3032 }
3033 break;
3034
3035 case BFD_RELOC_RISCV_JMP:
3036 if (fixP->fx_addsy)
3037 {
3038 /* Fill in a tentative value to improve objdump readability. */
3039 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3040 bfd_vma delta = target - md_pcrel_from (fixP);
3041 bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
3042 }
3043 break;
3044
3045 case BFD_RELOC_12_PCREL:
3046 if (fixP->fx_addsy)
3047 {
3048 /* Fill in a tentative value to improve objdump readability. */
3049 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3050 bfd_vma delta = target - md_pcrel_from (fixP);
3051 bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
3052 }
3053 break;
3054
3055 case BFD_RELOC_RISCV_RVC_BRANCH:
3056 if (fixP->fx_addsy)
3057 {
3058 /* Fill in a tentative value to improve objdump readability. */
3059 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3060 bfd_vma delta = target - md_pcrel_from (fixP);
3061 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
3062 }
3063 break;
3064
3065 case BFD_RELOC_RISCV_RVC_JUMP:
3066 if (fixP->fx_addsy)
3067 {
3068 /* Fill in a tentative value to improve objdump readability. */
3069 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3070 bfd_vma delta = target - md_pcrel_from (fixP);
3071 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
3072 }
3073 break;
3074
e23eba97
NC		 3075 case BFD_RELOC_RISCV_CALL:
3076 case BFD_RELOC_RISCV_CALL_PLT:
45f76423
AW		 3077 relaxable = TRUE;
3078 break;
3079
9d06997a 3080 case BFD_RELOC_RISCV_PCREL_HI20:
45f76423
AW		 3081 case BFD_RELOC_RISCV_PCREL_LO12_S:
3082 case BFD_RELOC_RISCV_PCREL_LO12_I:
9d06997a
PD		 3083 relaxable = riscv_opts.relax;
3084 break;
3085
e23eba97
NC		 3086 case BFD_RELOC_RISCV_ALIGN:
3087 break;
3088
3089 default:
3090 /* We ignore generic BFD relocations we don't know about. */
3091 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
b800637e 3092 as_fatal (_("internal: bad relocation #%d"), fixP->fx_r_type);
e23eba97 3093 }
45f76423 3094
e294484e
AW		 3095 if (fixP->fx_subsy != NULL)
3096 as_bad_where (fixP->fx_file, fixP->fx_line,
3097 _("unsupported symbol subtraction"));
3098
45f76423
AW		 3099 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3100 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
3101 {
3102 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3103 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
3104 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
b1b11e92 3105 fixP->fx_next->fx_size = 0;
45f76423
AW		 3106 }
3107}
3108
3109/* Because the value of .cfi_remember_state may changed after relaxation,
3110 we insert a fix to relocate it again in link-time. */
3111
3112void
3113riscv_pre_output_hook (void)
3114{
3115 const frchainS *frch;
72393fd1
JW		 3116 segT s;
3117
3118 /* Save the current segment info. */
3119 segT seg = now_seg;
3120 subsegT subseg = now_subseg;
45f76423
AW		 3121
3122 for (s = stdoutput->sections; s; s = s->next)
3123 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
3124 {
7cb7b948 3125 fragS *frag;
45f76423
AW		 3126
3127 for (frag = frch->frch_root; frag; frag = frag->fr_next)
3128 {
3129 if (frag->fr_type == rs_cfa)
3130 {
45f76423 3131 expressionS exp;
8d1015a8 3132 expressionS *symval;
45f76423 3133
8d1015a8 3134 symval = symbol_get_value_expression (frag->fr_symbol);
45f76423 3135 exp.X_op = O_subtract;
8d1015a8 3136 exp.X_add_symbol = symval->X_add_symbol;
45f76423 3137 exp.X_add_number = 0;
8d1015a8 3138 exp.X_op_symbol = symval->X_op_symbol;
45f76423 3139
72393fd1
JW		 3140 /* We must set the segment before creating a frag after all
3141 frag chains have been chained together. */
3142 subseg_set (s, frch->frch_subseg);
3143
c1b465c9 3144 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
45f76423
AW		 3145 BFD_RELOC_RISCV_CFA);
3146 }
3147 }
3148 }
72393fd1
JW		 3149
3150 /* Restore the original segment info. */
3151 subseg_set (seg, subseg);
e23eba97
NC		 3152}
3153
3154/* This structure is used to hold a stack of .option values. */
e23eba97
NC		 3155struct riscv_option_stack
3156{
3157 struct riscv_option_stack *next;
3158 struct riscv_set_options options;
3159};
3160
3161static struct riscv_option_stack *riscv_opts_stack;
3162
3163/* Handle the .option pseudo-op. */
3164
3165static void
3166s_riscv_option (int x ATTRIBUTE_UNUSED)
3167{
3168 char *name = input_line_pointer, ch;
3169
3170 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3171 ++input_line_pointer;
3172 ch = *input_line_pointer;
3173 *input_line_pointer = '\0';
3174
3175 if (strcmp (name, "rvc") == 0)
3176 riscv_set_rvc (TRUE);
3177 else if (strcmp (name, "norvc") == 0)
3178 riscv_set_rvc (FALSE);
3179 else if (strcmp (name, "pic") == 0)
3180 riscv_opts.pic = TRUE;
3181 else if (strcmp (name, "nopic") == 0)
3182 riscv_opts.pic = FALSE;
45f76423
AW		 3183 else if (strcmp (name, "relax") == 0)
3184 riscv_opts.relax = TRUE;
3185 else if (strcmp (name, "norelax") == 0)
3186 riscv_opts.relax = FALSE;
2ca89224
NC		 3187 else if (strcmp (name, "csr-check") == 0)
3188 riscv_opts.csr_check = TRUE;
3189 else if (strcmp (name, "no-csr-check") == 0)
3190 riscv_opts.csr_check = FALSE;
e23eba97
NC		 3191 else if (strcmp (name, "push") == 0)
3192 {
3193 struct riscv_option_stack *s;
3194
3195 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
3196 s->next = riscv_opts_stack;
3197 s->options = riscv_opts;
3198 riscv_opts_stack = s;
3199 }
3200 else if (strcmp (name, "pop") == 0)
3201 {
3202 struct riscv_option_stack *s;
3203
3204 s = riscv_opts_stack;
3205 if (s == NULL)
3206 as_bad (_(".option pop with no .option push"));
3207 else
3208 {
3209 riscv_opts = s->options;
3210 riscv_opts_stack = s->next;
3211 free (s);
3212 }
3213 }
3214 else
3215 {
b800637e 3216 as_warn (_("unrecognized .option directive: %s\n"), name);
e23eba97
NC		 3217 }
3218 *input_line_pointer = ch;
3219 demand_empty_rest_of_line ();
3220}
3221
3222/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3223 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3224 use in DWARF debug information. */
3225
3226static void
3227s_dtprel (int bytes)
3228{
3229 expressionS ex;
3230 char *p;
3231
3232 expression (&ex);
3233
3234 if (ex.X_op != O_symbol)
3235 {
b800637e 3236 as_bad (_("unsupported use of %s"), (bytes == 8
e23eba97
NC		 3237 ? ".dtpreldword"
3238 : ".dtprelword"));
3239 ignore_rest_of_line ();
3240 }
3241
3242 p = frag_more (bytes);
3243 md_number_to_chars (p, 0, bytes);
3244 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
3245 (bytes == 8
3246 ? BFD_RELOC_RISCV_TLS_DTPREL64
3247 : BFD_RELOC_RISCV_TLS_DTPREL32));
3248
3249 demand_empty_rest_of_line ();
3250}
3251
3252/* Handle the .bss pseudo-op. */
3253
3254static void
3255s_bss (int ignore ATTRIBUTE_UNUSED)
3256{
3257 subseg_set (bss_section, 0);
3258 demand_empty_rest_of_line ();
3259}
3260
e23eba97 3261static void
d115ab8e 3262riscv_make_nops (char *buf, bfd_vma bytes)
e23eba97 3263{
d115ab8e 3264 bfd_vma i = 0;
e23eba97 3265
e5b737de
AW		 3266 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3267 means we are not within a valid instruction sequence. It is thus safe
3268 to use a zero byte, even though that is not a valid instruction. */
3269 if (bytes % 2 == 1)
3270 buf[i++] = 0;
3271
3272 /* Use at most one 2-byte NOP. */
3273 if ((bytes - i) % 4 == 2)
e23eba97 3274 {
fbc09e7a 3275 number_to_chars_littleendian (buf + i, RVC_NOP, 2);
d115ab8e 3276 i += 2;
e23eba97
NC		 3277 }
3278
e5b737de 3279 /* Fill the remainder with 4-byte NOPs. */
d115ab8e 3280 for ( ; i < bytes; i += 4)
fbc09e7a 3281 number_to_chars_littleendian (buf + i, RISCV_NOP, 4);
d115ab8e 3282}
e23eba97 3283
d115ab8e
AW		 3284/* Called from md_do_align. Used to create an alignment frag in a
3285 code section by emitting a worst-case NOP sequence that the linker
3286 will later relax to the correct number of NOPs. We can't compute
3287 the correct alignment now because of other linker relaxations. */
3288
3289bfd_boolean
3290riscv_frag_align_code (int n)
3291{
e5b737de 3292 bfd_vma bytes = (bfd_vma) 1 << n;
36877bfb
JW		 3293 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
3294 bfd_vma worst_case_bytes = bytes - insn_alignment;
3295 char *nops;
ed0816bd 3296 expressionS ex;
d115ab8e 3297
36877bfb
JW		 3298 /* If we are moving to a smaller alignment than the instruction size, then no
3299 alignment is required. */
3300 if (bytes <= insn_alignment)
3301 return TRUE;
3302
d115ab8e
AW		 3303 /* When not relaxing, riscv_handle_align handles code alignment. */
3304 if (!riscv_opts.relax)
3305 return FALSE;
e23eba97 3306
e80ae190
JW		 3307 nops = frag_more (worst_case_bytes);
3308
ed0816bd
PD		 3309 ex.X_op = O_constant;
3310 ex.X_add_number = worst_case_bytes;
d115ab8e 3311
ed0816bd 3312 riscv_make_nops (nops, worst_case_bytes);
e23eba97 3313
ed0816bd
PD		 3314 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
3315 &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
e23eba97 3316
d115ab8e
AW		 3317 return TRUE;
3318}
e23eba97 3319
d115ab8e
AW		 3320/* Implement HANDLE_ALIGN. */
3321
3322void
3323riscv_handle_align (fragS *fragP)
3324{
3325 switch (fragP->fr_type)
3326 {
3327 case rs_align_code:
3328 /* When relaxing, riscv_frag_align_code handles code alignment. */
3329 if (!riscv_opts.relax)
3330 {
e80ae190
JW		 3331 bfd_signed_vma bytes = (fragP->fr_next->fr_address
3332 - fragP->fr_address - fragP->fr_fix);
3333 /* We have 4 byte uncompressed nops. */
3334 bfd_signed_vma size = 4;
3335 bfd_signed_vma excess = bytes % size;
3336 char *p = fragP->fr_literal + fragP->fr_fix;
3337
3338 if (bytes <= 0)
d115ab8e
AW		 3339 break;
3340
e80ae190
JW		 3341 /* Insert zeros or compressed nops to get 4 byte alignment. */
3342 if (excess)
3343 {
3344 riscv_make_nops (p, excess);
3345 fragP->fr_fix += excess;
3346 p += excess;
3347 }
3348
3349 /* Insert variable number of 4 byte uncompressed nops. */
3350 riscv_make_nops (p, size);
3351 fragP->fr_var = size;
d115ab8e
AW		 3352 }
3353 break;
3354
3355 default:
3356 break;
3357 }
e23eba97
NC		 3358}
3359
3360int
3361md_estimate_size_before_relax (fragS *fragp, asection *segtype)
3362{
3363 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
3364}
3365
3366/* Translate internal representation of relocation info to BFD target
3367 format. */
3368
3369arelent *
3370tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3371{
3372 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
3373
3374 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3375 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3376 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3377 reloc->addend = fixp->fx_addnumber;
3378
3379 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3380 if (reloc->howto == NULL)
3381 {
3382 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
3383 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
3384 {
3385 /* We don't have R_RISCV_8/16, but for this special case,
3386 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3387 return reloc;
3388 }
3389
3390 as_bad_where (fixp->fx_file, fixp->fx_line,
3391 _("cannot represent %s relocation in object file"),
3392 bfd_get_reloc_code_name (fixp->fx_r_type));
3393 return NULL;
3394 }
3395
3396 return reloc;
3397}
3398
3399int
3400riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
3401{
3402 if (RELAX_BRANCH_P (fragp->fr_subtype))
3403 {
3404 offsetT old_var = fragp->fr_var;
3405 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
3406 return fragp->fr_var - old_var;
3407 }
3408
3409 return 0;
3410}
3411
3412/* Expand far branches to multi-instruction sequences. */
3413
3414static void
3415md_convert_frag_branch (fragS *fragp)
3416{
3417 bfd_byte *buf;
3418 expressionS exp;
3419 fixS *fixp;
3420 insn_t insn;
3421 int rs1, reloc;
3422
3423 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
3424
3425 exp.X_op = O_symbol;
3426 exp.X_add_symbol = fragp->fr_symbol;
3427 exp.X_add_number = fragp->fr_offset;
3428
3429 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
3430
3431 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
3432 {
3433 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3434 {
3435 case 8:
3436 case 4:
3437 /* Expand the RVC branch into a RISC-V one. */
3438 insn = bfd_getl16 (buf);
3439 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
3440 if ((insn & MASK_C_J) == MATCH_C_J)
3441 insn = MATCH_JAL;
3442 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
3443 insn = MATCH_JAL | (X_RA << OP_SH_RD);
3444 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
3445 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
3446 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
3447 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
3448 else
3449 abort ();
3450 bfd_putl32 (insn, buf);
3451 break;
3452
3453 case 6:
3454 /* Invert the branch condition. Branch over the jump. */
3455 insn = bfd_getl16 (buf);
3456 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
3457 insn |= ENCODE_RVC_B_IMM (6);
3458 bfd_putl16 (insn, buf);
3459 buf += 2;
3460 goto jump;
3461
3462 case 2:
3463 /* Just keep the RVC branch. */
3464 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3465 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
3466 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3467 2, &exp, FALSE, reloc);
3468 buf += 2;
3469 goto done;
3470
3471 default:
1d65abb5 3472 abort ();
e23eba97
NC		 3473 }
3474 }
3475
3476 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3477 {
3478 case 8:
3479 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
3480
3481 /* Invert the branch condition. Branch over the jump. */
3482 insn = bfd_getl32 (buf);
3483 insn ^= MATCH_BEQ ^ MATCH_BNE;
3484 insn |= ENCODE_SBTYPE_IMM (8);
fbc09e7a 3485 bfd_putl32 (insn, buf);
e23eba97
NC		 3486 buf += 4;
3487
dc1e8a47 3488 jump:
e23eba97
NC		 3489 /* Jump to the target. */
3490 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3491 4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
fbc09e7a 3492 bfd_putl32 (MATCH_JAL, buf);
e23eba97
NC		 3493 buf += 4;
3494 break;
3495
3496 case 4:
3497 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3498 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
3499 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3500 4, &exp, FALSE, reloc);
3501 buf += 4;
3502 break;
3503
3504 default:
3505 abort ();
3506 }
3507
dc1e8a47 3508 done:
e23eba97
NC		 3509 fixp->fx_file = fragp->fr_file;
3510 fixp->fx_line = fragp->fr_line;
3511
3512 gas_assert (buf == (bfd_byte *)fragp->fr_literal
3513 + fragp->fr_fix + fragp->fr_var);
3514
3515 fragp->fr_fix += fragp->fr_var;
3516}
3517
3518/* Relax a machine dependent frag. This returns the amount by which
3519 the current size of the frag should change. */
3520
3521void
3522md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3523 fragS *fragp)
3524{
3525 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
3526 md_convert_frag_branch (fragp);
3527}
3528
3529void
3530md_show_usage (FILE *stream)
3531{
3532 fprintf (stream, _("\
3533RISC-V options:\n\
8f595e9b
NC		 3534 -fpic generate position-independent code\n\
3535 -fno-pic don't generate position-independent code (default)\n\
3536 -march=ISA set the RISC-V architecture\n\
3537 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3538 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3539 -mabi=ABI set the RISC-V ABI\n\
3540 -mrelax enable relax (default)\n\
3541 -mno-relax disable relax\n\
3542 -march-attr generate RISC-V arch attribute\n\
3543 -mno-arch-attr don't generate RISC-V arch attribute\n\
e23eba97
NC		 3544"));
3545}
3546
3547/* Standard calling conventions leave the CFA at SP on entry. */
dcd709e0 3548
e23eba97
NC		 3549void
3550riscv_cfi_frame_initial_instructions (void)
3551{
3552 cfi_add_CFA_def_cfa_register (X_SP);
3553}
3554
3555int
3556tc_riscv_regname_to_dw2regnum (char *regname)
3557{
3558 int reg;
3559
3560 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3561 return reg;
3562
3563 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3564 return reg + 32;
3565
4762fe62
AB		 3566 /* CSRs are numbered 4096 -> 8191. */
3567 if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
3568 return reg + 4096;
3569
e23eba97
NC		 3570 as_bad (_("unknown register `%s'"), regname);
3571 return -1;
3572}
3573
3574void
3575riscv_elf_final_processing (void)
3576{
6e1605e4 3577 riscv_set_abi_by_arch ();
e23eba97 3578 elf_elfheader (stdoutput)->e_flags |= elf_flags;
e23eba97
NC		 3579}
3580
3581/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3582 since these directives break relaxation when used with symbol deltas. */
3583
3584static void
3585s_riscv_leb128 (int sign)
3586{
3587 expressionS exp;
3588 char *save_in = input_line_pointer;
3589
3590 expression (&exp);
3591 if (exp.X_op != O_constant)
3592 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3593 demand_empty_rest_of_line ();
3594
3595 input_line_pointer = save_in;
3596 return s_leb128 (sign);
3597}
3598
0e35537d
JW		 3599/* Parse the .insn directive. */
3600
3601static void
3602s_riscv_insn (int x ATTRIBUTE_UNUSED)
3603{
3604 char *str = input_line_pointer;
3605 struct riscv_cl_insn insn;
3606 expressionS imm_expr;
3607 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3608 char save_c;
3609
3610 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3611 ++input_line_pointer;
3612
3613 save_c = *input_line_pointer;
3614 *input_line_pointer = '\0';
3615
3616 const char *error = riscv_ip (str, &insn, &imm_expr,
3617 &imm_reloc, insn_type_hash);
3618
3619 if (error)
3620 {
3621 as_bad ("%s `%s'", error, str);
3622 }
3623 else
3624 {
3625 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3626 append_insn (&insn, &imm_expr, imm_reloc);
3627 }
3628
3629 *input_line_pointer = save_c;
3630 demand_empty_rest_of_line ();
3631}
3632
dcd709e0
NC		 3633/* Update architecture and privileged elf attributes. If we don't set
3634 them, then try to output the default ones. */
2dc8dd17
JW		 3635
3636static void
8f595e9b 3637riscv_write_out_attrs (void)
2dc8dd17 3638{
8f595e9b 3639 const char *arch_str, *priv_str, *p;
dcd709e0
NC		 3640 /* versions[0]: major version.
3641 versions[1]: minor version.
3642 versions[2]: revision version. */
8f595e9b
NC		 3643 unsigned versions[3] = {0}, number = 0;
3644 unsigned int i;
2dc8dd17 3645
dcd709e0 3646 /* Re-write architecture elf attribute. */
8f595e9b 3647 arch_str = riscv_arch_str (xlen, &riscv_subsets);
2dc8dd17 3648 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
2dc8dd17 3649 xfree ((void *)arch_str);
8f595e9b
NC		 3650
3651 /* For the file without any instruction, we don't set the default_priv_spec
dcd709e0
NC		 3652 according to the privileged elf attributes since the md_assemble isn't
3653 called. */
8f595e9b
NC		 3654 if (!start_assemble
3655 && !riscv_set_default_priv_spec (NULL))
3656 return;
3657
dcd709e0
NC		 3658 /* If we already have set privileged elf attributes, then no need to do
3659 anything. Otherwise, don't generate or update them when no CSR and
3660 privileged instructions are used. */
1a79004f 3661 if (!explicit_priv_attr)
3fc6c3dc
NC		 3662 return;
3663
8f595e9b
NC		 3664 priv_str = riscv_get_priv_spec_name (default_priv_spec);
3665 p = priv_str;
3666 for (i = 0; *p; ++p)
3667 {
3668 if (*p == '.' && i < 3)
3669 {
3670 versions[i++] = number;
3671 number = 0;
3672 }
3673 else if (ISDIGIT (*p))
3674 number = (number * 10) + (*p - '0');
3675 else
3676 {
b800637e 3677 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str);
8f595e9b
NC		 3678 return;
3679 }
3680 }
3681 versions[i] = number;
3682
dcd709e0 3683 /* Re-write privileged elf attributes. */
8f595e9b
NC		 3684 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
3685 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
3686 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
2dc8dd17
JW		 3687}
3688
dcd709e0 3689/* Add the default contents for the .riscv.attributes section. */
2dc8dd17
JW		 3690
3691static void
3692riscv_set_public_attributes (void)
3693{
8f595e9b
NC		 3694 if (riscv_opts.arch_attr || explicit_attr)
3695 riscv_write_out_attrs ();
2dc8dd17
JW		 3696}
3697
3698/* Called after all assembly has been done. */
3699
3700void
3701riscv_md_end (void)
3702{
3703 riscv_set_public_attributes ();
3704}
3705
3706/* Given a symbolic attribute NAME, return the proper integer value.
3707 Returns -1 if the attribute is not known. */
3708
3709int
3710riscv_convert_symbolic_attribute (const char *name)
3711{
3712 static const struct
3713 {
3714 const char * name;
3715 const int tag;
3716 }
3717 attribute_table[] =
3718 {
3719 /* When you modify this table you should
3720 also modify the list in doc/c-riscv.texi. */
3721#define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3722 T(arch),
3723 T(priv_spec),
3724 T(priv_spec_minor),
3725 T(priv_spec_revision),
3726 T(unaligned_access),
3727 T(stack_align),
3728#undef T
3729 };
3730
3731 unsigned int i;
3732
3733 if (name == NULL)
3734 return -1;
3735
3736 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
3737 if (strcmp (name, attribute_table[i].name) == 0)
3738 return attribute_table[i].tag;
3739
3740 return -1;
3741}
3742
3743/* Parse a .attribute directive. */
3744
3745static void
3746s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
3747{
3748 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
8f595e9b
NC		 3749 unsigned old_xlen;
3750 obj_attribute *attr;
2dc8dd17 3751
8f595e9b
NC		 3752 explicit_attr = TRUE;
3753 switch (tag)
2dc8dd17 3754 {
8f595e9b
NC		 3755 case Tag_RISCV_arch:
3756 old_xlen = xlen;
2dc8dd17
JW		 3757 attr = elf_known_obj_attributes_proc (stdoutput);
3758 if (!start_assemble)
3759 riscv_set_arch (attr[Tag_RISCV_arch].s);
3760 else
b800637e
NC		 3761 as_fatal (_("architecture elf attributes must set before "
3762 "any instructions"));
2dc8dd17
JW		 3763
3764 if (old_xlen != xlen)
3765 {
3766 /* We must re-init bfd again if xlen is changed. */
3767 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
3768 bfd_find_target (riscv_target_format (), stdoutput);
3769
3770 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
b800637e 3771 as_warn (_("could not set architecture and machine"));
2dc8dd17 3772 }
8f595e9b
NC		 3773 break;
3774
3775 case Tag_RISCV_priv_spec:
3776 case Tag_RISCV_priv_spec_minor:
3777 case Tag_RISCV_priv_spec_revision:
3778 if (start_assemble)
b800637e
NC		 3779 as_fatal (_("privileged elf attributes must set before "
3780 "any instructions"));
8f595e9b
NC		 3781 break;
3782
3783 default:
3784 break;
2dc8dd17
JW		 3785 }
3786}
3787
dcd709e0 3788/* RISC-V pseudo-ops table. */
e23eba97
NC		 3789static const pseudo_typeS riscv_pseudo_table[] =
3790{
e23eba97
NC		 3791 {"option", s_riscv_option, 0},
3792 {"half", cons, 2},
3793 {"word", cons, 4},
3794 {"dword", cons, 8},
3795 {"dtprelword", s_dtprel, 4},
3796 {"dtpreldword", s_dtprel, 8},
3797 {"bss", s_bss, 0},
e23eba97
NC		 3798 {"uleb128", s_riscv_leb128, 0},
3799 {"sleb128", s_riscv_leb128, 1},
0e35537d 3800 {"insn", s_riscv_insn, 0},
2dc8dd17 3801 {"attribute", s_riscv_attribute, 0},
e23eba97
NC		 3802
3803 { NULL, NULL, 0 },
3804};
3805
3806void
3807riscv_pop_insert (void)
3808{
3809 extern void pop_insert (const pseudo_typeS *);
3810
3811 pop_insert (riscv_pseudo_table);
3812}
GDB Binutils - Deliverables
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