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[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
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e23eba97 1/* tc-riscv.c -- RISC-V assembler
b3adc24a 2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
1080bf78 32#include "bfd/elfxx-riscv.h"
e23eba97
NC		 33#include "elf/riscv.h"
34#include "opcode/riscv.h"
35
36#include <stdint.h>
37
38/* Information about an instruction, including its format, operands
39 and fixups. */
40struct riscv_cl_insn
41{
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode *insn_mo;
44
45 /* The encoded instruction bits. */
46 insn_t insn_opcode;
47
48 /* The frag that contains the instruction. */
49 struct frag *frag;
50
51 /* The offset into FRAG of the first instruction byte. */
52 long where;
53
54 /* The relocs associated with the instruction, if any. */
55 fixS *fixp;
56};
57
58#ifndef DEFAULT_ARCH
59#define DEFAULT_ARCH "riscv64"
60#endif
61
2dc8dd17
JW		 62#ifndef DEFAULT_RISCV_ATTR
63#define DEFAULT_RISCV_ATTR 0
64#endif
65
8f595e9b
NC		 66/* Let riscv_after_parse_args set the default value according to xlen. */
67
68#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
70#endif
71
72/* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
77
78#ifndef DEFAULT_RISCV_ISA_SPEC
79#define DEFAULT_RISCV_ISA_SPEC "2.2"
80#endif
81
82#ifndef DEFAULT_RISCV_PRIV_SPEC
83#define DEFAULT_RISCV_PRIV_SPEC "1.11"
84#endif
85
e23eba97 86static const char default_arch[] = DEFAULT_ARCH;
8f595e9b
NC		 87static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
88static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
89static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
e23eba97 90
2922d21d
AW		 91static unsigned xlen = 0; /* width of an x-register */
92static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
7f999549 93static bfd_boolean rve_abi = FALSE;
6e1605e4
NC		 94enum float_abi {
95 FLOAT_ABI_DEFAULT = -1,
96 FLOAT_ABI_SOFT,
97 FLOAT_ABI_SINGLE,
98 FLOAT_ABI_DOUBLE,
99 FLOAT_ABI_QUAD
100};
101static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
e23eba97 102
2922d21d 103#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
e23eba97
NC		 104#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
105
106static unsigned elf_flags = 0;
107
8f595e9b
NC		 108/* Set the default_isa_spec. Return 0 if the input spec string isn't
109 supported. Otherwise, return 1. */
110
111static int
112riscv_set_default_isa_spec (const char *s)
113{
114 enum riscv_isa_spec_class class;
115 if (!riscv_get_isa_spec_class (s, &class))
116 {
117 as_bad ("Unknown default ISA spec `%s' set by "
118 "-misa-spec or --with-isa-spec", s);
119 return 0;
120 }
121 else
122 default_isa_spec = class;
123 return 1;
124}
125
126/* Set the default_priv_spec, assembler will find the suitable CSR address
127 according to default_priv_spec. We will try to check priv attributes if
128 the input string is NULL. Return 0 if the input priv spec string isn't
129 supported. Otherwise, return 1. */
130
131static int
132riscv_set_default_priv_spec (const char *s)
133{
134 enum riscv_priv_spec_class class;
135 unsigned major, minor, revision;
136 obj_attribute *attr;
8f595e9b
NC		 137
138 /* Find the corresponding priv spec class. */
139 if (riscv_get_priv_spec_class (s, &class))
140 {
141 default_priv_spec = class;
142 return 1;
143 }
144
145 if (s != NULL)
146 {
147 as_bad (_("Unknown default privilege spec `%s' set by "
148 "-mpriv-spec or --with-priv-spec"), s);
149 return 0;
150 }
151
152 /* Try to set the default_priv_spec according to the priv attributes. */
153 attr = elf_known_obj_attributes_proc (stdoutput);
154 major = (unsigned) attr[Tag_RISCV_priv_spec].i;
155 minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
156 revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
157
39ff0b81
NC		 158 if (riscv_get_priv_spec_class_from_numbers (major,
159 minor,
160 revision,
161 &class))
8f595e9b 162 {
39ff0b81
NC		 163 /* The priv attributes setting 0.0.0 is meaningless. We should have set
164 the default_priv_spec by md_parse_option and riscv_after_parse_args,
165 so just skip the following setting. */
166 if (class == PRIV_SPEC_CLASS_NONE)
167 return 1;
8f595e9b 168
8f595e9b 169 default_priv_spec = class;
8f595e9b
NC		 170 return 1;
171 }
172
173 /* Still can not find the priv spec class. */
ddc73fa9 174 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
8f595e9b 175 "privilege attributes"), major, minor, revision);
8f595e9b
NC		 176 return 0;
177}
178
e23eba97
NC		 179/* This is the set of options which the .option pseudo-op may modify. */
180
181struct riscv_set_options
182{
183 int pic; /* Generate position-independent code. */
184 int rvc; /* Generate RVC code. */
7f999549 185 int rve; /* Generate RVE code. */
45f76423 186 int relax; /* Emit relocs the linker is allowed to relax. */
2dc8dd17 187 int arch_attr; /* Emit arch attribute. */
2ca89224 188 int csr_check; /* Enable the CSR checking. */
e23eba97
NC		 189};
190
191static struct riscv_set_options riscv_opts =
192{
193 0, /* pic */
194 0, /* rvc */
7f999549 195 0, /* rve */
45f76423 196 1, /* relax */
2dc8dd17 197 DEFAULT_RISCV_ATTR, /* arch_attr */
2ca89224 198 0. /* csr_check */
e23eba97
NC		 199};
200
201static void
202riscv_set_rvc (bfd_boolean rvc_value)
203{
204 if (rvc_value)
205 elf_flags |= EF_RISCV_RVC;
206
207 riscv_opts.rvc = rvc_value;
208}
209
7f999549
JW		 210static void
211riscv_set_rve (bfd_boolean rve_value)
212{
213 riscv_opts.rve = rve_value;
214}
215
1080bf78 216static riscv_subset_list_t riscv_subsets;
e23eba97
NC		 217
218static bfd_boolean
1080bf78 219riscv_subset_supports (const char *feature)
e23eba97 220{
dfe92496
NC		 221 struct riscv_subset_t *subset;
222
1080bf78
JW		 223 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
224 return TRUE;
e23eba97 225
dfe92496 226 return riscv_lookup_subset (&riscv_subsets, feature, &subset);
e23eba97
NC		 227}
228
43135d3b 229static bfd_boolean
7e9ad3a3 230riscv_multi_subset_supports (enum riscv_insn_class insn_class)
43135d3b 231{
7e9ad3a3
JW		 232 switch (insn_class)
233 {
234 case INSN_CLASS_I: return riscv_subset_supports ("i");
235 case INSN_CLASS_C: return riscv_subset_supports ("c");
236 case INSN_CLASS_A: return riscv_subset_supports ("a");
237 case INSN_CLASS_M: return riscv_subset_supports ("m");
238 case INSN_CLASS_F: return riscv_subset_supports ("f");
239 case INSN_CLASS_D: return riscv_subset_supports ("d");
240 case INSN_CLASS_D_AND_C:
241 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
242
243 case INSN_CLASS_F_AND_C:
244 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
43135d3b 245
7e9ad3a3 246 case INSN_CLASS_Q: return riscv_subset_supports ("q");
43135d3b 247
7e9ad3a3
JW		 248 default:
249 as_fatal ("Unreachable");
250 return FALSE;
251 }
43135d3b
JW		 252}
253
8f595e9b 254/* Handle of the extension with version hash table. */
629310ab 255static htab_t ext_version_hash = NULL;
8f595e9b 256
629310ab 257static htab_t
8f595e9b
NC		 258init_ext_version_hash (const struct riscv_ext_version *table)
259{
260 int i = 0;
629310ab 261 htab_t hash = str_htab_create ();
8f595e9b
NC		 262
263 while (table[i].name)
264 {
265 const char *name = table[i].name;
fe0e921f
AM		 266 if (str_hash_insert (hash, name, &table[i], 0) != NULL)
267 as_fatal (_("duplicate %s"), name);
8f595e9b
NC		 268
269 i++;
270 while (table[i].name
271 && strcmp (table[i].name, name) == 0)
272 i++;
273 }
274
275 return hash;
276}
277
278static void
279riscv_get_default_ext_version (const char *name,
7ef19aa6
NC		 280 int *major_version,
281 int *minor_version)
8f595e9b
NC		 282{
283 struct riscv_ext_version *ext;
284
8f595e9b
NC		 285 if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
286 return;
287
629310ab 288 ext = (struct riscv_ext_version *) str_hash_find (ext_version_hash, name);
8f595e9b 289 while (ext
7ef19aa6
NC		 290 && ext->name
291 && strcmp (ext->name, name) == 0)
8f595e9b
NC		 292 {
293 if (ext->isa_spec_class == default_isa_spec)
7ef19aa6
NC		 294 {
295 *major_version = ext->major_version;
296 *minor_version = ext->minor_version;
297 return;
298 }
8f595e9b
NC		 299 ext++;
300 }
301}
302
2922d21d 303/* Set which ISA and extensions are available. */
e23eba97 304
e23eba97 305static void
2922d21d 306riscv_set_arch (const char *s)
e23eba97 307{
1080bf78
JW		 308 riscv_parse_subset_t rps;
309 rps.subset_list = &riscv_subsets;
7ef19aa6 310 rps.error_handler = as_bad;
1080bf78 311 rps.xlen = &xlen;
8f595e9b
NC		 312 rps.get_default_version = riscv_get_default_ext_version;
313
314 if (s == NULL)
315 return;
7f999549 316
1080bf78
JW		 317 riscv_release_subset_list (&riscv_subsets);
318 riscv_parse_subset (&rps, s);
e23eba97
NC		 319}
320
6e1605e4
NC		 321/* Indicate -mabi= option is explictly set. */
322static bfd_boolean explicit_mabi = FALSE;
323
324static void
325riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
326{
327 abi_xlen = new_xlen;
328 float_abi = new_float_abi;
329 rve_abi = rve;
330}
331
332/* If the -mabi option isn't set, then we set the abi according to the arch
333 string. Otherwise, check if there are conflicts between architecture
334 and abi setting. */
335
336static void
337riscv_set_abi_by_arch (void)
338{
339 if (!explicit_mabi)
340 {
341 if (riscv_subset_supports ("q"))
342 riscv_set_abi (xlen, FLOAT_ABI_QUAD, FALSE);
343 else if (riscv_subset_supports ("d"))
344 riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, FALSE);
345 else
346 riscv_set_abi (xlen, FLOAT_ABI_SOFT, FALSE);
347 }
348 else
349 {
350 gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT);
351 if (abi_xlen > xlen)
352 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
353 else if (abi_xlen < xlen)
354 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
355 }
356
357 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
358 elf_flags &= ~EF_RISCV_FLOAT_ABI;
359 elf_flags |= float_abi << 1;
360
361 if (rve_abi)
362 elf_flags |= EF_RISCV_RVE;
363}
364
e23eba97 365/* Handle of the OPCODE hash table. */
629310ab 366static htab_t op_hash = NULL;
e23eba97 367
0e35537d 368/* Handle of the type of .insn hash table. */
629310ab 369static htab_t insn_type_hash = NULL;
0e35537d 370
e23eba97
NC		 371/* This array holds the chars that always start a comment. If the
372 pre-processor is disabled, these aren't very useful */
373const char comment_chars[] = "#";
374
375/* This array holds the chars that only start a comment at the beginning of
376 a line. If the line seems to have the form '# 123 filename'
377 .line and .file directives will appear in the pre-processed output */
378/* Note that input_file.c hand checks for '#' at the beginning of the
379 first line of the input file. This is because the compiler outputs
380 #NO_APP at the beginning of its output. */
381/* Also note that C style comments are always supported. */
382const char line_comment_chars[] = "#";
383
384/* This array holds machine specific line separator characters. */
385const char line_separator_chars[] = ";";
386
387/* Chars that can be used to separate mant from exp in floating point nums */
388const char EXP_CHARS[] = "eE";
389
390/* Chars that mean this number is a floating point constant */
391/* As in 0f12.456 */
392/* or 0d1.2345e12 */
393const char FLT_CHARS[] = "rRsSfFdDxXpP";
394
2dc8dd17
JW		 395/* Indicate we are already assemble any instructions or not. */
396static bfd_boolean start_assemble = FALSE;
397
8f595e9b
NC		 398/* Indicate ELF attributes are explictly set. */
399static bfd_boolean explicit_attr = FALSE;
2dc8dd17 400
1a79004f
NC		 401/* Indicate CSR or priv instructions are explictly used. */
402static bfd_boolean explicit_priv_attr = FALSE;
3fc6c3dc 403
e23eba97
NC		 404/* Macros for encoding relaxation state for RVC branches and far jumps. */
405#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
406 ((relax_substateT) \
407 (0xc0000000 \
408 | ((uncond) ? 1 : 0) \
409 | ((rvc) ? 2 : 0) \
410 | ((length) << 2)))
411#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
412#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
413#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
414#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
415
416/* Is the given value a sign-extended 32-bit value? */
417#define IS_SEXT_32BIT_NUM(x) \
418 (((x) &~ (offsetT) 0x7fffffff) == 0 \
419 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
420
421/* Is the given value a zero-extended 32-bit value? Or a negated one? */
422#define IS_ZEXT_32BIT_NUM(x) \
423 (((x) &~ (offsetT) 0xffffffff) == 0 \
424 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
425
426/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
427 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
428#define INSERT_OPERAND(FIELD, INSN, VALUE) \
429 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
430
431/* Determine if an instruction matches an opcode. */
432#define OPCODE_MATCHES(OPCODE, OP) \
433 (((OPCODE) & MASK_##OP) == MATCH_##OP)
434
435static char *expr_end;
436
437/* The default target format to use. */
438
439const char *
440riscv_target_format (void)
441{
442 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
443}
444
445/* Return the length of instruction INSN. */
446
447static inline unsigned int
448insn_length (const struct riscv_cl_insn *insn)
449{
450 return riscv_insn_length (insn->insn_opcode);
451}
452
453/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
454
455static void
456create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
457{
458 insn->insn_mo = mo;
459 insn->insn_opcode = mo->match;
460 insn->frag = NULL;
461 insn->where = 0;
462 insn->fixp = NULL;
463}
464
465/* Install INSN at the location specified by its "frag" and "where" fields. */
466
467static void
468install_insn (const struct riscv_cl_insn *insn)
469{
470 char *f = insn->frag->fr_literal + insn->where;
471 md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
472}
473
474/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
475 and install the opcode in the new location. */
476
477static void
478move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
479{
480 insn->frag = frag;
481 insn->where = where;
482 if (insn->fixp != NULL)
483 {
484 insn->fixp->fx_frag = frag;
485 insn->fixp->fx_where = where;
486 }
487 install_insn (insn);
488}
489
490/* Add INSN to the end of the output. */
491
492static void
493add_fixed_insn (struct riscv_cl_insn *insn)
494{
495 char *f = frag_more (insn_length (insn));
496 move_insn (insn, frag_now, f - frag_now->fr_literal);
497}
498
499static void
500add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
501 relax_substateT subtype, symbolS *symbol, offsetT offset)
502{
503 frag_grow (max_chars);
504 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
505 frag_var (rs_machine_dependent, max_chars, var,
506 subtype, symbol, offset, NULL);
507}
508
509/* Compute the length of a branch sequence, and adjust the stored length
510 accordingly. If FRAGP is NULL, the worst-case length is returned. */
511
512static unsigned
513relaxed_branch_length (fragS *fragp, asection *sec, int update)
514{
515 int jump, rvc, length = 8;
516
517 if (!fragp)
518 return length;
519
520 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
521 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
522 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
523
524 /* Assume jumps are in range; the linker will catch any that aren't. */
525 length = jump ? 4 : 8;
526
527 if (fragp->fr_symbol != NULL
528 && S_IS_DEFINED (fragp->fr_symbol)
01156111 529 && !S_IS_WEAK (fragp->fr_symbol)
e23eba97
NC		 530 && sec == S_GET_SEGMENT (fragp->fr_symbol))
531 {
532 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
533 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
534 val -= fragp->fr_address + fragp->fr_fix;
535
536 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
537 length = 2;
538 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
539 length = 4;
540 else if (!jump && rvc)
541 length = 6;
542 }
543
544 if (update)
545 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
546
547 return length;
548}
549
0e35537d
JW		 550/* Information about an opcode name, mnemonics and its value. */
551struct opcode_name_t
552{
553 const char *name;
554 unsigned int val;
555};
556
557/* List for all supported opcode name. */
558static const struct opcode_name_t opcode_name_list[] =
559{
560 {"C0", 0x0},
561 {"C1", 0x1},
562 {"C2", 0x2},
563
564 {"LOAD", 0x03},
565 {"LOAD_FP", 0x07},
566 {"CUSTOM_0", 0x0b},
567 {"MISC_MEM", 0x0f},
568 {"OP_IMM", 0x13},
569 {"AUIPC", 0x17},
570 {"OP_IMM_32", 0x1b},
571 /* 48b 0x1f. */
572
573 {"STORE", 0x23},
574 {"STORE_FP", 0x27},
575 {"CUSTOM_1", 0x2b},
576 {"AMO", 0x2f},
577 {"OP", 0x33},
578 {"LUI", 0x37},
579 {"OP_32", 0x3b},
580 /* 64b 0x3f. */
581
582 {"MADD", 0x43},
583 {"MSUB", 0x47},
584 {"NMADD", 0x4f},
585 {"NMSUB", 0x4b},
586 {"OP_FP", 0x53},
587 /*reserved 0x57. */
588 {"CUSTOM_2", 0x5b},
589 /* 48b 0x5f. */
590
591 {"BRANCH", 0x63},
592 {"JALR", 0x67},
593 /*reserved 0x5b. */
594 {"JAL", 0x6f},
595 {"SYSTEM", 0x73},
596 /*reserved 0x77. */
597 {"CUSTOM_3", 0x7b},
598 /* >80b 0x7f. */
599
600 {NULL, 0}
601};
602
603/* Hash table for lookup opcode name. */
629310ab 604static htab_t opcode_names_hash = NULL;
0e35537d
JW		 605
606/* Initialization for hash table of opcode name. */
607static void
608init_opcode_names_hash (void)
609{
0e35537d
JW		 610 const struct opcode_name_t *opcode;
611
612 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
fe0e921f
AM		 613 if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL)
614 as_fatal (_("duplicate %s"), opcode->name);
0e35537d
JW		 615}
616
617/* Find `s` is a valid opcode name or not,
618 return the opcode name info if found. */
619static const struct opcode_name_t *
620opcode_name_lookup (char **s)
621{
622 char *e;
623 char save_c;
624 struct opcode_name_t *o;
625
626 /* Find end of name. */
627 e = *s;
628 if (is_name_beginner (*e))
629 ++e;
630 while (is_part_of_name (*e))
631 ++e;
632
633 /* Terminate name. */
634 save_c = *e;
635 *e = '\0';
636
629310ab 637 o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s);
0e35537d
JW		 638
639 /* Advance to next token if one was recognized. */
640 if (o)
641 *s = e;
642
643 *e = save_c;
644 expr_end = e;
645
646 return o;
647}
648
e23eba97
NC		 649enum reg_class
650{
651 RCLASS_GPR,
652 RCLASS_FPR,
8f595e9b
NC		 653 RCLASS_MAX,
654
655 RCLASS_CSR
e23eba97
NC		 656};
657
629310ab
ML		 658static htab_t reg_names_hash = NULL;
659static htab_t csr_extra_hash = NULL;
e23eba97
NC		 660
661#define ENCODE_REG_HASH(cls, n) \
662 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
663#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
664#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
665
666static void
667hash_reg_name (enum reg_class class, const char *name, unsigned n)
668{
669 void *hash = ENCODE_REG_HASH (class, n);
fe0e921f
AM		 670 if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL)
671 as_fatal (_("duplicate %s"), name);
e23eba97
NC		 672}
673
674static void
675hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
676{
677 unsigned i;
678
679 for (i = 0; i < n; i++)
680 hash_reg_name (class, names[i], i);
681}
682
8f595e9b
NC		 683/* Init hash table csr_extra_hash to handle CSR. */
684static void
685riscv_init_csr_hash (const char *name,
686 unsigned address,
687 enum riscv_csr_class class,
688 enum riscv_priv_spec_class define_version,
689 enum riscv_priv_spec_class abort_version)
690{
691 struct riscv_csr_extra *entry, *pre_entry;
8f595e9b
NC		 692 bfd_boolean need_enrty = TRUE;
693
694 pre_entry = NULL;
629310ab 695 entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
8f595e9b
NC		 696 while (need_enrty && entry != NULL)
697 {
698 if (entry->csr_class == class
699 && entry->address == address
700 && entry->define_version == define_version
701 && entry->abort_version == abort_version)
702 need_enrty = FALSE;
703 pre_entry = entry;
704 entry = entry->next;
705 }
706
707 /* Duplicate setting for the CSR, just return and do nothing. */
708 if (!need_enrty)
709 return;
bd0cf5a6 710
8f595e9b
NC		 711 entry = XNEW (struct riscv_csr_extra);
712 entry->csr_class = class;
713 entry->address = address;
714 entry->define_version = define_version;
715 entry->abort_version = abort_version;
5c505568 716 entry->next = NULL;
8f595e9b
NC		 717
718 /* If the CSR hasn't been inserted in the hash table, then insert it.
719 Otherwise, attach the extra information to the entry which is already
720 in the hash table. */
721 if (pre_entry == NULL)
fe0e921f 722 str_hash_insert (csr_extra_hash, name, entry, 0);
8f595e9b
NC		 723 else
724 pre_entry->next = entry;
725}
bd0cf5a6 726
08ccfccf
NC		 727/* Return the suitable CSR address after checking the ISA dependency and
728 priv spec versions. */
bd0cf5a6 729
08ccfccf
NC		 730static unsigned int
731riscv_csr_address (const char *csr_name,
732 struct riscv_csr_extra *entry)
bd0cf5a6 733{
08ccfccf
NC		 734 struct riscv_csr_extra *saved_entry = entry;
735 enum riscv_csr_class csr_class = entry->csr_class;
736 bfd_boolean need_check_version = TRUE;
8f595e9b
NC		 737 bfd_boolean result = TRUE;
738
8f595e9b 739 switch (csr_class)
bd0cf5a6 740 {
8f595e9b
NC		 741 case CSR_CLASS_I:
742 result = riscv_subset_supports ("i");
743 break;
08ccfccf
NC		 744 case CSR_CLASS_I_32:
745 result = (xlen == 32 && riscv_subset_supports ("i"));
746 break;
8f595e9b
NC		 747 case CSR_CLASS_F:
748 result = riscv_subset_supports ("f");
08ccfccf 749 need_check_version = FALSE;
8f595e9b 750 break;
08ccfccf
NC		 751 case CSR_CLASS_DEBUG:
752 need_check_version = FALSE;
8f595e9b
NC		 753 break;
754 default:
755 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
bd0cf5a6
NC		 756 }
757
08ccfccf
NC		 758 /* Don't report the ISA conflict when -mcsr-check isn't set. */
759 if (riscv_opts.csr_check && !result)
760 as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name);
8f595e9b
NC		 761
762 while (entry != NULL)
bd0cf5a6 763 {
08ccfccf
NC		 764 if (!need_check_version
765 || (default_priv_spec >= entry->define_version
766 && default_priv_spec < entry->abort_version))
8f595e9b
NC		 767 {
768 /* Find the suitable CSR according to the specific version. */
08ccfccf 769 return entry->address;
8f595e9b
NC		 770 }
771 entry = entry->next;
772 }
bd0cf5a6 773
8f595e9b
NC		 774 /* We can not find the suitable CSR address according to the privilege
775 version. Therefore, we use the last defined value. Report the warning
776 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
777 otherwise, you may get the unexpected CSR address. */
778 if (riscv_opts.csr_check)
779 {
780 const char *priv_name = riscv_get_priv_spec_name (default_priv_spec);
781
782 if (priv_name != NULL)
783 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
784 csr_name, priv_name);
bd0cf5a6 785 }
08ccfccf
NC		 786
787 return saved_entry->address;
bd0cf5a6
NC		 788}
789
8f595e9b
NC		 790/* Once the CSR is defined, including the old privilege spec, then we call
791 riscv_csr_class_check and riscv_csr_version_check to do the further checking
792 and get the corresponding address. Return -1 if the CSR is never been
793 defined. Otherwise, return the address. */
bd0cf5a6 794
8f595e9b 795static unsigned int
bd0cf5a6
NC		 796reg_csr_lookup_internal (const char *s)
797{
798 struct riscv_csr_extra *r =
629310ab 799 (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s);
bd0cf5a6
NC		 800
801 if (r == NULL)
8f595e9b 802 return -1U;
bd0cf5a6 803
8f595e9b
NC		 804 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
805 the CSR was defined, but isn't allowed for the current ISA setting or
806 the privilege spec. If the CSR is never been defined, then assembler
807 will regard it as a "Unknown CSR" and report error. If user use number
808 to set the CSR, but over the range (> 0xfff), then assembler will report
809 "Improper CSR" error for it. */
08ccfccf 810 return riscv_csr_address (s, r);
bd0cf5a6
NC		 811}
812
e23eba97
NC		 813static unsigned int
814reg_lookup_internal (const char *s, enum reg_class class)
815{
8f595e9b
NC		 816 void *r;
817
818 if (class == RCLASS_CSR)
819 return reg_csr_lookup_internal (s);
e23eba97 820
629310ab 821 r = str_hash_find (reg_names_hash, s);
e23eba97
NC		 822 if (r == NULL || DECODE_REG_CLASS (r) != class)
823 return -1;
7f999549
JW		 824
825 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
826 return -1;
827
e23eba97
NC		 828 return DECODE_REG_NUM (r);
829}
830
831static bfd_boolean
832reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
833{
834 char *e;
835 char save_c;
836 int reg = -1;
837
838 /* Find end of name. */
839 e = *s;
840 if (is_name_beginner (*e))
841 ++e;
842 while (is_part_of_name (*e))
843 ++e;
844
845 /* Terminate name. */
846 save_c = *e;
847 *e = '\0';
848
849 /* Look for the register. Advance to next token if one was recognized. */
850 if ((reg = reg_lookup_internal (*s, class)) >= 0)
851 *s = e;
852
853 *e = save_c;
854 if (regnop)
855 *regnop = reg;
856 return reg >= 0;
857}
858
859static bfd_boolean
860arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
861{
862 const char *p = strchr (*s, ',');
863 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
864
bfb218e3
JW		 865 if (len == 0)
866 return FALSE;
867
e23eba97
NC		 868 for (i = 0; i < size; i++)
869 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
870 {
871 *regnop = i;
872 *s += len;
873 return TRUE;
874 }
875
876 return FALSE;
877}
878
879/* For consistency checking, verify that all bits are specified either
880 by the match/mask part of the instruction definition, or by the
0e35537d
JW		 881 operand list.
882
883 `length` could be 0, 4 or 8, 0 for auto detection. */
e23eba97 884static bfd_boolean
0e35537d 885validate_riscv_insn (const struct riscv_opcode *opc, int length)
e23eba97
NC		 886{
887 const char *p = opc->args;
888 char c;
889 insn_t used_bits = opc->mask;
0e35537d
JW		 890 int insn_width;
891 insn_t required_bits;
892
893 if (length == 0)
894 insn_width = 8 * riscv_insn_length (opc->match);
895 else
896 insn_width = 8 * length;
897
898 required_bits = ~0ULL >> (64 - insn_width);
e23eba97
NC		 899
900 if ((used_bits & opc->match) != (opc->match & required_bits))
901 {
902 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
903 opc->name, opc->args);
904 return FALSE;
905 }
906
907#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
908 while (*p)
909 switch (c = *p++)
910 {
911 case 'C': /* RVC */
912 switch (c = *p++)
913 {
1d65abb5 914 case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
e23eba97
NC		 915 case 'c': break; /* RS1, constrained to equal sp */
916 case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
1d65abb5 917 case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
b416fe87 918 case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
1d65abb5
AW		 919 case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
920 case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
921 case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
922 case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
923 case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
e23eba97
NC		 924 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
925 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
1d65abb5
AW		 926 case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
927 case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
e23eba97
NC		 928 case 'w': break; /* RS1S, constrained to equal RD */
929 case 'x': break; /* RS2S, constrained to equal RD */
ca0bc150 930 case 'z': break; /* RS2S, contrained to be x0 */
1d65abb5
AW		 931 case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
932 case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
933 case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
934 case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
e23eba97
NC		 935 case 'U': break; /* RS1, constrained to equal RD */
936 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1d65abb5
AW		 937 case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
938 case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
0e35537d
JW		 939 case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
940 case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
e23eba97
NC		 941 case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
942 case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
0e35537d
JW		 943 case 'F': /* funct */
944 switch (c = *p++)
945 {
4765cd61 946 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
0e35537d
JW		 947 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
948 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
4765cd61 949 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
0e35537d
JW		 950 default:
951 as_bad (_("internal: bad RISC-V opcode"
952 " (unknown operand type `CF%c'): %s %s"),
953 c, opc->name, opc->args);
954 return FALSE;
955 }
956 break;
e23eba97
NC		 957 default:
958 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
959 c, opc->name, opc->args);
960 return FALSE;
961 }
962 break;
963 case ',': break;
964 case '(': break;
965 case ')': break;
966 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
967 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
968 case 'A': break;
969 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
970 case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
971 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
972 case 'I': break;
973 case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
974 case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
975 case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */
976 case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
977 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
978 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
979 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
980 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
0e35537d 981 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
e23eba97
NC		 982 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
983 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
984 case 'o':
1d65abb5
AW		 985 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
986 case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
987 case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
988 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
989 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
e925c834 990 case 'z': break;
e23eba97
NC		 991 case '[': break;
992 case ']': break;
993 case '0': break;
f50fabe4 994 case '1': break;
0e35537d
JW		 995 case 'F': /* funct */
996 switch (c = *p++)
997 {
998 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
999 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
1000 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
1001 default:
1002 as_bad (_("internal: bad RISC-V opcode"
1003 " (unknown operand type `F%c'): %s %s"),
1004 c, opc->name, opc->args);
1005 return FALSE;
1006 }
1007 break;
1008 case 'O': /* opcode */
1009 switch (c = *p++)
1010 {
1011 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
1012 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
1013 default:
1014 as_bad (_("internal: bad RISC-V opcode"
1015 " (unknown operand type `F%c'): %s %s"),
1016 c, opc->name, opc->args);
1017 return FALSE;
1018 }
1019 break;
e23eba97
NC		 1020 default:
1021 as_bad (_("internal: bad RISC-V opcode "
1022 "(unknown operand type `%c'): %s %s"),
1023 c, opc->name, opc->args);
1024 return FALSE;
1025 }
1026#undef USE_BITS
1027 if (used_bits != required_bits)
1028 {
1029 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1030 ~(unsigned long)(used_bits & required_bits),
1031 opc->name, opc->args);
1032 return FALSE;
1033 }
1034 return TRUE;
1035}
1036
1037struct percent_op_match
1038{
1039 const char *str;
1040 bfd_reloc_code_real_type reloc;
1041};
1042
0e35537d
JW		 1043/* Common hash table initialization function for
1044 instruction and .insn directive. */
629310ab 1045static htab_t
0e35537d
JW		 1046init_opcode_hash (const struct riscv_opcode *opcodes,
1047 bfd_boolean insn_directive_p)
e23eba97
NC		 1048{
1049 int i = 0;
0e35537d 1050 int length;
629310ab 1051 htab_t hash = str_htab_create ();
0e35537d 1052 while (opcodes[i].name)
e23eba97 1053 {
0e35537d 1054 const char *name = opcodes[i].name;
fe0e921f
AM		 1055 if (str_hash_insert (hash, name, &opcodes[i], 0) != NULL)
1056 as_fatal (_("duplicate %s"), name);
e23eba97
NC		 1057
1058 do
1059 {
0e35537d 1060 if (opcodes[i].pinfo != INSN_MACRO)
e23eba97 1061 {
0e35537d
JW		 1062 if (insn_directive_p)
1063 length = ((name[0] == 'c') ? 2 : 4);
1064 else
1065 length = 0; /* Let assembler determine the length. */
1066 if (!validate_riscv_insn (&opcodes[i], length))
e23eba97
NC		 1067 as_fatal (_("Broken assembler. No assembly attempted."));
1068 }
0e35537d
JW		 1069 else
1070 gas_assert (!insn_directive_p);
e23eba97
NC		 1071 ++i;
1072 }
0e35537d 1073 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
e23eba97
NC		 1074 }
1075
0e35537d
JW		 1076 return hash;
1077}
1078
1079/* This function is called once, at assembler startup time. It should set up
1080 all the tables, etc. that the MD part of the assembler will need. */
1081
1082void
1083md_begin (void)
1084{
1085 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
1086
1087 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
1088 as_warn (_("Could not set architecture and machine"));
1089
1090 op_hash = init_opcode_hash (riscv_opcodes, FALSE);
1091 insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
1092
629310ab 1093 reg_names_hash = str_htab_create ();
e23eba97
NC		 1094 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
1095 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
1096 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
1097 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
b9c04e5a
JW		 1098 /* Add "fp" as an alias for "s0". */
1099 hash_reg_name (RCLASS_GPR, "fp", 8);
1100
bd0cf5a6 1101 /* Create and insert CSR hash tables. */
629310ab 1102 csr_extra_hash = str_htab_create ();
8f595e9b
NC		 1103#define DECLARE_CSR(name, num, class, define_version, abort_version) \
1104 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1105#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1106 DECLARE_CSR(name, num, class, define_version, abort_version);
e23eba97
NC		 1107#include "opcode/riscv-opc.h"
1108#undef DECLARE_CSR
1109
629310ab 1110 opcode_names_hash = str_htab_create ();
bd0cf5a6
NC		 1111 init_opcode_names_hash ();
1112
e23eba97
NC		 1113 /* Set the default alignment for the text section. */
1114 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
1115}
1116
45f76423
AW		 1117static insn_t
1118riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
1119{
1120 switch (reloc_type)
1121 {
1122 case BFD_RELOC_32:
1123 return value;
1124
1125 case BFD_RELOC_RISCV_HI20:
1126 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
1127
1128 case BFD_RELOC_RISCV_LO12_S:
1129 return ENCODE_STYPE_IMM (value);
1130
1131 case BFD_RELOC_RISCV_LO12_I:
1132 return ENCODE_ITYPE_IMM (value);
1133
1134 default:
1135 abort ();
1136 }
1137}
1138
e23eba97
NC		 1139/* Output an instruction. IP is the instruction information.
1140 ADDRESS_EXPR is an operand of the instruction to be used with
1141 RELOC_TYPE. */
1142
1143static void
1144append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
1145 bfd_reloc_code_real_type reloc_type)
1146{
1147 dwarf2_emit_insn (0);
1148
1149 if (reloc_type != BFD_RELOC_UNUSED)
1150 {
1151 reloc_howto_type *howto;
1152
1d65abb5 1153 gas_assert (address_expr);
e23eba97
NC		 1154 if (reloc_type == BFD_RELOC_12_PCREL
1155 || reloc_type == BFD_RELOC_RISCV_JMP)
1156 {
1157 int j = reloc_type == BFD_RELOC_RISCV_JMP;
1158 int best_case = riscv_insn_length (ip->insn_opcode);
1159 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
743f5cfc
JW		 1160
1161 if (now_seg == absolute_section)
1162 {
1163 as_bad (_("relaxable branches not supported in absolute section"));
1164 return;
1165 }
1166
e23eba97
NC		 1167 add_relaxed_insn (ip, worst_case, best_case,
1168 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
1169 address_expr->X_add_symbol,
1170 address_expr->X_add_number);
1171 return;
1172 }
45f76423 1173 else
e23eba97 1174 {
45f76423
AW		 1175 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
1176 if (howto == NULL)
1177 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
e23eba97 1178
45f76423
AW		 1179 ip->fixp = fix_new_exp (ip->frag, ip->where,
1180 bfd_get_reloc_size (howto),
1181 address_expr, FALSE, reloc_type);
e23eba97 1182
45f76423 1183 ip->fixp->fx_tcbit = riscv_opts.relax;
e23eba97 1184 }
e23eba97
NC		 1185 }
1186
e23eba97
NC		 1187 add_fixed_insn (ip);
1188 install_insn (ip);
f77bb6c5
JW		 1189
1190 /* We need to start a new frag after any instruction that can be
1191 optimized away or compressed by the linker during relaxation, to prevent
1192 the assembler from computing static offsets across such an instruction.
1193 This is necessary to get correct EH info. */
b1b11e92 1194 if (reloc_type == BFD_RELOC_RISCV_HI20
f77bb6c5
JW		 1195 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
1196 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
1197 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
1198 {
1199 frag_wane (frag_now);
1200 frag_new (0);
1201 }
e23eba97
NC		 1202}
1203
1204/* Build an instruction created by a macro expansion. This is passed
1205 a pointer to the count of instructions created so far, an
1206 expression, the name of the instruction to build, an operand format
1207 string, and corresponding arguments. */
1208
1209static void
1210macro_build (expressionS *ep, const char *name, const char *fmt, ...)
1211{
1212 const struct riscv_opcode *mo;
1213 struct riscv_cl_insn insn;
1214 bfd_reloc_code_real_type r;
1215 va_list args;
1216
1217 va_start (args, fmt);
1218
1219 r = BFD_RELOC_UNUSED;
629310ab 1220 mo = (struct riscv_opcode *) str_hash_find (op_hash, name);
e23eba97
NC		 1221 gas_assert (mo);
1222
1223 /* Find a non-RVC variant of the instruction. append_insn will compress
1224 it if possible. */
1225 while (riscv_insn_length (mo->match) < 4)
1226 mo++;
1227 gas_assert (strcmp (name, mo->name) == 0);
1228
1229 create_insn (&insn, mo);
1230 for (;;)
1231 {
1232 switch (*fmt++)
1233 {
1234 case 'd':
1235 INSERT_OPERAND (RD, insn, va_arg (args, int));
1236 continue;
1237
1238 case 's':
1239 INSERT_OPERAND (RS1, insn, va_arg (args, int));
1240 continue;
1241
1242 case 't':
1243 INSERT_OPERAND (RS2, insn, va_arg (args, int));
1244 continue;
1245
1246 case '>':
1247 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
1248 continue;
1249
1250 case 'j':
1251 case 'u':
1252 case 'q':
1253 gas_assert (ep != NULL);
1254 r = va_arg (args, int);
1255 continue;
1256
1257 case '\0':
1258 break;
1259 case ',':
1260 continue;
1261 default:
1262 as_fatal (_("internal error: invalid macro"));
1263 }
1264 break;
1265 }
1266 va_end (args);
1267 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1268
1269 append_insn (&insn, ep, r);
1270}
1271
db3b6ecc
KC		 1272/* Build an instruction created by a macro expansion. Like md_assemble but
1273 accept a printf-style format string and arguments. */
1274
1275static void
1276md_assemblef (const char *format, ...)
1277{
1278 char *buf = NULL;
1279 va_list ap;
1280 int r;
1281
1282 va_start (ap, format);
1283
1284 r = vasprintf (&buf, format, ap);
1285
1286 if (r < 0)
1287 as_fatal (_("internal error: vasprintf failed"));
1288
1289 md_assemble (buf);
1290 free(buf);
1291
1292 va_end (ap);
1293}
1294
e23eba97
NC		 1295/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1296 unset. */
1297static void
1298normalize_constant_expr (expressionS *ex)
1299{
1300 if (xlen > 32)
1301 return;
1302 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1303 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1304 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1305 - 0x80000000);
1306}
1307
ca2fd32c
JW		 1308/* Fail if an expression EX is not a constant. IP is the instruction using EX.
1309 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
e23eba97
NC		 1310
1311static void
ca2fd32c
JW		 1312check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
1313 bfd_boolean maybe_csr)
e23eba97
NC		 1314{
1315 if (ex->X_op == O_big)
1316 as_bad (_("unsupported large constant"));
ca2fd32c
JW		 1317 else if (maybe_csr && ex->X_op == O_symbol)
1318 as_bad (_("unknown CSR `%s'"),
1319 S_GET_NAME (ex->X_add_symbol));
e23eba97
NC		 1320 else if (ex->X_op != O_constant)
1321 as_bad (_("Instruction %s requires absolute expression"),
1322 ip->insn_mo->name);
1323 normalize_constant_expr (ex);
1324}
1325
1326static symbolS *
1327make_internal_label (void)
1328{
e01e1cee
AM		 1329 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now,
1330 frag_now_fix ());
e23eba97
NC		 1331}
1332
1333/* Load an entry from the GOT. */
1334static void
1335pcrel_access (int destreg, int tempreg, expressionS *ep,
1336 const char *lo_insn, const char *lo_pattern,
1337 bfd_reloc_code_real_type hi_reloc,
1338 bfd_reloc_code_real_type lo_reloc)
1339{
1340 expressionS ep2;
1341 ep2.X_op = O_symbol;
1342 ep2.X_add_symbol = make_internal_label ();
1343 ep2.X_add_number = 0;
1344
1345 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1346 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1347}
1348
1349static void
1350pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1351 bfd_reloc_code_real_type hi_reloc,
1352 bfd_reloc_code_real_type lo_reloc)
1353{
1354 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1355}
1356
1357static void
1358pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1359 bfd_reloc_code_real_type hi_reloc,
1360 bfd_reloc_code_real_type lo_reloc)
1361{
1362 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1363}
1364
1365/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1366static void
1367riscv_call (int destreg, int tempreg, expressionS *ep,
1368 bfd_reloc_code_real_type reloc)
1369{
b1b11e92
AM		 1370 /* Ensure the jalr is emitted to the same frag as the auipc. */
1371 frag_grow (8);
e23eba97
NC		 1372 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1373 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
b1b11e92
AM		 1374 /* See comment at end of append_insn. */
1375 frag_wane (frag_now);
1376 frag_new (0);
e23eba97
NC		 1377}
1378
1379/* Load an integer constant into a register. */
1380
1381static void
1382load_const (int reg, expressionS *ep)
1383{
1384 int shift = RISCV_IMM_BITS;
4f7cc141 1385 bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1);
e23eba97 1386 expressionS upper = *ep, lower = *ep;
4f7cc141 1387 lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign;
e23eba97
NC		 1388 upper.X_add_number -= lower.X_add_number;
1389
1390 if (ep->X_op != O_constant)
1391 {
1392 as_bad (_("unsupported large constant"));
1393 return;
1394 }
1395
1d65abb5 1396 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
e23eba97
NC		 1397 {
1398 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1399 while (((upper.X_add_number >> shift) & 1) == 0)
1400 shift++;
1401
1402 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1d65abb5 1403 load_const (reg, &upper);
e23eba97 1404
db3b6ecc 1405 md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift);
e23eba97 1406 if (lower.X_add_number != 0)
db3b6ecc
KC		 1407 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg,
1408 lower.X_add_number);
e23eba97
NC		 1409 }
1410 else
1411 {
1412 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1413 int hi_reg = 0;
1414
1415 if (upper.X_add_number != 0)
1416 {
db3b6ecc
KC		 1417 /* Discard low part and zero-extend upper immediate. */
1418 upper_imm = ((uint32_t)upper.X_add_number >> shift);
1419
1420 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm);
e23eba97
NC		 1421 hi_reg = reg;
1422 }
1423
1424 if (lower.X_add_number != 0 || hi_reg == 0)
db3b6ecc
KC		 1425 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg,
1426 lower.X_add_number);
e23eba97
NC		 1427 }
1428}
1429
1430/* Expand RISC-V assembly macros into one or more instructions. */
1431static void
1432macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1433 bfd_reloc_code_real_type *imm_reloc)
1434{
1435 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1436 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1437 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1438 int mask = ip->insn_mo->mask;
1439
1440 switch (mask)
1441 {
1442 case M_LI:
1443 load_const (rd, imm_expr);
1444 break;
1445
1446 case M_LA:
1447 case M_LLA:
1448 /* Load the address of a symbol into a register. */
1449 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1450 as_bad (_("offset too large"));
1451
1452 if (imm_expr->X_op == O_constant)
1453 load_const (rd, imm_expr);
1454 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */
1455 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1456 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1457 else /* Local PIC symbol, or any non-PIC symbol */
1458 pcrel_load (rd, rd, imm_expr, "addi",
1459 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1460 break;
1461
1462 case M_LA_TLS_GD:
1463 pcrel_load (rd, rd, imm_expr, "addi",
1464 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1465 break;
1466
1467 case M_LA_TLS_IE:
1468 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1469 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1470 break;
1471
1472 case M_LB:
1473 pcrel_load (rd, rd, imm_expr, "lb",
1474 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1475 break;
1476
1477 case M_LBU:
1478 pcrel_load (rd, rd, imm_expr, "lbu",
1479 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1480 break;
1481
1482 case M_LH:
1483 pcrel_load (rd, rd, imm_expr, "lh",
1484 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1485 break;
1486
1487 case M_LHU:
1488 pcrel_load (rd, rd, imm_expr, "lhu",
1489 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1490 break;
1491
1492 case M_LW:
1493 pcrel_load (rd, rd, imm_expr, "lw",
1494 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1495 break;
1496
1497 case M_LWU:
1498 pcrel_load (rd, rd, imm_expr, "lwu",
1499 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1500 break;
1501
1502 case M_LD:
1503 pcrel_load (rd, rd, imm_expr, "ld",
1504 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1505 break;
1506
1507 case M_FLW:
1508 pcrel_load (rd, rs1, imm_expr, "flw",
1509 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1510 break;
1511
1512 case M_FLD:
1513 pcrel_load (rd, rs1, imm_expr, "fld",
1514 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1515 break;
1516
1517 case M_SB:
1518 pcrel_store (rs2, rs1, imm_expr, "sb",
1519 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1520 break;
1521
1522 case M_SH:
1523 pcrel_store (rs2, rs1, imm_expr, "sh",
1524 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1525 break;
1526
1527 case M_SW:
1528 pcrel_store (rs2, rs1, imm_expr, "sw",
1529 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1530 break;
1531
1532 case M_SD:
1533 pcrel_store (rs2, rs1, imm_expr, "sd",
1534 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1535 break;
1536
1537 case M_FSW:
1538 pcrel_store (rs2, rs1, imm_expr, "fsw",
1539 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1540 break;
1541
1542 case M_FSD:
1543 pcrel_store (rs2, rs1, imm_expr, "fsd",
1544 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1545 break;
1546
1547 case M_CALL:
1548 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1549 break;
1550
1551 default:
1552 as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
1553 break;
1554 }
1555}
1556
1557static const struct percent_op_match percent_op_utype[] =
1558{
1559 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1560 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
dee35d02 1561 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
e23eba97
NC		 1562 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1563 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1564 {"%hi", BFD_RELOC_RISCV_HI20},
1565 {0, 0}
1566};
1567
1568static const struct percent_op_match percent_op_itype[] =
1569{
1570 {"%lo", BFD_RELOC_RISCV_LO12_I},
1571 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1572 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1573 {0, 0}
1574};
1575
1576static const struct percent_op_match percent_op_stype[] =
1577{
1578 {"%lo", BFD_RELOC_RISCV_LO12_S},
1579 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1580 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1581 {0, 0}
1582};
1583
1584static const struct percent_op_match percent_op_rtype[] =
1585{
1586 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1587 {0, 0}
1588};
1589
f50fabe4
JW		 1590static const struct percent_op_match percent_op_null[] =
1591{
1592 {0, 0}
1593};
1594
e23eba97
NC		 1595/* Return true if *STR points to a relocation operator. When returning true,
1596 move *STR over the operator and store its relocation code in *RELOC.
1597 Leave both *STR and *RELOC alone when returning false. */
1598
1599static bfd_boolean
1600parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1601 const struct percent_op_match *percent_op)
1602{
1603 for ( ; percent_op->str; percent_op++)
1604 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1605 {
1606 int len = strlen (percent_op->str);
1607
1608 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1609 continue;
1610
1611 *str += strlen (percent_op->str);
1612 *reloc = percent_op->reloc;
1613
1614 /* Check whether the output BFD supports this relocation.
1615 If not, issue an error and fall back on something safe. */
45f76423
AW		 1616 if (*reloc != BFD_RELOC_UNUSED
1617 && !bfd_reloc_type_lookup (stdoutput, *reloc))
e23eba97
NC		 1618 {
1619 as_bad ("relocation %s isn't supported by the current ABI",
1620 percent_op->str);
1621 *reloc = BFD_RELOC_UNUSED;
1622 }
1623 return TRUE;
1624 }
1625 return FALSE;
1626}
1627
1628static void
1629my_getExpression (expressionS *ep, char *str)
1630{
1631 char *save_in;
1632
1633 save_in = input_line_pointer;
1634 input_line_pointer = str;
1635 expression (ep);
1636 expr_end = input_line_pointer;
1637 input_line_pointer = save_in;
1638}
1639
1640/* Parse string STR as a 16-bit relocatable operand. Store the
1641 expression in *EP and the relocation, if any, in RELOC.
1642 Return the number of relocation operators used (0 or 1).
1643
1644 On exit, EXPR_END points to the first character after the expression. */
1645
1646static size_t
1647my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1648 char *str, const struct percent_op_match *percent_op)
1649{
1650 size_t reloc_index;
1651 unsigned crux_depth, str_depth, regno;
1652 char *crux;
1653
8970c022
JW		 1654 /* First, check for integer registers. No callers can accept a reg, but
1655 we need to avoid accidentally creating a useless undefined symbol below,
1656 if this is an instruction pattern that can't match. A glibc build fails
1657 if this is removed. */
e23eba97
NC		 1658 if (reg_lookup (&str, RCLASS_GPR, &regno))
1659 {
1660 ep->X_op = O_register;
1661 ep->X_add_number = regno;
8970c022 1662 expr_end = str;
e23eba97
NC		 1663 return 0;
1664 }
1665
1666 /* Search for the start of the main expression.
1667 End the loop with CRUX pointing to the start
1668 of the main expression and with CRUX_DEPTH containing the number
1669 of open brackets at that point. */
1670 reloc_index = -1;
1671 str_depth = 0;
1672 do
1673 {
1674 reloc_index++;
1675 crux = str;
1676 crux_depth = str_depth;
1677
1678 /* Skip over whitespace and brackets, keeping count of the number
1679 of brackets. */
1680 while (*str == ' ' || *str == '\t' || *str == '(')
1681 if (*str++ == '(')
1682 str_depth++;
1683 }
1684 while (*str == '%'
1685 && reloc_index < 1
1686 && parse_relocation (&str, reloc, percent_op));
1687
1688 my_getExpression (ep, crux);
1689 str = expr_end;
1690
1691 /* Match every open bracket. */
1692 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1693 if (*str++ == ')')
1694 crux_depth--;
1695
1696 if (crux_depth > 0)
1697 as_bad ("unclosed '('");
1698
1699 expr_end = str;
1700
1701 return reloc_index;
1702}
1703
0e35537d
JW		 1704/* Parse opcode name, could be an mnemonics or number. */
1705static size_t
1706my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1707 char *str, const struct percent_op_match *percent_op)
1708{
1709 const struct opcode_name_t *o = opcode_name_lookup (&str);
1710
1711 if (o != NULL)
1712 {
1713 ep->X_op = O_constant;
1714 ep->X_add_number = o->val;
1715 return 0;
1716 }
1717
1718 return my_getSmallExpression (ep, reloc, str, percent_op);
1719}
1720
f0531ed6
JW		 1721/* Detect and handle implicitly zero load-store offsets. For example,
1722 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1723 an implicit offset was detected. */
1724
1725static bfd_boolean
89424b1d 1726riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
f0531ed6
JW		 1727{
1728 /* Check whether there is only a single bracketed expression left.
1729 If so, it must be the base register and the constant must be zero. */
1730 if (*s == '(' && strchr (s + 1, '(') == 0)
1731 {
89424b1d
MR		 1732 ep->X_op = O_constant;
1733 ep->X_add_number = 0;
f0531ed6
JW		 1734 return TRUE;
1735 }
1736
1737 return FALSE;
1738}
1739
54b2aec1
NC		 1740/* All RISC-V CSR instructions belong to one of these classes. */
1741
1742enum csr_insn_type
1743{
1744 INSN_NOT_CSR,
1745 INSN_CSRRW,
1746 INSN_CSRRS,
1747 INSN_CSRRC
1748};
1749
1750/* Return which CSR instruction is checking. */
1751
1752static enum csr_insn_type
1753riscv_csr_insn_type (insn_t insn)
1754{
1755 if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
1756 || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
1757 return INSN_CSRRW;
1758 else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
1759 || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
1760 return INSN_CSRRS;
1761 else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
1762 || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
1763 return INSN_CSRRC;
1764 else
1765 return INSN_NOT_CSR;
1766}
1767
1768/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1769 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1770 CSR address is 0x3. */
1771
1772static bfd_boolean
1773riscv_csr_read_only_check (insn_t insn)
1774{
1775 int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
1776 int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
1777 int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
1778 enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
1779
1780 if (readonly
1781 && (((csr_insn == INSN_CSRRS
1782 || csr_insn == INSN_CSRRC)
1783 && rs1 != 0)
1784 || csr_insn == INSN_CSRRW))
1785 return FALSE;
1786
1787 return TRUE;
1788}
1789
1a79004f
NC		 1790/* Return True if it is a privileged instruction. Otherwise, return FALSE.
1791
1792 uret is actually a N-ext instruction. So it is better to regard it as
1793 an user instruction rather than the priv instruction.
1794
1795 hret is used to return from traps in H-mode. H-mode is removed since
1796 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1797 Therefore, hret should be controlled by the hypervisor spec rather than
1798 priv spec in the future.
1799
1800 dret is defined in the debug spec, so it should be checked in the future,
1801 too. */
1802
1803static bfd_boolean
1804riscv_is_priv_insn (insn_t insn)
1805{
1806 return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
1807 || ((insn ^ MATCH_MRET) & MASK_MRET) == 0
1808 || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0
1809 || ((insn ^ MATCH_WFI) & MASK_WFI) == 0
1810 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1811 check it here to keep the compatible. Maybe we should issue warning
1812 if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
1813 We already have a similar check for CSR, but not yet for instructions.
1814 It would be good if we could check the spec versions both for CSR and
1815 instructions, but not here. */
1816 || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
1817}
1818
e23eba97
NC		 1819/* This routine assembles an instruction into its binary format. As a
1820 side effect, it sets the global variable imm_reloc to the type of
1821 relocation to do if one of the operands is an address expression. */
1822
1823static const char *
1824riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
629310ab 1825 bfd_reloc_code_real_type *imm_reloc, htab_t hash)
e23eba97
NC		 1826{
1827 char *s;
1828 const char *args;
1829 char c = 0;
1830 struct riscv_opcode *insn;
1831 char *argsStart;
1832 unsigned int regno;
1833 char save_c = 0;
1834 int argnum;
1835 const struct percent_op_match *p;
1836 const char *error = "unrecognized opcode";
54b2aec1
NC		 1837 /* Indicate we are assembling instruction with CSR. */
1838 bfd_boolean insn_with_csr = FALSE;
e23eba97
NC		 1839
1840 /* Parse the name of the instruction. Terminate the string if whitespace
629310ab 1841 is found so that str_hash_find only sees the name part of the string. */
e23eba97
NC		 1842 for (s = str; *s != '\0'; ++s)
1843 if (ISSPACE (*s))
1844 {
1845 save_c = *s;
1846 *s++ = '\0';
1847 break;
1848 }
1849
629310ab 1850 insn = (struct riscv_opcode *) str_hash_find (hash, str);
e23eba97
NC		 1851
1852 argsStart = s;
1853 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1854 {
1080bf78
JW		 1855 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
1856 continue;
1857
7e9ad3a3 1858 if (!riscv_multi_subset_supports (insn->insn_class))
e23eba97
NC		 1859 continue;
1860
1861 create_insn (ip, insn);
1862 argnum = 1;
1863
1864 imm_expr->X_op = O_absent;
1865 *imm_reloc = BFD_RELOC_UNUSED;
1866 p = percent_op_itype;
1867
1868 for (args = insn->args;; ++args)
1869 {
1870 s += strspn (s, " \t");
1871 switch (*args)
1872 {
1873 case '\0': /* End of args. */
1874 if (insn->pinfo != INSN_MACRO)
1875 {
1876 if (!insn->match_func (insn, ip->insn_opcode))
1877 break;
0e35537d
JW		 1878
1879 /* For .insn, insn->match and insn->mask are 0. */
1880 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
1881 ? ip->insn_opcode
1882 : insn->match) == 2
1883 && !riscv_opts.rvc)
e23eba97 1884 break;
54b2aec1 1885
1a79004f
NC		 1886 if (riscv_is_priv_insn (ip->insn_opcode))
1887 explicit_priv_attr = TRUE;
1888
54b2aec1
NC		 1889 /* Check if we write a read-only CSR by the CSR
1890 instruction. */
1891 if (insn_with_csr
1892 && riscv_opts.csr_check
1893 && !riscv_csr_read_only_check (ip->insn_opcode))
1894 {
1895 /* Restore the character in advance, since we want to
1896 report the detailed warning message here. */
1897 if (save_c)
1898 *(argsStart - 1) = save_c;
1899 as_warn (_("Read-only CSR is written `%s'"), str);
1900 insn_with_csr = FALSE;
1901 }
e23eba97
NC		 1902 }
1903 if (*s != '\0')
1904 break;
1905 /* Successful assembly. */
1906 error = NULL;
54b2aec1 1907 insn_with_csr = FALSE;
e23eba97
NC		 1908 goto out;
1909
1910 case 'C': /* RVC */
1911 switch (*++args)
1912 {
1913 case 's': /* RS1 x8-x15 */
1914 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1915 || !(regno >= 8 && regno <= 15))
1916 break;
1917 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1918 continue;
1919 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1920 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1921 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
1922 break;
1923 continue;
1924 case 't': /* RS2 x8-x15 */
1925 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1926 || !(regno >= 8 && regno <= 15))
1927 break;
1928 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1929 continue;
1930 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1931 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1932 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
1933 break;
1934 continue;
1935 case 'U': /* RS1, constrained to equal RD. */
1936 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1937 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
1938 break;
1939 continue;
1940 case 'V': /* RS2 */
1941 if (!reg_lookup (&s, RCLASS_GPR, &regno))
1942 break;
1943 INSERT_OPERAND (CRS2, *ip, regno);
1944 continue;
1945 case 'c': /* RS1, constrained to equal sp. */
1946 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1947 || regno != X_SP)
1948 break;
1949 continue;
ca0bc150
JW		 1950 case 'z': /* RS2, contrained to equal x0. */
1951 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1952 || regno != 0)
1953 break;
1954 continue;
e23eba97
NC		 1955 case '>':
1956 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1957 || imm_expr->X_op != O_constant
1958 || imm_expr->X_add_number <= 0
1959 || imm_expr->X_add_number >= 64)
1960 break;
1961 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
dc1e8a47 1962 rvc_imm_done:
e23eba97
NC		 1963 s = expr_end;
1964 imm_expr->X_op = O_absent;
1965 continue;
1966 case '<':
1967 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1968 || imm_expr->X_op != O_constant
e23eba97 1969 || imm_expr->X_add_number <= 0
169ec512
AM		 1970 || imm_expr->X_add_number >= 32
1971 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1972 break;
1973 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1974 goto rvc_imm_done;
0e35537d
JW		 1975 case '8':
1976 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1977 || imm_expr->X_op != O_constant
0e35537d 1978 || imm_expr->X_add_number < 0
169ec512
AM		 1979 || imm_expr->X_add_number >= 256
1980 || !VALID_RVC_UIMM8 ((valueT) imm_expr->X_add_number))
0e35537d
JW		 1981 break;
1982 ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
1983 goto rvc_imm_done;
e23eba97
NC		 1984 case 'i':
1985 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1986 || imm_expr->X_op != O_constant
1987 || imm_expr->X_add_number == 0
169ec512 1988 || !VALID_RVC_SIMM3 ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1989 break;
1990 ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
1991 goto rvc_imm_done;
1992 case 'j':
1993 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1994 || imm_expr->X_op != O_constant
1995 || imm_expr->X_add_number == 0
169ec512 1996 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1997 break;
1998 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1999 goto rvc_imm_done;
2000 case 'k':
f0531ed6
JW		 2001 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2002 continue;
e23eba97
NC		 2003 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2004 || imm_expr->X_op != O_constant
169ec512 2005 || !VALID_RVC_LW_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2006 break;
2007 ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
2008 goto rvc_imm_done;
2009 case 'l':
f0531ed6
JW		 2010 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2011 continue;
e23eba97
NC		 2012 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2013 || imm_expr->X_op != O_constant
169ec512 2014 || !VALID_RVC_LD_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2015 break;
2016 ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
2017 goto rvc_imm_done;
2018 case 'm':
f0531ed6
JW		 2019 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2020 continue;
e23eba97
NC		 2021 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2022 || imm_expr->X_op != O_constant
169ec512 2023 || !VALID_RVC_LWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2024 break;
2025 ip->insn_opcode |=
2026 ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
2027 goto rvc_imm_done;
2028 case 'n':
f0531ed6
JW		 2029 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2030 continue;
e23eba97
NC		 2031 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2032 || imm_expr->X_op != O_constant
169ec512 2033 || !VALID_RVC_LDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2034 break;
2035 ip->insn_opcode |=
2036 ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
2037 goto rvc_imm_done;
b416fe87
KC		 2038 case 'o':
2039 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2040 || imm_expr->X_op != O_constant
21a186f2
JW		 2041 /* C.addiw, c.li, and c.andi allow zero immediate.
2042 C.addi allows zero immediate as hint. Otherwise this
2043 is same as 'j'. */
169ec512 2044 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
b416fe87
KC		 2045 break;
2046 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2047 goto rvc_imm_done;
e23eba97
NC		 2048 case 'K':
2049 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2050 || imm_expr->X_op != O_constant
169ec512
AM		 2051 || imm_expr->X_add_number == 0
2052 || !VALID_RVC_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2053 break;
2054 ip->insn_opcode |=
2055 ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
2056 goto rvc_imm_done;
2057 case 'L':
2058 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2059 || imm_expr->X_op != O_constant
169ec512
AM		 2060 || imm_expr->X_add_number == 0
2061 || !VALID_RVC_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2062 break;
2063 ip->insn_opcode |=
2064 ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
2065 goto rvc_imm_done;
2066 case 'M':
f0531ed6
JW		 2067 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2068 continue;
e23eba97
NC		 2069 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2070 || imm_expr->X_op != O_constant
169ec512 2071 || !VALID_RVC_SWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2072 break;
2073 ip->insn_opcode |=
2074 ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
2075 goto rvc_imm_done;
2076 case 'N':
f0531ed6
JW		 2077 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2078 continue;
e23eba97
NC		 2079 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2080 || imm_expr->X_op != O_constant
169ec512 2081 || !VALID_RVC_SDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2082 break;
2083 ip->insn_opcode |=
2084 ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
2085 goto rvc_imm_done;
2086 case 'u':
2087 p = percent_op_utype;
2088 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
2089 break;
dc1e8a47 2090 rvc_lui:
e23eba97
NC		 2091 if (imm_expr->X_op != O_constant
2092 || imm_expr->X_add_number <= 0
2093 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
2094 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
2095 && (imm_expr->X_add_number <
2096 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
2097 break;
2098 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2099 goto rvc_imm_done;
2100 case 'v':
2101 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2102 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
2103 || ((int32_t)imm_expr->X_add_number
2104 != imm_expr->X_add_number))
2105 break;
2106 imm_expr->X_add_number =
2107 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
2108 goto rvc_lui;
2109 case 'p':
2110 goto branch;
2111 case 'a':
2112 goto jump;
0e35537d
JW		 2113 case 'S': /* Floating-point RS1 x8-x15. */
2114 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2115 || !(regno >= 8 && regno <= 15))
2116 break;
2117 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2118 continue;
e23eba97
NC		 2119 case 'D': /* Floating-point RS2 x8-x15. */
2120 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2121 || !(regno >= 8 && regno <= 15))
2122 break;
2123 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2124 continue;
2125 case 'T': /* Floating-point RS2. */
2126 if (!reg_lookup (&s, RCLASS_FPR, &regno))
2127 break;
2128 INSERT_OPERAND (CRS2, *ip, regno);
2129 continue;
0e35537d
JW		 2130 case 'F':
2131 switch (*++args)
2132 {
4765cd61
JW		 2133 case '6':
2134 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2135 || imm_expr->X_op != O_constant
2136 || imm_expr->X_add_number < 0
2137 || imm_expr->X_add_number >= 64)
2138 {
2139 as_bad (_("bad value for funct6 field, "
2140 "value must be 0...64"));
2141 break;
2142 }
2143
2144 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
2145 imm_expr->X_op = O_absent;
2146 s = expr_end;
2147 continue;
0e35537d
JW		 2148 case '4':
2149 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2150 || imm_expr->X_op != O_constant
2151 || imm_expr->X_add_number < 0
2152 || imm_expr->X_add_number >= 16)
2153 {
2154 as_bad (_("bad value for funct4 field, "
2155 "value must be 0...15"));
2156 break;
2157 }
2158
2159 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
2160 imm_expr->X_op = O_absent;
2161 s = expr_end;
2162 continue;
2163 case '3':
2164 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2165 || imm_expr->X_op != O_constant
2166 || imm_expr->X_add_number < 0
2167 || imm_expr->X_add_number >= 8)
2168 {
2169 as_bad (_("bad value for funct3 field, "
2170 "value must be 0...7"));
2171 break;
2172 }
2173 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
2174 imm_expr->X_op = O_absent;
2175 s = expr_end;
2176 continue;
4765cd61
JW		 2177 case '2':
2178 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2179 || imm_expr->X_op != O_constant
2180 || imm_expr->X_add_number < 0
2181 || imm_expr->X_add_number >= 4)
2182 {
2183 as_bad (_("bad value for funct2 field, "
2184 "value must be 0...3"));
2185 break;
2186 }
2187 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number);
2188 imm_expr->X_op = O_absent;
2189 s = expr_end;
2190 continue;
0e35537d
JW		 2191 default:
2192 as_bad (_("bad compressed FUNCT field"
2193 " specifier 'CF%c'\n"),
2194 *args);
2195 }
2196 break;
2197
e23eba97
NC		 2198 default:
2199 as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
2200 }
2201 break;
2202
2203 case ',':
2204 ++argnum;
2205 if (*s++ == *args)
2206 continue;
2207 s--;
2208 break;
2209
2210 case '(':
2211 case ')':
2212 case '[':
2213 case ']':
2214 if (*s++ == *args)
2215 continue;
2216 break;
2217
2218 case '<': /* Shift amount, 0 - 31. */
2219 my_getExpression (imm_expr, s);
ca2fd32c 2220 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2221 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2222 as_bad (_("Improper shift amount (%lu)"),
2223 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2224 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
2225 imm_expr->X_op = O_absent;
2226 s = expr_end;
2227 continue;
2228
2229 case '>': /* Shift amount, 0 - (XLEN-1). */
2230 my_getExpression (imm_expr, s);
ca2fd32c 2231 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2232 if ((unsigned long) imm_expr->X_add_number >= xlen)
94f78a77
AW		 2233 as_bad (_("Improper shift amount (%lu)"),
2234 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2235 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
2236 imm_expr->X_op = O_absent;
2237 s = expr_end;
2238 continue;
2239
2240 case 'Z': /* CSRRxI immediate. */
2241 my_getExpression (imm_expr, s);
ca2fd32c 2242 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2243 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2244 as_bad (_("Improper CSRxI immediate (%lu)"),
2245 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2246 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
2247 imm_expr->X_op = O_absent;
2248 s = expr_end;
2249 continue;
2250
2251 case 'E': /* Control register. */
54b2aec1 2252 insn_with_csr = TRUE;
1a79004f 2253 explicit_priv_attr = TRUE;
e23eba97
NC		 2254 if (reg_lookup (&s, RCLASS_CSR, &regno))
2255 INSERT_OPERAND (CSR, *ip, regno);
2256 else
2257 {
2258 my_getExpression (imm_expr, s);
ca2fd32c 2259 check_absolute_expr (ip, imm_expr, TRUE);
e23eba97 2260 if ((unsigned long) imm_expr->X_add_number > 0xfff)
94f78a77
AW		 2261 as_bad (_("Improper CSR address (%lu)"),
2262 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2263 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
2264 imm_expr->X_op = O_absent;
2265 s = expr_end;
2266 }
2267 continue;
2268
2269 case 'm': /* Rounding mode. */
2270 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
2271 {
2272 INSERT_OPERAND (RM, *ip, regno);
2273 continue;
2274 }
2275 break;
2276
2277 case 'P':
2278 case 'Q': /* Fence predecessor/successor. */
2279 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
2280 &regno))
2281 {
2282 if (*args == 'P')
2283 INSERT_OPERAND (PRED, *ip, regno);
2284 else
2285 INSERT_OPERAND (SUCC, *ip, regno);
2286 continue;
2287 }
2288 break;
2289
2290 case 'd': /* Destination register. */
2291 case 's': /* Source register. */
2292 case 't': /* Target register. */
0e35537d 2293 case 'r': /* rs3. */
e23eba97
NC		 2294 if (reg_lookup (&s, RCLASS_GPR, &regno))
2295 {
2296 c = *args;
2297 if (*s == ' ')
2298 ++s;
2299
2300 /* Now that we have assembled one operand, we use the args
2301 string to figure out where it goes in the instruction. */
2302 switch (c)
2303 {
2304 case 's':
2305 INSERT_OPERAND (RS1, *ip, regno);
2306 break;
2307 case 'd':
2308 INSERT_OPERAND (RD, *ip, regno);
2309 break;
2310 case 't':
2311 INSERT_OPERAND (RS2, *ip, regno);
2312 break;
0e35537d
JW		 2313 case 'r':
2314 INSERT_OPERAND (RS3, *ip, regno);
2315 break;
e23eba97
NC		 2316 }
2317 continue;
2318 }
2319 break;
2320
2321 case 'D': /* Floating point rd. */
2322 case 'S': /* Floating point rs1. */
2323 case 'T': /* Floating point rs2. */
2324 case 'U': /* Floating point rs1 and rs2. */
2325 case 'R': /* Floating point rs3. */
2326 if (reg_lookup (&s, RCLASS_FPR, &regno))
2327 {
2328 c = *args;
2329 if (*s == ' ')
2330 ++s;
2331 switch (c)
2332 {
2333 case 'D':
2334 INSERT_OPERAND (RD, *ip, regno);
2335 break;
2336 case 'S':
2337 INSERT_OPERAND (RS1, *ip, regno);
2338 break;
2339 case 'U':
2340 INSERT_OPERAND (RS1, *ip, regno);
2341 /* fallthru */
2342 case 'T':
2343 INSERT_OPERAND (RS2, *ip, regno);
2344 break;
2345 case 'R':
2346 INSERT_OPERAND (RS3, *ip, regno);
2347 break;
2348 }
2349 continue;
2350 }
2351
2352 break;
2353
2354 case 'I':
2355 my_getExpression (imm_expr, s);
2356 if (imm_expr->X_op != O_big
2357 && imm_expr->X_op != O_constant)
2358 break;
2359 normalize_constant_expr (imm_expr);
2360 s = expr_end;
2361 continue;
2362
2363 case 'A':
2364 my_getExpression (imm_expr, s);
2365 normalize_constant_expr (imm_expr);
2366 /* The 'A' format specifier must be a symbol. */
2367 if (imm_expr->X_op != O_symbol)
2368 break;
2369 *imm_reloc = BFD_RELOC_32;
2370 s = expr_end;
2371 continue;
2372
160d1b3d
SH		 2373 case 'B':
2374 my_getExpression (imm_expr, s);
2375 normalize_constant_expr (imm_expr);
2376 /* The 'B' format specifier must be a symbol or a constant. */
2377 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
2378 break;
2379 if (imm_expr->X_op == O_symbol)
2380 *imm_reloc = BFD_RELOC_32;
2381 s = expr_end;
2382 continue;
2383
e23eba97 2384 case 'j': /* Sign-extended immediate. */
e23eba97 2385 p = percent_op_itype;
f50fabe4 2386 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
e23eba97
NC		 2387 goto alu_op;
2388 case 'q': /* Store displacement. */
2389 p = percent_op_stype;
2390 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
2391 goto load_store;
2392 case 'o': /* Load displacement. */
2393 p = percent_op_itype;
2394 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
2395 goto load_store;
f50fabe4 2396 case '1': /* 4-operand add, must be %tprel_add. */
e23eba97 2397 p = percent_op_rtype;
f50fabe4
JW		 2398 goto alu_op;
2399 case '0': /* AMO "displacement," which must be zero. */
2400 p = percent_op_null;
dc1e8a47 2401 load_store:
f0531ed6 2402 if (riscv_handle_implicit_zero_offset (imm_expr, s))
e23eba97 2403 continue;
dc1e8a47 2404 alu_op:
e23eba97
NC		 2405 /* If this value won't fit into a 16 bit offset, then go
2406 find a macro that will generate the 32 bit offset
2407 code pattern. */
2408 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
2409 {
2410 normalize_constant_expr (imm_expr);
2411 if (imm_expr->X_op != O_constant
2412 || (*args == '0' && imm_expr->X_add_number != 0)
f50fabe4 2413 || (*args == '1')
e23eba97
NC		 2414 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
2415 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
2416 break;
2417 }
2418
2419 s = expr_end;
2420 continue;
2421
2422 case 'p': /* PC-relative offset. */
dc1e8a47 2423 branch:
e23eba97
NC		 2424 *imm_reloc = BFD_RELOC_12_PCREL;
2425 my_getExpression (imm_expr, s);
2426 s = expr_end;
2427 continue;
2428
2429 case 'u': /* Upper 20 bits. */
2430 p = percent_op_utype;
4288405d 2431 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
e23eba97 2432 {
4288405d
JW		 2433 if (imm_expr->X_op != O_constant)
2434 break;
2435
e23eba97
NC		 2436 if (imm_expr->X_add_number < 0
2437 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
2438 as_bad (_("lui expression not in range 0..1048575"));
2439
2440 *imm_reloc = BFD_RELOC_RISCV_HI20;
2441 imm_expr->X_add_number <<= RISCV_IMM_BITS;
2442 }
2443 s = expr_end;
2444 continue;
2445
2446 case 'a': /* 20-bit PC-relative offset. */
dc1e8a47 2447 jump:
e23eba97
NC		 2448 my_getExpression (imm_expr, s);
2449 s = expr_end;
2450 *imm_reloc = BFD_RELOC_RISCV_JMP;
2451 continue;
2452
2453 case 'c':
2454 my_getExpression (imm_expr, s);
2455 s = expr_end;
2456 if (strcmp (s, "@plt") == 0)
2457 {
2458 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2459 s += 4;
2460 }
2461 else
2462 *imm_reloc = BFD_RELOC_RISCV_CALL;
2463 continue;
0e35537d
JW		 2464 case 'O':
2465 switch (*++args)
2466 {
2467 case '4':
2468 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2469 || imm_expr->X_op != O_constant
2470 || imm_expr->X_add_number < 0
2471 || imm_expr->X_add_number >= 128
2472 || (imm_expr->X_add_number & 0x3) != 3)
2473 {
2474 as_bad (_("bad value for opcode field, "
2475 "value must be 0...127 and "
2476 "lower 2 bits must be 0x3"));
2477 break;
2478 }
2479
2480 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2481 imm_expr->X_op = O_absent;
2482 s = expr_end;
2483 continue;
2484 case '2':
2485 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2486 || imm_expr->X_op != O_constant
2487 || imm_expr->X_add_number < 0
2488 || imm_expr->X_add_number >= 3)
2489 {
2490 as_bad (_("bad value for opcode field, "
2491 "value must be 0...2"));
2492 break;
2493 }
2494
2495 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2496 imm_expr->X_op = O_absent;
2497 s = expr_end;
2498 continue;
2499 default:
2500 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args);
2501 }
2502 break;
2503
2504 case 'F':
2505 switch (*++args)
2506 {
2507 case '7':
2508 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2509 || imm_expr->X_op != O_constant
2510 || imm_expr->X_add_number < 0
2511 || imm_expr->X_add_number >= 128)
2512 {
2513 as_bad (_("bad value for funct7 field, "
2514 "value must be 0...127"));
2515 break;
2516 }
2517
2518 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2519 imm_expr->X_op = O_absent;
2520 s = expr_end;
2521 continue;
2522 case '3':
2523 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2524 || imm_expr->X_op != O_constant
2525 || imm_expr->X_add_number < 0
2526 || imm_expr->X_add_number >= 8)
2527 {
2528 as_bad (_("bad value for funct3 field, "
2529 "value must be 0...7"));
2530 break;
2531 }
2532
2533 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2534 imm_expr->X_op = O_absent;
2535 s = expr_end;
2536 continue;
2537 case '2':
2538 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2539 || imm_expr->X_op != O_constant
2540 || imm_expr->X_add_number < 0
2541 || imm_expr->X_add_number >= 4)
2542 {
2543 as_bad (_("bad value for funct2 field, "
2544 "value must be 0...3"));
2545 break;
2546 }
2547
2548 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2549 imm_expr->X_op = O_absent;
2550 s = expr_end;
2551 continue;
2552
2553 default:
2554 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args);
2555 }
2556 break;
e23eba97 2557
e925c834
JW		 2558 case 'z':
2559 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2560 || imm_expr->X_op != O_constant
2561 || imm_expr->X_add_number != 0)
2562 break;
2563 s = expr_end;
2564 imm_expr->X_op = O_absent;
2565 continue;
2566
e23eba97
NC		 2567 default:
2568 as_fatal (_("internal error: bad argument type %c"), *args);
2569 }
2570 break;
2571 }
2572 s = argsStart;
2573 error = _("illegal operands");
54b2aec1 2574 insn_with_csr = FALSE;
e23eba97
NC		 2575 }
2576
dc1e8a47 2577 out:
e23eba97
NC		 2578 /* Restore the character we might have clobbered above. */
2579 if (save_c)
2580 *(argsStart - 1) = save_c;
2581
2582 return error;
2583}
2584
2585void
2586md_assemble (char *str)
2587{
2588 struct riscv_cl_insn insn;
2589 expressionS imm_expr;
2590 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2591
8f595e9b
NC		 2592 /* The arch and priv attributes should be set before assembling. */
2593 if (!start_assemble)
2594 {
2595 start_assemble = TRUE;
6e1605e4 2596 riscv_set_abi_by_arch ();
e23eba97 2597
8f595e9b
NC		 2598 /* Set the default_priv_spec according to the priv attributes. */
2599 if (!riscv_set_default_priv_spec (NULL))
2600 return;
2601 }
2602
2603 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
2dc8dd17 2604
e23eba97
NC		 2605 if (error)
2606 {
2607 as_bad ("%s `%s'", error, str);
2608 return;
2609 }
2610
2611 if (insn.insn_mo->pinfo == INSN_MACRO)
2612 macro (&insn, &imm_expr, &imm_reloc);
2613 else
2614 append_insn (&insn, &imm_expr, imm_reloc);
2615}
2616
2617const char *
2618md_atof (int type, char *litP, int *sizeP)
2619{
2620 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2621}
2622
2623void
2624md_number_to_chars (char *buf, valueT val, int n)
2625{
2626 number_to_chars_littleendian (buf, val, n);
2627}
2628
2629const char *md_shortopts = "O::g::G:";
2630
2631enum options
2632{
2922d21d 2633 OPTION_MARCH = OPTION_MD_BASE,
e23eba97
NC		 2634 OPTION_PIC,
2635 OPTION_NO_PIC,
2922d21d 2636 OPTION_MABI,
71060565
JW		 2637 OPTION_RELAX,
2638 OPTION_NO_RELAX,
2dc8dd17
JW		 2639 OPTION_ARCH_ATTR,
2640 OPTION_NO_ARCH_ATTR,
2ca89224
NC		 2641 OPTION_CSR_CHECK,
2642 OPTION_NO_CSR_CHECK,
8f595e9b
NC		 2643 OPTION_MISA_SPEC,
2644 OPTION_MPRIV_SPEC,
e23eba97
NC		 2645 OPTION_END_OF_ENUM
2646};
2647
2648struct option md_longopts[] =
2649{
e23eba97
NC		 2650 {"march", required_argument, NULL, OPTION_MARCH},
2651 {"fPIC", no_argument, NULL, OPTION_PIC},
2652 {"fpic", no_argument, NULL, OPTION_PIC},
2653 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2922d21d 2654 {"mabi", required_argument, NULL, OPTION_MABI},
71060565
JW		 2655 {"mrelax", no_argument, NULL, OPTION_RELAX},
2656 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2dc8dd17
JW		 2657 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
2658 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
2ca89224
NC		 2659 {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
2660 {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
8f595e9b
NC		 2661 {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
2662 {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
e23eba97
NC		 2663
2664 {NULL, no_argument, NULL, 0}
2665};
2666size_t md_longopts_size = sizeof (md_longopts);
2667
e23eba97
NC		 2668int
2669md_parse_option (int c, const char *arg)
2670{
2671 switch (c)
2672 {
e23eba97 2673 case OPTION_MARCH:
8f595e9b
NC		 2674 /* riscv_after_parse_args will call riscv_set_arch to parse
2675 the architecture. */
2676 default_arch_with_ext = arg;
e23eba97
NC		 2677 break;
2678
2679 case OPTION_NO_PIC:
2680 riscv_opts.pic = FALSE;
2681 break;
2682
2683 case OPTION_PIC:
2684 riscv_opts.pic = TRUE;
2685 break;
2686
2922d21d
AW		 2687 case OPTION_MABI:
2688 if (strcmp (arg, "ilp32") == 0)
7f999549
JW		 2689 riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
2690 else if (strcmp (arg, "ilp32e") == 0)
2691 riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
2922d21d 2692 else if (strcmp (arg, "ilp32f") == 0)
7f999549 2693 riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2694 else if (strcmp (arg, "ilp32d") == 0)
7f999549 2695 riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2696 else if (strcmp (arg, "ilp32q") == 0)
7f999549 2697 riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
2922d21d 2698 else if (strcmp (arg, "lp64") == 0)
7f999549 2699 riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
2922d21d 2700 else if (strcmp (arg, "lp64f") == 0)
7f999549 2701 riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2702 else if (strcmp (arg, "lp64d") == 0)
7f999549 2703 riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2704 else if (strcmp (arg, "lp64q") == 0)
7f999549 2705 riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
2922d21d
AW		 2706 else
2707 return 0;
6e1605e4 2708 explicit_mabi = TRUE;
2922d21d
AW		 2709 break;
2710
71060565
JW		 2711 case OPTION_RELAX:
2712 riscv_opts.relax = TRUE;
2713 break;
2714
2715 case OPTION_NO_RELAX:
2716 riscv_opts.relax = FALSE;
2717 break;
2718
2dc8dd17
JW		 2719 case OPTION_ARCH_ATTR:
2720 riscv_opts.arch_attr = TRUE;
2721 break;
2722
2723 case OPTION_NO_ARCH_ATTR:
2724 riscv_opts.arch_attr = FALSE;
2725 break;
2726
2ca89224
NC		 2727 case OPTION_CSR_CHECK:
2728 riscv_opts.csr_check = TRUE;
2729 break;
2730
2731 case OPTION_NO_CSR_CHECK:
2732 riscv_opts.csr_check = FALSE;
2733 break;
2734
8f595e9b
NC		 2735 case OPTION_MISA_SPEC:
2736 return riscv_set_default_isa_spec (arg);
2737
2738 case OPTION_MPRIV_SPEC:
2739 return riscv_set_default_priv_spec (arg);
2740
e23eba97
NC		 2741 default:
2742 return 0;
2743 }
2744
2745 return 1;
2746}
2747
2748void
2749riscv_after_parse_args (void)
2750{
8f595e9b
NC		 2751 /* The --with-arch is optional for now, so we have to set the xlen
2752 according to the default_arch, which is set by the --targte, first.
2753 Then, we use the xlen to set the default_arch_with_ext if the
2754 -march and --with-arch are not set. */
e23eba97
NC		 2755 if (xlen == 0)
2756 {
2757 if (strcmp (default_arch, "riscv32") == 0)
2758 xlen = 32;
2759 else if (strcmp (default_arch, "riscv64") == 0)
2760 xlen = 64;
2761 else
2762 as_bad ("unknown default architecture `%s'", default_arch);
2763 }
8f595e9b
NC		 2764 if (default_arch_with_ext == NULL)
2765 default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
2766
2767 /* Initialize the hash table for extensions with default version. */
2768 ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
2769
2770 /* If the -misa-spec isn't set, then we set the default ISA spec according
2771 to DEFAULT_RISCV_ISA_SPEC. */
2772 if (default_isa_spec == ISA_SPEC_CLASS_NONE)
2773 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
2922d21d 2774
8f595e9b
NC		 2775 /* Set the architecture according to -march or or --with-arch. */
2776 riscv_set_arch (default_arch_with_ext);
2922d21d
AW		 2777
2778 /* Add the RVC extension, regardless of -march, to support .option rvc. */
fecb9c46 2779 riscv_set_rvc (FALSE);
1080bf78 2780 if (riscv_subset_supports ("c"))
2922d21d 2781 riscv_set_rvc (TRUE);
2922d21d 2782
7f999549
JW		 2783 /* Enable RVE if specified by the -march option. */
2784 riscv_set_rve (FALSE);
1080bf78 2785 if (riscv_subset_supports ("e"))
7f999549
JW		 2786 riscv_set_rve (TRUE);
2787
8f595e9b
NC		 2788 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2789 according to DEFAULT_PRIV_SPEC. */
2790 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
2791 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
2792
0ac2b354
AB		 2793 /* If the CIE to be produced has not been overridden on the command line,
2794 then produce version 3 by default. This allows us to use the full
2795 range of registers in a .cfi_return_column directive. */
2796 if (flag_dwarf_cie_version == -1)
2797 flag_dwarf_cie_version = 3;
e23eba97
NC		 2798}
2799
2800long
2801md_pcrel_from (fixS *fixP)
2802{
2803 return fixP->fx_where + fixP->fx_frag->fr_address;
2804}
2805
2806/* Apply a fixup to the object file. */
2807
2808void
2809md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2810{
45f76423 2811 unsigned int subtype;
e23eba97 2812 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
45f76423 2813 bfd_boolean relaxable = FALSE;
c1b465c9 2814 offsetT loc;
a6cbf936 2815 segT sub_segment;
e23eba97
NC		 2816
2817 /* Remember value for tc_gen_reloc. */
2818 fixP->fx_addnumber = *valP;
2819
2820 switch (fixP->fx_r_type)
2821 {
e23eba97
NC		 2822 case BFD_RELOC_RISCV_HI20:
2823 case BFD_RELOC_RISCV_LO12_I:
2824 case BFD_RELOC_RISCV_LO12_S:
45f76423
AW		 2825 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2826 | bfd_getl32 (buf), buf);
a5ec5e3f
AW		 2827 if (fixP->fx_addsy == NULL)
2828 fixP->fx_done = TRUE;
45f76423
AW		 2829 relaxable = TRUE;
2830 break;
2831
2832 case BFD_RELOC_RISCV_GOT_HI20:
e23eba97
NC		 2833 case BFD_RELOC_RISCV_ADD8:
2834 case BFD_RELOC_RISCV_ADD16:
2835 case BFD_RELOC_RISCV_ADD32:
2836 case BFD_RELOC_RISCV_ADD64:
45f76423 2837 case BFD_RELOC_RISCV_SUB6:
e23eba97
NC		 2838 case BFD_RELOC_RISCV_SUB8:
2839 case BFD_RELOC_RISCV_SUB16:
2840 case BFD_RELOC_RISCV_SUB32:
2841 case BFD_RELOC_RISCV_SUB64:
45f76423
AW		 2842 case BFD_RELOC_RISCV_RELAX:
2843 break;
2844
2845 case BFD_RELOC_RISCV_TPREL_HI20:
2846 case BFD_RELOC_RISCV_TPREL_LO12_I:
2847 case BFD_RELOC_RISCV_TPREL_LO12_S:
2848 case BFD_RELOC_RISCV_TPREL_ADD:
2849 relaxable = TRUE;
2850 /* Fall through. */
2851
2852 case BFD_RELOC_RISCV_TLS_GOT_HI20:
2853 case BFD_RELOC_RISCV_TLS_GD_HI20:
2854 case BFD_RELOC_RISCV_TLS_DTPREL32:
2855 case BFD_RELOC_RISCV_TLS_DTPREL64:
e294484e
AW		 2856 if (fixP->fx_addsy != NULL)
2857 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2858 else
2859 as_bad_where (fixP->fx_file, fixP->fx_line,
2860 _("TLS relocation against a constant"));
e23eba97
NC		 2861 break;
2862
e23eba97 2863 case BFD_RELOC_32:
a6cbf936
KLC		 2864 /* Use pc-relative relocation for FDE initial location.
2865 The symbol address in .eh_frame may be adjusted in
2866 _bfd_elf_discard_section_eh_frame, and the content of
2867 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2868 Therefore, we cannot insert a relocation whose addend symbol is
2869 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2870 if (fixP->fx_addsy && fixP->fx_subsy
2871 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
2872 && strcmp (sub_segment->name, ".eh_frame") == 0
2873 && S_GET_VALUE (fixP->fx_subsy)
2874 == fixP->fx_frag->fr_address + fixP->fx_where)
2875 {
2876 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
2877 fixP->fx_subsy = NULL;
2878 break;
2879 }
2880 /* Fall through. */
2881 case BFD_RELOC_64:
e23eba97
NC		 2882 case BFD_RELOC_16:
2883 case BFD_RELOC_8:
45f76423 2884 case BFD_RELOC_RISCV_CFA:
e23eba97
NC		 2885 if (fixP->fx_addsy && fixP->fx_subsy)
2886 {
2887 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2888 fixP->fx_next->fx_addsy = fixP->fx_subsy;
2889 fixP->fx_next->fx_subsy = NULL;
2890 fixP->fx_next->fx_offset = 0;
2891 fixP->fx_subsy = NULL;
2892
2893 switch (fixP->fx_r_type)
2894 {
2895 case BFD_RELOC_64:
2896 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
2897 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
2898 break;
2899
2900 case BFD_RELOC_32:
2901 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
2902 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2903 break;
2904
2905 case BFD_RELOC_16:
2906 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
2907 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2908 break;
2909
2910 case BFD_RELOC_8:
2911 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
2912 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
073808ed 2913 break;
e23eba97 2914
45f76423
AW		 2915 case BFD_RELOC_RISCV_CFA:
2916 /* Load the byte to get the subtype. */
c1b465c9
KLC		 2917 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
2918 loc = fixP->fx_frag->fr_fix - (subtype & 7);
45f76423
AW		 2919 switch (subtype)
2920 {
2921 case DW_CFA_advance_loc1:
c1b465c9
KLC		 2922 fixP->fx_where = loc + 1;
2923 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2924 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
2925 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
2926 break;
2927
2928 case DW_CFA_advance_loc2:
2929 fixP->fx_size = 2;
45f76423 2930 fixP->fx_next->fx_size = 2;
c1b465c9
KLC		 2931 fixP->fx_where = loc + 1;
2932 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2933 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
2934 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2935 break;
2936
2937 case DW_CFA_advance_loc4:
2938 fixP->fx_size = 4;
45f76423 2939 fixP->fx_next->fx_size = 4;
c1b465c9
KLC		 2940 fixP->fx_where = loc;
2941 fixP->fx_next->fx_where = loc;
45f76423
AW		 2942 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
2943 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2944 break;
2945
2946 default:
2947 if (subtype < 0x80 && (subtype & 0x40))
2948 {
2949 /* DW_CFA_advance_loc */
2aece2ba
KLC		 2950 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
2951 fixP->fx_next->fx_frag = fixP->fx_frag;
45f76423
AW		 2952 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
2953 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
2954 }
2955 else
2956 as_fatal (_("internal error: bad CFA value #%d"), subtype);
2957 break;
2958 }
2959 break;
2960
e23eba97
NC		 2961 default:
2962 /* This case is unreachable. */
2963 abort ();
2964 }
2965 }
2966 /* Fall through. */
2967
2968 case BFD_RELOC_RVA:
2969 /* If we are deleting this reloc entry, we must fill in the
2970 value now. This can happen if we have a .word which is not
2971 resolved when it appears but is later defined. */
2972 if (fixP->fx_addsy == NULL)
2973 {
2974 gas_assert (fixP->fx_size <= sizeof (valueT));
2975 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
2976 fixP->fx_done = 1;
2977 }
2978 break;
2979
2980 case BFD_RELOC_RISCV_JMP:
2981 if (fixP->fx_addsy)
2982 {
2983 /* Fill in a tentative value to improve objdump readability. */
2984 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2985 bfd_vma delta = target - md_pcrel_from (fixP);
2986 bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
2987 }
2988 break;
2989
2990 case BFD_RELOC_12_PCREL:
2991 if (fixP->fx_addsy)
2992 {
2993 /* Fill in a tentative value to improve objdump readability. */
2994 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2995 bfd_vma delta = target - md_pcrel_from (fixP);
2996 bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
2997 }
2998 break;
2999
3000 case BFD_RELOC_RISCV_RVC_BRANCH:
3001 if (fixP->fx_addsy)
3002 {
3003 /* Fill in a tentative value to improve objdump readability. */
3004 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3005 bfd_vma delta = target - md_pcrel_from (fixP);
3006 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
3007 }
3008 break;
3009
3010 case BFD_RELOC_RISCV_RVC_JUMP:
3011 if (fixP->fx_addsy)
3012 {
3013 /* Fill in a tentative value to improve objdump readability. */
3014 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3015 bfd_vma delta = target - md_pcrel_from (fixP);
3016 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
3017 }
3018 break;
3019
e23eba97
NC		 3020 case BFD_RELOC_RISCV_CALL:
3021 case BFD_RELOC_RISCV_CALL_PLT:
45f76423
AW		 3022 relaxable = TRUE;
3023 break;
3024
9d06997a 3025 case BFD_RELOC_RISCV_PCREL_HI20:
45f76423
AW		 3026 case BFD_RELOC_RISCV_PCREL_LO12_S:
3027 case BFD_RELOC_RISCV_PCREL_LO12_I:
9d06997a
PD		 3028 relaxable = riscv_opts.relax;
3029 break;
3030
e23eba97
NC		 3031 case BFD_RELOC_RISCV_ALIGN:
3032 break;
3033
3034 default:
3035 /* We ignore generic BFD relocations we don't know about. */
3036 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
3037 as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type);
3038 }
45f76423 3039
e294484e
AW		 3040 if (fixP->fx_subsy != NULL)
3041 as_bad_where (fixP->fx_file, fixP->fx_line,
3042 _("unsupported symbol subtraction"));
3043
45f76423
AW		 3044 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3045 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
3046 {
3047 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3048 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
3049 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
b1b11e92 3050 fixP->fx_next->fx_size = 0;
45f76423
AW		 3051 }
3052}
3053
3054/* Because the value of .cfi_remember_state may changed after relaxation,
3055 we insert a fix to relocate it again in link-time. */
3056
3057void
3058riscv_pre_output_hook (void)
3059{
3060 const frchainS *frch;
72393fd1
JW		 3061 segT s;
3062
3063 /* Save the current segment info. */
3064 segT seg = now_seg;
3065 subsegT subseg = now_subseg;
45f76423
AW		 3066
3067 for (s = stdoutput->sections; s; s = s->next)
3068 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
3069 {
7cb7b948 3070 fragS *frag;
45f76423
AW		 3071
3072 for (frag = frch->frch_root; frag; frag = frag->fr_next)
3073 {
3074 if (frag->fr_type == rs_cfa)
3075 {
45f76423 3076 expressionS exp;
8d1015a8 3077 expressionS *symval;
45f76423 3078
8d1015a8 3079 symval = symbol_get_value_expression (frag->fr_symbol);
45f76423 3080 exp.X_op = O_subtract;
8d1015a8 3081 exp.X_add_symbol = symval->X_add_symbol;
45f76423 3082 exp.X_add_number = 0;
8d1015a8 3083 exp.X_op_symbol = symval->X_op_symbol;
45f76423 3084
72393fd1
JW		 3085 /* We must set the segment before creating a frag after all
3086 frag chains have been chained together. */
3087 subseg_set (s, frch->frch_subseg);
3088
c1b465c9 3089 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
45f76423
AW		 3090 BFD_RELOC_RISCV_CFA);
3091 }
3092 }
3093 }
72393fd1
JW		 3094
3095 /* Restore the original segment info. */
3096 subseg_set (seg, subseg);
e23eba97
NC		 3097}
3098
45f76423 3099
e23eba97
NC		 3100/* This structure is used to hold a stack of .option values. */
3101
3102struct riscv_option_stack
3103{
3104 struct riscv_option_stack *next;
3105 struct riscv_set_options options;
3106};
3107
3108static struct riscv_option_stack *riscv_opts_stack;
3109
3110/* Handle the .option pseudo-op. */
3111
3112static void
3113s_riscv_option (int x ATTRIBUTE_UNUSED)
3114{
3115 char *name = input_line_pointer, ch;
3116
3117 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3118 ++input_line_pointer;
3119 ch = *input_line_pointer;
3120 *input_line_pointer = '\0';
3121
3122 if (strcmp (name, "rvc") == 0)
3123 riscv_set_rvc (TRUE);
3124 else if (strcmp (name, "norvc") == 0)
3125 riscv_set_rvc (FALSE);
3126 else if (strcmp (name, "pic") == 0)
3127 riscv_opts.pic = TRUE;
3128 else if (strcmp (name, "nopic") == 0)
3129 riscv_opts.pic = FALSE;
45f76423
AW		 3130 else if (strcmp (name, "relax") == 0)
3131 riscv_opts.relax = TRUE;
3132 else if (strcmp (name, "norelax") == 0)
3133 riscv_opts.relax = FALSE;
2ca89224
NC		 3134 else if (strcmp (name, "csr-check") == 0)
3135 riscv_opts.csr_check = TRUE;
3136 else if (strcmp (name, "no-csr-check") == 0)
3137 riscv_opts.csr_check = FALSE;
e23eba97
NC		 3138 else if (strcmp (name, "push") == 0)
3139 {
3140 struct riscv_option_stack *s;
3141
3142 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
3143 s->next = riscv_opts_stack;
3144 s->options = riscv_opts;
3145 riscv_opts_stack = s;
3146 }
3147 else if (strcmp (name, "pop") == 0)
3148 {
3149 struct riscv_option_stack *s;
3150
3151 s = riscv_opts_stack;
3152 if (s == NULL)
3153 as_bad (_(".option pop with no .option push"));
3154 else
3155 {
3156 riscv_opts = s->options;
3157 riscv_opts_stack = s->next;
3158 free (s);
3159 }
3160 }
3161 else
3162 {
3163 as_warn (_("Unrecognized .option directive: %s\n"), name);
3164 }
3165 *input_line_pointer = ch;
3166 demand_empty_rest_of_line ();
3167}
3168
3169/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3170 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3171 use in DWARF debug information. */
3172
3173static void
3174s_dtprel (int bytes)
3175{
3176 expressionS ex;
3177 char *p;
3178
3179 expression (&ex);
3180
3181 if (ex.X_op != O_symbol)
3182 {
3183 as_bad (_("Unsupported use of %s"), (bytes == 8
3184 ? ".dtpreldword"
3185 : ".dtprelword"));
3186 ignore_rest_of_line ();
3187 }
3188
3189 p = frag_more (bytes);
3190 md_number_to_chars (p, 0, bytes);
3191 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
3192 (bytes == 8
3193 ? BFD_RELOC_RISCV_TLS_DTPREL64
3194 : BFD_RELOC_RISCV_TLS_DTPREL32));
3195
3196 demand_empty_rest_of_line ();
3197}
3198
3199/* Handle the .bss pseudo-op. */
3200
3201static void
3202s_bss (int ignore ATTRIBUTE_UNUSED)
3203{
3204 subseg_set (bss_section, 0);
3205 demand_empty_rest_of_line ();
3206}
3207
e23eba97 3208static void
d115ab8e 3209riscv_make_nops (char *buf, bfd_vma bytes)
e23eba97 3210{
d115ab8e 3211 bfd_vma i = 0;
e23eba97 3212
e5b737de
AW		 3213 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3214 means we are not within a valid instruction sequence. It is thus safe
3215 to use a zero byte, even though that is not a valid instruction. */
3216 if (bytes % 2 == 1)
3217 buf[i++] = 0;
3218
3219 /* Use at most one 2-byte NOP. */
3220 if ((bytes - i) % 4 == 2)
e23eba97 3221 {
e5b737de 3222 md_number_to_chars (buf + i, RVC_NOP, 2);
d115ab8e 3223 i += 2;
e23eba97
NC		 3224 }
3225
e5b737de 3226 /* Fill the remainder with 4-byte NOPs. */
d115ab8e
AW		 3227 for ( ; i < bytes; i += 4)
3228 md_number_to_chars (buf + i, RISCV_NOP, 4);
3229}
e23eba97 3230
d115ab8e
AW		 3231/* Called from md_do_align. Used to create an alignment frag in a
3232 code section by emitting a worst-case NOP sequence that the linker
3233 will later relax to the correct number of NOPs. We can't compute
3234 the correct alignment now because of other linker relaxations. */
3235
3236bfd_boolean
3237riscv_frag_align_code (int n)
3238{
e5b737de 3239 bfd_vma bytes = (bfd_vma) 1 << n;
36877bfb
JW		 3240 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
3241 bfd_vma worst_case_bytes = bytes - insn_alignment;
3242 char *nops;
ed0816bd 3243 expressionS ex;
d115ab8e 3244
36877bfb
JW		 3245 /* If we are moving to a smaller alignment than the instruction size, then no
3246 alignment is required. */
3247 if (bytes <= insn_alignment)
3248 return TRUE;
3249
d115ab8e
AW		 3250 /* When not relaxing, riscv_handle_align handles code alignment. */
3251 if (!riscv_opts.relax)
3252 return FALSE;
e23eba97 3253
e80ae190
JW		 3254 nops = frag_more (worst_case_bytes);
3255
ed0816bd
PD		 3256 ex.X_op = O_constant;
3257 ex.X_add_number = worst_case_bytes;
d115ab8e 3258
ed0816bd 3259 riscv_make_nops (nops, worst_case_bytes);
e23eba97 3260
ed0816bd
PD		 3261 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
3262 &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
e23eba97 3263
d115ab8e
AW		 3264 return TRUE;
3265}
e23eba97 3266
d115ab8e
AW		 3267/* Implement HANDLE_ALIGN. */
3268
3269void
3270riscv_handle_align (fragS *fragP)
3271{
3272 switch (fragP->fr_type)
3273 {
3274 case rs_align_code:
3275 /* When relaxing, riscv_frag_align_code handles code alignment. */
3276 if (!riscv_opts.relax)
3277 {
e80ae190
JW		 3278 bfd_signed_vma bytes = (fragP->fr_next->fr_address
3279 - fragP->fr_address - fragP->fr_fix);
3280 /* We have 4 byte uncompressed nops. */
3281 bfd_signed_vma size = 4;
3282 bfd_signed_vma excess = bytes % size;
3283 char *p = fragP->fr_literal + fragP->fr_fix;
3284
3285 if (bytes <= 0)
d115ab8e
AW		 3286 break;
3287
e80ae190
JW		 3288 /* Insert zeros or compressed nops to get 4 byte alignment. */
3289 if (excess)
3290 {
3291 riscv_make_nops (p, excess);
3292 fragP->fr_fix += excess;
3293 p += excess;
3294 }
3295
3296 /* Insert variable number of 4 byte uncompressed nops. */
3297 riscv_make_nops (p, size);
3298 fragP->fr_var = size;
d115ab8e
AW		 3299 }
3300 break;
3301
3302 default:
3303 break;
3304 }
e23eba97
NC		 3305}
3306
3307int
3308md_estimate_size_before_relax (fragS *fragp, asection *segtype)
3309{
3310 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
3311}
3312
3313/* Translate internal representation of relocation info to BFD target
3314 format. */
3315
3316arelent *
3317tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3318{
3319 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
3320
3321 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3322 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3323 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3324 reloc->addend = fixp->fx_addnumber;
3325
3326 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3327 if (reloc->howto == NULL)
3328 {
3329 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
3330 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
3331 {
3332 /* We don't have R_RISCV_8/16, but for this special case,
3333 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3334 return reloc;
3335 }
3336
3337 as_bad_where (fixp->fx_file, fixp->fx_line,
3338 _("cannot represent %s relocation in object file"),
3339 bfd_get_reloc_code_name (fixp->fx_r_type));
3340 return NULL;
3341 }
3342
3343 return reloc;
3344}
3345
3346int
3347riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
3348{
3349 if (RELAX_BRANCH_P (fragp->fr_subtype))
3350 {
3351 offsetT old_var = fragp->fr_var;
3352 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
3353 return fragp->fr_var - old_var;
3354 }
3355
3356 return 0;
3357}
3358
3359/* Expand far branches to multi-instruction sequences. */
3360
3361static void
3362md_convert_frag_branch (fragS *fragp)
3363{
3364 bfd_byte *buf;
3365 expressionS exp;
3366 fixS *fixp;
3367 insn_t insn;
3368 int rs1, reloc;
3369
3370 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
3371
3372 exp.X_op = O_symbol;
3373 exp.X_add_symbol = fragp->fr_symbol;
3374 exp.X_add_number = fragp->fr_offset;
3375
3376 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
3377
3378 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
3379 {
3380 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3381 {
3382 case 8:
3383 case 4:
3384 /* Expand the RVC branch into a RISC-V one. */
3385 insn = bfd_getl16 (buf);
3386 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
3387 if ((insn & MASK_C_J) == MATCH_C_J)
3388 insn = MATCH_JAL;
3389 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
3390 insn = MATCH_JAL | (X_RA << OP_SH_RD);
3391 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
3392 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
3393 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
3394 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
3395 else
3396 abort ();
3397 bfd_putl32 (insn, buf);
3398 break;
3399
3400 case 6:
3401 /* Invert the branch condition. Branch over the jump. */
3402 insn = bfd_getl16 (buf);
3403 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
3404 insn |= ENCODE_RVC_B_IMM (6);
3405 bfd_putl16 (insn, buf);
3406 buf += 2;
3407 goto jump;
3408
3409 case 2:
3410 /* Just keep the RVC branch. */
3411 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3412 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
3413 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3414 2, &exp, FALSE, reloc);
3415 buf += 2;
3416 goto done;
3417
3418 default:
1d65abb5 3419 abort ();
e23eba97
NC		 3420 }
3421 }
3422
3423 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3424 {
3425 case 8:
3426 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
3427
3428 /* Invert the branch condition. Branch over the jump. */
3429 insn = bfd_getl32 (buf);
3430 insn ^= MATCH_BEQ ^ MATCH_BNE;
3431 insn |= ENCODE_SBTYPE_IMM (8);
3432 md_number_to_chars ((char *) buf, insn, 4);
3433 buf += 4;
3434
dc1e8a47 3435 jump:
e23eba97
NC		 3436 /* Jump to the target. */
3437 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3438 4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
3439 md_number_to_chars ((char *) buf, MATCH_JAL, 4);
3440 buf += 4;
3441 break;
3442
3443 case 4:
3444 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3445 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
3446 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3447 4, &exp, FALSE, reloc);
3448 buf += 4;
3449 break;
3450
3451 default:
3452 abort ();
3453 }
3454
dc1e8a47 3455 done:
e23eba97
NC		 3456 fixp->fx_file = fragp->fr_file;
3457 fixp->fx_line = fragp->fr_line;
3458
3459 gas_assert (buf == (bfd_byte *)fragp->fr_literal
3460 + fragp->fr_fix + fragp->fr_var);
3461
3462 fragp->fr_fix += fragp->fr_var;
3463}
3464
3465/* Relax a machine dependent frag. This returns the amount by which
3466 the current size of the frag should change. */
3467
3468void
3469md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3470 fragS *fragp)
3471{
3472 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
3473 md_convert_frag_branch (fragp);
3474}
3475
3476void
3477md_show_usage (FILE *stream)
3478{
3479 fprintf (stream, _("\
3480RISC-V options:\n\
8f595e9b
NC		 3481 -fpic generate position-independent code\n\
3482 -fno-pic don't generate position-independent code (default)\n\
3483 -march=ISA set the RISC-V architecture\n\
3484 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3485 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3486 -mabi=ABI set the RISC-V ABI\n\
3487 -mrelax enable relax (default)\n\
3488 -mno-relax disable relax\n\
3489 -march-attr generate RISC-V arch attribute\n\
3490 -mno-arch-attr don't generate RISC-V arch attribute\n\
e23eba97
NC		 3491"));
3492}
3493
3494/* Standard calling conventions leave the CFA at SP on entry. */
3495void
3496riscv_cfi_frame_initial_instructions (void)
3497{
3498 cfi_add_CFA_def_cfa_register (X_SP);
3499}
3500
3501int
3502tc_riscv_regname_to_dw2regnum (char *regname)
3503{
3504 int reg;
3505
3506 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3507 return reg;
3508
3509 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3510 return reg + 32;
3511
4762fe62
AB		 3512 /* CSRs are numbered 4096 -> 8191. */
3513 if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
3514 return reg + 4096;
3515
e23eba97
NC		 3516 as_bad (_("unknown register `%s'"), regname);
3517 return -1;
3518}
3519
3520void
3521riscv_elf_final_processing (void)
3522{
6e1605e4 3523 riscv_set_abi_by_arch ();
e23eba97 3524 elf_elfheader (stdoutput)->e_flags |= elf_flags;
e23eba97
NC		 3525}
3526
3527/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3528 since these directives break relaxation when used with symbol deltas. */
3529
3530static void
3531s_riscv_leb128 (int sign)
3532{
3533 expressionS exp;
3534 char *save_in = input_line_pointer;
3535
3536 expression (&exp);
3537 if (exp.X_op != O_constant)
3538 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3539 demand_empty_rest_of_line ();
3540
3541 input_line_pointer = save_in;
3542 return s_leb128 (sign);
3543}
3544
0e35537d
JW		 3545/* Parse the .insn directive. */
3546
3547static void
3548s_riscv_insn (int x ATTRIBUTE_UNUSED)
3549{
3550 char *str = input_line_pointer;
3551 struct riscv_cl_insn insn;
3552 expressionS imm_expr;
3553 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3554 char save_c;
3555
3556 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3557 ++input_line_pointer;
3558
3559 save_c = *input_line_pointer;
3560 *input_line_pointer = '\0';
3561
3562 const char *error = riscv_ip (str, &insn, &imm_expr,
3563 &imm_reloc, insn_type_hash);
3564
3565 if (error)
3566 {
3567 as_bad ("%s `%s'", error, str);
3568 }
3569 else
3570 {
3571 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3572 append_insn (&insn, &imm_expr, imm_reloc);
3573 }
3574
3575 *input_line_pointer = save_c;
3576 demand_empty_rest_of_line ();
3577}
3578
8f595e9b
NC		 3579/* Update arch and priv attributes. If we don't set the corresponding ELF
3580 attributes, then try to output the default ones. */
2dc8dd17
JW		 3581
3582static void
8f595e9b 3583riscv_write_out_attrs (void)
2dc8dd17 3584{
8f595e9b
NC		 3585 const char *arch_str, *priv_str, *p;
3586 /* versions[0] is major, versions[1] is minor,
3587 and versions[3] is revision. */
3588 unsigned versions[3] = {0}, number = 0;
3589 unsigned int i;
2dc8dd17 3590
8f595e9b
NC		 3591 /* Re-write arch attribute to normalize the arch string. */
3592 arch_str = riscv_arch_str (xlen, &riscv_subsets);
2dc8dd17 3593 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
2dc8dd17 3594 xfree ((void *)arch_str);
8f595e9b
NC		 3595
3596 /* For the file without any instruction, we don't set the default_priv_spec
3597 according to the priv attributes since the md_assemble isn't called.
3598 Call riscv_set_default_priv_spec here for the above case, although
3599 it seems strange. */
3600 if (!start_assemble
3601 && !riscv_set_default_priv_spec (NULL))
3602 return;
3603
1a79004f
NC		 3604 /* If we already have set elf priv attributes, then no need to do anything,
3605 assembler will generate them according to what you set. Otherwise, don't
3606 generate or update them when no CSR and priv instructions are used.
3607 Generate the priv attributes according to default_priv_spec, which can be
3608 set by -mpriv-spec and --with-priv-spec, and be updated by the original
3609 priv attribute sets. */
3610 if (!explicit_priv_attr)
3fc6c3dc
NC		 3611 return;
3612
8f595e9b
NC		 3613 /* Re-write priv attributes by default_priv_spec. */
3614 priv_str = riscv_get_priv_spec_name (default_priv_spec);
3615 p = priv_str;
3616 for (i = 0; *p; ++p)
3617 {
3618 if (*p == '.' && i < 3)
3619 {
3620 versions[i++] = number;
3621 number = 0;
3622 }
3623 else if (ISDIGIT (*p))
3624 number = (number * 10) + (*p - '0');
3625 else
3626 {
3627 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str);
3628 return;
3629 }
3630 }
3631 versions[i] = number;
3632
3633 /* Set the priv attributes. */
3634 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
3635 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
3636 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
2dc8dd17
JW		 3637}
3638
8f595e9b
NC		 3639/* Add the default contents for the .riscv.attributes section. If any
3640 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3641 to update the arch and priv attributes. */
2dc8dd17
JW		 3642
3643static void
3644riscv_set_public_attributes (void)
3645{
8f595e9b
NC		 3646 if (riscv_opts.arch_attr || explicit_attr)
3647 riscv_write_out_attrs ();
2dc8dd17
JW		 3648}
3649
3650/* Called after all assembly has been done. */
3651
3652void
3653riscv_md_end (void)
3654{
3655 riscv_set_public_attributes ();
3656}
3657
3658/* Given a symbolic attribute NAME, return the proper integer value.
3659 Returns -1 if the attribute is not known. */
3660
3661int
3662riscv_convert_symbolic_attribute (const char *name)
3663{
3664 static const struct
3665 {
3666 const char * name;
3667 const int tag;
3668 }
3669 attribute_table[] =
3670 {
3671 /* When you modify this table you should
3672 also modify the list in doc/c-riscv.texi. */
3673#define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3674 T(arch),
3675 T(priv_spec),
3676 T(priv_spec_minor),
3677 T(priv_spec_revision),
3678 T(unaligned_access),
3679 T(stack_align),
3680#undef T
3681 };
3682
3683 unsigned int i;
3684
3685 if (name == NULL)
3686 return -1;
3687
3688 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
3689 if (strcmp (name, attribute_table[i].name) == 0)
3690 return attribute_table[i].tag;
3691
3692 return -1;
3693}
3694
3695/* Parse a .attribute directive. */
3696
3697static void
3698s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
3699{
3700 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
8f595e9b
NC		 3701 unsigned old_xlen;
3702 obj_attribute *attr;
2dc8dd17 3703
8f595e9b
NC		 3704 explicit_attr = TRUE;
3705 switch (tag)
2dc8dd17 3706 {
8f595e9b
NC		 3707 case Tag_RISCV_arch:
3708 old_xlen = xlen;
2dc8dd17
JW		 3709 attr = elf_known_obj_attributes_proc (stdoutput);
3710 if (!start_assemble)
3711 riscv_set_arch (attr[Tag_RISCV_arch].s);
3712 else
3713 as_fatal (_(".attribute arch must set before any instructions"));
3714
3715 if (old_xlen != xlen)
3716 {
3717 /* We must re-init bfd again if xlen is changed. */
3718 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
3719 bfd_find_target (riscv_target_format (), stdoutput);
3720
3721 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
3722 as_warn (_("Could not set architecture and machine"));
3723 }
8f595e9b
NC		 3724 break;
3725
3726 case Tag_RISCV_priv_spec:
3727 case Tag_RISCV_priv_spec_minor:
3728 case Tag_RISCV_priv_spec_revision:
3729 if (start_assemble)
3730 as_fatal (_(".attribute priv spec must set before any instructions"));
3731 break;
3732
3733 default:
3734 break;
2dc8dd17
JW		 3735 }
3736}
3737
e23eba97
NC		 3738/* Pseudo-op table. */
3739
3740static const pseudo_typeS riscv_pseudo_table[] =
3741{
3742 /* RISC-V-specific pseudo-ops. */
3743 {"option", s_riscv_option, 0},
3744 {"half", cons, 2},
3745 {"word", cons, 4},
3746 {"dword", cons, 8},
3747 {"dtprelword", s_dtprel, 4},
3748 {"dtpreldword", s_dtprel, 8},
3749 {"bss", s_bss, 0},
e23eba97
NC		 3750 {"uleb128", s_riscv_leb128, 0},
3751 {"sleb128", s_riscv_leb128, 1},
0e35537d 3752 {"insn", s_riscv_insn, 0},
2dc8dd17 3753 {"attribute", s_riscv_attribute, 0},
e23eba97
NC		 3754
3755 { NULL, NULL, 0 },
3756};
3757
3758void
3759riscv_pop_insert (void)
3760{
3761 extern void pop_insert (const pseudo_typeS *);
3762
3763 pop_insert (riscv_pseudo_table);
3764}
GDB Binutils - Deliverables
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