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[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
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e23eba97 1/* tc-riscv.c -- RISC-V assembler
250d07de 2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
1080bf78 32#include "bfd/elfxx-riscv.h"
e23eba97
NC		 33#include "elf/riscv.h"
34#include "opcode/riscv.h"
35
36#include <stdint.h>
37
38/* Information about an instruction, including its format, operands
39 and fixups. */
40struct riscv_cl_insn
41{
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode *insn_mo;
44
45 /* The encoded instruction bits. */
46 insn_t insn_opcode;
47
48 /* The frag that contains the instruction. */
49 struct frag *frag;
50
51 /* The offset into FRAG of the first instruction byte. */
52 long where;
53
54 /* The relocs associated with the instruction, if any. */
55 fixS *fixp;
56};
57
58#ifndef DEFAULT_ARCH
59#define DEFAULT_ARCH "riscv64"
60#endif
61
2dc8dd17
JW		 62#ifndef DEFAULT_RISCV_ATTR
63#define DEFAULT_RISCV_ATTR 0
64#endif
65
8f595e9b
NC		 66/* Let riscv_after_parse_args set the default value according to xlen. */
67
68#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
70#endif
71
72/* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
77
78#ifndef DEFAULT_RISCV_ISA_SPEC
79#define DEFAULT_RISCV_ISA_SPEC "2.2"
80#endif
81
82#ifndef DEFAULT_RISCV_PRIV_SPEC
83#define DEFAULT_RISCV_PRIV_SPEC "1.11"
84#endif
85
e23eba97 86static const char default_arch[] = DEFAULT_ARCH;
8f595e9b
NC		 87static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
88static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
89static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
e23eba97 90
2922d21d
AW		 91static unsigned xlen = 0; /* width of an x-register */
92static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
7f999549 93static bfd_boolean rve_abi = FALSE;
6e1605e4
NC		 94enum float_abi {
95 FLOAT_ABI_DEFAULT = -1,
96 FLOAT_ABI_SOFT,
97 FLOAT_ABI_SINGLE,
98 FLOAT_ABI_DOUBLE,
99 FLOAT_ABI_QUAD
100};
101static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
e23eba97 102
2922d21d 103#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
e23eba97
NC		 104#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
105
106static unsigned elf_flags = 0;
107
8f595e9b
NC		 108/* Set the default_isa_spec. Return 0 if the input spec string isn't
109 supported. Otherwise, return 1. */
110
111static int
112riscv_set_default_isa_spec (const char *s)
113{
114 enum riscv_isa_spec_class class;
115 if (!riscv_get_isa_spec_class (s, &class))
116 {
117 as_bad ("Unknown default ISA spec `%s' set by "
118 "-misa-spec or --with-isa-spec", s);
119 return 0;
120 }
121 else
122 default_isa_spec = class;
123 return 1;
124}
125
126/* Set the default_priv_spec, assembler will find the suitable CSR address
127 according to default_priv_spec. We will try to check priv attributes if
128 the input string is NULL. Return 0 if the input priv spec string isn't
129 supported. Otherwise, return 1. */
130
131static int
132riscv_set_default_priv_spec (const char *s)
133{
134 enum riscv_priv_spec_class class;
135 unsigned major, minor, revision;
136 obj_attribute *attr;
8f595e9b
NC		 137
138 /* Find the corresponding priv spec class. */
139 if (riscv_get_priv_spec_class (s, &class))
140 {
141 default_priv_spec = class;
142 return 1;
143 }
144
145 if (s != NULL)
146 {
147 as_bad (_("Unknown default privilege spec `%s' set by "
148 "-mpriv-spec or --with-priv-spec"), s);
149 return 0;
150 }
151
152 /* Try to set the default_priv_spec according to the priv attributes. */
153 attr = elf_known_obj_attributes_proc (stdoutput);
154 major = (unsigned) attr[Tag_RISCV_priv_spec].i;
155 minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
156 revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
157
39ff0b81
NC		 158 if (riscv_get_priv_spec_class_from_numbers (major,
159 minor,
160 revision,
161 &class))
8f595e9b 162 {
39ff0b81
NC		 163 /* The priv attributes setting 0.0.0 is meaningless. We should have set
164 the default_priv_spec by md_parse_option and riscv_after_parse_args,
165 so just skip the following setting. */
166 if (class == PRIV_SPEC_CLASS_NONE)
167 return 1;
8f595e9b 168
8f595e9b 169 default_priv_spec = class;
8f595e9b
NC		 170 return 1;
171 }
172
173 /* Still can not find the priv spec class. */
ddc73fa9 174 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
8f595e9b 175 "privilege attributes"), major, minor, revision);
8f595e9b
NC		 176 return 0;
177}
178
e23eba97
NC		 179/* This is the set of options which the .option pseudo-op may modify. */
180
181struct riscv_set_options
182{
183 int pic; /* Generate position-independent code. */
184 int rvc; /* Generate RVC code. */
7f999549 185 int rve; /* Generate RVE code. */
45f76423 186 int relax; /* Emit relocs the linker is allowed to relax. */
2dc8dd17 187 int arch_attr; /* Emit arch attribute. */
2ca89224 188 int csr_check; /* Enable the CSR checking. */
e23eba97
NC		 189};
190
191static struct riscv_set_options riscv_opts =
192{
193 0, /* pic */
194 0, /* rvc */
7f999549 195 0, /* rve */
45f76423 196 1, /* relax */
2dc8dd17 197 DEFAULT_RISCV_ATTR, /* arch_attr */
2ca89224 198 0. /* csr_check */
e23eba97
NC		 199};
200
201static void
202riscv_set_rvc (bfd_boolean rvc_value)
203{
204 if (rvc_value)
205 elf_flags |= EF_RISCV_RVC;
206
207 riscv_opts.rvc = rvc_value;
208}
209
7f999549
JW		 210static void
211riscv_set_rve (bfd_boolean rve_value)
212{
213 riscv_opts.rve = rve_value;
214}
215
1080bf78 216static riscv_subset_list_t riscv_subsets;
e23eba97
NC		 217
218static bfd_boolean
1080bf78 219riscv_subset_supports (const char *feature)
e23eba97 220{
dfe92496
NC		 221 struct riscv_subset_t *subset;
222
1080bf78
JW		 223 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
224 return TRUE;
e23eba97 225
dfe92496 226 return riscv_lookup_subset (&riscv_subsets, feature, &subset);
e23eba97
NC		 227}
228
43135d3b 229static bfd_boolean
7e9ad3a3 230riscv_multi_subset_supports (enum riscv_insn_class insn_class)
43135d3b 231{
7e9ad3a3
JW		 232 switch (insn_class)
233 {
234 case INSN_CLASS_I: return riscv_subset_supports ("i");
235 case INSN_CLASS_C: return riscv_subset_supports ("c");
236 case INSN_CLASS_A: return riscv_subset_supports ("a");
237 case INSN_CLASS_M: return riscv_subset_supports ("m");
238 case INSN_CLASS_F: return riscv_subset_supports ("f");
239 case INSN_CLASS_D: return riscv_subset_supports ("d");
729a5353 240 case INSN_CLASS_Q: return riscv_subset_supports ("q");
7e9ad3a3
JW		 241
242 case INSN_CLASS_F_AND_C:
729a5353
NC		 243 return (riscv_subset_supports ("f")
244 && riscv_subset_supports ("c"));
245 case INSN_CLASS_D_AND_C:
246 return (riscv_subset_supports ("d")
247 && riscv_subset_supports ("c"));
43135d3b 248
729a5353
NC		 249 case INSN_CLASS_ZICSR:
250 return riscv_subset_supports ("zicsr");
251 case INSN_CLASS_ZIFENCEI:
252 return riscv_subset_supports ("zifencei");
43135d3b 253
7e9ad3a3
JW		 254 default:
255 as_fatal ("Unreachable");
256 return FALSE;
257 }
43135d3b
JW		 258}
259
8f595e9b 260/* Handle of the extension with version hash table. */
629310ab 261static htab_t ext_version_hash = NULL;
8f595e9b 262
629310ab 263static htab_t
8f595e9b
NC		 264init_ext_version_hash (const struct riscv_ext_version *table)
265{
266 int i = 0;
629310ab 267 htab_t hash = str_htab_create ();
8f595e9b
NC		 268
269 while (table[i].name)
270 {
271 const char *name = table[i].name;
fe0e921f
AM		 272 if (str_hash_insert (hash, name, &table[i], 0) != NULL)
273 as_fatal (_("duplicate %s"), name);
8f595e9b
NC		 274
275 i++;
276 while (table[i].name
277 && strcmp (table[i].name, name) == 0)
278 i++;
279 }
280
281 return hash;
282}
283
284static void
285riscv_get_default_ext_version (const char *name,
7ef19aa6
NC		 286 int *major_version,
287 int *minor_version)
8f595e9b
NC		 288{
289 struct riscv_ext_version *ext;
290
8f595e9b
NC		 291 if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
292 return;
293
629310ab 294 ext = (struct riscv_ext_version *) str_hash_find (ext_version_hash, name);
8f595e9b 295 while (ext
7ef19aa6
NC		 296 && ext->name
297 && strcmp (ext->name, name) == 0)
8f595e9b
NC		 298 {
299 if (ext->isa_spec_class == default_isa_spec)
7ef19aa6
NC		 300 {
301 *major_version = ext->major_version;
302 *minor_version = ext->minor_version;
303 return;
304 }
8f595e9b
NC		 305 ext++;
306 }
307}
308
2922d21d 309/* Set which ISA and extensions are available. */
e23eba97 310
e23eba97 311static void
2922d21d 312riscv_set_arch (const char *s)
e23eba97 313{
1080bf78
JW		 314 riscv_parse_subset_t rps;
315 rps.subset_list = &riscv_subsets;
7ef19aa6 316 rps.error_handler = as_bad;
1080bf78 317 rps.xlen = &xlen;
8f595e9b
NC		 318 rps.get_default_version = riscv_get_default_ext_version;
319
320 if (s == NULL)
321 return;
7f999549 322
1080bf78
JW		 323 riscv_release_subset_list (&riscv_subsets);
324 riscv_parse_subset (&rps, s);
e23eba97
NC		 325}
326
6e1605e4
NC		 327/* Indicate -mabi= option is explictly set. */
328static bfd_boolean explicit_mabi = FALSE;
329
330static void
331riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
332{
333 abi_xlen = new_xlen;
334 float_abi = new_float_abi;
335 rve_abi = rve;
336}
337
338/* If the -mabi option isn't set, then we set the abi according to the arch
339 string. Otherwise, check if there are conflicts between architecture
340 and abi setting. */
341
342static void
343riscv_set_abi_by_arch (void)
344{
345 if (!explicit_mabi)
346 {
347 if (riscv_subset_supports ("q"))
348 riscv_set_abi (xlen, FLOAT_ABI_QUAD, FALSE);
349 else if (riscv_subset_supports ("d"))
350 riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, FALSE);
351 else
352 riscv_set_abi (xlen, FLOAT_ABI_SOFT, FALSE);
353 }
354 else
355 {
356 gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT);
357 if (abi_xlen > xlen)
358 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
359 else if (abi_xlen < xlen)
360 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
361 }
362
363 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
364 elf_flags &= ~EF_RISCV_FLOAT_ABI;
365 elf_flags |= float_abi << 1;
366
367 if (rve_abi)
368 elf_flags |= EF_RISCV_RVE;
369}
370
e23eba97 371/* Handle of the OPCODE hash table. */
629310ab 372static htab_t op_hash = NULL;
e23eba97 373
0e35537d 374/* Handle of the type of .insn hash table. */
629310ab 375static htab_t insn_type_hash = NULL;
0e35537d 376
e23eba97
NC		 377/* This array holds the chars that always start a comment. If the
378 pre-processor is disabled, these aren't very useful */
379const char comment_chars[] = "#";
380
381/* This array holds the chars that only start a comment at the beginning of
382 a line. If the line seems to have the form '# 123 filename'
383 .line and .file directives will appear in the pre-processed output */
384/* Note that input_file.c hand checks for '#' at the beginning of the
385 first line of the input file. This is because the compiler outputs
386 #NO_APP at the beginning of its output. */
387/* Also note that C style comments are always supported. */
388const char line_comment_chars[] = "#";
389
390/* This array holds machine specific line separator characters. */
391const char line_separator_chars[] = ";";
392
393/* Chars that can be used to separate mant from exp in floating point nums */
394const char EXP_CHARS[] = "eE";
395
396/* Chars that mean this number is a floating point constant */
397/* As in 0f12.456 */
398/* or 0d1.2345e12 */
399const char FLT_CHARS[] = "rRsSfFdDxXpP";
400
2dc8dd17
JW		 401/* Indicate we are already assemble any instructions or not. */
402static bfd_boolean start_assemble = FALSE;
403
f9a6a8f0 404/* Indicate ELF attributes are explicitly set. */
8f595e9b 405static bfd_boolean explicit_attr = FALSE;
2dc8dd17 406
f9a6a8f0 407/* Indicate CSR or priv instructions are explicitly used. */
1a79004f 408static bfd_boolean explicit_priv_attr = FALSE;
3fc6c3dc 409
e23eba97
NC		 410/* Macros for encoding relaxation state for RVC branches and far jumps. */
411#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
412 ((relax_substateT) \
413 (0xc0000000 \
414 | ((uncond) ? 1 : 0) \
415 | ((rvc) ? 2 : 0) \
416 | ((length) << 2)))
417#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
418#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
419#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
420#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
421
422/* Is the given value a sign-extended 32-bit value? */
423#define IS_SEXT_32BIT_NUM(x) \
424 (((x) &~ (offsetT) 0x7fffffff) == 0 \
425 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
426
427/* Is the given value a zero-extended 32-bit value? Or a negated one? */
428#define IS_ZEXT_32BIT_NUM(x) \
429 (((x) &~ (offsetT) 0xffffffff) == 0 \
430 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
431
432/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
433 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
434#define INSERT_OPERAND(FIELD, INSN, VALUE) \
435 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
436
437/* Determine if an instruction matches an opcode. */
438#define OPCODE_MATCHES(OPCODE, OP) \
439 (((OPCODE) & MASK_##OP) == MATCH_##OP)
440
441static char *expr_end;
442
443/* The default target format to use. */
444
445const char *
446riscv_target_format (void)
447{
fbc09e7a
MC		 448 if (target_big_endian)
449 return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv";
450 else
451 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
e23eba97
NC		 452}
453
454/* Return the length of instruction INSN. */
455
456static inline unsigned int
457insn_length (const struct riscv_cl_insn *insn)
458{
459 return riscv_insn_length (insn->insn_opcode);
460}
461
462/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
463
464static void
465create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
466{
467 insn->insn_mo = mo;
468 insn->insn_opcode = mo->match;
469 insn->frag = NULL;
470 insn->where = 0;
471 insn->fixp = NULL;
472}
473
474/* Install INSN at the location specified by its "frag" and "where" fields. */
475
476static void
477install_insn (const struct riscv_cl_insn *insn)
478{
479 char *f = insn->frag->fr_literal + insn->where;
fbc09e7a 480 number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn));
e23eba97
NC		 481}
482
483/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
484 and install the opcode in the new location. */
485
486static void
487move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
488{
489 insn->frag = frag;
490 insn->where = where;
491 if (insn->fixp != NULL)
492 {
493 insn->fixp->fx_frag = frag;
494 insn->fixp->fx_where = where;
495 }
496 install_insn (insn);
497}
498
499/* Add INSN to the end of the output. */
500
501static void
502add_fixed_insn (struct riscv_cl_insn *insn)
503{
504 char *f = frag_more (insn_length (insn));
505 move_insn (insn, frag_now, f - frag_now->fr_literal);
506}
507
508static void
509add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
510 relax_substateT subtype, symbolS *symbol, offsetT offset)
511{
512 frag_grow (max_chars);
513 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
514 frag_var (rs_machine_dependent, max_chars, var,
515 subtype, symbol, offset, NULL);
516}
517
518/* Compute the length of a branch sequence, and adjust the stored length
519 accordingly. If FRAGP is NULL, the worst-case length is returned. */
520
521static unsigned
522relaxed_branch_length (fragS *fragp, asection *sec, int update)
523{
524 int jump, rvc, length = 8;
525
526 if (!fragp)
527 return length;
528
529 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
530 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
531 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
532
533 /* Assume jumps are in range; the linker will catch any that aren't. */
534 length = jump ? 4 : 8;
535
536 if (fragp->fr_symbol != NULL
537 && S_IS_DEFINED (fragp->fr_symbol)
01156111 538 && !S_IS_WEAK (fragp->fr_symbol)
e23eba97
NC		 539 && sec == S_GET_SEGMENT (fragp->fr_symbol))
540 {
541 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
542 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
543 val -= fragp->fr_address + fragp->fr_fix;
544
545 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
546 length = 2;
547 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
548 length = 4;
549 else if (!jump && rvc)
550 length = 6;
551 }
552
553 if (update)
554 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
555
556 return length;
557}
558
0e35537d
JW		 559/* Information about an opcode name, mnemonics and its value. */
560struct opcode_name_t
561{
562 const char *name;
563 unsigned int val;
564};
565
566/* List for all supported opcode name. */
567static const struct opcode_name_t opcode_name_list[] =
568{
569 {"C0", 0x0},
570 {"C1", 0x1},
571 {"C2", 0x2},
572
573 {"LOAD", 0x03},
574 {"LOAD_FP", 0x07},
575 {"CUSTOM_0", 0x0b},
576 {"MISC_MEM", 0x0f},
577 {"OP_IMM", 0x13},
578 {"AUIPC", 0x17},
579 {"OP_IMM_32", 0x1b},
580 /* 48b 0x1f. */
581
582 {"STORE", 0x23},
583 {"STORE_FP", 0x27},
584 {"CUSTOM_1", 0x2b},
585 {"AMO", 0x2f},
586 {"OP", 0x33},
587 {"LUI", 0x37},
588 {"OP_32", 0x3b},
589 /* 64b 0x3f. */
590
591 {"MADD", 0x43},
592 {"MSUB", 0x47},
593 {"NMADD", 0x4f},
594 {"NMSUB", 0x4b},
595 {"OP_FP", 0x53},
596 /*reserved 0x57. */
597 {"CUSTOM_2", 0x5b},
598 /* 48b 0x5f. */
599
600 {"BRANCH", 0x63},
601 {"JALR", 0x67},
602 /*reserved 0x5b. */
603 {"JAL", 0x6f},
604 {"SYSTEM", 0x73},
605 /*reserved 0x77. */
606 {"CUSTOM_3", 0x7b},
607 /* >80b 0x7f. */
608
609 {NULL, 0}
610};
611
612/* Hash table for lookup opcode name. */
629310ab 613static htab_t opcode_names_hash = NULL;
0e35537d
JW		 614
615/* Initialization for hash table of opcode name. */
616static void
617init_opcode_names_hash (void)
618{
0e35537d
JW		 619 const struct opcode_name_t *opcode;
620
621 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
fe0e921f
AM		 622 if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL)
623 as_fatal (_("duplicate %s"), opcode->name);
0e35537d
JW		 624}
625
626/* Find `s` is a valid opcode name or not,
627 return the opcode name info if found. */
628static const struct opcode_name_t *
629opcode_name_lookup (char **s)
630{
631 char *e;
632 char save_c;
633 struct opcode_name_t *o;
634
635 /* Find end of name. */
636 e = *s;
637 if (is_name_beginner (*e))
638 ++e;
639 while (is_part_of_name (*e))
640 ++e;
641
642 /* Terminate name. */
643 save_c = *e;
644 *e = '\0';
645
629310ab 646 o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s);
0e35537d
JW		 647
648 /* Advance to next token if one was recognized. */
649 if (o)
650 *s = e;
651
652 *e = save_c;
653 expr_end = e;
654
655 return o;
656}
657
e23eba97
NC		 658enum reg_class
659{
660 RCLASS_GPR,
661 RCLASS_FPR,
8f595e9b
NC		 662 RCLASS_MAX,
663
664 RCLASS_CSR
e23eba97
NC		 665};
666
629310ab
ML		 667static htab_t reg_names_hash = NULL;
668static htab_t csr_extra_hash = NULL;
e23eba97
NC		 669
670#define ENCODE_REG_HASH(cls, n) \
671 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
672#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
673#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
674
675static void
676hash_reg_name (enum reg_class class, const char *name, unsigned n)
677{
678 void *hash = ENCODE_REG_HASH (class, n);
fe0e921f
AM		 679 if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL)
680 as_fatal (_("duplicate %s"), name);
e23eba97
NC		 681}
682
683static void
684hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
685{
686 unsigned i;
687
688 for (i = 0; i < n; i++)
689 hash_reg_name (class, names[i], i);
690}
691
8f595e9b
NC		 692/* Init hash table csr_extra_hash to handle CSR. */
693static void
694riscv_init_csr_hash (const char *name,
695 unsigned address,
696 enum riscv_csr_class class,
697 enum riscv_priv_spec_class define_version,
698 enum riscv_priv_spec_class abort_version)
699{
700 struct riscv_csr_extra *entry, *pre_entry;
8f595e9b
NC		 701 bfd_boolean need_enrty = TRUE;
702
703 pre_entry = NULL;
629310ab 704 entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
8f595e9b
NC		 705 while (need_enrty && entry != NULL)
706 {
707 if (entry->csr_class == class
708 && entry->address == address
709 && entry->define_version == define_version
710 && entry->abort_version == abort_version)
711 need_enrty = FALSE;
712 pre_entry = entry;
713 entry = entry->next;
714 }
715
716 /* Duplicate setting for the CSR, just return and do nothing. */
717 if (!need_enrty)
718 return;
bd0cf5a6 719
8f595e9b
NC		 720 entry = XNEW (struct riscv_csr_extra);
721 entry->csr_class = class;
722 entry->address = address;
723 entry->define_version = define_version;
724 entry->abort_version = abort_version;
5c505568 725 entry->next = NULL;
8f595e9b
NC		 726
727 /* If the CSR hasn't been inserted in the hash table, then insert it.
728 Otherwise, attach the extra information to the entry which is already
729 in the hash table. */
730 if (pre_entry == NULL)
fe0e921f 731 str_hash_insert (csr_extra_hash, name, entry, 0);
8f595e9b
NC		 732 else
733 pre_entry->next = entry;
734}
bd0cf5a6 735
08ccfccf
NC		 736/* Return the suitable CSR address after checking the ISA dependency and
737 priv spec versions. */
bd0cf5a6 738
08ccfccf
NC		 739static unsigned int
740riscv_csr_address (const char *csr_name,
741 struct riscv_csr_extra *entry)
bd0cf5a6 742{
08ccfccf
NC		 743 struct riscv_csr_extra *saved_entry = entry;
744 enum riscv_csr_class csr_class = entry->csr_class;
745 bfd_boolean need_check_version = TRUE;
8f595e9b
NC		 746 bfd_boolean result = TRUE;
747
8f595e9b 748 switch (csr_class)
bd0cf5a6 749 {
8f595e9b
NC		 750 case CSR_CLASS_I:
751 result = riscv_subset_supports ("i");
752 break;
08ccfccf
NC		 753 case CSR_CLASS_I_32:
754 result = (xlen == 32 && riscv_subset_supports ("i"));
755 break;
8f595e9b
NC		 756 case CSR_CLASS_F:
757 result = riscv_subset_supports ("f");
08ccfccf 758 need_check_version = FALSE;
8f595e9b 759 break;
08ccfccf
NC		 760 case CSR_CLASS_DEBUG:
761 need_check_version = FALSE;
8f595e9b
NC		 762 break;
763 default:
764 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
bd0cf5a6
NC		 765 }
766
08ccfccf
NC		 767 /* Don't report the ISA conflict when -mcsr-check isn't set. */
768 if (riscv_opts.csr_check && !result)
769 as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name);
8f595e9b
NC		 770
771 while (entry != NULL)
bd0cf5a6 772 {
08ccfccf
NC		 773 if (!need_check_version
774 || (default_priv_spec >= entry->define_version
775 && default_priv_spec < entry->abort_version))
8f595e9b
NC		 776 {
777 /* Find the suitable CSR according to the specific version. */
08ccfccf 778 return entry->address;
8f595e9b
NC		 779 }
780 entry = entry->next;
781 }
bd0cf5a6 782
8f595e9b
NC		 783 /* We can not find the suitable CSR address according to the privilege
784 version. Therefore, we use the last defined value. Report the warning
785 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
786 otherwise, you may get the unexpected CSR address. */
787 if (riscv_opts.csr_check)
788 {
789 const char *priv_name = riscv_get_priv_spec_name (default_priv_spec);
790
791 if (priv_name != NULL)
792 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
793 csr_name, priv_name);
bd0cf5a6 794 }
08ccfccf
NC		 795
796 return saved_entry->address;
bd0cf5a6
NC		 797}
798
8f595e9b
NC		 799/* Once the CSR is defined, including the old privilege spec, then we call
800 riscv_csr_class_check and riscv_csr_version_check to do the further checking
801 and get the corresponding address. Return -1 if the CSR is never been
802 defined. Otherwise, return the address. */
bd0cf5a6 803
8f595e9b 804static unsigned int
bd0cf5a6
NC		 805reg_csr_lookup_internal (const char *s)
806{
807 struct riscv_csr_extra *r =
629310ab 808 (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s);
bd0cf5a6
NC		 809
810 if (r == NULL)
8f595e9b 811 return -1U;
bd0cf5a6 812
8f595e9b
NC		 813 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
814 the CSR was defined, but isn't allowed for the current ISA setting or
815 the privilege spec. If the CSR is never been defined, then assembler
816 will regard it as a "Unknown CSR" and report error. If user use number
817 to set the CSR, but over the range (> 0xfff), then assembler will report
818 "Improper CSR" error for it. */
08ccfccf 819 return riscv_csr_address (s, r);
bd0cf5a6
NC		 820}
821
e23eba97
NC		 822static unsigned int
823reg_lookup_internal (const char *s, enum reg_class class)
824{
8f595e9b
NC		 825 void *r;
826
827 if (class == RCLASS_CSR)
828 return reg_csr_lookup_internal (s);
e23eba97 829
629310ab 830 r = str_hash_find (reg_names_hash, s);
e23eba97
NC		 831 if (r == NULL || DECODE_REG_CLASS (r) != class)
832 return -1;
7f999549
JW		 833
834 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
835 return -1;
836
e23eba97
NC		 837 return DECODE_REG_NUM (r);
838}
839
840static bfd_boolean
841reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
842{
843 char *e;
844 char save_c;
845 int reg = -1;
846
847 /* Find end of name. */
848 e = *s;
849 if (is_name_beginner (*e))
850 ++e;
851 while (is_part_of_name (*e))
852 ++e;
853
854 /* Terminate name. */
855 save_c = *e;
856 *e = '\0';
857
858 /* Look for the register. Advance to next token if one was recognized. */
859 if ((reg = reg_lookup_internal (*s, class)) >= 0)
860 *s = e;
861
862 *e = save_c;
863 if (regnop)
864 *regnop = reg;
865 return reg >= 0;
866}
867
868static bfd_boolean
869arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
870{
871 const char *p = strchr (*s, ',');
872 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
873
bfb218e3
JW		 874 if (len == 0)
875 return FALSE;
876
e23eba97
NC		 877 for (i = 0; i < size; i++)
878 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
879 {
880 *regnop = i;
881 *s += len;
882 return TRUE;
883 }
884
885 return FALSE;
886}
887
888/* For consistency checking, verify that all bits are specified either
889 by the match/mask part of the instruction definition, or by the
0e35537d
JW		 890 operand list.
891
892 `length` could be 0, 4 or 8, 0 for auto detection. */
e23eba97 893static bfd_boolean
0e35537d 894validate_riscv_insn (const struct riscv_opcode *opc, int length)
e23eba97
NC		 895{
896 const char *p = opc->args;
897 char c;
898 insn_t used_bits = opc->mask;
0e35537d
JW		 899 int insn_width;
900 insn_t required_bits;
901
902 if (length == 0)
903 insn_width = 8 * riscv_insn_length (opc->match);
904 else
905 insn_width = 8 * length;
906
907 required_bits = ~0ULL >> (64 - insn_width);
e23eba97
NC		 908
909 if ((used_bits & opc->match) != (opc->match & required_bits))
910 {
911 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
912 opc->name, opc->args);
913 return FALSE;
914 }
915
916#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
917 while (*p)
918 switch (c = *p++)
919 {
920 case 'C': /* RVC */
921 switch (c = *p++)
922 {
1d65abb5 923 case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
e23eba97
NC		 924 case 'c': break; /* RS1, constrained to equal sp */
925 case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
1d65abb5 926 case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
b416fe87 927 case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
1d65abb5
AW		 928 case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
929 case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
930 case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
931 case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
932 case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
e23eba97
NC		 933 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
934 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
1d65abb5
AW		 935 case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
936 case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
e23eba97
NC		 937 case 'w': break; /* RS1S, constrained to equal RD */
938 case 'x': break; /* RS2S, constrained to equal RD */
ca0bc150 939 case 'z': break; /* RS2S, contrained to be x0 */
1d65abb5
AW		 940 case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
941 case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
942 case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
943 case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
e23eba97
NC		 944 case 'U': break; /* RS1, constrained to equal RD */
945 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1d65abb5
AW		 946 case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
947 case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
0e35537d
JW		 948 case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
949 case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
e23eba97
NC		 950 case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
951 case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
0e35537d
JW		 952 case 'F': /* funct */
953 switch (c = *p++)
954 {
4765cd61 955 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
0e35537d
JW		 956 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
957 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
4765cd61 958 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
0e35537d
JW		 959 default:
960 as_bad (_("internal: bad RISC-V opcode"
961 " (unknown operand type `CF%c'): %s %s"),
962 c, opc->name, opc->args);
963 return FALSE;
964 }
965 break;
e23eba97
NC		 966 default:
967 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
968 c, opc->name, opc->args);
969 return FALSE;
970 }
971 break;
972 case ',': break;
973 case '(': break;
974 case ')': break;
975 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
976 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
977 case 'A': break;
978 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
979 case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
980 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
981 case 'I': break;
982 case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
983 case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
984 case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */
985 case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
986 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
987 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
988 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
989 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
0e35537d 990 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
e23eba97
NC		 991 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
992 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
993 case 'o':
1d65abb5
AW		 994 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
995 case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
996 case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
997 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
998 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
e925c834 999 case 'z': break;
e23eba97
NC		 1000 case '[': break;
1001 case ']': break;
1002 case '0': break;
f50fabe4 1003 case '1': break;
0e35537d
JW		 1004 case 'F': /* funct */
1005 switch (c = *p++)
1006 {
1007 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
1008 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
1009 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
1010 default:
1011 as_bad (_("internal: bad RISC-V opcode"
1012 " (unknown operand type `F%c'): %s %s"),
1013 c, opc->name, opc->args);
1014 return FALSE;
1015 }
1016 break;
1017 case 'O': /* opcode */
1018 switch (c = *p++)
1019 {
1020 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
1021 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
1022 default:
1023 as_bad (_("internal: bad RISC-V opcode"
1024 " (unknown operand type `F%c'): %s %s"),
1025 c, opc->name, opc->args);
1026 return FALSE;
1027 }
1028 break;
e23eba97
NC		 1029 default:
1030 as_bad (_("internal: bad RISC-V opcode "
1031 "(unknown operand type `%c'): %s %s"),
1032 c, opc->name, opc->args);
1033 return FALSE;
1034 }
1035#undef USE_BITS
1036 if (used_bits != required_bits)
1037 {
1038 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1039 ~(unsigned long)(used_bits & required_bits),
1040 opc->name, opc->args);
1041 return FALSE;
1042 }
1043 return TRUE;
1044}
1045
1046struct percent_op_match
1047{
1048 const char *str;
1049 bfd_reloc_code_real_type reloc;
1050};
1051
0e35537d
JW		 1052/* Common hash table initialization function for
1053 instruction and .insn directive. */
629310ab 1054static htab_t
0e35537d
JW		 1055init_opcode_hash (const struct riscv_opcode *opcodes,
1056 bfd_boolean insn_directive_p)
e23eba97
NC		 1057{
1058 int i = 0;
0e35537d 1059 int length;
629310ab 1060 htab_t hash = str_htab_create ();
0e35537d 1061 while (opcodes[i].name)
e23eba97 1062 {
0e35537d 1063 const char *name = opcodes[i].name;
fe0e921f
AM		 1064 if (str_hash_insert (hash, name, &opcodes[i], 0) != NULL)
1065 as_fatal (_("duplicate %s"), name);
e23eba97
NC		 1066
1067 do
1068 {
0e35537d 1069 if (opcodes[i].pinfo != INSN_MACRO)
e23eba97 1070 {
0e35537d
JW		 1071 if (insn_directive_p)
1072 length = ((name[0] == 'c') ? 2 : 4);
1073 else
1074 length = 0; /* Let assembler determine the length. */
1075 if (!validate_riscv_insn (&opcodes[i], length))
e23eba97
NC		 1076 as_fatal (_("Broken assembler. No assembly attempted."));
1077 }
0e35537d
JW		 1078 else
1079 gas_assert (!insn_directive_p);
e23eba97
NC		 1080 ++i;
1081 }
0e35537d 1082 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
e23eba97
NC		 1083 }
1084
0e35537d
JW		 1085 return hash;
1086}
1087
1088/* This function is called once, at assembler startup time. It should set up
1089 all the tables, etc. that the MD part of the assembler will need. */
1090
1091void
1092md_begin (void)
1093{
1094 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
1095
1096 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
1097 as_warn (_("Could not set architecture and machine"));
1098
1099 op_hash = init_opcode_hash (riscv_opcodes, FALSE);
1100 insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
1101
629310ab 1102 reg_names_hash = str_htab_create ();
e23eba97
NC		 1103 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
1104 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
1105 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
1106 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
b9c04e5a
JW		 1107 /* Add "fp" as an alias for "s0". */
1108 hash_reg_name (RCLASS_GPR, "fp", 8);
1109
bd0cf5a6 1110 /* Create and insert CSR hash tables. */
629310ab 1111 csr_extra_hash = str_htab_create ();
8f595e9b
NC		 1112#define DECLARE_CSR(name, num, class, define_version, abort_version) \
1113 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1114#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1115 DECLARE_CSR(name, num, class, define_version, abort_version);
e23eba97
NC		 1116#include "opcode/riscv-opc.h"
1117#undef DECLARE_CSR
1118
629310ab 1119 opcode_names_hash = str_htab_create ();
bd0cf5a6
NC		 1120 init_opcode_names_hash ();
1121
e23eba97
NC		 1122 /* Set the default alignment for the text section. */
1123 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
1124}
1125
45f76423
AW		 1126static insn_t
1127riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
1128{
1129 switch (reloc_type)
1130 {
1131 case BFD_RELOC_32:
1132 return value;
1133
1134 case BFD_RELOC_RISCV_HI20:
1135 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
1136
1137 case BFD_RELOC_RISCV_LO12_S:
1138 return ENCODE_STYPE_IMM (value);
1139
1140 case BFD_RELOC_RISCV_LO12_I:
1141 return ENCODE_ITYPE_IMM (value);
1142
1143 default:
1144 abort ();
1145 }
1146}
1147
e23eba97
NC		 1148/* Output an instruction. IP is the instruction information.
1149 ADDRESS_EXPR is an operand of the instruction to be used with
1150 RELOC_TYPE. */
1151
1152static void
1153append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
1154 bfd_reloc_code_real_type reloc_type)
1155{
1156 dwarf2_emit_insn (0);
1157
1158 if (reloc_type != BFD_RELOC_UNUSED)
1159 {
1160 reloc_howto_type *howto;
1161
1d65abb5 1162 gas_assert (address_expr);
e23eba97
NC		 1163 if (reloc_type == BFD_RELOC_12_PCREL
1164 || reloc_type == BFD_RELOC_RISCV_JMP)
1165 {
1166 int j = reloc_type == BFD_RELOC_RISCV_JMP;
1167 int best_case = riscv_insn_length (ip->insn_opcode);
1168 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
743f5cfc
JW		 1169
1170 if (now_seg == absolute_section)
1171 {
1172 as_bad (_("relaxable branches not supported in absolute section"));
1173 return;
1174 }
1175
e23eba97
NC		 1176 add_relaxed_insn (ip, worst_case, best_case,
1177 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
1178 address_expr->X_add_symbol,
1179 address_expr->X_add_number);
1180 return;
1181 }
45f76423 1182 else
e23eba97 1183 {
45f76423
AW		 1184 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
1185 if (howto == NULL)
1186 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
e23eba97 1187
45f76423
AW		 1188 ip->fixp = fix_new_exp (ip->frag, ip->where,
1189 bfd_get_reloc_size (howto),
1190 address_expr, FALSE, reloc_type);
e23eba97 1191
45f76423 1192 ip->fixp->fx_tcbit = riscv_opts.relax;
e23eba97 1193 }
e23eba97
NC		 1194 }
1195
e23eba97
NC		 1196 add_fixed_insn (ip);
1197 install_insn (ip);
f77bb6c5
JW		 1198
1199 /* We need to start a new frag after any instruction that can be
1200 optimized away or compressed by the linker during relaxation, to prevent
1201 the assembler from computing static offsets across such an instruction.
1202 This is necessary to get correct EH info. */
b1b11e92 1203 if (reloc_type == BFD_RELOC_RISCV_HI20
f77bb6c5
JW		 1204 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
1205 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
1206 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
1207 {
1208 frag_wane (frag_now);
1209 frag_new (0);
1210 }
e23eba97
NC		 1211}
1212
1213/* Build an instruction created by a macro expansion. This is passed
1214 a pointer to the count of instructions created so far, an
1215 expression, the name of the instruction to build, an operand format
1216 string, and corresponding arguments. */
1217
1218static void
1219macro_build (expressionS *ep, const char *name, const char *fmt, ...)
1220{
1221 const struct riscv_opcode *mo;
1222 struct riscv_cl_insn insn;
1223 bfd_reloc_code_real_type r;
1224 va_list args;
1225
1226 va_start (args, fmt);
1227
1228 r = BFD_RELOC_UNUSED;
629310ab 1229 mo = (struct riscv_opcode *) str_hash_find (op_hash, name);
e23eba97
NC		 1230 gas_assert (mo);
1231
1232 /* Find a non-RVC variant of the instruction. append_insn will compress
1233 it if possible. */
1234 while (riscv_insn_length (mo->match) < 4)
1235 mo++;
1236 gas_assert (strcmp (name, mo->name) == 0);
1237
1238 create_insn (&insn, mo);
1239 for (;;)
1240 {
1241 switch (*fmt++)
1242 {
1243 case 'd':
1244 INSERT_OPERAND (RD, insn, va_arg (args, int));
1245 continue;
1246
1247 case 's':
1248 INSERT_OPERAND (RS1, insn, va_arg (args, int));
1249 continue;
1250
1251 case 't':
1252 INSERT_OPERAND (RS2, insn, va_arg (args, int));
1253 continue;
1254
1255 case '>':
1256 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
1257 continue;
1258
1259 case 'j':
1260 case 'u':
1261 case 'q':
1262 gas_assert (ep != NULL);
1263 r = va_arg (args, int);
1264 continue;
1265
1266 case '\0':
1267 break;
1268 case ',':
1269 continue;
1270 default:
1271 as_fatal (_("internal error: invalid macro"));
1272 }
1273 break;
1274 }
1275 va_end (args);
1276 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1277
1278 append_insn (&insn, ep, r);
1279}
1280
db3b6ecc
KC		 1281/* Build an instruction created by a macro expansion. Like md_assemble but
1282 accept a printf-style format string and arguments. */
1283
1284static void
1285md_assemblef (const char *format, ...)
1286{
1287 char *buf = NULL;
1288 va_list ap;
1289 int r;
1290
1291 va_start (ap, format);
1292
1293 r = vasprintf (&buf, format, ap);
1294
1295 if (r < 0)
1296 as_fatal (_("internal error: vasprintf failed"));
1297
1298 md_assemble (buf);
1299 free(buf);
1300
1301 va_end (ap);
1302}
1303
e23eba97
NC		 1304/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1305 unset. */
1306static void
1307normalize_constant_expr (expressionS *ex)
1308{
1309 if (xlen > 32)
1310 return;
1311 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1312 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1313 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1314 - 0x80000000);
1315}
1316
ca2fd32c
JW		 1317/* Fail if an expression EX is not a constant. IP is the instruction using EX.
1318 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
e23eba97
NC		 1319
1320static void
ca2fd32c
JW		 1321check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
1322 bfd_boolean maybe_csr)
e23eba97
NC		 1323{
1324 if (ex->X_op == O_big)
1325 as_bad (_("unsupported large constant"));
ca2fd32c
JW		 1326 else if (maybe_csr && ex->X_op == O_symbol)
1327 as_bad (_("unknown CSR `%s'"),
1328 S_GET_NAME (ex->X_add_symbol));
e23eba97
NC		 1329 else if (ex->X_op != O_constant)
1330 as_bad (_("Instruction %s requires absolute expression"),
1331 ip->insn_mo->name);
1332 normalize_constant_expr (ex);
1333}
1334
1335static symbolS *
1336make_internal_label (void)
1337{
e01e1cee
AM		 1338 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now,
1339 frag_now_fix ());
e23eba97
NC		 1340}
1341
1342/* Load an entry from the GOT. */
1343static void
1344pcrel_access (int destreg, int tempreg, expressionS *ep,
1345 const char *lo_insn, const char *lo_pattern,
1346 bfd_reloc_code_real_type hi_reloc,
1347 bfd_reloc_code_real_type lo_reloc)
1348{
1349 expressionS ep2;
1350 ep2.X_op = O_symbol;
1351 ep2.X_add_symbol = make_internal_label ();
1352 ep2.X_add_number = 0;
1353
1354 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1355 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1356}
1357
1358static void
1359pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1360 bfd_reloc_code_real_type hi_reloc,
1361 bfd_reloc_code_real_type lo_reloc)
1362{
1363 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1364}
1365
1366static void
1367pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1368 bfd_reloc_code_real_type hi_reloc,
1369 bfd_reloc_code_real_type lo_reloc)
1370{
1371 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1372}
1373
1374/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1375static void
1376riscv_call (int destreg, int tempreg, expressionS *ep,
1377 bfd_reloc_code_real_type reloc)
1378{
b1b11e92
AM		 1379 /* Ensure the jalr is emitted to the same frag as the auipc. */
1380 frag_grow (8);
e23eba97
NC		 1381 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1382 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
b1b11e92
AM		 1383 /* See comment at end of append_insn. */
1384 frag_wane (frag_now);
1385 frag_new (0);
e23eba97
NC		 1386}
1387
1388/* Load an integer constant into a register. */
1389
1390static void
1391load_const (int reg, expressionS *ep)
1392{
1393 int shift = RISCV_IMM_BITS;
4f7cc141 1394 bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1);
e23eba97 1395 expressionS upper = *ep, lower = *ep;
4f7cc141 1396 lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign;
e23eba97
NC		 1397 upper.X_add_number -= lower.X_add_number;
1398
1399 if (ep->X_op != O_constant)
1400 {
1401 as_bad (_("unsupported large constant"));
1402 return;
1403 }
1404
1d65abb5 1405 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
e23eba97
NC		 1406 {
1407 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1408 while (((upper.X_add_number >> shift) & 1) == 0)
1409 shift++;
1410
1411 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1d65abb5 1412 load_const (reg, &upper);
e23eba97 1413
db3b6ecc 1414 md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift);
e23eba97 1415 if (lower.X_add_number != 0)
db3b6ecc
KC		 1416 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg,
1417 lower.X_add_number);
e23eba97
NC		 1418 }
1419 else
1420 {
1421 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1422 int hi_reg = 0;
1423
1424 if (upper.X_add_number != 0)
1425 {
db3b6ecc
KC		 1426 /* Discard low part and zero-extend upper immediate. */
1427 upper_imm = ((uint32_t)upper.X_add_number >> shift);
1428
1429 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm);
e23eba97
NC		 1430 hi_reg = reg;
1431 }
1432
1433 if (lower.X_add_number != 0 || hi_reg == 0)
db3b6ecc
KC		 1434 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg,
1435 lower.X_add_number);
e23eba97
NC		 1436 }
1437}
1438
c2137f55
NC		 1439/* Zero extend and sign extend byte/half-word/word. */
1440
1441static void
1442riscv_ext (int destreg, int srcreg, unsigned shift, bfd_boolean sign)
1443{
1444 if (sign)
1445 {
1446 md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
1447 md_assemblef ("srai x%d, x%d, 0x%x", destreg, destreg, shift);
1448 }
1449 else
1450 {
1451 md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
1452 md_assemblef ("srli x%d, x%d, 0x%x", destreg, destreg, shift);
1453 }
1454}
1455
e23eba97
NC		 1456/* Expand RISC-V assembly macros into one or more instructions. */
1457static void
1458macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1459 bfd_reloc_code_real_type *imm_reloc)
1460{
1461 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1462 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1463 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1464 int mask = ip->insn_mo->mask;
1465
1466 switch (mask)
1467 {
1468 case M_LI:
1469 load_const (rd, imm_expr);
1470 break;
1471
1472 case M_LA:
1473 case M_LLA:
1474 /* Load the address of a symbol into a register. */
1475 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1476 as_bad (_("offset too large"));
1477
1478 if (imm_expr->X_op == O_constant)
1479 load_const (rd, imm_expr);
1480 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */
1481 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1482 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1483 else /* Local PIC symbol, or any non-PIC symbol */
1484 pcrel_load (rd, rd, imm_expr, "addi",
1485 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1486 break;
1487
1488 case M_LA_TLS_GD:
1489 pcrel_load (rd, rd, imm_expr, "addi",
1490 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1491 break;
1492
1493 case M_LA_TLS_IE:
1494 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1495 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1496 break;
1497
1498 case M_LB:
1499 pcrel_load (rd, rd, imm_expr, "lb",
1500 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1501 break;
1502
1503 case M_LBU:
1504 pcrel_load (rd, rd, imm_expr, "lbu",
1505 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1506 break;
1507
1508 case M_LH:
1509 pcrel_load (rd, rd, imm_expr, "lh",
1510 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1511 break;
1512
1513 case M_LHU:
1514 pcrel_load (rd, rd, imm_expr, "lhu",
1515 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1516 break;
1517
1518 case M_LW:
1519 pcrel_load (rd, rd, imm_expr, "lw",
1520 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1521 break;
1522
1523 case M_LWU:
1524 pcrel_load (rd, rd, imm_expr, "lwu",
1525 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1526 break;
1527
1528 case M_LD:
1529 pcrel_load (rd, rd, imm_expr, "ld",
1530 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1531 break;
1532
1533 case M_FLW:
1534 pcrel_load (rd, rs1, imm_expr, "flw",
1535 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1536 break;
1537
1538 case M_FLD:
1539 pcrel_load (rd, rs1, imm_expr, "fld",
1540 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1541 break;
1542
1543 case M_SB:
1544 pcrel_store (rs2, rs1, imm_expr, "sb",
1545 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1546 break;
1547
1548 case M_SH:
1549 pcrel_store (rs2, rs1, imm_expr, "sh",
1550 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1551 break;
1552
1553 case M_SW:
1554 pcrel_store (rs2, rs1, imm_expr, "sw",
1555 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1556 break;
1557
1558 case M_SD:
1559 pcrel_store (rs2, rs1, imm_expr, "sd",
1560 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1561 break;
1562
1563 case M_FSW:
1564 pcrel_store (rs2, rs1, imm_expr, "fsw",
1565 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1566 break;
1567
1568 case M_FSD:
1569 pcrel_store (rs2, rs1, imm_expr, "fsd",
1570 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1571 break;
1572
1573 case M_CALL:
1574 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1575 break;
1576
c2137f55
NC		 1577 case M_ZEXTH:
1578 riscv_ext (rd, rs1, xlen - 16, FALSE);
1579 break;
1580
1581 case M_ZEXTW:
1582 riscv_ext (rd, rs1, xlen - 32, FALSE);
1583 break;
1584
1585 case M_SEXTB:
1586 riscv_ext (rd, rs1, xlen - 8, TRUE);
1587 break;
1588
1589 case M_SEXTH:
1590 riscv_ext (rd, rs1, xlen - 16, TRUE);
1591 break;
1592
e23eba97
NC		 1593 default:
1594 as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
1595 break;
1596 }
1597}
1598
1599static const struct percent_op_match percent_op_utype[] =
1600{
1601 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1602 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
dee35d02 1603 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
e23eba97
NC		 1604 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1605 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1606 {"%hi", BFD_RELOC_RISCV_HI20},
1607 {0, 0}
1608};
1609
1610static const struct percent_op_match percent_op_itype[] =
1611{
1612 {"%lo", BFD_RELOC_RISCV_LO12_I},
1613 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1614 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1615 {0, 0}
1616};
1617
1618static const struct percent_op_match percent_op_stype[] =
1619{
1620 {"%lo", BFD_RELOC_RISCV_LO12_S},
1621 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1622 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1623 {0, 0}
1624};
1625
1626static const struct percent_op_match percent_op_rtype[] =
1627{
1628 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1629 {0, 0}
1630};
1631
f50fabe4
JW		 1632static const struct percent_op_match percent_op_null[] =
1633{
1634 {0, 0}
1635};
1636
e23eba97
NC		 1637/* Return true if *STR points to a relocation operator. When returning true,
1638 move *STR over the operator and store its relocation code in *RELOC.
1639 Leave both *STR and *RELOC alone when returning false. */
1640
1641static bfd_boolean
1642parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1643 const struct percent_op_match *percent_op)
1644{
1645 for ( ; percent_op->str; percent_op++)
1646 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1647 {
1648 int len = strlen (percent_op->str);
1649
1650 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1651 continue;
1652
1653 *str += strlen (percent_op->str);
1654 *reloc = percent_op->reloc;
1655
1656 /* Check whether the output BFD supports this relocation.
1657 If not, issue an error and fall back on something safe. */
45f76423
AW		 1658 if (*reloc != BFD_RELOC_UNUSED
1659 && !bfd_reloc_type_lookup (stdoutput, *reloc))
e23eba97
NC		 1660 {
1661 as_bad ("relocation %s isn't supported by the current ABI",
1662 percent_op->str);
1663 *reloc = BFD_RELOC_UNUSED;
1664 }
1665 return TRUE;
1666 }
1667 return FALSE;
1668}
1669
1670static void
1671my_getExpression (expressionS *ep, char *str)
1672{
1673 char *save_in;
1674
1675 save_in = input_line_pointer;
1676 input_line_pointer = str;
1677 expression (ep);
1678 expr_end = input_line_pointer;
1679 input_line_pointer = save_in;
1680}
1681
1682/* Parse string STR as a 16-bit relocatable operand. Store the
1683 expression in *EP and the relocation, if any, in RELOC.
1684 Return the number of relocation operators used (0 or 1).
1685
1686 On exit, EXPR_END points to the first character after the expression. */
1687
1688static size_t
1689my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1690 char *str, const struct percent_op_match *percent_op)
1691{
1692 size_t reloc_index;
1693 unsigned crux_depth, str_depth, regno;
1694 char *crux;
1695
8970c022
JW		 1696 /* First, check for integer registers. No callers can accept a reg, but
1697 we need to avoid accidentally creating a useless undefined symbol below,
1698 if this is an instruction pattern that can't match. A glibc build fails
1699 if this is removed. */
e23eba97
NC		 1700 if (reg_lookup (&str, RCLASS_GPR, &regno))
1701 {
1702 ep->X_op = O_register;
1703 ep->X_add_number = regno;
8970c022 1704 expr_end = str;
e23eba97
NC		 1705 return 0;
1706 }
1707
1708 /* Search for the start of the main expression.
1709 End the loop with CRUX pointing to the start
1710 of the main expression and with CRUX_DEPTH containing the number
1711 of open brackets at that point. */
1712 reloc_index = -1;
1713 str_depth = 0;
1714 do
1715 {
1716 reloc_index++;
1717 crux = str;
1718 crux_depth = str_depth;
1719
1720 /* Skip over whitespace and brackets, keeping count of the number
1721 of brackets. */
1722 while (*str == ' ' || *str == '\t' || *str == '(')
1723 if (*str++ == '(')
1724 str_depth++;
1725 }
1726 while (*str == '%'
1727 && reloc_index < 1
1728 && parse_relocation (&str, reloc, percent_op));
1729
1730 my_getExpression (ep, crux);
1731 str = expr_end;
1732
1733 /* Match every open bracket. */
1734 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1735 if (*str++ == ')')
1736 crux_depth--;
1737
1738 if (crux_depth > 0)
1739 as_bad ("unclosed '('");
1740
1741 expr_end = str;
1742
1743 return reloc_index;
1744}
1745
0e35537d
JW		 1746/* Parse opcode name, could be an mnemonics or number. */
1747static size_t
1748my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1749 char *str, const struct percent_op_match *percent_op)
1750{
1751 const struct opcode_name_t *o = opcode_name_lookup (&str);
1752
1753 if (o != NULL)
1754 {
1755 ep->X_op = O_constant;
1756 ep->X_add_number = o->val;
1757 return 0;
1758 }
1759
1760 return my_getSmallExpression (ep, reloc, str, percent_op);
1761}
1762
f0531ed6
JW		 1763/* Detect and handle implicitly zero load-store offsets. For example,
1764 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1765 an implicit offset was detected. */
1766
1767static bfd_boolean
89424b1d 1768riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
f0531ed6
JW		 1769{
1770 /* Check whether there is only a single bracketed expression left.
1771 If so, it must be the base register and the constant must be zero. */
1772 if (*s == '(' && strchr (s + 1, '(') == 0)
1773 {
89424b1d
MR		 1774 ep->X_op = O_constant;
1775 ep->X_add_number = 0;
f0531ed6
JW		 1776 return TRUE;
1777 }
1778
1779 return FALSE;
1780}
1781
54b2aec1
NC		 1782/* All RISC-V CSR instructions belong to one of these classes. */
1783
1784enum csr_insn_type
1785{
1786 INSN_NOT_CSR,
1787 INSN_CSRRW,
1788 INSN_CSRRS,
1789 INSN_CSRRC
1790};
1791
1792/* Return which CSR instruction is checking. */
1793
1794static enum csr_insn_type
1795riscv_csr_insn_type (insn_t insn)
1796{
1797 if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
1798 || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
1799 return INSN_CSRRW;
1800 else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
1801 || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
1802 return INSN_CSRRS;
1803 else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
1804 || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
1805 return INSN_CSRRC;
1806 else
1807 return INSN_NOT_CSR;
1808}
1809
1810/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1811 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1812 CSR address is 0x3. */
1813
1814static bfd_boolean
1815riscv_csr_read_only_check (insn_t insn)
1816{
1817 int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
1818 int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
1819 int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
1820 enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
1821
1822 if (readonly
1823 && (((csr_insn == INSN_CSRRS
1824 || csr_insn == INSN_CSRRC)
1825 && rs1 != 0)
1826 || csr_insn == INSN_CSRRW))
1827 return FALSE;
1828
1829 return TRUE;
1830}
1831
1a79004f
NC		 1832/* Return True if it is a privileged instruction. Otherwise, return FALSE.
1833
1834 uret is actually a N-ext instruction. So it is better to regard it as
1835 an user instruction rather than the priv instruction.
1836
1837 hret is used to return from traps in H-mode. H-mode is removed since
1838 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1839 Therefore, hret should be controlled by the hypervisor spec rather than
1840 priv spec in the future.
1841
1842 dret is defined in the debug spec, so it should be checked in the future,
1843 too. */
1844
1845static bfd_boolean
1846riscv_is_priv_insn (insn_t insn)
1847{
1848 return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
1849 || ((insn ^ MATCH_MRET) & MASK_MRET) == 0
1850 || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0
1851 || ((insn ^ MATCH_WFI) & MASK_WFI) == 0
1852 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1853 check it here to keep the compatible. Maybe we should issue warning
1854 if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
1855 We already have a similar check for CSR, but not yet for instructions.
1856 It would be good if we could check the spec versions both for CSR and
1857 instructions, but not here. */
1858 || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
1859}
1860
e23eba97
NC		 1861/* This routine assembles an instruction into its binary format. As a
1862 side effect, it sets the global variable imm_reloc to the type of
1863 relocation to do if one of the operands is an address expression. */
1864
1865static const char *
1866riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
629310ab 1867 bfd_reloc_code_real_type *imm_reloc, htab_t hash)
e23eba97
NC		 1868{
1869 char *s;
1870 const char *args;
1871 char c = 0;
1872 struct riscv_opcode *insn;
1873 char *argsStart;
1874 unsigned int regno;
1875 char save_c = 0;
1876 int argnum;
1877 const struct percent_op_match *p;
1878 const char *error = "unrecognized opcode";
54b2aec1
NC		 1879 /* Indicate we are assembling instruction with CSR. */
1880 bfd_boolean insn_with_csr = FALSE;
e23eba97
NC		 1881
1882 /* Parse the name of the instruction. Terminate the string if whitespace
629310ab 1883 is found so that str_hash_find only sees the name part of the string. */
e23eba97
NC		 1884 for (s = str; *s != '\0'; ++s)
1885 if (ISSPACE (*s))
1886 {
1887 save_c = *s;
1888 *s++ = '\0';
1889 break;
1890 }
1891
629310ab 1892 insn = (struct riscv_opcode *) str_hash_find (hash, str);
e23eba97
NC		 1893
1894 argsStart = s;
1895 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1896 {
1080bf78
JW		 1897 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
1898 continue;
1899
7e9ad3a3 1900 if (!riscv_multi_subset_supports (insn->insn_class))
e23eba97
NC		 1901 continue;
1902
1903 create_insn (ip, insn);
1904 argnum = 1;
1905
1906 imm_expr->X_op = O_absent;
1907 *imm_reloc = BFD_RELOC_UNUSED;
1908 p = percent_op_itype;
1909
1910 for (args = insn->args;; ++args)
1911 {
1912 s += strspn (s, " \t");
1913 switch (*args)
1914 {
1915 case '\0': /* End of args. */
1916 if (insn->pinfo != INSN_MACRO)
1917 {
1918 if (!insn->match_func (insn, ip->insn_opcode))
1919 break;
0e35537d
JW		 1920
1921 /* For .insn, insn->match and insn->mask are 0. */
1922 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
1923 ? ip->insn_opcode
1924 : insn->match) == 2
1925 && !riscv_opts.rvc)
e23eba97 1926 break;
54b2aec1 1927
1a79004f
NC		 1928 if (riscv_is_priv_insn (ip->insn_opcode))
1929 explicit_priv_attr = TRUE;
1930
54b2aec1
NC		 1931 /* Check if we write a read-only CSR by the CSR
1932 instruction. */
1933 if (insn_with_csr
1934 && riscv_opts.csr_check
1935 && !riscv_csr_read_only_check (ip->insn_opcode))
1936 {
1937 /* Restore the character in advance, since we want to
1938 report the detailed warning message here. */
1939 if (save_c)
1940 *(argsStart - 1) = save_c;
1941 as_warn (_("Read-only CSR is written `%s'"), str);
1942 insn_with_csr = FALSE;
1943 }
e23eba97
NC		 1944 }
1945 if (*s != '\0')
1946 break;
1947 /* Successful assembly. */
1948 error = NULL;
54b2aec1 1949 insn_with_csr = FALSE;
e23eba97
NC		 1950 goto out;
1951
1952 case 'C': /* RVC */
1953 switch (*++args)
1954 {
1955 case 's': /* RS1 x8-x15 */
1956 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1957 || !(regno >= 8 && regno <= 15))
1958 break;
1959 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1960 continue;
1961 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1962 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1963 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
1964 break;
1965 continue;
1966 case 't': /* RS2 x8-x15 */
1967 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1968 || !(regno >= 8 && regno <= 15))
1969 break;
1970 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1971 continue;
1972 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1973 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1974 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
1975 break;
1976 continue;
1977 case 'U': /* RS1, constrained to equal RD. */
1978 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1979 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
1980 break;
1981 continue;
1982 case 'V': /* RS2 */
1983 if (!reg_lookup (&s, RCLASS_GPR, &regno))
1984 break;
1985 INSERT_OPERAND (CRS2, *ip, regno);
1986 continue;
1987 case 'c': /* RS1, constrained to equal sp. */
1988 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1989 || regno != X_SP)
1990 break;
1991 continue;
ca0bc150
JW		 1992 case 'z': /* RS2, contrained to equal x0. */
1993 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1994 || regno != 0)
1995 break;
1996 continue;
e23eba97
NC		 1997 case '>':
1998 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1999 || imm_expr->X_op != O_constant
2000 || imm_expr->X_add_number <= 0
2001 || imm_expr->X_add_number >= 64)
2002 break;
2003 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
dc1e8a47 2004 rvc_imm_done:
e23eba97
NC		 2005 s = expr_end;
2006 imm_expr->X_op = O_absent;
2007 continue;
2008 case '<':
2009 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2010 || imm_expr->X_op != O_constant
e23eba97 2011 || imm_expr->X_add_number <= 0
169ec512
AM		 2012 || imm_expr->X_add_number >= 32
2013 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2014 break;
2015 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2016 goto rvc_imm_done;
0e35537d
JW		 2017 case '8':
2018 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2019 || imm_expr->X_op != O_constant
0e35537d 2020 || imm_expr->X_add_number < 0
169ec512
AM		 2021 || imm_expr->X_add_number >= 256
2022 || !VALID_RVC_UIMM8 ((valueT) imm_expr->X_add_number))
0e35537d
JW		 2023 break;
2024 ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
2025 goto rvc_imm_done;
e23eba97
NC		 2026 case 'i':
2027 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2028 || imm_expr->X_op != O_constant
2029 || imm_expr->X_add_number == 0
169ec512 2030 || !VALID_RVC_SIMM3 ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2031 break;
2032 ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
2033 goto rvc_imm_done;
2034 case 'j':
2035 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2036 || imm_expr->X_op != O_constant
2037 || imm_expr->X_add_number == 0
169ec512 2038 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2039 break;
2040 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2041 goto rvc_imm_done;
2042 case 'k':
f0531ed6
JW		 2043 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2044 continue;
e23eba97
NC		 2045 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2046 || imm_expr->X_op != O_constant
169ec512 2047 || !VALID_RVC_LW_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2048 break;
2049 ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
2050 goto rvc_imm_done;
2051 case 'l':
f0531ed6
JW		 2052 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2053 continue;
e23eba97
NC		 2054 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2055 || imm_expr->X_op != O_constant
169ec512 2056 || !VALID_RVC_LD_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2057 break;
2058 ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
2059 goto rvc_imm_done;
2060 case 'm':
f0531ed6
JW		 2061 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2062 continue;
e23eba97
NC		 2063 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2064 || imm_expr->X_op != O_constant
169ec512 2065 || !VALID_RVC_LWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2066 break;
2067 ip->insn_opcode |=
2068 ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
2069 goto rvc_imm_done;
2070 case 'n':
f0531ed6
JW		 2071 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2072 continue;
e23eba97
NC		 2073 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2074 || imm_expr->X_op != O_constant
169ec512 2075 || !VALID_RVC_LDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2076 break;
2077 ip->insn_opcode |=
2078 ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
2079 goto rvc_imm_done;
b416fe87
KC		 2080 case 'o':
2081 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2082 || imm_expr->X_op != O_constant
21a186f2
JW		 2083 /* C.addiw, c.li, and c.andi allow zero immediate.
2084 C.addi allows zero immediate as hint. Otherwise this
2085 is same as 'j'. */
169ec512 2086 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
b416fe87
KC		 2087 break;
2088 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2089 goto rvc_imm_done;
e23eba97
NC		 2090 case 'K':
2091 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2092 || imm_expr->X_op != O_constant
169ec512
AM		 2093 || imm_expr->X_add_number == 0
2094 || !VALID_RVC_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2095 break;
2096 ip->insn_opcode |=
2097 ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
2098 goto rvc_imm_done;
2099 case 'L':
2100 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2101 || imm_expr->X_op != O_constant
169ec512
AM		 2102 || imm_expr->X_add_number == 0
2103 || !VALID_RVC_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2104 break;
2105 ip->insn_opcode |=
2106 ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
2107 goto rvc_imm_done;
2108 case 'M':
f0531ed6
JW		 2109 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2110 continue;
e23eba97
NC		 2111 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2112 || imm_expr->X_op != O_constant
169ec512 2113 || !VALID_RVC_SWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2114 break;
2115 ip->insn_opcode |=
2116 ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
2117 goto rvc_imm_done;
2118 case 'N':
f0531ed6
JW		 2119 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2120 continue;
e23eba97
NC		 2121 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2122 || imm_expr->X_op != O_constant
169ec512 2123 || !VALID_RVC_SDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2124 break;
2125 ip->insn_opcode |=
2126 ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
2127 goto rvc_imm_done;
2128 case 'u':
2129 p = percent_op_utype;
2130 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
2131 break;
dc1e8a47 2132 rvc_lui:
e23eba97
NC		 2133 if (imm_expr->X_op != O_constant
2134 || imm_expr->X_add_number <= 0
2135 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
2136 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
2137 && (imm_expr->X_add_number <
2138 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
2139 break;
2140 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2141 goto rvc_imm_done;
2142 case 'v':
2143 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2144 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
2145 || ((int32_t)imm_expr->X_add_number
2146 != imm_expr->X_add_number))
2147 break;
2148 imm_expr->X_add_number =
2149 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
2150 goto rvc_lui;
2151 case 'p':
2152 goto branch;
2153 case 'a':
2154 goto jump;
0e35537d
JW		 2155 case 'S': /* Floating-point RS1 x8-x15. */
2156 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2157 || !(regno >= 8 && regno <= 15))
2158 break;
2159 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2160 continue;
e23eba97
NC		 2161 case 'D': /* Floating-point RS2 x8-x15. */
2162 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2163 || !(regno >= 8 && regno <= 15))
2164 break;
2165 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2166 continue;
2167 case 'T': /* Floating-point RS2. */
2168 if (!reg_lookup (&s, RCLASS_FPR, &regno))
2169 break;
2170 INSERT_OPERAND (CRS2, *ip, regno);
2171 continue;
0e35537d
JW		 2172 case 'F':
2173 switch (*++args)
2174 {
4765cd61
JW		 2175 case '6':
2176 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2177 || imm_expr->X_op != O_constant
2178 || imm_expr->X_add_number < 0
2179 || imm_expr->X_add_number >= 64)
2180 {
2181 as_bad (_("bad value for funct6 field, "
2182 "value must be 0...64"));
2183 break;
2184 }
2185
2186 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
2187 imm_expr->X_op = O_absent;
2188 s = expr_end;
2189 continue;
0e35537d
JW		 2190 case '4':
2191 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2192 || imm_expr->X_op != O_constant
2193 || imm_expr->X_add_number < 0
2194 || imm_expr->X_add_number >= 16)
2195 {
2196 as_bad (_("bad value for funct4 field, "
2197 "value must be 0...15"));
2198 break;
2199 }
2200
2201 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
2202 imm_expr->X_op = O_absent;
2203 s = expr_end;
2204 continue;
2205 case '3':
2206 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2207 || imm_expr->X_op != O_constant
2208 || imm_expr->X_add_number < 0
2209 || imm_expr->X_add_number >= 8)
2210 {
2211 as_bad (_("bad value for funct3 field, "
2212 "value must be 0...7"));
2213 break;
2214 }
2215 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
2216 imm_expr->X_op = O_absent;
2217 s = expr_end;
2218 continue;
4765cd61
JW		 2219 case '2':
2220 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2221 || imm_expr->X_op != O_constant
2222 || imm_expr->X_add_number < 0
2223 || imm_expr->X_add_number >= 4)
2224 {
2225 as_bad (_("bad value for funct2 field, "
2226 "value must be 0...3"));
2227 break;
2228 }
2229 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number);
2230 imm_expr->X_op = O_absent;
2231 s = expr_end;
2232 continue;
0e35537d
JW		 2233 default:
2234 as_bad (_("bad compressed FUNCT field"
2235 " specifier 'CF%c'\n"),
2236 *args);
2237 }
2238 break;
2239
e23eba97
NC		 2240 default:
2241 as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
2242 }
2243 break;
2244
2245 case ',':
2246 ++argnum;
2247 if (*s++ == *args)
2248 continue;
2249 s--;
2250 break;
2251
2252 case '(':
2253 case ')':
2254 case '[':
2255 case ']':
2256 if (*s++ == *args)
2257 continue;
2258 break;
2259
2260 case '<': /* Shift amount, 0 - 31. */
2261 my_getExpression (imm_expr, s);
ca2fd32c 2262 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2263 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2264 as_bad (_("Improper shift amount (%lu)"),
2265 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2266 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
2267 imm_expr->X_op = O_absent;
2268 s = expr_end;
2269 continue;
2270
2271 case '>': /* Shift amount, 0 - (XLEN-1). */
2272 my_getExpression (imm_expr, s);
ca2fd32c 2273 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2274 if ((unsigned long) imm_expr->X_add_number >= xlen)
94f78a77
AW		 2275 as_bad (_("Improper shift amount (%lu)"),
2276 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2277 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
2278 imm_expr->X_op = O_absent;
2279 s = expr_end;
2280 continue;
2281
2282 case 'Z': /* CSRRxI immediate. */
2283 my_getExpression (imm_expr, s);
ca2fd32c 2284 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2285 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2286 as_bad (_("Improper CSRxI immediate (%lu)"),
2287 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2288 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
2289 imm_expr->X_op = O_absent;
2290 s = expr_end;
2291 continue;
2292
2293 case 'E': /* Control register. */
54b2aec1 2294 insn_with_csr = TRUE;
1a79004f 2295 explicit_priv_attr = TRUE;
e23eba97
NC		 2296 if (reg_lookup (&s, RCLASS_CSR, &regno))
2297 INSERT_OPERAND (CSR, *ip, regno);
2298 else
2299 {
2300 my_getExpression (imm_expr, s);
ca2fd32c 2301 check_absolute_expr (ip, imm_expr, TRUE);
e23eba97 2302 if ((unsigned long) imm_expr->X_add_number > 0xfff)
94f78a77
AW		 2303 as_bad (_("Improper CSR address (%lu)"),
2304 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2305 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
2306 imm_expr->X_op = O_absent;
2307 s = expr_end;
2308 }
2309 continue;
2310
2311 case 'm': /* Rounding mode. */
2312 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
2313 {
2314 INSERT_OPERAND (RM, *ip, regno);
2315 continue;
2316 }
2317 break;
2318
2319 case 'P':
2320 case 'Q': /* Fence predecessor/successor. */
2321 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
2322 &regno))
2323 {
2324 if (*args == 'P')
2325 INSERT_OPERAND (PRED, *ip, regno);
2326 else
2327 INSERT_OPERAND (SUCC, *ip, regno);
2328 continue;
2329 }
2330 break;
2331
2332 case 'd': /* Destination register. */
2333 case 's': /* Source register. */
2334 case 't': /* Target register. */
0e35537d 2335 case 'r': /* rs3. */
e23eba97
NC		 2336 if (reg_lookup (&s, RCLASS_GPR, &regno))
2337 {
2338 c = *args;
2339 if (*s == ' ')
2340 ++s;
2341
2342 /* Now that we have assembled one operand, we use the args
2343 string to figure out where it goes in the instruction. */
2344 switch (c)
2345 {
2346 case 's':
2347 INSERT_OPERAND (RS1, *ip, regno);
2348 break;
2349 case 'd':
2350 INSERT_OPERAND (RD, *ip, regno);
2351 break;
2352 case 't':
2353 INSERT_OPERAND (RS2, *ip, regno);
2354 break;
0e35537d
JW		 2355 case 'r':
2356 INSERT_OPERAND (RS3, *ip, regno);
2357 break;
e23eba97
NC		 2358 }
2359 continue;
2360 }
2361 break;
2362
2363 case 'D': /* Floating point rd. */
2364 case 'S': /* Floating point rs1. */
2365 case 'T': /* Floating point rs2. */
2366 case 'U': /* Floating point rs1 and rs2. */
2367 case 'R': /* Floating point rs3. */
2368 if (reg_lookup (&s, RCLASS_FPR, &regno))
2369 {
2370 c = *args;
2371 if (*s == ' ')
2372 ++s;
2373 switch (c)
2374 {
2375 case 'D':
2376 INSERT_OPERAND (RD, *ip, regno);
2377 break;
2378 case 'S':
2379 INSERT_OPERAND (RS1, *ip, regno);
2380 break;
2381 case 'U':
2382 INSERT_OPERAND (RS1, *ip, regno);
2383 /* fallthru */
2384 case 'T':
2385 INSERT_OPERAND (RS2, *ip, regno);
2386 break;
2387 case 'R':
2388 INSERT_OPERAND (RS3, *ip, regno);
2389 break;
2390 }
2391 continue;
2392 }
2393
2394 break;
2395
2396 case 'I':
2397 my_getExpression (imm_expr, s);
2398 if (imm_expr->X_op != O_big
2399 && imm_expr->X_op != O_constant)
2400 break;
2401 normalize_constant_expr (imm_expr);
2402 s = expr_end;
2403 continue;
2404
2405 case 'A':
2406 my_getExpression (imm_expr, s);
2407 normalize_constant_expr (imm_expr);
2408 /* The 'A' format specifier must be a symbol. */
2409 if (imm_expr->X_op != O_symbol)
2410 break;
2411 *imm_reloc = BFD_RELOC_32;
2412 s = expr_end;
2413 continue;
2414
160d1b3d
SH		 2415 case 'B':
2416 my_getExpression (imm_expr, s);
2417 normalize_constant_expr (imm_expr);
2418 /* The 'B' format specifier must be a symbol or a constant. */
2419 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
2420 break;
2421 if (imm_expr->X_op == O_symbol)
2422 *imm_reloc = BFD_RELOC_32;
2423 s = expr_end;
2424 continue;
2425
e23eba97 2426 case 'j': /* Sign-extended immediate. */
e23eba97 2427 p = percent_op_itype;
f50fabe4 2428 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
e23eba97
NC		 2429 goto alu_op;
2430 case 'q': /* Store displacement. */
2431 p = percent_op_stype;
2432 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
2433 goto load_store;
2434 case 'o': /* Load displacement. */
2435 p = percent_op_itype;
2436 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
2437 goto load_store;
f50fabe4 2438 case '1': /* 4-operand add, must be %tprel_add. */
e23eba97 2439 p = percent_op_rtype;
f50fabe4
JW		 2440 goto alu_op;
2441 case '0': /* AMO "displacement," which must be zero. */
2442 p = percent_op_null;
dc1e8a47 2443 load_store:
f0531ed6 2444 if (riscv_handle_implicit_zero_offset (imm_expr, s))
e23eba97 2445 continue;
dc1e8a47 2446 alu_op:
e23eba97
NC		 2447 /* If this value won't fit into a 16 bit offset, then go
2448 find a macro that will generate the 32 bit offset
2449 code pattern. */
2450 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
2451 {
2452 normalize_constant_expr (imm_expr);
2453 if (imm_expr->X_op != O_constant
2454 || (*args == '0' && imm_expr->X_add_number != 0)
f50fabe4 2455 || (*args == '1')
e23eba97
NC		 2456 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
2457 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
2458 break;
2459 }
2460
2461 s = expr_end;
2462 continue;
2463
2464 case 'p': /* PC-relative offset. */
dc1e8a47 2465 branch:
e23eba97
NC		 2466 *imm_reloc = BFD_RELOC_12_PCREL;
2467 my_getExpression (imm_expr, s);
2468 s = expr_end;
2469 continue;
2470
2471 case 'u': /* Upper 20 bits. */
2472 p = percent_op_utype;
4288405d 2473 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
e23eba97 2474 {
4288405d
JW		 2475 if (imm_expr->X_op != O_constant)
2476 break;
2477
e23eba97
NC		 2478 if (imm_expr->X_add_number < 0
2479 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
2480 as_bad (_("lui expression not in range 0..1048575"));
2481
2482 *imm_reloc = BFD_RELOC_RISCV_HI20;
2483 imm_expr->X_add_number <<= RISCV_IMM_BITS;
2484 }
2485 s = expr_end;
2486 continue;
2487
2488 case 'a': /* 20-bit PC-relative offset. */
dc1e8a47 2489 jump:
e23eba97
NC		 2490 my_getExpression (imm_expr, s);
2491 s = expr_end;
2492 *imm_reloc = BFD_RELOC_RISCV_JMP;
2493 continue;
2494
2495 case 'c':
2496 my_getExpression (imm_expr, s);
2497 s = expr_end;
2498 if (strcmp (s, "@plt") == 0)
2499 {
2500 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2501 s += 4;
2502 }
2503 else
2504 *imm_reloc = BFD_RELOC_RISCV_CALL;
2505 continue;
0e35537d
JW		 2506 case 'O':
2507 switch (*++args)
2508 {
2509 case '4':
2510 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2511 || imm_expr->X_op != O_constant
2512 || imm_expr->X_add_number < 0
2513 || imm_expr->X_add_number >= 128
2514 || (imm_expr->X_add_number & 0x3) != 3)
2515 {
2516 as_bad (_("bad value for opcode field, "
2517 "value must be 0...127 and "
2518 "lower 2 bits must be 0x3"));
2519 break;
2520 }
2521
2522 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2523 imm_expr->X_op = O_absent;
2524 s = expr_end;
2525 continue;
2526 case '2':
2527 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2528 || imm_expr->X_op != O_constant
2529 || imm_expr->X_add_number < 0
2530 || imm_expr->X_add_number >= 3)
2531 {
2532 as_bad (_("bad value for opcode field, "
2533 "value must be 0...2"));
2534 break;
2535 }
2536
2537 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2538 imm_expr->X_op = O_absent;
2539 s = expr_end;
2540 continue;
2541 default:
2542 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args);
2543 }
2544 break;
2545
2546 case 'F':
2547 switch (*++args)
2548 {
2549 case '7':
2550 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2551 || imm_expr->X_op != O_constant
2552 || imm_expr->X_add_number < 0
2553 || imm_expr->X_add_number >= 128)
2554 {
2555 as_bad (_("bad value for funct7 field, "
2556 "value must be 0...127"));
2557 break;
2558 }
2559
2560 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2561 imm_expr->X_op = O_absent;
2562 s = expr_end;
2563 continue;
2564 case '3':
2565 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2566 || imm_expr->X_op != O_constant
2567 || imm_expr->X_add_number < 0
2568 || imm_expr->X_add_number >= 8)
2569 {
2570 as_bad (_("bad value for funct3 field, "
2571 "value must be 0...7"));
2572 break;
2573 }
2574
2575 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2576 imm_expr->X_op = O_absent;
2577 s = expr_end;
2578 continue;
2579 case '2':
2580 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2581 || imm_expr->X_op != O_constant
2582 || imm_expr->X_add_number < 0
2583 || imm_expr->X_add_number >= 4)
2584 {
2585 as_bad (_("bad value for funct2 field, "
2586 "value must be 0...3"));
2587 break;
2588 }
2589
2590 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2591 imm_expr->X_op = O_absent;
2592 s = expr_end;
2593 continue;
2594
2595 default:
2596 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args);
2597 }
2598 break;
e23eba97 2599
e925c834
JW		 2600 case 'z':
2601 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2602 || imm_expr->X_op != O_constant
2603 || imm_expr->X_add_number != 0)
2604 break;
2605 s = expr_end;
2606 imm_expr->X_op = O_absent;
2607 continue;
2608
e23eba97
NC		 2609 default:
2610 as_fatal (_("internal error: bad argument type %c"), *args);
2611 }
2612 break;
2613 }
2614 s = argsStart;
2615 error = _("illegal operands");
54b2aec1 2616 insn_with_csr = FALSE;
e23eba97
NC		 2617 }
2618
dc1e8a47 2619 out:
e23eba97
NC		 2620 /* Restore the character we might have clobbered above. */
2621 if (save_c)
2622 *(argsStart - 1) = save_c;
2623
2624 return error;
2625}
2626
2627void
2628md_assemble (char *str)
2629{
2630 struct riscv_cl_insn insn;
2631 expressionS imm_expr;
2632 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2633
8f595e9b
NC		 2634 /* The arch and priv attributes should be set before assembling. */
2635 if (!start_assemble)
2636 {
2637 start_assemble = TRUE;
6e1605e4 2638 riscv_set_abi_by_arch ();
e23eba97 2639
8f595e9b
NC		 2640 /* Set the default_priv_spec according to the priv attributes. */
2641 if (!riscv_set_default_priv_spec (NULL))
2642 return;
2643 }
2644
2645 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
2dc8dd17 2646
e23eba97
NC		 2647 if (error)
2648 {
2649 as_bad ("%s `%s'", error, str);
2650 return;
2651 }
2652
2653 if (insn.insn_mo->pinfo == INSN_MACRO)
2654 macro (&insn, &imm_expr, &imm_reloc);
2655 else
2656 append_insn (&insn, &imm_expr, imm_reloc);
2657}
2658
2659const char *
2660md_atof (int type, char *litP, int *sizeP)
2661{
2662 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2663}
2664
2665void
2666md_number_to_chars (char *buf, valueT val, int n)
2667{
fbc09e7a
MC		 2668 if (target_big_endian)
2669 number_to_chars_bigendian (buf, val, n);
2670 else
2671 number_to_chars_littleendian (buf, val, n);
e23eba97
NC		 2672}
2673
2674const char *md_shortopts = "O::g::G:";
2675
2676enum options
2677{
2922d21d 2678 OPTION_MARCH = OPTION_MD_BASE,
e23eba97
NC		 2679 OPTION_PIC,
2680 OPTION_NO_PIC,
2922d21d 2681 OPTION_MABI,
71060565
JW		 2682 OPTION_RELAX,
2683 OPTION_NO_RELAX,
2dc8dd17
JW		 2684 OPTION_ARCH_ATTR,
2685 OPTION_NO_ARCH_ATTR,
2ca89224
NC		 2686 OPTION_CSR_CHECK,
2687 OPTION_NO_CSR_CHECK,
8f595e9b
NC		 2688 OPTION_MISA_SPEC,
2689 OPTION_MPRIV_SPEC,
fbc09e7a
MC		 2690 OPTION_BIG_ENDIAN,
2691 OPTION_LITTLE_ENDIAN,
e23eba97
NC		 2692 OPTION_END_OF_ENUM
2693};
2694
2695struct option md_longopts[] =
2696{
e23eba97
NC		 2697 {"march", required_argument, NULL, OPTION_MARCH},
2698 {"fPIC", no_argument, NULL, OPTION_PIC},
2699 {"fpic", no_argument, NULL, OPTION_PIC},
2700 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2922d21d 2701 {"mabi", required_argument, NULL, OPTION_MABI},
71060565
JW		 2702 {"mrelax", no_argument, NULL, OPTION_RELAX},
2703 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2dc8dd17
JW		 2704 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
2705 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
2ca89224
NC		 2706 {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
2707 {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
8f595e9b
NC		 2708 {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
2709 {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
fbc09e7a
MC		 2710 {"mbig-endian", no_argument, NULL, OPTION_BIG_ENDIAN},
2711 {"mlittle-endian", no_argument, NULL, OPTION_LITTLE_ENDIAN},
e23eba97
NC		 2712
2713 {NULL, no_argument, NULL, 0}
2714};
2715size_t md_longopts_size = sizeof (md_longopts);
2716
e23eba97
NC		 2717int
2718md_parse_option (int c, const char *arg)
2719{
2720 switch (c)
2721 {
e23eba97 2722 case OPTION_MARCH:
8f595e9b
NC		 2723 /* riscv_after_parse_args will call riscv_set_arch to parse
2724 the architecture. */
2725 default_arch_with_ext = arg;
e23eba97
NC		 2726 break;
2727
2728 case OPTION_NO_PIC:
2729 riscv_opts.pic = FALSE;
2730 break;
2731
2732 case OPTION_PIC:
2733 riscv_opts.pic = TRUE;
2734 break;
2735
2922d21d
AW		 2736 case OPTION_MABI:
2737 if (strcmp (arg, "ilp32") == 0)
7f999549
JW		 2738 riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
2739 else if (strcmp (arg, "ilp32e") == 0)
2740 riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
2922d21d 2741 else if (strcmp (arg, "ilp32f") == 0)
7f999549 2742 riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2743 else if (strcmp (arg, "ilp32d") == 0)
7f999549 2744 riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2745 else if (strcmp (arg, "ilp32q") == 0)
7f999549 2746 riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
2922d21d 2747 else if (strcmp (arg, "lp64") == 0)
7f999549 2748 riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
2922d21d 2749 else if (strcmp (arg, "lp64f") == 0)
7f999549 2750 riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2751 else if (strcmp (arg, "lp64d") == 0)
7f999549 2752 riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2753 else if (strcmp (arg, "lp64q") == 0)
7f999549 2754 riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
2922d21d
AW		 2755 else
2756 return 0;
6e1605e4 2757 explicit_mabi = TRUE;
2922d21d
AW		 2758 break;
2759
71060565
JW		 2760 case OPTION_RELAX:
2761 riscv_opts.relax = TRUE;
2762 break;
2763
2764 case OPTION_NO_RELAX:
2765 riscv_opts.relax = FALSE;
2766 break;
2767
2dc8dd17
JW		 2768 case OPTION_ARCH_ATTR:
2769 riscv_opts.arch_attr = TRUE;
2770 break;
2771
2772 case OPTION_NO_ARCH_ATTR:
2773 riscv_opts.arch_attr = FALSE;
2774 break;
2775
2ca89224
NC		 2776 case OPTION_CSR_CHECK:
2777 riscv_opts.csr_check = TRUE;
2778 break;
2779
2780 case OPTION_NO_CSR_CHECK:
2781 riscv_opts.csr_check = FALSE;
2782 break;
2783
8f595e9b
NC		 2784 case OPTION_MISA_SPEC:
2785 return riscv_set_default_isa_spec (arg);
2786
2787 case OPTION_MPRIV_SPEC:
2788 return riscv_set_default_priv_spec (arg);
2789
fbc09e7a
MC		 2790 case OPTION_BIG_ENDIAN:
2791 target_big_endian = 1;
2792 break;
2793
2794 case OPTION_LITTLE_ENDIAN:
2795 target_big_endian = 0;
2796 break;
2797
e23eba97
NC		 2798 default:
2799 return 0;
2800 }
2801
2802 return 1;
2803}
2804
2805void
2806riscv_after_parse_args (void)
2807{
8f595e9b
NC		 2808 /* The --with-arch is optional for now, so we have to set the xlen
2809 according to the default_arch, which is set by the --targte, first.
2810 Then, we use the xlen to set the default_arch_with_ext if the
2811 -march and --with-arch are not set. */
e23eba97
NC		 2812 if (xlen == 0)
2813 {
2814 if (strcmp (default_arch, "riscv32") == 0)
2815 xlen = 32;
2816 else if (strcmp (default_arch, "riscv64") == 0)
2817 xlen = 64;
2818 else
2819 as_bad ("unknown default architecture `%s'", default_arch);
2820 }
8f595e9b
NC		 2821 if (default_arch_with_ext == NULL)
2822 default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
2823
2824 /* Initialize the hash table for extensions with default version. */
2825 ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
2826
2827 /* If the -misa-spec isn't set, then we set the default ISA spec according
2828 to DEFAULT_RISCV_ISA_SPEC. */
2829 if (default_isa_spec == ISA_SPEC_CLASS_NONE)
2830 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
2922d21d 2831
8f595e9b
NC		 2832 /* Set the architecture according to -march or or --with-arch. */
2833 riscv_set_arch (default_arch_with_ext);
2922d21d
AW		 2834
2835 /* Add the RVC extension, regardless of -march, to support .option rvc. */
fecb9c46 2836 riscv_set_rvc (FALSE);
1080bf78 2837 if (riscv_subset_supports ("c"))
2922d21d 2838 riscv_set_rvc (TRUE);
2922d21d 2839
7f999549
JW		 2840 /* Enable RVE if specified by the -march option. */
2841 riscv_set_rve (FALSE);
1080bf78 2842 if (riscv_subset_supports ("e"))
7f999549
JW		 2843 riscv_set_rve (TRUE);
2844
8f595e9b
NC		 2845 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2846 according to DEFAULT_PRIV_SPEC. */
2847 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
2848 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
2849
0ac2b354
AB		 2850 /* If the CIE to be produced has not been overridden on the command line,
2851 then produce version 3 by default. This allows us to use the full
2852 range of registers in a .cfi_return_column directive. */
2853 if (flag_dwarf_cie_version == -1)
2854 flag_dwarf_cie_version = 3;
e23eba97
NC		 2855}
2856
2857long
2858md_pcrel_from (fixS *fixP)
2859{
2860 return fixP->fx_where + fixP->fx_frag->fr_address;
2861}
2862
2863/* Apply a fixup to the object file. */
2864
2865void
2866md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2867{
45f76423 2868 unsigned int subtype;
e23eba97 2869 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
45f76423 2870 bfd_boolean relaxable = FALSE;
c1b465c9 2871 offsetT loc;
a6cbf936 2872 segT sub_segment;
e23eba97
NC		 2873
2874 /* Remember value for tc_gen_reloc. */
2875 fixP->fx_addnumber = *valP;
2876
2877 switch (fixP->fx_r_type)
2878 {
e23eba97
NC		 2879 case BFD_RELOC_RISCV_HI20:
2880 case BFD_RELOC_RISCV_LO12_I:
2881 case BFD_RELOC_RISCV_LO12_S:
45f76423
AW		 2882 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2883 | bfd_getl32 (buf), buf);
a5ec5e3f
AW		 2884 if (fixP->fx_addsy == NULL)
2885 fixP->fx_done = TRUE;
45f76423
AW		 2886 relaxable = TRUE;
2887 break;
2888
2889 case BFD_RELOC_RISCV_GOT_HI20:
e23eba97
NC		 2890 case BFD_RELOC_RISCV_ADD8:
2891 case BFD_RELOC_RISCV_ADD16:
2892 case BFD_RELOC_RISCV_ADD32:
2893 case BFD_RELOC_RISCV_ADD64:
45f76423 2894 case BFD_RELOC_RISCV_SUB6:
e23eba97
NC		 2895 case BFD_RELOC_RISCV_SUB8:
2896 case BFD_RELOC_RISCV_SUB16:
2897 case BFD_RELOC_RISCV_SUB32:
2898 case BFD_RELOC_RISCV_SUB64:
45f76423
AW		 2899 case BFD_RELOC_RISCV_RELAX:
2900 break;
2901
2902 case BFD_RELOC_RISCV_TPREL_HI20:
2903 case BFD_RELOC_RISCV_TPREL_LO12_I:
2904 case BFD_RELOC_RISCV_TPREL_LO12_S:
2905 case BFD_RELOC_RISCV_TPREL_ADD:
2906 relaxable = TRUE;
2907 /* Fall through. */
2908
2909 case BFD_RELOC_RISCV_TLS_GOT_HI20:
2910 case BFD_RELOC_RISCV_TLS_GD_HI20:
2911 case BFD_RELOC_RISCV_TLS_DTPREL32:
2912 case BFD_RELOC_RISCV_TLS_DTPREL64:
e294484e
AW		 2913 if (fixP->fx_addsy != NULL)
2914 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2915 else
2916 as_bad_where (fixP->fx_file, fixP->fx_line,
2917 _("TLS relocation against a constant"));
e23eba97
NC		 2918 break;
2919
e23eba97 2920 case BFD_RELOC_32:
a6cbf936
KLC		 2921 /* Use pc-relative relocation for FDE initial location.
2922 The symbol address in .eh_frame may be adjusted in
2923 _bfd_elf_discard_section_eh_frame, and the content of
2924 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2925 Therefore, we cannot insert a relocation whose addend symbol is
2926 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2927 if (fixP->fx_addsy && fixP->fx_subsy
2928 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
2929 && strcmp (sub_segment->name, ".eh_frame") == 0
2930 && S_GET_VALUE (fixP->fx_subsy)
2931 == fixP->fx_frag->fr_address + fixP->fx_where)
2932 {
2933 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
2934 fixP->fx_subsy = NULL;
2935 break;
2936 }
2937 /* Fall through. */
2938 case BFD_RELOC_64:
e23eba97
NC		 2939 case BFD_RELOC_16:
2940 case BFD_RELOC_8:
45f76423 2941 case BFD_RELOC_RISCV_CFA:
e23eba97
NC		 2942 if (fixP->fx_addsy && fixP->fx_subsy)
2943 {
2944 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2945 fixP->fx_next->fx_addsy = fixP->fx_subsy;
2946 fixP->fx_next->fx_subsy = NULL;
2947 fixP->fx_next->fx_offset = 0;
2948 fixP->fx_subsy = NULL;
2949
2950 switch (fixP->fx_r_type)
2951 {
2952 case BFD_RELOC_64:
2953 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
2954 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
2955 break;
2956
2957 case BFD_RELOC_32:
2958 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
2959 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2960 break;
2961
2962 case BFD_RELOC_16:
2963 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
2964 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2965 break;
2966
2967 case BFD_RELOC_8:
2968 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
2969 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
073808ed 2970 break;
e23eba97 2971
45f76423
AW		 2972 case BFD_RELOC_RISCV_CFA:
2973 /* Load the byte to get the subtype. */
c1b465c9
KLC		 2974 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
2975 loc = fixP->fx_frag->fr_fix - (subtype & 7);
45f76423
AW		 2976 switch (subtype)
2977 {
2978 case DW_CFA_advance_loc1:
c1b465c9
KLC		 2979 fixP->fx_where = loc + 1;
2980 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2981 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
2982 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
2983 break;
2984
2985 case DW_CFA_advance_loc2:
2986 fixP->fx_size = 2;
45f76423 2987 fixP->fx_next->fx_size = 2;
c1b465c9
KLC		 2988 fixP->fx_where = loc + 1;
2989 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2990 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
2991 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2992 break;
2993
2994 case DW_CFA_advance_loc4:
2995 fixP->fx_size = 4;
45f76423 2996 fixP->fx_next->fx_size = 4;
c1b465c9
KLC		 2997 fixP->fx_where = loc;
2998 fixP->fx_next->fx_where = loc;
45f76423
AW		 2999 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
3000 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
3001 break;
3002
3003 default:
3004 if (subtype < 0x80 && (subtype & 0x40))
3005 {
3006 /* DW_CFA_advance_loc */
2aece2ba
KLC		 3007 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
3008 fixP->fx_next->fx_frag = fixP->fx_frag;
45f76423
AW		 3009 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
3010 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
3011 }
3012 else
3013 as_fatal (_("internal error: bad CFA value #%d"), subtype);
3014 break;
3015 }
3016 break;
3017
e23eba97
NC		 3018 default:
3019 /* This case is unreachable. */
3020 abort ();
3021 }
3022 }
3023 /* Fall through. */
3024
3025 case BFD_RELOC_RVA:
3026 /* If we are deleting this reloc entry, we must fill in the
3027 value now. This can happen if we have a .word which is not
3028 resolved when it appears but is later defined. */
3029 if (fixP->fx_addsy == NULL)
3030 {
3031 gas_assert (fixP->fx_size <= sizeof (valueT));
3032 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
3033 fixP->fx_done = 1;
3034 }
3035 break;
3036
3037 case BFD_RELOC_RISCV_JMP:
3038 if (fixP->fx_addsy)
3039 {
3040 /* Fill in a tentative value to improve objdump readability. */
3041 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3042 bfd_vma delta = target - md_pcrel_from (fixP);
3043 bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
3044 }
3045 break;
3046
3047 case BFD_RELOC_12_PCREL:
3048 if (fixP->fx_addsy)
3049 {
3050 /* Fill in a tentative value to improve objdump readability. */
3051 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3052 bfd_vma delta = target - md_pcrel_from (fixP);
3053 bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
3054 }
3055 break;
3056
3057 case BFD_RELOC_RISCV_RVC_BRANCH:
3058 if (fixP->fx_addsy)
3059 {
3060 /* Fill in a tentative value to improve objdump readability. */
3061 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3062 bfd_vma delta = target - md_pcrel_from (fixP);
3063 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
3064 }
3065 break;
3066
3067 case BFD_RELOC_RISCV_RVC_JUMP:
3068 if (fixP->fx_addsy)
3069 {
3070 /* Fill in a tentative value to improve objdump readability. */
3071 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3072 bfd_vma delta = target - md_pcrel_from (fixP);
3073 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
3074 }
3075 break;
3076
e23eba97
NC		 3077 case BFD_RELOC_RISCV_CALL:
3078 case BFD_RELOC_RISCV_CALL_PLT:
45f76423
AW		 3079 relaxable = TRUE;
3080 break;
3081
9d06997a 3082 case BFD_RELOC_RISCV_PCREL_HI20:
45f76423
AW		 3083 case BFD_RELOC_RISCV_PCREL_LO12_S:
3084 case BFD_RELOC_RISCV_PCREL_LO12_I:
9d06997a
PD		 3085 relaxable = riscv_opts.relax;
3086 break;
3087
e23eba97
NC		 3088 case BFD_RELOC_RISCV_ALIGN:
3089 break;
3090
3091 default:
3092 /* We ignore generic BFD relocations we don't know about. */
3093 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
3094 as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type);
3095 }
45f76423 3096
e294484e
AW		 3097 if (fixP->fx_subsy != NULL)
3098 as_bad_where (fixP->fx_file, fixP->fx_line,
3099 _("unsupported symbol subtraction"));
3100
45f76423
AW		 3101 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3102 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
3103 {
3104 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3105 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
3106 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
b1b11e92 3107 fixP->fx_next->fx_size = 0;
45f76423
AW		 3108 }
3109}
3110
3111/* Because the value of .cfi_remember_state may changed after relaxation,
3112 we insert a fix to relocate it again in link-time. */
3113
3114void
3115riscv_pre_output_hook (void)
3116{
3117 const frchainS *frch;
72393fd1
JW		 3118 segT s;
3119
3120 /* Save the current segment info. */
3121 segT seg = now_seg;
3122 subsegT subseg = now_subseg;
45f76423
AW		 3123
3124 for (s = stdoutput->sections; s; s = s->next)
3125 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
3126 {
7cb7b948 3127 fragS *frag;
45f76423
AW		 3128
3129 for (frag = frch->frch_root; frag; frag = frag->fr_next)
3130 {
3131 if (frag->fr_type == rs_cfa)
3132 {
45f76423 3133 expressionS exp;
8d1015a8 3134 expressionS *symval;
45f76423 3135
8d1015a8 3136 symval = symbol_get_value_expression (frag->fr_symbol);
45f76423 3137 exp.X_op = O_subtract;
8d1015a8 3138 exp.X_add_symbol = symval->X_add_symbol;
45f76423 3139 exp.X_add_number = 0;
8d1015a8 3140 exp.X_op_symbol = symval->X_op_symbol;
45f76423 3141
72393fd1
JW		 3142 /* We must set the segment before creating a frag after all
3143 frag chains have been chained together. */
3144 subseg_set (s, frch->frch_subseg);
3145
c1b465c9 3146 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
45f76423
AW		 3147 BFD_RELOC_RISCV_CFA);
3148 }
3149 }
3150 }
72393fd1
JW		 3151
3152 /* Restore the original segment info. */
3153 subseg_set (seg, subseg);
e23eba97
NC		 3154}
3155
45f76423 3156
e23eba97
NC		 3157/* This structure is used to hold a stack of .option values. */
3158
3159struct riscv_option_stack
3160{
3161 struct riscv_option_stack *next;
3162 struct riscv_set_options options;
3163};
3164
3165static struct riscv_option_stack *riscv_opts_stack;
3166
3167/* Handle the .option pseudo-op. */
3168
3169static void
3170s_riscv_option (int x ATTRIBUTE_UNUSED)
3171{
3172 char *name = input_line_pointer, ch;
3173
3174 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3175 ++input_line_pointer;
3176 ch = *input_line_pointer;
3177 *input_line_pointer = '\0';
3178
3179 if (strcmp (name, "rvc") == 0)
3180 riscv_set_rvc (TRUE);
3181 else if (strcmp (name, "norvc") == 0)
3182 riscv_set_rvc (FALSE);
3183 else if (strcmp (name, "pic") == 0)
3184 riscv_opts.pic = TRUE;
3185 else if (strcmp (name, "nopic") == 0)
3186 riscv_opts.pic = FALSE;
45f76423
AW		 3187 else if (strcmp (name, "relax") == 0)
3188 riscv_opts.relax = TRUE;
3189 else if (strcmp (name, "norelax") == 0)
3190 riscv_opts.relax = FALSE;
2ca89224
NC		 3191 else if (strcmp (name, "csr-check") == 0)
3192 riscv_opts.csr_check = TRUE;
3193 else if (strcmp (name, "no-csr-check") == 0)
3194 riscv_opts.csr_check = FALSE;
e23eba97
NC		 3195 else if (strcmp (name, "push") == 0)
3196 {
3197 struct riscv_option_stack *s;
3198
3199 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
3200 s->next = riscv_opts_stack;
3201 s->options = riscv_opts;
3202 riscv_opts_stack = s;
3203 }
3204 else if (strcmp (name, "pop") == 0)
3205 {
3206 struct riscv_option_stack *s;
3207
3208 s = riscv_opts_stack;
3209 if (s == NULL)
3210 as_bad (_(".option pop with no .option push"));
3211 else
3212 {
3213 riscv_opts = s->options;
3214 riscv_opts_stack = s->next;
3215 free (s);
3216 }
3217 }
3218 else
3219 {
3220 as_warn (_("Unrecognized .option directive: %s\n"), name);
3221 }
3222 *input_line_pointer = ch;
3223 demand_empty_rest_of_line ();
3224}
3225
3226/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3227 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3228 use in DWARF debug information. */
3229
3230static void
3231s_dtprel (int bytes)
3232{
3233 expressionS ex;
3234 char *p;
3235
3236 expression (&ex);
3237
3238 if (ex.X_op != O_symbol)
3239 {
3240 as_bad (_("Unsupported use of %s"), (bytes == 8
3241 ? ".dtpreldword"
3242 : ".dtprelword"));
3243 ignore_rest_of_line ();
3244 }
3245
3246 p = frag_more (bytes);
3247 md_number_to_chars (p, 0, bytes);
3248 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
3249 (bytes == 8
3250 ? BFD_RELOC_RISCV_TLS_DTPREL64
3251 : BFD_RELOC_RISCV_TLS_DTPREL32));
3252
3253 demand_empty_rest_of_line ();
3254}
3255
3256/* Handle the .bss pseudo-op. */
3257
3258static void
3259s_bss (int ignore ATTRIBUTE_UNUSED)
3260{
3261 subseg_set (bss_section, 0);
3262 demand_empty_rest_of_line ();
3263}
3264
e23eba97 3265static void
d115ab8e 3266riscv_make_nops (char *buf, bfd_vma bytes)
e23eba97 3267{
d115ab8e 3268 bfd_vma i = 0;
e23eba97 3269
e5b737de
AW		 3270 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3271 means we are not within a valid instruction sequence. It is thus safe
3272 to use a zero byte, even though that is not a valid instruction. */
3273 if (bytes % 2 == 1)
3274 buf[i++] = 0;
3275
3276 /* Use at most one 2-byte NOP. */
3277 if ((bytes - i) % 4 == 2)
e23eba97 3278 {
fbc09e7a 3279 number_to_chars_littleendian (buf + i, RVC_NOP, 2);
d115ab8e 3280 i += 2;
e23eba97
NC		 3281 }
3282
e5b737de 3283 /* Fill the remainder with 4-byte NOPs. */
d115ab8e 3284 for ( ; i < bytes; i += 4)
fbc09e7a 3285 number_to_chars_littleendian (buf + i, RISCV_NOP, 4);
d115ab8e 3286}
e23eba97 3287
d115ab8e
AW		 3288/* Called from md_do_align. Used to create an alignment frag in a
3289 code section by emitting a worst-case NOP sequence that the linker
3290 will later relax to the correct number of NOPs. We can't compute
3291 the correct alignment now because of other linker relaxations. */
3292
3293bfd_boolean
3294riscv_frag_align_code (int n)
3295{
e5b737de 3296 bfd_vma bytes = (bfd_vma) 1 << n;
36877bfb
JW		 3297 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
3298 bfd_vma worst_case_bytes = bytes - insn_alignment;
3299 char *nops;
ed0816bd 3300 expressionS ex;
d115ab8e 3301
36877bfb
JW		 3302 /* If we are moving to a smaller alignment than the instruction size, then no
3303 alignment is required. */
3304 if (bytes <= insn_alignment)
3305 return TRUE;
3306
d115ab8e
AW		 3307 /* When not relaxing, riscv_handle_align handles code alignment. */
3308 if (!riscv_opts.relax)
3309 return FALSE;
e23eba97 3310
e80ae190
JW		 3311 nops = frag_more (worst_case_bytes);
3312
ed0816bd
PD		 3313 ex.X_op = O_constant;
3314 ex.X_add_number = worst_case_bytes;
d115ab8e 3315
ed0816bd 3316 riscv_make_nops (nops, worst_case_bytes);
e23eba97 3317
ed0816bd
PD		 3318 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
3319 &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
e23eba97 3320
d115ab8e
AW		 3321 return TRUE;
3322}
e23eba97 3323
d115ab8e
AW		 3324/* Implement HANDLE_ALIGN. */
3325
3326void
3327riscv_handle_align (fragS *fragP)
3328{
3329 switch (fragP->fr_type)
3330 {
3331 case rs_align_code:
3332 /* When relaxing, riscv_frag_align_code handles code alignment. */
3333 if (!riscv_opts.relax)
3334 {
e80ae190
JW		 3335 bfd_signed_vma bytes = (fragP->fr_next->fr_address
3336 - fragP->fr_address - fragP->fr_fix);
3337 /* We have 4 byte uncompressed nops. */
3338 bfd_signed_vma size = 4;
3339 bfd_signed_vma excess = bytes % size;
3340 char *p = fragP->fr_literal + fragP->fr_fix;
3341
3342 if (bytes <= 0)
d115ab8e
AW		 3343 break;
3344
e80ae190
JW		 3345 /* Insert zeros or compressed nops to get 4 byte alignment. */
3346 if (excess)
3347 {
3348 riscv_make_nops (p, excess);
3349 fragP->fr_fix += excess;
3350 p += excess;
3351 }
3352
3353 /* Insert variable number of 4 byte uncompressed nops. */
3354 riscv_make_nops (p, size);
3355 fragP->fr_var = size;
d115ab8e
AW		 3356 }
3357 break;
3358
3359 default:
3360 break;
3361 }
e23eba97
NC		 3362}
3363
3364int
3365md_estimate_size_before_relax (fragS *fragp, asection *segtype)
3366{
3367 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
3368}
3369
3370/* Translate internal representation of relocation info to BFD target
3371 format. */
3372
3373arelent *
3374tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3375{
3376 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
3377
3378 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3379 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3380 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3381 reloc->addend = fixp->fx_addnumber;
3382
3383 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3384 if (reloc->howto == NULL)
3385 {
3386 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
3387 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
3388 {
3389 /* We don't have R_RISCV_8/16, but for this special case,
3390 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3391 return reloc;
3392 }
3393
3394 as_bad_where (fixp->fx_file, fixp->fx_line,
3395 _("cannot represent %s relocation in object file"),
3396 bfd_get_reloc_code_name (fixp->fx_r_type));
3397 return NULL;
3398 }
3399
3400 return reloc;
3401}
3402
3403int
3404riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
3405{
3406 if (RELAX_BRANCH_P (fragp->fr_subtype))
3407 {
3408 offsetT old_var = fragp->fr_var;
3409 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
3410 return fragp->fr_var - old_var;
3411 }
3412
3413 return 0;
3414}
3415
3416/* Expand far branches to multi-instruction sequences. */
3417
3418static void
3419md_convert_frag_branch (fragS *fragp)
3420{
3421 bfd_byte *buf;
3422 expressionS exp;
3423 fixS *fixp;
3424 insn_t insn;
3425 int rs1, reloc;
3426
3427 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
3428
3429 exp.X_op = O_symbol;
3430 exp.X_add_symbol = fragp->fr_symbol;
3431 exp.X_add_number = fragp->fr_offset;
3432
3433 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
3434
3435 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
3436 {
3437 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3438 {
3439 case 8:
3440 case 4:
3441 /* Expand the RVC branch into a RISC-V one. */
3442 insn = bfd_getl16 (buf);
3443 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
3444 if ((insn & MASK_C_J) == MATCH_C_J)
3445 insn = MATCH_JAL;
3446 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
3447 insn = MATCH_JAL | (X_RA << OP_SH_RD);
3448 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
3449 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
3450 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
3451 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
3452 else
3453 abort ();
3454 bfd_putl32 (insn, buf);
3455 break;
3456
3457 case 6:
3458 /* Invert the branch condition. Branch over the jump. */
3459 insn = bfd_getl16 (buf);
3460 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
3461 insn |= ENCODE_RVC_B_IMM (6);
3462 bfd_putl16 (insn, buf);
3463 buf += 2;
3464 goto jump;
3465
3466 case 2:
3467 /* Just keep the RVC branch. */
3468 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3469 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
3470 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3471 2, &exp, FALSE, reloc);
3472 buf += 2;
3473 goto done;
3474
3475 default:
1d65abb5 3476 abort ();
e23eba97
NC		 3477 }
3478 }
3479
3480 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3481 {
3482 case 8:
3483 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
3484
3485 /* Invert the branch condition. Branch over the jump. */
3486 insn = bfd_getl32 (buf);
3487 insn ^= MATCH_BEQ ^ MATCH_BNE;
3488 insn |= ENCODE_SBTYPE_IMM (8);
fbc09e7a 3489 bfd_putl32 (insn, buf);
e23eba97
NC		 3490 buf += 4;
3491
dc1e8a47 3492 jump:
e23eba97
NC		 3493 /* Jump to the target. */
3494 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3495 4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
fbc09e7a 3496 bfd_putl32 (MATCH_JAL, buf);
e23eba97
NC		 3497 buf += 4;
3498 break;
3499
3500 case 4:
3501 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3502 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
3503 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3504 4, &exp, FALSE, reloc);
3505 buf += 4;
3506 break;
3507
3508 default:
3509 abort ();
3510 }
3511
dc1e8a47 3512 done:
e23eba97
NC		 3513 fixp->fx_file = fragp->fr_file;
3514 fixp->fx_line = fragp->fr_line;
3515
3516 gas_assert (buf == (bfd_byte *)fragp->fr_literal
3517 + fragp->fr_fix + fragp->fr_var);
3518
3519 fragp->fr_fix += fragp->fr_var;
3520}
3521
3522/* Relax a machine dependent frag. This returns the amount by which
3523 the current size of the frag should change. */
3524
3525void
3526md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3527 fragS *fragp)
3528{
3529 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
3530 md_convert_frag_branch (fragp);
3531}
3532
3533void
3534md_show_usage (FILE *stream)
3535{
3536 fprintf (stream, _("\
3537RISC-V options:\n\
8f595e9b
NC		 3538 -fpic generate position-independent code\n\
3539 -fno-pic don't generate position-independent code (default)\n\
3540 -march=ISA set the RISC-V architecture\n\
3541 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3542 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3543 -mabi=ABI set the RISC-V ABI\n\
3544 -mrelax enable relax (default)\n\
3545 -mno-relax disable relax\n\
3546 -march-attr generate RISC-V arch attribute\n\
3547 -mno-arch-attr don't generate RISC-V arch attribute\n\
e23eba97
NC		 3548"));
3549}
3550
3551/* Standard calling conventions leave the CFA at SP on entry. */
3552void
3553riscv_cfi_frame_initial_instructions (void)
3554{
3555 cfi_add_CFA_def_cfa_register (X_SP);
3556}
3557
3558int
3559tc_riscv_regname_to_dw2regnum (char *regname)
3560{
3561 int reg;
3562
3563 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3564 return reg;
3565
3566 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3567 return reg + 32;
3568
4762fe62
AB		 3569 /* CSRs are numbered 4096 -> 8191. */
3570 if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
3571 return reg + 4096;
3572
e23eba97
NC		 3573 as_bad (_("unknown register `%s'"), regname);
3574 return -1;
3575}
3576
3577void
3578riscv_elf_final_processing (void)
3579{
6e1605e4 3580 riscv_set_abi_by_arch ();
e23eba97 3581 elf_elfheader (stdoutput)->e_flags |= elf_flags;
e23eba97
NC		 3582}
3583
3584/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3585 since these directives break relaxation when used with symbol deltas. */
3586
3587static void
3588s_riscv_leb128 (int sign)
3589{
3590 expressionS exp;
3591 char *save_in = input_line_pointer;
3592
3593 expression (&exp);
3594 if (exp.X_op != O_constant)
3595 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3596 demand_empty_rest_of_line ();
3597
3598 input_line_pointer = save_in;
3599 return s_leb128 (sign);
3600}
3601
0e35537d
JW		 3602/* Parse the .insn directive. */
3603
3604static void
3605s_riscv_insn (int x ATTRIBUTE_UNUSED)
3606{
3607 char *str = input_line_pointer;
3608 struct riscv_cl_insn insn;
3609 expressionS imm_expr;
3610 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3611 char save_c;
3612
3613 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3614 ++input_line_pointer;
3615
3616 save_c = *input_line_pointer;
3617 *input_line_pointer = '\0';
3618
3619 const char *error = riscv_ip (str, &insn, &imm_expr,
3620 &imm_reloc, insn_type_hash);
3621
3622 if (error)
3623 {
3624 as_bad ("%s `%s'", error, str);
3625 }
3626 else
3627 {
3628 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3629 append_insn (&insn, &imm_expr, imm_reloc);
3630 }
3631
3632 *input_line_pointer = save_c;
3633 demand_empty_rest_of_line ();
3634}
3635
8f595e9b
NC		 3636/* Update arch and priv attributes. If we don't set the corresponding ELF
3637 attributes, then try to output the default ones. */
2dc8dd17
JW		 3638
3639static void
8f595e9b 3640riscv_write_out_attrs (void)
2dc8dd17 3641{
8f595e9b
NC		 3642 const char *arch_str, *priv_str, *p;
3643 /* versions[0] is major, versions[1] is minor,
3644 and versions[3] is revision. */
3645 unsigned versions[3] = {0}, number = 0;
3646 unsigned int i;
2dc8dd17 3647
8f595e9b
NC		 3648 /* Re-write arch attribute to normalize the arch string. */
3649 arch_str = riscv_arch_str (xlen, &riscv_subsets);
2dc8dd17 3650 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
2dc8dd17 3651 xfree ((void *)arch_str);
8f595e9b
NC		 3652
3653 /* For the file without any instruction, we don't set the default_priv_spec
3654 according to the priv attributes since the md_assemble isn't called.
3655 Call riscv_set_default_priv_spec here for the above case, although
3656 it seems strange. */
3657 if (!start_assemble
3658 && !riscv_set_default_priv_spec (NULL))
3659 return;
3660
1a79004f
NC		 3661 /* If we already have set elf priv attributes, then no need to do anything,
3662 assembler will generate them according to what you set. Otherwise, don't
3663 generate or update them when no CSR and priv instructions are used.
3664 Generate the priv attributes according to default_priv_spec, which can be
3665 set by -mpriv-spec and --with-priv-spec, and be updated by the original
3666 priv attribute sets. */
3667 if (!explicit_priv_attr)
3fc6c3dc
NC		 3668 return;
3669
8f595e9b
NC		 3670 /* Re-write priv attributes by default_priv_spec. */
3671 priv_str = riscv_get_priv_spec_name (default_priv_spec);
3672 p = priv_str;
3673 for (i = 0; *p; ++p)
3674 {
3675 if (*p == '.' && i < 3)
3676 {
3677 versions[i++] = number;
3678 number = 0;
3679 }
3680 else if (ISDIGIT (*p))
3681 number = (number * 10) + (*p - '0');
3682 else
3683 {
3684 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str);
3685 return;
3686 }
3687 }
3688 versions[i] = number;
3689
3690 /* Set the priv attributes. */
3691 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
3692 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
3693 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
2dc8dd17
JW		 3694}
3695
8f595e9b
NC		 3696/* Add the default contents for the .riscv.attributes section. If any
3697 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3698 to update the arch and priv attributes. */
2dc8dd17
JW		 3699
3700static void
3701riscv_set_public_attributes (void)
3702{
8f595e9b
NC		 3703 if (riscv_opts.arch_attr || explicit_attr)
3704 riscv_write_out_attrs ();
2dc8dd17
JW		 3705}
3706
3707/* Called after all assembly has been done. */
3708
3709void
3710riscv_md_end (void)
3711{
3712 riscv_set_public_attributes ();
3713}
3714
3715/* Given a symbolic attribute NAME, return the proper integer value.
3716 Returns -1 if the attribute is not known. */
3717
3718int
3719riscv_convert_symbolic_attribute (const char *name)
3720{
3721 static const struct
3722 {
3723 const char * name;
3724 const int tag;
3725 }
3726 attribute_table[] =
3727 {
3728 /* When you modify this table you should
3729 also modify the list in doc/c-riscv.texi. */
3730#define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3731 T(arch),
3732 T(priv_spec),
3733 T(priv_spec_minor),
3734 T(priv_spec_revision),
3735 T(unaligned_access),
3736 T(stack_align),
3737#undef T
3738 };
3739
3740 unsigned int i;
3741
3742 if (name == NULL)
3743 return -1;
3744
3745 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
3746 if (strcmp (name, attribute_table[i].name) == 0)
3747 return attribute_table[i].tag;
3748
3749 return -1;
3750}
3751
3752/* Parse a .attribute directive. */
3753
3754static void
3755s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
3756{
3757 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
8f595e9b
NC		 3758 unsigned old_xlen;
3759 obj_attribute *attr;
2dc8dd17 3760
8f595e9b
NC		 3761 explicit_attr = TRUE;
3762 switch (tag)
2dc8dd17 3763 {
8f595e9b
NC		 3764 case Tag_RISCV_arch:
3765 old_xlen = xlen;
2dc8dd17
JW		 3766 attr = elf_known_obj_attributes_proc (stdoutput);
3767 if (!start_assemble)
3768 riscv_set_arch (attr[Tag_RISCV_arch].s);
3769 else
3770 as_fatal (_(".attribute arch must set before any instructions"));
3771
3772 if (old_xlen != xlen)
3773 {
3774 /* We must re-init bfd again if xlen is changed. */
3775 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
3776 bfd_find_target (riscv_target_format (), stdoutput);
3777
3778 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
3779 as_warn (_("Could not set architecture and machine"));
3780 }
8f595e9b
NC		 3781 break;
3782
3783 case Tag_RISCV_priv_spec:
3784 case Tag_RISCV_priv_spec_minor:
3785 case Tag_RISCV_priv_spec_revision:
3786 if (start_assemble)
3787 as_fatal (_(".attribute priv spec must set before any instructions"));
3788 break;
3789
3790 default:
3791 break;
2dc8dd17
JW		 3792 }
3793}
3794
e23eba97
NC		 3795/* Pseudo-op table. */
3796
3797static const pseudo_typeS riscv_pseudo_table[] =
3798{
3799 /* RISC-V-specific pseudo-ops. */
3800 {"option", s_riscv_option, 0},
3801 {"half", cons, 2},
3802 {"word", cons, 4},
3803 {"dword", cons, 8},
3804 {"dtprelword", s_dtprel, 4},
3805 {"dtpreldword", s_dtprel, 8},
3806 {"bss", s_bss, 0},
e23eba97
NC		 3807 {"uleb128", s_riscv_leb128, 0},
3808 {"sleb128", s_riscv_leb128, 1},
0e35537d 3809 {"insn", s_riscv_insn, 0},
2dc8dd17 3810 {"attribute", s_riscv_attribute, 0},
e23eba97
NC		 3811
3812 { NULL, NULL, 0 },
3813};
3814
3815void
3816riscv_pop_insert (void)
3817{
3818 extern void pop_insert (const pseudo_typeS *);
3819
3820 pop_insert (riscv_pseudo_table);
3821}
GDB Binutils - Deliverables
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