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[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
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e23eba97 1/* tc-riscv.c -- RISC-V assembler
b3adc24a 2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
1080bf78 32#include "bfd/elfxx-riscv.h"
e23eba97
NC		 33#include "elf/riscv.h"
34#include "opcode/riscv.h"
35
36#include <stdint.h>
37
38/* Information about an instruction, including its format, operands
39 and fixups. */
40struct riscv_cl_insn
41{
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode *insn_mo;
44
45 /* The encoded instruction bits. */
46 insn_t insn_opcode;
47
48 /* The frag that contains the instruction. */
49 struct frag *frag;
50
51 /* The offset into FRAG of the first instruction byte. */
52 long where;
53
54 /* The relocs associated with the instruction, if any. */
55 fixS *fixp;
56};
57
58#ifndef DEFAULT_ARCH
59#define DEFAULT_ARCH "riscv64"
60#endif
61
2dc8dd17
JW		 62#ifndef DEFAULT_RISCV_ATTR
63#define DEFAULT_RISCV_ATTR 0
64#endif
65
8f595e9b
NC		 66/* Let riscv_after_parse_args set the default value according to xlen. */
67
68#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
70#endif
71
72/* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
77
78#ifndef DEFAULT_RISCV_ISA_SPEC
79#define DEFAULT_RISCV_ISA_SPEC "2.2"
80#endif
81
82#ifndef DEFAULT_RISCV_PRIV_SPEC
83#define DEFAULT_RISCV_PRIV_SPEC "1.11"
84#endif
85
e23eba97 86static const char default_arch[] = DEFAULT_ARCH;
8f595e9b
NC		 87static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
88static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
89static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
e23eba97 90
2922d21d
AW		 91static unsigned xlen = 0; /* width of an x-register */
92static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
7f999549 93static bfd_boolean rve_abi = FALSE;
e23eba97 94
2922d21d 95#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
e23eba97
NC		 96#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
97
98static unsigned elf_flags = 0;
99
8f595e9b
NC		 100/* Set the default_isa_spec. Return 0 if the input spec string isn't
101 supported. Otherwise, return 1. */
102
103static int
104riscv_set_default_isa_spec (const char *s)
105{
106 enum riscv_isa_spec_class class;
107 if (!riscv_get_isa_spec_class (s, &class))
108 {
109 as_bad ("Unknown default ISA spec `%s' set by "
110 "-misa-spec or --with-isa-spec", s);
111 return 0;
112 }
113 else
114 default_isa_spec = class;
115 return 1;
116}
117
118/* Set the default_priv_spec, assembler will find the suitable CSR address
119 according to default_priv_spec. We will try to check priv attributes if
120 the input string is NULL. Return 0 if the input priv spec string isn't
121 supported. Otherwise, return 1. */
122
123static int
124riscv_set_default_priv_spec (const char *s)
125{
126 enum riscv_priv_spec_class class;
127 unsigned major, minor, revision;
128 obj_attribute *attr;
8f595e9b
NC		 129
130 /* Find the corresponding priv spec class. */
131 if (riscv_get_priv_spec_class (s, &class))
132 {
133 default_priv_spec = class;
134 return 1;
135 }
136
137 if (s != NULL)
138 {
139 as_bad (_("Unknown default privilege spec `%s' set by "
140 "-mpriv-spec or --with-priv-spec"), s);
141 return 0;
142 }
143
144 /* Try to set the default_priv_spec according to the priv attributes. */
145 attr = elf_known_obj_attributes_proc (stdoutput);
146 major = (unsigned) attr[Tag_RISCV_priv_spec].i;
147 minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
148 revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
149
39ff0b81
NC		 150 if (riscv_get_priv_spec_class_from_numbers (major,
151 minor,
152 revision,
153 &class))
8f595e9b 154 {
39ff0b81
NC		 155 /* The priv attributes setting 0.0.0 is meaningless. We should have set
156 the default_priv_spec by md_parse_option and riscv_after_parse_args,
157 so just skip the following setting. */
158 if (class == PRIV_SPEC_CLASS_NONE)
159 return 1;
8f595e9b 160
8f595e9b 161 default_priv_spec = class;
8f595e9b
NC		 162 return 1;
163 }
164
165 /* Still can not find the priv spec class. */
ddc73fa9 166 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
8f595e9b 167 "privilege attributes"), major, minor, revision);
8f595e9b
NC		 168 return 0;
169}
170
e23eba97
NC		 171/* This is the set of options which the .option pseudo-op may modify. */
172
173struct riscv_set_options
174{
175 int pic; /* Generate position-independent code. */
176 int rvc; /* Generate RVC code. */
7f999549 177 int rve; /* Generate RVE code. */
45f76423 178 int relax; /* Emit relocs the linker is allowed to relax. */
2dc8dd17 179 int arch_attr; /* Emit arch attribute. */
2ca89224 180 int csr_check; /* Enable the CSR checking. */
e23eba97
NC		 181};
182
183static struct riscv_set_options riscv_opts =
184{
185 0, /* pic */
186 0, /* rvc */
7f999549 187 0, /* rve */
45f76423 188 1, /* relax */
2dc8dd17 189 DEFAULT_RISCV_ATTR, /* arch_attr */
2ca89224 190 0. /* csr_check */
e23eba97
NC		 191};
192
193static void
194riscv_set_rvc (bfd_boolean rvc_value)
195{
196 if (rvc_value)
197 elf_flags |= EF_RISCV_RVC;
198
199 riscv_opts.rvc = rvc_value;
200}
201
7f999549
JW		 202static void
203riscv_set_rve (bfd_boolean rve_value)
204{
205 riscv_opts.rve = rve_value;
206}
207
1080bf78 208static riscv_subset_list_t riscv_subsets;
e23eba97
NC		 209
210static bfd_boolean
1080bf78 211riscv_subset_supports (const char *feature)
e23eba97 212{
1080bf78
JW		 213 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
214 return TRUE;
e23eba97 215
1080bf78 216 return riscv_lookup_subset (&riscv_subsets, feature) != NULL;
e23eba97
NC		 217}
218
43135d3b 219static bfd_boolean
7e9ad3a3 220riscv_multi_subset_supports (enum riscv_insn_class insn_class)
43135d3b 221{
7e9ad3a3
JW		 222 switch (insn_class)
223 {
224 case INSN_CLASS_I: return riscv_subset_supports ("i");
225 case INSN_CLASS_C: return riscv_subset_supports ("c");
226 case INSN_CLASS_A: return riscv_subset_supports ("a");
227 case INSN_CLASS_M: return riscv_subset_supports ("m");
228 case INSN_CLASS_F: return riscv_subset_supports ("f");
229 case INSN_CLASS_D: return riscv_subset_supports ("d");
230 case INSN_CLASS_D_AND_C:
231 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
232
233 case INSN_CLASS_F_AND_C:
234 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
43135d3b 235
7e9ad3a3 236 case INSN_CLASS_Q: return riscv_subset_supports ("q");
43135d3b 237
7e9ad3a3
JW		 238 default:
239 as_fatal ("Unreachable");
240 return FALSE;
241 }
43135d3b
JW		 242}
243
8f595e9b 244/* Handle of the extension with version hash table. */
629310ab 245static htab_t ext_version_hash = NULL;
8f595e9b 246
629310ab 247static htab_t
8f595e9b
NC		 248init_ext_version_hash (const struct riscv_ext_version *table)
249{
250 int i = 0;
629310ab 251 htab_t hash = str_htab_create ();
8f595e9b
NC		 252
253 while (table[i].name)
254 {
255 const char *name = table[i].name;
fe0e921f
AM		 256 if (str_hash_insert (hash, name, &table[i], 0) != NULL)
257 as_fatal (_("duplicate %s"), name);
8f595e9b
NC		 258
259 i++;
260 while (table[i].name
261 && strcmp (table[i].name, name) == 0)
262 i++;
263 }
264
265 return hash;
266}
267
268static void
269riscv_get_default_ext_version (const char *name,
270 unsigned int *major_version,
271 unsigned int *minor_version)
272{
273 struct riscv_ext_version *ext;
274
275 *major_version = 0;
276 *minor_version = 0;
277
278 if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
279 return;
280
629310ab 281 ext = (struct riscv_ext_version *) str_hash_find (ext_version_hash, name);
8f595e9b
NC		 282 while (ext
283 && ext->name
284 && strcmp (ext->name, name) == 0)
285 {
286 if (ext->isa_spec_class == default_isa_spec)
287 {
288 *major_version = ext->major_version;
289 *minor_version = ext->minor_version;
290 return;
291 }
292 ext++;
293 }
294}
295
2922d21d 296/* Set which ISA and extensions are available. */
e23eba97 297
e23eba97 298static void
2922d21d 299riscv_set_arch (const char *s)
e23eba97 300{
1080bf78
JW		 301 riscv_parse_subset_t rps;
302 rps.subset_list = &riscv_subsets;
303 rps.error_handler = as_fatal;
304 rps.xlen = &xlen;
8f595e9b
NC		 305 rps.get_default_version = riscv_get_default_ext_version;
306
307 if (s == NULL)
308 return;
7f999549 309
1080bf78
JW		 310 riscv_release_subset_list (&riscv_subsets);
311 riscv_parse_subset (&rps, s);
e23eba97
NC		 312}
313
314/* Handle of the OPCODE hash table. */
629310ab 315static htab_t op_hash = NULL;
e23eba97 316
0e35537d 317/* Handle of the type of .insn hash table. */
629310ab 318static htab_t insn_type_hash = NULL;
0e35537d 319
e23eba97
NC		 320/* This array holds the chars that always start a comment. If the
321 pre-processor is disabled, these aren't very useful */
322const char comment_chars[] = "#";
323
324/* This array holds the chars that only start a comment at the beginning of
325 a line. If the line seems to have the form '# 123 filename'
326 .line and .file directives will appear in the pre-processed output */
327/* Note that input_file.c hand checks for '#' at the beginning of the
328 first line of the input file. This is because the compiler outputs
329 #NO_APP at the beginning of its output. */
330/* Also note that C style comments are always supported. */
331const char line_comment_chars[] = "#";
332
333/* This array holds machine specific line separator characters. */
334const char line_separator_chars[] = ";";
335
336/* Chars that can be used to separate mant from exp in floating point nums */
337const char EXP_CHARS[] = "eE";
338
339/* Chars that mean this number is a floating point constant */
340/* As in 0f12.456 */
341/* or 0d1.2345e12 */
342const char FLT_CHARS[] = "rRsSfFdDxXpP";
343
2dc8dd17
JW		 344/* Indicate we are already assemble any instructions or not. */
345static bfd_boolean start_assemble = FALSE;
346
8f595e9b
NC		 347/* Indicate ELF attributes are explictly set. */
348static bfd_boolean explicit_attr = FALSE;
2dc8dd17 349
1a79004f
NC		 350/* Indicate CSR or priv instructions are explictly used. */
351static bfd_boolean explicit_priv_attr = FALSE;
3fc6c3dc 352
e23eba97
NC		 353/* Macros for encoding relaxation state for RVC branches and far jumps. */
354#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
355 ((relax_substateT) \
356 (0xc0000000 \
357 | ((uncond) ? 1 : 0) \
358 | ((rvc) ? 2 : 0) \
359 | ((length) << 2)))
360#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
361#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
362#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
363#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
364
365/* Is the given value a sign-extended 32-bit value? */
366#define IS_SEXT_32BIT_NUM(x) \
367 (((x) &~ (offsetT) 0x7fffffff) == 0 \
368 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
369
370/* Is the given value a zero-extended 32-bit value? Or a negated one? */
371#define IS_ZEXT_32BIT_NUM(x) \
372 (((x) &~ (offsetT) 0xffffffff) == 0 \
373 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
374
375/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
376 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
377#define INSERT_OPERAND(FIELD, INSN, VALUE) \
378 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
379
380/* Determine if an instruction matches an opcode. */
381#define OPCODE_MATCHES(OPCODE, OP) \
382 (((OPCODE) & MASK_##OP) == MATCH_##OP)
383
384static char *expr_end;
385
386/* The default target format to use. */
387
388const char *
389riscv_target_format (void)
390{
391 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
392}
393
394/* Return the length of instruction INSN. */
395
396static inline unsigned int
397insn_length (const struct riscv_cl_insn *insn)
398{
399 return riscv_insn_length (insn->insn_opcode);
400}
401
402/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
403
404static void
405create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
406{
407 insn->insn_mo = mo;
408 insn->insn_opcode = mo->match;
409 insn->frag = NULL;
410 insn->where = 0;
411 insn->fixp = NULL;
412}
413
414/* Install INSN at the location specified by its "frag" and "where" fields. */
415
416static void
417install_insn (const struct riscv_cl_insn *insn)
418{
419 char *f = insn->frag->fr_literal + insn->where;
420 md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
421}
422
423/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
424 and install the opcode in the new location. */
425
426static void
427move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
428{
429 insn->frag = frag;
430 insn->where = where;
431 if (insn->fixp != NULL)
432 {
433 insn->fixp->fx_frag = frag;
434 insn->fixp->fx_where = where;
435 }
436 install_insn (insn);
437}
438
439/* Add INSN to the end of the output. */
440
441static void
442add_fixed_insn (struct riscv_cl_insn *insn)
443{
444 char *f = frag_more (insn_length (insn));
445 move_insn (insn, frag_now, f - frag_now->fr_literal);
446}
447
448static void
449add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
450 relax_substateT subtype, symbolS *symbol, offsetT offset)
451{
452 frag_grow (max_chars);
453 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
454 frag_var (rs_machine_dependent, max_chars, var,
455 subtype, symbol, offset, NULL);
456}
457
458/* Compute the length of a branch sequence, and adjust the stored length
459 accordingly. If FRAGP is NULL, the worst-case length is returned. */
460
461static unsigned
462relaxed_branch_length (fragS *fragp, asection *sec, int update)
463{
464 int jump, rvc, length = 8;
465
466 if (!fragp)
467 return length;
468
469 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
470 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
471 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
472
473 /* Assume jumps are in range; the linker will catch any that aren't. */
474 length = jump ? 4 : 8;
475
476 if (fragp->fr_symbol != NULL
477 && S_IS_DEFINED (fragp->fr_symbol)
01156111 478 && !S_IS_WEAK (fragp->fr_symbol)
e23eba97
NC		 479 && sec == S_GET_SEGMENT (fragp->fr_symbol))
480 {
481 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
482 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
483 val -= fragp->fr_address + fragp->fr_fix;
484
485 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
486 length = 2;
487 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
488 length = 4;
489 else if (!jump && rvc)
490 length = 6;
491 }
492
493 if (update)
494 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
495
496 return length;
497}
498
0e35537d
JW		 499/* Information about an opcode name, mnemonics and its value. */
500struct opcode_name_t
501{
502 const char *name;
503 unsigned int val;
504};
505
506/* List for all supported opcode name. */
507static const struct opcode_name_t opcode_name_list[] =
508{
509 {"C0", 0x0},
510 {"C1", 0x1},
511 {"C2", 0x2},
512
513 {"LOAD", 0x03},
514 {"LOAD_FP", 0x07},
515 {"CUSTOM_0", 0x0b},
516 {"MISC_MEM", 0x0f},
517 {"OP_IMM", 0x13},
518 {"AUIPC", 0x17},
519 {"OP_IMM_32", 0x1b},
520 /* 48b 0x1f. */
521
522 {"STORE", 0x23},
523 {"STORE_FP", 0x27},
524 {"CUSTOM_1", 0x2b},
525 {"AMO", 0x2f},
526 {"OP", 0x33},
527 {"LUI", 0x37},
528 {"OP_32", 0x3b},
529 /* 64b 0x3f. */
530
531 {"MADD", 0x43},
532 {"MSUB", 0x47},
533 {"NMADD", 0x4f},
534 {"NMSUB", 0x4b},
535 {"OP_FP", 0x53},
536 /*reserved 0x57. */
537 {"CUSTOM_2", 0x5b},
538 /* 48b 0x5f. */
539
540 {"BRANCH", 0x63},
541 {"JALR", 0x67},
542 /*reserved 0x5b. */
543 {"JAL", 0x6f},
544 {"SYSTEM", 0x73},
545 /*reserved 0x77. */
546 {"CUSTOM_3", 0x7b},
547 /* >80b 0x7f. */
548
549 {NULL, 0}
550};
551
552/* Hash table for lookup opcode name. */
629310ab 553static htab_t opcode_names_hash = NULL;
0e35537d
JW		 554
555/* Initialization for hash table of opcode name. */
556static void
557init_opcode_names_hash (void)
558{
0e35537d
JW		 559 const struct opcode_name_t *opcode;
560
561 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
fe0e921f
AM		 562 if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL)
563 as_fatal (_("duplicate %s"), opcode->name);
0e35537d
JW		 564}
565
566/* Find `s` is a valid opcode name or not,
567 return the opcode name info if found. */
568static const struct opcode_name_t *
569opcode_name_lookup (char **s)
570{
571 char *e;
572 char save_c;
573 struct opcode_name_t *o;
574
575 /* Find end of name. */
576 e = *s;
577 if (is_name_beginner (*e))
578 ++e;
579 while (is_part_of_name (*e))
580 ++e;
581
582 /* Terminate name. */
583 save_c = *e;
584 *e = '\0';
585
629310ab 586 o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s);
0e35537d
JW		 587
588 /* Advance to next token if one was recognized. */
589 if (o)
590 *s = e;
591
592 *e = save_c;
593 expr_end = e;
594
595 return o;
596}
597
e23eba97
NC		 598enum reg_class
599{
600 RCLASS_GPR,
601 RCLASS_FPR,
8f595e9b
NC		 602 RCLASS_MAX,
603
604 RCLASS_CSR
e23eba97
NC		 605};
606
629310ab
ML		 607static htab_t reg_names_hash = NULL;
608static htab_t csr_extra_hash = NULL;
e23eba97
NC		 609
610#define ENCODE_REG_HASH(cls, n) \
611 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
612#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
613#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
614
615static void
616hash_reg_name (enum reg_class class, const char *name, unsigned n)
617{
618 void *hash = ENCODE_REG_HASH (class, n);
fe0e921f
AM		 619 if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL)
620 as_fatal (_("duplicate %s"), name);
e23eba97
NC		 621}
622
623static void
624hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
625{
626 unsigned i;
627
628 for (i = 0; i < n; i++)
629 hash_reg_name (class, names[i], i);
630}
631
8f595e9b
NC		 632/* Init hash table csr_extra_hash to handle CSR. */
633static void
634riscv_init_csr_hash (const char *name,
635 unsigned address,
636 enum riscv_csr_class class,
637 enum riscv_priv_spec_class define_version,
638 enum riscv_priv_spec_class abort_version)
639{
640 struct riscv_csr_extra *entry, *pre_entry;
8f595e9b
NC		 641 bfd_boolean need_enrty = TRUE;
642
643 pre_entry = NULL;
629310ab 644 entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
8f595e9b
NC		 645 while (need_enrty && entry != NULL)
646 {
647 if (entry->csr_class == class
648 && entry->address == address
649 && entry->define_version == define_version
650 && entry->abort_version == abort_version)
651 need_enrty = FALSE;
652 pre_entry = entry;
653 entry = entry->next;
654 }
655
656 /* Duplicate setting for the CSR, just return and do nothing. */
657 if (!need_enrty)
658 return;
bd0cf5a6 659
8f595e9b
NC		 660 entry = XNEW (struct riscv_csr_extra);
661 entry->csr_class = class;
662 entry->address = address;
663 entry->define_version = define_version;
664 entry->abort_version = abort_version;
5c505568 665 entry->next = NULL;
8f595e9b
NC		 666
667 /* If the CSR hasn't been inserted in the hash table, then insert it.
668 Otherwise, attach the extra information to the entry which is already
669 in the hash table. */
670 if (pre_entry == NULL)
fe0e921f 671 str_hash_insert (csr_extra_hash, name, entry, 0);
8f595e9b
NC		 672 else
673 pre_entry->next = entry;
674}
bd0cf5a6 675
08ccfccf
NC		 676/* Return the suitable CSR address after checking the ISA dependency and
677 priv spec versions. */
bd0cf5a6 678
08ccfccf
NC		 679static unsigned int
680riscv_csr_address (const char *csr_name,
681 struct riscv_csr_extra *entry)
bd0cf5a6 682{
08ccfccf
NC		 683 struct riscv_csr_extra *saved_entry = entry;
684 enum riscv_csr_class csr_class = entry->csr_class;
685 bfd_boolean need_check_version = TRUE;
8f595e9b
NC		 686 bfd_boolean result = TRUE;
687
8f595e9b 688 switch (csr_class)
bd0cf5a6 689 {
8f595e9b
NC		 690 case CSR_CLASS_I:
691 result = riscv_subset_supports ("i");
692 break;
08ccfccf
NC		 693 case CSR_CLASS_I_32:
694 result = (xlen == 32 && riscv_subset_supports ("i"));
695 break;
8f595e9b
NC		 696 case CSR_CLASS_F:
697 result = riscv_subset_supports ("f");
08ccfccf 698 need_check_version = FALSE;
8f595e9b 699 break;
08ccfccf
NC		 700 case CSR_CLASS_DEBUG:
701 need_check_version = FALSE;
8f595e9b
NC		 702 break;
703 default:
704 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
bd0cf5a6
NC		 705 }
706
08ccfccf
NC		 707 /* Don't report the ISA conflict when -mcsr-check isn't set. */
708 if (riscv_opts.csr_check && !result)
709 as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name);
8f595e9b
NC		 710
711 while (entry != NULL)
bd0cf5a6 712 {
08ccfccf
NC		 713 if (!need_check_version
714 || (default_priv_spec >= entry->define_version
715 && default_priv_spec < entry->abort_version))
8f595e9b
NC		 716 {
717 /* Find the suitable CSR according to the specific version. */
08ccfccf 718 return entry->address;
8f595e9b
NC		 719 }
720 entry = entry->next;
721 }
bd0cf5a6 722
8f595e9b
NC		 723 /* We can not find the suitable CSR address according to the privilege
724 version. Therefore, we use the last defined value. Report the warning
725 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
726 otherwise, you may get the unexpected CSR address. */
727 if (riscv_opts.csr_check)
728 {
729 const char *priv_name = riscv_get_priv_spec_name (default_priv_spec);
730
731 if (priv_name != NULL)
732 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
733 csr_name, priv_name);
bd0cf5a6 734 }
08ccfccf
NC		 735
736 return saved_entry->address;
bd0cf5a6
NC		 737}
738
8f595e9b
NC		 739/* Once the CSR is defined, including the old privilege spec, then we call
740 riscv_csr_class_check and riscv_csr_version_check to do the further checking
741 and get the corresponding address. Return -1 if the CSR is never been
742 defined. Otherwise, return the address. */
bd0cf5a6 743
8f595e9b 744static unsigned int
bd0cf5a6
NC		 745reg_csr_lookup_internal (const char *s)
746{
747 struct riscv_csr_extra *r =
629310ab 748 (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s);
bd0cf5a6
NC		 749
750 if (r == NULL)
8f595e9b 751 return -1U;
bd0cf5a6 752
8f595e9b
NC		 753 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
754 the CSR was defined, but isn't allowed for the current ISA setting or
755 the privilege spec. If the CSR is never been defined, then assembler
756 will regard it as a "Unknown CSR" and report error. If user use number
757 to set the CSR, but over the range (> 0xfff), then assembler will report
758 "Improper CSR" error for it. */
08ccfccf 759 return riscv_csr_address (s, r);
bd0cf5a6
NC		 760}
761
e23eba97
NC		 762static unsigned int
763reg_lookup_internal (const char *s, enum reg_class class)
764{
8f595e9b
NC		 765 void *r;
766
767 if (class == RCLASS_CSR)
768 return reg_csr_lookup_internal (s);
e23eba97 769
629310ab 770 r = str_hash_find (reg_names_hash, s);
e23eba97
NC		 771 if (r == NULL || DECODE_REG_CLASS (r) != class)
772 return -1;
7f999549
JW		 773
774 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
775 return -1;
776
e23eba97
NC		 777 return DECODE_REG_NUM (r);
778}
779
780static bfd_boolean
781reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
782{
783 char *e;
784 char save_c;
785 int reg = -1;
786
787 /* Find end of name. */
788 e = *s;
789 if (is_name_beginner (*e))
790 ++e;
791 while (is_part_of_name (*e))
792 ++e;
793
794 /* Terminate name. */
795 save_c = *e;
796 *e = '\0';
797
798 /* Look for the register. Advance to next token if one was recognized. */
799 if ((reg = reg_lookup_internal (*s, class)) >= 0)
800 *s = e;
801
802 *e = save_c;
803 if (regnop)
804 *regnop = reg;
805 return reg >= 0;
806}
807
808static bfd_boolean
809arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
810{
811 const char *p = strchr (*s, ',');
812 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
813
bfb218e3
JW		 814 if (len == 0)
815 return FALSE;
816
e23eba97
NC		 817 for (i = 0; i < size; i++)
818 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
819 {
820 *regnop = i;
821 *s += len;
822 return TRUE;
823 }
824
825 return FALSE;
826}
827
828/* For consistency checking, verify that all bits are specified either
829 by the match/mask part of the instruction definition, or by the
0e35537d
JW		 830 operand list.
831
832 `length` could be 0, 4 or 8, 0 for auto detection. */
e23eba97 833static bfd_boolean
0e35537d 834validate_riscv_insn (const struct riscv_opcode *opc, int length)
e23eba97
NC		 835{
836 const char *p = opc->args;
837 char c;
838 insn_t used_bits = opc->mask;
0e35537d
JW		 839 int insn_width;
840 insn_t required_bits;
841
842 if (length == 0)
843 insn_width = 8 * riscv_insn_length (opc->match);
844 else
845 insn_width = 8 * length;
846
847 required_bits = ~0ULL >> (64 - insn_width);
e23eba97
NC		 848
849 if ((used_bits & opc->match) != (opc->match & required_bits))
850 {
851 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
852 opc->name, opc->args);
853 return FALSE;
854 }
855
856#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
857 while (*p)
858 switch (c = *p++)
859 {
860 case 'C': /* RVC */
861 switch (c = *p++)
862 {
1d65abb5 863 case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
e23eba97
NC		 864 case 'c': break; /* RS1, constrained to equal sp */
865 case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
1d65abb5 866 case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
b416fe87 867 case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
1d65abb5
AW		 868 case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
869 case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
870 case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
871 case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
872 case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
e23eba97
NC		 873 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
874 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
1d65abb5
AW		 875 case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
876 case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
e23eba97
NC		 877 case 'w': break; /* RS1S, constrained to equal RD */
878 case 'x': break; /* RS2S, constrained to equal RD */
ca0bc150 879 case 'z': break; /* RS2S, contrained to be x0 */
1d65abb5
AW		 880 case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
881 case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
882 case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
883 case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
e23eba97
NC		 884 case 'U': break; /* RS1, constrained to equal RD */
885 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1d65abb5
AW		 886 case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
887 case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
0e35537d
JW		 888 case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
889 case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
e23eba97
NC		 890 case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
891 case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
0e35537d
JW		 892 case 'F': /* funct */
893 switch (c = *p++)
894 {
4765cd61 895 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
0e35537d
JW		 896 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
897 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
4765cd61 898 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
0e35537d
JW		 899 default:
900 as_bad (_("internal: bad RISC-V opcode"
901 " (unknown operand type `CF%c'): %s %s"),
902 c, opc->name, opc->args);
903 return FALSE;
904 }
905 break;
e23eba97
NC		 906 default:
907 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
908 c, opc->name, opc->args);
909 return FALSE;
910 }
911 break;
912 case ',': break;
913 case '(': break;
914 case ')': break;
915 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
916 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
917 case 'A': break;
918 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
919 case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
920 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
921 case 'I': break;
922 case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
923 case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
924 case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */
925 case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
926 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
927 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
928 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
929 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
0e35537d 930 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
e23eba97
NC		 931 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
932 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
933 case 'o':
1d65abb5
AW		 934 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
935 case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
936 case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
937 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
938 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
e925c834 939 case 'z': break;
e23eba97
NC		 940 case '[': break;
941 case ']': break;
942 case '0': break;
f50fabe4 943 case '1': break;
0e35537d
JW		 944 case 'F': /* funct */
945 switch (c = *p++)
946 {
947 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
948 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
949 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
950 default:
951 as_bad (_("internal: bad RISC-V opcode"
952 " (unknown operand type `F%c'): %s %s"),
953 c, opc->name, opc->args);
954 return FALSE;
955 }
956 break;
957 case 'O': /* opcode */
958 switch (c = *p++)
959 {
960 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
961 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
962 default:
963 as_bad (_("internal: bad RISC-V opcode"
964 " (unknown operand type `F%c'): %s %s"),
965 c, opc->name, opc->args);
966 return FALSE;
967 }
968 break;
e23eba97
NC		 969 default:
970 as_bad (_("internal: bad RISC-V opcode "
971 "(unknown operand type `%c'): %s %s"),
972 c, opc->name, opc->args);
973 return FALSE;
974 }
975#undef USE_BITS
976 if (used_bits != required_bits)
977 {
978 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
979 ~(unsigned long)(used_bits & required_bits),
980 opc->name, opc->args);
981 return FALSE;
982 }
983 return TRUE;
984}
985
986struct percent_op_match
987{
988 const char *str;
989 bfd_reloc_code_real_type reloc;
990};
991
0e35537d
JW		 992/* Common hash table initialization function for
993 instruction and .insn directive. */
629310ab 994static htab_t
0e35537d
JW		 995init_opcode_hash (const struct riscv_opcode *opcodes,
996 bfd_boolean insn_directive_p)
e23eba97
NC		 997{
998 int i = 0;
0e35537d 999 int length;
629310ab 1000 htab_t hash = str_htab_create ();
0e35537d 1001 while (opcodes[i].name)
e23eba97 1002 {
0e35537d 1003 const char *name = opcodes[i].name;
fe0e921f
AM		 1004 if (str_hash_insert (hash, name, &opcodes[i], 0) != NULL)
1005 as_fatal (_("duplicate %s"), name);
e23eba97
NC		 1006
1007 do
1008 {
0e35537d 1009 if (opcodes[i].pinfo != INSN_MACRO)
e23eba97 1010 {
0e35537d
JW		 1011 if (insn_directive_p)
1012 length = ((name[0] == 'c') ? 2 : 4);
1013 else
1014 length = 0; /* Let assembler determine the length. */
1015 if (!validate_riscv_insn (&opcodes[i], length))
e23eba97
NC		 1016 as_fatal (_("Broken assembler. No assembly attempted."));
1017 }
0e35537d
JW		 1018 else
1019 gas_assert (!insn_directive_p);
e23eba97
NC		 1020 ++i;
1021 }
0e35537d 1022 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
e23eba97
NC		 1023 }
1024
0e35537d
JW		 1025 return hash;
1026}
1027
1028/* This function is called once, at assembler startup time. It should set up
1029 all the tables, etc. that the MD part of the assembler will need. */
1030
1031void
1032md_begin (void)
1033{
1034 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
1035
1036 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
1037 as_warn (_("Could not set architecture and machine"));
1038
1039 op_hash = init_opcode_hash (riscv_opcodes, FALSE);
1040 insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
1041
629310ab 1042 reg_names_hash = str_htab_create ();
e23eba97
NC		 1043 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
1044 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
1045 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
1046 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
b9c04e5a
JW		 1047 /* Add "fp" as an alias for "s0". */
1048 hash_reg_name (RCLASS_GPR, "fp", 8);
1049
bd0cf5a6 1050 /* Create and insert CSR hash tables. */
629310ab 1051 csr_extra_hash = str_htab_create ();
8f595e9b
NC		 1052#define DECLARE_CSR(name, num, class, define_version, abort_version) \
1053 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1054#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1055 DECLARE_CSR(name, num, class, define_version, abort_version);
e23eba97
NC		 1056#include "opcode/riscv-opc.h"
1057#undef DECLARE_CSR
1058
629310ab 1059 opcode_names_hash = str_htab_create ();
bd0cf5a6
NC		 1060 init_opcode_names_hash ();
1061
e23eba97
NC		 1062 /* Set the default alignment for the text section. */
1063 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
1064}
1065
45f76423
AW		 1066static insn_t
1067riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
1068{
1069 switch (reloc_type)
1070 {
1071 case BFD_RELOC_32:
1072 return value;
1073
1074 case BFD_RELOC_RISCV_HI20:
1075 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
1076
1077 case BFD_RELOC_RISCV_LO12_S:
1078 return ENCODE_STYPE_IMM (value);
1079
1080 case BFD_RELOC_RISCV_LO12_I:
1081 return ENCODE_ITYPE_IMM (value);
1082
1083 default:
1084 abort ();
1085 }
1086}
1087
e23eba97
NC		 1088/* Output an instruction. IP is the instruction information.
1089 ADDRESS_EXPR is an operand of the instruction to be used with
1090 RELOC_TYPE. */
1091
1092static void
1093append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
1094 bfd_reloc_code_real_type reloc_type)
1095{
1096 dwarf2_emit_insn (0);
1097
1098 if (reloc_type != BFD_RELOC_UNUSED)
1099 {
1100 reloc_howto_type *howto;
1101
1d65abb5 1102 gas_assert (address_expr);
e23eba97
NC		 1103 if (reloc_type == BFD_RELOC_12_PCREL
1104 || reloc_type == BFD_RELOC_RISCV_JMP)
1105 {
1106 int j = reloc_type == BFD_RELOC_RISCV_JMP;
1107 int best_case = riscv_insn_length (ip->insn_opcode);
1108 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
1109 add_relaxed_insn (ip, worst_case, best_case,
1110 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
1111 address_expr->X_add_symbol,
1112 address_expr->X_add_number);
1113 return;
1114 }
45f76423 1115 else
e23eba97 1116 {
45f76423
AW		 1117 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
1118 if (howto == NULL)
1119 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
e23eba97 1120
45f76423
AW		 1121 ip->fixp = fix_new_exp (ip->frag, ip->where,
1122 bfd_get_reloc_size (howto),
1123 address_expr, FALSE, reloc_type);
e23eba97 1124
45f76423 1125 ip->fixp->fx_tcbit = riscv_opts.relax;
e23eba97 1126 }
e23eba97
NC		 1127 }
1128
e23eba97
NC		 1129 add_fixed_insn (ip);
1130 install_insn (ip);
f77bb6c5
JW		 1131
1132 /* We need to start a new frag after any instruction that can be
1133 optimized away or compressed by the linker during relaxation, to prevent
1134 the assembler from computing static offsets across such an instruction.
1135 This is necessary to get correct EH info. */
b1b11e92 1136 if (reloc_type == BFD_RELOC_RISCV_HI20
f77bb6c5
JW		 1137 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
1138 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
1139 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
1140 {
1141 frag_wane (frag_now);
1142 frag_new (0);
1143 }
e23eba97
NC		 1144}
1145
1146/* Build an instruction created by a macro expansion. This is passed
1147 a pointer to the count of instructions created so far, an
1148 expression, the name of the instruction to build, an operand format
1149 string, and corresponding arguments. */
1150
1151static void
1152macro_build (expressionS *ep, const char *name, const char *fmt, ...)
1153{
1154 const struct riscv_opcode *mo;
1155 struct riscv_cl_insn insn;
1156 bfd_reloc_code_real_type r;
1157 va_list args;
1158
1159 va_start (args, fmt);
1160
1161 r = BFD_RELOC_UNUSED;
629310ab 1162 mo = (struct riscv_opcode *) str_hash_find (op_hash, name);
e23eba97
NC		 1163 gas_assert (mo);
1164
1165 /* Find a non-RVC variant of the instruction. append_insn will compress
1166 it if possible. */
1167 while (riscv_insn_length (mo->match) < 4)
1168 mo++;
1169 gas_assert (strcmp (name, mo->name) == 0);
1170
1171 create_insn (&insn, mo);
1172 for (;;)
1173 {
1174 switch (*fmt++)
1175 {
1176 case 'd':
1177 INSERT_OPERAND (RD, insn, va_arg (args, int));
1178 continue;
1179
1180 case 's':
1181 INSERT_OPERAND (RS1, insn, va_arg (args, int));
1182 continue;
1183
1184 case 't':
1185 INSERT_OPERAND (RS2, insn, va_arg (args, int));
1186 continue;
1187
1188 case '>':
1189 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
1190 continue;
1191
1192 case 'j':
1193 case 'u':
1194 case 'q':
1195 gas_assert (ep != NULL);
1196 r = va_arg (args, int);
1197 continue;
1198
1199 case '\0':
1200 break;
1201 case ',':
1202 continue;
1203 default:
1204 as_fatal (_("internal error: invalid macro"));
1205 }
1206 break;
1207 }
1208 va_end (args);
1209 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1210
1211 append_insn (&insn, ep, r);
1212}
1213
db3b6ecc
KC		 1214/* Build an instruction created by a macro expansion. Like md_assemble but
1215 accept a printf-style format string and arguments. */
1216
1217static void
1218md_assemblef (const char *format, ...)
1219{
1220 char *buf = NULL;
1221 va_list ap;
1222 int r;
1223
1224 va_start (ap, format);
1225
1226 r = vasprintf (&buf, format, ap);
1227
1228 if (r < 0)
1229 as_fatal (_("internal error: vasprintf failed"));
1230
1231 md_assemble (buf);
1232 free(buf);
1233
1234 va_end (ap);
1235}
1236
e23eba97
NC		 1237/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1238 unset. */
1239static void
1240normalize_constant_expr (expressionS *ex)
1241{
1242 if (xlen > 32)
1243 return;
1244 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1245 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1246 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1247 - 0x80000000);
1248}
1249
ca2fd32c
JW		 1250/* Fail if an expression EX is not a constant. IP is the instruction using EX.
1251 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
e23eba97
NC		 1252
1253static void
ca2fd32c
JW		 1254check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
1255 bfd_boolean maybe_csr)
e23eba97
NC		 1256{
1257 if (ex->X_op == O_big)
1258 as_bad (_("unsupported large constant"));
ca2fd32c
JW		 1259 else if (maybe_csr && ex->X_op == O_symbol)
1260 as_bad (_("unknown CSR `%s'"),
1261 S_GET_NAME (ex->X_add_symbol));
e23eba97
NC		 1262 else if (ex->X_op != O_constant)
1263 as_bad (_("Instruction %s requires absolute expression"),
1264 ip->insn_mo->name);
1265 normalize_constant_expr (ex);
1266}
1267
1268static symbolS *
1269make_internal_label (void)
1270{
e01e1cee
AM		 1271 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now,
1272 frag_now_fix ());
e23eba97
NC		 1273}
1274
1275/* Load an entry from the GOT. */
1276static void
1277pcrel_access (int destreg, int tempreg, expressionS *ep,
1278 const char *lo_insn, const char *lo_pattern,
1279 bfd_reloc_code_real_type hi_reloc,
1280 bfd_reloc_code_real_type lo_reloc)
1281{
1282 expressionS ep2;
1283 ep2.X_op = O_symbol;
1284 ep2.X_add_symbol = make_internal_label ();
1285 ep2.X_add_number = 0;
1286
1287 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1288 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1289}
1290
1291static void
1292pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1293 bfd_reloc_code_real_type hi_reloc,
1294 bfd_reloc_code_real_type lo_reloc)
1295{
1296 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1297}
1298
1299static void
1300pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1301 bfd_reloc_code_real_type hi_reloc,
1302 bfd_reloc_code_real_type lo_reloc)
1303{
1304 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1305}
1306
1307/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1308static void
1309riscv_call (int destreg, int tempreg, expressionS *ep,
1310 bfd_reloc_code_real_type reloc)
1311{
b1b11e92
AM		 1312 /* Ensure the jalr is emitted to the same frag as the auipc. */
1313 frag_grow (8);
e23eba97
NC		 1314 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1315 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
b1b11e92
AM		 1316 /* See comment at end of append_insn. */
1317 frag_wane (frag_now);
1318 frag_new (0);
e23eba97
NC		 1319}
1320
1321/* Load an integer constant into a register. */
1322
1323static void
1324load_const (int reg, expressionS *ep)
1325{
1326 int shift = RISCV_IMM_BITS;
4f7cc141 1327 bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1);
e23eba97 1328 expressionS upper = *ep, lower = *ep;
4f7cc141 1329 lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign;
e23eba97
NC		 1330 upper.X_add_number -= lower.X_add_number;
1331
1332 if (ep->X_op != O_constant)
1333 {
1334 as_bad (_("unsupported large constant"));
1335 return;
1336 }
1337
1d65abb5 1338 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
e23eba97
NC		 1339 {
1340 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1341 while (((upper.X_add_number >> shift) & 1) == 0)
1342 shift++;
1343
1344 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1d65abb5 1345 load_const (reg, &upper);
e23eba97 1346
db3b6ecc 1347 md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift);
e23eba97 1348 if (lower.X_add_number != 0)
db3b6ecc
KC		 1349 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg,
1350 lower.X_add_number);
e23eba97
NC		 1351 }
1352 else
1353 {
1354 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1355 int hi_reg = 0;
1356
1357 if (upper.X_add_number != 0)
1358 {
db3b6ecc
KC		 1359 /* Discard low part and zero-extend upper immediate. */
1360 upper_imm = ((uint32_t)upper.X_add_number >> shift);
1361
1362 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm);
e23eba97
NC		 1363 hi_reg = reg;
1364 }
1365
1366 if (lower.X_add_number != 0 || hi_reg == 0)
db3b6ecc
KC		 1367 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg,
1368 lower.X_add_number);
e23eba97
NC		 1369 }
1370}
1371
1372/* Expand RISC-V assembly macros into one or more instructions. */
1373static void
1374macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1375 bfd_reloc_code_real_type *imm_reloc)
1376{
1377 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1378 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1379 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1380 int mask = ip->insn_mo->mask;
1381
1382 switch (mask)
1383 {
1384 case M_LI:
1385 load_const (rd, imm_expr);
1386 break;
1387
1388 case M_LA:
1389 case M_LLA:
1390 /* Load the address of a symbol into a register. */
1391 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1392 as_bad (_("offset too large"));
1393
1394 if (imm_expr->X_op == O_constant)
1395 load_const (rd, imm_expr);
1396 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */
1397 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1398 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1399 else /* Local PIC symbol, or any non-PIC symbol */
1400 pcrel_load (rd, rd, imm_expr, "addi",
1401 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1402 break;
1403
1404 case M_LA_TLS_GD:
1405 pcrel_load (rd, rd, imm_expr, "addi",
1406 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1407 break;
1408
1409 case M_LA_TLS_IE:
1410 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1411 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1412 break;
1413
1414 case M_LB:
1415 pcrel_load (rd, rd, imm_expr, "lb",
1416 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1417 break;
1418
1419 case M_LBU:
1420 pcrel_load (rd, rd, imm_expr, "lbu",
1421 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1422 break;
1423
1424 case M_LH:
1425 pcrel_load (rd, rd, imm_expr, "lh",
1426 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1427 break;
1428
1429 case M_LHU:
1430 pcrel_load (rd, rd, imm_expr, "lhu",
1431 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1432 break;
1433
1434 case M_LW:
1435 pcrel_load (rd, rd, imm_expr, "lw",
1436 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1437 break;
1438
1439 case M_LWU:
1440 pcrel_load (rd, rd, imm_expr, "lwu",
1441 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1442 break;
1443
1444 case M_LD:
1445 pcrel_load (rd, rd, imm_expr, "ld",
1446 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1447 break;
1448
1449 case M_FLW:
1450 pcrel_load (rd, rs1, imm_expr, "flw",
1451 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1452 break;
1453
1454 case M_FLD:
1455 pcrel_load (rd, rs1, imm_expr, "fld",
1456 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1457 break;
1458
1459 case M_SB:
1460 pcrel_store (rs2, rs1, imm_expr, "sb",
1461 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1462 break;
1463
1464 case M_SH:
1465 pcrel_store (rs2, rs1, imm_expr, "sh",
1466 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1467 break;
1468
1469 case M_SW:
1470 pcrel_store (rs2, rs1, imm_expr, "sw",
1471 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1472 break;
1473
1474 case M_SD:
1475 pcrel_store (rs2, rs1, imm_expr, "sd",
1476 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1477 break;
1478
1479 case M_FSW:
1480 pcrel_store (rs2, rs1, imm_expr, "fsw",
1481 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1482 break;
1483
1484 case M_FSD:
1485 pcrel_store (rs2, rs1, imm_expr, "fsd",
1486 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1487 break;
1488
1489 case M_CALL:
1490 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1491 break;
1492
1493 default:
1494 as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
1495 break;
1496 }
1497}
1498
1499static const struct percent_op_match percent_op_utype[] =
1500{
1501 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1502 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
dee35d02 1503 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
e23eba97
NC		 1504 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1505 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1506 {"%hi", BFD_RELOC_RISCV_HI20},
1507 {0, 0}
1508};
1509
1510static const struct percent_op_match percent_op_itype[] =
1511{
1512 {"%lo", BFD_RELOC_RISCV_LO12_I},
1513 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1514 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1515 {0, 0}
1516};
1517
1518static const struct percent_op_match percent_op_stype[] =
1519{
1520 {"%lo", BFD_RELOC_RISCV_LO12_S},
1521 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1522 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1523 {0, 0}
1524};
1525
1526static const struct percent_op_match percent_op_rtype[] =
1527{
1528 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1529 {0, 0}
1530};
1531
f50fabe4
JW		 1532static const struct percent_op_match percent_op_null[] =
1533{
1534 {0, 0}
1535};
1536
e23eba97
NC		 1537/* Return true if *STR points to a relocation operator. When returning true,
1538 move *STR over the operator and store its relocation code in *RELOC.
1539 Leave both *STR and *RELOC alone when returning false. */
1540
1541static bfd_boolean
1542parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1543 const struct percent_op_match *percent_op)
1544{
1545 for ( ; percent_op->str; percent_op++)
1546 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1547 {
1548 int len = strlen (percent_op->str);
1549
1550 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1551 continue;
1552
1553 *str += strlen (percent_op->str);
1554 *reloc = percent_op->reloc;
1555
1556 /* Check whether the output BFD supports this relocation.
1557 If not, issue an error and fall back on something safe. */
45f76423
AW		 1558 if (*reloc != BFD_RELOC_UNUSED
1559 && !bfd_reloc_type_lookup (stdoutput, *reloc))
e23eba97
NC		 1560 {
1561 as_bad ("relocation %s isn't supported by the current ABI",
1562 percent_op->str);
1563 *reloc = BFD_RELOC_UNUSED;
1564 }
1565 return TRUE;
1566 }
1567 return FALSE;
1568}
1569
1570static void
1571my_getExpression (expressionS *ep, char *str)
1572{
1573 char *save_in;
1574
1575 save_in = input_line_pointer;
1576 input_line_pointer = str;
1577 expression (ep);
1578 expr_end = input_line_pointer;
1579 input_line_pointer = save_in;
1580}
1581
1582/* Parse string STR as a 16-bit relocatable operand. Store the
1583 expression in *EP and the relocation, if any, in RELOC.
1584 Return the number of relocation operators used (0 or 1).
1585
1586 On exit, EXPR_END points to the first character after the expression. */
1587
1588static size_t
1589my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1590 char *str, const struct percent_op_match *percent_op)
1591{
1592 size_t reloc_index;
1593 unsigned crux_depth, str_depth, regno;
1594 char *crux;
1595
8970c022
JW		 1596 /* First, check for integer registers. No callers can accept a reg, but
1597 we need to avoid accidentally creating a useless undefined symbol below,
1598 if this is an instruction pattern that can't match. A glibc build fails
1599 if this is removed. */
e23eba97
NC		 1600 if (reg_lookup (&str, RCLASS_GPR, &regno))
1601 {
1602 ep->X_op = O_register;
1603 ep->X_add_number = regno;
8970c022 1604 expr_end = str;
e23eba97
NC		 1605 return 0;
1606 }
1607
1608 /* Search for the start of the main expression.
1609 End the loop with CRUX pointing to the start
1610 of the main expression and with CRUX_DEPTH containing the number
1611 of open brackets at that point. */
1612 reloc_index = -1;
1613 str_depth = 0;
1614 do
1615 {
1616 reloc_index++;
1617 crux = str;
1618 crux_depth = str_depth;
1619
1620 /* Skip over whitespace and brackets, keeping count of the number
1621 of brackets. */
1622 while (*str == ' ' || *str == '\t' || *str == '(')
1623 if (*str++ == '(')
1624 str_depth++;
1625 }
1626 while (*str == '%'
1627 && reloc_index < 1
1628 && parse_relocation (&str, reloc, percent_op));
1629
1630 my_getExpression (ep, crux);
1631 str = expr_end;
1632
1633 /* Match every open bracket. */
1634 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1635 if (*str++ == ')')
1636 crux_depth--;
1637
1638 if (crux_depth > 0)
1639 as_bad ("unclosed '('");
1640
1641 expr_end = str;
1642
1643 return reloc_index;
1644}
1645
0e35537d
JW		 1646/* Parse opcode name, could be an mnemonics or number. */
1647static size_t
1648my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1649 char *str, const struct percent_op_match *percent_op)
1650{
1651 const struct opcode_name_t *o = opcode_name_lookup (&str);
1652
1653 if (o != NULL)
1654 {
1655 ep->X_op = O_constant;
1656 ep->X_add_number = o->val;
1657 return 0;
1658 }
1659
1660 return my_getSmallExpression (ep, reloc, str, percent_op);
1661}
1662
f0531ed6
JW		 1663/* Detect and handle implicitly zero load-store offsets. For example,
1664 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1665 an implicit offset was detected. */
1666
1667static bfd_boolean
89424b1d 1668riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
f0531ed6
JW		 1669{
1670 /* Check whether there is only a single bracketed expression left.
1671 If so, it must be the base register and the constant must be zero. */
1672 if (*s == '(' && strchr (s + 1, '(') == 0)
1673 {
89424b1d
MR		 1674 ep->X_op = O_constant;
1675 ep->X_add_number = 0;
f0531ed6
JW		 1676 return TRUE;
1677 }
1678
1679 return FALSE;
1680}
1681
54b2aec1
NC		 1682/* All RISC-V CSR instructions belong to one of these classes. */
1683
1684enum csr_insn_type
1685{
1686 INSN_NOT_CSR,
1687 INSN_CSRRW,
1688 INSN_CSRRS,
1689 INSN_CSRRC
1690};
1691
1692/* Return which CSR instruction is checking. */
1693
1694static enum csr_insn_type
1695riscv_csr_insn_type (insn_t insn)
1696{
1697 if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
1698 || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
1699 return INSN_CSRRW;
1700 else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
1701 || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
1702 return INSN_CSRRS;
1703 else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
1704 || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
1705 return INSN_CSRRC;
1706 else
1707 return INSN_NOT_CSR;
1708}
1709
1710/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1711 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1712 CSR address is 0x3. */
1713
1714static bfd_boolean
1715riscv_csr_read_only_check (insn_t insn)
1716{
1717 int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
1718 int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
1719 int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
1720 enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
1721
1722 if (readonly
1723 && (((csr_insn == INSN_CSRRS
1724 || csr_insn == INSN_CSRRC)
1725 && rs1 != 0)
1726 || csr_insn == INSN_CSRRW))
1727 return FALSE;
1728
1729 return TRUE;
1730}
1731
1a79004f
NC		 1732/* Return True if it is a privileged instruction. Otherwise, return FALSE.
1733
1734 uret is actually a N-ext instruction. So it is better to regard it as
1735 an user instruction rather than the priv instruction.
1736
1737 hret is used to return from traps in H-mode. H-mode is removed since
1738 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1739 Therefore, hret should be controlled by the hypervisor spec rather than
1740 priv spec in the future.
1741
1742 dret is defined in the debug spec, so it should be checked in the future,
1743 too. */
1744
1745static bfd_boolean
1746riscv_is_priv_insn (insn_t insn)
1747{
1748 return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
1749 || ((insn ^ MATCH_MRET) & MASK_MRET) == 0
1750 || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0
1751 || ((insn ^ MATCH_WFI) & MASK_WFI) == 0
1752 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1753 check it here to keep the compatible. Maybe we should issue warning
1754 if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
1755 We already have a similar check for CSR, but not yet for instructions.
1756 It would be good if we could check the spec versions both for CSR and
1757 instructions, but not here. */
1758 || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
1759}
1760
e23eba97
NC		 1761/* This routine assembles an instruction into its binary format. As a
1762 side effect, it sets the global variable imm_reloc to the type of
1763 relocation to do if one of the operands is an address expression. */
1764
1765static const char *
1766riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
629310ab 1767 bfd_reloc_code_real_type *imm_reloc, htab_t hash)
e23eba97
NC		 1768{
1769 char *s;
1770 const char *args;
1771 char c = 0;
1772 struct riscv_opcode *insn;
1773 char *argsStart;
1774 unsigned int regno;
1775 char save_c = 0;
1776 int argnum;
1777 const struct percent_op_match *p;
1778 const char *error = "unrecognized opcode";
54b2aec1
NC		 1779 /* Indicate we are assembling instruction with CSR. */
1780 bfd_boolean insn_with_csr = FALSE;
e23eba97
NC		 1781
1782 /* Parse the name of the instruction. Terminate the string if whitespace
629310ab 1783 is found so that str_hash_find only sees the name part of the string. */
e23eba97
NC		 1784 for (s = str; *s != '\0'; ++s)
1785 if (ISSPACE (*s))
1786 {
1787 save_c = *s;
1788 *s++ = '\0';
1789 break;
1790 }
1791
629310ab 1792 insn = (struct riscv_opcode *) str_hash_find (hash, str);
e23eba97
NC		 1793
1794 argsStart = s;
1795 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1796 {
1080bf78
JW		 1797 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
1798 continue;
1799
7e9ad3a3 1800 if (!riscv_multi_subset_supports (insn->insn_class))
e23eba97
NC		 1801 continue;
1802
1803 create_insn (ip, insn);
1804 argnum = 1;
1805
1806 imm_expr->X_op = O_absent;
1807 *imm_reloc = BFD_RELOC_UNUSED;
1808 p = percent_op_itype;
1809
1810 for (args = insn->args;; ++args)
1811 {
1812 s += strspn (s, " \t");
1813 switch (*args)
1814 {
1815 case '\0': /* End of args. */
1816 if (insn->pinfo != INSN_MACRO)
1817 {
1818 if (!insn->match_func (insn, ip->insn_opcode))
1819 break;
0e35537d
JW		 1820
1821 /* For .insn, insn->match and insn->mask are 0. */
1822 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
1823 ? ip->insn_opcode
1824 : insn->match) == 2
1825 && !riscv_opts.rvc)
e23eba97 1826 break;
54b2aec1 1827
1a79004f
NC		 1828 if (riscv_is_priv_insn (ip->insn_opcode))
1829 explicit_priv_attr = TRUE;
1830
54b2aec1
NC		 1831 /* Check if we write a read-only CSR by the CSR
1832 instruction. */
1833 if (insn_with_csr
1834 && riscv_opts.csr_check
1835 && !riscv_csr_read_only_check (ip->insn_opcode))
1836 {
1837 /* Restore the character in advance, since we want to
1838 report the detailed warning message here. */
1839 if (save_c)
1840 *(argsStart - 1) = save_c;
1841 as_warn (_("Read-only CSR is written `%s'"), str);
1842 insn_with_csr = FALSE;
1843 }
e23eba97
NC		 1844 }
1845 if (*s != '\0')
1846 break;
1847 /* Successful assembly. */
1848 error = NULL;
54b2aec1 1849 insn_with_csr = FALSE;
e23eba97
NC		 1850 goto out;
1851
1852 case 'C': /* RVC */
1853 switch (*++args)
1854 {
1855 case 's': /* RS1 x8-x15 */
1856 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1857 || !(regno >= 8 && regno <= 15))
1858 break;
1859 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1860 continue;
1861 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1862 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1863 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
1864 break;
1865 continue;
1866 case 't': /* RS2 x8-x15 */
1867 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1868 || !(regno >= 8 && regno <= 15))
1869 break;
1870 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1871 continue;
1872 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1873 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1874 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
1875 break;
1876 continue;
1877 case 'U': /* RS1, constrained to equal RD. */
1878 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1879 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
1880 break;
1881 continue;
1882 case 'V': /* RS2 */
1883 if (!reg_lookup (&s, RCLASS_GPR, &regno))
1884 break;
1885 INSERT_OPERAND (CRS2, *ip, regno);
1886 continue;
1887 case 'c': /* RS1, constrained to equal sp. */
1888 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1889 || regno != X_SP)
1890 break;
1891 continue;
ca0bc150
JW		 1892 case 'z': /* RS2, contrained to equal x0. */
1893 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1894 || regno != 0)
1895 break;
1896 continue;
e23eba97
NC		 1897 case '>':
1898 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1899 || imm_expr->X_op != O_constant
1900 || imm_expr->X_add_number <= 0
1901 || imm_expr->X_add_number >= 64)
1902 break;
1903 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
dc1e8a47 1904 rvc_imm_done:
e23eba97
NC		 1905 s = expr_end;
1906 imm_expr->X_op = O_absent;
1907 continue;
1908 case '<':
1909 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1910 || imm_expr->X_op != O_constant
e23eba97 1911 || imm_expr->X_add_number <= 0
169ec512
AM		 1912 || imm_expr->X_add_number >= 32
1913 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1914 break;
1915 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1916 goto rvc_imm_done;
0e35537d
JW		 1917 case '8':
1918 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1919 || imm_expr->X_op != O_constant
0e35537d 1920 || imm_expr->X_add_number < 0
169ec512
AM		 1921 || imm_expr->X_add_number >= 256
1922 || !VALID_RVC_UIMM8 ((valueT) imm_expr->X_add_number))
0e35537d
JW		 1923 break;
1924 ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
1925 goto rvc_imm_done;
e23eba97
NC		 1926 case 'i':
1927 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1928 || imm_expr->X_op != O_constant
1929 || imm_expr->X_add_number == 0
169ec512 1930 || !VALID_RVC_SIMM3 ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1931 break;
1932 ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
1933 goto rvc_imm_done;
1934 case 'j':
1935 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1936 || imm_expr->X_op != O_constant
1937 || imm_expr->X_add_number == 0
169ec512 1938 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1939 break;
1940 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1941 goto rvc_imm_done;
1942 case 'k':
f0531ed6
JW		 1943 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1944 continue;
e23eba97
NC		 1945 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1946 || imm_expr->X_op != O_constant
169ec512 1947 || !VALID_RVC_LW_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1948 break;
1949 ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
1950 goto rvc_imm_done;
1951 case 'l':
f0531ed6
JW		 1952 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1953 continue;
e23eba97
NC		 1954 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1955 || imm_expr->X_op != O_constant
169ec512 1956 || !VALID_RVC_LD_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1957 break;
1958 ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
1959 goto rvc_imm_done;
1960 case 'm':
f0531ed6
JW		 1961 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1962 continue;
e23eba97
NC		 1963 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1964 || imm_expr->X_op != O_constant
169ec512 1965 || !VALID_RVC_LWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1966 break;
1967 ip->insn_opcode |=
1968 ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
1969 goto rvc_imm_done;
1970 case 'n':
f0531ed6
JW		 1971 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1972 continue;
e23eba97
NC		 1973 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1974 || imm_expr->X_op != O_constant
169ec512 1975 || !VALID_RVC_LDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1976 break;
1977 ip->insn_opcode |=
1978 ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
1979 goto rvc_imm_done;
b416fe87
KC		 1980 case 'o':
1981 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1982 || imm_expr->X_op != O_constant
21a186f2
JW		 1983 /* C.addiw, c.li, and c.andi allow zero immediate.
1984 C.addi allows zero immediate as hint. Otherwise this
1985 is same as 'j'. */
169ec512 1986 || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
b416fe87
KC		 1987 break;
1988 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1989 goto rvc_imm_done;
e23eba97
NC		 1990 case 'K':
1991 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1992 || imm_expr->X_op != O_constant
169ec512
AM		 1993 || imm_expr->X_add_number == 0
1994 || !VALID_RVC_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 1995 break;
1996 ip->insn_opcode |=
1997 ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
1998 goto rvc_imm_done;
1999 case 'L':
2000 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2001 || imm_expr->X_op != O_constant
169ec512
AM		 2002 || imm_expr->X_add_number == 0
2003 || !VALID_RVC_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2004 break;
2005 ip->insn_opcode |=
2006 ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
2007 goto rvc_imm_done;
2008 case 'M':
f0531ed6
JW		 2009 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2010 continue;
e23eba97
NC		 2011 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2012 || imm_expr->X_op != O_constant
169ec512 2013 || !VALID_RVC_SWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2014 break;
2015 ip->insn_opcode |=
2016 ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
2017 goto rvc_imm_done;
2018 case 'N':
f0531ed6
JW		 2019 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2020 continue;
e23eba97
NC		 2021 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2022 || imm_expr->X_op != O_constant
169ec512 2023 || !VALID_RVC_SDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2024 break;
2025 ip->insn_opcode |=
2026 ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
2027 goto rvc_imm_done;
2028 case 'u':
2029 p = percent_op_utype;
2030 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
2031 break;
dc1e8a47 2032 rvc_lui:
e23eba97
NC		 2033 if (imm_expr->X_op != O_constant
2034 || imm_expr->X_add_number <= 0
2035 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
2036 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
2037 && (imm_expr->X_add_number <
2038 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
2039 break;
2040 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2041 goto rvc_imm_done;
2042 case 'v':
2043 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2044 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
2045 || ((int32_t)imm_expr->X_add_number
2046 != imm_expr->X_add_number))
2047 break;
2048 imm_expr->X_add_number =
2049 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
2050 goto rvc_lui;
2051 case 'p':
2052 goto branch;
2053 case 'a':
2054 goto jump;
0e35537d
JW		 2055 case 'S': /* Floating-point RS1 x8-x15. */
2056 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2057 || !(regno >= 8 && regno <= 15))
2058 break;
2059 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2060 continue;
e23eba97
NC		 2061 case 'D': /* Floating-point RS2 x8-x15. */
2062 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2063 || !(regno >= 8 && regno <= 15))
2064 break;
2065 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2066 continue;
2067 case 'T': /* Floating-point RS2. */
2068 if (!reg_lookup (&s, RCLASS_FPR, &regno))
2069 break;
2070 INSERT_OPERAND (CRS2, *ip, regno);
2071 continue;
0e35537d
JW		 2072 case 'F':
2073 switch (*++args)
2074 {
4765cd61
JW		 2075 case '6':
2076 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2077 || imm_expr->X_op != O_constant
2078 || imm_expr->X_add_number < 0
2079 || imm_expr->X_add_number >= 64)
2080 {
2081 as_bad (_("bad value for funct6 field, "
2082 "value must be 0...64"));
2083 break;
2084 }
2085
2086 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
2087 imm_expr->X_op = O_absent;
2088 s = expr_end;
2089 continue;
0e35537d
JW		 2090 case '4':
2091 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2092 || imm_expr->X_op != O_constant
2093 || imm_expr->X_add_number < 0
2094 || imm_expr->X_add_number >= 16)
2095 {
2096 as_bad (_("bad value for funct4 field, "
2097 "value must be 0...15"));
2098 break;
2099 }
2100
2101 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
2102 imm_expr->X_op = O_absent;
2103 s = expr_end;
2104 continue;
2105 case '3':
2106 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2107 || imm_expr->X_op != O_constant
2108 || imm_expr->X_add_number < 0
2109 || imm_expr->X_add_number >= 8)
2110 {
2111 as_bad (_("bad value for funct3 field, "
2112 "value must be 0...7"));
2113 break;
2114 }
2115 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
2116 imm_expr->X_op = O_absent;
2117 s = expr_end;
2118 continue;
4765cd61
JW		 2119 case '2':
2120 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2121 || imm_expr->X_op != O_constant
2122 || imm_expr->X_add_number < 0
2123 || imm_expr->X_add_number >= 4)
2124 {
2125 as_bad (_("bad value for funct2 field, "
2126 "value must be 0...3"));
2127 break;
2128 }
2129 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number);
2130 imm_expr->X_op = O_absent;
2131 s = expr_end;
2132 continue;
0e35537d
JW		 2133 default:
2134 as_bad (_("bad compressed FUNCT field"
2135 " specifier 'CF%c'\n"),
2136 *args);
2137 }
2138 break;
2139
e23eba97
NC		 2140 default:
2141 as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
2142 }
2143 break;
2144
2145 case ',':
2146 ++argnum;
2147 if (*s++ == *args)
2148 continue;
2149 s--;
2150 break;
2151
2152 case '(':
2153 case ')':
2154 case '[':
2155 case ']':
2156 if (*s++ == *args)
2157 continue;
2158 break;
2159
2160 case '<': /* Shift amount, 0 - 31. */
2161 my_getExpression (imm_expr, s);
ca2fd32c 2162 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2163 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2164 as_bad (_("Improper shift amount (%lu)"),
2165 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2166 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
2167 imm_expr->X_op = O_absent;
2168 s = expr_end;
2169 continue;
2170
2171 case '>': /* Shift amount, 0 - (XLEN-1). */
2172 my_getExpression (imm_expr, s);
ca2fd32c 2173 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2174 if ((unsigned long) imm_expr->X_add_number >= xlen)
94f78a77
AW		 2175 as_bad (_("Improper shift amount (%lu)"),
2176 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2177 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
2178 imm_expr->X_op = O_absent;
2179 s = expr_end;
2180 continue;
2181
2182 case 'Z': /* CSRRxI immediate. */
2183 my_getExpression (imm_expr, s);
ca2fd32c 2184 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2185 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2186 as_bad (_("Improper CSRxI immediate (%lu)"),
2187 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2188 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
2189 imm_expr->X_op = O_absent;
2190 s = expr_end;
2191 continue;
2192
2193 case 'E': /* Control register. */
54b2aec1 2194 insn_with_csr = TRUE;
1a79004f 2195 explicit_priv_attr = TRUE;
e23eba97
NC		 2196 if (reg_lookup (&s, RCLASS_CSR, &regno))
2197 INSERT_OPERAND (CSR, *ip, regno);
2198 else
2199 {
2200 my_getExpression (imm_expr, s);
ca2fd32c 2201 check_absolute_expr (ip, imm_expr, TRUE);
e23eba97 2202 if ((unsigned long) imm_expr->X_add_number > 0xfff)
94f78a77
AW		 2203 as_bad (_("Improper CSR address (%lu)"),
2204 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2205 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
2206 imm_expr->X_op = O_absent;
2207 s = expr_end;
2208 }
2209 continue;
2210
2211 case 'm': /* Rounding mode. */
2212 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
2213 {
2214 INSERT_OPERAND (RM, *ip, regno);
2215 continue;
2216 }
2217 break;
2218
2219 case 'P':
2220 case 'Q': /* Fence predecessor/successor. */
2221 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
2222 &regno))
2223 {
2224 if (*args == 'P')
2225 INSERT_OPERAND (PRED, *ip, regno);
2226 else
2227 INSERT_OPERAND (SUCC, *ip, regno);
2228 continue;
2229 }
2230 break;
2231
2232 case 'd': /* Destination register. */
2233 case 's': /* Source register. */
2234 case 't': /* Target register. */
0e35537d 2235 case 'r': /* rs3. */
e23eba97
NC		 2236 if (reg_lookup (&s, RCLASS_GPR, &regno))
2237 {
2238 c = *args;
2239 if (*s == ' ')
2240 ++s;
2241
2242 /* Now that we have assembled one operand, we use the args
2243 string to figure out where it goes in the instruction. */
2244 switch (c)
2245 {
2246 case 's':
2247 INSERT_OPERAND (RS1, *ip, regno);
2248 break;
2249 case 'd':
2250 INSERT_OPERAND (RD, *ip, regno);
2251 break;
2252 case 't':
2253 INSERT_OPERAND (RS2, *ip, regno);
2254 break;
0e35537d
JW		 2255 case 'r':
2256 INSERT_OPERAND (RS3, *ip, regno);
2257 break;
e23eba97
NC		 2258 }
2259 continue;
2260 }
2261 break;
2262
2263 case 'D': /* Floating point rd. */
2264 case 'S': /* Floating point rs1. */
2265 case 'T': /* Floating point rs2. */
2266 case 'U': /* Floating point rs1 and rs2. */
2267 case 'R': /* Floating point rs3. */
2268 if (reg_lookup (&s, RCLASS_FPR, &regno))
2269 {
2270 c = *args;
2271 if (*s == ' ')
2272 ++s;
2273 switch (c)
2274 {
2275 case 'D':
2276 INSERT_OPERAND (RD, *ip, regno);
2277 break;
2278 case 'S':
2279 INSERT_OPERAND (RS1, *ip, regno);
2280 break;
2281 case 'U':
2282 INSERT_OPERAND (RS1, *ip, regno);
2283 /* fallthru */
2284 case 'T':
2285 INSERT_OPERAND (RS2, *ip, regno);
2286 break;
2287 case 'R':
2288 INSERT_OPERAND (RS3, *ip, regno);
2289 break;
2290 }
2291 continue;
2292 }
2293
2294 break;
2295
2296 case 'I':
2297 my_getExpression (imm_expr, s);
2298 if (imm_expr->X_op != O_big
2299 && imm_expr->X_op != O_constant)
2300 break;
2301 normalize_constant_expr (imm_expr);
2302 s = expr_end;
2303 continue;
2304
2305 case 'A':
2306 my_getExpression (imm_expr, s);
2307 normalize_constant_expr (imm_expr);
2308 /* The 'A' format specifier must be a symbol. */
2309 if (imm_expr->X_op != O_symbol)
2310 break;
2311 *imm_reloc = BFD_RELOC_32;
2312 s = expr_end;
2313 continue;
2314
160d1b3d
SH		 2315 case 'B':
2316 my_getExpression (imm_expr, s);
2317 normalize_constant_expr (imm_expr);
2318 /* The 'B' format specifier must be a symbol or a constant. */
2319 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
2320 break;
2321 if (imm_expr->X_op == O_symbol)
2322 *imm_reloc = BFD_RELOC_32;
2323 s = expr_end;
2324 continue;
2325
e23eba97 2326 case 'j': /* Sign-extended immediate. */
e23eba97 2327 p = percent_op_itype;
f50fabe4 2328 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
e23eba97
NC		 2329 goto alu_op;
2330 case 'q': /* Store displacement. */
2331 p = percent_op_stype;
2332 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
2333 goto load_store;
2334 case 'o': /* Load displacement. */
2335 p = percent_op_itype;
2336 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
2337 goto load_store;
f50fabe4 2338 case '1': /* 4-operand add, must be %tprel_add. */
e23eba97 2339 p = percent_op_rtype;
f50fabe4
JW		 2340 goto alu_op;
2341 case '0': /* AMO "displacement," which must be zero. */
2342 p = percent_op_null;
dc1e8a47 2343 load_store:
f0531ed6 2344 if (riscv_handle_implicit_zero_offset (imm_expr, s))
e23eba97 2345 continue;
dc1e8a47 2346 alu_op:
e23eba97
NC		 2347 /* If this value won't fit into a 16 bit offset, then go
2348 find a macro that will generate the 32 bit offset
2349 code pattern. */
2350 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
2351 {
2352 normalize_constant_expr (imm_expr);
2353 if (imm_expr->X_op != O_constant
2354 || (*args == '0' && imm_expr->X_add_number != 0)
f50fabe4 2355 || (*args == '1')
e23eba97
NC		 2356 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
2357 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
2358 break;
2359 }
2360
2361 s = expr_end;
2362 continue;
2363
2364 case 'p': /* PC-relative offset. */
dc1e8a47 2365 branch:
e23eba97
NC		 2366 *imm_reloc = BFD_RELOC_12_PCREL;
2367 my_getExpression (imm_expr, s);
2368 s = expr_end;
2369 continue;
2370
2371 case 'u': /* Upper 20 bits. */
2372 p = percent_op_utype;
4288405d 2373 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
e23eba97 2374 {
4288405d
JW		 2375 if (imm_expr->X_op != O_constant)
2376 break;
2377
e23eba97
NC		 2378 if (imm_expr->X_add_number < 0
2379 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
2380 as_bad (_("lui expression not in range 0..1048575"));
2381
2382 *imm_reloc = BFD_RELOC_RISCV_HI20;
2383 imm_expr->X_add_number <<= RISCV_IMM_BITS;
2384 }
2385 s = expr_end;
2386 continue;
2387
2388 case 'a': /* 20-bit PC-relative offset. */
dc1e8a47 2389 jump:
e23eba97
NC		 2390 my_getExpression (imm_expr, s);
2391 s = expr_end;
2392 *imm_reloc = BFD_RELOC_RISCV_JMP;
2393 continue;
2394
2395 case 'c':
2396 my_getExpression (imm_expr, s);
2397 s = expr_end;
2398 if (strcmp (s, "@plt") == 0)
2399 {
2400 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2401 s += 4;
2402 }
2403 else
2404 *imm_reloc = BFD_RELOC_RISCV_CALL;
2405 continue;
0e35537d
JW		 2406 case 'O':
2407 switch (*++args)
2408 {
2409 case '4':
2410 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2411 || imm_expr->X_op != O_constant
2412 || imm_expr->X_add_number < 0
2413 || imm_expr->X_add_number >= 128
2414 || (imm_expr->X_add_number & 0x3) != 3)
2415 {
2416 as_bad (_("bad value for opcode field, "
2417 "value must be 0...127 and "
2418 "lower 2 bits must be 0x3"));
2419 break;
2420 }
2421
2422 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2423 imm_expr->X_op = O_absent;
2424 s = expr_end;
2425 continue;
2426 case '2':
2427 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2428 || imm_expr->X_op != O_constant
2429 || imm_expr->X_add_number < 0
2430 || imm_expr->X_add_number >= 3)
2431 {
2432 as_bad (_("bad value for opcode field, "
2433 "value must be 0...2"));
2434 break;
2435 }
2436
2437 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2438 imm_expr->X_op = O_absent;
2439 s = expr_end;
2440 continue;
2441 default:
2442 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args);
2443 }
2444 break;
2445
2446 case 'F':
2447 switch (*++args)
2448 {
2449 case '7':
2450 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2451 || imm_expr->X_op != O_constant
2452 || imm_expr->X_add_number < 0
2453 || imm_expr->X_add_number >= 128)
2454 {
2455 as_bad (_("bad value for funct7 field, "
2456 "value must be 0...127"));
2457 break;
2458 }
2459
2460 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2461 imm_expr->X_op = O_absent;
2462 s = expr_end;
2463 continue;
2464 case '3':
2465 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2466 || imm_expr->X_op != O_constant
2467 || imm_expr->X_add_number < 0
2468 || imm_expr->X_add_number >= 8)
2469 {
2470 as_bad (_("bad value for funct3 field, "
2471 "value must be 0...7"));
2472 break;
2473 }
2474
2475 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2476 imm_expr->X_op = O_absent;
2477 s = expr_end;
2478 continue;
2479 case '2':
2480 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2481 || imm_expr->X_op != O_constant
2482 || imm_expr->X_add_number < 0
2483 || imm_expr->X_add_number >= 4)
2484 {
2485 as_bad (_("bad value for funct2 field, "
2486 "value must be 0...3"));
2487 break;
2488 }
2489
2490 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2491 imm_expr->X_op = O_absent;
2492 s = expr_end;
2493 continue;
2494
2495 default:
2496 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args);
2497 }
2498 break;
e23eba97 2499
e925c834
JW		 2500 case 'z':
2501 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2502 || imm_expr->X_op != O_constant
2503 || imm_expr->X_add_number != 0)
2504 break;
2505 s = expr_end;
2506 imm_expr->X_op = O_absent;
2507 continue;
2508
e23eba97
NC		 2509 default:
2510 as_fatal (_("internal error: bad argument type %c"), *args);
2511 }
2512 break;
2513 }
2514 s = argsStart;
2515 error = _("illegal operands");
54b2aec1 2516 insn_with_csr = FALSE;
e23eba97
NC		 2517 }
2518
dc1e8a47 2519 out:
e23eba97
NC		 2520 /* Restore the character we might have clobbered above. */
2521 if (save_c)
2522 *(argsStart - 1) = save_c;
2523
2524 return error;
2525}
2526
2527void
2528md_assemble (char *str)
2529{
2530 struct riscv_cl_insn insn;
2531 expressionS imm_expr;
2532 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2533
8f595e9b
NC		 2534 /* The arch and priv attributes should be set before assembling. */
2535 if (!start_assemble)
2536 {
2537 start_assemble = TRUE;
e23eba97 2538
8f595e9b
NC		 2539 /* Set the default_priv_spec according to the priv attributes. */
2540 if (!riscv_set_default_priv_spec (NULL))
2541 return;
2542 }
2543
2544 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
2dc8dd17 2545
e23eba97
NC		 2546 if (error)
2547 {
2548 as_bad ("%s `%s'", error, str);
2549 return;
2550 }
2551
2552 if (insn.insn_mo->pinfo == INSN_MACRO)
2553 macro (&insn, &imm_expr, &imm_reloc);
2554 else
2555 append_insn (&insn, &imm_expr, imm_reloc);
2556}
2557
2558const char *
2559md_atof (int type, char *litP, int *sizeP)
2560{
2561 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2562}
2563
2564void
2565md_number_to_chars (char *buf, valueT val, int n)
2566{
2567 number_to_chars_littleendian (buf, val, n);
2568}
2569
2570const char *md_shortopts = "O::g::G:";
2571
2572enum options
2573{
2922d21d 2574 OPTION_MARCH = OPTION_MD_BASE,
e23eba97
NC		 2575 OPTION_PIC,
2576 OPTION_NO_PIC,
2922d21d 2577 OPTION_MABI,
71060565
JW		 2578 OPTION_RELAX,
2579 OPTION_NO_RELAX,
2dc8dd17
JW		 2580 OPTION_ARCH_ATTR,
2581 OPTION_NO_ARCH_ATTR,
2ca89224
NC		 2582 OPTION_CSR_CHECK,
2583 OPTION_NO_CSR_CHECK,
8f595e9b
NC		 2584 OPTION_MISA_SPEC,
2585 OPTION_MPRIV_SPEC,
e23eba97
NC		 2586 OPTION_END_OF_ENUM
2587};
2588
2589struct option md_longopts[] =
2590{
e23eba97
NC		 2591 {"march", required_argument, NULL, OPTION_MARCH},
2592 {"fPIC", no_argument, NULL, OPTION_PIC},
2593 {"fpic", no_argument, NULL, OPTION_PIC},
2594 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2922d21d 2595 {"mabi", required_argument, NULL, OPTION_MABI},
71060565
JW		 2596 {"mrelax", no_argument, NULL, OPTION_RELAX},
2597 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2dc8dd17
JW		 2598 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
2599 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
2ca89224
NC		 2600 {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
2601 {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
8f595e9b
NC		 2602 {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
2603 {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
e23eba97
NC		 2604
2605 {NULL, no_argument, NULL, 0}
2606};
2607size_t md_longopts_size = sizeof (md_longopts);
2608
2922d21d
AW		 2609enum float_abi {
2610 FLOAT_ABI_DEFAULT = -1,
2611 FLOAT_ABI_SOFT,
2612 FLOAT_ABI_SINGLE,
2613 FLOAT_ABI_DOUBLE,
2614 FLOAT_ABI_QUAD
e23eba97 2615};
2922d21d
AW		 2616static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
2617
2618static void
7f999549 2619riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
2922d21d
AW		 2620{
2621 abi_xlen = new_xlen;
2622 float_abi = new_float_abi;
7f999549 2623 rve_abi = rve;
2922d21d 2624}
e23eba97
NC		 2625
2626int
2627md_parse_option (int c, const char *arg)
2628{
2629 switch (c)
2630 {
e23eba97 2631 case OPTION_MARCH:
8f595e9b
NC		 2632 /* riscv_after_parse_args will call riscv_set_arch to parse
2633 the architecture. */
2634 default_arch_with_ext = arg;
e23eba97
NC		 2635 break;
2636
2637 case OPTION_NO_PIC:
2638 riscv_opts.pic = FALSE;
2639 break;
2640
2641 case OPTION_PIC:
2642 riscv_opts.pic = TRUE;
2643 break;
2644
2922d21d
AW		 2645 case OPTION_MABI:
2646 if (strcmp (arg, "ilp32") == 0)
7f999549
JW		 2647 riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
2648 else if (strcmp (arg, "ilp32e") == 0)
2649 riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
2922d21d 2650 else if (strcmp (arg, "ilp32f") == 0)
7f999549 2651 riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2652 else if (strcmp (arg, "ilp32d") == 0)
7f999549 2653 riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2654 else if (strcmp (arg, "ilp32q") == 0)
7f999549 2655 riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
2922d21d 2656 else if (strcmp (arg, "lp64") == 0)
7f999549 2657 riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
2922d21d 2658 else if (strcmp (arg, "lp64f") == 0)
7f999549 2659 riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2660 else if (strcmp (arg, "lp64d") == 0)
7f999549 2661 riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2662 else if (strcmp (arg, "lp64q") == 0)
7f999549 2663 riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
2922d21d
AW		 2664 else
2665 return 0;
2666 break;
2667
71060565
JW		 2668 case OPTION_RELAX:
2669 riscv_opts.relax = TRUE;
2670 break;
2671
2672 case OPTION_NO_RELAX:
2673 riscv_opts.relax = FALSE;
2674 break;
2675
2dc8dd17
JW		 2676 case OPTION_ARCH_ATTR:
2677 riscv_opts.arch_attr = TRUE;
2678 break;
2679
2680 case OPTION_NO_ARCH_ATTR:
2681 riscv_opts.arch_attr = FALSE;
2682 break;
2683
2ca89224
NC		 2684 case OPTION_CSR_CHECK:
2685 riscv_opts.csr_check = TRUE;
2686 break;
2687
2688 case OPTION_NO_CSR_CHECK:
2689 riscv_opts.csr_check = FALSE;
2690 break;
2691
8f595e9b
NC		 2692 case OPTION_MISA_SPEC:
2693 return riscv_set_default_isa_spec (arg);
2694
2695 case OPTION_MPRIV_SPEC:
2696 return riscv_set_default_priv_spec (arg);
2697
e23eba97
NC		 2698 default:
2699 return 0;
2700 }
2701
2702 return 1;
2703}
2704
2705void
2706riscv_after_parse_args (void)
2707{
8f595e9b
NC		 2708 /* The --with-arch is optional for now, so we have to set the xlen
2709 according to the default_arch, which is set by the --targte, first.
2710 Then, we use the xlen to set the default_arch_with_ext if the
2711 -march and --with-arch are not set. */
e23eba97
NC		 2712 if (xlen == 0)
2713 {
2714 if (strcmp (default_arch, "riscv32") == 0)
2715 xlen = 32;
2716 else if (strcmp (default_arch, "riscv64") == 0)
2717 xlen = 64;
2718 else
2719 as_bad ("unknown default architecture `%s'", default_arch);
2720 }
8f595e9b
NC		 2721 if (default_arch_with_ext == NULL)
2722 default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
2723
2724 /* Initialize the hash table for extensions with default version. */
2725 ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
2726
2727 /* If the -misa-spec isn't set, then we set the default ISA spec according
2728 to DEFAULT_RISCV_ISA_SPEC. */
2729 if (default_isa_spec == ISA_SPEC_CLASS_NONE)
2730 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
2922d21d 2731
8f595e9b
NC		 2732 /* Set the architecture according to -march or or --with-arch. */
2733 riscv_set_arch (default_arch_with_ext);
2922d21d
AW		 2734
2735 /* Add the RVC extension, regardless of -march, to support .option rvc. */
fecb9c46 2736 riscv_set_rvc (FALSE);
1080bf78 2737 if (riscv_subset_supports ("c"))
2922d21d 2738 riscv_set_rvc (TRUE);
2922d21d 2739
7f999549
JW		 2740 /* Enable RVE if specified by the -march option. */
2741 riscv_set_rve (FALSE);
1080bf78 2742 if (riscv_subset_supports ("e"))
7f999549
JW		 2743 riscv_set_rve (TRUE);
2744
8f595e9b
NC		 2745 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2746 according to DEFAULT_PRIV_SPEC. */
2747 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
2748 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
2749
2922d21d
AW		 2750 /* Infer ABI from ISA if not specified on command line. */
2751 if (abi_xlen == 0)
2752 abi_xlen = xlen;
2753 else if (abi_xlen > xlen)
2754 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
2755 else if (abi_xlen < xlen)
2756 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
2757
2758 if (float_abi == FLOAT_ABI_DEFAULT)
2759 {
1080bf78 2760 riscv_subset_t *subset;
2922d21d
AW		 2761
2762 /* Assume soft-float unless D extension is present. */
2763 float_abi = FLOAT_ABI_SOFT;
2764
1080bf78 2765 for (subset = riscv_subsets.head; subset != NULL; subset = subset->next)
cc917fd9
KC		 2766 {
2767 if (strcasecmp (subset->name, "D") == 0)
2768 float_abi = FLOAT_ABI_DOUBLE;
2769 if (strcasecmp (subset->name, "Q") == 0)
2770 float_abi = FLOAT_ABI_QUAD;
2771 }
2922d21d
AW		 2772 }
2773
7f999549
JW		 2774 if (rve_abi)
2775 elf_flags |= EF_RISCV_RVE;
2776
2922d21d
AW		 2777 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2778 elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1));
0ac2b354
AB		 2779
2780 /* If the CIE to be produced has not been overridden on the command line,
2781 then produce version 3 by default. This allows us to use the full
2782 range of registers in a .cfi_return_column directive. */
2783 if (flag_dwarf_cie_version == -1)
2784 flag_dwarf_cie_version = 3;
e23eba97
NC		 2785}
2786
2787long
2788md_pcrel_from (fixS *fixP)
2789{
2790 return fixP->fx_where + fixP->fx_frag->fr_address;
2791}
2792
2793/* Apply a fixup to the object file. */
2794
2795void
2796md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2797{
45f76423 2798 unsigned int subtype;
e23eba97 2799 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
45f76423 2800 bfd_boolean relaxable = FALSE;
c1b465c9 2801 offsetT loc;
a6cbf936 2802 segT sub_segment;
e23eba97
NC		 2803
2804 /* Remember value for tc_gen_reloc. */
2805 fixP->fx_addnumber = *valP;
2806
2807 switch (fixP->fx_r_type)
2808 {
e23eba97
NC		 2809 case BFD_RELOC_RISCV_HI20:
2810 case BFD_RELOC_RISCV_LO12_I:
2811 case BFD_RELOC_RISCV_LO12_S:
45f76423
AW		 2812 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2813 | bfd_getl32 (buf), buf);
a5ec5e3f
AW		 2814 if (fixP->fx_addsy == NULL)
2815 fixP->fx_done = TRUE;
45f76423
AW		 2816 relaxable = TRUE;
2817 break;
2818
2819 case BFD_RELOC_RISCV_GOT_HI20:
e23eba97
NC		 2820 case BFD_RELOC_RISCV_ADD8:
2821 case BFD_RELOC_RISCV_ADD16:
2822 case BFD_RELOC_RISCV_ADD32:
2823 case BFD_RELOC_RISCV_ADD64:
45f76423 2824 case BFD_RELOC_RISCV_SUB6:
e23eba97
NC		 2825 case BFD_RELOC_RISCV_SUB8:
2826 case BFD_RELOC_RISCV_SUB16:
2827 case BFD_RELOC_RISCV_SUB32:
2828 case BFD_RELOC_RISCV_SUB64:
45f76423
AW		 2829 case BFD_RELOC_RISCV_RELAX:
2830 break;
2831
2832 case BFD_RELOC_RISCV_TPREL_HI20:
2833 case BFD_RELOC_RISCV_TPREL_LO12_I:
2834 case BFD_RELOC_RISCV_TPREL_LO12_S:
2835 case BFD_RELOC_RISCV_TPREL_ADD:
2836 relaxable = TRUE;
2837 /* Fall through. */
2838
2839 case BFD_RELOC_RISCV_TLS_GOT_HI20:
2840 case BFD_RELOC_RISCV_TLS_GD_HI20:
2841 case BFD_RELOC_RISCV_TLS_DTPREL32:
2842 case BFD_RELOC_RISCV_TLS_DTPREL64:
e294484e
AW		 2843 if (fixP->fx_addsy != NULL)
2844 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2845 else
2846 as_bad_where (fixP->fx_file, fixP->fx_line,
2847 _("TLS relocation against a constant"));
e23eba97
NC		 2848 break;
2849
e23eba97 2850 case BFD_RELOC_32:
a6cbf936
KLC		 2851 /* Use pc-relative relocation for FDE initial location.
2852 The symbol address in .eh_frame may be adjusted in
2853 _bfd_elf_discard_section_eh_frame, and the content of
2854 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2855 Therefore, we cannot insert a relocation whose addend symbol is
2856 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2857 if (fixP->fx_addsy && fixP->fx_subsy
2858 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
2859 && strcmp (sub_segment->name, ".eh_frame") == 0
2860 && S_GET_VALUE (fixP->fx_subsy)
2861 == fixP->fx_frag->fr_address + fixP->fx_where)
2862 {
2863 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
2864 fixP->fx_subsy = NULL;
2865 break;
2866 }
2867 /* Fall through. */
2868 case BFD_RELOC_64:
e23eba97
NC		 2869 case BFD_RELOC_16:
2870 case BFD_RELOC_8:
45f76423 2871 case BFD_RELOC_RISCV_CFA:
e23eba97
NC		 2872 if (fixP->fx_addsy && fixP->fx_subsy)
2873 {
2874 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2875 fixP->fx_next->fx_addsy = fixP->fx_subsy;
2876 fixP->fx_next->fx_subsy = NULL;
2877 fixP->fx_next->fx_offset = 0;
2878 fixP->fx_subsy = NULL;
2879
2880 switch (fixP->fx_r_type)
2881 {
2882 case BFD_RELOC_64:
2883 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
2884 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
2885 break;
2886
2887 case BFD_RELOC_32:
2888 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
2889 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2890 break;
2891
2892 case BFD_RELOC_16:
2893 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
2894 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2895 break;
2896
2897 case BFD_RELOC_8:
2898 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
2899 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
073808ed 2900 break;
e23eba97 2901
45f76423
AW		 2902 case BFD_RELOC_RISCV_CFA:
2903 /* Load the byte to get the subtype. */
c1b465c9
KLC		 2904 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
2905 loc = fixP->fx_frag->fr_fix - (subtype & 7);
45f76423
AW		 2906 switch (subtype)
2907 {
2908 case DW_CFA_advance_loc1:
c1b465c9
KLC		 2909 fixP->fx_where = loc + 1;
2910 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2911 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
2912 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
2913 break;
2914
2915 case DW_CFA_advance_loc2:
2916 fixP->fx_size = 2;
45f76423 2917 fixP->fx_next->fx_size = 2;
c1b465c9
KLC		 2918 fixP->fx_where = loc + 1;
2919 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2920 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
2921 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2922 break;
2923
2924 case DW_CFA_advance_loc4:
2925 fixP->fx_size = 4;
45f76423 2926 fixP->fx_next->fx_size = 4;
c1b465c9
KLC		 2927 fixP->fx_where = loc;
2928 fixP->fx_next->fx_where = loc;
45f76423
AW		 2929 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
2930 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2931 break;
2932
2933 default:
2934 if (subtype < 0x80 && (subtype & 0x40))
2935 {
2936 /* DW_CFA_advance_loc */
2aece2ba
KLC		 2937 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
2938 fixP->fx_next->fx_frag = fixP->fx_frag;
45f76423
AW		 2939 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
2940 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
2941 }
2942 else
2943 as_fatal (_("internal error: bad CFA value #%d"), subtype);
2944 break;
2945 }
2946 break;
2947
e23eba97
NC		 2948 default:
2949 /* This case is unreachable. */
2950 abort ();
2951 }
2952 }
2953 /* Fall through. */
2954
2955 case BFD_RELOC_RVA:
2956 /* If we are deleting this reloc entry, we must fill in the
2957 value now. This can happen if we have a .word which is not
2958 resolved when it appears but is later defined. */
2959 if (fixP->fx_addsy == NULL)
2960 {
2961 gas_assert (fixP->fx_size <= sizeof (valueT));
2962 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
2963 fixP->fx_done = 1;
2964 }
2965 break;
2966
2967 case BFD_RELOC_RISCV_JMP:
2968 if (fixP->fx_addsy)
2969 {
2970 /* Fill in a tentative value to improve objdump readability. */
2971 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2972 bfd_vma delta = target - md_pcrel_from (fixP);
2973 bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
2974 }
2975 break;
2976
2977 case BFD_RELOC_12_PCREL:
2978 if (fixP->fx_addsy)
2979 {
2980 /* Fill in a tentative value to improve objdump readability. */
2981 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2982 bfd_vma delta = target - md_pcrel_from (fixP);
2983 bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
2984 }
2985 break;
2986
2987 case BFD_RELOC_RISCV_RVC_BRANCH:
2988 if (fixP->fx_addsy)
2989 {
2990 /* Fill in a tentative value to improve objdump readability. */
2991 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2992 bfd_vma delta = target - md_pcrel_from (fixP);
2993 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
2994 }
2995 break;
2996
2997 case BFD_RELOC_RISCV_RVC_JUMP:
2998 if (fixP->fx_addsy)
2999 {
3000 /* Fill in a tentative value to improve objdump readability. */
3001 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3002 bfd_vma delta = target - md_pcrel_from (fixP);
3003 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
3004 }
3005 break;
3006
e23eba97
NC		 3007 case BFD_RELOC_RISCV_CALL:
3008 case BFD_RELOC_RISCV_CALL_PLT:
45f76423
AW		 3009 relaxable = TRUE;
3010 break;
3011
9d06997a 3012 case BFD_RELOC_RISCV_PCREL_HI20:
45f76423
AW		 3013 case BFD_RELOC_RISCV_PCREL_LO12_S:
3014 case BFD_RELOC_RISCV_PCREL_LO12_I:
9d06997a
PD		 3015 relaxable = riscv_opts.relax;
3016 break;
3017
e23eba97
NC		 3018 case BFD_RELOC_RISCV_ALIGN:
3019 break;
3020
3021 default:
3022 /* We ignore generic BFD relocations we don't know about. */
3023 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
3024 as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type);
3025 }
45f76423 3026
e294484e
AW		 3027 if (fixP->fx_subsy != NULL)
3028 as_bad_where (fixP->fx_file, fixP->fx_line,
3029 _("unsupported symbol subtraction"));
3030
45f76423
AW		 3031 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3032 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
3033 {
3034 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3035 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
3036 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
b1b11e92 3037 fixP->fx_next->fx_size = 0;
45f76423
AW		 3038 }
3039}
3040
3041/* Because the value of .cfi_remember_state may changed after relaxation,
3042 we insert a fix to relocate it again in link-time. */
3043
3044void
3045riscv_pre_output_hook (void)
3046{
3047 const frchainS *frch;
72393fd1
JW		 3048 segT s;
3049
3050 /* Save the current segment info. */
3051 segT seg = now_seg;
3052 subsegT subseg = now_subseg;
45f76423
AW		 3053
3054 for (s = stdoutput->sections; s; s = s->next)
3055 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
3056 {
7cb7b948 3057 fragS *frag;
45f76423
AW		 3058
3059 for (frag = frch->frch_root; frag; frag = frag->fr_next)
3060 {
3061 if (frag->fr_type == rs_cfa)
3062 {
45f76423 3063 expressionS exp;
8d1015a8 3064 expressionS *symval;
45f76423 3065
8d1015a8 3066 symval = symbol_get_value_expression (frag->fr_symbol);
45f76423 3067 exp.X_op = O_subtract;
8d1015a8 3068 exp.X_add_symbol = symval->X_add_symbol;
45f76423 3069 exp.X_add_number = 0;
8d1015a8 3070 exp.X_op_symbol = symval->X_op_symbol;
45f76423 3071
72393fd1
JW		 3072 /* We must set the segment before creating a frag after all
3073 frag chains have been chained together. */
3074 subseg_set (s, frch->frch_subseg);
3075
c1b465c9 3076 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
45f76423
AW		 3077 BFD_RELOC_RISCV_CFA);
3078 }
3079 }
3080 }
72393fd1
JW		 3081
3082 /* Restore the original segment info. */
3083 subseg_set (seg, subseg);
e23eba97
NC		 3084}
3085
45f76423 3086
e23eba97
NC		 3087/* This structure is used to hold a stack of .option values. */
3088
3089struct riscv_option_stack
3090{
3091 struct riscv_option_stack *next;
3092 struct riscv_set_options options;
3093};
3094
3095static struct riscv_option_stack *riscv_opts_stack;
3096
3097/* Handle the .option pseudo-op. */
3098
3099static void
3100s_riscv_option (int x ATTRIBUTE_UNUSED)
3101{
3102 char *name = input_line_pointer, ch;
3103
3104 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3105 ++input_line_pointer;
3106 ch = *input_line_pointer;
3107 *input_line_pointer = '\0';
3108
3109 if (strcmp (name, "rvc") == 0)
3110 riscv_set_rvc (TRUE);
3111 else if (strcmp (name, "norvc") == 0)
3112 riscv_set_rvc (FALSE);
3113 else if (strcmp (name, "pic") == 0)
3114 riscv_opts.pic = TRUE;
3115 else if (strcmp (name, "nopic") == 0)
3116 riscv_opts.pic = FALSE;
45f76423
AW		 3117 else if (strcmp (name, "relax") == 0)
3118 riscv_opts.relax = TRUE;
3119 else if (strcmp (name, "norelax") == 0)
3120 riscv_opts.relax = FALSE;
2ca89224
NC		 3121 else if (strcmp (name, "csr-check") == 0)
3122 riscv_opts.csr_check = TRUE;
3123 else if (strcmp (name, "no-csr-check") == 0)
3124 riscv_opts.csr_check = FALSE;
e23eba97
NC		 3125 else if (strcmp (name, "push") == 0)
3126 {
3127 struct riscv_option_stack *s;
3128
3129 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
3130 s->next = riscv_opts_stack;
3131 s->options = riscv_opts;
3132 riscv_opts_stack = s;
3133 }
3134 else if (strcmp (name, "pop") == 0)
3135 {
3136 struct riscv_option_stack *s;
3137
3138 s = riscv_opts_stack;
3139 if (s == NULL)
3140 as_bad (_(".option pop with no .option push"));
3141 else
3142 {
3143 riscv_opts = s->options;
3144 riscv_opts_stack = s->next;
3145 free (s);
3146 }
3147 }
3148 else
3149 {
3150 as_warn (_("Unrecognized .option directive: %s\n"), name);
3151 }
3152 *input_line_pointer = ch;
3153 demand_empty_rest_of_line ();
3154}
3155
3156/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3157 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3158 use in DWARF debug information. */
3159
3160static void
3161s_dtprel (int bytes)
3162{
3163 expressionS ex;
3164 char *p;
3165
3166 expression (&ex);
3167
3168 if (ex.X_op != O_symbol)
3169 {
3170 as_bad (_("Unsupported use of %s"), (bytes == 8
3171 ? ".dtpreldword"
3172 : ".dtprelword"));
3173 ignore_rest_of_line ();
3174 }
3175
3176 p = frag_more (bytes);
3177 md_number_to_chars (p, 0, bytes);
3178 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
3179 (bytes == 8
3180 ? BFD_RELOC_RISCV_TLS_DTPREL64
3181 : BFD_RELOC_RISCV_TLS_DTPREL32));
3182
3183 demand_empty_rest_of_line ();
3184}
3185
3186/* Handle the .bss pseudo-op. */
3187
3188static void
3189s_bss (int ignore ATTRIBUTE_UNUSED)
3190{
3191 subseg_set (bss_section, 0);
3192 demand_empty_rest_of_line ();
3193}
3194
e23eba97 3195static void
d115ab8e 3196riscv_make_nops (char *buf, bfd_vma bytes)
e23eba97 3197{
d115ab8e 3198 bfd_vma i = 0;
e23eba97 3199
e5b737de
AW		 3200 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3201 means we are not within a valid instruction sequence. It is thus safe
3202 to use a zero byte, even though that is not a valid instruction. */
3203 if (bytes % 2 == 1)
3204 buf[i++] = 0;
3205
3206 /* Use at most one 2-byte NOP. */
3207 if ((bytes - i) % 4 == 2)
e23eba97 3208 {
e5b737de 3209 md_number_to_chars (buf + i, RVC_NOP, 2);
d115ab8e 3210 i += 2;
e23eba97
NC		 3211 }
3212
e5b737de 3213 /* Fill the remainder with 4-byte NOPs. */
d115ab8e
AW		 3214 for ( ; i < bytes; i += 4)
3215 md_number_to_chars (buf + i, RISCV_NOP, 4);
3216}
e23eba97 3217
d115ab8e
AW		 3218/* Called from md_do_align. Used to create an alignment frag in a
3219 code section by emitting a worst-case NOP sequence that the linker
3220 will later relax to the correct number of NOPs. We can't compute
3221 the correct alignment now because of other linker relaxations. */
3222
3223bfd_boolean
3224riscv_frag_align_code (int n)
3225{
e5b737de 3226 bfd_vma bytes = (bfd_vma) 1 << n;
36877bfb
JW		 3227 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
3228 bfd_vma worst_case_bytes = bytes - insn_alignment;
3229 char *nops;
ed0816bd 3230 expressionS ex;
d115ab8e 3231
36877bfb
JW		 3232 /* If we are moving to a smaller alignment than the instruction size, then no
3233 alignment is required. */
3234 if (bytes <= insn_alignment)
3235 return TRUE;
3236
d115ab8e
AW		 3237 /* When not relaxing, riscv_handle_align handles code alignment. */
3238 if (!riscv_opts.relax)
3239 return FALSE;
e23eba97 3240
e80ae190
JW		 3241 nops = frag_more (worst_case_bytes);
3242
ed0816bd
PD		 3243 ex.X_op = O_constant;
3244 ex.X_add_number = worst_case_bytes;
d115ab8e 3245
ed0816bd 3246 riscv_make_nops (nops, worst_case_bytes);
e23eba97 3247
ed0816bd
PD		 3248 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
3249 &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
e23eba97 3250
d115ab8e
AW		 3251 return TRUE;
3252}
e23eba97 3253
d115ab8e
AW		 3254/* Implement HANDLE_ALIGN. */
3255
3256void
3257riscv_handle_align (fragS *fragP)
3258{
3259 switch (fragP->fr_type)
3260 {
3261 case rs_align_code:
3262 /* When relaxing, riscv_frag_align_code handles code alignment. */
3263 if (!riscv_opts.relax)
3264 {
e80ae190
JW		 3265 bfd_signed_vma bytes = (fragP->fr_next->fr_address
3266 - fragP->fr_address - fragP->fr_fix);
3267 /* We have 4 byte uncompressed nops. */
3268 bfd_signed_vma size = 4;
3269 bfd_signed_vma excess = bytes % size;
3270 char *p = fragP->fr_literal + fragP->fr_fix;
3271
3272 if (bytes <= 0)
d115ab8e
AW		 3273 break;
3274
e80ae190
JW		 3275 /* Insert zeros or compressed nops to get 4 byte alignment. */
3276 if (excess)
3277 {
3278 riscv_make_nops (p, excess);
3279 fragP->fr_fix += excess;
3280 p += excess;
3281 }
3282
3283 /* Insert variable number of 4 byte uncompressed nops. */
3284 riscv_make_nops (p, size);
3285 fragP->fr_var = size;
d115ab8e
AW		 3286 }
3287 break;
3288
3289 default:
3290 break;
3291 }
e23eba97
NC		 3292}
3293
3294int
3295md_estimate_size_before_relax (fragS *fragp, asection *segtype)
3296{
3297 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
3298}
3299
3300/* Translate internal representation of relocation info to BFD target
3301 format. */
3302
3303arelent *
3304tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3305{
3306 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
3307
3308 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3309 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3310 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3311 reloc->addend = fixp->fx_addnumber;
3312
3313 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3314 if (reloc->howto == NULL)
3315 {
3316 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
3317 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
3318 {
3319 /* We don't have R_RISCV_8/16, but for this special case,
3320 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3321 return reloc;
3322 }
3323
3324 as_bad_where (fixp->fx_file, fixp->fx_line,
3325 _("cannot represent %s relocation in object file"),
3326 bfd_get_reloc_code_name (fixp->fx_r_type));
3327 return NULL;
3328 }
3329
3330 return reloc;
3331}
3332
3333int
3334riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
3335{
3336 if (RELAX_BRANCH_P (fragp->fr_subtype))
3337 {
3338 offsetT old_var = fragp->fr_var;
3339 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
3340 return fragp->fr_var - old_var;
3341 }
3342
3343 return 0;
3344}
3345
3346/* Expand far branches to multi-instruction sequences. */
3347
3348static void
3349md_convert_frag_branch (fragS *fragp)
3350{
3351 bfd_byte *buf;
3352 expressionS exp;
3353 fixS *fixp;
3354 insn_t insn;
3355 int rs1, reloc;
3356
3357 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
3358
3359 exp.X_op = O_symbol;
3360 exp.X_add_symbol = fragp->fr_symbol;
3361 exp.X_add_number = fragp->fr_offset;
3362
3363 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
3364
3365 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
3366 {
3367 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3368 {
3369 case 8:
3370 case 4:
3371 /* Expand the RVC branch into a RISC-V one. */
3372 insn = bfd_getl16 (buf);
3373 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
3374 if ((insn & MASK_C_J) == MATCH_C_J)
3375 insn = MATCH_JAL;
3376 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
3377 insn = MATCH_JAL | (X_RA << OP_SH_RD);
3378 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
3379 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
3380 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
3381 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
3382 else
3383 abort ();
3384 bfd_putl32 (insn, buf);
3385 break;
3386
3387 case 6:
3388 /* Invert the branch condition. Branch over the jump. */
3389 insn = bfd_getl16 (buf);
3390 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
3391 insn |= ENCODE_RVC_B_IMM (6);
3392 bfd_putl16 (insn, buf);
3393 buf += 2;
3394 goto jump;
3395
3396 case 2:
3397 /* Just keep the RVC branch. */
3398 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3399 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
3400 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3401 2, &exp, FALSE, reloc);
3402 buf += 2;
3403 goto done;
3404
3405 default:
1d65abb5 3406 abort ();
e23eba97
NC		 3407 }
3408 }
3409
3410 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3411 {
3412 case 8:
3413 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
3414
3415 /* Invert the branch condition. Branch over the jump. */
3416 insn = bfd_getl32 (buf);
3417 insn ^= MATCH_BEQ ^ MATCH_BNE;
3418 insn |= ENCODE_SBTYPE_IMM (8);
3419 md_number_to_chars ((char *) buf, insn, 4);
3420 buf += 4;
3421
dc1e8a47 3422 jump:
e23eba97
NC		 3423 /* Jump to the target. */
3424 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3425 4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
3426 md_number_to_chars ((char *) buf, MATCH_JAL, 4);
3427 buf += 4;
3428 break;
3429
3430 case 4:
3431 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3432 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
3433 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3434 4, &exp, FALSE, reloc);
3435 buf += 4;
3436 break;
3437
3438 default:
3439 abort ();
3440 }
3441
dc1e8a47 3442 done:
e23eba97
NC		 3443 fixp->fx_file = fragp->fr_file;
3444 fixp->fx_line = fragp->fr_line;
3445
3446 gas_assert (buf == (bfd_byte *)fragp->fr_literal
3447 + fragp->fr_fix + fragp->fr_var);
3448
3449 fragp->fr_fix += fragp->fr_var;
3450}
3451
3452/* Relax a machine dependent frag. This returns the amount by which
3453 the current size of the frag should change. */
3454
3455void
3456md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3457 fragS *fragp)
3458{
3459 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
3460 md_convert_frag_branch (fragp);
3461}
3462
3463void
3464md_show_usage (FILE *stream)
3465{
3466 fprintf (stream, _("\
3467RISC-V options:\n\
8f595e9b
NC		 3468 -fpic generate position-independent code\n\
3469 -fno-pic don't generate position-independent code (default)\n\
3470 -march=ISA set the RISC-V architecture\n\
3471 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3472 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3473 -mabi=ABI set the RISC-V ABI\n\
3474 -mrelax enable relax (default)\n\
3475 -mno-relax disable relax\n\
3476 -march-attr generate RISC-V arch attribute\n\
3477 -mno-arch-attr don't generate RISC-V arch attribute\n\
e23eba97
NC		 3478"));
3479}
3480
3481/* Standard calling conventions leave the CFA at SP on entry. */
3482void
3483riscv_cfi_frame_initial_instructions (void)
3484{
3485 cfi_add_CFA_def_cfa_register (X_SP);
3486}
3487
3488int
3489tc_riscv_regname_to_dw2regnum (char *regname)
3490{
3491 int reg;
3492
3493 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3494 return reg;
3495
3496 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3497 return reg + 32;
3498
4762fe62
AB		 3499 /* CSRs are numbered 4096 -> 8191. */
3500 if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
3501 return reg + 4096;
3502
e23eba97
NC		 3503 as_bad (_("unknown register `%s'"), regname);
3504 return -1;
3505}
3506
3507void
3508riscv_elf_final_processing (void)
3509{
e23eba97 3510 elf_elfheader (stdoutput)->e_flags |= elf_flags;
e23eba97
NC		 3511}
3512
3513/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3514 since these directives break relaxation when used with symbol deltas. */
3515
3516static void
3517s_riscv_leb128 (int sign)
3518{
3519 expressionS exp;
3520 char *save_in = input_line_pointer;
3521
3522 expression (&exp);
3523 if (exp.X_op != O_constant)
3524 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3525 demand_empty_rest_of_line ();
3526
3527 input_line_pointer = save_in;
3528 return s_leb128 (sign);
3529}
3530
0e35537d
JW		 3531/* Parse the .insn directive. */
3532
3533static void
3534s_riscv_insn (int x ATTRIBUTE_UNUSED)
3535{
3536 char *str = input_line_pointer;
3537 struct riscv_cl_insn insn;
3538 expressionS imm_expr;
3539 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3540 char save_c;
3541
3542 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3543 ++input_line_pointer;
3544
3545 save_c = *input_line_pointer;
3546 *input_line_pointer = '\0';
3547
3548 const char *error = riscv_ip (str, &insn, &imm_expr,
3549 &imm_reloc, insn_type_hash);
3550
3551 if (error)
3552 {
3553 as_bad ("%s `%s'", error, str);
3554 }
3555 else
3556 {
3557 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3558 append_insn (&insn, &imm_expr, imm_reloc);
3559 }
3560
3561 *input_line_pointer = save_c;
3562 demand_empty_rest_of_line ();
3563}
3564
8f595e9b
NC		 3565/* Update arch and priv attributes. If we don't set the corresponding ELF
3566 attributes, then try to output the default ones. */
2dc8dd17
JW		 3567
3568static void
8f595e9b 3569riscv_write_out_attrs (void)
2dc8dd17 3570{
8f595e9b
NC		 3571 const char *arch_str, *priv_str, *p;
3572 /* versions[0] is major, versions[1] is minor,
3573 and versions[3] is revision. */
3574 unsigned versions[3] = {0}, number = 0;
3575 unsigned int i;
2dc8dd17 3576
8f595e9b
NC		 3577 /* Re-write arch attribute to normalize the arch string. */
3578 arch_str = riscv_arch_str (xlen, &riscv_subsets);
2dc8dd17 3579 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
2dc8dd17 3580 xfree ((void *)arch_str);
8f595e9b
NC		 3581
3582 /* For the file without any instruction, we don't set the default_priv_spec
3583 according to the priv attributes since the md_assemble isn't called.
3584 Call riscv_set_default_priv_spec here for the above case, although
3585 it seems strange. */
3586 if (!start_assemble
3587 && !riscv_set_default_priv_spec (NULL))
3588 return;
3589
1a79004f
NC		 3590 /* If we already have set elf priv attributes, then no need to do anything,
3591 assembler will generate them according to what you set. Otherwise, don't
3592 generate or update them when no CSR and priv instructions are used.
3593 Generate the priv attributes according to default_priv_spec, which can be
3594 set by -mpriv-spec and --with-priv-spec, and be updated by the original
3595 priv attribute sets. */
3596 if (!explicit_priv_attr)
3fc6c3dc
NC		 3597 return;
3598
8f595e9b
NC		 3599 /* Re-write priv attributes by default_priv_spec. */
3600 priv_str = riscv_get_priv_spec_name (default_priv_spec);
3601 p = priv_str;
3602 for (i = 0; *p; ++p)
3603 {
3604 if (*p == '.' && i < 3)
3605 {
3606 versions[i++] = number;
3607 number = 0;
3608 }
3609 else if (ISDIGIT (*p))
3610 number = (number * 10) + (*p - '0');
3611 else
3612 {
3613 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str);
3614 return;
3615 }
3616 }
3617 versions[i] = number;
3618
3619 /* Set the priv attributes. */
3620 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
3621 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
3622 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
2dc8dd17
JW		 3623}
3624
8f595e9b
NC		 3625/* Add the default contents for the .riscv.attributes section. If any
3626 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3627 to update the arch and priv attributes. */
2dc8dd17
JW		 3628
3629static void
3630riscv_set_public_attributes (void)
3631{
8f595e9b
NC		 3632 if (riscv_opts.arch_attr || explicit_attr)
3633 riscv_write_out_attrs ();
2dc8dd17
JW		 3634}
3635
3636/* Called after all assembly has been done. */
3637
3638void
3639riscv_md_end (void)
3640{
3641 riscv_set_public_attributes ();
3642}
3643
3644/* Given a symbolic attribute NAME, return the proper integer value.
3645 Returns -1 if the attribute is not known. */
3646
3647int
3648riscv_convert_symbolic_attribute (const char *name)
3649{
3650 static const struct
3651 {
3652 const char * name;
3653 const int tag;
3654 }
3655 attribute_table[] =
3656 {
3657 /* When you modify this table you should
3658 also modify the list in doc/c-riscv.texi. */
3659#define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3660 T(arch),
3661 T(priv_spec),
3662 T(priv_spec_minor),
3663 T(priv_spec_revision),
3664 T(unaligned_access),
3665 T(stack_align),
3666#undef T
3667 };
3668
3669 unsigned int i;
3670
3671 if (name == NULL)
3672 return -1;
3673
3674 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
3675 if (strcmp (name, attribute_table[i].name) == 0)
3676 return attribute_table[i].tag;
3677
3678 return -1;
3679}
3680
3681/* Parse a .attribute directive. */
3682
3683static void
3684s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
3685{
3686 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
8f595e9b
NC		 3687 unsigned old_xlen;
3688 obj_attribute *attr;
2dc8dd17 3689
8f595e9b
NC		 3690 explicit_attr = TRUE;
3691 switch (tag)
2dc8dd17 3692 {
8f595e9b
NC		 3693 case Tag_RISCV_arch:
3694 old_xlen = xlen;
2dc8dd17
JW		 3695 attr = elf_known_obj_attributes_proc (stdoutput);
3696 if (!start_assemble)
3697 riscv_set_arch (attr[Tag_RISCV_arch].s);
3698 else
3699 as_fatal (_(".attribute arch must set before any instructions"));
3700
3701 if (old_xlen != xlen)
3702 {
3703 /* We must re-init bfd again if xlen is changed. */
3704 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
3705 bfd_find_target (riscv_target_format (), stdoutput);
3706
3707 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
3708 as_warn (_("Could not set architecture and machine"));
3709 }
8f595e9b
NC		 3710 break;
3711
3712 case Tag_RISCV_priv_spec:
3713 case Tag_RISCV_priv_spec_minor:
3714 case Tag_RISCV_priv_spec_revision:
3715 if (start_assemble)
3716 as_fatal (_(".attribute priv spec must set before any instructions"));
3717 break;
3718
3719 default:
3720 break;
2dc8dd17
JW		 3721 }
3722}
3723
e23eba97
NC		 3724/* Pseudo-op table. */
3725
3726static const pseudo_typeS riscv_pseudo_table[] =
3727{
3728 /* RISC-V-specific pseudo-ops. */
3729 {"option", s_riscv_option, 0},
3730 {"half", cons, 2},
3731 {"word", cons, 4},
3732 {"dword", cons, 8},
3733 {"dtprelword", s_dtprel, 4},
3734 {"dtpreldword", s_dtprel, 8},
3735 {"bss", s_bss, 0},
e23eba97
NC		 3736 {"uleb128", s_riscv_leb128, 0},
3737 {"sleb128", s_riscv_leb128, 1},
0e35537d 3738 {"insn", s_riscv_insn, 0},
2dc8dd17 3739 {"attribute", s_riscv_attribute, 0},
e23eba97
NC		 3740
3741 { NULL, NULL, 0 },
3742};
3743
3744void
3745riscv_pop_insert (void)
3746{
3747 extern void pop_insert (const pseudo_typeS *);
3748
3749 pop_insert (riscv_pseudo_table);
3750}
GDB Binutils - Deliverables
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