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Rearrange symbol_create parameters
[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
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e23eba97 1/* tc-riscv.c -- RISC-V assembler
b3adc24a 2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
1080bf78 32#include "bfd/elfxx-riscv.h"
e23eba97
NC		 33#include "elf/riscv.h"
34#include "opcode/riscv.h"
35
36#include <stdint.h>
37
38/* Information about an instruction, including its format, operands
39 and fixups. */
40struct riscv_cl_insn
41{
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode *insn_mo;
44
45 /* The encoded instruction bits. */
46 insn_t insn_opcode;
47
48 /* The frag that contains the instruction. */
49 struct frag *frag;
50
51 /* The offset into FRAG of the first instruction byte. */
52 long where;
53
54 /* The relocs associated with the instruction, if any. */
55 fixS *fixp;
56};
57
58#ifndef DEFAULT_ARCH
59#define DEFAULT_ARCH "riscv64"
60#endif
61
2dc8dd17
JW		 62#ifndef DEFAULT_RISCV_ATTR
63#define DEFAULT_RISCV_ATTR 0
64#endif
65
8f595e9b
NC		 66/* Let riscv_after_parse_args set the default value according to xlen. */
67
68#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
70#endif
71
72/* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
77
78#ifndef DEFAULT_RISCV_ISA_SPEC
79#define DEFAULT_RISCV_ISA_SPEC "2.2"
80#endif
81
82#ifndef DEFAULT_RISCV_PRIV_SPEC
83#define DEFAULT_RISCV_PRIV_SPEC "1.11"
84#endif
85
e23eba97 86static const char default_arch[] = DEFAULT_ARCH;
8f595e9b
NC		 87static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
88static enum riscv_isa_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
89static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
e23eba97 90
2922d21d
AW		 91static unsigned xlen = 0; /* width of an x-register */
92static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
7f999549 93static bfd_boolean rve_abi = FALSE;
e23eba97 94
2922d21d 95#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
e23eba97
NC		 96#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
97
98static unsigned elf_flags = 0;
99
8f595e9b
NC		 100/* Set the default_isa_spec. Return 0 if the input spec string isn't
101 supported. Otherwise, return 1. */
102
103static int
104riscv_set_default_isa_spec (const char *s)
105{
106 enum riscv_isa_spec_class class;
107 if (!riscv_get_isa_spec_class (s, &class))
108 {
109 as_bad ("Unknown default ISA spec `%s' set by "
110 "-misa-spec or --with-isa-spec", s);
111 return 0;
112 }
113 else
114 default_isa_spec = class;
115 return 1;
116}
117
118/* Set the default_priv_spec, assembler will find the suitable CSR address
119 according to default_priv_spec. We will try to check priv attributes if
120 the input string is NULL. Return 0 if the input priv spec string isn't
121 supported. Otherwise, return 1. */
122
123static int
124riscv_set_default_priv_spec (const char *s)
125{
126 enum riscv_priv_spec_class class;
127 unsigned major, minor, revision;
128 obj_attribute *attr;
8f595e9b
NC		 129
130 /* Find the corresponding priv spec class. */
131 if (riscv_get_priv_spec_class (s, &class))
132 {
133 default_priv_spec = class;
134 return 1;
135 }
136
137 if (s != NULL)
138 {
139 as_bad (_("Unknown default privilege spec `%s' set by "
140 "-mpriv-spec or --with-priv-spec"), s);
141 return 0;
142 }
143
144 /* Try to set the default_priv_spec according to the priv attributes. */
145 attr = elf_known_obj_attributes_proc (stdoutput);
146 major = (unsigned) attr[Tag_RISCV_priv_spec].i;
147 minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
148 revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
149
39ff0b81
NC		 150 if (riscv_get_priv_spec_class_from_numbers (major,
151 minor,
152 revision,
153 &class))
8f595e9b 154 {
39ff0b81
NC		 155 /* The priv attributes setting 0.0.0 is meaningless. We should have set
156 the default_priv_spec by md_parse_option and riscv_after_parse_args,
157 so just skip the following setting. */
158 if (class == PRIV_SPEC_CLASS_NONE)
159 return 1;
8f595e9b 160
8f595e9b 161 default_priv_spec = class;
8f595e9b
NC		 162 return 1;
163 }
164
165 /* Still can not find the priv spec class. */
ddc73fa9 166 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
8f595e9b 167 "privilege attributes"), major, minor, revision);
8f595e9b
NC		 168 return 0;
169}
170
e23eba97
NC		 171/* This is the set of options which the .option pseudo-op may modify. */
172
173struct riscv_set_options
174{
175 int pic; /* Generate position-independent code. */
176 int rvc; /* Generate RVC code. */
7f999549 177 int rve; /* Generate RVE code. */
45f76423 178 int relax; /* Emit relocs the linker is allowed to relax. */
2dc8dd17 179 int arch_attr; /* Emit arch attribute. */
2ca89224 180 int csr_check; /* Enable the CSR checking. */
e23eba97
NC		 181};
182
183static struct riscv_set_options riscv_opts =
184{
185 0, /* pic */
186 0, /* rvc */
7f999549 187 0, /* rve */
45f76423 188 1, /* relax */
2dc8dd17 189 DEFAULT_RISCV_ATTR, /* arch_attr */
2ca89224 190 0. /* csr_check */
e23eba97
NC		 191};
192
193static void
194riscv_set_rvc (bfd_boolean rvc_value)
195{
196 if (rvc_value)
197 elf_flags |= EF_RISCV_RVC;
198
199 riscv_opts.rvc = rvc_value;
200}
201
7f999549
JW		 202static void
203riscv_set_rve (bfd_boolean rve_value)
204{
205 riscv_opts.rve = rve_value;
206}
207
1080bf78 208static riscv_subset_list_t riscv_subsets;
e23eba97
NC		 209
210static bfd_boolean
1080bf78 211riscv_subset_supports (const char *feature)
e23eba97 212{
1080bf78
JW		 213 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
214 return TRUE;
e23eba97 215
1080bf78 216 return riscv_lookup_subset (&riscv_subsets, feature) != NULL;
e23eba97
NC		 217}
218
43135d3b 219static bfd_boolean
7e9ad3a3 220riscv_multi_subset_supports (enum riscv_insn_class insn_class)
43135d3b 221{
7e9ad3a3
JW		 222 switch (insn_class)
223 {
224 case INSN_CLASS_I: return riscv_subset_supports ("i");
225 case INSN_CLASS_C: return riscv_subset_supports ("c");
226 case INSN_CLASS_A: return riscv_subset_supports ("a");
227 case INSN_CLASS_M: return riscv_subset_supports ("m");
228 case INSN_CLASS_F: return riscv_subset_supports ("f");
229 case INSN_CLASS_D: return riscv_subset_supports ("d");
230 case INSN_CLASS_D_AND_C:
231 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
232
233 case INSN_CLASS_F_AND_C:
234 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
43135d3b 235
7e9ad3a3 236 case INSN_CLASS_Q: return riscv_subset_supports ("q");
43135d3b 237
7e9ad3a3
JW		 238 default:
239 as_fatal ("Unreachable");
240 return FALSE;
241 }
43135d3b
JW		 242}
243
8f595e9b 244/* Handle of the extension with version hash table. */
629310ab 245static htab_t ext_version_hash = NULL;
8f595e9b 246
629310ab 247static htab_t
8f595e9b
NC		 248init_ext_version_hash (const struct riscv_ext_version *table)
249{
250 int i = 0;
629310ab 251 htab_t hash = str_htab_create ();
8f595e9b
NC		 252
253 while (table[i].name)
254 {
255 const char *name = table[i].name;
629310ab 256 str_hash_insert (hash, name, (void *) &table[i]);
8f595e9b
NC		 257
258 i++;
259 while (table[i].name
260 && strcmp (table[i].name, name) == 0)
261 i++;
262 }
263
264 return hash;
265}
266
267static void
268riscv_get_default_ext_version (const char *name,
269 unsigned int *major_version,
270 unsigned int *minor_version)
271{
272 struct riscv_ext_version *ext;
273
274 *major_version = 0;
275 *minor_version = 0;
276
277 if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
278 return;
279
629310ab 280 ext = (struct riscv_ext_version *) str_hash_find (ext_version_hash, name);
8f595e9b
NC		 281 while (ext
282 && ext->name
283 && strcmp (ext->name, name) == 0)
284 {
285 if (ext->isa_spec_class == default_isa_spec)
286 {
287 *major_version = ext->major_version;
288 *minor_version = ext->minor_version;
289 return;
290 }
291 ext++;
292 }
293}
294
2922d21d 295/* Set which ISA and extensions are available. */
e23eba97 296
e23eba97 297static void
2922d21d 298riscv_set_arch (const char *s)
e23eba97 299{
1080bf78
JW		 300 riscv_parse_subset_t rps;
301 rps.subset_list = &riscv_subsets;
302 rps.error_handler = as_fatal;
303 rps.xlen = &xlen;
8f595e9b
NC		 304 rps.get_default_version = riscv_get_default_ext_version;
305
306 if (s == NULL)
307 return;
7f999549 308
1080bf78
JW		 309 riscv_release_subset_list (&riscv_subsets);
310 riscv_parse_subset (&rps, s);
e23eba97
NC		 311}
312
313/* Handle of the OPCODE hash table. */
629310ab 314static htab_t op_hash = NULL;
e23eba97 315
0e35537d 316/* Handle of the type of .insn hash table. */
629310ab 317static htab_t insn_type_hash = NULL;
0e35537d 318
e23eba97
NC		 319/* This array holds the chars that always start a comment. If the
320 pre-processor is disabled, these aren't very useful */
321const char comment_chars[] = "#";
322
323/* This array holds the chars that only start a comment at the beginning of
324 a line. If the line seems to have the form '# 123 filename'
325 .line and .file directives will appear in the pre-processed output */
326/* Note that input_file.c hand checks for '#' at the beginning of the
327 first line of the input file. This is because the compiler outputs
328 #NO_APP at the beginning of its output. */
329/* Also note that C style comments are always supported. */
330const char line_comment_chars[] = "#";
331
332/* This array holds machine specific line separator characters. */
333const char line_separator_chars[] = ";";
334
335/* Chars that can be used to separate mant from exp in floating point nums */
336const char EXP_CHARS[] = "eE";
337
338/* Chars that mean this number is a floating point constant */
339/* As in 0f12.456 */
340/* or 0d1.2345e12 */
341const char FLT_CHARS[] = "rRsSfFdDxXpP";
342
2dc8dd17
JW		 343/* Indicate we are already assemble any instructions or not. */
344static bfd_boolean start_assemble = FALSE;
345
8f595e9b
NC		 346/* Indicate ELF attributes are explictly set. */
347static bfd_boolean explicit_attr = FALSE;
2dc8dd17 348
1a79004f
NC		 349/* Indicate CSR or priv instructions are explictly used. */
350static bfd_boolean explicit_priv_attr = FALSE;
3fc6c3dc 351
e23eba97
NC		 352/* Macros for encoding relaxation state for RVC branches and far jumps. */
353#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
354 ((relax_substateT) \
355 (0xc0000000 \
356 | ((uncond) ? 1 : 0) \
357 | ((rvc) ? 2 : 0) \
358 | ((length) << 2)))
359#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
360#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
361#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
362#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
363
364/* Is the given value a sign-extended 32-bit value? */
365#define IS_SEXT_32BIT_NUM(x) \
366 (((x) &~ (offsetT) 0x7fffffff) == 0 \
367 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
368
369/* Is the given value a zero-extended 32-bit value? Or a negated one? */
370#define IS_ZEXT_32BIT_NUM(x) \
371 (((x) &~ (offsetT) 0xffffffff) == 0 \
372 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
373
374/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
375 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
376#define INSERT_OPERAND(FIELD, INSN, VALUE) \
377 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
378
379/* Determine if an instruction matches an opcode. */
380#define OPCODE_MATCHES(OPCODE, OP) \
381 (((OPCODE) & MASK_##OP) == MATCH_##OP)
382
383static char *expr_end;
384
385/* The default target format to use. */
386
387const char *
388riscv_target_format (void)
389{
390 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
391}
392
393/* Return the length of instruction INSN. */
394
395static inline unsigned int
396insn_length (const struct riscv_cl_insn *insn)
397{
398 return riscv_insn_length (insn->insn_opcode);
399}
400
401/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
402
403static void
404create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
405{
406 insn->insn_mo = mo;
407 insn->insn_opcode = mo->match;
408 insn->frag = NULL;
409 insn->where = 0;
410 insn->fixp = NULL;
411}
412
413/* Install INSN at the location specified by its "frag" and "where" fields. */
414
415static void
416install_insn (const struct riscv_cl_insn *insn)
417{
418 char *f = insn->frag->fr_literal + insn->where;
419 md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
420}
421
422/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
423 and install the opcode in the new location. */
424
425static void
426move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
427{
428 insn->frag = frag;
429 insn->where = where;
430 if (insn->fixp != NULL)
431 {
432 insn->fixp->fx_frag = frag;
433 insn->fixp->fx_where = where;
434 }
435 install_insn (insn);
436}
437
438/* Add INSN to the end of the output. */
439
440static void
441add_fixed_insn (struct riscv_cl_insn *insn)
442{
443 char *f = frag_more (insn_length (insn));
444 move_insn (insn, frag_now, f - frag_now->fr_literal);
445}
446
447static void
448add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
449 relax_substateT subtype, symbolS *symbol, offsetT offset)
450{
451 frag_grow (max_chars);
452 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
453 frag_var (rs_machine_dependent, max_chars, var,
454 subtype, symbol, offset, NULL);
455}
456
457/* Compute the length of a branch sequence, and adjust the stored length
458 accordingly. If FRAGP is NULL, the worst-case length is returned. */
459
460static unsigned
461relaxed_branch_length (fragS *fragp, asection *sec, int update)
462{
463 int jump, rvc, length = 8;
464
465 if (!fragp)
466 return length;
467
468 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
469 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
470 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
471
472 /* Assume jumps are in range; the linker will catch any that aren't. */
473 length = jump ? 4 : 8;
474
475 if (fragp->fr_symbol != NULL
476 && S_IS_DEFINED (fragp->fr_symbol)
01156111 477 && !S_IS_WEAK (fragp->fr_symbol)
e23eba97
NC		 478 && sec == S_GET_SEGMENT (fragp->fr_symbol))
479 {
480 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
481 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
482 val -= fragp->fr_address + fragp->fr_fix;
483
484 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
485 length = 2;
486 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
487 length = 4;
488 else if (!jump && rvc)
489 length = 6;
490 }
491
492 if (update)
493 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
494
495 return length;
496}
497
0e35537d
JW		 498/* Information about an opcode name, mnemonics and its value. */
499struct opcode_name_t
500{
501 const char *name;
502 unsigned int val;
503};
504
505/* List for all supported opcode name. */
506static const struct opcode_name_t opcode_name_list[] =
507{
508 {"C0", 0x0},
509 {"C1", 0x1},
510 {"C2", 0x2},
511
512 {"LOAD", 0x03},
513 {"LOAD_FP", 0x07},
514 {"CUSTOM_0", 0x0b},
515 {"MISC_MEM", 0x0f},
516 {"OP_IMM", 0x13},
517 {"AUIPC", 0x17},
518 {"OP_IMM_32", 0x1b},
519 /* 48b 0x1f. */
520
521 {"STORE", 0x23},
522 {"STORE_FP", 0x27},
523 {"CUSTOM_1", 0x2b},
524 {"AMO", 0x2f},
525 {"OP", 0x33},
526 {"LUI", 0x37},
527 {"OP_32", 0x3b},
528 /* 64b 0x3f. */
529
530 {"MADD", 0x43},
531 {"MSUB", 0x47},
532 {"NMADD", 0x4f},
533 {"NMSUB", 0x4b},
534 {"OP_FP", 0x53},
535 /*reserved 0x57. */
536 {"CUSTOM_2", 0x5b},
537 /* 48b 0x5f. */
538
539 {"BRANCH", 0x63},
540 {"JALR", 0x67},
541 /*reserved 0x5b. */
542 {"JAL", 0x6f},
543 {"SYSTEM", 0x73},
544 /*reserved 0x77. */
545 {"CUSTOM_3", 0x7b},
546 /* >80b 0x7f. */
547
548 {NULL, 0}
549};
550
551/* Hash table for lookup opcode name. */
629310ab 552static htab_t opcode_names_hash = NULL;
0e35537d
JW		 553
554/* Initialization for hash table of opcode name. */
555static void
556init_opcode_names_hash (void)
557{
0e35537d
JW		 558 const struct opcode_name_t *opcode;
559
560 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
629310ab 561 str_hash_insert (opcode_names_hash, opcode->name, (void *)opcode);
0e35537d
JW		 562}
563
564/* Find `s` is a valid opcode name or not,
565 return the opcode name info if found. */
566static const struct opcode_name_t *
567opcode_name_lookup (char **s)
568{
569 char *e;
570 char save_c;
571 struct opcode_name_t *o;
572
573 /* Find end of name. */
574 e = *s;
575 if (is_name_beginner (*e))
576 ++e;
577 while (is_part_of_name (*e))
578 ++e;
579
580 /* Terminate name. */
581 save_c = *e;
582 *e = '\0';
583
629310ab 584 o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s);
0e35537d
JW		 585
586 /* Advance to next token if one was recognized. */
587 if (o)
588 *s = e;
589
590 *e = save_c;
591 expr_end = e;
592
593 return o;
594}
595
e23eba97
NC		 596enum reg_class
597{
598 RCLASS_GPR,
599 RCLASS_FPR,
8f595e9b
NC		 600 RCLASS_MAX,
601
602 RCLASS_CSR
e23eba97
NC		 603};
604
629310ab
ML		 605static htab_t reg_names_hash = NULL;
606static htab_t csr_extra_hash = NULL;
e23eba97
NC		 607
608#define ENCODE_REG_HASH(cls, n) \
609 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
610#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
611#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
612
613static void
614hash_reg_name (enum reg_class class, const char *name, unsigned n)
615{
616 void *hash = ENCODE_REG_HASH (class, n);
629310ab 617 str_hash_insert (reg_names_hash, name, hash);
e23eba97
NC		 618}
619
620static void
621hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
622{
623 unsigned i;
624
625 for (i = 0; i < n; i++)
626 hash_reg_name (class, names[i], i);
627}
628
8f595e9b
NC		 629/* Init hash table csr_extra_hash to handle CSR. */
630static void
631riscv_init_csr_hash (const char *name,
632 unsigned address,
633 enum riscv_csr_class class,
634 enum riscv_priv_spec_class define_version,
635 enum riscv_priv_spec_class abort_version)
636{
637 struct riscv_csr_extra *entry, *pre_entry;
8f595e9b
NC		 638 bfd_boolean need_enrty = TRUE;
639
640 pre_entry = NULL;
629310ab 641 entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
8f595e9b
NC		 642 while (need_enrty && entry != NULL)
643 {
644 if (entry->csr_class == class
645 && entry->address == address
646 && entry->define_version == define_version
647 && entry->abort_version == abort_version)
648 need_enrty = FALSE;
649 pre_entry = entry;
650 entry = entry->next;
651 }
652
653 /* Duplicate setting for the CSR, just return and do nothing. */
654 if (!need_enrty)
655 return;
bd0cf5a6 656
8f595e9b
NC		 657 entry = XNEW (struct riscv_csr_extra);
658 entry->csr_class = class;
659 entry->address = address;
660 entry->define_version = define_version;
661 entry->abort_version = abort_version;
5c505568 662 entry->next = NULL;
8f595e9b
NC		 663
664 /* If the CSR hasn't been inserted in the hash table, then insert it.
665 Otherwise, attach the extra information to the entry which is already
666 in the hash table. */
667 if (pre_entry == NULL)
629310ab 668 str_hash_insert (csr_extra_hash, name, (void *) entry);
8f595e9b
NC		 669 else
670 pre_entry->next = entry;
671}
bd0cf5a6 672
08ccfccf
NC		 673/* Return the suitable CSR address after checking the ISA dependency and
674 priv spec versions. */
bd0cf5a6 675
08ccfccf
NC		 676static unsigned int
677riscv_csr_address (const char *csr_name,
678 struct riscv_csr_extra *entry)
bd0cf5a6 679{
08ccfccf
NC		 680 struct riscv_csr_extra *saved_entry = entry;
681 enum riscv_csr_class csr_class = entry->csr_class;
682 bfd_boolean need_check_version = TRUE;
8f595e9b
NC		 683 bfd_boolean result = TRUE;
684
8f595e9b 685 switch (csr_class)
bd0cf5a6 686 {
8f595e9b
NC		 687 case CSR_CLASS_I:
688 result = riscv_subset_supports ("i");
689 break;
08ccfccf
NC		 690 case CSR_CLASS_I_32:
691 result = (xlen == 32 && riscv_subset_supports ("i"));
692 break;
8f595e9b
NC		 693 case CSR_CLASS_F:
694 result = riscv_subset_supports ("f");
08ccfccf 695 need_check_version = FALSE;
8f595e9b 696 break;
08ccfccf
NC		 697 case CSR_CLASS_DEBUG:
698 need_check_version = FALSE;
8f595e9b
NC		 699 break;
700 default:
701 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
bd0cf5a6
NC		 702 }
703
08ccfccf
NC		 704 /* Don't report the ISA conflict when -mcsr-check isn't set. */
705 if (riscv_opts.csr_check && !result)
706 as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name);
8f595e9b
NC		 707
708 while (entry != NULL)
bd0cf5a6 709 {
08ccfccf
NC		 710 if (!need_check_version
711 || (default_priv_spec >= entry->define_version
712 && default_priv_spec < entry->abort_version))
8f595e9b
NC		 713 {
714 /* Find the suitable CSR according to the specific version. */
08ccfccf 715 return entry->address;
8f595e9b
NC		 716 }
717 entry = entry->next;
718 }
bd0cf5a6 719
8f595e9b
NC		 720 /* We can not find the suitable CSR address according to the privilege
721 version. Therefore, we use the last defined value. Report the warning
722 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
723 otherwise, you may get the unexpected CSR address. */
724 if (riscv_opts.csr_check)
725 {
726 const char *priv_name = riscv_get_priv_spec_name (default_priv_spec);
727
728 if (priv_name != NULL)
729 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
730 csr_name, priv_name);
bd0cf5a6 731 }
08ccfccf
NC		 732
733 return saved_entry->address;
bd0cf5a6
NC		 734}
735
8f595e9b
NC		 736/* Once the CSR is defined, including the old privilege spec, then we call
737 riscv_csr_class_check and riscv_csr_version_check to do the further checking
738 and get the corresponding address. Return -1 if the CSR is never been
739 defined. Otherwise, return the address. */
bd0cf5a6 740
8f595e9b 741static unsigned int
bd0cf5a6
NC		 742reg_csr_lookup_internal (const char *s)
743{
744 struct riscv_csr_extra *r =
629310ab 745 (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s);
bd0cf5a6
NC		 746
747 if (r == NULL)
8f595e9b 748 return -1U;
bd0cf5a6 749
8f595e9b
NC		 750 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
751 the CSR was defined, but isn't allowed for the current ISA setting or
752 the privilege spec. If the CSR is never been defined, then assembler
753 will regard it as a "Unknown CSR" and report error. If user use number
754 to set the CSR, but over the range (> 0xfff), then assembler will report
755 "Improper CSR" error for it. */
08ccfccf 756 return riscv_csr_address (s, r);
bd0cf5a6
NC		 757}
758
e23eba97
NC		 759static unsigned int
760reg_lookup_internal (const char *s, enum reg_class class)
761{
8f595e9b
NC		 762 void *r;
763
764 if (class == RCLASS_CSR)
765 return reg_csr_lookup_internal (s);
e23eba97 766
629310ab 767 r = str_hash_find (reg_names_hash, s);
e23eba97
NC		 768 if (r == NULL || DECODE_REG_CLASS (r) != class)
769 return -1;
7f999549
JW		 770
771 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
772 return -1;
773
e23eba97
NC		 774 return DECODE_REG_NUM (r);
775}
776
777static bfd_boolean
778reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
779{
780 char *e;
781 char save_c;
782 int reg = -1;
783
784 /* Find end of name. */
785 e = *s;
786 if (is_name_beginner (*e))
787 ++e;
788 while (is_part_of_name (*e))
789 ++e;
790
791 /* Terminate name. */
792 save_c = *e;
793 *e = '\0';
794
795 /* Look for the register. Advance to next token if one was recognized. */
796 if ((reg = reg_lookup_internal (*s, class)) >= 0)
797 *s = e;
798
799 *e = save_c;
800 if (regnop)
801 *regnop = reg;
802 return reg >= 0;
803}
804
805static bfd_boolean
806arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
807{
808 const char *p = strchr (*s, ',');
809 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
810
bfb218e3
JW		 811 if (len == 0)
812 return FALSE;
813
e23eba97
NC		 814 for (i = 0; i < size; i++)
815 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
816 {
817 *regnop = i;
818 *s += len;
819 return TRUE;
820 }
821
822 return FALSE;
823}
824
825/* For consistency checking, verify that all bits are specified either
826 by the match/mask part of the instruction definition, or by the
0e35537d
JW		 827 operand list.
828
829 `length` could be 0, 4 or 8, 0 for auto detection. */
e23eba97 830static bfd_boolean
0e35537d 831validate_riscv_insn (const struct riscv_opcode *opc, int length)
e23eba97
NC		 832{
833 const char *p = opc->args;
834 char c;
835 insn_t used_bits = opc->mask;
0e35537d
JW		 836 int insn_width;
837 insn_t required_bits;
838
839 if (length == 0)
840 insn_width = 8 * riscv_insn_length (opc->match);
841 else
842 insn_width = 8 * length;
843
844 required_bits = ~0ULL >> (64 - insn_width);
e23eba97
NC		 845
846 if ((used_bits & opc->match) != (opc->match & required_bits))
847 {
848 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
849 opc->name, opc->args);
850 return FALSE;
851 }
852
853#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
854 while (*p)
855 switch (c = *p++)
856 {
857 case 'C': /* RVC */
858 switch (c = *p++)
859 {
1d65abb5 860 case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
e23eba97
NC		 861 case 'c': break; /* RS1, constrained to equal sp */
862 case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
1d65abb5 863 case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
b416fe87 864 case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
1d65abb5
AW		 865 case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
866 case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
867 case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
868 case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
869 case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
e23eba97
NC		 870 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
871 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
1d65abb5
AW		 872 case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
873 case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
e23eba97
NC		 874 case 'w': break; /* RS1S, constrained to equal RD */
875 case 'x': break; /* RS2S, constrained to equal RD */
ca0bc150 876 case 'z': break; /* RS2S, contrained to be x0 */
1d65abb5
AW		 877 case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
878 case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
879 case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
880 case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
e23eba97
NC		 881 case 'U': break; /* RS1, constrained to equal RD */
882 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1d65abb5
AW		 883 case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
884 case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
0e35537d
JW		 885 case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
886 case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
e23eba97
NC		 887 case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
888 case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
0e35537d
JW		 889 case 'F': /* funct */
890 switch (c = *p++)
891 {
4765cd61 892 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
0e35537d
JW		 893 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
894 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
4765cd61 895 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
0e35537d
JW		 896 default:
897 as_bad (_("internal: bad RISC-V opcode"
898 " (unknown operand type `CF%c'): %s %s"),
899 c, opc->name, opc->args);
900 return FALSE;
901 }
902 break;
e23eba97
NC		 903 default:
904 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
905 c, opc->name, opc->args);
906 return FALSE;
907 }
908 break;
909 case ',': break;
910 case '(': break;
911 case ')': break;
912 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
913 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
914 case 'A': break;
915 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
916 case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
917 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
918 case 'I': break;
919 case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
920 case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
921 case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */
922 case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
923 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
924 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
925 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
926 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
0e35537d 927 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
e23eba97
NC		 928 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
929 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
930 case 'o':
1d65abb5
AW		 931 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
932 case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
933 case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
934 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
935 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
e925c834 936 case 'z': break;
e23eba97
NC		 937 case '[': break;
938 case ']': break;
939 case '0': break;
f50fabe4 940 case '1': break;
0e35537d
JW		 941 case 'F': /* funct */
942 switch (c = *p++)
943 {
944 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
945 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
946 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
947 default:
948 as_bad (_("internal: bad RISC-V opcode"
949 " (unknown operand type `F%c'): %s %s"),
950 c, opc->name, opc->args);
951 return FALSE;
952 }
953 break;
954 case 'O': /* opcode */
955 switch (c = *p++)
956 {
957 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
958 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
959 default:
960 as_bad (_("internal: bad RISC-V opcode"
961 " (unknown operand type `F%c'): %s %s"),
962 c, opc->name, opc->args);
963 return FALSE;
964 }
965 break;
e23eba97
NC		 966 default:
967 as_bad (_("internal: bad RISC-V opcode "
968 "(unknown operand type `%c'): %s %s"),
969 c, opc->name, opc->args);
970 return FALSE;
971 }
972#undef USE_BITS
973 if (used_bits != required_bits)
974 {
975 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
976 ~(unsigned long)(used_bits & required_bits),
977 opc->name, opc->args);
978 return FALSE;
979 }
980 return TRUE;
981}
982
983struct percent_op_match
984{
985 const char *str;
986 bfd_reloc_code_real_type reloc;
987};
988
0e35537d
JW		 989/* Common hash table initialization function for
990 instruction and .insn directive. */
629310ab 991static htab_t
0e35537d
JW		 992init_opcode_hash (const struct riscv_opcode *opcodes,
993 bfd_boolean insn_directive_p)
e23eba97
NC		 994{
995 int i = 0;
0e35537d 996 int length;
629310ab 997 htab_t hash = str_htab_create ();
0e35537d 998 while (opcodes[i].name)
e23eba97 999 {
0e35537d 1000 const char *name = opcodes[i].name;
629310ab 1001 str_hash_insert (hash, name, (void *) &opcodes[i]);
e23eba97
NC		 1002
1003 do
1004 {
0e35537d 1005 if (opcodes[i].pinfo != INSN_MACRO)
e23eba97 1006 {
0e35537d
JW		 1007 if (insn_directive_p)
1008 length = ((name[0] == 'c') ? 2 : 4);
1009 else
1010 length = 0; /* Let assembler determine the length. */
1011 if (!validate_riscv_insn (&opcodes[i], length))
e23eba97
NC		 1012 as_fatal (_("Broken assembler. No assembly attempted."));
1013 }
0e35537d
JW		 1014 else
1015 gas_assert (!insn_directive_p);
e23eba97
NC		 1016 ++i;
1017 }
0e35537d 1018 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
e23eba97
NC		 1019 }
1020
0e35537d
JW		 1021 return hash;
1022}
1023
1024/* This function is called once, at assembler startup time. It should set up
1025 all the tables, etc. that the MD part of the assembler will need. */
1026
1027void
1028md_begin (void)
1029{
1030 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
1031
1032 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
1033 as_warn (_("Could not set architecture and machine"));
1034
1035 op_hash = init_opcode_hash (riscv_opcodes, FALSE);
1036 insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
1037
629310ab 1038 reg_names_hash = str_htab_create ();
e23eba97
NC		 1039 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
1040 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
1041 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
1042 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
b9c04e5a
JW		 1043 /* Add "fp" as an alias for "s0". */
1044 hash_reg_name (RCLASS_GPR, "fp", 8);
1045
bd0cf5a6 1046 /* Create and insert CSR hash tables. */
629310ab 1047 csr_extra_hash = str_htab_create ();
8f595e9b
NC		 1048#define DECLARE_CSR(name, num, class, define_version, abort_version) \
1049 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1050#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1051 DECLARE_CSR(name, num, class, define_version, abort_version);
e23eba97
NC		 1052#include "opcode/riscv-opc.h"
1053#undef DECLARE_CSR
1054
629310ab 1055 opcode_names_hash = str_htab_create ();
bd0cf5a6
NC		 1056 init_opcode_names_hash ();
1057
e23eba97
NC		 1058 /* Set the default alignment for the text section. */
1059 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
1060}
1061
45f76423
AW		 1062static insn_t
1063riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
1064{
1065 switch (reloc_type)
1066 {
1067 case BFD_RELOC_32:
1068 return value;
1069
1070 case BFD_RELOC_RISCV_HI20:
1071 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
1072
1073 case BFD_RELOC_RISCV_LO12_S:
1074 return ENCODE_STYPE_IMM (value);
1075
1076 case BFD_RELOC_RISCV_LO12_I:
1077 return ENCODE_ITYPE_IMM (value);
1078
1079 default:
1080 abort ();
1081 }
1082}
1083
e23eba97
NC		 1084/* Output an instruction. IP is the instruction information.
1085 ADDRESS_EXPR is an operand of the instruction to be used with
1086 RELOC_TYPE. */
1087
1088static void
1089append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
1090 bfd_reloc_code_real_type reloc_type)
1091{
1092 dwarf2_emit_insn (0);
1093
1094 if (reloc_type != BFD_RELOC_UNUSED)
1095 {
1096 reloc_howto_type *howto;
1097
1d65abb5 1098 gas_assert (address_expr);
e23eba97
NC		 1099 if (reloc_type == BFD_RELOC_12_PCREL
1100 || reloc_type == BFD_RELOC_RISCV_JMP)
1101 {
1102 int j = reloc_type == BFD_RELOC_RISCV_JMP;
1103 int best_case = riscv_insn_length (ip->insn_opcode);
1104 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
1105 add_relaxed_insn (ip, worst_case, best_case,
1106 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
1107 address_expr->X_add_symbol,
1108 address_expr->X_add_number);
1109 return;
1110 }
45f76423 1111 else
e23eba97 1112 {
45f76423
AW		 1113 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
1114 if (howto == NULL)
1115 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
e23eba97 1116
45f76423
AW		 1117 ip->fixp = fix_new_exp (ip->frag, ip->where,
1118 bfd_get_reloc_size (howto),
1119 address_expr, FALSE, reloc_type);
e23eba97 1120
45f76423 1121 ip->fixp->fx_tcbit = riscv_opts.relax;
e23eba97 1122 }
e23eba97
NC		 1123 }
1124
e23eba97
NC		 1125 add_fixed_insn (ip);
1126 install_insn (ip);
f77bb6c5
JW		 1127
1128 /* We need to start a new frag after any instruction that can be
1129 optimized away or compressed by the linker during relaxation, to prevent
1130 the assembler from computing static offsets across such an instruction.
1131 This is necessary to get correct EH info. */
1132 if (reloc_type == BFD_RELOC_RISCV_CALL
1133 || reloc_type == BFD_RELOC_RISCV_CALL_PLT
1134 || reloc_type == BFD_RELOC_RISCV_HI20
1135 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
1136 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
1137 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
1138 {
1139 frag_wane (frag_now);
1140 frag_new (0);
1141 }
e23eba97
NC		 1142}
1143
1144/* Build an instruction created by a macro expansion. This is passed
1145 a pointer to the count of instructions created so far, an
1146 expression, the name of the instruction to build, an operand format
1147 string, and corresponding arguments. */
1148
1149static void
1150macro_build (expressionS *ep, const char *name, const char *fmt, ...)
1151{
1152 const struct riscv_opcode *mo;
1153 struct riscv_cl_insn insn;
1154 bfd_reloc_code_real_type r;
1155 va_list args;
1156
1157 va_start (args, fmt);
1158
1159 r = BFD_RELOC_UNUSED;
629310ab 1160 mo = (struct riscv_opcode *) str_hash_find (op_hash, name);
e23eba97
NC		 1161 gas_assert (mo);
1162
1163 /* Find a non-RVC variant of the instruction. append_insn will compress
1164 it if possible. */
1165 while (riscv_insn_length (mo->match) < 4)
1166 mo++;
1167 gas_assert (strcmp (name, mo->name) == 0);
1168
1169 create_insn (&insn, mo);
1170 for (;;)
1171 {
1172 switch (*fmt++)
1173 {
1174 case 'd':
1175 INSERT_OPERAND (RD, insn, va_arg (args, int));
1176 continue;
1177
1178 case 's':
1179 INSERT_OPERAND (RS1, insn, va_arg (args, int));
1180 continue;
1181
1182 case 't':
1183 INSERT_OPERAND (RS2, insn, va_arg (args, int));
1184 continue;
1185
1186 case '>':
1187 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
1188 continue;
1189
1190 case 'j':
1191 case 'u':
1192 case 'q':
1193 gas_assert (ep != NULL);
1194 r = va_arg (args, int);
1195 continue;
1196
1197 case '\0':
1198 break;
1199 case ',':
1200 continue;
1201 default:
1202 as_fatal (_("internal error: invalid macro"));
1203 }
1204 break;
1205 }
1206 va_end (args);
1207 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1208
1209 append_insn (&insn, ep, r);
1210}
1211
db3b6ecc
KC		 1212/* Build an instruction created by a macro expansion. Like md_assemble but
1213 accept a printf-style format string and arguments. */
1214
1215static void
1216md_assemblef (const char *format, ...)
1217{
1218 char *buf = NULL;
1219 va_list ap;
1220 int r;
1221
1222 va_start (ap, format);
1223
1224 r = vasprintf (&buf, format, ap);
1225
1226 if (r < 0)
1227 as_fatal (_("internal error: vasprintf failed"));
1228
1229 md_assemble (buf);
1230 free(buf);
1231
1232 va_end (ap);
1233}
1234
e23eba97
NC		 1235/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1236 unset. */
1237static void
1238normalize_constant_expr (expressionS *ex)
1239{
1240 if (xlen > 32)
1241 return;
1242 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1243 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1244 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1245 - 0x80000000);
1246}
1247
ca2fd32c
JW		 1248/* Fail if an expression EX is not a constant. IP is the instruction using EX.
1249 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
e23eba97
NC		 1250
1251static void
ca2fd32c
JW		 1252check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
1253 bfd_boolean maybe_csr)
e23eba97
NC		 1254{
1255 if (ex->X_op == O_big)
1256 as_bad (_("unsupported large constant"));
ca2fd32c
JW		 1257 else if (maybe_csr && ex->X_op == O_symbol)
1258 as_bad (_("unknown CSR `%s'"),
1259 S_GET_NAME (ex->X_add_symbol));
e23eba97
NC		 1260 else if (ex->X_op != O_constant)
1261 as_bad (_("Instruction %s requires absolute expression"),
1262 ip->insn_mo->name);
1263 normalize_constant_expr (ex);
1264}
1265
1266static symbolS *
1267make_internal_label (void)
1268{
e01e1cee
AM		 1269 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now,
1270 frag_now_fix ());
e23eba97
NC		 1271}
1272
1273/* Load an entry from the GOT. */
1274static void
1275pcrel_access (int destreg, int tempreg, expressionS *ep,
1276 const char *lo_insn, const char *lo_pattern,
1277 bfd_reloc_code_real_type hi_reloc,
1278 bfd_reloc_code_real_type lo_reloc)
1279{
1280 expressionS ep2;
1281 ep2.X_op = O_symbol;
1282 ep2.X_add_symbol = make_internal_label ();
1283 ep2.X_add_number = 0;
1284
1285 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1286 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1287}
1288
1289static void
1290pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1291 bfd_reloc_code_real_type hi_reloc,
1292 bfd_reloc_code_real_type lo_reloc)
1293{
1294 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1295}
1296
1297static void
1298pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1299 bfd_reloc_code_real_type hi_reloc,
1300 bfd_reloc_code_real_type lo_reloc)
1301{
1302 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1303}
1304
1305/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1306static void
1307riscv_call (int destreg, int tempreg, expressionS *ep,
1308 bfd_reloc_code_real_type reloc)
1309{
1310 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1311 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
1312}
1313
1314/* Load an integer constant into a register. */
1315
1316static void
1317load_const (int reg, expressionS *ep)
1318{
1319 int shift = RISCV_IMM_BITS;
4f7cc141 1320 bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1);
e23eba97 1321 expressionS upper = *ep, lower = *ep;
4f7cc141 1322 lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign;
e23eba97
NC		 1323 upper.X_add_number -= lower.X_add_number;
1324
1325 if (ep->X_op != O_constant)
1326 {
1327 as_bad (_("unsupported large constant"));
1328 return;
1329 }
1330
1d65abb5 1331 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
e23eba97
NC		 1332 {
1333 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1334 while (((upper.X_add_number >> shift) & 1) == 0)
1335 shift++;
1336
1337 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1d65abb5 1338 load_const (reg, &upper);
e23eba97 1339
db3b6ecc 1340 md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift);
e23eba97 1341 if (lower.X_add_number != 0)
db3b6ecc
KC		 1342 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg,
1343 lower.X_add_number);
e23eba97
NC		 1344 }
1345 else
1346 {
1347 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1348 int hi_reg = 0;
1349
1350 if (upper.X_add_number != 0)
1351 {
db3b6ecc
KC		 1352 /* Discard low part and zero-extend upper immediate. */
1353 upper_imm = ((uint32_t)upper.X_add_number >> shift);
1354
1355 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm);
e23eba97
NC		 1356 hi_reg = reg;
1357 }
1358
1359 if (lower.X_add_number != 0 || hi_reg == 0)
db3b6ecc
KC		 1360 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg,
1361 lower.X_add_number);
e23eba97
NC		 1362 }
1363}
1364
1365/* Expand RISC-V assembly macros into one or more instructions. */
1366static void
1367macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1368 bfd_reloc_code_real_type *imm_reloc)
1369{
1370 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1371 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1372 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1373 int mask = ip->insn_mo->mask;
1374
1375 switch (mask)
1376 {
1377 case M_LI:
1378 load_const (rd, imm_expr);
1379 break;
1380
1381 case M_LA:
1382 case M_LLA:
1383 /* Load the address of a symbol into a register. */
1384 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1385 as_bad (_("offset too large"));
1386
1387 if (imm_expr->X_op == O_constant)
1388 load_const (rd, imm_expr);
1389 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */
1390 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1391 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1392 else /* Local PIC symbol, or any non-PIC symbol */
1393 pcrel_load (rd, rd, imm_expr, "addi",
1394 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1395 break;
1396
1397 case M_LA_TLS_GD:
1398 pcrel_load (rd, rd, imm_expr, "addi",
1399 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1400 break;
1401
1402 case M_LA_TLS_IE:
1403 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1404 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1405 break;
1406
1407 case M_LB:
1408 pcrel_load (rd, rd, imm_expr, "lb",
1409 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1410 break;
1411
1412 case M_LBU:
1413 pcrel_load (rd, rd, imm_expr, "lbu",
1414 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1415 break;
1416
1417 case M_LH:
1418 pcrel_load (rd, rd, imm_expr, "lh",
1419 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1420 break;
1421
1422 case M_LHU:
1423 pcrel_load (rd, rd, imm_expr, "lhu",
1424 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1425 break;
1426
1427 case M_LW:
1428 pcrel_load (rd, rd, imm_expr, "lw",
1429 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1430 break;
1431
1432 case M_LWU:
1433 pcrel_load (rd, rd, imm_expr, "lwu",
1434 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1435 break;
1436
1437 case M_LD:
1438 pcrel_load (rd, rd, imm_expr, "ld",
1439 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1440 break;
1441
1442 case M_FLW:
1443 pcrel_load (rd, rs1, imm_expr, "flw",
1444 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1445 break;
1446
1447 case M_FLD:
1448 pcrel_load (rd, rs1, imm_expr, "fld",
1449 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1450 break;
1451
1452 case M_SB:
1453 pcrel_store (rs2, rs1, imm_expr, "sb",
1454 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1455 break;
1456
1457 case M_SH:
1458 pcrel_store (rs2, rs1, imm_expr, "sh",
1459 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1460 break;
1461
1462 case M_SW:
1463 pcrel_store (rs2, rs1, imm_expr, "sw",
1464 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1465 break;
1466
1467 case M_SD:
1468 pcrel_store (rs2, rs1, imm_expr, "sd",
1469 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1470 break;
1471
1472 case M_FSW:
1473 pcrel_store (rs2, rs1, imm_expr, "fsw",
1474 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1475 break;
1476
1477 case M_FSD:
1478 pcrel_store (rs2, rs1, imm_expr, "fsd",
1479 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1480 break;
1481
1482 case M_CALL:
1483 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1484 break;
1485
1486 default:
1487 as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
1488 break;
1489 }
1490}
1491
1492static const struct percent_op_match percent_op_utype[] =
1493{
1494 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1495 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
dee35d02 1496 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
e23eba97
NC		 1497 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1498 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1499 {"%hi", BFD_RELOC_RISCV_HI20},
1500 {0, 0}
1501};
1502
1503static const struct percent_op_match percent_op_itype[] =
1504{
1505 {"%lo", BFD_RELOC_RISCV_LO12_I},
1506 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1507 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1508 {0, 0}
1509};
1510
1511static const struct percent_op_match percent_op_stype[] =
1512{
1513 {"%lo", BFD_RELOC_RISCV_LO12_S},
1514 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1515 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1516 {0, 0}
1517};
1518
1519static const struct percent_op_match percent_op_rtype[] =
1520{
1521 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1522 {0, 0}
1523};
1524
f50fabe4
JW		 1525static const struct percent_op_match percent_op_null[] =
1526{
1527 {0, 0}
1528};
1529
e23eba97
NC		 1530/* Return true if *STR points to a relocation operator. When returning true,
1531 move *STR over the operator and store its relocation code in *RELOC.
1532 Leave both *STR and *RELOC alone when returning false. */
1533
1534static bfd_boolean
1535parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1536 const struct percent_op_match *percent_op)
1537{
1538 for ( ; percent_op->str; percent_op++)
1539 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1540 {
1541 int len = strlen (percent_op->str);
1542
1543 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1544 continue;
1545
1546 *str += strlen (percent_op->str);
1547 *reloc = percent_op->reloc;
1548
1549 /* Check whether the output BFD supports this relocation.
1550 If not, issue an error and fall back on something safe. */
45f76423
AW		 1551 if (*reloc != BFD_RELOC_UNUSED
1552 && !bfd_reloc_type_lookup (stdoutput, *reloc))
e23eba97
NC		 1553 {
1554 as_bad ("relocation %s isn't supported by the current ABI",
1555 percent_op->str);
1556 *reloc = BFD_RELOC_UNUSED;
1557 }
1558 return TRUE;
1559 }
1560 return FALSE;
1561}
1562
1563static void
1564my_getExpression (expressionS *ep, char *str)
1565{
1566 char *save_in;
1567
1568 save_in = input_line_pointer;
1569 input_line_pointer = str;
1570 expression (ep);
1571 expr_end = input_line_pointer;
1572 input_line_pointer = save_in;
1573}
1574
1575/* Parse string STR as a 16-bit relocatable operand. Store the
1576 expression in *EP and the relocation, if any, in RELOC.
1577 Return the number of relocation operators used (0 or 1).
1578
1579 On exit, EXPR_END points to the first character after the expression. */
1580
1581static size_t
1582my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1583 char *str, const struct percent_op_match *percent_op)
1584{
1585 size_t reloc_index;
1586 unsigned crux_depth, str_depth, regno;
1587 char *crux;
1588
8970c022
JW		 1589 /* First, check for integer registers. No callers can accept a reg, but
1590 we need to avoid accidentally creating a useless undefined symbol below,
1591 if this is an instruction pattern that can't match. A glibc build fails
1592 if this is removed. */
e23eba97
NC		 1593 if (reg_lookup (&str, RCLASS_GPR, &regno))
1594 {
1595 ep->X_op = O_register;
1596 ep->X_add_number = regno;
8970c022 1597 expr_end = str;
e23eba97
NC		 1598 return 0;
1599 }
1600
1601 /* Search for the start of the main expression.
1602 End the loop with CRUX pointing to the start
1603 of the main expression and with CRUX_DEPTH containing the number
1604 of open brackets at that point. */
1605 reloc_index = -1;
1606 str_depth = 0;
1607 do
1608 {
1609 reloc_index++;
1610 crux = str;
1611 crux_depth = str_depth;
1612
1613 /* Skip over whitespace and brackets, keeping count of the number
1614 of brackets. */
1615 while (*str == ' ' || *str == '\t' || *str == '(')
1616 if (*str++ == '(')
1617 str_depth++;
1618 }
1619 while (*str == '%'
1620 && reloc_index < 1
1621 && parse_relocation (&str, reloc, percent_op));
1622
1623 my_getExpression (ep, crux);
1624 str = expr_end;
1625
1626 /* Match every open bracket. */
1627 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1628 if (*str++ == ')')
1629 crux_depth--;
1630
1631 if (crux_depth > 0)
1632 as_bad ("unclosed '('");
1633
1634 expr_end = str;
1635
1636 return reloc_index;
1637}
1638
0e35537d
JW		 1639/* Parse opcode name, could be an mnemonics or number. */
1640static size_t
1641my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1642 char *str, const struct percent_op_match *percent_op)
1643{
1644 const struct opcode_name_t *o = opcode_name_lookup (&str);
1645
1646 if (o != NULL)
1647 {
1648 ep->X_op = O_constant;
1649 ep->X_add_number = o->val;
1650 return 0;
1651 }
1652
1653 return my_getSmallExpression (ep, reloc, str, percent_op);
1654}
1655
f0531ed6
JW		 1656/* Detect and handle implicitly zero load-store offsets. For example,
1657 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1658 an implicit offset was detected. */
1659
1660static bfd_boolean
89424b1d 1661riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
f0531ed6
JW		 1662{
1663 /* Check whether there is only a single bracketed expression left.
1664 If so, it must be the base register and the constant must be zero. */
1665 if (*s == '(' && strchr (s + 1, '(') == 0)
1666 {
89424b1d
MR		 1667 ep->X_op = O_constant;
1668 ep->X_add_number = 0;
f0531ed6
JW		 1669 return TRUE;
1670 }
1671
1672 return FALSE;
1673}
1674
54b2aec1
NC		 1675/* All RISC-V CSR instructions belong to one of these classes. */
1676
1677enum csr_insn_type
1678{
1679 INSN_NOT_CSR,
1680 INSN_CSRRW,
1681 INSN_CSRRS,
1682 INSN_CSRRC
1683};
1684
1685/* Return which CSR instruction is checking. */
1686
1687static enum csr_insn_type
1688riscv_csr_insn_type (insn_t insn)
1689{
1690 if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
1691 || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
1692 return INSN_CSRRW;
1693 else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
1694 || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
1695 return INSN_CSRRS;
1696 else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
1697 || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
1698 return INSN_CSRRC;
1699 else
1700 return INSN_NOT_CSR;
1701}
1702
1703/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1704 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1705 CSR address is 0x3. */
1706
1707static bfd_boolean
1708riscv_csr_read_only_check (insn_t insn)
1709{
1710 int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
1711 int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
1712 int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
1713 enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
1714
1715 if (readonly
1716 && (((csr_insn == INSN_CSRRS
1717 || csr_insn == INSN_CSRRC)
1718 && rs1 != 0)
1719 || csr_insn == INSN_CSRRW))
1720 return FALSE;
1721
1722 return TRUE;
1723}
1724
1a79004f
NC		 1725/* Return True if it is a privileged instruction. Otherwise, return FALSE.
1726
1727 uret is actually a N-ext instruction. So it is better to regard it as
1728 an user instruction rather than the priv instruction.
1729
1730 hret is used to return from traps in H-mode. H-mode is removed since
1731 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1732 Therefore, hret should be controlled by the hypervisor spec rather than
1733 priv spec in the future.
1734
1735 dret is defined in the debug spec, so it should be checked in the future,
1736 too. */
1737
1738static bfd_boolean
1739riscv_is_priv_insn (insn_t insn)
1740{
1741 return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
1742 || ((insn ^ MATCH_MRET) & MASK_MRET) == 0
1743 || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0
1744 || ((insn ^ MATCH_WFI) & MASK_WFI) == 0
1745 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1746 check it here to keep the compatible. Maybe we should issue warning
1747 if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
1748 We already have a similar check for CSR, but not yet for instructions.
1749 It would be good if we could check the spec versions both for CSR and
1750 instructions, but not here. */
1751 || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
1752}
1753
e23eba97
NC		 1754/* This routine assembles an instruction into its binary format. As a
1755 side effect, it sets the global variable imm_reloc to the type of
1756 relocation to do if one of the operands is an address expression. */
1757
1758static const char *
1759riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
629310ab 1760 bfd_reloc_code_real_type *imm_reloc, htab_t hash)
e23eba97
NC		 1761{
1762 char *s;
1763 const char *args;
1764 char c = 0;
1765 struct riscv_opcode *insn;
1766 char *argsStart;
1767 unsigned int regno;
1768 char save_c = 0;
1769 int argnum;
1770 const struct percent_op_match *p;
1771 const char *error = "unrecognized opcode";
54b2aec1
NC		 1772 /* Indicate we are assembling instruction with CSR. */
1773 bfd_boolean insn_with_csr = FALSE;
e23eba97
NC		 1774
1775 /* Parse the name of the instruction. Terminate the string if whitespace
629310ab 1776 is found so that str_hash_find only sees the name part of the string. */
e23eba97
NC		 1777 for (s = str; *s != '\0'; ++s)
1778 if (ISSPACE (*s))
1779 {
1780 save_c = *s;
1781 *s++ = '\0';
1782 break;
1783 }
1784
629310ab 1785 insn = (struct riscv_opcode *) str_hash_find (hash, str);
e23eba97
NC		 1786
1787 argsStart = s;
1788 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1789 {
1080bf78
JW		 1790 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
1791 continue;
1792
7e9ad3a3 1793 if (!riscv_multi_subset_supports (insn->insn_class))
e23eba97
NC		 1794 continue;
1795
1796 create_insn (ip, insn);
1797 argnum = 1;
1798
1799 imm_expr->X_op = O_absent;
1800 *imm_reloc = BFD_RELOC_UNUSED;
1801 p = percent_op_itype;
1802
1803 for (args = insn->args;; ++args)
1804 {
1805 s += strspn (s, " \t");
1806 switch (*args)
1807 {
1808 case '\0': /* End of args. */
1809 if (insn->pinfo != INSN_MACRO)
1810 {
1811 if (!insn->match_func (insn, ip->insn_opcode))
1812 break;
0e35537d
JW		 1813
1814 /* For .insn, insn->match and insn->mask are 0. */
1815 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
1816 ? ip->insn_opcode
1817 : insn->match) == 2
1818 && !riscv_opts.rvc)
e23eba97 1819 break;
54b2aec1 1820
1a79004f
NC		 1821 if (riscv_is_priv_insn (ip->insn_opcode))
1822 explicit_priv_attr = TRUE;
1823
54b2aec1
NC		 1824 /* Check if we write a read-only CSR by the CSR
1825 instruction. */
1826 if (insn_with_csr
1827 && riscv_opts.csr_check
1828 && !riscv_csr_read_only_check (ip->insn_opcode))
1829 {
1830 /* Restore the character in advance, since we want to
1831 report the detailed warning message here. */
1832 if (save_c)
1833 *(argsStart - 1) = save_c;
1834 as_warn (_("Read-only CSR is written `%s'"), str);
1835 insn_with_csr = FALSE;
1836 }
e23eba97
NC		 1837 }
1838 if (*s != '\0')
1839 break;
1840 /* Successful assembly. */
1841 error = NULL;
54b2aec1 1842 insn_with_csr = FALSE;
e23eba97
NC		 1843 goto out;
1844
1845 case 'C': /* RVC */
1846 switch (*++args)
1847 {
1848 case 's': /* RS1 x8-x15 */
1849 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1850 || !(regno >= 8 && regno <= 15))
1851 break;
1852 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1853 continue;
1854 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1855 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1856 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
1857 break;
1858 continue;
1859 case 't': /* RS2 x8-x15 */
1860 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1861 || !(regno >= 8 && regno <= 15))
1862 break;
1863 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1864 continue;
1865 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1866 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1867 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
1868 break;
1869 continue;
1870 case 'U': /* RS1, constrained to equal RD. */
1871 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1872 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
1873 break;
1874 continue;
1875 case 'V': /* RS2 */
1876 if (!reg_lookup (&s, RCLASS_GPR, &regno))
1877 break;
1878 INSERT_OPERAND (CRS2, *ip, regno);
1879 continue;
1880 case 'c': /* RS1, constrained to equal sp. */
1881 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1882 || regno != X_SP)
1883 break;
1884 continue;
ca0bc150
JW		 1885 case 'z': /* RS2, contrained to equal x0. */
1886 if (!reg_lookup (&s, RCLASS_GPR, &regno)
1887 || regno != 0)
1888 break;
1889 continue;
e23eba97
NC		 1890 case '>':
1891 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1892 || imm_expr->X_op != O_constant
1893 || imm_expr->X_add_number <= 0
1894 || imm_expr->X_add_number >= 64)
1895 break;
1896 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
dc1e8a47 1897 rvc_imm_done:
e23eba97
NC		 1898 s = expr_end;
1899 imm_expr->X_op = O_absent;
1900 continue;
1901 case '<':
1902 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1903 || imm_expr->X_op != O_constant
1904 || !VALID_RVC_IMM (imm_expr->X_add_number)
1905 || imm_expr->X_add_number <= 0
1906 || imm_expr->X_add_number >= 32)
1907 break;
1908 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1909 goto rvc_imm_done;
0e35537d
JW		 1910 case '8':
1911 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1912 || imm_expr->X_op != O_constant
1913 || !VALID_RVC_UIMM8 (imm_expr->X_add_number)
1914 || imm_expr->X_add_number < 0
1915 || imm_expr->X_add_number >= 256)
1916 break;
1917 ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
1918 goto rvc_imm_done;
e23eba97
NC		 1919 case 'i':
1920 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1921 || imm_expr->X_op != O_constant
1922 || imm_expr->X_add_number == 0
1923 || !VALID_RVC_SIMM3 (imm_expr->X_add_number))
1924 break;
1925 ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
1926 goto rvc_imm_done;
1927 case 'j':
1928 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1929 || imm_expr->X_op != O_constant
1930 || imm_expr->X_add_number == 0
1931 || !VALID_RVC_IMM (imm_expr->X_add_number))
1932 break;
1933 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1934 goto rvc_imm_done;
1935 case 'k':
f0531ed6
JW		 1936 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1937 continue;
e23eba97
NC		 1938 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1939 || imm_expr->X_op != O_constant
1940 || !VALID_RVC_LW_IMM (imm_expr->X_add_number))
1941 break;
1942 ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
1943 goto rvc_imm_done;
1944 case 'l':
f0531ed6
JW		 1945 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1946 continue;
e23eba97
NC		 1947 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1948 || imm_expr->X_op != O_constant
1949 || !VALID_RVC_LD_IMM (imm_expr->X_add_number))
1950 break;
1951 ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
1952 goto rvc_imm_done;
1953 case 'm':
f0531ed6
JW		 1954 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1955 continue;
e23eba97
NC		 1956 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1957 || imm_expr->X_op != O_constant
1958 || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number))
1959 break;
1960 ip->insn_opcode |=
1961 ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
1962 goto rvc_imm_done;
1963 case 'n':
f0531ed6
JW		 1964 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1965 continue;
e23eba97
NC		 1966 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1967 || imm_expr->X_op != O_constant
1968 || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number))
1969 break;
1970 ip->insn_opcode |=
1971 ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
1972 goto rvc_imm_done;
b416fe87
KC		 1973 case 'o':
1974 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1975 || imm_expr->X_op != O_constant
21a186f2
JW		 1976 /* C.addiw, c.li, and c.andi allow zero immediate.
1977 C.addi allows zero immediate as hint. Otherwise this
1978 is same as 'j'. */
b416fe87
KC		 1979 || !VALID_RVC_IMM (imm_expr->X_add_number))
1980 break;
1981 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1982 goto rvc_imm_done;
e23eba97
NC		 1983 case 'K':
1984 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1985 || imm_expr->X_op != O_constant
1986 || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number)
1987 || imm_expr->X_add_number == 0)
1988 break;
1989 ip->insn_opcode |=
1990 ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
1991 goto rvc_imm_done;
1992 case 'L':
1993 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1994 || imm_expr->X_op != O_constant
1995 || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number)
1996 || imm_expr->X_add_number == 0)
1997 break;
1998 ip->insn_opcode |=
1999 ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
2000 goto rvc_imm_done;
2001 case 'M':
f0531ed6
JW		 2002 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2003 continue;
e23eba97
NC		 2004 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2005 || imm_expr->X_op != O_constant
2006 || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number))
2007 break;
2008 ip->insn_opcode |=
2009 ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
2010 goto rvc_imm_done;
2011 case 'N':
f0531ed6
JW		 2012 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2013 continue;
e23eba97
NC		 2014 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2015 || imm_expr->X_op != O_constant
2016 || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number))
2017 break;
2018 ip->insn_opcode |=
2019 ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
2020 goto rvc_imm_done;
2021 case 'u':
2022 p = percent_op_utype;
2023 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
2024 break;
dc1e8a47 2025 rvc_lui:
e23eba97
NC		 2026 if (imm_expr->X_op != O_constant
2027 || imm_expr->X_add_number <= 0
2028 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
2029 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
2030 && (imm_expr->X_add_number <
2031 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
2032 break;
2033 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
2034 goto rvc_imm_done;
2035 case 'v':
2036 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2037 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
2038 || ((int32_t)imm_expr->X_add_number
2039 != imm_expr->X_add_number))
2040 break;
2041 imm_expr->X_add_number =
2042 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
2043 goto rvc_lui;
2044 case 'p':
2045 goto branch;
2046 case 'a':
2047 goto jump;
0e35537d
JW		 2048 case 'S': /* Floating-point RS1 x8-x15. */
2049 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2050 || !(regno >= 8 && regno <= 15))
2051 break;
2052 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2053 continue;
e23eba97
NC		 2054 case 'D': /* Floating-point RS2 x8-x15. */
2055 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2056 || !(regno >= 8 && regno <= 15))
2057 break;
2058 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2059 continue;
2060 case 'T': /* Floating-point RS2. */
2061 if (!reg_lookup (&s, RCLASS_FPR, &regno))
2062 break;
2063 INSERT_OPERAND (CRS2, *ip, regno);
2064 continue;
0e35537d
JW		 2065 case 'F':
2066 switch (*++args)
2067 {
4765cd61
JW		 2068 case '6':
2069 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2070 || imm_expr->X_op != O_constant
2071 || imm_expr->X_add_number < 0
2072 || imm_expr->X_add_number >= 64)
2073 {
2074 as_bad (_("bad value for funct6 field, "
2075 "value must be 0...64"));
2076 break;
2077 }
2078
2079 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
2080 imm_expr->X_op = O_absent;
2081 s = expr_end;
2082 continue;
0e35537d
JW		 2083 case '4':
2084 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2085 || imm_expr->X_op != O_constant
2086 || imm_expr->X_add_number < 0
2087 || imm_expr->X_add_number >= 16)
2088 {
2089 as_bad (_("bad value for funct4 field, "
2090 "value must be 0...15"));
2091 break;
2092 }
2093
2094 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
2095 imm_expr->X_op = O_absent;
2096 s = expr_end;
2097 continue;
2098 case '3':
2099 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2100 || imm_expr->X_op != O_constant
2101 || imm_expr->X_add_number < 0
2102 || imm_expr->X_add_number >= 8)
2103 {
2104 as_bad (_("bad value for funct3 field, "
2105 "value must be 0...7"));
2106 break;
2107 }
2108 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
2109 imm_expr->X_op = O_absent;
2110 s = expr_end;
2111 continue;
4765cd61
JW		 2112 case '2':
2113 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2114 || imm_expr->X_op != O_constant
2115 || imm_expr->X_add_number < 0
2116 || imm_expr->X_add_number >= 4)
2117 {
2118 as_bad (_("bad value for funct2 field, "
2119 "value must be 0...3"));
2120 break;
2121 }
2122 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number);
2123 imm_expr->X_op = O_absent;
2124 s = expr_end;
2125 continue;
0e35537d
JW		 2126 default:
2127 as_bad (_("bad compressed FUNCT field"
2128 " specifier 'CF%c'\n"),
2129 *args);
2130 }
2131 break;
2132
e23eba97
NC		 2133 default:
2134 as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
2135 }
2136 break;
2137
2138 case ',':
2139 ++argnum;
2140 if (*s++ == *args)
2141 continue;
2142 s--;
2143 break;
2144
2145 case '(':
2146 case ')':
2147 case '[':
2148 case ']':
2149 if (*s++ == *args)
2150 continue;
2151 break;
2152
2153 case '<': /* Shift amount, 0 - 31. */
2154 my_getExpression (imm_expr, s);
ca2fd32c 2155 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2156 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2157 as_bad (_("Improper shift amount (%lu)"),
2158 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2159 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
2160 imm_expr->X_op = O_absent;
2161 s = expr_end;
2162 continue;
2163
2164 case '>': /* Shift amount, 0 - (XLEN-1). */
2165 my_getExpression (imm_expr, s);
ca2fd32c 2166 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2167 if ((unsigned long) imm_expr->X_add_number >= xlen)
94f78a77
AW		 2168 as_bad (_("Improper shift amount (%lu)"),
2169 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2170 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
2171 imm_expr->X_op = O_absent;
2172 s = expr_end;
2173 continue;
2174
2175 case 'Z': /* CSRRxI immediate. */
2176 my_getExpression (imm_expr, s);
ca2fd32c 2177 check_absolute_expr (ip, imm_expr, FALSE);
e23eba97 2178 if ((unsigned long) imm_expr->X_add_number > 31)
94f78a77
AW		 2179 as_bad (_("Improper CSRxI immediate (%lu)"),
2180 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2181 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
2182 imm_expr->X_op = O_absent;
2183 s = expr_end;
2184 continue;
2185
2186 case 'E': /* Control register. */
54b2aec1 2187 insn_with_csr = TRUE;
1a79004f 2188 explicit_priv_attr = TRUE;
e23eba97
NC		 2189 if (reg_lookup (&s, RCLASS_CSR, &regno))
2190 INSERT_OPERAND (CSR, *ip, regno);
2191 else
2192 {
2193 my_getExpression (imm_expr, s);
ca2fd32c 2194 check_absolute_expr (ip, imm_expr, TRUE);
e23eba97 2195 if ((unsigned long) imm_expr->X_add_number > 0xfff)
94f78a77
AW		 2196 as_bad (_("Improper CSR address (%lu)"),
2197 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2198 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
2199 imm_expr->X_op = O_absent;
2200 s = expr_end;
2201 }
2202 continue;
2203
2204 case 'm': /* Rounding mode. */
2205 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
2206 {
2207 INSERT_OPERAND (RM, *ip, regno);
2208 continue;
2209 }
2210 break;
2211
2212 case 'P':
2213 case 'Q': /* Fence predecessor/successor. */
2214 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
2215 &regno))
2216 {
2217 if (*args == 'P')
2218 INSERT_OPERAND (PRED, *ip, regno);
2219 else
2220 INSERT_OPERAND (SUCC, *ip, regno);
2221 continue;
2222 }
2223 break;
2224
2225 case 'd': /* Destination register. */
2226 case 's': /* Source register. */
2227 case 't': /* Target register. */
0e35537d 2228 case 'r': /* rs3. */
e23eba97
NC		 2229 if (reg_lookup (&s, RCLASS_GPR, &regno))
2230 {
2231 c = *args;
2232 if (*s == ' ')
2233 ++s;
2234
2235 /* Now that we have assembled one operand, we use the args
2236 string to figure out where it goes in the instruction. */
2237 switch (c)
2238 {
2239 case 's':
2240 INSERT_OPERAND (RS1, *ip, regno);
2241 break;
2242 case 'd':
2243 INSERT_OPERAND (RD, *ip, regno);
2244 break;
2245 case 't':
2246 INSERT_OPERAND (RS2, *ip, regno);
2247 break;
0e35537d
JW		 2248 case 'r':
2249 INSERT_OPERAND (RS3, *ip, regno);
2250 break;
e23eba97
NC		 2251 }
2252 continue;
2253 }
2254 break;
2255
2256 case 'D': /* Floating point rd. */
2257 case 'S': /* Floating point rs1. */
2258 case 'T': /* Floating point rs2. */
2259 case 'U': /* Floating point rs1 and rs2. */
2260 case 'R': /* Floating point rs3. */
2261 if (reg_lookup (&s, RCLASS_FPR, &regno))
2262 {
2263 c = *args;
2264 if (*s == ' ')
2265 ++s;
2266 switch (c)
2267 {
2268 case 'D':
2269 INSERT_OPERAND (RD, *ip, regno);
2270 break;
2271 case 'S':
2272 INSERT_OPERAND (RS1, *ip, regno);
2273 break;
2274 case 'U':
2275 INSERT_OPERAND (RS1, *ip, regno);
2276 /* fallthru */
2277 case 'T':
2278 INSERT_OPERAND (RS2, *ip, regno);
2279 break;
2280 case 'R':
2281 INSERT_OPERAND (RS3, *ip, regno);
2282 break;
2283 }
2284 continue;
2285 }
2286
2287 break;
2288
2289 case 'I':
2290 my_getExpression (imm_expr, s);
2291 if (imm_expr->X_op != O_big
2292 && imm_expr->X_op != O_constant)
2293 break;
2294 normalize_constant_expr (imm_expr);
2295 s = expr_end;
2296 continue;
2297
2298 case 'A':
2299 my_getExpression (imm_expr, s);
2300 normalize_constant_expr (imm_expr);
2301 /* The 'A' format specifier must be a symbol. */
2302 if (imm_expr->X_op != O_symbol)
2303 break;
2304 *imm_reloc = BFD_RELOC_32;
2305 s = expr_end;
2306 continue;
2307
160d1b3d
SH		 2308 case 'B':
2309 my_getExpression (imm_expr, s);
2310 normalize_constant_expr (imm_expr);
2311 /* The 'B' format specifier must be a symbol or a constant. */
2312 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
2313 break;
2314 if (imm_expr->X_op == O_symbol)
2315 *imm_reloc = BFD_RELOC_32;
2316 s = expr_end;
2317 continue;
2318
e23eba97 2319 case 'j': /* Sign-extended immediate. */
e23eba97 2320 p = percent_op_itype;
f50fabe4 2321 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
e23eba97
NC		 2322 goto alu_op;
2323 case 'q': /* Store displacement. */
2324 p = percent_op_stype;
2325 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
2326 goto load_store;
2327 case 'o': /* Load displacement. */
2328 p = percent_op_itype;
2329 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
2330 goto load_store;
f50fabe4 2331 case '1': /* 4-operand add, must be %tprel_add. */
e23eba97 2332 p = percent_op_rtype;
f50fabe4
JW		 2333 goto alu_op;
2334 case '0': /* AMO "displacement," which must be zero. */
2335 p = percent_op_null;
dc1e8a47 2336 load_store:
f0531ed6 2337 if (riscv_handle_implicit_zero_offset (imm_expr, s))
e23eba97 2338 continue;
dc1e8a47 2339 alu_op:
e23eba97
NC		 2340 /* If this value won't fit into a 16 bit offset, then go
2341 find a macro that will generate the 32 bit offset
2342 code pattern. */
2343 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
2344 {
2345 normalize_constant_expr (imm_expr);
2346 if (imm_expr->X_op != O_constant
2347 || (*args == '0' && imm_expr->X_add_number != 0)
f50fabe4 2348 || (*args == '1')
e23eba97
NC		 2349 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
2350 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
2351 break;
2352 }
2353
2354 s = expr_end;
2355 continue;
2356
2357 case 'p': /* PC-relative offset. */
dc1e8a47 2358 branch:
e23eba97
NC		 2359 *imm_reloc = BFD_RELOC_12_PCREL;
2360 my_getExpression (imm_expr, s);
2361 s = expr_end;
2362 continue;
2363
2364 case 'u': /* Upper 20 bits. */
2365 p = percent_op_utype;
4288405d 2366 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
e23eba97 2367 {
4288405d
JW		 2368 if (imm_expr->X_op != O_constant)
2369 break;
2370
e23eba97
NC		 2371 if (imm_expr->X_add_number < 0
2372 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
2373 as_bad (_("lui expression not in range 0..1048575"));
2374
2375 *imm_reloc = BFD_RELOC_RISCV_HI20;
2376 imm_expr->X_add_number <<= RISCV_IMM_BITS;
2377 }
2378 s = expr_end;
2379 continue;
2380
2381 case 'a': /* 20-bit PC-relative offset. */
dc1e8a47 2382 jump:
e23eba97
NC		 2383 my_getExpression (imm_expr, s);
2384 s = expr_end;
2385 *imm_reloc = BFD_RELOC_RISCV_JMP;
2386 continue;
2387
2388 case 'c':
2389 my_getExpression (imm_expr, s);
2390 s = expr_end;
2391 if (strcmp (s, "@plt") == 0)
2392 {
2393 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2394 s += 4;
2395 }
2396 else
2397 *imm_reloc = BFD_RELOC_RISCV_CALL;
2398 continue;
0e35537d
JW		 2399 case 'O':
2400 switch (*++args)
2401 {
2402 case '4':
2403 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2404 || imm_expr->X_op != O_constant
2405 || imm_expr->X_add_number < 0
2406 || imm_expr->X_add_number >= 128
2407 || (imm_expr->X_add_number & 0x3) != 3)
2408 {
2409 as_bad (_("bad value for opcode field, "
2410 "value must be 0...127 and "
2411 "lower 2 bits must be 0x3"));
2412 break;
2413 }
2414
2415 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2416 imm_expr->X_op = O_absent;
2417 s = expr_end;
2418 continue;
2419 case '2':
2420 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2421 || imm_expr->X_op != O_constant
2422 || imm_expr->X_add_number < 0
2423 || imm_expr->X_add_number >= 3)
2424 {
2425 as_bad (_("bad value for opcode field, "
2426 "value must be 0...2"));
2427 break;
2428 }
2429
2430 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2431 imm_expr->X_op = O_absent;
2432 s = expr_end;
2433 continue;
2434 default:
2435 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args);
2436 }
2437 break;
2438
2439 case 'F':
2440 switch (*++args)
2441 {
2442 case '7':
2443 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2444 || imm_expr->X_op != O_constant
2445 || imm_expr->X_add_number < 0
2446 || imm_expr->X_add_number >= 128)
2447 {
2448 as_bad (_("bad value for funct7 field, "
2449 "value must be 0...127"));
2450 break;
2451 }
2452
2453 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2454 imm_expr->X_op = O_absent;
2455 s = expr_end;
2456 continue;
2457 case '3':
2458 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2459 || imm_expr->X_op != O_constant
2460 || imm_expr->X_add_number < 0
2461 || imm_expr->X_add_number >= 8)
2462 {
2463 as_bad (_("bad value for funct3 field, "
2464 "value must be 0...7"));
2465 break;
2466 }
2467
2468 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2469 imm_expr->X_op = O_absent;
2470 s = expr_end;
2471 continue;
2472 case '2':
2473 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2474 || imm_expr->X_op != O_constant
2475 || imm_expr->X_add_number < 0
2476 || imm_expr->X_add_number >= 4)
2477 {
2478 as_bad (_("bad value for funct2 field, "
2479 "value must be 0...3"));
2480 break;
2481 }
2482
2483 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2484 imm_expr->X_op = O_absent;
2485 s = expr_end;
2486 continue;
2487
2488 default:
2489 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args);
2490 }
2491 break;
e23eba97 2492
e925c834
JW		 2493 case 'z':
2494 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2495 || imm_expr->X_op != O_constant
2496 || imm_expr->X_add_number != 0)
2497 break;
2498 s = expr_end;
2499 imm_expr->X_op = O_absent;
2500 continue;
2501
e23eba97
NC		 2502 default:
2503 as_fatal (_("internal error: bad argument type %c"), *args);
2504 }
2505 break;
2506 }
2507 s = argsStart;
2508 error = _("illegal operands");
54b2aec1 2509 insn_with_csr = FALSE;
e23eba97
NC		 2510 }
2511
dc1e8a47 2512 out:
e23eba97
NC		 2513 /* Restore the character we might have clobbered above. */
2514 if (save_c)
2515 *(argsStart - 1) = save_c;
2516
2517 return error;
2518}
2519
2520void
2521md_assemble (char *str)
2522{
2523 struct riscv_cl_insn insn;
2524 expressionS imm_expr;
2525 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2526
8f595e9b
NC		 2527 /* The arch and priv attributes should be set before assembling. */
2528 if (!start_assemble)
2529 {
2530 start_assemble = TRUE;
e23eba97 2531
8f595e9b
NC		 2532 /* Set the default_priv_spec according to the priv attributes. */
2533 if (!riscv_set_default_priv_spec (NULL))
2534 return;
2535 }
2536
2537 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
2dc8dd17 2538
e23eba97
NC		 2539 if (error)
2540 {
2541 as_bad ("%s `%s'", error, str);
2542 return;
2543 }
2544
2545 if (insn.insn_mo->pinfo == INSN_MACRO)
2546 macro (&insn, &imm_expr, &imm_reloc);
2547 else
2548 append_insn (&insn, &imm_expr, imm_reloc);
2549}
2550
2551const char *
2552md_atof (int type, char *litP, int *sizeP)
2553{
2554 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2555}
2556
2557void
2558md_number_to_chars (char *buf, valueT val, int n)
2559{
2560 number_to_chars_littleendian (buf, val, n);
2561}
2562
2563const char *md_shortopts = "O::g::G:";
2564
2565enum options
2566{
2922d21d 2567 OPTION_MARCH = OPTION_MD_BASE,
e23eba97
NC		 2568 OPTION_PIC,
2569 OPTION_NO_PIC,
2922d21d 2570 OPTION_MABI,
71060565
JW		 2571 OPTION_RELAX,
2572 OPTION_NO_RELAX,
2dc8dd17
JW		 2573 OPTION_ARCH_ATTR,
2574 OPTION_NO_ARCH_ATTR,
2ca89224
NC		 2575 OPTION_CSR_CHECK,
2576 OPTION_NO_CSR_CHECK,
8f595e9b
NC		 2577 OPTION_MISA_SPEC,
2578 OPTION_MPRIV_SPEC,
e23eba97
NC		 2579 OPTION_END_OF_ENUM
2580};
2581
2582struct option md_longopts[] =
2583{
e23eba97
NC		 2584 {"march", required_argument, NULL, OPTION_MARCH},
2585 {"fPIC", no_argument, NULL, OPTION_PIC},
2586 {"fpic", no_argument, NULL, OPTION_PIC},
2587 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2922d21d 2588 {"mabi", required_argument, NULL, OPTION_MABI},
71060565
JW		 2589 {"mrelax", no_argument, NULL, OPTION_RELAX},
2590 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2dc8dd17
JW		 2591 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
2592 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
2ca89224
NC		 2593 {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
2594 {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
8f595e9b
NC		 2595 {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
2596 {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
e23eba97
NC		 2597
2598 {NULL, no_argument, NULL, 0}
2599};
2600size_t md_longopts_size = sizeof (md_longopts);
2601
2922d21d
AW		 2602enum float_abi {
2603 FLOAT_ABI_DEFAULT = -1,
2604 FLOAT_ABI_SOFT,
2605 FLOAT_ABI_SINGLE,
2606 FLOAT_ABI_DOUBLE,
2607 FLOAT_ABI_QUAD
e23eba97 2608};
2922d21d
AW		 2609static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
2610
2611static void
7f999549 2612riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
2922d21d
AW		 2613{
2614 abi_xlen = new_xlen;
2615 float_abi = new_float_abi;
7f999549 2616 rve_abi = rve;
2922d21d 2617}
e23eba97
NC		 2618
2619int
2620md_parse_option (int c, const char *arg)
2621{
2622 switch (c)
2623 {
e23eba97 2624 case OPTION_MARCH:
8f595e9b
NC		 2625 /* riscv_after_parse_args will call riscv_set_arch to parse
2626 the architecture. */
2627 default_arch_with_ext = arg;
e23eba97
NC		 2628 break;
2629
2630 case OPTION_NO_PIC:
2631 riscv_opts.pic = FALSE;
2632 break;
2633
2634 case OPTION_PIC:
2635 riscv_opts.pic = TRUE;
2636 break;
2637
2922d21d
AW		 2638 case OPTION_MABI:
2639 if (strcmp (arg, "ilp32") == 0)
7f999549
JW		 2640 riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
2641 else if (strcmp (arg, "ilp32e") == 0)
2642 riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
2922d21d 2643 else if (strcmp (arg, "ilp32f") == 0)
7f999549 2644 riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2645 else if (strcmp (arg, "ilp32d") == 0)
7f999549 2646 riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2647 else if (strcmp (arg, "ilp32q") == 0)
7f999549 2648 riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
2922d21d 2649 else if (strcmp (arg, "lp64") == 0)
7f999549 2650 riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
2922d21d 2651 else if (strcmp (arg, "lp64f") == 0)
7f999549 2652 riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
2922d21d 2653 else if (strcmp (arg, "lp64d") == 0)
7f999549 2654 riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
2922d21d 2655 else if (strcmp (arg, "lp64q") == 0)
7f999549 2656 riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
2922d21d
AW		 2657 else
2658 return 0;
2659 break;
2660
71060565
JW		 2661 case OPTION_RELAX:
2662 riscv_opts.relax = TRUE;
2663 break;
2664
2665 case OPTION_NO_RELAX:
2666 riscv_opts.relax = FALSE;
2667 break;
2668
2dc8dd17
JW		 2669 case OPTION_ARCH_ATTR:
2670 riscv_opts.arch_attr = TRUE;
2671 break;
2672
2673 case OPTION_NO_ARCH_ATTR:
2674 riscv_opts.arch_attr = FALSE;
2675 break;
2676
2ca89224
NC		 2677 case OPTION_CSR_CHECK:
2678 riscv_opts.csr_check = TRUE;
2679 break;
2680
2681 case OPTION_NO_CSR_CHECK:
2682 riscv_opts.csr_check = FALSE;
2683 break;
2684
8f595e9b
NC		 2685 case OPTION_MISA_SPEC:
2686 return riscv_set_default_isa_spec (arg);
2687
2688 case OPTION_MPRIV_SPEC:
2689 return riscv_set_default_priv_spec (arg);
2690
e23eba97
NC		 2691 default:
2692 return 0;
2693 }
2694
2695 return 1;
2696}
2697
2698void
2699riscv_after_parse_args (void)
2700{
8f595e9b
NC		 2701 /* The --with-arch is optional for now, so we have to set the xlen
2702 according to the default_arch, which is set by the --targte, first.
2703 Then, we use the xlen to set the default_arch_with_ext if the
2704 -march and --with-arch are not set. */
e23eba97
NC		 2705 if (xlen == 0)
2706 {
2707 if (strcmp (default_arch, "riscv32") == 0)
2708 xlen = 32;
2709 else if (strcmp (default_arch, "riscv64") == 0)
2710 xlen = 64;
2711 else
2712 as_bad ("unknown default architecture `%s'", default_arch);
2713 }
8f595e9b
NC		 2714 if (default_arch_with_ext == NULL)
2715 default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
2716
2717 /* Initialize the hash table for extensions with default version. */
2718 ext_version_hash = init_ext_version_hash (riscv_ext_version_table);
2719
2720 /* If the -misa-spec isn't set, then we set the default ISA spec according
2721 to DEFAULT_RISCV_ISA_SPEC. */
2722 if (default_isa_spec == ISA_SPEC_CLASS_NONE)
2723 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
2922d21d 2724
8f595e9b
NC		 2725 /* Set the architecture according to -march or or --with-arch. */
2726 riscv_set_arch (default_arch_with_ext);
2922d21d
AW		 2727
2728 /* Add the RVC extension, regardless of -march, to support .option rvc. */
fecb9c46 2729 riscv_set_rvc (FALSE);
1080bf78 2730 if (riscv_subset_supports ("c"))
2922d21d 2731 riscv_set_rvc (TRUE);
2922d21d 2732
7f999549
JW		 2733 /* Enable RVE if specified by the -march option. */
2734 riscv_set_rve (FALSE);
1080bf78 2735 if (riscv_subset_supports ("e"))
7f999549
JW		 2736 riscv_set_rve (TRUE);
2737
8f595e9b
NC		 2738 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2739 according to DEFAULT_PRIV_SPEC. */
2740 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
2741 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
2742
2922d21d
AW		 2743 /* Infer ABI from ISA if not specified on command line. */
2744 if (abi_xlen == 0)
2745 abi_xlen = xlen;
2746 else if (abi_xlen > xlen)
2747 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
2748 else if (abi_xlen < xlen)
2749 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
2750
2751 if (float_abi == FLOAT_ABI_DEFAULT)
2752 {
1080bf78 2753 riscv_subset_t *subset;
2922d21d
AW		 2754
2755 /* Assume soft-float unless D extension is present. */
2756 float_abi = FLOAT_ABI_SOFT;
2757
1080bf78 2758 for (subset = riscv_subsets.head; subset != NULL; subset = subset->next)
cc917fd9
KC		 2759 {
2760 if (strcasecmp (subset->name, "D") == 0)
2761 float_abi = FLOAT_ABI_DOUBLE;
2762 if (strcasecmp (subset->name, "Q") == 0)
2763 float_abi = FLOAT_ABI_QUAD;
2764 }
2922d21d
AW		 2765 }
2766
7f999549
JW		 2767 if (rve_abi)
2768 elf_flags |= EF_RISCV_RVE;
2769
2922d21d
AW		 2770 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2771 elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1));
0ac2b354
AB		 2772
2773 /* If the CIE to be produced has not been overridden on the command line,
2774 then produce version 3 by default. This allows us to use the full
2775 range of registers in a .cfi_return_column directive. */
2776 if (flag_dwarf_cie_version == -1)
2777 flag_dwarf_cie_version = 3;
e23eba97
NC		 2778}
2779
2780long
2781md_pcrel_from (fixS *fixP)
2782{
2783 return fixP->fx_where + fixP->fx_frag->fr_address;
2784}
2785
2786/* Apply a fixup to the object file. */
2787
2788void
2789md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2790{
45f76423 2791 unsigned int subtype;
e23eba97 2792 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
45f76423 2793 bfd_boolean relaxable = FALSE;
c1b465c9 2794 offsetT loc;
a6cbf936 2795 segT sub_segment;
e23eba97
NC		 2796
2797 /* Remember value for tc_gen_reloc. */
2798 fixP->fx_addnumber = *valP;
2799
2800 switch (fixP->fx_r_type)
2801 {
e23eba97
NC		 2802 case BFD_RELOC_RISCV_HI20:
2803 case BFD_RELOC_RISCV_LO12_I:
2804 case BFD_RELOC_RISCV_LO12_S:
45f76423
AW		 2805 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2806 | bfd_getl32 (buf), buf);
a5ec5e3f
AW		 2807 if (fixP->fx_addsy == NULL)
2808 fixP->fx_done = TRUE;
45f76423
AW		 2809 relaxable = TRUE;
2810 break;
2811
2812 case BFD_RELOC_RISCV_GOT_HI20:
e23eba97
NC		 2813 case BFD_RELOC_RISCV_ADD8:
2814 case BFD_RELOC_RISCV_ADD16:
2815 case BFD_RELOC_RISCV_ADD32:
2816 case BFD_RELOC_RISCV_ADD64:
45f76423 2817 case BFD_RELOC_RISCV_SUB6:
e23eba97
NC		 2818 case BFD_RELOC_RISCV_SUB8:
2819 case BFD_RELOC_RISCV_SUB16:
2820 case BFD_RELOC_RISCV_SUB32:
2821 case BFD_RELOC_RISCV_SUB64:
45f76423
AW		 2822 case BFD_RELOC_RISCV_RELAX:
2823 break;
2824
2825 case BFD_RELOC_RISCV_TPREL_HI20:
2826 case BFD_RELOC_RISCV_TPREL_LO12_I:
2827 case BFD_RELOC_RISCV_TPREL_LO12_S:
2828 case BFD_RELOC_RISCV_TPREL_ADD:
2829 relaxable = TRUE;
2830 /* Fall through. */
2831
2832 case BFD_RELOC_RISCV_TLS_GOT_HI20:
2833 case BFD_RELOC_RISCV_TLS_GD_HI20:
2834 case BFD_RELOC_RISCV_TLS_DTPREL32:
2835 case BFD_RELOC_RISCV_TLS_DTPREL64:
e294484e
AW		 2836 if (fixP->fx_addsy != NULL)
2837 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2838 else
2839 as_bad_where (fixP->fx_file, fixP->fx_line,
2840 _("TLS relocation against a constant"));
e23eba97
NC		 2841 break;
2842
e23eba97 2843 case BFD_RELOC_32:
a6cbf936
KLC		 2844 /* Use pc-relative relocation for FDE initial location.
2845 The symbol address in .eh_frame may be adjusted in
2846 _bfd_elf_discard_section_eh_frame, and the content of
2847 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2848 Therefore, we cannot insert a relocation whose addend symbol is
2849 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2850 if (fixP->fx_addsy && fixP->fx_subsy
2851 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
2852 && strcmp (sub_segment->name, ".eh_frame") == 0
2853 && S_GET_VALUE (fixP->fx_subsy)
2854 == fixP->fx_frag->fr_address + fixP->fx_where)
2855 {
2856 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
2857 fixP->fx_subsy = NULL;
2858 break;
2859 }
2860 /* Fall through. */
2861 case BFD_RELOC_64:
e23eba97
NC		 2862 case BFD_RELOC_16:
2863 case BFD_RELOC_8:
45f76423 2864 case BFD_RELOC_RISCV_CFA:
e23eba97
NC		 2865 if (fixP->fx_addsy && fixP->fx_subsy)
2866 {
2867 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2868 fixP->fx_next->fx_addsy = fixP->fx_subsy;
2869 fixP->fx_next->fx_subsy = NULL;
2870 fixP->fx_next->fx_offset = 0;
2871 fixP->fx_subsy = NULL;
2872
2873 switch (fixP->fx_r_type)
2874 {
2875 case BFD_RELOC_64:
2876 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
2877 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
2878 break;
2879
2880 case BFD_RELOC_32:
2881 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
2882 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2883 break;
2884
2885 case BFD_RELOC_16:
2886 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
2887 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2888 break;
2889
2890 case BFD_RELOC_8:
2891 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
2892 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
073808ed 2893 break;
e23eba97 2894
45f76423
AW		 2895 case BFD_RELOC_RISCV_CFA:
2896 /* Load the byte to get the subtype. */
c1b465c9
KLC		 2897 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
2898 loc = fixP->fx_frag->fr_fix - (subtype & 7);
45f76423
AW		 2899 switch (subtype)
2900 {
2901 case DW_CFA_advance_loc1:
c1b465c9
KLC		 2902 fixP->fx_where = loc + 1;
2903 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2904 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
2905 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
2906 break;
2907
2908 case DW_CFA_advance_loc2:
2909 fixP->fx_size = 2;
45f76423 2910 fixP->fx_next->fx_size = 2;
c1b465c9
KLC		 2911 fixP->fx_where = loc + 1;
2912 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 2913 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
2914 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2915 break;
2916
2917 case DW_CFA_advance_loc4:
2918 fixP->fx_size = 4;
45f76423 2919 fixP->fx_next->fx_size = 4;
c1b465c9
KLC		 2920 fixP->fx_where = loc;
2921 fixP->fx_next->fx_where = loc;
45f76423
AW		 2922 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
2923 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2924 break;
2925
2926 default:
2927 if (subtype < 0x80 && (subtype & 0x40))
2928 {
2929 /* DW_CFA_advance_loc */
2aece2ba
KLC		 2930 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
2931 fixP->fx_next->fx_frag = fixP->fx_frag;
45f76423
AW		 2932 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
2933 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
2934 }
2935 else
2936 as_fatal (_("internal error: bad CFA value #%d"), subtype);
2937 break;
2938 }
2939 break;
2940
e23eba97
NC		 2941 default:
2942 /* This case is unreachable. */
2943 abort ();
2944 }
2945 }
2946 /* Fall through. */
2947
2948 case BFD_RELOC_RVA:
2949 /* If we are deleting this reloc entry, we must fill in the
2950 value now. This can happen if we have a .word which is not
2951 resolved when it appears but is later defined. */
2952 if (fixP->fx_addsy == NULL)
2953 {
2954 gas_assert (fixP->fx_size <= sizeof (valueT));
2955 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
2956 fixP->fx_done = 1;
2957 }
2958 break;
2959
2960 case BFD_RELOC_RISCV_JMP:
2961 if (fixP->fx_addsy)
2962 {
2963 /* Fill in a tentative value to improve objdump readability. */
2964 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2965 bfd_vma delta = target - md_pcrel_from (fixP);
2966 bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
2967 }
2968 break;
2969
2970 case BFD_RELOC_12_PCREL:
2971 if (fixP->fx_addsy)
2972 {
2973 /* Fill in a tentative value to improve objdump readability. */
2974 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2975 bfd_vma delta = target - md_pcrel_from (fixP);
2976 bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
2977 }
2978 break;
2979
2980 case BFD_RELOC_RISCV_RVC_BRANCH:
2981 if (fixP->fx_addsy)
2982 {
2983 /* Fill in a tentative value to improve objdump readability. */
2984 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2985 bfd_vma delta = target - md_pcrel_from (fixP);
2986 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
2987 }
2988 break;
2989
2990 case BFD_RELOC_RISCV_RVC_JUMP:
2991 if (fixP->fx_addsy)
2992 {
2993 /* Fill in a tentative value to improve objdump readability. */
2994 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2995 bfd_vma delta = target - md_pcrel_from (fixP);
2996 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
2997 }
2998 break;
2999
e23eba97
NC		 3000 case BFD_RELOC_RISCV_CALL:
3001 case BFD_RELOC_RISCV_CALL_PLT:
45f76423
AW		 3002 relaxable = TRUE;
3003 break;
3004
9d06997a 3005 case BFD_RELOC_RISCV_PCREL_HI20:
45f76423
AW		 3006 case BFD_RELOC_RISCV_PCREL_LO12_S:
3007 case BFD_RELOC_RISCV_PCREL_LO12_I:
9d06997a
PD		 3008 relaxable = riscv_opts.relax;
3009 break;
3010
e23eba97
NC		 3011 case BFD_RELOC_RISCV_ALIGN:
3012 break;
3013
3014 default:
3015 /* We ignore generic BFD relocations we don't know about. */
3016 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
3017 as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type);
3018 }
45f76423 3019
e294484e
AW		 3020 if (fixP->fx_subsy != NULL)
3021 as_bad_where (fixP->fx_file, fixP->fx_line,
3022 _("unsupported symbol subtraction"));
3023
45f76423
AW		 3024 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3025 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
3026 {
3027 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3028 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
3029 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
3030 }
3031}
3032
3033/* Because the value of .cfi_remember_state may changed after relaxation,
3034 we insert a fix to relocate it again in link-time. */
3035
3036void
3037riscv_pre_output_hook (void)
3038{
3039 const frchainS *frch;
72393fd1
JW		 3040 segT s;
3041
3042 /* Save the current segment info. */
3043 segT seg = now_seg;
3044 subsegT subseg = now_subseg;
45f76423
AW		 3045
3046 for (s = stdoutput->sections; s; s = s->next)
3047 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
3048 {
7cb7b948 3049 fragS *frag;
45f76423
AW		 3050
3051 for (frag = frch->frch_root; frag; frag = frag->fr_next)
3052 {
3053 if (frag->fr_type == rs_cfa)
3054 {
45f76423 3055 expressionS exp;
8d1015a8 3056 expressionS *symval;
45f76423 3057
8d1015a8 3058 symval = symbol_get_value_expression (frag->fr_symbol);
45f76423 3059 exp.X_op = O_subtract;
8d1015a8 3060 exp.X_add_symbol = symval->X_add_symbol;
45f76423 3061 exp.X_add_number = 0;
8d1015a8 3062 exp.X_op_symbol = symval->X_op_symbol;
45f76423 3063
72393fd1
JW		 3064 /* We must set the segment before creating a frag after all
3065 frag chains have been chained together. */
3066 subseg_set (s, frch->frch_subseg);
3067
c1b465c9 3068 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
45f76423
AW		 3069 BFD_RELOC_RISCV_CFA);
3070 }
3071 }
3072 }
72393fd1
JW		 3073
3074 /* Restore the original segment info. */
3075 subseg_set (seg, subseg);
e23eba97
NC		 3076}
3077
45f76423 3078
e23eba97
NC		 3079/* This structure is used to hold a stack of .option values. */
3080
3081struct riscv_option_stack
3082{
3083 struct riscv_option_stack *next;
3084 struct riscv_set_options options;
3085};
3086
3087static struct riscv_option_stack *riscv_opts_stack;
3088
3089/* Handle the .option pseudo-op. */
3090
3091static void
3092s_riscv_option (int x ATTRIBUTE_UNUSED)
3093{
3094 char *name = input_line_pointer, ch;
3095
3096 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3097 ++input_line_pointer;
3098 ch = *input_line_pointer;
3099 *input_line_pointer = '\0';
3100
3101 if (strcmp (name, "rvc") == 0)
3102 riscv_set_rvc (TRUE);
3103 else if (strcmp (name, "norvc") == 0)
3104 riscv_set_rvc (FALSE);
3105 else if (strcmp (name, "pic") == 0)
3106 riscv_opts.pic = TRUE;
3107 else if (strcmp (name, "nopic") == 0)
3108 riscv_opts.pic = FALSE;
45f76423
AW		 3109 else if (strcmp (name, "relax") == 0)
3110 riscv_opts.relax = TRUE;
3111 else if (strcmp (name, "norelax") == 0)
3112 riscv_opts.relax = FALSE;
2ca89224
NC		 3113 else if (strcmp (name, "csr-check") == 0)
3114 riscv_opts.csr_check = TRUE;
3115 else if (strcmp (name, "no-csr-check") == 0)
3116 riscv_opts.csr_check = FALSE;
e23eba97
NC		 3117 else if (strcmp (name, "push") == 0)
3118 {
3119 struct riscv_option_stack *s;
3120
3121 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
3122 s->next = riscv_opts_stack;
3123 s->options = riscv_opts;
3124 riscv_opts_stack = s;
3125 }
3126 else if (strcmp (name, "pop") == 0)
3127 {
3128 struct riscv_option_stack *s;
3129
3130 s = riscv_opts_stack;
3131 if (s == NULL)
3132 as_bad (_(".option pop with no .option push"));
3133 else
3134 {
3135 riscv_opts = s->options;
3136 riscv_opts_stack = s->next;
3137 free (s);
3138 }
3139 }
3140 else
3141 {
3142 as_warn (_("Unrecognized .option directive: %s\n"), name);
3143 }
3144 *input_line_pointer = ch;
3145 demand_empty_rest_of_line ();
3146}
3147
3148/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3149 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3150 use in DWARF debug information. */
3151
3152static void
3153s_dtprel (int bytes)
3154{
3155 expressionS ex;
3156 char *p;
3157
3158 expression (&ex);
3159
3160 if (ex.X_op != O_symbol)
3161 {
3162 as_bad (_("Unsupported use of %s"), (bytes == 8
3163 ? ".dtpreldword"
3164 : ".dtprelword"));
3165 ignore_rest_of_line ();
3166 }
3167
3168 p = frag_more (bytes);
3169 md_number_to_chars (p, 0, bytes);
3170 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
3171 (bytes == 8
3172 ? BFD_RELOC_RISCV_TLS_DTPREL64
3173 : BFD_RELOC_RISCV_TLS_DTPREL32));
3174
3175 demand_empty_rest_of_line ();
3176}
3177
3178/* Handle the .bss pseudo-op. */
3179
3180static void
3181s_bss (int ignore ATTRIBUTE_UNUSED)
3182{
3183 subseg_set (bss_section, 0);
3184 demand_empty_rest_of_line ();
3185}
3186
e23eba97 3187static void
d115ab8e 3188riscv_make_nops (char *buf, bfd_vma bytes)
e23eba97 3189{
d115ab8e 3190 bfd_vma i = 0;
e23eba97 3191
e5b737de
AW		 3192 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3193 means we are not within a valid instruction sequence. It is thus safe
3194 to use a zero byte, even though that is not a valid instruction. */
3195 if (bytes % 2 == 1)
3196 buf[i++] = 0;
3197
3198 /* Use at most one 2-byte NOP. */
3199 if ((bytes - i) % 4 == 2)
e23eba97 3200 {
e5b737de 3201 md_number_to_chars (buf + i, RVC_NOP, 2);
d115ab8e 3202 i += 2;
e23eba97
NC		 3203 }
3204
e5b737de 3205 /* Fill the remainder with 4-byte NOPs. */
d115ab8e
AW		 3206 for ( ; i < bytes; i += 4)
3207 md_number_to_chars (buf + i, RISCV_NOP, 4);
3208}
e23eba97 3209
d115ab8e
AW		 3210/* Called from md_do_align. Used to create an alignment frag in a
3211 code section by emitting a worst-case NOP sequence that the linker
3212 will later relax to the correct number of NOPs. We can't compute
3213 the correct alignment now because of other linker relaxations. */
3214
3215bfd_boolean
3216riscv_frag_align_code (int n)
3217{
e5b737de 3218 bfd_vma bytes = (bfd_vma) 1 << n;
36877bfb
JW		 3219 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
3220 bfd_vma worst_case_bytes = bytes - insn_alignment;
3221 char *nops;
ed0816bd 3222 expressionS ex;
d115ab8e 3223
36877bfb
JW		 3224 /* If we are moving to a smaller alignment than the instruction size, then no
3225 alignment is required. */
3226 if (bytes <= insn_alignment)
3227 return TRUE;
3228
d115ab8e
AW		 3229 /* When not relaxing, riscv_handle_align handles code alignment. */
3230 if (!riscv_opts.relax)
3231 return FALSE;
e23eba97 3232
e80ae190
JW		 3233 nops = frag_more (worst_case_bytes);
3234
ed0816bd
PD		 3235 ex.X_op = O_constant;
3236 ex.X_add_number = worst_case_bytes;
d115ab8e 3237
ed0816bd 3238 riscv_make_nops (nops, worst_case_bytes);
e23eba97 3239
ed0816bd
PD		 3240 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
3241 &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
e23eba97 3242
d115ab8e
AW		 3243 return TRUE;
3244}
e23eba97 3245
d115ab8e
AW		 3246/* Implement HANDLE_ALIGN. */
3247
3248void
3249riscv_handle_align (fragS *fragP)
3250{
3251 switch (fragP->fr_type)
3252 {
3253 case rs_align_code:
3254 /* When relaxing, riscv_frag_align_code handles code alignment. */
3255 if (!riscv_opts.relax)
3256 {
e80ae190
JW		 3257 bfd_signed_vma bytes = (fragP->fr_next->fr_address
3258 - fragP->fr_address - fragP->fr_fix);
3259 /* We have 4 byte uncompressed nops. */
3260 bfd_signed_vma size = 4;
3261 bfd_signed_vma excess = bytes % size;
3262 char *p = fragP->fr_literal + fragP->fr_fix;
3263
3264 if (bytes <= 0)
d115ab8e
AW		 3265 break;
3266
e80ae190
JW		 3267 /* Insert zeros or compressed nops to get 4 byte alignment. */
3268 if (excess)
3269 {
3270 riscv_make_nops (p, excess);
3271 fragP->fr_fix += excess;
3272 p += excess;
3273 }
3274
3275 /* Insert variable number of 4 byte uncompressed nops. */
3276 riscv_make_nops (p, size);
3277 fragP->fr_var = size;
d115ab8e
AW		 3278 }
3279 break;
3280
3281 default:
3282 break;
3283 }
e23eba97
NC		 3284}
3285
3286int
3287md_estimate_size_before_relax (fragS *fragp, asection *segtype)
3288{
3289 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
3290}
3291
3292/* Translate internal representation of relocation info to BFD target
3293 format. */
3294
3295arelent *
3296tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3297{
3298 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
3299
3300 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3301 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3302 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3303 reloc->addend = fixp->fx_addnumber;
3304
3305 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3306 if (reloc->howto == NULL)
3307 {
3308 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
3309 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
3310 {
3311 /* We don't have R_RISCV_8/16, but for this special case,
3312 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3313 return reloc;
3314 }
3315
3316 as_bad_where (fixp->fx_file, fixp->fx_line,
3317 _("cannot represent %s relocation in object file"),
3318 bfd_get_reloc_code_name (fixp->fx_r_type));
3319 return NULL;
3320 }
3321
3322 return reloc;
3323}
3324
3325int
3326riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
3327{
3328 if (RELAX_BRANCH_P (fragp->fr_subtype))
3329 {
3330 offsetT old_var = fragp->fr_var;
3331 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
3332 return fragp->fr_var - old_var;
3333 }
3334
3335 return 0;
3336}
3337
3338/* Expand far branches to multi-instruction sequences. */
3339
3340static void
3341md_convert_frag_branch (fragS *fragp)
3342{
3343 bfd_byte *buf;
3344 expressionS exp;
3345 fixS *fixp;
3346 insn_t insn;
3347 int rs1, reloc;
3348
3349 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
3350
3351 exp.X_op = O_symbol;
3352 exp.X_add_symbol = fragp->fr_symbol;
3353 exp.X_add_number = fragp->fr_offset;
3354
3355 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
3356
3357 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
3358 {
3359 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3360 {
3361 case 8:
3362 case 4:
3363 /* Expand the RVC branch into a RISC-V one. */
3364 insn = bfd_getl16 (buf);
3365 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
3366 if ((insn & MASK_C_J) == MATCH_C_J)
3367 insn = MATCH_JAL;
3368 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
3369 insn = MATCH_JAL | (X_RA << OP_SH_RD);
3370 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
3371 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
3372 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
3373 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
3374 else
3375 abort ();
3376 bfd_putl32 (insn, buf);
3377 break;
3378
3379 case 6:
3380 /* Invert the branch condition. Branch over the jump. */
3381 insn = bfd_getl16 (buf);
3382 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
3383 insn |= ENCODE_RVC_B_IMM (6);
3384 bfd_putl16 (insn, buf);
3385 buf += 2;
3386 goto jump;
3387
3388 case 2:
3389 /* Just keep the RVC branch. */
3390 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3391 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
3392 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3393 2, &exp, FALSE, reloc);
3394 buf += 2;
3395 goto done;
3396
3397 default:
1d65abb5 3398 abort ();
e23eba97
NC		 3399 }
3400 }
3401
3402 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3403 {
3404 case 8:
3405 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
3406
3407 /* Invert the branch condition. Branch over the jump. */
3408 insn = bfd_getl32 (buf);
3409 insn ^= MATCH_BEQ ^ MATCH_BNE;
3410 insn |= ENCODE_SBTYPE_IMM (8);
3411 md_number_to_chars ((char *) buf, insn, 4);
3412 buf += 4;
3413
dc1e8a47 3414 jump:
e23eba97
NC		 3415 /* Jump to the target. */
3416 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3417 4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
3418 md_number_to_chars ((char *) buf, MATCH_JAL, 4);
3419 buf += 4;
3420 break;
3421
3422 case 4:
3423 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3424 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
3425 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3426 4, &exp, FALSE, reloc);
3427 buf += 4;
3428 break;
3429
3430 default:
3431 abort ();
3432 }
3433
dc1e8a47 3434 done:
e23eba97
NC		 3435 fixp->fx_file = fragp->fr_file;
3436 fixp->fx_line = fragp->fr_line;
3437
3438 gas_assert (buf == (bfd_byte *)fragp->fr_literal
3439 + fragp->fr_fix + fragp->fr_var);
3440
3441 fragp->fr_fix += fragp->fr_var;
3442}
3443
3444/* Relax a machine dependent frag. This returns the amount by which
3445 the current size of the frag should change. */
3446
3447void
3448md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3449 fragS *fragp)
3450{
3451 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
3452 md_convert_frag_branch (fragp);
3453}
3454
3455void
3456md_show_usage (FILE *stream)
3457{
3458 fprintf (stream, _("\
3459RISC-V options:\n\
8f595e9b
NC		 3460 -fpic generate position-independent code\n\
3461 -fno-pic don't generate position-independent code (default)\n\
3462 -march=ISA set the RISC-V architecture\n\
3463 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3464 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3465 -mabi=ABI set the RISC-V ABI\n\
3466 -mrelax enable relax (default)\n\
3467 -mno-relax disable relax\n\
3468 -march-attr generate RISC-V arch attribute\n\
3469 -mno-arch-attr don't generate RISC-V arch attribute\n\
e23eba97
NC		 3470"));
3471}
3472
3473/* Standard calling conventions leave the CFA at SP on entry. */
3474void
3475riscv_cfi_frame_initial_instructions (void)
3476{
3477 cfi_add_CFA_def_cfa_register (X_SP);
3478}
3479
3480int
3481tc_riscv_regname_to_dw2regnum (char *regname)
3482{
3483 int reg;
3484
3485 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3486 return reg;
3487
3488 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3489 return reg + 32;
3490
4762fe62
AB		 3491 /* CSRs are numbered 4096 -> 8191. */
3492 if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
3493 return reg + 4096;
3494
e23eba97
NC		 3495 as_bad (_("unknown register `%s'"), regname);
3496 return -1;
3497}
3498
3499void
3500riscv_elf_final_processing (void)
3501{
e23eba97 3502 elf_elfheader (stdoutput)->e_flags |= elf_flags;
e23eba97
NC		 3503}
3504
3505/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3506 since these directives break relaxation when used with symbol deltas. */
3507
3508static void
3509s_riscv_leb128 (int sign)
3510{
3511 expressionS exp;
3512 char *save_in = input_line_pointer;
3513
3514 expression (&exp);
3515 if (exp.X_op != O_constant)
3516 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3517 demand_empty_rest_of_line ();
3518
3519 input_line_pointer = save_in;
3520 return s_leb128 (sign);
3521}
3522
0e35537d
JW		 3523/* Parse the .insn directive. */
3524
3525static void
3526s_riscv_insn (int x ATTRIBUTE_UNUSED)
3527{
3528 char *str = input_line_pointer;
3529 struct riscv_cl_insn insn;
3530 expressionS imm_expr;
3531 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3532 char save_c;
3533
3534 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3535 ++input_line_pointer;
3536
3537 save_c = *input_line_pointer;
3538 *input_line_pointer = '\0';
3539
3540 const char *error = riscv_ip (str, &insn, &imm_expr,
3541 &imm_reloc, insn_type_hash);
3542
3543 if (error)
3544 {
3545 as_bad ("%s `%s'", error, str);
3546 }
3547 else
3548 {
3549 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3550 append_insn (&insn, &imm_expr, imm_reloc);
3551 }
3552
3553 *input_line_pointer = save_c;
3554 demand_empty_rest_of_line ();
3555}
3556
8f595e9b
NC		 3557/* Update arch and priv attributes. If we don't set the corresponding ELF
3558 attributes, then try to output the default ones. */
2dc8dd17
JW		 3559
3560static void
8f595e9b 3561riscv_write_out_attrs (void)
2dc8dd17 3562{
8f595e9b
NC		 3563 const char *arch_str, *priv_str, *p;
3564 /* versions[0] is major, versions[1] is minor,
3565 and versions[3] is revision. */
3566 unsigned versions[3] = {0}, number = 0;
3567 unsigned int i;
2dc8dd17 3568
8f595e9b
NC		 3569 /* Re-write arch attribute to normalize the arch string. */
3570 arch_str = riscv_arch_str (xlen, &riscv_subsets);
2dc8dd17 3571 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
2dc8dd17 3572 xfree ((void *)arch_str);
8f595e9b
NC		 3573
3574 /* For the file without any instruction, we don't set the default_priv_spec
3575 according to the priv attributes since the md_assemble isn't called.
3576 Call riscv_set_default_priv_spec here for the above case, although
3577 it seems strange. */
3578 if (!start_assemble
3579 && !riscv_set_default_priv_spec (NULL))
3580 return;
3581
1a79004f
NC		 3582 /* If we already have set elf priv attributes, then no need to do anything,
3583 assembler will generate them according to what you set. Otherwise, don't
3584 generate or update them when no CSR and priv instructions are used.
3585 Generate the priv attributes according to default_priv_spec, which can be
3586 set by -mpriv-spec and --with-priv-spec, and be updated by the original
3587 priv attribute sets. */
3588 if (!explicit_priv_attr)
3fc6c3dc
NC		 3589 return;
3590
8f595e9b
NC		 3591 /* Re-write priv attributes by default_priv_spec. */
3592 priv_str = riscv_get_priv_spec_name (default_priv_spec);
3593 p = priv_str;
3594 for (i = 0; *p; ++p)
3595 {
3596 if (*p == '.' && i < 3)
3597 {
3598 versions[i++] = number;
3599 number = 0;
3600 }
3601 else if (ISDIGIT (*p))
3602 number = (number * 10) + (*p - '0');
3603 else
3604 {
3605 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str);
3606 return;
3607 }
3608 }
3609 versions[i] = number;
3610
3611 /* Set the priv attributes. */
3612 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
3613 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
3614 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
2dc8dd17
JW		 3615}
3616
8f595e9b
NC		 3617/* Add the default contents for the .riscv.attributes section. If any
3618 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3619 to update the arch and priv attributes. */
2dc8dd17
JW		 3620
3621static void
3622riscv_set_public_attributes (void)
3623{
8f595e9b
NC		 3624 if (riscv_opts.arch_attr || explicit_attr)
3625 riscv_write_out_attrs ();
2dc8dd17
JW		 3626}
3627
3628/* Called after all assembly has been done. */
3629
3630void
3631riscv_md_end (void)
3632{
3633 riscv_set_public_attributes ();
3634}
3635
3636/* Given a symbolic attribute NAME, return the proper integer value.
3637 Returns -1 if the attribute is not known. */
3638
3639int
3640riscv_convert_symbolic_attribute (const char *name)
3641{
3642 static const struct
3643 {
3644 const char * name;
3645 const int tag;
3646 }
3647 attribute_table[] =
3648 {
3649 /* When you modify this table you should
3650 also modify the list in doc/c-riscv.texi. */
3651#define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3652 T(arch),
3653 T(priv_spec),
3654 T(priv_spec_minor),
3655 T(priv_spec_revision),
3656 T(unaligned_access),
3657 T(stack_align),
3658#undef T
3659 };
3660
3661 unsigned int i;
3662
3663 if (name == NULL)
3664 return -1;
3665
3666 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
3667 if (strcmp (name, attribute_table[i].name) == 0)
3668 return attribute_table[i].tag;
3669
3670 return -1;
3671}
3672
3673/* Parse a .attribute directive. */
3674
3675static void
3676s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
3677{
3678 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
8f595e9b
NC		 3679 unsigned old_xlen;
3680 obj_attribute *attr;
2dc8dd17 3681
8f595e9b
NC		 3682 explicit_attr = TRUE;
3683 switch (tag)
2dc8dd17 3684 {
8f595e9b
NC		 3685 case Tag_RISCV_arch:
3686 old_xlen = xlen;
2dc8dd17
JW		 3687 attr = elf_known_obj_attributes_proc (stdoutput);
3688 if (!start_assemble)
3689 riscv_set_arch (attr[Tag_RISCV_arch].s);
3690 else
3691 as_fatal (_(".attribute arch must set before any instructions"));
3692
3693 if (old_xlen != xlen)
3694 {
3695 /* We must re-init bfd again if xlen is changed. */
3696 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
3697 bfd_find_target (riscv_target_format (), stdoutput);
3698
3699 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
3700 as_warn (_("Could not set architecture and machine"));
3701 }
8f595e9b
NC		 3702 break;
3703
3704 case Tag_RISCV_priv_spec:
3705 case Tag_RISCV_priv_spec_minor:
3706 case Tag_RISCV_priv_spec_revision:
3707 if (start_assemble)
3708 as_fatal (_(".attribute priv spec must set before any instructions"));
3709 break;
3710
3711 default:
3712 break;
2dc8dd17
JW		 3713 }
3714}
3715
e23eba97
NC		 3716/* Pseudo-op table. */
3717
3718static const pseudo_typeS riscv_pseudo_table[] =
3719{
3720 /* RISC-V-specific pseudo-ops. */
3721 {"option", s_riscv_option, 0},
3722 {"half", cons, 2},
3723 {"word", cons, 4},
3724 {"dword", cons, 8},
3725 {"dtprelword", s_dtprel, 4},
3726 {"dtpreldword", s_dtprel, 8},
3727 {"bss", s_bss, 0},
e23eba97
NC		 3728 {"uleb128", s_riscv_leb128, 0},
3729 {"sleb128", s_riscv_leb128, 1},
0e35537d 3730 {"insn", s_riscv_insn, 0},
2dc8dd17 3731 {"attribute", s_riscv_attribute, 0},
e23eba97
NC		 3732
3733 { NULL, NULL, 0 },
3734};
3735
3736void
3737riscv_pop_insert (void)
3738{
3739 extern void pop_insert (const pseudo_typeS *);
3740
3741 pop_insert (riscv_pseudo_table);
3742}
GDB Binutils - Deliverables
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