Commit | Line | Data |
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252b5132 | 1 | /* tc-sparc.c -- Assemble for the SPARC |
b90efa5b | 2 | Copyright (C) 1989-2015 Free Software Foundation, Inc. |
252b5132 RH |
3 | This file is part of GAS, the GNU Assembler. |
4 | ||
5 | GAS is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 7 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
8 | any later version. |
9 | ||
10 | GAS is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public | |
16 | License along with GAS; see the file COPYING. If not, write | |
4b4da160 NC |
17 | to the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
18 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 19 | |
252b5132 | 20 | #include "as.h" |
3882b010 | 21 | #include "safe-ctype.h" |
252b5132 RH |
22 | #include "subsegs.h" |
23 | ||
24 | #include "opcode/sparc.h" | |
364b6d8b | 25 | #include "dw2gencfi.h" |
252b5132 RH |
26 | |
27 | #ifdef OBJ_ELF | |
28 | #include "elf/sparc.h" | |
732d96b6 | 29 | #include "dwarf2dbg.h" |
252b5132 RH |
30 | #endif |
31 | ||
6c1b24e4 AO |
32 | /* Some ancient Sun C compilers would not take such hex constants as |
33 | unsigned, and would end up sign-extending them to form an offsetT, | |
34 | so use these constants instead. */ | |
35 | #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) | |
36 | #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) | |
37 | ||
5a49b8ac AM |
38 | static int sparc_ip (char *, const struct sparc_opcode **); |
39 | static int parse_keyword_arg (int (*) (const char *), char **, int *); | |
40 | static int parse_const_expr_arg (char **, int *); | |
41 | static int get_expression (char *); | |
252b5132 RH |
42 | |
43 | /* Default architecture. */ | |
44 | /* ??? The default value should be V8, but sparclite support was added | |
45 | by making it the default. GCC now passes -Asparclite, so maybe sometime in | |
46 | the future we can set this to V8. */ | |
47 | #ifndef DEFAULT_ARCH | |
48 | #define DEFAULT_ARCH "sparclite" | |
49 | #endif | |
50 | static char *default_arch = DEFAULT_ARCH; | |
51 | ||
52 | /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' | |
53 | have been set. */ | |
54 | static int default_init_p; | |
55 | ||
56 | /* Current architecture. We don't bump up unless necessary. */ | |
57 | static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; | |
58 | ||
59 | /* The maximum architecture level we can bump up to. | |
60 | In a 32 bit environment, don't allow bumping up to v9 by default. | |
61 | The native assembler works this way. The user is required to pass | |
62 | an explicit argument before we'll create v9 object files. However, if | |
63 | we don't see any v9 insns, a v8plus object file is not created. */ | |
64 | static enum sparc_opcode_arch_val max_architecture; | |
65 | ||
66 | /* Either 32 or 64, selects file format. */ | |
67 | static int sparc_arch_size; | |
68 | /* Initial (default) value, recorded separately in case a user option | |
69 | changes the value before md_show_usage is called. */ | |
70 | static int default_arch_size; | |
71 | ||
72 | #ifdef OBJ_ELF | |
73 | /* The currently selected v9 memory model. Currently only used for | |
74 | ELF. */ | |
75 | static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; | |
9e8c70f9 DM |
76 | |
77 | #ifndef TE_SOLARIS | |
78 | /* Bitmask of instruction types seen so far, used to populate the | |
79 | GNU attributes section with hwcap information. */ | |
3d68f91c | 80 | static bfd_uint64_t hwcap_seen; |
9e8c70f9 | 81 | #endif |
252b5132 RH |
82 | #endif |
83 | ||
3d68f91c | 84 | static bfd_uint64_t hwcap_allowed; |
4bafe00e | 85 | |
252b5132 RH |
86 | static int architecture_requested; |
87 | static int warn_on_bump; | |
88 | ||
89 | /* If warn_on_bump and the needed architecture is higher than this | |
90 | architecture, issue a warning. */ | |
91 | static enum sparc_opcode_arch_val warn_after_architecture; | |
92 | ||
6d8809aa RH |
93 | /* Non-zero if as should generate error if an undeclared g[23] register |
94 | has been used in -64. */ | |
95 | static int no_undeclared_regs; | |
96 | ||
6faf3d66 JJ |
97 | /* Non-zero if we should try to relax jumps and calls. */ |
98 | static int sparc_relax; | |
99 | ||
252b5132 RH |
100 | /* Non-zero if we are generating PIC code. */ |
101 | int sparc_pic_code; | |
102 | ||
103 | /* Non-zero if we should give an error when misaligned data is seen. */ | |
104 | static int enforce_aligned_data; | |
105 | ||
106 | extern int target_big_endian; | |
107 | ||
108 | static int target_little_endian_data; | |
109 | ||
6d8809aa RH |
110 | /* Symbols for global registers on v9. */ |
111 | static symbolS *globals[8]; | |
112 | ||
364b6d8b JJ |
113 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ |
114 | int sparc_cie_data_alignment; | |
115 | ||
252b5132 RH |
116 | /* V9 and 86x have big and little endian data, but instructions are always big |
117 | endian. The sparclet has bi-endian support but both data and insns have | |
118 | the same endianness. Global `target_big_endian' is used for data. | |
119 | The following macro is used for instructions. */ | |
120 | #ifndef INSN_BIG_ENDIAN | |
121 | #define INSN_BIG_ENDIAN (target_big_endian \ | |
122 | || default_arch_type == sparc86x \ | |
123 | || SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
124 | #endif | |
125 | ||
e0c6ed95 | 126 | /* Handle of the OPCODE hash table. */ |
252b5132 RH |
127 | static struct hash_control *op_hash; |
128 | ||
5a49b8ac AM |
129 | static void s_data1 (void); |
130 | static void s_seg (int); | |
131 | static void s_proc (int); | |
132 | static void s_reserve (int); | |
133 | static void s_common (int); | |
134 | static void s_empty (int); | |
135 | static void s_uacons (int); | |
136 | static void s_ncons (int); | |
a7982600 | 137 | #ifdef OBJ_ELF |
5a49b8ac | 138 | static void s_register (int); |
a7982600 | 139 | #endif |
252b5132 RH |
140 | |
141 | const pseudo_typeS md_pseudo_table[] = | |
142 | { | |
e0c6ed95 | 143 | {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ |
252b5132 RH |
144 | {"common", s_common, 0}, |
145 | {"empty", s_empty, 0}, | |
146 | {"global", s_globl, 0}, | |
147 | {"half", cons, 2}, | |
cf9a1301 | 148 | {"nword", s_ncons, 0}, |
252b5132 RH |
149 | {"optim", s_ignore, 0}, |
150 | {"proc", s_proc, 0}, | |
151 | {"reserve", s_reserve, 0}, | |
152 | {"seg", s_seg, 0}, | |
153 | {"skip", s_space, 0}, | |
154 | {"word", cons, 4}, | |
155 | {"xword", cons, 8}, | |
156 | {"uahalf", s_uacons, 2}, | |
157 | {"uaword", s_uacons, 4}, | |
158 | {"uaxword", s_uacons, 8}, | |
159 | #ifdef OBJ_ELF | |
e0c6ed95 | 160 | /* These are specific to sparc/svr4. */ |
252b5132 RH |
161 | {"2byte", s_uacons, 2}, |
162 | {"4byte", s_uacons, 4}, | |
163 | {"8byte", s_uacons, 8}, | |
6d8809aa | 164 | {"register", s_register, 0}, |
252b5132 RH |
165 | #endif |
166 | {NULL, 0, 0}, | |
167 | }; | |
168 | ||
252b5132 | 169 | /* This array holds the chars that always start a comment. If the |
e0c6ed95 AM |
170 | pre-processor is disabled, these aren't very useful. */ |
171 | const char comment_chars[] = "!"; /* JF removed '|' from | |
172 | comment_chars. */ | |
252b5132 RH |
173 | |
174 | /* This array holds the chars that only start a comment at the beginning of | |
175 | a line. If the line seems to have the form '# 123 filename' | |
e0c6ed95 | 176 | .line and .file directives will appear in the pre-processed output. */ |
252b5132 RH |
177 | /* Note that input_file.c hand checks for '#' at the beginning of the |
178 | first line of the input file. This is because the compiler outputs | |
e0c6ed95 | 179 | #NO_APP at the beginning of its output. */ |
252b5132 | 180 | /* Also note that comments started like this one will always |
e0c6ed95 | 181 | work if '/' isn't otherwise defined. */ |
252b5132 RH |
182 | const char line_comment_chars[] = "#"; |
183 | ||
63a0b638 | 184 | const char line_separator_chars[] = ";"; |
252b5132 | 185 | |
e0c6ed95 AM |
186 | /* Chars that can be used to separate mant from exp in floating point |
187 | nums. */ | |
252b5132 RH |
188 | const char EXP_CHARS[] = "eE"; |
189 | ||
e0c6ed95 AM |
190 | /* Chars that mean this number is a floating point constant. |
191 | As in 0f12.456 | |
192 | or 0d1.2345e12 */ | |
252b5132 RH |
193 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
194 | ||
195 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
196 | changed in read.c. Ideally it shouldn't have to know about it at all, | |
197 | but nothing is ideal around here. */ | |
198 | ||
74b56d1f | 199 | #define isoctal(c) ((unsigned) ((c) - '0') < 8) |
252b5132 RH |
200 | |
201 | struct sparc_it | |
202 | { | |
203 | char *error; | |
204 | unsigned long opcode; | |
205 | struct nlist *nlistp; | |
206 | expressionS exp; | |
cf9a1301 | 207 | expressionS exp2; |
252b5132 RH |
208 | int pcrel; |
209 | bfd_reloc_code_real_type reloc; | |
210 | }; | |
211 | ||
212 | struct sparc_it the_insn, set_insn; | |
213 | ||
5a49b8ac | 214 | static void output_insn (const struct sparc_opcode *, struct sparc_it *); |
252b5132 RH |
215 | \f |
216 | /* Table of arguments to -A. | |
217 | The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect | |
218 | for this use. That table is for opcodes only. This table is for opcodes | |
219 | and file formats. */ | |
220 | ||
d6787ef9 | 221 | enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus, |
19f7b010 | 222 | v8plusa, v9, v9a, v9b, v9_64}; |
252b5132 | 223 | |
3d68f91c JM |
224 | /* Hardware capability sets, used to keep sparc_arch_table easy to |
225 | read. */ | |
226 | #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD | |
227 | #define HWS_V9 HWS_V8 | HWCAP_POPC | |
228 | #define HWS_VA HWS_V9 | HWCAP_VIS | |
229 | #define HWS_VB HWS_VA | HWCAP_VIS2 | |
230 | #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT | |
231 | #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC | |
232 | #define HWS_VE HWS_VD \ | |
233 | | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \ | |
234 | | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \ | |
235 | | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE | |
236 | #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA | |
237 | #define HWS_VM HWS_VV | |
238 | ||
239 | #define HWS2_VM \ | |
240 | HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \ | |
241 | | HWCAP2_XMPMUL | HWCAP2_XMONT | |
242 | ||
252b5132 RH |
243 | static struct sparc_arch { |
244 | char *name; | |
245 | char *opcode_arch; | |
246 | enum sparc_arch_types arch_type; | |
247 | /* Default word size, as specified during configuration. | |
248 | A value of zero means can't be used to specify default architecture. */ | |
249 | int default_arch_size; | |
250 | /* Allowable arg to -A? */ | |
251 | int user_option_p; | |
4bafe00e | 252 | int hwcap_allowed; |
3d68f91c | 253 | int hwcap2_allowed; |
252b5132 | 254 | } sparc_arch_table[] = { |
3d68f91c JM |
255 | { "v6", "v6", v6, 0, 1, 0, 0 }, |
256 | { "v7", "v7", v7, 0, 1, 0, 0 }, | |
257 | { "v8", "v8", v8, 32, 1, HWS_V8, 0 }, | |
258 | { "v8a", "v8", v8, 32, 1, HWS_V8, 0 }, | |
259 | { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 }, | |
260 | { "sparcvis", "v9a", v9, 0, 1, HWS_VA, 0 }, | |
261 | { "sparcvis2", "v9b", v9, 0, 1, HWS_VB, 0 }, | |
262 | { "sparcfmaf", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF, 0 }, | |
263 | { "sparcima", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_IMA, 0 }, | |
264 | { "sparcvis3", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 }, | |
265 | { "sparcvis3r", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 }, | |
266 | ||
267 | { "sparc4", "v9b", v9, 0, 1, HWS_VV, 0 }, | |
268 | { "sparc5", "v9b", v9, 0, 1, HWS_VM, HWS2_VM }, | |
269 | ||
270 | { "leon", "leon", leon, 32, 1, HWS_V8, 0 }, | |
271 | { "sparclet", "sparclet", sparclet, 32, 1, HWS_V8, 0 }, | |
272 | { "sparclite", "sparclite", sparclite, 32, 1, HWS_V8, 0 }, | |
273 | { "sparc86x", "sparclite", sparc86x, 32, 1, HWS_V8, 0 }, | |
274 | ||
275 | { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 }, | |
276 | { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS|HWS_VA, 0 }, | |
277 | { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VB, 0 }, | |
278 | { "v8plusc", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VC, 0 }, | |
279 | { "v8plusd", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VD, 0 }, | |
280 | { "v8pluse", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VE, 0 }, | |
281 | { "v8plusv", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VV, 0 }, | |
282 | { "v8plusm", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VM, 0 }, | |
3739860c | 283 | |
3d68f91c JM |
284 | { "v9", "v9", v9, 0, 1, HWS_V9, 0 }, |
285 | { "v9a", "v9a", v9, 0, 1, HWS_VA, 0 }, | |
286 | { "v9b", "v9b", v9, 0, 1, HWS_VB, 0 }, | |
287 | { "v9c", "v9b", v9, 0, 1, HWS_VC, 0 }, | |
288 | { "v9d", "v9b", v9, 0, 1, HWS_VD, 0 }, | |
289 | { "v9e", "v9b", v9, 0, 1, HWS_VE, 0 }, | |
290 | { "v9v", "v9b", v9, 0, 1, HWS_VV, 0 }, | |
291 | { "v9m", "v9b", v9, 0, 1, HWS_VM, HWS2_VM }, | |
292 | ||
1110793a | 293 | /* This exists to allow configure.tgt to pass one |
252b5132 | 294 | value to specify both the default machine and default word size. */ |
3d68f91c JM |
295 | { "v9-64", "v9", v9, 64, 0, HWS_V9, 0 }, |
296 | { NULL, NULL, v8, 0, 0, 0, 0 } | |
252b5132 RH |
297 | }; |
298 | ||
299 | /* Variant of default_arch */ | |
300 | static enum sparc_arch_types default_arch_type; | |
301 | ||
302 | static struct sparc_arch * | |
5a49b8ac | 303 | lookup_arch (char *name) |
252b5132 RH |
304 | { |
305 | struct sparc_arch *sa; | |
306 | ||
307 | for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) | |
308 | if (strcmp (sa->name, name) == 0) | |
309 | break; | |
310 | if (sa->name == NULL) | |
311 | return NULL; | |
312 | return sa; | |
313 | } | |
314 | ||
315 | /* Initialize the default opcode arch and word size from the default | |
316 | architecture name. */ | |
317 | ||
318 | static void | |
5a49b8ac | 319 | init_default_arch (void) |
252b5132 RH |
320 | { |
321 | struct sparc_arch *sa = lookup_arch (default_arch); | |
322 | ||
323 | if (sa == NULL | |
324 | || sa->default_arch_size == 0) | |
325 | as_fatal (_("Invalid default architecture, broken assembler.")); | |
326 | ||
327 | max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); | |
328 | if (max_architecture == SPARC_OPCODE_ARCH_BAD) | |
329 | as_fatal (_("Bad opcode table, broken assembler.")); | |
330 | default_arch_size = sparc_arch_size = sa->default_arch_size; | |
331 | default_init_p = 1; | |
332 | default_arch_type = sa->arch_type; | |
333 | } | |
334 | ||
335 | /* Called by TARGET_FORMAT. */ | |
336 | ||
337 | const char * | |
5a49b8ac | 338 | sparc_target_format (void) |
252b5132 RH |
339 | { |
340 | /* We don't get a chance to initialize anything before we're called, | |
341 | so handle that now. */ | |
342 | if (! default_init_p) | |
343 | init_default_arch (); | |
344 | ||
345 | #ifdef OBJ_AOUT | |
346 | #ifdef TE_NetBSD | |
347 | return "a.out-sparc-netbsd"; | |
348 | #else | |
349 | #ifdef TE_SPARCAOUT | |
350 | if (target_big_endian) | |
351 | return "a.out-sunos-big"; | |
352 | else if (default_arch_type == sparc86x && target_little_endian_data) | |
353 | return "a.out-sunos-big"; | |
ab3e48dc KH |
354 | else |
355 | return "a.out-sparc-little"; | |
252b5132 RH |
356 | #else |
357 | return "a.out-sunos-big"; | |
358 | #endif | |
359 | #endif | |
360 | #endif | |
361 | ||
362 | #ifdef OBJ_BOUT | |
363 | return "b.out.big"; | |
364 | #endif | |
365 | ||
366 | #ifdef OBJ_COFF | |
367 | #ifdef TE_LYNX | |
368 | return "coff-sparc-lynx"; | |
369 | #else | |
370 | return "coff-sparc"; | |
371 | #endif | |
372 | #endif | |
373 | ||
910600e9 RS |
374 | #ifdef TE_VXWORKS |
375 | return "elf32-sparc-vxworks"; | |
376 | #endif | |
377 | ||
252b5132 | 378 | #ifdef OBJ_ELF |
71a75f6f | 379 | return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; |
252b5132 RH |
380 | #endif |
381 | ||
382 | abort (); | |
383 | } | |
384 | \f | |
e0c6ed95 | 385 | /* md_parse_option |
252b5132 RH |
386 | * Invocation line includes a switch not recognized by the base assembler. |
387 | * See if it's a processor-specific option. These are: | |
388 | * | |
389 | * -bump | |
390 | * Warn on architecture bumps. See also -A. | |
391 | * | |
d6787ef9 | 392 | * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet |
252b5132 | 393 | * Standard 32 bit architectures. |
19f7b010 | 394 | * -Av9, -Av9a, -Av9b |
252b5132 RH |
395 | * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). |
396 | * This used to only mean 64 bits, but properly specifying it | |
397 | * complicated gcc's ASM_SPECs, so now opcode selection is | |
398 | * specified orthogonally to word size (except when specifying | |
399 | * the default, but that is an internal implementation detail). | |
19f7b010 JJ |
400 | * -Av8plus, -Av8plusa, -Av8plusb |
401 | * Same as -Av9{,a,b}. | |
402 | * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb | |
403 | * Same as -Av8plus{,a,b} -32, for compatibility with Sun's | |
404 | * assembler. | |
405 | * -xarch=v9, -xarch=v9a, -xarch=v9b | |
406 | * Same as -Av9{,a,b} -64, for compatibility with Sun's | |
c2158c24 | 407 | * assembler. |
252b5132 RH |
408 | * |
409 | * Select the architecture and possibly the file format. | |
410 | * Instructions or features not supported by the selected | |
411 | * architecture cause fatal errors. | |
412 | * | |
413 | * The default is to start at v6, and bump the architecture up | |
414 | * whenever an instruction is seen at a higher level. In 32 bit | |
415 | * environments, v9 is not bumped up to, the user must pass | |
19f7b010 | 416 | * -Av8plus{,a,b}. |
252b5132 RH |
417 | * |
418 | * If -bump is specified, a warning is printing when bumping to | |
419 | * higher levels. | |
420 | * | |
421 | * If an architecture is specified, all instructions must match | |
422 | * that architecture. Any higher level instructions are flagged | |
423 | * as errors. Note that in the 32 bit environment specifying | |
424 | * -Av8plus does not automatically create a v8plus object file, a | |
425 | * v9 insn must be seen. | |
426 | * | |
427 | * If both an architecture and -bump are specified, the | |
428 | * architecture starts at the specified level, but bumps are | |
429 | * warnings. Note that we can't set `current_architecture' to | |
430 | * the requested level in this case: in the 32 bit environment, | |
431 | * we still must avoid creating v8plus object files unless v9 | |
432 | * insns are seen. | |
433 | * | |
434 | * Note: | |
435 | * Bumping between incompatible architectures is always an | |
436 | * error. For example, from sparclite to v9. | |
437 | */ | |
438 | ||
439 | #ifdef OBJ_ELF | |
5a38dc70 | 440 | const char *md_shortopts = "A:K:VQ:sq"; |
252b5132 RH |
441 | #else |
442 | #ifdef OBJ_AOUT | |
5a38dc70 | 443 | const char *md_shortopts = "A:k"; |
252b5132 | 444 | #else |
5a38dc70 | 445 | const char *md_shortopts = "A:"; |
252b5132 RH |
446 | #endif |
447 | #endif | |
448 | struct option md_longopts[] = { | |
449 | #define OPTION_BUMP (OPTION_MD_BASE) | |
450 | {"bump", no_argument, NULL, OPTION_BUMP}, | |
451 | #define OPTION_SPARC (OPTION_MD_BASE + 1) | |
452 | {"sparc", no_argument, NULL, OPTION_SPARC}, | |
453 | #define OPTION_XARCH (OPTION_MD_BASE + 2) | |
454 | {"xarch", required_argument, NULL, OPTION_XARCH}, | |
455 | #ifdef OBJ_ELF | |
456 | #define OPTION_32 (OPTION_MD_BASE + 3) | |
457 | {"32", no_argument, NULL, OPTION_32}, | |
458 | #define OPTION_64 (OPTION_MD_BASE + 4) | |
459 | {"64", no_argument, NULL, OPTION_64}, | |
460 | #define OPTION_TSO (OPTION_MD_BASE + 5) | |
461 | {"TSO", no_argument, NULL, OPTION_TSO}, | |
462 | #define OPTION_PSO (OPTION_MD_BASE + 6) | |
463 | {"PSO", no_argument, NULL, OPTION_PSO}, | |
464 | #define OPTION_RMO (OPTION_MD_BASE + 7) | |
465 | {"RMO", no_argument, NULL, OPTION_RMO}, | |
466 | #endif | |
467 | #ifdef SPARC_BIENDIAN | |
468 | #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) | |
469 | {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, | |
470 | #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) | |
471 | {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, | |
472 | #endif | |
473 | #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) | |
474 | {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, | |
475 | #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) | |
476 | {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, | |
6d8809aa RH |
477 | #ifdef OBJ_ELF |
478 | #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) | |
479 | {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, | |
a25fe906 ILT |
480 | #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) |
481 | {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, | |
6d8809aa | 482 | #endif |
6faf3d66 JJ |
483 | #define OPTION_RELAX (OPTION_MD_BASE + 14) |
484 | {"relax", no_argument, NULL, OPTION_RELAX}, | |
485 | #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) | |
486 | {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
252b5132 RH |
487 | {NULL, no_argument, NULL, 0} |
488 | }; | |
e0c6ed95 AM |
489 | |
490 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
491 | |
492 | int | |
5a49b8ac | 493 | md_parse_option (int c, char *arg) |
252b5132 RH |
494 | { |
495 | /* We don't get a chance to initialize anything before we're called, | |
496 | so handle that now. */ | |
497 | if (! default_init_p) | |
498 | init_default_arch (); | |
499 | ||
500 | switch (c) | |
501 | { | |
502 | case OPTION_BUMP: | |
503 | warn_on_bump = 1; | |
504 | warn_after_architecture = SPARC_OPCODE_ARCH_V6; | |
505 | break; | |
506 | ||
507 | case OPTION_XARCH: | |
c2158c24 | 508 | #ifdef OBJ_ELF |
668b27ea | 509 | if (!strncmp (arg, "v9", 2)) |
c2158c24 | 510 | md_parse_option (OPTION_64, NULL); |
668b27ea DM |
511 | else |
512 | { | |
513 | if (!strncmp (arg, "v8", 2) | |
514 | || !strncmp (arg, "v7", 2) | |
515 | || !strncmp (arg, "v6", 2) | |
516 | || !strcmp (arg, "sparclet") | |
517 | || !strcmp (arg, "sparclite") | |
518 | || !strcmp (arg, "sparc86x")) | |
519 | md_parse_option (OPTION_32, NULL); | |
520 | } | |
c2158c24 | 521 | #endif |
e0c6ed95 | 522 | /* Fall through. */ |
252b5132 RH |
523 | |
524 | case 'A': | |
525 | { | |
526 | struct sparc_arch *sa; | |
527 | enum sparc_opcode_arch_val opcode_arch; | |
528 | ||
529 | sa = lookup_arch (arg); | |
530 | if (sa == NULL | |
531 | || ! sa->user_option_p) | |
532 | { | |
c2158c24 JJ |
533 | if (c == OPTION_XARCH) |
534 | as_bad (_("invalid architecture -xarch=%s"), arg); | |
535 | else | |
536 | as_bad (_("invalid architecture -A%s"), arg); | |
252b5132 RH |
537 | return 0; |
538 | } | |
539 | ||
540 | opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); | |
541 | if (opcode_arch == SPARC_OPCODE_ARCH_BAD) | |
542 | as_fatal (_("Bad opcode table, broken assembler.")); | |
543 | ||
4bafe00e DM |
544 | if (!architecture_requested |
545 | || opcode_arch > max_architecture) | |
546 | max_architecture = opcode_arch; | |
3d68f91c JM |
547 | hwcap_allowed |
548 | |= (((bfd_uint64_t) sa->hwcap2_allowed) << 32) | sa->hwcap_allowed; | |
252b5132 RH |
549 | architecture_requested = 1; |
550 | } | |
551 | break; | |
552 | ||
553 | case OPTION_SPARC: | |
554 | /* Ignore -sparc, used by SunOS make default .s.o rule. */ | |
555 | break; | |
556 | ||
557 | case OPTION_ENFORCE_ALIGNED_DATA: | |
558 | enforce_aligned_data = 1; | |
559 | break; | |
560 | ||
561 | #ifdef SPARC_BIENDIAN | |
562 | case OPTION_LITTLE_ENDIAN: | |
563 | target_big_endian = 0; | |
564 | if (default_arch_type != sparclet) | |
565 | as_fatal ("This target does not support -EL"); | |
566 | break; | |
567 | case OPTION_LITTLE_ENDIAN_DATA: | |
568 | target_little_endian_data = 1; | |
569 | target_big_endian = 0; | |
570 | if (default_arch_type != sparc86x | |
571 | && default_arch_type != v9) | |
572 | as_fatal ("This target does not support --little-endian-data"); | |
573 | break; | |
574 | case OPTION_BIG_ENDIAN: | |
575 | target_big_endian = 1; | |
576 | break; | |
577 | #endif | |
578 | ||
579 | #ifdef OBJ_AOUT | |
580 | case 'k': | |
581 | sparc_pic_code = 1; | |
582 | break; | |
583 | #endif | |
584 | ||
585 | #ifdef OBJ_ELF | |
586 | case OPTION_32: | |
587 | case OPTION_64: | |
588 | { | |
589 | const char **list, **l; | |
590 | ||
591 | sparc_arch_size = c == OPTION_32 ? 32 : 64; | |
592 | list = bfd_target_list (); | |
593 | for (l = list; *l != NULL; l++) | |
594 | { | |
595 | if (sparc_arch_size == 32) | |
596 | { | |
71a75f6f | 597 | if (CONST_STRNEQ (*l, "elf32-sparc")) |
252b5132 RH |
598 | break; |
599 | } | |
600 | else | |
601 | { | |
71a75f6f | 602 | if (CONST_STRNEQ (*l, "elf64-sparc")) |
252b5132 RH |
603 | break; |
604 | } | |
605 | } | |
606 | if (*l == NULL) | |
607 | as_fatal (_("No compiled in support for %d bit object file format"), | |
608 | sparc_arch_size); | |
609 | free (list); | |
b7cac25f DM |
610 | |
611 | if (sparc_arch_size == 64 | |
612 | && max_architecture < SPARC_OPCODE_ARCH_V9) | |
613 | max_architecture = SPARC_OPCODE_ARCH_V9; | |
252b5132 RH |
614 | } |
615 | break; | |
616 | ||
617 | case OPTION_TSO: | |
618 | sparc_memory_model = MM_TSO; | |
619 | break; | |
620 | ||
621 | case OPTION_PSO: | |
622 | sparc_memory_model = MM_PSO; | |
623 | break; | |
624 | ||
625 | case OPTION_RMO: | |
626 | sparc_memory_model = MM_RMO; | |
627 | break; | |
628 | ||
629 | case 'V': | |
630 | print_version_id (); | |
631 | break; | |
632 | ||
633 | case 'Q': | |
634 | /* Qy - do emit .comment | |
e0c6ed95 | 635 | Qn - do not emit .comment. */ |
252b5132 RH |
636 | break; |
637 | ||
638 | case 's': | |
e0c6ed95 | 639 | /* Use .stab instead of .stab.excl. */ |
252b5132 RH |
640 | break; |
641 | ||
642 | case 'q': | |
e0c6ed95 | 643 | /* quick -- Native assembler does fewer checks. */ |
252b5132 RH |
644 | break; |
645 | ||
646 | case 'K': | |
647 | if (strcmp (arg, "PIC") != 0) | |
648 | as_warn (_("Unrecognized option following -K")); | |
649 | else | |
650 | sparc_pic_code = 1; | |
651 | break; | |
6d8809aa RH |
652 | |
653 | case OPTION_NO_UNDECLARED_REGS: | |
654 | no_undeclared_regs = 1; | |
655 | break; | |
a25fe906 ILT |
656 | |
657 | case OPTION_UNDECLARED_REGS: | |
658 | no_undeclared_regs = 0; | |
659 | break; | |
252b5132 RH |
660 | #endif |
661 | ||
6faf3d66 JJ |
662 | case OPTION_RELAX: |
663 | sparc_relax = 1; | |
664 | break; | |
665 | ||
666 | case OPTION_NO_RELAX: | |
667 | sparc_relax = 0; | |
668 | break; | |
669 | ||
252b5132 RH |
670 | default: |
671 | return 0; | |
672 | } | |
673 | ||
674 | return 1; | |
675 | } | |
676 | ||
677 | void | |
5a49b8ac | 678 | md_show_usage (FILE *stream) |
252b5132 RH |
679 | { |
680 | const struct sparc_arch *arch; | |
c2158c24 | 681 | int column; |
252b5132 RH |
682 | |
683 | /* We don't get a chance to initialize anything before we're called, | |
684 | so handle that now. */ | |
685 | if (! default_init_p) | |
686 | init_default_arch (); | |
687 | ||
e0c6ed95 | 688 | fprintf (stream, _("SPARC options:\n")); |
c2158c24 | 689 | column = 0; |
252b5132 RH |
690 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
691 | { | |
c2158c24 JJ |
692 | if (!arch->user_option_p) |
693 | continue; | |
252b5132 RH |
694 | if (arch != &sparc_arch_table[0]) |
695 | fprintf (stream, " | "); | |
07726851 | 696 | if (column + strlen (arch->name) > 70) |
c2158c24 JJ |
697 | { |
698 | column = 0; | |
699 | fputc ('\n', stream); | |
700 | } | |
07726851 | 701 | column += 5 + 2 + strlen (arch->name); |
c2158c24 | 702 | fprintf (stream, "-A%s", arch->name); |
252b5132 | 703 | } |
c2158c24 JJ |
704 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
705 | { | |
706 | if (!arch->user_option_p) | |
707 | continue; | |
708 | fprintf (stream, " | "); | |
07726851 | 709 | if (column + strlen (arch->name) > 65) |
c2158c24 JJ |
710 | { |
711 | column = 0; | |
712 | fputc ('\n', stream); | |
713 | } | |
07726851 | 714 | column += 5 + 7 + strlen (arch->name); |
c2158c24 JJ |
715 | fprintf (stream, "-xarch=%s", arch->name); |
716 | } | |
717 | fprintf (stream, _("\n\ | |
252b5132 RH |
718 | specify variant of SPARC architecture\n\ |
719 | -bump warn when assembler switches architectures\n\ | |
720 | -sparc ignored\n\ | |
6faf3d66 JJ |
721 | --enforce-aligned-data force .long, etc., to be aligned correctly\n\ |
722 | -relax relax jumps and branches (default)\n\ | |
723 | -no-relax avoid changing any jumps and branches\n")); | |
252b5132 RH |
724 | #ifdef OBJ_AOUT |
725 | fprintf (stream, _("\ | |
726 | -k generate PIC\n")); | |
727 | #endif | |
728 | #ifdef OBJ_ELF | |
729 | fprintf (stream, _("\ | |
730 | -32 create 32 bit object file\n\ | |
731 | -64 create 64 bit object file\n")); | |
732 | fprintf (stream, _("\ | |
733 | [default is %d]\n"), default_arch_size); | |
734 | fprintf (stream, _("\ | |
735 | -TSO use Total Store Ordering\n\ | |
736 | -PSO use Partial Store Ordering\n\ | |
737 | -RMO use Relaxed Memory Ordering\n")); | |
738 | fprintf (stream, _("\ | |
739 | [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); | |
740 | fprintf (stream, _("\ | |
741 | -KPIC generate PIC\n\ | |
742 | -V print assembler version number\n\ | |
a25fe906 ILT |
743 | -undeclared-regs ignore application global register usage without\n\ |
744 | appropriate .register directive (default)\n\ | |
745 | -no-undeclared-regs force error on application global register usage\n\ | |
746 | without appropriate .register directive\n\ | |
252b5132 RH |
747 | -q ignored\n\ |
748 | -Qy, -Qn ignored\n\ | |
749 | -s ignored\n")); | |
750 | #endif | |
751 | #ifdef SPARC_BIENDIAN | |
752 | fprintf (stream, _("\ | |
753 | -EL generate code for a little endian machine\n\ | |
754 | -EB generate code for a big endian machine\n\ | |
755 | --little-endian-data generate code for a machine having big endian\n\ | |
c20f4f8c | 756 | instructions and little endian data.\n")); |
252b5132 RH |
757 | #endif |
758 | } | |
759 | \f | |
e0c6ed95 | 760 | /* Native operand size opcode translation. */ |
cf9a1301 RH |
761 | struct |
762 | { | |
763 | char *name; | |
764 | char *name32; | |
765 | char *name64; | |
766 | } native_op_table[] = | |
767 | { | |
768 | {"ldn", "ld", "ldx"}, | |
769 | {"ldna", "lda", "ldxa"}, | |
770 | {"stn", "st", "stx"}, | |
771 | {"stna", "sta", "stxa"}, | |
772 | {"slln", "sll", "sllx"}, | |
773 | {"srln", "srl", "srlx"}, | |
774 | {"sran", "sra", "srax"}, | |
775 | {"casn", "cas", "casx"}, | |
776 | {"casna", "casa", "casxa"}, | |
777 | {"clrn", "clr", "clrx"}, | |
778 | {NULL, NULL, NULL}, | |
779 | }; | |
780 | \f | |
10156f83 | 781 | /* sparc64 privileged and hyperprivileged registers. */ |
252b5132 RH |
782 | |
783 | struct priv_reg_entry | |
ab3e48dc KH |
784 | { |
785 | char *name; | |
786 | int regnum; | |
787 | }; | |
252b5132 RH |
788 | |
789 | struct priv_reg_entry priv_reg_table[] = | |
790 | { | |
791 | {"tpc", 0}, | |
792 | {"tnpc", 1}, | |
793 | {"tstate", 2}, | |
794 | {"tt", 3}, | |
795 | {"tick", 4}, | |
796 | {"tba", 5}, | |
797 | {"pstate", 6}, | |
798 | {"tl", 7}, | |
799 | {"pil", 8}, | |
800 | {"cwp", 9}, | |
801 | {"cansave", 10}, | |
802 | {"canrestore", 11}, | |
803 | {"cleanwin", 12}, | |
804 | {"otherwin", 13}, | |
805 | {"wstate", 14}, | |
806 | {"fq", 15}, | |
10156f83 | 807 | {"gl", 16}, |
38074311 | 808 | {"pmcdper", 23}, |
252b5132 | 809 | {"ver", 31}, |
e0c6ed95 | 810 | {"", -1}, /* End marker. */ |
252b5132 RH |
811 | }; |
812 | ||
10156f83 DM |
813 | struct priv_reg_entry hpriv_reg_table[] = |
814 | { | |
815 | {"hpstate", 0}, | |
816 | {"htstate", 1}, | |
817 | {"hintp", 3}, | |
818 | {"htba", 5}, | |
819 | {"hver", 6}, | |
ec92c392 JM |
820 | {"hstick_offset", 28}, |
821 | {"hstick_enable", 29}, | |
10156f83 DM |
822 | {"hstick_cmpr", 31}, |
823 | {"", -1}, /* End marker. */ | |
824 | }; | |
825 | ||
1a6b486f DM |
826 | /* v9a specific asrs. This table is ordered by initial |
827 | letter, in reverse. */ | |
252b5132 RH |
828 | |
829 | struct priv_reg_entry v9a_asr_table[] = | |
830 | { | |
831 | {"tick_cmpr", 23}, | |
19f7b010 JJ |
832 | {"sys_tick_cmpr", 25}, |
833 | {"sys_tick", 24}, | |
1a6b486f DM |
834 | {"stick_cmpr", 25}, |
835 | {"stick", 24}, | |
f04d18b7 DM |
836 | {"softint_clear", 21}, |
837 | {"softint_set", 20}, | |
2b661f3d | 838 | {"softint", 22}, |
252b5132 | 839 | {"set_softint", 20}, |
58004e23 | 840 | {"pause", 27}, |
252b5132 RH |
841 | {"pic", 17}, |
842 | {"pcr", 16}, | |
3d68f91c | 843 | {"mwait", 28}, |
252b5132 RH |
844 | {"gsr", 19}, |
845 | {"dcr", 18}, | |
2e52845b | 846 | {"cfr", 26}, |
252b5132 | 847 | {"clear_softint", 21}, |
e0c6ed95 | 848 | {"", -1}, /* End marker. */ |
252b5132 RH |
849 | }; |
850 | ||
851 | static int | |
5a49b8ac | 852 | cmp_reg_entry (const void *parg, const void *qarg) |
252b5132 RH |
853 | { |
854 | const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; | |
855 | const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; | |
856 | ||
857 | return strcmp (q->name, p->name); | |
858 | } | |
859 | \f | |
860 | /* This function is called once, at assembler startup time. It should | |
e0c6ed95 AM |
861 | set up all the tables, etc. that the MD part of the assembler will |
862 | need. */ | |
252b5132 RH |
863 | |
864 | void | |
5a49b8ac | 865 | md_begin (void) |
252b5132 | 866 | { |
ed9e98c2 | 867 | const char *retval = NULL; |
252b5132 | 868 | int lose = 0; |
ed9e98c2 | 869 | unsigned int i = 0; |
252b5132 RH |
870 | |
871 | /* We don't get a chance to initialize anything before md_parse_option | |
872 | is called, and it may not be called, so handle default initialization | |
873 | now if not already done. */ | |
874 | if (! default_init_p) | |
875 | init_default_arch (); | |
876 | ||
364b6d8b | 877 | sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; |
252b5132 RH |
878 | op_hash = hash_new (); |
879 | ||
880 | while (i < (unsigned int) sparc_num_opcodes) | |
881 | { | |
882 | const char *name = sparc_opcodes[i].name; | |
5a49b8ac | 883 | retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); |
252b5132 RH |
884 | if (retval != NULL) |
885 | { | |
cf9a1301 RH |
886 | as_bad (_("Internal error: can't hash `%s': %s\n"), |
887 | sparc_opcodes[i].name, retval); | |
252b5132 RH |
888 | lose = 1; |
889 | } | |
890 | do | |
891 | { | |
892 | if (sparc_opcodes[i].match & sparc_opcodes[i].lose) | |
893 | { | |
cf9a1301 RH |
894 | as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), |
895 | sparc_opcodes[i].name, sparc_opcodes[i].args); | |
252b5132 RH |
896 | lose = 1; |
897 | } | |
898 | ++i; | |
899 | } | |
900 | while (i < (unsigned int) sparc_num_opcodes | |
901 | && !strcmp (sparc_opcodes[i].name, name)); | |
902 | } | |
903 | ||
cf9a1301 RH |
904 | for (i = 0; native_op_table[i].name; i++) |
905 | { | |
906 | const struct sparc_opcode *insn; | |
3d4ae3c0 NC |
907 | char *name = ((sparc_arch_size == 32) |
908 | ? native_op_table[i].name32 | |
909 | : native_op_table[i].name64); | |
e0c6ed95 | 910 | insn = (struct sparc_opcode *) hash_find (op_hash, name); |
cf9a1301 | 911 | if (insn == NULL) |
e0c6ed95 AM |
912 | { |
913 | as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), | |
914 | name, native_op_table[i].name); | |
915 | lose = 1; | |
916 | } | |
cf9a1301 RH |
917 | else |
918 | { | |
5a49b8ac AM |
919 | retval = hash_insert (op_hash, native_op_table[i].name, |
920 | (void *) insn); | |
cf9a1301 RH |
921 | if (retval != NULL) |
922 | { | |
923 | as_bad (_("Internal error: can't hash `%s': %s\n"), | |
924 | sparc_opcodes[i].name, retval); | |
925 | lose = 1; | |
926 | } | |
927 | } | |
928 | } | |
929 | ||
252b5132 RH |
930 | if (lose) |
931 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
932 | ||
252b5132 RH |
933 | qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), |
934 | sizeof (priv_reg_table[0]), cmp_reg_entry); | |
935 | ||
936 | /* If -bump, record the architecture level at which we start issuing | |
937 | warnings. The behaviour is different depending upon whether an | |
938 | architecture was explicitly specified. If it wasn't, we issue warnings | |
939 | for all upwards bumps. If it was, we don't start issuing warnings until | |
940 | we need to bump beyond the requested architecture or when we bump between | |
941 | conflicting architectures. */ | |
942 | ||
943 | if (warn_on_bump | |
944 | && architecture_requested) | |
945 | { | |
946 | /* `max_architecture' records the requested architecture. | |
947 | Issue warnings if we go above it. */ | |
948 | warn_after_architecture = max_architecture; | |
252b5132 | 949 | } |
75ac3a7f JM |
950 | |
951 | /* Find the highest architecture level that doesn't conflict with | |
952 | the requested one. */ | |
953 | ||
954 | if (warn_on_bump | |
955 | || !architecture_requested) | |
956 | { | |
957 | enum sparc_opcode_arch_val current_max_architecture | |
958 | = max_architecture; | |
959 | ||
960 | for (max_architecture = SPARC_OPCODE_ARCH_MAX; | |
961 | max_architecture > warn_after_architecture; | |
962 | --max_architecture) | |
963 | if (! SPARC_OPCODE_CONFLICT_P (max_architecture, | |
964 | current_max_architecture)) | |
965 | break; | |
966 | } | |
252b5132 RH |
967 | } |
968 | ||
969 | /* Called after all assembly has been done. */ | |
970 | ||
971 | void | |
5a49b8ac | 972 | sparc_md_end (void) |
252b5132 | 973 | { |
19f7b010 | 974 | unsigned long mach = bfd_mach_sparc; |
daf5e10e | 975 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) |
3d68f91c | 976 | int hwcaps, hwcaps2; |
daf5e10e | 977 | #endif |
19f7b010 | 978 | |
252b5132 | 979 | if (sparc_arch_size == 64) |
19f7b010 JJ |
980 | switch (current_architecture) |
981 | { | |
982 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; | |
983 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; | |
984 | default: mach = bfd_mach_sparc_v9; break; | |
985 | } | |
252b5132 | 986 | else |
19f7b010 JJ |
987 | switch (current_architecture) |
988 | { | |
989 | case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; | |
990 | case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; | |
991 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; | |
992 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; | |
993 | /* The sparclite is treated like a normal sparc. Perhaps it shouldn't | |
994 | be but for now it is (since that's the way it's always been | |
995 | treated). */ | |
996 | default: break; | |
997 | } | |
998 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); | |
9e8c70f9 DM |
999 | |
1000 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) | |
3d68f91c JM |
1001 | hwcaps = hwcap_seen & U0xffffffff; |
1002 | hwcaps2 = hwcap_seen >> 32; | |
1003 | ||
1004 | if (hwcaps) | |
1005 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcaps); | |
1006 | if (hwcaps2) | |
1007 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS2, hwcaps2); | |
9e8c70f9 | 1008 | #endif |
252b5132 RH |
1009 | } |
1010 | \f | |
1011 | /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ | |
1012 | ||
5a49b8ac AM |
1013 | static inline int |
1014 | in_signed_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
1015 | { |
1016 | if (max <= 0) | |
1017 | abort (); | |
1018 | /* Sign-extend the value from the architecture word size, so that | |
1019 | 0xffffffff is always considered -1 on sparc32. */ | |
1020 | if (sparc_arch_size == 32) | |
1021 | { | |
e0c6ed95 | 1022 | bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; |
6c1b24e4 | 1023 | val = ((val & U0xffffffff) ^ sign) - sign; |
252b5132 RH |
1024 | } |
1025 | if (val > max) | |
1026 | return 0; | |
1027 | if (val < ~max) | |
1028 | return 0; | |
1029 | return 1; | |
1030 | } | |
1031 | ||
1032 | /* Return non-zero if VAL is in the range 0 to MAX. */ | |
1033 | ||
5a49b8ac AM |
1034 | static inline int |
1035 | in_unsigned_range (bfd_vma val, bfd_vma max) | |
252b5132 RH |
1036 | { |
1037 | if (val > max) | |
1038 | return 0; | |
1039 | return 1; | |
1040 | } | |
1041 | ||
1042 | /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. | |
1043 | (e.g. -15 to +31). */ | |
1044 | ||
5a49b8ac AM |
1045 | static inline int |
1046 | in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
1047 | { |
1048 | if (max <= 0) | |
1049 | abort (); | |
1050 | if (val > max) | |
1051 | return 0; | |
1052 | if (val < ~(max >> 1)) | |
1053 | return 0; | |
1054 | return 1; | |
1055 | } | |
1056 | ||
1057 | static int | |
5a49b8ac | 1058 | sparc_ffs (unsigned int mask) |
252b5132 RH |
1059 | { |
1060 | int i; | |
1061 | ||
1062 | if (mask == 0) | |
1063 | return -1; | |
1064 | ||
1065 | for (i = 0; (mask & 1) == 0; ++i) | |
1066 | mask >>= 1; | |
1067 | return i; | |
1068 | } | |
1069 | ||
1070 | /* Implement big shift right. */ | |
1071 | static bfd_vma | |
5a49b8ac | 1072 | BSR (bfd_vma val, int amount) |
252b5132 RH |
1073 | { |
1074 | if (sizeof (bfd_vma) <= 4 && amount >= 32) | |
1075 | as_fatal (_("Support for 64-bit arithmetic not compiled in.")); | |
1076 | return val >> amount; | |
1077 | } | |
1078 | \f | |
1079 | /* For communication between sparc_ip and get_expression. */ | |
1080 | static char *expr_end; | |
1081 | ||
252b5132 RH |
1082 | /* Values for `special_case'. |
1083 | Instructions that require wierd handling because they're longer than | |
1084 | 4 bytes. */ | |
1085 | #define SPECIAL_CASE_NONE 0 | |
1086 | #define SPECIAL_CASE_SET 1 | |
1087 | #define SPECIAL_CASE_SETSW 2 | |
1088 | #define SPECIAL_CASE_SETX 3 | |
1089 | /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ | |
1090 | #define SPECIAL_CASE_FDIV 4 | |
1091 | ||
1092 | /* Bit masks of various insns. */ | |
1093 | #define NOP_INSN 0x01000000 | |
1094 | #define OR_INSN 0x80100000 | |
63fab58c | 1095 | #define XOR_INSN 0x80180000 |
252b5132 RH |
1096 | #define FMOVS_INSN 0x81A00020 |
1097 | #define SETHI_INSN 0x01000000 | |
1098 | #define SLLX_INSN 0x81281000 | |
1099 | #define SRA_INSN 0x81380000 | |
1100 | ||
1101 | /* The last instruction to be assembled. */ | |
1102 | static const struct sparc_opcode *last_insn; | |
1103 | /* The assembled opcode of `last_insn'. */ | |
1104 | static unsigned long last_opcode; | |
1105 | \f | |
a22b281c | 1106 | /* Handle the set and setuw synthetic instructions. */ |
e0c6ed95 | 1107 | |
a22b281c | 1108 | static void |
5a49b8ac | 1109 | synthetize_setuw (const struct sparc_opcode *insn) |
a22b281c RH |
1110 | { |
1111 | int need_hi22_p = 0; | |
1112 | int rd = (the_insn.opcode & RD (~0)) >> 25; | |
1113 | ||
1114 | if (the_insn.exp.X_op == O_constant) | |
1115 | { | |
1116 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1117 | { | |
e0c6ed95 | 1118 | if (sizeof (offsetT) > 4 |
a22b281c | 1119 | && (the_insn.exp.X_add_number < 0 |
6c1b24e4 | 1120 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) |
a22b281c RH |
1121 | as_warn (_("set: number not in 0..4294967295 range")); |
1122 | } | |
1123 | else | |
1124 | { | |
e0c6ed95 | 1125 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1126 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1127 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c | 1128 | as_warn (_("set: number not in -2147483648..4294967295 range")); |
e0c6ed95 | 1129 | the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; |
a22b281c RH |
1130 | } |
1131 | } | |
1132 | ||
1133 | /* See if operand is absolute and small; skip sethi if so. */ | |
1134 | if (the_insn.exp.X_op != O_constant | |
1135 | || the_insn.exp.X_add_number >= (1 << 12) | |
1136 | || the_insn.exp.X_add_number < -(1 << 12)) | |
1137 | { | |
1138 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1139 | | ((the_insn.exp.X_add_number >> 10) | |
ab3e48dc KH |
1140 | & (the_insn.exp.X_op == O_constant |
1141 | ? 0x3fffff : 0))); | |
a22b281c | 1142 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1143 | ? BFD_RELOC_HI22 : BFD_RELOC_NONE); |
a22b281c RH |
1144 | output_insn (insn, &the_insn); |
1145 | need_hi22_p = 1; | |
1146 | } | |
1147 | ||
1148 | /* See if operand has no low-order bits; skip OR if so. */ | |
1149 | if (the_insn.exp.X_op != O_constant | |
1150 | || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) | |
1151 | || ! need_hi22_p) | |
1152 | { | |
1153 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) | |
1154 | | RD (rd) | IMMED | |
1155 | | (the_insn.exp.X_add_number | |
ab3e48dc KH |
1156 | & (the_insn.exp.X_op != O_constant |
1157 | ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); | |
a22b281c | 1158 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1159 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); |
a22b281c RH |
1160 | output_insn (insn, &the_insn); |
1161 | } | |
1162 | } | |
e0c6ed95 | 1163 | |
a22b281c | 1164 | /* Handle the setsw synthetic instruction. */ |
e0c6ed95 | 1165 | |
a22b281c | 1166 | static void |
5a49b8ac | 1167 | synthetize_setsw (const struct sparc_opcode *insn) |
a22b281c RH |
1168 | { |
1169 | int low32, rd, opc; | |
1170 | ||
1171 | rd = (the_insn.opcode & RD (~0)) >> 25; | |
1172 | ||
1173 | if (the_insn.exp.X_op != O_constant) | |
1174 | { | |
1175 | synthetize_setuw (insn); | |
1176 | ||
1177 | /* Need to sign extend it. */ | |
1178 | the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); | |
1179 | the_insn.reloc = BFD_RELOC_NONE; | |
1180 | output_insn (insn, &the_insn); | |
1181 | return; | |
1182 | } | |
1183 | ||
e0c6ed95 | 1184 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1185 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1186 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c RH |
1187 | as_warn (_("setsw: number not in -2147483648..4294967295 range")); |
1188 | ||
e0c6ed95 AM |
1189 | low32 = the_insn.exp.X_add_number; |
1190 | ||
a22b281c RH |
1191 | if (low32 >= 0) |
1192 | { | |
1193 | synthetize_setuw (insn); | |
1194 | return; | |
1195 | } | |
1196 | ||
1197 | opc = OR_INSN; | |
e0c6ed95 | 1198 | |
a22b281c RH |
1199 | the_insn.reloc = BFD_RELOC_NONE; |
1200 | /* See if operand is absolute and small; skip sethi if so. */ | |
1201 | if (low32 < -(1 << 12)) | |
1202 | { | |
1203 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1204 | | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); | |
1205 | output_insn (insn, &the_insn); | |
1206 | low32 = 0x1c00 | (low32 & 0x3ff); | |
1207 | opc = RS1 (rd) | XOR_INSN; | |
1208 | } | |
1209 | ||
1210 | the_insn.opcode = (opc | RD (rd) | IMMED | |
1211 | | (low32 & 0x1fff)); | |
1212 | output_insn (insn, &the_insn); | |
1213 | } | |
1214 | ||
0d495746 | 1215 | /* Handle the setx synthetic instruction. */ |
e0c6ed95 | 1216 | |
a22b281c | 1217 | static void |
5a49b8ac | 1218 | synthetize_setx (const struct sparc_opcode *insn) |
a22b281c RH |
1219 | { |
1220 | int upper32, lower32; | |
1221 | int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; | |
1222 | int dstreg = (the_insn.opcode & RD (~0)) >> 25; | |
1223 | int upper_dstreg; | |
1224 | int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; | |
1225 | int need_xor10_p = 0; | |
e0c6ed95 | 1226 | |
6c1b24e4 | 1227 | #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) |
a22b281c RH |
1228 | lower32 = SIGNEXT32 (the_insn.exp.X_add_number); |
1229 | upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); | |
1230 | #undef SIGNEXT32 | |
1231 | ||
1232 | upper_dstreg = tmpreg; | |
1233 | /* The tmp reg should not be the dst reg. */ | |
1234 | if (tmpreg == dstreg) | |
1235 | as_warn (_("setx: temporary register same as destination register")); | |
1236 | ||
1237 | /* ??? Obviously there are other optimizations we can do | |
1238 | (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be | |
1239 | doing some of these. Later. If you do change things, try to | |
1240 | change all of this to be table driven as well. */ | |
1241 | /* What to output depends on the number if it's constant. | |
1242 | Compute that first, then output what we've decided upon. */ | |
1243 | if (the_insn.exp.X_op != O_constant) | |
1244 | { | |
1245 | if (sparc_arch_size == 32) | |
1246 | { | |
1247 | /* When arch size is 32, we want setx to be equivalent | |
1248 | to setuw for anything but constants. */ | |
1249 | the_insn.exp.X_add_number &= 0xffffffff; | |
1250 | synthetize_setuw (insn); | |
1251 | return; | |
1252 | } | |
1253 | need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; | |
ab3e48dc KH |
1254 | lower32 = 0; |
1255 | upper32 = 0; | |
a22b281c RH |
1256 | } |
1257 | else | |
1258 | { | |
1259 | /* Reset X_add_number, we've extracted it as upper32/lower32. | |
1260 | Otherwise fixup_segment will complain about not being able to | |
1261 | write an 8 byte number in a 4 byte field. */ | |
1262 | the_insn.exp.X_add_number = 0; | |
e0c6ed95 | 1263 | |
a22b281c RH |
1264 | /* Only need hh22 if `or' insn can't handle constant. */ |
1265 | if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) | |
1266 | need_hh22_p = 1; | |
e0c6ed95 | 1267 | |
a22b281c RH |
1268 | /* Does bottom part (after sethi) have bits? */ |
1269 | if ((need_hh22_p && (upper32 & 0x3ff) != 0) | |
1270 | /* No hh22, but does upper32 still have bits we can't set | |
1271 | from lower32? */ | |
1272 | || (! need_hh22_p && upper32 != 0 && upper32 != -1)) | |
1273 | need_hm10_p = 1; | |
e0c6ed95 | 1274 | |
a22b281c RH |
1275 | /* If the lower half is all zero, we build the upper half directly |
1276 | into the dst reg. */ | |
1277 | if (lower32 != 0 | |
1278 | /* Need lower half if number is zero or 0xffffffff00000000. */ | |
1279 | || (! need_hh22_p && ! need_hm10_p)) | |
1280 | { | |
1281 | /* No need for sethi if `or' insn can handle constant. */ | |
1282 | if (lower32 < -(1 << 12) || lower32 >= (1 << 12) | |
1283 | /* Note that we can't use a negative constant in the `or' | |
1284 | insn unless the upper 32 bits are all ones. */ | |
1285 | || (lower32 < 0 && upper32 != -1) | |
1286 | || (lower32 >= 0 && upper32 == -1)) | |
1287 | need_hi22_p = 1; | |
e0c6ed95 | 1288 | |
a22b281c RH |
1289 | if (need_hi22_p && upper32 == -1) |
1290 | need_xor10_p = 1; | |
1291 | ||
1292 | /* Does bottom part (after sethi) have bits? */ | |
1293 | else if ((need_hi22_p && (lower32 & 0x3ff) != 0) | |
1294 | /* No sethi. */ | |
1295 | || (! need_hi22_p && (lower32 & 0x1fff) != 0) | |
1296 | /* Need `or' if we didn't set anything else. */ | |
1297 | || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) | |
1298 | need_lo10_p = 1; | |
1299 | } | |
1300 | else | |
1301 | /* Output directly to dst reg if lower 32 bits are all zero. */ | |
1302 | upper_dstreg = dstreg; | |
1303 | } | |
e0c6ed95 | 1304 | |
a22b281c RH |
1305 | if (!upper_dstreg && dstreg) |
1306 | as_warn (_("setx: illegal temporary register g0")); | |
1307 | ||
1308 | if (need_hh22_p) | |
1309 | { | |
1310 | the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) | |
1311 | | ((upper32 >> 10) & 0x3fffff)); | |
1312 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1313 | ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); | |
1314 | output_insn (insn, &the_insn); | |
1315 | } | |
e0c6ed95 | 1316 | |
a22b281c RH |
1317 | if (need_hi22_p) |
1318 | { | |
1319 | the_insn.opcode = (SETHI_INSN | RD (dstreg) | |
1320 | | (((need_xor10_p ? ~lower32 : lower32) | |
ab3e48dc | 1321 | >> 10) & 0x3fffff)); |
a22b281c RH |
1322 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
1323 | ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); | |
1324 | output_insn (insn, &the_insn); | |
1325 | } | |
1326 | ||
1327 | if (need_hm10_p) | |
1328 | { | |
1329 | the_insn.opcode = (OR_INSN | |
1330 | | (need_hh22_p ? RS1 (upper_dstreg) : 0) | |
1331 | | RD (upper_dstreg) | |
1332 | | IMMED | |
1333 | | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); | |
1334 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1335 | ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); | |
1336 | output_insn (insn, &the_insn); | |
1337 | } | |
e0c6ed95 | 1338 | |
a22b281c RH |
1339 | if (need_lo10_p) |
1340 | { | |
1341 | /* FIXME: One nice optimization to do here is to OR the low part | |
1342 | with the highpart if hi22 isn't needed and the low part is | |
1343 | positive. */ | |
1344 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) | |
1345 | | RD (dstreg) | |
1346 | | IMMED | |
1347 | | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); | |
1348 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1349 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); | |
1350 | output_insn (insn, &the_insn); | |
1351 | } | |
e0c6ed95 | 1352 | |
a22b281c RH |
1353 | /* If we needed to build the upper part, shift it into place. */ |
1354 | if (need_hh22_p || need_hm10_p) | |
1355 | { | |
1356 | the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) | |
1357 | | IMMED | 32); | |
1358 | the_insn.reloc = BFD_RELOC_NONE; | |
1359 | output_insn (insn, &the_insn); | |
1360 | } | |
e0c6ed95 | 1361 | |
a22b281c RH |
1362 | /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ |
1363 | if (need_xor10_p) | |
1364 | { | |
1365 | the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED | |
1366 | | 0x1c00 | (lower32 & 0x3ff)); | |
1367 | the_insn.reloc = BFD_RELOC_NONE; | |
1368 | output_insn (insn, &the_insn); | |
1369 | } | |
1370 | ||
1371 | /* If we needed to build both upper and lower parts, OR them together. */ | |
1372 | else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) | |
1373 | { | |
1374 | the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) | |
1375 | | RD (dstreg)); | |
1376 | the_insn.reloc = BFD_RELOC_NONE; | |
1377 | output_insn (insn, &the_insn); | |
1378 | } | |
1379 | } | |
1380 | \f | |
252b5132 RH |
1381 | /* Main entry point to assemble one instruction. */ |
1382 | ||
1383 | void | |
5a49b8ac | 1384 | md_assemble (char *str) |
252b5132 RH |
1385 | { |
1386 | const struct sparc_opcode *insn; | |
a22b281c | 1387 | int special_case; |
252b5132 RH |
1388 | |
1389 | know (str); | |
a22b281c | 1390 | special_case = sparc_ip (str, &insn); |
b0825cc2 DM |
1391 | if (insn == NULL) |
1392 | return; | |
252b5132 RH |
1393 | |
1394 | /* We warn about attempts to put a floating point branch in a delay slot, | |
1395 | unless the delay slot has been annulled. */ | |
b0825cc2 | 1396 | if (last_insn != NULL |
252b5132 RH |
1397 | && (insn->flags & F_FBR) != 0 |
1398 | && (last_insn->flags & F_DELAYED) != 0 | |
1399 | /* ??? This test isn't completely accurate. We assume anything with | |
1400 | F_{UNBR,CONDBR,FBR} set is annullable. */ | |
1401 | && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 | |
1402 | || (last_opcode & ANNUL) == 0)) | |
1403 | as_warn (_("FP branch in delay slot")); | |
1404 | ||
1405 | /* SPARC before v9 requires a nop instruction between a floating | |
1406 | point instruction and a floating point branch. We insert one | |
1407 | automatically, with a warning. */ | |
1408 | if (max_architecture < SPARC_OPCODE_ARCH_V9 | |
252b5132 RH |
1409 | && last_insn != NULL |
1410 | && (insn->flags & F_FBR) != 0 | |
1411 | && (last_insn->flags & F_FLOAT) != 0) | |
1412 | { | |
1413 | struct sparc_it nop_insn; | |
1414 | ||
1415 | nop_insn.opcode = NOP_INSN; | |
1416 | nop_insn.reloc = BFD_RELOC_NONE; | |
1417 | output_insn (insn, &nop_insn); | |
1418 | as_warn (_("FP branch preceded by FP instruction; NOP inserted")); | |
1419 | } | |
1420 | ||
a22b281c RH |
1421 | switch (special_case) |
1422 | { | |
1423 | case SPECIAL_CASE_NONE: | |
e0c6ed95 | 1424 | /* Normal insn. */ |
a22b281c RH |
1425 | output_insn (insn, &the_insn); |
1426 | break; | |
252b5132 | 1427 | |
a22b281c RH |
1428 | case SPECIAL_CASE_SETSW: |
1429 | synthetize_setsw (insn); | |
1430 | break; | |
e0c6ed95 | 1431 | |
a22b281c RH |
1432 | case SPECIAL_CASE_SET: |
1433 | synthetize_setuw (insn); | |
1434 | break; | |
252b5132 | 1435 | |
a22b281c RH |
1436 | case SPECIAL_CASE_SETX: |
1437 | synthetize_setx (insn); | |
1438 | break; | |
e0c6ed95 | 1439 | |
a22b281c RH |
1440 | case SPECIAL_CASE_FDIV: |
1441 | { | |
1442 | int rd = (the_insn.opcode >> 25) & 0x1f; | |
e0c6ed95 | 1443 | |
a22b281c | 1444 | output_insn (insn, &the_insn); |
e0c6ed95 | 1445 | |
a22b281c RH |
1446 | /* According to information leaked from Sun, the "fdiv" instructions |
1447 | on early SPARC machines would produce incorrect results sometimes. | |
1448 | The workaround is to add an fmovs of the destination register to | |
1449 | itself just after the instruction. This was true on machines | |
e0c6ed95 | 1450 | with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ |
9c2799c2 | 1451 | gas_assert (the_insn.reloc == BFD_RELOC_NONE); |
a22b281c RH |
1452 | the_insn.opcode = FMOVS_INSN | rd | RD (rd); |
1453 | output_insn (insn, &the_insn); | |
1454 | return; | |
1455 | } | |
e0c6ed95 | 1456 | |
a22b281c RH |
1457 | default: |
1458 | as_fatal (_("failed special case insn sanity check")); | |
252b5132 RH |
1459 | } |
1460 | } | |
1461 | ||
4bafe00e | 1462 | static const char * |
3d68f91c | 1463 | get_hwcap_name (bfd_uint64_t mask) |
4bafe00e | 1464 | { |
ec668d69 | 1465 | if (mask & HWCAP_MUL32) |
4bafe00e | 1466 | return "mul32"; |
ec668d69 | 1467 | if (mask & HWCAP_DIV32) |
4bafe00e | 1468 | return "div32"; |
ec668d69 | 1469 | if (mask & HWCAP_FSMULD) |
4bafe00e | 1470 | return "fsmuld"; |
ec668d69 | 1471 | if (mask & HWCAP_V8PLUS) |
4bafe00e | 1472 | return "v8plus"; |
ec668d69 | 1473 | if (mask & HWCAP_POPC) |
4bafe00e | 1474 | return "popc"; |
ec668d69 | 1475 | if (mask & HWCAP_VIS) |
4bafe00e | 1476 | return "vis"; |
ec668d69 | 1477 | if (mask & HWCAP_VIS2) |
4bafe00e | 1478 | return "vis2"; |
ec668d69 | 1479 | if (mask & HWCAP_ASI_BLK_INIT) |
4bafe00e | 1480 | return "ASIBlkInit"; |
ec668d69 | 1481 | if (mask & HWCAP_FMAF) |
4bafe00e | 1482 | return "fmaf"; |
ec668d69 | 1483 | if (mask & HWCAP_VIS3) |
4bafe00e | 1484 | return "vis3"; |
ec668d69 | 1485 | if (mask & HWCAP_HPC) |
4bafe00e | 1486 | return "hpc"; |
ec668d69 | 1487 | if (mask & HWCAP_RANDOM) |
4bafe00e | 1488 | return "random"; |
ec668d69 | 1489 | if (mask & HWCAP_TRANS) |
4bafe00e | 1490 | return "trans"; |
ec668d69 | 1491 | if (mask & HWCAP_FJFMAU) |
4bafe00e | 1492 | return "fjfmau"; |
ec668d69 | 1493 | if (mask & HWCAP_IMA) |
4bafe00e | 1494 | return "ima"; |
ec668d69 | 1495 | if (mask & HWCAP_ASI_CACHE_SPARING) |
4bafe00e | 1496 | return "cspare"; |
ec668d69 DM |
1497 | if (mask & HWCAP_AES) |
1498 | return "aes"; | |
1499 | if (mask & HWCAP_DES) | |
1500 | return "des"; | |
1501 | if (mask & HWCAP_KASUMI) | |
1502 | return "kasumi"; | |
1503 | if (mask & HWCAP_CAMELLIA) | |
1504 | return "camellia"; | |
1505 | if (mask & HWCAP_MD5) | |
1506 | return "md5"; | |
1507 | if (mask & HWCAP_SHA1) | |
1508 | return "sha1"; | |
1509 | if (mask & HWCAP_SHA256) | |
1510 | return "sha256"; | |
1511 | if (mask & HWCAP_SHA512) | |
1512 | return "sha512"; | |
1513 | if (mask & HWCAP_MPMUL) | |
1514 | return "mpmul"; | |
1515 | if (mask & HWCAP_MONT) | |
1516 | return "mont"; | |
1517 | if (mask & HWCAP_PAUSE) | |
1518 | return "pause"; | |
1519 | if (mask & HWCAP_CBCOND) | |
1520 | return "cbcond"; | |
1521 | if (mask & HWCAP_CRC32C) | |
1522 | return "crc32c"; | |
3d68f91c JM |
1523 | |
1524 | mask = mask >> 32; | |
1525 | if (mask & HWCAP2_FJATHPLUS) | |
1526 | return "fjathplus"; | |
1527 | if (mask & HWCAP2_VIS3B) | |
1528 | return "vis3b"; | |
1529 | if (mask & HWCAP2_ADP) | |
1530 | return "adp"; | |
1531 | if (mask & HWCAP2_SPARC5) | |
1532 | return "sparc5"; | |
1533 | if (mask & HWCAP2_MWAIT) | |
1534 | return "mwait"; | |
1535 | if (mask & HWCAP2_XMPMUL) | |
1536 | return "xmpmul"; | |
1537 | if (mask & HWCAP2_XMONT) | |
1538 | return "xmont"; | |
1539 | if (mask & HWCAP2_NSEC) | |
1540 | return "nsec"; | |
1541 | ||
4bafe00e DM |
1542 | return "UNKNOWN"; |
1543 | } | |
1544 | ||
252b5132 RH |
1545 | /* Subroutine of md_assemble to do the actual parsing. */ |
1546 | ||
a22b281c | 1547 | static int |
5a49b8ac | 1548 | sparc_ip (char *str, const struct sparc_opcode **pinsn) |
252b5132 RH |
1549 | { |
1550 | char *error_message = ""; | |
1551 | char *s; | |
1552 | const char *args; | |
1553 | char c; | |
1554 | const struct sparc_opcode *insn; | |
1555 | char *argsStart; | |
1556 | unsigned long opcode; | |
1557 | unsigned int mask = 0; | |
1558 | int match = 0; | |
1559 | int comma = 0; | |
1560 | int v9_arg_p; | |
a22b281c | 1561 | int special_case = SPECIAL_CASE_NONE; |
252b5132 RH |
1562 | |
1563 | s = str; | |
3882b010 | 1564 | if (ISLOWER (*s)) |
252b5132 RH |
1565 | { |
1566 | do | |
1567 | ++s; | |
6cda1326 | 1568 | while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_'); |
252b5132 RH |
1569 | } |
1570 | ||
1571 | switch (*s) | |
1572 | { | |
1573 | case '\0': | |
1574 | break; | |
1575 | ||
1576 | case ',': | |
1577 | comma = 1; | |
e0c6ed95 | 1578 | /* Fall through. */ |
252b5132 RH |
1579 | |
1580 | case ' ': | |
1581 | *s++ = '\0'; | |
1582 | break; | |
1583 | ||
1584 | default: | |
b0825cc2 DM |
1585 | as_bad (_("Unknown opcode: `%s'"), str); |
1586 | *pinsn = NULL; | |
1587 | return special_case; | |
252b5132 RH |
1588 | } |
1589 | insn = (struct sparc_opcode *) hash_find (op_hash, str); | |
1590 | *pinsn = insn; | |
1591 | if (insn == NULL) | |
1592 | { | |
1593 | as_bad (_("Unknown opcode: `%s'"), str); | |
a22b281c | 1594 | return special_case; |
252b5132 RH |
1595 | } |
1596 | if (comma) | |
1597 | { | |
1598 | *--s = ','; | |
1599 | } | |
1600 | ||
1601 | argsStart = s; | |
1602 | for (;;) | |
1603 | { | |
1604 | opcode = insn->match; | |
1605 | memset (&the_insn, '\0', sizeof (the_insn)); | |
1606 | the_insn.reloc = BFD_RELOC_NONE; | |
1607 | v9_arg_p = 0; | |
1608 | ||
e0c6ed95 AM |
1609 | /* Build the opcode, checking as we go to make sure that the |
1610 | operands match. */ | |
252b5132 RH |
1611 | for (args = insn->args;; ++args) |
1612 | { | |
1613 | switch (*args) | |
1614 | { | |
1615 | case 'K': | |
1616 | { | |
1617 | int kmask = 0; | |
1618 | ||
1619 | /* Parse a series of masks. */ | |
1620 | if (*s == '#') | |
1621 | { | |
1622 | while (*s == '#') | |
1623 | { | |
91d6fa6a | 1624 | int jmask; |
252b5132 RH |
1625 | |
1626 | if (! parse_keyword_arg (sparc_encode_membar, &s, | |
91d6fa6a | 1627 | &jmask)) |
252b5132 RH |
1628 | { |
1629 | error_message = _(": invalid membar mask name"); | |
1630 | goto error; | |
1631 | } | |
91d6fa6a | 1632 | kmask |= jmask; |
47926f60 KH |
1633 | while (*s == ' ') |
1634 | ++s; | |
252b5132 RH |
1635 | if (*s == '|' || *s == '+') |
1636 | ++s; | |
47926f60 KH |
1637 | while (*s == ' ') |
1638 | ++s; | |
252b5132 RH |
1639 | } |
1640 | } | |
1641 | else | |
1642 | { | |
1643 | if (! parse_const_expr_arg (&s, &kmask)) | |
1644 | { | |
1645 | error_message = _(": invalid membar mask expression"); | |
1646 | goto error; | |
1647 | } | |
1648 | if (kmask < 0 || kmask > 127) | |
1649 | { | |
1650 | error_message = _(": invalid membar mask number"); | |
1651 | goto error; | |
1652 | } | |
1653 | } | |
1654 | ||
1655 | opcode |= MEMBAR (kmask); | |
1656 | continue; | |
1657 | } | |
1658 | ||
19f7b010 JJ |
1659 | case '3': |
1660 | { | |
1661 | int smask = 0; | |
1662 | ||
1663 | if (! parse_const_expr_arg (&s, &smask)) | |
1664 | { | |
1665 | error_message = _(": invalid siam mode expression"); | |
1666 | goto error; | |
1667 | } | |
1668 | if (smask < 0 || smask > 7) | |
1669 | { | |
1670 | error_message = _(": invalid siam mode number"); | |
1671 | goto error; | |
1672 | } | |
1673 | opcode |= smask; | |
1674 | continue; | |
1675 | } | |
1676 | ||
252b5132 RH |
1677 | case '*': |
1678 | { | |
1679 | int fcn = 0; | |
1680 | ||
1681 | /* Parse a prefetch function. */ | |
1682 | if (*s == '#') | |
1683 | { | |
1684 | if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) | |
1685 | { | |
1686 | error_message = _(": invalid prefetch function name"); | |
1687 | goto error; | |
1688 | } | |
1689 | } | |
1690 | else | |
1691 | { | |
1692 | if (! parse_const_expr_arg (&s, &fcn)) | |
1693 | { | |
1694 | error_message = _(": invalid prefetch function expression"); | |
1695 | goto error; | |
1696 | } | |
1697 | if (fcn < 0 || fcn > 31) | |
1698 | { | |
1699 | error_message = _(": invalid prefetch function number"); | |
1700 | goto error; | |
1701 | } | |
1702 | } | |
1703 | opcode |= RD (fcn); | |
1704 | continue; | |
1705 | } | |
1706 | ||
1707 | case '!': | |
1708 | case '?': | |
1709 | /* Parse a sparc64 privileged register. */ | |
1710 | if (*s == '%') | |
1711 | { | |
1712 | struct priv_reg_entry *p = priv_reg_table; | |
e0c6ed95 | 1713 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1714 | |
1715 | s += 1; | |
1716 | while (p->name[0] > s[0]) | |
1717 | p++; | |
1718 | while (p->name[0] == s[0]) | |
1719 | { | |
1720 | len = strlen (p->name); | |
1721 | if (strncmp (p->name, s, len) == 0) | |
1722 | break; | |
1723 | p++; | |
1724 | } | |
1725 | if (p->name[0] != s[0]) | |
1726 | { | |
1727 | error_message = _(": unrecognizable privileged register"); | |
1728 | goto error; | |
1729 | } | |
1730 | if (*args == '?') | |
1731 | opcode |= (p->regnum << 14); | |
1732 | else | |
1733 | opcode |= (p->regnum << 25); | |
1734 | s += len; | |
1735 | continue; | |
1736 | } | |
1737 | else | |
1738 | { | |
1739 | error_message = _(": unrecognizable privileged register"); | |
1740 | goto error; | |
1741 | } | |
1742 | ||
10156f83 DM |
1743 | case '$': |
1744 | case '%': | |
1745 | /* Parse a sparc64 hyperprivileged register. */ | |
1746 | if (*s == '%') | |
1747 | { | |
1748 | struct priv_reg_entry *p = hpriv_reg_table; | |
1749 | unsigned int len = 9999999; /* Init to make gcc happy. */ | |
1750 | ||
1751 | s += 1; | |
1752 | while (p->name[0] > s[0]) | |
1753 | p++; | |
1754 | while (p->name[0] == s[0]) | |
1755 | { | |
1756 | len = strlen (p->name); | |
1757 | if (strncmp (p->name, s, len) == 0) | |
1758 | break; | |
1759 | p++; | |
1760 | } | |
1761 | if (p->name[0] != s[0]) | |
1762 | { | |
1763 | error_message = _(": unrecognizable hyperprivileged register"); | |
1764 | goto error; | |
1765 | } | |
1766 | if (*args == '$') | |
1767 | opcode |= (p->regnum << 14); | |
1768 | else | |
1769 | opcode |= (p->regnum << 25); | |
1770 | s += len; | |
1771 | continue; | |
1772 | } | |
1773 | else | |
1774 | { | |
1775 | error_message = _(": unrecognizable hyperprivileged register"); | |
1776 | goto error; | |
1777 | } | |
1778 | ||
252b5132 RH |
1779 | case '_': |
1780 | case '/': | |
19f7b010 | 1781 | /* Parse a v9a/v9b ancillary state register. */ |
252b5132 RH |
1782 | if (*s == '%') |
1783 | { | |
1784 | struct priv_reg_entry *p = v9a_asr_table; | |
e0c6ed95 | 1785 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1786 | |
1787 | s += 1; | |
1788 | while (p->name[0] > s[0]) | |
1789 | p++; | |
1790 | while (p->name[0] == s[0]) | |
1791 | { | |
1792 | len = strlen (p->name); | |
1793 | if (strncmp (p->name, s, len) == 0) | |
1794 | break; | |
1795 | p++; | |
1796 | } | |
1797 | if (p->name[0] != s[0]) | |
1798 | { | |
19f7b010 | 1799 | error_message = _(": unrecognizable v9a or v9b ancillary state register"); |
252b5132 RH |
1800 | goto error; |
1801 | } | |
1802 | if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) | |
1803 | { | |
1804 | error_message = _(": rd on write only ancillary state register"); | |
1805 | goto error; | |
e0c6ed95 | 1806 | } |
19f7b010 JJ |
1807 | if (p->regnum >= 24 |
1808 | && (insn->architecture | |
1809 | & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) | |
1810 | { | |
1811 | /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ | |
1812 | error_message = _(": unrecognizable v9a ancillary state register"); | |
1813 | goto error; | |
1814 | } | |
252b5132 RH |
1815 | if (*args == '/') |
1816 | opcode |= (p->regnum << 14); | |
1817 | else | |
1818 | opcode |= (p->regnum << 25); | |
1819 | s += len; | |
1820 | continue; | |
1821 | } | |
1822 | else | |
1823 | { | |
19f7b010 | 1824 | error_message = _(": unrecognizable v9a or v9b ancillary state register"); |
252b5132 RH |
1825 | goto error; |
1826 | } | |
1827 | ||
1828 | case 'M': | |
1829 | case 'm': | |
1830 | if (strncmp (s, "%asr", 4) == 0) | |
1831 | { | |
1832 | s += 4; | |
1833 | ||
3882b010 | 1834 | if (ISDIGIT (*s)) |
252b5132 RH |
1835 | { |
1836 | long num = 0; | |
1837 | ||
3882b010 | 1838 | while (ISDIGIT (*s)) |
252b5132 RH |
1839 | { |
1840 | num = num * 10 + *s - '0'; | |
1841 | ++s; | |
1842 | } | |
1843 | ||
1844 | if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
1845 | { | |
1846 | if (num < 16 || 31 < num) | |
1847 | { | |
1848 | error_message = _(": asr number must be between 16 and 31"); | |
1849 | goto error; | |
1850 | } | |
1851 | } | |
1852 | else | |
1853 | { | |
1854 | if (num < 0 || 31 < num) | |
1855 | { | |
1856 | error_message = _(": asr number must be between 0 and 31"); | |
1857 | goto error; | |
1858 | } | |
1859 | } | |
1860 | ||
1861 | opcode |= (*args == 'M' ? RS1 (num) : RD (num)); | |
1862 | continue; | |
1863 | } | |
1864 | else | |
1865 | { | |
1866 | error_message = _(": expecting %asrN"); | |
1867 | goto error; | |
1868 | } | |
e0c6ed95 | 1869 | } /* if %asr */ |
252b5132 RH |
1870 | break; |
1871 | ||
1872 | case 'I': | |
1873 | the_insn.reloc = BFD_RELOC_SPARC_11; | |
1874 | goto immediate; | |
1875 | ||
1876 | case 'j': | |
1877 | the_insn.reloc = BFD_RELOC_SPARC_10; | |
1878 | goto immediate; | |
1879 | ||
6cda1326 DM |
1880 | case ')': |
1881 | if (*s == ' ') | |
1882 | s++; | |
1883 | if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2])) | |
1884 | || ISDIGIT (*s)) | |
1885 | { | |
1886 | long num = 0; | |
1887 | ||
1888 | if (s[0] == '0' && s[1] == 'x') | |
1889 | { | |
1890 | s += 2; | |
1891 | while (ISXDIGIT (*s)) | |
1892 | { | |
1893 | num <<= 4; | |
1894 | num |= hex_value (*s); | |
1895 | ++s; | |
1896 | } | |
1897 | } | |
1898 | else | |
1899 | { | |
1900 | while (ISDIGIT (*s)) | |
1901 | { | |
1902 | num = num * 10 + *s - '0'; | |
1903 | ++s; | |
1904 | } | |
1905 | } | |
1906 | if (num < 0 || num > 31) | |
1907 | { | |
1908 | error_message = _(": crypto immediate must be between 0 and 31"); | |
1909 | goto error; | |
1910 | } | |
1911 | ||
1912 | opcode |= RS3 (num); | |
1913 | continue; | |
1914 | } | |
1915 | else | |
1916 | { | |
1917 | error_message = _(": expecting crypto immediate"); | |
1918 | goto error; | |
1919 | } | |
1920 | ||
252b5132 RH |
1921 | case 'X': |
1922 | /* V8 systems don't understand BFD_RELOC_SPARC_5. */ | |
1923 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1924 | the_insn.reloc = BFD_RELOC_SPARC_5; | |
1925 | else | |
1926 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1927 | /* These fields are unsigned, but for upward compatibility, | |
1928 | allow negative values as well. */ | |
1929 | goto immediate; | |
1930 | ||
1931 | case 'Y': | |
1932 | /* V8 systems don't understand BFD_RELOC_SPARC_6. */ | |
1933 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1934 | the_insn.reloc = BFD_RELOC_SPARC_6; | |
1935 | else | |
1936 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1937 | /* These fields are unsigned, but for upward compatibility, | |
1938 | allow negative values as well. */ | |
1939 | goto immediate; | |
1940 | ||
1941 | case 'k': | |
1942 | the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; | |
1943 | the_insn.pcrel = 1; | |
1944 | goto immediate; | |
1945 | ||
2615994e DM |
1946 | case '=': |
1947 | the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10; | |
1948 | the_insn.pcrel = 1; | |
1949 | goto immediate; | |
1950 | ||
252b5132 RH |
1951 | case 'G': |
1952 | the_insn.reloc = BFD_RELOC_SPARC_WDISP19; | |
1953 | the_insn.pcrel = 1; | |
1954 | goto immediate; | |
1955 | ||
1956 | case 'N': | |
1957 | if (*s == 'p' && s[1] == 'n') | |
1958 | { | |
1959 | s += 2; | |
1960 | continue; | |
1961 | } | |
1962 | break; | |
1963 | ||
1964 | case 'T': | |
1965 | if (*s == 'p' && s[1] == 't') | |
1966 | { | |
1967 | s += 2; | |
1968 | continue; | |
1969 | } | |
1970 | break; | |
1971 | ||
1972 | case 'z': | |
1973 | if (*s == ' ') | |
1974 | { | |
1975 | ++s; | |
1976 | } | |
f9911beb JM |
1977 | if ((strncmp (s, "%icc", 4) == 0) |
1978 | || (sparc_arch_size == 32 && strncmp (s, "%ncc", 4) == 0)) | |
252b5132 RH |
1979 | { |
1980 | s += 4; | |
1981 | continue; | |
1982 | } | |
1983 | break; | |
1984 | ||
1985 | case 'Z': | |
1986 | if (*s == ' ') | |
1987 | { | |
1988 | ++s; | |
1989 | } | |
f9911beb JM |
1990 | if ((strncmp (s, "%xcc", 4) == 0) |
1991 | || (sparc_arch_size == 64 && strncmp (s, "%ncc", 4) == 0)) | |
252b5132 RH |
1992 | { |
1993 | s += 4; | |
1994 | continue; | |
1995 | } | |
1996 | break; | |
1997 | ||
1998 | case '6': | |
1999 | if (*s == ' ') | |
2000 | { | |
2001 | ++s; | |
2002 | } | |
2003 | if (strncmp (s, "%fcc0", 5) == 0) | |
2004 | { | |
2005 | s += 5; | |
2006 | continue; | |
2007 | } | |
2008 | break; | |
2009 | ||
2010 | case '7': | |
2011 | if (*s == ' ') | |
2012 | { | |
2013 | ++s; | |
2014 | } | |
2015 | if (strncmp (s, "%fcc1", 5) == 0) | |
2016 | { | |
2017 | s += 5; | |
2018 | continue; | |
2019 | } | |
2020 | break; | |
2021 | ||
2022 | case '8': | |
2023 | if (*s == ' ') | |
2024 | { | |
2025 | ++s; | |
2026 | } | |
2027 | if (strncmp (s, "%fcc2", 5) == 0) | |
2028 | { | |
2029 | s += 5; | |
2030 | continue; | |
2031 | } | |
2032 | break; | |
2033 | ||
2034 | case '9': | |
2035 | if (*s == ' ') | |
2036 | { | |
2037 | ++s; | |
2038 | } | |
2039 | if (strncmp (s, "%fcc3", 5) == 0) | |
2040 | { | |
2041 | s += 5; | |
2042 | continue; | |
2043 | } | |
2044 | break; | |
2045 | ||
2046 | case 'P': | |
2047 | if (strncmp (s, "%pc", 3) == 0) | |
2048 | { | |
2049 | s += 3; | |
2050 | continue; | |
2051 | } | |
2052 | break; | |
2053 | ||
2054 | case 'W': | |
2055 | if (strncmp (s, "%tick", 5) == 0) | |
2056 | { | |
2057 | s += 5; | |
2058 | continue; | |
2059 | } | |
2060 | break; | |
2061 | ||
e0c6ed95 | 2062 | case '\0': /* End of args. */ |
b9734f35 | 2063 | if (s[0] == ',' && s[1] == '%') |
252b5132 | 2064 | { |
739f7f82 | 2065 | static const struct ops |
dfeb0666 | 2066 | { |
b9734f35 JJ |
2067 | /* The name as it appears in assembler. */ |
2068 | char *name; | |
2069 | /* strlen (name), precomputed for speed */ | |
2070 | int len; | |
2071 | /* The reloc this pseudo-op translates to. */ | |
2072 | int reloc; | |
739f7f82 DM |
2073 | /* 1 if tls call. */ |
2074 | int tls_call; | |
dfeb0666 | 2075 | } |
739f7f82 | 2076 | ops[] = |
dfeb0666 | 2077 | { |
b9734f35 JJ |
2078 | { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 }, |
2079 | { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 }, | |
2080 | { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 }, | |
2081 | { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 }, | |
2082 | { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 }, | |
2083 | { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 }, | |
2084 | { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 }, | |
dfeb0666 | 2085 | { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }, |
739f7f82 | 2086 | { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 }, |
dfeb0666 | 2087 | { NULL, 0, 0, 0 } |
b9734f35 | 2088 | }; |
739f7f82 | 2089 | const struct ops *o; |
b9734f35 JJ |
2090 | char *s1; |
2091 | int npar = 0; | |
2092 | ||
739f7f82 | 2093 | for (o = ops; o->name; o++) |
b9734f35 JJ |
2094 | if (strncmp (s + 2, o->name, o->len) == 0) |
2095 | break; | |
2096 | if (o->name == NULL) | |
2097 | break; | |
2098 | ||
2099 | if (s[o->len + 2] != '(') | |
2100 | { | |
2101 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
2102 | return special_case; | |
2103 | } | |
2104 | ||
739f7f82 | 2105 | if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE) |
b9734f35 JJ |
2106 | { |
2107 | as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), | |
2108 | o->name); | |
2109 | return special_case; | |
2110 | } | |
2111 | ||
739f7f82 | 2112 | if (o->tls_call |
b9734f35 JJ |
2113 | && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 |
2114 | || the_insn.exp.X_add_number != 0 | |
2115 | || the_insn.exp.X_add_symbol | |
2116 | != symbol_find_or_make ("__tls_get_addr"))) | |
2117 | { | |
2118 | as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), | |
2119 | o->name); | |
2120 | return special_case; | |
2121 | } | |
2122 | ||
2123 | the_insn.reloc = o->reloc; | |
2124 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); | |
2125 | s += o->len + 3; | |
2126 | ||
2127 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2128 | if (*s1 == '(') | |
2129 | npar++; | |
2130 | else if (*s1 == ')') | |
2131 | { | |
2132 | if (!npar) | |
2133 | break; | |
2134 | npar--; | |
2135 | } | |
2136 | ||
2137 | if (*s1 != ')') | |
2138 | { | |
2139 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
2140 | return special_case; | |
2141 | } | |
2142 | ||
2143 | *s1 = '\0'; | |
2144 | (void) get_expression (s); | |
2145 | *s1 = ')'; | |
2146 | s = s1 + 1; | |
252b5132 | 2147 | } |
b9734f35 JJ |
2148 | if (*s == '\0') |
2149 | match = 1; | |
252b5132 RH |
2150 | break; |
2151 | ||
2152 | case '+': | |
2153 | if (*s == '+') | |
2154 | { | |
2155 | ++s; | |
2156 | continue; | |
2157 | } | |
2158 | if (*s == '-') | |
2159 | { | |
2160 | continue; | |
2161 | } | |
2162 | break; | |
2163 | ||
e0c6ed95 | 2164 | case '[': /* These must match exactly. */ |
252b5132 RH |
2165 | case ']': |
2166 | case ',': | |
2167 | case ' ': | |
2168 | if (*s++ == *args) | |
2169 | continue; | |
2170 | break; | |
2171 | ||
e0c6ed95 | 2172 | case '#': /* Must be at least one digit. */ |
3882b010 | 2173 | if (ISDIGIT (*s++)) |
252b5132 | 2174 | { |
3882b010 | 2175 | while (ISDIGIT (*s)) |
252b5132 RH |
2176 | { |
2177 | ++s; | |
2178 | } | |
2179 | continue; | |
2180 | } | |
2181 | break; | |
2182 | ||
e0c6ed95 | 2183 | case 'C': /* Coprocessor state register. */ |
252b5132 RH |
2184 | if (strncmp (s, "%csr", 4) == 0) |
2185 | { | |
2186 | s += 4; | |
2187 | continue; | |
2188 | } | |
2189 | break; | |
2190 | ||
e0c6ed95 | 2191 | case 'b': /* Next operand is a coprocessor register. */ |
252b5132 RH |
2192 | case 'c': |
2193 | case 'D': | |
3882b010 | 2194 | if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) |
252b5132 RH |
2195 | { |
2196 | mask = *s++; | |
3882b010 | 2197 | if (ISDIGIT (*s)) |
252b5132 RH |
2198 | { |
2199 | mask = 10 * (mask - '0') + (*s++ - '0'); | |
2200 | if (mask >= 32) | |
2201 | { | |
2202 | break; | |
2203 | } | |
2204 | } | |
2205 | else | |
2206 | { | |
2207 | mask -= '0'; | |
2208 | } | |
2209 | switch (*args) | |
2210 | { | |
2211 | ||
2212 | case 'b': | |
2213 | opcode |= mask << 14; | |
2214 | continue; | |
2215 | ||
2216 | case 'c': | |
2217 | opcode |= mask; | |
2218 | continue; | |
2219 | ||
2220 | case 'D': | |
2221 | opcode |= mask << 25; | |
2222 | continue; | |
2223 | } | |
2224 | } | |
2225 | break; | |
2226 | ||
2227 | case 'r': /* next operand must be a register */ | |
2228 | case 'O': | |
2229 | case '1': | |
2230 | case '2': | |
2231 | case 'd': | |
2232 | if (*s++ == '%') | |
2233 | { | |
2234 | switch (c = *s++) | |
2235 | { | |
2236 | ||
2237 | case 'f': /* frame pointer */ | |
2238 | if (*s++ == 'p') | |
2239 | { | |
2240 | mask = 0x1e; | |
2241 | break; | |
2242 | } | |
2243 | goto error; | |
2244 | ||
2245 | case 'g': /* global register */ | |
a22b281c RH |
2246 | c = *s++; |
2247 | if (isoctal (c)) | |
252b5132 RH |
2248 | { |
2249 | mask = c - '0'; | |
2250 | break; | |
2251 | } | |
2252 | goto error; | |
2253 | ||
2254 | case 'i': /* in register */ | |
a22b281c RH |
2255 | c = *s++; |
2256 | if (isoctal (c)) | |
252b5132 RH |
2257 | { |
2258 | mask = c - '0' + 24; | |
2259 | break; | |
2260 | } | |
2261 | goto error; | |
2262 | ||
2263 | case 'l': /* local register */ | |
a22b281c RH |
2264 | c = *s++; |
2265 | if (isoctal (c)) | |
252b5132 RH |
2266 | { |
2267 | mask = (c - '0' + 16); | |
2268 | break; | |
2269 | } | |
2270 | goto error; | |
2271 | ||
2272 | case 'o': /* out register */ | |
a22b281c RH |
2273 | c = *s++; |
2274 | if (isoctal (c)) | |
252b5132 RH |
2275 | { |
2276 | mask = (c - '0' + 8); | |
2277 | break; | |
2278 | } | |
2279 | goto error; | |
2280 | ||
2281 | case 's': /* stack pointer */ | |
2282 | if (*s++ == 'p') | |
2283 | { | |
2284 | mask = 0xe; | |
2285 | break; | |
2286 | } | |
2287 | goto error; | |
2288 | ||
2289 | case 'r': /* any register */ | |
3882b010 | 2290 | if (!ISDIGIT ((c = *s++))) |
252b5132 RH |
2291 | { |
2292 | goto error; | |
2293 | } | |
2294 | /* FALLTHROUGH */ | |
2295 | case '0': | |
2296 | case '1': | |
2297 | case '2': | |
2298 | case '3': | |
2299 | case '4': | |
2300 | case '5': | |
2301 | case '6': | |
2302 | case '7': | |
2303 | case '8': | |
2304 | case '9': | |
3882b010 | 2305 | if (ISDIGIT (*s)) |
252b5132 RH |
2306 | { |
2307 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) | |
2308 | { | |
2309 | goto error; | |
2310 | } | |
2311 | } | |
2312 | else | |
2313 | { | |
2314 | c -= '0'; | |
2315 | } | |
2316 | mask = c; | |
2317 | break; | |
2318 | ||
2319 | default: | |
2320 | goto error; | |
2321 | } | |
2322 | ||
6d8809aa | 2323 | if ((mask & ~1) == 2 && sparc_arch_size == 64 |
e0c6ed95 | 2324 | && no_undeclared_regs && ! globals[mask]) |
79bd78be | 2325 | as_bad (_("detected global register use not covered by .register pseudo-op")); |
6d8809aa | 2326 | |
252b5132 RH |
2327 | /* Got the register, now figure out where |
2328 | it goes in the opcode. */ | |
2329 | switch (*args) | |
2330 | { | |
2331 | case '1': | |
2332 | opcode |= mask << 14; | |
2333 | continue; | |
2334 | ||
2335 | case '2': | |
2336 | opcode |= mask; | |
2337 | continue; | |
2338 | ||
2339 | case 'd': | |
2340 | opcode |= mask << 25; | |
2341 | continue; | |
2342 | ||
2343 | case 'r': | |
2344 | opcode |= (mask << 25) | (mask << 14); | |
2345 | continue; | |
2346 | ||
2347 | case 'O': | |
2348 | opcode |= (mask << 25) | (mask << 0); | |
2349 | continue; | |
2350 | } | |
2351 | } | |
2352 | break; | |
2353 | ||
2354 | case 'e': /* next operand is a floating point register */ | |
2355 | case 'v': | |
2356 | case 'V': | |
2357 | ||
2358 | case 'f': | |
2359 | case 'B': | |
2360 | case 'R': | |
2361 | ||
ea783ef3 DM |
2362 | case '4': |
2363 | case '5': | |
2364 | ||
252b5132 RH |
2365 | case 'g': |
2366 | case 'H': | |
2367 | case 'J': | |
3d68f91c | 2368 | case '}': |
252b5132 RH |
2369 | { |
2370 | char format; | |
2371 | ||
2372 | if (*s++ == '%' | |
2373 | && ((format = *s) == 'f') | |
3882b010 | 2374 | && ISDIGIT (*++s)) |
252b5132 | 2375 | { |
3882b010 | 2376 | for (mask = 0; ISDIGIT (*s); ++s) |
252b5132 RH |
2377 | { |
2378 | mask = 10 * mask + (*s - '0'); | |
2379 | } /* read the number */ | |
2380 | ||
2381 | if ((*args == 'v' | |
2382 | || *args == 'B' | |
ea783ef3 | 2383 | || *args == '5' |
252b5132 RH |
2384 | || *args == 'H') |
2385 | && (mask & 1)) | |
2386 | { | |
2387 | break; | |
2388 | } /* register must be even numbered */ | |
2389 | ||
2390 | if ((*args == 'V' | |
2391 | || *args == 'R' | |
2392 | || *args == 'J') | |
2393 | && (mask & 3)) | |
2394 | { | |
2395 | break; | |
2396 | } /* register must be multiple of 4 */ | |
2397 | ||
2398 | if (mask >= 64) | |
2399 | { | |
2400 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2401 | error_message = _(": There are only 64 f registers; [0-63]"); | |
2402 | else | |
2403 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2404 | goto error; | |
2405 | } /* on error */ | |
2406 | else if (mask >= 32) | |
2407 | { | |
2408 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2409 | { | |
26664553 JJ |
2410 | if (*args == 'e' || *args == 'f' || *args == 'g') |
2411 | { | |
2412 | error_message | |
2413 | = _(": There are only 32 single precision f registers; [0-31]"); | |
2414 | goto error; | |
2415 | } | |
252b5132 RH |
2416 | v9_arg_p = 1; |
2417 | mask -= 31; /* wrap high bit */ | |
2418 | } | |
2419 | else | |
2420 | { | |
2421 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2422 | goto error; | |
2423 | } | |
2424 | } | |
2425 | } | |
2426 | else | |
2427 | { | |
2428 | break; | |
ab3e48dc | 2429 | } /* if not an 'f' register. */ |
252b5132 | 2430 | |
3d68f91c JM |
2431 | if (*args == '}' && mask != RS2 (opcode)) |
2432 | { | |
2433 | error_message | |
2434 | = _(": Instruction requires frs2 and frsd must be the same register"); | |
2435 | goto error; | |
2436 | } | |
2437 | ||
252b5132 RH |
2438 | switch (*args) |
2439 | { | |
2440 | case 'v': | |
2441 | case 'V': | |
2442 | case 'e': | |
2443 | opcode |= RS1 (mask); | |
2444 | continue; | |
2445 | ||
252b5132 RH |
2446 | case 'f': |
2447 | case 'B': | |
2448 | case 'R': | |
2449 | opcode |= RS2 (mask); | |
2450 | continue; | |
2451 | ||
ea783ef3 DM |
2452 | case '4': |
2453 | case '5': | |
2454 | opcode |= RS3 (mask); | |
2455 | continue; | |
2456 | ||
252b5132 RH |
2457 | case 'g': |
2458 | case 'H': | |
2459 | case 'J': | |
3d68f91c | 2460 | case '}': |
252b5132 RH |
2461 | opcode |= RD (mask); |
2462 | continue; | |
ab3e48dc | 2463 | } /* Pack it in. */ |
252b5132 RH |
2464 | |
2465 | know (0); | |
2466 | break; | |
ab3e48dc | 2467 | } /* float arg */ |
252b5132 RH |
2468 | |
2469 | case 'F': | |
2470 | if (strncmp (s, "%fsr", 4) == 0) | |
2471 | { | |
2472 | s += 4; | |
2473 | continue; | |
2474 | } | |
2475 | break; | |
2476 | ||
ea783ef3 DM |
2477 | case '(': |
2478 | if (strncmp (s, "%efsr", 5) == 0) | |
2479 | { | |
2480 | s += 5; | |
2481 | continue; | |
2482 | } | |
2483 | break; | |
2484 | ||
ab3e48dc KH |
2485 | case '0': /* 64 bit immediate (set, setsw, setx insn) */ |
2486 | the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ | |
252b5132 RH |
2487 | goto immediate; |
2488 | ||
ab3e48dc | 2489 | case 'l': /* 22 bit PC relative immediate */ |
252b5132 RH |
2490 | the_insn.reloc = BFD_RELOC_SPARC_WDISP22; |
2491 | the_insn.pcrel = 1; | |
2492 | goto immediate; | |
2493 | ||
ab3e48dc | 2494 | case 'L': /* 30 bit immediate */ |
252b5132 RH |
2495 | the_insn.reloc = BFD_RELOC_32_PCREL_S2; |
2496 | the_insn.pcrel = 1; | |
2497 | goto immediate; | |
2498 | ||
63fab58c | 2499 | case 'h': |
ab3e48dc | 2500 | case 'n': /* 22 bit immediate */ |
252b5132 RH |
2501 | the_insn.reloc = BFD_RELOC_SPARC22; |
2502 | goto immediate; | |
2503 | ||
ab3e48dc | 2504 | case 'i': /* 13 bit immediate */ |
252b5132 RH |
2505 | the_insn.reloc = BFD_RELOC_SPARC13; |
2506 | ||
2507 | /* fallthrough */ | |
2508 | ||
2509 | immediate: | |
2510 | if (*s == ' ') | |
2511 | s++; | |
2512 | ||
cf9a1301 RH |
2513 | { |
2514 | char *s1; | |
2515 | char *op_arg = NULL; | |
30eb9c17 | 2516 | static expressionS op_exp; |
cf9a1301 RH |
2517 | bfd_reloc_code_real_type old_reloc = the_insn.reloc; |
2518 | ||
2519 | /* Check for %hi, etc. */ | |
2520 | if (*s == '%') | |
2521 | { | |
2522 | static const struct ops { | |
2523 | /* The name as it appears in assembler. */ | |
2524 | char *name; | |
2525 | /* strlen (name), precomputed for speed */ | |
2526 | int len; | |
2527 | /* The reloc this pseudo-op translates to. */ | |
2528 | int reloc; | |
2529 | /* Non-zero if for v9 only. */ | |
2530 | int v9_p; | |
2531 | /* Non-zero if can be used in pc-relative contexts. */ | |
2532 | int pcrel_p;/*FIXME:wip*/ | |
2533 | } ops[] = { | |
2534 | /* hix/lox must appear before hi/lo so %hix won't be | |
2535 | mistaken for %hi. */ | |
2536 | { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, | |
2537 | { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, | |
2538 | { "hi", 2, BFD_RELOC_HI22, 0, 1 }, | |
2539 | { "lo", 2, BFD_RELOC_LO10, 0, 1 }, | |
14865d76 DM |
2540 | { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 }, |
2541 | { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 }, | |
cf9a1301 RH |
2542 | { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, |
2543 | { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, | |
2544 | { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, | |
2615994e DM |
2545 | { "h34", 3, BFD_RELOC_SPARC_H34, 1, 0 }, |
2546 | { "l34", 3, BFD_RELOC_SPARC_L44, 1, 0 }, | |
cf9a1301 RH |
2547 | { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, |
2548 | { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, | |
2549 | { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, | |
2550 | { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, | |
2551 | { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, | |
b9734f35 JJ |
2552 | { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 }, |
2553 | { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 }, | |
2554 | { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 }, | |
2555 | { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 }, | |
2556 | { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0, | |
2557 | 0 }, | |
2558 | { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0, | |
2559 | 0 }, | |
2560 | { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 }, | |
2561 | { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 }, | |
2562 | { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 }, | |
2563 | { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 }, | |
739f7f82 DM |
2564 | { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22, |
2565 | 0, 0 }, | |
2566 | { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10, | |
2567 | 0, 0 }, | |
c2158c24 | 2568 | { NULL, 0, 0, 0, 0 } |
cf9a1301 RH |
2569 | }; |
2570 | const struct ops *o; | |
e0c6ed95 | 2571 | |
cf9a1301 RH |
2572 | for (o = ops; o->name; o++) |
2573 | if (strncmp (s + 1, o->name, o->len) == 0) | |
2574 | break; | |
2575 | if (o->name == NULL) | |
252b5132 | 2576 | break; |
e0c6ed95 | 2577 | |
cf9a1301 RH |
2578 | if (s[o->len + 1] != '(') |
2579 | { | |
2580 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
a22b281c | 2581 | return special_case; |
cf9a1301 | 2582 | } |
252b5132 | 2583 | |
cf9a1301 RH |
2584 | op_arg = o->name; |
2585 | the_insn.reloc = o->reloc; | |
2586 | s += o->len + 2; | |
2587 | v9_arg_p = o->v9_p; | |
2588 | } | |
2589 | ||
2590 | /* Note that if the get_expression() fails, we will still | |
2591 | have created U entries in the symbol table for the | |
2592 | 'symbols' in the input string. Try not to create U | |
2593 | symbols for registers, etc. */ | |
252b5132 | 2594 | |
252b5132 RH |
2595 | /* This stuff checks to see if the expression ends in |
2596 | +%reg. If it does, it removes the register from | |
2597 | the expression, and re-sets 's' to point to the | |
2598 | right place. */ | |
2599 | ||
cf9a1301 RH |
2600 | if (op_arg) |
2601 | { | |
2602 | int npar = 0; | |
2603 | ||
2604 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2605 | if (*s1 == '(') | |
2606 | npar++; | |
2607 | else if (*s1 == ')') | |
2608 | { | |
2609 | if (!npar) | |
2610 | break; | |
2611 | npar--; | |
2612 | } | |
2613 | ||
2614 | if (*s1 != ')') | |
2615 | { | |
2616 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); | |
a22b281c | 2617 | return special_case; |
cf9a1301 | 2618 | } |
e0c6ed95 | 2619 | |
cf9a1301 RH |
2620 | *s1 = '\0'; |
2621 | (void) get_expression (s); | |
2622 | *s1 = ')'; | |
2623 | s = s1 + 1; | |
2624 | if (*s == ',' || *s == ']' || !*s) | |
2625 | continue; | |
2626 | if (*s != '+' && *s != '-') | |
2627 | { | |
2628 | as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); | |
a22b281c | 2629 | return special_case; |
cf9a1301 RH |
2630 | } |
2631 | *s1 = '0'; | |
2632 | s = s1; | |
2633 | op_exp = the_insn.exp; | |
e0c6ed95 | 2634 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
cf9a1301 | 2635 | } |
252b5132 | 2636 | |
e0c6ed95 AM |
2637 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) |
2638 | ; | |
252b5132 | 2639 | |
3882b010 | 2640 | if (s1 != s && ISDIGIT (s1[-1])) |
252b5132 RH |
2641 | { |
2642 | if (s1[-2] == '%' && s1[-3] == '+') | |
cf9a1301 | 2643 | s1 -= 3; |
f124dd4f | 2644 | else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') |
cf9a1301 | 2645 | s1 -= 4; |
f124dd4f DM |
2646 | else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+') |
2647 | s1 -= 5; | |
cf9a1301 RH |
2648 | else |
2649 | s1 = NULL; | |
2650 | if (s1) | |
252b5132 | 2651 | { |
252b5132 | 2652 | *s1 = '\0'; |
1eb7027c RH |
2653 | if (op_arg && s1 == s + 1) |
2654 | the_insn.exp.X_op = O_absent; | |
2655 | else | |
2656 | (void) get_expression (s); | |
252b5132 | 2657 | *s1 = '+'; |
cf9a1301 RH |
2658 | if (op_arg) |
2659 | *s = ')'; | |
252b5132 | 2660 | s = s1; |
252b5132 | 2661 | } |
cf9a1301 RH |
2662 | } |
2663 | else | |
2664 | s1 = NULL; | |
2665 | ||
2666 | if (!s1) | |
2667 | { | |
2668 | (void) get_expression (s); | |
2669 | if (op_arg) | |
2670 | *s = ')'; | |
2671 | s = expr_end; | |
2672 | } | |
2673 | ||
2674 | if (op_arg) | |
2675 | { | |
2676 | the_insn.exp2 = the_insn.exp; | |
2677 | the_insn.exp = op_exp; | |
2678 | if (the_insn.exp2.X_op == O_absent) | |
2679 | the_insn.exp2.X_op = O_illegal; | |
2680 | else if (the_insn.exp.X_op == O_absent) | |
252b5132 | 2681 | { |
cf9a1301 RH |
2682 | the_insn.exp = the_insn.exp2; |
2683 | the_insn.exp2.X_op = O_illegal; | |
2684 | } | |
2685 | else if (the_insn.exp.X_op == O_constant) | |
2686 | { | |
2687 | valueT val = the_insn.exp.X_add_number; | |
2688 | switch (the_insn.reloc) | |
2689 | { | |
1b50c718 ILT |
2690 | default: |
2691 | break; | |
2692 | ||
cf9a1301 RH |
2693 | case BFD_RELOC_SPARC_HH22: |
2694 | val = BSR (val, 32); | |
e0c6ed95 | 2695 | /* Fall through. */ |
cf9a1301 RH |
2696 | |
2697 | case BFD_RELOC_SPARC_LM22: | |
2698 | case BFD_RELOC_HI22: | |
2699 | val = (val >> 10) & 0x3fffff; | |
2700 | break; | |
2701 | ||
2702 | case BFD_RELOC_SPARC_HM10: | |
2703 | val = BSR (val, 32); | |
e0c6ed95 | 2704 | /* Fall through. */ |
cf9a1301 RH |
2705 | |
2706 | case BFD_RELOC_LO10: | |
2707 | val &= 0x3ff; | |
2708 | break; | |
2709 | ||
2615994e DM |
2710 | case BFD_RELOC_SPARC_H34: |
2711 | val >>= 12; | |
2712 | val &= 0x3fffff; | |
2713 | break; | |
2714 | ||
cf9a1301 RH |
2715 | case BFD_RELOC_SPARC_H44: |
2716 | val >>= 22; | |
2717 | val &= 0x3fffff; | |
2718 | break; | |
2719 | ||
2720 | case BFD_RELOC_SPARC_M44: | |
2721 | val >>= 12; | |
2722 | val &= 0x3ff; | |
2723 | break; | |
2724 | ||
2725 | case BFD_RELOC_SPARC_L44: | |
2726 | val &= 0xfff; | |
2727 | break; | |
2728 | ||
2729 | case BFD_RELOC_SPARC_HIX22: | |
ab3e48dc | 2730 | val = ~val; |
cf9a1301 RH |
2731 | val = (val >> 10) & 0x3fffff; |
2732 | break; | |
2733 | ||
2734 | case BFD_RELOC_SPARC_LOX10: | |
2735 | val = (val & 0x3ff) | 0x1c00; | |
2736 | break; | |
2737 | } | |
2738 | the_insn.exp = the_insn.exp2; | |
2739 | the_insn.exp.X_add_number += val; | |
2740 | the_insn.exp2.X_op = O_illegal; | |
2741 | the_insn.reloc = old_reloc; | |
2742 | } | |
2743 | else if (the_insn.exp2.X_op != O_constant) | |
2744 | { | |
2745 | as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); | |
a22b281c | 2746 | return special_case; |
cf9a1301 RH |
2747 | } |
2748 | else | |
2749 | { | |
dabe3bbc | 2750 | if (old_reloc != BFD_RELOC_SPARC13 |
cf9a1301 RH |
2751 | || the_insn.reloc != BFD_RELOC_LO10 |
2752 | || sparc_arch_size != 64 | |
2753 | || sparc_pic_code) | |
2754 | { | |
2755 | as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); | |
a22b281c | 2756 | return special_case; |
cf9a1301 RH |
2757 | } |
2758 | the_insn.reloc = BFD_RELOC_SPARC_OLO10; | |
252b5132 RH |
2759 | } |
2760 | } | |
2761 | } | |
252b5132 RH |
2762 | /* Check for constants that don't require emitting a reloc. */ |
2763 | if (the_insn.exp.X_op == O_constant | |
2764 | && the_insn.exp.X_add_symbol == 0 | |
2765 | && the_insn.exp.X_op_symbol == 0) | |
2766 | { | |
2767 | /* For pc-relative call instructions, we reject | |
2768 | constants to get better code. */ | |
2769 | if (the_insn.pcrel | |
2770 | && the_insn.reloc == BFD_RELOC_32_PCREL_S2 | |
2771 | && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) | |
2772 | { | |
2773 | error_message = _(": PC-relative operand can't be a constant"); | |
2774 | goto error; | |
2775 | } | |
2776 | ||
b9734f35 JJ |
2777 | if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 |
2778 | && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) | |
2779 | { | |
2780 | error_message = _(": TLS operand can't be a constant"); | |
2781 | goto error; | |
2782 | } | |
2783 | ||
55cf6793 | 2784 | /* Constants that won't fit are checked in md_apply_fix |
252b5132 RH |
2785 | and bfd_install_relocation. |
2786 | ??? It would be preferable to install the constants | |
2787 | into the insn here and save having to create a fixS | |
2788 | for each one. There already exists code to handle | |
55cf6793 | 2789 | all the various cases (e.g. in md_apply_fix and |
252b5132 RH |
2790 | bfd_install_relocation) so duplicating all that code |
2791 | here isn't right. */ | |
698544e1 DM |
2792 | |
2793 | /* This is a special case to handle cbcond instructions | |
2794 | properly, which can need two relocations. The first | |
2795 | one is for the 5-bit immediate field and the latter | |
2796 | is going to be for the WDISP10 branch part. We | |
2797 | handle the R_SPARC_5 immediate directly here so that | |
2798 | we don't need to add support for multiple relocations | |
2799 | in one instruction just yet. */ | |
2800 | if (the_insn.reloc == BFD_RELOC_SPARC_5) | |
2801 | { | |
2802 | valueT val = the_insn.exp.X_add_number; | |
2803 | ||
2804 | if (! in_bitfield_range (val, 0x1f)) | |
2805 | { | |
2806 | error_message = _(": Immediate value in cbcond is out of range."); | |
2807 | goto error; | |
2808 | } | |
2809 | opcode |= val & 0x1f; | |
2810 | the_insn.reloc = BFD_RELOC_NONE; | |
2811 | } | |
252b5132 RH |
2812 | } |
2813 | ||
2814 | continue; | |
2815 | ||
2816 | case 'a': | |
2817 | if (*s++ == 'a') | |
2818 | { | |
2819 | opcode |= ANNUL; | |
2820 | continue; | |
2821 | } | |
2822 | break; | |
2823 | ||
2824 | case 'A': | |
2825 | { | |
2826 | int asi = 0; | |
2827 | ||
2828 | /* Parse an asi. */ | |
2829 | if (*s == '#') | |
2830 | { | |
2831 | if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) | |
2832 | { | |
2833 | error_message = _(": invalid ASI name"); | |
2834 | goto error; | |
2835 | } | |
2836 | } | |
2837 | else | |
2838 | { | |
2839 | if (! parse_const_expr_arg (&s, &asi)) | |
2840 | { | |
2841 | error_message = _(": invalid ASI expression"); | |
2842 | goto error; | |
2843 | } | |
2844 | if (asi < 0 || asi > 255) | |
2845 | { | |
2846 | error_message = _(": invalid ASI number"); | |
2847 | goto error; | |
2848 | } | |
2849 | } | |
2850 | opcode |= ASI (asi); | |
2851 | continue; | |
e0c6ed95 | 2852 | } /* Alternate space. */ |
252b5132 RH |
2853 | |
2854 | case 'p': | |
2855 | if (strncmp (s, "%psr", 4) == 0) | |
2856 | { | |
2857 | s += 4; | |
2858 | continue; | |
2859 | } | |
2860 | break; | |
2861 | ||
e0c6ed95 | 2862 | case 'q': /* Floating point queue. */ |
252b5132 RH |
2863 | if (strncmp (s, "%fq", 3) == 0) |
2864 | { | |
2865 | s += 3; | |
2866 | continue; | |
2867 | } | |
2868 | break; | |
2869 | ||
e0c6ed95 | 2870 | case 'Q': /* Coprocessor queue. */ |
252b5132 RH |
2871 | if (strncmp (s, "%cq", 3) == 0) |
2872 | { | |
2873 | s += 3; | |
2874 | continue; | |
2875 | } | |
2876 | break; | |
2877 | ||
2878 | case 'S': | |
2879 | if (strcmp (str, "set") == 0 | |
2880 | || strcmp (str, "setuw") == 0) | |
2881 | { | |
2882 | special_case = SPECIAL_CASE_SET; | |
2883 | continue; | |
2884 | } | |
2885 | else if (strcmp (str, "setsw") == 0) | |
2886 | { | |
2887 | special_case = SPECIAL_CASE_SETSW; | |
2888 | continue; | |
2889 | } | |
2890 | else if (strcmp (str, "setx") == 0) | |
2891 | { | |
2892 | special_case = SPECIAL_CASE_SETX; | |
2893 | continue; | |
2894 | } | |
2895 | else if (strncmp (str, "fdiv", 4) == 0) | |
2896 | { | |
2897 | special_case = SPECIAL_CASE_FDIV; | |
2898 | continue; | |
2899 | } | |
2900 | break; | |
2901 | ||
2902 | case 'o': | |
2903 | if (strncmp (s, "%asi", 4) != 0) | |
2904 | break; | |
2905 | s += 4; | |
2906 | continue; | |
2907 | ||
2908 | case 's': | |
2909 | if (strncmp (s, "%fprs", 5) != 0) | |
2910 | break; | |
2911 | s += 5; | |
2912 | continue; | |
2913 | ||
3d68f91c JM |
2914 | case '{': |
2915 | if (strncmp (s, "%mcdper",7) != 0) | |
2916 | break; | |
2917 | s += 7; | |
2918 | continue; | |
2919 | ||
252b5132 RH |
2920 | case 'E': |
2921 | if (strncmp (s, "%ccr", 4) != 0) | |
2922 | break; | |
2923 | s += 4; | |
2924 | continue; | |
2925 | ||
2926 | case 't': | |
2927 | if (strncmp (s, "%tbr", 4) != 0) | |
2928 | break; | |
2929 | s += 4; | |
2930 | continue; | |
2931 | ||
2932 | case 'w': | |
2933 | if (strncmp (s, "%wim", 4) != 0) | |
2934 | break; | |
2935 | s += 4; | |
2936 | continue; | |
2937 | ||
2938 | case 'x': | |
2939 | { | |
2940 | char *push = input_line_pointer; | |
2941 | expressionS e; | |
2942 | ||
2943 | input_line_pointer = s; | |
2944 | expression (&e); | |
2945 | if (e.X_op == O_constant) | |
2946 | { | |
2947 | int n = e.X_add_number; | |
2948 | if (n != e.X_add_number || (n & ~0x1ff) != 0) | |
2949 | as_bad (_("OPF immediate operand out of range (0-0x1ff)")); | |
2950 | else | |
2951 | opcode |= e.X_add_number << 5; | |
2952 | } | |
2953 | else | |
2954 | as_bad (_("non-immediate OPF operand, ignored")); | |
2955 | s = input_line_pointer; | |
2956 | input_line_pointer = push; | |
2957 | continue; | |
2958 | } | |
2959 | ||
2960 | case 'y': | |
2961 | if (strncmp (s, "%y", 2) != 0) | |
2962 | break; | |
2963 | s += 2; | |
2964 | continue; | |
2965 | ||
2966 | case 'u': | |
2967 | case 'U': | |
2968 | { | |
2969 | /* Parse a sparclet cpreg. */ | |
2970 | int cpreg; | |
2971 | if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) | |
2972 | { | |
2973 | error_message = _(": invalid cpreg name"); | |
2974 | goto error; | |
2975 | } | |
2976 | opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); | |
2977 | continue; | |
2978 | } | |
2979 | ||
2980 | default: | |
2981 | as_fatal (_("failed sanity check.")); | |
e0c6ed95 | 2982 | } /* switch on arg code. */ |
252b5132 RH |
2983 | |
2984 | /* Break out of for() loop. */ | |
2985 | break; | |
e0c6ed95 | 2986 | } /* For each arg that we expect. */ |
252b5132 RH |
2987 | |
2988 | error: | |
2989 | if (match == 0) | |
2990 | { | |
e0c6ed95 | 2991 | /* Args don't match. */ |
252b5132 RH |
2992 | if (&insn[1] - sparc_opcodes < sparc_num_opcodes |
2993 | && (insn->name == insn[1].name | |
2994 | || !strcmp (insn->name, insn[1].name))) | |
2995 | { | |
2996 | ++insn; | |
2997 | s = argsStart; | |
2998 | continue; | |
2999 | } | |
3000 | else | |
3001 | { | |
3002 | as_bad (_("Illegal operands%s"), error_message); | |
a22b281c | 3003 | return special_case; |
252b5132 RH |
3004 | } |
3005 | } | |
3006 | else | |
3007 | { | |
e0c6ed95 | 3008 | /* We have a match. Now see if the architecture is OK. */ |
252b5132 | 3009 | int needed_arch_mask = insn->architecture; |
3d68f91c JM |
3010 | bfd_uint64_t hwcaps |
3011 | = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps; | |
252b5132 | 3012 | |
4bafe00e | 3013 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) |
9e8c70f9 DM |
3014 | if (hwcaps) |
3015 | hwcap_seen |= hwcaps; | |
3016 | #endif | |
252b5132 RH |
3017 | if (v9_arg_p) |
3018 | { | |
19f7b010 JJ |
3019 | needed_arch_mask &= |
3020 | ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); | |
3021 | if (! needed_arch_mask) | |
3022 | needed_arch_mask = | |
3023 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); | |
252b5132 RH |
3024 | } |
3025 | ||
e0c6ed95 AM |
3026 | if (needed_arch_mask |
3027 | & SPARC_OPCODE_SUPPORTED (current_architecture)) | |
3028 | /* OK. */ | |
3029 | ; | |
252b5132 | 3030 | /* Can we bump up the architecture? */ |
e0c6ed95 AM |
3031 | else if (needed_arch_mask |
3032 | & SPARC_OPCODE_SUPPORTED (max_architecture)) | |
252b5132 RH |
3033 | { |
3034 | enum sparc_opcode_arch_val needed_architecture = | |
3035 | sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) | |
3036 | & needed_arch_mask); | |
3037 | ||
9c2799c2 | 3038 | gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); |
252b5132 RH |
3039 | if (warn_on_bump |
3040 | && needed_architecture > warn_after_architecture) | |
3041 | { | |
3042 | as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), | |
3043 | sparc_opcode_archs[current_architecture].name, | |
3044 | sparc_opcode_archs[needed_architecture].name, | |
3045 | str); | |
3046 | warn_after_architecture = needed_architecture; | |
3047 | } | |
3048 | current_architecture = needed_architecture; | |
75ac3a7f | 3049 | hwcap_allowed |= hwcaps; |
252b5132 RH |
3050 | } |
3051 | /* Conflict. */ | |
3052 | /* ??? This seems to be a bit fragile. What if the next entry in | |
3053 | the opcode table is the one we want and it is supported? | |
3054 | It is possible to arrange the table today so that this can't | |
3055 | happen but what about tomorrow? */ | |
3056 | else | |
3057 | { | |
e0c6ed95 | 3058 | int arch, printed_one_p = 0; |
252b5132 RH |
3059 | char *p; |
3060 | char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; | |
3061 | ||
3062 | /* Create a list of the architectures that support the insn. */ | |
e0c6ed95 | 3063 | needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); |
252b5132 RH |
3064 | p = required_archs; |
3065 | arch = sparc_ffs (needed_arch_mask); | |
3066 | while ((1 << arch) <= needed_arch_mask) | |
3067 | { | |
3068 | if ((1 << arch) & needed_arch_mask) | |
3069 | { | |
3070 | if (printed_one_p) | |
3071 | *p++ = '|'; | |
3072 | strcpy (p, sparc_opcode_archs[arch].name); | |
3073 | p += strlen (p); | |
3074 | printed_one_p = 1; | |
3075 | } | |
3076 | ++arch; | |
3077 | } | |
3078 | ||
3079 | as_bad (_("Architecture mismatch on \"%s\"."), str); | |
3080 | as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), | |
3081 | required_archs, | |
3082 | sparc_opcode_archs[max_architecture].name); | |
a22b281c | 3083 | return special_case; |
252b5132 | 3084 | } |
4bafe00e | 3085 | |
9aff4b7a | 3086 | /* Make sure the hwcaps used by the instruction are |
4bafe00e DM |
3087 | currently enabled. */ |
3088 | if (hwcaps & ~hwcap_allowed) | |
3089 | { | |
3090 | const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed); | |
3091 | ||
3092 | as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."), | |
3093 | hwcap_name, str); | |
3094 | return special_case; | |
3095 | } | |
e0c6ed95 | 3096 | } /* If no match. */ |
252b5132 RH |
3097 | |
3098 | break; | |
e0c6ed95 | 3099 | } /* Forever looking for a match. */ |
252b5132 RH |
3100 | |
3101 | the_insn.opcode = opcode; | |
a22b281c | 3102 | return special_case; |
252b5132 RH |
3103 | } |
3104 | ||
3105 | /* Parse an argument that can be expressed as a keyword. | |
3106 | (eg: #StoreStore or %ccfr). | |
3107 | The result is a boolean indicating success. | |
3108 | If successful, INPUT_POINTER is updated. */ | |
3109 | ||
3110 | static int | |
5a49b8ac AM |
3111 | parse_keyword_arg (int (*lookup_fn) (const char *), |
3112 | char **input_pointerP, | |
3113 | int *valueP) | |
252b5132 RH |
3114 | { |
3115 | int value; | |
3116 | char c, *p, *q; | |
3117 | ||
3118 | p = *input_pointerP; | |
3119 | for (q = p + (*p == '#' || *p == '%'); | |
3882b010 | 3120 | ISALNUM (*q) || *q == '_'; |
252b5132 RH |
3121 | ++q) |
3122 | continue; | |
3123 | c = *q; | |
3124 | *q = 0; | |
3125 | value = (*lookup_fn) (p); | |
3126 | *q = c; | |
3127 | if (value == -1) | |
3128 | return 0; | |
3129 | *valueP = value; | |
3130 | *input_pointerP = q; | |
3131 | return 1; | |
3132 | } | |
3133 | ||
3134 | /* Parse an argument that is a constant expression. | |
3135 | The result is a boolean indicating success. */ | |
3136 | ||
3137 | static int | |
5a49b8ac | 3138 | parse_const_expr_arg (char **input_pointerP, int *valueP) |
252b5132 RH |
3139 | { |
3140 | char *save = input_line_pointer; | |
3141 | expressionS exp; | |
3142 | ||
3143 | input_line_pointer = *input_pointerP; | |
3144 | /* The next expression may be something other than a constant | |
3145 | (say if we're not processing the right variant of the insn). | |
3146 | Don't call expression unless we're sure it will succeed as it will | |
3147 | signal an error (which we want to defer until later). */ | |
3148 | /* FIXME: It might be better to define md_operand and have it recognize | |
3149 | things like %asi, etc. but continuing that route through to the end | |
3150 | is a lot of work. */ | |
3151 | if (*input_line_pointer == '%') | |
3152 | { | |
3153 | input_line_pointer = save; | |
3154 | return 0; | |
3155 | } | |
3156 | expression (&exp); | |
3157 | *input_pointerP = input_line_pointer; | |
3158 | input_line_pointer = save; | |
3159 | if (exp.X_op != O_constant) | |
3160 | return 0; | |
3161 | *valueP = exp.X_add_number; | |
3162 | return 1; | |
3163 | } | |
3164 | ||
3165 | /* Subroutine of sparc_ip to parse an expression. */ | |
3166 | ||
3167 | static int | |
5a49b8ac | 3168 | get_expression (char *str) |
252b5132 RH |
3169 | { |
3170 | char *save_in; | |
3171 | segT seg; | |
3172 | ||
3173 | save_in = input_line_pointer; | |
3174 | input_line_pointer = str; | |
3175 | seg = expression (&the_insn.exp); | |
3176 | if (seg != absolute_section | |
3177 | && seg != text_section | |
3178 | && seg != data_section | |
3179 | && seg != bss_section | |
3180 | && seg != undefined_section) | |
3181 | { | |
3182 | the_insn.error = _("bad segment"); | |
3183 | expr_end = input_line_pointer; | |
3184 | input_line_pointer = save_in; | |
3185 | return 1; | |
3186 | } | |
3187 | expr_end = input_line_pointer; | |
3188 | input_line_pointer = save_in; | |
3189 | return 0; | |
3190 | } | |
3191 | ||
3192 | /* Subroutine of md_assemble to output one insn. */ | |
3193 | ||
3194 | static void | |
91d6fa6a | 3195 | output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn) |
252b5132 RH |
3196 | { |
3197 | char *toP = frag_more (4); | |
3198 | ||
e0c6ed95 | 3199 | /* Put out the opcode. */ |
252b5132 | 3200 | if (INSN_BIG_ENDIAN) |
91d6fa6a | 3201 | number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 3202 | else |
91d6fa6a | 3203 | number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 3204 | |
e0c6ed95 | 3205 | /* Put out the symbol-dependent stuff. */ |
91d6fa6a | 3206 | if (theinsn->reloc != BFD_RELOC_NONE) |
252b5132 | 3207 | { |
e0c6ed95 AM |
3208 | fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ |
3209 | (toP - frag_now->fr_literal), /* Where. */ | |
3210 | 4, /* Size. */ | |
91d6fa6a NC |
3211 | &theinsn->exp, |
3212 | theinsn->pcrel, | |
3213 | theinsn->reloc); | |
252b5132 | 3214 | /* Turn off overflow checking in fixup_segment. We'll do our |
55cf6793 | 3215 | own overflow checking in md_apply_fix. This is necessary because |
252b5132 RH |
3216 | the insn size is 4 and fixup_segment will signal an overflow for |
3217 | large 8 byte quantities. */ | |
3218 | fixP->fx_no_overflow = 1; | |
91d6fa6a NC |
3219 | if (theinsn->reloc == BFD_RELOC_SPARC_OLO10) |
3220 | fixP->tc_fix_data = theinsn->exp2.X_add_number; | |
252b5132 RH |
3221 | } |
3222 | ||
3223 | last_insn = insn; | |
91d6fa6a | 3224 | last_opcode = theinsn->opcode; |
732d96b6 JJ |
3225 | |
3226 | #ifdef OBJ_ELF | |
3227 | dwarf2_emit_insn (4); | |
3228 | #endif | |
252b5132 RH |
3229 | } |
3230 | \f | |
252b5132 | 3231 | char * |
499ac353 | 3232 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 3233 | { |
499ac353 | 3234 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
3235 | } |
3236 | ||
3237 | /* Write a value out to the object file, using the appropriate | |
3238 | endianness. */ | |
3239 | ||
3240 | void | |
5a49b8ac | 3241 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
3242 | { |
3243 | if (target_big_endian) | |
3244 | number_to_chars_bigendian (buf, val, n); | |
3245 | else if (target_little_endian_data | |
3246 | && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) | |
e0c6ed95 AM |
3247 | /* Output debug words, which are not in allocated sections, as big |
3248 | endian. */ | |
252b5132 RH |
3249 | number_to_chars_bigendian (buf, val, n); |
3250 | else if (target_little_endian_data || ! target_big_endian) | |
3251 | number_to_chars_littleendian (buf, val, n); | |
3252 | } | |
3253 | \f | |
3254 | /* Apply a fixS to the frags, now that we know the value it ought to | |
81d4177b | 3255 | hold. */ |
252b5132 | 3256 | |
94f592af | 3257 | void |
5a49b8ac | 3258 | md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) |
252b5132 RH |
3259 | { |
3260 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
94f592af | 3261 | offsetT val = * (offsetT *) valP; |
252b5132 RH |
3262 | long insn; |
3263 | ||
9c2799c2 | 3264 | gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); |
252b5132 | 3265 | |
e0c6ed95 | 3266 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
252b5132 RH |
3267 | |
3268 | #ifdef OBJ_ELF | |
a161fe53 | 3269 | /* SPARC ELF relocations don't use an addend in the data field. */ |
252b5132 | 3270 | if (fixP->fx_addsy != NULL) |
7c1d0959 L |
3271 | { |
3272 | switch (fixP->fx_r_type) | |
3273 | { | |
3274 | case BFD_RELOC_SPARC_TLS_GD_HI22: | |
3275 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3276 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3277 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3278 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3279 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3280 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3281 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3282 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3283 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3284 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3285 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3286 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3287 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3288 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3289 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3290 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3291 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3292 | case BFD_RELOC_SPARC_TLS_DTPMOD32: | |
3293 | case BFD_RELOC_SPARC_TLS_DTPMOD64: | |
3294 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3295 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
3296 | case BFD_RELOC_SPARC_TLS_TPOFF32: | |
3297 | case BFD_RELOC_SPARC_TLS_TPOFF64: | |
3298 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
3299 | ||
3300 | default: | |
3301 | break; | |
3302 | } | |
3303 | ||
3304 | return; | |
3305 | } | |
252b5132 RH |
3306 | #endif |
3307 | ||
3308 | /* This is a hack. There should be a better way to | |
3309 | handle this. Probably in terms of howto fields, once | |
3310 | we can look at these fixups in terms of howtos. */ | |
3311 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) | |
3312 | val += fixP->fx_where + fixP->fx_frag->fr_address; | |
3313 | ||
3314 | #ifdef OBJ_AOUT | |
3315 | /* FIXME: More ridiculous gas reloc hacking. If we are going to | |
3316 | generate a reloc, then we just want to let the reloc addend set | |
3317 | the value. We do not want to also stuff the addend into the | |
3318 | object file. Including the addend in the object file works when | |
3319 | doing a static link, because the linker will ignore the object | |
3320 | file contents. However, the dynamic linker does not ignore the | |
3321 | object file contents. */ | |
3322 | if (fixP->fx_addsy != NULL | |
3323 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) | |
3324 | val = 0; | |
3325 | ||
3326 | /* When generating PIC code, we do not want an addend for a reloc | |
3327 | against a local symbol. We adjust fx_addnumber to cancel out the | |
3328 | value already included in val, and to also cancel out the | |
3329 | adjustment which bfd_install_relocation will create. */ | |
3330 | if (sparc_pic_code | |
3331 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 | |
3332 | && fixP->fx_addsy != NULL | |
3333 | && ! S_IS_COMMON (fixP->fx_addsy) | |
49309057 | 3334 | && symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3335 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); |
3336 | ||
3337 | /* When generating PIC code, we need to fiddle to get | |
3338 | bfd_install_relocation to do the right thing for a PC relative | |
3339 | reloc against a local symbol which we are going to keep. */ | |
3340 | if (sparc_pic_code | |
3341 | && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3342 | && fixP->fx_addsy != NULL | |
3343 | && (S_IS_EXTERNAL (fixP->fx_addsy) | |
3344 | || S_IS_WEAK (fixP->fx_addsy)) | |
3345 | && S_IS_DEFINED (fixP->fx_addsy) | |
3346 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
3347 | { | |
3348 | val = 0; | |
3349 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
3350 | } | |
3351 | #endif | |
3352 | ||
3353 | /* If this is a data relocation, just output VAL. */ | |
3354 | ||
a7bbf4e9 DM |
3355 | if (fixP->fx_r_type == BFD_RELOC_8) |
3356 | { | |
3357 | md_number_to_chars (buf, val, 1); | |
3358 | } | |
3359 | else if (fixP->fx_r_type == BFD_RELOC_16 | |
3360 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) | |
252b5132 RH |
3361 | { |
3362 | md_number_to_chars (buf, val, 2); | |
3363 | } | |
3364 | else if (fixP->fx_r_type == BFD_RELOC_32 | |
0f2712ed | 3365 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 |
252b5132 RH |
3366 | || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) |
3367 | { | |
3368 | md_number_to_chars (buf, val, 4); | |
3369 | } | |
0f2712ed NC |
3370 | else if (fixP->fx_r_type == BFD_RELOC_64 |
3371 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) | |
252b5132 RH |
3372 | { |
3373 | md_number_to_chars (buf, val, 8); | |
3374 | } | |
e0c6ed95 | 3375 | else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
252b5132 RH |
3376 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
3377 | { | |
3378 | fixP->fx_done = 0; | |
94f592af | 3379 | return; |
252b5132 RH |
3380 | } |
3381 | else | |
3382 | { | |
3383 | /* It's a relocation against an instruction. */ | |
3384 | ||
3385 | if (INSN_BIG_ENDIAN) | |
3386 | insn = bfd_getb32 ((unsigned char *) buf); | |
3387 | else | |
3388 | insn = bfd_getl32 ((unsigned char *) buf); | |
e0c6ed95 | 3389 | |
252b5132 RH |
3390 | switch (fixP->fx_r_type) |
3391 | { | |
3392 | case BFD_RELOC_32_PCREL_S2: | |
3393 | val = val >> 2; | |
3394 | /* FIXME: This increment-by-one deserves a comment of why it's | |
3395 | being done! */ | |
3396 | if (! sparc_pic_code | |
3397 | || fixP->fx_addsy == NULL | |
49309057 | 3398 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 | 3399 | ++val; |
6faf3d66 | 3400 | |
252b5132 | 3401 | insn |= val & 0x3fffffff; |
6faf3d66 | 3402 | |
e0c6ed95 | 3403 | /* See if we have a delay slot. */ |
6faf3d66 JJ |
3404 | if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) |
3405 | { | |
3406 | #define G0 0 | |
3407 | #define O7 15 | |
3408 | #define XCC (2 << 20) | |
3409 | #define COND(x) (((x)&0xf)<<25) | |
3410 | #define CONDA COND(0x8) | |
3411 | #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) | |
3412 | #define INSN_BA (F2(0,2) | CONDA) | |
3413 | #define INSN_OR F3(2, 0x2, 0) | |
3414 | #define INSN_NOP F2(0,4) | |
3415 | ||
3416 | long delay; | |
3417 | ||
3418 | /* If the instruction is a call with either: | |
3419 | restore | |
3420 | arithmetic instruction with rd == %o7 | |
3421 | where rs1 != %o7 and rs2 if it is register != %o7 | |
3422 | then we can optimize if the call destination is near | |
3423 | by changing the call into a branch always. */ | |
3424 | if (INSN_BIG_ENDIAN) | |
3425 | delay = bfd_getb32 ((unsigned char *) buf + 4); | |
3426 | else | |
3427 | delay = bfd_getl32 ((unsigned char *) buf + 4); | |
e0c6ed95 | 3428 | if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) |
6faf3d66 | 3429 | break; |
e0c6ed95 AM |
3430 | if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ |
3431 | && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ | |
3432 | || ((delay & RD (~0)) != RD (O7)))) | |
6faf3d66 | 3433 | break; |
e0c6ed95 AM |
3434 | if ((delay & RS1 (~0)) == RS1 (O7) |
3435 | || ((delay & F3I (~0)) == 0 | |
3436 | && (delay & RS2 (~0)) == RS2 (O7))) | |
6faf3d66 JJ |
3437 | break; |
3438 | /* Ensure the branch will fit into simm22. */ | |
3439 | if ((val & 0x3fe00000) | |
3440 | && (val & 0x3fe00000) != 0x3fe00000) | |
3441 | break; | |
3442 | /* Check if the arch is v9 and branch will fit | |
3443 | into simm19. */ | |
3444 | if (((val & 0x3c0000) == 0 | |
3445 | || (val & 0x3c0000) == 0x3c0000) | |
3446 | && (sparc_arch_size == 64 | |
3447 | || current_architecture >= SPARC_OPCODE_ARCH_V9)) | |
e0c6ed95 | 3448 | /* ba,pt %xcc */ |
6faf3d66 JJ |
3449 | insn = INSN_BPA | (val & 0x7ffff); |
3450 | else | |
e0c6ed95 | 3451 | /* ba */ |
6faf3d66 JJ |
3452 | insn = INSN_BA | (val & 0x3fffff); |
3453 | if (fixP->fx_where >= 4 | |
e0c6ed95 AM |
3454 | && ((delay & (0xffffffff ^ RS1 (~0))) |
3455 | == (INSN_OR | RD (O7) | RS2 (G0)))) | |
6faf3d66 JJ |
3456 | { |
3457 | long setter; | |
3458 | int reg; | |
3459 | ||
3460 | if (INSN_BIG_ENDIAN) | |
3461 | setter = bfd_getb32 ((unsigned char *) buf - 4); | |
3462 | else | |
3463 | setter = bfd_getl32 ((unsigned char *) buf - 4); | |
e0c6ed95 | 3464 | if ((setter & (0xffffffff ^ RD (~0))) |
ab3e48dc | 3465 | != (INSN_OR | RS1 (O7) | RS2 (G0))) |
6faf3d66 JJ |
3466 | break; |
3467 | /* The sequence was | |
3468 | or %o7, %g0, %rN | |
3469 | call foo | |
3470 | or %rN, %g0, %o7 | |
3471 | ||
3472 | If call foo was replaced with ba, replace | |
3473 | or %rN, %g0, %o7 with nop. */ | |
e0c6ed95 AM |
3474 | reg = (delay & RS1 (~0)) >> 14; |
3475 | if (reg != ((setter & RD (~0)) >> 25) | |
6faf3d66 JJ |
3476 | || reg == G0 || reg == O7) |
3477 | break; | |
3478 | ||
3479 | if (INSN_BIG_ENDIAN) | |
3480 | bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); | |
3481 | else | |
3482 | bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); | |
3483 | } | |
3484 | } | |
252b5132 RH |
3485 | break; |
3486 | ||
3487 | case BFD_RELOC_SPARC_11: | |
3488 | if (! in_signed_range (val, 0x7ff)) | |
3489 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3490 | _("relocation overflow")); | |
3491 | insn |= val & 0x7ff; | |
3492 | break; | |
3493 | ||
3494 | case BFD_RELOC_SPARC_10: | |
3495 | if (! in_signed_range (val, 0x3ff)) | |
3496 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3497 | _("relocation overflow")); | |
3498 | insn |= val & 0x3ff; | |
3499 | break; | |
3500 | ||
3501 | case BFD_RELOC_SPARC_7: | |
3502 | if (! in_bitfield_range (val, 0x7f)) | |
3503 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3504 | _("relocation overflow")); | |
3505 | insn |= val & 0x7f; | |
3506 | break; | |
3507 | ||
3508 | case BFD_RELOC_SPARC_6: | |
3509 | if (! in_bitfield_range (val, 0x3f)) | |
3510 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3511 | _("relocation overflow")); | |
3512 | insn |= val & 0x3f; | |
3513 | break; | |
3514 | ||
3515 | case BFD_RELOC_SPARC_5: | |
3516 | if (! in_bitfield_range (val, 0x1f)) | |
3517 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3518 | _("relocation overflow")); | |
3519 | insn |= val & 0x1f; | |
3520 | break; | |
3521 | ||
2615994e DM |
3522 | case BFD_RELOC_SPARC_WDISP10: |
3523 | if ((val & 3) | |
3524 | || val >= 0x007fc | |
3525 | || val <= -(offsetT) 0x808) | |
3526 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3527 | _("relocation overflow")); | |
3528 | /* FIXME: The +1 deserves a comment. */ | |
3529 | val = (val >> 2) + 1; | |
3530 | insn |= ((val & 0x300) << 11) | |
3531 | | ((val & 0xff) << 5); | |
3532 | break; | |
3533 | ||
252b5132 | 3534 | case BFD_RELOC_SPARC_WDISP16: |
c699f087 JJ |
3535 | if ((val & 3) |
3536 | || val >= 0x1fffc | |
3537 | || val <= -(offsetT) 0x20008) | |
252b5132 RH |
3538 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3539 | _("relocation overflow")); | |
3540 | /* FIXME: The +1 deserves a comment. */ | |
3541 | val = (val >> 2) + 1; | |
3542 | insn |= ((val & 0xc000) << 6) | (val & 0x3fff); | |
3543 | break; | |
3544 | ||
3545 | case BFD_RELOC_SPARC_WDISP19: | |
c699f087 JJ |
3546 | if ((val & 3) |
3547 | || val >= 0xffffc | |
3548 | || val <= -(offsetT) 0x100008) | |
252b5132 RH |
3549 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3550 | _("relocation overflow")); | |
3551 | /* FIXME: The +1 deserves a comment. */ | |
3552 | val = (val >> 2) + 1; | |
3553 | insn |= val & 0x7ffff; | |
3554 | break; | |
3555 | ||
3556 | case BFD_RELOC_SPARC_HH22: | |
3557 | val = BSR (val, 32); | |
e0c6ed95 | 3558 | /* Fall through. */ |
252b5132 RH |
3559 | |
3560 | case BFD_RELOC_SPARC_LM22: | |
3561 | case BFD_RELOC_HI22: | |
3562 | if (!fixP->fx_addsy) | |
94f592af | 3563 | insn |= (val >> 10) & 0x3fffff; |
252b5132 | 3564 | else |
94f592af NC |
3565 | /* FIXME: Need comment explaining why we do this. */ |
3566 | insn &= ~0xffff; | |
252b5132 RH |
3567 | break; |
3568 | ||
3569 | case BFD_RELOC_SPARC22: | |
3570 | if (val & ~0x003fffff) | |
3571 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3572 | _("relocation overflow")); | |
3573 | insn |= (val & 0x3fffff); | |
3574 | break; | |
3575 | ||
3576 | case BFD_RELOC_SPARC_HM10: | |
3577 | val = BSR (val, 32); | |
e0c6ed95 | 3578 | /* Fall through. */ |
252b5132 RH |
3579 | |
3580 | case BFD_RELOC_LO10: | |
3581 | if (!fixP->fx_addsy) | |
94f592af | 3582 | insn |= val & 0x3ff; |
252b5132 | 3583 | else |
94f592af NC |
3584 | /* FIXME: Need comment explaining why we do this. */ |
3585 | insn &= ~0xff; | |
252b5132 RH |
3586 | break; |
3587 | ||
dabe3bbc RH |
3588 | case BFD_RELOC_SPARC_OLO10: |
3589 | val &= 0x3ff; | |
3590 | val += fixP->tc_fix_data; | |
e0c6ed95 | 3591 | /* Fall through. */ |
dabe3bbc | 3592 | |
252b5132 RH |
3593 | case BFD_RELOC_SPARC13: |
3594 | if (! in_signed_range (val, 0x1fff)) | |
3595 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3596 | _("relocation overflow")); | |
3597 | insn |= val & 0x1fff; | |
3598 | break; | |
3599 | ||
3600 | case BFD_RELOC_SPARC_WDISP22: | |
3601 | val = (val >> 2) + 1; | |
e0c6ed95 | 3602 | /* Fall through. */ |
252b5132 RH |
3603 | case BFD_RELOC_SPARC_BASE22: |
3604 | insn |= val & 0x3fffff; | |
3605 | break; | |
3606 | ||
2615994e DM |
3607 | case BFD_RELOC_SPARC_H34: |
3608 | if (!fixP->fx_addsy) | |
3609 | { | |
3610 | bfd_vma tval = val; | |
3611 | tval >>= 12; | |
3612 | insn |= tval & 0x3fffff; | |
3613 | } | |
3614 | break; | |
3615 | ||
252b5132 RH |
3616 | case BFD_RELOC_SPARC_H44: |
3617 | if (!fixP->fx_addsy) | |
3618 | { | |
3619 | bfd_vma tval = val; | |
3620 | tval >>= 22; | |
3621 | insn |= tval & 0x3fffff; | |
3622 | } | |
3623 | break; | |
3624 | ||
3625 | case BFD_RELOC_SPARC_M44: | |
3626 | if (!fixP->fx_addsy) | |
3627 | insn |= (val >> 12) & 0x3ff; | |
3628 | break; | |
3629 | ||
3630 | case BFD_RELOC_SPARC_L44: | |
3631 | if (!fixP->fx_addsy) | |
3632 | insn |= val & 0xfff; | |
3633 | break; | |
3634 | ||
3635 | case BFD_RELOC_SPARC_HIX22: | |
3636 | if (!fixP->fx_addsy) | |
3637 | { | |
ab3e48dc | 3638 | val ^= ~(offsetT) 0; |
252b5132 RH |
3639 | insn |= (val >> 10) & 0x3fffff; |
3640 | } | |
3641 | break; | |
3642 | ||
3643 | case BFD_RELOC_SPARC_LOX10: | |
3644 | if (!fixP->fx_addsy) | |
3645 | insn |= 0x1c00 | (val & 0x3ff); | |
3646 | break; | |
3647 | ||
3648 | case BFD_RELOC_NONE: | |
3649 | default: | |
3650 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3651 | _("bad or unhandled relocation type: 0x%02x"), | |
3652 | fixP->fx_r_type); | |
3653 | break; | |
3654 | } | |
3655 | ||
3656 | if (INSN_BIG_ENDIAN) | |
3657 | bfd_putb32 (insn, (unsigned char *) buf); | |
3658 | else | |
3659 | bfd_putl32 (insn, (unsigned char *) buf); | |
3660 | } | |
3661 | ||
3662 | /* Are we finished with this relocation now? */ | |
3663 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
3664 | fixP->fx_done = 1; | |
252b5132 RH |
3665 | } |
3666 | ||
3667 | /* Translate internal representation of relocation info to BFD target | |
3668 | format. */ | |
e0c6ed95 | 3669 | |
dabe3bbc | 3670 | arelent ** |
5a49b8ac | 3671 | tc_gen_reloc (asection *section, fixS *fixp) |
252b5132 | 3672 | { |
dabe3bbc | 3673 | static arelent *relocs[3]; |
252b5132 RH |
3674 | arelent *reloc; |
3675 | bfd_reloc_code_real_type code; | |
3676 | ||
dabe3bbc RH |
3677 | relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); |
3678 | relocs[1] = NULL; | |
252b5132 | 3679 | |
49309057 ILT |
3680 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
3681 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
3682 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3683 | ||
3684 | switch (fixp->fx_r_type) | |
3685 | { | |
3686 | case BFD_RELOC_16: | |
3687 | case BFD_RELOC_32: | |
3688 | case BFD_RELOC_HI22: | |
3689 | case BFD_RELOC_LO10: | |
3690 | case BFD_RELOC_32_PCREL_S2: | |
3691 | case BFD_RELOC_SPARC13: | |
63fab58c | 3692 | case BFD_RELOC_SPARC22: |
1a6b486f DM |
3693 | case BFD_RELOC_SPARC_PC22: |
3694 | case BFD_RELOC_SPARC_PC10: | |
252b5132 | 3695 | case BFD_RELOC_SPARC_BASE13: |
2615994e | 3696 | case BFD_RELOC_SPARC_WDISP10: |
252b5132 RH |
3697 | case BFD_RELOC_SPARC_WDISP16: |
3698 | case BFD_RELOC_SPARC_WDISP19: | |
3699 | case BFD_RELOC_SPARC_WDISP22: | |
3700 | case BFD_RELOC_64: | |
3701 | case BFD_RELOC_SPARC_5: | |
3702 | case BFD_RELOC_SPARC_6: | |
3703 | case BFD_RELOC_SPARC_7: | |
3704 | case BFD_RELOC_SPARC_10: | |
3705 | case BFD_RELOC_SPARC_11: | |
3706 | case BFD_RELOC_SPARC_HH22: | |
3707 | case BFD_RELOC_SPARC_HM10: | |
3708 | case BFD_RELOC_SPARC_LM22: | |
3709 | case BFD_RELOC_SPARC_PC_HH22: | |
3710 | case BFD_RELOC_SPARC_PC_HM10: | |
3711 | case BFD_RELOC_SPARC_PC_LM22: | |
2615994e | 3712 | case BFD_RELOC_SPARC_H34: |
252b5132 RH |
3713 | case BFD_RELOC_SPARC_H44: |
3714 | case BFD_RELOC_SPARC_M44: | |
3715 | case BFD_RELOC_SPARC_L44: | |
3716 | case BFD_RELOC_SPARC_HIX22: | |
3717 | case BFD_RELOC_SPARC_LOX10: | |
3718 | case BFD_RELOC_SPARC_REV32: | |
dabe3bbc | 3719 | case BFD_RELOC_SPARC_OLO10: |
0f2712ed NC |
3720 | case BFD_RELOC_SPARC_UA16: |
3721 | case BFD_RELOC_SPARC_UA32: | |
3722 | case BFD_RELOC_SPARC_UA64: | |
bd5e6e7e JJ |
3723 | case BFD_RELOC_8_PCREL: |
3724 | case BFD_RELOC_16_PCREL: | |
3725 | case BFD_RELOC_32_PCREL: | |
3726 | case BFD_RELOC_64_PCREL: | |
3727 | case BFD_RELOC_SPARC_PLT32: | |
3728 | case BFD_RELOC_SPARC_PLT64: | |
252b5132 RH |
3729 | case BFD_RELOC_VTABLE_ENTRY: |
3730 | case BFD_RELOC_VTABLE_INHERIT: | |
b9734f35 JJ |
3731 | case BFD_RELOC_SPARC_TLS_GD_HI22: |
3732 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3733 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3734 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3735 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3736 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3737 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3738 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3739 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3740 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3741 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3742 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3743 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3744 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3745 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3746 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3747 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3748 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3749 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3750 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
739f7f82 DM |
3751 | case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: |
3752 | case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: | |
3753 | case BFD_RELOC_SPARC_GOTDATA_OP: | |
252b5132 RH |
3754 | code = fixp->fx_r_type; |
3755 | break; | |
3756 | default: | |
3757 | abort (); | |
3758 | return NULL; | |
3759 | } | |
3760 | ||
3761 | #if defined (OBJ_ELF) || defined (OBJ_AOUT) | |
3762 | /* If we are generating PIC code, we need to generate a different | |
3763 | set of relocs. */ | |
3764 | ||
3765 | #ifdef OBJ_ELF | |
3766 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" | |
3767 | #else | |
3768 | #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" | |
910600e9 RS |
3769 | #endif |
3770 | #ifdef TE_VXWORKS | |
3771 | #define GOTT_BASE "__GOTT_BASE__" | |
3772 | #define GOTT_INDEX "__GOTT_INDEX__" | |
252b5132 RH |
3773 | #endif |
3774 | ||
153b546a ILT |
3775 | /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ |
3776 | ||
252b5132 RH |
3777 | if (sparc_pic_code) |
3778 | { | |
3779 | switch (code) | |
3780 | { | |
3781 | case BFD_RELOC_32_PCREL_S2: | |
ae6063d4 | 3782 | if (generic_force_reloc (fixp)) |
252b5132 RH |
3783 | code = BFD_RELOC_SPARC_WPLT30; |
3784 | break; | |
3785 | case BFD_RELOC_HI22: | |
910600e9 RS |
3786 | code = BFD_RELOC_SPARC_GOT22; |
3787 | if (fixp->fx_addsy != NULL) | |
3788 | { | |
3789 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3790 | code = BFD_RELOC_SPARC_PC22; | |
3791 | #ifdef TE_VXWORKS | |
3792 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3793 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3794 | code = BFD_RELOC_HI22; /* Unchanged. */ | |
3795 | #endif | |
3796 | } | |
252b5132 RH |
3797 | break; |
3798 | case BFD_RELOC_LO10: | |
910600e9 RS |
3799 | code = BFD_RELOC_SPARC_GOT10; |
3800 | if (fixp->fx_addsy != NULL) | |
3801 | { | |
3802 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3803 | code = BFD_RELOC_SPARC_PC10; | |
3804 | #ifdef TE_VXWORKS | |
3805 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3806 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3807 | code = BFD_RELOC_LO10; /* Unchanged. */ | |
3808 | #endif | |
3809 | } | |
252b5132 RH |
3810 | break; |
3811 | case BFD_RELOC_SPARC13: | |
3812 | code = BFD_RELOC_SPARC_GOT13; | |
3813 | break; | |
3814 | default: | |
3815 | break; | |
3816 | } | |
3817 | } | |
e0c6ed95 | 3818 | #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ |
252b5132 | 3819 | |
062cf837 EB |
3820 | /* Nothing is aligned in DWARF debugging sections. */ |
3821 | if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) | |
3822 | switch (code) | |
3823 | { | |
3824 | case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; | |
3825 | case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; | |
3826 | case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; | |
3827 | default: break; | |
3828 | } | |
3829 | ||
dabe3bbc RH |
3830 | if (code == BFD_RELOC_SPARC_OLO10) |
3831 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); | |
3832 | else | |
3833 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
252b5132 RH |
3834 | if (reloc->howto == 0) |
3835 | { | |
3836 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3837 | _("internal error: can't export reloc type %d (`%s')"), | |
3838 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); | |
dabe3bbc RH |
3839 | xfree (reloc); |
3840 | relocs[0] = NULL; | |
3841 | return relocs; | |
252b5132 RH |
3842 | } |
3843 | ||
3844 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ | |
3845 | #ifdef OBJ_AOUT | |
3846 | ||
3847 | if (reloc->howto->pc_relative == 0 | |
3848 | || code == BFD_RELOC_SPARC_PC10 | |
3849 | || code == BFD_RELOC_SPARC_PC22) | |
3850 | reloc->addend = fixp->fx_addnumber; | |
3851 | else if (sparc_pic_code | |
3852 | && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3853 | && fixp->fx_addsy != NULL | |
3854 | && (S_IS_EXTERNAL (fixp->fx_addsy) | |
3855 | || S_IS_WEAK (fixp->fx_addsy)) | |
3856 | && S_IS_DEFINED (fixp->fx_addsy) | |
3857 | && ! S_IS_COMMON (fixp->fx_addsy)) | |
3858 | reloc->addend = fixp->fx_addnumber; | |
3859 | else | |
3860 | reloc->addend = fixp->fx_offset - reloc->address; | |
3861 | ||
e0c6ed95 | 3862 | #else /* elf or coff */ |
252b5132 | 3863 | |
bd5e6e7e JJ |
3864 | if (code != BFD_RELOC_32_PCREL_S2 |
3865 | && code != BFD_RELOC_SPARC_WDISP22 | |
3866 | && code != BFD_RELOC_SPARC_WDISP16 | |
3867 | && code != BFD_RELOC_SPARC_WDISP19 | |
2615994e | 3868 | && code != BFD_RELOC_SPARC_WDISP10 |
b9734f35 JJ |
3869 | && code != BFD_RELOC_SPARC_WPLT30 |
3870 | && code != BFD_RELOC_SPARC_TLS_GD_CALL | |
3871 | && code != BFD_RELOC_SPARC_TLS_LDM_CALL) | |
252b5132 | 3872 | reloc->addend = fixp->fx_addnumber; |
49309057 | 3873 | else if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
3874 | reloc->addend = (section->vma |
3875 | + fixp->fx_addnumber | |
3876 | + md_pcrel_from (fixp)); | |
3877 | else | |
3878 | reloc->addend = fixp->fx_offset; | |
3879 | #endif | |
3880 | ||
dabe3bbc RH |
3881 | /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 |
3882 | on the same location. */ | |
3883 | if (code == BFD_RELOC_SPARC_OLO10) | |
3884 | { | |
3885 | relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); | |
3886 | relocs[2] = NULL; | |
3887 | ||
3888 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
ab3e48dc KH |
3889 | *reloc->sym_ptr_ptr |
3890 | = symbol_get_bfdsym (section_symbol (absolute_section)); | |
dabe3bbc RH |
3891 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3892 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); | |
3893 | reloc->addend = fixp->tc_fix_data; | |
3894 | } | |
3895 | ||
3896 | return relocs; | |
252b5132 RH |
3897 | } |
3898 | \f | |
e0c6ed95 | 3899 | /* We have no need to default values of symbols. */ |
252b5132 | 3900 | |
252b5132 | 3901 | symbolS * |
5a49b8ac | 3902 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
3903 | { |
3904 | return 0; | |
e0c6ed95 AM |
3905 | } |
3906 | ||
3907 | /* Round up a section size to the appropriate boundary. */ | |
252b5132 | 3908 | |
252b5132 | 3909 | valueT |
5a49b8ac | 3910 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 RH |
3911 | { |
3912 | #ifndef OBJ_ELF | |
3913 | /* This is not right for ELF; a.out wants it, and COFF will force | |
3914 | the alignment anyways. */ | |
3915 | valueT align = ((valueT) 1 | |
3916 | << (valueT) bfd_get_section_alignment (stdoutput, segment)); | |
3917 | valueT newsize; | |
e0c6ed95 AM |
3918 | |
3919 | /* Turn alignment value into a mask. */ | |
252b5132 RH |
3920 | align--; |
3921 | newsize = (size + align) & ~align; | |
3922 | return newsize; | |
3923 | #else | |
3924 | return size; | |
3925 | #endif | |
3926 | } | |
3927 | ||
3928 | /* Exactly what point is a PC-relative offset relative TO? | |
3929 | On the sparc, they're relative to the address of the offset, plus | |
3930 | its size. This gets us to the following instruction. | |
e0c6ed95 AM |
3931 | (??? Is this right? FIXME-SOON) */ |
3932 | long | |
5a49b8ac | 3933 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
3934 | { |
3935 | long ret; | |
3936 | ||
3937 | ret = fixP->fx_where + fixP->fx_frag->fr_address; | |
3938 | if (! sparc_pic_code | |
3939 | || fixP->fx_addsy == NULL | |
49309057 | 3940 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3941 | ret += fixP->fx_size; |
3942 | return ret; | |
3943 | } | |
3944 | \f | |
3945 | /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power | |
3946 | of two. */ | |
3947 | ||
3948 | static int | |
5a49b8ac | 3949 | mylog2 (int value) |
252b5132 RH |
3950 | { |
3951 | int shift; | |
3952 | ||
3953 | if (value <= 0) | |
3954 | return -1; | |
3955 | ||
3956 | for (shift = 0; (value & 1) == 0; value >>= 1) | |
3957 | ++shift; | |
3958 | ||
3959 | return (value == 1) ? shift : -1; | |
3960 | } | |
3961 | ||
e0c6ed95 | 3962 | /* Sort of like s_lcomm. */ |
252b5132 RH |
3963 | |
3964 | #ifndef OBJ_ELF | |
3965 | static int max_alignment = 15; | |
3966 | #endif | |
3967 | ||
3968 | static void | |
5a49b8ac | 3969 | s_reserve (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
3970 | { |
3971 | char *name; | |
3972 | char *p; | |
3973 | char c; | |
3974 | int align; | |
3975 | int size; | |
3976 | int temp; | |
3977 | symbolS *symbolP; | |
3978 | ||
d02603dc | 3979 | c = get_symbol_name (&name); |
252b5132 RH |
3980 | p = input_line_pointer; |
3981 | *p = c; | |
d02603dc | 3982 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
3983 | |
3984 | if (*input_line_pointer != ',') | |
3985 | { | |
3986 | as_bad (_("Expected comma after name")); | |
3987 | ignore_rest_of_line (); | |
3988 | return; | |
3989 | } | |
3990 | ||
3991 | ++input_line_pointer; | |
3992 | ||
3993 | if ((size = get_absolute_expression ()) < 0) | |
3994 | { | |
3995 | as_bad (_("BSS length (%d.) <0! Ignored."), size); | |
3996 | ignore_rest_of_line (); | |
3997 | return; | |
e0c6ed95 | 3998 | } /* Bad length. */ |
252b5132 RH |
3999 | |
4000 | *p = 0; | |
4001 | symbolP = symbol_find_or_make (name); | |
4002 | *p = c; | |
4003 | ||
4004 | if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 | |
4005 | && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) | |
4006 | { | |
4007 | as_bad (_("bad .reserve segment -- expected BSS segment")); | |
4008 | return; | |
4009 | } | |
4010 | ||
4011 | if (input_line_pointer[2] == '.') | |
4012 | input_line_pointer += 7; | |
4013 | else | |
4014 | input_line_pointer += 6; | |
4015 | SKIP_WHITESPACE (); | |
4016 | ||
4017 | if (*input_line_pointer == ',') | |
4018 | { | |
4019 | ++input_line_pointer; | |
4020 | ||
4021 | SKIP_WHITESPACE (); | |
4022 | if (*input_line_pointer == '\n') | |
4023 | { | |
4024 | as_bad (_("missing alignment")); | |
4025 | ignore_rest_of_line (); | |
4026 | return; | |
4027 | } | |
4028 | ||
4029 | align = (int) get_absolute_expression (); | |
4030 | ||
4031 | #ifndef OBJ_ELF | |
4032 | if (align > max_alignment) | |
4033 | { | |
4034 | align = max_alignment; | |
4035 | as_warn (_("alignment too large; assuming %d"), align); | |
4036 | } | |
4037 | #endif | |
4038 | ||
4039 | if (align < 0) | |
4040 | { | |
4041 | as_bad (_("negative alignment")); | |
4042 | ignore_rest_of_line (); | |
4043 | return; | |
4044 | } | |
4045 | ||
4046 | if (align != 0) | |
4047 | { | |
f17c130b | 4048 | temp = mylog2 (align); |
252b5132 RH |
4049 | if (temp < 0) |
4050 | { | |
4051 | as_bad (_("alignment not a power of 2")); | |
4052 | ignore_rest_of_line (); | |
4053 | return; | |
4054 | } | |
4055 | ||
4056 | align = temp; | |
4057 | } | |
4058 | ||
4059 | record_alignment (bss_section, align); | |
4060 | } | |
4061 | else | |
4062 | align = 0; | |
4063 | ||
4064 | if (!S_IS_DEFINED (symbolP) | |
4065 | #ifdef OBJ_AOUT | |
4066 | && S_GET_OTHER (symbolP) == 0 | |
4067 | && S_GET_DESC (symbolP) == 0 | |
4068 | #endif | |
4069 | ) | |
4070 | { | |
4071 | if (! need_pass_2) | |
4072 | { | |
4073 | char *pfrag; | |
4074 | segT current_seg = now_seg; | |
4075 | subsegT current_subseg = now_subseg; | |
4076 | ||
e0c6ed95 AM |
4077 | /* Switch to bss. */ |
4078 | subseg_set (bss_section, 1); | |
252b5132 RH |
4079 | |
4080 | if (align) | |
e0c6ed95 AM |
4081 | /* Do alignment. */ |
4082 | frag_align (align, 0, 0); | |
252b5132 | 4083 | |
e0c6ed95 | 4084 | /* Detach from old frag. */ |
ab3e48dc | 4085 | if (S_GET_SEGMENT (symbolP) == bss_section) |
49309057 | 4086 | symbol_get_frag (symbolP)->fr_symbol = NULL; |
252b5132 | 4087 | |
49309057 | 4088 | symbol_set_frag (symbolP, frag_now); |
e0c6ed95 AM |
4089 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
4090 | (offsetT) size, (char *) 0); | |
252b5132 RH |
4091 | *pfrag = 0; |
4092 | ||
4093 | S_SET_SEGMENT (symbolP, bss_section); | |
4094 | ||
4095 | subseg_set (current_seg, current_subseg); | |
4096 | ||
4097 | #ifdef OBJ_ELF | |
4098 | S_SET_SIZE (symbolP, size); | |
4099 | #endif | |
4100 | } | |
4101 | } | |
4102 | else | |
4103 | { | |
20203fb9 | 4104 | as_warn (_("Ignoring attempt to re-define symbol %s"), |
ab3e48dc | 4105 | S_GET_NAME (symbolP)); |
20203fb9 | 4106 | } |
252b5132 RH |
4107 | |
4108 | demand_empty_rest_of_line (); | |
4109 | } | |
4110 | ||
4111 | static void | |
5a49b8ac | 4112 | s_common (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4113 | { |
4114 | char *name; | |
4115 | char c; | |
4116 | char *p; | |
685736be | 4117 | offsetT temp, size; |
252b5132 RH |
4118 | symbolS *symbolP; |
4119 | ||
d02603dc | 4120 | c = get_symbol_name (&name); |
e0c6ed95 | 4121 | /* Just after name is now '\0'. */ |
252b5132 RH |
4122 | p = input_line_pointer; |
4123 | *p = c; | |
d02603dc | 4124 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
4125 | if (*input_line_pointer != ',') |
4126 | { | |
4127 | as_bad (_("Expected comma after symbol-name")); | |
4128 | ignore_rest_of_line (); | |
4129 | return; | |
4130 | } | |
e0c6ed95 AM |
4131 | |
4132 | /* Skip ','. */ | |
4133 | input_line_pointer++; | |
4134 | ||
252b5132 RH |
4135 | if ((temp = get_absolute_expression ()) < 0) |
4136 | { | |
685736be NC |
4137 | as_bad (_(".COMMon length (%lu) out of range ignored"), |
4138 | (unsigned long) temp); | |
252b5132 RH |
4139 | ignore_rest_of_line (); |
4140 | return; | |
4141 | } | |
4142 | size = temp; | |
4143 | *p = 0; | |
4144 | symbolP = symbol_find_or_make (name); | |
4145 | *p = c; | |
4146 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
4147 | { | |
4148 | as_bad (_("Ignoring attempt to re-define symbol")); | |
4149 | ignore_rest_of_line (); | |
4150 | return; | |
4151 | } | |
4152 | if (S_GET_VALUE (symbolP) != 0) | |
4153 | { | |
4154 | if (S_GET_VALUE (symbolP) != (valueT) size) | |
4155 | { | |
364b6d8b JJ |
4156 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), |
4157 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); | |
252b5132 RH |
4158 | } |
4159 | } | |
4160 | else | |
4161 | { | |
4162 | #ifndef OBJ_ELF | |
4163 | S_SET_VALUE (symbolP, (valueT) size); | |
4164 | S_SET_EXTERNAL (symbolP); | |
4165 | #endif | |
4166 | } | |
7dcc9865 | 4167 | know (symbol_get_frag (symbolP) == &zero_address_frag); |
252b5132 RH |
4168 | if (*input_line_pointer != ',') |
4169 | { | |
4170 | as_bad (_("Expected comma after common length")); | |
4171 | ignore_rest_of_line (); | |
4172 | return; | |
4173 | } | |
4174 | input_line_pointer++; | |
4175 | SKIP_WHITESPACE (); | |
4176 | if (*input_line_pointer != '"') | |
4177 | { | |
4178 | temp = get_absolute_expression (); | |
4179 | ||
4180 | #ifndef OBJ_ELF | |
4181 | if (temp > max_alignment) | |
4182 | { | |
4183 | temp = max_alignment; | |
f17c130b | 4184 | as_warn (_("alignment too large; assuming %ld"), (long) temp); |
252b5132 RH |
4185 | } |
4186 | #endif | |
4187 | ||
4188 | if (temp < 0) | |
4189 | { | |
4190 | as_bad (_("negative alignment")); | |
4191 | ignore_rest_of_line (); | |
4192 | return; | |
4193 | } | |
4194 | ||
4195 | #ifdef OBJ_ELF | |
49309057 | 4196 | if (symbol_get_obj (symbolP)->local) |
252b5132 RH |
4197 | { |
4198 | segT old_sec; | |
4199 | int old_subsec; | |
252b5132 RH |
4200 | int align; |
4201 | ||
4202 | old_sec = now_seg; | |
4203 | old_subsec = now_subseg; | |
4204 | ||
4205 | if (temp == 0) | |
4206 | align = 0; | |
4207 | else | |
f17c130b | 4208 | align = mylog2 (temp); |
252b5132 RH |
4209 | |
4210 | if (align < 0) | |
4211 | { | |
4212 | as_bad (_("alignment not a power of 2")); | |
4213 | ignore_rest_of_line (); | |
4214 | return; | |
4215 | } | |
4216 | ||
4217 | record_alignment (bss_section, align); | |
4218 | subseg_set (bss_section, 0); | |
4219 | if (align) | |
4220 | frag_align (align, 0, 0); | |
4221 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
4222 | symbol_get_frag (symbolP)->fr_symbol = 0; |
4223 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
4224 | p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
4225 | (offsetT) size, (char *) 0); | |
4226 | *p = 0; | |
4227 | S_SET_SEGMENT (symbolP, bss_section); | |
4228 | S_CLEAR_EXTERNAL (symbolP); | |
4229 | S_SET_SIZE (symbolP, size); | |
4230 | subseg_set (old_sec, old_subsec); | |
4231 | } | |
4232 | else | |
e0c6ed95 | 4233 | #endif /* OBJ_ELF */ |
252b5132 RH |
4234 | { |
4235 | allocate_common: | |
4236 | S_SET_VALUE (symbolP, (valueT) size); | |
4237 | #ifdef OBJ_ELF | |
4238 | S_SET_ALIGN (symbolP, temp); | |
4239 | S_SET_SIZE (symbolP, size); | |
4240 | #endif | |
4241 | S_SET_EXTERNAL (symbolP); | |
4242 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); | |
4243 | } | |
4244 | } | |
4245 | else | |
4246 | { | |
4247 | input_line_pointer++; | |
4248 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ | |
4249 | if (*input_line_pointer == '.') | |
4250 | input_line_pointer++; | |
4251 | /* @@ Some say data, some say bss. */ | |
4252 | if (strncmp (input_line_pointer, "bss\"", 4) | |
4253 | && strncmp (input_line_pointer, "data\"", 5)) | |
4254 | { | |
4255 | while (*--input_line_pointer != '"') | |
4256 | ; | |
4257 | input_line_pointer--; | |
4258 | goto bad_common_segment; | |
4259 | } | |
4260 | while (*input_line_pointer++ != '"') | |
4261 | ; | |
4262 | goto allocate_common; | |
4263 | } | |
4264 | ||
49309057 | 4265 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; |
252b5132 RH |
4266 | |
4267 | demand_empty_rest_of_line (); | |
4268 | return; | |
4269 | ||
4270 | { | |
4271 | bad_common_segment: | |
4272 | p = input_line_pointer; | |
4273 | while (*p && *p != '\n') | |
4274 | p++; | |
4275 | c = *p; | |
4276 | *p = '\0'; | |
4277 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); | |
4278 | *p = c; | |
4279 | input_line_pointer = p; | |
4280 | ignore_rest_of_line (); | |
4281 | return; | |
4282 | } | |
4283 | } | |
4284 | ||
67c1ffbe | 4285 | /* Handle the .empty pseudo-op. This suppresses the warnings about |
252b5132 RH |
4286 | invalid delay slot usage. */ |
4287 | ||
4288 | static void | |
5a49b8ac | 4289 | s_empty (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4290 | { |
4291 | /* The easy way to implement is to just forget about the last | |
4292 | instruction. */ | |
4293 | last_insn = NULL; | |
4294 | } | |
4295 | ||
4296 | static void | |
5a49b8ac | 4297 | s_seg (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4298 | { |
4299 | ||
4300 | if (strncmp (input_line_pointer, "\"text\"", 6) == 0) | |
4301 | { | |
4302 | input_line_pointer += 6; | |
4303 | s_text (0); | |
4304 | return; | |
4305 | } | |
4306 | if (strncmp (input_line_pointer, "\"data\"", 6) == 0) | |
4307 | { | |
4308 | input_line_pointer += 6; | |
4309 | s_data (0); | |
4310 | return; | |
4311 | } | |
4312 | if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) | |
4313 | { | |
4314 | input_line_pointer += 7; | |
4315 | s_data1 (); | |
4316 | return; | |
4317 | } | |
4318 | if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) | |
4319 | { | |
4320 | input_line_pointer += 5; | |
4321 | /* We only support 2 segments -- text and data -- for now, so | |
4322 | things in the "bss segment" will have to go into data for now. | |
e0c6ed95 AM |
4323 | You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ |
4324 | subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ | |
252b5132 RH |
4325 | return; |
4326 | } | |
4327 | as_bad (_("Unknown segment type")); | |
4328 | demand_empty_rest_of_line (); | |
4329 | } | |
4330 | ||
4331 | static void | |
5a49b8ac | 4332 | s_data1 (void) |
252b5132 RH |
4333 | { |
4334 | subseg_set (data_section, 1); | |
4335 | demand_empty_rest_of_line (); | |
4336 | } | |
4337 | ||
4338 | static void | |
5a49b8ac | 4339 | s_proc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4340 | { |
4341 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4342 | { | |
4343 | ++input_line_pointer; | |
4344 | } | |
4345 | ++input_line_pointer; | |
4346 | } | |
4347 | ||
4348 | /* This static variable is set by s_uacons to tell sparc_cons_align | |
67c1ffbe | 4349 | that the expression does not need to be aligned. */ |
252b5132 RH |
4350 | |
4351 | static int sparc_no_align_cons = 0; | |
4352 | ||
4353 | /* This handles the unaligned space allocation pseudo-ops, such as | |
4354 | .uaword. .uaword is just like .word, but the value does not need | |
4355 | to be aligned. */ | |
4356 | ||
4357 | static void | |
5a49b8ac | 4358 | s_uacons (int bytes) |
252b5132 RH |
4359 | { |
4360 | /* Tell sparc_cons_align not to align this value. */ | |
4361 | sparc_no_align_cons = 1; | |
4362 | cons (bytes); | |
4ffadb11 | 4363 | sparc_no_align_cons = 0; |
252b5132 RH |
4364 | } |
4365 | ||
cf9a1301 RH |
4366 | /* This handles the native word allocation pseudo-op .nword. |
4367 | For sparc_arch_size 32 it is equivalent to .word, for | |
4368 | sparc_arch_size 64 it is equivalent to .xword. */ | |
4369 | ||
4370 | static void | |
5a49b8ac | 4371 | s_ncons (int bytes ATTRIBUTE_UNUSED) |
cf9a1301 RH |
4372 | { |
4373 | cons (sparc_arch_size == 32 ? 4 : 8); | |
4374 | } | |
4375 | ||
6d8809aa RH |
4376 | #ifdef OBJ_ELF |
4377 | /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a | |
4378 | global register. | |
4379 | The syntax is: | |
e0c6ed95 | 4380 | |
6d8809aa | 4381 | .register %g[2367],{#scratch|symbolname|#ignore} |
e0c6ed95 | 4382 | */ |
6d8809aa RH |
4383 | |
4384 | static void | |
5a49b8ac | 4385 | s_register (int ignore ATTRIBUTE_UNUSED) |
6d8809aa RH |
4386 | { |
4387 | char c; | |
4388 | int reg; | |
4389 | int flags; | |
d02603dc | 4390 | char *regname; |
6d8809aa RH |
4391 | |
4392 | if (input_line_pointer[0] != '%' | |
4393 | || input_line_pointer[1] != 'g' | |
4394 | || ((input_line_pointer[2] & ~1) != '2' | |
4395 | && (input_line_pointer[2] & ~1) != '6') | |
4396 | || input_line_pointer[3] != ',') | |
4397 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
4398 | reg = input_line_pointer[2] - '0'; | |
4399 | input_line_pointer += 4; | |
4400 | ||
4401 | if (*input_line_pointer == '#') | |
4402 | { | |
4403 | ++input_line_pointer; | |
d02603dc | 4404 | c = get_symbol_name (®name); |
6d8809aa RH |
4405 | if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) |
4406 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
ab3e48dc | 4407 | if (regname[0] == 'i') |
6d8809aa RH |
4408 | regname = NULL; |
4409 | else | |
4410 | regname = ""; | |
4411 | } | |
4412 | else | |
4413 | { | |
d02603dc | 4414 | c = get_symbol_name (®name); |
6d8809aa | 4415 | } |
d02603dc | 4416 | |
6d8809aa RH |
4417 | if (sparc_arch_size == 64) |
4418 | { | |
e0c6ed95 | 4419 | if (globals[reg]) |
6d8809aa | 4420 | { |
e0c6ed95 AM |
4421 | if ((regname && globals[reg] != (symbolS *) 1 |
4422 | && strcmp (S_GET_NAME (globals[reg]), regname)) | |
4423 | || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) | |
6d8809aa RH |
4424 | as_bad (_("redefinition of global register")); |
4425 | } | |
4426 | else | |
4427 | { | |
4428 | if (regname == NULL) | |
e0c6ed95 | 4429 | globals[reg] = (symbolS *) 1; |
6d8809aa RH |
4430 | else |
4431 | { | |
4432 | if (*regname) | |
4433 | { | |
4434 | if (symbol_find (regname)) | |
4435 | as_bad (_("Register symbol %s already defined."), | |
4436 | regname); | |
4437 | } | |
e0c6ed95 AM |
4438 | globals[reg] = symbol_make (regname); |
4439 | flags = symbol_get_bfdsym (globals[reg])->flags; | |
6d8809aa RH |
4440 | if (! *regname) |
4441 | flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); | |
4442 | if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) | |
4443 | flags |= BSF_GLOBAL; | |
e0c6ed95 AM |
4444 | symbol_get_bfdsym (globals[reg])->flags = flags; |
4445 | S_SET_VALUE (globals[reg], (valueT) reg); | |
4446 | S_SET_ALIGN (globals[reg], reg); | |
4447 | S_SET_SIZE (globals[reg], 0); | |
6d8809aa RH |
4448 | /* Although we actually want undefined_section here, |
4449 | we have to use absolute_section, because otherwise | |
4450 | generic as code will make it a COM section. | |
4451 | We fix this up in sparc_adjust_symtab. */ | |
e0c6ed95 AM |
4452 | S_SET_SEGMENT (globals[reg], absolute_section); |
4453 | S_SET_OTHER (globals[reg], 0); | |
4454 | elf_symbol (symbol_get_bfdsym (globals[reg])) | |
6d8809aa RH |
4455 | ->internal_elf_sym.st_info = |
4456 | ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); | |
e0c6ed95 | 4457 | elf_symbol (symbol_get_bfdsym (globals[reg])) |
6d8809aa RH |
4458 | ->internal_elf_sym.st_shndx = SHN_UNDEF; |
4459 | } | |
4460 | } | |
4461 | } | |
4462 | ||
d02603dc | 4463 | (void) restore_line_pointer (c); |
6d8809aa RH |
4464 | |
4465 | demand_empty_rest_of_line (); | |
4466 | } | |
4467 | ||
4468 | /* Adjust the symbol table. We set undefined sections for STT_REGISTER | |
4469 | symbols which need it. */ | |
e0c6ed95 | 4470 | |
6d8809aa | 4471 | void |
5a49b8ac | 4472 | sparc_adjust_symtab (void) |
6d8809aa RH |
4473 | { |
4474 | symbolS *sym; | |
e0c6ed95 | 4475 | |
6d8809aa RH |
4476 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
4477 | { | |
4478 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4479 | ->internal_elf_sym.st_info) != STT_REGISTER) | |
4480 | continue; | |
4481 | ||
4482 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4483 | ->internal_elf_sym.st_shndx != SHN_UNDEF)) | |
4484 | continue; | |
4485 | ||
4486 | S_SET_SEGMENT (sym, undefined_section); | |
4487 | } | |
4488 | } | |
4489 | #endif | |
4490 | ||
252b5132 RH |
4491 | /* If the --enforce-aligned-data option is used, we require .word, |
4492 | et. al., to be aligned correctly. We do it by setting up an | |
4493 | rs_align_code frag, and checking in HANDLE_ALIGN to make sure that | |
4494 | no unexpected alignment was introduced. | |
4495 | ||
4496 | The SunOS and Solaris native assemblers enforce aligned data by | |
4497 | default. We don't want to do that, because gcc can deliberately | |
4498 | generate misaligned data if the packed attribute is used. Instead, | |
4499 | we permit misaligned data by default, and permit the user to set an | |
4500 | option to check for it. */ | |
4501 | ||
4502 | void | |
5a49b8ac | 4503 | sparc_cons_align (int nbytes) |
252b5132 RH |
4504 | { |
4505 | int nalign; | |
252b5132 RH |
4506 | |
4507 | /* Only do this if we are enforcing aligned data. */ | |
4508 | if (! enforce_aligned_data) | |
4509 | return; | |
4510 | ||
0f2712ed | 4511 | /* Don't align if this is an unaligned pseudo-op. */ |
252b5132 | 4512 | if (sparc_no_align_cons) |
0f2712ed | 4513 | return; |
252b5132 | 4514 | |
f17c130b | 4515 | nalign = mylog2 (nbytes); |
252b5132 RH |
4516 | if (nalign == 0) |
4517 | return; | |
4518 | ||
9c2799c2 | 4519 | gas_assert (nalign > 0); |
252b5132 RH |
4520 | |
4521 | if (now_seg == absolute_section) | |
4522 | { | |
4523 | if ((abs_section_offset & ((1 << nalign) - 1)) != 0) | |
4524 | as_bad (_("misaligned data")); | |
4525 | return; | |
4526 | } | |
4527 | ||
87975d2a AM |
4528 | frag_var (rs_align_test, 1, 1, (relax_substateT) 0, |
4529 | (symbolS *) NULL, (offsetT) nalign, (char *) NULL); | |
252b5132 RH |
4530 | |
4531 | record_alignment (now_seg, nalign); | |
4532 | } | |
4533 | ||
0a9ef439 | 4534 | /* This is called from HANDLE_ALIGN in tc-sparc.h. */ |
252b5132 RH |
4535 | |
4536 | void | |
5a49b8ac | 4537 | sparc_handle_align (fragS *fragp) |
252b5132 | 4538 | { |
0a9ef439 RH |
4539 | int count, fix; |
4540 | char *p; | |
4541 | ||
4542 | count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
bfb32b52 | 4543 | |
0a9ef439 | 4544 | switch (fragp->fr_type) |
252b5132 | 4545 | { |
0a9ef439 RH |
4546 | case rs_align_test: |
4547 | if (count != 0) | |
4548 | as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); | |
4549 | break; | |
e0c6ed95 | 4550 | |
0a9ef439 RH |
4551 | case rs_align_code: |
4552 | p = fragp->fr_literal + fragp->fr_fix; | |
4553 | fix = 0; | |
e0c6ed95 | 4554 | |
0a9ef439 RH |
4555 | if (count & 3) |
4556 | { | |
4557 | fix = count & 3; | |
4558 | memset (p, 0, fix); | |
4559 | p += fix; | |
4560 | count -= fix; | |
4561 | } | |
e0c6ed95 | 4562 | |
0a9ef439 RH |
4563 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) |
4564 | { | |
4565 | unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ | |
4566 | if (INSN_BIG_ENDIAN) | |
4567 | number_to_chars_bigendian (p, wval, 4); | |
4568 | else | |
4569 | number_to_chars_littleendian (p, wval, 4); | |
4570 | p += 4; | |
4571 | count -= 4; | |
4572 | fix += 4; | |
e0c6ed95 | 4573 | } |
0a9ef439 RH |
4574 | |
4575 | if (INSN_BIG_ENDIAN) | |
4576 | number_to_chars_bigendian (p, 0x01000000, 4); | |
4577 | else | |
4578 | number_to_chars_littleendian (p, 0x01000000, 4); | |
4579 | ||
4580 | fragp->fr_fix += fix; | |
4581 | fragp->fr_var = 4; | |
4582 | break; | |
4583 | ||
4584 | default: | |
4585 | break; | |
252b5132 RH |
4586 | } |
4587 | } | |
4588 | ||
4589 | #ifdef OBJ_ELF | |
4590 | /* Some special processing for a Sparc ELF file. */ | |
4591 | ||
4592 | void | |
5a49b8ac | 4593 | sparc_elf_final_processing (void) |
252b5132 RH |
4594 | { |
4595 | /* Set the Sparc ELF flag bits. FIXME: There should probably be some | |
4596 | sort of BFD interface for this. */ | |
4597 | if (sparc_arch_size == 64) | |
4598 | { | |
4599 | switch (sparc_memory_model) | |
4600 | { | |
4601 | case MM_RMO: | |
4602 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; | |
4603 | break; | |
4604 | case MM_PSO: | |
4605 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; | |
4606 | break; | |
4607 | default: | |
4608 | break; | |
4609 | } | |
4610 | } | |
4611 | else if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
4612 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; | |
4613 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
4614 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; | |
19f7b010 JJ |
4615 | else if (current_architecture == SPARC_OPCODE_ARCH_V9B) |
4616 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; | |
252b5132 | 4617 | } |
bd5e6e7e | 4618 | |
62ebcb5c | 4619 | const char * |
5a49b8ac | 4620 | sparc_cons (expressionS *exp, int size) |
bd5e6e7e JJ |
4621 | { |
4622 | char *save; | |
62ebcb5c | 4623 | const char *sparc_cons_special_reloc = NULL; |
bd5e6e7e JJ |
4624 | |
4625 | SKIP_WHITESPACE (); | |
bd5e6e7e JJ |
4626 | save = input_line_pointer; |
4627 | if (input_line_pointer[0] == '%' | |
4628 | && input_line_pointer[1] == 'r' | |
4629 | && input_line_pointer[2] == '_') | |
4630 | { | |
4631 | if (strncmp (input_line_pointer + 3, "disp", 4) == 0) | |
4632 | { | |
4633 | input_line_pointer += 7; | |
4634 | sparc_cons_special_reloc = "disp"; | |
4635 | } | |
4636 | else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) | |
4637 | { | |
4638 | if (size != 4 && size != 8) | |
4639 | as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); | |
4640 | else | |
4641 | { | |
4642 | input_line_pointer += 6; | |
4643 | sparc_cons_special_reloc = "plt"; | |
4644 | } | |
4645 | } | |
b9734f35 JJ |
4646 | else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) |
4647 | { | |
4648 | if (size != 4 && size != 8) | |
4649 | as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); | |
4650 | else | |
4651 | { | |
4652 | input_line_pointer += 13; | |
4653 | sparc_cons_special_reloc = "tls_dtpoff"; | |
4654 | } | |
4655 | } | |
bd5e6e7e JJ |
4656 | if (sparc_cons_special_reloc) |
4657 | { | |
4658 | int bad = 0; | |
4659 | ||
4660 | switch (size) | |
4661 | { | |
4662 | case 1: | |
4663 | if (*input_line_pointer != '8') | |
4664 | bad = 1; | |
4665 | input_line_pointer--; | |
4666 | break; | |
4667 | case 2: | |
4668 | if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') | |
4669 | bad = 1; | |
4670 | break; | |
4671 | case 4: | |
4672 | if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') | |
4673 | bad = 1; | |
4674 | break; | |
4675 | case 8: | |
4676 | if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') | |
4677 | bad = 1; | |
4678 | break; | |
4679 | default: | |
4680 | bad = 1; | |
4681 | break; | |
4682 | } | |
4683 | ||
4684 | if (bad) | |
4685 | { | |
4686 | as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), | |
4687 | sparc_cons_special_reloc, size * 8, size); | |
4688 | } | |
4689 | else | |
4690 | { | |
4691 | input_line_pointer += 2; | |
4692 | if (*input_line_pointer != '(') | |
4693 | { | |
4694 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4695 | sparc_cons_special_reloc, size * 8); | |
4696 | bad = 1; | |
4697 | } | |
4698 | } | |
4699 | ||
4700 | if (bad) | |
4701 | { | |
4702 | input_line_pointer = save; | |
4703 | sparc_cons_special_reloc = NULL; | |
4704 | } | |
4705 | else | |
4706 | { | |
4707 | int c; | |
4708 | char *end = ++input_line_pointer; | |
4709 | int npar = 0; | |
4710 | ||
4711 | while (! is_end_of_line[(c = *end)]) | |
4712 | { | |
4713 | if (c == '(') | |
4714 | npar++; | |
4715 | else if (c == ')') | |
4716 | { | |
4717 | if (!npar) | |
4718 | break; | |
4719 | npar--; | |
4720 | } | |
4721 | end++; | |
4722 | } | |
4723 | ||
4724 | if (c != ')') | |
4725 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4726 | sparc_cons_special_reloc, size * 8); | |
4727 | else | |
4728 | { | |
4729 | *end = '\0'; | |
4730 | expression (exp); | |
4731 | *end = c; | |
4732 | if (input_line_pointer != end) | |
4733 | { | |
4734 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4735 | sparc_cons_special_reloc, size * 8); | |
4736 | } | |
4737 | else | |
4738 | { | |
4739 | input_line_pointer++; | |
4740 | SKIP_WHITESPACE (); | |
4741 | c = *input_line_pointer; | |
4742 | if (! is_end_of_line[c] && c != ',') | |
4743 | as_bad (_("Illegal operands: garbage after %%r_%s%d()"), | |
4744 | sparc_cons_special_reloc, size * 8); | |
4745 | } | |
4746 | } | |
4747 | } | |
4748 | } | |
4749 | } | |
4750 | if (sparc_cons_special_reloc == NULL) | |
4751 | expression (exp); | |
62ebcb5c | 4752 | return sparc_cons_special_reloc; |
bd5e6e7e JJ |
4753 | } |
4754 | ||
252b5132 RH |
4755 | #endif |
4756 | ||
4757 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
4758 | reloc for a cons. We could use the definition there, except that | |
4759 | we want to handle little endian relocs specially. */ | |
4760 | ||
4761 | void | |
5a49b8ac AM |
4762 | cons_fix_new_sparc (fragS *frag, |
4763 | int where, | |
4764 | unsigned int nbytes, | |
62ebcb5c AM |
4765 | expressionS *exp, |
4766 | const char *sparc_cons_special_reloc) | |
252b5132 RH |
4767 | { |
4768 | bfd_reloc_code_real_type r; | |
4769 | ||
4770 | r = (nbytes == 1 ? BFD_RELOC_8 : | |
4771 | (nbytes == 2 ? BFD_RELOC_16 : | |
4772 | (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
4773 | ||
0f2712ed NC |
4774 | if (target_little_endian_data |
4775 | && nbytes == 4 | |
e0c6ed95 | 4776 | && now_seg->flags & SEC_ALLOC) |
252b5132 | 4777 | r = BFD_RELOC_SPARC_REV32; |
0f2712ed | 4778 | |
bd5e6e7e JJ |
4779 | if (sparc_cons_special_reloc) |
4780 | { | |
4781 | if (*sparc_cons_special_reloc == 'd') | |
4782 | switch (nbytes) | |
4783 | { | |
4784 | case 1: r = BFD_RELOC_8_PCREL; break; | |
4785 | case 2: r = BFD_RELOC_16_PCREL; break; | |
4786 | case 4: r = BFD_RELOC_32_PCREL; break; | |
4787 | case 8: r = BFD_RELOC_64_PCREL; break; | |
4788 | default: abort (); | |
4789 | } | |
b9734f35 | 4790 | else if (*sparc_cons_special_reloc == 'p') |
bd5e6e7e JJ |
4791 | switch (nbytes) |
4792 | { | |
4793 | case 4: r = BFD_RELOC_SPARC_PLT32; break; | |
4794 | case 8: r = BFD_RELOC_SPARC_PLT64; break; | |
4795 | } | |
b9734f35 JJ |
4796 | else |
4797 | switch (nbytes) | |
4798 | { | |
4799 | case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; | |
4800 | case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; | |
4801 | } | |
bd5e6e7e JJ |
4802 | } |
4803 | else if (sparc_no_align_cons) | |
0f2712ed NC |
4804 | { |
4805 | switch (nbytes) | |
4806 | { | |
4807 | case 2: r = BFD_RELOC_SPARC_UA16; break; | |
4808 | case 4: r = BFD_RELOC_SPARC_UA32; break; | |
4809 | case 8: r = BFD_RELOC_SPARC_UA64; break; | |
4810 | default: abort (); | |
4811 | } | |
4ffadb11 | 4812 | } |
0f2712ed | 4813 | |
252b5132 | 4814 | fix_new_exp (frag, where, (int) nbytes, exp, 0, r); |
364b6d8b JJ |
4815 | } |
4816 | ||
4817 | void | |
5a49b8ac | 4818 | sparc_cfi_frame_initial_instructions (void) |
364b6d8b JJ |
4819 | { |
4820 | cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); | |
4821 | } | |
4822 | ||
4823 | int | |
1df69f4f | 4824 | sparc_regname_to_dw2regnum (char *regname) |
364b6d8b JJ |
4825 | { |
4826 | char *p, *q; | |
4827 | ||
4828 | if (!regname[0]) | |
4829 | return -1; | |
4830 | ||
4831 | q = "goli"; | |
4832 | p = strchr (q, regname[0]); | |
4833 | if (p) | |
4834 | { | |
4835 | if (regname[1] < '0' || regname[1] > '8' || regname[2]) | |
4836 | return -1; | |
4837 | return (p - q) * 8 + regname[1] - '0'; | |
4838 | } | |
4839 | if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) | |
4840 | return 14; | |
4841 | if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) | |
4842 | return 30; | |
4843 | if (regname[0] == 'f' || regname[0] == 'r') | |
4844 | { | |
4845 | unsigned int regnum; | |
4846 | ||
4847 | regnum = strtoul (regname + 1, &q, 10); | |
4848 | if (p == q || *q) | |
4849 | return -1; | |
4850 | if (regnum >= ((regname[0] == 'f' | |
4851 | && SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
4852 | ? 64 : 32)) | |
4853 | return -1; | |
4854 | if (regname[0] == 'f') | |
4855 | { | |
4856 | regnum += 32; | |
4857 | if (regnum >= 64 && (regnum & 1)) | |
4858 | return -1; | |
4859 | } | |
4860 | return regnum; | |
4861 | } | |
4862 | return -1; | |
4863 | } | |
4864 | ||
4865 | void | |
4866 | sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) | |
4867 | { | |
364b6d8b | 4868 | sparc_no_align_cons = 1; |
62ebcb5c | 4869 | emit_expr_with_reloc (exp, nbytes, "disp"); |
364b6d8b | 4870 | sparc_no_align_cons = 0; |
252b5132 | 4871 | } |