projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gas/
[deliverable/binutils-gdb.git] / gas / config / tc-sparc.c
CommitLineData
252b5132 1/* tc-sparc.c -- Assemble for the SPARC
f7e42eb4 2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
ae6063d4 3 1999, 2000, 2001, 2002, 2003
e0c6ed95 4 Free Software Foundation, Inc.
252b5132
RH		 5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 59 Temple Place - Suite 330,
81d4177b 20 Boston, MA 02111-1307, USA. */
252b5132
RH		 21
22#include <stdio.h>
252b5132
RH		 23
24#include "as.h"
3882b010 25#include "safe-ctype.h"
252b5132
RH		 26#include "subsegs.h"
27
28#include "opcode/sparc.h"
29
30#ifdef OBJ_ELF
31#include "elf/sparc.h"
732d96b6 32#include "dwarf2dbg.h"
252b5132
RH		 33#endif
34
6c1b24e4
AO		 35/* Some ancient Sun C compilers would not take such hex constants as
36 unsigned, and would end up sign-extending them to form an offsetT,
37 so use these constants instead. */
38#define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39#define U0x80000000 ((((unsigned long) 1 << 16) << 15))
40
252b5132
RH		 41static struct sparc_arch *lookup_arch PARAMS ((char *));
42static void init_default_arch PARAMS ((void));
a22b281c 43static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
252b5132
RH		 44static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
45static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
46static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
47static int sparc_ffs PARAMS ((unsigned int));
a22b281c
RH		 48static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
49static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
50static void synthetize_setx PARAMS ((const struct sparc_opcode *));
252b5132
RH		 51static bfd_vma BSR PARAMS ((bfd_vma, int));
52static int cmp_reg_entry PARAMS ((const PTR, const PTR));
53static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
54static int parse_const_expr_arg PARAMS ((char **, int *));
55static int get_expression PARAMS ((char *str));
56
57/* Default architecture. */
58/* ??? The default value should be V8, but sparclite support was added
59 by making it the default. GCC now passes -Asparclite, so maybe sometime in
60 the future we can set this to V8. */
61#ifndef DEFAULT_ARCH
62#define DEFAULT_ARCH "sparclite"
63#endif
64static char *default_arch = DEFAULT_ARCH;
65
66/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
67 have been set. */
68static int default_init_p;
69
70/* Current architecture. We don't bump up unless necessary. */
71static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
72
73/* The maximum architecture level we can bump up to.
74 In a 32 bit environment, don't allow bumping up to v9 by default.
75 The native assembler works this way. The user is required to pass
76 an explicit argument before we'll create v9 object files. However, if
77 we don't see any v9 insns, a v8plus object file is not created. */
78static enum sparc_opcode_arch_val max_architecture;
79
80/* Either 32 or 64, selects file format. */
81static int sparc_arch_size;
82/* Initial (default) value, recorded separately in case a user option
83 changes the value before md_show_usage is called. */
84static int default_arch_size;
85
86#ifdef OBJ_ELF
87/* The currently selected v9 memory model. Currently only used for
88 ELF. */
89static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
90#endif
91
92static int architecture_requested;
93static int warn_on_bump;
94
95/* If warn_on_bump and the needed architecture is higher than this
96 architecture, issue a warning. */
97static enum sparc_opcode_arch_val warn_after_architecture;
98
6d8809aa
RH		 99/* Non-zero if as should generate error if an undeclared g[23] register
100 has been used in -64. */
101static int no_undeclared_regs;
102
6faf3d66
JJ		 103/* Non-zero if we should try to relax jumps and calls. */
104static int sparc_relax;
105
252b5132
RH		 106/* Non-zero if we are generating PIC code. */
107int sparc_pic_code;
108
109/* Non-zero if we should give an error when misaligned data is seen. */
110static int enforce_aligned_data;
111
112extern int target_big_endian;
113
114static int target_little_endian_data;
115
6d8809aa
RH		 116/* Symbols for global registers on v9. */
117static symbolS *globals[8];
118
252b5132
RH		 119/* V9 and 86x have big and little endian data, but instructions are always big
120 endian. The sparclet has bi-endian support but both data and insns have
121 the same endianness. Global `target_big_endian' is used for data.
122 The following macro is used for instructions. */
123#ifndef INSN_BIG_ENDIAN
124#define INSN_BIG_ENDIAN (target_big_endian \
125 || default_arch_type == sparc86x \
126 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
127#endif
128
e0c6ed95 129/* Handle of the OPCODE hash table. */
252b5132
RH		 130static struct hash_control *op_hash;
131
132static int log2 PARAMS ((int));
133static void s_data1 PARAMS ((void));
134static void s_seg PARAMS ((int));
135static void s_proc PARAMS ((int));
136static void s_reserve PARAMS ((int));
137static void s_common PARAMS ((int));
138static void s_empty PARAMS ((int));
139static void s_uacons PARAMS ((int));
cf9a1301 140static void s_ncons PARAMS ((int));
a7982600 141#ifdef OBJ_ELF
6d8809aa 142static void s_register PARAMS ((int));
a7982600 143#endif
252b5132
RH		 144
145const pseudo_typeS md_pseudo_table[] =
146{
e0c6ed95 147 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
252b5132
RH		 148 {"common", s_common, 0},
149 {"empty", s_empty, 0},
150 {"global", s_globl, 0},
151 {"half", cons, 2},
cf9a1301 152 {"nword", s_ncons, 0},
252b5132
RH		 153 {"optim", s_ignore, 0},
154 {"proc", s_proc, 0},
155 {"reserve", s_reserve, 0},
156 {"seg", s_seg, 0},
157 {"skip", s_space, 0},
158 {"word", cons, 4},
159 {"xword", cons, 8},
160 {"uahalf", s_uacons, 2},
161 {"uaword", s_uacons, 4},
162 {"uaxword", s_uacons, 8},
163#ifdef OBJ_ELF
9f1838ed 164 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
732d96b6 165 {"loc", dwarf2_directive_loc, 0},
e0c6ed95 166 /* These are specific to sparc/svr4. */
252b5132
RH		 167 {"2byte", s_uacons, 2},
168 {"4byte", s_uacons, 4},
169 {"8byte", s_uacons, 8},
6d8809aa 170 {"register", s_register, 0},
252b5132
RH		 171#endif
172 {NULL, 0, 0},
173};
174
e0c6ed95
AM		 175/* Size of relocation record. */
176const int md_reloc_size = 12;
252b5132
RH		 177
178/* This array holds the chars that always start a comment. If the
e0c6ed95
AM		 179 pre-processor is disabled, these aren't very useful. */
180const char comment_chars[] = "!"; /* JF removed '|' from
181 comment_chars. */
252b5132
RH		 182
183/* This array holds the chars that only start a comment at the beginning of
184 a line. If the line seems to have the form '# 123 filename'
e0c6ed95 185 .line and .file directives will appear in the pre-processed output. */
252b5132
RH		 186/* Note that input_file.c hand checks for '#' at the beginning of the
187 first line of the input file. This is because the compiler outputs
e0c6ed95 188 #NO_APP at the beginning of its output. */
252b5132 189/* Also note that comments started like this one will always
e0c6ed95 190 work if '/' isn't otherwise defined. */
252b5132
RH		 191const char line_comment_chars[] = "#";
192
63a0b638 193const char line_separator_chars[] = ";";
252b5132 194
e0c6ed95
AM		 195/* Chars that can be used to separate mant from exp in floating point
196 nums. */
252b5132
RH		 197const char EXP_CHARS[] = "eE";
198
e0c6ed95
AM		 199/* Chars that mean this number is a floating point constant.
200 As in 0f12.456
201 or 0d1.2345e12 */
252b5132
RH		 202const char FLT_CHARS[] = "rRsSfFdDxXpP";
203
204/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
205 changed in read.c. Ideally it shouldn't have to know about it at all,
206 but nothing is ideal around here. */
207
bc805888 208#define isoctal(c) ((unsigned) ((c) - '0') < '8')
252b5132
RH		 209
210struct sparc_it
211 {
212 char *error;
213 unsigned long opcode;
214 struct nlist *nlistp;
215 expressionS exp;
cf9a1301 216 expressionS exp2;
252b5132
RH		 217 int pcrel;
218 bfd_reloc_code_real_type reloc;
219 };
220
221struct sparc_it the_insn, set_insn;
222
223static void output_insn
224 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
225\f
226/* Table of arguments to -A.
227 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
228 for this use. That table is for opcodes only. This table is for opcodes
229 and file formats. */
230
231enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
19f7b010 232 v8plusa, v9, v9a, v9b, v9_64};
252b5132
RH		 233
234static struct sparc_arch {
235 char *name;
236 char *opcode_arch;
237 enum sparc_arch_types arch_type;
238 /* Default word size, as specified during configuration.
239 A value of zero means can't be used to specify default architecture. */
240 int default_arch_size;
241 /* Allowable arg to -A? */
242 int user_option_p;
243} sparc_arch_table[] = {
244 { "v6", "v6", v6, 0, 1 },
245 { "v7", "v7", v7, 0, 1 },
246 { "v8", "v8", v8, 32, 1 },
247 { "sparclet", "sparclet", sparclet, 32, 1 },
248 { "sparclite", "sparclite", sparclite, 32, 1 },
249 { "sparc86x", "sparclite", sparc86x, 32, 1 },
250 { "v8plus", "v9", v9, 0, 1 },
251 { "v8plusa", "v9a", v9, 0, 1 },
19f7b010 252 { "v8plusb", "v9b", v9, 0, 1 },
252b5132
RH		 253 { "v9", "v9", v9, 0, 1 },
254 { "v9a", "v9a", v9, 0, 1 },
19f7b010 255 { "v9b", "v9b", v9, 0, 1 },
252b5132
RH		 256 /* This exists to allow configure.in/Makefile.in to pass one
257 value to specify both the default machine and default word size. */
258 { "v9-64", "v9", v9, 64, 0 },
259 { NULL, NULL, v8, 0, 0 }
260};
261
262/* Variant of default_arch */
263static enum sparc_arch_types default_arch_type;
264
265static struct sparc_arch *
266lookup_arch (name)
267 char *name;
268{
269 struct sparc_arch *sa;
270
271 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
272 if (strcmp (sa->name, name) == 0)
273 break;
274 if (sa->name == NULL)
275 return NULL;
276 return sa;
277}
278
279/* Initialize the default opcode arch and word size from the default
280 architecture name. */
281
282static void
283init_default_arch ()
284{
285 struct sparc_arch *sa = lookup_arch (default_arch);
286
287 if (sa == NULL
288 || sa->default_arch_size == 0)
289 as_fatal (_("Invalid default architecture, broken assembler."));
290
291 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
292 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
293 as_fatal (_("Bad opcode table, broken assembler."));
294 default_arch_size = sparc_arch_size = sa->default_arch_size;
295 default_init_p = 1;
296 default_arch_type = sa->arch_type;
297}
298
299/* Called by TARGET_FORMAT. */
300
301const char *
302sparc_target_format ()
303{
304 /* We don't get a chance to initialize anything before we're called,
305 so handle that now. */
306 if (! default_init_p)
307 init_default_arch ();
308
309#ifdef OBJ_AOUT
310#ifdef TE_NetBSD
311 return "a.out-sparc-netbsd";
312#else
313#ifdef TE_SPARCAOUT
314 if (target_big_endian)
315 return "a.out-sunos-big";
316 else if (default_arch_type == sparc86x && target_little_endian_data)
317 return "a.out-sunos-big";
ab3e48dc
KH		 318 else
319 return "a.out-sparc-little";
252b5132
RH		 320#else
321 return "a.out-sunos-big";
322#endif
323#endif
324#endif
325
326#ifdef OBJ_BOUT
327 return "b.out.big";
328#endif
329
330#ifdef OBJ_COFF
331#ifdef TE_LYNX
332 return "coff-sparc-lynx";
333#else
334 return "coff-sparc";
335#endif
336#endif
337
338#ifdef OBJ_ELF
339 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
340#endif
341
342 abort ();
343}
344\f
e0c6ed95 345/* md_parse_option
252b5132
RH		 346 * Invocation line includes a switch not recognized by the base assembler.
347 * See if it's a processor-specific option. These are:
348 *
349 * -bump
350 * Warn on architecture bumps. See also -A.
351 *
352 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
353 * Standard 32 bit architectures.
19f7b010 354 * -Av9, -Av9a, -Av9b
252b5132
RH		 355 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
356 * This used to only mean 64 bits, but properly specifying it
357 * complicated gcc's ASM_SPECs, so now opcode selection is
358 * specified orthogonally to word size (except when specifying
359 * the default, but that is an internal implementation detail).
19f7b010
JJ		 360 * -Av8plus, -Av8plusa, -Av8plusb
361 * Same as -Av9{,a,b}.
362 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
363 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
364 * assembler.
365 * -xarch=v9, -xarch=v9a, -xarch=v9b
366 * Same as -Av9{,a,b} -64, for compatibility with Sun's
c2158c24 367 * assembler.
252b5132
RH		 368 *
369 * Select the architecture and possibly the file format.
370 * Instructions or features not supported by the selected
371 * architecture cause fatal errors.
372 *
373 * The default is to start at v6, and bump the architecture up
374 * whenever an instruction is seen at a higher level. In 32 bit
375 * environments, v9 is not bumped up to, the user must pass
19f7b010 376 * -Av8plus{,a,b}.
252b5132
RH		 377 *
378 * If -bump is specified, a warning is printing when bumping to
379 * higher levels.
380 *
381 * If an architecture is specified, all instructions must match
382 * that architecture. Any higher level instructions are flagged
383 * as errors. Note that in the 32 bit environment specifying
384 * -Av8plus does not automatically create a v8plus object file, a
385 * v9 insn must be seen.
386 *
387 * If both an architecture and -bump are specified, the
388 * architecture starts at the specified level, but bumps are
389 * warnings. Note that we can't set `current_architecture' to
390 * the requested level in this case: in the 32 bit environment,
391 * we still must avoid creating v8plus object files unless v9
392 * insns are seen.
393 *
394 * Note:
395 * Bumping between incompatible architectures is always an
396 * error. For example, from sparclite to v9.
397 */
398
399#ifdef OBJ_ELF
5a38dc70 400const char *md_shortopts = "A:K:VQ:sq";
252b5132
RH		 401#else
402#ifdef OBJ_AOUT
5a38dc70 403const char *md_shortopts = "A:k";
252b5132 404#else
5a38dc70 405const char *md_shortopts = "A:";
252b5132
RH		 406#endif
407#endif
408struct option md_longopts[] = {
409#define OPTION_BUMP (OPTION_MD_BASE)
410 {"bump", no_argument, NULL, OPTION_BUMP},
411#define OPTION_SPARC (OPTION_MD_BASE + 1)
412 {"sparc", no_argument, NULL, OPTION_SPARC},
413#define OPTION_XARCH (OPTION_MD_BASE + 2)
414 {"xarch", required_argument, NULL, OPTION_XARCH},
415#ifdef OBJ_ELF
416#define OPTION_32 (OPTION_MD_BASE + 3)
417 {"32", no_argument, NULL, OPTION_32},
418#define OPTION_64 (OPTION_MD_BASE + 4)
419 {"64", no_argument, NULL, OPTION_64},
420#define OPTION_TSO (OPTION_MD_BASE + 5)
421 {"TSO", no_argument, NULL, OPTION_TSO},
422#define OPTION_PSO (OPTION_MD_BASE + 6)
423 {"PSO", no_argument, NULL, OPTION_PSO},
424#define OPTION_RMO (OPTION_MD_BASE + 7)
425 {"RMO", no_argument, NULL, OPTION_RMO},
426#endif
427#ifdef SPARC_BIENDIAN
428#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
429 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
430#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
431 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
432#endif
433#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
434 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
435#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
436 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
6d8809aa
RH		 437#ifdef OBJ_ELF
438#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
439 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
a25fe906
ILT		 440#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
441 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
6d8809aa 442#endif
6faf3d66
JJ		 443#define OPTION_RELAX (OPTION_MD_BASE + 14)
444 {"relax", no_argument, NULL, OPTION_RELAX},
445#define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
446 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
252b5132
RH		 447 {NULL, no_argument, NULL, 0}
448};
e0c6ed95
AM		 449
450size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 451
452int
453md_parse_option (c, arg)
454 int c;
455 char *arg;
456{
457 /* We don't get a chance to initialize anything before we're called,
458 so handle that now. */
459 if (! default_init_p)
460 init_default_arch ();
461
462 switch (c)
463 {
464 case OPTION_BUMP:
465 warn_on_bump = 1;
466 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
467 break;
468
469 case OPTION_XARCH:
c2158c24
JJ		 470#ifdef OBJ_ELF
471 if (strncmp (arg, "v9", 2) != 0)
472 md_parse_option (OPTION_32, NULL);
473 else
474 md_parse_option (OPTION_64, NULL);
475#endif
e0c6ed95 476 /* Fall through. */
252b5132
RH		 477
478 case 'A':
479 {
480 struct sparc_arch *sa;
481 enum sparc_opcode_arch_val opcode_arch;
482
483 sa = lookup_arch (arg);
484 if (sa == NULL
485 || ! sa->user_option_p)
486 {
c2158c24
JJ		 487 if (c == OPTION_XARCH)
488 as_bad (_("invalid architecture -xarch=%s"), arg);
489 else
490 as_bad (_("invalid architecture -A%s"), arg);
252b5132
RH		 491 return 0;
492 }
493
494 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
495 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
496 as_fatal (_("Bad opcode table, broken assembler."));
497
498 max_architecture = opcode_arch;
499 architecture_requested = 1;
500 }
501 break;
502
503 case OPTION_SPARC:
504 /* Ignore -sparc, used by SunOS make default .s.o rule. */
505 break;
506
507 case OPTION_ENFORCE_ALIGNED_DATA:
508 enforce_aligned_data = 1;
509 break;
510
511#ifdef SPARC_BIENDIAN
512 case OPTION_LITTLE_ENDIAN:
513 target_big_endian = 0;
514 if (default_arch_type != sparclet)
515 as_fatal ("This target does not support -EL");
516 break;
517 case OPTION_LITTLE_ENDIAN_DATA:
518 target_little_endian_data = 1;
519 target_big_endian = 0;
520 if (default_arch_type != sparc86x
521 && default_arch_type != v9)
522 as_fatal ("This target does not support --little-endian-data");
523 break;
524 case OPTION_BIG_ENDIAN:
525 target_big_endian = 1;
526 break;
527#endif
528
529#ifdef OBJ_AOUT
530 case 'k':
531 sparc_pic_code = 1;
532 break;
533#endif
534
535#ifdef OBJ_ELF
536 case OPTION_32:
537 case OPTION_64:
538 {
539 const char **list, **l;
540
541 sparc_arch_size = c == OPTION_32 ? 32 : 64;
542 list = bfd_target_list ();
543 for (l = list; *l != NULL; l++)
544 {
545 if (sparc_arch_size == 32)
546 {
547 if (strcmp (*l, "elf32-sparc") == 0)
548 break;
549 }
550 else
551 {
552 if (strcmp (*l, "elf64-sparc") == 0)
553 break;
554 }
555 }
556 if (*l == NULL)
557 as_fatal (_("No compiled in support for %d bit object file format"),
558 sparc_arch_size);
559 free (list);
560 }
561 break;
562
563 case OPTION_TSO:
564 sparc_memory_model = MM_TSO;
565 break;
566
567 case OPTION_PSO:
568 sparc_memory_model = MM_PSO;
569 break;
570
571 case OPTION_RMO:
572 sparc_memory_model = MM_RMO;
573 break;
574
575 case 'V':
576 print_version_id ();
577 break;
578
579 case 'Q':
580 /* Qy - do emit .comment
e0c6ed95 581 Qn - do not emit .comment. */
252b5132
RH		 582 break;
583
584 case 's':
e0c6ed95 585 /* Use .stab instead of .stab.excl. */
252b5132
RH		 586 break;
587
588 case 'q':
e0c6ed95 589 /* quick -- Native assembler does fewer checks. */
252b5132
RH		 590 break;
591
592 case 'K':
593 if (strcmp (arg, "PIC") != 0)
594 as_warn (_("Unrecognized option following -K"));
595 else
596 sparc_pic_code = 1;
597 break;
6d8809aa
RH		 598
599 case OPTION_NO_UNDECLARED_REGS:
600 no_undeclared_regs = 1;
601 break;
a25fe906
ILT		 602
603 case OPTION_UNDECLARED_REGS:
604 no_undeclared_regs = 0;
605 break;
252b5132
RH		 606#endif
607
6faf3d66
JJ		 608 case OPTION_RELAX:
609 sparc_relax = 1;
610 break;
611
612 case OPTION_NO_RELAX:
613 sparc_relax = 0;
614 break;
615
252b5132
RH		 616 default:
617 return 0;
618 }
619
620 return 1;
621}
622
623void
624md_show_usage (stream)
625 FILE *stream;
626{
627 const struct sparc_arch *arch;
c2158c24 628 int column;
252b5132
RH		 629
630 /* We don't get a chance to initialize anything before we're called,
631 so handle that now. */
632 if (! default_init_p)
633 init_default_arch ();
634
e0c6ed95 635 fprintf (stream, _("SPARC options:\n"));
c2158c24 636 column = 0;
252b5132
RH		 637 for (arch = &sparc_arch_table[0]; arch->name; arch++)
638 {
c2158c24
JJ		 639 if (!arch->user_option_p)
640 continue;
252b5132
RH		 641 if (arch != &sparc_arch_table[0])
642 fprintf (stream, " | ");
07726851 643 if (column + strlen (arch->name) > 70)
c2158c24
JJ		 644 {
645 column = 0;
646 fputc ('\n', stream);
647 }
07726851 648 column += 5 + 2 + strlen (arch->name);
c2158c24 649 fprintf (stream, "-A%s", arch->name);
252b5132 650 }
c2158c24
JJ		 651 for (arch = &sparc_arch_table[0]; arch->name; arch++)
652 {
653 if (!arch->user_option_p)
654 continue;
655 fprintf (stream, " | ");
07726851 656 if (column + strlen (arch->name) > 65)
c2158c24
JJ		 657 {
658 column = 0;
659 fputc ('\n', stream);
660 }
07726851 661 column += 5 + 7 + strlen (arch->name);
c2158c24
JJ		 662 fprintf (stream, "-xarch=%s", arch->name);
663 }
664 fprintf (stream, _("\n\
252b5132
RH		 665 specify variant of SPARC architecture\n\
666-bump warn when assembler switches architectures\n\
667-sparc ignored\n\
6faf3d66
JJ		 668--enforce-aligned-data force .long, etc., to be aligned correctly\n\
669-relax relax jumps and branches (default)\n\
670-no-relax avoid changing any jumps and branches\n"));
252b5132
RH		 671#ifdef OBJ_AOUT
672 fprintf (stream, _("\
673-k generate PIC\n"));
674#endif
675#ifdef OBJ_ELF
676 fprintf (stream, _("\
677-32 create 32 bit object file\n\
678-64 create 64 bit object file\n"));
679 fprintf (stream, _("\
680 [default is %d]\n"), default_arch_size);
681 fprintf (stream, _("\
682-TSO use Total Store Ordering\n\
683-PSO use Partial Store Ordering\n\
684-RMO use Relaxed Memory Ordering\n"));
685 fprintf (stream, _("\
686 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
687 fprintf (stream, _("\
688-KPIC generate PIC\n\
689-V print assembler version number\n\
a25fe906
ILT		 690-undeclared-regs ignore application global register usage without\n\
691 appropriate .register directive (default)\n\
692-no-undeclared-regs force error on application global register usage\n\
693 without appropriate .register directive\n\
252b5132
RH		 694-q ignored\n\
695-Qy, -Qn ignored\n\
696-s ignored\n"));
697#endif
698#ifdef SPARC_BIENDIAN
699 fprintf (stream, _("\
700-EL generate code for a little endian machine\n\
701-EB generate code for a big endian machine\n\
702--little-endian-data generate code for a machine having big endian\n\
c20f4f8c 703 instructions and little endian data.\n"));
252b5132
RH		 704#endif
705}
706\f
e0c6ed95 707/* Native operand size opcode translation. */
cf9a1301
RH		 708struct
709 {
710 char *name;
711 char *name32;
712 char *name64;
713 } native_op_table[] =
714{
715 {"ldn", "ld", "ldx"},
716 {"ldna", "lda", "ldxa"},
717 {"stn", "st", "stx"},
718 {"stna", "sta", "stxa"},
719 {"slln", "sll", "sllx"},
720 {"srln", "srl", "srlx"},
721 {"sran", "sra", "srax"},
722 {"casn", "cas", "casx"},
723 {"casna", "casa", "casxa"},
724 {"clrn", "clr", "clrx"},
725 {NULL, NULL, NULL},
726};
727\f
e0c6ed95 728/* sparc64 priviledged registers. */
252b5132
RH		 729
730struct priv_reg_entry
ab3e48dc
KH		 731{
732 char *name;
733 int regnum;
734};
252b5132
RH		 735
736struct priv_reg_entry priv_reg_table[] =
737{
738 {"tpc", 0},
739 {"tnpc", 1},
740 {"tstate", 2},
741 {"tt", 3},
742 {"tick", 4},
743 {"tba", 5},
744 {"pstate", 6},
745 {"tl", 7},
746 {"pil", 8},
747 {"cwp", 9},
748 {"cansave", 10},
749 {"canrestore", 11},
750 {"cleanwin", 12},
751 {"otherwin", 13},
752 {"wstate", 14},
753 {"fq", 15},
754 {"ver", 31},
e0c6ed95 755 {"", -1}, /* End marker. */
252b5132
RH		 756};
757
e0c6ed95 758/* v9a specific asrs. */
252b5132
RH		 759
760struct priv_reg_entry v9a_asr_table[] =
761{
762 {"tick_cmpr", 23},
19f7b010
JJ		 763 {"sys_tick_cmpr", 25},
764 {"sys_tick", 24},
252b5132
RH		 765 {"softint", 22},
766 {"set_softint", 20},
767 {"pic", 17},
768 {"pcr", 16},
769 {"gsr", 19},
770 {"dcr", 18},
771 {"clear_softint", 21},
e0c6ed95 772 {"", -1}, /* End marker. */
252b5132
RH		 773};
774
775static int
776cmp_reg_entry (parg, qarg)
777 const PTR parg;
778 const PTR qarg;
779{
780 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
781 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
782
783 return strcmp (q->name, p->name);
784}
785\f
786/* This function is called once, at assembler startup time. It should
e0c6ed95
AM		 787 set up all the tables, etc. that the MD part of the assembler will
788 need. */
252b5132
RH		 789
790void
791md_begin ()
792{
793 register const char *retval = NULL;
794 int lose = 0;
795 register unsigned int i = 0;
796
797 /* We don't get a chance to initialize anything before md_parse_option
798 is called, and it may not be called, so handle default initialization
799 now if not already done. */
800 if (! default_init_p)
801 init_default_arch ();
802
803 op_hash = hash_new ();
804
805 while (i < (unsigned int) sparc_num_opcodes)
806 {
807 const char *name = sparc_opcodes[i].name;
808 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
809 if (retval != NULL)
810 {
cf9a1301
RH		 811 as_bad (_("Internal error: can't hash `%s': %s\n"),
812 sparc_opcodes[i].name, retval);
252b5132
RH		 813 lose = 1;
814 }
815 do
816 {
817 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
818 {
cf9a1301
RH		 819 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
820 sparc_opcodes[i].name, sparc_opcodes[i].args);
252b5132
RH		 821 lose = 1;
822 }
823 ++i;
824 }
825 while (i < (unsigned int) sparc_num_opcodes
826 && !strcmp (sparc_opcodes[i].name, name));
827 }
828
cf9a1301
RH		 829 for (i = 0; native_op_table[i].name; i++)
830 {
831 const struct sparc_opcode *insn;
3d4ae3c0
NC		 832 char *name = ((sparc_arch_size == 32)
833 ? native_op_table[i].name32
834 : native_op_table[i].name64);
e0c6ed95 835 insn = (struct sparc_opcode *) hash_find (op_hash, name);
cf9a1301 836 if (insn == NULL)
e0c6ed95
AM		 837 {
838 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
839 name, native_op_table[i].name);
840 lose = 1;
841 }
cf9a1301
RH		 842 else
843 {
844 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
845 if (retval != NULL)
846 {
847 as_bad (_("Internal error: can't hash `%s': %s\n"),
848 sparc_opcodes[i].name, retval);
849 lose = 1;
850 }
851 }
852 }
853
252b5132
RH		 854 if (lose)
855 as_fatal (_("Broken assembler. No assembly attempted."));
856
252b5132
RH		 857 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
858 sizeof (priv_reg_table[0]), cmp_reg_entry);
859
860 /* If -bump, record the architecture level at which we start issuing
861 warnings. The behaviour is different depending upon whether an
862 architecture was explicitly specified. If it wasn't, we issue warnings
863 for all upwards bumps. If it was, we don't start issuing warnings until
864 we need to bump beyond the requested architecture or when we bump between
865 conflicting architectures. */
866
867 if (warn_on_bump
868 && architecture_requested)
869 {
870 /* `max_architecture' records the requested architecture.
871 Issue warnings if we go above it. */
872 warn_after_architecture = max_architecture;
873
874 /* Find the highest architecture level that doesn't conflict with
875 the requested one. */
876 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
877 max_architecture > warn_after_architecture;
878 --max_architecture)
879 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
880 warn_after_architecture))
881 break;
882 }
883}
884
885/* Called after all assembly has been done. */
886
887void
888sparc_md_end ()
889{
19f7b010
JJ		 890 unsigned long mach = bfd_mach_sparc;
891
252b5132 892 if (sparc_arch_size == 64)
19f7b010
JJ		 893 switch (current_architecture)
894 {
895 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
896 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
897 default: mach = bfd_mach_sparc_v9; break;
898 }
252b5132 899 else
19f7b010
JJ		 900 switch (current_architecture)
901 {
902 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
903 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
904 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
905 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
906 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
907 be but for now it is (since that's the way it's always been
908 treated). */
909 default: break;
910 }
911 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
252b5132
RH		 912}
913\f
914/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
915
916static INLINE int
917in_signed_range (val, max)
918 bfd_signed_vma val, max;
919{
920 if (max <= 0)
921 abort ();
922 /* Sign-extend the value from the architecture word size, so that
923 0xffffffff is always considered -1 on sparc32. */
924 if (sparc_arch_size == 32)
925 {
e0c6ed95 926 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
6c1b24e4 927 val = ((val & U0xffffffff) ^ sign) - sign;
252b5132
RH		 928 }
929 if (val > max)
930 return 0;
931 if (val < ~max)
932 return 0;
933 return 1;
934}
935
936/* Return non-zero if VAL is in the range 0 to MAX. */
937
938static INLINE int
939in_unsigned_range (val, max)
940 bfd_vma val, max;
941{
942 if (val > max)
943 return 0;
944 return 1;
945}
946
947/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
948 (e.g. -15 to +31). */
949
950static INLINE int
951in_bitfield_range (val, max)
952 bfd_signed_vma val, max;
953{
954 if (max <= 0)
955 abort ();
956 if (val > max)
957 return 0;
958 if (val < ~(max >> 1))
959 return 0;
960 return 1;
961}
962
963static int
964sparc_ffs (mask)
965 unsigned int mask;
966{
967 int i;
968
969 if (mask == 0)
970 return -1;
971
972 for (i = 0; (mask & 1) == 0; ++i)
973 mask >>= 1;
974 return i;
975}
976
977/* Implement big shift right. */
978static bfd_vma
979BSR (val, amount)
980 bfd_vma val;
981 int amount;
982{
983 if (sizeof (bfd_vma) <= 4 && amount >= 32)
984 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
985 return val >> amount;
986}
987\f
988/* For communication between sparc_ip and get_expression. */
989static char *expr_end;
990
252b5132
RH		 991/* Values for `special_case'.
992 Instructions that require wierd handling because they're longer than
993 4 bytes. */
994#define SPECIAL_CASE_NONE 0
995#define SPECIAL_CASE_SET 1
996#define SPECIAL_CASE_SETSW 2
997#define SPECIAL_CASE_SETX 3
998/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
999#define SPECIAL_CASE_FDIV 4
1000
1001/* Bit masks of various insns. */
1002#define NOP_INSN 0x01000000
1003#define OR_INSN 0x80100000
63fab58c 1004#define XOR_INSN 0x80180000
252b5132
RH		 1005#define FMOVS_INSN 0x81A00020
1006#define SETHI_INSN 0x01000000
1007#define SLLX_INSN 0x81281000
1008#define SRA_INSN 0x81380000
1009
1010/* The last instruction to be assembled. */
1011static const struct sparc_opcode *last_insn;
1012/* The assembled opcode of `last_insn'. */
1013static unsigned long last_opcode;
1014\f
a22b281c 1015/* Handle the set and setuw synthetic instructions. */
e0c6ed95 1016
a22b281c
RH		 1017static void
1018synthetize_setuw (insn)
1019 const struct sparc_opcode *insn;
1020{
1021 int need_hi22_p = 0;
1022 int rd = (the_insn.opcode & RD (~0)) >> 25;
1023
1024 if (the_insn.exp.X_op == O_constant)
1025 {
1026 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1027 {
e0c6ed95 1028 if (sizeof (offsetT) > 4
a22b281c 1029 && (the_insn.exp.X_add_number < 0
6c1b24e4 1030 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
a22b281c
RH		 1031 as_warn (_("set: number not in 0..4294967295 range"));
1032 }
1033 else
1034 {
e0c6ed95 1035 if (sizeof (offsetT) > 4
6c1b24e4
AO		 1036 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1037 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
a22b281c 1038 as_warn (_("set: number not in -2147483648..4294967295 range"));
e0c6ed95 1039 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
a22b281c
RH		 1040 }
1041 }
1042
1043 /* See if operand is absolute and small; skip sethi if so. */
1044 if (the_insn.exp.X_op != O_constant
1045 || the_insn.exp.X_add_number >= (1 << 12)
1046 || the_insn.exp.X_add_number < -(1 << 12))
1047 {
1048 the_insn.opcode = (SETHI_INSN | RD (rd)
1049 | ((the_insn.exp.X_add_number >> 10)
ab3e48dc
KH		 1050 & (the_insn.exp.X_op == O_constant
1051 ? 0x3fffff : 0)));
a22b281c 1052 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1053 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
a22b281c
RH		 1054 output_insn (insn, &the_insn);
1055 need_hi22_p = 1;
1056 }
1057
1058 /* See if operand has no low-order bits; skip OR if so. */
1059 if (the_insn.exp.X_op != O_constant
1060 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1061 || ! need_hi22_p)
1062 {
1063 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1064 | RD (rd) | IMMED
1065 | (the_insn.exp.X_add_number
ab3e48dc
KH		 1066 & (the_insn.exp.X_op != O_constant
1067 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
a22b281c 1068 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1069 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
a22b281c
RH		 1070 output_insn (insn, &the_insn);
1071 }
1072}
e0c6ed95 1073
a22b281c 1074/* Handle the setsw synthetic instruction. */
e0c6ed95 1075
a22b281c
RH		 1076static void
1077synthetize_setsw (insn)
1078 const struct sparc_opcode *insn;
1079{
1080 int low32, rd, opc;
1081
1082 rd = (the_insn.opcode & RD (~0)) >> 25;
1083
1084 if (the_insn.exp.X_op != O_constant)
1085 {
1086 synthetize_setuw (insn);
1087
1088 /* Need to sign extend it. */
1089 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1090 the_insn.reloc = BFD_RELOC_NONE;
1091 output_insn (insn, &the_insn);
1092 return;
1093 }
1094
e0c6ed95 1095 if (sizeof (offsetT) > 4
6c1b24e4
AO		 1096 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1097 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
a22b281c
RH		 1098 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1099
e0c6ed95
AM		 1100 low32 = the_insn.exp.X_add_number;
1101
a22b281c
RH		 1102 if (low32 >= 0)
1103 {
1104 synthetize_setuw (insn);
1105 return;
1106 }
1107
1108 opc = OR_INSN;
e0c6ed95 1109
a22b281c
RH		 1110 the_insn.reloc = BFD_RELOC_NONE;
1111 /* See if operand is absolute and small; skip sethi if so. */
1112 if (low32 < -(1 << 12))
1113 {
1114 the_insn.opcode = (SETHI_INSN | RD (rd)
1115 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1116 output_insn (insn, &the_insn);
1117 low32 = 0x1c00 | (low32 & 0x3ff);
1118 opc = RS1 (rd) | XOR_INSN;
1119 }
1120
1121 the_insn.opcode = (opc | RD (rd) | IMMED
1122 | (low32 & 0x1fff));
1123 output_insn (insn, &the_insn);
1124}
1125
1126/* Handle the setsw synthetic instruction. */
e0c6ed95 1127
a22b281c
RH		 1128static void
1129synthetize_setx (insn)
1130 const struct sparc_opcode *insn;
1131{
1132 int upper32, lower32;
1133 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1134 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1135 int upper_dstreg;
1136 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1137 int need_xor10_p = 0;
e0c6ed95 1138
6c1b24e4 1139#define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
a22b281c
RH		 1140 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1141 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1142#undef SIGNEXT32
1143
1144 upper_dstreg = tmpreg;
1145 /* The tmp reg should not be the dst reg. */
1146 if (tmpreg == dstreg)
1147 as_warn (_("setx: temporary register same as destination register"));
1148
1149 /* ??? Obviously there are other optimizations we can do
1150 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1151 doing some of these. Later. If you do change things, try to
1152 change all of this to be table driven as well. */
1153 /* What to output depends on the number if it's constant.
1154 Compute that first, then output what we've decided upon. */
1155 if (the_insn.exp.X_op != O_constant)
1156 {
1157 if (sparc_arch_size == 32)
1158 {
1159 /* When arch size is 32, we want setx to be equivalent
1160 to setuw for anything but constants. */
1161 the_insn.exp.X_add_number &= 0xffffffff;
1162 synthetize_setuw (insn);
1163 return;
1164 }
1165 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
ab3e48dc
KH		 1166 lower32 = 0;
1167 upper32 = 0;
a22b281c
RH		 1168 }
1169 else
1170 {
1171 /* Reset X_add_number, we've extracted it as upper32/lower32.
1172 Otherwise fixup_segment will complain about not being able to
1173 write an 8 byte number in a 4 byte field. */
1174 the_insn.exp.X_add_number = 0;
e0c6ed95 1175
a22b281c
RH		 1176 /* Only need hh22 if `or' insn can't handle constant. */
1177 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1178 need_hh22_p = 1;
e0c6ed95 1179
a22b281c
RH		 1180 /* Does bottom part (after sethi) have bits? */
1181 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1182 /* No hh22, but does upper32 still have bits we can't set
1183 from lower32? */
1184 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1185 need_hm10_p = 1;
e0c6ed95 1186
a22b281c
RH		 1187 /* If the lower half is all zero, we build the upper half directly
1188 into the dst reg. */
1189 if (lower32 != 0
1190 /* Need lower half if number is zero or 0xffffffff00000000. */
1191 || (! need_hh22_p && ! need_hm10_p))
1192 {
1193 /* No need for sethi if `or' insn can handle constant. */
1194 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1195 /* Note that we can't use a negative constant in the `or'
1196 insn unless the upper 32 bits are all ones. */
1197 || (lower32 < 0 && upper32 != -1)
1198 || (lower32 >= 0 && upper32 == -1))
1199 need_hi22_p = 1;
e0c6ed95 1200
a22b281c
RH		 1201 if (need_hi22_p && upper32 == -1)
1202 need_xor10_p = 1;
1203
1204 /* Does bottom part (after sethi) have bits? */
1205 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1206 /* No sethi. */
1207 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1208 /* Need `or' if we didn't set anything else. */
1209 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1210 need_lo10_p = 1;
1211 }
1212 else
1213 /* Output directly to dst reg if lower 32 bits are all zero. */
1214 upper_dstreg = dstreg;
1215 }
e0c6ed95 1216
a22b281c
RH		 1217 if (!upper_dstreg && dstreg)
1218 as_warn (_("setx: illegal temporary register g0"));
1219
1220 if (need_hh22_p)
1221 {
1222 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1223 | ((upper32 >> 10) & 0x3fffff));
1224 the_insn.reloc = (the_insn.exp.X_op != O_constant
1225 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1226 output_insn (insn, &the_insn);
1227 }
e0c6ed95 1228
a22b281c
RH		 1229 if (need_hi22_p)
1230 {
1231 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1232 | (((need_xor10_p ? ~lower32 : lower32)
ab3e48dc 1233 >> 10) & 0x3fffff));
a22b281c
RH		 1234 the_insn.reloc = (the_insn.exp.X_op != O_constant
1235 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1236 output_insn (insn, &the_insn);
1237 }
1238
1239 if (need_hm10_p)
1240 {
1241 the_insn.opcode = (OR_INSN
1242 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1243 | RD (upper_dstreg)
1244 | IMMED
1245 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1246 the_insn.reloc = (the_insn.exp.X_op != O_constant
1247 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1248 output_insn (insn, &the_insn);
1249 }
e0c6ed95 1250
a22b281c
RH		 1251 if (need_lo10_p)
1252 {
1253 /* FIXME: One nice optimization to do here is to OR the low part
1254 with the highpart if hi22 isn't needed and the low part is
1255 positive. */
1256 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1257 | RD (dstreg)
1258 | IMMED
1259 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1260 the_insn.reloc = (the_insn.exp.X_op != O_constant
1261 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1262 output_insn (insn, &the_insn);
1263 }
e0c6ed95 1264
a22b281c
RH		 1265 /* If we needed to build the upper part, shift it into place. */
1266 if (need_hh22_p || need_hm10_p)
1267 {
1268 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1269 | IMMED | 32);
1270 the_insn.reloc = BFD_RELOC_NONE;
1271 output_insn (insn, &the_insn);
1272 }
e0c6ed95 1273
a22b281c
RH		 1274 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1275 if (need_xor10_p)
1276 {
1277 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1278 | 0x1c00 | (lower32 & 0x3ff));
1279 the_insn.reloc = BFD_RELOC_NONE;
1280 output_insn (insn, &the_insn);
1281 }
1282
1283 /* If we needed to build both upper and lower parts, OR them together. */
1284 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1285 {
1286 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1287 | RD (dstreg));
1288 the_insn.reloc = BFD_RELOC_NONE;
1289 output_insn (insn, &the_insn);
1290 }
1291}
1292\f
252b5132
RH		 1293/* Main entry point to assemble one instruction. */
1294
1295void
1296md_assemble (str)
1297 char *str;
1298{
1299 const struct sparc_opcode *insn;
a22b281c 1300 int special_case;
252b5132
RH		 1301
1302 know (str);
a22b281c 1303 special_case = sparc_ip (str, &insn);
252b5132
RH		 1304
1305 /* We warn about attempts to put a floating point branch in a delay slot,
1306 unless the delay slot has been annulled. */
1307 if (insn != NULL
1308 && last_insn != NULL
1309 && (insn->flags & F_FBR) != 0
1310 && (last_insn->flags & F_DELAYED) != 0
1311 /* ??? This test isn't completely accurate. We assume anything with
1312 F_{UNBR,CONDBR,FBR} set is annullable. */
1313 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1314 || (last_opcode & ANNUL) == 0))
1315 as_warn (_("FP branch in delay slot"));
1316
1317 /* SPARC before v9 requires a nop instruction between a floating
1318 point instruction and a floating point branch. We insert one
1319 automatically, with a warning. */
1320 if (max_architecture < SPARC_OPCODE_ARCH_V9
1321 && insn != NULL
1322 && last_insn != NULL
1323 && (insn->flags & F_FBR) != 0
1324 && (last_insn->flags & F_FLOAT) != 0)
1325 {
1326 struct sparc_it nop_insn;
1327
1328 nop_insn.opcode = NOP_INSN;
1329 nop_insn.reloc = BFD_RELOC_NONE;
1330 output_insn (insn, &nop_insn);
1331 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1332 }
1333
a22b281c
RH		 1334 switch (special_case)
1335 {
1336 case SPECIAL_CASE_NONE:
e0c6ed95 1337 /* Normal insn. */
a22b281c
RH		 1338 output_insn (insn, &the_insn);
1339 break;
252b5132 1340
a22b281c
RH		 1341 case SPECIAL_CASE_SETSW:
1342 synthetize_setsw (insn);
1343 break;
e0c6ed95 1344
a22b281c
RH		 1345 case SPECIAL_CASE_SET:
1346 synthetize_setuw (insn);
1347 break;
252b5132 1348
a22b281c
RH		 1349 case SPECIAL_CASE_SETX:
1350 synthetize_setx (insn);
1351 break;
e0c6ed95 1352
a22b281c
RH		 1353 case SPECIAL_CASE_FDIV:
1354 {
1355 int rd = (the_insn.opcode >> 25) & 0x1f;
e0c6ed95 1356
a22b281c 1357 output_insn (insn, &the_insn);
e0c6ed95 1358
a22b281c
RH		 1359 /* According to information leaked from Sun, the "fdiv" instructions
1360 on early SPARC machines would produce incorrect results sometimes.
1361 The workaround is to add an fmovs of the destination register to
1362 itself just after the instruction. This was true on machines
e0c6ed95 1363 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
a22b281c
RH		 1364 assert (the_insn.reloc == BFD_RELOC_NONE);
1365 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1366 output_insn (insn, &the_insn);
1367 return;
1368 }
e0c6ed95 1369
a22b281c
RH		 1370 default:
1371 as_fatal (_("failed special case insn sanity check"));
252b5132
RH		 1372 }
1373}
1374
1375/* Subroutine of md_assemble to do the actual parsing. */
1376
a22b281c 1377static int
252b5132
RH		 1378sparc_ip (str, pinsn)
1379 char *str;
1380 const struct sparc_opcode **pinsn;
1381{
1382 char *error_message = "";
1383 char *s;
1384 const char *args;
1385 char c;
1386 const struct sparc_opcode *insn;
1387 char *argsStart;
1388 unsigned long opcode;
1389 unsigned int mask = 0;
1390 int match = 0;
1391 int comma = 0;
1392 int v9_arg_p;
a22b281c 1393 int special_case = SPECIAL_CASE_NONE;
252b5132
RH		 1394
1395 s = str;
3882b010 1396 if (ISLOWER (*s))
252b5132
RH		 1397 {
1398 do
1399 ++s;
3882b010 1400 while (ISLOWER (*s) || ISDIGIT (*s));
252b5132
RH		 1401 }
1402
1403 switch (*s)
1404 {
1405 case '\0':
1406 break;
1407
1408 case ',':
1409 comma = 1;
e0c6ed95 1410 /* Fall through. */
252b5132
RH		 1411
1412 case ' ':
1413 *s++ = '\0';
1414 break;
1415
1416 default:
1417 as_fatal (_("Unknown opcode: `%s'"), str);
1418 }
1419 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1420 *pinsn = insn;
1421 if (insn == NULL)
1422 {
1423 as_bad (_("Unknown opcode: `%s'"), str);
a22b281c 1424 return special_case;
252b5132
RH		 1425 }
1426 if (comma)
1427 {
1428 *--s = ',';
1429 }
1430
1431 argsStart = s;
1432 for (;;)
1433 {
1434 opcode = insn->match;
1435 memset (&the_insn, '\0', sizeof (the_insn));
1436 the_insn.reloc = BFD_RELOC_NONE;
1437 v9_arg_p = 0;
1438
e0c6ed95
AM		 1439 /* Build the opcode, checking as we go to make sure that the
1440 operands match. */
252b5132
RH		 1441 for (args = insn->args;; ++args)
1442 {
1443 switch (*args)
1444 {
1445 case 'K':
1446 {
1447 int kmask = 0;
1448
1449 /* Parse a series of masks. */
1450 if (*s == '#')
1451 {
1452 while (*s == '#')
1453 {
1454 int mask;
1455
1456 if (! parse_keyword_arg (sparc_encode_membar, &s,
1457 &mask))
1458 {
1459 error_message = _(": invalid membar mask name");
1460 goto error;
1461 }
1462 kmask |= mask;
47926f60
KH		 1463 while (*s == ' ')
1464 ++s;
252b5132
RH		 1465 if (*s == '|' || *s == '+')
1466 ++s;
47926f60
KH		 1467 while (*s == ' ')
1468 ++s;
252b5132
RH		 1469 }
1470 }
1471 else
1472 {
1473 if (! parse_const_expr_arg (&s, &kmask))
1474 {
1475 error_message = _(": invalid membar mask expression");
1476 goto error;
1477 }
1478 if (kmask < 0 || kmask > 127)
1479 {
1480 error_message = _(": invalid membar mask number");
1481 goto error;
1482 }
1483 }
1484
1485 opcode |= MEMBAR (kmask);
1486 continue;
1487 }
1488
19f7b010
JJ		 1489 case '3':
1490 {
1491 int smask = 0;
1492
1493 if (! parse_const_expr_arg (&s, &smask))
1494 {
1495 error_message = _(": invalid siam mode expression");
1496 goto error;
1497 }
1498 if (smask < 0 || smask > 7)
1499 {
1500 error_message = _(": invalid siam mode number");
1501 goto error;
1502 }
1503 opcode |= smask;
1504 continue;
1505 }
1506
252b5132
RH		 1507 case '*':
1508 {
1509 int fcn = 0;
1510
1511 /* Parse a prefetch function. */
1512 if (*s == '#')
1513 {
1514 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1515 {
1516 error_message = _(": invalid prefetch function name");
1517 goto error;
1518 }
1519 }
1520 else
1521 {
1522 if (! parse_const_expr_arg (&s, &fcn))
1523 {
1524 error_message = _(": invalid prefetch function expression");
1525 goto error;
1526 }
1527 if (fcn < 0 || fcn > 31)
1528 {
1529 error_message = _(": invalid prefetch function number");
1530 goto error;
1531 }
1532 }
1533 opcode |= RD (fcn);
1534 continue;
1535 }
1536
1537 case '!':
1538 case '?':
1539 /* Parse a sparc64 privileged register. */
1540 if (*s == '%')
1541 {
1542 struct priv_reg_entry *p = priv_reg_table;
e0c6ed95 1543 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1544
1545 s += 1;
1546 while (p->name[0] > s[0])
1547 p++;
1548 while (p->name[0] == s[0])
1549 {
1550 len = strlen (p->name);
1551 if (strncmp (p->name, s, len) == 0)
1552 break;
1553 p++;
1554 }
1555 if (p->name[0] != s[0])
1556 {
1557 error_message = _(": unrecognizable privileged register");
1558 goto error;
1559 }
1560 if (*args == '?')
1561 opcode |= (p->regnum << 14);
1562 else
1563 opcode |= (p->regnum << 25);
1564 s += len;
1565 continue;
1566 }
1567 else
1568 {
1569 error_message = _(": unrecognizable privileged register");
1570 goto error;
1571 }
1572
1573 case '_':
1574 case '/':
19f7b010 1575 /* Parse a v9a/v9b ancillary state register. */
252b5132
RH		 1576 if (*s == '%')
1577 {
1578 struct priv_reg_entry *p = v9a_asr_table;
e0c6ed95 1579 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1580
1581 s += 1;
1582 while (p->name[0] > s[0])
1583 p++;
1584 while (p->name[0] == s[0])
1585 {
1586 len = strlen (p->name);
1587 if (strncmp (p->name, s, len) == 0)
1588 break;
1589 p++;
1590 }
1591 if (p->name[0] != s[0])
1592 {
19f7b010 1593 error_message = _(": unrecognizable v9a or v9b ancillary state register");
252b5132
RH		 1594 goto error;
1595 }
1596 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1597 {
1598 error_message = _(": rd on write only ancillary state register");
1599 goto error;
e0c6ed95 1600 }
19f7b010
JJ		 1601 if (p->regnum >= 24
1602 && (insn->architecture
1603 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1604 {
1605 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1606 error_message = _(": unrecognizable v9a ancillary state register");
1607 goto error;
1608 }
252b5132
RH		 1609 if (*args == '/')
1610 opcode |= (p->regnum << 14);
1611 else
1612 opcode |= (p->regnum << 25);
1613 s += len;
1614 continue;
1615 }
1616 else
1617 {
19f7b010 1618 error_message = _(": unrecognizable v9a or v9b ancillary state register");
252b5132
RH		 1619 goto error;
1620 }
1621
1622 case 'M':
1623 case 'm':
1624 if (strncmp (s, "%asr", 4) == 0)
1625 {
1626 s += 4;
1627
3882b010 1628 if (ISDIGIT (*s))
252b5132
RH		 1629 {
1630 long num = 0;
1631
3882b010 1632 while (ISDIGIT (*s))
252b5132
RH		 1633 {
1634 num = num * 10 + *s - '0';
1635 ++s;
1636 }
1637
1638 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1639 {
1640 if (num < 16 || 31 < num)
1641 {
1642 error_message = _(": asr number must be between 16 and 31");
1643 goto error;
1644 }
1645 }
1646 else
1647 {
1648 if (num < 0 || 31 < num)
1649 {
1650 error_message = _(": asr number must be between 0 and 31");
1651 goto error;
1652 }
1653 }
1654
1655 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1656 continue;
1657 }
1658 else
1659 {
1660 error_message = _(": expecting %asrN");
1661 goto error;
1662 }
e0c6ed95 1663 } /* if %asr */
252b5132
RH		 1664 break;
1665
1666 case 'I':
1667 the_insn.reloc = BFD_RELOC_SPARC_11;
1668 goto immediate;
1669
1670 case 'j':
1671 the_insn.reloc = BFD_RELOC_SPARC_10;
1672 goto immediate;
1673
1674 case 'X':
1675 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1676 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1677 the_insn.reloc = BFD_RELOC_SPARC_5;
1678 else
1679 the_insn.reloc = BFD_RELOC_SPARC13;
1680 /* These fields are unsigned, but for upward compatibility,
1681 allow negative values as well. */
1682 goto immediate;
1683
1684 case 'Y':
1685 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1686 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1687 the_insn.reloc = BFD_RELOC_SPARC_6;
1688 else
1689 the_insn.reloc = BFD_RELOC_SPARC13;
1690 /* These fields are unsigned, but for upward compatibility,
1691 allow negative values as well. */
1692 goto immediate;
1693
1694 case 'k':
1695 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1696 the_insn.pcrel = 1;
1697 goto immediate;
1698
1699 case 'G':
1700 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1701 the_insn.pcrel = 1;
1702 goto immediate;
1703
1704 case 'N':
1705 if (*s == 'p' && s[1] == 'n')
1706 {
1707 s += 2;
1708 continue;
1709 }
1710 break;
1711
1712 case 'T':
1713 if (*s == 'p' && s[1] == 't')
1714 {
1715 s += 2;
1716 continue;
1717 }
1718 break;
1719
1720 case 'z':
1721 if (*s == ' ')
1722 {
1723 ++s;
1724 }
1725 if (strncmp (s, "%icc", 4) == 0)
1726 {
1727 s += 4;
1728 continue;
1729 }
1730 break;
1731
1732 case 'Z':
1733 if (*s == ' ')
1734 {
1735 ++s;
1736 }
1737 if (strncmp (s, "%xcc", 4) == 0)
1738 {
1739 s += 4;
1740 continue;
1741 }
1742 break;
1743
1744 case '6':
1745 if (*s == ' ')
1746 {
1747 ++s;
1748 }
1749 if (strncmp (s, "%fcc0", 5) == 0)
1750 {
1751 s += 5;
1752 continue;
1753 }
1754 break;
1755
1756 case '7':
1757 if (*s == ' ')
1758 {
1759 ++s;
1760 }
1761 if (strncmp (s, "%fcc1", 5) == 0)
1762 {
1763 s += 5;
1764 continue;
1765 }
1766 break;
1767
1768 case '8':
1769 if (*s == ' ')
1770 {
1771 ++s;
1772 }
1773 if (strncmp (s, "%fcc2", 5) == 0)
1774 {
1775 s += 5;
1776 continue;
1777 }
1778 break;
1779
1780 case '9':
1781 if (*s == ' ')
1782 {
1783 ++s;
1784 }
1785 if (strncmp (s, "%fcc3", 5) == 0)
1786 {
1787 s += 5;
1788 continue;
1789 }
1790 break;
1791
1792 case 'P':
1793 if (strncmp (s, "%pc", 3) == 0)
1794 {
1795 s += 3;
1796 continue;
1797 }
1798 break;
1799
1800 case 'W':
1801 if (strncmp (s, "%tick", 5) == 0)
1802 {
1803 s += 5;
1804 continue;
1805 }
1806 break;
1807
e0c6ed95 1808 case '\0': /* End of args. */
b9734f35 1809 if (s[0] == ',' && s[1] == '%')
252b5132 1810 {
b9734f35
JJ		 1811 static const struct tls_ops {
1812 /* The name as it appears in assembler. */
1813 char *name;
1814 /* strlen (name), precomputed for speed */
1815 int len;
1816 /* The reloc this pseudo-op translates to. */
1817 int reloc;
1818 /* 1 if call. */
1819 int call;
1820 } tls_ops[] = {
1821 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
1822 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
1823 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
1824 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
1825 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
1826 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
1827 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
1828 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }
1829 };
1830 const struct tls_ops *o;
1831 char *s1;
1832 int npar = 0;
1833
1834 for (o = tls_ops; o->name; o++)
1835 if (strncmp (s + 2, o->name, o->len) == 0)
1836 break;
1837 if (o->name == NULL)
1838 break;
1839
1840 if (s[o->len + 2] != '(')
1841 {
1842 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1843 return special_case;
1844 }
1845
1846 if (! o->call && the_insn.reloc != BFD_RELOC_NONE)
1847 {
1848 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1849 o->name);
1850 return special_case;
1851 }
1852
1853 if (o->call
1854 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
1855 || the_insn.exp.X_add_number != 0
1856 || the_insn.exp.X_add_symbol
1857 != symbol_find_or_make ("__tls_get_addr")))
1858 {
1859 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1860 o->name);
1861 return special_case;
1862 }
1863
1864 the_insn.reloc = o->reloc;
1865 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
1866 s += o->len + 3;
1867
1868 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
1869 if (*s1 == '(')
1870 npar++;
1871 else if (*s1 == ')')
1872 {
1873 if (!npar)
1874 break;
1875 npar--;
1876 }
1877
1878 if (*s1 != ')')
1879 {
1880 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1881 return special_case;
1882 }
1883
1884 *s1 = '\0';
1885 (void) get_expression (s);
1886 *s1 = ')';
1887 s = s1 + 1;
252b5132 1888 }
b9734f35
JJ		 1889 if (*s == '\0')
1890 match = 1;
252b5132
RH		 1891 break;
1892
1893 case '+':
1894 if (*s == '+')
1895 {
1896 ++s;
1897 continue;
1898 }
1899 if (*s == '-')
1900 {
1901 continue;
1902 }
1903 break;
1904
e0c6ed95 1905 case '[': /* These must match exactly. */
252b5132
RH		 1906 case ']':
1907 case ',':
1908 case ' ':
1909 if (*s++ == *args)
1910 continue;
1911 break;
1912
e0c6ed95 1913 case '#': /* Must be at least one digit. */
3882b010 1914 if (ISDIGIT (*s++))
252b5132 1915 {
3882b010 1916 while (ISDIGIT (*s))
252b5132
RH		 1917 {
1918 ++s;
1919 }
1920 continue;
1921 }
1922 break;
1923
e0c6ed95 1924 case 'C': /* Coprocessor state register. */
252b5132
RH		 1925 if (strncmp (s, "%csr", 4) == 0)
1926 {
1927 s += 4;
1928 continue;
1929 }
1930 break;
1931
e0c6ed95 1932 case 'b': /* Next operand is a coprocessor register. */
252b5132
RH		 1933 case 'c':
1934 case 'D':
3882b010 1935 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
252b5132
RH		 1936 {
1937 mask = *s++;
3882b010 1938 if (ISDIGIT (*s))
252b5132
RH		 1939 {
1940 mask = 10 * (mask - '0') + (*s++ - '0');
1941 if (mask >= 32)
1942 {
1943 break;
1944 }
1945 }
1946 else
1947 {
1948 mask -= '0';
1949 }
1950 switch (*args)
1951 {
1952
1953 case 'b':
1954 opcode |= mask << 14;
1955 continue;
1956
1957 case 'c':
1958 opcode |= mask;
1959 continue;
1960
1961 case 'D':
1962 opcode |= mask << 25;
1963 continue;
1964 }
1965 }
1966 break;
1967
1968 case 'r': /* next operand must be a register */
1969 case 'O':
1970 case '1':
1971 case '2':
1972 case 'd':
1973 if (*s++ == '%')
1974 {
1975 switch (c = *s++)
1976 {
1977
1978 case 'f': /* frame pointer */
1979 if (*s++ == 'p')
1980 {
1981 mask = 0x1e;
1982 break;
1983 }
1984 goto error;
1985
1986 case 'g': /* global register */
a22b281c
RH		 1987 c = *s++;
1988 if (isoctal (c))
252b5132
RH		 1989 {
1990 mask = c - '0';
1991 break;
1992 }
1993 goto error;
1994
1995 case 'i': /* in register */
a22b281c
RH		 1996 c = *s++;
1997 if (isoctal (c))
252b5132
RH		 1998 {
1999 mask = c - '0' + 24;
2000 break;
2001 }
2002 goto error;
2003
2004 case 'l': /* local register */
a22b281c
RH		 2005 c = *s++;
2006 if (isoctal (c))
252b5132
RH		 2007 {
2008 mask = (c - '0' + 16);
2009 break;
2010 }
2011 goto error;
2012
2013 case 'o': /* out register */
a22b281c
RH		 2014 c = *s++;
2015 if (isoctal (c))
252b5132
RH		 2016 {
2017 mask = (c - '0' + 8);
2018 break;
2019 }
2020 goto error;
2021
2022 case 's': /* stack pointer */
2023 if (*s++ == 'p')
2024 {
2025 mask = 0xe;
2026 break;
2027 }
2028 goto error;
2029
2030 case 'r': /* any register */
3882b010 2031 if (!ISDIGIT ((c = *s++)))
252b5132
RH		 2032 {
2033 goto error;
2034 }
2035 /* FALLTHROUGH */
2036 case '0':
2037 case '1':
2038 case '2':
2039 case '3':
2040 case '4':
2041 case '5':
2042 case '6':
2043 case '7':
2044 case '8':
2045 case '9':
3882b010 2046 if (ISDIGIT (*s))
252b5132
RH		 2047 {
2048 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2049 {
2050 goto error;
2051 }
2052 }
2053 else
2054 {
2055 c -= '0';
2056 }
2057 mask = c;
2058 break;
2059
2060 default:
2061 goto error;
2062 }
2063
6d8809aa 2064 if ((mask & ~1) == 2 && sparc_arch_size == 64
e0c6ed95 2065 && no_undeclared_regs && ! globals[mask])
79bd78be 2066 as_bad (_("detected global register use not covered by .register pseudo-op"));
6d8809aa 2067
252b5132
RH		 2068 /* Got the register, now figure out where
2069 it goes in the opcode. */
2070 switch (*args)
2071 {
2072 case '1':
2073 opcode |= mask << 14;
2074 continue;
2075
2076 case '2':
2077 opcode |= mask;
2078 continue;
2079
2080 case 'd':
2081 opcode |= mask << 25;
2082 continue;
2083
2084 case 'r':
2085 opcode |= (mask << 25) | (mask << 14);
2086 continue;
2087
2088 case 'O':
2089 opcode |= (mask << 25) | (mask << 0);
2090 continue;
2091 }
2092 }
2093 break;
2094
2095 case 'e': /* next operand is a floating point register */
2096 case 'v':
2097 case 'V':
2098
2099 case 'f':
2100 case 'B':
2101 case 'R':
2102
2103 case 'g':
2104 case 'H':
2105 case 'J':
2106 {
2107 char format;
2108
2109 if (*s++ == '%'
2110 && ((format = *s) == 'f')
3882b010 2111 && ISDIGIT (*++s))
252b5132 2112 {
3882b010 2113 for (mask = 0; ISDIGIT (*s); ++s)
252b5132
RH		 2114 {
2115 mask = 10 * mask + (*s - '0');
2116 } /* read the number */
2117
2118 if ((*args == 'v'
2119 || *args == 'B'
2120 || *args == 'H')
2121 && (mask & 1))
2122 {
2123 break;
2124 } /* register must be even numbered */
2125
2126 if ((*args == 'V'
2127 || *args == 'R'
2128 || *args == 'J')
2129 && (mask & 3))
2130 {
2131 break;
2132 } /* register must be multiple of 4 */
2133
2134 if (mask >= 64)
2135 {
2136 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2137 error_message = _(": There are only 64 f registers; [0-63]");
2138 else
2139 error_message = _(": There are only 32 f registers; [0-31]");
2140 goto error;
2141 } /* on error */
2142 else if (mask >= 32)
2143 {
2144 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2145 {
2146 v9_arg_p = 1;
2147 mask -= 31; /* wrap high bit */
2148 }
2149 else
2150 {
2151 error_message = _(": There are only 32 f registers; [0-31]");
2152 goto error;
2153 }
2154 }
2155 }
2156 else
2157 {
2158 break;
ab3e48dc 2159 } /* if not an 'f' register. */
252b5132
RH		 2160
2161 switch (*args)
2162 {
2163 case 'v':
2164 case 'V':
2165 case 'e':
2166 opcode |= RS1 (mask);
2167 continue;
2168
252b5132
RH		 2169 case 'f':
2170 case 'B':
2171 case 'R':
2172 opcode |= RS2 (mask);
2173 continue;
2174
2175 case 'g':
2176 case 'H':
2177 case 'J':
2178 opcode |= RD (mask);
2179 continue;
ab3e48dc 2180 } /* Pack it in. */
252b5132
RH		 2181
2182 know (0);
2183 break;
ab3e48dc 2184 } /* float arg */
252b5132
RH		 2185
2186 case 'F':
2187 if (strncmp (s, "%fsr", 4) == 0)
2188 {
2189 s += 4;
2190 continue;
2191 }
2192 break;
2193
ab3e48dc
KH		 2194 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2195 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
252b5132
RH		 2196 goto immediate;
2197
ab3e48dc 2198 case 'l': /* 22 bit PC relative immediate */
252b5132
RH		 2199 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2200 the_insn.pcrel = 1;
2201 goto immediate;
2202
ab3e48dc 2203 case 'L': /* 30 bit immediate */
252b5132
RH		 2204 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2205 the_insn.pcrel = 1;
2206 goto immediate;
2207
63fab58c 2208 case 'h':
ab3e48dc 2209 case 'n': /* 22 bit immediate */
252b5132
RH		 2210 the_insn.reloc = BFD_RELOC_SPARC22;
2211 goto immediate;
2212
ab3e48dc 2213 case 'i': /* 13 bit immediate */
252b5132
RH		 2214 the_insn.reloc = BFD_RELOC_SPARC13;
2215
2216 /* fallthrough */
2217
2218 immediate:
2219 if (*s == ' ')
2220 s++;
2221
cf9a1301
RH		 2222 {
2223 char *s1;
2224 char *op_arg = NULL;
2225 expressionS op_exp;
2226 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2227
2228 /* Check for %hi, etc. */
2229 if (*s == '%')
2230 {
2231 static const struct ops {
2232 /* The name as it appears in assembler. */
2233 char *name;
2234 /* strlen (name), precomputed for speed */
2235 int len;
2236 /* The reloc this pseudo-op translates to. */
2237 int reloc;
2238 /* Non-zero if for v9 only. */
2239 int v9_p;
2240 /* Non-zero if can be used in pc-relative contexts. */
2241 int pcrel_p;/*FIXME:wip*/
2242 } ops[] = {
2243 /* hix/lox must appear before hi/lo so %hix won't be
2244 mistaken for %hi. */
2245 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2246 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2247 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2248 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2249 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2250 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2251 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2252 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2253 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2254 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2255 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2256 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
b9734f35
JJ		 2257 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2258 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2259 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2260 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2261 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2262 0 },
2263 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2264 0 },
2265 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2266 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2267 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2268 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
c2158c24 2269 { NULL, 0, 0, 0, 0 }
cf9a1301
RH		 2270 };
2271 const struct ops *o;
e0c6ed95 2272
cf9a1301
RH		 2273 for (o = ops; o->name; o++)
2274 if (strncmp (s + 1, o->name, o->len) == 0)
2275 break;
2276 if (o->name == NULL)
252b5132 2277 break;
e0c6ed95 2278
cf9a1301
RH		 2279 if (s[o->len + 1] != '(')
2280 {
2281 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
a22b281c 2282 return special_case;
cf9a1301 2283 }
252b5132 2284
cf9a1301
RH		 2285 op_arg = o->name;
2286 the_insn.reloc = o->reloc;
2287 s += o->len + 2;
2288 v9_arg_p = o->v9_p;
2289 }
2290
2291 /* Note that if the get_expression() fails, we will still
2292 have created U entries in the symbol table for the
2293 'symbols' in the input string. Try not to create U
2294 symbols for registers, etc. */
252b5132 2295
252b5132
RH		 2296 /* This stuff checks to see if the expression ends in
2297 +%reg. If it does, it removes the register from
2298 the expression, and re-sets 's' to point to the
2299 right place. */
2300
cf9a1301
RH		 2301 if (op_arg)
2302 {
2303 int npar = 0;
2304
2305 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2306 if (*s1 == '(')
2307 npar++;
2308 else if (*s1 == ')')
2309 {
2310 if (!npar)
2311 break;
2312 npar--;
2313 }
2314
2315 if (*s1 != ')')
2316 {
2317 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
a22b281c 2318 return special_case;
cf9a1301 2319 }
e0c6ed95 2320
cf9a1301
RH		 2321 *s1 = '\0';
2322 (void) get_expression (s);
2323 *s1 = ')';
2324 s = s1 + 1;
2325 if (*s == ',' || *s == ']' || !*s)
2326 continue;
2327 if (*s != '+' && *s != '-')
2328 {
2329 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
a22b281c 2330 return special_case;
cf9a1301
RH		 2331 }
2332 *s1 = '0';
2333 s = s1;
2334 op_exp = the_insn.exp;
e0c6ed95 2335 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
cf9a1301 2336 }
252b5132 2337
e0c6ed95
AM		 2338 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2339 ;
252b5132 2340
3882b010 2341 if (s1 != s && ISDIGIT (s1[-1]))
252b5132
RH		 2342 {
2343 if (s1[-2] == '%' && s1[-3] == '+')
cf9a1301
RH		 2344 s1 -= 3;
2345 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2346 s1 -= 4;
2347 else
2348 s1 = NULL;
2349 if (s1)
252b5132 2350 {
252b5132 2351 *s1 = '\0';
1eb7027c
RH		 2352 if (op_arg && s1 == s + 1)
2353 the_insn.exp.X_op = O_absent;
2354 else
2355 (void) get_expression (s);
252b5132 2356 *s1 = '+';
cf9a1301
RH		 2357 if (op_arg)
2358 *s = ')';
252b5132 2359 s = s1;
252b5132 2360 }
cf9a1301
RH		 2361 }
2362 else
2363 s1 = NULL;
2364
2365 if (!s1)
2366 {
2367 (void) get_expression (s);
2368 if (op_arg)
2369 *s = ')';
2370 s = expr_end;
2371 }
2372
2373 if (op_arg)
2374 {
2375 the_insn.exp2 = the_insn.exp;
2376 the_insn.exp = op_exp;
2377 if (the_insn.exp2.X_op == O_absent)
2378 the_insn.exp2.X_op = O_illegal;
2379 else if (the_insn.exp.X_op == O_absent)
252b5132 2380 {
cf9a1301
RH		 2381 the_insn.exp = the_insn.exp2;
2382 the_insn.exp2.X_op = O_illegal;
2383 }
2384 else if (the_insn.exp.X_op == O_constant)
2385 {
2386 valueT val = the_insn.exp.X_add_number;
2387 switch (the_insn.reloc)
2388 {
1b50c718
ILT		 2389 default:
2390 break;
2391
cf9a1301
RH		 2392 case BFD_RELOC_SPARC_HH22:
2393 val = BSR (val, 32);
e0c6ed95 2394 /* Fall through. */
cf9a1301
RH		 2395
2396 case BFD_RELOC_SPARC_LM22:
2397 case BFD_RELOC_HI22:
2398 val = (val >> 10) & 0x3fffff;
2399 break;
2400
2401 case BFD_RELOC_SPARC_HM10:
2402 val = BSR (val, 32);
e0c6ed95 2403 /* Fall through. */
cf9a1301
RH		 2404
2405 case BFD_RELOC_LO10:
2406 val &= 0x3ff;
2407 break;
2408
2409 case BFD_RELOC_SPARC_H44:
2410 val >>= 22;
2411 val &= 0x3fffff;
2412 break;
2413
2414 case BFD_RELOC_SPARC_M44:
2415 val >>= 12;
2416 val &= 0x3ff;
2417 break;
2418
2419 case BFD_RELOC_SPARC_L44:
2420 val &= 0xfff;
2421 break;
2422
2423 case BFD_RELOC_SPARC_HIX22:
ab3e48dc 2424 val = ~val;
cf9a1301
RH		 2425 val = (val >> 10) & 0x3fffff;
2426 break;
2427
2428 case BFD_RELOC_SPARC_LOX10:
2429 val = (val & 0x3ff) | 0x1c00;
2430 break;
2431 }
2432 the_insn.exp = the_insn.exp2;
2433 the_insn.exp.X_add_number += val;
2434 the_insn.exp2.X_op = O_illegal;
2435 the_insn.reloc = old_reloc;
2436 }
2437 else if (the_insn.exp2.X_op != O_constant)
2438 {
2439 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
a22b281c 2440 return special_case;
cf9a1301
RH		 2441 }
2442 else
2443 {
dabe3bbc 2444 if (old_reloc != BFD_RELOC_SPARC13
cf9a1301
RH		 2445 || the_insn.reloc != BFD_RELOC_LO10
2446 || sparc_arch_size != 64
2447 || sparc_pic_code)
2448 {
2449 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
a22b281c 2450 return special_case;
cf9a1301
RH		 2451 }
2452 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
252b5132
RH		 2453 }
2454 }
2455 }
252b5132
RH		 2456 /* Check for constants that don't require emitting a reloc. */
2457 if (the_insn.exp.X_op == O_constant
2458 && the_insn.exp.X_add_symbol == 0
2459 && the_insn.exp.X_op_symbol == 0)
2460 {
2461 /* For pc-relative call instructions, we reject
2462 constants to get better code. */
2463 if (the_insn.pcrel
2464 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2465 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2466 {
2467 error_message = _(": PC-relative operand can't be a constant");
2468 goto error;
2469 }
2470
b9734f35
JJ		 2471 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2472 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2473 {
2474 error_message = _(": TLS operand can't be a constant");
2475 goto error;
2476 }
2477
252b5132
RH		 2478 /* Constants that won't fit are checked in md_apply_fix3
2479 and bfd_install_relocation.
2480 ??? It would be preferable to install the constants
2481 into the insn here and save having to create a fixS
2482 for each one. There already exists code to handle
2483 all the various cases (e.g. in md_apply_fix3 and
2484 bfd_install_relocation) so duplicating all that code
2485 here isn't right. */
2486 }
2487
2488 continue;
2489
2490 case 'a':
2491 if (*s++ == 'a')
2492 {
2493 opcode |= ANNUL;
2494 continue;
2495 }
2496 break;
2497
2498 case 'A':
2499 {
2500 int asi = 0;
2501
2502 /* Parse an asi. */
2503 if (*s == '#')
2504 {
2505 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2506 {
2507 error_message = _(": invalid ASI name");
2508 goto error;
2509 }
2510 }
2511 else
2512 {
2513 if (! parse_const_expr_arg (&s, &asi))
2514 {
2515 error_message = _(": invalid ASI expression");
2516 goto error;
2517 }
2518 if (asi < 0 || asi > 255)
2519 {
2520 error_message = _(": invalid ASI number");
2521 goto error;
2522 }
2523 }
2524 opcode |= ASI (asi);
2525 continue;
e0c6ed95 2526 } /* Alternate space. */
252b5132
RH		 2527
2528 case 'p':
2529 if (strncmp (s, "%psr", 4) == 0)
2530 {
2531 s += 4;
2532 continue;
2533 }
2534 break;
2535
e0c6ed95 2536 case 'q': /* Floating point queue. */
252b5132
RH		 2537 if (strncmp (s, "%fq", 3) == 0)
2538 {
2539 s += 3;
2540 continue;
2541 }
2542 break;
2543
e0c6ed95 2544 case 'Q': /* Coprocessor queue. */
252b5132
RH		 2545 if (strncmp (s, "%cq", 3) == 0)
2546 {
2547 s += 3;
2548 continue;
2549 }
2550 break;
2551
2552 case 'S':
2553 if (strcmp (str, "set") == 0
2554 || strcmp (str, "setuw") == 0)
2555 {
2556 special_case = SPECIAL_CASE_SET;
2557 continue;
2558 }
2559 else if (strcmp (str, "setsw") == 0)
2560 {
2561 special_case = SPECIAL_CASE_SETSW;
2562 continue;
2563 }
2564 else if (strcmp (str, "setx") == 0)
2565 {
2566 special_case = SPECIAL_CASE_SETX;
2567 continue;
2568 }
2569 else if (strncmp (str, "fdiv", 4) == 0)
2570 {
2571 special_case = SPECIAL_CASE_FDIV;
2572 continue;
2573 }
2574 break;
2575
2576 case 'o':
2577 if (strncmp (s, "%asi", 4) != 0)
2578 break;
2579 s += 4;
2580 continue;
2581
2582 case 's':
2583 if (strncmp (s, "%fprs", 5) != 0)
2584 break;
2585 s += 5;
2586 continue;
2587
2588 case 'E':
2589 if (strncmp (s, "%ccr", 4) != 0)
2590 break;
2591 s += 4;
2592 continue;
2593
2594 case 't':
2595 if (strncmp (s, "%tbr", 4) != 0)
2596 break;
2597 s += 4;
2598 continue;
2599
2600 case 'w':
2601 if (strncmp (s, "%wim", 4) != 0)
2602 break;
2603 s += 4;
2604 continue;
2605
2606 case 'x':
2607 {
2608 char *push = input_line_pointer;
2609 expressionS e;
2610
2611 input_line_pointer = s;
2612 expression (&e);
2613 if (e.X_op == O_constant)
2614 {
2615 int n = e.X_add_number;
2616 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2617 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2618 else
2619 opcode |= e.X_add_number << 5;
2620 }
2621 else
2622 as_bad (_("non-immediate OPF operand, ignored"));
2623 s = input_line_pointer;
2624 input_line_pointer = push;
2625 continue;
2626 }
2627
2628 case 'y':
2629 if (strncmp (s, "%y", 2) != 0)
2630 break;
2631 s += 2;
2632 continue;
2633
2634 case 'u':
2635 case 'U':
2636 {
2637 /* Parse a sparclet cpreg. */
2638 int cpreg;
2639 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2640 {
2641 error_message = _(": invalid cpreg name");
2642 goto error;
2643 }
2644 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2645 continue;
2646 }
2647
2648 default:
2649 as_fatal (_("failed sanity check."));
e0c6ed95 2650 } /* switch on arg code. */
252b5132
RH		 2651
2652 /* Break out of for() loop. */
2653 break;
e0c6ed95 2654 } /* For each arg that we expect. */
252b5132
RH		 2655
2656 error:
2657 if (match == 0)
2658 {
e0c6ed95 2659 /* Args don't match. */
252b5132
RH		 2660 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2661 && (insn->name == insn[1].name
2662 || !strcmp (insn->name, insn[1].name)))
2663 {
2664 ++insn;
2665 s = argsStart;
2666 continue;
2667 }
2668 else
2669 {
2670 as_bad (_("Illegal operands%s"), error_message);
a22b281c 2671 return special_case;
252b5132
RH		 2672 }
2673 }
2674 else
2675 {
e0c6ed95 2676 /* We have a match. Now see if the architecture is OK. */
252b5132
RH		 2677 int needed_arch_mask = insn->architecture;
2678
2679 if (v9_arg_p)
2680 {
19f7b010
JJ		 2681 needed_arch_mask &=
2682 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2683 if (! needed_arch_mask)
2684 needed_arch_mask =
2685 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
252b5132
RH		 2686 }
2687
e0c6ed95
AM		 2688 if (needed_arch_mask
2689 & SPARC_OPCODE_SUPPORTED (current_architecture))
2690 /* OK. */
2691 ;
252b5132 2692 /* Can we bump up the architecture? */
e0c6ed95
AM		 2693 else if (needed_arch_mask
2694 & SPARC_OPCODE_SUPPORTED (max_architecture))
252b5132
RH		 2695 {
2696 enum sparc_opcode_arch_val needed_architecture =
2697 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2698 & needed_arch_mask);
2699
2700 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2701 if (warn_on_bump
2702 && needed_architecture > warn_after_architecture)
2703 {
2704 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2705 sparc_opcode_archs[current_architecture].name,
2706 sparc_opcode_archs[needed_architecture].name,
2707 str);
2708 warn_after_architecture = needed_architecture;
2709 }
2710 current_architecture = needed_architecture;
2711 }
2712 /* Conflict. */
2713 /* ??? This seems to be a bit fragile. What if the next entry in
2714 the opcode table is the one we want and it is supported?
2715 It is possible to arrange the table today so that this can't
2716 happen but what about tomorrow? */
2717 else
2718 {
e0c6ed95 2719 int arch, printed_one_p = 0;
252b5132
RH		 2720 char *p;
2721 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2722
2723 /* Create a list of the architectures that support the insn. */
e0c6ed95 2724 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
252b5132
RH		 2725 p = required_archs;
2726 arch = sparc_ffs (needed_arch_mask);
2727 while ((1 << arch) <= needed_arch_mask)
2728 {
2729 if ((1 << arch) & needed_arch_mask)
2730 {
2731 if (printed_one_p)
2732 *p++ = '|';
2733 strcpy (p, sparc_opcode_archs[arch].name);
2734 p += strlen (p);
2735 printed_one_p = 1;
2736 }
2737 ++arch;
2738 }
2739
2740 as_bad (_("Architecture mismatch on \"%s\"."), str);
2741 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2742 required_archs,
2743 sparc_opcode_archs[max_architecture].name);
a22b281c 2744 return special_case;
252b5132 2745 }
e0c6ed95 2746 } /* If no match. */
252b5132
RH		 2747
2748 break;
e0c6ed95 2749 } /* Forever looking for a match. */
252b5132
RH		 2750
2751 the_insn.opcode = opcode;
a22b281c 2752 return special_case;
252b5132
RH		 2753}
2754
2755/* Parse an argument that can be expressed as a keyword.
2756 (eg: #StoreStore or %ccfr).
2757 The result is a boolean indicating success.
2758 If successful, INPUT_POINTER is updated. */
2759
2760static int
2761parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2762 int (*lookup_fn) PARAMS ((const char *));
2763 char **input_pointerP;
2764 int *valueP;
2765{
2766 int value;
2767 char c, *p, *q;
2768
2769 p = *input_pointerP;
2770 for (q = p + (*p == '#' || *p == '%');
3882b010 2771 ISALNUM (*q) || *q == '_';
252b5132
RH		 2772 ++q)
2773 continue;
2774 c = *q;
2775 *q = 0;
2776 value = (*lookup_fn) (p);
2777 *q = c;
2778 if (value == -1)
2779 return 0;
2780 *valueP = value;
2781 *input_pointerP = q;
2782 return 1;
2783}
2784
2785/* Parse an argument that is a constant expression.
2786 The result is a boolean indicating success. */
2787
2788static int
2789parse_const_expr_arg (input_pointerP, valueP)
2790 char **input_pointerP;
2791 int *valueP;
2792{
2793 char *save = input_line_pointer;
2794 expressionS exp;
2795
2796 input_line_pointer = *input_pointerP;
2797 /* The next expression may be something other than a constant
2798 (say if we're not processing the right variant of the insn).
2799 Don't call expression unless we're sure it will succeed as it will
2800 signal an error (which we want to defer until later). */
2801 /* FIXME: It might be better to define md_operand and have it recognize
2802 things like %asi, etc. but continuing that route through to the end
2803 is a lot of work. */
2804 if (*input_line_pointer == '%')
2805 {
2806 input_line_pointer = save;
2807 return 0;
2808 }
2809 expression (&exp);
2810 *input_pointerP = input_line_pointer;
2811 input_line_pointer = save;
2812 if (exp.X_op != O_constant)
2813 return 0;
2814 *valueP = exp.X_add_number;
2815 return 1;
2816}
2817
2818/* Subroutine of sparc_ip to parse an expression. */
2819
2820static int
2821get_expression (str)
2822 char *str;
2823{
2824 char *save_in;
2825 segT seg;
2826
2827 save_in = input_line_pointer;
2828 input_line_pointer = str;
2829 seg = expression (&the_insn.exp);
2830 if (seg != absolute_section
2831 && seg != text_section
2832 && seg != data_section
2833 && seg != bss_section
2834 && seg != undefined_section)
2835 {
2836 the_insn.error = _("bad segment");
2837 expr_end = input_line_pointer;
2838 input_line_pointer = save_in;
2839 return 1;
2840 }
2841 expr_end = input_line_pointer;
2842 input_line_pointer = save_in;
2843 return 0;
2844}
2845
2846/* Subroutine of md_assemble to output one insn. */
2847
2848static void
2849output_insn (insn, the_insn)
2850 const struct sparc_opcode *insn;
2851 struct sparc_it *the_insn;
2852{
2853 char *toP = frag_more (4);
2854
e0c6ed95 2855 /* Put out the opcode. */
252b5132
RH		 2856 if (INSN_BIG_ENDIAN)
2857 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2858 else
2859 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2860
e0c6ed95 2861 /* Put out the symbol-dependent stuff. */
252b5132
RH		 2862 if (the_insn->reloc != BFD_RELOC_NONE)
2863 {
e0c6ed95
AM		 2864 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2865 (toP - frag_now->fr_literal), /* Where. */
2866 4, /* Size. */
252b5132
RH		 2867 &the_insn->exp,
2868 the_insn->pcrel,
2869 the_insn->reloc);
2870 /* Turn off overflow checking in fixup_segment. We'll do our
2871 own overflow checking in md_apply_fix3. This is necessary because
2872 the insn size is 4 and fixup_segment will signal an overflow for
2873 large 8 byte quantities. */
2874 fixP->fx_no_overflow = 1;
dabe3bbc
RH		 2875 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2876 fixP->tc_fix_data = the_insn->exp2.X_add_number;
252b5132
RH		 2877 }
2878
2879 last_insn = insn;
2880 last_opcode = the_insn->opcode;
732d96b6
JJ		 2881
2882#ifdef OBJ_ELF
2883 dwarf2_emit_insn (4);
2884#endif
252b5132
RH		 2885}
2886\f
e0c6ed95
AM		 2887/* This is identical to the md_atof in m68k.c. I think this is right,
2888 but I'm not sure.
252b5132 2889
e0c6ed95
AM		 2890 Turn a string in input_line_pointer into a floating point constant
2891 of type TYPE, and store the appropriate bytes in *LITP. The number
2892 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2893 returned, or NULL on OK. */
252b5132 2894
e0c6ed95 2895/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 2896#define MAX_LITTLENUMS 6
2897
2898char *
2899md_atof (type, litP, sizeP)
2900 char type;
2901 char *litP;
2902 int *sizeP;
2903{
e0c6ed95 2904 int i, prec;
252b5132
RH		 2905 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2906 char *t;
2907
2908 switch (type)
2909 {
2910 case 'f':
2911 case 'F':
2912 case 's':
2913 case 'S':
2914 prec = 2;
2915 break;
2916
2917 case 'd':
2918 case 'D':
2919 case 'r':
2920 case 'R':
2921 prec = 4;
2922 break;
2923
2924 case 'x':
2925 case 'X':
2926 prec = 6;
2927 break;
2928
2929 case 'p':
2930 case 'P':
2931 prec = 6;
2932 break;
2933
2934 default:
2935 *sizeP = 0;
2936 return _("Bad call to MD_ATOF()");
2937 }
2938
2939 t = atof_ieee (input_line_pointer, type, words);
2940 if (t)
2941 input_line_pointer = t;
2942 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2943
2944 if (target_big_endian)
2945 {
2946 for (i = 0; i < prec; i++)
2947 {
ab3e48dc
KH		 2948 md_number_to_chars (litP, (valueT) words[i],
2949 sizeof (LITTLENUM_TYPE));
252b5132
RH		 2950 litP += sizeof (LITTLENUM_TYPE);
2951 }
2952 }
2953 else
2954 {
2955 for (i = prec - 1; i >= 0; i--)
2956 {
ab3e48dc
KH		 2957 md_number_to_chars (litP, (valueT) words[i],
2958 sizeof (LITTLENUM_TYPE));
252b5132
RH		 2959 litP += sizeof (LITTLENUM_TYPE);
2960 }
2961 }
e0c6ed95 2962
252b5132
RH		 2963 return 0;
2964}
2965
2966/* Write a value out to the object file, using the appropriate
2967 endianness. */
2968
2969void
2970md_number_to_chars (buf, val, n)
2971 char *buf;
2972 valueT val;
2973 int n;
2974{
2975 if (target_big_endian)
2976 number_to_chars_bigendian (buf, val, n);
2977 else if (target_little_endian_data
2978 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
e0c6ed95
AM		 2979 /* Output debug words, which are not in allocated sections, as big
2980 endian. */
252b5132
RH		 2981 number_to_chars_bigendian (buf, val, n);
2982 else if (target_little_endian_data || ! target_big_endian)
2983 number_to_chars_littleendian (buf, val, n);
2984}
2985\f
2986/* Apply a fixS to the frags, now that we know the value it ought to
81d4177b 2987 hold. */
252b5132 2988
94f592af
NC		 2989void
2990md_apply_fix3 (fixP, valP, segment)
252b5132 2991 fixS *fixP;
94f592af 2992 valueT *valP;
a7982600 2993 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 2994{
2995 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
94f592af 2996 offsetT val = * (offsetT *) valP;
252b5132
RH		 2997 long insn;
2998
252b5132
RH		 2999 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3000
e0c6ed95 3001 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 3002
3003#ifdef OBJ_ELF
a161fe53 3004 /* SPARC ELF relocations don't use an addend in the data field. */
252b5132 3005 if (fixP->fx_addsy != NULL)
a161fe53 3006 return;
252b5132
RH		 3007#endif
3008
3009 /* This is a hack. There should be a better way to
3010 handle this. Probably in terms of howto fields, once
3011 we can look at these fixups in terms of howtos. */
3012 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3013 val += fixP->fx_where + fixP->fx_frag->fr_address;
3014
3015#ifdef OBJ_AOUT
3016 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3017 generate a reloc, then we just want to let the reloc addend set
3018 the value. We do not want to also stuff the addend into the
3019 object file. Including the addend in the object file works when
3020 doing a static link, because the linker will ignore the object
3021 file contents. However, the dynamic linker does not ignore the
3022 object file contents. */
3023 if (fixP->fx_addsy != NULL
3024 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3025 val = 0;
3026
3027 /* When generating PIC code, we do not want an addend for a reloc
3028 against a local symbol. We adjust fx_addnumber to cancel out the
3029 value already included in val, and to also cancel out the
3030 adjustment which bfd_install_relocation will create. */
3031 if (sparc_pic_code
3032 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3033 && fixP->fx_addsy != NULL
3034 && ! S_IS_COMMON (fixP->fx_addsy)
49309057 3035 && symbol_section_p (fixP->fx_addsy))
252b5132
RH		 3036 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3037
3038 /* When generating PIC code, we need to fiddle to get
3039 bfd_install_relocation to do the right thing for a PC relative
3040 reloc against a local symbol which we are going to keep. */
3041 if (sparc_pic_code
3042 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3043 && fixP->fx_addsy != NULL
3044 && (S_IS_EXTERNAL (fixP->fx_addsy)
3045 || S_IS_WEAK (fixP->fx_addsy))
3046 && S_IS_DEFINED (fixP->fx_addsy)
3047 && ! S_IS_COMMON (fixP->fx_addsy))
3048 {
3049 val = 0;
3050 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3051 }
3052#endif
3053
3054 /* If this is a data relocation, just output VAL. */
3055
0f2712ed
NC		 3056 if (fixP->fx_r_type == BFD_RELOC_16
3057 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
252b5132
RH		 3058 {
3059 md_number_to_chars (buf, val, 2);
3060 }
3061 else if (fixP->fx_r_type == BFD_RELOC_32
0f2712ed 3062 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
252b5132
RH		 3063 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3064 {
3065 md_number_to_chars (buf, val, 4);
3066 }
0f2712ed
NC		 3067 else if (fixP->fx_r_type == BFD_RELOC_64
3068 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
252b5132
RH		 3069 {
3070 md_number_to_chars (buf, val, 8);
3071 }
e0c6ed95 3072 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
252b5132
RH		 3073 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3074 {
3075 fixP->fx_done = 0;
94f592af 3076 return;
252b5132
RH		 3077 }
3078 else
3079 {
3080 /* It's a relocation against an instruction. */
3081
3082 if (INSN_BIG_ENDIAN)
3083 insn = bfd_getb32 ((unsigned char *) buf);
3084 else
3085 insn = bfd_getl32 ((unsigned char *) buf);
e0c6ed95 3086
252b5132
RH		 3087 switch (fixP->fx_r_type)
3088 {
3089 case BFD_RELOC_32_PCREL_S2:
3090 val = val >> 2;
3091 /* FIXME: This increment-by-one deserves a comment of why it's
3092 being done! */
3093 if (! sparc_pic_code
3094 || fixP->fx_addsy == NULL
49309057 3095 || symbol_section_p (fixP->fx_addsy))
252b5132 3096 ++val;
6faf3d66 3097
252b5132 3098 insn |= val & 0x3fffffff;
6faf3d66 3099
e0c6ed95 3100 /* See if we have a delay slot. */
6faf3d66
JJ		 3101 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3102 {
3103#define G0 0
3104#define O7 15
3105#define XCC (2 << 20)
3106#define COND(x) (((x)&0xf)<<25)
3107#define CONDA COND(0x8)
3108#define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3109#define INSN_BA (F2(0,2) | CONDA)
3110#define INSN_OR F3(2, 0x2, 0)
3111#define INSN_NOP F2(0,4)
3112
3113 long delay;
3114
3115 /* If the instruction is a call with either:
3116 restore
3117 arithmetic instruction with rd == %o7
3118 where rs1 != %o7 and rs2 if it is register != %o7
3119 then we can optimize if the call destination is near
3120 by changing the call into a branch always. */
3121 if (INSN_BIG_ENDIAN)
3122 delay = bfd_getb32 ((unsigned char *) buf + 4);
3123 else
3124 delay = bfd_getl32 ((unsigned char *) buf + 4);
e0c6ed95 3125 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
6faf3d66 3126 break;
e0c6ed95
AM		 3127 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3128 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3129 || ((delay & RD (~0)) != RD (O7))))
6faf3d66 3130 break;
e0c6ed95
AM		 3131 if ((delay & RS1 (~0)) == RS1 (O7)
3132 || ((delay & F3I (~0)) == 0
3133 && (delay & RS2 (~0)) == RS2 (O7)))
6faf3d66
JJ		 3134 break;
3135 /* Ensure the branch will fit into simm22. */
3136 if ((val & 0x3fe00000)
3137 && (val & 0x3fe00000) != 0x3fe00000)
3138 break;
3139 /* Check if the arch is v9 and branch will fit
3140 into simm19. */
3141 if (((val & 0x3c0000) == 0
3142 || (val & 0x3c0000) == 0x3c0000)
3143 && (sparc_arch_size == 64
3144 || current_architecture >= SPARC_OPCODE_ARCH_V9))
e0c6ed95 3145 /* ba,pt %xcc */
6faf3d66
JJ		 3146 insn = INSN_BPA | (val & 0x7ffff);
3147 else
e0c6ed95 3148 /* ba */
6faf3d66
JJ		 3149 insn = INSN_BA | (val & 0x3fffff);
3150 if (fixP->fx_where >= 4
e0c6ed95
AM		 3151 && ((delay & (0xffffffff ^ RS1 (~0)))
3152 == (INSN_OR | RD (O7) | RS2 (G0))))
6faf3d66
JJ		 3153 {
3154 long setter;
3155 int reg;
3156
3157 if (INSN_BIG_ENDIAN)
3158 setter = bfd_getb32 ((unsigned char *) buf - 4);
3159 else
3160 setter = bfd_getl32 ((unsigned char *) buf - 4);
e0c6ed95 3161 if ((setter & (0xffffffff ^ RD (~0)))
ab3e48dc 3162 != (INSN_OR | RS1 (O7) | RS2 (G0)))
6faf3d66
JJ		 3163 break;
3164 /* The sequence was
3165 or %o7, %g0, %rN
3166 call foo
3167 or %rN, %g0, %o7
3168
3169 If call foo was replaced with ba, replace
3170 or %rN, %g0, %o7 with nop. */
e0c6ed95
AM		 3171 reg = (delay & RS1 (~0)) >> 14;
3172 if (reg != ((setter & RD (~0)) >> 25)
6faf3d66
JJ		 3173 || reg == G0 || reg == O7)
3174 break;
3175
3176 if (INSN_BIG_ENDIAN)
3177 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3178 else
3179 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3180 }
3181 }
252b5132
RH		 3182 break;
3183
3184 case BFD_RELOC_SPARC_11:
3185 if (! in_signed_range (val, 0x7ff))
3186 as_bad_where (fixP->fx_file, fixP->fx_line,
3187 _("relocation overflow"));
3188 insn |= val & 0x7ff;
3189 break;
3190
3191 case BFD_RELOC_SPARC_10:
3192 if (! in_signed_range (val, 0x3ff))
3193 as_bad_where (fixP->fx_file, fixP->fx_line,
3194 _("relocation overflow"));
3195 insn |= val & 0x3ff;
3196 break;
3197
3198 case BFD_RELOC_SPARC_7:
3199 if (! in_bitfield_range (val, 0x7f))
3200 as_bad_where (fixP->fx_file, fixP->fx_line,
3201 _("relocation overflow"));
3202 insn |= val & 0x7f;
3203 break;
3204
3205 case BFD_RELOC_SPARC_6:
3206 if (! in_bitfield_range (val, 0x3f))
3207 as_bad_where (fixP->fx_file, fixP->fx_line,
3208 _("relocation overflow"));
3209 insn |= val & 0x3f;
3210 break;
3211
3212 case BFD_RELOC_SPARC_5:
3213 if (! in_bitfield_range (val, 0x1f))
3214 as_bad_where (fixP->fx_file, fixP->fx_line,
3215 _("relocation overflow"));
3216 insn |= val & 0x1f;
3217 break;
3218
3219 case BFD_RELOC_SPARC_WDISP16:
e0c6ed95 3220 /* FIXME: simplify. */
252b5132
RH		 3221 if (((val > 0) && (val & ~0x3fffc))
3222 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3223 as_bad_where (fixP->fx_file, fixP->fx_line,
3224 _("relocation overflow"));
3225 /* FIXME: The +1 deserves a comment. */
3226 val = (val >> 2) + 1;
3227 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3228 break;
3229
3230 case BFD_RELOC_SPARC_WDISP19:
e0c6ed95 3231 /* FIXME: simplify. */
252b5132
RH		 3232 if (((val > 0) && (val & ~0x1ffffc))
3233 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3234 as_bad_where (fixP->fx_file, fixP->fx_line,
3235 _("relocation overflow"));
3236 /* FIXME: The +1 deserves a comment. */
3237 val = (val >> 2) + 1;
3238 insn |= val & 0x7ffff;
3239 break;
3240
3241 case BFD_RELOC_SPARC_HH22:
3242 val = BSR (val, 32);
e0c6ed95 3243 /* Fall through. */
252b5132
RH		 3244
3245 case BFD_RELOC_SPARC_LM22:
3246 case BFD_RELOC_HI22:
3247 if (!fixP->fx_addsy)
94f592af 3248 insn |= (val >> 10) & 0x3fffff;
252b5132 3249 else
94f592af
NC		 3250 /* FIXME: Need comment explaining why we do this. */
3251 insn &= ~0xffff;
252b5132
RH		 3252 break;
3253
3254 case BFD_RELOC_SPARC22:
3255 if (val & ~0x003fffff)
3256 as_bad_where (fixP->fx_file, fixP->fx_line,
3257 _("relocation overflow"));
3258 insn |= (val & 0x3fffff);
3259 break;
3260
3261 case BFD_RELOC_SPARC_HM10:
3262 val = BSR (val, 32);
e0c6ed95 3263 /* Fall through. */
252b5132
RH		 3264
3265 case BFD_RELOC_LO10:
3266 if (!fixP->fx_addsy)
94f592af 3267 insn |= val & 0x3ff;
252b5132 3268 else
94f592af
NC		 3269 /* FIXME: Need comment explaining why we do this. */
3270 insn &= ~0xff;
252b5132
RH		 3271 break;
3272
dabe3bbc
RH		 3273 case BFD_RELOC_SPARC_OLO10:
3274 val &= 0x3ff;
3275 val += fixP->tc_fix_data;
e0c6ed95 3276 /* Fall through. */
dabe3bbc 3277
252b5132
RH		 3278 case BFD_RELOC_SPARC13:
3279 if (! in_signed_range (val, 0x1fff))
3280 as_bad_where (fixP->fx_file, fixP->fx_line,
3281 _("relocation overflow"));
3282 insn |= val & 0x1fff;
3283 break;
3284
3285 case BFD_RELOC_SPARC_WDISP22:
3286 val = (val >> 2) + 1;
e0c6ed95 3287 /* Fall through. */
252b5132
RH		 3288 case BFD_RELOC_SPARC_BASE22:
3289 insn |= val & 0x3fffff;
3290 break;
3291
3292 case BFD_RELOC_SPARC_H44:
3293 if (!fixP->fx_addsy)
3294 {
3295 bfd_vma tval = val;
3296 tval >>= 22;
3297 insn |= tval & 0x3fffff;
3298 }
3299 break;
3300
3301 case BFD_RELOC_SPARC_M44:
3302 if (!fixP->fx_addsy)
3303 insn |= (val >> 12) & 0x3ff;
3304 break;
3305
3306 case BFD_RELOC_SPARC_L44:
3307 if (!fixP->fx_addsy)
3308 insn |= val & 0xfff;
3309 break;
3310
3311 case BFD_RELOC_SPARC_HIX22:
3312 if (!fixP->fx_addsy)
3313 {
ab3e48dc 3314 val ^= ~(offsetT) 0;
252b5132
RH		 3315 insn |= (val >> 10) & 0x3fffff;
3316 }
3317 break;
3318
3319 case BFD_RELOC_SPARC_LOX10:
3320 if (!fixP->fx_addsy)
3321 insn |= 0x1c00 | (val & 0x3ff);
3322 break;
3323
3324 case BFD_RELOC_NONE:
3325 default:
3326 as_bad_where (fixP->fx_file, fixP->fx_line,
3327 _("bad or unhandled relocation type: 0x%02x"),
3328 fixP->fx_r_type);
3329 break;
3330 }
3331
3332 if (INSN_BIG_ENDIAN)
3333 bfd_putb32 (insn, (unsigned char *) buf);
3334 else
3335 bfd_putl32 (insn, (unsigned char *) buf);
3336 }
3337
3338 /* Are we finished with this relocation now? */
3339 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3340 fixP->fx_done = 1;
252b5132
RH		 3341}
3342
3343/* Translate internal representation of relocation info to BFD target
3344 format. */
e0c6ed95 3345
dabe3bbc 3346arelent **
252b5132 3347tc_gen_reloc (section, fixp)
a7982600 3348 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 3349 fixS *fixp;
3350{
dabe3bbc 3351 static arelent *relocs[3];
252b5132
RH		 3352 arelent *reloc;
3353 bfd_reloc_code_real_type code;
3354
dabe3bbc
RH		 3355 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3356 relocs[1] = NULL;
252b5132 3357
49309057
ILT		 3358 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3359 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 3360 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3361
3362 switch (fixp->fx_r_type)
3363 {
3364 case BFD_RELOC_16:
3365 case BFD_RELOC_32:
3366 case BFD_RELOC_HI22:
3367 case BFD_RELOC_LO10:
3368 case BFD_RELOC_32_PCREL_S2:
3369 case BFD_RELOC_SPARC13:
63fab58c 3370 case BFD_RELOC_SPARC22:
252b5132
RH		 3371 case BFD_RELOC_SPARC_BASE13:
3372 case BFD_RELOC_SPARC_WDISP16:
3373 case BFD_RELOC_SPARC_WDISP19:
3374 case BFD_RELOC_SPARC_WDISP22:
3375 case BFD_RELOC_64:
3376 case BFD_RELOC_SPARC_5:
3377 case BFD_RELOC_SPARC_6:
3378 case BFD_RELOC_SPARC_7:
3379 case BFD_RELOC_SPARC_10:
3380 case BFD_RELOC_SPARC_11:
3381 case BFD_RELOC_SPARC_HH22:
3382 case BFD_RELOC_SPARC_HM10:
3383 case BFD_RELOC_SPARC_LM22:
3384 case BFD_RELOC_SPARC_PC_HH22:
3385 case BFD_RELOC_SPARC_PC_HM10:
3386 case BFD_RELOC_SPARC_PC_LM22:
3387 case BFD_RELOC_SPARC_H44:
3388 case BFD_RELOC_SPARC_M44:
3389 case BFD_RELOC_SPARC_L44:
3390 case BFD_RELOC_SPARC_HIX22:
3391 case BFD_RELOC_SPARC_LOX10:
3392 case BFD_RELOC_SPARC_REV32:
dabe3bbc 3393 case BFD_RELOC_SPARC_OLO10:
0f2712ed
NC		 3394 case BFD_RELOC_SPARC_UA16:
3395 case BFD_RELOC_SPARC_UA32:
3396 case BFD_RELOC_SPARC_UA64:
bd5e6e7e
JJ		 3397 case BFD_RELOC_8_PCREL:
3398 case BFD_RELOC_16_PCREL:
3399 case BFD_RELOC_32_PCREL:
3400 case BFD_RELOC_64_PCREL:
3401 case BFD_RELOC_SPARC_PLT32:
3402 case BFD_RELOC_SPARC_PLT64:
252b5132
RH		 3403 case BFD_RELOC_VTABLE_ENTRY:
3404 case BFD_RELOC_VTABLE_INHERIT:
b9734f35
JJ		 3405 case BFD_RELOC_SPARC_TLS_GD_HI22:
3406 case BFD_RELOC_SPARC_TLS_GD_LO10:
3407 case BFD_RELOC_SPARC_TLS_GD_ADD:
3408 case BFD_RELOC_SPARC_TLS_GD_CALL:
3409 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3410 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3411 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3412 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3413 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3414 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3415 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3416 case BFD_RELOC_SPARC_TLS_IE_HI22:
3417 case BFD_RELOC_SPARC_TLS_IE_LO10:
3418 case BFD_RELOC_SPARC_TLS_IE_LD:
3419 case BFD_RELOC_SPARC_TLS_IE_LDX:
3420 case BFD_RELOC_SPARC_TLS_IE_ADD:
3421 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3422 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3423 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3424 case BFD_RELOC_SPARC_TLS_DTPOFF64:
252b5132
RH		 3425 code = fixp->fx_r_type;
3426 break;
3427 default:
3428 abort ();
3429 return NULL;
3430 }
3431
3432#if defined (OBJ_ELF) || defined (OBJ_AOUT)
3433 /* If we are generating PIC code, we need to generate a different
3434 set of relocs. */
3435
3436#ifdef OBJ_ELF
3437#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3438#else
3439#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3440#endif
3441
153b546a
ILT		 3442 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3443
252b5132
RH		 3444 if (sparc_pic_code)
3445 {
3446 switch (code)
3447 {
3448 case BFD_RELOC_32_PCREL_S2:
ae6063d4 3449 if (generic_force_reloc (fixp))
252b5132
RH		 3450 code = BFD_RELOC_SPARC_WPLT30;
3451 break;
3452 case BFD_RELOC_HI22:
3453 if (fixp->fx_addsy != NULL
3454 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3455 code = BFD_RELOC_SPARC_PC22;
3456 else
3457 code = BFD_RELOC_SPARC_GOT22;
3458 break;
3459 case BFD_RELOC_LO10:
3460 if (fixp->fx_addsy != NULL
3461 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3462 code = BFD_RELOC_SPARC_PC10;
3463 else
3464 code = BFD_RELOC_SPARC_GOT10;
3465 break;
3466 case BFD_RELOC_SPARC13:
3467 code = BFD_RELOC_SPARC_GOT13;
3468 break;
3469 default:
3470 break;
3471 }
3472 }
e0c6ed95 3473#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
252b5132 3474
dabe3bbc
RH		 3475 if (code == BFD_RELOC_SPARC_OLO10)
3476 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3477 else
3478 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH		 3479 if (reloc->howto == 0)
3480 {
3481 as_bad_where (fixp->fx_file, fixp->fx_line,
3482 _("internal error: can't export reloc type %d (`%s')"),
3483 fixp->fx_r_type, bfd_get_reloc_code_name (code));
dabe3bbc
RH		 3484 xfree (reloc);
3485 relocs[0] = NULL;
3486 return relocs;
252b5132
RH		 3487 }
3488
3489 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3490#ifdef OBJ_AOUT
3491
3492 if (reloc->howto->pc_relative == 0
3493 || code == BFD_RELOC_SPARC_PC10
3494 || code == BFD_RELOC_SPARC_PC22)
3495 reloc->addend = fixp->fx_addnumber;
3496 else if (sparc_pic_code
3497 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3498 && fixp->fx_addsy != NULL
3499 && (S_IS_EXTERNAL (fixp->fx_addsy)
3500 || S_IS_WEAK (fixp->fx_addsy))
3501 && S_IS_DEFINED (fixp->fx_addsy)
3502 && ! S_IS_COMMON (fixp->fx_addsy))
3503 reloc->addend = fixp->fx_addnumber;
3504 else
3505 reloc->addend = fixp->fx_offset - reloc->address;
3506
e0c6ed95 3507#else /* elf or coff */
252b5132 3508
bd5e6e7e
JJ		 3509 if (code != BFD_RELOC_32_PCREL_S2
3510 && code != BFD_RELOC_SPARC_WDISP22
3511 && code != BFD_RELOC_SPARC_WDISP16
3512 && code != BFD_RELOC_SPARC_WDISP19
b9734f35
JJ		 3513 && code != BFD_RELOC_SPARC_WPLT30
3514 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3515 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
252b5132 3516 reloc->addend = fixp->fx_addnumber;
49309057 3517 else if (symbol_section_p (fixp->fx_addsy))
252b5132
RH		 3518 reloc->addend = (section->vma
3519 + fixp->fx_addnumber
3520 + md_pcrel_from (fixp));
3521 else
3522 reloc->addend = fixp->fx_offset;
3523#endif
3524
dabe3bbc
RH		 3525 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3526 on the same location. */
3527 if (code == BFD_RELOC_SPARC_OLO10)
3528 {
3529 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3530 relocs[2] = NULL;
3531
3532 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
ab3e48dc
KH		 3533 *reloc->sym_ptr_ptr
3534 = symbol_get_bfdsym (section_symbol (absolute_section));
dabe3bbc
RH		 3535 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3536 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3537 reloc->addend = fixp->tc_fix_data;
3538 }
3539
3540 return relocs;
252b5132
RH		 3541}
3542\f
e0c6ed95 3543/* We have no need to default values of symbols. */
252b5132 3544
252b5132
RH		 3545symbolS *
3546md_undefined_symbol (name)
c2158c24 3547 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 3548{
3549 return 0;
e0c6ed95
AM		 3550}
3551
3552/* Round up a section size to the appropriate boundary. */
252b5132 3553
252b5132
RH		 3554valueT
3555md_section_align (segment, size)
c2158c24 3556 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 3557 valueT size;
3558{
3559#ifndef OBJ_ELF
3560 /* This is not right for ELF; a.out wants it, and COFF will force
3561 the alignment anyways. */
3562 valueT align = ((valueT) 1
3563 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3564 valueT newsize;
e0c6ed95
AM		 3565
3566 /* Turn alignment value into a mask. */
252b5132
RH		 3567 align--;
3568 newsize = (size + align) & ~align;
3569 return newsize;
3570#else
3571 return size;
3572#endif
3573}
3574
3575/* Exactly what point is a PC-relative offset relative TO?
3576 On the sparc, they're relative to the address of the offset, plus
3577 its size. This gets us to the following instruction.
e0c6ed95
AM		 3578 (??? Is this right? FIXME-SOON) */
3579long
252b5132
RH		 3580md_pcrel_from (fixP)
3581 fixS *fixP;
3582{
3583 long ret;
3584
3585 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3586 if (! sparc_pic_code
3587 || fixP->fx_addsy == NULL
49309057 3588 || symbol_section_p (fixP->fx_addsy))
252b5132
RH		 3589 ret += fixP->fx_size;
3590 return ret;
3591}
3592\f
3593/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3594 of two. */
3595
3596static int
3597log2 (value)
3598 int value;
3599{
3600 int shift;
3601
3602 if (value <= 0)
3603 return -1;
3604
3605 for (shift = 0; (value & 1) == 0; value >>= 1)
3606 ++shift;
3607
3608 return (value == 1) ? shift : -1;
3609}
3610
e0c6ed95 3611/* Sort of like s_lcomm. */
252b5132
RH		 3612
3613#ifndef OBJ_ELF
3614static int max_alignment = 15;
3615#endif
3616
3617static void
3618s_reserve (ignore)
c2158c24 3619 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3620{
3621 char *name;
3622 char *p;
3623 char c;
3624 int align;
3625 int size;
3626 int temp;
3627 symbolS *symbolP;
3628
3629 name = input_line_pointer;
3630 c = get_symbol_end ();
3631 p = input_line_pointer;
3632 *p = c;
3633 SKIP_WHITESPACE ();
3634
3635 if (*input_line_pointer != ',')
3636 {
3637 as_bad (_("Expected comma after name"));
3638 ignore_rest_of_line ();
3639 return;
3640 }
3641
3642 ++input_line_pointer;
3643
3644 if ((size = get_absolute_expression ()) < 0)
3645 {
3646 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3647 ignore_rest_of_line ();
3648 return;
e0c6ed95 3649 } /* Bad length. */
252b5132
RH		 3650
3651 *p = 0;
3652 symbolP = symbol_find_or_make (name);
3653 *p = c;
3654
3655 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3656 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3657 {
3658 as_bad (_("bad .reserve segment -- expected BSS segment"));
3659 return;
3660 }
3661
3662 if (input_line_pointer[2] == '.')
3663 input_line_pointer += 7;
3664 else
3665 input_line_pointer += 6;
3666 SKIP_WHITESPACE ();
3667
3668 if (*input_line_pointer == ',')
3669 {
3670 ++input_line_pointer;
3671
3672 SKIP_WHITESPACE ();
3673 if (*input_line_pointer == '\n')
3674 {
3675 as_bad (_("missing alignment"));
3676 ignore_rest_of_line ();
3677 return;
3678 }
3679
3680 align = (int) get_absolute_expression ();
3681
3682#ifndef OBJ_ELF
3683 if (align > max_alignment)
3684 {
3685 align = max_alignment;
3686 as_warn (_("alignment too large; assuming %d"), align);
3687 }
3688#endif
3689
3690 if (align < 0)
3691 {
3692 as_bad (_("negative alignment"));
3693 ignore_rest_of_line ();
3694 return;
3695 }
3696
3697 if (align != 0)
3698 {
3699 temp = log2 (align);
3700 if (temp < 0)
3701 {
3702 as_bad (_("alignment not a power of 2"));
3703 ignore_rest_of_line ();
3704 return;
3705 }
3706
3707 align = temp;
3708 }
3709
3710 record_alignment (bss_section, align);
3711 }
3712 else
3713 align = 0;
3714
3715 if (!S_IS_DEFINED (symbolP)
3716#ifdef OBJ_AOUT
3717 && S_GET_OTHER (symbolP) == 0
3718 && S_GET_DESC (symbolP) == 0
3719#endif
3720 )
3721 {
3722 if (! need_pass_2)
3723 {
3724 char *pfrag;
3725 segT current_seg = now_seg;
3726 subsegT current_subseg = now_subseg;
3727
e0c6ed95
AM		 3728 /* Switch to bss. */
3729 subseg_set (bss_section, 1);
252b5132
RH		 3730
3731 if (align)
e0c6ed95
AM		 3732 /* Do alignment. */
3733 frag_align (align, 0, 0);
252b5132 3734
e0c6ed95 3735 /* Detach from old frag. */
ab3e48dc 3736 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057 3737 symbol_get_frag (symbolP)->fr_symbol = NULL;
252b5132 3738
49309057 3739 symbol_set_frag (symbolP, frag_now);
e0c6ed95
AM		 3740 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3741 (offsetT) size, (char *) 0);
252b5132
RH		 3742 *pfrag = 0;
3743
3744 S_SET_SEGMENT (symbolP, bss_section);
3745
3746 subseg_set (current_seg, current_subseg);
3747
3748#ifdef OBJ_ELF
3749 S_SET_SIZE (symbolP, size);
3750#endif
3751 }
3752 }
3753 else
3754 {
ab3e48dc
KH		 3755 as_warn ("Ignoring attempt to re-define symbol %s",
3756 S_GET_NAME (symbolP));
e0c6ed95 3757 } /* if not redefining. */
252b5132
RH		 3758
3759 demand_empty_rest_of_line ();
3760}
3761
3762static void
3763s_common (ignore)
c2158c24 3764 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3765{
3766 char *name;
3767 char c;
3768 char *p;
3769 int temp, size;
3770 symbolS *symbolP;
3771
3772 name = input_line_pointer;
3773 c = get_symbol_end ();
e0c6ed95 3774 /* Just after name is now '\0'. */
252b5132
RH		 3775 p = input_line_pointer;
3776 *p = c;
3777 SKIP_WHITESPACE ();
3778 if (*input_line_pointer != ',')
3779 {
3780 as_bad (_("Expected comma after symbol-name"));
3781 ignore_rest_of_line ();
3782 return;
3783 }
e0c6ed95
AM		 3784
3785 /* Skip ','. */
3786 input_line_pointer++;
3787
252b5132
RH		 3788 if ((temp = get_absolute_expression ()) < 0)
3789 {
3790 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3791 ignore_rest_of_line ();
3792 return;
3793 }
3794 size = temp;
3795 *p = 0;
3796 symbolP = symbol_find_or_make (name);
3797 *p = c;
3798 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3799 {
3800 as_bad (_("Ignoring attempt to re-define symbol"));
3801 ignore_rest_of_line ();
3802 return;
3803 }
3804 if (S_GET_VALUE (symbolP) != 0)
3805 {
3806 if (S_GET_VALUE (symbolP) != (valueT) size)
3807 {
3808 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3809 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3810 }
3811 }
3812 else
3813 {
3814#ifndef OBJ_ELF
3815 S_SET_VALUE (symbolP, (valueT) size);
3816 S_SET_EXTERNAL (symbolP);
3817#endif
3818 }
7dcc9865 3819 know (symbol_get_frag (symbolP) == &zero_address_frag);
252b5132
RH		 3820 if (*input_line_pointer != ',')
3821 {
3822 as_bad (_("Expected comma after common length"));
3823 ignore_rest_of_line ();
3824 return;
3825 }
3826 input_line_pointer++;
3827 SKIP_WHITESPACE ();
3828 if (*input_line_pointer != '"')
3829 {
3830 temp = get_absolute_expression ();
3831
3832#ifndef OBJ_ELF
3833 if (temp > max_alignment)
3834 {
3835 temp = max_alignment;
3836 as_warn (_("alignment too large; assuming %d"), temp);
3837 }
3838#endif
3839
3840 if (temp < 0)
3841 {
3842 as_bad (_("negative alignment"));
3843 ignore_rest_of_line ();
3844 return;
3845 }
3846
3847#ifdef OBJ_ELF
49309057 3848 if (symbol_get_obj (symbolP)->local)
252b5132
RH		 3849 {
3850 segT old_sec;
3851 int old_subsec;
3852 char *p;
3853 int align;
3854
3855 old_sec = now_seg;
3856 old_subsec = now_subseg;
3857
3858 if (temp == 0)
3859 align = 0;
3860 else
3861 align = log2 (temp);
3862
3863 if (align < 0)
3864 {
3865 as_bad (_("alignment not a power of 2"));
3866 ignore_rest_of_line ();
3867 return;
3868 }
3869
3870 record_alignment (bss_section, align);
3871 subseg_set (bss_section, 0);
3872 if (align)
3873 frag_align (align, 0, 0);
3874 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057
ILT		 3875 symbol_get_frag (symbolP)->fr_symbol = 0;
3876 symbol_set_frag (symbolP, frag_now);
252b5132
RH		 3877 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3878 (offsetT) size, (char *) 0);
3879 *p = 0;
3880 S_SET_SEGMENT (symbolP, bss_section);
3881 S_CLEAR_EXTERNAL (symbolP);
3882 S_SET_SIZE (symbolP, size);
3883 subseg_set (old_sec, old_subsec);
3884 }
3885 else
e0c6ed95 3886#endif /* OBJ_ELF */
252b5132
RH		 3887 {
3888 allocate_common:
3889 S_SET_VALUE (symbolP, (valueT) size);
3890#ifdef OBJ_ELF
3891 S_SET_ALIGN (symbolP, temp);
3892 S_SET_SIZE (symbolP, size);
3893#endif
3894 S_SET_EXTERNAL (symbolP);
3895 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3896 }
3897 }
3898 else
3899 {
3900 input_line_pointer++;
3901 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3902 if (*input_line_pointer == '.')
3903 input_line_pointer++;
3904 /* @@ Some say data, some say bss. */
3905 if (strncmp (input_line_pointer, "bss\"", 4)
3906 && strncmp (input_line_pointer, "data\"", 5))
3907 {
3908 while (*--input_line_pointer != '"')
3909 ;
3910 input_line_pointer--;
3911 goto bad_common_segment;
3912 }
3913 while (*input_line_pointer++ != '"')
3914 ;
3915 goto allocate_common;
3916 }
3917
3918#ifdef BFD_ASSEMBLER
49309057 3919 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
252b5132
RH		 3920#endif
3921
3922 demand_empty_rest_of_line ();
3923 return;
3924
3925 {
3926 bad_common_segment:
3927 p = input_line_pointer;
3928 while (*p && *p != '\n')
3929 p++;
3930 c = *p;
3931 *p = '\0';
3932 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3933 *p = c;
3934 input_line_pointer = p;
3935 ignore_rest_of_line ();
3936 return;
3937 }
3938}
3939
3940/* Handle the .empty pseudo-op. This supresses the warnings about
3941 invalid delay slot usage. */
3942
3943static void
3944s_empty (ignore)
c2158c24 3945 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3946{
3947 /* The easy way to implement is to just forget about the last
3948 instruction. */
3949 last_insn = NULL;
3950}
3951
3952static void
3953s_seg (ignore)
c2158c24 3954 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3955{
3956
3957 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3958 {
3959 input_line_pointer += 6;
3960 s_text (0);
3961 return;
3962 }
3963 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3964 {
3965 input_line_pointer += 6;
3966 s_data (0);
3967 return;
3968 }
3969 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3970 {
3971 input_line_pointer += 7;
3972 s_data1 ();
3973 return;
3974 }
3975 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3976 {
3977 input_line_pointer += 5;
3978 /* We only support 2 segments -- text and data -- for now, so
3979 things in the "bss segment" will have to go into data for now.
e0c6ed95
AM		 3980 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3981 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
252b5132
RH		 3982 return;
3983 }
3984 as_bad (_("Unknown segment type"));
3985 demand_empty_rest_of_line ();
3986}
3987
3988static void
3989s_data1 ()
3990{
3991 subseg_set (data_section, 1);
3992 demand_empty_rest_of_line ();
3993}
3994
3995static void
3996s_proc (ignore)
c2158c24 3997 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3998{
3999 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4000 {
4001 ++input_line_pointer;
4002 }
4003 ++input_line_pointer;
4004}
4005
4006/* This static variable is set by s_uacons to tell sparc_cons_align
4007 that the expession does not need to be aligned. */
4008
4009static int sparc_no_align_cons = 0;
4010
bd5e6e7e
JJ		 4011/* This static variable is set by sparc_cons to emit requested types
4012 of relocations in cons_fix_new_sparc. */
4013
4014static const char *sparc_cons_special_reloc;
4015
252b5132
RH		 4016/* This handles the unaligned space allocation pseudo-ops, such as
4017 .uaword. .uaword is just like .word, but the value does not need
4018 to be aligned. */
4019
4020static void
4021s_uacons (bytes)
4022 int bytes;
4023{
4024 /* Tell sparc_cons_align not to align this value. */
4025 sparc_no_align_cons = 1;
4026 cons (bytes);
4ffadb11 4027 sparc_no_align_cons = 0;
252b5132
RH		 4028}
4029
cf9a1301
RH		 4030/* This handles the native word allocation pseudo-op .nword.
4031 For sparc_arch_size 32 it is equivalent to .word, for
4032 sparc_arch_size 64 it is equivalent to .xword. */
4033
4034static void
4035s_ncons (bytes)
c2158c24 4036 int bytes ATTRIBUTE_UNUSED;
cf9a1301
RH		 4037{
4038 cons (sparc_arch_size == 32 ? 4 : 8);
4039}
4040
6d8809aa
RH		 4041#ifdef OBJ_ELF
4042/* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4043 global register.
4044 The syntax is:
e0c6ed95 4045
6d8809aa 4046 .register %g[2367],{#scratch|symbolname|#ignore}
e0c6ed95 4047*/
6d8809aa
RH		 4048
4049static void
4050s_register (ignore)
c2158c24 4051 int ignore ATTRIBUTE_UNUSED;
6d8809aa
RH		 4052{
4053 char c;
4054 int reg;
4055 int flags;
4056 const char *regname;
4057
4058 if (input_line_pointer[0] != '%'
4059 || input_line_pointer[1] != 'g'
4060 || ((input_line_pointer[2] & ~1) != '2'
4061 && (input_line_pointer[2] & ~1) != '6')
4062 || input_line_pointer[3] != ',')
4063 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4064 reg = input_line_pointer[2] - '0';
4065 input_line_pointer += 4;
4066
4067 if (*input_line_pointer == '#')
4068 {
4069 ++input_line_pointer;
4070 regname = input_line_pointer;
4071 c = get_symbol_end ();
4072 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4073 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
ab3e48dc 4074 if (regname[0] == 'i')
6d8809aa
RH		 4075 regname = NULL;
4076 else
4077 regname = "";
4078 }
4079 else
4080 {
4081 regname = input_line_pointer;
4082 c = get_symbol_end ();
4083 }
4084 if (sparc_arch_size == 64)
4085 {
e0c6ed95 4086 if (globals[reg])
6d8809aa 4087 {
e0c6ed95
AM		 4088 if ((regname && globals[reg] != (symbolS *) 1
4089 && strcmp (S_GET_NAME (globals[reg]), regname))
4090 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
6d8809aa
RH		 4091 as_bad (_("redefinition of global register"));
4092 }
4093 else
4094 {
4095 if (regname == NULL)
e0c6ed95 4096 globals[reg] = (symbolS *) 1;
6d8809aa
RH		 4097 else
4098 {
4099 if (*regname)
4100 {
4101 if (symbol_find (regname))
4102 as_bad (_("Register symbol %s already defined."),
4103 regname);
4104 }
e0c6ed95
AM		 4105 globals[reg] = symbol_make (regname);
4106 flags = symbol_get_bfdsym (globals[reg])->flags;
6d8809aa
RH		 4107 if (! *regname)
4108 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4109 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4110 flags |= BSF_GLOBAL;
e0c6ed95
AM		 4111 symbol_get_bfdsym (globals[reg])->flags = flags;
4112 S_SET_VALUE (globals[reg], (valueT) reg);
4113 S_SET_ALIGN (globals[reg], reg);
4114 S_SET_SIZE (globals[reg], 0);
6d8809aa
RH		 4115 /* Although we actually want undefined_section here,
4116 we have to use absolute_section, because otherwise
4117 generic as code will make it a COM section.
4118 We fix this up in sparc_adjust_symtab. */
e0c6ed95
AM		 4119 S_SET_SEGMENT (globals[reg], absolute_section);
4120 S_SET_OTHER (globals[reg], 0);
4121 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 4122 ->internal_elf_sym.st_info =
4123 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
e0c6ed95 4124 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 4125 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4126 }
4127 }
4128 }
4129
4130 *input_line_pointer = c;
4131
4132 demand_empty_rest_of_line ();
4133}
4134
4135/* Adjust the symbol table. We set undefined sections for STT_REGISTER
4136 symbols which need it. */
e0c6ed95 4137
6d8809aa
RH		 4138void
4139sparc_adjust_symtab ()
4140{
4141 symbolS *sym;
e0c6ed95 4142
6d8809aa
RH		 4143 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4144 {
4145 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4146 ->internal_elf_sym.st_info) != STT_REGISTER)
4147 continue;
4148
4149 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4150 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4151 continue;
4152
4153 S_SET_SEGMENT (sym, undefined_section);
4154 }
4155}
4156#endif
4157
252b5132
RH		 4158/* If the --enforce-aligned-data option is used, we require .word,
4159 et. al., to be aligned correctly. We do it by setting up an
4160 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4161 no unexpected alignment was introduced.
4162
4163 The SunOS and Solaris native assemblers enforce aligned data by
4164 default. We don't want to do that, because gcc can deliberately
4165 generate misaligned data if the packed attribute is used. Instead,
4166 we permit misaligned data by default, and permit the user to set an
4167 option to check for it. */
4168
4169void
4170sparc_cons_align (nbytes)
4171 int nbytes;
4172{
4173 int nalign;
4174 char *p;
4175
4176 /* Only do this if we are enforcing aligned data. */
4177 if (! enforce_aligned_data)
4178 return;
4179
0f2712ed 4180 /* Don't align if this is an unaligned pseudo-op. */
252b5132 4181 if (sparc_no_align_cons)
0f2712ed 4182 return;
252b5132
RH		 4183
4184 nalign = log2 (nbytes);
4185 if (nalign == 0)
4186 return;
4187
4188 assert (nalign > 0);
4189
4190 if (now_seg == absolute_section)
4191 {
4192 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4193 as_bad (_("misaligned data"));
4194 return;
4195 }
4196
0a9ef439 4197 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
252b5132
RH		 4198 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4199
4200 record_alignment (now_seg, nalign);
4201}
4202
0a9ef439 4203/* This is called from HANDLE_ALIGN in tc-sparc.h. */
252b5132
RH		 4204
4205void
4206sparc_handle_align (fragp)
4207 fragS *fragp;
4208{
0a9ef439
RH		 4209 int count, fix;
4210 char *p;
4211
4212 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
bfb32b52 4213
0a9ef439 4214 switch (fragp->fr_type)
252b5132 4215 {
0a9ef439
RH		 4216 case rs_align_test:
4217 if (count != 0)
4218 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4219 break;
e0c6ed95 4220
0a9ef439
RH		 4221 case rs_align_code:
4222 p = fragp->fr_literal + fragp->fr_fix;
4223 fix = 0;
e0c6ed95 4224
0a9ef439
RH		 4225 if (count & 3)
4226 {
4227 fix = count & 3;
4228 memset (p, 0, fix);
4229 p += fix;
4230 count -= fix;
4231 }
e0c6ed95 4232
0a9ef439
RH		 4233 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4234 {
4235 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4236 if (INSN_BIG_ENDIAN)
4237 number_to_chars_bigendian (p, wval, 4);
4238 else
4239 number_to_chars_littleendian (p, wval, 4);
4240 p += 4;
4241 count -= 4;
4242 fix += 4;
e0c6ed95 4243 }
0a9ef439
RH		 4244
4245 if (INSN_BIG_ENDIAN)
4246 number_to_chars_bigendian (p, 0x01000000, 4);
4247 else
4248 number_to_chars_littleendian (p, 0x01000000, 4);
4249
4250 fragp->fr_fix += fix;
4251 fragp->fr_var = 4;
4252 break;
4253
4254 default:
4255 break;
252b5132
RH		 4256 }
4257}
4258
4259#ifdef OBJ_ELF
4260/* Some special processing for a Sparc ELF file. */
4261
4262void
4263sparc_elf_final_processing ()
4264{
4265 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4266 sort of BFD interface for this. */
4267 if (sparc_arch_size == 64)
4268 {
4269 switch (sparc_memory_model)
4270 {
4271 case MM_RMO:
4272 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4273 break;
4274 case MM_PSO:
4275 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4276 break;
4277 default:
4278 break;
4279 }
4280 }
4281 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4282 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4283 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4284 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
19f7b010
JJ		 4285 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4286 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
252b5132 4287}
bd5e6e7e
JJ		 4288
4289void
4290sparc_cons (exp, size)
4291 expressionS *exp;
4292 int size;
4293{
4294 char *save;
4295
4296 SKIP_WHITESPACE ();
4297 sparc_cons_special_reloc = NULL;
4298 save = input_line_pointer;
4299 if (input_line_pointer[0] == '%'
4300 && input_line_pointer[1] == 'r'
4301 && input_line_pointer[2] == '_')
4302 {
4303 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4304 {
4305 input_line_pointer += 7;
4306 sparc_cons_special_reloc = "disp";
4307 }
4308 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4309 {
4310 if (size != 4 && size != 8)
4311 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4312 else
4313 {
4314 input_line_pointer += 6;
4315 sparc_cons_special_reloc = "plt";
4316 }
4317 }
b9734f35
JJ		 4318 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4319 {
4320 if (size != 4 && size != 8)
4321 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4322 else
4323 {
4324 input_line_pointer += 13;
4325 sparc_cons_special_reloc = "tls_dtpoff";
4326 }
4327 }
bd5e6e7e
JJ		 4328 if (sparc_cons_special_reloc)
4329 {
4330 int bad = 0;
4331
4332 switch (size)
4333 {
4334 case 1:
4335 if (*input_line_pointer != '8')
4336 bad = 1;
4337 input_line_pointer--;
4338 break;
4339 case 2:
4340 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4341 bad = 1;
4342 break;
4343 case 4:
4344 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4345 bad = 1;
4346 break;
4347 case 8:
4348 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4349 bad = 1;
4350 break;
4351 default:
4352 bad = 1;
4353 break;
4354 }
4355
4356 if (bad)
4357 {
4358 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4359 sparc_cons_special_reloc, size * 8, size);
4360 }
4361 else
4362 {
4363 input_line_pointer += 2;
4364 if (*input_line_pointer != '(')
4365 {
4366 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4367 sparc_cons_special_reloc, size * 8);
4368 bad = 1;
4369 }
4370 }
4371
4372 if (bad)
4373 {
4374 input_line_pointer = save;
4375 sparc_cons_special_reloc = NULL;
4376 }
4377 else
4378 {
4379 int c;
4380 char *end = ++input_line_pointer;
4381 int npar = 0;
4382
4383 while (! is_end_of_line[(c = *end)])
4384 {
4385 if (c == '(')
4386 npar++;
4387 else if (c == ')')
4388 {
4389 if (!npar)
4390 break;
4391 npar--;
4392 }
4393 end++;
4394 }
4395
4396 if (c != ')')
4397 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4398 sparc_cons_special_reloc, size * 8);
4399 else
4400 {
4401 *end = '\0';
4402 expression (exp);
4403 *end = c;
4404 if (input_line_pointer != end)
4405 {
4406 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4407 sparc_cons_special_reloc, size * 8);
4408 }
4409 else
4410 {
4411 input_line_pointer++;
4412 SKIP_WHITESPACE ();
4413 c = *input_line_pointer;
4414 if (! is_end_of_line[c] && c != ',')
4415 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4416 sparc_cons_special_reloc, size * 8);
4417 }
4418 }
4419 }
4420 }
4421 }
4422 if (sparc_cons_special_reloc == NULL)
4423 expression (exp);
4424}
4425
252b5132
RH		 4426#endif
4427
4428/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4429 reloc for a cons. We could use the definition there, except that
4430 we want to handle little endian relocs specially. */
4431
4432void
4433cons_fix_new_sparc (frag, where, nbytes, exp)
4434 fragS *frag;
4435 int where;
4436 unsigned int nbytes;
4437 expressionS *exp;
4438{
4439 bfd_reloc_code_real_type r;
4440
4441 r = (nbytes == 1 ? BFD_RELOC_8 :
4442 (nbytes == 2 ? BFD_RELOC_16 :
4443 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4444
0f2712ed
NC		 4445 if (target_little_endian_data
4446 && nbytes == 4
e0c6ed95 4447 && now_seg->flags & SEC_ALLOC)
252b5132 4448 r = BFD_RELOC_SPARC_REV32;
0f2712ed 4449
bd5e6e7e
JJ		 4450 if (sparc_cons_special_reloc)
4451 {
4452 if (*sparc_cons_special_reloc == 'd')
4453 switch (nbytes)
4454 {
4455 case 1: r = BFD_RELOC_8_PCREL; break;
4456 case 2: r = BFD_RELOC_16_PCREL; break;
4457 case 4: r = BFD_RELOC_32_PCREL; break;
4458 case 8: r = BFD_RELOC_64_PCREL; break;
4459 default: abort ();
4460 }
b9734f35 4461 else if (*sparc_cons_special_reloc == 'p')
bd5e6e7e
JJ		 4462 switch (nbytes)
4463 {
4464 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4465 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4466 }
b9734f35
JJ		 4467 else
4468 switch (nbytes)
4469 {
4470 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4471 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4472 }
bd5e6e7e
JJ		 4473 }
4474 else if (sparc_no_align_cons)
0f2712ed
NC		 4475 {
4476 switch (nbytes)
4477 {
4478 case 2: r = BFD_RELOC_SPARC_UA16; break;
4479 case 4: r = BFD_RELOC_SPARC_UA32; break;
4480 case 8: r = BFD_RELOC_SPARC_UA64; break;
4481 default: abort ();
4482 }
4ffadb11 4483 }
0f2712ed 4484
252b5132
RH		 4485 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4486}
GDB Binutils - Deliverables
This page took 0.406097 seconds and 4 git commands to generate.