Commit | Line | Data |
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252b5132 | 1 | /* tc-sparc.c -- Assemble for the SPARC |
6f2750fe | 2 | Copyright (C) 1989-2016 Free Software Foundation, Inc. |
252b5132 RH |
3 | This file is part of GAS, the GNU Assembler. |
4 | ||
5 | GAS is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 7 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
8 | any later version. |
9 | ||
10 | GAS is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public | |
16 | License along with GAS; see the file COPYING. If not, write | |
4b4da160 NC |
17 | to the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
18 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 19 | |
252b5132 | 20 | #include "as.h" |
3882b010 | 21 | #include "safe-ctype.h" |
252b5132 RH |
22 | #include "subsegs.h" |
23 | ||
24 | #include "opcode/sparc.h" | |
364b6d8b | 25 | #include "dw2gencfi.h" |
252b5132 RH |
26 | |
27 | #ifdef OBJ_ELF | |
28 | #include "elf/sparc.h" | |
732d96b6 | 29 | #include "dwarf2dbg.h" |
252b5132 RH |
30 | #endif |
31 | ||
6c1b24e4 AO |
32 | /* Some ancient Sun C compilers would not take such hex constants as |
33 | unsigned, and would end up sign-extending them to form an offsetT, | |
34 | so use these constants instead. */ | |
35 | #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) | |
36 | #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) | |
37 | ||
5a49b8ac AM |
38 | static int sparc_ip (char *, const struct sparc_opcode **); |
39 | static int parse_keyword_arg (int (*) (const char *), char **, int *); | |
40 | static int parse_const_expr_arg (char **, int *); | |
41 | static int get_expression (char *); | |
252b5132 RH |
42 | |
43 | /* Default architecture. */ | |
44 | /* ??? The default value should be V8, but sparclite support was added | |
45 | by making it the default. GCC now passes -Asparclite, so maybe sometime in | |
46 | the future we can set this to V8. */ | |
47 | #ifndef DEFAULT_ARCH | |
48 | #define DEFAULT_ARCH "sparclite" | |
49 | #endif | |
e0471c16 | 50 | static const char *default_arch = DEFAULT_ARCH; |
252b5132 RH |
51 | |
52 | /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' | |
53 | have been set. */ | |
54 | static int default_init_p; | |
55 | ||
56 | /* Current architecture. We don't bump up unless necessary. */ | |
57 | static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; | |
58 | ||
59 | /* The maximum architecture level we can bump up to. | |
60 | In a 32 bit environment, don't allow bumping up to v9 by default. | |
61 | The native assembler works this way. The user is required to pass | |
62 | an explicit argument before we'll create v9 object files. However, if | |
63 | we don't see any v9 insns, a v8plus object file is not created. */ | |
64 | static enum sparc_opcode_arch_val max_architecture; | |
65 | ||
66 | /* Either 32 or 64, selects file format. */ | |
67 | static int sparc_arch_size; | |
68 | /* Initial (default) value, recorded separately in case a user option | |
69 | changes the value before md_show_usage is called. */ | |
70 | static int default_arch_size; | |
71 | ||
72 | #ifdef OBJ_ELF | |
73 | /* The currently selected v9 memory model. Currently only used for | |
74 | ELF. */ | |
75 | static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; | |
9e8c70f9 DM |
76 | |
77 | #ifndef TE_SOLARIS | |
78 | /* Bitmask of instruction types seen so far, used to populate the | |
79 | GNU attributes section with hwcap information. */ | |
3d68f91c | 80 | static bfd_uint64_t hwcap_seen; |
9e8c70f9 | 81 | #endif |
252b5132 RH |
82 | #endif |
83 | ||
3d68f91c | 84 | static bfd_uint64_t hwcap_allowed; |
4bafe00e | 85 | |
252b5132 RH |
86 | static int architecture_requested; |
87 | static int warn_on_bump; | |
88 | ||
89 | /* If warn_on_bump and the needed architecture is higher than this | |
90 | architecture, issue a warning. */ | |
91 | static enum sparc_opcode_arch_val warn_after_architecture; | |
92 | ||
46a2d504 JM |
93 | /* Non-zero if the assembler should generate error if an undeclared |
94 | g[23] register has been used in -64. */ | |
6d8809aa RH |
95 | static int no_undeclared_regs; |
96 | ||
46a2d504 JM |
97 | /* Non-zero if the assembler should generate a warning if an |
98 | unpredictable DCTI (delayed control transfer instruction) couple is | |
99 | found. */ | |
100 | static int dcti_couples_detect; | |
101 | ||
6faf3d66 JJ |
102 | /* Non-zero if we should try to relax jumps and calls. */ |
103 | static int sparc_relax; | |
104 | ||
252b5132 RH |
105 | /* Non-zero if we are generating PIC code. */ |
106 | int sparc_pic_code; | |
107 | ||
108 | /* Non-zero if we should give an error when misaligned data is seen. */ | |
109 | static int enforce_aligned_data; | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
113 | static int target_little_endian_data; | |
114 | ||
6d8809aa RH |
115 | /* Symbols for global registers on v9. */ |
116 | static symbolS *globals[8]; | |
117 | ||
364b6d8b JJ |
118 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ |
119 | int sparc_cie_data_alignment; | |
120 | ||
252b5132 RH |
121 | /* V9 and 86x have big and little endian data, but instructions are always big |
122 | endian. The sparclet has bi-endian support but both data and insns have | |
123 | the same endianness. Global `target_big_endian' is used for data. | |
124 | The following macro is used for instructions. */ | |
125 | #ifndef INSN_BIG_ENDIAN | |
126 | #define INSN_BIG_ENDIAN (target_big_endian \ | |
127 | || default_arch_type == sparc86x \ | |
128 | || SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
129 | #endif | |
130 | ||
e0c6ed95 | 131 | /* Handle of the OPCODE hash table. */ |
252b5132 RH |
132 | static struct hash_control *op_hash; |
133 | ||
5a49b8ac AM |
134 | static void s_data1 (void); |
135 | static void s_seg (int); | |
136 | static void s_proc (int); | |
137 | static void s_reserve (int); | |
138 | static void s_common (int); | |
139 | static void s_empty (int); | |
140 | static void s_uacons (int); | |
141 | static void s_ncons (int); | |
a7982600 | 142 | #ifdef OBJ_ELF |
5a49b8ac | 143 | static void s_register (int); |
a7982600 | 144 | #endif |
252b5132 RH |
145 | |
146 | const pseudo_typeS md_pseudo_table[] = | |
147 | { | |
e0c6ed95 | 148 | {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ |
252b5132 RH |
149 | {"common", s_common, 0}, |
150 | {"empty", s_empty, 0}, | |
151 | {"global", s_globl, 0}, | |
152 | {"half", cons, 2}, | |
cf9a1301 | 153 | {"nword", s_ncons, 0}, |
252b5132 RH |
154 | {"optim", s_ignore, 0}, |
155 | {"proc", s_proc, 0}, | |
156 | {"reserve", s_reserve, 0}, | |
157 | {"seg", s_seg, 0}, | |
158 | {"skip", s_space, 0}, | |
159 | {"word", cons, 4}, | |
160 | {"xword", cons, 8}, | |
161 | {"uahalf", s_uacons, 2}, | |
162 | {"uaword", s_uacons, 4}, | |
163 | {"uaxword", s_uacons, 8}, | |
164 | #ifdef OBJ_ELF | |
e0c6ed95 | 165 | /* These are specific to sparc/svr4. */ |
252b5132 RH |
166 | {"2byte", s_uacons, 2}, |
167 | {"4byte", s_uacons, 4}, | |
168 | {"8byte", s_uacons, 8}, | |
6d8809aa | 169 | {"register", s_register, 0}, |
252b5132 RH |
170 | #endif |
171 | {NULL, 0, 0}, | |
172 | }; | |
173 | ||
252b5132 | 174 | /* This array holds the chars that always start a comment. If the |
e0c6ed95 AM |
175 | pre-processor is disabled, these aren't very useful. */ |
176 | const char comment_chars[] = "!"; /* JF removed '|' from | |
177 | comment_chars. */ | |
252b5132 RH |
178 | |
179 | /* This array holds the chars that only start a comment at the beginning of | |
180 | a line. If the line seems to have the form '# 123 filename' | |
e0c6ed95 | 181 | .line and .file directives will appear in the pre-processed output. */ |
252b5132 RH |
182 | /* Note that input_file.c hand checks for '#' at the beginning of the |
183 | first line of the input file. This is because the compiler outputs | |
e0c6ed95 | 184 | #NO_APP at the beginning of its output. */ |
252b5132 | 185 | /* Also note that comments started like this one will always |
e0c6ed95 | 186 | work if '/' isn't otherwise defined. */ |
252b5132 RH |
187 | const char line_comment_chars[] = "#"; |
188 | ||
63a0b638 | 189 | const char line_separator_chars[] = ";"; |
252b5132 | 190 | |
e0c6ed95 AM |
191 | /* Chars that can be used to separate mant from exp in floating point |
192 | nums. */ | |
252b5132 RH |
193 | const char EXP_CHARS[] = "eE"; |
194 | ||
e0c6ed95 AM |
195 | /* Chars that mean this number is a floating point constant. |
196 | As in 0f12.456 | |
197 | or 0d1.2345e12 */ | |
252b5132 RH |
198 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
199 | ||
200 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
201 | changed in read.c. Ideally it shouldn't have to know about it at all, | |
202 | but nothing is ideal around here. */ | |
203 | ||
74b56d1f | 204 | #define isoctal(c) ((unsigned) ((c) - '0') < 8) |
252b5132 RH |
205 | |
206 | struct sparc_it | |
207 | { | |
6d4af3c2 | 208 | const char *error; |
252b5132 RH |
209 | unsigned long opcode; |
210 | struct nlist *nlistp; | |
211 | expressionS exp; | |
cf9a1301 | 212 | expressionS exp2; |
252b5132 RH |
213 | int pcrel; |
214 | bfd_reloc_code_real_type reloc; | |
215 | }; | |
216 | ||
217 | struct sparc_it the_insn, set_insn; | |
218 | ||
5a49b8ac | 219 | static void output_insn (const struct sparc_opcode *, struct sparc_it *); |
252b5132 RH |
220 | \f |
221 | /* Table of arguments to -A. | |
222 | The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect | |
223 | for this use. That table is for opcodes only. This table is for opcodes | |
224 | and file formats. */ | |
225 | ||
d6787ef9 | 226 | enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus, |
19f7b010 | 227 | v8plusa, v9, v9a, v9b, v9_64}; |
252b5132 | 228 | |
3d68f91c JM |
229 | /* Hardware capability sets, used to keep sparc_arch_table easy to |
230 | read. */ | |
231 | #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD | |
232 | #define HWS_V9 HWS_V8 | HWCAP_POPC | |
233 | #define HWS_VA HWS_V9 | HWCAP_VIS | |
234 | #define HWS_VB HWS_VA | HWCAP_VIS2 | |
235 | #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT | |
236 | #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC | |
237 | #define HWS_VE HWS_VD \ | |
238 | | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \ | |
239 | | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \ | |
240 | | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE | |
241 | #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA | |
242 | #define HWS_VM HWS_VV | |
243 | ||
244 | #define HWS2_VM \ | |
245 | HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \ | |
246 | | HWCAP2_XMPMUL | HWCAP2_XMONT | |
247 | ||
252b5132 | 248 | static struct sparc_arch { |
e0471c16 TS |
249 | const char *name; |
250 | const char *opcode_arch; | |
252b5132 RH |
251 | enum sparc_arch_types arch_type; |
252 | /* Default word size, as specified during configuration. | |
253 | A value of zero means can't be used to specify default architecture. */ | |
254 | int default_arch_size; | |
255 | /* Allowable arg to -A? */ | |
256 | int user_option_p; | |
4bafe00e | 257 | int hwcap_allowed; |
3d68f91c | 258 | int hwcap2_allowed; |
252b5132 | 259 | } sparc_arch_table[] = { |
3d68f91c JM |
260 | { "v6", "v6", v6, 0, 1, 0, 0 }, |
261 | { "v7", "v7", v7, 0, 1, 0, 0 }, | |
262 | { "v8", "v8", v8, 32, 1, HWS_V8, 0 }, | |
263 | { "v8a", "v8", v8, 32, 1, HWS_V8, 0 }, | |
264 | { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 }, | |
265 | { "sparcvis", "v9a", v9, 0, 1, HWS_VA, 0 }, | |
266 | { "sparcvis2", "v9b", v9, 0, 1, HWS_VB, 0 }, | |
267 | { "sparcfmaf", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF, 0 }, | |
268 | { "sparcima", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_IMA, 0 }, | |
269 | { "sparcvis3", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 }, | |
270 | { "sparcvis3r", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 }, | |
271 | ||
7a10c22f JM |
272 | { "sparc4", "v9v", v9, 0, 1, HWS_VV, 0 }, |
273 | { "sparc5", "v9m", v9, 0, 1, HWS_VM, HWS2_VM }, | |
3d68f91c JM |
274 | |
275 | { "leon", "leon", leon, 32, 1, HWS_V8, 0 }, | |
276 | { "sparclet", "sparclet", sparclet, 32, 1, HWS_V8, 0 }, | |
277 | { "sparclite", "sparclite", sparclite, 32, 1, HWS_V8, 0 }, | |
278 | { "sparc86x", "sparclite", sparc86x, 32, 1, HWS_V8, 0 }, | |
279 | ||
280 | { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 }, | |
281 | { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS|HWS_VA, 0 }, | |
282 | { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VB, 0 }, | |
7a10c22f JM |
283 | { "v8plusc", "v9c", v9, 0, 1, HWCAP_V8PLUS|HWS_VC, 0 }, |
284 | { "v8plusd", "v9d", v9, 0, 1, HWCAP_V8PLUS|HWS_VD, 0 }, | |
285 | { "v8pluse", "v9e", v9, 0, 1, HWCAP_V8PLUS|HWS_VE, 0 }, | |
286 | { "v8plusv", "v9v", v9, 0, 1, HWCAP_V8PLUS|HWS_VV, 0 }, | |
287 | { "v8plusm", "v9m", v9, 0, 1, HWCAP_V8PLUS|HWS_VM, 0 }, | |
3739860c | 288 | |
3d68f91c JM |
289 | { "v9", "v9", v9, 0, 1, HWS_V9, 0 }, |
290 | { "v9a", "v9a", v9, 0, 1, HWS_VA, 0 }, | |
291 | { "v9b", "v9b", v9, 0, 1, HWS_VB, 0 }, | |
7a10c22f JM |
292 | { "v9c", "v9c", v9, 0, 1, HWS_VC, 0 }, |
293 | { "v9d", "v9d", v9, 0, 1, HWS_VD, 0 }, | |
294 | { "v9e", "v9e", v9, 0, 1, HWS_VE, 0 }, | |
295 | { "v9v", "v9v", v9, 0, 1, HWS_VV, 0 }, | |
296 | { "v9m", "v9m", v9, 0, 1, HWS_VM, HWS2_VM }, | |
3d68f91c | 297 | |
1110793a | 298 | /* This exists to allow configure.tgt to pass one |
252b5132 | 299 | value to specify both the default machine and default word size. */ |
3d68f91c JM |
300 | { "v9-64", "v9", v9, 64, 0, HWS_V9, 0 }, |
301 | { NULL, NULL, v8, 0, 0, 0, 0 } | |
252b5132 RH |
302 | }; |
303 | ||
304 | /* Variant of default_arch */ | |
305 | static enum sparc_arch_types default_arch_type; | |
306 | ||
307 | static struct sparc_arch * | |
e0471c16 | 308 | lookup_arch (const char *name) |
252b5132 RH |
309 | { |
310 | struct sparc_arch *sa; | |
311 | ||
312 | for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) | |
313 | if (strcmp (sa->name, name) == 0) | |
314 | break; | |
315 | if (sa->name == NULL) | |
316 | return NULL; | |
317 | return sa; | |
318 | } | |
319 | ||
320 | /* Initialize the default opcode arch and word size from the default | |
321 | architecture name. */ | |
322 | ||
323 | static void | |
5a49b8ac | 324 | init_default_arch (void) |
252b5132 RH |
325 | { |
326 | struct sparc_arch *sa = lookup_arch (default_arch); | |
327 | ||
328 | if (sa == NULL | |
329 | || sa->default_arch_size == 0) | |
330 | as_fatal (_("Invalid default architecture, broken assembler.")); | |
331 | ||
332 | max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); | |
333 | if (max_architecture == SPARC_OPCODE_ARCH_BAD) | |
334 | as_fatal (_("Bad opcode table, broken assembler.")); | |
335 | default_arch_size = sparc_arch_size = sa->default_arch_size; | |
336 | default_init_p = 1; | |
337 | default_arch_type = sa->arch_type; | |
338 | } | |
339 | ||
340 | /* Called by TARGET_FORMAT. */ | |
341 | ||
342 | const char * | |
5a49b8ac | 343 | sparc_target_format (void) |
252b5132 RH |
344 | { |
345 | /* We don't get a chance to initialize anything before we're called, | |
346 | so handle that now. */ | |
347 | if (! default_init_p) | |
348 | init_default_arch (); | |
349 | ||
350 | #ifdef OBJ_AOUT | |
351 | #ifdef TE_NetBSD | |
352 | return "a.out-sparc-netbsd"; | |
353 | #else | |
354 | #ifdef TE_SPARCAOUT | |
355 | if (target_big_endian) | |
356 | return "a.out-sunos-big"; | |
357 | else if (default_arch_type == sparc86x && target_little_endian_data) | |
358 | return "a.out-sunos-big"; | |
ab3e48dc KH |
359 | else |
360 | return "a.out-sparc-little"; | |
252b5132 RH |
361 | #else |
362 | return "a.out-sunos-big"; | |
363 | #endif | |
364 | #endif | |
365 | #endif | |
366 | ||
367 | #ifdef OBJ_BOUT | |
368 | return "b.out.big"; | |
369 | #endif | |
370 | ||
371 | #ifdef OBJ_COFF | |
372 | #ifdef TE_LYNX | |
373 | return "coff-sparc-lynx"; | |
374 | #else | |
375 | return "coff-sparc"; | |
376 | #endif | |
377 | #endif | |
378 | ||
910600e9 RS |
379 | #ifdef TE_VXWORKS |
380 | return "elf32-sparc-vxworks"; | |
381 | #endif | |
382 | ||
252b5132 | 383 | #ifdef OBJ_ELF |
71a75f6f | 384 | return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; |
252b5132 RH |
385 | #endif |
386 | ||
387 | abort (); | |
388 | } | |
389 | \f | |
e0c6ed95 | 390 | /* md_parse_option |
252b5132 RH |
391 | * Invocation line includes a switch not recognized by the base assembler. |
392 | * See if it's a processor-specific option. These are: | |
393 | * | |
394 | * -bump | |
395 | * Warn on architecture bumps. See also -A. | |
396 | * | |
d6787ef9 | 397 | * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet |
252b5132 | 398 | * Standard 32 bit architectures. |
19f7b010 | 399 | * -Av9, -Av9a, -Av9b |
252b5132 RH |
400 | * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). |
401 | * This used to only mean 64 bits, but properly specifying it | |
402 | * complicated gcc's ASM_SPECs, so now opcode selection is | |
403 | * specified orthogonally to word size (except when specifying | |
404 | * the default, but that is an internal implementation detail). | |
19f7b010 JJ |
405 | * -Av8plus, -Av8plusa, -Av8plusb |
406 | * Same as -Av9{,a,b}. | |
407 | * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb | |
408 | * Same as -Av8plus{,a,b} -32, for compatibility with Sun's | |
409 | * assembler. | |
410 | * -xarch=v9, -xarch=v9a, -xarch=v9b | |
411 | * Same as -Av9{,a,b} -64, for compatibility with Sun's | |
c2158c24 | 412 | * assembler. |
252b5132 RH |
413 | * |
414 | * Select the architecture and possibly the file format. | |
415 | * Instructions or features not supported by the selected | |
416 | * architecture cause fatal errors. | |
417 | * | |
418 | * The default is to start at v6, and bump the architecture up | |
419 | * whenever an instruction is seen at a higher level. In 32 bit | |
420 | * environments, v9 is not bumped up to, the user must pass | |
19f7b010 | 421 | * -Av8plus{,a,b}. |
252b5132 RH |
422 | * |
423 | * If -bump is specified, a warning is printing when bumping to | |
424 | * higher levels. | |
425 | * | |
426 | * If an architecture is specified, all instructions must match | |
427 | * that architecture. Any higher level instructions are flagged | |
428 | * as errors. Note that in the 32 bit environment specifying | |
429 | * -Av8plus does not automatically create a v8plus object file, a | |
430 | * v9 insn must be seen. | |
431 | * | |
432 | * If both an architecture and -bump are specified, the | |
433 | * architecture starts at the specified level, but bumps are | |
434 | * warnings. Note that we can't set `current_architecture' to | |
435 | * the requested level in this case: in the 32 bit environment, | |
436 | * we still must avoid creating v8plus object files unless v9 | |
437 | * insns are seen. | |
438 | * | |
439 | * Note: | |
440 | * Bumping between incompatible architectures is always an | |
441 | * error. For example, from sparclite to v9. | |
442 | */ | |
443 | ||
444 | #ifdef OBJ_ELF | |
5a38dc70 | 445 | const char *md_shortopts = "A:K:VQ:sq"; |
252b5132 RH |
446 | #else |
447 | #ifdef OBJ_AOUT | |
5a38dc70 | 448 | const char *md_shortopts = "A:k"; |
252b5132 | 449 | #else |
5a38dc70 | 450 | const char *md_shortopts = "A:"; |
252b5132 RH |
451 | #endif |
452 | #endif | |
453 | struct option md_longopts[] = { | |
454 | #define OPTION_BUMP (OPTION_MD_BASE) | |
455 | {"bump", no_argument, NULL, OPTION_BUMP}, | |
456 | #define OPTION_SPARC (OPTION_MD_BASE + 1) | |
457 | {"sparc", no_argument, NULL, OPTION_SPARC}, | |
458 | #define OPTION_XARCH (OPTION_MD_BASE + 2) | |
459 | {"xarch", required_argument, NULL, OPTION_XARCH}, | |
460 | #ifdef OBJ_ELF | |
461 | #define OPTION_32 (OPTION_MD_BASE + 3) | |
462 | {"32", no_argument, NULL, OPTION_32}, | |
463 | #define OPTION_64 (OPTION_MD_BASE + 4) | |
464 | {"64", no_argument, NULL, OPTION_64}, | |
465 | #define OPTION_TSO (OPTION_MD_BASE + 5) | |
466 | {"TSO", no_argument, NULL, OPTION_TSO}, | |
467 | #define OPTION_PSO (OPTION_MD_BASE + 6) | |
468 | {"PSO", no_argument, NULL, OPTION_PSO}, | |
469 | #define OPTION_RMO (OPTION_MD_BASE + 7) | |
470 | {"RMO", no_argument, NULL, OPTION_RMO}, | |
471 | #endif | |
472 | #ifdef SPARC_BIENDIAN | |
473 | #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) | |
474 | {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, | |
475 | #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) | |
476 | {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, | |
477 | #endif | |
478 | #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) | |
479 | {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, | |
480 | #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) | |
481 | {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, | |
6d8809aa RH |
482 | #ifdef OBJ_ELF |
483 | #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) | |
484 | {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, | |
a25fe906 ILT |
485 | #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) |
486 | {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, | |
6d8809aa | 487 | #endif |
6faf3d66 JJ |
488 | #define OPTION_RELAX (OPTION_MD_BASE + 14) |
489 | {"relax", no_argument, NULL, OPTION_RELAX}, | |
490 | #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) | |
491 | {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
46a2d504 JM |
492 | #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16) |
493 | {"dcti-couples-detect", no_argument, NULL, OPTION_DCTI_COUPLES_DETECT}, | |
252b5132 RH |
494 | {NULL, no_argument, NULL, 0} |
495 | }; | |
e0c6ed95 AM |
496 | |
497 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
498 | |
499 | int | |
17b9d67d | 500 | md_parse_option (int c, const char *arg) |
252b5132 RH |
501 | { |
502 | /* We don't get a chance to initialize anything before we're called, | |
503 | so handle that now. */ | |
504 | if (! default_init_p) | |
505 | init_default_arch (); | |
506 | ||
507 | switch (c) | |
508 | { | |
509 | case OPTION_BUMP: | |
510 | warn_on_bump = 1; | |
511 | warn_after_architecture = SPARC_OPCODE_ARCH_V6; | |
512 | break; | |
513 | ||
514 | case OPTION_XARCH: | |
c2158c24 | 515 | #ifdef OBJ_ELF |
668b27ea | 516 | if (!strncmp (arg, "v9", 2)) |
c2158c24 | 517 | md_parse_option (OPTION_64, NULL); |
668b27ea DM |
518 | else |
519 | { | |
520 | if (!strncmp (arg, "v8", 2) | |
521 | || !strncmp (arg, "v7", 2) | |
522 | || !strncmp (arg, "v6", 2) | |
523 | || !strcmp (arg, "sparclet") | |
524 | || !strcmp (arg, "sparclite") | |
525 | || !strcmp (arg, "sparc86x")) | |
526 | md_parse_option (OPTION_32, NULL); | |
527 | } | |
c2158c24 | 528 | #endif |
e0c6ed95 | 529 | /* Fall through. */ |
252b5132 RH |
530 | |
531 | case 'A': | |
532 | { | |
533 | struct sparc_arch *sa; | |
534 | enum sparc_opcode_arch_val opcode_arch; | |
535 | ||
536 | sa = lookup_arch (arg); | |
537 | if (sa == NULL | |
538 | || ! sa->user_option_p) | |
539 | { | |
c2158c24 JJ |
540 | if (c == OPTION_XARCH) |
541 | as_bad (_("invalid architecture -xarch=%s"), arg); | |
542 | else | |
543 | as_bad (_("invalid architecture -A%s"), arg); | |
252b5132 RH |
544 | return 0; |
545 | } | |
546 | ||
547 | opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); | |
548 | if (opcode_arch == SPARC_OPCODE_ARCH_BAD) | |
549 | as_fatal (_("Bad opcode table, broken assembler.")); | |
550 | ||
4bafe00e DM |
551 | if (!architecture_requested |
552 | || opcode_arch > max_architecture) | |
553 | max_architecture = opcode_arch; | |
3d68f91c JM |
554 | hwcap_allowed |
555 | |= (((bfd_uint64_t) sa->hwcap2_allowed) << 32) | sa->hwcap_allowed; | |
252b5132 RH |
556 | architecture_requested = 1; |
557 | } | |
558 | break; | |
559 | ||
560 | case OPTION_SPARC: | |
561 | /* Ignore -sparc, used by SunOS make default .s.o rule. */ | |
562 | break; | |
563 | ||
564 | case OPTION_ENFORCE_ALIGNED_DATA: | |
565 | enforce_aligned_data = 1; | |
566 | break; | |
567 | ||
568 | #ifdef SPARC_BIENDIAN | |
569 | case OPTION_LITTLE_ENDIAN: | |
570 | target_big_endian = 0; | |
571 | if (default_arch_type != sparclet) | |
572 | as_fatal ("This target does not support -EL"); | |
573 | break; | |
574 | case OPTION_LITTLE_ENDIAN_DATA: | |
575 | target_little_endian_data = 1; | |
576 | target_big_endian = 0; | |
577 | if (default_arch_type != sparc86x | |
578 | && default_arch_type != v9) | |
579 | as_fatal ("This target does not support --little-endian-data"); | |
580 | break; | |
581 | case OPTION_BIG_ENDIAN: | |
582 | target_big_endian = 1; | |
583 | break; | |
584 | #endif | |
585 | ||
586 | #ifdef OBJ_AOUT | |
587 | case 'k': | |
588 | sparc_pic_code = 1; | |
589 | break; | |
590 | #endif | |
591 | ||
592 | #ifdef OBJ_ELF | |
593 | case OPTION_32: | |
594 | case OPTION_64: | |
595 | { | |
596 | const char **list, **l; | |
597 | ||
598 | sparc_arch_size = c == OPTION_32 ? 32 : 64; | |
599 | list = bfd_target_list (); | |
600 | for (l = list; *l != NULL; l++) | |
601 | { | |
602 | if (sparc_arch_size == 32) | |
603 | { | |
71a75f6f | 604 | if (CONST_STRNEQ (*l, "elf32-sparc")) |
252b5132 RH |
605 | break; |
606 | } | |
607 | else | |
608 | { | |
71a75f6f | 609 | if (CONST_STRNEQ (*l, "elf64-sparc")) |
252b5132 RH |
610 | break; |
611 | } | |
612 | } | |
613 | if (*l == NULL) | |
614 | as_fatal (_("No compiled in support for %d bit object file format"), | |
615 | sparc_arch_size); | |
616 | free (list); | |
b7cac25f DM |
617 | |
618 | if (sparc_arch_size == 64 | |
619 | && max_architecture < SPARC_OPCODE_ARCH_V9) | |
620 | max_architecture = SPARC_OPCODE_ARCH_V9; | |
252b5132 RH |
621 | } |
622 | break; | |
623 | ||
624 | case OPTION_TSO: | |
625 | sparc_memory_model = MM_TSO; | |
626 | break; | |
627 | ||
628 | case OPTION_PSO: | |
629 | sparc_memory_model = MM_PSO; | |
630 | break; | |
631 | ||
632 | case OPTION_RMO: | |
633 | sparc_memory_model = MM_RMO; | |
634 | break; | |
635 | ||
636 | case 'V': | |
637 | print_version_id (); | |
638 | break; | |
639 | ||
640 | case 'Q': | |
641 | /* Qy - do emit .comment | |
e0c6ed95 | 642 | Qn - do not emit .comment. */ |
252b5132 RH |
643 | break; |
644 | ||
645 | case 's': | |
e0c6ed95 | 646 | /* Use .stab instead of .stab.excl. */ |
252b5132 RH |
647 | break; |
648 | ||
649 | case 'q': | |
e0c6ed95 | 650 | /* quick -- Native assembler does fewer checks. */ |
252b5132 RH |
651 | break; |
652 | ||
653 | case 'K': | |
654 | if (strcmp (arg, "PIC") != 0) | |
655 | as_warn (_("Unrecognized option following -K")); | |
656 | else | |
657 | sparc_pic_code = 1; | |
658 | break; | |
6d8809aa RH |
659 | |
660 | case OPTION_NO_UNDECLARED_REGS: | |
661 | no_undeclared_regs = 1; | |
662 | break; | |
a25fe906 ILT |
663 | |
664 | case OPTION_UNDECLARED_REGS: | |
665 | no_undeclared_regs = 0; | |
666 | break; | |
252b5132 RH |
667 | #endif |
668 | ||
6faf3d66 JJ |
669 | case OPTION_RELAX: |
670 | sparc_relax = 1; | |
671 | break; | |
672 | ||
673 | case OPTION_NO_RELAX: | |
674 | sparc_relax = 0; | |
675 | break; | |
676 | ||
46a2d504 JM |
677 | case OPTION_DCTI_COUPLES_DETECT: |
678 | dcti_couples_detect = 1; | |
679 | break; | |
680 | ||
252b5132 RH |
681 | default: |
682 | return 0; | |
683 | } | |
684 | ||
685 | return 1; | |
686 | } | |
687 | ||
688 | void | |
5a49b8ac | 689 | md_show_usage (FILE *stream) |
252b5132 RH |
690 | { |
691 | const struct sparc_arch *arch; | |
c2158c24 | 692 | int column; |
252b5132 RH |
693 | |
694 | /* We don't get a chance to initialize anything before we're called, | |
695 | so handle that now. */ | |
696 | if (! default_init_p) | |
697 | init_default_arch (); | |
698 | ||
e0c6ed95 | 699 | fprintf (stream, _("SPARC options:\n")); |
c2158c24 | 700 | column = 0; |
252b5132 RH |
701 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
702 | { | |
c2158c24 JJ |
703 | if (!arch->user_option_p) |
704 | continue; | |
252b5132 RH |
705 | if (arch != &sparc_arch_table[0]) |
706 | fprintf (stream, " | "); | |
07726851 | 707 | if (column + strlen (arch->name) > 70) |
c2158c24 JJ |
708 | { |
709 | column = 0; | |
710 | fputc ('\n', stream); | |
711 | } | |
07726851 | 712 | column += 5 + 2 + strlen (arch->name); |
c2158c24 | 713 | fprintf (stream, "-A%s", arch->name); |
252b5132 | 714 | } |
c2158c24 JJ |
715 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
716 | { | |
717 | if (!arch->user_option_p) | |
718 | continue; | |
719 | fprintf (stream, " | "); | |
07726851 | 720 | if (column + strlen (arch->name) > 65) |
c2158c24 JJ |
721 | { |
722 | column = 0; | |
723 | fputc ('\n', stream); | |
724 | } | |
07726851 | 725 | column += 5 + 7 + strlen (arch->name); |
c2158c24 JJ |
726 | fprintf (stream, "-xarch=%s", arch->name); |
727 | } | |
728 | fprintf (stream, _("\n\ | |
252b5132 RH |
729 | specify variant of SPARC architecture\n\ |
730 | -bump warn when assembler switches architectures\n\ | |
731 | -sparc ignored\n\ | |
6faf3d66 JJ |
732 | --enforce-aligned-data force .long, etc., to be aligned correctly\n\ |
733 | -relax relax jumps and branches (default)\n\ | |
734 | -no-relax avoid changing any jumps and branches\n")); | |
252b5132 RH |
735 | #ifdef OBJ_AOUT |
736 | fprintf (stream, _("\ | |
737 | -k generate PIC\n")); | |
738 | #endif | |
739 | #ifdef OBJ_ELF | |
740 | fprintf (stream, _("\ | |
741 | -32 create 32 bit object file\n\ | |
742 | -64 create 64 bit object file\n")); | |
743 | fprintf (stream, _("\ | |
744 | [default is %d]\n"), default_arch_size); | |
745 | fprintf (stream, _("\ | |
746 | -TSO use Total Store Ordering\n\ | |
747 | -PSO use Partial Store Ordering\n\ | |
748 | -RMO use Relaxed Memory Ordering\n")); | |
749 | fprintf (stream, _("\ | |
750 | [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); | |
751 | fprintf (stream, _("\ | |
752 | -KPIC generate PIC\n\ | |
753 | -V print assembler version number\n\ | |
a25fe906 ILT |
754 | -undeclared-regs ignore application global register usage without\n\ |
755 | appropriate .register directive (default)\n\ | |
756 | -no-undeclared-regs force error on application global register usage\n\ | |
757 | without appropriate .register directive\n\ | |
46a2d504 | 758 | --dcti-couples-detect warn when an unpredictable DCTI couple is found\n\ |
252b5132 RH |
759 | -q ignored\n\ |
760 | -Qy, -Qn ignored\n\ | |
761 | -s ignored\n")); | |
762 | #endif | |
763 | #ifdef SPARC_BIENDIAN | |
764 | fprintf (stream, _("\ | |
765 | -EL generate code for a little endian machine\n\ | |
766 | -EB generate code for a big endian machine\n\ | |
767 | --little-endian-data generate code for a machine having big endian\n\ | |
c20f4f8c | 768 | instructions and little endian data.\n")); |
252b5132 RH |
769 | #endif |
770 | } | |
771 | \f | |
e0c6ed95 | 772 | /* Native operand size opcode translation. */ |
4f2a7b51 | 773 | static struct |
cf9a1301 | 774 | { |
e0471c16 TS |
775 | const char *name; |
776 | const char *name32; | |
777 | const char *name64; | |
cf9a1301 RH |
778 | } native_op_table[] = |
779 | { | |
780 | {"ldn", "ld", "ldx"}, | |
781 | {"ldna", "lda", "ldxa"}, | |
782 | {"stn", "st", "stx"}, | |
783 | {"stna", "sta", "stxa"}, | |
784 | {"slln", "sll", "sllx"}, | |
785 | {"srln", "srl", "srlx"}, | |
786 | {"sran", "sra", "srax"}, | |
787 | {"casn", "cas", "casx"}, | |
788 | {"casna", "casa", "casxa"}, | |
789 | {"clrn", "clr", "clrx"}, | |
790 | {NULL, NULL, NULL}, | |
791 | }; | |
792 | \f | |
10156f83 | 793 | /* sparc64 privileged and hyperprivileged registers. */ |
252b5132 RH |
794 | |
795 | struct priv_reg_entry | |
ab3e48dc | 796 | { |
e0471c16 | 797 | const char *name; |
ab3e48dc KH |
798 | int regnum; |
799 | }; | |
252b5132 RH |
800 | |
801 | struct priv_reg_entry priv_reg_table[] = | |
802 | { | |
803 | {"tpc", 0}, | |
804 | {"tnpc", 1}, | |
805 | {"tstate", 2}, | |
806 | {"tt", 3}, | |
807 | {"tick", 4}, | |
808 | {"tba", 5}, | |
809 | {"pstate", 6}, | |
810 | {"tl", 7}, | |
811 | {"pil", 8}, | |
812 | {"cwp", 9}, | |
813 | {"cansave", 10}, | |
814 | {"canrestore", 11}, | |
815 | {"cleanwin", 12}, | |
816 | {"otherwin", 13}, | |
817 | {"wstate", 14}, | |
818 | {"fq", 15}, | |
10156f83 | 819 | {"gl", 16}, |
38074311 | 820 | {"pmcdper", 23}, |
252b5132 | 821 | {"ver", 31}, |
8b8c7c9f | 822 | {NULL, -1}, /* End marker. */ |
252b5132 RH |
823 | }; |
824 | ||
10156f83 DM |
825 | struct priv_reg_entry hpriv_reg_table[] = |
826 | { | |
827 | {"hpstate", 0}, | |
828 | {"htstate", 1}, | |
829 | {"hintp", 3}, | |
830 | {"htba", 5}, | |
831 | {"hver", 6}, | |
96074adc JM |
832 | {"hmcdper", 23}, |
833 | {"hmcddfr", 24}, | |
834 | {"hva_mask_nz", 27}, | |
ec92c392 JM |
835 | {"hstick_offset", 28}, |
836 | {"hstick_enable", 29}, | |
10156f83 | 837 | {"hstick_cmpr", 31}, |
8b8c7c9f | 838 | {NULL, -1}, /* End marker. */ |
10156f83 DM |
839 | }; |
840 | ||
8b8c7c9f | 841 | /* v9a or later specific ancillary state registers. */ |
252b5132 RH |
842 | |
843 | struct priv_reg_entry v9a_asr_table[] = | |
844 | { | |
845 | {"tick_cmpr", 23}, | |
19f7b010 JJ |
846 | {"sys_tick_cmpr", 25}, |
847 | {"sys_tick", 24}, | |
1a6b486f DM |
848 | {"stick_cmpr", 25}, |
849 | {"stick", 24}, | |
f04d18b7 DM |
850 | {"softint_clear", 21}, |
851 | {"softint_set", 20}, | |
2b661f3d | 852 | {"softint", 22}, |
252b5132 | 853 | {"set_softint", 20}, |
58004e23 | 854 | {"pause", 27}, |
252b5132 RH |
855 | {"pic", 17}, |
856 | {"pcr", 16}, | |
3d68f91c | 857 | {"mwait", 28}, |
252b5132 RH |
858 | {"gsr", 19}, |
859 | {"dcr", 18}, | |
2e52845b | 860 | {"cfr", 26}, |
252b5132 | 861 | {"clear_softint", 21}, |
8b8c7c9f | 862 | {NULL, -1}, /* End marker. */ |
252b5132 RH |
863 | }; |
864 | ||
865 | static int | |
5a49b8ac | 866 | cmp_reg_entry (const void *parg, const void *qarg) |
252b5132 RH |
867 | { |
868 | const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; | |
869 | const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; | |
870 | ||
8b8c7c9f JM |
871 | if (p->name == q->name) |
872 | return 0; | |
873 | else if (p->name == NULL) | |
874 | return 1; | |
875 | else if (q->name == NULL) | |
876 | return -1; | |
877 | else | |
878 | return strcmp (q->name, p->name); | |
879 | } | |
880 | \f | |
881 | /* sparc %-pseudo-operations. */ | |
882 | ||
883 | ||
884 | #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */ | |
885 | #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative | |
886 | contexts. */ | |
887 | #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */ | |
888 | #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the | |
889 | last operand of an | |
890 | instruction. (Generally they can appear | |
891 | anywhere an immediate operand is | |
892 | expected. */ | |
893 | struct pop_entry | |
894 | { | |
895 | /* The name as it appears in assembler. */ | |
896 | const char *name; | |
897 | /* The reloc this pseudo-op translates to. */ | |
9bceab41 | 898 | bfd_reloc_code_real_type reloc; |
8b8c7c9f JM |
899 | /* Flags. See F_POP_* above. */ |
900 | int flags; | |
901 | }; | |
902 | ||
903 | struct pop_entry pop_table[] = | |
904 | { | |
905 | { "hix", BFD_RELOC_SPARC_HIX22, F_POP_V9 }, | |
906 | { "lox", BFD_RELOC_SPARC_LOX10, F_POP_V9 }, | |
907 | { "hi", BFD_RELOC_HI22, F_POP_PCREL }, | |
908 | { "lo", BFD_RELOC_LO10, F_POP_PCREL }, | |
909 | { "pc22", BFD_RELOC_SPARC_PC22, F_POP_PCREL }, | |
910 | { "pc10", BFD_RELOC_SPARC_PC10, F_POP_PCREL }, | |
911 | { "hh", BFD_RELOC_SPARC_HH22, F_POP_V9|F_POP_PCREL }, | |
912 | { "hm", BFD_RELOC_SPARC_HM10, F_POP_V9|F_POP_PCREL }, | |
913 | { "lm", BFD_RELOC_SPARC_LM22, F_POP_V9|F_POP_PCREL }, | |
914 | { "h34", BFD_RELOC_SPARC_H34, F_POP_V9 }, | |
915 | { "l34", BFD_RELOC_SPARC_L44, F_POP_V9 }, | |
916 | { "h44", BFD_RELOC_SPARC_H44, F_POP_V9 }, | |
917 | { "m44", BFD_RELOC_SPARC_M44, F_POP_V9 }, | |
918 | { "l44", BFD_RELOC_SPARC_L44, F_POP_V9 }, | |
919 | { "uhi", BFD_RELOC_SPARC_HH22, F_POP_V9 }, | |
920 | { "ulo", BFD_RELOC_SPARC_HM10, F_POP_V9 }, | |
921 | { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22, 0 }, | |
922 | { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10, 0 }, | |
923 | { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22, 0 }, | |
924 | { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10, 0 }, | |
925 | { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22, 0 }, | |
926 | { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10, 0 }, | |
927 | { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22, 0 }, | |
928 | { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10, 0 }, | |
929 | { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22, 0 }, | |
930 | { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10, 0 }, | |
931 | { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22, 0 }, | |
932 | { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10, 0 }, | |
933 | { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD, F_POP_POSTFIX }, | |
934 | { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, | |
935 | { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD, F_POP_POSTFIX }, | |
936 | { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, | |
937 | { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD, F_POP_POSTFIX }, | |
938 | { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX, F_POP_POSTFIX }, | |
939 | { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD, F_POP_POSTFIX }, | |
940 | { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD, F_POP_POSTFIX }, | |
cf80913a | 941 | { "gdop", BFD_RELOC_SPARC_GOTDATA_OP, F_POP_POSTFIX } |
8b8c7c9f JM |
942 | }; |
943 | \f | |
944 | /* Table of %-names that can appear in a sparc assembly program. This | |
945 | table is initialized in md_begin and contains entries for each | |
946 | privileged/hyperprivileged/alternate register and %-pseudo-op. */ | |
947 | ||
948 | enum perc_entry_type | |
949 | { | |
950 | perc_entry_none = 0, | |
951 | perc_entry_reg, | |
952 | perc_entry_post_pop, | |
953 | perc_entry_imm_pop | |
954 | }; | |
955 | ||
956 | struct perc_entry | |
957 | { | |
958 | /* Entry type. */ | |
959 | enum perc_entry_type type; | |
960 | /* Name of the %-entity. */ | |
961 | const char *name; | |
962 | /* strlen (name). */ | |
963 | int len; | |
964 | /* Value. Either a pop or a reg depending on type.*/ | |
965 | union | |
966 | { | |
967 | struct pop_entry *pop; | |
968 | struct priv_reg_entry *reg; | |
969 | }; | |
970 | }; | |
971 | ||
972 | #define NUM_PERC_ENTRIES \ | |
973 | (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \ | |
974 | + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \ | |
975 | + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \ | |
cf80913a | 976 | + ARRAY_SIZE (pop_table) \ |
8b8c7c9f JM |
977 | + 1) |
978 | ||
979 | struct perc_entry perc_table[NUM_PERC_ENTRIES]; | |
980 | ||
981 | static int | |
982 | cmp_perc_entry (const void *parg, const void *qarg) | |
983 | { | |
984 | const struct perc_entry *p = (const struct perc_entry *) parg; | |
985 | const struct perc_entry *q = (const struct perc_entry *) qarg; | |
986 | ||
987 | if (p->name == q->name) | |
988 | return 0; | |
989 | else if (p->name == NULL) | |
990 | return 1; | |
991 | else if (q->name == NULL) | |
992 | return -1; | |
993 | else | |
994 | return strcmp (q->name, p->name); | |
252b5132 RH |
995 | } |
996 | \f | |
997 | /* This function is called once, at assembler startup time. It should | |
e0c6ed95 AM |
998 | set up all the tables, etc. that the MD part of the assembler will |
999 | need. */ | |
252b5132 RH |
1000 | |
1001 | void | |
5a49b8ac | 1002 | md_begin (void) |
252b5132 | 1003 | { |
ed9e98c2 | 1004 | const char *retval = NULL; |
252b5132 | 1005 | int lose = 0; |
ed9e98c2 | 1006 | unsigned int i = 0; |
252b5132 RH |
1007 | |
1008 | /* We don't get a chance to initialize anything before md_parse_option | |
1009 | is called, and it may not be called, so handle default initialization | |
1010 | now if not already done. */ | |
1011 | if (! default_init_p) | |
1012 | init_default_arch (); | |
1013 | ||
364b6d8b | 1014 | sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; |
252b5132 RH |
1015 | op_hash = hash_new (); |
1016 | ||
1017 | while (i < (unsigned int) sparc_num_opcodes) | |
1018 | { | |
1019 | const char *name = sparc_opcodes[i].name; | |
5a49b8ac | 1020 | retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); |
252b5132 RH |
1021 | if (retval != NULL) |
1022 | { | |
cf9a1301 RH |
1023 | as_bad (_("Internal error: can't hash `%s': %s\n"), |
1024 | sparc_opcodes[i].name, retval); | |
252b5132 RH |
1025 | lose = 1; |
1026 | } | |
1027 | do | |
1028 | { | |
1029 | if (sparc_opcodes[i].match & sparc_opcodes[i].lose) | |
1030 | { | |
cf9a1301 RH |
1031 | as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), |
1032 | sparc_opcodes[i].name, sparc_opcodes[i].args); | |
252b5132 RH |
1033 | lose = 1; |
1034 | } | |
1035 | ++i; | |
1036 | } | |
1037 | while (i < (unsigned int) sparc_num_opcodes | |
1038 | && !strcmp (sparc_opcodes[i].name, name)); | |
1039 | } | |
1040 | ||
cf9a1301 RH |
1041 | for (i = 0; native_op_table[i].name; i++) |
1042 | { | |
1043 | const struct sparc_opcode *insn; | |
e0471c16 | 1044 | const char *name = ((sparc_arch_size == 32) |
3d4ae3c0 NC |
1045 | ? native_op_table[i].name32 |
1046 | : native_op_table[i].name64); | |
e0c6ed95 | 1047 | insn = (struct sparc_opcode *) hash_find (op_hash, name); |
cf9a1301 | 1048 | if (insn == NULL) |
e0c6ed95 AM |
1049 | { |
1050 | as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), | |
1051 | name, native_op_table[i].name); | |
1052 | lose = 1; | |
1053 | } | |
cf9a1301 RH |
1054 | else |
1055 | { | |
5a49b8ac AM |
1056 | retval = hash_insert (op_hash, native_op_table[i].name, |
1057 | (void *) insn); | |
cf9a1301 RH |
1058 | if (retval != NULL) |
1059 | { | |
1060 | as_bad (_("Internal error: can't hash `%s': %s\n"), | |
1061 | sparc_opcodes[i].name, retval); | |
1062 | lose = 1; | |
1063 | } | |
1064 | } | |
1065 | } | |
1066 | ||
252b5132 RH |
1067 | if (lose) |
1068 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1069 | ||
252b5132 RH |
1070 | qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), |
1071 | sizeof (priv_reg_table[0]), cmp_reg_entry); | |
8b8c7c9f JM |
1072 | qsort (hpriv_reg_table, sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0]), |
1073 | sizeof (hpriv_reg_table[0]), cmp_reg_entry); | |
1074 | qsort (v9a_asr_table, sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0]), | |
1075 | sizeof (v9a_asr_table[0]), cmp_reg_entry); | |
1076 | ||
252b5132 RH |
1077 | /* If -bump, record the architecture level at which we start issuing |
1078 | warnings. The behaviour is different depending upon whether an | |
1079 | architecture was explicitly specified. If it wasn't, we issue warnings | |
1080 | for all upwards bumps. If it was, we don't start issuing warnings until | |
1081 | we need to bump beyond the requested architecture or when we bump between | |
1082 | conflicting architectures. */ | |
1083 | ||
1084 | if (warn_on_bump | |
1085 | && architecture_requested) | |
1086 | { | |
1087 | /* `max_architecture' records the requested architecture. | |
1088 | Issue warnings if we go above it. */ | |
1089 | warn_after_architecture = max_architecture; | |
252b5132 | 1090 | } |
75ac3a7f JM |
1091 | |
1092 | /* Find the highest architecture level that doesn't conflict with | |
1093 | the requested one. */ | |
1094 | ||
1095 | if (warn_on_bump | |
1096 | || !architecture_requested) | |
1097 | { | |
1098 | enum sparc_opcode_arch_val current_max_architecture | |
1099 | = max_architecture; | |
1100 | ||
1101 | for (max_architecture = SPARC_OPCODE_ARCH_MAX; | |
1102 | max_architecture > warn_after_architecture; | |
1103 | --max_architecture) | |
1104 | if (! SPARC_OPCODE_CONFLICT_P (max_architecture, | |
1105 | current_max_architecture)) | |
1106 | break; | |
1107 | } | |
8b8c7c9f JM |
1108 | |
1109 | /* Prepare the tables of %-pseudo-ops. */ | |
1110 | { | |
1111 | struct priv_reg_entry *reg_tables[] | |
1112 | = {priv_reg_table, hpriv_reg_table, v9a_asr_table, NULL}; | |
1113 | struct priv_reg_entry **reg_table; | |
1114 | int entry = 0; | |
1115 | ||
1116 | /* Add registers. */ | |
1117 | for (reg_table = reg_tables; reg_table[0]; reg_table++) | |
1118 | { | |
1119 | struct priv_reg_entry *reg; | |
1120 | for (reg = *reg_table; reg->name; reg++) | |
1121 | { | |
1122 | struct perc_entry *p = &perc_table[entry++]; | |
1123 | p->type = perc_entry_reg; | |
1124 | p->name = reg->name; | |
1125 | p->len = strlen (reg->name); | |
1126 | p->reg = reg; | |
1127 | } | |
1128 | } | |
1129 | ||
1130 | /* Add %-pseudo-ops. */ | |
cf80913a TS |
1131 | for (i = 0; i < ARRAY_SIZE (pop_table); i++) |
1132 | { | |
1133 | struct perc_entry *p = &perc_table[entry++]; | |
1134 | p->type = (pop_table[i].flags & F_POP_POSTFIX | |
1135 | ? perc_entry_post_pop : perc_entry_imm_pop); | |
1136 | p->name = pop_table[i].name; | |
1137 | p->len = strlen (pop_table[i].name); | |
1138 | p->pop = &pop_table[i]; | |
1139 | } | |
8b8c7c9f JM |
1140 | |
1141 | /* Last entry is the centinel. */ | |
1142 | perc_table[entry].type = perc_entry_none; | |
1143 | ||
1144 | qsort (perc_table, sizeof (perc_table) / sizeof (perc_table[0]), | |
1145 | sizeof (perc_table[0]), cmp_perc_entry); | |
1146 | ||
1147 | } | |
252b5132 RH |
1148 | } |
1149 | ||
1150 | /* Called after all assembly has been done. */ | |
1151 | ||
1152 | void | |
5a49b8ac | 1153 | sparc_md_end (void) |
252b5132 | 1154 | { |
19f7b010 | 1155 | unsigned long mach = bfd_mach_sparc; |
daf5e10e | 1156 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) |
3d68f91c | 1157 | int hwcaps, hwcaps2; |
daf5e10e | 1158 | #endif |
19f7b010 | 1159 | |
252b5132 | 1160 | if (sparc_arch_size == 64) |
19f7b010 JJ |
1161 | switch (current_architecture) |
1162 | { | |
1163 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; | |
1164 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; | |
7a10c22f JM |
1165 | case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v9c; break; |
1166 | case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v9d; break; | |
1167 | case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v9e; break; | |
1168 | case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v9v; break; | |
1169 | case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v9m; break; | |
19f7b010 JJ |
1170 | default: mach = bfd_mach_sparc_v9; break; |
1171 | } | |
252b5132 | 1172 | else |
19f7b010 JJ |
1173 | switch (current_architecture) |
1174 | { | |
1175 | case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; | |
1176 | case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; | |
1177 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; | |
1178 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; | |
7a10c22f JM |
1179 | case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v8plusc; break; |
1180 | case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v8plusd; break; | |
1181 | case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v8pluse; break; | |
1182 | case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v8plusv; break; | |
1183 | case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v8plusm; break; | |
19f7b010 JJ |
1184 | /* The sparclite is treated like a normal sparc. Perhaps it shouldn't |
1185 | be but for now it is (since that's the way it's always been | |
1186 | treated). */ | |
1187 | default: break; | |
1188 | } | |
1189 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); | |
9e8c70f9 DM |
1190 | |
1191 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) | |
3d68f91c JM |
1192 | hwcaps = hwcap_seen & U0xffffffff; |
1193 | hwcaps2 = hwcap_seen >> 32; | |
1194 | ||
1195 | if (hwcaps) | |
1196 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcaps); | |
1197 | if (hwcaps2) | |
1198 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS2, hwcaps2); | |
9e8c70f9 | 1199 | #endif |
252b5132 RH |
1200 | } |
1201 | \f | |
1202 | /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ | |
1203 | ||
5a49b8ac AM |
1204 | static inline int |
1205 | in_signed_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
1206 | { |
1207 | if (max <= 0) | |
1208 | abort (); | |
1209 | /* Sign-extend the value from the architecture word size, so that | |
1210 | 0xffffffff is always considered -1 on sparc32. */ | |
1211 | if (sparc_arch_size == 32) | |
1212 | { | |
e0c6ed95 | 1213 | bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; |
6c1b24e4 | 1214 | val = ((val & U0xffffffff) ^ sign) - sign; |
252b5132 RH |
1215 | } |
1216 | if (val > max) | |
1217 | return 0; | |
1218 | if (val < ~max) | |
1219 | return 0; | |
1220 | return 1; | |
1221 | } | |
1222 | ||
1223 | /* Return non-zero if VAL is in the range 0 to MAX. */ | |
1224 | ||
5a49b8ac AM |
1225 | static inline int |
1226 | in_unsigned_range (bfd_vma val, bfd_vma max) | |
252b5132 RH |
1227 | { |
1228 | if (val > max) | |
1229 | return 0; | |
1230 | return 1; | |
1231 | } | |
1232 | ||
1233 | /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. | |
1234 | (e.g. -15 to +31). */ | |
1235 | ||
5a49b8ac AM |
1236 | static inline int |
1237 | in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
1238 | { |
1239 | if (max <= 0) | |
1240 | abort (); | |
1241 | if (val > max) | |
1242 | return 0; | |
1243 | if (val < ~(max >> 1)) | |
1244 | return 0; | |
1245 | return 1; | |
1246 | } | |
1247 | ||
1248 | static int | |
5a49b8ac | 1249 | sparc_ffs (unsigned int mask) |
252b5132 RH |
1250 | { |
1251 | int i; | |
1252 | ||
1253 | if (mask == 0) | |
1254 | return -1; | |
1255 | ||
1256 | for (i = 0; (mask & 1) == 0; ++i) | |
1257 | mask >>= 1; | |
1258 | return i; | |
1259 | } | |
1260 | ||
1261 | /* Implement big shift right. */ | |
1262 | static bfd_vma | |
5a49b8ac | 1263 | BSR (bfd_vma val, int amount) |
252b5132 RH |
1264 | { |
1265 | if (sizeof (bfd_vma) <= 4 && amount >= 32) | |
1266 | as_fatal (_("Support for 64-bit arithmetic not compiled in.")); | |
1267 | return val >> amount; | |
1268 | } | |
1269 | \f | |
1270 | /* For communication between sparc_ip and get_expression. */ | |
1271 | static char *expr_end; | |
1272 | ||
252b5132 RH |
1273 | /* Values for `special_case'. |
1274 | Instructions that require wierd handling because they're longer than | |
1275 | 4 bytes. */ | |
1276 | #define SPECIAL_CASE_NONE 0 | |
1277 | #define SPECIAL_CASE_SET 1 | |
1278 | #define SPECIAL_CASE_SETSW 2 | |
1279 | #define SPECIAL_CASE_SETX 3 | |
1280 | /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ | |
1281 | #define SPECIAL_CASE_FDIV 4 | |
1282 | ||
1283 | /* Bit masks of various insns. */ | |
1284 | #define NOP_INSN 0x01000000 | |
1285 | #define OR_INSN 0x80100000 | |
63fab58c | 1286 | #define XOR_INSN 0x80180000 |
252b5132 RH |
1287 | #define FMOVS_INSN 0x81A00020 |
1288 | #define SETHI_INSN 0x01000000 | |
1289 | #define SLLX_INSN 0x81281000 | |
1290 | #define SRA_INSN 0x81380000 | |
1291 | ||
1292 | /* The last instruction to be assembled. */ | |
1293 | static const struct sparc_opcode *last_insn; | |
1294 | /* The assembled opcode of `last_insn'. */ | |
1295 | static unsigned long last_opcode; | |
1296 | \f | |
a22b281c | 1297 | /* Handle the set and setuw synthetic instructions. */ |
e0c6ed95 | 1298 | |
a22b281c | 1299 | static void |
5a49b8ac | 1300 | synthetize_setuw (const struct sparc_opcode *insn) |
a22b281c RH |
1301 | { |
1302 | int need_hi22_p = 0; | |
1303 | int rd = (the_insn.opcode & RD (~0)) >> 25; | |
1304 | ||
1305 | if (the_insn.exp.X_op == O_constant) | |
1306 | { | |
1307 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1308 | { | |
e0c6ed95 | 1309 | if (sizeof (offsetT) > 4 |
a22b281c | 1310 | && (the_insn.exp.X_add_number < 0 |
6c1b24e4 | 1311 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) |
a22b281c RH |
1312 | as_warn (_("set: number not in 0..4294967295 range")); |
1313 | } | |
1314 | else | |
1315 | { | |
e0c6ed95 | 1316 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1317 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1318 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c | 1319 | as_warn (_("set: number not in -2147483648..4294967295 range")); |
e0c6ed95 | 1320 | the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; |
a22b281c RH |
1321 | } |
1322 | } | |
1323 | ||
1324 | /* See if operand is absolute and small; skip sethi if so. */ | |
1325 | if (the_insn.exp.X_op != O_constant | |
1326 | || the_insn.exp.X_add_number >= (1 << 12) | |
1327 | || the_insn.exp.X_add_number < -(1 << 12)) | |
1328 | { | |
1329 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1330 | | ((the_insn.exp.X_add_number >> 10) | |
ab3e48dc KH |
1331 | & (the_insn.exp.X_op == O_constant |
1332 | ? 0x3fffff : 0))); | |
a22b281c | 1333 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1334 | ? BFD_RELOC_HI22 : BFD_RELOC_NONE); |
a22b281c RH |
1335 | output_insn (insn, &the_insn); |
1336 | need_hi22_p = 1; | |
1337 | } | |
1338 | ||
1339 | /* See if operand has no low-order bits; skip OR if so. */ | |
1340 | if (the_insn.exp.X_op != O_constant | |
1341 | || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) | |
1342 | || ! need_hi22_p) | |
1343 | { | |
1344 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) | |
1345 | | RD (rd) | IMMED | |
1346 | | (the_insn.exp.X_add_number | |
ab3e48dc KH |
1347 | & (the_insn.exp.X_op != O_constant |
1348 | ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); | |
a22b281c | 1349 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1350 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); |
a22b281c RH |
1351 | output_insn (insn, &the_insn); |
1352 | } | |
1353 | } | |
e0c6ed95 | 1354 | |
a22b281c | 1355 | /* Handle the setsw synthetic instruction. */ |
e0c6ed95 | 1356 | |
a22b281c | 1357 | static void |
5a49b8ac | 1358 | synthetize_setsw (const struct sparc_opcode *insn) |
a22b281c RH |
1359 | { |
1360 | int low32, rd, opc; | |
1361 | ||
1362 | rd = (the_insn.opcode & RD (~0)) >> 25; | |
1363 | ||
1364 | if (the_insn.exp.X_op != O_constant) | |
1365 | { | |
1366 | synthetize_setuw (insn); | |
1367 | ||
1368 | /* Need to sign extend it. */ | |
1369 | the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); | |
1370 | the_insn.reloc = BFD_RELOC_NONE; | |
1371 | output_insn (insn, &the_insn); | |
1372 | return; | |
1373 | } | |
1374 | ||
e0c6ed95 | 1375 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1376 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1377 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c RH |
1378 | as_warn (_("setsw: number not in -2147483648..4294967295 range")); |
1379 | ||
e0c6ed95 AM |
1380 | low32 = the_insn.exp.X_add_number; |
1381 | ||
a22b281c RH |
1382 | if (low32 >= 0) |
1383 | { | |
1384 | synthetize_setuw (insn); | |
1385 | return; | |
1386 | } | |
1387 | ||
1388 | opc = OR_INSN; | |
e0c6ed95 | 1389 | |
a22b281c RH |
1390 | the_insn.reloc = BFD_RELOC_NONE; |
1391 | /* See if operand is absolute and small; skip sethi if so. */ | |
1392 | if (low32 < -(1 << 12)) | |
1393 | { | |
1394 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1395 | | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); | |
1396 | output_insn (insn, &the_insn); | |
1397 | low32 = 0x1c00 | (low32 & 0x3ff); | |
1398 | opc = RS1 (rd) | XOR_INSN; | |
1399 | } | |
1400 | ||
1401 | the_insn.opcode = (opc | RD (rd) | IMMED | |
1402 | | (low32 & 0x1fff)); | |
1403 | output_insn (insn, &the_insn); | |
1404 | } | |
1405 | ||
0d495746 | 1406 | /* Handle the setx synthetic instruction. */ |
e0c6ed95 | 1407 | |
a22b281c | 1408 | static void |
5a49b8ac | 1409 | synthetize_setx (const struct sparc_opcode *insn) |
a22b281c RH |
1410 | { |
1411 | int upper32, lower32; | |
1412 | int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; | |
1413 | int dstreg = (the_insn.opcode & RD (~0)) >> 25; | |
1414 | int upper_dstreg; | |
1415 | int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; | |
1416 | int need_xor10_p = 0; | |
e0c6ed95 | 1417 | |
6c1b24e4 | 1418 | #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) |
a22b281c RH |
1419 | lower32 = SIGNEXT32 (the_insn.exp.X_add_number); |
1420 | upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); | |
1421 | #undef SIGNEXT32 | |
1422 | ||
1423 | upper_dstreg = tmpreg; | |
1424 | /* The tmp reg should not be the dst reg. */ | |
1425 | if (tmpreg == dstreg) | |
1426 | as_warn (_("setx: temporary register same as destination register")); | |
1427 | ||
1428 | /* ??? Obviously there are other optimizations we can do | |
1429 | (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be | |
1430 | doing some of these. Later. If you do change things, try to | |
1431 | change all of this to be table driven as well. */ | |
1432 | /* What to output depends on the number if it's constant. | |
1433 | Compute that first, then output what we've decided upon. */ | |
1434 | if (the_insn.exp.X_op != O_constant) | |
1435 | { | |
1436 | if (sparc_arch_size == 32) | |
1437 | { | |
1438 | /* When arch size is 32, we want setx to be equivalent | |
1439 | to setuw for anything but constants. */ | |
1440 | the_insn.exp.X_add_number &= 0xffffffff; | |
1441 | synthetize_setuw (insn); | |
1442 | return; | |
1443 | } | |
1444 | need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; | |
ab3e48dc KH |
1445 | lower32 = 0; |
1446 | upper32 = 0; | |
a22b281c RH |
1447 | } |
1448 | else | |
1449 | { | |
1450 | /* Reset X_add_number, we've extracted it as upper32/lower32. | |
1451 | Otherwise fixup_segment will complain about not being able to | |
1452 | write an 8 byte number in a 4 byte field. */ | |
1453 | the_insn.exp.X_add_number = 0; | |
e0c6ed95 | 1454 | |
a22b281c RH |
1455 | /* Only need hh22 if `or' insn can't handle constant. */ |
1456 | if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) | |
1457 | need_hh22_p = 1; | |
e0c6ed95 | 1458 | |
a22b281c RH |
1459 | /* Does bottom part (after sethi) have bits? */ |
1460 | if ((need_hh22_p && (upper32 & 0x3ff) != 0) | |
1461 | /* No hh22, but does upper32 still have bits we can't set | |
1462 | from lower32? */ | |
1463 | || (! need_hh22_p && upper32 != 0 && upper32 != -1)) | |
1464 | need_hm10_p = 1; | |
e0c6ed95 | 1465 | |
a22b281c RH |
1466 | /* If the lower half is all zero, we build the upper half directly |
1467 | into the dst reg. */ | |
1468 | if (lower32 != 0 | |
1469 | /* Need lower half if number is zero or 0xffffffff00000000. */ | |
1470 | || (! need_hh22_p && ! need_hm10_p)) | |
1471 | { | |
1472 | /* No need for sethi if `or' insn can handle constant. */ | |
1473 | if (lower32 < -(1 << 12) || lower32 >= (1 << 12) | |
1474 | /* Note that we can't use a negative constant in the `or' | |
1475 | insn unless the upper 32 bits are all ones. */ | |
1476 | || (lower32 < 0 && upper32 != -1) | |
1477 | || (lower32 >= 0 && upper32 == -1)) | |
1478 | need_hi22_p = 1; | |
e0c6ed95 | 1479 | |
a22b281c RH |
1480 | if (need_hi22_p && upper32 == -1) |
1481 | need_xor10_p = 1; | |
1482 | ||
1483 | /* Does bottom part (after sethi) have bits? */ | |
1484 | else if ((need_hi22_p && (lower32 & 0x3ff) != 0) | |
1485 | /* No sethi. */ | |
1486 | || (! need_hi22_p && (lower32 & 0x1fff) != 0) | |
1487 | /* Need `or' if we didn't set anything else. */ | |
1488 | || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) | |
1489 | need_lo10_p = 1; | |
1490 | } | |
1491 | else | |
1492 | /* Output directly to dst reg if lower 32 bits are all zero. */ | |
1493 | upper_dstreg = dstreg; | |
1494 | } | |
e0c6ed95 | 1495 | |
a22b281c RH |
1496 | if (!upper_dstreg && dstreg) |
1497 | as_warn (_("setx: illegal temporary register g0")); | |
1498 | ||
1499 | if (need_hh22_p) | |
1500 | { | |
1501 | the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) | |
1502 | | ((upper32 >> 10) & 0x3fffff)); | |
1503 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1504 | ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); | |
1505 | output_insn (insn, &the_insn); | |
1506 | } | |
e0c6ed95 | 1507 | |
a22b281c RH |
1508 | if (need_hi22_p) |
1509 | { | |
1510 | the_insn.opcode = (SETHI_INSN | RD (dstreg) | |
1511 | | (((need_xor10_p ? ~lower32 : lower32) | |
ab3e48dc | 1512 | >> 10) & 0x3fffff)); |
a22b281c RH |
1513 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
1514 | ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); | |
1515 | output_insn (insn, &the_insn); | |
1516 | } | |
1517 | ||
1518 | if (need_hm10_p) | |
1519 | { | |
1520 | the_insn.opcode = (OR_INSN | |
1521 | | (need_hh22_p ? RS1 (upper_dstreg) : 0) | |
1522 | | RD (upper_dstreg) | |
1523 | | IMMED | |
1524 | | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); | |
1525 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1526 | ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); | |
1527 | output_insn (insn, &the_insn); | |
1528 | } | |
e0c6ed95 | 1529 | |
a22b281c RH |
1530 | if (need_lo10_p) |
1531 | { | |
1532 | /* FIXME: One nice optimization to do here is to OR the low part | |
1533 | with the highpart if hi22 isn't needed and the low part is | |
1534 | positive. */ | |
1535 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) | |
1536 | | RD (dstreg) | |
1537 | | IMMED | |
1538 | | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); | |
1539 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1540 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); | |
1541 | output_insn (insn, &the_insn); | |
1542 | } | |
e0c6ed95 | 1543 | |
a22b281c RH |
1544 | /* If we needed to build the upper part, shift it into place. */ |
1545 | if (need_hh22_p || need_hm10_p) | |
1546 | { | |
1547 | the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) | |
1548 | | IMMED | 32); | |
1549 | the_insn.reloc = BFD_RELOC_NONE; | |
1550 | output_insn (insn, &the_insn); | |
1551 | } | |
e0c6ed95 | 1552 | |
a22b281c RH |
1553 | /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ |
1554 | if (need_xor10_p) | |
1555 | { | |
1556 | the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED | |
1557 | | 0x1c00 | (lower32 & 0x3ff)); | |
1558 | the_insn.reloc = BFD_RELOC_NONE; | |
1559 | output_insn (insn, &the_insn); | |
1560 | } | |
1561 | ||
1562 | /* If we needed to build both upper and lower parts, OR them together. */ | |
1563 | else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) | |
1564 | { | |
1565 | the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) | |
1566 | | RD (dstreg)); | |
1567 | the_insn.reloc = BFD_RELOC_NONE; | |
1568 | output_insn (insn, &the_insn); | |
1569 | } | |
1570 | } | |
1571 | \f | |
252b5132 RH |
1572 | /* Main entry point to assemble one instruction. */ |
1573 | ||
1574 | void | |
5a49b8ac | 1575 | md_assemble (char *str) |
252b5132 RH |
1576 | { |
1577 | const struct sparc_opcode *insn; | |
a22b281c | 1578 | int special_case; |
252b5132 RH |
1579 | |
1580 | know (str); | |
a22b281c | 1581 | special_case = sparc_ip (str, &insn); |
b0825cc2 DM |
1582 | if (insn == NULL) |
1583 | return; | |
252b5132 | 1584 | |
46a2d504 JM |
1585 | /* Certain instructions may not appear on delay slots. Check for |
1586 | these situations. */ | |
b0825cc2 | 1587 | if (last_insn != NULL |
46a2d504 JM |
1588 | && (last_insn->flags & F_DELAYED) != 0) |
1589 | { | |
1590 | /* Before SPARC V9 the effect of having a delayed branch | |
1591 | instruction in the delay slot of a conditional delayed branch | |
1592 | was undefined. | |
1593 | ||
1594 | In SPARC V9 DCTI couples are well defined. | |
1595 | ||
1596 | However, starting with the UltraSPARC Architecture 2005, DCTI | |
1597 | couples (of all kind) are deprecated and should not be used, | |
1598 | as they may be slow or behave differently to what the | |
1599 | programmer expects. */ | |
1600 | if (dcti_couples_detect | |
1601 | && (insn->flags & F_DELAYED) != 0 | |
1602 | && ((max_architecture < SPARC_OPCODE_ARCH_V9 | |
1603 | && (last_insn->flags & F_CONDBR) != 0) | |
1604 | || max_architecture >= SPARC_OPCODE_ARCH_V9C)) | |
1605 | as_warn (_("unpredictable DCTI couple")); | |
1606 | ||
1607 | ||
1608 | /* We warn about attempts to put a floating point branch in a | |
1609 | delay slot, unless the delay slot has been annulled. */ | |
1610 | if ((insn->flags & F_FBR) != 0 | |
1611 | /* ??? This test isn't completely accurate. We assume anything with | |
1612 | F_{UNBR,CONDBR,FBR} set is annullable. */ | |
1613 | && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 | |
1614 | || (last_opcode & ANNUL) == 0)) | |
1615 | as_warn (_("FP branch in delay slot")); | |
1616 | } | |
252b5132 RH |
1617 | |
1618 | /* SPARC before v9 requires a nop instruction between a floating | |
1619 | point instruction and a floating point branch. We insert one | |
1620 | automatically, with a warning. */ | |
1621 | if (max_architecture < SPARC_OPCODE_ARCH_V9 | |
252b5132 RH |
1622 | && last_insn != NULL |
1623 | && (insn->flags & F_FBR) != 0 | |
1624 | && (last_insn->flags & F_FLOAT) != 0) | |
1625 | { | |
1626 | struct sparc_it nop_insn; | |
1627 | ||
1628 | nop_insn.opcode = NOP_INSN; | |
1629 | nop_insn.reloc = BFD_RELOC_NONE; | |
1630 | output_insn (insn, &nop_insn); | |
1631 | as_warn (_("FP branch preceded by FP instruction; NOP inserted")); | |
1632 | } | |
1633 | ||
a22b281c RH |
1634 | switch (special_case) |
1635 | { | |
1636 | case SPECIAL_CASE_NONE: | |
e0c6ed95 | 1637 | /* Normal insn. */ |
a22b281c RH |
1638 | output_insn (insn, &the_insn); |
1639 | break; | |
252b5132 | 1640 | |
a22b281c RH |
1641 | case SPECIAL_CASE_SETSW: |
1642 | synthetize_setsw (insn); | |
1643 | break; | |
e0c6ed95 | 1644 | |
a22b281c RH |
1645 | case SPECIAL_CASE_SET: |
1646 | synthetize_setuw (insn); | |
1647 | break; | |
252b5132 | 1648 | |
a22b281c RH |
1649 | case SPECIAL_CASE_SETX: |
1650 | synthetize_setx (insn); | |
1651 | break; | |
e0c6ed95 | 1652 | |
a22b281c RH |
1653 | case SPECIAL_CASE_FDIV: |
1654 | { | |
1655 | int rd = (the_insn.opcode >> 25) & 0x1f; | |
e0c6ed95 | 1656 | |
a22b281c | 1657 | output_insn (insn, &the_insn); |
e0c6ed95 | 1658 | |
a22b281c RH |
1659 | /* According to information leaked from Sun, the "fdiv" instructions |
1660 | on early SPARC machines would produce incorrect results sometimes. | |
1661 | The workaround is to add an fmovs of the destination register to | |
1662 | itself just after the instruction. This was true on machines | |
e0c6ed95 | 1663 | with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ |
9c2799c2 | 1664 | gas_assert (the_insn.reloc == BFD_RELOC_NONE); |
a22b281c RH |
1665 | the_insn.opcode = FMOVS_INSN | rd | RD (rd); |
1666 | output_insn (insn, &the_insn); | |
1667 | return; | |
1668 | } | |
e0c6ed95 | 1669 | |
a22b281c RH |
1670 | default: |
1671 | as_fatal (_("failed special case insn sanity check")); | |
252b5132 RH |
1672 | } |
1673 | } | |
1674 | ||
4bafe00e | 1675 | static const char * |
3d68f91c | 1676 | get_hwcap_name (bfd_uint64_t mask) |
4bafe00e | 1677 | { |
ec668d69 | 1678 | if (mask & HWCAP_MUL32) |
4bafe00e | 1679 | return "mul32"; |
ec668d69 | 1680 | if (mask & HWCAP_DIV32) |
4bafe00e | 1681 | return "div32"; |
ec668d69 | 1682 | if (mask & HWCAP_FSMULD) |
4bafe00e | 1683 | return "fsmuld"; |
ec668d69 | 1684 | if (mask & HWCAP_V8PLUS) |
4bafe00e | 1685 | return "v8plus"; |
ec668d69 | 1686 | if (mask & HWCAP_POPC) |
4bafe00e | 1687 | return "popc"; |
ec668d69 | 1688 | if (mask & HWCAP_VIS) |
4bafe00e | 1689 | return "vis"; |
ec668d69 | 1690 | if (mask & HWCAP_VIS2) |
4bafe00e | 1691 | return "vis2"; |
ec668d69 | 1692 | if (mask & HWCAP_ASI_BLK_INIT) |
4bafe00e | 1693 | return "ASIBlkInit"; |
ec668d69 | 1694 | if (mask & HWCAP_FMAF) |
4bafe00e | 1695 | return "fmaf"; |
ec668d69 | 1696 | if (mask & HWCAP_VIS3) |
4bafe00e | 1697 | return "vis3"; |
ec668d69 | 1698 | if (mask & HWCAP_HPC) |
4bafe00e | 1699 | return "hpc"; |
ec668d69 | 1700 | if (mask & HWCAP_RANDOM) |
4bafe00e | 1701 | return "random"; |
ec668d69 | 1702 | if (mask & HWCAP_TRANS) |
4bafe00e | 1703 | return "trans"; |
ec668d69 | 1704 | if (mask & HWCAP_FJFMAU) |
4bafe00e | 1705 | return "fjfmau"; |
ec668d69 | 1706 | if (mask & HWCAP_IMA) |
4bafe00e | 1707 | return "ima"; |
ec668d69 | 1708 | if (mask & HWCAP_ASI_CACHE_SPARING) |
4bafe00e | 1709 | return "cspare"; |
ec668d69 DM |
1710 | if (mask & HWCAP_AES) |
1711 | return "aes"; | |
1712 | if (mask & HWCAP_DES) | |
1713 | return "des"; | |
1714 | if (mask & HWCAP_KASUMI) | |
1715 | return "kasumi"; | |
1716 | if (mask & HWCAP_CAMELLIA) | |
1717 | return "camellia"; | |
1718 | if (mask & HWCAP_MD5) | |
1719 | return "md5"; | |
1720 | if (mask & HWCAP_SHA1) | |
1721 | return "sha1"; | |
1722 | if (mask & HWCAP_SHA256) | |
1723 | return "sha256"; | |
1724 | if (mask & HWCAP_SHA512) | |
1725 | return "sha512"; | |
1726 | if (mask & HWCAP_MPMUL) | |
1727 | return "mpmul"; | |
1728 | if (mask & HWCAP_MONT) | |
1729 | return "mont"; | |
1730 | if (mask & HWCAP_PAUSE) | |
1731 | return "pause"; | |
1732 | if (mask & HWCAP_CBCOND) | |
1733 | return "cbcond"; | |
1734 | if (mask & HWCAP_CRC32C) | |
1735 | return "crc32c"; | |
3d68f91c JM |
1736 | |
1737 | mask = mask >> 32; | |
1738 | if (mask & HWCAP2_FJATHPLUS) | |
1739 | return "fjathplus"; | |
1740 | if (mask & HWCAP2_VIS3B) | |
1741 | return "vis3b"; | |
1742 | if (mask & HWCAP2_ADP) | |
1743 | return "adp"; | |
1744 | if (mask & HWCAP2_SPARC5) | |
1745 | return "sparc5"; | |
1746 | if (mask & HWCAP2_MWAIT) | |
1747 | return "mwait"; | |
1748 | if (mask & HWCAP2_XMPMUL) | |
1749 | return "xmpmul"; | |
1750 | if (mask & HWCAP2_XMONT) | |
1751 | return "xmont"; | |
1752 | if (mask & HWCAP2_NSEC) | |
1753 | return "nsec"; | |
1754 | ||
4bafe00e DM |
1755 | return "UNKNOWN"; |
1756 | } | |
1757 | ||
252b5132 RH |
1758 | /* Subroutine of md_assemble to do the actual parsing. */ |
1759 | ||
a22b281c | 1760 | static int |
5a49b8ac | 1761 | sparc_ip (char *str, const struct sparc_opcode **pinsn) |
252b5132 | 1762 | { |
e0471c16 | 1763 | const char *error_message = ""; |
252b5132 RH |
1764 | char *s; |
1765 | const char *args; | |
1766 | char c; | |
1767 | const struct sparc_opcode *insn; | |
1768 | char *argsStart; | |
1769 | unsigned long opcode; | |
1770 | unsigned int mask = 0; | |
1771 | int match = 0; | |
1772 | int comma = 0; | |
1773 | int v9_arg_p; | |
a22b281c | 1774 | int special_case = SPECIAL_CASE_NONE; |
252b5132 RH |
1775 | |
1776 | s = str; | |
3882b010 | 1777 | if (ISLOWER (*s)) |
252b5132 RH |
1778 | { |
1779 | do | |
1780 | ++s; | |
6cda1326 | 1781 | while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_'); |
252b5132 RH |
1782 | } |
1783 | ||
1784 | switch (*s) | |
1785 | { | |
1786 | case '\0': | |
1787 | break; | |
1788 | ||
1789 | case ',': | |
1790 | comma = 1; | |
e0c6ed95 | 1791 | /* Fall through. */ |
252b5132 RH |
1792 | |
1793 | case ' ': | |
1794 | *s++ = '\0'; | |
1795 | break; | |
1796 | ||
1797 | default: | |
b0825cc2 DM |
1798 | as_bad (_("Unknown opcode: `%s'"), str); |
1799 | *pinsn = NULL; | |
1800 | return special_case; | |
252b5132 RH |
1801 | } |
1802 | insn = (struct sparc_opcode *) hash_find (op_hash, str); | |
1803 | *pinsn = insn; | |
1804 | if (insn == NULL) | |
1805 | { | |
1806 | as_bad (_("Unknown opcode: `%s'"), str); | |
a22b281c | 1807 | return special_case; |
252b5132 RH |
1808 | } |
1809 | if (comma) | |
1810 | { | |
1811 | *--s = ','; | |
1812 | } | |
1813 | ||
1814 | argsStart = s; | |
1815 | for (;;) | |
1816 | { | |
1817 | opcode = insn->match; | |
1818 | memset (&the_insn, '\0', sizeof (the_insn)); | |
1819 | the_insn.reloc = BFD_RELOC_NONE; | |
1820 | v9_arg_p = 0; | |
1821 | ||
e0c6ed95 AM |
1822 | /* Build the opcode, checking as we go to make sure that the |
1823 | operands match. */ | |
252b5132 RH |
1824 | for (args = insn->args;; ++args) |
1825 | { | |
1826 | switch (*args) | |
1827 | { | |
1828 | case 'K': | |
1829 | { | |
1830 | int kmask = 0; | |
1831 | ||
1832 | /* Parse a series of masks. */ | |
1833 | if (*s == '#') | |
1834 | { | |
1835 | while (*s == '#') | |
1836 | { | |
91d6fa6a | 1837 | int jmask; |
252b5132 RH |
1838 | |
1839 | if (! parse_keyword_arg (sparc_encode_membar, &s, | |
91d6fa6a | 1840 | &jmask)) |
252b5132 RH |
1841 | { |
1842 | error_message = _(": invalid membar mask name"); | |
1843 | goto error; | |
1844 | } | |
91d6fa6a | 1845 | kmask |= jmask; |
47926f60 KH |
1846 | while (*s == ' ') |
1847 | ++s; | |
252b5132 RH |
1848 | if (*s == '|' || *s == '+') |
1849 | ++s; | |
47926f60 KH |
1850 | while (*s == ' ') |
1851 | ++s; | |
252b5132 RH |
1852 | } |
1853 | } | |
1854 | else | |
1855 | { | |
1856 | if (! parse_const_expr_arg (&s, &kmask)) | |
1857 | { | |
1858 | error_message = _(": invalid membar mask expression"); | |
1859 | goto error; | |
1860 | } | |
1861 | if (kmask < 0 || kmask > 127) | |
1862 | { | |
1863 | error_message = _(": invalid membar mask number"); | |
1864 | goto error; | |
1865 | } | |
1866 | } | |
1867 | ||
1868 | opcode |= MEMBAR (kmask); | |
1869 | continue; | |
1870 | } | |
1871 | ||
19f7b010 JJ |
1872 | case '3': |
1873 | { | |
1874 | int smask = 0; | |
1875 | ||
1876 | if (! parse_const_expr_arg (&s, &smask)) | |
1877 | { | |
1878 | error_message = _(": invalid siam mode expression"); | |
1879 | goto error; | |
1880 | } | |
1881 | if (smask < 0 || smask > 7) | |
1882 | { | |
1883 | error_message = _(": invalid siam mode number"); | |
1884 | goto error; | |
1885 | } | |
1886 | opcode |= smask; | |
1887 | continue; | |
1888 | } | |
1889 | ||
252b5132 RH |
1890 | case '*': |
1891 | { | |
1892 | int fcn = 0; | |
1893 | ||
1894 | /* Parse a prefetch function. */ | |
1895 | if (*s == '#') | |
1896 | { | |
1897 | if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) | |
1898 | { | |
1899 | error_message = _(": invalid prefetch function name"); | |
1900 | goto error; | |
1901 | } | |
1902 | } | |
1903 | else | |
1904 | { | |
1905 | if (! parse_const_expr_arg (&s, &fcn)) | |
1906 | { | |
1907 | error_message = _(": invalid prefetch function expression"); | |
1908 | goto error; | |
1909 | } | |
1910 | if (fcn < 0 || fcn > 31) | |
1911 | { | |
1912 | error_message = _(": invalid prefetch function number"); | |
1913 | goto error; | |
1914 | } | |
1915 | } | |
1916 | opcode |= RD (fcn); | |
1917 | continue; | |
1918 | } | |
1919 | ||
1920 | case '!': | |
1921 | case '?': | |
1922 | /* Parse a sparc64 privileged register. */ | |
1923 | if (*s == '%') | |
1924 | { | |
8b8c7c9f | 1925 | struct priv_reg_entry *p; |
e0c6ed95 | 1926 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1927 | |
1928 | s += 1; | |
8b8c7c9f JM |
1929 | for (p = priv_reg_table; p->name; p++) |
1930 | if (p->name[0] == s[0]) | |
1931 | { | |
1932 | len = strlen (p->name); | |
1933 | if (strncmp (p->name, s, len) == 0) | |
1934 | break; | |
1935 | } | |
1936 | ||
1937 | if (!p->name) | |
252b5132 RH |
1938 | { |
1939 | error_message = _(": unrecognizable privileged register"); | |
1940 | goto error; | |
1941 | } | |
96074adc JM |
1942 | |
1943 | if (((opcode >> (*args == '?' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) | |
1944 | { | |
1945 | error_message = _(": unrecognizable privileged register"); | |
1946 | goto error; | |
1947 | } | |
1948 | ||
252b5132 RH |
1949 | s += len; |
1950 | continue; | |
1951 | } | |
1952 | else | |
1953 | { | |
1954 | error_message = _(": unrecognizable privileged register"); | |
1955 | goto error; | |
1956 | } | |
1957 | ||
10156f83 DM |
1958 | case '$': |
1959 | case '%': | |
1960 | /* Parse a sparc64 hyperprivileged register. */ | |
1961 | if (*s == '%') | |
1962 | { | |
8b8c7c9f | 1963 | struct priv_reg_entry *p; |
10156f83 DM |
1964 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
1965 | ||
1966 | s += 1; | |
8b8c7c9f JM |
1967 | for (p = hpriv_reg_table; p->name; p++) |
1968 | if (p->name[0] == s[0]) | |
1969 | { | |
1970 | len = strlen (p->name); | |
1971 | if (strncmp (p->name, s, len) == 0) | |
1972 | break; | |
1973 | } | |
1974 | ||
1975 | if (!p->name) | |
10156f83 DM |
1976 | { |
1977 | error_message = _(": unrecognizable hyperprivileged register"); | |
1978 | goto error; | |
1979 | } | |
96074adc JM |
1980 | |
1981 | if (((opcode >> (*args == '$' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) | |
1982 | { | |
1983 | error_message = _(": unrecognizable hyperprivileged register"); | |
1984 | goto error; | |
1985 | } | |
1986 | ||
1987 | s += len; | |
10156f83 DM |
1988 | continue; |
1989 | } | |
1990 | else | |
1991 | { | |
1992 | error_message = _(": unrecognizable hyperprivileged register"); | |
1993 | goto error; | |
1994 | } | |
1995 | ||
252b5132 RH |
1996 | case '_': |
1997 | case '/': | |
7a10c22f | 1998 | /* Parse a v9a or later ancillary state register. */ |
252b5132 RH |
1999 | if (*s == '%') |
2000 | { | |
8b8c7c9f | 2001 | struct priv_reg_entry *p; |
e0c6ed95 | 2002 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
2003 | |
2004 | s += 1; | |
8b8c7c9f JM |
2005 | for (p = v9a_asr_table; p->name; p++) |
2006 | if (p->name[0] == s[0]) | |
2007 | { | |
2008 | len = strlen (p->name); | |
2009 | if (strncmp (p->name, s, len) == 0) | |
2010 | break; | |
2011 | } | |
2012 | ||
2013 | if (!p->name) | |
252b5132 | 2014 | { |
7a10c22f | 2015 | error_message = _(": unrecognizable ancillary state register"); |
252b5132 RH |
2016 | goto error; |
2017 | } | |
96074adc JM |
2018 | |
2019 | if (((opcode >> (*args == '/' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) | |
2020 | { | |
2021 | error_message = _(": unrecognizable ancillary state register"); | |
2022 | goto error; | |
2023 | } | |
2024 | ||
252b5132 RH |
2025 | s += len; |
2026 | continue; | |
2027 | } | |
2028 | else | |
2029 | { | |
7a10c22f | 2030 | error_message = _(": unrecognizable ancillary state register"); |
252b5132 RH |
2031 | goto error; |
2032 | } | |
2033 | ||
2034 | case 'M': | |
2035 | case 'm': | |
2036 | if (strncmp (s, "%asr", 4) == 0) | |
2037 | { | |
2038 | s += 4; | |
2039 | ||
3882b010 | 2040 | if (ISDIGIT (*s)) |
252b5132 RH |
2041 | { |
2042 | long num = 0; | |
2043 | ||
3882b010 | 2044 | while (ISDIGIT (*s)) |
252b5132 RH |
2045 | { |
2046 | num = num * 10 + *s - '0'; | |
2047 | ++s; | |
2048 | } | |
2049 | ||
f65c3d1b JM |
2050 | /* We used to check here for the asr number to |
2051 | be between 16 and 31 in V9 and later, as | |
2052 | mandated by the section C.1.1 "Register | |
2053 | Names" in the SPARC spec. However, we | |
2054 | decided to remove this restriction as a) it | |
2055 | introduces problems when new V9 asr registers | |
2056 | are introduced, b) the Solaris assembler | |
2057 | doesn't implement this restriction and c) the | |
2058 | restriction will go away in future revisions | |
2059 | of the Oracle SPARC Architecture. */ | |
2060 | ||
2061 | if (num < 0 || 31 < num) | |
2062 | { | |
2063 | error_message = _(": asr number must be between 0 and 31"); | |
2064 | goto error; | |
2065 | } | |
252b5132 RH |
2066 | |
2067 | opcode |= (*args == 'M' ? RS1 (num) : RD (num)); | |
2068 | continue; | |
2069 | } | |
2070 | else | |
2071 | { | |
2072 | error_message = _(": expecting %asrN"); | |
2073 | goto error; | |
2074 | } | |
e0c6ed95 | 2075 | } /* if %asr */ |
252b5132 RH |
2076 | break; |
2077 | ||
2078 | case 'I': | |
2079 | the_insn.reloc = BFD_RELOC_SPARC_11; | |
2080 | goto immediate; | |
2081 | ||
2082 | case 'j': | |
2083 | the_insn.reloc = BFD_RELOC_SPARC_10; | |
2084 | goto immediate; | |
2085 | ||
6cda1326 DM |
2086 | case ')': |
2087 | if (*s == ' ') | |
2088 | s++; | |
2089 | if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2])) | |
2090 | || ISDIGIT (*s)) | |
2091 | { | |
2092 | long num = 0; | |
2093 | ||
2094 | if (s[0] == '0' && s[1] == 'x') | |
2095 | { | |
2096 | s += 2; | |
2097 | while (ISXDIGIT (*s)) | |
2098 | { | |
2099 | num <<= 4; | |
2100 | num |= hex_value (*s); | |
2101 | ++s; | |
2102 | } | |
2103 | } | |
2104 | else | |
2105 | { | |
2106 | while (ISDIGIT (*s)) | |
2107 | { | |
2108 | num = num * 10 + *s - '0'; | |
2109 | ++s; | |
2110 | } | |
2111 | } | |
2112 | if (num < 0 || num > 31) | |
2113 | { | |
2114 | error_message = _(": crypto immediate must be between 0 and 31"); | |
2115 | goto error; | |
2116 | } | |
2117 | ||
2118 | opcode |= RS3 (num); | |
2119 | continue; | |
2120 | } | |
2121 | else | |
2122 | { | |
2123 | error_message = _(": expecting crypto immediate"); | |
2124 | goto error; | |
2125 | } | |
2126 | ||
252b5132 RH |
2127 | case 'X': |
2128 | /* V8 systems don't understand BFD_RELOC_SPARC_5. */ | |
2129 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2130 | the_insn.reloc = BFD_RELOC_SPARC_5; | |
2131 | else | |
2132 | the_insn.reloc = BFD_RELOC_SPARC13; | |
2133 | /* These fields are unsigned, but for upward compatibility, | |
2134 | allow negative values as well. */ | |
2135 | goto immediate; | |
2136 | ||
2137 | case 'Y': | |
2138 | /* V8 systems don't understand BFD_RELOC_SPARC_6. */ | |
2139 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2140 | the_insn.reloc = BFD_RELOC_SPARC_6; | |
2141 | else | |
2142 | the_insn.reloc = BFD_RELOC_SPARC13; | |
2143 | /* These fields are unsigned, but for upward compatibility, | |
2144 | allow negative values as well. */ | |
2145 | goto immediate; | |
2146 | ||
2147 | case 'k': | |
2148 | the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; | |
2149 | the_insn.pcrel = 1; | |
2150 | goto immediate; | |
2151 | ||
2615994e DM |
2152 | case '=': |
2153 | the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10; | |
2154 | the_insn.pcrel = 1; | |
2155 | goto immediate; | |
2156 | ||
252b5132 RH |
2157 | case 'G': |
2158 | the_insn.reloc = BFD_RELOC_SPARC_WDISP19; | |
2159 | the_insn.pcrel = 1; | |
2160 | goto immediate; | |
2161 | ||
2162 | case 'N': | |
2163 | if (*s == 'p' && s[1] == 'n') | |
2164 | { | |
2165 | s += 2; | |
2166 | continue; | |
2167 | } | |
2168 | break; | |
2169 | ||
2170 | case 'T': | |
2171 | if (*s == 'p' && s[1] == 't') | |
2172 | { | |
2173 | s += 2; | |
2174 | continue; | |
2175 | } | |
2176 | break; | |
2177 | ||
2178 | case 'z': | |
2179 | if (*s == ' ') | |
2180 | { | |
2181 | ++s; | |
2182 | } | |
f9911beb JM |
2183 | if ((strncmp (s, "%icc", 4) == 0) |
2184 | || (sparc_arch_size == 32 && strncmp (s, "%ncc", 4) == 0)) | |
252b5132 RH |
2185 | { |
2186 | s += 4; | |
2187 | continue; | |
2188 | } | |
2189 | break; | |
2190 | ||
2191 | case 'Z': | |
2192 | if (*s == ' ') | |
2193 | { | |
2194 | ++s; | |
2195 | } | |
f9911beb JM |
2196 | if ((strncmp (s, "%xcc", 4) == 0) |
2197 | || (sparc_arch_size == 64 && strncmp (s, "%ncc", 4) == 0)) | |
252b5132 RH |
2198 | { |
2199 | s += 4; | |
2200 | continue; | |
2201 | } | |
2202 | break; | |
2203 | ||
2204 | case '6': | |
2205 | if (*s == ' ') | |
2206 | { | |
2207 | ++s; | |
2208 | } | |
2209 | if (strncmp (s, "%fcc0", 5) == 0) | |
2210 | { | |
2211 | s += 5; | |
2212 | continue; | |
2213 | } | |
2214 | break; | |
2215 | ||
2216 | case '7': | |
2217 | if (*s == ' ') | |
2218 | { | |
2219 | ++s; | |
2220 | } | |
2221 | if (strncmp (s, "%fcc1", 5) == 0) | |
2222 | { | |
2223 | s += 5; | |
2224 | continue; | |
2225 | } | |
2226 | break; | |
2227 | ||
2228 | case '8': | |
2229 | if (*s == ' ') | |
2230 | { | |
2231 | ++s; | |
2232 | } | |
2233 | if (strncmp (s, "%fcc2", 5) == 0) | |
2234 | { | |
2235 | s += 5; | |
2236 | continue; | |
2237 | } | |
2238 | break; | |
2239 | ||
2240 | case '9': | |
2241 | if (*s == ' ') | |
2242 | { | |
2243 | ++s; | |
2244 | } | |
2245 | if (strncmp (s, "%fcc3", 5) == 0) | |
2246 | { | |
2247 | s += 5; | |
2248 | continue; | |
2249 | } | |
2250 | break; | |
2251 | ||
2252 | case 'P': | |
2253 | if (strncmp (s, "%pc", 3) == 0) | |
2254 | { | |
2255 | s += 3; | |
2256 | continue; | |
2257 | } | |
2258 | break; | |
2259 | ||
2260 | case 'W': | |
2261 | if (strncmp (s, "%tick", 5) == 0) | |
2262 | { | |
2263 | s += 5; | |
2264 | continue; | |
2265 | } | |
2266 | break; | |
2267 | ||
e0c6ed95 | 2268 | case '\0': /* End of args. */ |
b9734f35 | 2269 | if (s[0] == ',' && s[1] == '%') |
252b5132 | 2270 | { |
b9734f35 JJ |
2271 | char *s1; |
2272 | int npar = 0; | |
8b8c7c9f | 2273 | const struct perc_entry *p; |
b9734f35 | 2274 | |
8b8c7c9f JM |
2275 | for (p = perc_table; p->type != perc_entry_none; p++) |
2276 | if ((p->type == perc_entry_post_pop || p->type == perc_entry_reg) | |
2277 | && strncmp (s + 2, p->name, p->len) == 0) | |
2278 | break; | |
2279 | if (p->type == perc_entry_none || p->type == perc_entry_reg) | |
2280 | break; | |
b9734f35 | 2281 | |
8b8c7c9f | 2282 | if (s[p->len + 2] != '(') |
b9734f35 | 2283 | { |
8b8c7c9f | 2284 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); |
b9734f35 JJ |
2285 | return special_case; |
2286 | } | |
2287 | ||
8b8c7c9f JM |
2288 | if (! (p->pop->flags & F_POP_TLS_CALL) |
2289 | && the_insn.reloc != BFD_RELOC_NONE) | |
b9734f35 JJ |
2290 | { |
2291 | as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), | |
8b8c7c9f | 2292 | p->name); |
b9734f35 JJ |
2293 | return special_case; |
2294 | } | |
2295 | ||
8b8c7c9f | 2296 | if ((p->pop->flags & F_POP_TLS_CALL) |
b9734f35 JJ |
2297 | && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 |
2298 | || the_insn.exp.X_add_number != 0 | |
2299 | || the_insn.exp.X_add_symbol | |
2300 | != symbol_find_or_make ("__tls_get_addr"))) | |
2301 | { | |
2302 | as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), | |
8b8c7c9f | 2303 | p->name); |
b9734f35 JJ |
2304 | return special_case; |
2305 | } | |
2306 | ||
8b8c7c9f | 2307 | the_insn.reloc = p->pop->reloc; |
b9734f35 | 2308 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
8b8c7c9f | 2309 | s += p->len + 3; |
b9734f35 JJ |
2310 | |
2311 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2312 | if (*s1 == '(') | |
2313 | npar++; | |
2314 | else if (*s1 == ')') | |
2315 | { | |
2316 | if (!npar) | |
2317 | break; | |
2318 | npar--; | |
2319 | } | |
2320 | ||
2321 | if (*s1 != ')') | |
2322 | { | |
8b8c7c9f | 2323 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); |
b9734f35 JJ |
2324 | return special_case; |
2325 | } | |
2326 | ||
2327 | *s1 = '\0'; | |
2328 | (void) get_expression (s); | |
2329 | *s1 = ')'; | |
2330 | s = s1 + 1; | |
252b5132 | 2331 | } |
b9734f35 JJ |
2332 | if (*s == '\0') |
2333 | match = 1; | |
252b5132 RH |
2334 | break; |
2335 | ||
2336 | case '+': | |
2337 | if (*s == '+') | |
2338 | { | |
2339 | ++s; | |
2340 | continue; | |
2341 | } | |
2342 | if (*s == '-') | |
2343 | { | |
2344 | continue; | |
2345 | } | |
2346 | break; | |
2347 | ||
e0c6ed95 | 2348 | case '[': /* These must match exactly. */ |
252b5132 RH |
2349 | case ']': |
2350 | case ',': | |
2351 | case ' ': | |
2352 | if (*s++ == *args) | |
2353 | continue; | |
2354 | break; | |
2355 | ||
e0c6ed95 | 2356 | case '#': /* Must be at least one digit. */ |
3882b010 | 2357 | if (ISDIGIT (*s++)) |
252b5132 | 2358 | { |
3882b010 | 2359 | while (ISDIGIT (*s)) |
252b5132 RH |
2360 | { |
2361 | ++s; | |
2362 | } | |
2363 | continue; | |
2364 | } | |
2365 | break; | |
2366 | ||
e0c6ed95 | 2367 | case 'C': /* Coprocessor state register. */ |
252b5132 RH |
2368 | if (strncmp (s, "%csr", 4) == 0) |
2369 | { | |
2370 | s += 4; | |
2371 | continue; | |
2372 | } | |
2373 | break; | |
2374 | ||
e0c6ed95 | 2375 | case 'b': /* Next operand is a coprocessor register. */ |
252b5132 RH |
2376 | case 'c': |
2377 | case 'D': | |
3882b010 | 2378 | if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) |
252b5132 RH |
2379 | { |
2380 | mask = *s++; | |
3882b010 | 2381 | if (ISDIGIT (*s)) |
252b5132 RH |
2382 | { |
2383 | mask = 10 * (mask - '0') + (*s++ - '0'); | |
2384 | if (mask >= 32) | |
2385 | { | |
2386 | break; | |
2387 | } | |
2388 | } | |
2389 | else | |
2390 | { | |
2391 | mask -= '0'; | |
2392 | } | |
2393 | switch (*args) | |
2394 | { | |
2395 | ||
2396 | case 'b': | |
2397 | opcode |= mask << 14; | |
2398 | continue; | |
2399 | ||
2400 | case 'c': | |
2401 | opcode |= mask; | |
2402 | continue; | |
2403 | ||
2404 | case 'D': | |
2405 | opcode |= mask << 25; | |
2406 | continue; | |
2407 | } | |
2408 | } | |
2409 | break; | |
2410 | ||
2411 | case 'r': /* next operand must be a register */ | |
2412 | case 'O': | |
2413 | case '1': | |
2414 | case '2': | |
2415 | case 'd': | |
2416 | if (*s++ == '%') | |
2417 | { | |
2418 | switch (c = *s++) | |
2419 | { | |
2420 | ||
2421 | case 'f': /* frame pointer */ | |
2422 | if (*s++ == 'p') | |
2423 | { | |
2424 | mask = 0x1e; | |
2425 | break; | |
2426 | } | |
2427 | goto error; | |
2428 | ||
2429 | case 'g': /* global register */ | |
a22b281c RH |
2430 | c = *s++; |
2431 | if (isoctal (c)) | |
252b5132 RH |
2432 | { |
2433 | mask = c - '0'; | |
2434 | break; | |
2435 | } | |
2436 | goto error; | |
2437 | ||
2438 | case 'i': /* in register */ | |
a22b281c RH |
2439 | c = *s++; |
2440 | if (isoctal (c)) | |
252b5132 RH |
2441 | { |
2442 | mask = c - '0' + 24; | |
2443 | break; | |
2444 | } | |
2445 | goto error; | |
2446 | ||
2447 | case 'l': /* local register */ | |
a22b281c RH |
2448 | c = *s++; |
2449 | if (isoctal (c)) | |
252b5132 RH |
2450 | { |
2451 | mask = (c - '0' + 16); | |
2452 | break; | |
2453 | } | |
2454 | goto error; | |
2455 | ||
2456 | case 'o': /* out register */ | |
a22b281c RH |
2457 | c = *s++; |
2458 | if (isoctal (c)) | |
252b5132 RH |
2459 | { |
2460 | mask = (c - '0' + 8); | |
2461 | break; | |
2462 | } | |
2463 | goto error; | |
2464 | ||
2465 | case 's': /* stack pointer */ | |
2466 | if (*s++ == 'p') | |
2467 | { | |
2468 | mask = 0xe; | |
2469 | break; | |
2470 | } | |
2471 | goto error; | |
2472 | ||
2473 | case 'r': /* any register */ | |
3882b010 | 2474 | if (!ISDIGIT ((c = *s++))) |
252b5132 RH |
2475 | { |
2476 | goto error; | |
2477 | } | |
2478 | /* FALLTHROUGH */ | |
2479 | case '0': | |
2480 | case '1': | |
2481 | case '2': | |
2482 | case '3': | |
2483 | case '4': | |
2484 | case '5': | |
2485 | case '6': | |
2486 | case '7': | |
2487 | case '8': | |
2488 | case '9': | |
3882b010 | 2489 | if (ISDIGIT (*s)) |
252b5132 RH |
2490 | { |
2491 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) | |
2492 | { | |
2493 | goto error; | |
2494 | } | |
2495 | } | |
2496 | else | |
2497 | { | |
2498 | c -= '0'; | |
2499 | } | |
2500 | mask = c; | |
2501 | break; | |
2502 | ||
2503 | default: | |
2504 | goto error; | |
2505 | } | |
2506 | ||
6d8809aa | 2507 | if ((mask & ~1) == 2 && sparc_arch_size == 64 |
e0c6ed95 | 2508 | && no_undeclared_regs && ! globals[mask]) |
79bd78be | 2509 | as_bad (_("detected global register use not covered by .register pseudo-op")); |
6d8809aa | 2510 | |
252b5132 RH |
2511 | /* Got the register, now figure out where |
2512 | it goes in the opcode. */ | |
2513 | switch (*args) | |
2514 | { | |
2515 | case '1': | |
2516 | opcode |= mask << 14; | |
2517 | continue; | |
2518 | ||
2519 | case '2': | |
2520 | opcode |= mask; | |
2521 | continue; | |
2522 | ||
2523 | case 'd': | |
2524 | opcode |= mask << 25; | |
2525 | continue; | |
2526 | ||
2527 | case 'r': | |
2528 | opcode |= (mask << 25) | (mask << 14); | |
2529 | continue; | |
2530 | ||
2531 | case 'O': | |
2532 | opcode |= (mask << 25) | (mask << 0); | |
2533 | continue; | |
2534 | } | |
2535 | } | |
2536 | break; | |
2537 | ||
2538 | case 'e': /* next operand is a floating point register */ | |
2539 | case 'v': | |
2540 | case 'V': | |
2541 | ||
2542 | case 'f': | |
2543 | case 'B': | |
2544 | case 'R': | |
2545 | ||
ea783ef3 DM |
2546 | case '4': |
2547 | case '5': | |
2548 | ||
252b5132 RH |
2549 | case 'g': |
2550 | case 'H': | |
2551 | case 'J': | |
3d68f91c | 2552 | case '}': |
252b5132 RH |
2553 | { |
2554 | char format; | |
2555 | ||
2556 | if (*s++ == '%' | |
ec892a07 JM |
2557 | && ((format = *s) == 'f' |
2558 | || format == 'd' | |
2559 | || format == 'q') | |
3882b010 | 2560 | && ISDIGIT (*++s)) |
252b5132 | 2561 | { |
3882b010 | 2562 | for (mask = 0; ISDIGIT (*s); ++s) |
252b5132 RH |
2563 | { |
2564 | mask = 10 * mask + (*s - '0'); | |
2565 | } /* read the number */ | |
2566 | ||
2567 | if ((*args == 'v' | |
2568 | || *args == 'B' | |
ea783ef3 | 2569 | || *args == '5' |
ec892a07 JM |
2570 | || *args == 'H' |
2571 | || format == 'd') | |
252b5132 RH |
2572 | && (mask & 1)) |
2573 | { | |
ec892a07 | 2574 | /* register must be even numbered */ |
252b5132 | 2575 | break; |
ec892a07 | 2576 | } |
252b5132 RH |
2577 | |
2578 | if ((*args == 'V' | |
2579 | || *args == 'R' | |
ec892a07 JM |
2580 | || *args == 'J' |
2581 | || format == 'q') | |
252b5132 RH |
2582 | && (mask & 3)) |
2583 | { | |
ec892a07 | 2584 | /* register must be multiple of 4 */ |
252b5132 | 2585 | break; |
ec892a07 | 2586 | } |
252b5132 RH |
2587 | |
2588 | if (mask >= 64) | |
2589 | { | |
2590 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2591 | error_message = _(": There are only 64 f registers; [0-63]"); | |
2592 | else | |
2593 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2594 | goto error; | |
2595 | } /* on error */ | |
2596 | else if (mask >= 32) | |
2597 | { | |
2598 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2599 | { | |
26664553 JJ |
2600 | if (*args == 'e' || *args == 'f' || *args == 'g') |
2601 | { | |
2602 | error_message | |
2603 | = _(": There are only 32 single precision f registers; [0-31]"); | |
2604 | goto error; | |
2605 | } | |
252b5132 RH |
2606 | v9_arg_p = 1; |
2607 | mask -= 31; /* wrap high bit */ | |
2608 | } | |
2609 | else | |
2610 | { | |
2611 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2612 | goto error; | |
2613 | } | |
2614 | } | |
2615 | } | |
2616 | else | |
2617 | { | |
2618 | break; | |
ab3e48dc | 2619 | } /* if not an 'f' register. */ |
252b5132 | 2620 | |
3d68f91c JM |
2621 | if (*args == '}' && mask != RS2 (opcode)) |
2622 | { | |
2623 | error_message | |
2624 | = _(": Instruction requires frs2 and frsd must be the same register"); | |
2625 | goto error; | |
2626 | } | |
2627 | ||
252b5132 RH |
2628 | switch (*args) |
2629 | { | |
2630 | case 'v': | |
2631 | case 'V': | |
2632 | case 'e': | |
2633 | opcode |= RS1 (mask); | |
2634 | continue; | |
2635 | ||
252b5132 RH |
2636 | case 'f': |
2637 | case 'B': | |
2638 | case 'R': | |
2639 | opcode |= RS2 (mask); | |
2640 | continue; | |
2641 | ||
ea783ef3 DM |
2642 | case '4': |
2643 | case '5': | |
2644 | opcode |= RS3 (mask); | |
2645 | continue; | |
2646 | ||
252b5132 RH |
2647 | case 'g': |
2648 | case 'H': | |
2649 | case 'J': | |
3d68f91c | 2650 | case '}': |
252b5132 RH |
2651 | opcode |= RD (mask); |
2652 | continue; | |
ab3e48dc | 2653 | } /* Pack it in. */ |
252b5132 RH |
2654 | |
2655 | know (0); | |
2656 | break; | |
ab3e48dc | 2657 | } /* float arg */ |
252b5132 RH |
2658 | |
2659 | case 'F': | |
2660 | if (strncmp (s, "%fsr", 4) == 0) | |
2661 | { | |
2662 | s += 4; | |
2663 | continue; | |
2664 | } | |
2665 | break; | |
2666 | ||
ea783ef3 DM |
2667 | case '(': |
2668 | if (strncmp (s, "%efsr", 5) == 0) | |
2669 | { | |
2670 | s += 5; | |
2671 | continue; | |
2672 | } | |
2673 | break; | |
2674 | ||
ab3e48dc KH |
2675 | case '0': /* 64 bit immediate (set, setsw, setx insn) */ |
2676 | the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ | |
252b5132 RH |
2677 | goto immediate; |
2678 | ||
ab3e48dc | 2679 | case 'l': /* 22 bit PC relative immediate */ |
252b5132 RH |
2680 | the_insn.reloc = BFD_RELOC_SPARC_WDISP22; |
2681 | the_insn.pcrel = 1; | |
2682 | goto immediate; | |
2683 | ||
ab3e48dc | 2684 | case 'L': /* 30 bit immediate */ |
252b5132 RH |
2685 | the_insn.reloc = BFD_RELOC_32_PCREL_S2; |
2686 | the_insn.pcrel = 1; | |
2687 | goto immediate; | |
2688 | ||
63fab58c | 2689 | case 'h': |
ab3e48dc | 2690 | case 'n': /* 22 bit immediate */ |
252b5132 RH |
2691 | the_insn.reloc = BFD_RELOC_SPARC22; |
2692 | goto immediate; | |
2693 | ||
ab3e48dc | 2694 | case 'i': /* 13 bit immediate */ |
252b5132 RH |
2695 | the_insn.reloc = BFD_RELOC_SPARC13; |
2696 | ||
2697 | /* fallthrough */ | |
2698 | ||
2699 | immediate: | |
2700 | if (*s == ' ') | |
2701 | s++; | |
2702 | ||
cf9a1301 RH |
2703 | { |
2704 | char *s1; | |
e0471c16 | 2705 | const char *op_arg = NULL; |
30eb9c17 | 2706 | static expressionS op_exp; |
cf9a1301 RH |
2707 | bfd_reloc_code_real_type old_reloc = the_insn.reloc; |
2708 | ||
2709 | /* Check for %hi, etc. */ | |
2710 | if (*s == '%') | |
2711 | { | |
8b8c7c9f JM |
2712 | const struct perc_entry *p; |
2713 | ||
2714 | for (p = perc_table; p->type != perc_entry_none; p++) | |
2715 | if ((p->type == perc_entry_imm_pop || p->type == perc_entry_reg) | |
2716 | && strncmp (s + 1, p->name, p->len) == 0) | |
2717 | break; | |
2718 | if (p->type == perc_entry_none || p->type == perc_entry_reg) | |
2719 | break; | |
2720 | ||
2721 | if (s[p->len + 1] != '(') | |
cf9a1301 | 2722 | { |
8b8c7c9f | 2723 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); |
a22b281c | 2724 | return special_case; |
cf9a1301 | 2725 | } |
252b5132 | 2726 | |
8b8c7c9f JM |
2727 | op_arg = p->name; |
2728 | the_insn.reloc = p->pop->reloc; | |
2729 | s += p->len + 2; | |
2730 | v9_arg_p = p->pop->flags & F_POP_V9; | |
cf9a1301 RH |
2731 | } |
2732 | ||
2733 | /* Note that if the get_expression() fails, we will still | |
2734 | have created U entries in the symbol table for the | |
2735 | 'symbols' in the input string. Try not to create U | |
2736 | symbols for registers, etc. */ | |
252b5132 | 2737 | |
252b5132 RH |
2738 | /* This stuff checks to see if the expression ends in |
2739 | +%reg. If it does, it removes the register from | |
2740 | the expression, and re-sets 's' to point to the | |
2741 | right place. */ | |
2742 | ||
cf9a1301 RH |
2743 | if (op_arg) |
2744 | { | |
2745 | int npar = 0; | |
2746 | ||
2747 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2748 | if (*s1 == '(') | |
2749 | npar++; | |
2750 | else if (*s1 == ')') | |
2751 | { | |
2752 | if (!npar) | |
2753 | break; | |
2754 | npar--; | |
2755 | } | |
2756 | ||
2757 | if (*s1 != ')') | |
2758 | { | |
2759 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); | |
a22b281c | 2760 | return special_case; |
cf9a1301 | 2761 | } |
e0c6ed95 | 2762 | |
cf9a1301 RH |
2763 | *s1 = '\0'; |
2764 | (void) get_expression (s); | |
2765 | *s1 = ')'; | |
e140100a NC |
2766 | if (expr_end != s1) |
2767 | { | |
2768 | as_bad (_("Expression inside %%%s could not be parsed"), op_arg); | |
2769 | return special_case; | |
2770 | } | |
cf9a1301 RH |
2771 | s = s1 + 1; |
2772 | if (*s == ',' || *s == ']' || !*s) | |
2773 | continue; | |
2774 | if (*s != '+' && *s != '-') | |
2775 | { | |
2776 | as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); | |
a22b281c | 2777 | return special_case; |
cf9a1301 RH |
2778 | } |
2779 | *s1 = '0'; | |
2780 | s = s1; | |
2781 | op_exp = the_insn.exp; | |
e0c6ed95 | 2782 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
cf9a1301 | 2783 | } |
252b5132 | 2784 | |
e0c6ed95 AM |
2785 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) |
2786 | ; | |
252b5132 | 2787 | |
3882b010 | 2788 | if (s1 != s && ISDIGIT (s1[-1])) |
252b5132 RH |
2789 | { |
2790 | if (s1[-2] == '%' && s1[-3] == '+') | |
cf9a1301 | 2791 | s1 -= 3; |
f124dd4f | 2792 | else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') |
cf9a1301 | 2793 | s1 -= 4; |
f124dd4f DM |
2794 | else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+') |
2795 | s1 -= 5; | |
cf9a1301 RH |
2796 | else |
2797 | s1 = NULL; | |
2798 | if (s1) | |
252b5132 | 2799 | { |
252b5132 | 2800 | *s1 = '\0'; |
1eb7027c RH |
2801 | if (op_arg && s1 == s + 1) |
2802 | the_insn.exp.X_op = O_absent; | |
2803 | else | |
2804 | (void) get_expression (s); | |
252b5132 | 2805 | *s1 = '+'; |
cf9a1301 RH |
2806 | if (op_arg) |
2807 | *s = ')'; | |
252b5132 | 2808 | s = s1; |
252b5132 | 2809 | } |
cf9a1301 RH |
2810 | } |
2811 | else | |
2812 | s1 = NULL; | |
2813 | ||
2814 | if (!s1) | |
2815 | { | |
2816 | (void) get_expression (s); | |
2817 | if (op_arg) | |
2818 | *s = ')'; | |
2819 | s = expr_end; | |
2820 | } | |
2821 | ||
2822 | if (op_arg) | |
2823 | { | |
2824 | the_insn.exp2 = the_insn.exp; | |
2825 | the_insn.exp = op_exp; | |
2826 | if (the_insn.exp2.X_op == O_absent) | |
2827 | the_insn.exp2.X_op = O_illegal; | |
2828 | else if (the_insn.exp.X_op == O_absent) | |
252b5132 | 2829 | { |
cf9a1301 RH |
2830 | the_insn.exp = the_insn.exp2; |
2831 | the_insn.exp2.X_op = O_illegal; | |
2832 | } | |
2833 | else if (the_insn.exp.X_op == O_constant) | |
2834 | { | |
2835 | valueT val = the_insn.exp.X_add_number; | |
2836 | switch (the_insn.reloc) | |
2837 | { | |
1b50c718 ILT |
2838 | default: |
2839 | break; | |
2840 | ||
cf9a1301 RH |
2841 | case BFD_RELOC_SPARC_HH22: |
2842 | val = BSR (val, 32); | |
e0c6ed95 | 2843 | /* Fall through. */ |
cf9a1301 RH |
2844 | |
2845 | case BFD_RELOC_SPARC_LM22: | |
2846 | case BFD_RELOC_HI22: | |
2847 | val = (val >> 10) & 0x3fffff; | |
2848 | break; | |
2849 | ||
2850 | case BFD_RELOC_SPARC_HM10: | |
2851 | val = BSR (val, 32); | |
e0c6ed95 | 2852 | /* Fall through. */ |
cf9a1301 RH |
2853 | |
2854 | case BFD_RELOC_LO10: | |
2855 | val &= 0x3ff; | |
2856 | break; | |
2857 | ||
2615994e DM |
2858 | case BFD_RELOC_SPARC_H34: |
2859 | val >>= 12; | |
2860 | val &= 0x3fffff; | |
2861 | break; | |
2862 | ||
cf9a1301 RH |
2863 | case BFD_RELOC_SPARC_H44: |
2864 | val >>= 22; | |
2865 | val &= 0x3fffff; | |
2866 | break; | |
2867 | ||
2868 | case BFD_RELOC_SPARC_M44: | |
2869 | val >>= 12; | |
2870 | val &= 0x3ff; | |
2871 | break; | |
2872 | ||
2873 | case BFD_RELOC_SPARC_L44: | |
2874 | val &= 0xfff; | |
2875 | break; | |
2876 | ||
2877 | case BFD_RELOC_SPARC_HIX22: | |
ab3e48dc | 2878 | val = ~val; |
cf9a1301 RH |
2879 | val = (val >> 10) & 0x3fffff; |
2880 | break; | |
2881 | ||
2882 | case BFD_RELOC_SPARC_LOX10: | |
2883 | val = (val & 0x3ff) | 0x1c00; | |
2884 | break; | |
2885 | } | |
2886 | the_insn.exp = the_insn.exp2; | |
2887 | the_insn.exp.X_add_number += val; | |
2888 | the_insn.exp2.X_op = O_illegal; | |
2889 | the_insn.reloc = old_reloc; | |
2890 | } | |
2891 | else if (the_insn.exp2.X_op != O_constant) | |
2892 | { | |
2893 | as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); | |
a22b281c | 2894 | return special_case; |
cf9a1301 RH |
2895 | } |
2896 | else | |
2897 | { | |
dabe3bbc | 2898 | if (old_reloc != BFD_RELOC_SPARC13 |
cf9a1301 RH |
2899 | || the_insn.reloc != BFD_RELOC_LO10 |
2900 | || sparc_arch_size != 64 | |
2901 | || sparc_pic_code) | |
2902 | { | |
2903 | as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); | |
a22b281c | 2904 | return special_case; |
cf9a1301 RH |
2905 | } |
2906 | the_insn.reloc = BFD_RELOC_SPARC_OLO10; | |
252b5132 RH |
2907 | } |
2908 | } | |
2909 | } | |
252b5132 RH |
2910 | /* Check for constants that don't require emitting a reloc. */ |
2911 | if (the_insn.exp.X_op == O_constant | |
2912 | && the_insn.exp.X_add_symbol == 0 | |
2913 | && the_insn.exp.X_op_symbol == 0) | |
2914 | { | |
2915 | /* For pc-relative call instructions, we reject | |
2916 | constants to get better code. */ | |
2917 | if (the_insn.pcrel | |
2918 | && the_insn.reloc == BFD_RELOC_32_PCREL_S2 | |
2919 | && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) | |
2920 | { | |
2921 | error_message = _(": PC-relative operand can't be a constant"); | |
2922 | goto error; | |
2923 | } | |
2924 | ||
b9734f35 JJ |
2925 | if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 |
2926 | && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) | |
2927 | { | |
2928 | error_message = _(": TLS operand can't be a constant"); | |
2929 | goto error; | |
2930 | } | |
2931 | ||
55cf6793 | 2932 | /* Constants that won't fit are checked in md_apply_fix |
252b5132 RH |
2933 | and bfd_install_relocation. |
2934 | ??? It would be preferable to install the constants | |
2935 | into the insn here and save having to create a fixS | |
2936 | for each one. There already exists code to handle | |
55cf6793 | 2937 | all the various cases (e.g. in md_apply_fix and |
252b5132 RH |
2938 | bfd_install_relocation) so duplicating all that code |
2939 | here isn't right. */ | |
698544e1 DM |
2940 | |
2941 | /* This is a special case to handle cbcond instructions | |
2942 | properly, which can need two relocations. The first | |
2943 | one is for the 5-bit immediate field and the latter | |
2944 | is going to be for the WDISP10 branch part. We | |
2945 | handle the R_SPARC_5 immediate directly here so that | |
2946 | we don't need to add support for multiple relocations | |
2947 | in one instruction just yet. */ | |
2948 | if (the_insn.reloc == BFD_RELOC_SPARC_5) | |
2949 | { | |
2950 | valueT val = the_insn.exp.X_add_number; | |
2951 | ||
2952 | if (! in_bitfield_range (val, 0x1f)) | |
2953 | { | |
2954 | error_message = _(": Immediate value in cbcond is out of range."); | |
2955 | goto error; | |
2956 | } | |
2957 | opcode |= val & 0x1f; | |
2958 | the_insn.reloc = BFD_RELOC_NONE; | |
2959 | } | |
252b5132 RH |
2960 | } |
2961 | ||
2962 | continue; | |
2963 | ||
2964 | case 'a': | |
2965 | if (*s++ == 'a') | |
2966 | { | |
2967 | opcode |= ANNUL; | |
2968 | continue; | |
2969 | } | |
2970 | break; | |
2971 | ||
2972 | case 'A': | |
2973 | { | |
2974 | int asi = 0; | |
2975 | ||
2976 | /* Parse an asi. */ | |
2977 | if (*s == '#') | |
2978 | { | |
2979 | if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) | |
2980 | { | |
2981 | error_message = _(": invalid ASI name"); | |
2982 | goto error; | |
2983 | } | |
2984 | } | |
2985 | else | |
2986 | { | |
2987 | if (! parse_const_expr_arg (&s, &asi)) | |
2988 | { | |
2989 | error_message = _(": invalid ASI expression"); | |
2990 | goto error; | |
2991 | } | |
2992 | if (asi < 0 || asi > 255) | |
2993 | { | |
2994 | error_message = _(": invalid ASI number"); | |
2995 | goto error; | |
2996 | } | |
2997 | } | |
2998 | opcode |= ASI (asi); | |
2999 | continue; | |
e0c6ed95 | 3000 | } /* Alternate space. */ |
252b5132 RH |
3001 | |
3002 | case 'p': | |
3003 | if (strncmp (s, "%psr", 4) == 0) | |
3004 | { | |
3005 | s += 4; | |
3006 | continue; | |
3007 | } | |
3008 | break; | |
3009 | ||
e0c6ed95 | 3010 | case 'q': /* Floating point queue. */ |
252b5132 RH |
3011 | if (strncmp (s, "%fq", 3) == 0) |
3012 | { | |
3013 | s += 3; | |
3014 | continue; | |
3015 | } | |
3016 | break; | |
3017 | ||
e0c6ed95 | 3018 | case 'Q': /* Coprocessor queue. */ |
252b5132 RH |
3019 | if (strncmp (s, "%cq", 3) == 0) |
3020 | { | |
3021 | s += 3; | |
3022 | continue; | |
3023 | } | |
3024 | break; | |
3025 | ||
3026 | case 'S': | |
3027 | if (strcmp (str, "set") == 0 | |
3028 | || strcmp (str, "setuw") == 0) | |
3029 | { | |
3030 | special_case = SPECIAL_CASE_SET; | |
3031 | continue; | |
3032 | } | |
3033 | else if (strcmp (str, "setsw") == 0) | |
3034 | { | |
3035 | special_case = SPECIAL_CASE_SETSW; | |
3036 | continue; | |
3037 | } | |
3038 | else if (strcmp (str, "setx") == 0) | |
3039 | { | |
3040 | special_case = SPECIAL_CASE_SETX; | |
3041 | continue; | |
3042 | } | |
3043 | else if (strncmp (str, "fdiv", 4) == 0) | |
3044 | { | |
3045 | special_case = SPECIAL_CASE_FDIV; | |
3046 | continue; | |
3047 | } | |
3048 | break; | |
3049 | ||
3050 | case 'o': | |
3051 | if (strncmp (s, "%asi", 4) != 0) | |
3052 | break; | |
3053 | s += 4; | |
3054 | continue; | |
3055 | ||
3056 | case 's': | |
3057 | if (strncmp (s, "%fprs", 5) != 0) | |
3058 | break; | |
3059 | s += 5; | |
3060 | continue; | |
3061 | ||
3d68f91c JM |
3062 | case '{': |
3063 | if (strncmp (s, "%mcdper",7) != 0) | |
3064 | break; | |
3065 | s += 7; | |
3066 | continue; | |
3067 | ||
252b5132 RH |
3068 | case 'E': |
3069 | if (strncmp (s, "%ccr", 4) != 0) | |
3070 | break; | |
3071 | s += 4; | |
3072 | continue; | |
3073 | ||
3074 | case 't': | |
3075 | if (strncmp (s, "%tbr", 4) != 0) | |
3076 | break; | |
3077 | s += 4; | |
3078 | continue; | |
3079 | ||
3080 | case 'w': | |
3081 | if (strncmp (s, "%wim", 4) != 0) | |
3082 | break; | |
3083 | s += 4; | |
3084 | continue; | |
3085 | ||
3086 | case 'x': | |
3087 | { | |
3088 | char *push = input_line_pointer; | |
3089 | expressionS e; | |
3090 | ||
3091 | input_line_pointer = s; | |
3092 | expression (&e); | |
3093 | if (e.X_op == O_constant) | |
3094 | { | |
3095 | int n = e.X_add_number; | |
3096 | if (n != e.X_add_number || (n & ~0x1ff) != 0) | |
3097 | as_bad (_("OPF immediate operand out of range (0-0x1ff)")); | |
3098 | else | |
3099 | opcode |= e.X_add_number << 5; | |
3100 | } | |
3101 | else | |
3102 | as_bad (_("non-immediate OPF operand, ignored")); | |
3103 | s = input_line_pointer; | |
3104 | input_line_pointer = push; | |
3105 | continue; | |
3106 | } | |
3107 | ||
3108 | case 'y': | |
3109 | if (strncmp (s, "%y", 2) != 0) | |
3110 | break; | |
3111 | s += 2; | |
3112 | continue; | |
3113 | ||
3114 | case 'u': | |
3115 | case 'U': | |
3116 | { | |
3117 | /* Parse a sparclet cpreg. */ | |
3118 | int cpreg; | |
3119 | if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) | |
3120 | { | |
3121 | error_message = _(": invalid cpreg name"); | |
3122 | goto error; | |
3123 | } | |
3124 | opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); | |
3125 | continue; | |
3126 | } | |
3127 | ||
3128 | default: | |
3129 | as_fatal (_("failed sanity check.")); | |
e0c6ed95 | 3130 | } /* switch on arg code. */ |
252b5132 RH |
3131 | |
3132 | /* Break out of for() loop. */ | |
3133 | break; | |
e0c6ed95 | 3134 | } /* For each arg that we expect. */ |
252b5132 RH |
3135 | |
3136 | error: | |
3137 | if (match == 0) | |
3138 | { | |
e0c6ed95 | 3139 | /* Args don't match. */ |
252b5132 RH |
3140 | if (&insn[1] - sparc_opcodes < sparc_num_opcodes |
3141 | && (insn->name == insn[1].name | |
3142 | || !strcmp (insn->name, insn[1].name))) | |
3143 | { | |
3144 | ++insn; | |
3145 | s = argsStart; | |
3146 | continue; | |
3147 | } | |
3148 | else | |
3149 | { | |
3150 | as_bad (_("Illegal operands%s"), error_message); | |
a22b281c | 3151 | return special_case; |
252b5132 RH |
3152 | } |
3153 | } | |
3154 | else | |
3155 | { | |
e0c6ed95 | 3156 | /* We have a match. Now see if the architecture is OK. */ |
252b5132 | 3157 | int needed_arch_mask = insn->architecture; |
3d68f91c JM |
3158 | bfd_uint64_t hwcaps |
3159 | = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps; | |
252b5132 | 3160 | |
4bafe00e | 3161 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) |
9e8c70f9 DM |
3162 | if (hwcaps) |
3163 | hwcap_seen |= hwcaps; | |
3164 | #endif | |
252b5132 RH |
3165 | if (v9_arg_p) |
3166 | { | |
19f7b010 JJ |
3167 | needed_arch_mask &= |
3168 | ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); | |
3169 | if (! needed_arch_mask) | |
3170 | needed_arch_mask = | |
3171 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); | |
252b5132 RH |
3172 | } |
3173 | ||
e0c6ed95 AM |
3174 | if (needed_arch_mask |
3175 | & SPARC_OPCODE_SUPPORTED (current_architecture)) | |
3176 | /* OK. */ | |
3177 | ; | |
252b5132 | 3178 | /* Can we bump up the architecture? */ |
e0c6ed95 AM |
3179 | else if (needed_arch_mask |
3180 | & SPARC_OPCODE_SUPPORTED (max_architecture)) | |
252b5132 RH |
3181 | { |
3182 | enum sparc_opcode_arch_val needed_architecture = | |
3183 | sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) | |
3184 | & needed_arch_mask); | |
3185 | ||
9c2799c2 | 3186 | gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); |
252b5132 RH |
3187 | if (warn_on_bump |
3188 | && needed_architecture > warn_after_architecture) | |
3189 | { | |
3190 | as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), | |
3191 | sparc_opcode_archs[current_architecture].name, | |
3192 | sparc_opcode_archs[needed_architecture].name, | |
3193 | str); | |
3194 | warn_after_architecture = needed_architecture; | |
3195 | } | |
3196 | current_architecture = needed_architecture; | |
75ac3a7f | 3197 | hwcap_allowed |= hwcaps; |
252b5132 RH |
3198 | } |
3199 | /* Conflict. */ | |
3200 | /* ??? This seems to be a bit fragile. What if the next entry in | |
3201 | the opcode table is the one we want and it is supported? | |
3202 | It is possible to arrange the table today so that this can't | |
3203 | happen but what about tomorrow? */ | |
3204 | else | |
3205 | { | |
e0c6ed95 | 3206 | int arch, printed_one_p = 0; |
252b5132 RH |
3207 | char *p; |
3208 | char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; | |
3209 | ||
3210 | /* Create a list of the architectures that support the insn. */ | |
e0c6ed95 | 3211 | needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); |
252b5132 RH |
3212 | p = required_archs; |
3213 | arch = sparc_ffs (needed_arch_mask); | |
3214 | while ((1 << arch) <= needed_arch_mask) | |
3215 | { | |
3216 | if ((1 << arch) & needed_arch_mask) | |
3217 | { | |
3218 | if (printed_one_p) | |
3219 | *p++ = '|'; | |
3220 | strcpy (p, sparc_opcode_archs[arch].name); | |
3221 | p += strlen (p); | |
3222 | printed_one_p = 1; | |
3223 | } | |
3224 | ++arch; | |
3225 | } | |
3226 | ||
fc7514d6 | 3227 | as_bad (_("Architecture mismatch on \"%s %s\"."), str, argsStart); |
252b5132 RH |
3228 | as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), |
3229 | required_archs, | |
3230 | sparc_opcode_archs[max_architecture].name); | |
a22b281c | 3231 | return special_case; |
252b5132 | 3232 | } |
4bafe00e | 3233 | |
9aff4b7a | 3234 | /* Make sure the hwcaps used by the instruction are |
4bafe00e DM |
3235 | currently enabled. */ |
3236 | if (hwcaps & ~hwcap_allowed) | |
3237 | { | |
3238 | const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed); | |
3239 | ||
3240 | as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."), | |
3241 | hwcap_name, str); | |
3242 | return special_case; | |
3243 | } | |
e0c6ed95 | 3244 | } /* If no match. */ |
252b5132 RH |
3245 | |
3246 | break; | |
e0c6ed95 | 3247 | } /* Forever looking for a match. */ |
252b5132 RH |
3248 | |
3249 | the_insn.opcode = opcode; | |
a22b281c | 3250 | return special_case; |
252b5132 RH |
3251 | } |
3252 | ||
3253 | /* Parse an argument that can be expressed as a keyword. | |
3254 | (eg: #StoreStore or %ccfr). | |
3255 | The result is a boolean indicating success. | |
3256 | If successful, INPUT_POINTER is updated. */ | |
3257 | ||
3258 | static int | |
5a49b8ac AM |
3259 | parse_keyword_arg (int (*lookup_fn) (const char *), |
3260 | char **input_pointerP, | |
3261 | int *valueP) | |
252b5132 RH |
3262 | { |
3263 | int value; | |
3264 | char c, *p, *q; | |
3265 | ||
3266 | p = *input_pointerP; | |
3267 | for (q = p + (*p == '#' || *p == '%'); | |
3882b010 | 3268 | ISALNUM (*q) || *q == '_'; |
252b5132 RH |
3269 | ++q) |
3270 | continue; | |
3271 | c = *q; | |
3272 | *q = 0; | |
3273 | value = (*lookup_fn) (p); | |
3274 | *q = c; | |
3275 | if (value == -1) | |
3276 | return 0; | |
3277 | *valueP = value; | |
3278 | *input_pointerP = q; | |
3279 | return 1; | |
3280 | } | |
3281 | ||
3282 | /* Parse an argument that is a constant expression. | |
3283 | The result is a boolean indicating success. */ | |
3284 | ||
3285 | static int | |
5a49b8ac | 3286 | parse_const_expr_arg (char **input_pointerP, int *valueP) |
252b5132 RH |
3287 | { |
3288 | char *save = input_line_pointer; | |
3289 | expressionS exp; | |
3290 | ||
3291 | input_line_pointer = *input_pointerP; | |
3292 | /* The next expression may be something other than a constant | |
3293 | (say if we're not processing the right variant of the insn). | |
3294 | Don't call expression unless we're sure it will succeed as it will | |
3295 | signal an error (which we want to defer until later). */ | |
3296 | /* FIXME: It might be better to define md_operand and have it recognize | |
3297 | things like %asi, etc. but continuing that route through to the end | |
3298 | is a lot of work. */ | |
3299 | if (*input_line_pointer == '%') | |
3300 | { | |
3301 | input_line_pointer = save; | |
3302 | return 0; | |
3303 | } | |
3304 | expression (&exp); | |
3305 | *input_pointerP = input_line_pointer; | |
3306 | input_line_pointer = save; | |
3307 | if (exp.X_op != O_constant) | |
3308 | return 0; | |
3309 | *valueP = exp.X_add_number; | |
3310 | return 1; | |
3311 | } | |
3312 | ||
3313 | /* Subroutine of sparc_ip to parse an expression. */ | |
3314 | ||
3315 | static int | |
5a49b8ac | 3316 | get_expression (char *str) |
252b5132 RH |
3317 | { |
3318 | char *save_in; | |
3319 | segT seg; | |
3320 | ||
3321 | save_in = input_line_pointer; | |
3322 | input_line_pointer = str; | |
3323 | seg = expression (&the_insn.exp); | |
3324 | if (seg != absolute_section | |
3325 | && seg != text_section | |
3326 | && seg != data_section | |
3327 | && seg != bss_section | |
3328 | && seg != undefined_section) | |
3329 | { | |
3330 | the_insn.error = _("bad segment"); | |
3331 | expr_end = input_line_pointer; | |
3332 | input_line_pointer = save_in; | |
3333 | return 1; | |
3334 | } | |
3335 | expr_end = input_line_pointer; | |
3336 | input_line_pointer = save_in; | |
3337 | return 0; | |
3338 | } | |
3339 | ||
3340 | /* Subroutine of md_assemble to output one insn. */ | |
3341 | ||
3342 | static void | |
91d6fa6a | 3343 | output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn) |
252b5132 RH |
3344 | { |
3345 | char *toP = frag_more (4); | |
3346 | ||
e0c6ed95 | 3347 | /* Put out the opcode. */ |
252b5132 | 3348 | if (INSN_BIG_ENDIAN) |
91d6fa6a | 3349 | number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 3350 | else |
91d6fa6a | 3351 | number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 3352 | |
e0c6ed95 | 3353 | /* Put out the symbol-dependent stuff. */ |
91d6fa6a | 3354 | if (theinsn->reloc != BFD_RELOC_NONE) |
252b5132 | 3355 | { |
e0c6ed95 AM |
3356 | fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ |
3357 | (toP - frag_now->fr_literal), /* Where. */ | |
3358 | 4, /* Size. */ | |
91d6fa6a NC |
3359 | &theinsn->exp, |
3360 | theinsn->pcrel, | |
3361 | theinsn->reloc); | |
252b5132 | 3362 | /* Turn off overflow checking in fixup_segment. We'll do our |
55cf6793 | 3363 | own overflow checking in md_apply_fix. This is necessary because |
252b5132 RH |
3364 | the insn size is 4 and fixup_segment will signal an overflow for |
3365 | large 8 byte quantities. */ | |
3366 | fixP->fx_no_overflow = 1; | |
91d6fa6a NC |
3367 | if (theinsn->reloc == BFD_RELOC_SPARC_OLO10) |
3368 | fixP->tc_fix_data = theinsn->exp2.X_add_number; | |
252b5132 RH |
3369 | } |
3370 | ||
3371 | last_insn = insn; | |
91d6fa6a | 3372 | last_opcode = theinsn->opcode; |
732d96b6 JJ |
3373 | |
3374 | #ifdef OBJ_ELF | |
3375 | dwarf2_emit_insn (4); | |
3376 | #endif | |
252b5132 RH |
3377 | } |
3378 | \f | |
6d4af3c2 | 3379 | const char * |
499ac353 | 3380 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 3381 | { |
499ac353 | 3382 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
3383 | } |
3384 | ||
3385 | /* Write a value out to the object file, using the appropriate | |
3386 | endianness. */ | |
3387 | ||
3388 | void | |
5a49b8ac | 3389 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
3390 | { |
3391 | if (target_big_endian) | |
3392 | number_to_chars_bigendian (buf, val, n); | |
3393 | else if (target_little_endian_data | |
3394 | && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) | |
e0c6ed95 AM |
3395 | /* Output debug words, which are not in allocated sections, as big |
3396 | endian. */ | |
252b5132 RH |
3397 | number_to_chars_bigendian (buf, val, n); |
3398 | else if (target_little_endian_data || ! target_big_endian) | |
3399 | number_to_chars_littleendian (buf, val, n); | |
3400 | } | |
3401 | \f | |
3402 | /* Apply a fixS to the frags, now that we know the value it ought to | |
81d4177b | 3403 | hold. */ |
252b5132 | 3404 | |
94f592af | 3405 | void |
5a49b8ac | 3406 | md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) |
252b5132 RH |
3407 | { |
3408 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
94f592af | 3409 | offsetT val = * (offsetT *) valP; |
252b5132 RH |
3410 | long insn; |
3411 | ||
9c2799c2 | 3412 | gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); |
252b5132 | 3413 | |
e0c6ed95 | 3414 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
252b5132 RH |
3415 | |
3416 | #ifdef OBJ_ELF | |
a161fe53 | 3417 | /* SPARC ELF relocations don't use an addend in the data field. */ |
252b5132 | 3418 | if (fixP->fx_addsy != NULL) |
7c1d0959 L |
3419 | { |
3420 | switch (fixP->fx_r_type) | |
3421 | { | |
3422 | case BFD_RELOC_SPARC_TLS_GD_HI22: | |
3423 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3424 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3425 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3426 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3427 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3428 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3429 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3430 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3431 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3432 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3433 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3434 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3435 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3436 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3437 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3438 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3439 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3440 | case BFD_RELOC_SPARC_TLS_DTPMOD32: | |
3441 | case BFD_RELOC_SPARC_TLS_DTPMOD64: | |
3442 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3443 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
3444 | case BFD_RELOC_SPARC_TLS_TPOFF32: | |
3445 | case BFD_RELOC_SPARC_TLS_TPOFF64: | |
3446 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
3447 | ||
3448 | default: | |
3449 | break; | |
3450 | } | |
3451 | ||
3452 | return; | |
3453 | } | |
252b5132 RH |
3454 | #endif |
3455 | ||
3456 | /* This is a hack. There should be a better way to | |
3457 | handle this. Probably in terms of howto fields, once | |
3458 | we can look at these fixups in terms of howtos. */ | |
3459 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) | |
3460 | val += fixP->fx_where + fixP->fx_frag->fr_address; | |
3461 | ||
3462 | #ifdef OBJ_AOUT | |
3463 | /* FIXME: More ridiculous gas reloc hacking. If we are going to | |
3464 | generate a reloc, then we just want to let the reloc addend set | |
3465 | the value. We do not want to also stuff the addend into the | |
3466 | object file. Including the addend in the object file works when | |
3467 | doing a static link, because the linker will ignore the object | |
3468 | file contents. However, the dynamic linker does not ignore the | |
3469 | object file contents. */ | |
3470 | if (fixP->fx_addsy != NULL | |
3471 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) | |
3472 | val = 0; | |
3473 | ||
3474 | /* When generating PIC code, we do not want an addend for a reloc | |
3475 | against a local symbol. We adjust fx_addnumber to cancel out the | |
3476 | value already included in val, and to also cancel out the | |
3477 | adjustment which bfd_install_relocation will create. */ | |
3478 | if (sparc_pic_code | |
3479 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 | |
3480 | && fixP->fx_addsy != NULL | |
3481 | && ! S_IS_COMMON (fixP->fx_addsy) | |
49309057 | 3482 | && symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3483 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); |
3484 | ||
3485 | /* When generating PIC code, we need to fiddle to get | |
3486 | bfd_install_relocation to do the right thing for a PC relative | |
3487 | reloc against a local symbol which we are going to keep. */ | |
3488 | if (sparc_pic_code | |
3489 | && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3490 | && fixP->fx_addsy != NULL | |
3491 | && (S_IS_EXTERNAL (fixP->fx_addsy) | |
3492 | || S_IS_WEAK (fixP->fx_addsy)) | |
3493 | && S_IS_DEFINED (fixP->fx_addsy) | |
3494 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
3495 | { | |
3496 | val = 0; | |
3497 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
3498 | } | |
3499 | #endif | |
3500 | ||
3501 | /* If this is a data relocation, just output VAL. */ | |
3502 | ||
a7bbf4e9 DM |
3503 | if (fixP->fx_r_type == BFD_RELOC_8) |
3504 | { | |
3505 | md_number_to_chars (buf, val, 1); | |
3506 | } | |
3507 | else if (fixP->fx_r_type == BFD_RELOC_16 | |
3508 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) | |
252b5132 RH |
3509 | { |
3510 | md_number_to_chars (buf, val, 2); | |
3511 | } | |
3512 | else if (fixP->fx_r_type == BFD_RELOC_32 | |
0f2712ed | 3513 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 |
252b5132 RH |
3514 | || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) |
3515 | { | |
3516 | md_number_to_chars (buf, val, 4); | |
3517 | } | |
0f2712ed NC |
3518 | else if (fixP->fx_r_type == BFD_RELOC_64 |
3519 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) | |
252b5132 RH |
3520 | { |
3521 | md_number_to_chars (buf, val, 8); | |
3522 | } | |
e0c6ed95 | 3523 | else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
252b5132 RH |
3524 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
3525 | { | |
3526 | fixP->fx_done = 0; | |
94f592af | 3527 | return; |
252b5132 RH |
3528 | } |
3529 | else | |
3530 | { | |
3531 | /* It's a relocation against an instruction. */ | |
3532 | ||
3533 | if (INSN_BIG_ENDIAN) | |
3534 | insn = bfd_getb32 ((unsigned char *) buf); | |
3535 | else | |
3536 | insn = bfd_getl32 ((unsigned char *) buf); | |
e0c6ed95 | 3537 | |
252b5132 RH |
3538 | switch (fixP->fx_r_type) |
3539 | { | |
3540 | case BFD_RELOC_32_PCREL_S2: | |
3541 | val = val >> 2; | |
3542 | /* FIXME: This increment-by-one deserves a comment of why it's | |
3543 | being done! */ | |
3544 | if (! sparc_pic_code | |
3545 | || fixP->fx_addsy == NULL | |
49309057 | 3546 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 | 3547 | ++val; |
6faf3d66 | 3548 | |
252b5132 | 3549 | insn |= val & 0x3fffffff; |
6faf3d66 | 3550 | |
e0c6ed95 | 3551 | /* See if we have a delay slot. */ |
6faf3d66 JJ |
3552 | if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) |
3553 | { | |
3554 | #define G0 0 | |
3555 | #define O7 15 | |
3556 | #define XCC (2 << 20) | |
3557 | #define COND(x) (((x)&0xf)<<25) | |
3558 | #define CONDA COND(0x8) | |
3559 | #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) | |
3560 | #define INSN_BA (F2(0,2) | CONDA) | |
3561 | #define INSN_OR F3(2, 0x2, 0) | |
3562 | #define INSN_NOP F2(0,4) | |
3563 | ||
3564 | long delay; | |
3565 | ||
3566 | /* If the instruction is a call with either: | |
3567 | restore | |
3568 | arithmetic instruction with rd == %o7 | |
3569 | where rs1 != %o7 and rs2 if it is register != %o7 | |
3570 | then we can optimize if the call destination is near | |
3571 | by changing the call into a branch always. */ | |
3572 | if (INSN_BIG_ENDIAN) | |
3573 | delay = bfd_getb32 ((unsigned char *) buf + 4); | |
3574 | else | |
3575 | delay = bfd_getl32 ((unsigned char *) buf + 4); | |
e0c6ed95 | 3576 | if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) |
6faf3d66 | 3577 | break; |
e0c6ed95 AM |
3578 | if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ |
3579 | && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ | |
3580 | || ((delay & RD (~0)) != RD (O7)))) | |
6faf3d66 | 3581 | break; |
e0c6ed95 AM |
3582 | if ((delay & RS1 (~0)) == RS1 (O7) |
3583 | || ((delay & F3I (~0)) == 0 | |
3584 | && (delay & RS2 (~0)) == RS2 (O7))) | |
6faf3d66 JJ |
3585 | break; |
3586 | /* Ensure the branch will fit into simm22. */ | |
3587 | if ((val & 0x3fe00000) | |
3588 | && (val & 0x3fe00000) != 0x3fe00000) | |
3589 | break; | |
3590 | /* Check if the arch is v9 and branch will fit | |
3591 | into simm19. */ | |
3592 | if (((val & 0x3c0000) == 0 | |
3593 | || (val & 0x3c0000) == 0x3c0000) | |
3594 | && (sparc_arch_size == 64 | |
3595 | || current_architecture >= SPARC_OPCODE_ARCH_V9)) | |
e0c6ed95 | 3596 | /* ba,pt %xcc */ |
6faf3d66 JJ |
3597 | insn = INSN_BPA | (val & 0x7ffff); |
3598 | else | |
e0c6ed95 | 3599 | /* ba */ |
6faf3d66 JJ |
3600 | insn = INSN_BA | (val & 0x3fffff); |
3601 | if (fixP->fx_where >= 4 | |
e0c6ed95 AM |
3602 | && ((delay & (0xffffffff ^ RS1 (~0))) |
3603 | == (INSN_OR | RD (O7) | RS2 (G0)))) | |
6faf3d66 JJ |
3604 | { |
3605 | long setter; | |
3606 | int reg; | |
3607 | ||
3608 | if (INSN_BIG_ENDIAN) | |
3609 | setter = bfd_getb32 ((unsigned char *) buf - 4); | |
3610 | else | |
3611 | setter = bfd_getl32 ((unsigned char *) buf - 4); | |
e0c6ed95 | 3612 | if ((setter & (0xffffffff ^ RD (~0))) |
ab3e48dc | 3613 | != (INSN_OR | RS1 (O7) | RS2 (G0))) |
6faf3d66 JJ |
3614 | break; |
3615 | /* The sequence was | |
3616 | or %o7, %g0, %rN | |
3617 | call foo | |
3618 | or %rN, %g0, %o7 | |
3619 | ||
3620 | If call foo was replaced with ba, replace | |
3621 | or %rN, %g0, %o7 with nop. */ | |
e0c6ed95 AM |
3622 | reg = (delay & RS1 (~0)) >> 14; |
3623 | if (reg != ((setter & RD (~0)) >> 25) | |
6faf3d66 JJ |
3624 | || reg == G0 || reg == O7) |
3625 | break; | |
3626 | ||
3627 | if (INSN_BIG_ENDIAN) | |
3628 | bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); | |
3629 | else | |
3630 | bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); | |
3631 | } | |
3632 | } | |
252b5132 RH |
3633 | break; |
3634 | ||
3635 | case BFD_RELOC_SPARC_11: | |
3636 | if (! in_signed_range (val, 0x7ff)) | |
3637 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3638 | _("relocation overflow")); | |
3639 | insn |= val & 0x7ff; | |
3640 | break; | |
3641 | ||
3642 | case BFD_RELOC_SPARC_10: | |
3643 | if (! in_signed_range (val, 0x3ff)) | |
3644 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3645 | _("relocation overflow")); | |
3646 | insn |= val & 0x3ff; | |
3647 | break; | |
3648 | ||
3649 | case BFD_RELOC_SPARC_7: | |
3650 | if (! in_bitfield_range (val, 0x7f)) | |
3651 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3652 | _("relocation overflow")); | |
3653 | insn |= val & 0x7f; | |
3654 | break; | |
3655 | ||
3656 | case BFD_RELOC_SPARC_6: | |
3657 | if (! in_bitfield_range (val, 0x3f)) | |
3658 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3659 | _("relocation overflow")); | |
3660 | insn |= val & 0x3f; | |
3661 | break; | |
3662 | ||
3663 | case BFD_RELOC_SPARC_5: | |
3664 | if (! in_bitfield_range (val, 0x1f)) | |
3665 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3666 | _("relocation overflow")); | |
3667 | insn |= val & 0x1f; | |
3668 | break; | |
3669 | ||
2615994e DM |
3670 | case BFD_RELOC_SPARC_WDISP10: |
3671 | if ((val & 3) | |
3672 | || val >= 0x007fc | |
3673 | || val <= -(offsetT) 0x808) | |
3674 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3675 | _("relocation overflow")); | |
3676 | /* FIXME: The +1 deserves a comment. */ | |
3677 | val = (val >> 2) + 1; | |
3678 | insn |= ((val & 0x300) << 11) | |
3679 | | ((val & 0xff) << 5); | |
3680 | break; | |
3681 | ||
252b5132 | 3682 | case BFD_RELOC_SPARC_WDISP16: |
c699f087 JJ |
3683 | if ((val & 3) |
3684 | || val >= 0x1fffc | |
3685 | || val <= -(offsetT) 0x20008) | |
252b5132 RH |
3686 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3687 | _("relocation overflow")); | |
3688 | /* FIXME: The +1 deserves a comment. */ | |
3689 | val = (val >> 2) + 1; | |
3690 | insn |= ((val & 0xc000) << 6) | (val & 0x3fff); | |
3691 | break; | |
3692 | ||
3693 | case BFD_RELOC_SPARC_WDISP19: | |
c699f087 JJ |
3694 | if ((val & 3) |
3695 | || val >= 0xffffc | |
3696 | || val <= -(offsetT) 0x100008) | |
252b5132 RH |
3697 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3698 | _("relocation overflow")); | |
3699 | /* FIXME: The +1 deserves a comment. */ | |
3700 | val = (val >> 2) + 1; | |
3701 | insn |= val & 0x7ffff; | |
3702 | break; | |
3703 | ||
3704 | case BFD_RELOC_SPARC_HH22: | |
3705 | val = BSR (val, 32); | |
e0c6ed95 | 3706 | /* Fall through. */ |
252b5132 RH |
3707 | |
3708 | case BFD_RELOC_SPARC_LM22: | |
3709 | case BFD_RELOC_HI22: | |
3710 | if (!fixP->fx_addsy) | |
94f592af | 3711 | insn |= (val >> 10) & 0x3fffff; |
252b5132 | 3712 | else |
94f592af NC |
3713 | /* FIXME: Need comment explaining why we do this. */ |
3714 | insn &= ~0xffff; | |
252b5132 RH |
3715 | break; |
3716 | ||
3717 | case BFD_RELOC_SPARC22: | |
3718 | if (val & ~0x003fffff) | |
3719 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3720 | _("relocation overflow")); | |
3721 | insn |= (val & 0x3fffff); | |
3722 | break; | |
3723 | ||
3724 | case BFD_RELOC_SPARC_HM10: | |
3725 | val = BSR (val, 32); | |
e0c6ed95 | 3726 | /* Fall through. */ |
252b5132 RH |
3727 | |
3728 | case BFD_RELOC_LO10: | |
3729 | if (!fixP->fx_addsy) | |
94f592af | 3730 | insn |= val & 0x3ff; |
252b5132 | 3731 | else |
94f592af NC |
3732 | /* FIXME: Need comment explaining why we do this. */ |
3733 | insn &= ~0xff; | |
252b5132 RH |
3734 | break; |
3735 | ||
dabe3bbc RH |
3736 | case BFD_RELOC_SPARC_OLO10: |
3737 | val &= 0x3ff; | |
3738 | val += fixP->tc_fix_data; | |
e0c6ed95 | 3739 | /* Fall through. */ |
dabe3bbc | 3740 | |
252b5132 RH |
3741 | case BFD_RELOC_SPARC13: |
3742 | if (! in_signed_range (val, 0x1fff)) | |
3743 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3744 | _("relocation overflow")); | |
3745 | insn |= val & 0x1fff; | |
3746 | break; | |
3747 | ||
3748 | case BFD_RELOC_SPARC_WDISP22: | |
3749 | val = (val >> 2) + 1; | |
e0c6ed95 | 3750 | /* Fall through. */ |
252b5132 RH |
3751 | case BFD_RELOC_SPARC_BASE22: |
3752 | insn |= val & 0x3fffff; | |
3753 | break; | |
3754 | ||
2615994e DM |
3755 | case BFD_RELOC_SPARC_H34: |
3756 | if (!fixP->fx_addsy) | |
3757 | { | |
3758 | bfd_vma tval = val; | |
3759 | tval >>= 12; | |
3760 | insn |= tval & 0x3fffff; | |
3761 | } | |
3762 | break; | |
3763 | ||
252b5132 RH |
3764 | case BFD_RELOC_SPARC_H44: |
3765 | if (!fixP->fx_addsy) | |
3766 | { | |
3767 | bfd_vma tval = val; | |
3768 | tval >>= 22; | |
3769 | insn |= tval & 0x3fffff; | |
3770 | } | |
3771 | break; | |
3772 | ||
3773 | case BFD_RELOC_SPARC_M44: | |
3774 | if (!fixP->fx_addsy) | |
3775 | insn |= (val >> 12) & 0x3ff; | |
3776 | break; | |
3777 | ||
3778 | case BFD_RELOC_SPARC_L44: | |
3779 | if (!fixP->fx_addsy) | |
3780 | insn |= val & 0xfff; | |
3781 | break; | |
3782 | ||
3783 | case BFD_RELOC_SPARC_HIX22: | |
3784 | if (!fixP->fx_addsy) | |
3785 | { | |
ab3e48dc | 3786 | val ^= ~(offsetT) 0; |
252b5132 RH |
3787 | insn |= (val >> 10) & 0x3fffff; |
3788 | } | |
3789 | break; | |
3790 | ||
3791 | case BFD_RELOC_SPARC_LOX10: | |
3792 | if (!fixP->fx_addsy) | |
3793 | insn |= 0x1c00 | (val & 0x3ff); | |
3794 | break; | |
3795 | ||
3796 | case BFD_RELOC_NONE: | |
3797 | default: | |
3798 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3799 | _("bad or unhandled relocation type: 0x%02x"), | |
3800 | fixP->fx_r_type); | |
3801 | break; | |
3802 | } | |
3803 | ||
3804 | if (INSN_BIG_ENDIAN) | |
3805 | bfd_putb32 (insn, (unsigned char *) buf); | |
3806 | else | |
3807 | bfd_putl32 (insn, (unsigned char *) buf); | |
3808 | } | |
3809 | ||
3810 | /* Are we finished with this relocation now? */ | |
3811 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
3812 | fixP->fx_done = 1; | |
252b5132 RH |
3813 | } |
3814 | ||
3815 | /* Translate internal representation of relocation info to BFD target | |
3816 | format. */ | |
e0c6ed95 | 3817 | |
dabe3bbc | 3818 | arelent ** |
5a49b8ac | 3819 | tc_gen_reloc (asection *section, fixS *fixp) |
252b5132 | 3820 | { |
dabe3bbc | 3821 | static arelent *relocs[3]; |
252b5132 RH |
3822 | arelent *reloc; |
3823 | bfd_reloc_code_real_type code; | |
3824 | ||
add39d23 | 3825 | relocs[0] = reloc = XNEW (arelent); |
dabe3bbc | 3826 | relocs[1] = NULL; |
252b5132 | 3827 | |
add39d23 | 3828 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
49309057 | 3829 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
3830 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3831 | ||
3832 | switch (fixp->fx_r_type) | |
3833 | { | |
3834 | case BFD_RELOC_16: | |
3835 | case BFD_RELOC_32: | |
3836 | case BFD_RELOC_HI22: | |
3837 | case BFD_RELOC_LO10: | |
3838 | case BFD_RELOC_32_PCREL_S2: | |
3839 | case BFD_RELOC_SPARC13: | |
63fab58c | 3840 | case BFD_RELOC_SPARC22: |
1a6b486f DM |
3841 | case BFD_RELOC_SPARC_PC22: |
3842 | case BFD_RELOC_SPARC_PC10: | |
252b5132 | 3843 | case BFD_RELOC_SPARC_BASE13: |
2615994e | 3844 | case BFD_RELOC_SPARC_WDISP10: |
252b5132 RH |
3845 | case BFD_RELOC_SPARC_WDISP16: |
3846 | case BFD_RELOC_SPARC_WDISP19: | |
3847 | case BFD_RELOC_SPARC_WDISP22: | |
3848 | case BFD_RELOC_64: | |
3849 | case BFD_RELOC_SPARC_5: | |
3850 | case BFD_RELOC_SPARC_6: | |
3851 | case BFD_RELOC_SPARC_7: | |
3852 | case BFD_RELOC_SPARC_10: | |
3853 | case BFD_RELOC_SPARC_11: | |
3854 | case BFD_RELOC_SPARC_HH22: | |
3855 | case BFD_RELOC_SPARC_HM10: | |
3856 | case BFD_RELOC_SPARC_LM22: | |
3857 | case BFD_RELOC_SPARC_PC_HH22: | |
3858 | case BFD_RELOC_SPARC_PC_HM10: | |
3859 | case BFD_RELOC_SPARC_PC_LM22: | |
2615994e | 3860 | case BFD_RELOC_SPARC_H34: |
252b5132 RH |
3861 | case BFD_RELOC_SPARC_H44: |
3862 | case BFD_RELOC_SPARC_M44: | |
3863 | case BFD_RELOC_SPARC_L44: | |
3864 | case BFD_RELOC_SPARC_HIX22: | |
3865 | case BFD_RELOC_SPARC_LOX10: | |
3866 | case BFD_RELOC_SPARC_REV32: | |
dabe3bbc | 3867 | case BFD_RELOC_SPARC_OLO10: |
0f2712ed NC |
3868 | case BFD_RELOC_SPARC_UA16: |
3869 | case BFD_RELOC_SPARC_UA32: | |
3870 | case BFD_RELOC_SPARC_UA64: | |
bd5e6e7e JJ |
3871 | case BFD_RELOC_8_PCREL: |
3872 | case BFD_RELOC_16_PCREL: | |
3873 | case BFD_RELOC_32_PCREL: | |
3874 | case BFD_RELOC_64_PCREL: | |
3875 | case BFD_RELOC_SPARC_PLT32: | |
3876 | case BFD_RELOC_SPARC_PLT64: | |
252b5132 RH |
3877 | case BFD_RELOC_VTABLE_ENTRY: |
3878 | case BFD_RELOC_VTABLE_INHERIT: | |
b9734f35 JJ |
3879 | case BFD_RELOC_SPARC_TLS_GD_HI22: |
3880 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3881 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3882 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3883 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3884 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3885 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3886 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3887 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3888 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3889 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3890 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3891 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3892 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3893 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3894 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3895 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3896 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3897 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3898 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
739f7f82 DM |
3899 | case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: |
3900 | case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: | |
3901 | case BFD_RELOC_SPARC_GOTDATA_OP: | |
252b5132 RH |
3902 | code = fixp->fx_r_type; |
3903 | break; | |
3904 | default: | |
3905 | abort (); | |
3906 | return NULL; | |
3907 | } | |
3908 | ||
3909 | #if defined (OBJ_ELF) || defined (OBJ_AOUT) | |
3910 | /* If we are generating PIC code, we need to generate a different | |
3911 | set of relocs. */ | |
3912 | ||
3913 | #ifdef OBJ_ELF | |
3914 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" | |
3915 | #else | |
3916 | #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" | |
910600e9 RS |
3917 | #endif |
3918 | #ifdef TE_VXWORKS | |
3919 | #define GOTT_BASE "__GOTT_BASE__" | |
3920 | #define GOTT_INDEX "__GOTT_INDEX__" | |
252b5132 RH |
3921 | #endif |
3922 | ||
153b546a ILT |
3923 | /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ |
3924 | ||
252b5132 RH |
3925 | if (sparc_pic_code) |
3926 | { | |
3927 | switch (code) | |
3928 | { | |
3929 | case BFD_RELOC_32_PCREL_S2: | |
ae6063d4 | 3930 | if (generic_force_reloc (fixp)) |
252b5132 RH |
3931 | code = BFD_RELOC_SPARC_WPLT30; |
3932 | break; | |
3933 | case BFD_RELOC_HI22: | |
910600e9 RS |
3934 | code = BFD_RELOC_SPARC_GOT22; |
3935 | if (fixp->fx_addsy != NULL) | |
3936 | { | |
3937 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3938 | code = BFD_RELOC_SPARC_PC22; | |
3939 | #ifdef TE_VXWORKS | |
3940 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3941 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3942 | code = BFD_RELOC_HI22; /* Unchanged. */ | |
3943 | #endif | |
3944 | } | |
252b5132 RH |
3945 | break; |
3946 | case BFD_RELOC_LO10: | |
910600e9 RS |
3947 | code = BFD_RELOC_SPARC_GOT10; |
3948 | if (fixp->fx_addsy != NULL) | |
3949 | { | |
3950 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3951 | code = BFD_RELOC_SPARC_PC10; | |
3952 | #ifdef TE_VXWORKS | |
3953 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3954 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3955 | code = BFD_RELOC_LO10; /* Unchanged. */ | |
3956 | #endif | |
3957 | } | |
252b5132 RH |
3958 | break; |
3959 | case BFD_RELOC_SPARC13: | |
3960 | code = BFD_RELOC_SPARC_GOT13; | |
3961 | break; | |
3962 | default: | |
3963 | break; | |
3964 | } | |
3965 | } | |
e0c6ed95 | 3966 | #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ |
252b5132 | 3967 | |
062cf837 EB |
3968 | /* Nothing is aligned in DWARF debugging sections. */ |
3969 | if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) | |
3970 | switch (code) | |
3971 | { | |
3972 | case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; | |
3973 | case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; | |
3974 | case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; | |
3975 | default: break; | |
3976 | } | |
3977 | ||
dabe3bbc RH |
3978 | if (code == BFD_RELOC_SPARC_OLO10) |
3979 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); | |
3980 | else | |
3981 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
252b5132 RH |
3982 | if (reloc->howto == 0) |
3983 | { | |
3984 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3985 | _("internal error: can't export reloc type %d (`%s')"), | |
3986 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); | |
dabe3bbc RH |
3987 | xfree (reloc); |
3988 | relocs[0] = NULL; | |
3989 | return relocs; | |
252b5132 RH |
3990 | } |
3991 | ||
3992 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ | |
3993 | #ifdef OBJ_AOUT | |
3994 | ||
3995 | if (reloc->howto->pc_relative == 0 | |
3996 | || code == BFD_RELOC_SPARC_PC10 | |
3997 | || code == BFD_RELOC_SPARC_PC22) | |
3998 | reloc->addend = fixp->fx_addnumber; | |
3999 | else if (sparc_pic_code | |
4000 | && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
4001 | && fixp->fx_addsy != NULL | |
4002 | && (S_IS_EXTERNAL (fixp->fx_addsy) | |
4003 | || S_IS_WEAK (fixp->fx_addsy)) | |
4004 | && S_IS_DEFINED (fixp->fx_addsy) | |
4005 | && ! S_IS_COMMON (fixp->fx_addsy)) | |
4006 | reloc->addend = fixp->fx_addnumber; | |
4007 | else | |
4008 | reloc->addend = fixp->fx_offset - reloc->address; | |
4009 | ||
e0c6ed95 | 4010 | #else /* elf or coff */ |
252b5132 | 4011 | |
bd5e6e7e JJ |
4012 | if (code != BFD_RELOC_32_PCREL_S2 |
4013 | && code != BFD_RELOC_SPARC_WDISP22 | |
4014 | && code != BFD_RELOC_SPARC_WDISP16 | |
4015 | && code != BFD_RELOC_SPARC_WDISP19 | |
2615994e | 4016 | && code != BFD_RELOC_SPARC_WDISP10 |
b9734f35 JJ |
4017 | && code != BFD_RELOC_SPARC_WPLT30 |
4018 | && code != BFD_RELOC_SPARC_TLS_GD_CALL | |
4019 | && code != BFD_RELOC_SPARC_TLS_LDM_CALL) | |
252b5132 | 4020 | reloc->addend = fixp->fx_addnumber; |
49309057 | 4021 | else if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
4022 | reloc->addend = (section->vma |
4023 | + fixp->fx_addnumber | |
4024 | + md_pcrel_from (fixp)); | |
4025 | else | |
4026 | reloc->addend = fixp->fx_offset; | |
4027 | #endif | |
4028 | ||
dabe3bbc RH |
4029 | /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 |
4030 | on the same location. */ | |
4031 | if (code == BFD_RELOC_SPARC_OLO10) | |
4032 | { | |
add39d23 | 4033 | relocs[1] = reloc = XNEW (arelent); |
dabe3bbc RH |
4034 | relocs[2] = NULL; |
4035 | ||
add39d23 | 4036 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
ab3e48dc KH |
4037 | *reloc->sym_ptr_ptr |
4038 | = symbol_get_bfdsym (section_symbol (absolute_section)); | |
dabe3bbc RH |
4039 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
4040 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); | |
4041 | reloc->addend = fixp->tc_fix_data; | |
4042 | } | |
4043 | ||
4044 | return relocs; | |
252b5132 RH |
4045 | } |
4046 | \f | |
e0c6ed95 | 4047 | /* We have no need to default values of symbols. */ |
252b5132 | 4048 | |
252b5132 | 4049 | symbolS * |
5a49b8ac | 4050 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
4051 | { |
4052 | return 0; | |
e0c6ed95 AM |
4053 | } |
4054 | ||
4055 | /* Round up a section size to the appropriate boundary. */ | |
252b5132 | 4056 | |
252b5132 | 4057 | valueT |
5a49b8ac | 4058 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 RH |
4059 | { |
4060 | #ifndef OBJ_ELF | |
4061 | /* This is not right for ELF; a.out wants it, and COFF will force | |
4062 | the alignment anyways. */ | |
4063 | valueT align = ((valueT) 1 | |
4064 | << (valueT) bfd_get_section_alignment (stdoutput, segment)); | |
4065 | valueT newsize; | |
e0c6ed95 AM |
4066 | |
4067 | /* Turn alignment value into a mask. */ | |
252b5132 RH |
4068 | align--; |
4069 | newsize = (size + align) & ~align; | |
4070 | return newsize; | |
4071 | #else | |
4072 | return size; | |
4073 | #endif | |
4074 | } | |
4075 | ||
4076 | /* Exactly what point is a PC-relative offset relative TO? | |
4077 | On the sparc, they're relative to the address of the offset, plus | |
4078 | its size. This gets us to the following instruction. | |
e0c6ed95 AM |
4079 | (??? Is this right? FIXME-SOON) */ |
4080 | long | |
5a49b8ac | 4081 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
4082 | { |
4083 | long ret; | |
4084 | ||
4085 | ret = fixP->fx_where + fixP->fx_frag->fr_address; | |
4086 | if (! sparc_pic_code | |
4087 | || fixP->fx_addsy == NULL | |
49309057 | 4088 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
4089 | ret += fixP->fx_size; |
4090 | return ret; | |
4091 | } | |
4092 | \f | |
4093 | /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power | |
4094 | of two. */ | |
4095 | ||
4096 | static int | |
5a49b8ac | 4097 | mylog2 (int value) |
252b5132 RH |
4098 | { |
4099 | int shift; | |
4100 | ||
4101 | if (value <= 0) | |
4102 | return -1; | |
4103 | ||
4104 | for (shift = 0; (value & 1) == 0; value >>= 1) | |
4105 | ++shift; | |
4106 | ||
4107 | return (value == 1) ? shift : -1; | |
4108 | } | |
4109 | ||
e0c6ed95 | 4110 | /* Sort of like s_lcomm. */ |
252b5132 RH |
4111 | |
4112 | #ifndef OBJ_ELF | |
4113 | static int max_alignment = 15; | |
4114 | #endif | |
4115 | ||
4116 | static void | |
5a49b8ac | 4117 | s_reserve (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4118 | { |
4119 | char *name; | |
4120 | char *p; | |
4121 | char c; | |
4122 | int align; | |
4123 | int size; | |
4124 | int temp; | |
4125 | symbolS *symbolP; | |
4126 | ||
d02603dc | 4127 | c = get_symbol_name (&name); |
252b5132 RH |
4128 | p = input_line_pointer; |
4129 | *p = c; | |
d02603dc | 4130 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
4131 | |
4132 | if (*input_line_pointer != ',') | |
4133 | { | |
4134 | as_bad (_("Expected comma after name")); | |
4135 | ignore_rest_of_line (); | |
4136 | return; | |
4137 | } | |
4138 | ||
4139 | ++input_line_pointer; | |
4140 | ||
4141 | if ((size = get_absolute_expression ()) < 0) | |
4142 | { | |
4143 | as_bad (_("BSS length (%d.) <0! Ignored."), size); | |
4144 | ignore_rest_of_line (); | |
4145 | return; | |
e0c6ed95 | 4146 | } /* Bad length. */ |
252b5132 RH |
4147 | |
4148 | *p = 0; | |
4149 | symbolP = symbol_find_or_make (name); | |
4150 | *p = c; | |
4151 | ||
4152 | if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 | |
4153 | && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) | |
4154 | { | |
4155 | as_bad (_("bad .reserve segment -- expected BSS segment")); | |
4156 | return; | |
4157 | } | |
4158 | ||
4159 | if (input_line_pointer[2] == '.') | |
4160 | input_line_pointer += 7; | |
4161 | else | |
4162 | input_line_pointer += 6; | |
4163 | SKIP_WHITESPACE (); | |
4164 | ||
4165 | if (*input_line_pointer == ',') | |
4166 | { | |
4167 | ++input_line_pointer; | |
4168 | ||
4169 | SKIP_WHITESPACE (); | |
4170 | if (*input_line_pointer == '\n') | |
4171 | { | |
4172 | as_bad (_("missing alignment")); | |
4173 | ignore_rest_of_line (); | |
4174 | return; | |
4175 | } | |
4176 | ||
4177 | align = (int) get_absolute_expression (); | |
4178 | ||
4179 | #ifndef OBJ_ELF | |
4180 | if (align > max_alignment) | |
4181 | { | |
4182 | align = max_alignment; | |
4183 | as_warn (_("alignment too large; assuming %d"), align); | |
4184 | } | |
4185 | #endif | |
4186 | ||
4187 | if (align < 0) | |
4188 | { | |
4189 | as_bad (_("negative alignment")); | |
4190 | ignore_rest_of_line (); | |
4191 | return; | |
4192 | } | |
4193 | ||
4194 | if (align != 0) | |
4195 | { | |
f17c130b | 4196 | temp = mylog2 (align); |
252b5132 RH |
4197 | if (temp < 0) |
4198 | { | |
4199 | as_bad (_("alignment not a power of 2")); | |
4200 | ignore_rest_of_line (); | |
4201 | return; | |
4202 | } | |
4203 | ||
4204 | align = temp; | |
4205 | } | |
4206 | ||
4207 | record_alignment (bss_section, align); | |
4208 | } | |
4209 | else | |
4210 | align = 0; | |
4211 | ||
4212 | if (!S_IS_DEFINED (symbolP) | |
4213 | #ifdef OBJ_AOUT | |
4214 | && S_GET_OTHER (symbolP) == 0 | |
4215 | && S_GET_DESC (symbolP) == 0 | |
4216 | #endif | |
4217 | ) | |
4218 | { | |
4219 | if (! need_pass_2) | |
4220 | { | |
4221 | char *pfrag; | |
4222 | segT current_seg = now_seg; | |
4223 | subsegT current_subseg = now_subseg; | |
4224 | ||
e0c6ed95 AM |
4225 | /* Switch to bss. */ |
4226 | subseg_set (bss_section, 1); | |
252b5132 RH |
4227 | |
4228 | if (align) | |
e0c6ed95 AM |
4229 | /* Do alignment. */ |
4230 | frag_align (align, 0, 0); | |
252b5132 | 4231 | |
e0c6ed95 | 4232 | /* Detach from old frag. */ |
ab3e48dc | 4233 | if (S_GET_SEGMENT (symbolP) == bss_section) |
49309057 | 4234 | symbol_get_frag (symbolP)->fr_symbol = NULL; |
252b5132 | 4235 | |
49309057 | 4236 | symbol_set_frag (symbolP, frag_now); |
e0c6ed95 AM |
4237 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
4238 | (offsetT) size, (char *) 0); | |
252b5132 RH |
4239 | *pfrag = 0; |
4240 | ||
4241 | S_SET_SEGMENT (symbolP, bss_section); | |
4242 | ||
4243 | subseg_set (current_seg, current_subseg); | |
4244 | ||
4245 | #ifdef OBJ_ELF | |
4246 | S_SET_SIZE (symbolP, size); | |
4247 | #endif | |
4248 | } | |
4249 | } | |
4250 | else | |
4251 | { | |
20203fb9 | 4252 | as_warn (_("Ignoring attempt to re-define symbol %s"), |
ab3e48dc | 4253 | S_GET_NAME (symbolP)); |
20203fb9 | 4254 | } |
252b5132 RH |
4255 | |
4256 | demand_empty_rest_of_line (); | |
4257 | } | |
4258 | ||
4259 | static void | |
5a49b8ac | 4260 | s_common (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4261 | { |
4262 | char *name; | |
4263 | char c; | |
4264 | char *p; | |
685736be | 4265 | offsetT temp, size; |
252b5132 RH |
4266 | symbolS *symbolP; |
4267 | ||
d02603dc | 4268 | c = get_symbol_name (&name); |
e0c6ed95 | 4269 | /* Just after name is now '\0'. */ |
252b5132 RH |
4270 | p = input_line_pointer; |
4271 | *p = c; | |
d02603dc | 4272 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
4273 | if (*input_line_pointer != ',') |
4274 | { | |
4275 | as_bad (_("Expected comma after symbol-name")); | |
4276 | ignore_rest_of_line (); | |
4277 | return; | |
4278 | } | |
e0c6ed95 AM |
4279 | |
4280 | /* Skip ','. */ | |
4281 | input_line_pointer++; | |
4282 | ||
252b5132 RH |
4283 | if ((temp = get_absolute_expression ()) < 0) |
4284 | { | |
685736be NC |
4285 | as_bad (_(".COMMon length (%lu) out of range ignored"), |
4286 | (unsigned long) temp); | |
252b5132 RH |
4287 | ignore_rest_of_line (); |
4288 | return; | |
4289 | } | |
4290 | size = temp; | |
4291 | *p = 0; | |
4292 | symbolP = symbol_find_or_make (name); | |
4293 | *p = c; | |
4294 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
4295 | { | |
4296 | as_bad (_("Ignoring attempt to re-define symbol")); | |
4297 | ignore_rest_of_line (); | |
4298 | return; | |
4299 | } | |
4300 | if (S_GET_VALUE (symbolP) != 0) | |
4301 | { | |
4302 | if (S_GET_VALUE (symbolP) != (valueT) size) | |
4303 | { | |
364b6d8b JJ |
4304 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), |
4305 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); | |
252b5132 RH |
4306 | } |
4307 | } | |
4308 | else | |
4309 | { | |
4310 | #ifndef OBJ_ELF | |
4311 | S_SET_VALUE (symbolP, (valueT) size); | |
4312 | S_SET_EXTERNAL (symbolP); | |
4313 | #endif | |
4314 | } | |
7dcc9865 | 4315 | know (symbol_get_frag (symbolP) == &zero_address_frag); |
252b5132 RH |
4316 | if (*input_line_pointer != ',') |
4317 | { | |
4318 | as_bad (_("Expected comma after common length")); | |
4319 | ignore_rest_of_line (); | |
4320 | return; | |
4321 | } | |
4322 | input_line_pointer++; | |
4323 | SKIP_WHITESPACE (); | |
4324 | if (*input_line_pointer != '"') | |
4325 | { | |
4326 | temp = get_absolute_expression (); | |
4327 | ||
4328 | #ifndef OBJ_ELF | |
4329 | if (temp > max_alignment) | |
4330 | { | |
4331 | temp = max_alignment; | |
f17c130b | 4332 | as_warn (_("alignment too large; assuming %ld"), (long) temp); |
252b5132 RH |
4333 | } |
4334 | #endif | |
4335 | ||
4336 | if (temp < 0) | |
4337 | { | |
4338 | as_bad (_("negative alignment")); | |
4339 | ignore_rest_of_line (); | |
4340 | return; | |
4341 | } | |
4342 | ||
4343 | #ifdef OBJ_ELF | |
49309057 | 4344 | if (symbol_get_obj (symbolP)->local) |
252b5132 RH |
4345 | { |
4346 | segT old_sec; | |
4347 | int old_subsec; | |
252b5132 RH |
4348 | int align; |
4349 | ||
4350 | old_sec = now_seg; | |
4351 | old_subsec = now_subseg; | |
4352 | ||
4353 | if (temp == 0) | |
4354 | align = 0; | |
4355 | else | |
f17c130b | 4356 | align = mylog2 (temp); |
252b5132 RH |
4357 | |
4358 | if (align < 0) | |
4359 | { | |
4360 | as_bad (_("alignment not a power of 2")); | |
4361 | ignore_rest_of_line (); | |
4362 | return; | |
4363 | } | |
4364 | ||
4365 | record_alignment (bss_section, align); | |
4366 | subseg_set (bss_section, 0); | |
4367 | if (align) | |
4368 | frag_align (align, 0, 0); | |
4369 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
4370 | symbol_get_frag (symbolP)->fr_symbol = 0; |
4371 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
4372 | p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
4373 | (offsetT) size, (char *) 0); | |
4374 | *p = 0; | |
4375 | S_SET_SEGMENT (symbolP, bss_section); | |
4376 | S_CLEAR_EXTERNAL (symbolP); | |
4377 | S_SET_SIZE (symbolP, size); | |
4378 | subseg_set (old_sec, old_subsec); | |
4379 | } | |
4380 | else | |
e0c6ed95 | 4381 | #endif /* OBJ_ELF */ |
252b5132 RH |
4382 | { |
4383 | allocate_common: | |
4384 | S_SET_VALUE (symbolP, (valueT) size); | |
4385 | #ifdef OBJ_ELF | |
4386 | S_SET_ALIGN (symbolP, temp); | |
4387 | S_SET_SIZE (symbolP, size); | |
4388 | #endif | |
4389 | S_SET_EXTERNAL (symbolP); | |
4390 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); | |
4391 | } | |
4392 | } | |
4393 | else | |
4394 | { | |
4395 | input_line_pointer++; | |
4396 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ | |
4397 | if (*input_line_pointer == '.') | |
4398 | input_line_pointer++; | |
4399 | /* @@ Some say data, some say bss. */ | |
4400 | if (strncmp (input_line_pointer, "bss\"", 4) | |
4401 | && strncmp (input_line_pointer, "data\"", 5)) | |
4402 | { | |
4403 | while (*--input_line_pointer != '"') | |
4404 | ; | |
4405 | input_line_pointer--; | |
4406 | goto bad_common_segment; | |
4407 | } | |
4408 | while (*input_line_pointer++ != '"') | |
4409 | ; | |
4410 | goto allocate_common; | |
4411 | } | |
4412 | ||
49309057 | 4413 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; |
252b5132 RH |
4414 | |
4415 | demand_empty_rest_of_line (); | |
4416 | return; | |
4417 | ||
4418 | { | |
4419 | bad_common_segment: | |
4420 | p = input_line_pointer; | |
4421 | while (*p && *p != '\n') | |
4422 | p++; | |
4423 | c = *p; | |
4424 | *p = '\0'; | |
4425 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); | |
4426 | *p = c; | |
4427 | input_line_pointer = p; | |
4428 | ignore_rest_of_line (); | |
4429 | return; | |
4430 | } | |
4431 | } | |
4432 | ||
67c1ffbe | 4433 | /* Handle the .empty pseudo-op. This suppresses the warnings about |
252b5132 RH |
4434 | invalid delay slot usage. */ |
4435 | ||
4436 | static void | |
5a49b8ac | 4437 | s_empty (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4438 | { |
4439 | /* The easy way to implement is to just forget about the last | |
4440 | instruction. */ | |
4441 | last_insn = NULL; | |
4442 | } | |
4443 | ||
4444 | static void | |
5a49b8ac | 4445 | s_seg (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4446 | { |
4447 | ||
4448 | if (strncmp (input_line_pointer, "\"text\"", 6) == 0) | |
4449 | { | |
4450 | input_line_pointer += 6; | |
4451 | s_text (0); | |
4452 | return; | |
4453 | } | |
4454 | if (strncmp (input_line_pointer, "\"data\"", 6) == 0) | |
4455 | { | |
4456 | input_line_pointer += 6; | |
4457 | s_data (0); | |
4458 | return; | |
4459 | } | |
4460 | if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) | |
4461 | { | |
4462 | input_line_pointer += 7; | |
4463 | s_data1 (); | |
4464 | return; | |
4465 | } | |
4466 | if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) | |
4467 | { | |
4468 | input_line_pointer += 5; | |
4469 | /* We only support 2 segments -- text and data -- for now, so | |
4470 | things in the "bss segment" will have to go into data for now. | |
e0c6ed95 AM |
4471 | You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ |
4472 | subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ | |
252b5132 RH |
4473 | return; |
4474 | } | |
4475 | as_bad (_("Unknown segment type")); | |
4476 | demand_empty_rest_of_line (); | |
4477 | } | |
4478 | ||
4479 | static void | |
5a49b8ac | 4480 | s_data1 (void) |
252b5132 RH |
4481 | { |
4482 | subseg_set (data_section, 1); | |
4483 | demand_empty_rest_of_line (); | |
4484 | } | |
4485 | ||
4486 | static void | |
5a49b8ac | 4487 | s_proc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4488 | { |
4489 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4490 | { | |
4491 | ++input_line_pointer; | |
4492 | } | |
4493 | ++input_line_pointer; | |
4494 | } | |
4495 | ||
4496 | /* This static variable is set by s_uacons to tell sparc_cons_align | |
67c1ffbe | 4497 | that the expression does not need to be aligned. */ |
252b5132 RH |
4498 | |
4499 | static int sparc_no_align_cons = 0; | |
4500 | ||
4501 | /* This handles the unaligned space allocation pseudo-ops, such as | |
4502 | .uaword. .uaword is just like .word, but the value does not need | |
4503 | to be aligned. */ | |
4504 | ||
4505 | static void | |
5a49b8ac | 4506 | s_uacons (int bytes) |
252b5132 RH |
4507 | { |
4508 | /* Tell sparc_cons_align not to align this value. */ | |
4509 | sparc_no_align_cons = 1; | |
4510 | cons (bytes); | |
4ffadb11 | 4511 | sparc_no_align_cons = 0; |
252b5132 RH |
4512 | } |
4513 | ||
cf9a1301 RH |
4514 | /* This handles the native word allocation pseudo-op .nword. |
4515 | For sparc_arch_size 32 it is equivalent to .word, for | |
4516 | sparc_arch_size 64 it is equivalent to .xword. */ | |
4517 | ||
4518 | static void | |
5a49b8ac | 4519 | s_ncons (int bytes ATTRIBUTE_UNUSED) |
cf9a1301 RH |
4520 | { |
4521 | cons (sparc_arch_size == 32 ? 4 : 8); | |
4522 | } | |
4523 | ||
6d8809aa RH |
4524 | #ifdef OBJ_ELF |
4525 | /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a | |
4526 | global register. | |
4527 | The syntax is: | |
e0c6ed95 | 4528 | |
6d8809aa | 4529 | .register %g[2367],{#scratch|symbolname|#ignore} |
e0c6ed95 | 4530 | */ |
6d8809aa RH |
4531 | |
4532 | static void | |
5a49b8ac | 4533 | s_register (int ignore ATTRIBUTE_UNUSED) |
6d8809aa RH |
4534 | { |
4535 | char c; | |
4536 | int reg; | |
4537 | int flags; | |
d02603dc | 4538 | char *regname; |
6d8809aa RH |
4539 | |
4540 | if (input_line_pointer[0] != '%' | |
4541 | || input_line_pointer[1] != 'g' | |
4542 | || ((input_line_pointer[2] & ~1) != '2' | |
4543 | && (input_line_pointer[2] & ~1) != '6') | |
4544 | || input_line_pointer[3] != ',') | |
4545 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
4546 | reg = input_line_pointer[2] - '0'; | |
4547 | input_line_pointer += 4; | |
4548 | ||
4549 | if (*input_line_pointer == '#') | |
4550 | { | |
4551 | ++input_line_pointer; | |
d02603dc | 4552 | c = get_symbol_name (®name); |
6d8809aa RH |
4553 | if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) |
4554 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
ab3e48dc | 4555 | if (regname[0] == 'i') |
6d8809aa RH |
4556 | regname = NULL; |
4557 | else | |
e87de513 | 4558 | regname = (char *) ""; |
6d8809aa RH |
4559 | } |
4560 | else | |
4561 | { | |
d02603dc | 4562 | c = get_symbol_name (®name); |
6d8809aa | 4563 | } |
d02603dc | 4564 | |
6d8809aa RH |
4565 | if (sparc_arch_size == 64) |
4566 | { | |
e0c6ed95 | 4567 | if (globals[reg]) |
6d8809aa | 4568 | { |
e0c6ed95 AM |
4569 | if ((regname && globals[reg] != (symbolS *) 1 |
4570 | && strcmp (S_GET_NAME (globals[reg]), regname)) | |
4571 | || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) | |
6d8809aa RH |
4572 | as_bad (_("redefinition of global register")); |
4573 | } | |
4574 | else | |
4575 | { | |
4576 | if (regname == NULL) | |
e0c6ed95 | 4577 | globals[reg] = (symbolS *) 1; |
6d8809aa RH |
4578 | else |
4579 | { | |
4580 | if (*regname) | |
4581 | { | |
4582 | if (symbol_find (regname)) | |
4583 | as_bad (_("Register symbol %s already defined."), | |
4584 | regname); | |
4585 | } | |
e0c6ed95 AM |
4586 | globals[reg] = symbol_make (regname); |
4587 | flags = symbol_get_bfdsym (globals[reg])->flags; | |
6d8809aa RH |
4588 | if (! *regname) |
4589 | flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); | |
4590 | if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) | |
4591 | flags |= BSF_GLOBAL; | |
e0c6ed95 AM |
4592 | symbol_get_bfdsym (globals[reg])->flags = flags; |
4593 | S_SET_VALUE (globals[reg], (valueT) reg); | |
4594 | S_SET_ALIGN (globals[reg], reg); | |
4595 | S_SET_SIZE (globals[reg], 0); | |
6d8809aa RH |
4596 | /* Although we actually want undefined_section here, |
4597 | we have to use absolute_section, because otherwise | |
4598 | generic as code will make it a COM section. | |
4599 | We fix this up in sparc_adjust_symtab. */ | |
e0c6ed95 AM |
4600 | S_SET_SEGMENT (globals[reg], absolute_section); |
4601 | S_SET_OTHER (globals[reg], 0); | |
4602 | elf_symbol (symbol_get_bfdsym (globals[reg])) | |
6d8809aa RH |
4603 | ->internal_elf_sym.st_info = |
4604 | ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); | |
e0c6ed95 | 4605 | elf_symbol (symbol_get_bfdsym (globals[reg])) |
6d8809aa RH |
4606 | ->internal_elf_sym.st_shndx = SHN_UNDEF; |
4607 | } | |
4608 | } | |
4609 | } | |
4610 | ||
d02603dc | 4611 | (void) restore_line_pointer (c); |
6d8809aa RH |
4612 | |
4613 | demand_empty_rest_of_line (); | |
4614 | } | |
4615 | ||
4616 | /* Adjust the symbol table. We set undefined sections for STT_REGISTER | |
4617 | symbols which need it. */ | |
e0c6ed95 | 4618 | |
6d8809aa | 4619 | void |
5a49b8ac | 4620 | sparc_adjust_symtab (void) |
6d8809aa RH |
4621 | { |
4622 | symbolS *sym; | |
e0c6ed95 | 4623 | |
6d8809aa RH |
4624 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
4625 | { | |
4626 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4627 | ->internal_elf_sym.st_info) != STT_REGISTER) | |
4628 | continue; | |
4629 | ||
4630 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4631 | ->internal_elf_sym.st_shndx != SHN_UNDEF)) | |
4632 | continue; | |
4633 | ||
4634 | S_SET_SEGMENT (sym, undefined_section); | |
4635 | } | |
4636 | } | |
4637 | #endif | |
4638 | ||
252b5132 RH |
4639 | /* If the --enforce-aligned-data option is used, we require .word, |
4640 | et. al., to be aligned correctly. We do it by setting up an | |
4641 | rs_align_code frag, and checking in HANDLE_ALIGN to make sure that | |
4642 | no unexpected alignment was introduced. | |
4643 | ||
4644 | The SunOS and Solaris native assemblers enforce aligned data by | |
4645 | default. We don't want to do that, because gcc can deliberately | |
4646 | generate misaligned data if the packed attribute is used. Instead, | |
4647 | we permit misaligned data by default, and permit the user to set an | |
4648 | option to check for it. */ | |
4649 | ||
4650 | void | |
5a49b8ac | 4651 | sparc_cons_align (int nbytes) |
252b5132 RH |
4652 | { |
4653 | int nalign; | |
252b5132 RH |
4654 | |
4655 | /* Only do this if we are enforcing aligned data. */ | |
4656 | if (! enforce_aligned_data) | |
4657 | return; | |
4658 | ||
0f2712ed | 4659 | /* Don't align if this is an unaligned pseudo-op. */ |
252b5132 | 4660 | if (sparc_no_align_cons) |
0f2712ed | 4661 | return; |
252b5132 | 4662 | |
f17c130b | 4663 | nalign = mylog2 (nbytes); |
252b5132 RH |
4664 | if (nalign == 0) |
4665 | return; | |
4666 | ||
9c2799c2 | 4667 | gas_assert (nalign > 0); |
252b5132 RH |
4668 | |
4669 | if (now_seg == absolute_section) | |
4670 | { | |
4671 | if ((abs_section_offset & ((1 << nalign) - 1)) != 0) | |
4672 | as_bad (_("misaligned data")); | |
4673 | return; | |
4674 | } | |
4675 | ||
87975d2a AM |
4676 | frag_var (rs_align_test, 1, 1, (relax_substateT) 0, |
4677 | (symbolS *) NULL, (offsetT) nalign, (char *) NULL); | |
252b5132 RH |
4678 | |
4679 | record_alignment (now_seg, nalign); | |
4680 | } | |
4681 | ||
0a9ef439 | 4682 | /* This is called from HANDLE_ALIGN in tc-sparc.h. */ |
252b5132 RH |
4683 | |
4684 | void | |
5a49b8ac | 4685 | sparc_handle_align (fragS *fragp) |
252b5132 | 4686 | { |
0a9ef439 RH |
4687 | int count, fix; |
4688 | char *p; | |
4689 | ||
4690 | count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
bfb32b52 | 4691 | |
0a9ef439 | 4692 | switch (fragp->fr_type) |
252b5132 | 4693 | { |
0a9ef439 RH |
4694 | case rs_align_test: |
4695 | if (count != 0) | |
4696 | as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); | |
4697 | break; | |
e0c6ed95 | 4698 | |
0a9ef439 RH |
4699 | case rs_align_code: |
4700 | p = fragp->fr_literal + fragp->fr_fix; | |
4701 | fix = 0; | |
e0c6ed95 | 4702 | |
0a9ef439 RH |
4703 | if (count & 3) |
4704 | { | |
4705 | fix = count & 3; | |
4706 | memset (p, 0, fix); | |
4707 | p += fix; | |
4708 | count -= fix; | |
4709 | } | |
e0c6ed95 | 4710 | |
0a9ef439 RH |
4711 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) |
4712 | { | |
4713 | unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ | |
4714 | if (INSN_BIG_ENDIAN) | |
4715 | number_to_chars_bigendian (p, wval, 4); | |
4716 | else | |
4717 | number_to_chars_littleendian (p, wval, 4); | |
4718 | p += 4; | |
4719 | count -= 4; | |
4720 | fix += 4; | |
e0c6ed95 | 4721 | } |
0a9ef439 RH |
4722 | |
4723 | if (INSN_BIG_ENDIAN) | |
4724 | number_to_chars_bigendian (p, 0x01000000, 4); | |
4725 | else | |
4726 | number_to_chars_littleendian (p, 0x01000000, 4); | |
4727 | ||
4728 | fragp->fr_fix += fix; | |
4729 | fragp->fr_var = 4; | |
4730 | break; | |
4731 | ||
4732 | default: | |
4733 | break; | |
252b5132 RH |
4734 | } |
4735 | } | |
4736 | ||
4737 | #ifdef OBJ_ELF | |
4738 | /* Some special processing for a Sparc ELF file. */ | |
4739 | ||
4740 | void | |
5a49b8ac | 4741 | sparc_elf_final_processing (void) |
252b5132 RH |
4742 | { |
4743 | /* Set the Sparc ELF flag bits. FIXME: There should probably be some | |
4744 | sort of BFD interface for this. */ | |
4745 | if (sparc_arch_size == 64) | |
4746 | { | |
4747 | switch (sparc_memory_model) | |
4748 | { | |
4749 | case MM_RMO: | |
4750 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; | |
4751 | break; | |
4752 | case MM_PSO: | |
4753 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; | |
4754 | break; | |
4755 | default: | |
4756 | break; | |
4757 | } | |
4758 | } | |
4759 | else if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
4760 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; | |
4761 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
4762 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; | |
19f7b010 JJ |
4763 | else if (current_architecture == SPARC_OPCODE_ARCH_V9B) |
4764 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; | |
252b5132 | 4765 | } |
bd5e6e7e | 4766 | |
62ebcb5c | 4767 | const char * |
5a49b8ac | 4768 | sparc_cons (expressionS *exp, int size) |
bd5e6e7e JJ |
4769 | { |
4770 | char *save; | |
62ebcb5c | 4771 | const char *sparc_cons_special_reloc = NULL; |
bd5e6e7e JJ |
4772 | |
4773 | SKIP_WHITESPACE (); | |
bd5e6e7e JJ |
4774 | save = input_line_pointer; |
4775 | if (input_line_pointer[0] == '%' | |
4776 | && input_line_pointer[1] == 'r' | |
4777 | && input_line_pointer[2] == '_') | |
4778 | { | |
4779 | if (strncmp (input_line_pointer + 3, "disp", 4) == 0) | |
4780 | { | |
4781 | input_line_pointer += 7; | |
4782 | sparc_cons_special_reloc = "disp"; | |
4783 | } | |
4784 | else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) | |
4785 | { | |
4786 | if (size != 4 && size != 8) | |
4787 | as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); | |
4788 | else | |
4789 | { | |
4790 | input_line_pointer += 6; | |
4791 | sparc_cons_special_reloc = "plt"; | |
4792 | } | |
4793 | } | |
b9734f35 JJ |
4794 | else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) |
4795 | { | |
4796 | if (size != 4 && size != 8) | |
4797 | as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); | |
4798 | else | |
4799 | { | |
4800 | input_line_pointer += 13; | |
4801 | sparc_cons_special_reloc = "tls_dtpoff"; | |
4802 | } | |
4803 | } | |
bd5e6e7e JJ |
4804 | if (sparc_cons_special_reloc) |
4805 | { | |
4806 | int bad = 0; | |
4807 | ||
4808 | switch (size) | |
4809 | { | |
4810 | case 1: | |
4811 | if (*input_line_pointer != '8') | |
4812 | bad = 1; | |
4813 | input_line_pointer--; | |
4814 | break; | |
4815 | case 2: | |
4816 | if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') | |
4817 | bad = 1; | |
4818 | break; | |
4819 | case 4: | |
4820 | if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') | |
4821 | bad = 1; | |
4822 | break; | |
4823 | case 8: | |
4824 | if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') | |
4825 | bad = 1; | |
4826 | break; | |
4827 | default: | |
4828 | bad = 1; | |
4829 | break; | |
4830 | } | |
4831 | ||
4832 | if (bad) | |
4833 | { | |
4834 | as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), | |
4835 | sparc_cons_special_reloc, size * 8, size); | |
4836 | } | |
4837 | else | |
4838 | { | |
4839 | input_line_pointer += 2; | |
4840 | if (*input_line_pointer != '(') | |
4841 | { | |
4842 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4843 | sparc_cons_special_reloc, size * 8); | |
4844 | bad = 1; | |
4845 | } | |
4846 | } | |
4847 | ||
4848 | if (bad) | |
4849 | { | |
4850 | input_line_pointer = save; | |
4851 | sparc_cons_special_reloc = NULL; | |
4852 | } | |
4853 | else | |
4854 | { | |
4855 | int c; | |
4856 | char *end = ++input_line_pointer; | |
4857 | int npar = 0; | |
4858 | ||
4859 | while (! is_end_of_line[(c = *end)]) | |
4860 | { | |
4861 | if (c == '(') | |
4862 | npar++; | |
4863 | else if (c == ')') | |
4864 | { | |
4865 | if (!npar) | |
4866 | break; | |
4867 | npar--; | |
4868 | } | |
4869 | end++; | |
4870 | } | |
4871 | ||
4872 | if (c != ')') | |
4873 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4874 | sparc_cons_special_reloc, size * 8); | |
4875 | else | |
4876 | { | |
4877 | *end = '\0'; | |
4878 | expression (exp); | |
4879 | *end = c; | |
4880 | if (input_line_pointer != end) | |
4881 | { | |
4882 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4883 | sparc_cons_special_reloc, size * 8); | |
4884 | } | |
4885 | else | |
4886 | { | |
4887 | input_line_pointer++; | |
4888 | SKIP_WHITESPACE (); | |
4889 | c = *input_line_pointer; | |
4890 | if (! is_end_of_line[c] && c != ',') | |
4891 | as_bad (_("Illegal operands: garbage after %%r_%s%d()"), | |
4892 | sparc_cons_special_reloc, size * 8); | |
4893 | } | |
4894 | } | |
4895 | } | |
4896 | } | |
4897 | } | |
4898 | if (sparc_cons_special_reloc == NULL) | |
4899 | expression (exp); | |
62ebcb5c | 4900 | return sparc_cons_special_reloc; |
bd5e6e7e JJ |
4901 | } |
4902 | ||
252b5132 RH |
4903 | #endif |
4904 | ||
4905 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
4906 | reloc for a cons. We could use the definition there, except that | |
4907 | we want to handle little endian relocs specially. */ | |
4908 | ||
4909 | void | |
5a49b8ac AM |
4910 | cons_fix_new_sparc (fragS *frag, |
4911 | int where, | |
4912 | unsigned int nbytes, | |
62ebcb5c AM |
4913 | expressionS *exp, |
4914 | const char *sparc_cons_special_reloc) | |
252b5132 RH |
4915 | { |
4916 | bfd_reloc_code_real_type r; | |
4917 | ||
4918 | r = (nbytes == 1 ? BFD_RELOC_8 : | |
4919 | (nbytes == 2 ? BFD_RELOC_16 : | |
4920 | (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
4921 | ||
0f2712ed NC |
4922 | if (target_little_endian_data |
4923 | && nbytes == 4 | |
e0c6ed95 | 4924 | && now_seg->flags & SEC_ALLOC) |
252b5132 | 4925 | r = BFD_RELOC_SPARC_REV32; |
0f2712ed | 4926 | |
02442566 ST |
4927 | #ifdef TE_SOLARIS |
4928 | /* The Solaris linker does not allow R_SPARC_UA64 | |
4929 | relocations for 32-bit executables. */ | |
4930 | if (!target_little_endian_data | |
4931 | && sparc_arch_size != 64 | |
4932 | && r == BFD_RELOC_64) | |
4933 | r = BFD_RELOC_32; | |
4934 | #endif | |
4935 | ||
bd5e6e7e JJ |
4936 | if (sparc_cons_special_reloc) |
4937 | { | |
4938 | if (*sparc_cons_special_reloc == 'd') | |
4939 | switch (nbytes) | |
4940 | { | |
4941 | case 1: r = BFD_RELOC_8_PCREL; break; | |
4942 | case 2: r = BFD_RELOC_16_PCREL; break; | |
4943 | case 4: r = BFD_RELOC_32_PCREL; break; | |
4944 | case 8: r = BFD_RELOC_64_PCREL; break; | |
4945 | default: abort (); | |
4946 | } | |
b9734f35 | 4947 | else if (*sparc_cons_special_reloc == 'p') |
bd5e6e7e JJ |
4948 | switch (nbytes) |
4949 | { | |
4950 | case 4: r = BFD_RELOC_SPARC_PLT32; break; | |
4951 | case 8: r = BFD_RELOC_SPARC_PLT64; break; | |
4952 | } | |
b9734f35 JJ |
4953 | else |
4954 | switch (nbytes) | |
4955 | { | |
4956 | case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; | |
4957 | case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; | |
4958 | } | |
bd5e6e7e JJ |
4959 | } |
4960 | else if (sparc_no_align_cons) | |
0f2712ed NC |
4961 | { |
4962 | switch (nbytes) | |
4963 | { | |
4964 | case 2: r = BFD_RELOC_SPARC_UA16; break; | |
4965 | case 4: r = BFD_RELOC_SPARC_UA32; break; | |
02442566 ST |
4966 | #ifdef TE_SOLARIS |
4967 | /* The Solaris linker does not allow R_SPARC_UA64 | |
4968 | relocations for 32-bit executables. */ | |
4969 | case 8: r = sparc_arch_size == 64 ? | |
4970 | BFD_RELOC_SPARC_UA64 : BFD_RELOC_SPARC_UA32; break; | |
4971 | #else | |
0f2712ed | 4972 | case 8: r = BFD_RELOC_SPARC_UA64; break; |
02442566 | 4973 | #endif |
0f2712ed NC |
4974 | default: abort (); |
4975 | } | |
4ffadb11 | 4976 | } |
0f2712ed | 4977 | |
252b5132 | 4978 | fix_new_exp (frag, where, (int) nbytes, exp, 0, r); |
364b6d8b JJ |
4979 | } |
4980 | ||
4981 | void | |
5a49b8ac | 4982 | sparc_cfi_frame_initial_instructions (void) |
364b6d8b JJ |
4983 | { |
4984 | cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); | |
4985 | } | |
4986 | ||
4987 | int | |
1df69f4f | 4988 | sparc_regname_to_dw2regnum (char *regname) |
364b6d8b | 4989 | { |
74b4e47a TS |
4990 | char *q; |
4991 | int i; | |
364b6d8b JJ |
4992 | |
4993 | if (!regname[0]) | |
4994 | return -1; | |
4995 | ||
74b4e47a TS |
4996 | switch (regname[0]) |
4997 | { | |
4998 | case 'g': i = 0; break; | |
4999 | case 'o': i = 1; break; | |
5000 | case 'l': i = 2; break; | |
5001 | case 'i': i = 3; break; | |
5002 | default: i = -1; break; | |
5003 | } | |
5004 | if (i != -1) | |
364b6d8b JJ |
5005 | { |
5006 | if (regname[1] < '0' || regname[1] > '8' || regname[2]) | |
5007 | return -1; | |
74b4e47a | 5008 | return i * 8 + regname[1] - '0'; |
364b6d8b JJ |
5009 | } |
5010 | if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) | |
5011 | return 14; | |
5012 | if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) | |
5013 | return 30; | |
5014 | if (regname[0] == 'f' || regname[0] == 'r') | |
5015 | { | |
5016 | unsigned int regnum; | |
5017 | ||
5018 | regnum = strtoul (regname + 1, &q, 10); | |
74b4e47a | 5019 | if (q == NULL || *q) |
364b6d8b JJ |
5020 | return -1; |
5021 | if (regnum >= ((regname[0] == 'f' | |
5022 | && SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
5023 | ? 64 : 32)) | |
5024 | return -1; | |
5025 | if (regname[0] == 'f') | |
5026 | { | |
5027 | regnum += 32; | |
5028 | if (regnum >= 64 && (regnum & 1)) | |
5029 | return -1; | |
5030 | } | |
5031 | return regnum; | |
5032 | } | |
5033 | return -1; | |
5034 | } | |
5035 | ||
5036 | void | |
5037 | sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) | |
5038 | { | |
364b6d8b | 5039 | sparc_no_align_cons = 1; |
62ebcb5c | 5040 | emit_expr_with_reloc (exp, nbytes, "disp"); |
364b6d8b | 5041 | sparc_no_align_cons = 0; |
252b5132 | 5042 | } |