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[deliverable/binutils-gdb.git] / gas / config / tc-sparc.c
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252b5132 1/* tc-sparc.c -- Assemble for the SPARC
f7e42eb4 2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
87975d2a 3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
e0c6ed95 4 Free Software Foundation, Inc.
252b5132
RH		 5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
ec2655a6 9 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
4b4da160
NC		 19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
252b5132 21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "subsegs.h"
25
26#include "opcode/sparc.h"
364b6d8b 27#include "dw2gencfi.h"
252b5132
RH		 28
29#ifdef OBJ_ELF
30#include "elf/sparc.h"
732d96b6 31#include "dwarf2dbg.h"
252b5132
RH		 32#endif
33
6c1b24e4
AO		 34/* Some ancient Sun C compilers would not take such hex constants as
35 unsigned, and would end up sign-extending them to form an offsetT,
36 so use these constants instead. */
37#define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
38#define U0x80000000 ((((unsigned long) 1 << 16) << 15))
39
5a49b8ac
AM		 40static int sparc_ip (char *, const struct sparc_opcode **);
41static int parse_keyword_arg (int (*) (const char *), char **, int *);
42static int parse_const_expr_arg (char **, int *);
43static int get_expression (char *);
252b5132
RH		 44
45/* Default architecture. */
46/* ??? The default value should be V8, but sparclite support was added
47 by making it the default. GCC now passes -Asparclite, so maybe sometime in
48 the future we can set this to V8. */
49#ifndef DEFAULT_ARCH
50#define DEFAULT_ARCH "sparclite"
51#endif
52static char *default_arch = DEFAULT_ARCH;
53
54/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
55 have been set. */
56static int default_init_p;
57
58/* Current architecture. We don't bump up unless necessary. */
59static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
60
61/* The maximum architecture level we can bump up to.
62 In a 32 bit environment, don't allow bumping up to v9 by default.
63 The native assembler works this way. The user is required to pass
64 an explicit argument before we'll create v9 object files. However, if
65 we don't see any v9 insns, a v8plus object file is not created. */
66static enum sparc_opcode_arch_val max_architecture;
67
68/* Either 32 or 64, selects file format. */
69static int sparc_arch_size;
70/* Initial (default) value, recorded separately in case a user option
71 changes the value before md_show_usage is called. */
72static int default_arch_size;
73
74#ifdef OBJ_ELF
75/* The currently selected v9 memory model. Currently only used for
76 ELF. */
77static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
78#endif
79
80static int architecture_requested;
81static int warn_on_bump;
82
83/* If warn_on_bump and the needed architecture is higher than this
84 architecture, issue a warning. */
85static enum sparc_opcode_arch_val warn_after_architecture;
86
6d8809aa
RH		 87/* Non-zero if as should generate error if an undeclared g[23] register
88 has been used in -64. */
89static int no_undeclared_regs;
90
6faf3d66
JJ		 91/* Non-zero if we should try to relax jumps and calls. */
92static int sparc_relax;
93
252b5132
RH		 94/* Non-zero if we are generating PIC code. */
95int sparc_pic_code;
96
97/* Non-zero if we should give an error when misaligned data is seen. */
98static int enforce_aligned_data;
99
100extern int target_big_endian;
101
102static int target_little_endian_data;
103
6d8809aa
RH		 104/* Symbols for global registers on v9. */
105static symbolS *globals[8];
106
364b6d8b
JJ		 107/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
108int sparc_cie_data_alignment;
109
252b5132
RH		 110/* V9 and 86x have big and little endian data, but instructions are always big
111 endian. The sparclet has bi-endian support but both data and insns have
112 the same endianness. Global `target_big_endian' is used for data.
113 The following macro is used for instructions. */
114#ifndef INSN_BIG_ENDIAN
115#define INSN_BIG_ENDIAN (target_big_endian \
116 || default_arch_type == sparc86x \
117 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
118#endif
119
e0c6ed95 120/* Handle of the OPCODE hash table. */
252b5132
RH		 121static struct hash_control *op_hash;
122
5a49b8ac
AM		 123static void s_data1 (void);
124static void s_seg (int);
125static void s_proc (int);
126static void s_reserve (int);
127static void s_common (int);
128static void s_empty (int);
129static void s_uacons (int);
130static void s_ncons (int);
a7982600 131#ifdef OBJ_ELF
5a49b8ac 132static void s_register (int);
a7982600 133#endif
252b5132
RH		 134
135const pseudo_typeS md_pseudo_table[] =
136{
e0c6ed95 137 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
252b5132
RH		 138 {"common", s_common, 0},
139 {"empty", s_empty, 0},
140 {"global", s_globl, 0},
141 {"half", cons, 2},
cf9a1301 142 {"nword", s_ncons, 0},
252b5132
RH		 143 {"optim", s_ignore, 0},
144 {"proc", s_proc, 0},
145 {"reserve", s_reserve, 0},
146 {"seg", s_seg, 0},
147 {"skip", s_space, 0},
148 {"word", cons, 4},
149 {"xword", cons, 8},
150 {"uahalf", s_uacons, 2},
151 {"uaword", s_uacons, 4},
152 {"uaxword", s_uacons, 8},
153#ifdef OBJ_ELF
e0c6ed95 154 /* These are specific to sparc/svr4. */
252b5132
RH		 155 {"2byte", s_uacons, 2},
156 {"4byte", s_uacons, 4},
157 {"8byte", s_uacons, 8},
6d8809aa 158 {"register", s_register, 0},
252b5132
RH		 159#endif
160 {NULL, 0, 0},
161};
162
252b5132 163/* This array holds the chars that always start a comment. If the
e0c6ed95
AM		 164 pre-processor is disabled, these aren't very useful. */
165const char comment_chars[] = "!"; /* JF removed '|' from
166 comment_chars. */
252b5132
RH		 167
168/* This array holds the chars that only start a comment at the beginning of
169 a line. If the line seems to have the form '# 123 filename'
e0c6ed95 170 .line and .file directives will appear in the pre-processed output. */
252b5132
RH		 171/* Note that input_file.c hand checks for '#' at the beginning of the
172 first line of the input file. This is because the compiler outputs
e0c6ed95 173 #NO_APP at the beginning of its output. */
252b5132 174/* Also note that comments started like this one will always
e0c6ed95 175 work if '/' isn't otherwise defined. */
252b5132
RH		 176const char line_comment_chars[] = "#";
177
63a0b638 178const char line_separator_chars[] = ";";
252b5132 179
e0c6ed95
AM		 180/* Chars that can be used to separate mant from exp in floating point
181 nums. */
252b5132
RH		 182const char EXP_CHARS[] = "eE";
183
e0c6ed95
AM		 184/* Chars that mean this number is a floating point constant.
185 As in 0f12.456
186 or 0d1.2345e12 */
252b5132
RH		 187const char FLT_CHARS[] = "rRsSfFdDxXpP";
188
189/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
190 changed in read.c. Ideally it shouldn't have to know about it at all,
191 but nothing is ideal around here. */
192
74b56d1f 193#define isoctal(c) ((unsigned) ((c) - '0') < 8)
252b5132
RH		 194
195struct sparc_it
196 {
197 char *error;
198 unsigned long opcode;
199 struct nlist *nlistp;
200 expressionS exp;
cf9a1301 201 expressionS exp2;
252b5132
RH		 202 int pcrel;
203 bfd_reloc_code_real_type reloc;
204 };
205
206struct sparc_it the_insn, set_insn;
207
5a49b8ac 208static void output_insn (const struct sparc_opcode *, struct sparc_it *);
252b5132
RH		 209\f
210/* Table of arguments to -A.
211 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
212 for this use. That table is for opcodes only. This table is for opcodes
213 and file formats. */
214
215enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
19f7b010 216 v8plusa, v9, v9a, v9b, v9_64};
252b5132
RH		 217
218static struct sparc_arch {
219 char *name;
220 char *opcode_arch;
221 enum sparc_arch_types arch_type;
222 /* Default word size, as specified during configuration.
223 A value of zero means can't be used to specify default architecture. */
224 int default_arch_size;
225 /* Allowable arg to -A? */
226 int user_option_p;
227} sparc_arch_table[] = {
228 { "v6", "v6", v6, 0, 1 },
229 { "v7", "v7", v7, 0, 1 },
230 { "v8", "v8", v8, 32, 1 },
231 { "sparclet", "sparclet", sparclet, 32, 1 },
232 { "sparclite", "sparclite", sparclite, 32, 1 },
233 { "sparc86x", "sparclite", sparc86x, 32, 1 },
234 { "v8plus", "v9", v9, 0, 1 },
235 { "v8plusa", "v9a", v9, 0, 1 },
19f7b010 236 { "v8plusb", "v9b", v9, 0, 1 },
252b5132
RH		 237 { "v9", "v9", v9, 0, 1 },
238 { "v9a", "v9a", v9, 0, 1 },
19f7b010 239 { "v9b", "v9b", v9, 0, 1 },
252b5132
RH		 240 /* This exists to allow configure.in/Makefile.in to pass one
241 value to specify both the default machine and default word size. */
242 { "v9-64", "v9", v9, 64, 0 },
243 { NULL, NULL, v8, 0, 0 }
244};
245
246/* Variant of default_arch */
247static enum sparc_arch_types default_arch_type;
248
249static struct sparc_arch *
5a49b8ac 250lookup_arch (char *name)
252b5132
RH		 251{
252 struct sparc_arch *sa;
253
254 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
255 if (strcmp (sa->name, name) == 0)
256 break;
257 if (sa->name == NULL)
258 return NULL;
259 return sa;
260}
261
262/* Initialize the default opcode arch and word size from the default
263 architecture name. */
264
265static void
5a49b8ac 266init_default_arch (void)
252b5132
RH		 267{
268 struct sparc_arch *sa = lookup_arch (default_arch);
269
270 if (sa == NULL
271 || sa->default_arch_size == 0)
272 as_fatal (_("Invalid default architecture, broken assembler."));
273
274 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
275 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
276 as_fatal (_("Bad opcode table, broken assembler."));
277 default_arch_size = sparc_arch_size = sa->default_arch_size;
278 default_init_p = 1;
279 default_arch_type = sa->arch_type;
280}
281
282/* Called by TARGET_FORMAT. */
283
284const char *
5a49b8ac 285sparc_target_format (void)
252b5132
RH		 286{
287 /* We don't get a chance to initialize anything before we're called,
288 so handle that now. */
289 if (! default_init_p)
290 init_default_arch ();
291
292#ifdef OBJ_AOUT
293#ifdef TE_NetBSD
294 return "a.out-sparc-netbsd";
295#else
296#ifdef TE_SPARCAOUT
297 if (target_big_endian)
298 return "a.out-sunos-big";
299 else if (default_arch_type == sparc86x && target_little_endian_data)
300 return "a.out-sunos-big";
ab3e48dc
KH		 301 else
302 return "a.out-sparc-little";
252b5132
RH		 303#else
304 return "a.out-sunos-big";
305#endif
306#endif
307#endif
308
309#ifdef OBJ_BOUT
310 return "b.out.big";
311#endif
312
313#ifdef OBJ_COFF
314#ifdef TE_LYNX
315 return "coff-sparc-lynx";
316#else
317 return "coff-sparc";
318#endif
319#endif
320
910600e9
RS		 321#ifdef TE_VXWORKS
322 return "elf32-sparc-vxworks";
323#endif
324
252b5132 325#ifdef OBJ_ELF
71a75f6f 326 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
252b5132
RH		 327#endif
328
329 abort ();
330}
331\f
e0c6ed95 332/* md_parse_option
252b5132
RH		 333 * Invocation line includes a switch not recognized by the base assembler.
334 * See if it's a processor-specific option. These are:
335 *
336 * -bump
337 * Warn on architecture bumps. See also -A.
338 *
339 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
340 * Standard 32 bit architectures.
19f7b010 341 * -Av9, -Av9a, -Av9b
252b5132
RH		 342 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
343 * This used to only mean 64 bits, but properly specifying it
344 * complicated gcc's ASM_SPECs, so now opcode selection is
345 * specified orthogonally to word size (except when specifying
346 * the default, but that is an internal implementation detail).
19f7b010
JJ		 347 * -Av8plus, -Av8plusa, -Av8plusb
348 * Same as -Av9{,a,b}.
349 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
350 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
351 * assembler.
352 * -xarch=v9, -xarch=v9a, -xarch=v9b
353 * Same as -Av9{,a,b} -64, for compatibility with Sun's
c2158c24 354 * assembler.
252b5132
RH		 355 *
356 * Select the architecture and possibly the file format.
357 * Instructions or features not supported by the selected
358 * architecture cause fatal errors.
359 *
360 * The default is to start at v6, and bump the architecture up
361 * whenever an instruction is seen at a higher level. In 32 bit
362 * environments, v9 is not bumped up to, the user must pass
19f7b010 363 * -Av8plus{,a,b}.
252b5132
RH		 364 *
365 * If -bump is specified, a warning is printing when bumping to
366 * higher levels.
367 *
368 * If an architecture is specified, all instructions must match
369 * that architecture. Any higher level instructions are flagged
370 * as errors. Note that in the 32 bit environment specifying
371 * -Av8plus does not automatically create a v8plus object file, a
372 * v9 insn must be seen.
373 *
374 * If both an architecture and -bump are specified, the
375 * architecture starts at the specified level, but bumps are
376 * warnings. Note that we can't set `current_architecture' to
377 * the requested level in this case: in the 32 bit environment,
378 * we still must avoid creating v8plus object files unless v9
379 * insns are seen.
380 *
381 * Note:
382 * Bumping between incompatible architectures is always an
383 * error. For example, from sparclite to v9.
384 */
385
386#ifdef OBJ_ELF
5a38dc70 387const char *md_shortopts = "A:K:VQ:sq";
252b5132
RH		 388#else
389#ifdef OBJ_AOUT
5a38dc70 390const char *md_shortopts = "A:k";
252b5132 391#else
5a38dc70 392const char *md_shortopts = "A:";
252b5132
RH		 393#endif
394#endif
395struct option md_longopts[] = {
396#define OPTION_BUMP (OPTION_MD_BASE)
397 {"bump", no_argument, NULL, OPTION_BUMP},
398#define OPTION_SPARC (OPTION_MD_BASE + 1)
399 {"sparc", no_argument, NULL, OPTION_SPARC},
400#define OPTION_XARCH (OPTION_MD_BASE + 2)
401 {"xarch", required_argument, NULL, OPTION_XARCH},
402#ifdef OBJ_ELF
403#define OPTION_32 (OPTION_MD_BASE + 3)
404 {"32", no_argument, NULL, OPTION_32},
405#define OPTION_64 (OPTION_MD_BASE + 4)
406 {"64", no_argument, NULL, OPTION_64},
407#define OPTION_TSO (OPTION_MD_BASE + 5)
408 {"TSO", no_argument, NULL, OPTION_TSO},
409#define OPTION_PSO (OPTION_MD_BASE + 6)
410 {"PSO", no_argument, NULL, OPTION_PSO},
411#define OPTION_RMO (OPTION_MD_BASE + 7)
412 {"RMO", no_argument, NULL, OPTION_RMO},
413#endif
414#ifdef SPARC_BIENDIAN
415#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
416 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
417#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
418 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
419#endif
420#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
421 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
422#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
423 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
6d8809aa
RH		 424#ifdef OBJ_ELF
425#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
426 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
a25fe906
ILT		 427#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
428 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
6d8809aa 429#endif
6faf3d66
JJ		 430#define OPTION_RELAX (OPTION_MD_BASE + 14)
431 {"relax", no_argument, NULL, OPTION_RELAX},
432#define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
433 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
252b5132
RH		 434 {NULL, no_argument, NULL, 0}
435};
e0c6ed95
AM		 436
437size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 438
439int
5a49b8ac 440md_parse_option (int c, char *arg)
252b5132
RH		 441{
442 /* We don't get a chance to initialize anything before we're called,
443 so handle that now. */
444 if (! default_init_p)
445 init_default_arch ();
446
447 switch (c)
448 {
449 case OPTION_BUMP:
450 warn_on_bump = 1;
451 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
452 break;
453
454 case OPTION_XARCH:
c2158c24
JJ		 455#ifdef OBJ_ELF
456 if (strncmp (arg, "v9", 2) != 0)
457 md_parse_option (OPTION_32, NULL);
458 else
459 md_parse_option (OPTION_64, NULL);
460#endif
e0c6ed95 461 /* Fall through. */
252b5132
RH		 462
463 case 'A':
464 {
465 struct sparc_arch *sa;
466 enum sparc_opcode_arch_val opcode_arch;
467
468 sa = lookup_arch (arg);
469 if (sa == NULL
470 || ! sa->user_option_p)
471 {
c2158c24
JJ		 472 if (c == OPTION_XARCH)
473 as_bad (_("invalid architecture -xarch=%s"), arg);
474 else
475 as_bad (_("invalid architecture -A%s"), arg);
252b5132
RH		 476 return 0;
477 }
478
479 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
480 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
481 as_fatal (_("Bad opcode table, broken assembler."));
482
483 max_architecture = opcode_arch;
484 architecture_requested = 1;
485 }
486 break;
487
488 case OPTION_SPARC:
489 /* Ignore -sparc, used by SunOS make default .s.o rule. */
490 break;
491
492 case OPTION_ENFORCE_ALIGNED_DATA:
493 enforce_aligned_data = 1;
494 break;
495
496#ifdef SPARC_BIENDIAN
497 case OPTION_LITTLE_ENDIAN:
498 target_big_endian = 0;
499 if (default_arch_type != sparclet)
500 as_fatal ("This target does not support -EL");
501 break;
502 case OPTION_LITTLE_ENDIAN_DATA:
503 target_little_endian_data = 1;
504 target_big_endian = 0;
505 if (default_arch_type != sparc86x
506 && default_arch_type != v9)
507 as_fatal ("This target does not support --little-endian-data");
508 break;
509 case OPTION_BIG_ENDIAN:
510 target_big_endian = 1;
511 break;
512#endif
513
514#ifdef OBJ_AOUT
515 case 'k':
516 sparc_pic_code = 1;
517 break;
518#endif
519
520#ifdef OBJ_ELF
521 case OPTION_32:
522 case OPTION_64:
523 {
524 const char **list, **l;
525
526 sparc_arch_size = c == OPTION_32 ? 32 : 64;
527 list = bfd_target_list ();
528 for (l = list; *l != NULL; l++)
529 {
530 if (sparc_arch_size == 32)
531 {
71a75f6f 532 if (CONST_STRNEQ (*l, "elf32-sparc"))
252b5132
RH		 533 break;
534 }
535 else
536 {
71a75f6f 537 if (CONST_STRNEQ (*l, "elf64-sparc"))
252b5132
RH		 538 break;
539 }
540 }
541 if (*l == NULL)
542 as_fatal (_("No compiled in support for %d bit object file format"),
543 sparc_arch_size);
544 free (list);
b7cac25f
DM		 545
546 if (sparc_arch_size == 64
547 && max_architecture < SPARC_OPCODE_ARCH_V9)
548 max_architecture = SPARC_OPCODE_ARCH_V9;
252b5132
RH		 549 }
550 break;
551
552 case OPTION_TSO:
553 sparc_memory_model = MM_TSO;
554 break;
555
556 case OPTION_PSO:
557 sparc_memory_model = MM_PSO;
558 break;
559
560 case OPTION_RMO:
561 sparc_memory_model = MM_RMO;
562 break;
563
564 case 'V':
565 print_version_id ();
566 break;
567
568 case 'Q':
569 /* Qy - do emit .comment
e0c6ed95 570 Qn - do not emit .comment. */
252b5132
RH		 571 break;
572
573 case 's':
e0c6ed95 574 /* Use .stab instead of .stab.excl. */
252b5132
RH		 575 break;
576
577 case 'q':
e0c6ed95 578 /* quick -- Native assembler does fewer checks. */
252b5132
RH		 579 break;
580
581 case 'K':
582 if (strcmp (arg, "PIC") != 0)
583 as_warn (_("Unrecognized option following -K"));
584 else
585 sparc_pic_code = 1;
586 break;
6d8809aa
RH		 587
588 case OPTION_NO_UNDECLARED_REGS:
589 no_undeclared_regs = 1;
590 break;
a25fe906
ILT		 591
592 case OPTION_UNDECLARED_REGS:
593 no_undeclared_regs = 0;
594 break;
252b5132
RH		 595#endif
596
6faf3d66
JJ		 597 case OPTION_RELAX:
598 sparc_relax = 1;
599 break;
600
601 case OPTION_NO_RELAX:
602 sparc_relax = 0;
603 break;
604
252b5132
RH		 605 default:
606 return 0;
607 }
608
609 return 1;
610}
611
612void
5a49b8ac 613md_show_usage (FILE *stream)
252b5132
RH		 614{
615 const struct sparc_arch *arch;
c2158c24 616 int column;
252b5132
RH		 617
618 /* We don't get a chance to initialize anything before we're called,
619 so handle that now. */
620 if (! default_init_p)
621 init_default_arch ();
622
e0c6ed95 623 fprintf (stream, _("SPARC options:\n"));
c2158c24 624 column = 0;
252b5132
RH		 625 for (arch = &sparc_arch_table[0]; arch->name; arch++)
626 {
c2158c24
JJ		 627 if (!arch->user_option_p)
628 continue;
252b5132
RH		 629 if (arch != &sparc_arch_table[0])
630 fprintf (stream, " | ");
07726851 631 if (column + strlen (arch->name) > 70)
c2158c24
JJ		 632 {
633 column = 0;
634 fputc ('\n', stream);
635 }
07726851 636 column += 5 + 2 + strlen (arch->name);
c2158c24 637 fprintf (stream, "-A%s", arch->name);
252b5132 638 }
c2158c24
JJ		 639 for (arch = &sparc_arch_table[0]; arch->name; arch++)
640 {
641 if (!arch->user_option_p)
642 continue;
643 fprintf (stream, " | ");
07726851 644 if (column + strlen (arch->name) > 65)
c2158c24
JJ		 645 {
646 column = 0;
647 fputc ('\n', stream);
648 }
07726851 649 column += 5 + 7 + strlen (arch->name);
c2158c24
JJ		 650 fprintf (stream, "-xarch=%s", arch->name);
651 }
652 fprintf (stream, _("\n\
252b5132
RH		 653 specify variant of SPARC architecture\n\
654-bump warn when assembler switches architectures\n\
655-sparc ignored\n\
6faf3d66
JJ		 656--enforce-aligned-data force .long, etc., to be aligned correctly\n\
657-relax relax jumps and branches (default)\n\
658-no-relax avoid changing any jumps and branches\n"));
252b5132
RH		 659#ifdef OBJ_AOUT
660 fprintf (stream, _("\
661-k generate PIC\n"));
662#endif
663#ifdef OBJ_ELF
664 fprintf (stream, _("\
665-32 create 32 bit object file\n\
666-64 create 64 bit object file\n"));
667 fprintf (stream, _("\
668 [default is %d]\n"), default_arch_size);
669 fprintf (stream, _("\
670-TSO use Total Store Ordering\n\
671-PSO use Partial Store Ordering\n\
672-RMO use Relaxed Memory Ordering\n"));
673 fprintf (stream, _("\
674 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
675 fprintf (stream, _("\
676-KPIC generate PIC\n\
677-V print assembler version number\n\
a25fe906
ILT		 678-undeclared-regs ignore application global register usage without\n\
679 appropriate .register directive (default)\n\
680-no-undeclared-regs force error on application global register usage\n\
681 without appropriate .register directive\n\
252b5132
RH		 682-q ignored\n\
683-Qy, -Qn ignored\n\
684-s ignored\n"));
685#endif
686#ifdef SPARC_BIENDIAN
687 fprintf (stream, _("\
688-EL generate code for a little endian machine\n\
689-EB generate code for a big endian machine\n\
690--little-endian-data generate code for a machine having big endian\n\
c20f4f8c 691 instructions and little endian data.\n"));
252b5132
RH		 692#endif
693}
694\f
e0c6ed95 695/* Native operand size opcode translation. */
cf9a1301
RH		 696struct
697 {
698 char *name;
699 char *name32;
700 char *name64;
701 } native_op_table[] =
702{
703 {"ldn", "ld", "ldx"},
704 {"ldna", "lda", "ldxa"},
705 {"stn", "st", "stx"},
706 {"stna", "sta", "stxa"},
707 {"slln", "sll", "sllx"},
708 {"srln", "srl", "srlx"},
709 {"sran", "sra", "srax"},
710 {"casn", "cas", "casx"},
711 {"casna", "casa", "casxa"},
712 {"clrn", "clr", "clrx"},
713 {NULL, NULL, NULL},
714};
715\f
10156f83 716/* sparc64 privileged and hyperprivileged registers. */
252b5132
RH		 717
718struct priv_reg_entry
ab3e48dc
KH		 719{
720 char *name;
721 int regnum;
722};
252b5132
RH		 723
724struct priv_reg_entry priv_reg_table[] =
725{
726 {"tpc", 0},
727 {"tnpc", 1},
728 {"tstate", 2},
729 {"tt", 3},
730 {"tick", 4},
731 {"tba", 5},
732 {"pstate", 6},
733 {"tl", 7},
734 {"pil", 8},
735 {"cwp", 9},
736 {"cansave", 10},
737 {"canrestore", 11},
738 {"cleanwin", 12},
739 {"otherwin", 13},
740 {"wstate", 14},
741 {"fq", 15},
10156f83 742 {"gl", 16},
252b5132 743 {"ver", 31},
e0c6ed95 744 {"", -1}, /* End marker. */
252b5132
RH		 745};
746
10156f83
DM		 747struct priv_reg_entry hpriv_reg_table[] =
748{
749 {"hpstate", 0},
750 {"htstate", 1},
751 {"hintp", 3},
752 {"htba", 5},
753 {"hver", 6},
754 {"hstick_cmpr", 31},
755 {"", -1}, /* End marker. */
756};
757
1a6b486f
DM		 758/* v9a specific asrs. This table is ordered by initial
759 letter, in reverse. */
252b5132
RH		 760
761struct priv_reg_entry v9a_asr_table[] =
762{
763 {"tick_cmpr", 23},
19f7b010
JJ		 764 {"sys_tick_cmpr", 25},
765 {"sys_tick", 24},
1a6b486f
DM		 766 {"stick_cmpr", 25},
767 {"stick", 24},
f04d18b7
DM		 768 {"softint_clear", 21},
769 {"softint_set", 20},
2b661f3d 770 {"softint", 22},
252b5132
RH		 771 {"set_softint", 20},
772 {"pic", 17},
773 {"pcr", 16},
774 {"gsr", 19},
775 {"dcr", 18},
ea783ef3 776 {"cps", 28},
252b5132 777 {"clear_softint", 21},
e0c6ed95 778 {"", -1}, /* End marker. */
252b5132
RH		 779};
780
781static int
5a49b8ac 782cmp_reg_entry (const void *parg, const void *qarg)
252b5132
RH		 783{
784 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
785 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
786
787 return strcmp (q->name, p->name);
788}
789\f
790/* This function is called once, at assembler startup time. It should
e0c6ed95
AM		 791 set up all the tables, etc. that the MD part of the assembler will
792 need. */
252b5132
RH		 793
794void
5a49b8ac 795md_begin (void)
252b5132
RH		 796{
797 register const char *retval = NULL;
798 int lose = 0;
799 register unsigned int i = 0;
800
801 /* We don't get a chance to initialize anything before md_parse_option
802 is called, and it may not be called, so handle default initialization
803 now if not already done. */
804 if (! default_init_p)
805 init_default_arch ();
806
364b6d8b 807 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
252b5132
RH		 808 op_hash = hash_new ();
809
810 while (i < (unsigned int) sparc_num_opcodes)
811 {
812 const char *name = sparc_opcodes[i].name;
5a49b8ac 813 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]);
252b5132
RH		 814 if (retval != NULL)
815 {
cf9a1301
RH		 816 as_bad (_("Internal error: can't hash `%s': %s\n"),
817 sparc_opcodes[i].name, retval);
252b5132
RH		 818 lose = 1;
819 }
820 do
821 {
822 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
823 {
cf9a1301
RH		 824 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
825 sparc_opcodes[i].name, sparc_opcodes[i].args);
252b5132
RH		 826 lose = 1;
827 }
828 ++i;
829 }
830 while (i < (unsigned int) sparc_num_opcodes
831 && !strcmp (sparc_opcodes[i].name, name));
832 }
833
cf9a1301
RH		 834 for (i = 0; native_op_table[i].name; i++)
835 {
836 const struct sparc_opcode *insn;
3d4ae3c0
NC		 837 char *name = ((sparc_arch_size == 32)
838 ? native_op_table[i].name32
839 : native_op_table[i].name64);
e0c6ed95 840 insn = (struct sparc_opcode *) hash_find (op_hash, name);
cf9a1301 841 if (insn == NULL)
e0c6ed95
AM		 842 {
843 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
844 name, native_op_table[i].name);
845 lose = 1;
846 }
cf9a1301
RH		 847 else
848 {
5a49b8ac
AM		 849 retval = hash_insert (op_hash, native_op_table[i].name,
850 (void *) insn);
cf9a1301
RH		 851 if (retval != NULL)
852 {
853 as_bad (_("Internal error: can't hash `%s': %s\n"),
854 sparc_opcodes[i].name, retval);
855 lose = 1;
856 }
857 }
858 }
859
252b5132
RH		 860 if (lose)
861 as_fatal (_("Broken assembler. No assembly attempted."));
862
252b5132
RH		 863 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
864 sizeof (priv_reg_table[0]), cmp_reg_entry);
865
866 /* If -bump, record the architecture level at which we start issuing
867 warnings. The behaviour is different depending upon whether an
868 architecture was explicitly specified. If it wasn't, we issue warnings
869 for all upwards bumps. If it was, we don't start issuing warnings until
870 we need to bump beyond the requested architecture or when we bump between
871 conflicting architectures. */
872
873 if (warn_on_bump
874 && architecture_requested)
875 {
876 /* `max_architecture' records the requested architecture.
877 Issue warnings if we go above it. */
878 warn_after_architecture = max_architecture;
879
880 /* Find the highest architecture level that doesn't conflict with
881 the requested one. */
882 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
883 max_architecture > warn_after_architecture;
884 --max_architecture)
885 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
886 warn_after_architecture))
887 break;
888 }
889}
890
891/* Called after all assembly has been done. */
892
893void
5a49b8ac 894sparc_md_end (void)
252b5132 895{
19f7b010
JJ		 896 unsigned long mach = bfd_mach_sparc;
897
252b5132 898 if (sparc_arch_size == 64)
19f7b010
JJ		 899 switch (current_architecture)
900 {
901 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
902 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
903 default: mach = bfd_mach_sparc_v9; break;
904 }
252b5132 905 else
19f7b010
JJ		 906 switch (current_architecture)
907 {
908 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
909 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
910 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
911 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
912 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
913 be but for now it is (since that's the way it's always been
914 treated). */
915 default: break;
916 }
917 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
252b5132
RH		 918}
919\f
920/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
921
5a49b8ac
AM		 922static inline int
923in_signed_range (bfd_signed_vma val, bfd_signed_vma max)
252b5132
RH		 924{
925 if (max <= 0)
926 abort ();
927 /* Sign-extend the value from the architecture word size, so that
928 0xffffffff is always considered -1 on sparc32. */
929 if (sparc_arch_size == 32)
930 {
e0c6ed95 931 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
6c1b24e4 932 val = ((val & U0xffffffff) ^ sign) - sign;
252b5132
RH		 933 }
934 if (val > max)
935 return 0;
936 if (val < ~max)
937 return 0;
938 return 1;
939}
940
941/* Return non-zero if VAL is in the range 0 to MAX. */
942
5a49b8ac
AM		 943static inline int
944in_unsigned_range (bfd_vma val, bfd_vma max)
252b5132
RH		 945{
946 if (val > max)
947 return 0;
948 return 1;
949}
950
951/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
952 (e.g. -15 to +31). */
953
5a49b8ac
AM		 954static inline int
955in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max)
252b5132
RH		 956{
957 if (max <= 0)
958 abort ();
959 if (val > max)
960 return 0;
961 if (val < ~(max >> 1))
962 return 0;
963 return 1;
964}
965
966static int
5a49b8ac 967sparc_ffs (unsigned int mask)
252b5132
RH		 968{
969 int i;
970
971 if (mask == 0)
972 return -1;
973
974 for (i = 0; (mask & 1) == 0; ++i)
975 mask >>= 1;
976 return i;
977}
978
979/* Implement big shift right. */
980static bfd_vma
5a49b8ac 981BSR (bfd_vma val, int amount)
252b5132
RH		 982{
983 if (sizeof (bfd_vma) <= 4 && amount >= 32)
984 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
985 return val >> amount;
986}
987\f
988/* For communication between sparc_ip and get_expression. */
989static char *expr_end;
990
252b5132
RH		 991/* Values for `special_case'.
992 Instructions that require wierd handling because they're longer than
993 4 bytes. */
994#define SPECIAL_CASE_NONE 0
995#define SPECIAL_CASE_SET 1
996#define SPECIAL_CASE_SETSW 2
997#define SPECIAL_CASE_SETX 3
998/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
999#define SPECIAL_CASE_FDIV 4
1000
1001/* Bit masks of various insns. */
1002#define NOP_INSN 0x01000000
1003#define OR_INSN 0x80100000
63fab58c 1004#define XOR_INSN 0x80180000
252b5132
RH		 1005#define FMOVS_INSN 0x81A00020
1006#define SETHI_INSN 0x01000000
1007#define SLLX_INSN 0x81281000
1008#define SRA_INSN 0x81380000
1009
1010/* The last instruction to be assembled. */
1011static const struct sparc_opcode *last_insn;
1012/* The assembled opcode of `last_insn'. */
1013static unsigned long last_opcode;
1014\f
a22b281c 1015/* Handle the set and setuw synthetic instructions. */
e0c6ed95 1016
a22b281c 1017static void
5a49b8ac 1018synthetize_setuw (const struct sparc_opcode *insn)
a22b281c
RH		 1019{
1020 int need_hi22_p = 0;
1021 int rd = (the_insn.opcode & RD (~0)) >> 25;
1022
1023 if (the_insn.exp.X_op == O_constant)
1024 {
1025 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1026 {
e0c6ed95 1027 if (sizeof (offsetT) > 4
a22b281c 1028 && (the_insn.exp.X_add_number < 0
6c1b24e4 1029 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
a22b281c
RH		 1030 as_warn (_("set: number not in 0..4294967295 range"));
1031 }
1032 else
1033 {
e0c6ed95 1034 if (sizeof (offsetT) > 4
6c1b24e4
AO		 1035 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1036 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
a22b281c 1037 as_warn (_("set: number not in -2147483648..4294967295 range"));
e0c6ed95 1038 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
a22b281c
RH		 1039 }
1040 }
1041
1042 /* See if operand is absolute and small; skip sethi if so. */
1043 if (the_insn.exp.X_op != O_constant
1044 || the_insn.exp.X_add_number >= (1 << 12)
1045 || the_insn.exp.X_add_number < -(1 << 12))
1046 {
1047 the_insn.opcode = (SETHI_INSN | RD (rd)
1048 | ((the_insn.exp.X_add_number >> 10)
ab3e48dc
KH		 1049 & (the_insn.exp.X_op == O_constant
1050 ? 0x3fffff : 0)));
a22b281c 1051 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1052 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
a22b281c
RH		 1053 output_insn (insn, &the_insn);
1054 need_hi22_p = 1;
1055 }
1056
1057 /* See if operand has no low-order bits; skip OR if so. */
1058 if (the_insn.exp.X_op != O_constant
1059 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1060 || ! need_hi22_p)
1061 {
1062 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1063 | RD (rd) | IMMED
1064 | (the_insn.exp.X_add_number
ab3e48dc
KH		 1065 & (the_insn.exp.X_op != O_constant
1066 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
a22b281c 1067 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1068 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
a22b281c
RH		 1069 output_insn (insn, &the_insn);
1070 }
1071}
e0c6ed95 1072
a22b281c 1073/* Handle the setsw synthetic instruction. */
e0c6ed95 1074
a22b281c 1075static void
5a49b8ac 1076synthetize_setsw (const struct sparc_opcode *insn)
a22b281c
RH		 1077{
1078 int low32, rd, opc;
1079
1080 rd = (the_insn.opcode & RD (~0)) >> 25;
1081
1082 if (the_insn.exp.X_op != O_constant)
1083 {
1084 synthetize_setuw (insn);
1085
1086 /* Need to sign extend it. */
1087 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1088 the_insn.reloc = BFD_RELOC_NONE;
1089 output_insn (insn, &the_insn);
1090 return;
1091 }
1092
e0c6ed95 1093 if (sizeof (offsetT) > 4
6c1b24e4
AO		 1094 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1095 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
a22b281c
RH		 1096 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1097
e0c6ed95
AM		 1098 low32 = the_insn.exp.X_add_number;
1099
a22b281c
RH		 1100 if (low32 >= 0)
1101 {
1102 synthetize_setuw (insn);
1103 return;
1104 }
1105
1106 opc = OR_INSN;
e0c6ed95 1107
a22b281c
RH		 1108 the_insn.reloc = BFD_RELOC_NONE;
1109 /* See if operand is absolute and small; skip sethi if so. */
1110 if (low32 < -(1 << 12))
1111 {
1112 the_insn.opcode = (SETHI_INSN | RD (rd)
1113 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1114 output_insn (insn, &the_insn);
1115 low32 = 0x1c00 | (low32 & 0x3ff);
1116 opc = RS1 (rd) | XOR_INSN;
1117 }
1118
1119 the_insn.opcode = (opc | RD (rd) | IMMED
1120 | (low32 & 0x1fff));
1121 output_insn (insn, &the_insn);
1122}
1123
1124/* Handle the setsw synthetic instruction. */
e0c6ed95 1125
a22b281c 1126static void
5a49b8ac 1127synthetize_setx (const struct sparc_opcode *insn)
a22b281c
RH		 1128{
1129 int upper32, lower32;
1130 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1131 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1132 int upper_dstreg;
1133 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1134 int need_xor10_p = 0;
e0c6ed95 1135
6c1b24e4 1136#define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
a22b281c
RH		 1137 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1138 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1139#undef SIGNEXT32
1140
1141 upper_dstreg = tmpreg;
1142 /* The tmp reg should not be the dst reg. */
1143 if (tmpreg == dstreg)
1144 as_warn (_("setx: temporary register same as destination register"));
1145
1146 /* ??? Obviously there are other optimizations we can do
1147 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1148 doing some of these. Later. If you do change things, try to
1149 change all of this to be table driven as well. */
1150 /* What to output depends on the number if it's constant.
1151 Compute that first, then output what we've decided upon. */
1152 if (the_insn.exp.X_op != O_constant)
1153 {
1154 if (sparc_arch_size == 32)
1155 {
1156 /* When arch size is 32, we want setx to be equivalent
1157 to setuw for anything but constants. */
1158 the_insn.exp.X_add_number &= 0xffffffff;
1159 synthetize_setuw (insn);
1160 return;
1161 }
1162 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
ab3e48dc
KH		 1163 lower32 = 0;
1164 upper32 = 0;
a22b281c
RH		 1165 }
1166 else
1167 {
1168 /* Reset X_add_number, we've extracted it as upper32/lower32.
1169 Otherwise fixup_segment will complain about not being able to
1170 write an 8 byte number in a 4 byte field. */
1171 the_insn.exp.X_add_number = 0;
e0c6ed95 1172
a22b281c
RH		 1173 /* Only need hh22 if `or' insn can't handle constant. */
1174 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1175 need_hh22_p = 1;
e0c6ed95 1176
a22b281c
RH		 1177 /* Does bottom part (after sethi) have bits? */
1178 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1179 /* No hh22, but does upper32 still have bits we can't set
1180 from lower32? */
1181 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1182 need_hm10_p = 1;
e0c6ed95 1183
a22b281c
RH		 1184 /* If the lower half is all zero, we build the upper half directly
1185 into the dst reg. */
1186 if (lower32 != 0
1187 /* Need lower half if number is zero or 0xffffffff00000000. */
1188 || (! need_hh22_p && ! need_hm10_p))
1189 {
1190 /* No need for sethi if `or' insn can handle constant. */
1191 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1192 /* Note that we can't use a negative constant in the `or'
1193 insn unless the upper 32 bits are all ones. */
1194 || (lower32 < 0 && upper32 != -1)
1195 || (lower32 >= 0 && upper32 == -1))
1196 need_hi22_p = 1;
e0c6ed95 1197
a22b281c
RH		 1198 if (need_hi22_p && upper32 == -1)
1199 need_xor10_p = 1;
1200
1201 /* Does bottom part (after sethi) have bits? */
1202 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1203 /* No sethi. */
1204 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1205 /* Need `or' if we didn't set anything else. */
1206 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1207 need_lo10_p = 1;
1208 }
1209 else
1210 /* Output directly to dst reg if lower 32 bits are all zero. */
1211 upper_dstreg = dstreg;
1212 }
e0c6ed95 1213
a22b281c
RH		 1214 if (!upper_dstreg && dstreg)
1215 as_warn (_("setx: illegal temporary register g0"));
1216
1217 if (need_hh22_p)
1218 {
1219 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1220 | ((upper32 >> 10) & 0x3fffff));
1221 the_insn.reloc = (the_insn.exp.X_op != O_constant
1222 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1223 output_insn (insn, &the_insn);
1224 }
e0c6ed95 1225
a22b281c
RH		 1226 if (need_hi22_p)
1227 {
1228 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1229 | (((need_xor10_p ? ~lower32 : lower32)
ab3e48dc 1230 >> 10) & 0x3fffff));
a22b281c
RH		 1231 the_insn.reloc = (the_insn.exp.X_op != O_constant
1232 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1233 output_insn (insn, &the_insn);
1234 }
1235
1236 if (need_hm10_p)
1237 {
1238 the_insn.opcode = (OR_INSN
1239 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1240 | RD (upper_dstreg)
1241 | IMMED
1242 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1243 the_insn.reloc = (the_insn.exp.X_op != O_constant
1244 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1245 output_insn (insn, &the_insn);
1246 }
e0c6ed95 1247
a22b281c
RH		 1248 if (need_lo10_p)
1249 {
1250 /* FIXME: One nice optimization to do here is to OR the low part
1251 with the highpart if hi22 isn't needed and the low part is
1252 positive. */
1253 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1254 | RD (dstreg)
1255 | IMMED
1256 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1257 the_insn.reloc = (the_insn.exp.X_op != O_constant
1258 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1259 output_insn (insn, &the_insn);
1260 }
e0c6ed95 1261
a22b281c
RH		 1262 /* If we needed to build the upper part, shift it into place. */
1263 if (need_hh22_p || need_hm10_p)
1264 {
1265 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1266 | IMMED | 32);
1267 the_insn.reloc = BFD_RELOC_NONE;
1268 output_insn (insn, &the_insn);
1269 }
e0c6ed95 1270
a22b281c
RH		 1271 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1272 if (need_xor10_p)
1273 {
1274 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1275 | 0x1c00 | (lower32 & 0x3ff));
1276 the_insn.reloc = BFD_RELOC_NONE;
1277 output_insn (insn, &the_insn);
1278 }
1279
1280 /* If we needed to build both upper and lower parts, OR them together. */
1281 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1282 {
1283 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1284 | RD (dstreg));
1285 the_insn.reloc = BFD_RELOC_NONE;
1286 output_insn (insn, &the_insn);
1287 }
1288}
1289\f
252b5132
RH		 1290/* Main entry point to assemble one instruction. */
1291
1292void
5a49b8ac 1293md_assemble (char *str)
252b5132
RH		 1294{
1295 const struct sparc_opcode *insn;
a22b281c 1296 int special_case;
252b5132
RH		 1297
1298 know (str);
a22b281c 1299 special_case = sparc_ip (str, &insn);
b0825cc2
DM		 1300 if (insn == NULL)
1301 return;
252b5132
RH		 1302
1303 /* We warn about attempts to put a floating point branch in a delay slot,
1304 unless the delay slot has been annulled. */
b0825cc2 1305 if (last_insn != NULL
252b5132
RH		 1306 && (insn->flags & F_FBR) != 0
1307 && (last_insn->flags & F_DELAYED) != 0
1308 /* ??? This test isn't completely accurate. We assume anything with
1309 F_{UNBR,CONDBR,FBR} set is annullable. */
1310 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1311 || (last_opcode & ANNUL) == 0))
1312 as_warn (_("FP branch in delay slot"));
1313
1314 /* SPARC before v9 requires a nop instruction between a floating
1315 point instruction and a floating point branch. We insert one
1316 automatically, with a warning. */
1317 if (max_architecture < SPARC_OPCODE_ARCH_V9
252b5132
RH		 1318 && last_insn != NULL
1319 && (insn->flags & F_FBR) != 0
1320 && (last_insn->flags & F_FLOAT) != 0)
1321 {
1322 struct sparc_it nop_insn;
1323
1324 nop_insn.opcode = NOP_INSN;
1325 nop_insn.reloc = BFD_RELOC_NONE;
1326 output_insn (insn, &nop_insn);
1327 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1328 }
1329
a22b281c
RH		 1330 switch (special_case)
1331 {
1332 case SPECIAL_CASE_NONE:
e0c6ed95 1333 /* Normal insn. */
a22b281c
RH		 1334 output_insn (insn, &the_insn);
1335 break;
252b5132 1336
a22b281c
RH		 1337 case SPECIAL_CASE_SETSW:
1338 synthetize_setsw (insn);
1339 break;
e0c6ed95 1340
a22b281c
RH		 1341 case SPECIAL_CASE_SET:
1342 synthetize_setuw (insn);
1343 break;
252b5132 1344
a22b281c
RH		 1345 case SPECIAL_CASE_SETX:
1346 synthetize_setx (insn);
1347 break;
e0c6ed95 1348
a22b281c
RH		 1349 case SPECIAL_CASE_FDIV:
1350 {
1351 int rd = (the_insn.opcode >> 25) & 0x1f;
e0c6ed95 1352
a22b281c 1353 output_insn (insn, &the_insn);
e0c6ed95 1354
a22b281c
RH		 1355 /* According to information leaked from Sun, the "fdiv" instructions
1356 on early SPARC machines would produce incorrect results sometimes.
1357 The workaround is to add an fmovs of the destination register to
1358 itself just after the instruction. This was true on machines
e0c6ed95 1359 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
9c2799c2 1360 gas_assert (the_insn.reloc == BFD_RELOC_NONE);
a22b281c
RH		 1361 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1362 output_insn (insn, &the_insn);
1363 return;
1364 }
e0c6ed95 1365
a22b281c
RH		 1366 default:
1367 as_fatal (_("failed special case insn sanity check"));
252b5132
RH		 1368 }
1369}
1370
1371/* Subroutine of md_assemble to do the actual parsing. */
1372
a22b281c 1373static int
5a49b8ac 1374sparc_ip (char *str, const struct sparc_opcode **pinsn)
252b5132
RH		 1375{
1376 char *error_message = "";
1377 char *s;
1378 const char *args;
1379 char c;
1380 const struct sparc_opcode *insn;
1381 char *argsStart;
1382 unsigned long opcode;
1383 unsigned int mask = 0;
1384 int match = 0;
1385 int comma = 0;
1386 int v9_arg_p;
a22b281c 1387 int special_case = SPECIAL_CASE_NONE;
252b5132
RH		 1388
1389 s = str;
3882b010 1390 if (ISLOWER (*s))
252b5132
RH		 1391 {
1392 do
1393 ++s;
3882b010 1394 while (ISLOWER (*s) || ISDIGIT (*s));
252b5132
RH		 1395 }
1396
1397 switch (*s)
1398 {
1399 case '\0':
1400 break;
1401
1402 case ',':
1403 comma = 1;
e0c6ed95 1404 /* Fall through. */
252b5132
RH		 1405
1406 case ' ':
1407 *s++ = '\0';
1408 break;
1409
1410 default:
b0825cc2
DM		 1411 as_bad (_("Unknown opcode: `%s'"), str);
1412 *pinsn = NULL;
1413 return special_case;
252b5132
RH		 1414 }
1415 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1416 *pinsn = insn;
1417 if (insn == NULL)
1418 {
1419 as_bad (_("Unknown opcode: `%s'"), str);
a22b281c 1420 return special_case;
252b5132
RH		 1421 }
1422 if (comma)
1423 {
1424 *--s = ',';
1425 }
1426
1427 argsStart = s;
1428 for (;;)
1429 {
1430 opcode = insn->match;
1431 memset (&the_insn, '\0', sizeof (the_insn));
1432 the_insn.reloc = BFD_RELOC_NONE;
1433 v9_arg_p = 0;
1434
e0c6ed95
AM		 1435 /* Build the opcode, checking as we go to make sure that the
1436 operands match. */
252b5132
RH		 1437 for (args = insn->args;; ++args)
1438 {
1439 switch (*args)
1440 {
1441 case 'K':
1442 {
1443 int kmask = 0;
1444
1445 /* Parse a series of masks. */
1446 if (*s == '#')
1447 {
1448 while (*s == '#')
1449 {
91d6fa6a 1450 int jmask;
252b5132
RH		 1451
1452 if (! parse_keyword_arg (sparc_encode_membar, &s,
91d6fa6a 1453 &jmask))
252b5132
RH		 1454 {
1455 error_message = _(": invalid membar mask name");
1456 goto error;
1457 }
91d6fa6a 1458 kmask |= jmask;
47926f60
KH		 1459 while (*s == ' ')
1460 ++s;
252b5132
RH		 1461 if (*s == '|' || *s == '+')
1462 ++s;
47926f60
KH		 1463 while (*s == ' ')
1464 ++s;
252b5132
RH		 1465 }
1466 }
1467 else
1468 {
1469 if (! parse_const_expr_arg (&s, &kmask))
1470 {
1471 error_message = _(": invalid membar mask expression");
1472 goto error;
1473 }
1474 if (kmask < 0 || kmask > 127)
1475 {
1476 error_message = _(": invalid membar mask number");
1477 goto error;
1478 }
1479 }
1480
1481 opcode |= MEMBAR (kmask);
1482 continue;
1483 }
1484
19f7b010
JJ		 1485 case '3':
1486 {
1487 int smask = 0;
1488
1489 if (! parse_const_expr_arg (&s, &smask))
1490 {
1491 error_message = _(": invalid siam mode expression");
1492 goto error;
1493 }
1494 if (smask < 0 || smask > 7)
1495 {
1496 error_message = _(": invalid siam mode number");
1497 goto error;
1498 }
1499 opcode |= smask;
1500 continue;
1501 }
1502
252b5132
RH		 1503 case '*':
1504 {
1505 int fcn = 0;
1506
1507 /* Parse a prefetch function. */
1508 if (*s == '#')
1509 {
1510 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1511 {
1512 error_message = _(": invalid prefetch function name");
1513 goto error;
1514 }
1515 }
1516 else
1517 {
1518 if (! parse_const_expr_arg (&s, &fcn))
1519 {
1520 error_message = _(": invalid prefetch function expression");
1521 goto error;
1522 }
1523 if (fcn < 0 || fcn > 31)
1524 {
1525 error_message = _(": invalid prefetch function number");
1526 goto error;
1527 }
1528 }
1529 opcode |= RD (fcn);
1530 continue;
1531 }
1532
1533 case '!':
1534 case '?':
1535 /* Parse a sparc64 privileged register. */
1536 if (*s == '%')
1537 {
1538 struct priv_reg_entry *p = priv_reg_table;
e0c6ed95 1539 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1540
1541 s += 1;
1542 while (p->name[0] > s[0])
1543 p++;
1544 while (p->name[0] == s[0])
1545 {
1546 len = strlen (p->name);
1547 if (strncmp (p->name, s, len) == 0)
1548 break;
1549 p++;
1550 }
1551 if (p->name[0] != s[0])
1552 {
1553 error_message = _(": unrecognizable privileged register");
1554 goto error;
1555 }
1556 if (*args == '?')
1557 opcode |= (p->regnum << 14);
1558 else
1559 opcode |= (p->regnum << 25);
1560 s += len;
1561 continue;
1562 }
1563 else
1564 {
1565 error_message = _(": unrecognizable privileged register");
1566 goto error;
1567 }
1568
10156f83
DM		 1569 case '$':
1570 case '%':
1571 /* Parse a sparc64 hyperprivileged register. */
1572 if (*s == '%')
1573 {
1574 struct priv_reg_entry *p = hpriv_reg_table;
1575 unsigned int len = 9999999; /* Init to make gcc happy. */
1576
1577 s += 1;
1578 while (p->name[0] > s[0])
1579 p++;
1580 while (p->name[0] == s[0])
1581 {
1582 len = strlen (p->name);
1583 if (strncmp (p->name, s, len) == 0)
1584 break;
1585 p++;
1586 }
1587 if (p->name[0] != s[0])
1588 {
1589 error_message = _(": unrecognizable hyperprivileged register");
1590 goto error;
1591 }
1592 if (*args == '$')
1593 opcode |= (p->regnum << 14);
1594 else
1595 opcode |= (p->regnum << 25);
1596 s += len;
1597 continue;
1598 }
1599 else
1600 {
1601 error_message = _(": unrecognizable hyperprivileged register");
1602 goto error;
1603 }
1604
252b5132
RH		 1605 case '_':
1606 case '/':
19f7b010 1607 /* Parse a v9a/v9b ancillary state register. */
252b5132
RH		 1608 if (*s == '%')
1609 {
1610 struct priv_reg_entry *p = v9a_asr_table;
e0c6ed95 1611 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1612
1613 s += 1;
1614 while (p->name[0] > s[0])
1615 p++;
1616 while (p->name[0] == s[0])
1617 {
1618 len = strlen (p->name);
1619 if (strncmp (p->name, s, len) == 0)
1620 break;
1621 p++;
1622 }
1623 if (p->name[0] != s[0])
1624 {
19f7b010 1625 error_message = _(": unrecognizable v9a or v9b ancillary state register");
252b5132
RH		 1626 goto error;
1627 }
1628 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1629 {
1630 error_message = _(": rd on write only ancillary state register");
1631 goto error;
e0c6ed95 1632 }
19f7b010
JJ		 1633 if (p->regnum >= 24
1634 && (insn->architecture
1635 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1636 {
1637 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1638 error_message = _(": unrecognizable v9a ancillary state register");
1639 goto error;
1640 }
252b5132
RH		 1641 if (*args == '/')
1642 opcode |= (p->regnum << 14);
1643 else
1644 opcode |= (p->regnum << 25);
1645 s += len;
1646 continue;
1647 }
1648 else
1649 {
19f7b010 1650 error_message = _(": unrecognizable v9a or v9b ancillary state register");
252b5132
RH		 1651 goto error;
1652 }
1653
1654 case 'M':
1655 case 'm':
1656 if (strncmp (s, "%asr", 4) == 0)
1657 {
1658 s += 4;
1659
3882b010 1660 if (ISDIGIT (*s))
252b5132
RH		 1661 {
1662 long num = 0;
1663
3882b010 1664 while (ISDIGIT (*s))
252b5132
RH		 1665 {
1666 num = num * 10 + *s - '0';
1667 ++s;
1668 }
1669
1670 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1671 {
1672 if (num < 16 || 31 < num)
1673 {
1674 error_message = _(": asr number must be between 16 and 31");
1675 goto error;
1676 }
1677 }
1678 else
1679 {
1680 if (num < 0 || 31 < num)
1681 {
1682 error_message = _(": asr number must be between 0 and 31");
1683 goto error;
1684 }
1685 }
1686
1687 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1688 continue;
1689 }
1690 else
1691 {
1692 error_message = _(": expecting %asrN");
1693 goto error;
1694 }
e0c6ed95 1695 } /* if %asr */
252b5132
RH		 1696 break;
1697
1698 case 'I':
1699 the_insn.reloc = BFD_RELOC_SPARC_11;
1700 goto immediate;
1701
1702 case 'j':
1703 the_insn.reloc = BFD_RELOC_SPARC_10;
1704 goto immediate;
1705
1706 case 'X':
1707 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1708 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1709 the_insn.reloc = BFD_RELOC_SPARC_5;
1710 else
1711 the_insn.reloc = BFD_RELOC_SPARC13;
1712 /* These fields are unsigned, but for upward compatibility,
1713 allow negative values as well. */
1714 goto immediate;
1715
1716 case 'Y':
1717 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1718 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1719 the_insn.reloc = BFD_RELOC_SPARC_6;
1720 else
1721 the_insn.reloc = BFD_RELOC_SPARC13;
1722 /* These fields are unsigned, but for upward compatibility,
1723 allow negative values as well. */
1724 goto immediate;
1725
1726 case 'k':
1727 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1728 the_insn.pcrel = 1;
1729 goto immediate;
1730
1731 case 'G':
1732 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1733 the_insn.pcrel = 1;
1734 goto immediate;
1735
1736 case 'N':
1737 if (*s == 'p' && s[1] == 'n')
1738 {
1739 s += 2;
1740 continue;
1741 }
1742 break;
1743
1744 case 'T':
1745 if (*s == 'p' && s[1] == 't')
1746 {
1747 s += 2;
1748 continue;
1749 }
1750 break;
1751
1752 case 'z':
1753 if (*s == ' ')
1754 {
1755 ++s;
1756 }
1757 if (strncmp (s, "%icc", 4) == 0)
1758 {
1759 s += 4;
1760 continue;
1761 }
1762 break;
1763
1764 case 'Z':
1765 if (*s == ' ')
1766 {
1767 ++s;
1768 }
1769 if (strncmp (s, "%xcc", 4) == 0)
1770 {
1771 s += 4;
1772 continue;
1773 }
1774 break;
1775
1776 case '6':
1777 if (*s == ' ')
1778 {
1779 ++s;
1780 }
1781 if (strncmp (s, "%fcc0", 5) == 0)
1782 {
1783 s += 5;
1784 continue;
1785 }
1786 break;
1787
1788 case '7':
1789 if (*s == ' ')
1790 {
1791 ++s;
1792 }
1793 if (strncmp (s, "%fcc1", 5) == 0)
1794 {
1795 s += 5;
1796 continue;
1797 }
1798 break;
1799
1800 case '8':
1801 if (*s == ' ')
1802 {
1803 ++s;
1804 }
1805 if (strncmp (s, "%fcc2", 5) == 0)
1806 {
1807 s += 5;
1808 continue;
1809 }
1810 break;
1811
1812 case '9':
1813 if (*s == ' ')
1814 {
1815 ++s;
1816 }
1817 if (strncmp (s, "%fcc3", 5) == 0)
1818 {
1819 s += 5;
1820 continue;
1821 }
1822 break;
1823
1824 case 'P':
1825 if (strncmp (s, "%pc", 3) == 0)
1826 {
1827 s += 3;
1828 continue;
1829 }
1830 break;
1831
1832 case 'W':
1833 if (strncmp (s, "%tick", 5) == 0)
1834 {
1835 s += 5;
1836 continue;
1837 }
1838 break;
1839
e0c6ed95 1840 case '\0': /* End of args. */
b9734f35 1841 if (s[0] == ',' && s[1] == '%')
252b5132 1842 {
739f7f82 1843 static const struct ops
dfeb0666 1844 {
b9734f35
JJ		 1845 /* The name as it appears in assembler. */
1846 char *name;
1847 /* strlen (name), precomputed for speed */
1848 int len;
1849 /* The reloc this pseudo-op translates to. */
1850 int reloc;
739f7f82
DM		 1851 /* 1 if tls call. */
1852 int tls_call;
dfeb0666 1853 }
739f7f82 1854 ops[] =
dfeb0666 1855 {
b9734f35
JJ		 1856 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
1857 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
1858 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
1859 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
1860 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
1861 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
1862 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
dfeb0666 1863 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
739f7f82 1864 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 },
dfeb0666 1865 { NULL, 0, 0, 0 }
b9734f35 1866 };
739f7f82 1867 const struct ops *o;
b9734f35
JJ		 1868 char *s1;
1869 int npar = 0;
1870
739f7f82 1871 for (o = ops; o->name; o++)
b9734f35
JJ		 1872 if (strncmp (s + 2, o->name, o->len) == 0)
1873 break;
1874 if (o->name == NULL)
1875 break;
1876
1877 if (s[o->len + 2] != '(')
1878 {
1879 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1880 return special_case;
1881 }
1882
739f7f82 1883 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE)
b9734f35
JJ		 1884 {
1885 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1886 o->name);
1887 return special_case;
1888 }
1889
739f7f82 1890 if (o->tls_call
b9734f35
JJ		 1891 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
1892 || the_insn.exp.X_add_number != 0
1893 || the_insn.exp.X_add_symbol
1894 != symbol_find_or_make ("__tls_get_addr")))
1895 {
1896 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1897 o->name);
1898 return special_case;
1899 }
1900
1901 the_insn.reloc = o->reloc;
1902 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
1903 s += o->len + 3;
1904
1905 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
1906 if (*s1 == '(')
1907 npar++;
1908 else if (*s1 == ')')
1909 {
1910 if (!npar)
1911 break;
1912 npar--;
1913 }
1914
1915 if (*s1 != ')')
1916 {
1917 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1918 return special_case;
1919 }
1920
1921 *s1 = '\0';
1922 (void) get_expression (s);
1923 *s1 = ')';
1924 s = s1 + 1;
252b5132 1925 }
b9734f35
JJ		 1926 if (*s == '\0')
1927 match = 1;
252b5132
RH		 1928 break;
1929
1930 case '+':
1931 if (*s == '+')
1932 {
1933 ++s;
1934 continue;
1935 }
1936 if (*s == '-')
1937 {
1938 continue;
1939 }
1940 break;
1941
e0c6ed95 1942 case '[': /* These must match exactly. */
252b5132
RH		 1943 case ']':
1944 case ',':
1945 case ' ':
1946 if (*s++ == *args)
1947 continue;
1948 break;
1949
e0c6ed95 1950 case '#': /* Must be at least one digit. */
3882b010 1951 if (ISDIGIT (*s++))
252b5132 1952 {
3882b010 1953 while (ISDIGIT (*s))
252b5132
RH		 1954 {
1955 ++s;
1956 }
1957 continue;
1958 }
1959 break;
1960
e0c6ed95 1961 case 'C': /* Coprocessor state register. */
252b5132
RH		 1962 if (strncmp (s, "%csr", 4) == 0)
1963 {
1964 s += 4;
1965 continue;
1966 }
1967 break;
1968
e0c6ed95 1969 case 'b': /* Next operand is a coprocessor register. */
252b5132
RH		 1970 case 'c':
1971 case 'D':
3882b010 1972 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
252b5132
RH		 1973 {
1974 mask = *s++;
3882b010 1975 if (ISDIGIT (*s))
252b5132
RH		 1976 {
1977 mask = 10 * (mask - '0') + (*s++ - '0');
1978 if (mask >= 32)
1979 {
1980 break;
1981 }
1982 }
1983 else
1984 {
1985 mask -= '0';
1986 }
1987 switch (*args)
1988 {
1989
1990 case 'b':
1991 opcode |= mask << 14;
1992 continue;
1993
1994 case 'c':
1995 opcode |= mask;
1996 continue;
1997
1998 case 'D':
1999 opcode |= mask << 25;
2000 continue;
2001 }
2002 }
2003 break;
2004
2005 case 'r': /* next operand must be a register */
2006 case 'O':
2007 case '1':
2008 case '2':
2009 case 'd':
2010 if (*s++ == '%')
2011 {
2012 switch (c = *s++)
2013 {
2014
2015 case 'f': /* frame pointer */
2016 if (*s++ == 'p')
2017 {
2018 mask = 0x1e;
2019 break;
2020 }
2021 goto error;
2022
2023 case 'g': /* global register */
a22b281c
RH		 2024 c = *s++;
2025 if (isoctal (c))
252b5132
RH		 2026 {
2027 mask = c - '0';
2028 break;
2029 }
2030 goto error;
2031
2032 case 'i': /* in register */
a22b281c
RH		 2033 c = *s++;
2034 if (isoctal (c))
252b5132
RH		 2035 {
2036 mask = c - '0' + 24;
2037 break;
2038 }
2039 goto error;
2040
2041 case 'l': /* local register */
a22b281c
RH		 2042 c = *s++;
2043 if (isoctal (c))
252b5132
RH		 2044 {
2045 mask = (c - '0' + 16);
2046 break;
2047 }
2048 goto error;
2049
2050 case 'o': /* out register */
a22b281c
RH		 2051 c = *s++;
2052 if (isoctal (c))
252b5132
RH		 2053 {
2054 mask = (c - '0' + 8);
2055 break;
2056 }
2057 goto error;
2058
2059 case 's': /* stack pointer */
2060 if (*s++ == 'p')
2061 {
2062 mask = 0xe;
2063 break;
2064 }
2065 goto error;
2066
2067 case 'r': /* any register */
3882b010 2068 if (!ISDIGIT ((c = *s++)))
252b5132
RH		 2069 {
2070 goto error;
2071 }
2072 /* FALLTHROUGH */
2073 case '0':
2074 case '1':
2075 case '2':
2076 case '3':
2077 case '4':
2078 case '5':
2079 case '6':
2080 case '7':
2081 case '8':
2082 case '9':
3882b010 2083 if (ISDIGIT (*s))
252b5132
RH		 2084 {
2085 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2086 {
2087 goto error;
2088 }
2089 }
2090 else
2091 {
2092 c -= '0';
2093 }
2094 mask = c;
2095 break;
2096
2097 default:
2098 goto error;
2099 }
2100
6d8809aa 2101 if ((mask & ~1) == 2 && sparc_arch_size == 64
e0c6ed95 2102 && no_undeclared_regs && ! globals[mask])
79bd78be 2103 as_bad (_("detected global register use not covered by .register pseudo-op"));
6d8809aa 2104
252b5132
RH		 2105 /* Got the register, now figure out where
2106 it goes in the opcode. */
2107 switch (*args)
2108 {
2109 case '1':
2110 opcode |= mask << 14;
2111 continue;
2112
2113 case '2':
2114 opcode |= mask;
2115 continue;
2116
2117 case 'd':
2118 opcode |= mask << 25;
2119 continue;
2120
2121 case 'r':
2122 opcode |= (mask << 25) | (mask << 14);
2123 continue;
2124
2125 case 'O':
2126 opcode |= (mask << 25) | (mask << 0);
2127 continue;
2128 }
2129 }
2130 break;
2131
2132 case 'e': /* next operand is a floating point register */
2133 case 'v':
2134 case 'V':
2135
2136 case 'f':
2137 case 'B':
2138 case 'R':
2139
ea783ef3
DM		 2140 case '4':
2141 case '5':
2142
252b5132
RH		 2143 case 'g':
2144 case 'H':
2145 case 'J':
2146 {
2147 char format;
2148
2149 if (*s++ == '%'
2150 && ((format = *s) == 'f')
3882b010 2151 && ISDIGIT (*++s))
252b5132 2152 {
3882b010 2153 for (mask = 0; ISDIGIT (*s); ++s)
252b5132
RH		 2154 {
2155 mask = 10 * mask + (*s - '0');
2156 } /* read the number */
2157
2158 if ((*args == 'v'
2159 || *args == 'B'
ea783ef3 2160 || *args == '5'
252b5132
RH		 2161 || *args == 'H')
2162 && (mask & 1))
2163 {
2164 break;
2165 } /* register must be even numbered */
2166
2167 if ((*args == 'V'
2168 || *args == 'R'
2169 || *args == 'J')
2170 && (mask & 3))
2171 {
2172 break;
2173 } /* register must be multiple of 4 */
2174
2175 if (mask >= 64)
2176 {
2177 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2178 error_message = _(": There are only 64 f registers; [0-63]");
2179 else
2180 error_message = _(": There are only 32 f registers; [0-31]");
2181 goto error;
2182 } /* on error */
2183 else if (mask >= 32)
2184 {
2185 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2186 {
26664553
JJ		 2187 if (*args == 'e' || *args == 'f' || *args == 'g')
2188 {
2189 error_message
2190 = _(": There are only 32 single precision f registers; [0-31]");
2191 goto error;
2192 }
252b5132
RH		 2193 v9_arg_p = 1;
2194 mask -= 31; /* wrap high bit */
2195 }
2196 else
2197 {
2198 error_message = _(": There are only 32 f registers; [0-31]");
2199 goto error;
2200 }
2201 }
2202 }
2203 else
2204 {
2205 break;
ab3e48dc 2206 } /* if not an 'f' register. */
252b5132
RH		 2207
2208 switch (*args)
2209 {
2210 case 'v':
2211 case 'V':
2212 case 'e':
2213 opcode |= RS1 (mask);
2214 continue;
2215
252b5132
RH		 2216 case 'f':
2217 case 'B':
2218 case 'R':
2219 opcode |= RS2 (mask);
2220 continue;
2221
ea783ef3
DM		 2222 case '4':
2223 case '5':
2224 opcode |= RS3 (mask);
2225 continue;
2226
252b5132
RH		 2227 case 'g':
2228 case 'H':
2229 case 'J':
2230 opcode |= RD (mask);
2231 continue;
ab3e48dc 2232 } /* Pack it in. */
252b5132
RH		 2233
2234 know (0);
2235 break;
ab3e48dc 2236 } /* float arg */
252b5132
RH		 2237
2238 case 'F':
2239 if (strncmp (s, "%fsr", 4) == 0)
2240 {
2241 s += 4;
2242 continue;
2243 }
2244 break;
2245
ea783ef3
DM		 2246 case '(':
2247 if (strncmp (s, "%efsr", 5) == 0)
2248 {
2249 s += 5;
2250 continue;
2251 }
2252 break;
2253
ab3e48dc
KH		 2254 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2255 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
252b5132
RH		 2256 goto immediate;
2257
ab3e48dc 2258 case 'l': /* 22 bit PC relative immediate */
252b5132
RH		 2259 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2260 the_insn.pcrel = 1;
2261 goto immediate;
2262
ab3e48dc 2263 case 'L': /* 30 bit immediate */
252b5132
RH		 2264 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2265 the_insn.pcrel = 1;
2266 goto immediate;
2267
63fab58c 2268 case 'h':
ab3e48dc 2269 case 'n': /* 22 bit immediate */
252b5132
RH		 2270 the_insn.reloc = BFD_RELOC_SPARC22;
2271 goto immediate;
2272
ab3e48dc 2273 case 'i': /* 13 bit immediate */
252b5132
RH		 2274 the_insn.reloc = BFD_RELOC_SPARC13;
2275
2276 /* fallthrough */
2277
2278 immediate:
2279 if (*s == ' ')
2280 s++;
2281
cf9a1301
RH		 2282 {
2283 char *s1;
2284 char *op_arg = NULL;
30eb9c17 2285 static expressionS op_exp;
cf9a1301
RH		 2286 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2287
2288 /* Check for %hi, etc. */
2289 if (*s == '%')
2290 {
2291 static const struct ops {
2292 /* The name as it appears in assembler. */
2293 char *name;
2294 /* strlen (name), precomputed for speed */
2295 int len;
2296 /* The reloc this pseudo-op translates to. */
2297 int reloc;
2298 /* Non-zero if for v9 only. */
2299 int v9_p;
2300 /* Non-zero if can be used in pc-relative contexts. */
2301 int pcrel_p;/*FIXME:wip*/
2302 } ops[] = {
2303 /* hix/lox must appear before hi/lo so %hix won't be
2304 mistaken for %hi. */
2305 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2306 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2307 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2308 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
14865d76
DM		 2309 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 },
2310 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 },
cf9a1301
RH		 2311 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2312 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2313 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2314 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2315 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2316 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2317 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2318 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
b9734f35
JJ		 2319 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2320 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2321 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2322 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2323 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2324 0 },
2325 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2326 0 },
2327 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2328 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2329 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2330 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
739f7f82
DM		 2331 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
2332 0, 0 },
2333 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10,
2334 0, 0 },
c2158c24 2335 { NULL, 0, 0, 0, 0 }
cf9a1301
RH		 2336 };
2337 const struct ops *o;
e0c6ed95 2338
cf9a1301
RH		 2339 for (o = ops; o->name; o++)
2340 if (strncmp (s + 1, o->name, o->len) == 0)
2341 break;
2342 if (o->name == NULL)
252b5132 2343 break;
e0c6ed95 2344
cf9a1301
RH		 2345 if (s[o->len + 1] != '(')
2346 {
2347 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
a22b281c 2348 return special_case;
cf9a1301 2349 }
252b5132 2350
cf9a1301
RH		 2351 op_arg = o->name;
2352 the_insn.reloc = o->reloc;
2353 s += o->len + 2;
2354 v9_arg_p = o->v9_p;
2355 }
2356
2357 /* Note that if the get_expression() fails, we will still
2358 have created U entries in the symbol table for the
2359 'symbols' in the input string. Try not to create U
2360 symbols for registers, etc. */
252b5132 2361
252b5132
RH		 2362 /* This stuff checks to see if the expression ends in
2363 +%reg. If it does, it removes the register from
2364 the expression, and re-sets 's' to point to the
2365 right place. */
2366
cf9a1301
RH		 2367 if (op_arg)
2368 {
2369 int npar = 0;
2370
2371 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2372 if (*s1 == '(')
2373 npar++;
2374 else if (*s1 == ')')
2375 {
2376 if (!npar)
2377 break;
2378 npar--;
2379 }
2380
2381 if (*s1 != ')')
2382 {
2383 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
a22b281c 2384 return special_case;
cf9a1301 2385 }
e0c6ed95 2386
cf9a1301
RH		 2387 *s1 = '\0';
2388 (void) get_expression (s);
2389 *s1 = ')';
2390 s = s1 + 1;
2391 if (*s == ',' || *s == ']' || !*s)
2392 continue;
2393 if (*s != '+' && *s != '-')
2394 {
2395 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
a22b281c 2396 return special_case;
cf9a1301
RH		 2397 }
2398 *s1 = '0';
2399 s = s1;
2400 op_exp = the_insn.exp;
e0c6ed95 2401 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
cf9a1301 2402 }
252b5132 2403
e0c6ed95
AM		 2404 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2405 ;
252b5132 2406
3882b010 2407 if (s1 != s && ISDIGIT (s1[-1]))
252b5132
RH		 2408 {
2409 if (s1[-2] == '%' && s1[-3] == '+')
cf9a1301 2410 s1 -= 3;
f124dd4f 2411 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
cf9a1301 2412 s1 -= 4;
f124dd4f
DM		 2413 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+')
2414 s1 -= 5;
cf9a1301
RH		 2415 else
2416 s1 = NULL;
2417 if (s1)
252b5132 2418 {
252b5132 2419 *s1 = '\0';
1eb7027c
RH		 2420 if (op_arg && s1 == s + 1)
2421 the_insn.exp.X_op = O_absent;
2422 else
2423 (void) get_expression (s);
252b5132 2424 *s1 = '+';
cf9a1301
RH		 2425 if (op_arg)
2426 *s = ')';
252b5132 2427 s = s1;
252b5132 2428 }
cf9a1301
RH		 2429 }
2430 else
2431 s1 = NULL;
2432
2433 if (!s1)
2434 {
2435 (void) get_expression (s);
2436 if (op_arg)
2437 *s = ')';
2438 s = expr_end;
2439 }
2440
2441 if (op_arg)
2442 {
2443 the_insn.exp2 = the_insn.exp;
2444 the_insn.exp = op_exp;
2445 if (the_insn.exp2.X_op == O_absent)
2446 the_insn.exp2.X_op = O_illegal;
2447 else if (the_insn.exp.X_op == O_absent)
252b5132 2448 {
cf9a1301
RH		 2449 the_insn.exp = the_insn.exp2;
2450 the_insn.exp2.X_op = O_illegal;
2451 }
2452 else if (the_insn.exp.X_op == O_constant)
2453 {
2454 valueT val = the_insn.exp.X_add_number;
2455 switch (the_insn.reloc)
2456 {
1b50c718
ILT		 2457 default:
2458 break;
2459
cf9a1301
RH		 2460 case BFD_RELOC_SPARC_HH22:
2461 val = BSR (val, 32);
e0c6ed95 2462 /* Fall through. */
cf9a1301
RH		 2463
2464 case BFD_RELOC_SPARC_LM22:
2465 case BFD_RELOC_HI22:
2466 val = (val >> 10) & 0x3fffff;
2467 break;
2468
2469 case BFD_RELOC_SPARC_HM10:
2470 val = BSR (val, 32);
e0c6ed95 2471 /* Fall through. */
cf9a1301
RH		 2472
2473 case BFD_RELOC_LO10:
2474 val &= 0x3ff;
2475 break;
2476
2477 case BFD_RELOC_SPARC_H44:
2478 val >>= 22;
2479 val &= 0x3fffff;
2480 break;
2481
2482 case BFD_RELOC_SPARC_M44:
2483 val >>= 12;
2484 val &= 0x3ff;
2485 break;
2486
2487 case BFD_RELOC_SPARC_L44:
2488 val &= 0xfff;
2489 break;
2490
2491 case BFD_RELOC_SPARC_HIX22:
ab3e48dc 2492 val = ~val;
cf9a1301
RH		 2493 val = (val >> 10) & 0x3fffff;
2494 break;
2495
2496 case BFD_RELOC_SPARC_LOX10:
2497 val = (val & 0x3ff) | 0x1c00;
2498 break;
2499 }
2500 the_insn.exp = the_insn.exp2;
2501 the_insn.exp.X_add_number += val;
2502 the_insn.exp2.X_op = O_illegal;
2503 the_insn.reloc = old_reloc;
2504 }
2505 else if (the_insn.exp2.X_op != O_constant)
2506 {
2507 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
a22b281c 2508 return special_case;
cf9a1301
RH		 2509 }
2510 else
2511 {
dabe3bbc 2512 if (old_reloc != BFD_RELOC_SPARC13
cf9a1301
RH		 2513 || the_insn.reloc != BFD_RELOC_LO10
2514 || sparc_arch_size != 64
2515 || sparc_pic_code)
2516 {
2517 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
a22b281c 2518 return special_case;
cf9a1301
RH		 2519 }
2520 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
252b5132
RH		 2521 }
2522 }
2523 }
252b5132
RH		 2524 /* Check for constants that don't require emitting a reloc. */
2525 if (the_insn.exp.X_op == O_constant
2526 && the_insn.exp.X_add_symbol == 0
2527 && the_insn.exp.X_op_symbol == 0)
2528 {
2529 /* For pc-relative call instructions, we reject
2530 constants to get better code. */
2531 if (the_insn.pcrel
2532 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2533 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2534 {
2535 error_message = _(": PC-relative operand can't be a constant");
2536 goto error;
2537 }
2538
b9734f35
JJ		 2539 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2540 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2541 {
2542 error_message = _(": TLS operand can't be a constant");
2543 goto error;
2544 }
2545
55cf6793 2546 /* Constants that won't fit are checked in md_apply_fix
252b5132
RH		 2547 and bfd_install_relocation.
2548 ??? It would be preferable to install the constants
2549 into the insn here and save having to create a fixS
2550 for each one. There already exists code to handle
55cf6793 2551 all the various cases (e.g. in md_apply_fix and
252b5132
RH		 2552 bfd_install_relocation) so duplicating all that code
2553 here isn't right. */
2554 }
2555
2556 continue;
2557
2558 case 'a':
2559 if (*s++ == 'a')
2560 {
2561 opcode |= ANNUL;
2562 continue;
2563 }
2564 break;
2565
2566 case 'A':
2567 {
2568 int asi = 0;
2569
2570 /* Parse an asi. */
2571 if (*s == '#')
2572 {
2573 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2574 {
2575 error_message = _(": invalid ASI name");
2576 goto error;
2577 }
2578 }
2579 else
2580 {
2581 if (! parse_const_expr_arg (&s, &asi))
2582 {
2583 error_message = _(": invalid ASI expression");
2584 goto error;
2585 }
2586 if (asi < 0 || asi > 255)
2587 {
2588 error_message = _(": invalid ASI number");
2589 goto error;
2590 }
2591 }
2592 opcode |= ASI (asi);
2593 continue;
e0c6ed95 2594 } /* Alternate space. */
252b5132
RH		 2595
2596 case 'p':
2597 if (strncmp (s, "%psr", 4) == 0)
2598 {
2599 s += 4;
2600 continue;
2601 }
2602 break;
2603
e0c6ed95 2604 case 'q': /* Floating point queue. */
252b5132
RH		 2605 if (strncmp (s, "%fq", 3) == 0)
2606 {
2607 s += 3;
2608 continue;
2609 }
2610 break;
2611
e0c6ed95 2612 case 'Q': /* Coprocessor queue. */
252b5132
RH		 2613 if (strncmp (s, "%cq", 3) == 0)
2614 {
2615 s += 3;
2616 continue;
2617 }
2618 break;
2619
2620 case 'S':
2621 if (strcmp (str, "set") == 0
2622 || strcmp (str, "setuw") == 0)
2623 {
2624 special_case = SPECIAL_CASE_SET;
2625 continue;
2626 }
2627 else if (strcmp (str, "setsw") == 0)
2628 {
2629 special_case = SPECIAL_CASE_SETSW;
2630 continue;
2631 }
2632 else if (strcmp (str, "setx") == 0)
2633 {
2634 special_case = SPECIAL_CASE_SETX;
2635 continue;
2636 }
2637 else if (strncmp (str, "fdiv", 4) == 0)
2638 {
2639 special_case = SPECIAL_CASE_FDIV;
2640 continue;
2641 }
2642 break;
2643
2644 case 'o':
2645 if (strncmp (s, "%asi", 4) != 0)
2646 break;
2647 s += 4;
2648 continue;
2649
2650 case 's':
2651 if (strncmp (s, "%fprs", 5) != 0)
2652 break;
2653 s += 5;
2654 continue;
2655
2656 case 'E':
2657 if (strncmp (s, "%ccr", 4) != 0)
2658 break;
2659 s += 4;
2660 continue;
2661
2662 case 't':
2663 if (strncmp (s, "%tbr", 4) != 0)
2664 break;
2665 s += 4;
2666 continue;
2667
2668 case 'w':
2669 if (strncmp (s, "%wim", 4) != 0)
2670 break;
2671 s += 4;
2672 continue;
2673
2674 case 'x':
2675 {
2676 char *push = input_line_pointer;
2677 expressionS e;
2678
2679 input_line_pointer = s;
2680 expression (&e);
2681 if (e.X_op == O_constant)
2682 {
2683 int n = e.X_add_number;
2684 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2685 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2686 else
2687 opcode |= e.X_add_number << 5;
2688 }
2689 else
2690 as_bad (_("non-immediate OPF operand, ignored"));
2691 s = input_line_pointer;
2692 input_line_pointer = push;
2693 continue;
2694 }
2695
2696 case 'y':
2697 if (strncmp (s, "%y", 2) != 0)
2698 break;
2699 s += 2;
2700 continue;
2701
2702 case 'u':
2703 case 'U':
2704 {
2705 /* Parse a sparclet cpreg. */
2706 int cpreg;
2707 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2708 {
2709 error_message = _(": invalid cpreg name");
2710 goto error;
2711 }
2712 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2713 continue;
2714 }
2715
2716 default:
2717 as_fatal (_("failed sanity check."));
e0c6ed95 2718 } /* switch on arg code. */
252b5132
RH		 2719
2720 /* Break out of for() loop. */
2721 break;
e0c6ed95 2722 } /* For each arg that we expect. */
252b5132
RH		 2723
2724 error:
2725 if (match == 0)
2726 {
e0c6ed95 2727 /* Args don't match. */
252b5132
RH		 2728 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2729 && (insn->name == insn[1].name
2730 || !strcmp (insn->name, insn[1].name)))
2731 {
2732 ++insn;
2733 s = argsStart;
2734 continue;
2735 }
2736 else
2737 {
2738 as_bad (_("Illegal operands%s"), error_message);
a22b281c 2739 return special_case;
252b5132
RH		 2740 }
2741 }
2742 else
2743 {
e0c6ed95 2744 /* We have a match. Now see if the architecture is OK. */
252b5132
RH		 2745 int needed_arch_mask = insn->architecture;
2746
2747 if (v9_arg_p)
2748 {
19f7b010
JJ		 2749 needed_arch_mask &=
2750 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2751 if (! needed_arch_mask)
2752 needed_arch_mask =
2753 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
252b5132
RH		 2754 }
2755
e0c6ed95
AM		 2756 if (needed_arch_mask
2757 & SPARC_OPCODE_SUPPORTED (current_architecture))
2758 /* OK. */
2759 ;
252b5132 2760 /* Can we bump up the architecture? */
e0c6ed95
AM		 2761 else if (needed_arch_mask
2762 & SPARC_OPCODE_SUPPORTED (max_architecture))
252b5132
RH		 2763 {
2764 enum sparc_opcode_arch_val needed_architecture =
2765 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2766 & needed_arch_mask);
2767
9c2799c2 2768 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
252b5132
RH		 2769 if (warn_on_bump
2770 && needed_architecture > warn_after_architecture)
2771 {
2772 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2773 sparc_opcode_archs[current_architecture].name,
2774 sparc_opcode_archs[needed_architecture].name,
2775 str);
2776 warn_after_architecture = needed_architecture;
2777 }
2778 current_architecture = needed_architecture;
2779 }
2780 /* Conflict. */
2781 /* ??? This seems to be a bit fragile. What if the next entry in
2782 the opcode table is the one we want and it is supported?
2783 It is possible to arrange the table today so that this can't
2784 happen but what about tomorrow? */
2785 else
2786 {
e0c6ed95 2787 int arch, printed_one_p = 0;
252b5132
RH		 2788 char *p;
2789 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2790
2791 /* Create a list of the architectures that support the insn. */
e0c6ed95 2792 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
252b5132
RH		 2793 p = required_archs;
2794 arch = sparc_ffs (needed_arch_mask);
2795 while ((1 << arch) <= needed_arch_mask)
2796 {
2797 if ((1 << arch) & needed_arch_mask)
2798 {
2799 if (printed_one_p)
2800 *p++ = '|';
2801 strcpy (p, sparc_opcode_archs[arch].name);
2802 p += strlen (p);
2803 printed_one_p = 1;
2804 }
2805 ++arch;
2806 }
2807
2808 as_bad (_("Architecture mismatch on \"%s\"."), str);
2809 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2810 required_archs,
2811 sparc_opcode_archs[max_architecture].name);
a22b281c 2812 return special_case;
252b5132 2813 }
e0c6ed95 2814 } /* If no match. */
252b5132
RH		 2815
2816 break;
e0c6ed95 2817 } /* Forever looking for a match. */
252b5132
RH		 2818
2819 the_insn.opcode = opcode;
a22b281c 2820 return special_case;
252b5132
RH		 2821}
2822
2823/* Parse an argument that can be expressed as a keyword.
2824 (eg: #StoreStore or %ccfr).
2825 The result is a boolean indicating success.
2826 If successful, INPUT_POINTER is updated. */
2827
2828static int
5a49b8ac
AM		 2829parse_keyword_arg (int (*lookup_fn) (const char *),
2830 char **input_pointerP,
2831 int *valueP)
252b5132
RH		 2832{
2833 int value;
2834 char c, *p, *q;
2835
2836 p = *input_pointerP;
2837 for (q = p + (*p == '#' || *p == '%');
3882b010 2838 ISALNUM (*q) || *q == '_';
252b5132
RH		 2839 ++q)
2840 continue;
2841 c = *q;
2842 *q = 0;
2843 value = (*lookup_fn) (p);
2844 *q = c;
2845 if (value == -1)
2846 return 0;
2847 *valueP = value;
2848 *input_pointerP = q;
2849 return 1;
2850}
2851
2852/* Parse an argument that is a constant expression.
2853 The result is a boolean indicating success. */
2854
2855static int
5a49b8ac 2856parse_const_expr_arg (char **input_pointerP, int *valueP)
252b5132
RH		 2857{
2858 char *save = input_line_pointer;
2859 expressionS exp;
2860
2861 input_line_pointer = *input_pointerP;
2862 /* The next expression may be something other than a constant
2863 (say if we're not processing the right variant of the insn).
2864 Don't call expression unless we're sure it will succeed as it will
2865 signal an error (which we want to defer until later). */
2866 /* FIXME: It might be better to define md_operand and have it recognize
2867 things like %asi, etc. but continuing that route through to the end
2868 is a lot of work. */
2869 if (*input_line_pointer == '%')
2870 {
2871 input_line_pointer = save;
2872 return 0;
2873 }
2874 expression (&exp);
2875 *input_pointerP = input_line_pointer;
2876 input_line_pointer = save;
2877 if (exp.X_op != O_constant)
2878 return 0;
2879 *valueP = exp.X_add_number;
2880 return 1;
2881}
2882
2883/* Subroutine of sparc_ip to parse an expression. */
2884
2885static int
5a49b8ac 2886get_expression (char *str)
252b5132
RH		 2887{
2888 char *save_in;
2889 segT seg;
2890
2891 save_in = input_line_pointer;
2892 input_line_pointer = str;
2893 seg = expression (&the_insn.exp);
2894 if (seg != absolute_section
2895 && seg != text_section
2896 && seg != data_section
2897 && seg != bss_section
2898 && seg != undefined_section)
2899 {
2900 the_insn.error = _("bad segment");
2901 expr_end = input_line_pointer;
2902 input_line_pointer = save_in;
2903 return 1;
2904 }
2905 expr_end = input_line_pointer;
2906 input_line_pointer = save_in;
2907 return 0;
2908}
2909
2910/* Subroutine of md_assemble to output one insn. */
2911
2912static void
91d6fa6a 2913output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn)
252b5132
RH		 2914{
2915 char *toP = frag_more (4);
2916
e0c6ed95 2917 /* Put out the opcode. */
252b5132 2918 if (INSN_BIG_ENDIAN)
91d6fa6a 2919 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4);
252b5132 2920 else
91d6fa6a 2921 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4);
252b5132 2922
e0c6ed95 2923 /* Put out the symbol-dependent stuff. */
91d6fa6a 2924 if (theinsn->reloc != BFD_RELOC_NONE)
252b5132 2925 {
e0c6ed95
AM		 2926 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2927 (toP - frag_now->fr_literal), /* Where. */
2928 4, /* Size. */
91d6fa6a
NC		 2929 &theinsn->exp,
2930 theinsn->pcrel,
2931 theinsn->reloc);
252b5132 2932 /* Turn off overflow checking in fixup_segment. We'll do our
55cf6793 2933 own overflow checking in md_apply_fix. This is necessary because
252b5132
RH		 2934 the insn size is 4 and fixup_segment will signal an overflow for
2935 large 8 byte quantities. */
2936 fixP->fx_no_overflow = 1;
91d6fa6a
NC		 2937 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10)
2938 fixP->tc_fix_data = theinsn->exp2.X_add_number;
252b5132
RH		 2939 }
2940
2941 last_insn = insn;
91d6fa6a 2942 last_opcode = theinsn->opcode;
732d96b6
JJ		 2943
2944#ifdef OBJ_ELF
2945 dwarf2_emit_insn (4);
2946#endif
252b5132
RH		 2947}
2948\f
252b5132 2949char *
499ac353 2950md_atof (int type, char *litP, int *sizeP)
252b5132 2951{
499ac353 2952 return ieee_md_atof (type, litP, sizeP, target_big_endian);
252b5132
RH		 2953}
2954
2955/* Write a value out to the object file, using the appropriate
2956 endianness. */
2957
2958void
5a49b8ac 2959md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 2960{
2961 if (target_big_endian)
2962 number_to_chars_bigendian (buf, val, n);
2963 else if (target_little_endian_data
2964 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
e0c6ed95
AM		 2965 /* Output debug words, which are not in allocated sections, as big
2966 endian. */
252b5132
RH		 2967 number_to_chars_bigendian (buf, val, n);
2968 else if (target_little_endian_data || ! target_big_endian)
2969 number_to_chars_littleendian (buf, val, n);
2970}
2971\f
2972/* Apply a fixS to the frags, now that we know the value it ought to
81d4177b 2973 hold. */
252b5132 2974
94f592af 2975void
5a49b8ac 2976md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
252b5132
RH		 2977{
2978 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
94f592af 2979 offsetT val = * (offsetT *) valP;
252b5132
RH		 2980 long insn;
2981
9c2799c2 2982 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
252b5132 2983
e0c6ed95 2984 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 2985
2986#ifdef OBJ_ELF
a161fe53 2987 /* SPARC ELF relocations don't use an addend in the data field. */
252b5132 2988 if (fixP->fx_addsy != NULL)
7c1d0959
L		 2989 {
2990 switch (fixP->fx_r_type)
2991 {
2992 case BFD_RELOC_SPARC_TLS_GD_HI22:
2993 case BFD_RELOC_SPARC_TLS_GD_LO10:
2994 case BFD_RELOC_SPARC_TLS_GD_ADD:
2995 case BFD_RELOC_SPARC_TLS_GD_CALL:
2996 case BFD_RELOC_SPARC_TLS_LDM_HI22:
2997 case BFD_RELOC_SPARC_TLS_LDM_LO10:
2998 case BFD_RELOC_SPARC_TLS_LDM_ADD:
2999 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3000 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3001 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3002 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3003 case BFD_RELOC_SPARC_TLS_IE_HI22:
3004 case BFD_RELOC_SPARC_TLS_IE_LO10:
3005 case BFD_RELOC_SPARC_TLS_IE_LD:
3006 case BFD_RELOC_SPARC_TLS_IE_LDX:
3007 case BFD_RELOC_SPARC_TLS_IE_ADD:
3008 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3009 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3010 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3011 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3012 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3013 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3014 case BFD_RELOC_SPARC_TLS_TPOFF32:
3015 case BFD_RELOC_SPARC_TLS_TPOFF64:
3016 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3017
3018 default:
3019 break;
3020 }
3021
3022 return;
3023 }
252b5132
RH		 3024#endif
3025
3026 /* This is a hack. There should be a better way to
3027 handle this. Probably in terms of howto fields, once
3028 we can look at these fixups in terms of howtos. */
3029 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3030 val += fixP->fx_where + fixP->fx_frag->fr_address;
3031
3032#ifdef OBJ_AOUT
3033 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3034 generate a reloc, then we just want to let the reloc addend set
3035 the value. We do not want to also stuff the addend into the
3036 object file. Including the addend in the object file works when
3037 doing a static link, because the linker will ignore the object
3038 file contents. However, the dynamic linker does not ignore the
3039 object file contents. */
3040 if (fixP->fx_addsy != NULL
3041 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3042 val = 0;
3043
3044 /* When generating PIC code, we do not want an addend for a reloc
3045 against a local symbol. We adjust fx_addnumber to cancel out the
3046 value already included in val, and to also cancel out the
3047 adjustment which bfd_install_relocation will create. */
3048 if (sparc_pic_code
3049 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3050 && fixP->fx_addsy != NULL
3051 && ! S_IS_COMMON (fixP->fx_addsy)
49309057 3052 && symbol_section_p (fixP->fx_addsy))
252b5132
RH		 3053 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3054
3055 /* When generating PIC code, we need to fiddle to get
3056 bfd_install_relocation to do the right thing for a PC relative
3057 reloc against a local symbol which we are going to keep. */
3058 if (sparc_pic_code
3059 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3060 && fixP->fx_addsy != NULL
3061 && (S_IS_EXTERNAL (fixP->fx_addsy)
3062 || S_IS_WEAK (fixP->fx_addsy))
3063 && S_IS_DEFINED (fixP->fx_addsy)
3064 && ! S_IS_COMMON (fixP->fx_addsy))
3065 {
3066 val = 0;
3067 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3068 }
3069#endif
3070
3071 /* If this is a data relocation, just output VAL. */
3072
0f2712ed
NC		 3073 if (fixP->fx_r_type == BFD_RELOC_16
3074 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
252b5132
RH		 3075 {
3076 md_number_to_chars (buf, val, 2);
3077 }
3078 else if (fixP->fx_r_type == BFD_RELOC_32
0f2712ed 3079 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
252b5132
RH		 3080 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3081 {
3082 md_number_to_chars (buf, val, 4);
3083 }
0f2712ed
NC		 3084 else if (fixP->fx_r_type == BFD_RELOC_64
3085 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
252b5132
RH		 3086 {
3087 md_number_to_chars (buf, val, 8);
3088 }
e0c6ed95 3089 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
252b5132
RH		 3090 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3091 {
3092 fixP->fx_done = 0;
94f592af 3093 return;
252b5132
RH		 3094 }
3095 else
3096 {
3097 /* It's a relocation against an instruction. */
3098
3099 if (INSN_BIG_ENDIAN)
3100 insn = bfd_getb32 ((unsigned char *) buf);
3101 else
3102 insn = bfd_getl32 ((unsigned char *) buf);
e0c6ed95 3103
252b5132
RH		 3104 switch (fixP->fx_r_type)
3105 {
3106 case BFD_RELOC_32_PCREL_S2:
3107 val = val >> 2;
3108 /* FIXME: This increment-by-one deserves a comment of why it's
3109 being done! */
3110 if (! sparc_pic_code
3111 || fixP->fx_addsy == NULL
49309057 3112 || symbol_section_p (fixP->fx_addsy))
252b5132 3113 ++val;
6faf3d66 3114
252b5132 3115 insn |= val & 0x3fffffff;
6faf3d66 3116
e0c6ed95 3117 /* See if we have a delay slot. */
6faf3d66
JJ		 3118 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3119 {
3120#define G0 0
3121#define O7 15
3122#define XCC (2 << 20)
3123#define COND(x) (((x)&0xf)<<25)
3124#define CONDA COND(0x8)
3125#define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3126#define INSN_BA (F2(0,2) | CONDA)
3127#define INSN_OR F3(2, 0x2, 0)
3128#define INSN_NOP F2(0,4)
3129
3130 long delay;
3131
3132 /* If the instruction is a call with either:
3133 restore
3134 arithmetic instruction with rd == %o7
3135 where rs1 != %o7 and rs2 if it is register != %o7
3136 then we can optimize if the call destination is near
3137 by changing the call into a branch always. */
3138 if (INSN_BIG_ENDIAN)
3139 delay = bfd_getb32 ((unsigned char *) buf + 4);
3140 else
3141 delay = bfd_getl32 ((unsigned char *) buf + 4);
e0c6ed95 3142 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
6faf3d66 3143 break;
e0c6ed95
AM		 3144 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3145 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3146 || ((delay & RD (~0)) != RD (O7))))
6faf3d66 3147 break;
e0c6ed95
AM		 3148 if ((delay & RS1 (~0)) == RS1 (O7)
3149 || ((delay & F3I (~0)) == 0
3150 && (delay & RS2 (~0)) == RS2 (O7)))
6faf3d66
JJ		 3151 break;
3152 /* Ensure the branch will fit into simm22. */
3153 if ((val & 0x3fe00000)
3154 && (val & 0x3fe00000) != 0x3fe00000)
3155 break;
3156 /* Check if the arch is v9 and branch will fit
3157 into simm19. */
3158 if (((val & 0x3c0000) == 0
3159 || (val & 0x3c0000) == 0x3c0000)
3160 && (sparc_arch_size == 64
3161 || current_architecture >= SPARC_OPCODE_ARCH_V9))
e0c6ed95 3162 /* ba,pt %xcc */
6faf3d66
JJ		 3163 insn = INSN_BPA | (val & 0x7ffff);
3164 else
e0c6ed95 3165 /* ba */
6faf3d66
JJ		 3166 insn = INSN_BA | (val & 0x3fffff);
3167 if (fixP->fx_where >= 4
e0c6ed95
AM		 3168 && ((delay & (0xffffffff ^ RS1 (~0)))
3169 == (INSN_OR | RD (O7) | RS2 (G0))))
6faf3d66
JJ		 3170 {
3171 long setter;
3172 int reg;
3173
3174 if (INSN_BIG_ENDIAN)
3175 setter = bfd_getb32 ((unsigned char *) buf - 4);
3176 else
3177 setter = bfd_getl32 ((unsigned char *) buf - 4);
e0c6ed95 3178 if ((setter & (0xffffffff ^ RD (~0)))
ab3e48dc 3179 != (INSN_OR | RS1 (O7) | RS2 (G0)))
6faf3d66
JJ		 3180 break;
3181 /* The sequence was
3182 or %o7, %g0, %rN
3183 call foo
3184 or %rN, %g0, %o7
3185
3186 If call foo was replaced with ba, replace
3187 or %rN, %g0, %o7 with nop. */
e0c6ed95
AM		 3188 reg = (delay & RS1 (~0)) >> 14;
3189 if (reg != ((setter & RD (~0)) >> 25)
6faf3d66
JJ		 3190 || reg == G0 || reg == O7)
3191 break;
3192
3193 if (INSN_BIG_ENDIAN)
3194 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3195 else
3196 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3197 }
3198 }
252b5132
RH		 3199 break;
3200
3201 case BFD_RELOC_SPARC_11:
3202 if (! in_signed_range (val, 0x7ff))
3203 as_bad_where (fixP->fx_file, fixP->fx_line,
3204 _("relocation overflow"));
3205 insn |= val & 0x7ff;
3206 break;
3207
3208 case BFD_RELOC_SPARC_10:
3209 if (! in_signed_range (val, 0x3ff))
3210 as_bad_where (fixP->fx_file, fixP->fx_line,
3211 _("relocation overflow"));
3212 insn |= val & 0x3ff;
3213 break;
3214
3215 case BFD_RELOC_SPARC_7:
3216 if (! in_bitfield_range (val, 0x7f))
3217 as_bad_where (fixP->fx_file, fixP->fx_line,
3218 _("relocation overflow"));
3219 insn |= val & 0x7f;
3220 break;
3221
3222 case BFD_RELOC_SPARC_6:
3223 if (! in_bitfield_range (val, 0x3f))
3224 as_bad_where (fixP->fx_file, fixP->fx_line,
3225 _("relocation overflow"));
3226 insn |= val & 0x3f;
3227 break;
3228
3229 case BFD_RELOC_SPARC_5:
3230 if (! in_bitfield_range (val, 0x1f))
3231 as_bad_where (fixP->fx_file, fixP->fx_line,
3232 _("relocation overflow"));
3233 insn |= val & 0x1f;
3234 break;
3235
3236 case BFD_RELOC_SPARC_WDISP16:
c699f087
JJ		 3237 if ((val & 3)
3238 || val >= 0x1fffc
3239 || val <= -(offsetT) 0x20008)
252b5132
RH		 3240 as_bad_where (fixP->fx_file, fixP->fx_line,
3241 _("relocation overflow"));
3242 /* FIXME: The +1 deserves a comment. */
3243 val = (val >> 2) + 1;
3244 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3245 break;
3246
3247 case BFD_RELOC_SPARC_WDISP19:
c699f087
JJ		 3248 if ((val & 3)
3249 || val >= 0xffffc
3250 || val <= -(offsetT) 0x100008)
252b5132
RH		 3251 as_bad_where (fixP->fx_file, fixP->fx_line,
3252 _("relocation overflow"));
3253 /* FIXME: The +1 deserves a comment. */
3254 val = (val >> 2) + 1;
3255 insn |= val & 0x7ffff;
3256 break;
3257
3258 case BFD_RELOC_SPARC_HH22:
3259 val = BSR (val, 32);
e0c6ed95 3260 /* Fall through. */
252b5132
RH		 3261
3262 case BFD_RELOC_SPARC_LM22:
3263 case BFD_RELOC_HI22:
3264 if (!fixP->fx_addsy)
94f592af 3265 insn |= (val >> 10) & 0x3fffff;
252b5132 3266 else
94f592af
NC		 3267 /* FIXME: Need comment explaining why we do this. */
3268 insn &= ~0xffff;
252b5132
RH		 3269 break;
3270
3271 case BFD_RELOC_SPARC22:
3272 if (val & ~0x003fffff)
3273 as_bad_where (fixP->fx_file, fixP->fx_line,
3274 _("relocation overflow"));
3275 insn |= (val & 0x3fffff);
3276 break;
3277
3278 case BFD_RELOC_SPARC_HM10:
3279 val = BSR (val, 32);
e0c6ed95 3280 /* Fall through. */
252b5132
RH		 3281
3282 case BFD_RELOC_LO10:
3283 if (!fixP->fx_addsy)
94f592af 3284 insn |= val & 0x3ff;
252b5132 3285 else
94f592af
NC		 3286 /* FIXME: Need comment explaining why we do this. */
3287 insn &= ~0xff;
252b5132
RH		 3288 break;
3289
dabe3bbc
RH		 3290 case BFD_RELOC_SPARC_OLO10:
3291 val &= 0x3ff;
3292 val += fixP->tc_fix_data;
e0c6ed95 3293 /* Fall through. */
dabe3bbc 3294
252b5132
RH		 3295 case BFD_RELOC_SPARC13:
3296 if (! in_signed_range (val, 0x1fff))
3297 as_bad_where (fixP->fx_file, fixP->fx_line,
3298 _("relocation overflow"));
3299 insn |= val & 0x1fff;
3300 break;
3301
3302 case BFD_RELOC_SPARC_WDISP22:
3303 val = (val >> 2) + 1;
e0c6ed95 3304 /* Fall through. */
252b5132
RH		 3305 case BFD_RELOC_SPARC_BASE22:
3306 insn |= val & 0x3fffff;
3307 break;
3308
3309 case BFD_RELOC_SPARC_H44:
3310 if (!fixP->fx_addsy)
3311 {
3312 bfd_vma tval = val;
3313 tval >>= 22;
3314 insn |= tval & 0x3fffff;
3315 }
3316 break;
3317
3318 case BFD_RELOC_SPARC_M44:
3319 if (!fixP->fx_addsy)
3320 insn |= (val >> 12) & 0x3ff;
3321 break;
3322
3323 case BFD_RELOC_SPARC_L44:
3324 if (!fixP->fx_addsy)
3325 insn |= val & 0xfff;
3326 break;
3327
3328 case BFD_RELOC_SPARC_HIX22:
3329 if (!fixP->fx_addsy)
3330 {
ab3e48dc 3331 val ^= ~(offsetT) 0;
252b5132
RH		 3332 insn |= (val >> 10) & 0x3fffff;
3333 }
3334 break;
3335
3336 case BFD_RELOC_SPARC_LOX10:
3337 if (!fixP->fx_addsy)
3338 insn |= 0x1c00 | (val & 0x3ff);
3339 break;
3340
3341 case BFD_RELOC_NONE:
3342 default:
3343 as_bad_where (fixP->fx_file, fixP->fx_line,
3344 _("bad or unhandled relocation type: 0x%02x"),
3345 fixP->fx_r_type);
3346 break;
3347 }
3348
3349 if (INSN_BIG_ENDIAN)
3350 bfd_putb32 (insn, (unsigned char *) buf);
3351 else
3352 bfd_putl32 (insn, (unsigned char *) buf);
3353 }
3354
3355 /* Are we finished with this relocation now? */
3356 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3357 fixP->fx_done = 1;
252b5132
RH		 3358}
3359
3360/* Translate internal representation of relocation info to BFD target
3361 format. */
e0c6ed95 3362
dabe3bbc 3363arelent **
5a49b8ac 3364tc_gen_reloc (asection *section, fixS *fixp)
252b5132 3365{
dabe3bbc 3366 static arelent *relocs[3];
252b5132
RH		 3367 arelent *reloc;
3368 bfd_reloc_code_real_type code;
3369
dabe3bbc
RH		 3370 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3371 relocs[1] = NULL;
252b5132 3372
49309057
ILT		 3373 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3374 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 3375 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3376
3377 switch (fixp->fx_r_type)
3378 {
3379 case BFD_RELOC_16:
3380 case BFD_RELOC_32:
3381 case BFD_RELOC_HI22:
3382 case BFD_RELOC_LO10:
3383 case BFD_RELOC_32_PCREL_S2:
3384 case BFD_RELOC_SPARC13:
63fab58c 3385 case BFD_RELOC_SPARC22:
1a6b486f
DM		 3386 case BFD_RELOC_SPARC_PC22:
3387 case BFD_RELOC_SPARC_PC10:
252b5132
RH		 3388 case BFD_RELOC_SPARC_BASE13:
3389 case BFD_RELOC_SPARC_WDISP16:
3390 case BFD_RELOC_SPARC_WDISP19:
3391 case BFD_RELOC_SPARC_WDISP22:
3392 case BFD_RELOC_64:
3393 case BFD_RELOC_SPARC_5:
3394 case BFD_RELOC_SPARC_6:
3395 case BFD_RELOC_SPARC_7:
3396 case BFD_RELOC_SPARC_10:
3397 case BFD_RELOC_SPARC_11:
3398 case BFD_RELOC_SPARC_HH22:
3399 case BFD_RELOC_SPARC_HM10:
3400 case BFD_RELOC_SPARC_LM22:
3401 case BFD_RELOC_SPARC_PC_HH22:
3402 case BFD_RELOC_SPARC_PC_HM10:
3403 case BFD_RELOC_SPARC_PC_LM22:
3404 case BFD_RELOC_SPARC_H44:
3405 case BFD_RELOC_SPARC_M44:
3406 case BFD_RELOC_SPARC_L44:
3407 case BFD_RELOC_SPARC_HIX22:
3408 case BFD_RELOC_SPARC_LOX10:
3409 case BFD_RELOC_SPARC_REV32:
dabe3bbc 3410 case BFD_RELOC_SPARC_OLO10:
0f2712ed
NC		 3411 case BFD_RELOC_SPARC_UA16:
3412 case BFD_RELOC_SPARC_UA32:
3413 case BFD_RELOC_SPARC_UA64:
bd5e6e7e
JJ		 3414 case BFD_RELOC_8_PCREL:
3415 case BFD_RELOC_16_PCREL:
3416 case BFD_RELOC_32_PCREL:
3417 case BFD_RELOC_64_PCREL:
3418 case BFD_RELOC_SPARC_PLT32:
3419 case BFD_RELOC_SPARC_PLT64:
252b5132
RH		 3420 case BFD_RELOC_VTABLE_ENTRY:
3421 case BFD_RELOC_VTABLE_INHERIT:
b9734f35
JJ		 3422 case BFD_RELOC_SPARC_TLS_GD_HI22:
3423 case BFD_RELOC_SPARC_TLS_GD_LO10:
3424 case BFD_RELOC_SPARC_TLS_GD_ADD:
3425 case BFD_RELOC_SPARC_TLS_GD_CALL:
3426 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3427 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3428 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3429 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3430 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3431 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3432 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3433 case BFD_RELOC_SPARC_TLS_IE_HI22:
3434 case BFD_RELOC_SPARC_TLS_IE_LO10:
3435 case BFD_RELOC_SPARC_TLS_IE_LD:
3436 case BFD_RELOC_SPARC_TLS_IE_LDX:
3437 case BFD_RELOC_SPARC_TLS_IE_ADD:
3438 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3439 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3440 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3441 case BFD_RELOC_SPARC_TLS_DTPOFF64:
739f7f82
DM		 3442 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
3443 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
3444 case BFD_RELOC_SPARC_GOTDATA_OP:
252b5132
RH		 3445 code = fixp->fx_r_type;
3446 break;
3447 default:
3448 abort ();
3449 return NULL;
3450 }
3451
3452#if defined (OBJ_ELF) || defined (OBJ_AOUT)
3453 /* If we are generating PIC code, we need to generate a different
3454 set of relocs. */
3455
3456#ifdef OBJ_ELF
3457#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3458#else
3459#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
910600e9
RS		 3460#endif
3461#ifdef TE_VXWORKS
3462#define GOTT_BASE "__GOTT_BASE__"
3463#define GOTT_INDEX "__GOTT_INDEX__"
252b5132
RH		 3464#endif
3465
153b546a
ILT		 3466 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3467
252b5132
RH		 3468 if (sparc_pic_code)
3469 {
3470 switch (code)
3471 {
3472 case BFD_RELOC_32_PCREL_S2:
ae6063d4 3473 if (generic_force_reloc (fixp))
252b5132
RH		 3474 code = BFD_RELOC_SPARC_WPLT30;
3475 break;
3476 case BFD_RELOC_HI22:
910600e9
RS		 3477 code = BFD_RELOC_SPARC_GOT22;
3478 if (fixp->fx_addsy != NULL)
3479 {
3480 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3481 code = BFD_RELOC_SPARC_PC22;
3482#ifdef TE_VXWORKS
3483 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3484 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3485 code = BFD_RELOC_HI22; /* Unchanged. */
3486#endif
3487 }
252b5132
RH		 3488 break;
3489 case BFD_RELOC_LO10:
910600e9
RS		 3490 code = BFD_RELOC_SPARC_GOT10;
3491 if (fixp->fx_addsy != NULL)
3492 {
3493 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3494 code = BFD_RELOC_SPARC_PC10;
3495#ifdef TE_VXWORKS
3496 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3497 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3498 code = BFD_RELOC_LO10; /* Unchanged. */
3499#endif
3500 }
252b5132
RH		 3501 break;
3502 case BFD_RELOC_SPARC13:
3503 code = BFD_RELOC_SPARC_GOT13;
3504 break;
3505 default:
3506 break;
3507 }
3508 }
e0c6ed95 3509#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
252b5132 3510
062cf837
EB		 3511 /* Nothing is aligned in DWARF debugging sections. */
3512 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3513 switch (code)
3514 {
3515 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3516 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3517 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3518 default: break;
3519 }
3520
dabe3bbc
RH		 3521 if (code == BFD_RELOC_SPARC_OLO10)
3522 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3523 else
3524 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH		 3525 if (reloc->howto == 0)
3526 {
3527 as_bad_where (fixp->fx_file, fixp->fx_line,
3528 _("internal error: can't export reloc type %d (`%s')"),
3529 fixp->fx_r_type, bfd_get_reloc_code_name (code));
dabe3bbc
RH		 3530 xfree (reloc);
3531 relocs[0] = NULL;
3532 return relocs;
252b5132
RH		 3533 }
3534
3535 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3536#ifdef OBJ_AOUT
3537
3538 if (reloc->howto->pc_relative == 0
3539 || code == BFD_RELOC_SPARC_PC10
3540 || code == BFD_RELOC_SPARC_PC22)
3541 reloc->addend = fixp->fx_addnumber;
3542 else if (sparc_pic_code
3543 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3544 && fixp->fx_addsy != NULL
3545 && (S_IS_EXTERNAL (fixp->fx_addsy)
3546 || S_IS_WEAK (fixp->fx_addsy))
3547 && S_IS_DEFINED (fixp->fx_addsy)
3548 && ! S_IS_COMMON (fixp->fx_addsy))
3549 reloc->addend = fixp->fx_addnumber;
3550 else
3551 reloc->addend = fixp->fx_offset - reloc->address;
3552
e0c6ed95 3553#else /* elf or coff */
252b5132 3554
bd5e6e7e
JJ		 3555 if (code != BFD_RELOC_32_PCREL_S2
3556 && code != BFD_RELOC_SPARC_WDISP22
3557 && code != BFD_RELOC_SPARC_WDISP16
3558 && code != BFD_RELOC_SPARC_WDISP19
b9734f35
JJ		 3559 && code != BFD_RELOC_SPARC_WPLT30
3560 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3561 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
252b5132 3562 reloc->addend = fixp->fx_addnumber;
49309057 3563 else if (symbol_section_p (fixp->fx_addsy))
252b5132
RH		 3564 reloc->addend = (section->vma
3565 + fixp->fx_addnumber
3566 + md_pcrel_from (fixp));
3567 else
3568 reloc->addend = fixp->fx_offset;
3569#endif
3570
dabe3bbc
RH		 3571 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3572 on the same location. */
3573 if (code == BFD_RELOC_SPARC_OLO10)
3574 {
3575 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3576 relocs[2] = NULL;
3577
3578 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
ab3e48dc
KH		 3579 *reloc->sym_ptr_ptr
3580 = symbol_get_bfdsym (section_symbol (absolute_section));
dabe3bbc
RH		 3581 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3582 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3583 reloc->addend = fixp->tc_fix_data;
3584 }
3585
3586 return relocs;
252b5132
RH		 3587}
3588\f
e0c6ed95 3589/* We have no need to default values of symbols. */
252b5132 3590
252b5132 3591symbolS *
5a49b8ac 3592md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 3593{
3594 return 0;
e0c6ed95
AM		 3595}
3596
3597/* Round up a section size to the appropriate boundary. */
252b5132 3598
252b5132 3599valueT
5a49b8ac 3600md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 3601{
3602#ifndef OBJ_ELF
3603 /* This is not right for ELF; a.out wants it, and COFF will force
3604 the alignment anyways. */
3605 valueT align = ((valueT) 1
3606 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3607 valueT newsize;
e0c6ed95
AM		 3608
3609 /* Turn alignment value into a mask. */
252b5132
RH		 3610 align--;
3611 newsize = (size + align) & ~align;
3612 return newsize;
3613#else
3614 return size;
3615#endif
3616}
3617
3618/* Exactly what point is a PC-relative offset relative TO?
3619 On the sparc, they're relative to the address of the offset, plus
3620 its size. This gets us to the following instruction.
e0c6ed95
AM		 3621 (??? Is this right? FIXME-SOON) */
3622long
5a49b8ac 3623md_pcrel_from (fixS *fixP)
252b5132
RH		 3624{
3625 long ret;
3626
3627 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3628 if (! sparc_pic_code
3629 || fixP->fx_addsy == NULL
49309057 3630 || symbol_section_p (fixP->fx_addsy))
252b5132
RH		 3631 ret += fixP->fx_size;
3632 return ret;
3633}
3634\f
3635/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3636 of two. */
3637
3638static int
5a49b8ac 3639mylog2 (int value)
252b5132
RH		 3640{
3641 int shift;
3642
3643 if (value <= 0)
3644 return -1;
3645
3646 for (shift = 0; (value & 1) == 0; value >>= 1)
3647 ++shift;
3648
3649 return (value == 1) ? shift : -1;
3650}
3651
e0c6ed95 3652/* Sort of like s_lcomm. */
252b5132
RH		 3653
3654#ifndef OBJ_ELF
3655static int max_alignment = 15;
3656#endif
3657
3658static void
5a49b8ac 3659s_reserve (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 3660{
3661 char *name;
3662 char *p;
3663 char c;
3664 int align;
3665 int size;
3666 int temp;
3667 symbolS *symbolP;
3668
3669 name = input_line_pointer;
3670 c = get_symbol_end ();
3671 p = input_line_pointer;
3672 *p = c;
3673 SKIP_WHITESPACE ();
3674
3675 if (*input_line_pointer != ',')
3676 {
3677 as_bad (_("Expected comma after name"));
3678 ignore_rest_of_line ();
3679 return;
3680 }
3681
3682 ++input_line_pointer;
3683
3684 if ((size = get_absolute_expression ()) < 0)
3685 {
3686 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3687 ignore_rest_of_line ();
3688 return;
e0c6ed95 3689 } /* Bad length. */
252b5132
RH		 3690
3691 *p = 0;
3692 symbolP = symbol_find_or_make (name);
3693 *p = c;
3694
3695 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3696 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3697 {
3698 as_bad (_("bad .reserve segment -- expected BSS segment"));
3699 return;
3700 }
3701
3702 if (input_line_pointer[2] == '.')
3703 input_line_pointer += 7;
3704 else
3705 input_line_pointer += 6;
3706 SKIP_WHITESPACE ();
3707
3708 if (*input_line_pointer == ',')
3709 {
3710 ++input_line_pointer;
3711
3712 SKIP_WHITESPACE ();
3713 if (*input_line_pointer == '\n')
3714 {
3715 as_bad (_("missing alignment"));
3716 ignore_rest_of_line ();
3717 return;
3718 }
3719
3720 align = (int) get_absolute_expression ();
3721
3722#ifndef OBJ_ELF
3723 if (align > max_alignment)
3724 {
3725 align = max_alignment;
3726 as_warn (_("alignment too large; assuming %d"), align);
3727 }
3728#endif
3729
3730 if (align < 0)
3731 {
3732 as_bad (_("negative alignment"));
3733 ignore_rest_of_line ();
3734 return;
3735 }
3736
3737 if (align != 0)
3738 {
f17c130b 3739 temp = mylog2 (align);
252b5132
RH		 3740 if (temp < 0)
3741 {
3742 as_bad (_("alignment not a power of 2"));
3743 ignore_rest_of_line ();
3744 return;
3745 }
3746
3747 align = temp;
3748 }
3749
3750 record_alignment (bss_section, align);
3751 }
3752 else
3753 align = 0;
3754
3755 if (!S_IS_DEFINED (symbolP)
3756#ifdef OBJ_AOUT
3757 && S_GET_OTHER (symbolP) == 0
3758 && S_GET_DESC (symbolP) == 0
3759#endif
3760 )
3761 {
3762 if (! need_pass_2)
3763 {
3764 char *pfrag;
3765 segT current_seg = now_seg;
3766 subsegT current_subseg = now_subseg;
3767
e0c6ed95
AM		 3768 /* Switch to bss. */
3769 subseg_set (bss_section, 1);
252b5132
RH		 3770
3771 if (align)
e0c6ed95
AM		 3772 /* Do alignment. */
3773 frag_align (align, 0, 0);
252b5132 3774
e0c6ed95 3775 /* Detach from old frag. */
ab3e48dc 3776 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057 3777 symbol_get_frag (symbolP)->fr_symbol = NULL;
252b5132 3778
49309057 3779 symbol_set_frag (symbolP, frag_now);
e0c6ed95
AM		 3780 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3781 (offsetT) size, (char *) 0);
252b5132
RH		 3782 *pfrag = 0;
3783
3784 S_SET_SEGMENT (symbolP, bss_section);
3785
3786 subseg_set (current_seg, current_subseg);
3787
3788#ifdef OBJ_ELF
3789 S_SET_SIZE (symbolP, size);
3790#endif
3791 }
3792 }
3793 else
3794 {
20203fb9 3795 as_warn (_("Ignoring attempt to re-define symbol %s"),
ab3e48dc 3796 S_GET_NAME (symbolP));
20203fb9 3797 }
252b5132
RH		 3798
3799 demand_empty_rest_of_line ();
3800}
3801
3802static void
5a49b8ac 3803s_common (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 3804{
3805 char *name;
3806 char c;
3807 char *p;
685736be 3808 offsetT temp, size;
252b5132
RH		 3809 symbolS *symbolP;
3810
3811 name = input_line_pointer;
3812 c = get_symbol_end ();
e0c6ed95 3813 /* Just after name is now '\0'. */
252b5132
RH		 3814 p = input_line_pointer;
3815 *p = c;
3816 SKIP_WHITESPACE ();
3817 if (*input_line_pointer != ',')
3818 {
3819 as_bad (_("Expected comma after symbol-name"));
3820 ignore_rest_of_line ();
3821 return;
3822 }
e0c6ed95
AM		 3823
3824 /* Skip ','. */
3825 input_line_pointer++;
3826
252b5132
RH		 3827 if ((temp = get_absolute_expression ()) < 0)
3828 {
685736be
NC		 3829 as_bad (_(".COMMon length (%lu) out of range ignored"),
3830 (unsigned long) temp);
252b5132
RH		 3831 ignore_rest_of_line ();
3832 return;
3833 }
3834 size = temp;
3835 *p = 0;
3836 symbolP = symbol_find_or_make (name);
3837 *p = c;
3838 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3839 {
3840 as_bad (_("Ignoring attempt to re-define symbol"));
3841 ignore_rest_of_line ();
3842 return;
3843 }
3844 if (S_GET_VALUE (symbolP) != 0)
3845 {
3846 if (S_GET_VALUE (symbolP) != (valueT) size)
3847 {
364b6d8b
JJ		 3848 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3849 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
252b5132
RH		 3850 }
3851 }
3852 else
3853 {
3854#ifndef OBJ_ELF
3855 S_SET_VALUE (symbolP, (valueT) size);
3856 S_SET_EXTERNAL (symbolP);
3857#endif
3858 }
7dcc9865 3859 know (symbol_get_frag (symbolP) == &zero_address_frag);
252b5132
RH		 3860 if (*input_line_pointer != ',')
3861 {
3862 as_bad (_("Expected comma after common length"));
3863 ignore_rest_of_line ();
3864 return;
3865 }
3866 input_line_pointer++;
3867 SKIP_WHITESPACE ();
3868 if (*input_line_pointer != '"')
3869 {
3870 temp = get_absolute_expression ();
3871
3872#ifndef OBJ_ELF
3873 if (temp > max_alignment)
3874 {
3875 temp = max_alignment;
f17c130b 3876 as_warn (_("alignment too large; assuming %ld"), (long) temp);
252b5132
RH		 3877 }
3878#endif
3879
3880 if (temp < 0)
3881 {
3882 as_bad (_("negative alignment"));
3883 ignore_rest_of_line ();
3884 return;
3885 }
3886
3887#ifdef OBJ_ELF
49309057 3888 if (symbol_get_obj (symbolP)->local)
252b5132
RH		 3889 {
3890 segT old_sec;
3891 int old_subsec;
252b5132
RH		 3892 int align;
3893
3894 old_sec = now_seg;
3895 old_subsec = now_subseg;
3896
3897 if (temp == 0)
3898 align = 0;
3899 else
f17c130b 3900 align = mylog2 (temp);
252b5132
RH		 3901
3902 if (align < 0)
3903 {
3904 as_bad (_("alignment not a power of 2"));
3905 ignore_rest_of_line ();
3906 return;
3907 }
3908
3909 record_alignment (bss_section, align);
3910 subseg_set (bss_section, 0);
3911 if (align)
3912 frag_align (align, 0, 0);
3913 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057
ILT		 3914 symbol_get_frag (symbolP)->fr_symbol = 0;
3915 symbol_set_frag (symbolP, frag_now);
252b5132
RH		 3916 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3917 (offsetT) size, (char *) 0);
3918 *p = 0;
3919 S_SET_SEGMENT (symbolP, bss_section);
3920 S_CLEAR_EXTERNAL (symbolP);
3921 S_SET_SIZE (symbolP, size);
3922 subseg_set (old_sec, old_subsec);
3923 }
3924 else
e0c6ed95 3925#endif /* OBJ_ELF */
252b5132
RH		 3926 {
3927 allocate_common:
3928 S_SET_VALUE (symbolP, (valueT) size);
3929#ifdef OBJ_ELF
3930 S_SET_ALIGN (symbolP, temp);
3931 S_SET_SIZE (symbolP, size);
3932#endif
3933 S_SET_EXTERNAL (symbolP);
3934 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3935 }
3936 }
3937 else
3938 {
3939 input_line_pointer++;
3940 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3941 if (*input_line_pointer == '.')
3942 input_line_pointer++;
3943 /* @@ Some say data, some say bss. */
3944 if (strncmp (input_line_pointer, "bss\"", 4)
3945 && strncmp (input_line_pointer, "data\"", 5))
3946 {
3947 while (*--input_line_pointer != '"')
3948 ;
3949 input_line_pointer--;
3950 goto bad_common_segment;
3951 }
3952 while (*input_line_pointer++ != '"')
3953 ;
3954 goto allocate_common;
3955 }
3956
49309057 3957 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
252b5132
RH		 3958
3959 demand_empty_rest_of_line ();
3960 return;
3961
3962 {
3963 bad_common_segment:
3964 p = input_line_pointer;
3965 while (*p && *p != '\n')
3966 p++;
3967 c = *p;
3968 *p = '\0';
3969 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3970 *p = c;
3971 input_line_pointer = p;
3972 ignore_rest_of_line ();
3973 return;
3974 }
3975}
3976
67c1ffbe 3977/* Handle the .empty pseudo-op. This suppresses the warnings about
252b5132
RH		 3978 invalid delay slot usage. */
3979
3980static void
5a49b8ac 3981s_empty (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 3982{
3983 /* The easy way to implement is to just forget about the last
3984 instruction. */
3985 last_insn = NULL;
3986}
3987
3988static void
5a49b8ac 3989s_seg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 3990{
3991
3992 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3993 {
3994 input_line_pointer += 6;
3995 s_text (0);
3996 return;
3997 }
3998 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3999 {
4000 input_line_pointer += 6;
4001 s_data (0);
4002 return;
4003 }
4004 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4005 {
4006 input_line_pointer += 7;
4007 s_data1 ();
4008 return;
4009 }
4010 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4011 {
4012 input_line_pointer += 5;
4013 /* We only support 2 segments -- text and data -- for now, so
4014 things in the "bss segment" will have to go into data for now.
e0c6ed95
AM		 4015 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4016 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
252b5132
RH		 4017 return;
4018 }
4019 as_bad (_("Unknown segment type"));
4020 demand_empty_rest_of_line ();
4021}
4022
4023static void
5a49b8ac 4024s_data1 (void)
252b5132
RH		 4025{
4026 subseg_set (data_section, 1);
4027 demand_empty_rest_of_line ();
4028}
4029
4030static void
5a49b8ac 4031s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 4032{
4033 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4034 {
4035 ++input_line_pointer;
4036 }
4037 ++input_line_pointer;
4038}
4039
4040/* This static variable is set by s_uacons to tell sparc_cons_align
67c1ffbe 4041 that the expression does not need to be aligned. */
252b5132
RH		 4042
4043static int sparc_no_align_cons = 0;
4044
bd5e6e7e
JJ		 4045/* This static variable is set by sparc_cons to emit requested types
4046 of relocations in cons_fix_new_sparc. */
4047
4048static const char *sparc_cons_special_reloc;
4049
252b5132
RH		 4050/* This handles the unaligned space allocation pseudo-ops, such as
4051 .uaword. .uaword is just like .word, but the value does not need
4052 to be aligned. */
4053
4054static void
5a49b8ac 4055s_uacons (int bytes)
252b5132
RH		 4056{
4057 /* Tell sparc_cons_align not to align this value. */
4058 sparc_no_align_cons = 1;
4059 cons (bytes);
4ffadb11 4060 sparc_no_align_cons = 0;
252b5132
RH		 4061}
4062
cf9a1301
RH		 4063/* This handles the native word allocation pseudo-op .nword.
4064 For sparc_arch_size 32 it is equivalent to .word, for
4065 sparc_arch_size 64 it is equivalent to .xword. */
4066
4067static void
5a49b8ac 4068s_ncons (int bytes ATTRIBUTE_UNUSED)
cf9a1301
RH		 4069{
4070 cons (sparc_arch_size == 32 ? 4 : 8);
4071}
4072
6d8809aa
RH		 4073#ifdef OBJ_ELF
4074/* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4075 global register.
4076 The syntax is:
e0c6ed95 4077
6d8809aa 4078 .register %g[2367],{#scratch|symbolname|#ignore}
e0c6ed95 4079*/
6d8809aa
RH		 4080
4081static void
5a49b8ac 4082s_register (int ignore ATTRIBUTE_UNUSED)
6d8809aa
RH		 4083{
4084 char c;
4085 int reg;
4086 int flags;
4087 const char *regname;
4088
4089 if (input_line_pointer[0] != '%'
4090 || input_line_pointer[1] != 'g'
4091 || ((input_line_pointer[2] & ~1) != '2'
4092 && (input_line_pointer[2] & ~1) != '6')
4093 || input_line_pointer[3] != ',')
4094 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4095 reg = input_line_pointer[2] - '0';
4096 input_line_pointer += 4;
4097
4098 if (*input_line_pointer == '#')
4099 {
4100 ++input_line_pointer;
4101 regname = input_line_pointer;
4102 c = get_symbol_end ();
4103 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4104 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
ab3e48dc 4105 if (regname[0] == 'i')
6d8809aa
RH		 4106 regname = NULL;
4107 else
4108 regname = "";
4109 }
4110 else
4111 {
4112 regname = input_line_pointer;
4113 c = get_symbol_end ();
4114 }
4115 if (sparc_arch_size == 64)
4116 {
e0c6ed95 4117 if (globals[reg])
6d8809aa 4118 {
e0c6ed95
AM		 4119 if ((regname && globals[reg] != (symbolS *) 1
4120 && strcmp (S_GET_NAME (globals[reg]), regname))
4121 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
6d8809aa
RH		 4122 as_bad (_("redefinition of global register"));
4123 }
4124 else
4125 {
4126 if (regname == NULL)
e0c6ed95 4127 globals[reg] = (symbolS *) 1;
6d8809aa
RH		 4128 else
4129 {
4130 if (*regname)
4131 {
4132 if (symbol_find (regname))
4133 as_bad (_("Register symbol %s already defined."),
4134 regname);
4135 }
e0c6ed95
AM		 4136 globals[reg] = symbol_make (regname);
4137 flags = symbol_get_bfdsym (globals[reg])->flags;
6d8809aa
RH		 4138 if (! *regname)
4139 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4140 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4141 flags |= BSF_GLOBAL;
e0c6ed95
AM		 4142 symbol_get_bfdsym (globals[reg])->flags = flags;
4143 S_SET_VALUE (globals[reg], (valueT) reg);
4144 S_SET_ALIGN (globals[reg], reg);
4145 S_SET_SIZE (globals[reg], 0);
6d8809aa
RH		 4146 /* Although we actually want undefined_section here,
4147 we have to use absolute_section, because otherwise
4148 generic as code will make it a COM section.
4149 We fix this up in sparc_adjust_symtab. */
e0c6ed95
AM		 4150 S_SET_SEGMENT (globals[reg], absolute_section);
4151 S_SET_OTHER (globals[reg], 0);
4152 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 4153 ->internal_elf_sym.st_info =
4154 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
e0c6ed95 4155 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 4156 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4157 }
4158 }
4159 }
4160
4161 *input_line_pointer = c;
4162
4163 demand_empty_rest_of_line ();
4164}
4165
4166/* Adjust the symbol table. We set undefined sections for STT_REGISTER
4167 symbols which need it. */
e0c6ed95 4168
6d8809aa 4169void
5a49b8ac 4170sparc_adjust_symtab (void)
6d8809aa
RH		 4171{
4172 symbolS *sym;
e0c6ed95 4173
6d8809aa
RH		 4174 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4175 {
4176 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4177 ->internal_elf_sym.st_info) != STT_REGISTER)
4178 continue;
4179
4180 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4181 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4182 continue;
4183
4184 S_SET_SEGMENT (sym, undefined_section);
4185 }
4186}
4187#endif
4188
252b5132
RH		 4189/* If the --enforce-aligned-data option is used, we require .word,
4190 et. al., to be aligned correctly. We do it by setting up an
4191 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4192 no unexpected alignment was introduced.
4193
4194 The SunOS and Solaris native assemblers enforce aligned data by
4195 default. We don't want to do that, because gcc can deliberately
4196 generate misaligned data if the packed attribute is used. Instead,
4197 we permit misaligned data by default, and permit the user to set an
4198 option to check for it. */
4199
4200void
5a49b8ac 4201sparc_cons_align (int nbytes)
252b5132
RH		 4202{
4203 int nalign;
252b5132
RH		 4204
4205 /* Only do this if we are enforcing aligned data. */
4206 if (! enforce_aligned_data)
4207 return;
4208
0f2712ed 4209 /* Don't align if this is an unaligned pseudo-op. */
252b5132 4210 if (sparc_no_align_cons)
0f2712ed 4211 return;
252b5132 4212
f17c130b 4213 nalign = mylog2 (nbytes);
252b5132
RH		 4214 if (nalign == 0)
4215 return;
4216
9c2799c2 4217 gas_assert (nalign > 0);
252b5132
RH		 4218
4219 if (now_seg == absolute_section)
4220 {
4221 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4222 as_bad (_("misaligned data"));
4223 return;
4224 }
4225
87975d2a
AM		 4226 frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4227 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
252b5132
RH		 4228
4229 record_alignment (now_seg, nalign);
4230}
4231
0a9ef439 4232/* This is called from HANDLE_ALIGN in tc-sparc.h. */
252b5132
RH		 4233
4234void
5a49b8ac 4235sparc_handle_align (fragS *fragp)
252b5132 4236{
0a9ef439
RH		 4237 int count, fix;
4238 char *p;
4239
4240 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
bfb32b52 4241
0a9ef439 4242 switch (fragp->fr_type)
252b5132 4243 {
0a9ef439
RH		 4244 case rs_align_test:
4245 if (count != 0)
4246 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4247 break;
e0c6ed95 4248
0a9ef439
RH		 4249 case rs_align_code:
4250 p = fragp->fr_literal + fragp->fr_fix;
4251 fix = 0;
e0c6ed95 4252
0a9ef439
RH		 4253 if (count & 3)
4254 {
4255 fix = count & 3;
4256 memset (p, 0, fix);
4257 p += fix;
4258 count -= fix;
4259 }
e0c6ed95 4260
0a9ef439
RH		 4261 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4262 {
4263 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4264 if (INSN_BIG_ENDIAN)
4265 number_to_chars_bigendian (p, wval, 4);
4266 else
4267 number_to_chars_littleendian (p, wval, 4);
4268 p += 4;
4269 count -= 4;
4270 fix += 4;
e0c6ed95 4271 }
0a9ef439
RH		 4272
4273 if (INSN_BIG_ENDIAN)
4274 number_to_chars_bigendian (p, 0x01000000, 4);
4275 else
4276 number_to_chars_littleendian (p, 0x01000000, 4);
4277
4278 fragp->fr_fix += fix;
4279 fragp->fr_var = 4;
4280 break;
4281
4282 default:
4283 break;
252b5132
RH		 4284 }
4285}
4286
4287#ifdef OBJ_ELF
4288/* Some special processing for a Sparc ELF file. */
4289
4290void
5a49b8ac 4291sparc_elf_final_processing (void)
252b5132
RH		 4292{
4293 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4294 sort of BFD interface for this. */
4295 if (sparc_arch_size == 64)
4296 {
4297 switch (sparc_memory_model)
4298 {
4299 case MM_RMO:
4300 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4301 break;
4302 case MM_PSO:
4303 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4304 break;
4305 default:
4306 break;
4307 }
4308 }
4309 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4310 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4311 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4312 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
19f7b010
JJ		 4313 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4314 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
252b5132 4315}
bd5e6e7e
JJ		 4316
4317void
5a49b8ac 4318sparc_cons (expressionS *exp, int size)
bd5e6e7e
JJ		 4319{
4320 char *save;
4321
4322 SKIP_WHITESPACE ();
4323 sparc_cons_special_reloc = NULL;
4324 save = input_line_pointer;
4325 if (input_line_pointer[0] == '%'
4326 && input_line_pointer[1] == 'r'
4327 && input_line_pointer[2] == '_')
4328 {
4329 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4330 {
4331 input_line_pointer += 7;
4332 sparc_cons_special_reloc = "disp";
4333 }
4334 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4335 {
4336 if (size != 4 && size != 8)
4337 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4338 else
4339 {
4340 input_line_pointer += 6;
4341 sparc_cons_special_reloc = "plt";
4342 }
4343 }
b9734f35
JJ		 4344 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4345 {
4346 if (size != 4 && size != 8)
4347 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4348 else
4349 {
4350 input_line_pointer += 13;
4351 sparc_cons_special_reloc = "tls_dtpoff";
4352 }
4353 }
bd5e6e7e
JJ		 4354 if (sparc_cons_special_reloc)
4355 {
4356 int bad = 0;
4357
4358 switch (size)
4359 {
4360 case 1:
4361 if (*input_line_pointer != '8')
4362 bad = 1;
4363 input_line_pointer--;
4364 break;
4365 case 2:
4366 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4367 bad = 1;
4368 break;
4369 case 4:
4370 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4371 bad = 1;
4372 break;
4373 case 8:
4374 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4375 bad = 1;
4376 break;
4377 default:
4378 bad = 1;
4379 break;
4380 }
4381
4382 if (bad)
4383 {
4384 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4385 sparc_cons_special_reloc, size * 8, size);
4386 }
4387 else
4388 {
4389 input_line_pointer += 2;
4390 if (*input_line_pointer != '(')
4391 {
4392 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4393 sparc_cons_special_reloc, size * 8);
4394 bad = 1;
4395 }
4396 }
4397
4398 if (bad)
4399 {
4400 input_line_pointer = save;
4401 sparc_cons_special_reloc = NULL;
4402 }
4403 else
4404 {
4405 int c;
4406 char *end = ++input_line_pointer;
4407 int npar = 0;
4408
4409 while (! is_end_of_line[(c = *end)])
4410 {
4411 if (c == '(')
4412 npar++;
4413 else if (c == ')')
4414 {
4415 if (!npar)
4416 break;
4417 npar--;
4418 }
4419 end++;
4420 }
4421
4422 if (c != ')')
4423 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4424 sparc_cons_special_reloc, size * 8);
4425 else
4426 {
4427 *end = '\0';
4428 expression (exp);
4429 *end = c;
4430 if (input_line_pointer != end)
4431 {
4432 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4433 sparc_cons_special_reloc, size * 8);
4434 }
4435 else
4436 {
4437 input_line_pointer++;
4438 SKIP_WHITESPACE ();
4439 c = *input_line_pointer;
4440 if (! is_end_of_line[c] && c != ',')
4441 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4442 sparc_cons_special_reloc, size * 8);
4443 }
4444 }
4445 }
4446 }
4447 }
4448 if (sparc_cons_special_reloc == NULL)
4449 expression (exp);
4450}
4451
252b5132
RH		 4452#endif
4453
4454/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4455 reloc for a cons. We could use the definition there, except that
4456 we want to handle little endian relocs specially. */
4457
4458void
5a49b8ac
AM		 4459cons_fix_new_sparc (fragS *frag,
4460 int where,
4461 unsigned int nbytes,
4462 expressionS *exp)
252b5132
RH		 4463{
4464 bfd_reloc_code_real_type r;
4465
4466 r = (nbytes == 1 ? BFD_RELOC_8 :
4467 (nbytes == 2 ? BFD_RELOC_16 :
4468 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4469
0f2712ed
NC		 4470 if (target_little_endian_data
4471 && nbytes == 4
e0c6ed95 4472 && now_seg->flags & SEC_ALLOC)
252b5132 4473 r = BFD_RELOC_SPARC_REV32;
0f2712ed 4474
bd5e6e7e
JJ		 4475 if (sparc_cons_special_reloc)
4476 {
4477 if (*sparc_cons_special_reloc == 'd')
4478 switch (nbytes)
4479 {
4480 case 1: r = BFD_RELOC_8_PCREL; break;
4481 case 2: r = BFD_RELOC_16_PCREL; break;
4482 case 4: r = BFD_RELOC_32_PCREL; break;
4483 case 8: r = BFD_RELOC_64_PCREL; break;
4484 default: abort ();
4485 }
b9734f35 4486 else if (*sparc_cons_special_reloc == 'p')
bd5e6e7e
JJ		 4487 switch (nbytes)
4488 {
4489 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4490 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4491 }
b9734f35
JJ		 4492 else
4493 switch (nbytes)
4494 {
4495 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4496 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4497 }
bd5e6e7e
JJ		 4498 }
4499 else if (sparc_no_align_cons)
0f2712ed
NC		 4500 {
4501 switch (nbytes)
4502 {
4503 case 2: r = BFD_RELOC_SPARC_UA16; break;
4504 case 4: r = BFD_RELOC_SPARC_UA32; break;
4505 case 8: r = BFD_RELOC_SPARC_UA64; break;
4506 default: abort ();
4507 }
4ffadb11 4508 }
0f2712ed 4509
252b5132 4510 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
364b6d8b
JJ		 4511 sparc_cons_special_reloc = NULL;
4512}
4513
4514void
5a49b8ac 4515sparc_cfi_frame_initial_instructions (void)
364b6d8b
JJ		 4516{
4517 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4518}
4519
4520int
1df69f4f 4521sparc_regname_to_dw2regnum (char *regname)
364b6d8b
JJ		 4522{
4523 char *p, *q;
4524
4525 if (!regname[0])
4526 return -1;
4527
4528 q = "goli";
4529 p = strchr (q, regname[0]);
4530 if (p)
4531 {
4532 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4533 return -1;
4534 return (p - q) * 8 + regname[1] - '0';
4535 }
4536 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4537 return 14;
4538 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4539 return 30;
4540 if (regname[0] == 'f' || regname[0] == 'r')
4541 {
4542 unsigned int regnum;
4543
4544 regnum = strtoul (regname + 1, &q, 10);
4545 if (p == q || *q)
4546 return -1;
4547 if (regnum >= ((regname[0] == 'f'
4548 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4549 ? 64 : 32))
4550 return -1;
4551 if (regname[0] == 'f')
4552 {
4553 regnum += 32;
4554 if (regnum >= 64 && (regnum & 1))
4555 return -1;
4556 }
4557 return regnum;
4558 }
4559 return -1;
4560}
4561
4562void
4563sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4564{
4565 sparc_cons_special_reloc = "disp";
4566 sparc_no_align_cons = 1;
4567 emit_expr (exp, nbytes);
4568 sparc_no_align_cons = 0;
4569 sparc_cons_special_reloc = NULL;
252b5132 4570}
GDB Binutils - Deliverables
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