Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-sparc.c -- Assemble for the SPARC |
f7e42eb4 | 2 | Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
9e8c70f9 DM |
3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, |
4 | 2011 | |
e0c6ed95 | 5 | Free Software Foundation, Inc. |
252b5132 RH |
6 | This file is part of GAS, the GNU Assembler. |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public | |
19 | License along with GAS; see the file COPYING. If not, write | |
4b4da160 NC |
20 | to the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 22 | |
252b5132 | 23 | #include "as.h" |
3882b010 | 24 | #include "safe-ctype.h" |
252b5132 RH |
25 | #include "subsegs.h" |
26 | ||
27 | #include "opcode/sparc.h" | |
364b6d8b | 28 | #include "dw2gencfi.h" |
252b5132 RH |
29 | |
30 | #ifdef OBJ_ELF | |
31 | #include "elf/sparc.h" | |
732d96b6 | 32 | #include "dwarf2dbg.h" |
252b5132 RH |
33 | #endif |
34 | ||
6c1b24e4 AO |
35 | /* Some ancient Sun C compilers would not take such hex constants as |
36 | unsigned, and would end up sign-extending them to form an offsetT, | |
37 | so use these constants instead. */ | |
38 | #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) | |
39 | #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) | |
40 | ||
5a49b8ac AM |
41 | static int sparc_ip (char *, const struct sparc_opcode **); |
42 | static int parse_keyword_arg (int (*) (const char *), char **, int *); | |
43 | static int parse_const_expr_arg (char **, int *); | |
44 | static int get_expression (char *); | |
252b5132 RH |
45 | |
46 | /* Default architecture. */ | |
47 | /* ??? The default value should be V8, but sparclite support was added | |
48 | by making it the default. GCC now passes -Asparclite, so maybe sometime in | |
49 | the future we can set this to V8. */ | |
50 | #ifndef DEFAULT_ARCH | |
51 | #define DEFAULT_ARCH "sparclite" | |
52 | #endif | |
53 | static char *default_arch = DEFAULT_ARCH; | |
54 | ||
55 | /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' | |
56 | have been set. */ | |
57 | static int default_init_p; | |
58 | ||
59 | /* Current architecture. We don't bump up unless necessary. */ | |
60 | static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; | |
61 | ||
62 | /* The maximum architecture level we can bump up to. | |
63 | In a 32 bit environment, don't allow bumping up to v9 by default. | |
64 | The native assembler works this way. The user is required to pass | |
65 | an explicit argument before we'll create v9 object files. However, if | |
66 | we don't see any v9 insns, a v8plus object file is not created. */ | |
67 | static enum sparc_opcode_arch_val max_architecture; | |
68 | ||
69 | /* Either 32 or 64, selects file format. */ | |
70 | static int sparc_arch_size; | |
71 | /* Initial (default) value, recorded separately in case a user option | |
72 | changes the value before md_show_usage is called. */ | |
73 | static int default_arch_size; | |
74 | ||
75 | #ifdef OBJ_ELF | |
76 | /* The currently selected v9 memory model. Currently only used for | |
77 | ELF. */ | |
78 | static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; | |
9e8c70f9 DM |
79 | |
80 | #ifndef TE_SOLARIS | |
81 | /* Bitmask of instruction types seen so far, used to populate the | |
82 | GNU attributes section with hwcap information. */ | |
83 | static int hwcap_seen; | |
84 | #endif | |
252b5132 RH |
85 | #endif |
86 | ||
4bafe00e DM |
87 | static int hwcap_allowed; |
88 | ||
252b5132 RH |
89 | static int architecture_requested; |
90 | static int warn_on_bump; | |
91 | ||
92 | /* If warn_on_bump and the needed architecture is higher than this | |
93 | architecture, issue a warning. */ | |
94 | static enum sparc_opcode_arch_val warn_after_architecture; | |
95 | ||
6d8809aa RH |
96 | /* Non-zero if as should generate error if an undeclared g[23] register |
97 | has been used in -64. */ | |
98 | static int no_undeclared_regs; | |
99 | ||
6faf3d66 JJ |
100 | /* Non-zero if we should try to relax jumps and calls. */ |
101 | static int sparc_relax; | |
102 | ||
252b5132 RH |
103 | /* Non-zero if we are generating PIC code. */ |
104 | int sparc_pic_code; | |
105 | ||
106 | /* Non-zero if we should give an error when misaligned data is seen. */ | |
107 | static int enforce_aligned_data; | |
108 | ||
109 | extern int target_big_endian; | |
110 | ||
111 | static int target_little_endian_data; | |
112 | ||
6d8809aa RH |
113 | /* Symbols for global registers on v9. */ |
114 | static symbolS *globals[8]; | |
115 | ||
364b6d8b JJ |
116 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ |
117 | int sparc_cie_data_alignment; | |
118 | ||
252b5132 RH |
119 | /* V9 and 86x have big and little endian data, but instructions are always big |
120 | endian. The sparclet has bi-endian support but both data and insns have | |
121 | the same endianness. Global `target_big_endian' is used for data. | |
122 | The following macro is used for instructions. */ | |
123 | #ifndef INSN_BIG_ENDIAN | |
124 | #define INSN_BIG_ENDIAN (target_big_endian \ | |
125 | || default_arch_type == sparc86x \ | |
126 | || SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
127 | #endif | |
128 | ||
e0c6ed95 | 129 | /* Handle of the OPCODE hash table. */ |
252b5132 RH |
130 | static struct hash_control *op_hash; |
131 | ||
5a49b8ac AM |
132 | static void s_data1 (void); |
133 | static void s_seg (int); | |
134 | static void s_proc (int); | |
135 | static void s_reserve (int); | |
136 | static void s_common (int); | |
137 | static void s_empty (int); | |
138 | static void s_uacons (int); | |
139 | static void s_ncons (int); | |
a7982600 | 140 | #ifdef OBJ_ELF |
5a49b8ac | 141 | static void s_register (int); |
a7982600 | 142 | #endif |
252b5132 RH |
143 | |
144 | const pseudo_typeS md_pseudo_table[] = | |
145 | { | |
e0c6ed95 | 146 | {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ |
252b5132 RH |
147 | {"common", s_common, 0}, |
148 | {"empty", s_empty, 0}, | |
149 | {"global", s_globl, 0}, | |
150 | {"half", cons, 2}, | |
cf9a1301 | 151 | {"nword", s_ncons, 0}, |
252b5132 RH |
152 | {"optim", s_ignore, 0}, |
153 | {"proc", s_proc, 0}, | |
154 | {"reserve", s_reserve, 0}, | |
155 | {"seg", s_seg, 0}, | |
156 | {"skip", s_space, 0}, | |
157 | {"word", cons, 4}, | |
158 | {"xword", cons, 8}, | |
159 | {"uahalf", s_uacons, 2}, | |
160 | {"uaword", s_uacons, 4}, | |
161 | {"uaxword", s_uacons, 8}, | |
162 | #ifdef OBJ_ELF | |
e0c6ed95 | 163 | /* These are specific to sparc/svr4. */ |
252b5132 RH |
164 | {"2byte", s_uacons, 2}, |
165 | {"4byte", s_uacons, 4}, | |
166 | {"8byte", s_uacons, 8}, | |
6d8809aa | 167 | {"register", s_register, 0}, |
252b5132 RH |
168 | #endif |
169 | {NULL, 0, 0}, | |
170 | }; | |
171 | ||
252b5132 | 172 | /* This array holds the chars that always start a comment. If the |
e0c6ed95 AM |
173 | pre-processor is disabled, these aren't very useful. */ |
174 | const char comment_chars[] = "!"; /* JF removed '|' from | |
175 | comment_chars. */ | |
252b5132 RH |
176 | |
177 | /* This array holds the chars that only start a comment at the beginning of | |
178 | a line. If the line seems to have the form '# 123 filename' | |
e0c6ed95 | 179 | .line and .file directives will appear in the pre-processed output. */ |
252b5132 RH |
180 | /* Note that input_file.c hand checks for '#' at the beginning of the |
181 | first line of the input file. This is because the compiler outputs | |
e0c6ed95 | 182 | #NO_APP at the beginning of its output. */ |
252b5132 | 183 | /* Also note that comments started like this one will always |
e0c6ed95 | 184 | work if '/' isn't otherwise defined. */ |
252b5132 RH |
185 | const char line_comment_chars[] = "#"; |
186 | ||
63a0b638 | 187 | const char line_separator_chars[] = ";"; |
252b5132 | 188 | |
e0c6ed95 AM |
189 | /* Chars that can be used to separate mant from exp in floating point |
190 | nums. */ | |
252b5132 RH |
191 | const char EXP_CHARS[] = "eE"; |
192 | ||
e0c6ed95 AM |
193 | /* Chars that mean this number is a floating point constant. |
194 | As in 0f12.456 | |
195 | or 0d1.2345e12 */ | |
252b5132 RH |
196 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
197 | ||
198 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
199 | changed in read.c. Ideally it shouldn't have to know about it at all, | |
200 | but nothing is ideal around here. */ | |
201 | ||
74b56d1f | 202 | #define isoctal(c) ((unsigned) ((c) - '0') < 8) |
252b5132 RH |
203 | |
204 | struct sparc_it | |
205 | { | |
206 | char *error; | |
207 | unsigned long opcode; | |
208 | struct nlist *nlistp; | |
209 | expressionS exp; | |
cf9a1301 | 210 | expressionS exp2; |
252b5132 RH |
211 | int pcrel; |
212 | bfd_reloc_code_real_type reloc; | |
213 | }; | |
214 | ||
215 | struct sparc_it the_insn, set_insn; | |
216 | ||
5a49b8ac | 217 | static void output_insn (const struct sparc_opcode *, struct sparc_it *); |
252b5132 RH |
218 | \f |
219 | /* Table of arguments to -A. | |
220 | The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect | |
221 | for this use. That table is for opcodes only. This table is for opcodes | |
222 | and file formats. */ | |
223 | ||
224 | enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, | |
19f7b010 | 225 | v8plusa, v9, v9a, v9b, v9_64}; |
252b5132 RH |
226 | |
227 | static struct sparc_arch { | |
228 | char *name; | |
229 | char *opcode_arch; | |
230 | enum sparc_arch_types arch_type; | |
231 | /* Default word size, as specified during configuration. | |
232 | A value of zero means can't be used to specify default architecture. */ | |
233 | int default_arch_size; | |
234 | /* Allowable arg to -A? */ | |
235 | int user_option_p; | |
4bafe00e | 236 | int hwcap_allowed; |
252b5132 | 237 | } sparc_arch_table[] = { |
4bafe00e DM |
238 | { "v6", "v6", v6, 0, 1, 0 }, |
239 | { "v7", "v7", v7, 0, 1, 0 }, | |
ec668d69 DM |
240 | { "v8", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD }, |
241 | { "v8a", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD }, | |
242 | { "sparc", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS }, | |
243 | { "sparcvis", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS }, | |
244 | { "sparcvis2", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 }, | |
245 | { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF }, | |
246 | { "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA }, | |
247 | { "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC }, | |
58004e23 | 248 | { "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE }, |
ec668d69 DM |
249 | { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU }, |
250 | { "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD }, | |
251 | { "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD }, | |
252 | { "sparc86x", "sparclite", sparc86x, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD }, | |
253 | { "v8plus", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS }, | |
254 | { "v8plusa", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS }, | |
255 | { "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 }, | |
256 | { "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT }, | |
257 | { "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC }, | |
58004e23 DM |
258 | { "v8pluse", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE }, |
259 | { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE }, | |
ec668d69 DM |
260 | { "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC }, |
261 | { "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS }, | |
262 | { "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 }, | |
263 | { "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT }, | |
264 | { "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC }, | |
58004e23 DM |
265 | { "v9e", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE }, |
266 | { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE }, | |
252b5132 RH |
267 | /* This exists to allow configure.in/Makefile.in to pass one |
268 | value to specify both the default machine and default word size. */ | |
ec668d69 | 269 | { "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC }, |
4bafe00e | 270 | { NULL, NULL, v8, 0, 0, 0 } |
252b5132 RH |
271 | }; |
272 | ||
273 | /* Variant of default_arch */ | |
274 | static enum sparc_arch_types default_arch_type; | |
275 | ||
276 | static struct sparc_arch * | |
5a49b8ac | 277 | lookup_arch (char *name) |
252b5132 RH |
278 | { |
279 | struct sparc_arch *sa; | |
280 | ||
281 | for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) | |
282 | if (strcmp (sa->name, name) == 0) | |
283 | break; | |
284 | if (sa->name == NULL) | |
285 | return NULL; | |
286 | return sa; | |
287 | } | |
288 | ||
289 | /* Initialize the default opcode arch and word size from the default | |
290 | architecture name. */ | |
291 | ||
292 | static void | |
5a49b8ac | 293 | init_default_arch (void) |
252b5132 RH |
294 | { |
295 | struct sparc_arch *sa = lookup_arch (default_arch); | |
296 | ||
297 | if (sa == NULL | |
298 | || sa->default_arch_size == 0) | |
299 | as_fatal (_("Invalid default architecture, broken assembler.")); | |
300 | ||
301 | max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); | |
302 | if (max_architecture == SPARC_OPCODE_ARCH_BAD) | |
303 | as_fatal (_("Bad opcode table, broken assembler.")); | |
304 | default_arch_size = sparc_arch_size = sa->default_arch_size; | |
305 | default_init_p = 1; | |
306 | default_arch_type = sa->arch_type; | |
307 | } | |
308 | ||
309 | /* Called by TARGET_FORMAT. */ | |
310 | ||
311 | const char * | |
5a49b8ac | 312 | sparc_target_format (void) |
252b5132 RH |
313 | { |
314 | /* We don't get a chance to initialize anything before we're called, | |
315 | so handle that now. */ | |
316 | if (! default_init_p) | |
317 | init_default_arch (); | |
318 | ||
319 | #ifdef OBJ_AOUT | |
320 | #ifdef TE_NetBSD | |
321 | return "a.out-sparc-netbsd"; | |
322 | #else | |
323 | #ifdef TE_SPARCAOUT | |
324 | if (target_big_endian) | |
325 | return "a.out-sunos-big"; | |
326 | else if (default_arch_type == sparc86x && target_little_endian_data) | |
327 | return "a.out-sunos-big"; | |
ab3e48dc KH |
328 | else |
329 | return "a.out-sparc-little"; | |
252b5132 RH |
330 | #else |
331 | return "a.out-sunos-big"; | |
332 | #endif | |
333 | #endif | |
334 | #endif | |
335 | ||
336 | #ifdef OBJ_BOUT | |
337 | return "b.out.big"; | |
338 | #endif | |
339 | ||
340 | #ifdef OBJ_COFF | |
341 | #ifdef TE_LYNX | |
342 | return "coff-sparc-lynx"; | |
343 | #else | |
344 | return "coff-sparc"; | |
345 | #endif | |
346 | #endif | |
347 | ||
910600e9 RS |
348 | #ifdef TE_VXWORKS |
349 | return "elf32-sparc-vxworks"; | |
350 | #endif | |
351 | ||
252b5132 | 352 | #ifdef OBJ_ELF |
71a75f6f | 353 | return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; |
252b5132 RH |
354 | #endif |
355 | ||
356 | abort (); | |
357 | } | |
358 | \f | |
e0c6ed95 | 359 | /* md_parse_option |
252b5132 RH |
360 | * Invocation line includes a switch not recognized by the base assembler. |
361 | * See if it's a processor-specific option. These are: | |
362 | * | |
363 | * -bump | |
364 | * Warn on architecture bumps. See also -A. | |
365 | * | |
366 | * -Av6, -Av7, -Av8, -Asparclite, -Asparclet | |
367 | * Standard 32 bit architectures. | |
19f7b010 | 368 | * -Av9, -Av9a, -Av9b |
252b5132 RH |
369 | * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). |
370 | * This used to only mean 64 bits, but properly specifying it | |
371 | * complicated gcc's ASM_SPECs, so now opcode selection is | |
372 | * specified orthogonally to word size (except when specifying | |
373 | * the default, but that is an internal implementation detail). | |
19f7b010 JJ |
374 | * -Av8plus, -Av8plusa, -Av8plusb |
375 | * Same as -Av9{,a,b}. | |
376 | * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb | |
377 | * Same as -Av8plus{,a,b} -32, for compatibility with Sun's | |
378 | * assembler. | |
379 | * -xarch=v9, -xarch=v9a, -xarch=v9b | |
380 | * Same as -Av9{,a,b} -64, for compatibility with Sun's | |
c2158c24 | 381 | * assembler. |
252b5132 RH |
382 | * |
383 | * Select the architecture and possibly the file format. | |
384 | * Instructions or features not supported by the selected | |
385 | * architecture cause fatal errors. | |
386 | * | |
387 | * The default is to start at v6, and bump the architecture up | |
388 | * whenever an instruction is seen at a higher level. In 32 bit | |
389 | * environments, v9 is not bumped up to, the user must pass | |
19f7b010 | 390 | * -Av8plus{,a,b}. |
252b5132 RH |
391 | * |
392 | * If -bump is specified, a warning is printing when bumping to | |
393 | * higher levels. | |
394 | * | |
395 | * If an architecture is specified, all instructions must match | |
396 | * that architecture. Any higher level instructions are flagged | |
397 | * as errors. Note that in the 32 bit environment specifying | |
398 | * -Av8plus does not automatically create a v8plus object file, a | |
399 | * v9 insn must be seen. | |
400 | * | |
401 | * If both an architecture and -bump are specified, the | |
402 | * architecture starts at the specified level, but bumps are | |
403 | * warnings. Note that we can't set `current_architecture' to | |
404 | * the requested level in this case: in the 32 bit environment, | |
405 | * we still must avoid creating v8plus object files unless v9 | |
406 | * insns are seen. | |
407 | * | |
408 | * Note: | |
409 | * Bumping between incompatible architectures is always an | |
410 | * error. For example, from sparclite to v9. | |
411 | */ | |
412 | ||
413 | #ifdef OBJ_ELF | |
5a38dc70 | 414 | const char *md_shortopts = "A:K:VQ:sq"; |
252b5132 RH |
415 | #else |
416 | #ifdef OBJ_AOUT | |
5a38dc70 | 417 | const char *md_shortopts = "A:k"; |
252b5132 | 418 | #else |
5a38dc70 | 419 | const char *md_shortopts = "A:"; |
252b5132 RH |
420 | #endif |
421 | #endif | |
422 | struct option md_longopts[] = { | |
423 | #define OPTION_BUMP (OPTION_MD_BASE) | |
424 | {"bump", no_argument, NULL, OPTION_BUMP}, | |
425 | #define OPTION_SPARC (OPTION_MD_BASE + 1) | |
426 | {"sparc", no_argument, NULL, OPTION_SPARC}, | |
427 | #define OPTION_XARCH (OPTION_MD_BASE + 2) | |
428 | {"xarch", required_argument, NULL, OPTION_XARCH}, | |
429 | #ifdef OBJ_ELF | |
430 | #define OPTION_32 (OPTION_MD_BASE + 3) | |
431 | {"32", no_argument, NULL, OPTION_32}, | |
432 | #define OPTION_64 (OPTION_MD_BASE + 4) | |
433 | {"64", no_argument, NULL, OPTION_64}, | |
434 | #define OPTION_TSO (OPTION_MD_BASE + 5) | |
435 | {"TSO", no_argument, NULL, OPTION_TSO}, | |
436 | #define OPTION_PSO (OPTION_MD_BASE + 6) | |
437 | {"PSO", no_argument, NULL, OPTION_PSO}, | |
438 | #define OPTION_RMO (OPTION_MD_BASE + 7) | |
439 | {"RMO", no_argument, NULL, OPTION_RMO}, | |
440 | #endif | |
441 | #ifdef SPARC_BIENDIAN | |
442 | #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) | |
443 | {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, | |
444 | #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) | |
445 | {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, | |
446 | #endif | |
447 | #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) | |
448 | {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, | |
449 | #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) | |
450 | {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, | |
6d8809aa RH |
451 | #ifdef OBJ_ELF |
452 | #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) | |
453 | {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, | |
a25fe906 ILT |
454 | #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) |
455 | {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, | |
6d8809aa | 456 | #endif |
6faf3d66 JJ |
457 | #define OPTION_RELAX (OPTION_MD_BASE + 14) |
458 | {"relax", no_argument, NULL, OPTION_RELAX}, | |
459 | #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) | |
460 | {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
252b5132 RH |
461 | {NULL, no_argument, NULL, 0} |
462 | }; | |
e0c6ed95 AM |
463 | |
464 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
465 | |
466 | int | |
5a49b8ac | 467 | md_parse_option (int c, char *arg) |
252b5132 RH |
468 | { |
469 | /* We don't get a chance to initialize anything before we're called, | |
470 | so handle that now. */ | |
471 | if (! default_init_p) | |
472 | init_default_arch (); | |
473 | ||
474 | switch (c) | |
475 | { | |
476 | case OPTION_BUMP: | |
477 | warn_on_bump = 1; | |
478 | warn_after_architecture = SPARC_OPCODE_ARCH_V6; | |
479 | break; | |
480 | ||
481 | case OPTION_XARCH: | |
c2158c24 | 482 | #ifdef OBJ_ELF |
668b27ea | 483 | if (!strncmp (arg, "v9", 2)) |
c2158c24 | 484 | md_parse_option (OPTION_64, NULL); |
668b27ea DM |
485 | else |
486 | { | |
487 | if (!strncmp (arg, "v8", 2) | |
488 | || !strncmp (arg, "v7", 2) | |
489 | || !strncmp (arg, "v6", 2) | |
490 | || !strcmp (arg, "sparclet") | |
491 | || !strcmp (arg, "sparclite") | |
492 | || !strcmp (arg, "sparc86x")) | |
493 | md_parse_option (OPTION_32, NULL); | |
494 | } | |
c2158c24 | 495 | #endif |
e0c6ed95 | 496 | /* Fall through. */ |
252b5132 RH |
497 | |
498 | case 'A': | |
499 | { | |
500 | struct sparc_arch *sa; | |
501 | enum sparc_opcode_arch_val opcode_arch; | |
502 | ||
503 | sa = lookup_arch (arg); | |
504 | if (sa == NULL | |
505 | || ! sa->user_option_p) | |
506 | { | |
c2158c24 JJ |
507 | if (c == OPTION_XARCH) |
508 | as_bad (_("invalid architecture -xarch=%s"), arg); | |
509 | else | |
510 | as_bad (_("invalid architecture -A%s"), arg); | |
252b5132 RH |
511 | return 0; |
512 | } | |
513 | ||
514 | opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); | |
515 | if (opcode_arch == SPARC_OPCODE_ARCH_BAD) | |
516 | as_fatal (_("Bad opcode table, broken assembler.")); | |
517 | ||
4bafe00e DM |
518 | if (!architecture_requested |
519 | || opcode_arch > max_architecture) | |
520 | max_architecture = opcode_arch; | |
521 | hwcap_allowed |= sa->hwcap_allowed; | |
252b5132 RH |
522 | architecture_requested = 1; |
523 | } | |
524 | break; | |
525 | ||
526 | case OPTION_SPARC: | |
527 | /* Ignore -sparc, used by SunOS make default .s.o rule. */ | |
528 | break; | |
529 | ||
530 | case OPTION_ENFORCE_ALIGNED_DATA: | |
531 | enforce_aligned_data = 1; | |
532 | break; | |
533 | ||
534 | #ifdef SPARC_BIENDIAN | |
535 | case OPTION_LITTLE_ENDIAN: | |
536 | target_big_endian = 0; | |
537 | if (default_arch_type != sparclet) | |
538 | as_fatal ("This target does not support -EL"); | |
539 | break; | |
540 | case OPTION_LITTLE_ENDIAN_DATA: | |
541 | target_little_endian_data = 1; | |
542 | target_big_endian = 0; | |
543 | if (default_arch_type != sparc86x | |
544 | && default_arch_type != v9) | |
545 | as_fatal ("This target does not support --little-endian-data"); | |
546 | break; | |
547 | case OPTION_BIG_ENDIAN: | |
548 | target_big_endian = 1; | |
549 | break; | |
550 | #endif | |
551 | ||
552 | #ifdef OBJ_AOUT | |
553 | case 'k': | |
554 | sparc_pic_code = 1; | |
555 | break; | |
556 | #endif | |
557 | ||
558 | #ifdef OBJ_ELF | |
559 | case OPTION_32: | |
560 | case OPTION_64: | |
561 | { | |
562 | const char **list, **l; | |
563 | ||
564 | sparc_arch_size = c == OPTION_32 ? 32 : 64; | |
565 | list = bfd_target_list (); | |
566 | for (l = list; *l != NULL; l++) | |
567 | { | |
568 | if (sparc_arch_size == 32) | |
569 | { | |
71a75f6f | 570 | if (CONST_STRNEQ (*l, "elf32-sparc")) |
252b5132 RH |
571 | break; |
572 | } | |
573 | else | |
574 | { | |
71a75f6f | 575 | if (CONST_STRNEQ (*l, "elf64-sparc")) |
252b5132 RH |
576 | break; |
577 | } | |
578 | } | |
579 | if (*l == NULL) | |
580 | as_fatal (_("No compiled in support for %d bit object file format"), | |
581 | sparc_arch_size); | |
582 | free (list); | |
b7cac25f DM |
583 | |
584 | if (sparc_arch_size == 64 | |
585 | && max_architecture < SPARC_OPCODE_ARCH_V9) | |
586 | max_architecture = SPARC_OPCODE_ARCH_V9; | |
252b5132 RH |
587 | } |
588 | break; | |
589 | ||
590 | case OPTION_TSO: | |
591 | sparc_memory_model = MM_TSO; | |
592 | break; | |
593 | ||
594 | case OPTION_PSO: | |
595 | sparc_memory_model = MM_PSO; | |
596 | break; | |
597 | ||
598 | case OPTION_RMO: | |
599 | sparc_memory_model = MM_RMO; | |
600 | break; | |
601 | ||
602 | case 'V': | |
603 | print_version_id (); | |
604 | break; | |
605 | ||
606 | case 'Q': | |
607 | /* Qy - do emit .comment | |
e0c6ed95 | 608 | Qn - do not emit .comment. */ |
252b5132 RH |
609 | break; |
610 | ||
611 | case 's': | |
e0c6ed95 | 612 | /* Use .stab instead of .stab.excl. */ |
252b5132 RH |
613 | break; |
614 | ||
615 | case 'q': | |
e0c6ed95 | 616 | /* quick -- Native assembler does fewer checks. */ |
252b5132 RH |
617 | break; |
618 | ||
619 | case 'K': | |
620 | if (strcmp (arg, "PIC") != 0) | |
621 | as_warn (_("Unrecognized option following -K")); | |
622 | else | |
623 | sparc_pic_code = 1; | |
624 | break; | |
6d8809aa RH |
625 | |
626 | case OPTION_NO_UNDECLARED_REGS: | |
627 | no_undeclared_regs = 1; | |
628 | break; | |
a25fe906 ILT |
629 | |
630 | case OPTION_UNDECLARED_REGS: | |
631 | no_undeclared_regs = 0; | |
632 | break; | |
252b5132 RH |
633 | #endif |
634 | ||
6faf3d66 JJ |
635 | case OPTION_RELAX: |
636 | sparc_relax = 1; | |
637 | break; | |
638 | ||
639 | case OPTION_NO_RELAX: | |
640 | sparc_relax = 0; | |
641 | break; | |
642 | ||
252b5132 RH |
643 | default: |
644 | return 0; | |
645 | } | |
646 | ||
647 | return 1; | |
648 | } | |
649 | ||
650 | void | |
5a49b8ac | 651 | md_show_usage (FILE *stream) |
252b5132 RH |
652 | { |
653 | const struct sparc_arch *arch; | |
c2158c24 | 654 | int column; |
252b5132 RH |
655 | |
656 | /* We don't get a chance to initialize anything before we're called, | |
657 | so handle that now. */ | |
658 | if (! default_init_p) | |
659 | init_default_arch (); | |
660 | ||
e0c6ed95 | 661 | fprintf (stream, _("SPARC options:\n")); |
c2158c24 | 662 | column = 0; |
252b5132 RH |
663 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
664 | { | |
c2158c24 JJ |
665 | if (!arch->user_option_p) |
666 | continue; | |
252b5132 RH |
667 | if (arch != &sparc_arch_table[0]) |
668 | fprintf (stream, " | "); | |
07726851 | 669 | if (column + strlen (arch->name) > 70) |
c2158c24 JJ |
670 | { |
671 | column = 0; | |
672 | fputc ('\n', stream); | |
673 | } | |
07726851 | 674 | column += 5 + 2 + strlen (arch->name); |
c2158c24 | 675 | fprintf (stream, "-A%s", arch->name); |
252b5132 | 676 | } |
c2158c24 JJ |
677 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
678 | { | |
679 | if (!arch->user_option_p) | |
680 | continue; | |
681 | fprintf (stream, " | "); | |
07726851 | 682 | if (column + strlen (arch->name) > 65) |
c2158c24 JJ |
683 | { |
684 | column = 0; | |
685 | fputc ('\n', stream); | |
686 | } | |
07726851 | 687 | column += 5 + 7 + strlen (arch->name); |
c2158c24 JJ |
688 | fprintf (stream, "-xarch=%s", arch->name); |
689 | } | |
690 | fprintf (stream, _("\n\ | |
252b5132 RH |
691 | specify variant of SPARC architecture\n\ |
692 | -bump warn when assembler switches architectures\n\ | |
693 | -sparc ignored\n\ | |
6faf3d66 JJ |
694 | --enforce-aligned-data force .long, etc., to be aligned correctly\n\ |
695 | -relax relax jumps and branches (default)\n\ | |
696 | -no-relax avoid changing any jumps and branches\n")); | |
252b5132 RH |
697 | #ifdef OBJ_AOUT |
698 | fprintf (stream, _("\ | |
699 | -k generate PIC\n")); | |
700 | #endif | |
701 | #ifdef OBJ_ELF | |
702 | fprintf (stream, _("\ | |
703 | -32 create 32 bit object file\n\ | |
704 | -64 create 64 bit object file\n")); | |
705 | fprintf (stream, _("\ | |
706 | [default is %d]\n"), default_arch_size); | |
707 | fprintf (stream, _("\ | |
708 | -TSO use Total Store Ordering\n\ | |
709 | -PSO use Partial Store Ordering\n\ | |
710 | -RMO use Relaxed Memory Ordering\n")); | |
711 | fprintf (stream, _("\ | |
712 | [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); | |
713 | fprintf (stream, _("\ | |
714 | -KPIC generate PIC\n\ | |
715 | -V print assembler version number\n\ | |
a25fe906 ILT |
716 | -undeclared-regs ignore application global register usage without\n\ |
717 | appropriate .register directive (default)\n\ | |
718 | -no-undeclared-regs force error on application global register usage\n\ | |
719 | without appropriate .register directive\n\ | |
252b5132 RH |
720 | -q ignored\n\ |
721 | -Qy, -Qn ignored\n\ | |
722 | -s ignored\n")); | |
723 | #endif | |
724 | #ifdef SPARC_BIENDIAN | |
725 | fprintf (stream, _("\ | |
726 | -EL generate code for a little endian machine\n\ | |
727 | -EB generate code for a big endian machine\n\ | |
728 | --little-endian-data generate code for a machine having big endian\n\ | |
c20f4f8c | 729 | instructions and little endian data.\n")); |
252b5132 RH |
730 | #endif |
731 | } | |
732 | \f | |
e0c6ed95 | 733 | /* Native operand size opcode translation. */ |
cf9a1301 RH |
734 | struct |
735 | { | |
736 | char *name; | |
737 | char *name32; | |
738 | char *name64; | |
739 | } native_op_table[] = | |
740 | { | |
741 | {"ldn", "ld", "ldx"}, | |
742 | {"ldna", "lda", "ldxa"}, | |
743 | {"stn", "st", "stx"}, | |
744 | {"stna", "sta", "stxa"}, | |
745 | {"slln", "sll", "sllx"}, | |
746 | {"srln", "srl", "srlx"}, | |
747 | {"sran", "sra", "srax"}, | |
748 | {"casn", "cas", "casx"}, | |
749 | {"casna", "casa", "casxa"}, | |
750 | {"clrn", "clr", "clrx"}, | |
751 | {NULL, NULL, NULL}, | |
752 | }; | |
753 | \f | |
10156f83 | 754 | /* sparc64 privileged and hyperprivileged registers. */ |
252b5132 RH |
755 | |
756 | struct priv_reg_entry | |
ab3e48dc KH |
757 | { |
758 | char *name; | |
759 | int regnum; | |
760 | }; | |
252b5132 RH |
761 | |
762 | struct priv_reg_entry priv_reg_table[] = | |
763 | { | |
764 | {"tpc", 0}, | |
765 | {"tnpc", 1}, | |
766 | {"tstate", 2}, | |
767 | {"tt", 3}, | |
768 | {"tick", 4}, | |
769 | {"tba", 5}, | |
770 | {"pstate", 6}, | |
771 | {"tl", 7}, | |
772 | {"pil", 8}, | |
773 | {"cwp", 9}, | |
774 | {"cansave", 10}, | |
775 | {"canrestore", 11}, | |
776 | {"cleanwin", 12}, | |
777 | {"otherwin", 13}, | |
778 | {"wstate", 14}, | |
779 | {"fq", 15}, | |
10156f83 | 780 | {"gl", 16}, |
252b5132 | 781 | {"ver", 31}, |
e0c6ed95 | 782 | {"", -1}, /* End marker. */ |
252b5132 RH |
783 | }; |
784 | ||
10156f83 DM |
785 | struct priv_reg_entry hpriv_reg_table[] = |
786 | { | |
787 | {"hpstate", 0}, | |
788 | {"htstate", 1}, | |
789 | {"hintp", 3}, | |
790 | {"htba", 5}, | |
791 | {"hver", 6}, | |
792 | {"hstick_cmpr", 31}, | |
793 | {"", -1}, /* End marker. */ | |
794 | }; | |
795 | ||
1a6b486f DM |
796 | /* v9a specific asrs. This table is ordered by initial |
797 | letter, in reverse. */ | |
252b5132 RH |
798 | |
799 | struct priv_reg_entry v9a_asr_table[] = | |
800 | { | |
801 | {"tick_cmpr", 23}, | |
19f7b010 JJ |
802 | {"sys_tick_cmpr", 25}, |
803 | {"sys_tick", 24}, | |
1a6b486f DM |
804 | {"stick_cmpr", 25}, |
805 | {"stick", 24}, | |
f04d18b7 DM |
806 | {"softint_clear", 21}, |
807 | {"softint_set", 20}, | |
2b661f3d | 808 | {"softint", 22}, |
252b5132 | 809 | {"set_softint", 20}, |
58004e23 | 810 | {"pause", 27}, |
252b5132 RH |
811 | {"pic", 17}, |
812 | {"pcr", 16}, | |
813 | {"gsr", 19}, | |
814 | {"dcr", 18}, | |
ea783ef3 | 815 | {"cps", 28}, |
2e52845b | 816 | {"cfr", 26}, |
252b5132 | 817 | {"clear_softint", 21}, |
e0c6ed95 | 818 | {"", -1}, /* End marker. */ |
252b5132 RH |
819 | }; |
820 | ||
821 | static int | |
5a49b8ac | 822 | cmp_reg_entry (const void *parg, const void *qarg) |
252b5132 RH |
823 | { |
824 | const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; | |
825 | const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; | |
826 | ||
827 | return strcmp (q->name, p->name); | |
828 | } | |
829 | \f | |
830 | /* This function is called once, at assembler startup time. It should | |
e0c6ed95 AM |
831 | set up all the tables, etc. that the MD part of the assembler will |
832 | need. */ | |
252b5132 RH |
833 | |
834 | void | |
5a49b8ac | 835 | md_begin (void) |
252b5132 RH |
836 | { |
837 | register const char *retval = NULL; | |
838 | int lose = 0; | |
839 | register unsigned int i = 0; | |
840 | ||
841 | /* We don't get a chance to initialize anything before md_parse_option | |
842 | is called, and it may not be called, so handle default initialization | |
843 | now if not already done. */ | |
844 | if (! default_init_p) | |
845 | init_default_arch (); | |
846 | ||
364b6d8b | 847 | sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; |
252b5132 RH |
848 | op_hash = hash_new (); |
849 | ||
850 | while (i < (unsigned int) sparc_num_opcodes) | |
851 | { | |
852 | const char *name = sparc_opcodes[i].name; | |
5a49b8ac | 853 | retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); |
252b5132 RH |
854 | if (retval != NULL) |
855 | { | |
cf9a1301 RH |
856 | as_bad (_("Internal error: can't hash `%s': %s\n"), |
857 | sparc_opcodes[i].name, retval); | |
252b5132 RH |
858 | lose = 1; |
859 | } | |
860 | do | |
861 | { | |
862 | if (sparc_opcodes[i].match & sparc_opcodes[i].lose) | |
863 | { | |
cf9a1301 RH |
864 | as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), |
865 | sparc_opcodes[i].name, sparc_opcodes[i].args); | |
252b5132 RH |
866 | lose = 1; |
867 | } | |
868 | ++i; | |
869 | } | |
870 | while (i < (unsigned int) sparc_num_opcodes | |
871 | && !strcmp (sparc_opcodes[i].name, name)); | |
872 | } | |
873 | ||
cf9a1301 RH |
874 | for (i = 0; native_op_table[i].name; i++) |
875 | { | |
876 | const struct sparc_opcode *insn; | |
3d4ae3c0 NC |
877 | char *name = ((sparc_arch_size == 32) |
878 | ? native_op_table[i].name32 | |
879 | : native_op_table[i].name64); | |
e0c6ed95 | 880 | insn = (struct sparc_opcode *) hash_find (op_hash, name); |
cf9a1301 | 881 | if (insn == NULL) |
e0c6ed95 AM |
882 | { |
883 | as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), | |
884 | name, native_op_table[i].name); | |
885 | lose = 1; | |
886 | } | |
cf9a1301 RH |
887 | else |
888 | { | |
5a49b8ac AM |
889 | retval = hash_insert (op_hash, native_op_table[i].name, |
890 | (void *) insn); | |
cf9a1301 RH |
891 | if (retval != NULL) |
892 | { | |
893 | as_bad (_("Internal error: can't hash `%s': %s\n"), | |
894 | sparc_opcodes[i].name, retval); | |
895 | lose = 1; | |
896 | } | |
897 | } | |
898 | } | |
899 | ||
252b5132 RH |
900 | if (lose) |
901 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
902 | ||
252b5132 RH |
903 | qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), |
904 | sizeof (priv_reg_table[0]), cmp_reg_entry); | |
905 | ||
906 | /* If -bump, record the architecture level at which we start issuing | |
907 | warnings. The behaviour is different depending upon whether an | |
908 | architecture was explicitly specified. If it wasn't, we issue warnings | |
909 | for all upwards bumps. If it was, we don't start issuing warnings until | |
910 | we need to bump beyond the requested architecture or when we bump between | |
911 | conflicting architectures. */ | |
912 | ||
913 | if (warn_on_bump | |
914 | && architecture_requested) | |
915 | { | |
916 | /* `max_architecture' records the requested architecture. | |
917 | Issue warnings if we go above it. */ | |
918 | warn_after_architecture = max_architecture; | |
919 | ||
920 | /* Find the highest architecture level that doesn't conflict with | |
921 | the requested one. */ | |
922 | for (max_architecture = SPARC_OPCODE_ARCH_MAX; | |
923 | max_architecture > warn_after_architecture; | |
924 | --max_architecture) | |
925 | if (! SPARC_OPCODE_CONFLICT_P (max_architecture, | |
926 | warn_after_architecture)) | |
927 | break; | |
928 | } | |
929 | } | |
930 | ||
931 | /* Called after all assembly has been done. */ | |
932 | ||
933 | void | |
5a49b8ac | 934 | sparc_md_end (void) |
252b5132 | 935 | { |
19f7b010 JJ |
936 | unsigned long mach = bfd_mach_sparc; |
937 | ||
252b5132 | 938 | if (sparc_arch_size == 64) |
19f7b010 JJ |
939 | switch (current_architecture) |
940 | { | |
941 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; | |
942 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; | |
943 | default: mach = bfd_mach_sparc_v9; break; | |
944 | } | |
252b5132 | 945 | else |
19f7b010 JJ |
946 | switch (current_architecture) |
947 | { | |
948 | case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; | |
949 | case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; | |
950 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; | |
951 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; | |
952 | /* The sparclite is treated like a normal sparc. Perhaps it shouldn't | |
953 | be but for now it is (since that's the way it's always been | |
954 | treated). */ | |
955 | default: break; | |
956 | } | |
957 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); | |
9e8c70f9 DM |
958 | |
959 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) | |
960 | if (hwcap_seen) | |
ec668d69 | 961 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcap_seen); |
9e8c70f9 | 962 | #endif |
252b5132 RH |
963 | } |
964 | \f | |
965 | /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ | |
966 | ||
5a49b8ac AM |
967 | static inline int |
968 | in_signed_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
969 | { |
970 | if (max <= 0) | |
971 | abort (); | |
972 | /* Sign-extend the value from the architecture word size, so that | |
973 | 0xffffffff is always considered -1 on sparc32. */ | |
974 | if (sparc_arch_size == 32) | |
975 | { | |
e0c6ed95 | 976 | bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; |
6c1b24e4 | 977 | val = ((val & U0xffffffff) ^ sign) - sign; |
252b5132 RH |
978 | } |
979 | if (val > max) | |
980 | return 0; | |
981 | if (val < ~max) | |
982 | return 0; | |
983 | return 1; | |
984 | } | |
985 | ||
986 | /* Return non-zero if VAL is in the range 0 to MAX. */ | |
987 | ||
5a49b8ac AM |
988 | static inline int |
989 | in_unsigned_range (bfd_vma val, bfd_vma max) | |
252b5132 RH |
990 | { |
991 | if (val > max) | |
992 | return 0; | |
993 | return 1; | |
994 | } | |
995 | ||
996 | /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. | |
997 | (e.g. -15 to +31). */ | |
998 | ||
5a49b8ac AM |
999 | static inline int |
1000 | in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
1001 | { |
1002 | if (max <= 0) | |
1003 | abort (); | |
1004 | if (val > max) | |
1005 | return 0; | |
1006 | if (val < ~(max >> 1)) | |
1007 | return 0; | |
1008 | return 1; | |
1009 | } | |
1010 | ||
1011 | static int | |
5a49b8ac | 1012 | sparc_ffs (unsigned int mask) |
252b5132 RH |
1013 | { |
1014 | int i; | |
1015 | ||
1016 | if (mask == 0) | |
1017 | return -1; | |
1018 | ||
1019 | for (i = 0; (mask & 1) == 0; ++i) | |
1020 | mask >>= 1; | |
1021 | return i; | |
1022 | } | |
1023 | ||
1024 | /* Implement big shift right. */ | |
1025 | static bfd_vma | |
5a49b8ac | 1026 | BSR (bfd_vma val, int amount) |
252b5132 RH |
1027 | { |
1028 | if (sizeof (bfd_vma) <= 4 && amount >= 32) | |
1029 | as_fatal (_("Support for 64-bit arithmetic not compiled in.")); | |
1030 | return val >> amount; | |
1031 | } | |
1032 | \f | |
1033 | /* For communication between sparc_ip and get_expression. */ | |
1034 | static char *expr_end; | |
1035 | ||
252b5132 RH |
1036 | /* Values for `special_case'. |
1037 | Instructions that require wierd handling because they're longer than | |
1038 | 4 bytes. */ | |
1039 | #define SPECIAL_CASE_NONE 0 | |
1040 | #define SPECIAL_CASE_SET 1 | |
1041 | #define SPECIAL_CASE_SETSW 2 | |
1042 | #define SPECIAL_CASE_SETX 3 | |
1043 | /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ | |
1044 | #define SPECIAL_CASE_FDIV 4 | |
1045 | ||
1046 | /* Bit masks of various insns. */ | |
1047 | #define NOP_INSN 0x01000000 | |
1048 | #define OR_INSN 0x80100000 | |
63fab58c | 1049 | #define XOR_INSN 0x80180000 |
252b5132 RH |
1050 | #define FMOVS_INSN 0x81A00020 |
1051 | #define SETHI_INSN 0x01000000 | |
1052 | #define SLLX_INSN 0x81281000 | |
1053 | #define SRA_INSN 0x81380000 | |
1054 | ||
1055 | /* The last instruction to be assembled. */ | |
1056 | static const struct sparc_opcode *last_insn; | |
1057 | /* The assembled opcode of `last_insn'. */ | |
1058 | static unsigned long last_opcode; | |
1059 | \f | |
a22b281c | 1060 | /* Handle the set and setuw synthetic instructions. */ |
e0c6ed95 | 1061 | |
a22b281c | 1062 | static void |
5a49b8ac | 1063 | synthetize_setuw (const struct sparc_opcode *insn) |
a22b281c RH |
1064 | { |
1065 | int need_hi22_p = 0; | |
1066 | int rd = (the_insn.opcode & RD (~0)) >> 25; | |
1067 | ||
1068 | if (the_insn.exp.X_op == O_constant) | |
1069 | { | |
1070 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1071 | { | |
e0c6ed95 | 1072 | if (sizeof (offsetT) > 4 |
a22b281c | 1073 | && (the_insn.exp.X_add_number < 0 |
6c1b24e4 | 1074 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) |
a22b281c RH |
1075 | as_warn (_("set: number not in 0..4294967295 range")); |
1076 | } | |
1077 | else | |
1078 | { | |
e0c6ed95 | 1079 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1080 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1081 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c | 1082 | as_warn (_("set: number not in -2147483648..4294967295 range")); |
e0c6ed95 | 1083 | the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; |
a22b281c RH |
1084 | } |
1085 | } | |
1086 | ||
1087 | /* See if operand is absolute and small; skip sethi if so. */ | |
1088 | if (the_insn.exp.X_op != O_constant | |
1089 | || the_insn.exp.X_add_number >= (1 << 12) | |
1090 | || the_insn.exp.X_add_number < -(1 << 12)) | |
1091 | { | |
1092 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1093 | | ((the_insn.exp.X_add_number >> 10) | |
ab3e48dc KH |
1094 | & (the_insn.exp.X_op == O_constant |
1095 | ? 0x3fffff : 0))); | |
a22b281c | 1096 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1097 | ? BFD_RELOC_HI22 : BFD_RELOC_NONE); |
a22b281c RH |
1098 | output_insn (insn, &the_insn); |
1099 | need_hi22_p = 1; | |
1100 | } | |
1101 | ||
1102 | /* See if operand has no low-order bits; skip OR if so. */ | |
1103 | if (the_insn.exp.X_op != O_constant | |
1104 | || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) | |
1105 | || ! need_hi22_p) | |
1106 | { | |
1107 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) | |
1108 | | RD (rd) | IMMED | |
1109 | | (the_insn.exp.X_add_number | |
ab3e48dc KH |
1110 | & (the_insn.exp.X_op != O_constant |
1111 | ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); | |
a22b281c | 1112 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1113 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); |
a22b281c RH |
1114 | output_insn (insn, &the_insn); |
1115 | } | |
1116 | } | |
e0c6ed95 | 1117 | |
a22b281c | 1118 | /* Handle the setsw synthetic instruction. */ |
e0c6ed95 | 1119 | |
a22b281c | 1120 | static void |
5a49b8ac | 1121 | synthetize_setsw (const struct sparc_opcode *insn) |
a22b281c RH |
1122 | { |
1123 | int low32, rd, opc; | |
1124 | ||
1125 | rd = (the_insn.opcode & RD (~0)) >> 25; | |
1126 | ||
1127 | if (the_insn.exp.X_op != O_constant) | |
1128 | { | |
1129 | synthetize_setuw (insn); | |
1130 | ||
1131 | /* Need to sign extend it. */ | |
1132 | the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); | |
1133 | the_insn.reloc = BFD_RELOC_NONE; | |
1134 | output_insn (insn, &the_insn); | |
1135 | return; | |
1136 | } | |
1137 | ||
e0c6ed95 | 1138 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1139 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1140 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c RH |
1141 | as_warn (_("setsw: number not in -2147483648..4294967295 range")); |
1142 | ||
e0c6ed95 AM |
1143 | low32 = the_insn.exp.X_add_number; |
1144 | ||
a22b281c RH |
1145 | if (low32 >= 0) |
1146 | { | |
1147 | synthetize_setuw (insn); | |
1148 | return; | |
1149 | } | |
1150 | ||
1151 | opc = OR_INSN; | |
e0c6ed95 | 1152 | |
a22b281c RH |
1153 | the_insn.reloc = BFD_RELOC_NONE; |
1154 | /* See if operand is absolute and small; skip sethi if so. */ | |
1155 | if (low32 < -(1 << 12)) | |
1156 | { | |
1157 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1158 | | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); | |
1159 | output_insn (insn, &the_insn); | |
1160 | low32 = 0x1c00 | (low32 & 0x3ff); | |
1161 | opc = RS1 (rd) | XOR_INSN; | |
1162 | } | |
1163 | ||
1164 | the_insn.opcode = (opc | RD (rd) | IMMED | |
1165 | | (low32 & 0x1fff)); | |
1166 | output_insn (insn, &the_insn); | |
1167 | } | |
1168 | ||
1169 | /* Handle the setsw synthetic instruction. */ | |
e0c6ed95 | 1170 | |
a22b281c | 1171 | static void |
5a49b8ac | 1172 | synthetize_setx (const struct sparc_opcode *insn) |
a22b281c RH |
1173 | { |
1174 | int upper32, lower32; | |
1175 | int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; | |
1176 | int dstreg = (the_insn.opcode & RD (~0)) >> 25; | |
1177 | int upper_dstreg; | |
1178 | int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; | |
1179 | int need_xor10_p = 0; | |
e0c6ed95 | 1180 | |
6c1b24e4 | 1181 | #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) |
a22b281c RH |
1182 | lower32 = SIGNEXT32 (the_insn.exp.X_add_number); |
1183 | upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); | |
1184 | #undef SIGNEXT32 | |
1185 | ||
1186 | upper_dstreg = tmpreg; | |
1187 | /* The tmp reg should not be the dst reg. */ | |
1188 | if (tmpreg == dstreg) | |
1189 | as_warn (_("setx: temporary register same as destination register")); | |
1190 | ||
1191 | /* ??? Obviously there are other optimizations we can do | |
1192 | (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be | |
1193 | doing some of these. Later. If you do change things, try to | |
1194 | change all of this to be table driven as well. */ | |
1195 | /* What to output depends on the number if it's constant. | |
1196 | Compute that first, then output what we've decided upon. */ | |
1197 | if (the_insn.exp.X_op != O_constant) | |
1198 | { | |
1199 | if (sparc_arch_size == 32) | |
1200 | { | |
1201 | /* When arch size is 32, we want setx to be equivalent | |
1202 | to setuw for anything but constants. */ | |
1203 | the_insn.exp.X_add_number &= 0xffffffff; | |
1204 | synthetize_setuw (insn); | |
1205 | return; | |
1206 | } | |
1207 | need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; | |
ab3e48dc KH |
1208 | lower32 = 0; |
1209 | upper32 = 0; | |
a22b281c RH |
1210 | } |
1211 | else | |
1212 | { | |
1213 | /* Reset X_add_number, we've extracted it as upper32/lower32. | |
1214 | Otherwise fixup_segment will complain about not being able to | |
1215 | write an 8 byte number in a 4 byte field. */ | |
1216 | the_insn.exp.X_add_number = 0; | |
e0c6ed95 | 1217 | |
a22b281c RH |
1218 | /* Only need hh22 if `or' insn can't handle constant. */ |
1219 | if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) | |
1220 | need_hh22_p = 1; | |
e0c6ed95 | 1221 | |
a22b281c RH |
1222 | /* Does bottom part (after sethi) have bits? */ |
1223 | if ((need_hh22_p && (upper32 & 0x3ff) != 0) | |
1224 | /* No hh22, but does upper32 still have bits we can't set | |
1225 | from lower32? */ | |
1226 | || (! need_hh22_p && upper32 != 0 && upper32 != -1)) | |
1227 | need_hm10_p = 1; | |
e0c6ed95 | 1228 | |
a22b281c RH |
1229 | /* If the lower half is all zero, we build the upper half directly |
1230 | into the dst reg. */ | |
1231 | if (lower32 != 0 | |
1232 | /* Need lower half if number is zero or 0xffffffff00000000. */ | |
1233 | || (! need_hh22_p && ! need_hm10_p)) | |
1234 | { | |
1235 | /* No need for sethi if `or' insn can handle constant. */ | |
1236 | if (lower32 < -(1 << 12) || lower32 >= (1 << 12) | |
1237 | /* Note that we can't use a negative constant in the `or' | |
1238 | insn unless the upper 32 bits are all ones. */ | |
1239 | || (lower32 < 0 && upper32 != -1) | |
1240 | || (lower32 >= 0 && upper32 == -1)) | |
1241 | need_hi22_p = 1; | |
e0c6ed95 | 1242 | |
a22b281c RH |
1243 | if (need_hi22_p && upper32 == -1) |
1244 | need_xor10_p = 1; | |
1245 | ||
1246 | /* Does bottom part (after sethi) have bits? */ | |
1247 | else if ((need_hi22_p && (lower32 & 0x3ff) != 0) | |
1248 | /* No sethi. */ | |
1249 | || (! need_hi22_p && (lower32 & 0x1fff) != 0) | |
1250 | /* Need `or' if we didn't set anything else. */ | |
1251 | || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) | |
1252 | need_lo10_p = 1; | |
1253 | } | |
1254 | else | |
1255 | /* Output directly to dst reg if lower 32 bits are all zero. */ | |
1256 | upper_dstreg = dstreg; | |
1257 | } | |
e0c6ed95 | 1258 | |
a22b281c RH |
1259 | if (!upper_dstreg && dstreg) |
1260 | as_warn (_("setx: illegal temporary register g0")); | |
1261 | ||
1262 | if (need_hh22_p) | |
1263 | { | |
1264 | the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) | |
1265 | | ((upper32 >> 10) & 0x3fffff)); | |
1266 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1267 | ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); | |
1268 | output_insn (insn, &the_insn); | |
1269 | } | |
e0c6ed95 | 1270 | |
a22b281c RH |
1271 | if (need_hi22_p) |
1272 | { | |
1273 | the_insn.opcode = (SETHI_INSN | RD (dstreg) | |
1274 | | (((need_xor10_p ? ~lower32 : lower32) | |
ab3e48dc | 1275 | >> 10) & 0x3fffff)); |
a22b281c RH |
1276 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
1277 | ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); | |
1278 | output_insn (insn, &the_insn); | |
1279 | } | |
1280 | ||
1281 | if (need_hm10_p) | |
1282 | { | |
1283 | the_insn.opcode = (OR_INSN | |
1284 | | (need_hh22_p ? RS1 (upper_dstreg) : 0) | |
1285 | | RD (upper_dstreg) | |
1286 | | IMMED | |
1287 | | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); | |
1288 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1289 | ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); | |
1290 | output_insn (insn, &the_insn); | |
1291 | } | |
e0c6ed95 | 1292 | |
a22b281c RH |
1293 | if (need_lo10_p) |
1294 | { | |
1295 | /* FIXME: One nice optimization to do here is to OR the low part | |
1296 | with the highpart if hi22 isn't needed and the low part is | |
1297 | positive. */ | |
1298 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) | |
1299 | | RD (dstreg) | |
1300 | | IMMED | |
1301 | | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); | |
1302 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1303 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); | |
1304 | output_insn (insn, &the_insn); | |
1305 | } | |
e0c6ed95 | 1306 | |
a22b281c RH |
1307 | /* If we needed to build the upper part, shift it into place. */ |
1308 | if (need_hh22_p || need_hm10_p) | |
1309 | { | |
1310 | the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) | |
1311 | | IMMED | 32); | |
1312 | the_insn.reloc = BFD_RELOC_NONE; | |
1313 | output_insn (insn, &the_insn); | |
1314 | } | |
e0c6ed95 | 1315 | |
a22b281c RH |
1316 | /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ |
1317 | if (need_xor10_p) | |
1318 | { | |
1319 | the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED | |
1320 | | 0x1c00 | (lower32 & 0x3ff)); | |
1321 | the_insn.reloc = BFD_RELOC_NONE; | |
1322 | output_insn (insn, &the_insn); | |
1323 | } | |
1324 | ||
1325 | /* If we needed to build both upper and lower parts, OR them together. */ | |
1326 | else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) | |
1327 | { | |
1328 | the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) | |
1329 | | RD (dstreg)); | |
1330 | the_insn.reloc = BFD_RELOC_NONE; | |
1331 | output_insn (insn, &the_insn); | |
1332 | } | |
1333 | } | |
1334 | \f | |
252b5132 RH |
1335 | /* Main entry point to assemble one instruction. */ |
1336 | ||
1337 | void | |
5a49b8ac | 1338 | md_assemble (char *str) |
252b5132 RH |
1339 | { |
1340 | const struct sparc_opcode *insn; | |
a22b281c | 1341 | int special_case; |
252b5132 RH |
1342 | |
1343 | know (str); | |
a22b281c | 1344 | special_case = sparc_ip (str, &insn); |
b0825cc2 DM |
1345 | if (insn == NULL) |
1346 | return; | |
252b5132 RH |
1347 | |
1348 | /* We warn about attempts to put a floating point branch in a delay slot, | |
1349 | unless the delay slot has been annulled. */ | |
b0825cc2 | 1350 | if (last_insn != NULL |
252b5132 RH |
1351 | && (insn->flags & F_FBR) != 0 |
1352 | && (last_insn->flags & F_DELAYED) != 0 | |
1353 | /* ??? This test isn't completely accurate. We assume anything with | |
1354 | F_{UNBR,CONDBR,FBR} set is annullable. */ | |
1355 | && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 | |
1356 | || (last_opcode & ANNUL) == 0)) | |
1357 | as_warn (_("FP branch in delay slot")); | |
1358 | ||
1359 | /* SPARC before v9 requires a nop instruction between a floating | |
1360 | point instruction and a floating point branch. We insert one | |
1361 | automatically, with a warning. */ | |
1362 | if (max_architecture < SPARC_OPCODE_ARCH_V9 | |
252b5132 RH |
1363 | && last_insn != NULL |
1364 | && (insn->flags & F_FBR) != 0 | |
1365 | && (last_insn->flags & F_FLOAT) != 0) | |
1366 | { | |
1367 | struct sparc_it nop_insn; | |
1368 | ||
1369 | nop_insn.opcode = NOP_INSN; | |
1370 | nop_insn.reloc = BFD_RELOC_NONE; | |
1371 | output_insn (insn, &nop_insn); | |
1372 | as_warn (_("FP branch preceded by FP instruction; NOP inserted")); | |
1373 | } | |
1374 | ||
a22b281c RH |
1375 | switch (special_case) |
1376 | { | |
1377 | case SPECIAL_CASE_NONE: | |
e0c6ed95 | 1378 | /* Normal insn. */ |
a22b281c RH |
1379 | output_insn (insn, &the_insn); |
1380 | break; | |
252b5132 | 1381 | |
a22b281c RH |
1382 | case SPECIAL_CASE_SETSW: |
1383 | synthetize_setsw (insn); | |
1384 | break; | |
e0c6ed95 | 1385 | |
a22b281c RH |
1386 | case SPECIAL_CASE_SET: |
1387 | synthetize_setuw (insn); | |
1388 | break; | |
252b5132 | 1389 | |
a22b281c RH |
1390 | case SPECIAL_CASE_SETX: |
1391 | synthetize_setx (insn); | |
1392 | break; | |
e0c6ed95 | 1393 | |
a22b281c RH |
1394 | case SPECIAL_CASE_FDIV: |
1395 | { | |
1396 | int rd = (the_insn.opcode >> 25) & 0x1f; | |
e0c6ed95 | 1397 | |
a22b281c | 1398 | output_insn (insn, &the_insn); |
e0c6ed95 | 1399 | |
a22b281c RH |
1400 | /* According to information leaked from Sun, the "fdiv" instructions |
1401 | on early SPARC machines would produce incorrect results sometimes. | |
1402 | The workaround is to add an fmovs of the destination register to | |
1403 | itself just after the instruction. This was true on machines | |
e0c6ed95 | 1404 | with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ |
9c2799c2 | 1405 | gas_assert (the_insn.reloc == BFD_RELOC_NONE); |
a22b281c RH |
1406 | the_insn.opcode = FMOVS_INSN | rd | RD (rd); |
1407 | output_insn (insn, &the_insn); | |
1408 | return; | |
1409 | } | |
e0c6ed95 | 1410 | |
a22b281c RH |
1411 | default: |
1412 | as_fatal (_("failed special case insn sanity check")); | |
252b5132 RH |
1413 | } |
1414 | } | |
1415 | ||
4bafe00e DM |
1416 | static const char * |
1417 | get_hwcap_name (int mask) | |
1418 | { | |
ec668d69 | 1419 | if (mask & HWCAP_MUL32) |
4bafe00e | 1420 | return "mul32"; |
ec668d69 | 1421 | if (mask & HWCAP_DIV32) |
4bafe00e | 1422 | return "div32"; |
ec668d69 | 1423 | if (mask & HWCAP_FSMULD) |
4bafe00e | 1424 | return "fsmuld"; |
ec668d69 | 1425 | if (mask & HWCAP_V8PLUS) |
4bafe00e | 1426 | return "v8plus"; |
ec668d69 | 1427 | if (mask & HWCAP_POPC) |
4bafe00e | 1428 | return "popc"; |
ec668d69 | 1429 | if (mask & HWCAP_VIS) |
4bafe00e | 1430 | return "vis"; |
ec668d69 | 1431 | if (mask & HWCAP_VIS2) |
4bafe00e | 1432 | return "vis2"; |
ec668d69 | 1433 | if (mask & HWCAP_ASI_BLK_INIT) |
4bafe00e | 1434 | return "ASIBlkInit"; |
ec668d69 | 1435 | if (mask & HWCAP_FMAF) |
4bafe00e | 1436 | return "fmaf"; |
ec668d69 | 1437 | if (mask & HWCAP_VIS3) |
4bafe00e | 1438 | return "vis3"; |
ec668d69 | 1439 | if (mask & HWCAP_HPC) |
4bafe00e | 1440 | return "hpc"; |
ec668d69 | 1441 | if (mask & HWCAP_RANDOM) |
4bafe00e | 1442 | return "random"; |
ec668d69 | 1443 | if (mask & HWCAP_TRANS) |
4bafe00e | 1444 | return "trans"; |
ec668d69 | 1445 | if (mask & HWCAP_FJFMAU) |
4bafe00e | 1446 | return "fjfmau"; |
ec668d69 | 1447 | if (mask & HWCAP_IMA) |
4bafe00e | 1448 | return "ima"; |
ec668d69 | 1449 | if (mask & HWCAP_ASI_CACHE_SPARING) |
4bafe00e | 1450 | return "cspare"; |
ec668d69 DM |
1451 | if (mask & HWCAP_AES) |
1452 | return "aes"; | |
1453 | if (mask & HWCAP_DES) | |
1454 | return "des"; | |
1455 | if (mask & HWCAP_KASUMI) | |
1456 | return "kasumi"; | |
1457 | if (mask & HWCAP_CAMELLIA) | |
1458 | return "camellia"; | |
1459 | if (mask & HWCAP_MD5) | |
1460 | return "md5"; | |
1461 | if (mask & HWCAP_SHA1) | |
1462 | return "sha1"; | |
1463 | if (mask & HWCAP_SHA256) | |
1464 | return "sha256"; | |
1465 | if (mask & HWCAP_SHA512) | |
1466 | return "sha512"; | |
1467 | if (mask & HWCAP_MPMUL) | |
1468 | return "mpmul"; | |
1469 | if (mask & HWCAP_MONT) | |
1470 | return "mont"; | |
1471 | if (mask & HWCAP_PAUSE) | |
1472 | return "pause"; | |
1473 | if (mask & HWCAP_CBCOND) | |
1474 | return "cbcond"; | |
1475 | if (mask & HWCAP_CRC32C) | |
1476 | return "crc32c"; | |
4bafe00e DM |
1477 | return "UNKNOWN"; |
1478 | } | |
1479 | ||
252b5132 RH |
1480 | /* Subroutine of md_assemble to do the actual parsing. */ |
1481 | ||
a22b281c | 1482 | static int |
5a49b8ac | 1483 | sparc_ip (char *str, const struct sparc_opcode **pinsn) |
252b5132 RH |
1484 | { |
1485 | char *error_message = ""; | |
1486 | char *s; | |
1487 | const char *args; | |
1488 | char c; | |
1489 | const struct sparc_opcode *insn; | |
1490 | char *argsStart; | |
1491 | unsigned long opcode; | |
1492 | unsigned int mask = 0; | |
1493 | int match = 0; | |
1494 | int comma = 0; | |
1495 | int v9_arg_p; | |
a22b281c | 1496 | int special_case = SPECIAL_CASE_NONE; |
252b5132 RH |
1497 | |
1498 | s = str; | |
3882b010 | 1499 | if (ISLOWER (*s)) |
252b5132 RH |
1500 | { |
1501 | do | |
1502 | ++s; | |
6cda1326 | 1503 | while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_'); |
252b5132 RH |
1504 | } |
1505 | ||
1506 | switch (*s) | |
1507 | { | |
1508 | case '\0': | |
1509 | break; | |
1510 | ||
1511 | case ',': | |
1512 | comma = 1; | |
e0c6ed95 | 1513 | /* Fall through. */ |
252b5132 RH |
1514 | |
1515 | case ' ': | |
1516 | *s++ = '\0'; | |
1517 | break; | |
1518 | ||
1519 | default: | |
b0825cc2 DM |
1520 | as_bad (_("Unknown opcode: `%s'"), str); |
1521 | *pinsn = NULL; | |
1522 | return special_case; | |
252b5132 RH |
1523 | } |
1524 | insn = (struct sparc_opcode *) hash_find (op_hash, str); | |
1525 | *pinsn = insn; | |
1526 | if (insn == NULL) | |
1527 | { | |
1528 | as_bad (_("Unknown opcode: `%s'"), str); | |
a22b281c | 1529 | return special_case; |
252b5132 RH |
1530 | } |
1531 | if (comma) | |
1532 | { | |
1533 | *--s = ','; | |
1534 | } | |
1535 | ||
1536 | argsStart = s; | |
1537 | for (;;) | |
1538 | { | |
1539 | opcode = insn->match; | |
1540 | memset (&the_insn, '\0', sizeof (the_insn)); | |
1541 | the_insn.reloc = BFD_RELOC_NONE; | |
1542 | v9_arg_p = 0; | |
1543 | ||
e0c6ed95 AM |
1544 | /* Build the opcode, checking as we go to make sure that the |
1545 | operands match. */ | |
252b5132 RH |
1546 | for (args = insn->args;; ++args) |
1547 | { | |
1548 | switch (*args) | |
1549 | { | |
1550 | case 'K': | |
1551 | { | |
1552 | int kmask = 0; | |
1553 | ||
1554 | /* Parse a series of masks. */ | |
1555 | if (*s == '#') | |
1556 | { | |
1557 | while (*s == '#') | |
1558 | { | |
91d6fa6a | 1559 | int jmask; |
252b5132 RH |
1560 | |
1561 | if (! parse_keyword_arg (sparc_encode_membar, &s, | |
91d6fa6a | 1562 | &jmask)) |
252b5132 RH |
1563 | { |
1564 | error_message = _(": invalid membar mask name"); | |
1565 | goto error; | |
1566 | } | |
91d6fa6a | 1567 | kmask |= jmask; |
47926f60 KH |
1568 | while (*s == ' ') |
1569 | ++s; | |
252b5132 RH |
1570 | if (*s == '|' || *s == '+') |
1571 | ++s; | |
47926f60 KH |
1572 | while (*s == ' ') |
1573 | ++s; | |
252b5132 RH |
1574 | } |
1575 | } | |
1576 | else | |
1577 | { | |
1578 | if (! parse_const_expr_arg (&s, &kmask)) | |
1579 | { | |
1580 | error_message = _(": invalid membar mask expression"); | |
1581 | goto error; | |
1582 | } | |
1583 | if (kmask < 0 || kmask > 127) | |
1584 | { | |
1585 | error_message = _(": invalid membar mask number"); | |
1586 | goto error; | |
1587 | } | |
1588 | } | |
1589 | ||
1590 | opcode |= MEMBAR (kmask); | |
1591 | continue; | |
1592 | } | |
1593 | ||
19f7b010 JJ |
1594 | case '3': |
1595 | { | |
1596 | int smask = 0; | |
1597 | ||
1598 | if (! parse_const_expr_arg (&s, &smask)) | |
1599 | { | |
1600 | error_message = _(": invalid siam mode expression"); | |
1601 | goto error; | |
1602 | } | |
1603 | if (smask < 0 || smask > 7) | |
1604 | { | |
1605 | error_message = _(": invalid siam mode number"); | |
1606 | goto error; | |
1607 | } | |
1608 | opcode |= smask; | |
1609 | continue; | |
1610 | } | |
1611 | ||
252b5132 RH |
1612 | case '*': |
1613 | { | |
1614 | int fcn = 0; | |
1615 | ||
1616 | /* Parse a prefetch function. */ | |
1617 | if (*s == '#') | |
1618 | { | |
1619 | if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) | |
1620 | { | |
1621 | error_message = _(": invalid prefetch function name"); | |
1622 | goto error; | |
1623 | } | |
1624 | } | |
1625 | else | |
1626 | { | |
1627 | if (! parse_const_expr_arg (&s, &fcn)) | |
1628 | { | |
1629 | error_message = _(": invalid prefetch function expression"); | |
1630 | goto error; | |
1631 | } | |
1632 | if (fcn < 0 || fcn > 31) | |
1633 | { | |
1634 | error_message = _(": invalid prefetch function number"); | |
1635 | goto error; | |
1636 | } | |
1637 | } | |
1638 | opcode |= RD (fcn); | |
1639 | continue; | |
1640 | } | |
1641 | ||
1642 | case '!': | |
1643 | case '?': | |
1644 | /* Parse a sparc64 privileged register. */ | |
1645 | if (*s == '%') | |
1646 | { | |
1647 | struct priv_reg_entry *p = priv_reg_table; | |
e0c6ed95 | 1648 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1649 | |
1650 | s += 1; | |
1651 | while (p->name[0] > s[0]) | |
1652 | p++; | |
1653 | while (p->name[0] == s[0]) | |
1654 | { | |
1655 | len = strlen (p->name); | |
1656 | if (strncmp (p->name, s, len) == 0) | |
1657 | break; | |
1658 | p++; | |
1659 | } | |
1660 | if (p->name[0] != s[0]) | |
1661 | { | |
1662 | error_message = _(": unrecognizable privileged register"); | |
1663 | goto error; | |
1664 | } | |
1665 | if (*args == '?') | |
1666 | opcode |= (p->regnum << 14); | |
1667 | else | |
1668 | opcode |= (p->regnum << 25); | |
1669 | s += len; | |
1670 | continue; | |
1671 | } | |
1672 | else | |
1673 | { | |
1674 | error_message = _(": unrecognizable privileged register"); | |
1675 | goto error; | |
1676 | } | |
1677 | ||
10156f83 DM |
1678 | case '$': |
1679 | case '%': | |
1680 | /* Parse a sparc64 hyperprivileged register. */ | |
1681 | if (*s == '%') | |
1682 | { | |
1683 | struct priv_reg_entry *p = hpriv_reg_table; | |
1684 | unsigned int len = 9999999; /* Init to make gcc happy. */ | |
1685 | ||
1686 | s += 1; | |
1687 | while (p->name[0] > s[0]) | |
1688 | p++; | |
1689 | while (p->name[0] == s[0]) | |
1690 | { | |
1691 | len = strlen (p->name); | |
1692 | if (strncmp (p->name, s, len) == 0) | |
1693 | break; | |
1694 | p++; | |
1695 | } | |
1696 | if (p->name[0] != s[0]) | |
1697 | { | |
1698 | error_message = _(": unrecognizable hyperprivileged register"); | |
1699 | goto error; | |
1700 | } | |
1701 | if (*args == '$') | |
1702 | opcode |= (p->regnum << 14); | |
1703 | else | |
1704 | opcode |= (p->regnum << 25); | |
1705 | s += len; | |
1706 | continue; | |
1707 | } | |
1708 | else | |
1709 | { | |
1710 | error_message = _(": unrecognizable hyperprivileged register"); | |
1711 | goto error; | |
1712 | } | |
1713 | ||
252b5132 RH |
1714 | case '_': |
1715 | case '/': | |
19f7b010 | 1716 | /* Parse a v9a/v9b ancillary state register. */ |
252b5132 RH |
1717 | if (*s == '%') |
1718 | { | |
1719 | struct priv_reg_entry *p = v9a_asr_table; | |
e0c6ed95 | 1720 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1721 | |
1722 | s += 1; | |
1723 | while (p->name[0] > s[0]) | |
1724 | p++; | |
1725 | while (p->name[0] == s[0]) | |
1726 | { | |
1727 | len = strlen (p->name); | |
1728 | if (strncmp (p->name, s, len) == 0) | |
1729 | break; | |
1730 | p++; | |
1731 | } | |
1732 | if (p->name[0] != s[0]) | |
1733 | { | |
19f7b010 | 1734 | error_message = _(": unrecognizable v9a or v9b ancillary state register"); |
252b5132 RH |
1735 | goto error; |
1736 | } | |
1737 | if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) | |
1738 | { | |
1739 | error_message = _(": rd on write only ancillary state register"); | |
1740 | goto error; | |
e0c6ed95 | 1741 | } |
19f7b010 JJ |
1742 | if (p->regnum >= 24 |
1743 | && (insn->architecture | |
1744 | & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) | |
1745 | { | |
1746 | /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ | |
1747 | error_message = _(": unrecognizable v9a ancillary state register"); | |
1748 | goto error; | |
1749 | } | |
252b5132 RH |
1750 | if (*args == '/') |
1751 | opcode |= (p->regnum << 14); | |
1752 | else | |
1753 | opcode |= (p->regnum << 25); | |
1754 | s += len; | |
1755 | continue; | |
1756 | } | |
1757 | else | |
1758 | { | |
19f7b010 | 1759 | error_message = _(": unrecognizable v9a or v9b ancillary state register"); |
252b5132 RH |
1760 | goto error; |
1761 | } | |
1762 | ||
1763 | case 'M': | |
1764 | case 'm': | |
1765 | if (strncmp (s, "%asr", 4) == 0) | |
1766 | { | |
1767 | s += 4; | |
1768 | ||
3882b010 | 1769 | if (ISDIGIT (*s)) |
252b5132 RH |
1770 | { |
1771 | long num = 0; | |
1772 | ||
3882b010 | 1773 | while (ISDIGIT (*s)) |
252b5132 RH |
1774 | { |
1775 | num = num * 10 + *s - '0'; | |
1776 | ++s; | |
1777 | } | |
1778 | ||
1779 | if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
1780 | { | |
1781 | if (num < 16 || 31 < num) | |
1782 | { | |
1783 | error_message = _(": asr number must be between 16 and 31"); | |
1784 | goto error; | |
1785 | } | |
1786 | } | |
1787 | else | |
1788 | { | |
1789 | if (num < 0 || 31 < num) | |
1790 | { | |
1791 | error_message = _(": asr number must be between 0 and 31"); | |
1792 | goto error; | |
1793 | } | |
1794 | } | |
1795 | ||
1796 | opcode |= (*args == 'M' ? RS1 (num) : RD (num)); | |
1797 | continue; | |
1798 | } | |
1799 | else | |
1800 | { | |
1801 | error_message = _(": expecting %asrN"); | |
1802 | goto error; | |
1803 | } | |
e0c6ed95 | 1804 | } /* if %asr */ |
252b5132 RH |
1805 | break; |
1806 | ||
1807 | case 'I': | |
1808 | the_insn.reloc = BFD_RELOC_SPARC_11; | |
1809 | goto immediate; | |
1810 | ||
1811 | case 'j': | |
1812 | the_insn.reloc = BFD_RELOC_SPARC_10; | |
1813 | goto immediate; | |
1814 | ||
6cda1326 DM |
1815 | case ')': |
1816 | if (*s == ' ') | |
1817 | s++; | |
1818 | if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2])) | |
1819 | || ISDIGIT (*s)) | |
1820 | { | |
1821 | long num = 0; | |
1822 | ||
1823 | if (s[0] == '0' && s[1] == 'x') | |
1824 | { | |
1825 | s += 2; | |
1826 | while (ISXDIGIT (*s)) | |
1827 | { | |
1828 | num <<= 4; | |
1829 | num |= hex_value (*s); | |
1830 | ++s; | |
1831 | } | |
1832 | } | |
1833 | else | |
1834 | { | |
1835 | while (ISDIGIT (*s)) | |
1836 | { | |
1837 | num = num * 10 + *s - '0'; | |
1838 | ++s; | |
1839 | } | |
1840 | } | |
1841 | if (num < 0 || num > 31) | |
1842 | { | |
1843 | error_message = _(": crypto immediate must be between 0 and 31"); | |
1844 | goto error; | |
1845 | } | |
1846 | ||
1847 | opcode |= RS3 (num); | |
1848 | continue; | |
1849 | } | |
1850 | else | |
1851 | { | |
1852 | error_message = _(": expecting crypto immediate"); | |
1853 | goto error; | |
1854 | } | |
1855 | ||
252b5132 RH |
1856 | case 'X': |
1857 | /* V8 systems don't understand BFD_RELOC_SPARC_5. */ | |
1858 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1859 | the_insn.reloc = BFD_RELOC_SPARC_5; | |
1860 | else | |
1861 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1862 | /* These fields are unsigned, but for upward compatibility, | |
1863 | allow negative values as well. */ | |
1864 | goto immediate; | |
1865 | ||
1866 | case 'Y': | |
1867 | /* V8 systems don't understand BFD_RELOC_SPARC_6. */ | |
1868 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1869 | the_insn.reloc = BFD_RELOC_SPARC_6; | |
1870 | else | |
1871 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1872 | /* These fields are unsigned, but for upward compatibility, | |
1873 | allow negative values as well. */ | |
1874 | goto immediate; | |
1875 | ||
1876 | case 'k': | |
1877 | the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; | |
1878 | the_insn.pcrel = 1; | |
1879 | goto immediate; | |
1880 | ||
2615994e DM |
1881 | case '=': |
1882 | the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10; | |
1883 | the_insn.pcrel = 1; | |
1884 | goto immediate; | |
1885 | ||
252b5132 RH |
1886 | case 'G': |
1887 | the_insn.reloc = BFD_RELOC_SPARC_WDISP19; | |
1888 | the_insn.pcrel = 1; | |
1889 | goto immediate; | |
1890 | ||
1891 | case 'N': | |
1892 | if (*s == 'p' && s[1] == 'n') | |
1893 | { | |
1894 | s += 2; | |
1895 | continue; | |
1896 | } | |
1897 | break; | |
1898 | ||
1899 | case 'T': | |
1900 | if (*s == 'p' && s[1] == 't') | |
1901 | { | |
1902 | s += 2; | |
1903 | continue; | |
1904 | } | |
1905 | break; | |
1906 | ||
1907 | case 'z': | |
1908 | if (*s == ' ') | |
1909 | { | |
1910 | ++s; | |
1911 | } | |
1912 | if (strncmp (s, "%icc", 4) == 0) | |
1913 | { | |
1914 | s += 4; | |
1915 | continue; | |
1916 | } | |
1917 | break; | |
1918 | ||
1919 | case 'Z': | |
1920 | if (*s == ' ') | |
1921 | { | |
1922 | ++s; | |
1923 | } | |
1924 | if (strncmp (s, "%xcc", 4) == 0) | |
1925 | { | |
1926 | s += 4; | |
1927 | continue; | |
1928 | } | |
1929 | break; | |
1930 | ||
1931 | case '6': | |
1932 | if (*s == ' ') | |
1933 | { | |
1934 | ++s; | |
1935 | } | |
1936 | if (strncmp (s, "%fcc0", 5) == 0) | |
1937 | { | |
1938 | s += 5; | |
1939 | continue; | |
1940 | } | |
1941 | break; | |
1942 | ||
1943 | case '7': | |
1944 | if (*s == ' ') | |
1945 | { | |
1946 | ++s; | |
1947 | } | |
1948 | if (strncmp (s, "%fcc1", 5) == 0) | |
1949 | { | |
1950 | s += 5; | |
1951 | continue; | |
1952 | } | |
1953 | break; | |
1954 | ||
1955 | case '8': | |
1956 | if (*s == ' ') | |
1957 | { | |
1958 | ++s; | |
1959 | } | |
1960 | if (strncmp (s, "%fcc2", 5) == 0) | |
1961 | { | |
1962 | s += 5; | |
1963 | continue; | |
1964 | } | |
1965 | break; | |
1966 | ||
1967 | case '9': | |
1968 | if (*s == ' ') | |
1969 | { | |
1970 | ++s; | |
1971 | } | |
1972 | if (strncmp (s, "%fcc3", 5) == 0) | |
1973 | { | |
1974 | s += 5; | |
1975 | continue; | |
1976 | } | |
1977 | break; | |
1978 | ||
1979 | case 'P': | |
1980 | if (strncmp (s, "%pc", 3) == 0) | |
1981 | { | |
1982 | s += 3; | |
1983 | continue; | |
1984 | } | |
1985 | break; | |
1986 | ||
1987 | case 'W': | |
1988 | if (strncmp (s, "%tick", 5) == 0) | |
1989 | { | |
1990 | s += 5; | |
1991 | continue; | |
1992 | } | |
1993 | break; | |
1994 | ||
e0c6ed95 | 1995 | case '\0': /* End of args. */ |
b9734f35 | 1996 | if (s[0] == ',' && s[1] == '%') |
252b5132 | 1997 | { |
739f7f82 | 1998 | static const struct ops |
dfeb0666 | 1999 | { |
b9734f35 JJ |
2000 | /* The name as it appears in assembler. */ |
2001 | char *name; | |
2002 | /* strlen (name), precomputed for speed */ | |
2003 | int len; | |
2004 | /* The reloc this pseudo-op translates to. */ | |
2005 | int reloc; | |
739f7f82 DM |
2006 | /* 1 if tls call. */ |
2007 | int tls_call; | |
dfeb0666 | 2008 | } |
739f7f82 | 2009 | ops[] = |
dfeb0666 | 2010 | { |
b9734f35 JJ |
2011 | { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 }, |
2012 | { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 }, | |
2013 | { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 }, | |
2014 | { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 }, | |
2015 | { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 }, | |
2016 | { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 }, | |
2017 | { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 }, | |
dfeb0666 | 2018 | { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }, |
739f7f82 | 2019 | { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 }, |
dfeb0666 | 2020 | { NULL, 0, 0, 0 } |
b9734f35 | 2021 | }; |
739f7f82 | 2022 | const struct ops *o; |
b9734f35 JJ |
2023 | char *s1; |
2024 | int npar = 0; | |
2025 | ||
739f7f82 | 2026 | for (o = ops; o->name; o++) |
b9734f35 JJ |
2027 | if (strncmp (s + 2, o->name, o->len) == 0) |
2028 | break; | |
2029 | if (o->name == NULL) | |
2030 | break; | |
2031 | ||
2032 | if (s[o->len + 2] != '(') | |
2033 | { | |
2034 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
2035 | return special_case; | |
2036 | } | |
2037 | ||
739f7f82 | 2038 | if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE) |
b9734f35 JJ |
2039 | { |
2040 | as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), | |
2041 | o->name); | |
2042 | return special_case; | |
2043 | } | |
2044 | ||
739f7f82 | 2045 | if (o->tls_call |
b9734f35 JJ |
2046 | && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 |
2047 | || the_insn.exp.X_add_number != 0 | |
2048 | || the_insn.exp.X_add_symbol | |
2049 | != symbol_find_or_make ("__tls_get_addr"))) | |
2050 | { | |
2051 | as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), | |
2052 | o->name); | |
2053 | return special_case; | |
2054 | } | |
2055 | ||
2056 | the_insn.reloc = o->reloc; | |
2057 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); | |
2058 | s += o->len + 3; | |
2059 | ||
2060 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2061 | if (*s1 == '(') | |
2062 | npar++; | |
2063 | else if (*s1 == ')') | |
2064 | { | |
2065 | if (!npar) | |
2066 | break; | |
2067 | npar--; | |
2068 | } | |
2069 | ||
2070 | if (*s1 != ')') | |
2071 | { | |
2072 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
2073 | return special_case; | |
2074 | } | |
2075 | ||
2076 | *s1 = '\0'; | |
2077 | (void) get_expression (s); | |
2078 | *s1 = ')'; | |
2079 | s = s1 + 1; | |
252b5132 | 2080 | } |
b9734f35 JJ |
2081 | if (*s == '\0') |
2082 | match = 1; | |
252b5132 RH |
2083 | break; |
2084 | ||
2085 | case '+': | |
2086 | if (*s == '+') | |
2087 | { | |
2088 | ++s; | |
2089 | continue; | |
2090 | } | |
2091 | if (*s == '-') | |
2092 | { | |
2093 | continue; | |
2094 | } | |
2095 | break; | |
2096 | ||
e0c6ed95 | 2097 | case '[': /* These must match exactly. */ |
252b5132 RH |
2098 | case ']': |
2099 | case ',': | |
2100 | case ' ': | |
2101 | if (*s++ == *args) | |
2102 | continue; | |
2103 | break; | |
2104 | ||
e0c6ed95 | 2105 | case '#': /* Must be at least one digit. */ |
3882b010 | 2106 | if (ISDIGIT (*s++)) |
252b5132 | 2107 | { |
3882b010 | 2108 | while (ISDIGIT (*s)) |
252b5132 RH |
2109 | { |
2110 | ++s; | |
2111 | } | |
2112 | continue; | |
2113 | } | |
2114 | break; | |
2115 | ||
e0c6ed95 | 2116 | case 'C': /* Coprocessor state register. */ |
252b5132 RH |
2117 | if (strncmp (s, "%csr", 4) == 0) |
2118 | { | |
2119 | s += 4; | |
2120 | continue; | |
2121 | } | |
2122 | break; | |
2123 | ||
e0c6ed95 | 2124 | case 'b': /* Next operand is a coprocessor register. */ |
252b5132 RH |
2125 | case 'c': |
2126 | case 'D': | |
3882b010 | 2127 | if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) |
252b5132 RH |
2128 | { |
2129 | mask = *s++; | |
3882b010 | 2130 | if (ISDIGIT (*s)) |
252b5132 RH |
2131 | { |
2132 | mask = 10 * (mask - '0') + (*s++ - '0'); | |
2133 | if (mask >= 32) | |
2134 | { | |
2135 | break; | |
2136 | } | |
2137 | } | |
2138 | else | |
2139 | { | |
2140 | mask -= '0'; | |
2141 | } | |
2142 | switch (*args) | |
2143 | { | |
2144 | ||
2145 | case 'b': | |
2146 | opcode |= mask << 14; | |
2147 | continue; | |
2148 | ||
2149 | case 'c': | |
2150 | opcode |= mask; | |
2151 | continue; | |
2152 | ||
2153 | case 'D': | |
2154 | opcode |= mask << 25; | |
2155 | continue; | |
2156 | } | |
2157 | } | |
2158 | break; | |
2159 | ||
2160 | case 'r': /* next operand must be a register */ | |
2161 | case 'O': | |
2162 | case '1': | |
2163 | case '2': | |
2164 | case 'd': | |
2165 | if (*s++ == '%') | |
2166 | { | |
2167 | switch (c = *s++) | |
2168 | { | |
2169 | ||
2170 | case 'f': /* frame pointer */ | |
2171 | if (*s++ == 'p') | |
2172 | { | |
2173 | mask = 0x1e; | |
2174 | break; | |
2175 | } | |
2176 | goto error; | |
2177 | ||
2178 | case 'g': /* global register */ | |
a22b281c RH |
2179 | c = *s++; |
2180 | if (isoctal (c)) | |
252b5132 RH |
2181 | { |
2182 | mask = c - '0'; | |
2183 | break; | |
2184 | } | |
2185 | goto error; | |
2186 | ||
2187 | case 'i': /* in register */ | |
a22b281c RH |
2188 | c = *s++; |
2189 | if (isoctal (c)) | |
252b5132 RH |
2190 | { |
2191 | mask = c - '0' + 24; | |
2192 | break; | |
2193 | } | |
2194 | goto error; | |
2195 | ||
2196 | case 'l': /* local register */ | |
a22b281c RH |
2197 | c = *s++; |
2198 | if (isoctal (c)) | |
252b5132 RH |
2199 | { |
2200 | mask = (c - '0' + 16); | |
2201 | break; | |
2202 | } | |
2203 | goto error; | |
2204 | ||
2205 | case 'o': /* out register */ | |
a22b281c RH |
2206 | c = *s++; |
2207 | if (isoctal (c)) | |
252b5132 RH |
2208 | { |
2209 | mask = (c - '0' + 8); | |
2210 | break; | |
2211 | } | |
2212 | goto error; | |
2213 | ||
2214 | case 's': /* stack pointer */ | |
2215 | if (*s++ == 'p') | |
2216 | { | |
2217 | mask = 0xe; | |
2218 | break; | |
2219 | } | |
2220 | goto error; | |
2221 | ||
2222 | case 'r': /* any register */ | |
3882b010 | 2223 | if (!ISDIGIT ((c = *s++))) |
252b5132 RH |
2224 | { |
2225 | goto error; | |
2226 | } | |
2227 | /* FALLTHROUGH */ | |
2228 | case '0': | |
2229 | case '1': | |
2230 | case '2': | |
2231 | case '3': | |
2232 | case '4': | |
2233 | case '5': | |
2234 | case '6': | |
2235 | case '7': | |
2236 | case '8': | |
2237 | case '9': | |
3882b010 | 2238 | if (ISDIGIT (*s)) |
252b5132 RH |
2239 | { |
2240 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) | |
2241 | { | |
2242 | goto error; | |
2243 | } | |
2244 | } | |
2245 | else | |
2246 | { | |
2247 | c -= '0'; | |
2248 | } | |
2249 | mask = c; | |
2250 | break; | |
2251 | ||
2252 | default: | |
2253 | goto error; | |
2254 | } | |
2255 | ||
6d8809aa | 2256 | if ((mask & ~1) == 2 && sparc_arch_size == 64 |
e0c6ed95 | 2257 | && no_undeclared_regs && ! globals[mask]) |
79bd78be | 2258 | as_bad (_("detected global register use not covered by .register pseudo-op")); |
6d8809aa | 2259 | |
252b5132 RH |
2260 | /* Got the register, now figure out where |
2261 | it goes in the opcode. */ | |
2262 | switch (*args) | |
2263 | { | |
2264 | case '1': | |
2265 | opcode |= mask << 14; | |
2266 | continue; | |
2267 | ||
2268 | case '2': | |
2269 | opcode |= mask; | |
2270 | continue; | |
2271 | ||
2272 | case 'd': | |
2273 | opcode |= mask << 25; | |
2274 | continue; | |
2275 | ||
2276 | case 'r': | |
2277 | opcode |= (mask << 25) | (mask << 14); | |
2278 | continue; | |
2279 | ||
2280 | case 'O': | |
2281 | opcode |= (mask << 25) | (mask << 0); | |
2282 | continue; | |
2283 | } | |
2284 | } | |
2285 | break; | |
2286 | ||
2287 | case 'e': /* next operand is a floating point register */ | |
2288 | case 'v': | |
2289 | case 'V': | |
2290 | ||
2291 | case 'f': | |
2292 | case 'B': | |
2293 | case 'R': | |
2294 | ||
ea783ef3 DM |
2295 | case '4': |
2296 | case '5': | |
2297 | ||
252b5132 RH |
2298 | case 'g': |
2299 | case 'H': | |
2300 | case 'J': | |
2301 | { | |
2302 | char format; | |
2303 | ||
2304 | if (*s++ == '%' | |
2305 | && ((format = *s) == 'f') | |
3882b010 | 2306 | && ISDIGIT (*++s)) |
252b5132 | 2307 | { |
3882b010 | 2308 | for (mask = 0; ISDIGIT (*s); ++s) |
252b5132 RH |
2309 | { |
2310 | mask = 10 * mask + (*s - '0'); | |
2311 | } /* read the number */ | |
2312 | ||
2313 | if ((*args == 'v' | |
2314 | || *args == 'B' | |
ea783ef3 | 2315 | || *args == '5' |
252b5132 RH |
2316 | || *args == 'H') |
2317 | && (mask & 1)) | |
2318 | { | |
2319 | break; | |
2320 | } /* register must be even numbered */ | |
2321 | ||
2322 | if ((*args == 'V' | |
2323 | || *args == 'R' | |
2324 | || *args == 'J') | |
2325 | && (mask & 3)) | |
2326 | { | |
2327 | break; | |
2328 | } /* register must be multiple of 4 */ | |
2329 | ||
2330 | if (mask >= 64) | |
2331 | { | |
2332 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2333 | error_message = _(": There are only 64 f registers; [0-63]"); | |
2334 | else | |
2335 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2336 | goto error; | |
2337 | } /* on error */ | |
2338 | else if (mask >= 32) | |
2339 | { | |
2340 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2341 | { | |
26664553 JJ |
2342 | if (*args == 'e' || *args == 'f' || *args == 'g') |
2343 | { | |
2344 | error_message | |
2345 | = _(": There are only 32 single precision f registers; [0-31]"); | |
2346 | goto error; | |
2347 | } | |
252b5132 RH |
2348 | v9_arg_p = 1; |
2349 | mask -= 31; /* wrap high bit */ | |
2350 | } | |
2351 | else | |
2352 | { | |
2353 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2354 | goto error; | |
2355 | } | |
2356 | } | |
2357 | } | |
2358 | else | |
2359 | { | |
2360 | break; | |
ab3e48dc | 2361 | } /* if not an 'f' register. */ |
252b5132 RH |
2362 | |
2363 | switch (*args) | |
2364 | { | |
2365 | case 'v': | |
2366 | case 'V': | |
2367 | case 'e': | |
2368 | opcode |= RS1 (mask); | |
2369 | continue; | |
2370 | ||
252b5132 RH |
2371 | case 'f': |
2372 | case 'B': | |
2373 | case 'R': | |
2374 | opcode |= RS2 (mask); | |
2375 | continue; | |
2376 | ||
ea783ef3 DM |
2377 | case '4': |
2378 | case '5': | |
2379 | opcode |= RS3 (mask); | |
2380 | continue; | |
2381 | ||
252b5132 RH |
2382 | case 'g': |
2383 | case 'H': | |
2384 | case 'J': | |
2385 | opcode |= RD (mask); | |
2386 | continue; | |
ab3e48dc | 2387 | } /* Pack it in. */ |
252b5132 RH |
2388 | |
2389 | know (0); | |
2390 | break; | |
ab3e48dc | 2391 | } /* float arg */ |
252b5132 RH |
2392 | |
2393 | case 'F': | |
2394 | if (strncmp (s, "%fsr", 4) == 0) | |
2395 | { | |
2396 | s += 4; | |
2397 | continue; | |
2398 | } | |
2399 | break; | |
2400 | ||
ea783ef3 DM |
2401 | case '(': |
2402 | if (strncmp (s, "%efsr", 5) == 0) | |
2403 | { | |
2404 | s += 5; | |
2405 | continue; | |
2406 | } | |
2407 | break; | |
2408 | ||
ab3e48dc KH |
2409 | case '0': /* 64 bit immediate (set, setsw, setx insn) */ |
2410 | the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ | |
252b5132 RH |
2411 | goto immediate; |
2412 | ||
ab3e48dc | 2413 | case 'l': /* 22 bit PC relative immediate */ |
252b5132 RH |
2414 | the_insn.reloc = BFD_RELOC_SPARC_WDISP22; |
2415 | the_insn.pcrel = 1; | |
2416 | goto immediate; | |
2417 | ||
ab3e48dc | 2418 | case 'L': /* 30 bit immediate */ |
252b5132 RH |
2419 | the_insn.reloc = BFD_RELOC_32_PCREL_S2; |
2420 | the_insn.pcrel = 1; | |
2421 | goto immediate; | |
2422 | ||
63fab58c | 2423 | case 'h': |
ab3e48dc | 2424 | case 'n': /* 22 bit immediate */ |
252b5132 RH |
2425 | the_insn.reloc = BFD_RELOC_SPARC22; |
2426 | goto immediate; | |
2427 | ||
ab3e48dc | 2428 | case 'i': /* 13 bit immediate */ |
252b5132 RH |
2429 | the_insn.reloc = BFD_RELOC_SPARC13; |
2430 | ||
2431 | /* fallthrough */ | |
2432 | ||
2433 | immediate: | |
2434 | if (*s == ' ') | |
2435 | s++; | |
2436 | ||
cf9a1301 RH |
2437 | { |
2438 | char *s1; | |
2439 | char *op_arg = NULL; | |
30eb9c17 | 2440 | static expressionS op_exp; |
cf9a1301 RH |
2441 | bfd_reloc_code_real_type old_reloc = the_insn.reloc; |
2442 | ||
2443 | /* Check for %hi, etc. */ | |
2444 | if (*s == '%') | |
2445 | { | |
2446 | static const struct ops { | |
2447 | /* The name as it appears in assembler. */ | |
2448 | char *name; | |
2449 | /* strlen (name), precomputed for speed */ | |
2450 | int len; | |
2451 | /* The reloc this pseudo-op translates to. */ | |
2452 | int reloc; | |
2453 | /* Non-zero if for v9 only. */ | |
2454 | int v9_p; | |
2455 | /* Non-zero if can be used in pc-relative contexts. */ | |
2456 | int pcrel_p;/*FIXME:wip*/ | |
2457 | } ops[] = { | |
2458 | /* hix/lox must appear before hi/lo so %hix won't be | |
2459 | mistaken for %hi. */ | |
2460 | { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, | |
2461 | { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, | |
2462 | { "hi", 2, BFD_RELOC_HI22, 0, 1 }, | |
2463 | { "lo", 2, BFD_RELOC_LO10, 0, 1 }, | |
14865d76 DM |
2464 | { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 }, |
2465 | { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 }, | |
cf9a1301 RH |
2466 | { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, |
2467 | { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, | |
2468 | { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, | |
2615994e DM |
2469 | { "h34", 3, BFD_RELOC_SPARC_H34, 1, 0 }, |
2470 | { "l34", 3, BFD_RELOC_SPARC_L44, 1, 0 }, | |
cf9a1301 RH |
2471 | { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, |
2472 | { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, | |
2473 | { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, | |
2474 | { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, | |
2475 | { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, | |
b9734f35 JJ |
2476 | { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 }, |
2477 | { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 }, | |
2478 | { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 }, | |
2479 | { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 }, | |
2480 | { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0, | |
2481 | 0 }, | |
2482 | { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0, | |
2483 | 0 }, | |
2484 | { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 }, | |
2485 | { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 }, | |
2486 | { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 }, | |
2487 | { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 }, | |
739f7f82 DM |
2488 | { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22, |
2489 | 0, 0 }, | |
2490 | { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10, | |
2491 | 0, 0 }, | |
c2158c24 | 2492 | { NULL, 0, 0, 0, 0 } |
cf9a1301 RH |
2493 | }; |
2494 | const struct ops *o; | |
e0c6ed95 | 2495 | |
cf9a1301 RH |
2496 | for (o = ops; o->name; o++) |
2497 | if (strncmp (s + 1, o->name, o->len) == 0) | |
2498 | break; | |
2499 | if (o->name == NULL) | |
252b5132 | 2500 | break; |
e0c6ed95 | 2501 | |
cf9a1301 RH |
2502 | if (s[o->len + 1] != '(') |
2503 | { | |
2504 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
a22b281c | 2505 | return special_case; |
cf9a1301 | 2506 | } |
252b5132 | 2507 | |
cf9a1301 RH |
2508 | op_arg = o->name; |
2509 | the_insn.reloc = o->reloc; | |
2510 | s += o->len + 2; | |
2511 | v9_arg_p = o->v9_p; | |
2512 | } | |
2513 | ||
2514 | /* Note that if the get_expression() fails, we will still | |
2515 | have created U entries in the symbol table for the | |
2516 | 'symbols' in the input string. Try not to create U | |
2517 | symbols for registers, etc. */ | |
252b5132 | 2518 | |
252b5132 RH |
2519 | /* This stuff checks to see if the expression ends in |
2520 | +%reg. If it does, it removes the register from | |
2521 | the expression, and re-sets 's' to point to the | |
2522 | right place. */ | |
2523 | ||
cf9a1301 RH |
2524 | if (op_arg) |
2525 | { | |
2526 | int npar = 0; | |
2527 | ||
2528 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2529 | if (*s1 == '(') | |
2530 | npar++; | |
2531 | else if (*s1 == ')') | |
2532 | { | |
2533 | if (!npar) | |
2534 | break; | |
2535 | npar--; | |
2536 | } | |
2537 | ||
2538 | if (*s1 != ')') | |
2539 | { | |
2540 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); | |
a22b281c | 2541 | return special_case; |
cf9a1301 | 2542 | } |
e0c6ed95 | 2543 | |
cf9a1301 RH |
2544 | *s1 = '\0'; |
2545 | (void) get_expression (s); | |
2546 | *s1 = ')'; | |
2547 | s = s1 + 1; | |
2548 | if (*s == ',' || *s == ']' || !*s) | |
2549 | continue; | |
2550 | if (*s != '+' && *s != '-') | |
2551 | { | |
2552 | as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); | |
a22b281c | 2553 | return special_case; |
cf9a1301 RH |
2554 | } |
2555 | *s1 = '0'; | |
2556 | s = s1; | |
2557 | op_exp = the_insn.exp; | |
e0c6ed95 | 2558 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
cf9a1301 | 2559 | } |
252b5132 | 2560 | |
e0c6ed95 AM |
2561 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) |
2562 | ; | |
252b5132 | 2563 | |
3882b010 | 2564 | if (s1 != s && ISDIGIT (s1[-1])) |
252b5132 RH |
2565 | { |
2566 | if (s1[-2] == '%' && s1[-3] == '+') | |
cf9a1301 | 2567 | s1 -= 3; |
f124dd4f | 2568 | else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') |
cf9a1301 | 2569 | s1 -= 4; |
f124dd4f DM |
2570 | else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+') |
2571 | s1 -= 5; | |
cf9a1301 RH |
2572 | else |
2573 | s1 = NULL; | |
2574 | if (s1) | |
252b5132 | 2575 | { |
252b5132 | 2576 | *s1 = '\0'; |
1eb7027c RH |
2577 | if (op_arg && s1 == s + 1) |
2578 | the_insn.exp.X_op = O_absent; | |
2579 | else | |
2580 | (void) get_expression (s); | |
252b5132 | 2581 | *s1 = '+'; |
cf9a1301 RH |
2582 | if (op_arg) |
2583 | *s = ')'; | |
252b5132 | 2584 | s = s1; |
252b5132 | 2585 | } |
cf9a1301 RH |
2586 | } |
2587 | else | |
2588 | s1 = NULL; | |
2589 | ||
2590 | if (!s1) | |
2591 | { | |
2592 | (void) get_expression (s); | |
2593 | if (op_arg) | |
2594 | *s = ')'; | |
2595 | s = expr_end; | |
2596 | } | |
2597 | ||
2598 | if (op_arg) | |
2599 | { | |
2600 | the_insn.exp2 = the_insn.exp; | |
2601 | the_insn.exp = op_exp; | |
2602 | if (the_insn.exp2.X_op == O_absent) | |
2603 | the_insn.exp2.X_op = O_illegal; | |
2604 | else if (the_insn.exp.X_op == O_absent) | |
252b5132 | 2605 | { |
cf9a1301 RH |
2606 | the_insn.exp = the_insn.exp2; |
2607 | the_insn.exp2.X_op = O_illegal; | |
2608 | } | |
2609 | else if (the_insn.exp.X_op == O_constant) | |
2610 | { | |
2611 | valueT val = the_insn.exp.X_add_number; | |
2612 | switch (the_insn.reloc) | |
2613 | { | |
1b50c718 ILT |
2614 | default: |
2615 | break; | |
2616 | ||
cf9a1301 RH |
2617 | case BFD_RELOC_SPARC_HH22: |
2618 | val = BSR (val, 32); | |
e0c6ed95 | 2619 | /* Fall through. */ |
cf9a1301 RH |
2620 | |
2621 | case BFD_RELOC_SPARC_LM22: | |
2622 | case BFD_RELOC_HI22: | |
2623 | val = (val >> 10) & 0x3fffff; | |
2624 | break; | |
2625 | ||
2626 | case BFD_RELOC_SPARC_HM10: | |
2627 | val = BSR (val, 32); | |
e0c6ed95 | 2628 | /* Fall through. */ |
cf9a1301 RH |
2629 | |
2630 | case BFD_RELOC_LO10: | |
2631 | val &= 0x3ff; | |
2632 | break; | |
2633 | ||
2615994e DM |
2634 | case BFD_RELOC_SPARC_H34: |
2635 | val >>= 12; | |
2636 | val &= 0x3fffff; | |
2637 | break; | |
2638 | ||
cf9a1301 RH |
2639 | case BFD_RELOC_SPARC_H44: |
2640 | val >>= 22; | |
2641 | val &= 0x3fffff; | |
2642 | break; | |
2643 | ||
2644 | case BFD_RELOC_SPARC_M44: | |
2645 | val >>= 12; | |
2646 | val &= 0x3ff; | |
2647 | break; | |
2648 | ||
2649 | case BFD_RELOC_SPARC_L44: | |
2650 | val &= 0xfff; | |
2651 | break; | |
2652 | ||
2653 | case BFD_RELOC_SPARC_HIX22: | |
ab3e48dc | 2654 | val = ~val; |
cf9a1301 RH |
2655 | val = (val >> 10) & 0x3fffff; |
2656 | break; | |
2657 | ||
2658 | case BFD_RELOC_SPARC_LOX10: | |
2659 | val = (val & 0x3ff) | 0x1c00; | |
2660 | break; | |
2661 | } | |
2662 | the_insn.exp = the_insn.exp2; | |
2663 | the_insn.exp.X_add_number += val; | |
2664 | the_insn.exp2.X_op = O_illegal; | |
2665 | the_insn.reloc = old_reloc; | |
2666 | } | |
2667 | else if (the_insn.exp2.X_op != O_constant) | |
2668 | { | |
2669 | as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); | |
a22b281c | 2670 | return special_case; |
cf9a1301 RH |
2671 | } |
2672 | else | |
2673 | { | |
dabe3bbc | 2674 | if (old_reloc != BFD_RELOC_SPARC13 |
cf9a1301 RH |
2675 | || the_insn.reloc != BFD_RELOC_LO10 |
2676 | || sparc_arch_size != 64 | |
2677 | || sparc_pic_code) | |
2678 | { | |
2679 | as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); | |
a22b281c | 2680 | return special_case; |
cf9a1301 RH |
2681 | } |
2682 | the_insn.reloc = BFD_RELOC_SPARC_OLO10; | |
252b5132 RH |
2683 | } |
2684 | } | |
2685 | } | |
252b5132 RH |
2686 | /* Check for constants that don't require emitting a reloc. */ |
2687 | if (the_insn.exp.X_op == O_constant | |
2688 | && the_insn.exp.X_add_symbol == 0 | |
2689 | && the_insn.exp.X_op_symbol == 0) | |
2690 | { | |
2691 | /* For pc-relative call instructions, we reject | |
2692 | constants to get better code. */ | |
2693 | if (the_insn.pcrel | |
2694 | && the_insn.reloc == BFD_RELOC_32_PCREL_S2 | |
2695 | && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) | |
2696 | { | |
2697 | error_message = _(": PC-relative operand can't be a constant"); | |
2698 | goto error; | |
2699 | } | |
2700 | ||
b9734f35 JJ |
2701 | if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 |
2702 | && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) | |
2703 | { | |
2704 | error_message = _(": TLS operand can't be a constant"); | |
2705 | goto error; | |
2706 | } | |
2707 | ||
55cf6793 | 2708 | /* Constants that won't fit are checked in md_apply_fix |
252b5132 RH |
2709 | and bfd_install_relocation. |
2710 | ??? It would be preferable to install the constants | |
2711 | into the insn here and save having to create a fixS | |
2712 | for each one. There already exists code to handle | |
55cf6793 | 2713 | all the various cases (e.g. in md_apply_fix and |
252b5132 RH |
2714 | bfd_install_relocation) so duplicating all that code |
2715 | here isn't right. */ | |
698544e1 DM |
2716 | |
2717 | /* This is a special case to handle cbcond instructions | |
2718 | properly, which can need two relocations. The first | |
2719 | one is for the 5-bit immediate field and the latter | |
2720 | is going to be for the WDISP10 branch part. We | |
2721 | handle the R_SPARC_5 immediate directly here so that | |
2722 | we don't need to add support for multiple relocations | |
2723 | in one instruction just yet. */ | |
2724 | if (the_insn.reloc == BFD_RELOC_SPARC_5) | |
2725 | { | |
2726 | valueT val = the_insn.exp.X_add_number; | |
2727 | ||
2728 | if (! in_bitfield_range (val, 0x1f)) | |
2729 | { | |
2730 | error_message = _(": Immediate value in cbcond is out of range."); | |
2731 | goto error; | |
2732 | } | |
2733 | opcode |= val & 0x1f; | |
2734 | the_insn.reloc = BFD_RELOC_NONE; | |
2735 | } | |
252b5132 RH |
2736 | } |
2737 | ||
2738 | continue; | |
2739 | ||
2740 | case 'a': | |
2741 | if (*s++ == 'a') | |
2742 | { | |
2743 | opcode |= ANNUL; | |
2744 | continue; | |
2745 | } | |
2746 | break; | |
2747 | ||
2748 | case 'A': | |
2749 | { | |
2750 | int asi = 0; | |
2751 | ||
2752 | /* Parse an asi. */ | |
2753 | if (*s == '#') | |
2754 | { | |
2755 | if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) | |
2756 | { | |
2757 | error_message = _(": invalid ASI name"); | |
2758 | goto error; | |
2759 | } | |
2760 | } | |
2761 | else | |
2762 | { | |
2763 | if (! parse_const_expr_arg (&s, &asi)) | |
2764 | { | |
2765 | error_message = _(": invalid ASI expression"); | |
2766 | goto error; | |
2767 | } | |
2768 | if (asi < 0 || asi > 255) | |
2769 | { | |
2770 | error_message = _(": invalid ASI number"); | |
2771 | goto error; | |
2772 | } | |
2773 | } | |
2774 | opcode |= ASI (asi); | |
2775 | continue; | |
e0c6ed95 | 2776 | } /* Alternate space. */ |
252b5132 RH |
2777 | |
2778 | case 'p': | |
2779 | if (strncmp (s, "%psr", 4) == 0) | |
2780 | { | |
2781 | s += 4; | |
2782 | continue; | |
2783 | } | |
2784 | break; | |
2785 | ||
e0c6ed95 | 2786 | case 'q': /* Floating point queue. */ |
252b5132 RH |
2787 | if (strncmp (s, "%fq", 3) == 0) |
2788 | { | |
2789 | s += 3; | |
2790 | continue; | |
2791 | } | |
2792 | break; | |
2793 | ||
e0c6ed95 | 2794 | case 'Q': /* Coprocessor queue. */ |
252b5132 RH |
2795 | if (strncmp (s, "%cq", 3) == 0) |
2796 | { | |
2797 | s += 3; | |
2798 | continue; | |
2799 | } | |
2800 | break; | |
2801 | ||
2802 | case 'S': | |
2803 | if (strcmp (str, "set") == 0 | |
2804 | || strcmp (str, "setuw") == 0) | |
2805 | { | |
2806 | special_case = SPECIAL_CASE_SET; | |
2807 | continue; | |
2808 | } | |
2809 | else if (strcmp (str, "setsw") == 0) | |
2810 | { | |
2811 | special_case = SPECIAL_CASE_SETSW; | |
2812 | continue; | |
2813 | } | |
2814 | else if (strcmp (str, "setx") == 0) | |
2815 | { | |
2816 | special_case = SPECIAL_CASE_SETX; | |
2817 | continue; | |
2818 | } | |
2819 | else if (strncmp (str, "fdiv", 4) == 0) | |
2820 | { | |
2821 | special_case = SPECIAL_CASE_FDIV; | |
2822 | continue; | |
2823 | } | |
2824 | break; | |
2825 | ||
2826 | case 'o': | |
2827 | if (strncmp (s, "%asi", 4) != 0) | |
2828 | break; | |
2829 | s += 4; | |
2830 | continue; | |
2831 | ||
2832 | case 's': | |
2833 | if (strncmp (s, "%fprs", 5) != 0) | |
2834 | break; | |
2835 | s += 5; | |
2836 | continue; | |
2837 | ||
2838 | case 'E': | |
2839 | if (strncmp (s, "%ccr", 4) != 0) | |
2840 | break; | |
2841 | s += 4; | |
2842 | continue; | |
2843 | ||
2844 | case 't': | |
2845 | if (strncmp (s, "%tbr", 4) != 0) | |
2846 | break; | |
2847 | s += 4; | |
2848 | continue; | |
2849 | ||
2850 | case 'w': | |
2851 | if (strncmp (s, "%wim", 4) != 0) | |
2852 | break; | |
2853 | s += 4; | |
2854 | continue; | |
2855 | ||
2856 | case 'x': | |
2857 | { | |
2858 | char *push = input_line_pointer; | |
2859 | expressionS e; | |
2860 | ||
2861 | input_line_pointer = s; | |
2862 | expression (&e); | |
2863 | if (e.X_op == O_constant) | |
2864 | { | |
2865 | int n = e.X_add_number; | |
2866 | if (n != e.X_add_number || (n & ~0x1ff) != 0) | |
2867 | as_bad (_("OPF immediate operand out of range (0-0x1ff)")); | |
2868 | else | |
2869 | opcode |= e.X_add_number << 5; | |
2870 | } | |
2871 | else | |
2872 | as_bad (_("non-immediate OPF operand, ignored")); | |
2873 | s = input_line_pointer; | |
2874 | input_line_pointer = push; | |
2875 | continue; | |
2876 | } | |
2877 | ||
2878 | case 'y': | |
2879 | if (strncmp (s, "%y", 2) != 0) | |
2880 | break; | |
2881 | s += 2; | |
2882 | continue; | |
2883 | ||
2884 | case 'u': | |
2885 | case 'U': | |
2886 | { | |
2887 | /* Parse a sparclet cpreg. */ | |
2888 | int cpreg; | |
2889 | if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) | |
2890 | { | |
2891 | error_message = _(": invalid cpreg name"); | |
2892 | goto error; | |
2893 | } | |
2894 | opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); | |
2895 | continue; | |
2896 | } | |
2897 | ||
2898 | default: | |
2899 | as_fatal (_("failed sanity check.")); | |
e0c6ed95 | 2900 | } /* switch on arg code. */ |
252b5132 RH |
2901 | |
2902 | /* Break out of for() loop. */ | |
2903 | break; | |
e0c6ed95 | 2904 | } /* For each arg that we expect. */ |
252b5132 RH |
2905 | |
2906 | error: | |
2907 | if (match == 0) | |
2908 | { | |
e0c6ed95 | 2909 | /* Args don't match. */ |
252b5132 RH |
2910 | if (&insn[1] - sparc_opcodes < sparc_num_opcodes |
2911 | && (insn->name == insn[1].name | |
2912 | || !strcmp (insn->name, insn[1].name))) | |
2913 | { | |
2914 | ++insn; | |
2915 | s = argsStart; | |
2916 | continue; | |
2917 | } | |
2918 | else | |
2919 | { | |
2920 | as_bad (_("Illegal operands%s"), error_message); | |
a22b281c | 2921 | return special_case; |
252b5132 RH |
2922 | } |
2923 | } | |
2924 | else | |
2925 | { | |
e0c6ed95 | 2926 | /* We have a match. Now see if the architecture is OK. */ |
252b5132 | 2927 | int needed_arch_mask = insn->architecture; |
ec668d69 | 2928 | int hwcaps = insn->hwcaps; |
252b5132 | 2929 | |
4bafe00e | 2930 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) |
9e8c70f9 DM |
2931 | if (hwcaps) |
2932 | hwcap_seen |= hwcaps; | |
2933 | #endif | |
252b5132 RH |
2934 | if (v9_arg_p) |
2935 | { | |
19f7b010 JJ |
2936 | needed_arch_mask &= |
2937 | ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); | |
2938 | if (! needed_arch_mask) | |
2939 | needed_arch_mask = | |
2940 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); | |
252b5132 RH |
2941 | } |
2942 | ||
e0c6ed95 AM |
2943 | if (needed_arch_mask |
2944 | & SPARC_OPCODE_SUPPORTED (current_architecture)) | |
2945 | /* OK. */ | |
2946 | ; | |
252b5132 | 2947 | /* Can we bump up the architecture? */ |
e0c6ed95 AM |
2948 | else if (needed_arch_mask |
2949 | & SPARC_OPCODE_SUPPORTED (max_architecture)) | |
252b5132 RH |
2950 | { |
2951 | enum sparc_opcode_arch_val needed_architecture = | |
2952 | sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) | |
2953 | & needed_arch_mask); | |
2954 | ||
9c2799c2 | 2955 | gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); |
252b5132 RH |
2956 | if (warn_on_bump |
2957 | && needed_architecture > warn_after_architecture) | |
2958 | { | |
2959 | as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), | |
2960 | sparc_opcode_archs[current_architecture].name, | |
2961 | sparc_opcode_archs[needed_architecture].name, | |
2962 | str); | |
2963 | warn_after_architecture = needed_architecture; | |
2964 | } | |
2965 | current_architecture = needed_architecture; | |
2966 | } | |
2967 | /* Conflict. */ | |
2968 | /* ??? This seems to be a bit fragile. What if the next entry in | |
2969 | the opcode table is the one we want and it is supported? | |
2970 | It is possible to arrange the table today so that this can't | |
2971 | happen but what about tomorrow? */ | |
2972 | else | |
2973 | { | |
e0c6ed95 | 2974 | int arch, printed_one_p = 0; |
252b5132 RH |
2975 | char *p; |
2976 | char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; | |
2977 | ||
2978 | /* Create a list of the architectures that support the insn. */ | |
e0c6ed95 | 2979 | needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); |
252b5132 RH |
2980 | p = required_archs; |
2981 | arch = sparc_ffs (needed_arch_mask); | |
2982 | while ((1 << arch) <= needed_arch_mask) | |
2983 | { | |
2984 | if ((1 << arch) & needed_arch_mask) | |
2985 | { | |
2986 | if (printed_one_p) | |
2987 | *p++ = '|'; | |
2988 | strcpy (p, sparc_opcode_archs[arch].name); | |
2989 | p += strlen (p); | |
2990 | printed_one_p = 1; | |
2991 | } | |
2992 | ++arch; | |
2993 | } | |
2994 | ||
2995 | as_bad (_("Architecture mismatch on \"%s\"."), str); | |
2996 | as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), | |
2997 | required_archs, | |
2998 | sparc_opcode_archs[max_architecture].name); | |
a22b281c | 2999 | return special_case; |
252b5132 | 3000 | } |
4bafe00e DM |
3001 | |
3002 | /* Make sure the the hwcaps used by the instruction are | |
3003 | currently enabled. */ | |
3004 | if (hwcaps & ~hwcap_allowed) | |
3005 | { | |
3006 | const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed); | |
3007 | ||
3008 | as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."), | |
3009 | hwcap_name, str); | |
3010 | return special_case; | |
3011 | } | |
e0c6ed95 | 3012 | } /* If no match. */ |
252b5132 RH |
3013 | |
3014 | break; | |
e0c6ed95 | 3015 | } /* Forever looking for a match. */ |
252b5132 RH |
3016 | |
3017 | the_insn.opcode = opcode; | |
a22b281c | 3018 | return special_case; |
252b5132 RH |
3019 | } |
3020 | ||
3021 | /* Parse an argument that can be expressed as a keyword. | |
3022 | (eg: #StoreStore or %ccfr). | |
3023 | The result is a boolean indicating success. | |
3024 | If successful, INPUT_POINTER is updated. */ | |
3025 | ||
3026 | static int | |
5a49b8ac AM |
3027 | parse_keyword_arg (int (*lookup_fn) (const char *), |
3028 | char **input_pointerP, | |
3029 | int *valueP) | |
252b5132 RH |
3030 | { |
3031 | int value; | |
3032 | char c, *p, *q; | |
3033 | ||
3034 | p = *input_pointerP; | |
3035 | for (q = p + (*p == '#' || *p == '%'); | |
3882b010 | 3036 | ISALNUM (*q) || *q == '_'; |
252b5132 RH |
3037 | ++q) |
3038 | continue; | |
3039 | c = *q; | |
3040 | *q = 0; | |
3041 | value = (*lookup_fn) (p); | |
3042 | *q = c; | |
3043 | if (value == -1) | |
3044 | return 0; | |
3045 | *valueP = value; | |
3046 | *input_pointerP = q; | |
3047 | return 1; | |
3048 | } | |
3049 | ||
3050 | /* Parse an argument that is a constant expression. | |
3051 | The result is a boolean indicating success. */ | |
3052 | ||
3053 | static int | |
5a49b8ac | 3054 | parse_const_expr_arg (char **input_pointerP, int *valueP) |
252b5132 RH |
3055 | { |
3056 | char *save = input_line_pointer; | |
3057 | expressionS exp; | |
3058 | ||
3059 | input_line_pointer = *input_pointerP; | |
3060 | /* The next expression may be something other than a constant | |
3061 | (say if we're not processing the right variant of the insn). | |
3062 | Don't call expression unless we're sure it will succeed as it will | |
3063 | signal an error (which we want to defer until later). */ | |
3064 | /* FIXME: It might be better to define md_operand and have it recognize | |
3065 | things like %asi, etc. but continuing that route through to the end | |
3066 | is a lot of work. */ | |
3067 | if (*input_line_pointer == '%') | |
3068 | { | |
3069 | input_line_pointer = save; | |
3070 | return 0; | |
3071 | } | |
3072 | expression (&exp); | |
3073 | *input_pointerP = input_line_pointer; | |
3074 | input_line_pointer = save; | |
3075 | if (exp.X_op != O_constant) | |
3076 | return 0; | |
3077 | *valueP = exp.X_add_number; | |
3078 | return 1; | |
3079 | } | |
3080 | ||
3081 | /* Subroutine of sparc_ip to parse an expression. */ | |
3082 | ||
3083 | static int | |
5a49b8ac | 3084 | get_expression (char *str) |
252b5132 RH |
3085 | { |
3086 | char *save_in; | |
3087 | segT seg; | |
3088 | ||
3089 | save_in = input_line_pointer; | |
3090 | input_line_pointer = str; | |
3091 | seg = expression (&the_insn.exp); | |
3092 | if (seg != absolute_section | |
3093 | && seg != text_section | |
3094 | && seg != data_section | |
3095 | && seg != bss_section | |
3096 | && seg != undefined_section) | |
3097 | { | |
3098 | the_insn.error = _("bad segment"); | |
3099 | expr_end = input_line_pointer; | |
3100 | input_line_pointer = save_in; | |
3101 | return 1; | |
3102 | } | |
3103 | expr_end = input_line_pointer; | |
3104 | input_line_pointer = save_in; | |
3105 | return 0; | |
3106 | } | |
3107 | ||
3108 | /* Subroutine of md_assemble to output one insn. */ | |
3109 | ||
3110 | static void | |
91d6fa6a | 3111 | output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn) |
252b5132 RH |
3112 | { |
3113 | char *toP = frag_more (4); | |
3114 | ||
e0c6ed95 | 3115 | /* Put out the opcode. */ |
252b5132 | 3116 | if (INSN_BIG_ENDIAN) |
91d6fa6a | 3117 | number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 3118 | else |
91d6fa6a | 3119 | number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 3120 | |
e0c6ed95 | 3121 | /* Put out the symbol-dependent stuff. */ |
91d6fa6a | 3122 | if (theinsn->reloc != BFD_RELOC_NONE) |
252b5132 | 3123 | { |
e0c6ed95 AM |
3124 | fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ |
3125 | (toP - frag_now->fr_literal), /* Where. */ | |
3126 | 4, /* Size. */ | |
91d6fa6a NC |
3127 | &theinsn->exp, |
3128 | theinsn->pcrel, | |
3129 | theinsn->reloc); | |
252b5132 | 3130 | /* Turn off overflow checking in fixup_segment. We'll do our |
55cf6793 | 3131 | own overflow checking in md_apply_fix. This is necessary because |
252b5132 RH |
3132 | the insn size is 4 and fixup_segment will signal an overflow for |
3133 | large 8 byte quantities. */ | |
3134 | fixP->fx_no_overflow = 1; | |
91d6fa6a NC |
3135 | if (theinsn->reloc == BFD_RELOC_SPARC_OLO10) |
3136 | fixP->tc_fix_data = theinsn->exp2.X_add_number; | |
252b5132 RH |
3137 | } |
3138 | ||
3139 | last_insn = insn; | |
91d6fa6a | 3140 | last_opcode = theinsn->opcode; |
732d96b6 JJ |
3141 | |
3142 | #ifdef OBJ_ELF | |
3143 | dwarf2_emit_insn (4); | |
3144 | #endif | |
252b5132 RH |
3145 | } |
3146 | \f | |
252b5132 | 3147 | char * |
499ac353 | 3148 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 3149 | { |
499ac353 | 3150 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
3151 | } |
3152 | ||
3153 | /* Write a value out to the object file, using the appropriate | |
3154 | endianness. */ | |
3155 | ||
3156 | void | |
5a49b8ac | 3157 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
3158 | { |
3159 | if (target_big_endian) | |
3160 | number_to_chars_bigendian (buf, val, n); | |
3161 | else if (target_little_endian_data | |
3162 | && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) | |
e0c6ed95 AM |
3163 | /* Output debug words, which are not in allocated sections, as big |
3164 | endian. */ | |
252b5132 RH |
3165 | number_to_chars_bigendian (buf, val, n); |
3166 | else if (target_little_endian_data || ! target_big_endian) | |
3167 | number_to_chars_littleendian (buf, val, n); | |
3168 | } | |
3169 | \f | |
3170 | /* Apply a fixS to the frags, now that we know the value it ought to | |
81d4177b | 3171 | hold. */ |
252b5132 | 3172 | |
94f592af | 3173 | void |
5a49b8ac | 3174 | md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) |
252b5132 RH |
3175 | { |
3176 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
94f592af | 3177 | offsetT val = * (offsetT *) valP; |
252b5132 RH |
3178 | long insn; |
3179 | ||
9c2799c2 | 3180 | gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); |
252b5132 | 3181 | |
e0c6ed95 | 3182 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
252b5132 RH |
3183 | |
3184 | #ifdef OBJ_ELF | |
a161fe53 | 3185 | /* SPARC ELF relocations don't use an addend in the data field. */ |
252b5132 | 3186 | if (fixP->fx_addsy != NULL) |
7c1d0959 L |
3187 | { |
3188 | switch (fixP->fx_r_type) | |
3189 | { | |
3190 | case BFD_RELOC_SPARC_TLS_GD_HI22: | |
3191 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3192 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3193 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3194 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3195 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3196 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3197 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3198 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3199 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3200 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3201 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3202 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3203 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3204 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3205 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3206 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3207 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3208 | case BFD_RELOC_SPARC_TLS_DTPMOD32: | |
3209 | case BFD_RELOC_SPARC_TLS_DTPMOD64: | |
3210 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3211 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
3212 | case BFD_RELOC_SPARC_TLS_TPOFF32: | |
3213 | case BFD_RELOC_SPARC_TLS_TPOFF64: | |
3214 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
3215 | ||
3216 | default: | |
3217 | break; | |
3218 | } | |
3219 | ||
3220 | return; | |
3221 | } | |
252b5132 RH |
3222 | #endif |
3223 | ||
3224 | /* This is a hack. There should be a better way to | |
3225 | handle this. Probably in terms of howto fields, once | |
3226 | we can look at these fixups in terms of howtos. */ | |
3227 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) | |
3228 | val += fixP->fx_where + fixP->fx_frag->fr_address; | |
3229 | ||
3230 | #ifdef OBJ_AOUT | |
3231 | /* FIXME: More ridiculous gas reloc hacking. If we are going to | |
3232 | generate a reloc, then we just want to let the reloc addend set | |
3233 | the value. We do not want to also stuff the addend into the | |
3234 | object file. Including the addend in the object file works when | |
3235 | doing a static link, because the linker will ignore the object | |
3236 | file contents. However, the dynamic linker does not ignore the | |
3237 | object file contents. */ | |
3238 | if (fixP->fx_addsy != NULL | |
3239 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) | |
3240 | val = 0; | |
3241 | ||
3242 | /* When generating PIC code, we do not want an addend for a reloc | |
3243 | against a local symbol. We adjust fx_addnumber to cancel out the | |
3244 | value already included in val, and to also cancel out the | |
3245 | adjustment which bfd_install_relocation will create. */ | |
3246 | if (sparc_pic_code | |
3247 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 | |
3248 | && fixP->fx_addsy != NULL | |
3249 | && ! S_IS_COMMON (fixP->fx_addsy) | |
49309057 | 3250 | && symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3251 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); |
3252 | ||
3253 | /* When generating PIC code, we need to fiddle to get | |
3254 | bfd_install_relocation to do the right thing for a PC relative | |
3255 | reloc against a local symbol which we are going to keep. */ | |
3256 | if (sparc_pic_code | |
3257 | && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3258 | && fixP->fx_addsy != NULL | |
3259 | && (S_IS_EXTERNAL (fixP->fx_addsy) | |
3260 | || S_IS_WEAK (fixP->fx_addsy)) | |
3261 | && S_IS_DEFINED (fixP->fx_addsy) | |
3262 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
3263 | { | |
3264 | val = 0; | |
3265 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
3266 | } | |
3267 | #endif | |
3268 | ||
3269 | /* If this is a data relocation, just output VAL. */ | |
3270 | ||
a7bbf4e9 DM |
3271 | if (fixP->fx_r_type == BFD_RELOC_8) |
3272 | { | |
3273 | md_number_to_chars (buf, val, 1); | |
3274 | } | |
3275 | else if (fixP->fx_r_type == BFD_RELOC_16 | |
3276 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) | |
252b5132 RH |
3277 | { |
3278 | md_number_to_chars (buf, val, 2); | |
3279 | } | |
3280 | else if (fixP->fx_r_type == BFD_RELOC_32 | |
0f2712ed | 3281 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 |
252b5132 RH |
3282 | || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) |
3283 | { | |
3284 | md_number_to_chars (buf, val, 4); | |
3285 | } | |
0f2712ed NC |
3286 | else if (fixP->fx_r_type == BFD_RELOC_64 |
3287 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) | |
252b5132 RH |
3288 | { |
3289 | md_number_to_chars (buf, val, 8); | |
3290 | } | |
e0c6ed95 | 3291 | else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
252b5132 RH |
3292 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
3293 | { | |
3294 | fixP->fx_done = 0; | |
94f592af | 3295 | return; |
252b5132 RH |
3296 | } |
3297 | else | |
3298 | { | |
3299 | /* It's a relocation against an instruction. */ | |
3300 | ||
3301 | if (INSN_BIG_ENDIAN) | |
3302 | insn = bfd_getb32 ((unsigned char *) buf); | |
3303 | else | |
3304 | insn = bfd_getl32 ((unsigned char *) buf); | |
e0c6ed95 | 3305 | |
252b5132 RH |
3306 | switch (fixP->fx_r_type) |
3307 | { | |
3308 | case BFD_RELOC_32_PCREL_S2: | |
3309 | val = val >> 2; | |
3310 | /* FIXME: This increment-by-one deserves a comment of why it's | |
3311 | being done! */ | |
3312 | if (! sparc_pic_code | |
3313 | || fixP->fx_addsy == NULL | |
49309057 | 3314 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 | 3315 | ++val; |
6faf3d66 | 3316 | |
252b5132 | 3317 | insn |= val & 0x3fffffff; |
6faf3d66 | 3318 | |
e0c6ed95 | 3319 | /* See if we have a delay slot. */ |
6faf3d66 JJ |
3320 | if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) |
3321 | { | |
3322 | #define G0 0 | |
3323 | #define O7 15 | |
3324 | #define XCC (2 << 20) | |
3325 | #define COND(x) (((x)&0xf)<<25) | |
3326 | #define CONDA COND(0x8) | |
3327 | #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) | |
3328 | #define INSN_BA (F2(0,2) | CONDA) | |
3329 | #define INSN_OR F3(2, 0x2, 0) | |
3330 | #define INSN_NOP F2(0,4) | |
3331 | ||
3332 | long delay; | |
3333 | ||
3334 | /* If the instruction is a call with either: | |
3335 | restore | |
3336 | arithmetic instruction with rd == %o7 | |
3337 | where rs1 != %o7 and rs2 if it is register != %o7 | |
3338 | then we can optimize if the call destination is near | |
3339 | by changing the call into a branch always. */ | |
3340 | if (INSN_BIG_ENDIAN) | |
3341 | delay = bfd_getb32 ((unsigned char *) buf + 4); | |
3342 | else | |
3343 | delay = bfd_getl32 ((unsigned char *) buf + 4); | |
e0c6ed95 | 3344 | if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) |
6faf3d66 | 3345 | break; |
e0c6ed95 AM |
3346 | if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ |
3347 | && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ | |
3348 | || ((delay & RD (~0)) != RD (O7)))) | |
6faf3d66 | 3349 | break; |
e0c6ed95 AM |
3350 | if ((delay & RS1 (~0)) == RS1 (O7) |
3351 | || ((delay & F3I (~0)) == 0 | |
3352 | && (delay & RS2 (~0)) == RS2 (O7))) | |
6faf3d66 JJ |
3353 | break; |
3354 | /* Ensure the branch will fit into simm22. */ | |
3355 | if ((val & 0x3fe00000) | |
3356 | && (val & 0x3fe00000) != 0x3fe00000) | |
3357 | break; | |
3358 | /* Check if the arch is v9 and branch will fit | |
3359 | into simm19. */ | |
3360 | if (((val & 0x3c0000) == 0 | |
3361 | || (val & 0x3c0000) == 0x3c0000) | |
3362 | && (sparc_arch_size == 64 | |
3363 | || current_architecture >= SPARC_OPCODE_ARCH_V9)) | |
e0c6ed95 | 3364 | /* ba,pt %xcc */ |
6faf3d66 JJ |
3365 | insn = INSN_BPA | (val & 0x7ffff); |
3366 | else | |
e0c6ed95 | 3367 | /* ba */ |
6faf3d66 JJ |
3368 | insn = INSN_BA | (val & 0x3fffff); |
3369 | if (fixP->fx_where >= 4 | |
e0c6ed95 AM |
3370 | && ((delay & (0xffffffff ^ RS1 (~0))) |
3371 | == (INSN_OR | RD (O7) | RS2 (G0)))) | |
6faf3d66 JJ |
3372 | { |
3373 | long setter; | |
3374 | int reg; | |
3375 | ||
3376 | if (INSN_BIG_ENDIAN) | |
3377 | setter = bfd_getb32 ((unsigned char *) buf - 4); | |
3378 | else | |
3379 | setter = bfd_getl32 ((unsigned char *) buf - 4); | |
e0c6ed95 | 3380 | if ((setter & (0xffffffff ^ RD (~0))) |
ab3e48dc | 3381 | != (INSN_OR | RS1 (O7) | RS2 (G0))) |
6faf3d66 JJ |
3382 | break; |
3383 | /* The sequence was | |
3384 | or %o7, %g0, %rN | |
3385 | call foo | |
3386 | or %rN, %g0, %o7 | |
3387 | ||
3388 | If call foo was replaced with ba, replace | |
3389 | or %rN, %g0, %o7 with nop. */ | |
e0c6ed95 AM |
3390 | reg = (delay & RS1 (~0)) >> 14; |
3391 | if (reg != ((setter & RD (~0)) >> 25) | |
6faf3d66 JJ |
3392 | || reg == G0 || reg == O7) |
3393 | break; | |
3394 | ||
3395 | if (INSN_BIG_ENDIAN) | |
3396 | bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); | |
3397 | else | |
3398 | bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); | |
3399 | } | |
3400 | } | |
252b5132 RH |
3401 | break; |
3402 | ||
3403 | case BFD_RELOC_SPARC_11: | |
3404 | if (! in_signed_range (val, 0x7ff)) | |
3405 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3406 | _("relocation overflow")); | |
3407 | insn |= val & 0x7ff; | |
3408 | break; | |
3409 | ||
3410 | case BFD_RELOC_SPARC_10: | |
3411 | if (! in_signed_range (val, 0x3ff)) | |
3412 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3413 | _("relocation overflow")); | |
3414 | insn |= val & 0x3ff; | |
3415 | break; | |
3416 | ||
3417 | case BFD_RELOC_SPARC_7: | |
3418 | if (! in_bitfield_range (val, 0x7f)) | |
3419 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3420 | _("relocation overflow")); | |
3421 | insn |= val & 0x7f; | |
3422 | break; | |
3423 | ||
3424 | case BFD_RELOC_SPARC_6: | |
3425 | if (! in_bitfield_range (val, 0x3f)) | |
3426 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3427 | _("relocation overflow")); | |
3428 | insn |= val & 0x3f; | |
3429 | break; | |
3430 | ||
3431 | case BFD_RELOC_SPARC_5: | |
3432 | if (! in_bitfield_range (val, 0x1f)) | |
3433 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3434 | _("relocation overflow")); | |
3435 | insn |= val & 0x1f; | |
3436 | break; | |
3437 | ||
2615994e DM |
3438 | case BFD_RELOC_SPARC_WDISP10: |
3439 | if ((val & 3) | |
3440 | || val >= 0x007fc | |
3441 | || val <= -(offsetT) 0x808) | |
3442 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3443 | _("relocation overflow")); | |
3444 | /* FIXME: The +1 deserves a comment. */ | |
3445 | val = (val >> 2) + 1; | |
3446 | insn |= ((val & 0x300) << 11) | |
3447 | | ((val & 0xff) << 5); | |
3448 | break; | |
3449 | ||
252b5132 | 3450 | case BFD_RELOC_SPARC_WDISP16: |
c699f087 JJ |
3451 | if ((val & 3) |
3452 | || val >= 0x1fffc | |
3453 | || val <= -(offsetT) 0x20008) | |
252b5132 RH |
3454 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3455 | _("relocation overflow")); | |
3456 | /* FIXME: The +1 deserves a comment. */ | |
3457 | val = (val >> 2) + 1; | |
3458 | insn |= ((val & 0xc000) << 6) | (val & 0x3fff); | |
3459 | break; | |
3460 | ||
3461 | case BFD_RELOC_SPARC_WDISP19: | |
c699f087 JJ |
3462 | if ((val & 3) |
3463 | || val >= 0xffffc | |
3464 | || val <= -(offsetT) 0x100008) | |
252b5132 RH |
3465 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3466 | _("relocation overflow")); | |
3467 | /* FIXME: The +1 deserves a comment. */ | |
3468 | val = (val >> 2) + 1; | |
3469 | insn |= val & 0x7ffff; | |
3470 | break; | |
3471 | ||
3472 | case BFD_RELOC_SPARC_HH22: | |
3473 | val = BSR (val, 32); | |
e0c6ed95 | 3474 | /* Fall through. */ |
252b5132 RH |
3475 | |
3476 | case BFD_RELOC_SPARC_LM22: | |
3477 | case BFD_RELOC_HI22: | |
3478 | if (!fixP->fx_addsy) | |
94f592af | 3479 | insn |= (val >> 10) & 0x3fffff; |
252b5132 | 3480 | else |
94f592af NC |
3481 | /* FIXME: Need comment explaining why we do this. */ |
3482 | insn &= ~0xffff; | |
252b5132 RH |
3483 | break; |
3484 | ||
3485 | case BFD_RELOC_SPARC22: | |
3486 | if (val & ~0x003fffff) | |
3487 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3488 | _("relocation overflow")); | |
3489 | insn |= (val & 0x3fffff); | |
3490 | break; | |
3491 | ||
3492 | case BFD_RELOC_SPARC_HM10: | |
3493 | val = BSR (val, 32); | |
e0c6ed95 | 3494 | /* Fall through. */ |
252b5132 RH |
3495 | |
3496 | case BFD_RELOC_LO10: | |
3497 | if (!fixP->fx_addsy) | |
94f592af | 3498 | insn |= val & 0x3ff; |
252b5132 | 3499 | else |
94f592af NC |
3500 | /* FIXME: Need comment explaining why we do this. */ |
3501 | insn &= ~0xff; | |
252b5132 RH |
3502 | break; |
3503 | ||
dabe3bbc RH |
3504 | case BFD_RELOC_SPARC_OLO10: |
3505 | val &= 0x3ff; | |
3506 | val += fixP->tc_fix_data; | |
e0c6ed95 | 3507 | /* Fall through. */ |
dabe3bbc | 3508 | |
252b5132 RH |
3509 | case BFD_RELOC_SPARC13: |
3510 | if (! in_signed_range (val, 0x1fff)) | |
3511 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3512 | _("relocation overflow")); | |
3513 | insn |= val & 0x1fff; | |
3514 | break; | |
3515 | ||
3516 | case BFD_RELOC_SPARC_WDISP22: | |
3517 | val = (val >> 2) + 1; | |
e0c6ed95 | 3518 | /* Fall through. */ |
252b5132 RH |
3519 | case BFD_RELOC_SPARC_BASE22: |
3520 | insn |= val & 0x3fffff; | |
3521 | break; | |
3522 | ||
2615994e DM |
3523 | case BFD_RELOC_SPARC_H34: |
3524 | if (!fixP->fx_addsy) | |
3525 | { | |
3526 | bfd_vma tval = val; | |
3527 | tval >>= 12; | |
3528 | insn |= tval & 0x3fffff; | |
3529 | } | |
3530 | break; | |
3531 | ||
252b5132 RH |
3532 | case BFD_RELOC_SPARC_H44: |
3533 | if (!fixP->fx_addsy) | |
3534 | { | |
3535 | bfd_vma tval = val; | |
3536 | tval >>= 22; | |
3537 | insn |= tval & 0x3fffff; | |
3538 | } | |
3539 | break; | |
3540 | ||
3541 | case BFD_RELOC_SPARC_M44: | |
3542 | if (!fixP->fx_addsy) | |
3543 | insn |= (val >> 12) & 0x3ff; | |
3544 | break; | |
3545 | ||
3546 | case BFD_RELOC_SPARC_L44: | |
3547 | if (!fixP->fx_addsy) | |
3548 | insn |= val & 0xfff; | |
3549 | break; | |
3550 | ||
3551 | case BFD_RELOC_SPARC_HIX22: | |
3552 | if (!fixP->fx_addsy) | |
3553 | { | |
ab3e48dc | 3554 | val ^= ~(offsetT) 0; |
252b5132 RH |
3555 | insn |= (val >> 10) & 0x3fffff; |
3556 | } | |
3557 | break; | |
3558 | ||
3559 | case BFD_RELOC_SPARC_LOX10: | |
3560 | if (!fixP->fx_addsy) | |
3561 | insn |= 0x1c00 | (val & 0x3ff); | |
3562 | break; | |
3563 | ||
3564 | case BFD_RELOC_NONE: | |
3565 | default: | |
3566 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3567 | _("bad or unhandled relocation type: 0x%02x"), | |
3568 | fixP->fx_r_type); | |
3569 | break; | |
3570 | } | |
3571 | ||
3572 | if (INSN_BIG_ENDIAN) | |
3573 | bfd_putb32 (insn, (unsigned char *) buf); | |
3574 | else | |
3575 | bfd_putl32 (insn, (unsigned char *) buf); | |
3576 | } | |
3577 | ||
3578 | /* Are we finished with this relocation now? */ | |
3579 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
3580 | fixP->fx_done = 1; | |
252b5132 RH |
3581 | } |
3582 | ||
3583 | /* Translate internal representation of relocation info to BFD target | |
3584 | format. */ | |
e0c6ed95 | 3585 | |
dabe3bbc | 3586 | arelent ** |
5a49b8ac | 3587 | tc_gen_reloc (asection *section, fixS *fixp) |
252b5132 | 3588 | { |
dabe3bbc | 3589 | static arelent *relocs[3]; |
252b5132 RH |
3590 | arelent *reloc; |
3591 | bfd_reloc_code_real_type code; | |
3592 | ||
dabe3bbc RH |
3593 | relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); |
3594 | relocs[1] = NULL; | |
252b5132 | 3595 | |
49309057 ILT |
3596 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
3597 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
3598 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3599 | ||
3600 | switch (fixp->fx_r_type) | |
3601 | { | |
3602 | case BFD_RELOC_16: | |
3603 | case BFD_RELOC_32: | |
3604 | case BFD_RELOC_HI22: | |
3605 | case BFD_RELOC_LO10: | |
3606 | case BFD_RELOC_32_PCREL_S2: | |
3607 | case BFD_RELOC_SPARC13: | |
63fab58c | 3608 | case BFD_RELOC_SPARC22: |
1a6b486f DM |
3609 | case BFD_RELOC_SPARC_PC22: |
3610 | case BFD_RELOC_SPARC_PC10: | |
252b5132 | 3611 | case BFD_RELOC_SPARC_BASE13: |
2615994e | 3612 | case BFD_RELOC_SPARC_WDISP10: |
252b5132 RH |
3613 | case BFD_RELOC_SPARC_WDISP16: |
3614 | case BFD_RELOC_SPARC_WDISP19: | |
3615 | case BFD_RELOC_SPARC_WDISP22: | |
3616 | case BFD_RELOC_64: | |
3617 | case BFD_RELOC_SPARC_5: | |
3618 | case BFD_RELOC_SPARC_6: | |
3619 | case BFD_RELOC_SPARC_7: | |
3620 | case BFD_RELOC_SPARC_10: | |
3621 | case BFD_RELOC_SPARC_11: | |
3622 | case BFD_RELOC_SPARC_HH22: | |
3623 | case BFD_RELOC_SPARC_HM10: | |
3624 | case BFD_RELOC_SPARC_LM22: | |
3625 | case BFD_RELOC_SPARC_PC_HH22: | |
3626 | case BFD_RELOC_SPARC_PC_HM10: | |
3627 | case BFD_RELOC_SPARC_PC_LM22: | |
2615994e | 3628 | case BFD_RELOC_SPARC_H34: |
252b5132 RH |
3629 | case BFD_RELOC_SPARC_H44: |
3630 | case BFD_RELOC_SPARC_M44: | |
3631 | case BFD_RELOC_SPARC_L44: | |
3632 | case BFD_RELOC_SPARC_HIX22: | |
3633 | case BFD_RELOC_SPARC_LOX10: | |
3634 | case BFD_RELOC_SPARC_REV32: | |
dabe3bbc | 3635 | case BFD_RELOC_SPARC_OLO10: |
0f2712ed NC |
3636 | case BFD_RELOC_SPARC_UA16: |
3637 | case BFD_RELOC_SPARC_UA32: | |
3638 | case BFD_RELOC_SPARC_UA64: | |
bd5e6e7e JJ |
3639 | case BFD_RELOC_8_PCREL: |
3640 | case BFD_RELOC_16_PCREL: | |
3641 | case BFD_RELOC_32_PCREL: | |
3642 | case BFD_RELOC_64_PCREL: | |
3643 | case BFD_RELOC_SPARC_PLT32: | |
3644 | case BFD_RELOC_SPARC_PLT64: | |
252b5132 RH |
3645 | case BFD_RELOC_VTABLE_ENTRY: |
3646 | case BFD_RELOC_VTABLE_INHERIT: | |
b9734f35 JJ |
3647 | case BFD_RELOC_SPARC_TLS_GD_HI22: |
3648 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3649 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3650 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3651 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3652 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3653 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3654 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3655 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3656 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3657 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3658 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3659 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3660 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3661 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3662 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3663 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3664 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3665 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3666 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
739f7f82 DM |
3667 | case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: |
3668 | case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: | |
3669 | case BFD_RELOC_SPARC_GOTDATA_OP: | |
252b5132 RH |
3670 | code = fixp->fx_r_type; |
3671 | break; | |
3672 | default: | |
3673 | abort (); | |
3674 | return NULL; | |
3675 | } | |
3676 | ||
3677 | #if defined (OBJ_ELF) || defined (OBJ_AOUT) | |
3678 | /* If we are generating PIC code, we need to generate a different | |
3679 | set of relocs. */ | |
3680 | ||
3681 | #ifdef OBJ_ELF | |
3682 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" | |
3683 | #else | |
3684 | #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" | |
910600e9 RS |
3685 | #endif |
3686 | #ifdef TE_VXWORKS | |
3687 | #define GOTT_BASE "__GOTT_BASE__" | |
3688 | #define GOTT_INDEX "__GOTT_INDEX__" | |
252b5132 RH |
3689 | #endif |
3690 | ||
153b546a ILT |
3691 | /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ |
3692 | ||
252b5132 RH |
3693 | if (sparc_pic_code) |
3694 | { | |
3695 | switch (code) | |
3696 | { | |
3697 | case BFD_RELOC_32_PCREL_S2: | |
ae6063d4 | 3698 | if (generic_force_reloc (fixp)) |
252b5132 RH |
3699 | code = BFD_RELOC_SPARC_WPLT30; |
3700 | break; | |
3701 | case BFD_RELOC_HI22: | |
910600e9 RS |
3702 | code = BFD_RELOC_SPARC_GOT22; |
3703 | if (fixp->fx_addsy != NULL) | |
3704 | { | |
3705 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3706 | code = BFD_RELOC_SPARC_PC22; | |
3707 | #ifdef TE_VXWORKS | |
3708 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3709 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3710 | code = BFD_RELOC_HI22; /* Unchanged. */ | |
3711 | #endif | |
3712 | } | |
252b5132 RH |
3713 | break; |
3714 | case BFD_RELOC_LO10: | |
910600e9 RS |
3715 | code = BFD_RELOC_SPARC_GOT10; |
3716 | if (fixp->fx_addsy != NULL) | |
3717 | { | |
3718 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3719 | code = BFD_RELOC_SPARC_PC10; | |
3720 | #ifdef TE_VXWORKS | |
3721 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3722 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3723 | code = BFD_RELOC_LO10; /* Unchanged. */ | |
3724 | #endif | |
3725 | } | |
252b5132 RH |
3726 | break; |
3727 | case BFD_RELOC_SPARC13: | |
3728 | code = BFD_RELOC_SPARC_GOT13; | |
3729 | break; | |
3730 | default: | |
3731 | break; | |
3732 | } | |
3733 | } | |
e0c6ed95 | 3734 | #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ |
252b5132 | 3735 | |
062cf837 EB |
3736 | /* Nothing is aligned in DWARF debugging sections. */ |
3737 | if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) | |
3738 | switch (code) | |
3739 | { | |
3740 | case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; | |
3741 | case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; | |
3742 | case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; | |
3743 | default: break; | |
3744 | } | |
3745 | ||
dabe3bbc RH |
3746 | if (code == BFD_RELOC_SPARC_OLO10) |
3747 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); | |
3748 | else | |
3749 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
252b5132 RH |
3750 | if (reloc->howto == 0) |
3751 | { | |
3752 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3753 | _("internal error: can't export reloc type %d (`%s')"), | |
3754 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); | |
dabe3bbc RH |
3755 | xfree (reloc); |
3756 | relocs[0] = NULL; | |
3757 | return relocs; | |
252b5132 RH |
3758 | } |
3759 | ||
3760 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ | |
3761 | #ifdef OBJ_AOUT | |
3762 | ||
3763 | if (reloc->howto->pc_relative == 0 | |
3764 | || code == BFD_RELOC_SPARC_PC10 | |
3765 | || code == BFD_RELOC_SPARC_PC22) | |
3766 | reloc->addend = fixp->fx_addnumber; | |
3767 | else if (sparc_pic_code | |
3768 | && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3769 | && fixp->fx_addsy != NULL | |
3770 | && (S_IS_EXTERNAL (fixp->fx_addsy) | |
3771 | || S_IS_WEAK (fixp->fx_addsy)) | |
3772 | && S_IS_DEFINED (fixp->fx_addsy) | |
3773 | && ! S_IS_COMMON (fixp->fx_addsy)) | |
3774 | reloc->addend = fixp->fx_addnumber; | |
3775 | else | |
3776 | reloc->addend = fixp->fx_offset - reloc->address; | |
3777 | ||
e0c6ed95 | 3778 | #else /* elf or coff */ |
252b5132 | 3779 | |
bd5e6e7e JJ |
3780 | if (code != BFD_RELOC_32_PCREL_S2 |
3781 | && code != BFD_RELOC_SPARC_WDISP22 | |
3782 | && code != BFD_RELOC_SPARC_WDISP16 | |
3783 | && code != BFD_RELOC_SPARC_WDISP19 | |
2615994e | 3784 | && code != BFD_RELOC_SPARC_WDISP10 |
b9734f35 JJ |
3785 | && code != BFD_RELOC_SPARC_WPLT30 |
3786 | && code != BFD_RELOC_SPARC_TLS_GD_CALL | |
3787 | && code != BFD_RELOC_SPARC_TLS_LDM_CALL) | |
252b5132 | 3788 | reloc->addend = fixp->fx_addnumber; |
49309057 | 3789 | else if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
3790 | reloc->addend = (section->vma |
3791 | + fixp->fx_addnumber | |
3792 | + md_pcrel_from (fixp)); | |
3793 | else | |
3794 | reloc->addend = fixp->fx_offset; | |
3795 | #endif | |
3796 | ||
dabe3bbc RH |
3797 | /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 |
3798 | on the same location. */ | |
3799 | if (code == BFD_RELOC_SPARC_OLO10) | |
3800 | { | |
3801 | relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); | |
3802 | relocs[2] = NULL; | |
3803 | ||
3804 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
ab3e48dc KH |
3805 | *reloc->sym_ptr_ptr |
3806 | = symbol_get_bfdsym (section_symbol (absolute_section)); | |
dabe3bbc RH |
3807 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3808 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); | |
3809 | reloc->addend = fixp->tc_fix_data; | |
3810 | } | |
3811 | ||
3812 | return relocs; | |
252b5132 RH |
3813 | } |
3814 | \f | |
e0c6ed95 | 3815 | /* We have no need to default values of symbols. */ |
252b5132 | 3816 | |
252b5132 | 3817 | symbolS * |
5a49b8ac | 3818 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
3819 | { |
3820 | return 0; | |
e0c6ed95 AM |
3821 | } |
3822 | ||
3823 | /* Round up a section size to the appropriate boundary. */ | |
252b5132 | 3824 | |
252b5132 | 3825 | valueT |
5a49b8ac | 3826 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 RH |
3827 | { |
3828 | #ifndef OBJ_ELF | |
3829 | /* This is not right for ELF; a.out wants it, and COFF will force | |
3830 | the alignment anyways. */ | |
3831 | valueT align = ((valueT) 1 | |
3832 | << (valueT) bfd_get_section_alignment (stdoutput, segment)); | |
3833 | valueT newsize; | |
e0c6ed95 AM |
3834 | |
3835 | /* Turn alignment value into a mask. */ | |
252b5132 RH |
3836 | align--; |
3837 | newsize = (size + align) & ~align; | |
3838 | return newsize; | |
3839 | #else | |
3840 | return size; | |
3841 | #endif | |
3842 | } | |
3843 | ||
3844 | /* Exactly what point is a PC-relative offset relative TO? | |
3845 | On the sparc, they're relative to the address of the offset, plus | |
3846 | its size. This gets us to the following instruction. | |
e0c6ed95 AM |
3847 | (??? Is this right? FIXME-SOON) */ |
3848 | long | |
5a49b8ac | 3849 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
3850 | { |
3851 | long ret; | |
3852 | ||
3853 | ret = fixP->fx_where + fixP->fx_frag->fr_address; | |
3854 | if (! sparc_pic_code | |
3855 | || fixP->fx_addsy == NULL | |
49309057 | 3856 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3857 | ret += fixP->fx_size; |
3858 | return ret; | |
3859 | } | |
3860 | \f | |
3861 | /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power | |
3862 | of two. */ | |
3863 | ||
3864 | static int | |
5a49b8ac | 3865 | mylog2 (int value) |
252b5132 RH |
3866 | { |
3867 | int shift; | |
3868 | ||
3869 | if (value <= 0) | |
3870 | return -1; | |
3871 | ||
3872 | for (shift = 0; (value & 1) == 0; value >>= 1) | |
3873 | ++shift; | |
3874 | ||
3875 | return (value == 1) ? shift : -1; | |
3876 | } | |
3877 | ||
e0c6ed95 | 3878 | /* Sort of like s_lcomm. */ |
252b5132 RH |
3879 | |
3880 | #ifndef OBJ_ELF | |
3881 | static int max_alignment = 15; | |
3882 | #endif | |
3883 | ||
3884 | static void | |
5a49b8ac | 3885 | s_reserve (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
3886 | { |
3887 | char *name; | |
3888 | char *p; | |
3889 | char c; | |
3890 | int align; | |
3891 | int size; | |
3892 | int temp; | |
3893 | symbolS *symbolP; | |
3894 | ||
3895 | name = input_line_pointer; | |
3896 | c = get_symbol_end (); | |
3897 | p = input_line_pointer; | |
3898 | *p = c; | |
3899 | SKIP_WHITESPACE (); | |
3900 | ||
3901 | if (*input_line_pointer != ',') | |
3902 | { | |
3903 | as_bad (_("Expected comma after name")); | |
3904 | ignore_rest_of_line (); | |
3905 | return; | |
3906 | } | |
3907 | ||
3908 | ++input_line_pointer; | |
3909 | ||
3910 | if ((size = get_absolute_expression ()) < 0) | |
3911 | { | |
3912 | as_bad (_("BSS length (%d.) <0! Ignored."), size); | |
3913 | ignore_rest_of_line (); | |
3914 | return; | |
e0c6ed95 | 3915 | } /* Bad length. */ |
252b5132 RH |
3916 | |
3917 | *p = 0; | |
3918 | symbolP = symbol_find_or_make (name); | |
3919 | *p = c; | |
3920 | ||
3921 | if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 | |
3922 | && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) | |
3923 | { | |
3924 | as_bad (_("bad .reserve segment -- expected BSS segment")); | |
3925 | return; | |
3926 | } | |
3927 | ||
3928 | if (input_line_pointer[2] == '.') | |
3929 | input_line_pointer += 7; | |
3930 | else | |
3931 | input_line_pointer += 6; | |
3932 | SKIP_WHITESPACE (); | |
3933 | ||
3934 | if (*input_line_pointer == ',') | |
3935 | { | |
3936 | ++input_line_pointer; | |
3937 | ||
3938 | SKIP_WHITESPACE (); | |
3939 | if (*input_line_pointer == '\n') | |
3940 | { | |
3941 | as_bad (_("missing alignment")); | |
3942 | ignore_rest_of_line (); | |
3943 | return; | |
3944 | } | |
3945 | ||
3946 | align = (int) get_absolute_expression (); | |
3947 | ||
3948 | #ifndef OBJ_ELF | |
3949 | if (align > max_alignment) | |
3950 | { | |
3951 | align = max_alignment; | |
3952 | as_warn (_("alignment too large; assuming %d"), align); | |
3953 | } | |
3954 | #endif | |
3955 | ||
3956 | if (align < 0) | |
3957 | { | |
3958 | as_bad (_("negative alignment")); | |
3959 | ignore_rest_of_line (); | |
3960 | return; | |
3961 | } | |
3962 | ||
3963 | if (align != 0) | |
3964 | { | |
f17c130b | 3965 | temp = mylog2 (align); |
252b5132 RH |
3966 | if (temp < 0) |
3967 | { | |
3968 | as_bad (_("alignment not a power of 2")); | |
3969 | ignore_rest_of_line (); | |
3970 | return; | |
3971 | } | |
3972 | ||
3973 | align = temp; | |
3974 | } | |
3975 | ||
3976 | record_alignment (bss_section, align); | |
3977 | } | |
3978 | else | |
3979 | align = 0; | |
3980 | ||
3981 | if (!S_IS_DEFINED (symbolP) | |
3982 | #ifdef OBJ_AOUT | |
3983 | && S_GET_OTHER (symbolP) == 0 | |
3984 | && S_GET_DESC (symbolP) == 0 | |
3985 | #endif | |
3986 | ) | |
3987 | { | |
3988 | if (! need_pass_2) | |
3989 | { | |
3990 | char *pfrag; | |
3991 | segT current_seg = now_seg; | |
3992 | subsegT current_subseg = now_subseg; | |
3993 | ||
e0c6ed95 AM |
3994 | /* Switch to bss. */ |
3995 | subseg_set (bss_section, 1); | |
252b5132 RH |
3996 | |
3997 | if (align) | |
e0c6ed95 AM |
3998 | /* Do alignment. */ |
3999 | frag_align (align, 0, 0); | |
252b5132 | 4000 | |
e0c6ed95 | 4001 | /* Detach from old frag. */ |
ab3e48dc | 4002 | if (S_GET_SEGMENT (symbolP) == bss_section) |
49309057 | 4003 | symbol_get_frag (symbolP)->fr_symbol = NULL; |
252b5132 | 4004 | |
49309057 | 4005 | symbol_set_frag (symbolP, frag_now); |
e0c6ed95 AM |
4006 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
4007 | (offsetT) size, (char *) 0); | |
252b5132 RH |
4008 | *pfrag = 0; |
4009 | ||
4010 | S_SET_SEGMENT (symbolP, bss_section); | |
4011 | ||
4012 | subseg_set (current_seg, current_subseg); | |
4013 | ||
4014 | #ifdef OBJ_ELF | |
4015 | S_SET_SIZE (symbolP, size); | |
4016 | #endif | |
4017 | } | |
4018 | } | |
4019 | else | |
4020 | { | |
20203fb9 | 4021 | as_warn (_("Ignoring attempt to re-define symbol %s"), |
ab3e48dc | 4022 | S_GET_NAME (symbolP)); |
20203fb9 | 4023 | } |
252b5132 RH |
4024 | |
4025 | demand_empty_rest_of_line (); | |
4026 | } | |
4027 | ||
4028 | static void | |
5a49b8ac | 4029 | s_common (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4030 | { |
4031 | char *name; | |
4032 | char c; | |
4033 | char *p; | |
685736be | 4034 | offsetT temp, size; |
252b5132 RH |
4035 | symbolS *symbolP; |
4036 | ||
4037 | name = input_line_pointer; | |
4038 | c = get_symbol_end (); | |
e0c6ed95 | 4039 | /* Just after name is now '\0'. */ |
252b5132 RH |
4040 | p = input_line_pointer; |
4041 | *p = c; | |
4042 | SKIP_WHITESPACE (); | |
4043 | if (*input_line_pointer != ',') | |
4044 | { | |
4045 | as_bad (_("Expected comma after symbol-name")); | |
4046 | ignore_rest_of_line (); | |
4047 | return; | |
4048 | } | |
e0c6ed95 AM |
4049 | |
4050 | /* Skip ','. */ | |
4051 | input_line_pointer++; | |
4052 | ||
252b5132 RH |
4053 | if ((temp = get_absolute_expression ()) < 0) |
4054 | { | |
685736be NC |
4055 | as_bad (_(".COMMon length (%lu) out of range ignored"), |
4056 | (unsigned long) temp); | |
252b5132 RH |
4057 | ignore_rest_of_line (); |
4058 | return; | |
4059 | } | |
4060 | size = temp; | |
4061 | *p = 0; | |
4062 | symbolP = symbol_find_or_make (name); | |
4063 | *p = c; | |
4064 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
4065 | { | |
4066 | as_bad (_("Ignoring attempt to re-define symbol")); | |
4067 | ignore_rest_of_line (); | |
4068 | return; | |
4069 | } | |
4070 | if (S_GET_VALUE (symbolP) != 0) | |
4071 | { | |
4072 | if (S_GET_VALUE (symbolP) != (valueT) size) | |
4073 | { | |
364b6d8b JJ |
4074 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), |
4075 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); | |
252b5132 RH |
4076 | } |
4077 | } | |
4078 | else | |
4079 | { | |
4080 | #ifndef OBJ_ELF | |
4081 | S_SET_VALUE (symbolP, (valueT) size); | |
4082 | S_SET_EXTERNAL (symbolP); | |
4083 | #endif | |
4084 | } | |
7dcc9865 | 4085 | know (symbol_get_frag (symbolP) == &zero_address_frag); |
252b5132 RH |
4086 | if (*input_line_pointer != ',') |
4087 | { | |
4088 | as_bad (_("Expected comma after common length")); | |
4089 | ignore_rest_of_line (); | |
4090 | return; | |
4091 | } | |
4092 | input_line_pointer++; | |
4093 | SKIP_WHITESPACE (); | |
4094 | if (*input_line_pointer != '"') | |
4095 | { | |
4096 | temp = get_absolute_expression (); | |
4097 | ||
4098 | #ifndef OBJ_ELF | |
4099 | if (temp > max_alignment) | |
4100 | { | |
4101 | temp = max_alignment; | |
f17c130b | 4102 | as_warn (_("alignment too large; assuming %ld"), (long) temp); |
252b5132 RH |
4103 | } |
4104 | #endif | |
4105 | ||
4106 | if (temp < 0) | |
4107 | { | |
4108 | as_bad (_("negative alignment")); | |
4109 | ignore_rest_of_line (); | |
4110 | return; | |
4111 | } | |
4112 | ||
4113 | #ifdef OBJ_ELF | |
49309057 | 4114 | if (symbol_get_obj (symbolP)->local) |
252b5132 RH |
4115 | { |
4116 | segT old_sec; | |
4117 | int old_subsec; | |
252b5132 RH |
4118 | int align; |
4119 | ||
4120 | old_sec = now_seg; | |
4121 | old_subsec = now_subseg; | |
4122 | ||
4123 | if (temp == 0) | |
4124 | align = 0; | |
4125 | else | |
f17c130b | 4126 | align = mylog2 (temp); |
252b5132 RH |
4127 | |
4128 | if (align < 0) | |
4129 | { | |
4130 | as_bad (_("alignment not a power of 2")); | |
4131 | ignore_rest_of_line (); | |
4132 | return; | |
4133 | } | |
4134 | ||
4135 | record_alignment (bss_section, align); | |
4136 | subseg_set (bss_section, 0); | |
4137 | if (align) | |
4138 | frag_align (align, 0, 0); | |
4139 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
4140 | symbol_get_frag (symbolP)->fr_symbol = 0; |
4141 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
4142 | p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
4143 | (offsetT) size, (char *) 0); | |
4144 | *p = 0; | |
4145 | S_SET_SEGMENT (symbolP, bss_section); | |
4146 | S_CLEAR_EXTERNAL (symbolP); | |
4147 | S_SET_SIZE (symbolP, size); | |
4148 | subseg_set (old_sec, old_subsec); | |
4149 | } | |
4150 | else | |
e0c6ed95 | 4151 | #endif /* OBJ_ELF */ |
252b5132 RH |
4152 | { |
4153 | allocate_common: | |
4154 | S_SET_VALUE (symbolP, (valueT) size); | |
4155 | #ifdef OBJ_ELF | |
4156 | S_SET_ALIGN (symbolP, temp); | |
4157 | S_SET_SIZE (symbolP, size); | |
4158 | #endif | |
4159 | S_SET_EXTERNAL (symbolP); | |
4160 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); | |
4161 | } | |
4162 | } | |
4163 | else | |
4164 | { | |
4165 | input_line_pointer++; | |
4166 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ | |
4167 | if (*input_line_pointer == '.') | |
4168 | input_line_pointer++; | |
4169 | /* @@ Some say data, some say bss. */ | |
4170 | if (strncmp (input_line_pointer, "bss\"", 4) | |
4171 | && strncmp (input_line_pointer, "data\"", 5)) | |
4172 | { | |
4173 | while (*--input_line_pointer != '"') | |
4174 | ; | |
4175 | input_line_pointer--; | |
4176 | goto bad_common_segment; | |
4177 | } | |
4178 | while (*input_line_pointer++ != '"') | |
4179 | ; | |
4180 | goto allocate_common; | |
4181 | } | |
4182 | ||
49309057 | 4183 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; |
252b5132 RH |
4184 | |
4185 | demand_empty_rest_of_line (); | |
4186 | return; | |
4187 | ||
4188 | { | |
4189 | bad_common_segment: | |
4190 | p = input_line_pointer; | |
4191 | while (*p && *p != '\n') | |
4192 | p++; | |
4193 | c = *p; | |
4194 | *p = '\0'; | |
4195 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); | |
4196 | *p = c; | |
4197 | input_line_pointer = p; | |
4198 | ignore_rest_of_line (); | |
4199 | return; | |
4200 | } | |
4201 | } | |
4202 | ||
67c1ffbe | 4203 | /* Handle the .empty pseudo-op. This suppresses the warnings about |
252b5132 RH |
4204 | invalid delay slot usage. */ |
4205 | ||
4206 | static void | |
5a49b8ac | 4207 | s_empty (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4208 | { |
4209 | /* The easy way to implement is to just forget about the last | |
4210 | instruction. */ | |
4211 | last_insn = NULL; | |
4212 | } | |
4213 | ||
4214 | static void | |
5a49b8ac | 4215 | s_seg (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4216 | { |
4217 | ||
4218 | if (strncmp (input_line_pointer, "\"text\"", 6) == 0) | |
4219 | { | |
4220 | input_line_pointer += 6; | |
4221 | s_text (0); | |
4222 | return; | |
4223 | } | |
4224 | if (strncmp (input_line_pointer, "\"data\"", 6) == 0) | |
4225 | { | |
4226 | input_line_pointer += 6; | |
4227 | s_data (0); | |
4228 | return; | |
4229 | } | |
4230 | if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) | |
4231 | { | |
4232 | input_line_pointer += 7; | |
4233 | s_data1 (); | |
4234 | return; | |
4235 | } | |
4236 | if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) | |
4237 | { | |
4238 | input_line_pointer += 5; | |
4239 | /* We only support 2 segments -- text and data -- for now, so | |
4240 | things in the "bss segment" will have to go into data for now. | |
e0c6ed95 AM |
4241 | You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ |
4242 | subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ | |
252b5132 RH |
4243 | return; |
4244 | } | |
4245 | as_bad (_("Unknown segment type")); | |
4246 | demand_empty_rest_of_line (); | |
4247 | } | |
4248 | ||
4249 | static void | |
5a49b8ac | 4250 | s_data1 (void) |
252b5132 RH |
4251 | { |
4252 | subseg_set (data_section, 1); | |
4253 | demand_empty_rest_of_line (); | |
4254 | } | |
4255 | ||
4256 | static void | |
5a49b8ac | 4257 | s_proc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4258 | { |
4259 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4260 | { | |
4261 | ++input_line_pointer; | |
4262 | } | |
4263 | ++input_line_pointer; | |
4264 | } | |
4265 | ||
4266 | /* This static variable is set by s_uacons to tell sparc_cons_align | |
67c1ffbe | 4267 | that the expression does not need to be aligned. */ |
252b5132 RH |
4268 | |
4269 | static int sparc_no_align_cons = 0; | |
4270 | ||
bd5e6e7e JJ |
4271 | /* This static variable is set by sparc_cons to emit requested types |
4272 | of relocations in cons_fix_new_sparc. */ | |
4273 | ||
4274 | static const char *sparc_cons_special_reloc; | |
4275 | ||
252b5132 RH |
4276 | /* This handles the unaligned space allocation pseudo-ops, such as |
4277 | .uaword. .uaword is just like .word, but the value does not need | |
4278 | to be aligned. */ | |
4279 | ||
4280 | static void | |
5a49b8ac | 4281 | s_uacons (int bytes) |
252b5132 RH |
4282 | { |
4283 | /* Tell sparc_cons_align not to align this value. */ | |
4284 | sparc_no_align_cons = 1; | |
4285 | cons (bytes); | |
4ffadb11 | 4286 | sparc_no_align_cons = 0; |
252b5132 RH |
4287 | } |
4288 | ||
cf9a1301 RH |
4289 | /* This handles the native word allocation pseudo-op .nword. |
4290 | For sparc_arch_size 32 it is equivalent to .word, for | |
4291 | sparc_arch_size 64 it is equivalent to .xword. */ | |
4292 | ||
4293 | static void | |
5a49b8ac | 4294 | s_ncons (int bytes ATTRIBUTE_UNUSED) |
cf9a1301 RH |
4295 | { |
4296 | cons (sparc_arch_size == 32 ? 4 : 8); | |
4297 | } | |
4298 | ||
6d8809aa RH |
4299 | #ifdef OBJ_ELF |
4300 | /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a | |
4301 | global register. | |
4302 | The syntax is: | |
e0c6ed95 | 4303 | |
6d8809aa | 4304 | .register %g[2367],{#scratch|symbolname|#ignore} |
e0c6ed95 | 4305 | */ |
6d8809aa RH |
4306 | |
4307 | static void | |
5a49b8ac | 4308 | s_register (int ignore ATTRIBUTE_UNUSED) |
6d8809aa RH |
4309 | { |
4310 | char c; | |
4311 | int reg; | |
4312 | int flags; | |
4313 | const char *regname; | |
4314 | ||
4315 | if (input_line_pointer[0] != '%' | |
4316 | || input_line_pointer[1] != 'g' | |
4317 | || ((input_line_pointer[2] & ~1) != '2' | |
4318 | && (input_line_pointer[2] & ~1) != '6') | |
4319 | || input_line_pointer[3] != ',') | |
4320 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
4321 | reg = input_line_pointer[2] - '0'; | |
4322 | input_line_pointer += 4; | |
4323 | ||
4324 | if (*input_line_pointer == '#') | |
4325 | { | |
4326 | ++input_line_pointer; | |
4327 | regname = input_line_pointer; | |
4328 | c = get_symbol_end (); | |
4329 | if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) | |
4330 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
ab3e48dc | 4331 | if (regname[0] == 'i') |
6d8809aa RH |
4332 | regname = NULL; |
4333 | else | |
4334 | regname = ""; | |
4335 | } | |
4336 | else | |
4337 | { | |
4338 | regname = input_line_pointer; | |
4339 | c = get_symbol_end (); | |
4340 | } | |
4341 | if (sparc_arch_size == 64) | |
4342 | { | |
e0c6ed95 | 4343 | if (globals[reg]) |
6d8809aa | 4344 | { |
e0c6ed95 AM |
4345 | if ((regname && globals[reg] != (symbolS *) 1 |
4346 | && strcmp (S_GET_NAME (globals[reg]), regname)) | |
4347 | || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) | |
6d8809aa RH |
4348 | as_bad (_("redefinition of global register")); |
4349 | } | |
4350 | else | |
4351 | { | |
4352 | if (regname == NULL) | |
e0c6ed95 | 4353 | globals[reg] = (symbolS *) 1; |
6d8809aa RH |
4354 | else |
4355 | { | |
4356 | if (*regname) | |
4357 | { | |
4358 | if (symbol_find (regname)) | |
4359 | as_bad (_("Register symbol %s already defined."), | |
4360 | regname); | |
4361 | } | |
e0c6ed95 AM |
4362 | globals[reg] = symbol_make (regname); |
4363 | flags = symbol_get_bfdsym (globals[reg])->flags; | |
6d8809aa RH |
4364 | if (! *regname) |
4365 | flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); | |
4366 | if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) | |
4367 | flags |= BSF_GLOBAL; | |
e0c6ed95 AM |
4368 | symbol_get_bfdsym (globals[reg])->flags = flags; |
4369 | S_SET_VALUE (globals[reg], (valueT) reg); | |
4370 | S_SET_ALIGN (globals[reg], reg); | |
4371 | S_SET_SIZE (globals[reg], 0); | |
6d8809aa RH |
4372 | /* Although we actually want undefined_section here, |
4373 | we have to use absolute_section, because otherwise | |
4374 | generic as code will make it a COM section. | |
4375 | We fix this up in sparc_adjust_symtab. */ | |
e0c6ed95 AM |
4376 | S_SET_SEGMENT (globals[reg], absolute_section); |
4377 | S_SET_OTHER (globals[reg], 0); | |
4378 | elf_symbol (symbol_get_bfdsym (globals[reg])) | |
6d8809aa RH |
4379 | ->internal_elf_sym.st_info = |
4380 | ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); | |
e0c6ed95 | 4381 | elf_symbol (symbol_get_bfdsym (globals[reg])) |
6d8809aa RH |
4382 | ->internal_elf_sym.st_shndx = SHN_UNDEF; |
4383 | } | |
4384 | } | |
4385 | } | |
4386 | ||
4387 | *input_line_pointer = c; | |
4388 | ||
4389 | demand_empty_rest_of_line (); | |
4390 | } | |
4391 | ||
4392 | /* Adjust the symbol table. We set undefined sections for STT_REGISTER | |
4393 | symbols which need it. */ | |
e0c6ed95 | 4394 | |
6d8809aa | 4395 | void |
5a49b8ac | 4396 | sparc_adjust_symtab (void) |
6d8809aa RH |
4397 | { |
4398 | symbolS *sym; | |
e0c6ed95 | 4399 | |
6d8809aa RH |
4400 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
4401 | { | |
4402 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4403 | ->internal_elf_sym.st_info) != STT_REGISTER) | |
4404 | continue; | |
4405 | ||
4406 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4407 | ->internal_elf_sym.st_shndx != SHN_UNDEF)) | |
4408 | continue; | |
4409 | ||
4410 | S_SET_SEGMENT (sym, undefined_section); | |
4411 | } | |
4412 | } | |
4413 | #endif | |
4414 | ||
252b5132 RH |
4415 | /* If the --enforce-aligned-data option is used, we require .word, |
4416 | et. al., to be aligned correctly. We do it by setting up an | |
4417 | rs_align_code frag, and checking in HANDLE_ALIGN to make sure that | |
4418 | no unexpected alignment was introduced. | |
4419 | ||
4420 | The SunOS and Solaris native assemblers enforce aligned data by | |
4421 | default. We don't want to do that, because gcc can deliberately | |
4422 | generate misaligned data if the packed attribute is used. Instead, | |
4423 | we permit misaligned data by default, and permit the user to set an | |
4424 | option to check for it. */ | |
4425 | ||
4426 | void | |
5a49b8ac | 4427 | sparc_cons_align (int nbytes) |
252b5132 RH |
4428 | { |
4429 | int nalign; | |
252b5132 RH |
4430 | |
4431 | /* Only do this if we are enforcing aligned data. */ | |
4432 | if (! enforce_aligned_data) | |
4433 | return; | |
4434 | ||
0f2712ed | 4435 | /* Don't align if this is an unaligned pseudo-op. */ |
252b5132 | 4436 | if (sparc_no_align_cons) |
0f2712ed | 4437 | return; |
252b5132 | 4438 | |
f17c130b | 4439 | nalign = mylog2 (nbytes); |
252b5132 RH |
4440 | if (nalign == 0) |
4441 | return; | |
4442 | ||
9c2799c2 | 4443 | gas_assert (nalign > 0); |
252b5132 RH |
4444 | |
4445 | if (now_seg == absolute_section) | |
4446 | { | |
4447 | if ((abs_section_offset & ((1 << nalign) - 1)) != 0) | |
4448 | as_bad (_("misaligned data")); | |
4449 | return; | |
4450 | } | |
4451 | ||
87975d2a AM |
4452 | frag_var (rs_align_test, 1, 1, (relax_substateT) 0, |
4453 | (symbolS *) NULL, (offsetT) nalign, (char *) NULL); | |
252b5132 RH |
4454 | |
4455 | record_alignment (now_seg, nalign); | |
4456 | } | |
4457 | ||
0a9ef439 | 4458 | /* This is called from HANDLE_ALIGN in tc-sparc.h. */ |
252b5132 RH |
4459 | |
4460 | void | |
5a49b8ac | 4461 | sparc_handle_align (fragS *fragp) |
252b5132 | 4462 | { |
0a9ef439 RH |
4463 | int count, fix; |
4464 | char *p; | |
4465 | ||
4466 | count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
bfb32b52 | 4467 | |
0a9ef439 | 4468 | switch (fragp->fr_type) |
252b5132 | 4469 | { |
0a9ef439 RH |
4470 | case rs_align_test: |
4471 | if (count != 0) | |
4472 | as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); | |
4473 | break; | |
e0c6ed95 | 4474 | |
0a9ef439 RH |
4475 | case rs_align_code: |
4476 | p = fragp->fr_literal + fragp->fr_fix; | |
4477 | fix = 0; | |
e0c6ed95 | 4478 | |
0a9ef439 RH |
4479 | if (count & 3) |
4480 | { | |
4481 | fix = count & 3; | |
4482 | memset (p, 0, fix); | |
4483 | p += fix; | |
4484 | count -= fix; | |
4485 | } | |
e0c6ed95 | 4486 | |
0a9ef439 RH |
4487 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) |
4488 | { | |
4489 | unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ | |
4490 | if (INSN_BIG_ENDIAN) | |
4491 | number_to_chars_bigendian (p, wval, 4); | |
4492 | else | |
4493 | number_to_chars_littleendian (p, wval, 4); | |
4494 | p += 4; | |
4495 | count -= 4; | |
4496 | fix += 4; | |
e0c6ed95 | 4497 | } |
0a9ef439 RH |
4498 | |
4499 | if (INSN_BIG_ENDIAN) | |
4500 | number_to_chars_bigendian (p, 0x01000000, 4); | |
4501 | else | |
4502 | number_to_chars_littleendian (p, 0x01000000, 4); | |
4503 | ||
4504 | fragp->fr_fix += fix; | |
4505 | fragp->fr_var = 4; | |
4506 | break; | |
4507 | ||
4508 | default: | |
4509 | break; | |
252b5132 RH |
4510 | } |
4511 | } | |
4512 | ||
4513 | #ifdef OBJ_ELF | |
4514 | /* Some special processing for a Sparc ELF file. */ | |
4515 | ||
4516 | void | |
5a49b8ac | 4517 | sparc_elf_final_processing (void) |
252b5132 RH |
4518 | { |
4519 | /* Set the Sparc ELF flag bits. FIXME: There should probably be some | |
4520 | sort of BFD interface for this. */ | |
4521 | if (sparc_arch_size == 64) | |
4522 | { | |
4523 | switch (sparc_memory_model) | |
4524 | { | |
4525 | case MM_RMO: | |
4526 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; | |
4527 | break; | |
4528 | case MM_PSO: | |
4529 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; | |
4530 | break; | |
4531 | default: | |
4532 | break; | |
4533 | } | |
4534 | } | |
4535 | else if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
4536 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; | |
4537 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
4538 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; | |
19f7b010 JJ |
4539 | else if (current_architecture == SPARC_OPCODE_ARCH_V9B) |
4540 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; | |
252b5132 | 4541 | } |
bd5e6e7e JJ |
4542 | |
4543 | void | |
5a49b8ac | 4544 | sparc_cons (expressionS *exp, int size) |
bd5e6e7e JJ |
4545 | { |
4546 | char *save; | |
4547 | ||
4548 | SKIP_WHITESPACE (); | |
4549 | sparc_cons_special_reloc = NULL; | |
4550 | save = input_line_pointer; | |
4551 | if (input_line_pointer[0] == '%' | |
4552 | && input_line_pointer[1] == 'r' | |
4553 | && input_line_pointer[2] == '_') | |
4554 | { | |
4555 | if (strncmp (input_line_pointer + 3, "disp", 4) == 0) | |
4556 | { | |
4557 | input_line_pointer += 7; | |
4558 | sparc_cons_special_reloc = "disp"; | |
4559 | } | |
4560 | else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) | |
4561 | { | |
4562 | if (size != 4 && size != 8) | |
4563 | as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); | |
4564 | else | |
4565 | { | |
4566 | input_line_pointer += 6; | |
4567 | sparc_cons_special_reloc = "plt"; | |
4568 | } | |
4569 | } | |
b9734f35 JJ |
4570 | else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) |
4571 | { | |
4572 | if (size != 4 && size != 8) | |
4573 | as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); | |
4574 | else | |
4575 | { | |
4576 | input_line_pointer += 13; | |
4577 | sparc_cons_special_reloc = "tls_dtpoff"; | |
4578 | } | |
4579 | } | |
bd5e6e7e JJ |
4580 | if (sparc_cons_special_reloc) |
4581 | { | |
4582 | int bad = 0; | |
4583 | ||
4584 | switch (size) | |
4585 | { | |
4586 | case 1: | |
4587 | if (*input_line_pointer != '8') | |
4588 | bad = 1; | |
4589 | input_line_pointer--; | |
4590 | break; | |
4591 | case 2: | |
4592 | if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') | |
4593 | bad = 1; | |
4594 | break; | |
4595 | case 4: | |
4596 | if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') | |
4597 | bad = 1; | |
4598 | break; | |
4599 | case 8: | |
4600 | if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') | |
4601 | bad = 1; | |
4602 | break; | |
4603 | default: | |
4604 | bad = 1; | |
4605 | break; | |
4606 | } | |
4607 | ||
4608 | if (bad) | |
4609 | { | |
4610 | as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), | |
4611 | sparc_cons_special_reloc, size * 8, size); | |
4612 | } | |
4613 | else | |
4614 | { | |
4615 | input_line_pointer += 2; | |
4616 | if (*input_line_pointer != '(') | |
4617 | { | |
4618 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4619 | sparc_cons_special_reloc, size * 8); | |
4620 | bad = 1; | |
4621 | } | |
4622 | } | |
4623 | ||
4624 | if (bad) | |
4625 | { | |
4626 | input_line_pointer = save; | |
4627 | sparc_cons_special_reloc = NULL; | |
4628 | } | |
4629 | else | |
4630 | { | |
4631 | int c; | |
4632 | char *end = ++input_line_pointer; | |
4633 | int npar = 0; | |
4634 | ||
4635 | while (! is_end_of_line[(c = *end)]) | |
4636 | { | |
4637 | if (c == '(') | |
4638 | npar++; | |
4639 | else if (c == ')') | |
4640 | { | |
4641 | if (!npar) | |
4642 | break; | |
4643 | npar--; | |
4644 | } | |
4645 | end++; | |
4646 | } | |
4647 | ||
4648 | if (c != ')') | |
4649 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4650 | sparc_cons_special_reloc, size * 8); | |
4651 | else | |
4652 | { | |
4653 | *end = '\0'; | |
4654 | expression (exp); | |
4655 | *end = c; | |
4656 | if (input_line_pointer != end) | |
4657 | { | |
4658 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4659 | sparc_cons_special_reloc, size * 8); | |
4660 | } | |
4661 | else | |
4662 | { | |
4663 | input_line_pointer++; | |
4664 | SKIP_WHITESPACE (); | |
4665 | c = *input_line_pointer; | |
4666 | if (! is_end_of_line[c] && c != ',') | |
4667 | as_bad (_("Illegal operands: garbage after %%r_%s%d()"), | |
4668 | sparc_cons_special_reloc, size * 8); | |
4669 | } | |
4670 | } | |
4671 | } | |
4672 | } | |
4673 | } | |
4674 | if (sparc_cons_special_reloc == NULL) | |
4675 | expression (exp); | |
4676 | } | |
4677 | ||
252b5132 RH |
4678 | #endif |
4679 | ||
4680 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
4681 | reloc for a cons. We could use the definition there, except that | |
4682 | we want to handle little endian relocs specially. */ | |
4683 | ||
4684 | void | |
5a49b8ac AM |
4685 | cons_fix_new_sparc (fragS *frag, |
4686 | int where, | |
4687 | unsigned int nbytes, | |
4688 | expressionS *exp) | |
252b5132 RH |
4689 | { |
4690 | bfd_reloc_code_real_type r; | |
4691 | ||
4692 | r = (nbytes == 1 ? BFD_RELOC_8 : | |
4693 | (nbytes == 2 ? BFD_RELOC_16 : | |
4694 | (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
4695 | ||
0f2712ed NC |
4696 | if (target_little_endian_data |
4697 | && nbytes == 4 | |
e0c6ed95 | 4698 | && now_seg->flags & SEC_ALLOC) |
252b5132 | 4699 | r = BFD_RELOC_SPARC_REV32; |
0f2712ed | 4700 | |
bd5e6e7e JJ |
4701 | if (sparc_cons_special_reloc) |
4702 | { | |
4703 | if (*sparc_cons_special_reloc == 'd') | |
4704 | switch (nbytes) | |
4705 | { | |
4706 | case 1: r = BFD_RELOC_8_PCREL; break; | |
4707 | case 2: r = BFD_RELOC_16_PCREL; break; | |
4708 | case 4: r = BFD_RELOC_32_PCREL; break; | |
4709 | case 8: r = BFD_RELOC_64_PCREL; break; | |
4710 | default: abort (); | |
4711 | } | |
b9734f35 | 4712 | else if (*sparc_cons_special_reloc == 'p') |
bd5e6e7e JJ |
4713 | switch (nbytes) |
4714 | { | |
4715 | case 4: r = BFD_RELOC_SPARC_PLT32; break; | |
4716 | case 8: r = BFD_RELOC_SPARC_PLT64; break; | |
4717 | } | |
b9734f35 JJ |
4718 | else |
4719 | switch (nbytes) | |
4720 | { | |
4721 | case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; | |
4722 | case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; | |
4723 | } | |
bd5e6e7e JJ |
4724 | } |
4725 | else if (sparc_no_align_cons) | |
0f2712ed NC |
4726 | { |
4727 | switch (nbytes) | |
4728 | { | |
4729 | case 2: r = BFD_RELOC_SPARC_UA16; break; | |
4730 | case 4: r = BFD_RELOC_SPARC_UA32; break; | |
4731 | case 8: r = BFD_RELOC_SPARC_UA64; break; | |
4732 | default: abort (); | |
4733 | } | |
4ffadb11 | 4734 | } |
0f2712ed | 4735 | |
252b5132 | 4736 | fix_new_exp (frag, where, (int) nbytes, exp, 0, r); |
364b6d8b JJ |
4737 | sparc_cons_special_reloc = NULL; |
4738 | } | |
4739 | ||
4740 | void | |
5a49b8ac | 4741 | sparc_cfi_frame_initial_instructions (void) |
364b6d8b JJ |
4742 | { |
4743 | cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); | |
4744 | } | |
4745 | ||
4746 | int | |
1df69f4f | 4747 | sparc_regname_to_dw2regnum (char *regname) |
364b6d8b JJ |
4748 | { |
4749 | char *p, *q; | |
4750 | ||
4751 | if (!regname[0]) | |
4752 | return -1; | |
4753 | ||
4754 | q = "goli"; | |
4755 | p = strchr (q, regname[0]); | |
4756 | if (p) | |
4757 | { | |
4758 | if (regname[1] < '0' || regname[1] > '8' || regname[2]) | |
4759 | return -1; | |
4760 | return (p - q) * 8 + regname[1] - '0'; | |
4761 | } | |
4762 | if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) | |
4763 | return 14; | |
4764 | if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) | |
4765 | return 30; | |
4766 | if (regname[0] == 'f' || regname[0] == 'r') | |
4767 | { | |
4768 | unsigned int regnum; | |
4769 | ||
4770 | regnum = strtoul (regname + 1, &q, 10); | |
4771 | if (p == q || *q) | |
4772 | return -1; | |
4773 | if (regnum >= ((regname[0] == 'f' | |
4774 | && SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
4775 | ? 64 : 32)) | |
4776 | return -1; | |
4777 | if (regname[0] == 'f') | |
4778 | { | |
4779 | regnum += 32; | |
4780 | if (regnum >= 64 && (regnum & 1)) | |
4781 | return -1; | |
4782 | } | |
4783 | return regnum; | |
4784 | } | |
4785 | return -1; | |
4786 | } | |
4787 | ||
4788 | void | |
4789 | sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) | |
4790 | { | |
4791 | sparc_cons_special_reloc = "disp"; | |
4792 | sparc_no_align_cons = 1; | |
4793 | emit_expr (exp, nbytes); | |
4794 | sparc_no_align_cons = 0; | |
4795 | sparc_cons_special_reloc = NULL; | |
252b5132 | 4796 | } |