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252b5132 | 1 | /* tc-sparc.c -- Assemble for the SPARC |
49309057 | 2 | Copyright (C) 1989, 90-96, 97, 98, 1999 Free Software Foundation, Inc. |
252b5132 RH |
3 | This file is part of GAS, the GNU Assembler. |
4 | ||
5 | GAS is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2, or (at your option) | |
8 | any later version. | |
9 | ||
10 | GAS is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public | |
16 | License along with GAS; see the file COPYING. If not, write | |
17 | to the Free Software Foundation, 59 Temple Place - Suite 330, | |
18 | Boston, MA 02111-1307, USA. */ | |
19 | ||
20 | #include <stdio.h> | |
21 | #include <ctype.h> | |
22 | ||
23 | #include "as.h" | |
24 | #include "subsegs.h" | |
25 | ||
26 | #include "opcode/sparc.h" | |
27 | ||
28 | #ifdef OBJ_ELF | |
29 | #include "elf/sparc.h" | |
30 | #endif | |
31 | ||
32 | static struct sparc_arch *lookup_arch PARAMS ((char *)); | |
33 | static void init_default_arch PARAMS ((void)); | |
a22b281c | 34 | static int sparc_ip PARAMS ((char *, const struct sparc_opcode **)); |
252b5132 RH |
35 | static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); |
36 | static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma)); | |
37 | static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); | |
38 | static int sparc_ffs PARAMS ((unsigned int)); | |
a22b281c RH |
39 | static void synthetize_setuw PARAMS ((const struct sparc_opcode *)); |
40 | static void synthetize_setsw PARAMS ((const struct sparc_opcode *)); | |
41 | static void synthetize_setx PARAMS ((const struct sparc_opcode *)); | |
252b5132 RH |
42 | static bfd_vma BSR PARAMS ((bfd_vma, int)); |
43 | static int cmp_reg_entry PARAMS ((const PTR, const PTR)); | |
44 | static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *)); | |
45 | static int parse_const_expr_arg PARAMS ((char **, int *)); | |
46 | static int get_expression PARAMS ((char *str)); | |
47 | ||
48 | /* Default architecture. */ | |
49 | /* ??? The default value should be V8, but sparclite support was added | |
50 | by making it the default. GCC now passes -Asparclite, so maybe sometime in | |
51 | the future we can set this to V8. */ | |
52 | #ifndef DEFAULT_ARCH | |
53 | #define DEFAULT_ARCH "sparclite" | |
54 | #endif | |
55 | static char *default_arch = DEFAULT_ARCH; | |
56 | ||
57 | /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' | |
58 | have been set. */ | |
59 | static int default_init_p; | |
60 | ||
61 | /* Current architecture. We don't bump up unless necessary. */ | |
62 | static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; | |
63 | ||
64 | /* The maximum architecture level we can bump up to. | |
65 | In a 32 bit environment, don't allow bumping up to v9 by default. | |
66 | The native assembler works this way. The user is required to pass | |
67 | an explicit argument before we'll create v9 object files. However, if | |
68 | we don't see any v9 insns, a v8plus object file is not created. */ | |
69 | static enum sparc_opcode_arch_val max_architecture; | |
70 | ||
71 | /* Either 32 or 64, selects file format. */ | |
72 | static int sparc_arch_size; | |
73 | /* Initial (default) value, recorded separately in case a user option | |
74 | changes the value before md_show_usage is called. */ | |
75 | static int default_arch_size; | |
76 | ||
77 | #ifdef OBJ_ELF | |
78 | /* The currently selected v9 memory model. Currently only used for | |
79 | ELF. */ | |
80 | static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; | |
81 | #endif | |
82 | ||
83 | static int architecture_requested; | |
84 | static int warn_on_bump; | |
85 | ||
86 | /* If warn_on_bump and the needed architecture is higher than this | |
87 | architecture, issue a warning. */ | |
88 | static enum sparc_opcode_arch_val warn_after_architecture; | |
89 | ||
6d8809aa RH |
90 | /* Non-zero if as should generate error if an undeclared g[23] register |
91 | has been used in -64. */ | |
92 | static int no_undeclared_regs; | |
93 | ||
252b5132 RH |
94 | /* Non-zero if we are generating PIC code. */ |
95 | int sparc_pic_code; | |
96 | ||
97 | /* Non-zero if we should give an error when misaligned data is seen. */ | |
98 | static int enforce_aligned_data; | |
99 | ||
100 | extern int target_big_endian; | |
101 | ||
102 | static int target_little_endian_data; | |
103 | ||
6d8809aa RH |
104 | /* Symbols for global registers on v9. */ |
105 | static symbolS *globals[8]; | |
106 | ||
252b5132 RH |
107 | /* V9 and 86x have big and little endian data, but instructions are always big |
108 | endian. The sparclet has bi-endian support but both data and insns have | |
109 | the same endianness. Global `target_big_endian' is used for data. | |
110 | The following macro is used for instructions. */ | |
111 | #ifndef INSN_BIG_ENDIAN | |
112 | #define INSN_BIG_ENDIAN (target_big_endian \ | |
113 | || default_arch_type == sparc86x \ | |
114 | || SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
115 | #endif | |
116 | ||
117 | /* handle of the OPCODE hash table */ | |
118 | static struct hash_control *op_hash; | |
119 | ||
120 | static int log2 PARAMS ((int)); | |
121 | static void s_data1 PARAMS ((void)); | |
122 | static void s_seg PARAMS ((int)); | |
123 | static void s_proc PARAMS ((int)); | |
124 | static void s_reserve PARAMS ((int)); | |
125 | static void s_common PARAMS ((int)); | |
126 | static void s_empty PARAMS ((int)); | |
127 | static void s_uacons PARAMS ((int)); | |
cf9a1301 | 128 | static void s_ncons PARAMS ((int)); |
6d8809aa | 129 | static void s_register PARAMS ((int)); |
252b5132 RH |
130 | |
131 | const pseudo_typeS md_pseudo_table[] = | |
132 | { | |
133 | {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */ | |
134 | {"common", s_common, 0}, | |
135 | {"empty", s_empty, 0}, | |
136 | {"global", s_globl, 0}, | |
137 | {"half", cons, 2}, | |
cf9a1301 | 138 | {"nword", s_ncons, 0}, |
252b5132 RH |
139 | {"optim", s_ignore, 0}, |
140 | {"proc", s_proc, 0}, | |
141 | {"reserve", s_reserve, 0}, | |
142 | {"seg", s_seg, 0}, | |
143 | {"skip", s_space, 0}, | |
144 | {"word", cons, 4}, | |
145 | {"xword", cons, 8}, | |
146 | {"uahalf", s_uacons, 2}, | |
147 | {"uaword", s_uacons, 4}, | |
148 | {"uaxword", s_uacons, 8}, | |
149 | #ifdef OBJ_ELF | |
150 | /* these are specific to sparc/svr4 */ | |
252b5132 RH |
151 | {"2byte", s_uacons, 2}, |
152 | {"4byte", s_uacons, 4}, | |
153 | {"8byte", s_uacons, 8}, | |
6d8809aa | 154 | {"register", s_register, 0}, |
252b5132 RH |
155 | #endif |
156 | {NULL, 0, 0}, | |
157 | }; | |
158 | ||
159 | const int md_reloc_size = 12; /* Size of relocation record */ | |
160 | ||
161 | /* This array holds the chars that always start a comment. If the | |
162 | pre-processor is disabled, these aren't very useful */ | |
163 | const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */ | |
164 | ||
165 | /* This array holds the chars that only start a comment at the beginning of | |
166 | a line. If the line seems to have the form '# 123 filename' | |
167 | .line and .file directives will appear in the pre-processed output */ | |
168 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
169 | first line of the input file. This is because the compiler outputs | |
170 | #NO_APP at the beginning of its output. */ | |
171 | /* Also note that comments started like this one will always | |
172 | work if '/' isn't otherwise defined. */ | |
173 | const char line_comment_chars[] = "#"; | |
174 | ||
175 | const char line_separator_chars[] = ""; | |
176 | ||
177 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
178 | const char EXP_CHARS[] = "eE"; | |
179 | ||
180 | /* Chars that mean this number is a floating point constant */ | |
181 | /* As in 0f12.456 */ | |
182 | /* or 0d1.2345e12 */ | |
183 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
184 | ||
185 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
186 | changed in read.c. Ideally it shouldn't have to know about it at all, | |
187 | but nothing is ideal around here. */ | |
188 | ||
a22b281c | 189 | #define isoctal(c) ((unsigned)((c) - '0') < '8') |
252b5132 RH |
190 | |
191 | struct sparc_it | |
192 | { | |
193 | char *error; | |
194 | unsigned long opcode; | |
195 | struct nlist *nlistp; | |
196 | expressionS exp; | |
cf9a1301 | 197 | expressionS exp2; |
252b5132 RH |
198 | int pcrel; |
199 | bfd_reloc_code_real_type reloc; | |
200 | }; | |
201 | ||
202 | struct sparc_it the_insn, set_insn; | |
203 | ||
204 | static void output_insn | |
205 | PARAMS ((const struct sparc_opcode *, struct sparc_it *)); | |
206 | \f | |
207 | /* Table of arguments to -A. | |
208 | The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect | |
209 | for this use. That table is for opcodes only. This table is for opcodes | |
210 | and file formats. */ | |
211 | ||
212 | enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, | |
213 | v8plusa, v9, v9a, v9_64}; | |
214 | ||
215 | static struct sparc_arch { | |
216 | char *name; | |
217 | char *opcode_arch; | |
218 | enum sparc_arch_types arch_type; | |
219 | /* Default word size, as specified during configuration. | |
220 | A value of zero means can't be used to specify default architecture. */ | |
221 | int default_arch_size; | |
222 | /* Allowable arg to -A? */ | |
223 | int user_option_p; | |
224 | } sparc_arch_table[] = { | |
225 | { "v6", "v6", v6, 0, 1 }, | |
226 | { "v7", "v7", v7, 0, 1 }, | |
227 | { "v8", "v8", v8, 32, 1 }, | |
228 | { "sparclet", "sparclet", sparclet, 32, 1 }, | |
229 | { "sparclite", "sparclite", sparclite, 32, 1 }, | |
230 | { "sparc86x", "sparclite", sparc86x, 32, 1 }, | |
231 | { "v8plus", "v9", v9, 0, 1 }, | |
232 | { "v8plusa", "v9a", v9, 0, 1 }, | |
233 | { "v9", "v9", v9, 0, 1 }, | |
234 | { "v9a", "v9a", v9, 0, 1 }, | |
235 | /* This exists to allow configure.in/Makefile.in to pass one | |
236 | value to specify both the default machine and default word size. */ | |
237 | { "v9-64", "v9", v9, 64, 0 }, | |
238 | { NULL, NULL, v8, 0, 0 } | |
239 | }; | |
240 | ||
241 | /* Variant of default_arch */ | |
242 | static enum sparc_arch_types default_arch_type; | |
243 | ||
244 | static struct sparc_arch * | |
245 | lookup_arch (name) | |
246 | char *name; | |
247 | { | |
248 | struct sparc_arch *sa; | |
249 | ||
250 | for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) | |
251 | if (strcmp (sa->name, name) == 0) | |
252 | break; | |
253 | if (sa->name == NULL) | |
254 | return NULL; | |
255 | return sa; | |
256 | } | |
257 | ||
258 | /* Initialize the default opcode arch and word size from the default | |
259 | architecture name. */ | |
260 | ||
261 | static void | |
262 | init_default_arch () | |
263 | { | |
264 | struct sparc_arch *sa = lookup_arch (default_arch); | |
265 | ||
266 | if (sa == NULL | |
267 | || sa->default_arch_size == 0) | |
268 | as_fatal (_("Invalid default architecture, broken assembler.")); | |
269 | ||
270 | max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); | |
271 | if (max_architecture == SPARC_OPCODE_ARCH_BAD) | |
272 | as_fatal (_("Bad opcode table, broken assembler.")); | |
273 | default_arch_size = sparc_arch_size = sa->default_arch_size; | |
274 | default_init_p = 1; | |
275 | default_arch_type = sa->arch_type; | |
276 | } | |
277 | ||
278 | /* Called by TARGET_FORMAT. */ | |
279 | ||
280 | const char * | |
281 | sparc_target_format () | |
282 | { | |
283 | /* We don't get a chance to initialize anything before we're called, | |
284 | so handle that now. */ | |
285 | if (! default_init_p) | |
286 | init_default_arch (); | |
287 | ||
288 | #ifdef OBJ_AOUT | |
289 | #ifdef TE_NetBSD | |
290 | return "a.out-sparc-netbsd"; | |
291 | #else | |
292 | #ifdef TE_SPARCAOUT | |
293 | if (target_big_endian) | |
294 | return "a.out-sunos-big"; | |
295 | else if (default_arch_type == sparc86x && target_little_endian_data) | |
296 | return "a.out-sunos-big"; | |
297 | else return "a.out-sparc-little"; | |
298 | #else | |
299 | return "a.out-sunos-big"; | |
300 | #endif | |
301 | #endif | |
302 | #endif | |
303 | ||
304 | #ifdef OBJ_BOUT | |
305 | return "b.out.big"; | |
306 | #endif | |
307 | ||
308 | #ifdef OBJ_COFF | |
309 | #ifdef TE_LYNX | |
310 | return "coff-sparc-lynx"; | |
311 | #else | |
312 | return "coff-sparc"; | |
313 | #endif | |
314 | #endif | |
315 | ||
316 | #ifdef OBJ_ELF | |
317 | return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc"; | |
318 | #endif | |
319 | ||
320 | abort (); | |
321 | } | |
322 | \f | |
323 | /* | |
324 | * md_parse_option | |
325 | * Invocation line includes a switch not recognized by the base assembler. | |
326 | * See if it's a processor-specific option. These are: | |
327 | * | |
328 | * -bump | |
329 | * Warn on architecture bumps. See also -A. | |
330 | * | |
331 | * -Av6, -Av7, -Av8, -Asparclite, -Asparclet | |
332 | * Standard 32 bit architectures. | |
333 | * -Av8plus, -Av8plusa | |
334 | * Sparc64 in a 32 bit world. | |
335 | * -Av9, -Av9a | |
336 | * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). | |
337 | * This used to only mean 64 bits, but properly specifying it | |
338 | * complicated gcc's ASM_SPECs, so now opcode selection is | |
339 | * specified orthogonally to word size (except when specifying | |
340 | * the default, but that is an internal implementation detail). | |
341 | * -xarch=v8plus, -xarch=v8plusa | |
342 | * Same as -Av8plus{,a}, for compatibility with Sun's assembler. | |
343 | * | |
344 | * Select the architecture and possibly the file format. | |
345 | * Instructions or features not supported by the selected | |
346 | * architecture cause fatal errors. | |
347 | * | |
348 | * The default is to start at v6, and bump the architecture up | |
349 | * whenever an instruction is seen at a higher level. In 32 bit | |
350 | * environments, v9 is not bumped up to, the user must pass | |
351 | * -Av8plus{,a}. | |
352 | * | |
353 | * If -bump is specified, a warning is printing when bumping to | |
354 | * higher levels. | |
355 | * | |
356 | * If an architecture is specified, all instructions must match | |
357 | * that architecture. Any higher level instructions are flagged | |
358 | * as errors. Note that in the 32 bit environment specifying | |
359 | * -Av8plus does not automatically create a v8plus object file, a | |
360 | * v9 insn must be seen. | |
361 | * | |
362 | * If both an architecture and -bump are specified, the | |
363 | * architecture starts at the specified level, but bumps are | |
364 | * warnings. Note that we can't set `current_architecture' to | |
365 | * the requested level in this case: in the 32 bit environment, | |
366 | * we still must avoid creating v8plus object files unless v9 | |
367 | * insns are seen. | |
368 | * | |
369 | * Note: | |
370 | * Bumping between incompatible architectures is always an | |
371 | * error. For example, from sparclite to v9. | |
372 | */ | |
373 | ||
374 | #ifdef OBJ_ELF | |
375 | CONST char *md_shortopts = "A:K:VQ:sq"; | |
376 | #else | |
377 | #ifdef OBJ_AOUT | |
378 | CONST char *md_shortopts = "A:k"; | |
379 | #else | |
380 | CONST char *md_shortopts = "A:"; | |
381 | #endif | |
382 | #endif | |
383 | struct option md_longopts[] = { | |
384 | #define OPTION_BUMP (OPTION_MD_BASE) | |
385 | {"bump", no_argument, NULL, OPTION_BUMP}, | |
386 | #define OPTION_SPARC (OPTION_MD_BASE + 1) | |
387 | {"sparc", no_argument, NULL, OPTION_SPARC}, | |
388 | #define OPTION_XARCH (OPTION_MD_BASE + 2) | |
389 | {"xarch", required_argument, NULL, OPTION_XARCH}, | |
390 | #ifdef OBJ_ELF | |
391 | #define OPTION_32 (OPTION_MD_BASE + 3) | |
392 | {"32", no_argument, NULL, OPTION_32}, | |
393 | #define OPTION_64 (OPTION_MD_BASE + 4) | |
394 | {"64", no_argument, NULL, OPTION_64}, | |
395 | #define OPTION_TSO (OPTION_MD_BASE + 5) | |
396 | {"TSO", no_argument, NULL, OPTION_TSO}, | |
397 | #define OPTION_PSO (OPTION_MD_BASE + 6) | |
398 | {"PSO", no_argument, NULL, OPTION_PSO}, | |
399 | #define OPTION_RMO (OPTION_MD_BASE + 7) | |
400 | {"RMO", no_argument, NULL, OPTION_RMO}, | |
401 | #endif | |
402 | #ifdef SPARC_BIENDIAN | |
403 | #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) | |
404 | {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, | |
405 | #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) | |
406 | {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, | |
407 | #endif | |
408 | #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) | |
409 | {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, | |
410 | #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) | |
411 | {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, | |
6d8809aa RH |
412 | #ifdef OBJ_ELF |
413 | #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) | |
414 | {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, | |
415 | #endif | |
252b5132 RH |
416 | {NULL, no_argument, NULL, 0} |
417 | }; | |
418 | size_t md_longopts_size = sizeof(md_longopts); | |
419 | ||
420 | int | |
421 | md_parse_option (c, arg) | |
422 | int c; | |
423 | char *arg; | |
424 | { | |
425 | /* We don't get a chance to initialize anything before we're called, | |
426 | so handle that now. */ | |
427 | if (! default_init_p) | |
428 | init_default_arch (); | |
429 | ||
430 | switch (c) | |
431 | { | |
432 | case OPTION_BUMP: | |
433 | warn_on_bump = 1; | |
434 | warn_after_architecture = SPARC_OPCODE_ARCH_V6; | |
435 | break; | |
436 | ||
437 | case OPTION_XARCH: | |
438 | /* This is for compatibility with Sun's assembler. */ | |
439 | if (strcmp (arg, "v8plus") != 0 | |
440 | && strcmp (arg, "v8plusa") != 0) | |
441 | { | |
442 | as_bad (_("invalid architecture -xarch=%s"), arg); | |
443 | return 0; | |
444 | } | |
445 | ||
446 | /* fall through */ | |
447 | ||
448 | case 'A': | |
449 | { | |
450 | struct sparc_arch *sa; | |
451 | enum sparc_opcode_arch_val opcode_arch; | |
452 | ||
453 | sa = lookup_arch (arg); | |
454 | if (sa == NULL | |
455 | || ! sa->user_option_p) | |
456 | { | |
457 | as_bad (_("invalid architecture -A%s"), arg); | |
458 | return 0; | |
459 | } | |
460 | ||
461 | opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); | |
462 | if (opcode_arch == SPARC_OPCODE_ARCH_BAD) | |
463 | as_fatal (_("Bad opcode table, broken assembler.")); | |
464 | ||
465 | max_architecture = opcode_arch; | |
466 | architecture_requested = 1; | |
467 | } | |
468 | break; | |
469 | ||
470 | case OPTION_SPARC: | |
471 | /* Ignore -sparc, used by SunOS make default .s.o rule. */ | |
472 | break; | |
473 | ||
474 | case OPTION_ENFORCE_ALIGNED_DATA: | |
475 | enforce_aligned_data = 1; | |
476 | break; | |
477 | ||
478 | #ifdef SPARC_BIENDIAN | |
479 | case OPTION_LITTLE_ENDIAN: | |
480 | target_big_endian = 0; | |
481 | if (default_arch_type != sparclet) | |
482 | as_fatal ("This target does not support -EL"); | |
483 | break; | |
484 | case OPTION_LITTLE_ENDIAN_DATA: | |
485 | target_little_endian_data = 1; | |
486 | target_big_endian = 0; | |
487 | if (default_arch_type != sparc86x | |
488 | && default_arch_type != v9) | |
489 | as_fatal ("This target does not support --little-endian-data"); | |
490 | break; | |
491 | case OPTION_BIG_ENDIAN: | |
492 | target_big_endian = 1; | |
493 | break; | |
494 | #endif | |
495 | ||
496 | #ifdef OBJ_AOUT | |
497 | case 'k': | |
498 | sparc_pic_code = 1; | |
499 | break; | |
500 | #endif | |
501 | ||
502 | #ifdef OBJ_ELF | |
503 | case OPTION_32: | |
504 | case OPTION_64: | |
505 | { | |
506 | const char **list, **l; | |
507 | ||
508 | sparc_arch_size = c == OPTION_32 ? 32 : 64; | |
509 | list = bfd_target_list (); | |
510 | for (l = list; *l != NULL; l++) | |
511 | { | |
512 | if (sparc_arch_size == 32) | |
513 | { | |
514 | if (strcmp (*l, "elf32-sparc") == 0) | |
515 | break; | |
516 | } | |
517 | else | |
518 | { | |
519 | if (strcmp (*l, "elf64-sparc") == 0) | |
520 | break; | |
521 | } | |
522 | } | |
523 | if (*l == NULL) | |
524 | as_fatal (_("No compiled in support for %d bit object file format"), | |
525 | sparc_arch_size); | |
526 | free (list); | |
527 | } | |
528 | break; | |
529 | ||
530 | case OPTION_TSO: | |
531 | sparc_memory_model = MM_TSO; | |
532 | break; | |
533 | ||
534 | case OPTION_PSO: | |
535 | sparc_memory_model = MM_PSO; | |
536 | break; | |
537 | ||
538 | case OPTION_RMO: | |
539 | sparc_memory_model = MM_RMO; | |
540 | break; | |
541 | ||
542 | case 'V': | |
543 | print_version_id (); | |
544 | break; | |
545 | ||
546 | case 'Q': | |
547 | /* Qy - do emit .comment | |
548 | Qn - do not emit .comment */ | |
549 | break; | |
550 | ||
551 | case 's': | |
552 | /* use .stab instead of .stab.excl */ | |
553 | break; | |
554 | ||
555 | case 'q': | |
556 | /* quick -- native assembler does fewer checks */ | |
557 | break; | |
558 | ||
559 | case 'K': | |
560 | if (strcmp (arg, "PIC") != 0) | |
561 | as_warn (_("Unrecognized option following -K")); | |
562 | else | |
563 | sparc_pic_code = 1; | |
564 | break; | |
6d8809aa RH |
565 | |
566 | case OPTION_NO_UNDECLARED_REGS: | |
567 | no_undeclared_regs = 1; | |
568 | break; | |
252b5132 RH |
569 | #endif |
570 | ||
571 | default: | |
572 | return 0; | |
573 | } | |
574 | ||
575 | return 1; | |
576 | } | |
577 | ||
578 | void | |
579 | md_show_usage (stream) | |
580 | FILE *stream; | |
581 | { | |
582 | const struct sparc_arch *arch; | |
583 | ||
584 | /* We don't get a chance to initialize anything before we're called, | |
585 | so handle that now. */ | |
586 | if (! default_init_p) | |
587 | init_default_arch (); | |
588 | ||
589 | fprintf(stream, _("SPARC options:\n")); | |
590 | for (arch = &sparc_arch_table[0]; arch->name; arch++) | |
591 | { | |
592 | if (arch != &sparc_arch_table[0]) | |
593 | fprintf (stream, " | "); | |
594 | if (arch->user_option_p) | |
595 | fprintf (stream, "-A%s", arch->name); | |
596 | } | |
597 | fprintf (stream, _("\n-xarch=v8plus | -xarch=v8plusa\n")); | |
598 | fprintf (stream, _("\ | |
599 | specify variant of SPARC architecture\n\ | |
600 | -bump warn when assembler switches architectures\n\ | |
601 | -sparc ignored\n\ | |
602 | --enforce-aligned-data force .long, etc., to be aligned correctly\n")); | |
603 | #ifdef OBJ_AOUT | |
604 | fprintf (stream, _("\ | |
605 | -k generate PIC\n")); | |
606 | #endif | |
607 | #ifdef OBJ_ELF | |
608 | fprintf (stream, _("\ | |
609 | -32 create 32 bit object file\n\ | |
610 | -64 create 64 bit object file\n")); | |
611 | fprintf (stream, _("\ | |
612 | [default is %d]\n"), default_arch_size); | |
613 | fprintf (stream, _("\ | |
614 | -TSO use Total Store Ordering\n\ | |
615 | -PSO use Partial Store Ordering\n\ | |
616 | -RMO use Relaxed Memory Ordering\n")); | |
617 | fprintf (stream, _("\ | |
618 | [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); | |
619 | fprintf (stream, _("\ | |
620 | -KPIC generate PIC\n\ | |
621 | -V print assembler version number\n\ | |
622 | -q ignored\n\ | |
623 | -Qy, -Qn ignored\n\ | |
624 | -s ignored\n")); | |
625 | #endif | |
626 | #ifdef SPARC_BIENDIAN | |
627 | fprintf (stream, _("\ | |
628 | -EL generate code for a little endian machine\n\ | |
629 | -EB generate code for a big endian machine\n\ | |
630 | --little-endian-data generate code for a machine having big endian\n\ | |
631 | instructions and little endian data.")); | |
632 | #endif | |
633 | } | |
634 | \f | |
cf9a1301 RH |
635 | /* native operand size opcode translation */ |
636 | struct | |
637 | { | |
638 | char *name; | |
639 | char *name32; | |
640 | char *name64; | |
641 | } native_op_table[] = | |
642 | { | |
643 | {"ldn", "ld", "ldx"}, | |
644 | {"ldna", "lda", "ldxa"}, | |
645 | {"stn", "st", "stx"}, | |
646 | {"stna", "sta", "stxa"}, | |
647 | {"slln", "sll", "sllx"}, | |
648 | {"srln", "srl", "srlx"}, | |
649 | {"sran", "sra", "srax"}, | |
650 | {"casn", "cas", "casx"}, | |
651 | {"casna", "casa", "casxa"}, | |
652 | {"clrn", "clr", "clrx"}, | |
653 | {NULL, NULL, NULL}, | |
654 | }; | |
655 | \f | |
252b5132 RH |
656 | /* sparc64 priviledged registers */ |
657 | ||
658 | struct priv_reg_entry | |
659 | { | |
660 | char *name; | |
661 | int regnum; | |
662 | }; | |
663 | ||
664 | struct priv_reg_entry priv_reg_table[] = | |
665 | { | |
666 | {"tpc", 0}, | |
667 | {"tnpc", 1}, | |
668 | {"tstate", 2}, | |
669 | {"tt", 3}, | |
670 | {"tick", 4}, | |
671 | {"tba", 5}, | |
672 | {"pstate", 6}, | |
673 | {"tl", 7}, | |
674 | {"pil", 8}, | |
675 | {"cwp", 9}, | |
676 | {"cansave", 10}, | |
677 | {"canrestore", 11}, | |
678 | {"cleanwin", 12}, | |
679 | {"otherwin", 13}, | |
680 | {"wstate", 14}, | |
681 | {"fq", 15}, | |
682 | {"ver", 31}, | |
683 | {"", -1}, /* end marker */ | |
684 | }; | |
685 | ||
686 | /* v9a specific asrs */ | |
687 | ||
688 | struct priv_reg_entry v9a_asr_table[] = | |
689 | { | |
690 | {"tick_cmpr", 23}, | |
691 | {"softint", 22}, | |
692 | {"set_softint", 20}, | |
693 | {"pic", 17}, | |
694 | {"pcr", 16}, | |
695 | {"gsr", 19}, | |
696 | {"dcr", 18}, | |
697 | {"clear_softint", 21}, | |
698 | {"", -1}, /* end marker */ | |
699 | }; | |
700 | ||
701 | static int | |
702 | cmp_reg_entry (parg, qarg) | |
703 | const PTR parg; | |
704 | const PTR qarg; | |
705 | { | |
706 | const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; | |
707 | const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; | |
708 | ||
709 | return strcmp (q->name, p->name); | |
710 | } | |
711 | \f | |
712 | /* This function is called once, at assembler startup time. It should | |
713 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
714 | ||
715 | void | |
716 | md_begin () | |
717 | { | |
718 | register const char *retval = NULL; | |
719 | int lose = 0; | |
720 | register unsigned int i = 0; | |
721 | ||
722 | /* We don't get a chance to initialize anything before md_parse_option | |
723 | is called, and it may not be called, so handle default initialization | |
724 | now if not already done. */ | |
725 | if (! default_init_p) | |
726 | init_default_arch (); | |
727 | ||
728 | op_hash = hash_new (); | |
729 | ||
730 | while (i < (unsigned int) sparc_num_opcodes) | |
731 | { | |
732 | const char *name = sparc_opcodes[i].name; | |
733 | retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]); | |
734 | if (retval != NULL) | |
735 | { | |
cf9a1301 RH |
736 | as_bad (_("Internal error: can't hash `%s': %s\n"), |
737 | sparc_opcodes[i].name, retval); | |
252b5132 RH |
738 | lose = 1; |
739 | } | |
740 | do | |
741 | { | |
742 | if (sparc_opcodes[i].match & sparc_opcodes[i].lose) | |
743 | { | |
cf9a1301 RH |
744 | as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), |
745 | sparc_opcodes[i].name, sparc_opcodes[i].args); | |
252b5132 RH |
746 | lose = 1; |
747 | } | |
748 | ++i; | |
749 | } | |
750 | while (i < (unsigned int) sparc_num_opcodes | |
751 | && !strcmp (sparc_opcodes[i].name, name)); | |
752 | } | |
753 | ||
cf9a1301 RH |
754 | for (i = 0; native_op_table[i].name; i++) |
755 | { | |
756 | const struct sparc_opcode *insn; | |
757 | char *name = sparc_arch_size == 32 ? native_op_table[i].name32 : | |
758 | native_op_table[i].name64; | |
759 | insn = (struct sparc_opcode *)hash_find (op_hash, name); | |
760 | if (insn == NULL) | |
761 | { | |
762 | as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), | |
763 | name, native_op_table[i].name); | |
764 | lose = 1; | |
765 | } | |
766 | else | |
767 | { | |
768 | retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn); | |
769 | if (retval != NULL) | |
770 | { | |
771 | as_bad (_("Internal error: can't hash `%s': %s\n"), | |
772 | sparc_opcodes[i].name, retval); | |
773 | lose = 1; | |
774 | } | |
775 | } | |
776 | } | |
777 | ||
252b5132 RH |
778 | if (lose) |
779 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
780 | ||
252b5132 RH |
781 | qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), |
782 | sizeof (priv_reg_table[0]), cmp_reg_entry); | |
783 | ||
784 | /* If -bump, record the architecture level at which we start issuing | |
785 | warnings. The behaviour is different depending upon whether an | |
786 | architecture was explicitly specified. If it wasn't, we issue warnings | |
787 | for all upwards bumps. If it was, we don't start issuing warnings until | |
788 | we need to bump beyond the requested architecture or when we bump between | |
789 | conflicting architectures. */ | |
790 | ||
791 | if (warn_on_bump | |
792 | && architecture_requested) | |
793 | { | |
794 | /* `max_architecture' records the requested architecture. | |
795 | Issue warnings if we go above it. */ | |
796 | warn_after_architecture = max_architecture; | |
797 | ||
798 | /* Find the highest architecture level that doesn't conflict with | |
799 | the requested one. */ | |
800 | for (max_architecture = SPARC_OPCODE_ARCH_MAX; | |
801 | max_architecture > warn_after_architecture; | |
802 | --max_architecture) | |
803 | if (! SPARC_OPCODE_CONFLICT_P (max_architecture, | |
804 | warn_after_architecture)) | |
805 | break; | |
806 | } | |
807 | } | |
808 | ||
809 | /* Called after all assembly has been done. */ | |
810 | ||
811 | void | |
812 | sparc_md_end () | |
813 | { | |
814 | if (sparc_arch_size == 64) | |
815 | { | |
816 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
817 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a); | |
818 | else | |
819 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9); | |
820 | } | |
821 | else | |
822 | { | |
823 | if (current_architecture == SPARC_OPCODE_ARCH_V9) | |
824 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus); | |
825 | else if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
826 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa); | |
827 | else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET) | |
828 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet); | |
829 | else if (default_arch_type == sparc86x && target_little_endian_data) | |
830 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le); | |
831 | else | |
832 | { | |
833 | /* The sparclite is treated like a normal sparc. Perhaps it shouldn't | |
834 | be but for now it is (since that's the way it's always been | |
835 | treated). */ | |
836 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc); | |
837 | } | |
838 | } | |
839 | } | |
840 | \f | |
841 | /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ | |
842 | ||
843 | static INLINE int | |
844 | in_signed_range (val, max) | |
845 | bfd_signed_vma val, max; | |
846 | { | |
847 | if (max <= 0) | |
848 | abort (); | |
849 | /* Sign-extend the value from the architecture word size, so that | |
850 | 0xffffffff is always considered -1 on sparc32. */ | |
851 | if (sparc_arch_size == 32) | |
852 | { | |
853 | bfd_signed_vma sign = (bfd_signed_vma)1 << 31; | |
854 | val = ((val & 0xffffffff) ^ sign) - sign; | |
855 | } | |
856 | if (val > max) | |
857 | return 0; | |
858 | if (val < ~max) | |
859 | return 0; | |
860 | return 1; | |
861 | } | |
862 | ||
863 | /* Return non-zero if VAL is in the range 0 to MAX. */ | |
864 | ||
865 | static INLINE int | |
866 | in_unsigned_range (val, max) | |
867 | bfd_vma val, max; | |
868 | { | |
869 | if (val > max) | |
870 | return 0; | |
871 | return 1; | |
872 | } | |
873 | ||
874 | /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. | |
875 | (e.g. -15 to +31). */ | |
876 | ||
877 | static INLINE int | |
878 | in_bitfield_range (val, max) | |
879 | bfd_signed_vma val, max; | |
880 | { | |
881 | if (max <= 0) | |
882 | abort (); | |
883 | if (val > max) | |
884 | return 0; | |
885 | if (val < ~(max >> 1)) | |
886 | return 0; | |
887 | return 1; | |
888 | } | |
889 | ||
890 | static int | |
891 | sparc_ffs (mask) | |
892 | unsigned int mask; | |
893 | { | |
894 | int i; | |
895 | ||
896 | if (mask == 0) | |
897 | return -1; | |
898 | ||
899 | for (i = 0; (mask & 1) == 0; ++i) | |
900 | mask >>= 1; | |
901 | return i; | |
902 | } | |
903 | ||
904 | /* Implement big shift right. */ | |
905 | static bfd_vma | |
906 | BSR (val, amount) | |
907 | bfd_vma val; | |
908 | int amount; | |
909 | { | |
910 | if (sizeof (bfd_vma) <= 4 && amount >= 32) | |
911 | as_fatal (_("Support for 64-bit arithmetic not compiled in.")); | |
912 | return val >> amount; | |
913 | } | |
914 | \f | |
915 | /* For communication between sparc_ip and get_expression. */ | |
916 | static char *expr_end; | |
917 | ||
252b5132 RH |
918 | /* Values for `special_case'. |
919 | Instructions that require wierd handling because they're longer than | |
920 | 4 bytes. */ | |
921 | #define SPECIAL_CASE_NONE 0 | |
922 | #define SPECIAL_CASE_SET 1 | |
923 | #define SPECIAL_CASE_SETSW 2 | |
924 | #define SPECIAL_CASE_SETX 3 | |
925 | /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ | |
926 | #define SPECIAL_CASE_FDIV 4 | |
927 | ||
928 | /* Bit masks of various insns. */ | |
929 | #define NOP_INSN 0x01000000 | |
930 | #define OR_INSN 0x80100000 | |
63fab58c | 931 | #define XOR_INSN 0x80180000 |
252b5132 RH |
932 | #define FMOVS_INSN 0x81A00020 |
933 | #define SETHI_INSN 0x01000000 | |
934 | #define SLLX_INSN 0x81281000 | |
935 | #define SRA_INSN 0x81380000 | |
936 | ||
937 | /* The last instruction to be assembled. */ | |
938 | static const struct sparc_opcode *last_insn; | |
939 | /* The assembled opcode of `last_insn'. */ | |
940 | static unsigned long last_opcode; | |
941 | \f | |
a22b281c RH |
942 | /* Handle the set and setuw synthetic instructions. */ |
943 | static void | |
944 | synthetize_setuw (insn) | |
945 | const struct sparc_opcode *insn; | |
946 | { | |
947 | int need_hi22_p = 0; | |
948 | int rd = (the_insn.opcode & RD (~0)) >> 25; | |
949 | ||
950 | if (the_insn.exp.X_op == O_constant) | |
951 | { | |
952 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
953 | { | |
954 | if (sizeof(offsetT) > 4 | |
955 | && (the_insn.exp.X_add_number < 0 | |
956 | || the_insn.exp.X_add_number > (offsetT) 0xffffffff)) | |
957 | as_warn (_("set: number not in 0..4294967295 range")); | |
958 | } | |
959 | else | |
960 | { | |
961 | if (sizeof(offsetT) > 4 | |
962 | && (the_insn.exp.X_add_number < -(offsetT) 0x80000000 | |
963 | || the_insn.exp.X_add_number > (offsetT) 0xffffffff)) | |
964 | as_warn (_("set: number not in -2147483648..4294967295 range")); | |
965 | the_insn.exp.X_add_number = (int)the_insn.exp.X_add_number; | |
966 | } | |
967 | } | |
968 | ||
969 | /* See if operand is absolute and small; skip sethi if so. */ | |
970 | if (the_insn.exp.X_op != O_constant | |
971 | || the_insn.exp.X_add_number >= (1 << 12) | |
972 | || the_insn.exp.X_add_number < -(1 << 12)) | |
973 | { | |
974 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
975 | | ((the_insn.exp.X_add_number >> 10) | |
976 | & (the_insn.exp.X_op == O_constant ? 0x3fffff : 0))); | |
977 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
978 | ? BFD_RELOC_HI22 | |
979 | : BFD_RELOC_NONE); | |
980 | output_insn (insn, &the_insn); | |
981 | need_hi22_p = 1; | |
982 | } | |
983 | ||
984 | /* See if operand has no low-order bits; skip OR if so. */ | |
985 | if (the_insn.exp.X_op != O_constant | |
986 | || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) | |
987 | || ! need_hi22_p) | |
988 | { | |
989 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) | |
990 | | RD (rd) | IMMED | |
991 | | (the_insn.exp.X_add_number | |
992 | & (the_insn.exp.X_op != O_constant ? 0 : | |
993 | need_hi22_p ? 0x3ff : 0x1fff))); | |
994 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
995 | ? BFD_RELOC_LO10 | |
996 | : BFD_RELOC_NONE); | |
997 | output_insn (insn, &the_insn); | |
998 | } | |
999 | } | |
1000 | ||
1001 | /* Handle the setsw synthetic instruction. */ | |
1002 | static void | |
1003 | synthetize_setsw (insn) | |
1004 | const struct sparc_opcode *insn; | |
1005 | { | |
1006 | int low32, rd, opc; | |
1007 | ||
1008 | rd = (the_insn.opcode & RD (~0)) >> 25; | |
1009 | ||
1010 | if (the_insn.exp.X_op != O_constant) | |
1011 | { | |
1012 | synthetize_setuw (insn); | |
1013 | ||
1014 | /* Need to sign extend it. */ | |
1015 | the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); | |
1016 | the_insn.reloc = BFD_RELOC_NONE; | |
1017 | output_insn (insn, &the_insn); | |
1018 | return; | |
1019 | } | |
1020 | ||
1021 | if (sizeof(offsetT) > 4 | |
1022 | && (the_insn.exp.X_add_number < -(offsetT) 0x80000000 | |
1023 | || the_insn.exp.X_add_number > (offsetT) 0xffffffff)) | |
1024 | as_warn (_("setsw: number not in -2147483648..4294967295 range")); | |
1025 | ||
1026 | low32 = the_insn.exp.X_add_number; | |
1027 | ||
1028 | if (low32 >= 0) | |
1029 | { | |
1030 | synthetize_setuw (insn); | |
1031 | return; | |
1032 | } | |
1033 | ||
1034 | opc = OR_INSN; | |
1035 | ||
1036 | the_insn.reloc = BFD_RELOC_NONE; | |
1037 | /* See if operand is absolute and small; skip sethi if so. */ | |
1038 | if (low32 < -(1 << 12)) | |
1039 | { | |
1040 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1041 | | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); | |
1042 | output_insn (insn, &the_insn); | |
1043 | low32 = 0x1c00 | (low32 & 0x3ff); | |
1044 | opc = RS1 (rd) | XOR_INSN; | |
1045 | } | |
1046 | ||
1047 | the_insn.opcode = (opc | RD (rd) | IMMED | |
1048 | | (low32 & 0x1fff)); | |
1049 | output_insn (insn, &the_insn); | |
1050 | } | |
1051 | ||
1052 | /* Handle the setsw synthetic instruction. */ | |
1053 | static void | |
1054 | synthetize_setx (insn) | |
1055 | const struct sparc_opcode *insn; | |
1056 | { | |
1057 | int upper32, lower32; | |
1058 | int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; | |
1059 | int dstreg = (the_insn.opcode & RD (~0)) >> 25; | |
1060 | int upper_dstreg; | |
1061 | int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; | |
1062 | int need_xor10_p = 0; | |
1063 | ||
1064 | #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000) | |
1065 | lower32 = SIGNEXT32 (the_insn.exp.X_add_number); | |
1066 | upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); | |
1067 | #undef SIGNEXT32 | |
1068 | ||
1069 | upper_dstreg = tmpreg; | |
1070 | /* The tmp reg should not be the dst reg. */ | |
1071 | if (tmpreg == dstreg) | |
1072 | as_warn (_("setx: temporary register same as destination register")); | |
1073 | ||
1074 | /* ??? Obviously there are other optimizations we can do | |
1075 | (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be | |
1076 | doing some of these. Later. If you do change things, try to | |
1077 | change all of this to be table driven as well. */ | |
1078 | /* What to output depends on the number if it's constant. | |
1079 | Compute that first, then output what we've decided upon. */ | |
1080 | if (the_insn.exp.X_op != O_constant) | |
1081 | { | |
1082 | if (sparc_arch_size == 32) | |
1083 | { | |
1084 | /* When arch size is 32, we want setx to be equivalent | |
1085 | to setuw for anything but constants. */ | |
1086 | the_insn.exp.X_add_number &= 0xffffffff; | |
1087 | synthetize_setuw (insn); | |
1088 | return; | |
1089 | } | |
1090 | need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; | |
1091 | lower32 = 0; upper32 = 0; | |
1092 | } | |
1093 | else | |
1094 | { | |
1095 | /* Reset X_add_number, we've extracted it as upper32/lower32. | |
1096 | Otherwise fixup_segment will complain about not being able to | |
1097 | write an 8 byte number in a 4 byte field. */ | |
1098 | the_insn.exp.X_add_number = 0; | |
1099 | ||
1100 | /* Only need hh22 if `or' insn can't handle constant. */ | |
1101 | if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) | |
1102 | need_hh22_p = 1; | |
1103 | ||
1104 | /* Does bottom part (after sethi) have bits? */ | |
1105 | if ((need_hh22_p && (upper32 & 0x3ff) != 0) | |
1106 | /* No hh22, but does upper32 still have bits we can't set | |
1107 | from lower32? */ | |
1108 | || (! need_hh22_p && upper32 != 0 && upper32 != -1)) | |
1109 | need_hm10_p = 1; | |
1110 | ||
1111 | /* If the lower half is all zero, we build the upper half directly | |
1112 | into the dst reg. */ | |
1113 | if (lower32 != 0 | |
1114 | /* Need lower half if number is zero or 0xffffffff00000000. */ | |
1115 | || (! need_hh22_p && ! need_hm10_p)) | |
1116 | { | |
1117 | /* No need for sethi if `or' insn can handle constant. */ | |
1118 | if (lower32 < -(1 << 12) || lower32 >= (1 << 12) | |
1119 | /* Note that we can't use a negative constant in the `or' | |
1120 | insn unless the upper 32 bits are all ones. */ | |
1121 | || (lower32 < 0 && upper32 != -1) | |
1122 | || (lower32 >= 0 && upper32 == -1)) | |
1123 | need_hi22_p = 1; | |
1124 | ||
1125 | if (need_hi22_p && upper32 == -1) | |
1126 | need_xor10_p = 1; | |
1127 | ||
1128 | /* Does bottom part (after sethi) have bits? */ | |
1129 | else if ((need_hi22_p && (lower32 & 0x3ff) != 0) | |
1130 | /* No sethi. */ | |
1131 | || (! need_hi22_p && (lower32 & 0x1fff) != 0) | |
1132 | /* Need `or' if we didn't set anything else. */ | |
1133 | || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) | |
1134 | need_lo10_p = 1; | |
1135 | } | |
1136 | else | |
1137 | /* Output directly to dst reg if lower 32 bits are all zero. */ | |
1138 | upper_dstreg = dstreg; | |
1139 | } | |
1140 | ||
1141 | if (!upper_dstreg && dstreg) | |
1142 | as_warn (_("setx: illegal temporary register g0")); | |
1143 | ||
1144 | if (need_hh22_p) | |
1145 | { | |
1146 | the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) | |
1147 | | ((upper32 >> 10) & 0x3fffff)); | |
1148 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1149 | ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); | |
1150 | output_insn (insn, &the_insn); | |
1151 | } | |
1152 | ||
1153 | if (need_hi22_p) | |
1154 | { | |
1155 | the_insn.opcode = (SETHI_INSN | RD (dstreg) | |
1156 | | (((need_xor10_p ? ~lower32 : lower32) | |
1157 | >> 10) & 0x3fffff)); | |
1158 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1159 | ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); | |
1160 | output_insn (insn, &the_insn); | |
1161 | } | |
1162 | ||
1163 | if (need_hm10_p) | |
1164 | { | |
1165 | the_insn.opcode = (OR_INSN | |
1166 | | (need_hh22_p ? RS1 (upper_dstreg) : 0) | |
1167 | | RD (upper_dstreg) | |
1168 | | IMMED | |
1169 | | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); | |
1170 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1171 | ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); | |
1172 | output_insn (insn, &the_insn); | |
1173 | } | |
1174 | ||
1175 | if (need_lo10_p) | |
1176 | { | |
1177 | /* FIXME: One nice optimization to do here is to OR the low part | |
1178 | with the highpart if hi22 isn't needed and the low part is | |
1179 | positive. */ | |
1180 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) | |
1181 | | RD (dstreg) | |
1182 | | IMMED | |
1183 | | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); | |
1184 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1185 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); | |
1186 | output_insn (insn, &the_insn); | |
1187 | } | |
1188 | ||
1189 | /* If we needed to build the upper part, shift it into place. */ | |
1190 | if (need_hh22_p || need_hm10_p) | |
1191 | { | |
1192 | the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) | |
1193 | | IMMED | 32); | |
1194 | the_insn.reloc = BFD_RELOC_NONE; | |
1195 | output_insn (insn, &the_insn); | |
1196 | } | |
1197 | ||
1198 | /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ | |
1199 | if (need_xor10_p) | |
1200 | { | |
1201 | the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED | |
1202 | | 0x1c00 | (lower32 & 0x3ff)); | |
1203 | the_insn.reloc = BFD_RELOC_NONE; | |
1204 | output_insn (insn, &the_insn); | |
1205 | } | |
1206 | ||
1207 | /* If we needed to build both upper and lower parts, OR them together. */ | |
1208 | else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) | |
1209 | { | |
1210 | the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) | |
1211 | | RD (dstreg)); | |
1212 | the_insn.reloc = BFD_RELOC_NONE; | |
1213 | output_insn (insn, &the_insn); | |
1214 | } | |
1215 | } | |
1216 | \f | |
252b5132 RH |
1217 | /* Main entry point to assemble one instruction. */ |
1218 | ||
1219 | void | |
1220 | md_assemble (str) | |
1221 | char *str; | |
1222 | { | |
1223 | const struct sparc_opcode *insn; | |
a22b281c | 1224 | int special_case; |
252b5132 RH |
1225 | |
1226 | know (str); | |
a22b281c | 1227 | special_case = sparc_ip (str, &insn); |
252b5132 RH |
1228 | |
1229 | /* We warn about attempts to put a floating point branch in a delay slot, | |
1230 | unless the delay slot has been annulled. */ | |
1231 | if (insn != NULL | |
1232 | && last_insn != NULL | |
1233 | && (insn->flags & F_FBR) != 0 | |
1234 | && (last_insn->flags & F_DELAYED) != 0 | |
1235 | /* ??? This test isn't completely accurate. We assume anything with | |
1236 | F_{UNBR,CONDBR,FBR} set is annullable. */ | |
1237 | && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 | |
1238 | || (last_opcode & ANNUL) == 0)) | |
1239 | as_warn (_("FP branch in delay slot")); | |
1240 | ||
1241 | /* SPARC before v9 requires a nop instruction between a floating | |
1242 | point instruction and a floating point branch. We insert one | |
1243 | automatically, with a warning. */ | |
1244 | if (max_architecture < SPARC_OPCODE_ARCH_V9 | |
1245 | && insn != NULL | |
1246 | && last_insn != NULL | |
1247 | && (insn->flags & F_FBR) != 0 | |
1248 | && (last_insn->flags & F_FLOAT) != 0) | |
1249 | { | |
1250 | struct sparc_it nop_insn; | |
1251 | ||
1252 | nop_insn.opcode = NOP_INSN; | |
1253 | nop_insn.reloc = BFD_RELOC_NONE; | |
1254 | output_insn (insn, &nop_insn); | |
1255 | as_warn (_("FP branch preceded by FP instruction; NOP inserted")); | |
1256 | } | |
1257 | ||
a22b281c RH |
1258 | switch (special_case) |
1259 | { | |
1260 | case SPECIAL_CASE_NONE: | |
1261 | /* normal insn */ | |
1262 | output_insn (insn, &the_insn); | |
1263 | break; | |
252b5132 | 1264 | |
a22b281c RH |
1265 | case SPECIAL_CASE_SETSW: |
1266 | synthetize_setsw (insn); | |
1267 | break; | |
1268 | ||
1269 | case SPECIAL_CASE_SET: | |
1270 | synthetize_setuw (insn); | |
1271 | break; | |
252b5132 | 1272 | |
a22b281c RH |
1273 | case SPECIAL_CASE_SETX: |
1274 | synthetize_setx (insn); | |
1275 | break; | |
1276 | ||
1277 | case SPECIAL_CASE_FDIV: | |
1278 | { | |
1279 | int rd = (the_insn.opcode >> 25) & 0x1f; | |
63fab58c | 1280 | |
a22b281c | 1281 | output_insn (insn, &the_insn); |
63fab58c | 1282 | |
a22b281c RH |
1283 | /* According to information leaked from Sun, the "fdiv" instructions |
1284 | on early SPARC machines would produce incorrect results sometimes. | |
1285 | The workaround is to add an fmovs of the destination register to | |
1286 | itself just after the instruction. This was true on machines | |
1287 | with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ | |
1288 | assert (the_insn.reloc == BFD_RELOC_NONE); | |
1289 | the_insn.opcode = FMOVS_INSN | rd | RD (rd); | |
1290 | output_insn (insn, &the_insn); | |
1291 | return; | |
1292 | } | |
63fab58c | 1293 | |
a22b281c RH |
1294 | default: |
1295 | as_fatal (_("failed special case insn sanity check")); | |
252b5132 RH |
1296 | } |
1297 | } | |
1298 | ||
1299 | /* Subroutine of md_assemble to do the actual parsing. */ | |
1300 | ||
a22b281c | 1301 | static int |
252b5132 RH |
1302 | sparc_ip (str, pinsn) |
1303 | char *str; | |
1304 | const struct sparc_opcode **pinsn; | |
1305 | { | |
1306 | char *error_message = ""; | |
1307 | char *s; | |
1308 | const char *args; | |
1309 | char c; | |
1310 | const struct sparc_opcode *insn; | |
1311 | char *argsStart; | |
1312 | unsigned long opcode; | |
1313 | unsigned int mask = 0; | |
1314 | int match = 0; | |
1315 | int comma = 0; | |
1316 | int v9_arg_p; | |
a22b281c | 1317 | int special_case = SPECIAL_CASE_NONE; |
252b5132 RH |
1318 | |
1319 | s = str; | |
1320 | if (islower ((unsigned char) *s)) | |
1321 | { | |
1322 | do | |
1323 | ++s; | |
1324 | while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s)); | |
1325 | } | |
1326 | ||
1327 | switch (*s) | |
1328 | { | |
1329 | case '\0': | |
1330 | break; | |
1331 | ||
1332 | case ',': | |
1333 | comma = 1; | |
1334 | ||
1335 | /*FALLTHROUGH */ | |
1336 | ||
1337 | case ' ': | |
1338 | *s++ = '\0'; | |
1339 | break; | |
1340 | ||
1341 | default: | |
1342 | as_fatal (_("Unknown opcode: `%s'"), str); | |
1343 | } | |
1344 | insn = (struct sparc_opcode *) hash_find (op_hash, str); | |
1345 | *pinsn = insn; | |
1346 | if (insn == NULL) | |
1347 | { | |
1348 | as_bad (_("Unknown opcode: `%s'"), str); | |
a22b281c | 1349 | return special_case; |
252b5132 RH |
1350 | } |
1351 | if (comma) | |
1352 | { | |
1353 | *--s = ','; | |
1354 | } | |
1355 | ||
1356 | argsStart = s; | |
1357 | for (;;) | |
1358 | { | |
1359 | opcode = insn->match; | |
1360 | memset (&the_insn, '\0', sizeof (the_insn)); | |
1361 | the_insn.reloc = BFD_RELOC_NONE; | |
1362 | v9_arg_p = 0; | |
1363 | ||
1364 | /* | |
1365 | * Build the opcode, checking as we go to make | |
1366 | * sure that the operands match | |
1367 | */ | |
1368 | for (args = insn->args;; ++args) | |
1369 | { | |
1370 | switch (*args) | |
1371 | { | |
1372 | case 'K': | |
1373 | { | |
1374 | int kmask = 0; | |
1375 | ||
1376 | /* Parse a series of masks. */ | |
1377 | if (*s == '#') | |
1378 | { | |
1379 | while (*s == '#') | |
1380 | { | |
1381 | int mask; | |
1382 | ||
1383 | if (! parse_keyword_arg (sparc_encode_membar, &s, | |
1384 | &mask)) | |
1385 | { | |
1386 | error_message = _(": invalid membar mask name"); | |
1387 | goto error; | |
1388 | } | |
1389 | kmask |= mask; | |
1390 | while (*s == ' ') { ++s; continue; } | |
1391 | if (*s == '|' || *s == '+') | |
1392 | ++s; | |
1393 | while (*s == ' ') { ++s; continue; } | |
1394 | } | |
1395 | } | |
1396 | else | |
1397 | { | |
1398 | if (! parse_const_expr_arg (&s, &kmask)) | |
1399 | { | |
1400 | error_message = _(": invalid membar mask expression"); | |
1401 | goto error; | |
1402 | } | |
1403 | if (kmask < 0 || kmask > 127) | |
1404 | { | |
1405 | error_message = _(": invalid membar mask number"); | |
1406 | goto error; | |
1407 | } | |
1408 | } | |
1409 | ||
1410 | opcode |= MEMBAR (kmask); | |
1411 | continue; | |
1412 | } | |
1413 | ||
1414 | case '*': | |
1415 | { | |
1416 | int fcn = 0; | |
1417 | ||
1418 | /* Parse a prefetch function. */ | |
1419 | if (*s == '#') | |
1420 | { | |
1421 | if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) | |
1422 | { | |
1423 | error_message = _(": invalid prefetch function name"); | |
1424 | goto error; | |
1425 | } | |
1426 | } | |
1427 | else | |
1428 | { | |
1429 | if (! parse_const_expr_arg (&s, &fcn)) | |
1430 | { | |
1431 | error_message = _(": invalid prefetch function expression"); | |
1432 | goto error; | |
1433 | } | |
1434 | if (fcn < 0 || fcn > 31) | |
1435 | { | |
1436 | error_message = _(": invalid prefetch function number"); | |
1437 | goto error; | |
1438 | } | |
1439 | } | |
1440 | opcode |= RD (fcn); | |
1441 | continue; | |
1442 | } | |
1443 | ||
1444 | case '!': | |
1445 | case '?': | |
1446 | /* Parse a sparc64 privileged register. */ | |
1447 | if (*s == '%') | |
1448 | { | |
1449 | struct priv_reg_entry *p = priv_reg_table; | |
1450 | unsigned int len = 9999999; /* init to make gcc happy */ | |
1451 | ||
1452 | s += 1; | |
1453 | while (p->name[0] > s[0]) | |
1454 | p++; | |
1455 | while (p->name[0] == s[0]) | |
1456 | { | |
1457 | len = strlen (p->name); | |
1458 | if (strncmp (p->name, s, len) == 0) | |
1459 | break; | |
1460 | p++; | |
1461 | } | |
1462 | if (p->name[0] != s[0]) | |
1463 | { | |
1464 | error_message = _(": unrecognizable privileged register"); | |
1465 | goto error; | |
1466 | } | |
1467 | if (*args == '?') | |
1468 | opcode |= (p->regnum << 14); | |
1469 | else | |
1470 | opcode |= (p->regnum << 25); | |
1471 | s += len; | |
1472 | continue; | |
1473 | } | |
1474 | else | |
1475 | { | |
1476 | error_message = _(": unrecognizable privileged register"); | |
1477 | goto error; | |
1478 | } | |
1479 | ||
1480 | case '_': | |
1481 | case '/': | |
1482 | /* Parse a v9a ancillary state register. */ | |
1483 | if (*s == '%') | |
1484 | { | |
1485 | struct priv_reg_entry *p = v9a_asr_table; | |
1486 | unsigned int len = 9999999; /* init to make gcc happy */ | |
1487 | ||
1488 | s += 1; | |
1489 | while (p->name[0] > s[0]) | |
1490 | p++; | |
1491 | while (p->name[0] == s[0]) | |
1492 | { | |
1493 | len = strlen (p->name); | |
1494 | if (strncmp (p->name, s, len) == 0) | |
1495 | break; | |
1496 | p++; | |
1497 | } | |
1498 | if (p->name[0] != s[0]) | |
1499 | { | |
1500 | error_message = _(": unrecognizable v9a ancillary state register"); | |
1501 | goto error; | |
1502 | } | |
1503 | if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) | |
1504 | { | |
1505 | error_message = _(": rd on write only ancillary state register"); | |
1506 | goto error; | |
1507 | } | |
1508 | if (*args == '/') | |
1509 | opcode |= (p->regnum << 14); | |
1510 | else | |
1511 | opcode |= (p->regnum << 25); | |
1512 | s += len; | |
1513 | continue; | |
1514 | } | |
1515 | else | |
1516 | { | |
1517 | error_message = _(": unrecognizable v9a ancillary state register"); | |
1518 | goto error; | |
1519 | } | |
1520 | ||
1521 | case 'M': | |
1522 | case 'm': | |
1523 | if (strncmp (s, "%asr", 4) == 0) | |
1524 | { | |
1525 | s += 4; | |
1526 | ||
1527 | if (isdigit ((unsigned char) *s)) | |
1528 | { | |
1529 | long num = 0; | |
1530 | ||
1531 | while (isdigit ((unsigned char) *s)) | |
1532 | { | |
1533 | num = num * 10 + *s - '0'; | |
1534 | ++s; | |
1535 | } | |
1536 | ||
1537 | if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
1538 | { | |
1539 | if (num < 16 || 31 < num) | |
1540 | { | |
1541 | error_message = _(": asr number must be between 16 and 31"); | |
1542 | goto error; | |
1543 | } | |
1544 | } | |
1545 | else | |
1546 | { | |
1547 | if (num < 0 || 31 < num) | |
1548 | { | |
1549 | error_message = _(": asr number must be between 0 and 31"); | |
1550 | goto error; | |
1551 | } | |
1552 | } | |
1553 | ||
1554 | opcode |= (*args == 'M' ? RS1 (num) : RD (num)); | |
1555 | continue; | |
1556 | } | |
1557 | else | |
1558 | { | |
1559 | error_message = _(": expecting %asrN"); | |
1560 | goto error; | |
1561 | } | |
1562 | } /* if %asr */ | |
1563 | break; | |
1564 | ||
1565 | case 'I': | |
1566 | the_insn.reloc = BFD_RELOC_SPARC_11; | |
1567 | goto immediate; | |
1568 | ||
1569 | case 'j': | |
1570 | the_insn.reloc = BFD_RELOC_SPARC_10; | |
1571 | goto immediate; | |
1572 | ||
1573 | case 'X': | |
1574 | /* V8 systems don't understand BFD_RELOC_SPARC_5. */ | |
1575 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1576 | the_insn.reloc = BFD_RELOC_SPARC_5; | |
1577 | else | |
1578 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1579 | /* These fields are unsigned, but for upward compatibility, | |
1580 | allow negative values as well. */ | |
1581 | goto immediate; | |
1582 | ||
1583 | case 'Y': | |
1584 | /* V8 systems don't understand BFD_RELOC_SPARC_6. */ | |
1585 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1586 | the_insn.reloc = BFD_RELOC_SPARC_6; | |
1587 | else | |
1588 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1589 | /* These fields are unsigned, but for upward compatibility, | |
1590 | allow negative values as well. */ | |
1591 | goto immediate; | |
1592 | ||
1593 | case 'k': | |
1594 | the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; | |
1595 | the_insn.pcrel = 1; | |
1596 | goto immediate; | |
1597 | ||
1598 | case 'G': | |
1599 | the_insn.reloc = BFD_RELOC_SPARC_WDISP19; | |
1600 | the_insn.pcrel = 1; | |
1601 | goto immediate; | |
1602 | ||
1603 | case 'N': | |
1604 | if (*s == 'p' && s[1] == 'n') | |
1605 | { | |
1606 | s += 2; | |
1607 | continue; | |
1608 | } | |
1609 | break; | |
1610 | ||
1611 | case 'T': | |
1612 | if (*s == 'p' && s[1] == 't') | |
1613 | { | |
1614 | s += 2; | |
1615 | continue; | |
1616 | } | |
1617 | break; | |
1618 | ||
1619 | case 'z': | |
1620 | if (*s == ' ') | |
1621 | { | |
1622 | ++s; | |
1623 | } | |
1624 | if (strncmp (s, "%icc", 4) == 0) | |
1625 | { | |
1626 | s += 4; | |
1627 | continue; | |
1628 | } | |
1629 | break; | |
1630 | ||
1631 | case 'Z': | |
1632 | if (*s == ' ') | |
1633 | { | |
1634 | ++s; | |
1635 | } | |
1636 | if (strncmp (s, "%xcc", 4) == 0) | |
1637 | { | |
1638 | s += 4; | |
1639 | continue; | |
1640 | } | |
1641 | break; | |
1642 | ||
1643 | case '6': | |
1644 | if (*s == ' ') | |
1645 | { | |
1646 | ++s; | |
1647 | } | |
1648 | if (strncmp (s, "%fcc0", 5) == 0) | |
1649 | { | |
1650 | s += 5; | |
1651 | continue; | |
1652 | } | |
1653 | break; | |
1654 | ||
1655 | case '7': | |
1656 | if (*s == ' ') | |
1657 | { | |
1658 | ++s; | |
1659 | } | |
1660 | if (strncmp (s, "%fcc1", 5) == 0) | |
1661 | { | |
1662 | s += 5; | |
1663 | continue; | |
1664 | } | |
1665 | break; | |
1666 | ||
1667 | case '8': | |
1668 | if (*s == ' ') | |
1669 | { | |
1670 | ++s; | |
1671 | } | |
1672 | if (strncmp (s, "%fcc2", 5) == 0) | |
1673 | { | |
1674 | s += 5; | |
1675 | continue; | |
1676 | } | |
1677 | break; | |
1678 | ||
1679 | case '9': | |
1680 | if (*s == ' ') | |
1681 | { | |
1682 | ++s; | |
1683 | } | |
1684 | if (strncmp (s, "%fcc3", 5) == 0) | |
1685 | { | |
1686 | s += 5; | |
1687 | continue; | |
1688 | } | |
1689 | break; | |
1690 | ||
1691 | case 'P': | |
1692 | if (strncmp (s, "%pc", 3) == 0) | |
1693 | { | |
1694 | s += 3; | |
1695 | continue; | |
1696 | } | |
1697 | break; | |
1698 | ||
1699 | case 'W': | |
1700 | if (strncmp (s, "%tick", 5) == 0) | |
1701 | { | |
1702 | s += 5; | |
1703 | continue; | |
1704 | } | |
1705 | break; | |
1706 | ||
1707 | case '\0': /* end of args */ | |
1708 | if (*s == '\0') | |
1709 | { | |
1710 | match = 1; | |
1711 | } | |
1712 | break; | |
1713 | ||
1714 | case '+': | |
1715 | if (*s == '+') | |
1716 | { | |
1717 | ++s; | |
1718 | continue; | |
1719 | } | |
1720 | if (*s == '-') | |
1721 | { | |
1722 | continue; | |
1723 | } | |
1724 | break; | |
1725 | ||
1726 | case '[': /* these must match exactly */ | |
1727 | case ']': | |
1728 | case ',': | |
1729 | case ' ': | |
1730 | if (*s++ == *args) | |
1731 | continue; | |
1732 | break; | |
1733 | ||
1734 | case '#': /* must be at least one digit */ | |
1735 | if (isdigit ((unsigned char) *s++)) | |
1736 | { | |
1737 | while (isdigit ((unsigned char) *s)) | |
1738 | { | |
1739 | ++s; | |
1740 | } | |
1741 | continue; | |
1742 | } | |
1743 | break; | |
1744 | ||
1745 | case 'C': /* coprocessor state register */ | |
1746 | if (strncmp (s, "%csr", 4) == 0) | |
1747 | { | |
1748 | s += 4; | |
1749 | continue; | |
1750 | } | |
1751 | break; | |
1752 | ||
1753 | case 'b': /* next operand is a coprocessor register */ | |
1754 | case 'c': | |
1755 | case 'D': | |
1756 | if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s)) | |
1757 | { | |
1758 | mask = *s++; | |
1759 | if (isdigit ((unsigned char) *s)) | |
1760 | { | |
1761 | mask = 10 * (mask - '0') + (*s++ - '0'); | |
1762 | if (mask >= 32) | |
1763 | { | |
1764 | break; | |
1765 | } | |
1766 | } | |
1767 | else | |
1768 | { | |
1769 | mask -= '0'; | |
1770 | } | |
1771 | switch (*args) | |
1772 | { | |
1773 | ||
1774 | case 'b': | |
1775 | opcode |= mask << 14; | |
1776 | continue; | |
1777 | ||
1778 | case 'c': | |
1779 | opcode |= mask; | |
1780 | continue; | |
1781 | ||
1782 | case 'D': | |
1783 | opcode |= mask << 25; | |
1784 | continue; | |
1785 | } | |
1786 | } | |
1787 | break; | |
1788 | ||
1789 | case 'r': /* next operand must be a register */ | |
1790 | case 'O': | |
1791 | case '1': | |
1792 | case '2': | |
1793 | case 'd': | |
1794 | if (*s++ == '%') | |
1795 | { | |
1796 | switch (c = *s++) | |
1797 | { | |
1798 | ||
1799 | case 'f': /* frame pointer */ | |
1800 | if (*s++ == 'p') | |
1801 | { | |
1802 | mask = 0x1e; | |
1803 | break; | |
1804 | } | |
1805 | goto error; | |
1806 | ||
1807 | case 'g': /* global register */ | |
a22b281c RH |
1808 | c = *s++; |
1809 | if (isoctal (c)) | |
252b5132 RH |
1810 | { |
1811 | mask = c - '0'; | |
1812 | break; | |
1813 | } | |
1814 | goto error; | |
1815 | ||
1816 | case 'i': /* in register */ | |
a22b281c RH |
1817 | c = *s++; |
1818 | if (isoctal (c)) | |
252b5132 RH |
1819 | { |
1820 | mask = c - '0' + 24; | |
1821 | break; | |
1822 | } | |
1823 | goto error; | |
1824 | ||
1825 | case 'l': /* local register */ | |
a22b281c RH |
1826 | c = *s++; |
1827 | if (isoctal (c)) | |
252b5132 RH |
1828 | { |
1829 | mask = (c - '0' + 16); | |
1830 | break; | |
1831 | } | |
1832 | goto error; | |
1833 | ||
1834 | case 'o': /* out register */ | |
a22b281c RH |
1835 | c = *s++; |
1836 | if (isoctal (c)) | |
252b5132 RH |
1837 | { |
1838 | mask = (c - '0' + 8); | |
1839 | break; | |
1840 | } | |
1841 | goto error; | |
1842 | ||
1843 | case 's': /* stack pointer */ | |
1844 | if (*s++ == 'p') | |
1845 | { | |
1846 | mask = 0xe; | |
1847 | break; | |
1848 | } | |
1849 | goto error; | |
1850 | ||
1851 | case 'r': /* any register */ | |
1852 | if (!isdigit ((unsigned char) (c = *s++))) | |
1853 | { | |
1854 | goto error; | |
1855 | } | |
1856 | /* FALLTHROUGH */ | |
1857 | case '0': | |
1858 | case '1': | |
1859 | case '2': | |
1860 | case '3': | |
1861 | case '4': | |
1862 | case '5': | |
1863 | case '6': | |
1864 | case '7': | |
1865 | case '8': | |
1866 | case '9': | |
1867 | if (isdigit ((unsigned char) *s)) | |
1868 | { | |
1869 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) | |
1870 | { | |
1871 | goto error; | |
1872 | } | |
1873 | } | |
1874 | else | |
1875 | { | |
1876 | c -= '0'; | |
1877 | } | |
1878 | mask = c; | |
1879 | break; | |
1880 | ||
1881 | default: | |
1882 | goto error; | |
1883 | } | |
1884 | ||
6d8809aa RH |
1885 | if ((mask & ~1) == 2 && sparc_arch_size == 64 |
1886 | && no_undeclared_regs && ! globals [mask]) | |
1887 | as_bad (_("detected global register use not " | |
1888 | "covered by .register pseudo-op")); | |
1889 | ||
252b5132 RH |
1890 | /* Got the register, now figure out where |
1891 | it goes in the opcode. */ | |
1892 | switch (*args) | |
1893 | { | |
1894 | case '1': | |
1895 | opcode |= mask << 14; | |
1896 | continue; | |
1897 | ||
1898 | case '2': | |
1899 | opcode |= mask; | |
1900 | continue; | |
1901 | ||
1902 | case 'd': | |
1903 | opcode |= mask << 25; | |
1904 | continue; | |
1905 | ||
1906 | case 'r': | |
1907 | opcode |= (mask << 25) | (mask << 14); | |
1908 | continue; | |
1909 | ||
1910 | case 'O': | |
1911 | opcode |= (mask << 25) | (mask << 0); | |
1912 | continue; | |
1913 | } | |
1914 | } | |
1915 | break; | |
1916 | ||
1917 | case 'e': /* next operand is a floating point register */ | |
1918 | case 'v': | |
1919 | case 'V': | |
1920 | ||
1921 | case 'f': | |
1922 | case 'B': | |
1923 | case 'R': | |
1924 | ||
1925 | case 'g': | |
1926 | case 'H': | |
1927 | case 'J': | |
1928 | { | |
1929 | char format; | |
1930 | ||
1931 | if (*s++ == '%' | |
1932 | && ((format = *s) == 'f') | |
1933 | && isdigit ((unsigned char) *++s)) | |
1934 | { | |
1935 | for (mask = 0; isdigit ((unsigned char) *s); ++s) | |
1936 | { | |
1937 | mask = 10 * mask + (*s - '0'); | |
1938 | } /* read the number */ | |
1939 | ||
1940 | if ((*args == 'v' | |
1941 | || *args == 'B' | |
1942 | || *args == 'H') | |
1943 | && (mask & 1)) | |
1944 | { | |
1945 | break; | |
1946 | } /* register must be even numbered */ | |
1947 | ||
1948 | if ((*args == 'V' | |
1949 | || *args == 'R' | |
1950 | || *args == 'J') | |
1951 | && (mask & 3)) | |
1952 | { | |
1953 | break; | |
1954 | } /* register must be multiple of 4 */ | |
1955 | ||
1956 | if (mask >= 64) | |
1957 | { | |
1958 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1959 | error_message = _(": There are only 64 f registers; [0-63]"); | |
1960 | else | |
1961 | error_message = _(": There are only 32 f registers; [0-31]"); | |
1962 | goto error; | |
1963 | } /* on error */ | |
1964 | else if (mask >= 32) | |
1965 | { | |
1966 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1967 | { | |
1968 | v9_arg_p = 1; | |
1969 | mask -= 31; /* wrap high bit */ | |
1970 | } | |
1971 | else | |
1972 | { | |
1973 | error_message = _(": There are only 32 f registers; [0-31]"); | |
1974 | goto error; | |
1975 | } | |
1976 | } | |
1977 | } | |
1978 | else | |
1979 | { | |
1980 | break; | |
1981 | } /* if not an 'f' register. */ | |
1982 | ||
1983 | switch (*args) | |
1984 | { | |
1985 | case 'v': | |
1986 | case 'V': | |
1987 | case 'e': | |
1988 | opcode |= RS1 (mask); | |
1989 | continue; | |
1990 | ||
1991 | ||
1992 | case 'f': | |
1993 | case 'B': | |
1994 | case 'R': | |
1995 | opcode |= RS2 (mask); | |
1996 | continue; | |
1997 | ||
1998 | case 'g': | |
1999 | case 'H': | |
2000 | case 'J': | |
2001 | opcode |= RD (mask); | |
2002 | continue; | |
2003 | } /* pack it in. */ | |
2004 | ||
2005 | know (0); | |
2006 | break; | |
2007 | } /* float arg */ | |
2008 | ||
2009 | case 'F': | |
2010 | if (strncmp (s, "%fsr", 4) == 0) | |
2011 | { | |
2012 | s += 4; | |
2013 | continue; | |
2014 | } | |
2015 | break; | |
2016 | ||
63fab58c | 2017 | case '0': /* 64 bit immediate (set, setsw, setx insn) */ |
252b5132 RH |
2018 | the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ |
2019 | goto immediate; | |
2020 | ||
252b5132 RH |
2021 | case 'l': /* 22 bit PC relative immediate */ |
2022 | the_insn.reloc = BFD_RELOC_SPARC_WDISP22; | |
2023 | the_insn.pcrel = 1; | |
2024 | goto immediate; | |
2025 | ||
2026 | case 'L': /* 30 bit immediate */ | |
2027 | the_insn.reloc = BFD_RELOC_32_PCREL_S2; | |
2028 | the_insn.pcrel = 1; | |
2029 | goto immediate; | |
2030 | ||
63fab58c | 2031 | case 'h': |
252b5132 RH |
2032 | case 'n': /* 22 bit immediate */ |
2033 | the_insn.reloc = BFD_RELOC_SPARC22; | |
2034 | goto immediate; | |
2035 | ||
2036 | case 'i': /* 13 bit immediate */ | |
2037 | the_insn.reloc = BFD_RELOC_SPARC13; | |
2038 | ||
2039 | /* fallthrough */ | |
2040 | ||
2041 | immediate: | |
2042 | if (*s == ' ') | |
2043 | s++; | |
2044 | ||
cf9a1301 RH |
2045 | { |
2046 | char *s1; | |
2047 | char *op_arg = NULL; | |
2048 | expressionS op_exp; | |
2049 | bfd_reloc_code_real_type old_reloc = the_insn.reloc; | |
2050 | ||
2051 | /* Check for %hi, etc. */ | |
2052 | if (*s == '%') | |
2053 | { | |
2054 | static const struct ops { | |
2055 | /* The name as it appears in assembler. */ | |
2056 | char *name; | |
2057 | /* strlen (name), precomputed for speed */ | |
2058 | int len; | |
2059 | /* The reloc this pseudo-op translates to. */ | |
2060 | int reloc; | |
2061 | /* Non-zero if for v9 only. */ | |
2062 | int v9_p; | |
2063 | /* Non-zero if can be used in pc-relative contexts. */ | |
2064 | int pcrel_p;/*FIXME:wip*/ | |
2065 | } ops[] = { | |
2066 | /* hix/lox must appear before hi/lo so %hix won't be | |
2067 | mistaken for %hi. */ | |
2068 | { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, | |
2069 | { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, | |
2070 | { "hi", 2, BFD_RELOC_HI22, 0, 1 }, | |
2071 | { "lo", 2, BFD_RELOC_LO10, 0, 1 }, | |
2072 | { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, | |
2073 | { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, | |
2074 | { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, | |
2075 | { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, | |
2076 | { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, | |
2077 | { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, | |
2078 | { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, | |
2079 | { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, | |
2080 | { NULL } | |
2081 | }; | |
2082 | const struct ops *o; | |
2083 | ||
2084 | for (o = ops; o->name; o++) | |
2085 | if (strncmp (s + 1, o->name, o->len) == 0) | |
2086 | break; | |
2087 | if (o->name == NULL) | |
252b5132 | 2088 | break; |
cf9a1301 RH |
2089 | |
2090 | if (s[o->len + 1] != '(') | |
2091 | { | |
2092 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
a22b281c | 2093 | return special_case; |
cf9a1301 | 2094 | } |
252b5132 | 2095 | |
cf9a1301 RH |
2096 | op_arg = o->name; |
2097 | the_insn.reloc = o->reloc; | |
2098 | s += o->len + 2; | |
2099 | v9_arg_p = o->v9_p; | |
2100 | } | |
2101 | ||
2102 | /* Note that if the get_expression() fails, we will still | |
2103 | have created U entries in the symbol table for the | |
2104 | 'symbols' in the input string. Try not to create U | |
2105 | symbols for registers, etc. */ | |
252b5132 | 2106 | |
252b5132 RH |
2107 | /* This stuff checks to see if the expression ends in |
2108 | +%reg. If it does, it removes the register from | |
2109 | the expression, and re-sets 's' to point to the | |
2110 | right place. */ | |
2111 | ||
cf9a1301 RH |
2112 | if (op_arg) |
2113 | { | |
2114 | int npar = 0; | |
2115 | ||
2116 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2117 | if (*s1 == '(') | |
2118 | npar++; | |
2119 | else if (*s1 == ')') | |
2120 | { | |
2121 | if (!npar) | |
2122 | break; | |
2123 | npar--; | |
2124 | } | |
2125 | ||
2126 | if (*s1 != ')') | |
2127 | { | |
2128 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); | |
a22b281c | 2129 | return special_case; |
cf9a1301 RH |
2130 | } |
2131 | ||
2132 | *s1 = '\0'; | |
2133 | (void) get_expression (s); | |
2134 | *s1 = ')'; | |
2135 | s = s1 + 1; | |
2136 | if (*s == ',' || *s == ']' || !*s) | |
2137 | continue; | |
2138 | if (*s != '+' && *s != '-') | |
2139 | { | |
2140 | as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); | |
a22b281c | 2141 | return special_case; |
cf9a1301 RH |
2142 | } |
2143 | *s1 = '0'; | |
2144 | s = s1; | |
2145 | op_exp = the_insn.exp; | |
2146 | memset (&the_insn.exp, 0, sizeof(the_insn.exp)); | |
2147 | } | |
252b5132 RH |
2148 | |
2149 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ; | |
2150 | ||
2151 | if (s1 != s && isdigit ((unsigned char) s1[-1])) | |
2152 | { | |
2153 | if (s1[-2] == '%' && s1[-3] == '+') | |
cf9a1301 RH |
2154 | s1 -= 3; |
2155 | else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') | |
2156 | s1 -= 4; | |
2157 | else | |
2158 | s1 = NULL; | |
2159 | if (s1) | |
252b5132 | 2160 | { |
252b5132 | 2161 | *s1 = '\0'; |
1eb7027c RH |
2162 | if (op_arg && s1 == s + 1) |
2163 | the_insn.exp.X_op = O_absent; | |
2164 | else | |
2165 | (void) get_expression (s); | |
252b5132 | 2166 | *s1 = '+'; |
cf9a1301 RH |
2167 | if (op_arg) |
2168 | *s = ')'; | |
252b5132 | 2169 | s = s1; |
252b5132 | 2170 | } |
cf9a1301 RH |
2171 | } |
2172 | else | |
2173 | s1 = NULL; | |
2174 | ||
2175 | if (!s1) | |
2176 | { | |
2177 | (void) get_expression (s); | |
2178 | if (op_arg) | |
2179 | *s = ')'; | |
2180 | s = expr_end; | |
2181 | } | |
2182 | ||
2183 | if (op_arg) | |
2184 | { | |
2185 | the_insn.exp2 = the_insn.exp; | |
2186 | the_insn.exp = op_exp; | |
2187 | if (the_insn.exp2.X_op == O_absent) | |
2188 | the_insn.exp2.X_op = O_illegal; | |
2189 | else if (the_insn.exp.X_op == O_absent) | |
252b5132 | 2190 | { |
cf9a1301 RH |
2191 | the_insn.exp = the_insn.exp2; |
2192 | the_insn.exp2.X_op = O_illegal; | |
2193 | } | |
2194 | else if (the_insn.exp.X_op == O_constant) | |
2195 | { | |
2196 | valueT val = the_insn.exp.X_add_number; | |
2197 | switch (the_insn.reloc) | |
2198 | { | |
1b50c718 ILT |
2199 | default: |
2200 | break; | |
2201 | ||
cf9a1301 RH |
2202 | case BFD_RELOC_SPARC_HH22: |
2203 | val = BSR (val, 32); | |
2204 | /* intentional fallthrough */ | |
2205 | ||
2206 | case BFD_RELOC_SPARC_LM22: | |
2207 | case BFD_RELOC_HI22: | |
2208 | val = (val >> 10) & 0x3fffff; | |
2209 | break; | |
2210 | ||
2211 | case BFD_RELOC_SPARC_HM10: | |
2212 | val = BSR (val, 32); | |
2213 | /* intentional fallthrough */ | |
2214 | ||
2215 | case BFD_RELOC_LO10: | |
2216 | val &= 0x3ff; | |
2217 | break; | |
2218 | ||
2219 | case BFD_RELOC_SPARC_H44: | |
2220 | val >>= 22; | |
2221 | val &= 0x3fffff; | |
2222 | break; | |
2223 | ||
2224 | case BFD_RELOC_SPARC_M44: | |
2225 | val >>= 12; | |
2226 | val &= 0x3ff; | |
2227 | break; | |
2228 | ||
2229 | case BFD_RELOC_SPARC_L44: | |
2230 | val &= 0xfff; | |
2231 | break; | |
2232 | ||
2233 | case BFD_RELOC_SPARC_HIX22: | |
2234 | val = ~ val; | |
2235 | val = (val >> 10) & 0x3fffff; | |
2236 | break; | |
2237 | ||
2238 | case BFD_RELOC_SPARC_LOX10: | |
2239 | val = (val & 0x3ff) | 0x1c00; | |
2240 | break; | |
2241 | } | |
2242 | the_insn.exp = the_insn.exp2; | |
2243 | the_insn.exp.X_add_number += val; | |
2244 | the_insn.exp2.X_op = O_illegal; | |
2245 | the_insn.reloc = old_reloc; | |
2246 | } | |
2247 | else if (the_insn.exp2.X_op != O_constant) | |
2248 | { | |
2249 | as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); | |
a22b281c | 2250 | return special_case; |
cf9a1301 RH |
2251 | } |
2252 | else | |
2253 | { | |
dabe3bbc | 2254 | if (old_reloc != BFD_RELOC_SPARC13 |
cf9a1301 RH |
2255 | || the_insn.reloc != BFD_RELOC_LO10 |
2256 | || sparc_arch_size != 64 | |
2257 | || sparc_pic_code) | |
2258 | { | |
2259 | as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); | |
a22b281c | 2260 | return special_case; |
cf9a1301 RH |
2261 | } |
2262 | the_insn.reloc = BFD_RELOC_SPARC_OLO10; | |
252b5132 RH |
2263 | } |
2264 | } | |
2265 | } | |
252b5132 RH |
2266 | /* Check for constants that don't require emitting a reloc. */ |
2267 | if (the_insn.exp.X_op == O_constant | |
2268 | && the_insn.exp.X_add_symbol == 0 | |
2269 | && the_insn.exp.X_op_symbol == 0) | |
2270 | { | |
2271 | /* For pc-relative call instructions, we reject | |
2272 | constants to get better code. */ | |
2273 | if (the_insn.pcrel | |
2274 | && the_insn.reloc == BFD_RELOC_32_PCREL_S2 | |
2275 | && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) | |
2276 | { | |
2277 | error_message = _(": PC-relative operand can't be a constant"); | |
2278 | goto error; | |
2279 | } | |
2280 | ||
2281 | /* Constants that won't fit are checked in md_apply_fix3 | |
2282 | and bfd_install_relocation. | |
2283 | ??? It would be preferable to install the constants | |
2284 | into the insn here and save having to create a fixS | |
2285 | for each one. There already exists code to handle | |
2286 | all the various cases (e.g. in md_apply_fix3 and | |
2287 | bfd_install_relocation) so duplicating all that code | |
2288 | here isn't right. */ | |
2289 | } | |
2290 | ||
2291 | continue; | |
2292 | ||
2293 | case 'a': | |
2294 | if (*s++ == 'a') | |
2295 | { | |
2296 | opcode |= ANNUL; | |
2297 | continue; | |
2298 | } | |
2299 | break; | |
2300 | ||
2301 | case 'A': | |
2302 | { | |
2303 | int asi = 0; | |
2304 | ||
2305 | /* Parse an asi. */ | |
2306 | if (*s == '#') | |
2307 | { | |
2308 | if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) | |
2309 | { | |
2310 | error_message = _(": invalid ASI name"); | |
2311 | goto error; | |
2312 | } | |
2313 | } | |
2314 | else | |
2315 | { | |
2316 | if (! parse_const_expr_arg (&s, &asi)) | |
2317 | { | |
2318 | error_message = _(": invalid ASI expression"); | |
2319 | goto error; | |
2320 | } | |
2321 | if (asi < 0 || asi > 255) | |
2322 | { | |
2323 | error_message = _(": invalid ASI number"); | |
2324 | goto error; | |
2325 | } | |
2326 | } | |
2327 | opcode |= ASI (asi); | |
2328 | continue; | |
2329 | } /* alternate space */ | |
2330 | ||
2331 | case 'p': | |
2332 | if (strncmp (s, "%psr", 4) == 0) | |
2333 | { | |
2334 | s += 4; | |
2335 | continue; | |
2336 | } | |
2337 | break; | |
2338 | ||
2339 | case 'q': /* floating point queue */ | |
2340 | if (strncmp (s, "%fq", 3) == 0) | |
2341 | { | |
2342 | s += 3; | |
2343 | continue; | |
2344 | } | |
2345 | break; | |
2346 | ||
2347 | case 'Q': /* coprocessor queue */ | |
2348 | if (strncmp (s, "%cq", 3) == 0) | |
2349 | { | |
2350 | s += 3; | |
2351 | continue; | |
2352 | } | |
2353 | break; | |
2354 | ||
2355 | case 'S': | |
2356 | if (strcmp (str, "set") == 0 | |
2357 | || strcmp (str, "setuw") == 0) | |
2358 | { | |
2359 | special_case = SPECIAL_CASE_SET; | |
2360 | continue; | |
2361 | } | |
2362 | else if (strcmp (str, "setsw") == 0) | |
2363 | { | |
2364 | special_case = SPECIAL_CASE_SETSW; | |
2365 | continue; | |
2366 | } | |
2367 | else if (strcmp (str, "setx") == 0) | |
2368 | { | |
2369 | special_case = SPECIAL_CASE_SETX; | |
2370 | continue; | |
2371 | } | |
2372 | else if (strncmp (str, "fdiv", 4) == 0) | |
2373 | { | |
2374 | special_case = SPECIAL_CASE_FDIV; | |
2375 | continue; | |
2376 | } | |
2377 | break; | |
2378 | ||
2379 | case 'o': | |
2380 | if (strncmp (s, "%asi", 4) != 0) | |
2381 | break; | |
2382 | s += 4; | |
2383 | continue; | |
2384 | ||
2385 | case 's': | |
2386 | if (strncmp (s, "%fprs", 5) != 0) | |
2387 | break; | |
2388 | s += 5; | |
2389 | continue; | |
2390 | ||
2391 | case 'E': | |
2392 | if (strncmp (s, "%ccr", 4) != 0) | |
2393 | break; | |
2394 | s += 4; | |
2395 | continue; | |
2396 | ||
2397 | case 't': | |
2398 | if (strncmp (s, "%tbr", 4) != 0) | |
2399 | break; | |
2400 | s += 4; | |
2401 | continue; | |
2402 | ||
2403 | case 'w': | |
2404 | if (strncmp (s, "%wim", 4) != 0) | |
2405 | break; | |
2406 | s += 4; | |
2407 | continue; | |
2408 | ||
2409 | case 'x': | |
2410 | { | |
2411 | char *push = input_line_pointer; | |
2412 | expressionS e; | |
2413 | ||
2414 | input_line_pointer = s; | |
2415 | expression (&e); | |
2416 | if (e.X_op == O_constant) | |
2417 | { | |
2418 | int n = e.X_add_number; | |
2419 | if (n != e.X_add_number || (n & ~0x1ff) != 0) | |
2420 | as_bad (_("OPF immediate operand out of range (0-0x1ff)")); | |
2421 | else | |
2422 | opcode |= e.X_add_number << 5; | |
2423 | } | |
2424 | else | |
2425 | as_bad (_("non-immediate OPF operand, ignored")); | |
2426 | s = input_line_pointer; | |
2427 | input_line_pointer = push; | |
2428 | continue; | |
2429 | } | |
2430 | ||
2431 | case 'y': | |
2432 | if (strncmp (s, "%y", 2) != 0) | |
2433 | break; | |
2434 | s += 2; | |
2435 | continue; | |
2436 | ||
2437 | case 'u': | |
2438 | case 'U': | |
2439 | { | |
2440 | /* Parse a sparclet cpreg. */ | |
2441 | int cpreg; | |
2442 | if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) | |
2443 | { | |
2444 | error_message = _(": invalid cpreg name"); | |
2445 | goto error; | |
2446 | } | |
2447 | opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); | |
2448 | continue; | |
2449 | } | |
2450 | ||
2451 | default: | |
2452 | as_fatal (_("failed sanity check.")); | |
2453 | } /* switch on arg code */ | |
2454 | ||
2455 | /* Break out of for() loop. */ | |
2456 | break; | |
2457 | } /* for each arg that we expect */ | |
2458 | ||
2459 | error: | |
2460 | if (match == 0) | |
2461 | { | |
2462 | /* Args don't match. */ | |
2463 | if (&insn[1] - sparc_opcodes < sparc_num_opcodes | |
2464 | && (insn->name == insn[1].name | |
2465 | || !strcmp (insn->name, insn[1].name))) | |
2466 | { | |
2467 | ++insn; | |
2468 | s = argsStart; | |
2469 | continue; | |
2470 | } | |
2471 | else | |
2472 | { | |
2473 | as_bad (_("Illegal operands%s"), error_message); | |
a22b281c | 2474 | return special_case; |
252b5132 RH |
2475 | } |
2476 | } | |
2477 | else | |
2478 | { | |
2479 | /* We have a match. Now see if the architecture is ok. */ | |
2480 | int needed_arch_mask = insn->architecture; | |
2481 | ||
2482 | if (v9_arg_p) | |
2483 | { | |
2484 | needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9) | |
2485 | | (1 << SPARC_OPCODE_ARCH_V9A)); | |
2486 | needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9); | |
2487 | } | |
2488 | ||
2489 | if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture)) | |
2490 | ; /* ok */ | |
2491 | /* Can we bump up the architecture? */ | |
2492 | else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture)) | |
2493 | { | |
2494 | enum sparc_opcode_arch_val needed_architecture = | |
2495 | sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) | |
2496 | & needed_arch_mask); | |
2497 | ||
2498 | assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); | |
2499 | if (warn_on_bump | |
2500 | && needed_architecture > warn_after_architecture) | |
2501 | { | |
2502 | as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), | |
2503 | sparc_opcode_archs[current_architecture].name, | |
2504 | sparc_opcode_archs[needed_architecture].name, | |
2505 | str); | |
2506 | warn_after_architecture = needed_architecture; | |
2507 | } | |
2508 | current_architecture = needed_architecture; | |
2509 | } | |
2510 | /* Conflict. */ | |
2511 | /* ??? This seems to be a bit fragile. What if the next entry in | |
2512 | the opcode table is the one we want and it is supported? | |
2513 | It is possible to arrange the table today so that this can't | |
2514 | happen but what about tomorrow? */ | |
2515 | else | |
2516 | { | |
2517 | int arch,printed_one_p = 0; | |
2518 | char *p; | |
2519 | char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; | |
2520 | ||
2521 | /* Create a list of the architectures that support the insn. */ | |
2522 | needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture); | |
2523 | p = required_archs; | |
2524 | arch = sparc_ffs (needed_arch_mask); | |
2525 | while ((1 << arch) <= needed_arch_mask) | |
2526 | { | |
2527 | if ((1 << arch) & needed_arch_mask) | |
2528 | { | |
2529 | if (printed_one_p) | |
2530 | *p++ = '|'; | |
2531 | strcpy (p, sparc_opcode_archs[arch].name); | |
2532 | p += strlen (p); | |
2533 | printed_one_p = 1; | |
2534 | } | |
2535 | ++arch; | |
2536 | } | |
2537 | ||
2538 | as_bad (_("Architecture mismatch on \"%s\"."), str); | |
2539 | as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), | |
2540 | required_archs, | |
2541 | sparc_opcode_archs[max_architecture].name); | |
a22b281c | 2542 | return special_case; |
252b5132 RH |
2543 | } |
2544 | } /* if no match */ | |
2545 | ||
2546 | break; | |
2547 | } /* forever looking for a match */ | |
2548 | ||
2549 | the_insn.opcode = opcode; | |
a22b281c | 2550 | return special_case; |
252b5132 RH |
2551 | } |
2552 | ||
2553 | /* Parse an argument that can be expressed as a keyword. | |
2554 | (eg: #StoreStore or %ccfr). | |
2555 | The result is a boolean indicating success. | |
2556 | If successful, INPUT_POINTER is updated. */ | |
2557 | ||
2558 | static int | |
2559 | parse_keyword_arg (lookup_fn, input_pointerP, valueP) | |
2560 | int (*lookup_fn) PARAMS ((const char *)); | |
2561 | char **input_pointerP; | |
2562 | int *valueP; | |
2563 | { | |
2564 | int value; | |
2565 | char c, *p, *q; | |
2566 | ||
2567 | p = *input_pointerP; | |
2568 | for (q = p + (*p == '#' || *p == '%'); | |
2569 | isalnum ((unsigned char) *q) || *q == '_'; | |
2570 | ++q) | |
2571 | continue; | |
2572 | c = *q; | |
2573 | *q = 0; | |
2574 | value = (*lookup_fn) (p); | |
2575 | *q = c; | |
2576 | if (value == -1) | |
2577 | return 0; | |
2578 | *valueP = value; | |
2579 | *input_pointerP = q; | |
2580 | return 1; | |
2581 | } | |
2582 | ||
2583 | /* Parse an argument that is a constant expression. | |
2584 | The result is a boolean indicating success. */ | |
2585 | ||
2586 | static int | |
2587 | parse_const_expr_arg (input_pointerP, valueP) | |
2588 | char **input_pointerP; | |
2589 | int *valueP; | |
2590 | { | |
2591 | char *save = input_line_pointer; | |
2592 | expressionS exp; | |
2593 | ||
2594 | input_line_pointer = *input_pointerP; | |
2595 | /* The next expression may be something other than a constant | |
2596 | (say if we're not processing the right variant of the insn). | |
2597 | Don't call expression unless we're sure it will succeed as it will | |
2598 | signal an error (which we want to defer until later). */ | |
2599 | /* FIXME: It might be better to define md_operand and have it recognize | |
2600 | things like %asi, etc. but continuing that route through to the end | |
2601 | is a lot of work. */ | |
2602 | if (*input_line_pointer == '%') | |
2603 | { | |
2604 | input_line_pointer = save; | |
2605 | return 0; | |
2606 | } | |
2607 | expression (&exp); | |
2608 | *input_pointerP = input_line_pointer; | |
2609 | input_line_pointer = save; | |
2610 | if (exp.X_op != O_constant) | |
2611 | return 0; | |
2612 | *valueP = exp.X_add_number; | |
2613 | return 1; | |
2614 | } | |
2615 | ||
2616 | /* Subroutine of sparc_ip to parse an expression. */ | |
2617 | ||
2618 | static int | |
2619 | get_expression (str) | |
2620 | char *str; | |
2621 | { | |
2622 | char *save_in; | |
2623 | segT seg; | |
2624 | ||
2625 | save_in = input_line_pointer; | |
2626 | input_line_pointer = str; | |
2627 | seg = expression (&the_insn.exp); | |
2628 | if (seg != absolute_section | |
2629 | && seg != text_section | |
2630 | && seg != data_section | |
2631 | && seg != bss_section | |
2632 | && seg != undefined_section) | |
2633 | { | |
2634 | the_insn.error = _("bad segment"); | |
2635 | expr_end = input_line_pointer; | |
2636 | input_line_pointer = save_in; | |
2637 | return 1; | |
2638 | } | |
2639 | expr_end = input_line_pointer; | |
2640 | input_line_pointer = save_in; | |
2641 | return 0; | |
2642 | } | |
2643 | ||
2644 | /* Subroutine of md_assemble to output one insn. */ | |
2645 | ||
2646 | static void | |
2647 | output_insn (insn, the_insn) | |
2648 | const struct sparc_opcode *insn; | |
2649 | struct sparc_it *the_insn; | |
2650 | { | |
2651 | char *toP = frag_more (4); | |
2652 | ||
2653 | /* put out the opcode */ | |
2654 | if (INSN_BIG_ENDIAN) | |
2655 | number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4); | |
2656 | else | |
2657 | number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4); | |
2658 | ||
2659 | /* put out the symbol-dependent stuff */ | |
2660 | if (the_insn->reloc != BFD_RELOC_NONE) | |
2661 | { | |
2662 | fixS *fixP = fix_new_exp (frag_now, /* which frag */ | |
2663 | (toP - frag_now->fr_literal), /* where */ | |
2664 | 4, /* size */ | |
2665 | &the_insn->exp, | |
2666 | the_insn->pcrel, | |
2667 | the_insn->reloc); | |
2668 | /* Turn off overflow checking in fixup_segment. We'll do our | |
2669 | own overflow checking in md_apply_fix3. This is necessary because | |
2670 | the insn size is 4 and fixup_segment will signal an overflow for | |
2671 | large 8 byte quantities. */ | |
2672 | fixP->fx_no_overflow = 1; | |
dabe3bbc RH |
2673 | if (the_insn->reloc == BFD_RELOC_SPARC_OLO10) |
2674 | fixP->tc_fix_data = the_insn->exp2.X_add_number; | |
252b5132 RH |
2675 | } |
2676 | ||
2677 | last_insn = insn; | |
2678 | last_opcode = the_insn->opcode; | |
2679 | } | |
2680 | \f | |
2681 | /* | |
2682 | This is identical to the md_atof in m68k.c. I think this is right, | |
2683 | but I'm not sure. | |
2684 | ||
2685 | Turn a string in input_line_pointer into a floating point constant of type | |
2686 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
2687 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
2688 | */ | |
2689 | ||
2690 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
2691 | #define MAX_LITTLENUMS 6 | |
2692 | ||
2693 | char * | |
2694 | md_atof (type, litP, sizeP) | |
2695 | char type; | |
2696 | char *litP; | |
2697 | int *sizeP; | |
2698 | { | |
2699 | int i,prec; | |
2700 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2701 | char *t; | |
2702 | ||
2703 | switch (type) | |
2704 | { | |
2705 | case 'f': | |
2706 | case 'F': | |
2707 | case 's': | |
2708 | case 'S': | |
2709 | prec = 2; | |
2710 | break; | |
2711 | ||
2712 | case 'd': | |
2713 | case 'D': | |
2714 | case 'r': | |
2715 | case 'R': | |
2716 | prec = 4; | |
2717 | break; | |
2718 | ||
2719 | case 'x': | |
2720 | case 'X': | |
2721 | prec = 6; | |
2722 | break; | |
2723 | ||
2724 | case 'p': | |
2725 | case 'P': | |
2726 | prec = 6; | |
2727 | break; | |
2728 | ||
2729 | default: | |
2730 | *sizeP = 0; | |
2731 | return _("Bad call to MD_ATOF()"); | |
2732 | } | |
2733 | ||
2734 | t = atof_ieee (input_line_pointer, type, words); | |
2735 | if (t) | |
2736 | input_line_pointer = t; | |
2737 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
2738 | ||
2739 | if (target_big_endian) | |
2740 | { | |
2741 | for (i = 0; i < prec; i++) | |
2742 | { | |
2743 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
2744 | litP += sizeof (LITTLENUM_TYPE); | |
2745 | } | |
2746 | } | |
2747 | else | |
2748 | { | |
2749 | for (i = prec - 1; i >= 0; i--) | |
2750 | { | |
2751 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
2752 | litP += sizeof (LITTLENUM_TYPE); | |
2753 | } | |
2754 | } | |
2755 | ||
2756 | return 0; | |
2757 | } | |
2758 | ||
2759 | /* Write a value out to the object file, using the appropriate | |
2760 | endianness. */ | |
2761 | ||
2762 | void | |
2763 | md_number_to_chars (buf, val, n) | |
2764 | char *buf; | |
2765 | valueT val; | |
2766 | int n; | |
2767 | { | |
2768 | if (target_big_endian) | |
2769 | number_to_chars_bigendian (buf, val, n); | |
2770 | else if (target_little_endian_data | |
2771 | && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) | |
2772 | /* Output debug words, which are not in allocated sections, as big endian */ | |
2773 | number_to_chars_bigendian (buf, val, n); | |
2774 | else if (target_little_endian_data || ! target_big_endian) | |
2775 | number_to_chars_littleendian (buf, val, n); | |
2776 | } | |
2777 | \f | |
2778 | /* Apply a fixS to the frags, now that we know the value it ought to | |
2779 | hold. */ | |
2780 | ||
2781 | int | |
2782 | md_apply_fix3 (fixP, value, segment) | |
2783 | fixS *fixP; | |
2784 | valueT *value; | |
2785 | segT segment; | |
2786 | { | |
2787 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
2788 | offsetT val; | |
2789 | long insn; | |
2790 | ||
2791 | val = *value; | |
2792 | ||
2793 | assert (fixP->fx_r_type < BFD_RELOC_UNUSED); | |
2794 | ||
2795 | fixP->fx_addnumber = val; /* Remember value for emit_reloc */ | |
2796 | ||
2797 | #ifdef OBJ_ELF | |
2798 | /* FIXME: SPARC ELF relocations don't use an addend in the data | |
2799 | field itself. This whole approach should be somehow combined | |
2800 | with the calls to bfd_install_relocation. Also, the value passed | |
2801 | in by fixup_segment includes the value of a defined symbol. We | |
2802 | don't want to include the value of an externally visible symbol. */ | |
2803 | if (fixP->fx_addsy != NULL) | |
2804 | { | |
49309057 | 2805 | if (symbol_used_in_reloc_p (fixP->fx_addsy) |
252b5132 RH |
2806 | && (S_IS_EXTERNAL (fixP->fx_addsy) |
2807 | || S_IS_WEAK (fixP->fx_addsy) | |
2808 | || (sparc_pic_code && ! fixP->fx_pcrel) | |
2809 | || (S_GET_SEGMENT (fixP->fx_addsy) != segment | |
2810 | && ((bfd_get_section_flags (stdoutput, | |
2811 | S_GET_SEGMENT (fixP->fx_addsy)) | |
2812 | & SEC_LINK_ONCE) != 0 | |
2813 | || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
2814 | ".gnu.linkonce", | |
2815 | sizeof ".gnu.linkonce" - 1) == 0))) | |
2816 | && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section | |
2817 | && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section | |
2818 | && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy))) | |
2819 | fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy); | |
2820 | return 1; | |
2821 | } | |
2822 | #endif | |
2823 | ||
2824 | /* This is a hack. There should be a better way to | |
2825 | handle this. Probably in terms of howto fields, once | |
2826 | we can look at these fixups in terms of howtos. */ | |
2827 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) | |
2828 | val += fixP->fx_where + fixP->fx_frag->fr_address; | |
2829 | ||
2830 | #ifdef OBJ_AOUT | |
2831 | /* FIXME: More ridiculous gas reloc hacking. If we are going to | |
2832 | generate a reloc, then we just want to let the reloc addend set | |
2833 | the value. We do not want to also stuff the addend into the | |
2834 | object file. Including the addend in the object file works when | |
2835 | doing a static link, because the linker will ignore the object | |
2836 | file contents. However, the dynamic linker does not ignore the | |
2837 | object file contents. */ | |
2838 | if (fixP->fx_addsy != NULL | |
2839 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) | |
2840 | val = 0; | |
2841 | ||
2842 | /* When generating PIC code, we do not want an addend for a reloc | |
2843 | against a local symbol. We adjust fx_addnumber to cancel out the | |
2844 | value already included in val, and to also cancel out the | |
2845 | adjustment which bfd_install_relocation will create. */ | |
2846 | if (sparc_pic_code | |
2847 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 | |
2848 | && fixP->fx_addsy != NULL | |
2849 | && ! S_IS_COMMON (fixP->fx_addsy) | |
49309057 | 2850 | && symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
2851 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); |
2852 | ||
2853 | /* When generating PIC code, we need to fiddle to get | |
2854 | bfd_install_relocation to do the right thing for a PC relative | |
2855 | reloc against a local symbol which we are going to keep. */ | |
2856 | if (sparc_pic_code | |
2857 | && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
2858 | && fixP->fx_addsy != NULL | |
2859 | && (S_IS_EXTERNAL (fixP->fx_addsy) | |
2860 | || S_IS_WEAK (fixP->fx_addsy)) | |
2861 | && S_IS_DEFINED (fixP->fx_addsy) | |
2862 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
2863 | { | |
2864 | val = 0; | |
2865 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
2866 | } | |
2867 | #endif | |
2868 | ||
2869 | /* If this is a data relocation, just output VAL. */ | |
2870 | ||
2871 | if (fixP->fx_r_type == BFD_RELOC_16) | |
2872 | { | |
2873 | md_number_to_chars (buf, val, 2); | |
2874 | } | |
2875 | else if (fixP->fx_r_type == BFD_RELOC_32 | |
2876 | || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) | |
2877 | { | |
2878 | md_number_to_chars (buf, val, 4); | |
2879 | } | |
2880 | else if (fixP->fx_r_type == BFD_RELOC_64) | |
2881 | { | |
2882 | md_number_to_chars (buf, val, 8); | |
2883 | } | |
2884 | else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
2885 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
2886 | { | |
2887 | fixP->fx_done = 0; | |
2888 | return 1; | |
2889 | } | |
2890 | else | |
2891 | { | |
2892 | /* It's a relocation against an instruction. */ | |
2893 | ||
2894 | if (INSN_BIG_ENDIAN) | |
2895 | insn = bfd_getb32 ((unsigned char *) buf); | |
2896 | else | |
2897 | insn = bfd_getl32 ((unsigned char *) buf); | |
2898 | ||
2899 | switch (fixP->fx_r_type) | |
2900 | { | |
2901 | case BFD_RELOC_32_PCREL_S2: | |
2902 | val = val >> 2; | |
2903 | /* FIXME: This increment-by-one deserves a comment of why it's | |
2904 | being done! */ | |
2905 | if (! sparc_pic_code | |
2906 | || fixP->fx_addsy == NULL | |
49309057 | 2907 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
2908 | ++val; |
2909 | insn |= val & 0x3fffffff; | |
2910 | break; | |
2911 | ||
2912 | case BFD_RELOC_SPARC_11: | |
2913 | if (! in_signed_range (val, 0x7ff)) | |
2914 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2915 | _("relocation overflow")); | |
2916 | insn |= val & 0x7ff; | |
2917 | break; | |
2918 | ||
2919 | case BFD_RELOC_SPARC_10: | |
2920 | if (! in_signed_range (val, 0x3ff)) | |
2921 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2922 | _("relocation overflow")); | |
2923 | insn |= val & 0x3ff; | |
2924 | break; | |
2925 | ||
2926 | case BFD_RELOC_SPARC_7: | |
2927 | if (! in_bitfield_range (val, 0x7f)) | |
2928 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2929 | _("relocation overflow")); | |
2930 | insn |= val & 0x7f; | |
2931 | break; | |
2932 | ||
2933 | case BFD_RELOC_SPARC_6: | |
2934 | if (! in_bitfield_range (val, 0x3f)) | |
2935 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2936 | _("relocation overflow")); | |
2937 | insn |= val & 0x3f; | |
2938 | break; | |
2939 | ||
2940 | case BFD_RELOC_SPARC_5: | |
2941 | if (! in_bitfield_range (val, 0x1f)) | |
2942 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2943 | _("relocation overflow")); | |
2944 | insn |= val & 0x1f; | |
2945 | break; | |
2946 | ||
2947 | case BFD_RELOC_SPARC_WDISP16: | |
2948 | /* FIXME: simplify */ | |
2949 | if (((val > 0) && (val & ~0x3fffc)) | |
2950 | || ((val < 0) && (~(val - 1) & ~0x3fffc))) | |
2951 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2952 | _("relocation overflow")); | |
2953 | /* FIXME: The +1 deserves a comment. */ | |
2954 | val = (val >> 2) + 1; | |
2955 | insn |= ((val & 0xc000) << 6) | (val & 0x3fff); | |
2956 | break; | |
2957 | ||
2958 | case BFD_RELOC_SPARC_WDISP19: | |
2959 | /* FIXME: simplify */ | |
2960 | if (((val > 0) && (val & ~0x1ffffc)) | |
2961 | || ((val < 0) && (~(val - 1) & ~0x1ffffc))) | |
2962 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2963 | _("relocation overflow")); | |
2964 | /* FIXME: The +1 deserves a comment. */ | |
2965 | val = (val >> 2) + 1; | |
2966 | insn |= val & 0x7ffff; | |
2967 | break; | |
2968 | ||
2969 | case BFD_RELOC_SPARC_HH22: | |
2970 | val = BSR (val, 32); | |
2971 | /* intentional fallthrough */ | |
2972 | ||
2973 | case BFD_RELOC_SPARC_LM22: | |
2974 | case BFD_RELOC_HI22: | |
2975 | if (!fixP->fx_addsy) | |
2976 | { | |
2977 | insn |= (val >> 10) & 0x3fffff; | |
2978 | } | |
2979 | else | |
2980 | { | |
2981 | /* FIXME: Need comment explaining why we do this. */ | |
2982 | insn &= ~0xffff; | |
2983 | } | |
2984 | break; | |
2985 | ||
2986 | case BFD_RELOC_SPARC22: | |
2987 | if (val & ~0x003fffff) | |
2988 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
2989 | _("relocation overflow")); | |
2990 | insn |= (val & 0x3fffff); | |
2991 | break; | |
2992 | ||
2993 | case BFD_RELOC_SPARC_HM10: | |
2994 | val = BSR (val, 32); | |
2995 | /* intentional fallthrough */ | |
2996 | ||
2997 | case BFD_RELOC_LO10: | |
2998 | if (!fixP->fx_addsy) | |
2999 | { | |
3000 | insn |= val & 0x3ff; | |
3001 | } | |
3002 | else | |
3003 | { | |
3004 | /* FIXME: Need comment explaining why we do this. */ | |
3005 | insn &= ~0xff; | |
3006 | } | |
3007 | break; | |
3008 | ||
dabe3bbc RH |
3009 | case BFD_RELOC_SPARC_OLO10: |
3010 | val &= 0x3ff; | |
3011 | val += fixP->tc_fix_data; | |
3012 | /* intentional fallthrough */ | |
3013 | ||
252b5132 RH |
3014 | case BFD_RELOC_SPARC13: |
3015 | if (! in_signed_range (val, 0x1fff)) | |
3016 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3017 | _("relocation overflow")); | |
3018 | insn |= val & 0x1fff; | |
3019 | break; | |
3020 | ||
3021 | case BFD_RELOC_SPARC_WDISP22: | |
3022 | val = (val >> 2) + 1; | |
3023 | /* FALLTHROUGH */ | |
3024 | case BFD_RELOC_SPARC_BASE22: | |
3025 | insn |= val & 0x3fffff; | |
3026 | break; | |
3027 | ||
3028 | case BFD_RELOC_SPARC_H44: | |
3029 | if (!fixP->fx_addsy) | |
3030 | { | |
3031 | bfd_vma tval = val; | |
3032 | tval >>= 22; | |
3033 | insn |= tval & 0x3fffff; | |
3034 | } | |
3035 | break; | |
3036 | ||
3037 | case BFD_RELOC_SPARC_M44: | |
3038 | if (!fixP->fx_addsy) | |
3039 | insn |= (val >> 12) & 0x3ff; | |
3040 | break; | |
3041 | ||
3042 | case BFD_RELOC_SPARC_L44: | |
3043 | if (!fixP->fx_addsy) | |
3044 | insn |= val & 0xfff; | |
3045 | break; | |
3046 | ||
3047 | case BFD_RELOC_SPARC_HIX22: | |
3048 | if (!fixP->fx_addsy) | |
3049 | { | |
3050 | val ^= ~ (offsetT) 0; | |
3051 | insn |= (val >> 10) & 0x3fffff; | |
3052 | } | |
3053 | break; | |
3054 | ||
3055 | case BFD_RELOC_SPARC_LOX10: | |
3056 | if (!fixP->fx_addsy) | |
3057 | insn |= 0x1c00 | (val & 0x3ff); | |
3058 | break; | |
3059 | ||
3060 | case BFD_RELOC_NONE: | |
3061 | default: | |
3062 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3063 | _("bad or unhandled relocation type: 0x%02x"), | |
3064 | fixP->fx_r_type); | |
3065 | break; | |
3066 | } | |
3067 | ||
3068 | if (INSN_BIG_ENDIAN) | |
3069 | bfd_putb32 (insn, (unsigned char *) buf); | |
3070 | else | |
3071 | bfd_putl32 (insn, (unsigned char *) buf); | |
3072 | } | |
3073 | ||
3074 | /* Are we finished with this relocation now? */ | |
3075 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
3076 | fixP->fx_done = 1; | |
3077 | ||
3078 | return 1; | |
3079 | } | |
3080 | ||
3081 | /* Translate internal representation of relocation info to BFD target | |
3082 | format. */ | |
dabe3bbc | 3083 | arelent ** |
252b5132 RH |
3084 | tc_gen_reloc (section, fixp) |
3085 | asection *section; | |
3086 | fixS *fixp; | |
3087 | { | |
dabe3bbc | 3088 | static arelent *relocs[3]; |
252b5132 RH |
3089 | arelent *reloc; |
3090 | bfd_reloc_code_real_type code; | |
3091 | ||
dabe3bbc RH |
3092 | relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); |
3093 | relocs[1] = NULL; | |
252b5132 | 3094 | |
49309057 ILT |
3095 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
3096 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
3097 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3098 | ||
3099 | switch (fixp->fx_r_type) | |
3100 | { | |
3101 | case BFD_RELOC_16: | |
3102 | case BFD_RELOC_32: | |
3103 | case BFD_RELOC_HI22: | |
3104 | case BFD_RELOC_LO10: | |
3105 | case BFD_RELOC_32_PCREL_S2: | |
3106 | case BFD_RELOC_SPARC13: | |
63fab58c | 3107 | case BFD_RELOC_SPARC22: |
252b5132 RH |
3108 | case BFD_RELOC_SPARC_BASE13: |
3109 | case BFD_RELOC_SPARC_WDISP16: | |
3110 | case BFD_RELOC_SPARC_WDISP19: | |
3111 | case BFD_RELOC_SPARC_WDISP22: | |
3112 | case BFD_RELOC_64: | |
3113 | case BFD_RELOC_SPARC_5: | |
3114 | case BFD_RELOC_SPARC_6: | |
3115 | case BFD_RELOC_SPARC_7: | |
3116 | case BFD_RELOC_SPARC_10: | |
3117 | case BFD_RELOC_SPARC_11: | |
3118 | case BFD_RELOC_SPARC_HH22: | |
3119 | case BFD_RELOC_SPARC_HM10: | |
3120 | case BFD_RELOC_SPARC_LM22: | |
3121 | case BFD_RELOC_SPARC_PC_HH22: | |
3122 | case BFD_RELOC_SPARC_PC_HM10: | |
3123 | case BFD_RELOC_SPARC_PC_LM22: | |
3124 | case BFD_RELOC_SPARC_H44: | |
3125 | case BFD_RELOC_SPARC_M44: | |
3126 | case BFD_RELOC_SPARC_L44: | |
3127 | case BFD_RELOC_SPARC_HIX22: | |
3128 | case BFD_RELOC_SPARC_LOX10: | |
3129 | case BFD_RELOC_SPARC_REV32: | |
dabe3bbc | 3130 | case BFD_RELOC_SPARC_OLO10: |
252b5132 RH |
3131 | case BFD_RELOC_VTABLE_ENTRY: |
3132 | case BFD_RELOC_VTABLE_INHERIT: | |
3133 | code = fixp->fx_r_type; | |
3134 | break; | |
3135 | default: | |
3136 | abort (); | |
3137 | return NULL; | |
3138 | } | |
3139 | ||
3140 | #if defined (OBJ_ELF) || defined (OBJ_AOUT) | |
3141 | /* If we are generating PIC code, we need to generate a different | |
3142 | set of relocs. */ | |
3143 | ||
3144 | #ifdef OBJ_ELF | |
3145 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" | |
3146 | #else | |
3147 | #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" | |
3148 | #endif | |
3149 | ||
153b546a ILT |
3150 | /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ |
3151 | ||
252b5132 RH |
3152 | if (sparc_pic_code) |
3153 | { | |
3154 | switch (code) | |
3155 | { | |
3156 | case BFD_RELOC_32_PCREL_S2: | |
3157 | if (! S_IS_DEFINED (fixp->fx_addsy) | |
3158 | || S_IS_COMMON (fixp->fx_addsy) | |
3159 | || S_IS_EXTERNAL (fixp->fx_addsy) | |
3160 | || S_IS_WEAK (fixp->fx_addsy)) | |
3161 | code = BFD_RELOC_SPARC_WPLT30; | |
3162 | break; | |
3163 | case BFD_RELOC_HI22: | |
3164 | if (fixp->fx_addsy != NULL | |
3165 | && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3166 | code = BFD_RELOC_SPARC_PC22; | |
3167 | else | |
3168 | code = BFD_RELOC_SPARC_GOT22; | |
3169 | break; | |
3170 | case BFD_RELOC_LO10: | |
3171 | if (fixp->fx_addsy != NULL | |
3172 | && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3173 | code = BFD_RELOC_SPARC_PC10; | |
3174 | else | |
3175 | code = BFD_RELOC_SPARC_GOT10; | |
3176 | break; | |
3177 | case BFD_RELOC_SPARC13: | |
3178 | code = BFD_RELOC_SPARC_GOT13; | |
3179 | break; | |
3180 | default: | |
3181 | break; | |
3182 | } | |
3183 | } | |
3184 | #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ | |
3185 | ||
dabe3bbc RH |
3186 | if (code == BFD_RELOC_SPARC_OLO10) |
3187 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); | |
3188 | else | |
3189 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
252b5132 RH |
3190 | if (reloc->howto == 0) |
3191 | { | |
3192 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3193 | _("internal error: can't export reloc type %d (`%s')"), | |
3194 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); | |
dabe3bbc RH |
3195 | xfree (reloc); |
3196 | relocs[0] = NULL; | |
3197 | return relocs; | |
252b5132 RH |
3198 | } |
3199 | ||
3200 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ | |
3201 | #ifdef OBJ_AOUT | |
3202 | ||
3203 | if (reloc->howto->pc_relative == 0 | |
3204 | || code == BFD_RELOC_SPARC_PC10 | |
3205 | || code == BFD_RELOC_SPARC_PC22) | |
3206 | reloc->addend = fixp->fx_addnumber; | |
3207 | else if (sparc_pic_code | |
3208 | && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3209 | && fixp->fx_addsy != NULL | |
3210 | && (S_IS_EXTERNAL (fixp->fx_addsy) | |
3211 | || S_IS_WEAK (fixp->fx_addsy)) | |
3212 | && S_IS_DEFINED (fixp->fx_addsy) | |
3213 | && ! S_IS_COMMON (fixp->fx_addsy)) | |
3214 | reloc->addend = fixp->fx_addnumber; | |
3215 | else | |
3216 | reloc->addend = fixp->fx_offset - reloc->address; | |
3217 | ||
3218 | #else /* elf or coff */ | |
3219 | ||
3220 | if (reloc->howto->pc_relative == 0 | |
3221 | || code == BFD_RELOC_SPARC_PC10 | |
3222 | || code == BFD_RELOC_SPARC_PC22) | |
3223 | reloc->addend = fixp->fx_addnumber; | |
49309057 | 3224 | else if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
3225 | reloc->addend = (section->vma |
3226 | + fixp->fx_addnumber | |
3227 | + md_pcrel_from (fixp)); | |
3228 | else | |
3229 | reloc->addend = fixp->fx_offset; | |
3230 | #endif | |
3231 | ||
dabe3bbc RH |
3232 | /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 |
3233 | on the same location. */ | |
3234 | if (code == BFD_RELOC_SPARC_OLO10) | |
3235 | { | |
3236 | relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); | |
3237 | relocs[2] = NULL; | |
3238 | ||
3239 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
3240 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (section_symbol (absolute_section)); | |
3241 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
3242 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); | |
3243 | reloc->addend = fixp->tc_fix_data; | |
3244 | } | |
3245 | ||
3246 | return relocs; | |
252b5132 RH |
3247 | } |
3248 | \f | |
3249 | /* We have no need to default values of symbols. */ | |
3250 | ||
3251 | /* ARGSUSED */ | |
3252 | symbolS * | |
3253 | md_undefined_symbol (name) | |
3254 | char *name; | |
3255 | { | |
3256 | return 0; | |
3257 | } /* md_undefined_symbol() */ | |
3258 | ||
3259 | /* Round up a section size to the appropriate boundary. */ | |
3260 | valueT | |
3261 | md_section_align (segment, size) | |
3262 | segT segment; | |
3263 | valueT size; | |
3264 | { | |
3265 | #ifndef OBJ_ELF | |
3266 | /* This is not right for ELF; a.out wants it, and COFF will force | |
3267 | the alignment anyways. */ | |
3268 | valueT align = ((valueT) 1 | |
3269 | << (valueT) bfd_get_section_alignment (stdoutput, segment)); | |
3270 | valueT newsize; | |
3271 | /* turn alignment value into a mask */ | |
3272 | align--; | |
3273 | newsize = (size + align) & ~align; | |
3274 | return newsize; | |
3275 | #else | |
3276 | return size; | |
3277 | #endif | |
3278 | } | |
3279 | ||
3280 | /* Exactly what point is a PC-relative offset relative TO? | |
3281 | On the sparc, they're relative to the address of the offset, plus | |
3282 | its size. This gets us to the following instruction. | |
3283 | (??? Is this right? FIXME-SOON) */ | |
3284 | long | |
3285 | md_pcrel_from (fixP) | |
3286 | fixS *fixP; | |
3287 | { | |
3288 | long ret; | |
3289 | ||
3290 | ret = fixP->fx_where + fixP->fx_frag->fr_address; | |
3291 | if (! sparc_pic_code | |
3292 | || fixP->fx_addsy == NULL | |
49309057 | 3293 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3294 | ret += fixP->fx_size; |
3295 | return ret; | |
3296 | } | |
3297 | \f | |
3298 | /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power | |
3299 | of two. */ | |
3300 | ||
3301 | static int | |
3302 | log2 (value) | |
3303 | int value; | |
3304 | { | |
3305 | int shift; | |
3306 | ||
3307 | if (value <= 0) | |
3308 | return -1; | |
3309 | ||
3310 | for (shift = 0; (value & 1) == 0; value >>= 1) | |
3311 | ++shift; | |
3312 | ||
3313 | return (value == 1) ? shift : -1; | |
3314 | } | |
3315 | ||
3316 | /* | |
3317 | * sort of like s_lcomm | |
3318 | */ | |
3319 | ||
3320 | #ifndef OBJ_ELF | |
3321 | static int max_alignment = 15; | |
3322 | #endif | |
3323 | ||
3324 | static void | |
3325 | s_reserve (ignore) | |
3326 | int ignore; | |
3327 | { | |
3328 | char *name; | |
3329 | char *p; | |
3330 | char c; | |
3331 | int align; | |
3332 | int size; | |
3333 | int temp; | |
3334 | symbolS *symbolP; | |
3335 | ||
3336 | name = input_line_pointer; | |
3337 | c = get_symbol_end (); | |
3338 | p = input_line_pointer; | |
3339 | *p = c; | |
3340 | SKIP_WHITESPACE (); | |
3341 | ||
3342 | if (*input_line_pointer != ',') | |
3343 | { | |
3344 | as_bad (_("Expected comma after name")); | |
3345 | ignore_rest_of_line (); | |
3346 | return; | |
3347 | } | |
3348 | ||
3349 | ++input_line_pointer; | |
3350 | ||
3351 | if ((size = get_absolute_expression ()) < 0) | |
3352 | { | |
3353 | as_bad (_("BSS length (%d.) <0! Ignored."), size); | |
3354 | ignore_rest_of_line (); | |
3355 | return; | |
3356 | } /* bad length */ | |
3357 | ||
3358 | *p = 0; | |
3359 | symbolP = symbol_find_or_make (name); | |
3360 | *p = c; | |
3361 | ||
3362 | if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 | |
3363 | && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) | |
3364 | { | |
3365 | as_bad (_("bad .reserve segment -- expected BSS segment")); | |
3366 | return; | |
3367 | } | |
3368 | ||
3369 | if (input_line_pointer[2] == '.') | |
3370 | input_line_pointer += 7; | |
3371 | else | |
3372 | input_line_pointer += 6; | |
3373 | SKIP_WHITESPACE (); | |
3374 | ||
3375 | if (*input_line_pointer == ',') | |
3376 | { | |
3377 | ++input_line_pointer; | |
3378 | ||
3379 | SKIP_WHITESPACE (); | |
3380 | if (*input_line_pointer == '\n') | |
3381 | { | |
3382 | as_bad (_("missing alignment")); | |
3383 | ignore_rest_of_line (); | |
3384 | return; | |
3385 | } | |
3386 | ||
3387 | align = (int) get_absolute_expression (); | |
3388 | ||
3389 | #ifndef OBJ_ELF | |
3390 | if (align > max_alignment) | |
3391 | { | |
3392 | align = max_alignment; | |
3393 | as_warn (_("alignment too large; assuming %d"), align); | |
3394 | } | |
3395 | #endif | |
3396 | ||
3397 | if (align < 0) | |
3398 | { | |
3399 | as_bad (_("negative alignment")); | |
3400 | ignore_rest_of_line (); | |
3401 | return; | |
3402 | } | |
3403 | ||
3404 | if (align != 0) | |
3405 | { | |
3406 | temp = log2 (align); | |
3407 | if (temp < 0) | |
3408 | { | |
3409 | as_bad (_("alignment not a power of 2")); | |
3410 | ignore_rest_of_line (); | |
3411 | return; | |
3412 | } | |
3413 | ||
3414 | align = temp; | |
3415 | } | |
3416 | ||
3417 | record_alignment (bss_section, align); | |
3418 | } | |
3419 | else | |
3420 | align = 0; | |
3421 | ||
3422 | if (!S_IS_DEFINED (symbolP) | |
3423 | #ifdef OBJ_AOUT | |
3424 | && S_GET_OTHER (symbolP) == 0 | |
3425 | && S_GET_DESC (symbolP) == 0 | |
3426 | #endif | |
3427 | ) | |
3428 | { | |
3429 | if (! need_pass_2) | |
3430 | { | |
3431 | char *pfrag; | |
3432 | segT current_seg = now_seg; | |
3433 | subsegT current_subseg = now_subseg; | |
3434 | ||
3435 | subseg_set (bss_section, 1); /* switch to bss */ | |
3436 | ||
3437 | if (align) | |
3438 | frag_align (align, 0, 0); /* do alignment */ | |
3439 | ||
3440 | /* detach from old frag */ | |
3441 | if (S_GET_SEGMENT(symbolP) == bss_section) | |
49309057 | 3442 | symbol_get_frag (symbolP)->fr_symbol = NULL; |
252b5132 | 3443 | |
49309057 | 3444 | symbol_set_frag (symbolP, frag_now); |
252b5132 RH |
3445 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP, |
3446 | (offsetT) size, (char *)0); | |
3447 | *pfrag = 0; | |
3448 | ||
3449 | S_SET_SEGMENT (symbolP, bss_section); | |
3450 | ||
3451 | subseg_set (current_seg, current_subseg); | |
3452 | ||
3453 | #ifdef OBJ_ELF | |
3454 | S_SET_SIZE (symbolP, size); | |
3455 | #endif | |
3456 | } | |
3457 | } | |
3458 | else | |
3459 | { | |
3460 | as_warn("Ignoring attempt to re-define symbol %s", | |
3461 | S_GET_NAME (symbolP)); | |
3462 | } /* if not redefining */ | |
3463 | ||
3464 | demand_empty_rest_of_line (); | |
3465 | } | |
3466 | ||
3467 | static void | |
3468 | s_common (ignore) | |
3469 | int ignore; | |
3470 | { | |
3471 | char *name; | |
3472 | char c; | |
3473 | char *p; | |
3474 | int temp, size; | |
3475 | symbolS *symbolP; | |
3476 | ||
3477 | name = input_line_pointer; | |
3478 | c = get_symbol_end (); | |
3479 | /* just after name is now '\0' */ | |
3480 | p = input_line_pointer; | |
3481 | *p = c; | |
3482 | SKIP_WHITESPACE (); | |
3483 | if (*input_line_pointer != ',') | |
3484 | { | |
3485 | as_bad (_("Expected comma after symbol-name")); | |
3486 | ignore_rest_of_line (); | |
3487 | return; | |
3488 | } | |
3489 | input_line_pointer++; /* skip ',' */ | |
3490 | if ((temp = get_absolute_expression ()) < 0) | |
3491 | { | |
3492 | as_bad (_(".COMMon length (%d.) <0! Ignored."), temp); | |
3493 | ignore_rest_of_line (); | |
3494 | return; | |
3495 | } | |
3496 | size = temp; | |
3497 | *p = 0; | |
3498 | symbolP = symbol_find_or_make (name); | |
3499 | *p = c; | |
3500 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
3501 | { | |
3502 | as_bad (_("Ignoring attempt to re-define symbol")); | |
3503 | ignore_rest_of_line (); | |
3504 | return; | |
3505 | } | |
3506 | if (S_GET_VALUE (symbolP) != 0) | |
3507 | { | |
3508 | if (S_GET_VALUE (symbolP) != (valueT) size) | |
3509 | { | |
3510 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."), | |
3511 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); | |
3512 | } | |
3513 | } | |
3514 | else | |
3515 | { | |
3516 | #ifndef OBJ_ELF | |
3517 | S_SET_VALUE (symbolP, (valueT) size); | |
3518 | S_SET_EXTERNAL (symbolP); | |
3519 | #endif | |
3520 | } | |
7dcc9865 | 3521 | know (symbol_get_frag (symbolP) == &zero_address_frag); |
252b5132 RH |
3522 | if (*input_line_pointer != ',') |
3523 | { | |
3524 | as_bad (_("Expected comma after common length")); | |
3525 | ignore_rest_of_line (); | |
3526 | return; | |
3527 | } | |
3528 | input_line_pointer++; | |
3529 | SKIP_WHITESPACE (); | |
3530 | if (*input_line_pointer != '"') | |
3531 | { | |
3532 | temp = get_absolute_expression (); | |
3533 | ||
3534 | #ifndef OBJ_ELF | |
3535 | if (temp > max_alignment) | |
3536 | { | |
3537 | temp = max_alignment; | |
3538 | as_warn (_("alignment too large; assuming %d"), temp); | |
3539 | } | |
3540 | #endif | |
3541 | ||
3542 | if (temp < 0) | |
3543 | { | |
3544 | as_bad (_("negative alignment")); | |
3545 | ignore_rest_of_line (); | |
3546 | return; | |
3547 | } | |
3548 | ||
3549 | #ifdef OBJ_ELF | |
49309057 | 3550 | if (symbol_get_obj (symbolP)->local) |
252b5132 RH |
3551 | { |
3552 | segT old_sec; | |
3553 | int old_subsec; | |
3554 | char *p; | |
3555 | int align; | |
3556 | ||
3557 | old_sec = now_seg; | |
3558 | old_subsec = now_subseg; | |
3559 | ||
3560 | if (temp == 0) | |
3561 | align = 0; | |
3562 | else | |
3563 | align = log2 (temp); | |
3564 | ||
3565 | if (align < 0) | |
3566 | { | |
3567 | as_bad (_("alignment not a power of 2")); | |
3568 | ignore_rest_of_line (); | |
3569 | return; | |
3570 | } | |
3571 | ||
3572 | record_alignment (bss_section, align); | |
3573 | subseg_set (bss_section, 0); | |
3574 | if (align) | |
3575 | frag_align (align, 0, 0); | |
3576 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
3577 | symbol_get_frag (symbolP)->fr_symbol = 0; |
3578 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
3579 | p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
3580 | (offsetT) size, (char *) 0); | |
3581 | *p = 0; | |
3582 | S_SET_SEGMENT (symbolP, bss_section); | |
3583 | S_CLEAR_EXTERNAL (symbolP); | |
3584 | S_SET_SIZE (symbolP, size); | |
3585 | subseg_set (old_sec, old_subsec); | |
3586 | } | |
3587 | else | |
3588 | #endif /* OBJ_ELF */ | |
3589 | { | |
3590 | allocate_common: | |
3591 | S_SET_VALUE (symbolP, (valueT) size); | |
3592 | #ifdef OBJ_ELF | |
3593 | S_SET_ALIGN (symbolP, temp); | |
3594 | S_SET_SIZE (symbolP, size); | |
3595 | #endif | |
3596 | S_SET_EXTERNAL (symbolP); | |
3597 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); | |
3598 | } | |
3599 | } | |
3600 | else | |
3601 | { | |
3602 | input_line_pointer++; | |
3603 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ | |
3604 | if (*input_line_pointer == '.') | |
3605 | input_line_pointer++; | |
3606 | /* @@ Some say data, some say bss. */ | |
3607 | if (strncmp (input_line_pointer, "bss\"", 4) | |
3608 | && strncmp (input_line_pointer, "data\"", 5)) | |
3609 | { | |
3610 | while (*--input_line_pointer != '"') | |
3611 | ; | |
3612 | input_line_pointer--; | |
3613 | goto bad_common_segment; | |
3614 | } | |
3615 | while (*input_line_pointer++ != '"') | |
3616 | ; | |
3617 | goto allocate_common; | |
3618 | } | |
3619 | ||
3620 | #ifdef BFD_ASSEMBLER | |
49309057 | 3621 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; |
252b5132 RH |
3622 | #endif |
3623 | ||
3624 | demand_empty_rest_of_line (); | |
3625 | return; | |
3626 | ||
3627 | { | |
3628 | bad_common_segment: | |
3629 | p = input_line_pointer; | |
3630 | while (*p && *p != '\n') | |
3631 | p++; | |
3632 | c = *p; | |
3633 | *p = '\0'; | |
3634 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); | |
3635 | *p = c; | |
3636 | input_line_pointer = p; | |
3637 | ignore_rest_of_line (); | |
3638 | return; | |
3639 | } | |
3640 | } | |
3641 | ||
3642 | /* Handle the .empty pseudo-op. This supresses the warnings about | |
3643 | invalid delay slot usage. */ | |
3644 | ||
3645 | static void | |
3646 | s_empty (ignore) | |
3647 | int ignore; | |
3648 | { | |
3649 | /* The easy way to implement is to just forget about the last | |
3650 | instruction. */ | |
3651 | last_insn = NULL; | |
3652 | } | |
3653 | ||
3654 | static void | |
3655 | s_seg (ignore) | |
3656 | int ignore; | |
3657 | { | |
3658 | ||
3659 | if (strncmp (input_line_pointer, "\"text\"", 6) == 0) | |
3660 | { | |
3661 | input_line_pointer += 6; | |
3662 | s_text (0); | |
3663 | return; | |
3664 | } | |
3665 | if (strncmp (input_line_pointer, "\"data\"", 6) == 0) | |
3666 | { | |
3667 | input_line_pointer += 6; | |
3668 | s_data (0); | |
3669 | return; | |
3670 | } | |
3671 | if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) | |
3672 | { | |
3673 | input_line_pointer += 7; | |
3674 | s_data1 (); | |
3675 | return; | |
3676 | } | |
3677 | if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) | |
3678 | { | |
3679 | input_line_pointer += 5; | |
3680 | /* We only support 2 segments -- text and data -- for now, so | |
3681 | things in the "bss segment" will have to go into data for now. | |
3682 | You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ | |
3683 | subseg_set (data_section, 255); /* FIXME-SOMEDAY */ | |
3684 | return; | |
3685 | } | |
3686 | as_bad (_("Unknown segment type")); | |
3687 | demand_empty_rest_of_line (); | |
3688 | } | |
3689 | ||
3690 | static void | |
3691 | s_data1 () | |
3692 | { | |
3693 | subseg_set (data_section, 1); | |
3694 | demand_empty_rest_of_line (); | |
3695 | } | |
3696 | ||
3697 | static void | |
3698 | s_proc (ignore) | |
3699 | int ignore; | |
3700 | { | |
3701 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
3702 | { | |
3703 | ++input_line_pointer; | |
3704 | } | |
3705 | ++input_line_pointer; | |
3706 | } | |
3707 | ||
3708 | /* This static variable is set by s_uacons to tell sparc_cons_align | |
3709 | that the expession does not need to be aligned. */ | |
3710 | ||
3711 | static int sparc_no_align_cons = 0; | |
3712 | ||
3713 | /* This handles the unaligned space allocation pseudo-ops, such as | |
3714 | .uaword. .uaword is just like .word, but the value does not need | |
3715 | to be aligned. */ | |
3716 | ||
3717 | static void | |
3718 | s_uacons (bytes) | |
3719 | int bytes; | |
3720 | { | |
3721 | /* Tell sparc_cons_align not to align this value. */ | |
3722 | sparc_no_align_cons = 1; | |
3723 | cons (bytes); | |
3724 | } | |
3725 | ||
cf9a1301 RH |
3726 | /* This handles the native word allocation pseudo-op .nword. |
3727 | For sparc_arch_size 32 it is equivalent to .word, for | |
3728 | sparc_arch_size 64 it is equivalent to .xword. */ | |
3729 | ||
3730 | static void | |
3731 | s_ncons (bytes) | |
3732 | int bytes; | |
3733 | { | |
3734 | cons (sparc_arch_size == 32 ? 4 : 8); | |
3735 | } | |
3736 | ||
6d8809aa RH |
3737 | #ifdef OBJ_ELF |
3738 | /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a | |
3739 | global register. | |
3740 | The syntax is: | |
3741 | ||
3742 | .register %g[2367],{#scratch|symbolname|#ignore} | |
3743 | */ | |
3744 | ||
3745 | static void | |
3746 | s_register (ignore) | |
3747 | int ignore; | |
3748 | { | |
3749 | char c; | |
3750 | int reg; | |
3751 | int flags; | |
3752 | const char *regname; | |
3753 | ||
3754 | if (input_line_pointer[0] != '%' | |
3755 | || input_line_pointer[1] != 'g' | |
3756 | || ((input_line_pointer[2] & ~1) != '2' | |
3757 | && (input_line_pointer[2] & ~1) != '6') | |
3758 | || input_line_pointer[3] != ',') | |
3759 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
3760 | reg = input_line_pointer[2] - '0'; | |
3761 | input_line_pointer += 4; | |
3762 | ||
3763 | if (*input_line_pointer == '#') | |
3764 | { | |
3765 | ++input_line_pointer; | |
3766 | regname = input_line_pointer; | |
3767 | c = get_symbol_end (); | |
3768 | if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) | |
3769 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
3770 | if (regname [0] == 'i') | |
3771 | regname = NULL; | |
3772 | else | |
3773 | regname = ""; | |
3774 | } | |
3775 | else | |
3776 | { | |
3777 | regname = input_line_pointer; | |
3778 | c = get_symbol_end (); | |
3779 | } | |
3780 | if (sparc_arch_size == 64) | |
3781 | { | |
3782 | if (globals [reg]) | |
3783 | { | |
3784 | if ((regname && globals [reg] != (symbolS *)1 | |
3785 | && strcmp (S_GET_NAME (globals [reg]), regname)) | |
3786 | || ((regname != NULL) ^ (globals [reg] != (symbolS *)1))) | |
3787 | as_bad (_("redefinition of global register")); | |
3788 | } | |
3789 | else | |
3790 | { | |
3791 | if (regname == NULL) | |
3792 | globals [reg] = (symbolS *)1; | |
3793 | else | |
3794 | { | |
3795 | if (*regname) | |
3796 | { | |
3797 | if (symbol_find (regname)) | |
3798 | as_bad (_("Register symbol %s already defined."), | |
3799 | regname); | |
3800 | } | |
3801 | globals [reg] = symbol_make (regname); | |
3802 | flags = symbol_get_bfdsym (globals [reg])->flags; | |
3803 | if (! *regname) | |
3804 | flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); | |
3805 | if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) | |
3806 | flags |= BSF_GLOBAL; | |
3807 | symbol_get_bfdsym (globals [reg])->flags = flags; | |
3808 | S_SET_VALUE (globals [reg], (valueT)reg); | |
3809 | S_SET_ALIGN (globals [reg], reg); | |
3810 | S_SET_SIZE (globals [reg], 0); | |
3811 | /* Although we actually want undefined_section here, | |
3812 | we have to use absolute_section, because otherwise | |
3813 | generic as code will make it a COM section. | |
3814 | We fix this up in sparc_adjust_symtab. */ | |
3815 | S_SET_SEGMENT (globals [reg], absolute_section); | |
3816 | S_SET_OTHER (globals [reg], 0); | |
3817 | elf_symbol (symbol_get_bfdsym (globals [reg])) | |
3818 | ->internal_elf_sym.st_info = | |
3819 | ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); | |
3820 | elf_symbol (symbol_get_bfdsym (globals [reg])) | |
3821 | ->internal_elf_sym.st_shndx = SHN_UNDEF; | |
3822 | } | |
3823 | } | |
3824 | } | |
3825 | ||
3826 | *input_line_pointer = c; | |
3827 | ||
3828 | demand_empty_rest_of_line (); | |
3829 | } | |
3830 | ||
3831 | /* Adjust the symbol table. We set undefined sections for STT_REGISTER | |
3832 | symbols which need it. */ | |
3833 | ||
3834 | void | |
3835 | sparc_adjust_symtab () | |
3836 | { | |
3837 | symbolS *sym; | |
3838 | ||
3839 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
3840 | { | |
3841 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
3842 | ->internal_elf_sym.st_info) != STT_REGISTER) | |
3843 | continue; | |
3844 | ||
3845 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
3846 | ->internal_elf_sym.st_shndx != SHN_UNDEF)) | |
3847 | continue; | |
3848 | ||
3849 | S_SET_SEGMENT (sym, undefined_section); | |
3850 | } | |
3851 | } | |
3852 | #endif | |
3853 | ||
252b5132 RH |
3854 | /* If the --enforce-aligned-data option is used, we require .word, |
3855 | et. al., to be aligned correctly. We do it by setting up an | |
3856 | rs_align_code frag, and checking in HANDLE_ALIGN to make sure that | |
3857 | no unexpected alignment was introduced. | |
3858 | ||
3859 | The SunOS and Solaris native assemblers enforce aligned data by | |
3860 | default. We don't want to do that, because gcc can deliberately | |
3861 | generate misaligned data if the packed attribute is used. Instead, | |
3862 | we permit misaligned data by default, and permit the user to set an | |
3863 | option to check for it. */ | |
3864 | ||
3865 | void | |
3866 | sparc_cons_align (nbytes) | |
3867 | int nbytes; | |
3868 | { | |
3869 | int nalign; | |
3870 | char *p; | |
3871 | ||
3872 | /* Only do this if we are enforcing aligned data. */ | |
3873 | if (! enforce_aligned_data) | |
3874 | return; | |
3875 | ||
3876 | if (sparc_no_align_cons) | |
3877 | { | |
3878 | /* This is an unaligned pseudo-op. */ | |
3879 | sparc_no_align_cons = 0; | |
3880 | return; | |
3881 | } | |
3882 | ||
3883 | nalign = log2 (nbytes); | |
3884 | if (nalign == 0) | |
3885 | return; | |
3886 | ||
3887 | assert (nalign > 0); | |
3888 | ||
3889 | if (now_seg == absolute_section) | |
3890 | { | |
3891 | if ((abs_section_offset & ((1 << nalign) - 1)) != 0) | |
3892 | as_bad (_("misaligned data")); | |
3893 | return; | |
3894 | } | |
3895 | ||
3896 | p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0, | |
3897 | (symbolS *) NULL, (offsetT) nalign, (char *) NULL); | |
3898 | ||
3899 | record_alignment (now_seg, nalign); | |
3900 | } | |
3901 | ||
3902 | /* This is where we do the unexpected alignment check. | |
3903 | This is called from HANDLE_ALIGN in tc-sparc.h. */ | |
3904 | ||
3905 | void | |
3906 | sparc_handle_align (fragp) | |
3907 | fragS *fragp; | |
3908 | { | |
3909 | if (fragp->fr_type == rs_align_code && !fragp->fr_subtype | |
3910 | && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0) | |
3911 | as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); | |
3912 | if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024) | |
3913 | { | |
3914 | int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
3915 | ||
3916 | if (count >= 4 | |
3917 | && !(count & 3) | |
3918 | && count <= 1024 | |
3919 | && !((long)(fragp->fr_literal + fragp->fr_fix) & 3)) | |
3920 | { | |
3921 | unsigned *p = (unsigned *)(fragp->fr_literal + fragp->fr_fix); | |
3922 | int i; | |
3923 | ||
3924 | for (i = 0; i < count; i += 4, p++) | |
3925 | if (INSN_BIG_ENDIAN) | |
3926 | number_to_chars_bigendian ((char *)p, 0x01000000, 4); /* emit nops */ | |
3927 | else | |
3928 | number_to_chars_littleendian ((char *)p, 0x10000000, 4); | |
3929 | ||
3930 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) | |
3931 | { | |
3932 | char *waddr = &fragp->fr_literal[fragp->fr_fix]; | |
3933 | unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ | |
3934 | if (INSN_BIG_ENDIAN) | |
3935 | number_to_chars_bigendian (waddr, wval, 4); | |
3936 | else | |
3937 | number_to_chars_littleendian (waddr, wval, 4); | |
3938 | } | |
3939 | fragp->fr_var = count; | |
3940 | } | |
3941 | } | |
3942 | } | |
3943 | ||
3944 | #ifdef OBJ_ELF | |
3945 | /* Some special processing for a Sparc ELF file. */ | |
3946 | ||
3947 | void | |
3948 | sparc_elf_final_processing () | |
3949 | { | |
3950 | /* Set the Sparc ELF flag bits. FIXME: There should probably be some | |
3951 | sort of BFD interface for this. */ | |
3952 | if (sparc_arch_size == 64) | |
3953 | { | |
3954 | switch (sparc_memory_model) | |
3955 | { | |
3956 | case MM_RMO: | |
3957 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; | |
3958 | break; | |
3959 | case MM_PSO: | |
3960 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; | |
3961 | break; | |
3962 | default: | |
3963 | break; | |
3964 | } | |
3965 | } | |
3966 | else if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
3967 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; | |
3968 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
3969 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; | |
3970 | } | |
3971 | #endif | |
3972 | ||
3973 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
3974 | reloc for a cons. We could use the definition there, except that | |
3975 | we want to handle little endian relocs specially. */ | |
3976 | ||
3977 | void | |
3978 | cons_fix_new_sparc (frag, where, nbytes, exp) | |
3979 | fragS *frag; | |
3980 | int where; | |
3981 | unsigned int nbytes; | |
3982 | expressionS *exp; | |
3983 | { | |
3984 | bfd_reloc_code_real_type r; | |
3985 | ||
3986 | r = (nbytes == 1 ? BFD_RELOC_8 : | |
3987 | (nbytes == 2 ? BFD_RELOC_16 : | |
3988 | (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
3989 | ||
3990 | if (target_little_endian_data && nbytes == 4 | |
3991 | && now_seg->flags & SEC_ALLOC) | |
3992 | r = BFD_RELOC_SPARC_REV32; | |
3993 | fix_new_exp (frag, where, (int) nbytes, exp, 0, r); | |
3994 | } | |
3995 | ||
3996 | #ifdef OBJ_ELF | |
3997 | int | |
3998 | elf32_sparc_force_relocation (fixp) | |
3999 | struct fix *fixp; | |
4000 | { | |
4001 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
4002 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4003 | return 1; | |
4004 | ||
4005 | return 0; | |
4006 | } | |
4007 | #endif | |
4008 |