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* symbols.c (S_FORCE_RELOC): Add "strict" param.
[deliverable/binutils-gdb.git] / gas / config / tc-sparc.c
CommitLineData
252b5132 1/* tc-sparc.c -- Assemble for the SPARC
f7e42eb4 2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
ae6063d4 3 1999, 2000, 2001, 2002, 2003
e0c6ed95 4 Free Software Foundation, Inc.
252b5132
RH		 5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 59 Temple Place - Suite 330,
81d4177b 20 Boston, MA 02111-1307, USA. */
252b5132
RH		 21
22#include <stdio.h>
252b5132
RH		 23
24#include "as.h"
3882b010 25#include "safe-ctype.h"
252b5132
RH		 26#include "subsegs.h"
27
28#include "opcode/sparc.h"
29
30#ifdef OBJ_ELF
31#include "elf/sparc.h"
732d96b6 32#include "dwarf2dbg.h"
252b5132
RH		 33#endif
34
6c1b24e4
AO		 35/* Some ancient Sun C compilers would not take such hex constants as
36 unsigned, and would end up sign-extending them to form an offsetT,
37 so use these constants instead. */
38#define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39#define U0x80000000 ((((unsigned long) 1 << 16) << 15))
40
252b5132
RH		 41static struct sparc_arch *lookup_arch PARAMS ((char *));
42static void init_default_arch PARAMS ((void));
a22b281c 43static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
252b5132
RH		 44static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
45static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
46static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
47static int sparc_ffs PARAMS ((unsigned int));
a22b281c
RH		 48static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
49static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
50static void synthetize_setx PARAMS ((const struct sparc_opcode *));
252b5132
RH		 51static bfd_vma BSR PARAMS ((bfd_vma, int));
52static int cmp_reg_entry PARAMS ((const PTR, const PTR));
53static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
54static int parse_const_expr_arg PARAMS ((char **, int *));
55static int get_expression PARAMS ((char *str));
56
57/* Default architecture. */
58/* ??? The default value should be V8, but sparclite support was added
59 by making it the default. GCC now passes -Asparclite, so maybe sometime in
60 the future we can set this to V8. */
61#ifndef DEFAULT_ARCH
62#define DEFAULT_ARCH "sparclite"
63#endif
64static char *default_arch = DEFAULT_ARCH;
65
66/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
67 have been set. */
68static int default_init_p;
69
70/* Current architecture. We don't bump up unless necessary. */
71static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
72
73/* The maximum architecture level we can bump up to.
74 In a 32 bit environment, don't allow bumping up to v9 by default.
75 The native assembler works this way. The user is required to pass
76 an explicit argument before we'll create v9 object files. However, if
77 we don't see any v9 insns, a v8plus object file is not created. */
78static enum sparc_opcode_arch_val max_architecture;
79
80/* Either 32 or 64, selects file format. */
81static int sparc_arch_size;
82/* Initial (default) value, recorded separately in case a user option
83 changes the value before md_show_usage is called. */
84static int default_arch_size;
85
86#ifdef OBJ_ELF
87/* The currently selected v9 memory model. Currently only used for
88 ELF. */
89static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
90#endif
91
92static int architecture_requested;
93static int warn_on_bump;
94
95/* If warn_on_bump and the needed architecture is higher than this
96 architecture, issue a warning. */
97static enum sparc_opcode_arch_val warn_after_architecture;
98
6d8809aa
RH		 99/* Non-zero if as should generate error if an undeclared g[23] register
100 has been used in -64. */
101static int no_undeclared_regs;
102
6faf3d66
JJ		 103/* Non-zero if we should try to relax jumps and calls. */
104static int sparc_relax;
105
252b5132
RH		 106/* Non-zero if we are generating PIC code. */
107int sparc_pic_code;
108
109/* Non-zero if we should give an error when misaligned data is seen. */
110static int enforce_aligned_data;
111
112extern int target_big_endian;
113
114static int target_little_endian_data;
115
6d8809aa
RH		 116/* Symbols for global registers on v9. */
117static symbolS *globals[8];
118
252b5132
RH		 119/* V9 and 86x have big and little endian data, but instructions are always big
120 endian. The sparclet has bi-endian support but both data and insns have
121 the same endianness. Global `target_big_endian' is used for data.
122 The following macro is used for instructions. */
123#ifndef INSN_BIG_ENDIAN
124#define INSN_BIG_ENDIAN (target_big_endian \
125 || default_arch_type == sparc86x \
126 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
127#endif
128
e0c6ed95 129/* Handle of the OPCODE hash table. */
252b5132
RH		 130static struct hash_control *op_hash;
131
132static int log2 PARAMS ((int));
133static void s_data1 PARAMS ((void));
134static void s_seg PARAMS ((int));
135static void s_proc PARAMS ((int));
136static void s_reserve PARAMS ((int));
137static void s_common PARAMS ((int));
138static void s_empty PARAMS ((int));
139static void s_uacons PARAMS ((int));
cf9a1301 140static void s_ncons PARAMS ((int));
a7982600 141#ifdef OBJ_ELF
6d8809aa 142static void s_register PARAMS ((int));
a7982600 143#endif
252b5132
RH		 144
145const pseudo_typeS md_pseudo_table[] =
146{
e0c6ed95 147 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
252b5132
RH		 148 {"common", s_common, 0},
149 {"empty", s_empty, 0},
150 {"global", s_globl, 0},
151 {"half", cons, 2},
cf9a1301 152 {"nword", s_ncons, 0},
252b5132
RH		 153 {"optim", s_ignore, 0},
154 {"proc", s_proc, 0},
155 {"reserve", s_reserve, 0},
156 {"seg", s_seg, 0},
157 {"skip", s_space, 0},
158 {"word", cons, 4},
159 {"xword", cons, 8},
160 {"uahalf", s_uacons, 2},
161 {"uaword", s_uacons, 4},
162 {"uaxword", s_uacons, 8},
163#ifdef OBJ_ELF
9f1838ed 164 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
732d96b6 165 {"loc", dwarf2_directive_loc, 0},
e0c6ed95 166 /* These are specific to sparc/svr4. */
252b5132
RH		 167 {"2byte", s_uacons, 2},
168 {"4byte", s_uacons, 4},
169 {"8byte", s_uacons, 8},
6d8809aa 170 {"register", s_register, 0},
252b5132
RH		 171#endif
172 {NULL, 0, 0},
173};
174
e0c6ed95
AM		 175/* Size of relocation record. */
176const int md_reloc_size = 12;
252b5132
RH		 177
178/* This array holds the chars that always start a comment. If the
e0c6ed95
AM		 179 pre-processor is disabled, these aren't very useful. */
180const char comment_chars[] = "!"; /* JF removed '|' from
181 comment_chars. */
252b5132
RH		 182
183/* This array holds the chars that only start a comment at the beginning of
184 a line. If the line seems to have the form '# 123 filename'
e0c6ed95 185 .line and .file directives will appear in the pre-processed output. */
252b5132
RH		 186/* Note that input_file.c hand checks for '#' at the beginning of the
187 first line of the input file. This is because the compiler outputs
e0c6ed95 188 #NO_APP at the beginning of its output. */
252b5132 189/* Also note that comments started like this one will always
e0c6ed95 190 work if '/' isn't otherwise defined. */
252b5132
RH		 191const char line_comment_chars[] = "#";
192
63a0b638 193const char line_separator_chars[] = ";";
252b5132 194
e0c6ed95
AM		 195/* Chars that can be used to separate mant from exp in floating point
196 nums. */
252b5132
RH		 197const char EXP_CHARS[] = "eE";
198
e0c6ed95
AM		 199/* Chars that mean this number is a floating point constant.
200 As in 0f12.456
201 or 0d1.2345e12 */
252b5132
RH		 202const char FLT_CHARS[] = "rRsSfFdDxXpP";
203
204/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
205 changed in read.c. Ideally it shouldn't have to know about it at all,
206 but nothing is ideal around here. */
207
bc805888 208#define isoctal(c) ((unsigned) ((c) - '0') < '8')
252b5132
RH		 209
210struct sparc_it
211 {
212 char *error;
213 unsigned long opcode;
214 struct nlist *nlistp;
215 expressionS exp;
cf9a1301 216 expressionS exp2;
252b5132
RH		 217 int pcrel;
218 bfd_reloc_code_real_type reloc;
219 };
220
221struct sparc_it the_insn, set_insn;
222
223static void output_insn
224 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
225\f
226/* Table of arguments to -A.
227 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
228 for this use. That table is for opcodes only. This table is for opcodes
229 and file formats. */
230
231enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
19f7b010 232 v8plusa, v9, v9a, v9b, v9_64};
252b5132
RH		 233
234static struct sparc_arch {
235 char *name;
236 char *opcode_arch;
237 enum sparc_arch_types arch_type;
238 /* Default word size, as specified during configuration.
239 A value of zero means can't be used to specify default architecture. */
240 int default_arch_size;
241 /* Allowable arg to -A? */
242 int user_option_p;
243} sparc_arch_table[] = {
244 { "v6", "v6", v6, 0, 1 },
245 { "v7", "v7", v7, 0, 1 },
246 { "v8", "v8", v8, 32, 1 },
247 { "sparclet", "sparclet", sparclet, 32, 1 },
248 { "sparclite", "sparclite", sparclite, 32, 1 },
249 { "sparc86x", "sparclite", sparc86x, 32, 1 },
250 { "v8plus", "v9", v9, 0, 1 },
251 { "v8plusa", "v9a", v9, 0, 1 },
19f7b010 252 { "v8plusb", "v9b", v9, 0, 1 },
252b5132
RH		 253 { "v9", "v9", v9, 0, 1 },
254 { "v9a", "v9a", v9, 0, 1 },
19f7b010 255 { "v9b", "v9b", v9, 0, 1 },
252b5132
RH		 256 /* This exists to allow configure.in/Makefile.in to pass one
257 value to specify both the default machine and default word size. */
258 { "v9-64", "v9", v9, 64, 0 },
259 { NULL, NULL, v8, 0, 0 }
260};
261
262/* Variant of default_arch */
263static enum sparc_arch_types default_arch_type;
264
265static struct sparc_arch *
266lookup_arch (name)
267 char *name;
268{
269 struct sparc_arch *sa;
270
271 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
272 if (strcmp (sa->name, name) == 0)
273 break;
274 if (sa->name == NULL)
275 return NULL;
276 return sa;
277}
278
279/* Initialize the default opcode arch and word size from the default
280 architecture name. */
281
282static void
283init_default_arch ()
284{
285 struct sparc_arch *sa = lookup_arch (default_arch);
286
287 if (sa == NULL
288 || sa->default_arch_size == 0)
289 as_fatal (_("Invalid default architecture, broken assembler."));
290
291 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
292 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
293 as_fatal (_("Bad opcode table, broken assembler."));
294 default_arch_size = sparc_arch_size = sa->default_arch_size;
295 default_init_p = 1;
296 default_arch_type = sa->arch_type;
297}
298
299/* Called by TARGET_FORMAT. */
300
301const char *
302sparc_target_format ()
303{
304 /* We don't get a chance to initialize anything before we're called,
305 so handle that now. */
306 if (! default_init_p)
307 init_default_arch ();
308
309#ifdef OBJ_AOUT
310#ifdef TE_NetBSD
311 return "a.out-sparc-netbsd";
312#else
313#ifdef TE_SPARCAOUT
314 if (target_big_endian)
315 return "a.out-sunos-big";
316 else if (default_arch_type == sparc86x && target_little_endian_data)
317 return "a.out-sunos-big";
ab3e48dc
KH		 318 else
319 return "a.out-sparc-little";
252b5132
RH		 320#else
321 return "a.out-sunos-big";
322#endif
323#endif
324#endif
325
326#ifdef OBJ_BOUT
327 return "b.out.big";
328#endif
329
330#ifdef OBJ_COFF
331#ifdef TE_LYNX
332 return "coff-sparc-lynx";
333#else
334 return "coff-sparc";
335#endif
336#endif
337
338#ifdef OBJ_ELF
339 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
340#endif
341
342 abort ();
343}
344\f
e0c6ed95 345/* md_parse_option
252b5132
RH		 346 * Invocation line includes a switch not recognized by the base assembler.
347 * See if it's a processor-specific option. These are:
348 *
349 * -bump
350 * Warn on architecture bumps. See also -A.
351 *
352 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
353 * Standard 32 bit architectures.
19f7b010 354 * -Av9, -Av9a, -Av9b
252b5132
RH		 355 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
356 * This used to only mean 64 bits, but properly specifying it
357 * complicated gcc's ASM_SPECs, so now opcode selection is
358 * specified orthogonally to word size (except when specifying
359 * the default, but that is an internal implementation detail).
19f7b010
JJ		 360 * -Av8plus, -Av8plusa, -Av8plusb
361 * Same as -Av9{,a,b}.
362 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
363 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
364 * assembler.
365 * -xarch=v9, -xarch=v9a, -xarch=v9b
366 * Same as -Av9{,a,b} -64, for compatibility with Sun's
c2158c24 367 * assembler.
252b5132
RH		 368 *
369 * Select the architecture and possibly the file format.
370 * Instructions or features not supported by the selected
371 * architecture cause fatal errors.
372 *
373 * The default is to start at v6, and bump the architecture up
374 * whenever an instruction is seen at a higher level. In 32 bit
375 * environments, v9 is not bumped up to, the user must pass
19f7b010 376 * -Av8plus{,a,b}.
252b5132
RH		 377 *
378 * If -bump is specified, a warning is printing when bumping to
379 * higher levels.
380 *
381 * If an architecture is specified, all instructions must match
382 * that architecture. Any higher level instructions are flagged
383 * as errors. Note that in the 32 bit environment specifying
384 * -Av8plus does not automatically create a v8plus object file, a
385 * v9 insn must be seen.
386 *
387 * If both an architecture and -bump are specified, the
388 * architecture starts at the specified level, but bumps are
389 * warnings. Note that we can't set `current_architecture' to
390 * the requested level in this case: in the 32 bit environment,
391 * we still must avoid creating v8plus object files unless v9
392 * insns are seen.
393 *
394 * Note:
395 * Bumping between incompatible architectures is always an
396 * error. For example, from sparclite to v9.
397 */
398
399#ifdef OBJ_ELF
5a38dc70 400const char *md_shortopts = "A:K:VQ:sq";
252b5132
RH		 401#else
402#ifdef OBJ_AOUT
5a38dc70 403const char *md_shortopts = "A:k";
252b5132 404#else
5a38dc70 405const char *md_shortopts = "A:";
252b5132
RH		 406#endif
407#endif
408struct option md_longopts[] = {
409#define OPTION_BUMP (OPTION_MD_BASE)
410 {"bump", no_argument, NULL, OPTION_BUMP},
411#define OPTION_SPARC (OPTION_MD_BASE + 1)
412 {"sparc", no_argument, NULL, OPTION_SPARC},
413#define OPTION_XARCH (OPTION_MD_BASE + 2)
414 {"xarch", required_argument, NULL, OPTION_XARCH},
415#ifdef OBJ_ELF
416#define OPTION_32 (OPTION_MD_BASE + 3)
417 {"32", no_argument, NULL, OPTION_32},
418#define OPTION_64 (OPTION_MD_BASE + 4)
419 {"64", no_argument, NULL, OPTION_64},
420#define OPTION_TSO (OPTION_MD_BASE + 5)
421 {"TSO", no_argument, NULL, OPTION_TSO},
422#define OPTION_PSO (OPTION_MD_BASE + 6)
423 {"PSO", no_argument, NULL, OPTION_PSO},
424#define OPTION_RMO (OPTION_MD_BASE + 7)
425 {"RMO", no_argument, NULL, OPTION_RMO},
426#endif
427#ifdef SPARC_BIENDIAN
428#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
429 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
430#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
431 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
432#endif
433#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
434 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
435#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
436 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
6d8809aa
RH		 437#ifdef OBJ_ELF
438#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
439 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
a25fe906
ILT		 440#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
441 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
6d8809aa 442#endif
6faf3d66
JJ		 443#define OPTION_RELAX (OPTION_MD_BASE + 14)
444 {"relax", no_argument, NULL, OPTION_RELAX},
445#define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
446 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
252b5132
RH		 447 {NULL, no_argument, NULL, 0}
448};
e0c6ed95
AM		 449
450size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 451
452int
453md_parse_option (c, arg)
454 int c;
455 char *arg;
456{
457 /* We don't get a chance to initialize anything before we're called,
458 so handle that now. */
459 if (! default_init_p)
460 init_default_arch ();
461
462 switch (c)
463 {
464 case OPTION_BUMP:
465 warn_on_bump = 1;
466 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
467 break;
468
469 case OPTION_XARCH:
c2158c24
JJ		 470#ifdef OBJ_ELF
471 if (strncmp (arg, "v9", 2) != 0)
472 md_parse_option (OPTION_32, NULL);
473 else
474 md_parse_option (OPTION_64, NULL);
475#endif
e0c6ed95 476 /* Fall through. */
252b5132
RH		 477
478 case 'A':
479 {
480 struct sparc_arch *sa;
481 enum sparc_opcode_arch_val opcode_arch;
482
483 sa = lookup_arch (arg);
484 if (sa == NULL
485 || ! sa->user_option_p)
486 {
c2158c24
JJ		 487 if (c == OPTION_XARCH)
488 as_bad (_("invalid architecture -xarch=%s"), arg);
489 else
490 as_bad (_("invalid architecture -A%s"), arg);
252b5132
RH		 491 return 0;
492 }
493
494 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
495 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
496 as_fatal (_("Bad opcode table, broken assembler."));
497
498 max_architecture = opcode_arch;
499 architecture_requested = 1;
500 }
501 break;
502
503 case OPTION_SPARC:
504 /* Ignore -sparc, used by SunOS make default .s.o rule. */
505 break;
506
507 case OPTION_ENFORCE_ALIGNED_DATA:
508 enforce_aligned_data = 1;
509 break;
510
511#ifdef SPARC_BIENDIAN
512 case OPTION_LITTLE_ENDIAN:
513 target_big_endian = 0;
514 if (default_arch_type != sparclet)
515 as_fatal ("This target does not support -EL");
516 break;
517 case OPTION_LITTLE_ENDIAN_DATA:
518 target_little_endian_data = 1;
519 target_big_endian = 0;
520 if (default_arch_type != sparc86x
521 && default_arch_type != v9)
522 as_fatal ("This target does not support --little-endian-data");
523 break;
524 case OPTION_BIG_ENDIAN:
525 target_big_endian = 1;
526 break;
527#endif
528
529#ifdef OBJ_AOUT
530 case 'k':
531 sparc_pic_code = 1;
532 break;
533#endif
534
535#ifdef OBJ_ELF
536 case OPTION_32:
537 case OPTION_64:
538 {
539 const char **list, **l;
540
541 sparc_arch_size = c == OPTION_32 ? 32 : 64;
542 list = bfd_target_list ();
543 for (l = list; *l != NULL; l++)
544 {
545 if (sparc_arch_size == 32)
546 {
547 if (strcmp (*l, "elf32-sparc") == 0)
548 break;
549 }
550 else
551 {
552 if (strcmp (*l, "elf64-sparc") == 0)
553 break;
554 }
555 }
556 if (*l == NULL)
557 as_fatal (_("No compiled in support for %d bit object file format"),
558 sparc_arch_size);
559 free (list);
560 }
561 break;
562
563 case OPTION_TSO:
564 sparc_memory_model = MM_TSO;
565 break;
566
567 case OPTION_PSO:
568 sparc_memory_model = MM_PSO;
569 break;
570
571 case OPTION_RMO:
572 sparc_memory_model = MM_RMO;
573 break;
574
575 case 'V':
576 print_version_id ();
577 break;
578
579 case 'Q':
580 /* Qy - do emit .comment
e0c6ed95 581 Qn - do not emit .comment. */
252b5132
RH		 582 break;
583
584 case 's':
e0c6ed95 585 /* Use .stab instead of .stab.excl. */
252b5132
RH		 586 break;
587
588 case 'q':
e0c6ed95 589 /* quick -- Native assembler does fewer checks. */
252b5132
RH		 590 break;
591
592 case 'K':
593 if (strcmp (arg, "PIC") != 0)
594 as_warn (_("Unrecognized option following -K"));
595 else
596 sparc_pic_code = 1;
597 break;
6d8809aa
RH		 598
599 case OPTION_NO_UNDECLARED_REGS:
600 no_undeclared_regs = 1;
601 break;
a25fe906
ILT		 602
603 case OPTION_UNDECLARED_REGS:
604 no_undeclared_regs = 0;
605 break;
252b5132
RH		 606#endif
607
6faf3d66
JJ		 608 case OPTION_RELAX:
609 sparc_relax = 1;
610 break;
611
612 case OPTION_NO_RELAX:
613 sparc_relax = 0;
614 break;
615
252b5132
RH		 616 default:
617 return 0;
618 }
619
620 return 1;
621}
622
623void
624md_show_usage (stream)
625 FILE *stream;
626{
627 const struct sparc_arch *arch;
c2158c24 628 int column;
252b5132
RH		 629
630 /* We don't get a chance to initialize anything before we're called,
631 so handle that now. */
632 if (! default_init_p)
633 init_default_arch ();
634
e0c6ed95 635 fprintf (stream, _("SPARC options:\n"));
c2158c24 636 column = 0;
252b5132
RH		 637 for (arch = &sparc_arch_table[0]; arch->name; arch++)
638 {
c2158c24
JJ		 639 if (!arch->user_option_p)
640 continue;
252b5132
RH		 641 if (arch != &sparc_arch_table[0])
642 fprintf (stream, " | ");
07726851 643 if (column + strlen (arch->name) > 70)
c2158c24
JJ		 644 {
645 column = 0;
646 fputc ('\n', stream);
647 }
07726851 648 column += 5 + 2 + strlen (arch->name);
c2158c24 649 fprintf (stream, "-A%s", arch->name);
252b5132 650 }
c2158c24
JJ		 651 for (arch = &sparc_arch_table[0]; arch->name; arch++)
652 {
653 if (!arch->user_option_p)
654 continue;
655 fprintf (stream, " | ");
07726851 656 if (column + strlen (arch->name) > 65)
c2158c24
JJ		 657 {
658 column = 0;
659 fputc ('\n', stream);
660 }
07726851 661 column += 5 + 7 + strlen (arch->name);
c2158c24
JJ		 662 fprintf (stream, "-xarch=%s", arch->name);
663 }
664 fprintf (stream, _("\n\
252b5132
RH		 665 specify variant of SPARC architecture\n\
666-bump warn when assembler switches architectures\n\
667-sparc ignored\n\
6faf3d66
JJ		 668--enforce-aligned-data force .long, etc., to be aligned correctly\n\
669-relax relax jumps and branches (default)\n\
670-no-relax avoid changing any jumps and branches\n"));
252b5132
RH		 671#ifdef OBJ_AOUT
672 fprintf (stream, _("\
673-k generate PIC\n"));
674#endif
675#ifdef OBJ_ELF
676 fprintf (stream, _("\
677-32 create 32 bit object file\n\
678-64 create 64 bit object file\n"));
679 fprintf (stream, _("\
680 [default is %d]\n"), default_arch_size);
681 fprintf (stream, _("\
682-TSO use Total Store Ordering\n\
683-PSO use Partial Store Ordering\n\
684-RMO use Relaxed Memory Ordering\n"));
685 fprintf (stream, _("\
686 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
687 fprintf (stream, _("\
688-KPIC generate PIC\n\
689-V print assembler version number\n\
a25fe906
ILT		 690-undeclared-regs ignore application global register usage without\n\
691 appropriate .register directive (default)\n\
692-no-undeclared-regs force error on application global register usage\n\
693 without appropriate .register directive\n\
252b5132
RH		 694-q ignored\n\
695-Qy, -Qn ignored\n\
696-s ignored\n"));
697#endif
698#ifdef SPARC_BIENDIAN
699 fprintf (stream, _("\
700-EL generate code for a little endian machine\n\
701-EB generate code for a big endian machine\n\
702--little-endian-data generate code for a machine having big endian\n\
c20f4f8c 703 instructions and little endian data.\n"));
252b5132
RH		 704#endif
705}
706\f
e0c6ed95 707/* Native operand size opcode translation. */
cf9a1301
RH		 708struct
709 {
710 char *name;
711 char *name32;
712 char *name64;
713 } native_op_table[] =
714{
715 {"ldn", "ld", "ldx"},
716 {"ldna", "lda", "ldxa"},
717 {"stn", "st", "stx"},
718 {"stna", "sta", "stxa"},
719 {"slln", "sll", "sllx"},
720 {"srln", "srl", "srlx"},
721 {"sran", "sra", "srax"},
722 {"casn", "cas", "casx"},
723 {"casna", "casa", "casxa"},
724 {"clrn", "clr", "clrx"},
725 {NULL, NULL, NULL},
726};
727\f
e0c6ed95 728/* sparc64 priviledged registers. */
252b5132
RH		 729
730struct priv_reg_entry
ab3e48dc
KH		 731{
732 char *name;
733 int regnum;
734};
252b5132
RH		 735
736struct priv_reg_entry priv_reg_table[] =
737{
738 {"tpc", 0},
739 {"tnpc", 1},
740 {"tstate", 2},
741 {"tt", 3},
742 {"tick", 4},
743 {"tba", 5},
744 {"pstate", 6},
745 {"tl", 7},
746 {"pil", 8},
747 {"cwp", 9},
748 {"cansave", 10},
749 {"canrestore", 11},
750 {"cleanwin", 12},
751 {"otherwin", 13},
752 {"wstate", 14},
753 {"fq", 15},
754 {"ver", 31},
e0c6ed95 755 {"", -1}, /* End marker. */
252b5132
RH		 756};
757
e0c6ed95 758/* v9a specific asrs. */
252b5132
RH		 759
760struct priv_reg_entry v9a_asr_table[] =
761{
762 {"tick_cmpr", 23},
19f7b010
JJ		 763 {"sys_tick_cmpr", 25},
764 {"sys_tick", 24},
252b5132
RH		 765 {"softint", 22},
766 {"set_softint", 20},
767 {"pic", 17},
768 {"pcr", 16},
769 {"gsr", 19},
770 {"dcr", 18},
771 {"clear_softint", 21},
e0c6ed95 772 {"", -1}, /* End marker. */
252b5132
RH		 773};
774
775static int
776cmp_reg_entry (parg, qarg)
777 const PTR parg;
778 const PTR qarg;
779{
780 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
781 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
782
783 return strcmp (q->name, p->name);
784}
785\f
786/* This function is called once, at assembler startup time. It should
e0c6ed95
AM		 787 set up all the tables, etc. that the MD part of the assembler will
788 need. */
252b5132
RH		 789
790void
791md_begin ()
792{
793 register const char *retval = NULL;
794 int lose = 0;
795 register unsigned int i = 0;
796
797 /* We don't get a chance to initialize anything before md_parse_option
798 is called, and it may not be called, so handle default initialization
799 now if not already done. */
800 if (! default_init_p)
801 init_default_arch ();
802
803 op_hash = hash_new ();
804
805 while (i < (unsigned int) sparc_num_opcodes)
806 {
807 const char *name = sparc_opcodes[i].name;
808 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
809 if (retval != NULL)
810 {
cf9a1301
RH		 811 as_bad (_("Internal error: can't hash `%s': %s\n"),
812 sparc_opcodes[i].name, retval);
252b5132
RH		 813 lose = 1;
814 }
815 do
816 {
817 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
818 {
cf9a1301
RH		 819 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
820 sparc_opcodes[i].name, sparc_opcodes[i].args);
252b5132
RH		 821 lose = 1;
822 }
823 ++i;
824 }
825 while (i < (unsigned int) sparc_num_opcodes
826 && !strcmp (sparc_opcodes[i].name, name));
827 }
828
cf9a1301
RH		 829 for (i = 0; native_op_table[i].name; i++)
830 {
831 const struct sparc_opcode *insn;
3d4ae3c0
NC		 832 char *name = ((sparc_arch_size == 32)
833 ? native_op_table[i].name32
834 : native_op_table[i].name64);
e0c6ed95 835 insn = (struct sparc_opcode *) hash_find (op_hash, name);
cf9a1301 836 if (insn == NULL)
e0c6ed95
AM		 837 {
838 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
839 name, native_op_table[i].name);
840 lose = 1;
841 }
cf9a1301
RH		 842 else
843 {
844 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
845 if (retval != NULL)
846 {
847 as_bad (_("Internal error: can't hash `%s': %s\n"),
848 sparc_opcodes[i].name, retval);
849 lose = 1;
850 }
851 }
852 }
853
252b5132
RH		 854 if (lose)
855 as_fatal (_("Broken assembler. No assembly attempted."));
856
252b5132
RH		 857 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
858 sizeof (priv_reg_table[0]), cmp_reg_entry);
859
860 /* If -bump, record the architecture level at which we start issuing
861 warnings. The behaviour is different depending upon whether an
862 architecture was explicitly specified. If it wasn't, we issue warnings
863 for all upwards bumps. If it was, we don't start issuing warnings until
864 we need to bump beyond the requested architecture or when we bump between
865 conflicting architectures. */
866
867 if (warn_on_bump
868 && architecture_requested)
869 {
870 /* `max_architecture' records the requested architecture.
871 Issue warnings if we go above it. */
872 warn_after_architecture = max_architecture;
873
874 /* Find the highest architecture level that doesn't conflict with
875 the requested one. */
876 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
877 max_architecture > warn_after_architecture;
878 --max_architecture)
879 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
880 warn_after_architecture))
881 break;
882 }
883}
884
885/* Called after all assembly has been done. */
886
887void
888sparc_md_end ()
889{
19f7b010
JJ		 890 unsigned long mach = bfd_mach_sparc;
891
252b5132 892 if (sparc_arch_size == 64)
19f7b010
JJ		 893 switch (current_architecture)
894 {
895 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
896 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
897 default: mach = bfd_mach_sparc_v9; break;
898 }
252b5132 899 else
19f7b010
JJ		 900 switch (current_architecture)
901 {
902 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
903 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
904 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
905 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
906 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
907 be but for now it is (since that's the way it's always been
908 treated). */
909 default: break;
910 }
911 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
252b5132
RH		 912}
913\f
914/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
915
916static INLINE int
917in_signed_range (val, max)
918 bfd_signed_vma val, max;
919{
920 if (max <= 0)
921 abort ();
922 /* Sign-extend the value from the architecture word size, so that
923 0xffffffff is always considered -1 on sparc32. */
924 if (sparc_arch_size == 32)
925 {
e0c6ed95 926 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
6c1b24e4 927 val = ((val & U0xffffffff) ^ sign) - sign;
252b5132
RH		 928 }
929 if (val > max)
930 return 0;
931 if (val < ~max)
932 return 0;
933 return 1;
934}
935
936/* Return non-zero if VAL is in the range 0 to MAX. */
937
938static INLINE int
939in_unsigned_range (val, max)
940 bfd_vma val, max;
941{
942 if (val > max)
943 return 0;
944 return 1;
945}
946
947/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
948 (e.g. -15 to +31). */
949
950static INLINE int
951in_bitfield_range (val, max)
952 bfd_signed_vma val, max;
953{
954 if (max <= 0)
955 abort ();
956 if (val > max)
957 return 0;
958 if (val < ~(max >> 1))
959 return 0;
960 return 1;
961}
962
963static int
964sparc_ffs (mask)
965 unsigned int mask;
966{
967 int i;
968
969 if (mask == 0)
970 return -1;
971
972 for (i = 0; (mask & 1) == 0; ++i)
973 mask >>= 1;
974 return i;
975}
976
977/* Implement big shift right. */
978static bfd_vma
979BSR (val, amount)
980 bfd_vma val;
981 int amount;
982{
983 if (sizeof (bfd_vma) <= 4 && amount >= 32)
984 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
985 return val >> amount;
986}
987\f
988/* For communication between sparc_ip and get_expression. */
989static char *expr_end;
990
252b5132
RH		 991/* Values for `special_case'.
992 Instructions that require wierd handling because they're longer than
993 4 bytes. */
994#define SPECIAL_CASE_NONE 0
995#define SPECIAL_CASE_SET 1
996#define SPECIAL_CASE_SETSW 2
997#define SPECIAL_CASE_SETX 3
998/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
999#define SPECIAL_CASE_FDIV 4
1000
1001/* Bit masks of various insns. */
1002#define NOP_INSN 0x01000000
1003#define OR_INSN 0x80100000
63fab58c 1004#define XOR_INSN 0x80180000
252b5132
RH		 1005#define FMOVS_INSN 0x81A00020
1006#define SETHI_INSN 0x01000000
1007#define SLLX_INSN 0x81281000
1008#define SRA_INSN 0x81380000
1009
1010/* The last instruction to be assembled. */
1011static const struct sparc_opcode *last_insn;
1012/* The assembled opcode of `last_insn'. */
1013static unsigned long last_opcode;
1014\f
a22b281c 1015/* Handle the set and setuw synthetic instructions. */
e0c6ed95 1016
a22b281c
RH		 1017static void
1018synthetize_setuw (insn)
1019 const struct sparc_opcode *insn;
1020{
1021 int need_hi22_p = 0;
1022 int rd = (the_insn.opcode & RD (~0)) >> 25;
1023
1024 if (the_insn.exp.X_op == O_constant)
1025 {
1026 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1027 {
e0c6ed95 1028 if (sizeof (offsetT) > 4
a22b281c 1029 && (the_insn.exp.X_add_number < 0
6c1b24e4 1030 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
a22b281c
RH		 1031 as_warn (_("set: number not in 0..4294967295 range"));
1032 }
1033 else
1034 {
e0c6ed95 1035 if (sizeof (offsetT) > 4
6c1b24e4
AO		 1036 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1037 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
a22b281c 1038 as_warn (_("set: number not in -2147483648..4294967295 range"));
e0c6ed95 1039 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
a22b281c
RH		 1040 }
1041 }
1042
1043 /* See if operand is absolute and small; skip sethi if so. */
1044 if (the_insn.exp.X_op != O_constant
1045 || the_insn.exp.X_add_number >= (1 << 12)
1046 || the_insn.exp.X_add_number < -(1 << 12))
1047 {
1048 the_insn.opcode = (SETHI_INSN | RD (rd)
1049 | ((the_insn.exp.X_add_number >> 10)
ab3e48dc
KH		 1050 & (the_insn.exp.X_op == O_constant
1051 ? 0x3fffff : 0)));
a22b281c 1052 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1053 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
a22b281c
RH		 1054 output_insn (insn, &the_insn);
1055 need_hi22_p = 1;
1056 }
1057
1058 /* See if operand has no low-order bits; skip OR if so. */
1059 if (the_insn.exp.X_op != O_constant
1060 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1061 || ! need_hi22_p)
1062 {
1063 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1064 | RD (rd) | IMMED
1065 | (the_insn.exp.X_add_number
ab3e48dc
KH		 1066 & (the_insn.exp.X_op != O_constant
1067 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
a22b281c 1068 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1069 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
a22b281c
RH		 1070 output_insn (insn, &the_insn);
1071 }
1072}
e0c6ed95 1073
a22b281c 1074/* Handle the setsw synthetic instruction. */
e0c6ed95 1075
a22b281c
RH		 1076static void
1077synthetize_setsw (insn)
1078 const struct sparc_opcode *insn;
1079{
1080 int low32, rd, opc;
1081
1082 rd = (the_insn.opcode & RD (~0)) >> 25;
1083
1084 if (the_insn.exp.X_op != O_constant)
1085 {
1086 synthetize_setuw (insn);
1087
1088 /* Need to sign extend it. */
1089 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1090 the_insn.reloc = BFD_RELOC_NONE;
1091 output_insn (insn, &the_insn);
1092 return;
1093 }
1094
e0c6ed95 1095 if (sizeof (offsetT) > 4
6c1b24e4
AO		 1096 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1097 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
a22b281c
RH		 1098 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1099
e0c6ed95
AM		 1100 low32 = the_insn.exp.X_add_number;
1101
a22b281c
RH		 1102 if (low32 >= 0)
1103 {
1104 synthetize_setuw (insn);
1105 return;
1106 }
1107
1108 opc = OR_INSN;
e0c6ed95 1109
a22b281c
RH		 1110 the_insn.reloc = BFD_RELOC_NONE;
1111 /* See if operand is absolute and small; skip sethi if so. */
1112 if (low32 < -(1 << 12))
1113 {
1114 the_insn.opcode = (SETHI_INSN | RD (rd)
1115 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1116 output_insn (insn, &the_insn);
1117 low32 = 0x1c00 | (low32 & 0x3ff);
1118 opc = RS1 (rd) | XOR_INSN;
1119 }
1120
1121 the_insn.opcode = (opc | RD (rd) | IMMED
1122 | (low32 & 0x1fff));
1123 output_insn (insn, &the_insn);
1124}
1125
1126/* Handle the setsw synthetic instruction. */
e0c6ed95 1127
a22b281c
RH		 1128static void
1129synthetize_setx (insn)
1130 const struct sparc_opcode *insn;
1131{
1132 int upper32, lower32;
1133 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1134 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1135 int upper_dstreg;
1136 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1137 int need_xor10_p = 0;
e0c6ed95 1138
6c1b24e4 1139#define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
a22b281c
RH		 1140 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1141 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1142#undef SIGNEXT32
1143
1144 upper_dstreg = tmpreg;
1145 /* The tmp reg should not be the dst reg. */
1146 if (tmpreg == dstreg)
1147 as_warn (_("setx: temporary register same as destination register"));
1148
1149 /* ??? Obviously there are other optimizations we can do
1150 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1151 doing some of these. Later. If you do change things, try to
1152 change all of this to be table driven as well. */
1153 /* What to output depends on the number if it's constant.
1154 Compute that first, then output what we've decided upon. */
1155 if (the_insn.exp.X_op != O_constant)
1156 {
1157 if (sparc_arch_size == 32)
1158 {
1159 /* When arch size is 32, we want setx to be equivalent
1160 to setuw for anything but constants. */
1161 the_insn.exp.X_add_number &= 0xffffffff;
1162 synthetize_setuw (insn);
1163 return;
1164 }
1165 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
ab3e48dc
KH		 1166 lower32 = 0;
1167 upper32 = 0;
a22b281c
RH		 1168 }
1169 else
1170 {
1171 /* Reset X_add_number, we've extracted it as upper32/lower32.
1172 Otherwise fixup_segment will complain about not being able to
1173 write an 8 byte number in a 4 byte field. */
1174 the_insn.exp.X_add_number = 0;
e0c6ed95 1175
a22b281c
RH		 1176 /* Only need hh22 if `or' insn can't handle constant. */
1177 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1178 need_hh22_p = 1;
e0c6ed95 1179
a22b281c
RH		 1180 /* Does bottom part (after sethi) have bits? */
1181 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1182 /* No hh22, but does upper32 still have bits we can't set
1183 from lower32? */
1184 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1185 need_hm10_p = 1;
e0c6ed95 1186
a22b281c
RH		 1187 /* If the lower half is all zero, we build the upper half directly
1188 into the dst reg. */
1189 if (lower32 != 0
1190 /* Need lower half if number is zero or 0xffffffff00000000. */
1191 || (! need_hh22_p && ! need_hm10_p))
1192 {
1193 /* No need for sethi if `or' insn can handle constant. */
1194 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1195 /* Note that we can't use a negative constant in the `or'
1196 insn unless the upper 32 bits are all ones. */
1197 || (lower32 < 0 && upper32 != -1)
1198 || (lower32 >= 0 && upper32 == -1))
1199 need_hi22_p = 1;
e0c6ed95 1200
a22b281c
RH		 1201 if (need_hi22_p && upper32 == -1)
1202 need_xor10_p = 1;
1203
1204 /* Does bottom part (after sethi) have bits? */
1205 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1206 /* No sethi. */
1207 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1208 /* Need `or' if we didn't set anything else. */
1209 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1210 need_lo10_p = 1;
1211 }
1212 else
1213 /* Output directly to dst reg if lower 32 bits are all zero. */
1214 upper_dstreg = dstreg;
1215 }
e0c6ed95 1216
a22b281c
RH		 1217 if (!upper_dstreg && dstreg)
1218 as_warn (_("setx: illegal temporary register g0"));
1219
1220 if (need_hh22_p)
1221 {
1222 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1223 | ((upper32 >> 10) & 0x3fffff));
1224 the_insn.reloc = (the_insn.exp.X_op != O_constant
1225 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1226 output_insn (insn, &the_insn);
1227 }
e0c6ed95 1228
a22b281c
RH		 1229 if (need_hi22_p)
1230 {
1231 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1232 | (((need_xor10_p ? ~lower32 : lower32)
ab3e48dc 1233 >> 10) & 0x3fffff));
a22b281c
RH		 1234 the_insn.reloc = (the_insn.exp.X_op != O_constant
1235 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1236 output_insn (insn, &the_insn);
1237 }
1238
1239 if (need_hm10_p)
1240 {
1241 the_insn.opcode = (OR_INSN
1242 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1243 | RD (upper_dstreg)
1244 | IMMED
1245 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1246 the_insn.reloc = (the_insn.exp.X_op != O_constant
1247 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1248 output_insn (insn, &the_insn);
1249 }
e0c6ed95 1250
a22b281c
RH		 1251 if (need_lo10_p)
1252 {
1253 /* FIXME: One nice optimization to do here is to OR the low part
1254 with the highpart if hi22 isn't needed and the low part is
1255 positive. */
1256 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1257 | RD (dstreg)
1258 | IMMED
1259 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1260 the_insn.reloc = (the_insn.exp.X_op != O_constant
1261 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1262 output_insn (insn, &the_insn);
1263 }
e0c6ed95 1264
a22b281c
RH		 1265 /* If we needed to build the upper part, shift it into place. */
1266 if (need_hh22_p || need_hm10_p)
1267 {
1268 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1269 | IMMED | 32);
1270 the_insn.reloc = BFD_RELOC_NONE;
1271 output_insn (insn, &the_insn);
1272 }
e0c6ed95 1273
a22b281c
RH		 1274 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1275 if (need_xor10_p)
1276 {
1277 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1278 | 0x1c00 | (lower32 & 0x3ff));
1279 the_insn.reloc = BFD_RELOC_NONE;
1280 output_insn (insn, &the_insn);
1281 }
1282
1283 /* If we needed to build both upper and lower parts, OR them together. */
1284 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1285 {
1286 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1287 | RD (dstreg));
1288 the_insn.reloc = BFD_RELOC_NONE;
1289 output_insn (insn, &the_insn);
1290 }
1291}
1292\f
252b5132
RH		 1293/* Main entry point to assemble one instruction. */
1294
1295void
1296md_assemble (str)
1297 char *str;
1298{
1299 const struct sparc_opcode *insn;
a22b281c 1300 int special_case;
252b5132
RH		 1301
1302 know (str);
a22b281c 1303 special_case = sparc_ip (str, &insn);
252b5132
RH		 1304
1305 /* We warn about attempts to put a floating point branch in a delay slot,
1306 unless the delay slot has been annulled. */
1307 if (insn != NULL
1308 && last_insn != NULL
1309 && (insn->flags & F_FBR) != 0
1310 && (last_insn->flags & F_DELAYED) != 0
1311 /* ??? This test isn't completely accurate. We assume anything with
1312 F_{UNBR,CONDBR,FBR} set is annullable. */
1313 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1314 || (last_opcode & ANNUL) == 0))
1315 as_warn (_("FP branch in delay slot"));
1316
1317 /* SPARC before v9 requires a nop instruction between a floating
1318 point instruction and a floating point branch. We insert one
1319 automatically, with a warning. */
1320 if (max_architecture < SPARC_OPCODE_ARCH_V9
1321 && insn != NULL
1322 && last_insn != NULL
1323 && (insn->flags & F_FBR) != 0
1324 && (last_insn->flags & F_FLOAT) != 0)
1325 {
1326 struct sparc_it nop_insn;
1327
1328 nop_insn.opcode = NOP_INSN;
1329 nop_insn.reloc = BFD_RELOC_NONE;
1330 output_insn (insn, &nop_insn);
1331 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1332 }
1333
a22b281c
RH		 1334 switch (special_case)
1335 {
1336 case SPECIAL_CASE_NONE:
e0c6ed95 1337 /* Normal insn. */
a22b281c
RH		 1338 output_insn (insn, &the_insn);
1339 break;
252b5132 1340
a22b281c
RH		 1341 case SPECIAL_CASE_SETSW:
1342 synthetize_setsw (insn);
1343 break;
e0c6ed95 1344
a22b281c
RH		 1345 case SPECIAL_CASE_SET:
1346 synthetize_setuw (insn);
1347 break;
252b5132 1348
a22b281c
RH		 1349 case SPECIAL_CASE_SETX:
1350 synthetize_setx (insn);
1351 break;
e0c6ed95 1352
a22b281c
RH		 1353 case SPECIAL_CASE_FDIV:
1354 {
1355 int rd = (the_insn.opcode >> 25) & 0x1f;
e0c6ed95 1356
a22b281c 1357 output_insn (insn, &the_insn);
e0c6ed95 1358
a22b281c
RH		 1359 /* According to information leaked from Sun, the "fdiv" instructions
1360 on early SPARC machines would produce incorrect results sometimes.
1361 The workaround is to add an fmovs of the destination register to
1362 itself just after the instruction. This was true on machines
e0c6ed95 1363 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
a22b281c
RH		 1364 assert (the_insn.reloc == BFD_RELOC_NONE);
1365 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1366 output_insn (insn, &the_insn);
1367 return;
1368 }
e0c6ed95 1369
a22b281c
RH		 1370 default:
1371 as_fatal (_("failed special case insn sanity check"));
252b5132
RH		 1372 }
1373}
1374
1375/* Subroutine of md_assemble to do the actual parsing. */
1376
a22b281c 1377static int
252b5132
RH		 1378sparc_ip (str, pinsn)
1379 char *str;
1380 const struct sparc_opcode **pinsn;
1381{
1382 char *error_message = "";
1383 char *s;
1384 const char *args;
1385 char c;
1386 const struct sparc_opcode *insn;
1387 char *argsStart;
1388 unsigned long opcode;
1389 unsigned int mask = 0;
1390 int match = 0;
1391 int comma = 0;
1392 int v9_arg_p;
a22b281c 1393 int special_case = SPECIAL_CASE_NONE;
252b5132
RH		 1394
1395 s = str;
3882b010 1396 if (ISLOWER (*s))
252b5132
RH		 1397 {
1398 do
1399 ++s;
3882b010 1400 while (ISLOWER (*s) || ISDIGIT (*s));
252b5132
RH		 1401 }
1402
1403 switch (*s)
1404 {
1405 case '\0':
1406 break;
1407
1408 case ',':
1409 comma = 1;
e0c6ed95 1410 /* Fall through. */
252b5132
RH		 1411
1412 case ' ':
1413 *s++ = '\0';
1414 break;
1415
1416 default:
1417 as_fatal (_("Unknown opcode: `%s'"), str);
1418 }
1419 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1420 *pinsn = insn;
1421 if (insn == NULL)
1422 {
1423 as_bad (_("Unknown opcode: `%s'"), str);
a22b281c 1424 return special_case;
252b5132
RH		 1425 }
1426 if (comma)
1427 {
1428 *--s = ',';
1429 }
1430
1431 argsStart = s;
1432 for (;;)
1433 {
1434 opcode = insn->match;
1435 memset (&the_insn, '\0', sizeof (the_insn));
1436 the_insn.reloc = BFD_RELOC_NONE;
1437 v9_arg_p = 0;
1438
e0c6ed95
AM		 1439 /* Build the opcode, checking as we go to make sure that the
1440 operands match. */
252b5132
RH		 1441 for (args = insn->args;; ++args)
1442 {
1443 switch (*args)
1444 {
1445 case 'K':
1446 {
1447 int kmask = 0;
1448
1449 /* Parse a series of masks. */
1450 if (*s == '#')
1451 {
1452 while (*s == '#')
1453 {
1454 int mask;
1455
1456 if (! parse_keyword_arg (sparc_encode_membar, &s,
1457 &mask))
1458 {
1459 error_message = _(": invalid membar mask name");
1460 goto error;
1461 }
1462 kmask |= mask;
47926f60
KH		 1463 while (*s == ' ')
1464 ++s;
252b5132
RH		 1465 if (*s == '|' || *s == '+')
1466 ++s;
47926f60
KH		 1467 while (*s == ' ')
1468 ++s;
252b5132
RH		 1469 }
1470 }
1471 else
1472 {
1473 if (! parse_const_expr_arg (&s, &kmask))
1474 {
1475 error_message = _(": invalid membar mask expression");
1476 goto error;
1477 }
1478 if (kmask < 0 || kmask > 127)
1479 {
1480 error_message = _(": invalid membar mask number");
1481 goto error;
1482 }
1483 }
1484
1485 opcode |= MEMBAR (kmask);
1486 continue;
1487 }
1488
19f7b010
JJ		 1489 case '3':
1490 {
1491 int smask = 0;
1492
1493 if (! parse_const_expr_arg (&s, &smask))
1494 {
1495 error_message = _(": invalid siam mode expression");
1496 goto error;
1497 }
1498 if (smask < 0 || smask > 7)
1499 {
1500 error_message = _(": invalid siam mode number");
1501 goto error;
1502 }
1503 opcode |= smask;
1504 continue;
1505 }
1506
252b5132
RH		 1507 case '*':
1508 {
1509 int fcn = 0;
1510
1511 /* Parse a prefetch function. */
1512 if (*s == '#')
1513 {
1514 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1515 {
1516 error_message = _(": invalid prefetch function name");
1517 goto error;
1518 }
1519 }
1520 else
1521 {
1522 if (! parse_const_expr_arg (&s, &fcn))
1523 {
1524 error_message = _(": invalid prefetch function expression");
1525 goto error;
1526 }
1527 if (fcn < 0 || fcn > 31)
1528 {
1529 error_message = _(": invalid prefetch function number");
1530 goto error;
1531 }
1532 }
1533 opcode |= RD (fcn);
1534 continue;
1535 }
1536
1537 case '!':
1538 case '?':
1539 /* Parse a sparc64 privileged register. */
1540 if (*s == '%')
1541 {
1542 struct priv_reg_entry *p = priv_reg_table;
e0c6ed95 1543 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1544
1545 s += 1;
1546 while (p->name[0] > s[0])
1547 p++;
1548 while (p->name[0] == s[0])
1549 {
1550 len = strlen (p->name);
1551 if (strncmp (p->name, s, len) == 0)
1552 break;
1553 p++;
1554 }
1555 if (p->name[0] != s[0])
1556 {
1557 error_message = _(": unrecognizable privileged register");
1558 goto error;
1559 }
1560 if (*args == '?')
1561 opcode |= (p->regnum << 14);
1562 else
1563 opcode |= (p->regnum << 25);
1564 s += len;
1565 continue;
1566 }
1567 else
1568 {
1569 error_message = _(": unrecognizable privileged register");
1570 goto error;
1571 }
1572
1573 case '_':
1574 case '/':
19f7b010 1575 /* Parse a v9a/v9b ancillary state register. */
252b5132
RH		 1576 if (*s == '%')
1577 {
1578 struct priv_reg_entry *p = v9a_asr_table;
e0c6ed95 1579 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1580
1581 s += 1;
1582 while (p->name[0] > s[0])
1583 p++;
1584 while (p->name[0] == s[0])
1585 {
1586 len = strlen (p->name);
1587 if (strncmp (p->name, s, len) == 0)
1588 break;
1589 p++;
1590 }
1591 if (p->name[0] != s[0])
1592 {
19f7b010 1593 error_message = _(": unrecognizable v9a or v9b ancillary state register");
252b5132
RH		 1594 goto error;
1595 }
1596 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1597 {
1598 error_message = _(": rd on write only ancillary state register");
1599 goto error;
e0c6ed95 1600 }
19f7b010
JJ		 1601 if (p->regnum >= 24
1602 && (insn->architecture
1603 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1604 {
1605 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1606 error_message = _(": unrecognizable v9a ancillary state register");
1607 goto error;
1608 }
252b5132
RH		 1609 if (*args == '/')
1610 opcode |= (p->regnum << 14);
1611 else
1612 opcode |= (p->regnum << 25);
1613 s += len;
1614 continue;
1615 }
1616 else
1617 {
19f7b010 1618 error_message = _(": unrecognizable v9a or v9b ancillary state register");
252b5132
RH		 1619 goto error;
1620 }
1621
1622 case 'M':
1623 case 'm':
1624 if (strncmp (s, "%asr", 4) == 0)
1625 {
1626 s += 4;
1627
3882b010 1628 if (ISDIGIT (*s))
252b5132
RH		 1629 {
1630 long num = 0;
1631
3882b010 1632 while (ISDIGIT (*s))
252b5132
RH		 1633 {
1634 num = num * 10 + *s - '0';
1635 ++s;
1636 }
1637
1638 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1639 {
1640 if (num < 16 || 31 < num)
1641 {
1642 error_message = _(": asr number must be between 16 and 31");
1643 goto error;
1644 }
1645 }
1646 else
1647 {
1648 if (num < 0 || 31 < num)
1649 {
1650 error_message = _(": asr number must be between 0 and 31");
1651 goto error;
1652 }
1653 }
1654
1655 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1656 continue;
1657 }
1658 else
1659 {
1660 error_message = _(": expecting %asrN");
1661 goto error;
1662 }
e0c6ed95 1663 } /* if %asr */
252b5132
RH		 1664 break;
1665
1666 case 'I':
1667 the_insn.reloc = BFD_RELOC_SPARC_11;
1668 goto immediate;
1669
1670 case 'j':
1671 the_insn.reloc = BFD_RELOC_SPARC_10;
1672 goto immediate;
1673
1674 case 'X':
1675 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1676 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1677 the_insn.reloc = BFD_RELOC_SPARC_5;
1678 else
1679 the_insn.reloc = BFD_RELOC_SPARC13;
1680 /* These fields are unsigned, but for upward compatibility,
1681 allow negative values as well. */
1682 goto immediate;
1683
1684 case 'Y':
1685 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1686 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1687 the_insn.reloc = BFD_RELOC_SPARC_6;
1688 else
1689 the_insn.reloc = BFD_RELOC_SPARC13;
1690 /* These fields are unsigned, but for upward compatibility,
1691 allow negative values as well. */
1692 goto immediate;
1693
1694 case 'k':
1695 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1696 the_insn.pcrel = 1;
1697 goto immediate;
1698
1699 case 'G':
1700 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1701 the_insn.pcrel = 1;
1702 goto immediate;
1703
1704 case 'N':
1705 if (*s == 'p' && s[1] == 'n')
1706 {
1707 s += 2;
1708 continue;
1709 }
1710 break;
1711
1712 case 'T':
1713 if (*s == 'p' && s[1] == 't')
1714 {
1715 s += 2;
1716 continue;
1717 }
1718 break;
1719
1720 case 'z':
1721 if (*s == ' ')
1722 {
1723 ++s;
1724 }
1725 if (strncmp (s, "%icc", 4) == 0)
1726 {
1727 s += 4;
1728 continue;
1729 }
1730 break;
1731
1732 case 'Z':
1733 if (*s == ' ')
1734 {
1735 ++s;
1736 }
1737 if (strncmp (s, "%xcc", 4) == 0)
1738 {
1739 s += 4;
1740 continue;
1741 }
1742 break;
1743
1744 case '6':
1745 if (*s == ' ')
1746 {
1747 ++s;
1748 }
1749 if (strncmp (s, "%fcc0", 5) == 0)
1750 {
1751 s += 5;
1752 continue;
1753 }
1754 break;
1755
1756 case '7':
1757 if (*s == ' ')
1758 {
1759 ++s;
1760 }
1761 if (strncmp (s, "%fcc1", 5) == 0)
1762 {
1763 s += 5;
1764 continue;
1765 }
1766 break;
1767
1768 case '8':
1769 if (*s == ' ')
1770 {
1771 ++s;
1772 }
1773 if (strncmp (s, "%fcc2", 5) == 0)
1774 {
1775 s += 5;
1776 continue;
1777 }
1778 break;
1779
1780 case '9':
1781 if (*s == ' ')
1782 {
1783 ++s;
1784 }
1785 if (strncmp (s, "%fcc3", 5) == 0)
1786 {
1787 s += 5;
1788 continue;
1789 }
1790 break;
1791
1792 case 'P':
1793 if (strncmp (s, "%pc", 3) == 0)
1794 {
1795 s += 3;
1796 continue;
1797 }
1798 break;
1799
1800 case 'W':
1801 if (strncmp (s, "%tick", 5) == 0)
1802 {
1803 s += 5;
1804 continue;
1805 }
1806 break;
1807
e0c6ed95 1808 case '\0': /* End of args. */
252b5132
RH		 1809 if (*s == '\0')
1810 {
1811 match = 1;
1812 }
1813 break;
1814
1815 case '+':
1816 if (*s == '+')
1817 {
1818 ++s;
1819 continue;
1820 }
1821 if (*s == '-')
1822 {
1823 continue;
1824 }
1825 break;
1826
e0c6ed95 1827 case '[': /* These must match exactly. */
252b5132
RH		 1828 case ']':
1829 case ',':
1830 case ' ':
1831 if (*s++ == *args)
1832 continue;
1833 break;
1834
e0c6ed95 1835 case '#': /* Must be at least one digit. */
3882b010 1836 if (ISDIGIT (*s++))
252b5132 1837 {
3882b010 1838 while (ISDIGIT (*s))
252b5132
RH		 1839 {
1840 ++s;
1841 }
1842 continue;
1843 }
1844 break;
1845
e0c6ed95 1846 case 'C': /* Coprocessor state register. */
252b5132
RH		 1847 if (strncmp (s, "%csr", 4) == 0)
1848 {
1849 s += 4;
1850 continue;
1851 }
1852 break;
1853
e0c6ed95 1854 case 'b': /* Next operand is a coprocessor register. */
252b5132
RH		 1855 case 'c':
1856 case 'D':
3882b010 1857 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
252b5132
RH		 1858 {
1859 mask = *s++;
3882b010 1860 if (ISDIGIT (*s))
252b5132
RH		 1861 {
1862 mask = 10 * (mask - '0') + (*s++ - '0');
1863 if (mask >= 32)
1864 {
1865 break;
1866 }
1867 }
1868 else
1869 {
1870 mask -= '0';
1871 }
1872 switch (*args)
1873 {
1874
1875 case 'b':
1876 opcode |= mask << 14;
1877 continue;
1878
1879 case 'c':
1880 opcode |= mask;
1881 continue;
1882
1883 case 'D':
1884 opcode |= mask << 25;
1885 continue;
1886 }
1887 }
1888 break;
1889
1890 case 'r': /* next operand must be a register */
1891 case 'O':
1892 case '1':
1893 case '2':
1894 case 'd':
1895 if (*s++ == '%')
1896 {
1897 switch (c = *s++)
1898 {
1899
1900 case 'f': /* frame pointer */
1901 if (*s++ == 'p')
1902 {
1903 mask = 0x1e;
1904 break;
1905 }
1906 goto error;
1907
1908 case 'g': /* global register */
a22b281c
RH		 1909 c = *s++;
1910 if (isoctal (c))
252b5132
RH		 1911 {
1912 mask = c - '0';
1913 break;
1914 }
1915 goto error;
1916
1917 case 'i': /* in register */
a22b281c
RH		 1918 c = *s++;
1919 if (isoctal (c))
252b5132
RH		 1920 {
1921 mask = c - '0' + 24;
1922 break;
1923 }
1924 goto error;
1925
1926 case 'l': /* local register */
a22b281c
RH		 1927 c = *s++;
1928 if (isoctal (c))
252b5132
RH		 1929 {
1930 mask = (c - '0' + 16);
1931 break;
1932 }
1933 goto error;
1934
1935 case 'o': /* out register */
a22b281c
RH		 1936 c = *s++;
1937 if (isoctal (c))
252b5132
RH		 1938 {
1939 mask = (c - '0' + 8);
1940 break;
1941 }
1942 goto error;
1943
1944 case 's': /* stack pointer */
1945 if (*s++ == 'p')
1946 {
1947 mask = 0xe;
1948 break;
1949 }
1950 goto error;
1951
1952 case 'r': /* any register */
3882b010 1953 if (!ISDIGIT ((c = *s++)))
252b5132
RH		 1954 {
1955 goto error;
1956 }
1957 /* FALLTHROUGH */
1958 case '0':
1959 case '1':
1960 case '2':
1961 case '3':
1962 case '4':
1963 case '5':
1964 case '6':
1965 case '7':
1966 case '8':
1967 case '9':
3882b010 1968 if (ISDIGIT (*s))
252b5132
RH		 1969 {
1970 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1971 {
1972 goto error;
1973 }
1974 }
1975 else
1976 {
1977 c -= '0';
1978 }
1979 mask = c;
1980 break;
1981
1982 default:
1983 goto error;
1984 }
1985
6d8809aa 1986 if ((mask & ~1) == 2 && sparc_arch_size == 64
e0c6ed95 1987 && no_undeclared_regs && ! globals[mask])
79bd78be 1988 as_bad (_("detected global register use not covered by .register pseudo-op"));
6d8809aa 1989
252b5132
RH		 1990 /* Got the register, now figure out where
1991 it goes in the opcode. */
1992 switch (*args)
1993 {
1994 case '1':
1995 opcode |= mask << 14;
1996 continue;
1997
1998 case '2':
1999 opcode |= mask;
2000 continue;
2001
2002 case 'd':
2003 opcode |= mask << 25;
2004 continue;
2005
2006 case 'r':
2007 opcode |= (mask << 25) | (mask << 14);
2008 continue;
2009
2010 case 'O':
2011 opcode |= (mask << 25) | (mask << 0);
2012 continue;
2013 }
2014 }
2015 break;
2016
2017 case 'e': /* next operand is a floating point register */
2018 case 'v':
2019 case 'V':
2020
2021 case 'f':
2022 case 'B':
2023 case 'R':
2024
2025 case 'g':
2026 case 'H':
2027 case 'J':
2028 {
2029 char format;
2030
2031 if (*s++ == '%'
2032 && ((format = *s) == 'f')
3882b010 2033 && ISDIGIT (*++s))
252b5132 2034 {
3882b010 2035 for (mask = 0; ISDIGIT (*s); ++s)
252b5132
RH		 2036 {
2037 mask = 10 * mask + (*s - '0');
2038 } /* read the number */
2039
2040 if ((*args == 'v'
2041 || *args == 'B'
2042 || *args == 'H')
2043 && (mask & 1))
2044 {
2045 break;
2046 } /* register must be even numbered */
2047
2048 if ((*args == 'V'
2049 || *args == 'R'
2050 || *args == 'J')
2051 && (mask & 3))
2052 {
2053 break;
2054 } /* register must be multiple of 4 */
2055
2056 if (mask >= 64)
2057 {
2058 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2059 error_message = _(": There are only 64 f registers; [0-63]");
2060 else
2061 error_message = _(": There are only 32 f registers; [0-31]");
2062 goto error;
2063 } /* on error */
2064 else if (mask >= 32)
2065 {
2066 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2067 {
2068 v9_arg_p = 1;
2069 mask -= 31; /* wrap high bit */
2070 }
2071 else
2072 {
2073 error_message = _(": There are only 32 f registers; [0-31]");
2074 goto error;
2075 }
2076 }
2077 }
2078 else
2079 {
2080 break;
ab3e48dc 2081 } /* if not an 'f' register. */
252b5132
RH		 2082
2083 switch (*args)
2084 {
2085 case 'v':
2086 case 'V':
2087 case 'e':
2088 opcode |= RS1 (mask);
2089 continue;
2090
252b5132
RH		 2091 case 'f':
2092 case 'B':
2093 case 'R':
2094 opcode |= RS2 (mask);
2095 continue;
2096
2097 case 'g':
2098 case 'H':
2099 case 'J':
2100 opcode |= RD (mask);
2101 continue;
ab3e48dc 2102 } /* Pack it in. */
252b5132
RH		 2103
2104 know (0);
2105 break;
ab3e48dc 2106 } /* float arg */
252b5132
RH		 2107
2108 case 'F':
2109 if (strncmp (s, "%fsr", 4) == 0)
2110 {
2111 s += 4;
2112 continue;
2113 }
2114 break;
2115
ab3e48dc
KH		 2116 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2117 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
252b5132
RH		 2118 goto immediate;
2119
ab3e48dc 2120 case 'l': /* 22 bit PC relative immediate */
252b5132
RH		 2121 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2122 the_insn.pcrel = 1;
2123 goto immediate;
2124
ab3e48dc 2125 case 'L': /* 30 bit immediate */
252b5132
RH		 2126 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2127 the_insn.pcrel = 1;
2128 goto immediate;
2129
63fab58c 2130 case 'h':
ab3e48dc 2131 case 'n': /* 22 bit immediate */
252b5132
RH		 2132 the_insn.reloc = BFD_RELOC_SPARC22;
2133 goto immediate;
2134
ab3e48dc 2135 case 'i': /* 13 bit immediate */
252b5132
RH		 2136 the_insn.reloc = BFD_RELOC_SPARC13;
2137
2138 /* fallthrough */
2139
2140 immediate:
2141 if (*s == ' ')
2142 s++;
2143
cf9a1301
RH		 2144 {
2145 char *s1;
2146 char *op_arg = NULL;
2147 expressionS op_exp;
2148 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2149
2150 /* Check for %hi, etc. */
2151 if (*s == '%')
2152 {
2153 static const struct ops {
2154 /* The name as it appears in assembler. */
2155 char *name;
2156 /* strlen (name), precomputed for speed */
2157 int len;
2158 /* The reloc this pseudo-op translates to. */
2159 int reloc;
2160 /* Non-zero if for v9 only. */
2161 int v9_p;
2162 /* Non-zero if can be used in pc-relative contexts. */
2163 int pcrel_p;/*FIXME:wip*/
2164 } ops[] = {
2165 /* hix/lox must appear before hi/lo so %hix won't be
2166 mistaken for %hi. */
2167 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2168 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2169 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2170 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2171 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2172 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2173 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2174 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2175 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2176 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2177 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2178 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
c2158c24 2179 { NULL, 0, 0, 0, 0 }
cf9a1301
RH		 2180 };
2181 const struct ops *o;
e0c6ed95 2182
cf9a1301
RH		 2183 for (o = ops; o->name; o++)
2184 if (strncmp (s + 1, o->name, o->len) == 0)
2185 break;
2186 if (o->name == NULL)
252b5132 2187 break;
e0c6ed95 2188
cf9a1301
RH		 2189 if (s[o->len + 1] != '(')
2190 {
2191 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
a22b281c 2192 return special_case;
cf9a1301 2193 }
252b5132 2194
cf9a1301
RH		 2195 op_arg = o->name;
2196 the_insn.reloc = o->reloc;
2197 s += o->len + 2;
2198 v9_arg_p = o->v9_p;
2199 }
2200
2201 /* Note that if the get_expression() fails, we will still
2202 have created U entries in the symbol table for the
2203 'symbols' in the input string. Try not to create U
2204 symbols for registers, etc. */
252b5132 2205
252b5132
RH		 2206 /* This stuff checks to see if the expression ends in
2207 +%reg. If it does, it removes the register from
2208 the expression, and re-sets 's' to point to the
2209 right place. */
2210
cf9a1301
RH		 2211 if (op_arg)
2212 {
2213 int npar = 0;
2214
2215 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2216 if (*s1 == '(')
2217 npar++;
2218 else if (*s1 == ')')
2219 {
2220 if (!npar)
2221 break;
2222 npar--;
2223 }
2224
2225 if (*s1 != ')')
2226 {
2227 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
a22b281c 2228 return special_case;
cf9a1301 2229 }
e0c6ed95 2230
cf9a1301
RH		 2231 *s1 = '\0';
2232 (void) get_expression (s);
2233 *s1 = ')';
2234 s = s1 + 1;
2235 if (*s == ',' || *s == ']' || !*s)
2236 continue;
2237 if (*s != '+' && *s != '-')
2238 {
2239 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
a22b281c 2240 return special_case;
cf9a1301
RH		 2241 }
2242 *s1 = '0';
2243 s = s1;
2244 op_exp = the_insn.exp;
e0c6ed95 2245 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
cf9a1301 2246 }
252b5132 2247
e0c6ed95
AM		 2248 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2249 ;
252b5132 2250
3882b010 2251 if (s1 != s && ISDIGIT (s1[-1]))
252b5132
RH		 2252 {
2253 if (s1[-2] == '%' && s1[-3] == '+')
cf9a1301
RH		 2254 s1 -= 3;
2255 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2256 s1 -= 4;
2257 else
2258 s1 = NULL;
2259 if (s1)
252b5132 2260 {
252b5132 2261 *s1 = '\0';
1eb7027c
RH		 2262 if (op_arg && s1 == s + 1)
2263 the_insn.exp.X_op = O_absent;
2264 else
2265 (void) get_expression (s);
252b5132 2266 *s1 = '+';
cf9a1301
RH		 2267 if (op_arg)
2268 *s = ')';
252b5132 2269 s = s1;
252b5132 2270 }
cf9a1301
RH		 2271 }
2272 else
2273 s1 = NULL;
2274
2275 if (!s1)
2276 {
2277 (void) get_expression (s);
2278 if (op_arg)
2279 *s = ')';
2280 s = expr_end;
2281 }
2282
2283 if (op_arg)
2284 {
2285 the_insn.exp2 = the_insn.exp;
2286 the_insn.exp = op_exp;
2287 if (the_insn.exp2.X_op == O_absent)
2288 the_insn.exp2.X_op = O_illegal;
2289 else if (the_insn.exp.X_op == O_absent)
252b5132 2290 {
cf9a1301
RH		 2291 the_insn.exp = the_insn.exp2;
2292 the_insn.exp2.X_op = O_illegal;
2293 }
2294 else if (the_insn.exp.X_op == O_constant)
2295 {
2296 valueT val = the_insn.exp.X_add_number;
2297 switch (the_insn.reloc)
2298 {
1b50c718
ILT		 2299 default:
2300 break;
2301
cf9a1301
RH		 2302 case BFD_RELOC_SPARC_HH22:
2303 val = BSR (val, 32);
e0c6ed95 2304 /* Fall through. */
cf9a1301
RH		 2305
2306 case BFD_RELOC_SPARC_LM22:
2307 case BFD_RELOC_HI22:
2308 val = (val >> 10) & 0x3fffff;
2309 break;
2310
2311 case BFD_RELOC_SPARC_HM10:
2312 val = BSR (val, 32);
e0c6ed95 2313 /* Fall through. */
cf9a1301
RH		 2314
2315 case BFD_RELOC_LO10:
2316 val &= 0x3ff;
2317 break;
2318
2319 case BFD_RELOC_SPARC_H44:
2320 val >>= 22;
2321 val &= 0x3fffff;
2322 break;
2323
2324 case BFD_RELOC_SPARC_M44:
2325 val >>= 12;
2326 val &= 0x3ff;
2327 break;
2328
2329 case BFD_RELOC_SPARC_L44:
2330 val &= 0xfff;
2331 break;
2332
2333 case BFD_RELOC_SPARC_HIX22:
ab3e48dc 2334 val = ~val;
cf9a1301
RH		 2335 val = (val >> 10) & 0x3fffff;
2336 break;
2337
2338 case BFD_RELOC_SPARC_LOX10:
2339 val = (val & 0x3ff) | 0x1c00;
2340 break;
2341 }
2342 the_insn.exp = the_insn.exp2;
2343 the_insn.exp.X_add_number += val;
2344 the_insn.exp2.X_op = O_illegal;
2345 the_insn.reloc = old_reloc;
2346 }
2347 else if (the_insn.exp2.X_op != O_constant)
2348 {
2349 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
a22b281c 2350 return special_case;
cf9a1301
RH		 2351 }
2352 else
2353 {
dabe3bbc 2354 if (old_reloc != BFD_RELOC_SPARC13
cf9a1301
RH		 2355 || the_insn.reloc != BFD_RELOC_LO10
2356 || sparc_arch_size != 64
2357 || sparc_pic_code)
2358 {
2359 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
a22b281c 2360 return special_case;
cf9a1301
RH		 2361 }
2362 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
252b5132
RH		 2363 }
2364 }
2365 }
252b5132
RH		 2366 /* Check for constants that don't require emitting a reloc. */
2367 if (the_insn.exp.X_op == O_constant
2368 && the_insn.exp.X_add_symbol == 0
2369 && the_insn.exp.X_op_symbol == 0)
2370 {
2371 /* For pc-relative call instructions, we reject
2372 constants to get better code. */
2373 if (the_insn.pcrel
2374 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2375 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2376 {
2377 error_message = _(": PC-relative operand can't be a constant");
2378 goto error;
2379 }
2380
2381 /* Constants that won't fit are checked in md_apply_fix3
2382 and bfd_install_relocation.
2383 ??? It would be preferable to install the constants
2384 into the insn here and save having to create a fixS
2385 for each one. There already exists code to handle
2386 all the various cases (e.g. in md_apply_fix3 and
2387 bfd_install_relocation) so duplicating all that code
2388 here isn't right. */
2389 }
2390
2391 continue;
2392
2393 case 'a':
2394 if (*s++ == 'a')
2395 {
2396 opcode |= ANNUL;
2397 continue;
2398 }
2399 break;
2400
2401 case 'A':
2402 {
2403 int asi = 0;
2404
2405 /* Parse an asi. */
2406 if (*s == '#')
2407 {
2408 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2409 {
2410 error_message = _(": invalid ASI name");
2411 goto error;
2412 }
2413 }
2414 else
2415 {
2416 if (! parse_const_expr_arg (&s, &asi))
2417 {
2418 error_message = _(": invalid ASI expression");
2419 goto error;
2420 }
2421 if (asi < 0 || asi > 255)
2422 {
2423 error_message = _(": invalid ASI number");
2424 goto error;
2425 }
2426 }
2427 opcode |= ASI (asi);
2428 continue;
e0c6ed95 2429 } /* Alternate space. */
252b5132
RH		 2430
2431 case 'p':
2432 if (strncmp (s, "%psr", 4) == 0)
2433 {
2434 s += 4;
2435 continue;
2436 }
2437 break;
2438
e0c6ed95 2439 case 'q': /* Floating point queue. */
252b5132
RH		 2440 if (strncmp (s, "%fq", 3) == 0)
2441 {
2442 s += 3;
2443 continue;
2444 }
2445 break;
2446
e0c6ed95 2447 case 'Q': /* Coprocessor queue. */
252b5132
RH		 2448 if (strncmp (s, "%cq", 3) == 0)
2449 {
2450 s += 3;
2451 continue;
2452 }
2453 break;
2454
2455 case 'S':
2456 if (strcmp (str, "set") == 0
2457 || strcmp (str, "setuw") == 0)
2458 {
2459 special_case = SPECIAL_CASE_SET;
2460 continue;
2461 }
2462 else if (strcmp (str, "setsw") == 0)
2463 {
2464 special_case = SPECIAL_CASE_SETSW;
2465 continue;
2466 }
2467 else if (strcmp (str, "setx") == 0)
2468 {
2469 special_case = SPECIAL_CASE_SETX;
2470 continue;
2471 }
2472 else if (strncmp (str, "fdiv", 4) == 0)
2473 {
2474 special_case = SPECIAL_CASE_FDIV;
2475 continue;
2476 }
2477 break;
2478
2479 case 'o':
2480 if (strncmp (s, "%asi", 4) != 0)
2481 break;
2482 s += 4;
2483 continue;
2484
2485 case 's':
2486 if (strncmp (s, "%fprs", 5) != 0)
2487 break;
2488 s += 5;
2489 continue;
2490
2491 case 'E':
2492 if (strncmp (s, "%ccr", 4) != 0)
2493 break;
2494 s += 4;
2495 continue;
2496
2497 case 't':
2498 if (strncmp (s, "%tbr", 4) != 0)
2499 break;
2500 s += 4;
2501 continue;
2502
2503 case 'w':
2504 if (strncmp (s, "%wim", 4) != 0)
2505 break;
2506 s += 4;
2507 continue;
2508
2509 case 'x':
2510 {
2511 char *push = input_line_pointer;
2512 expressionS e;
2513
2514 input_line_pointer = s;
2515 expression (&e);
2516 if (e.X_op == O_constant)
2517 {
2518 int n = e.X_add_number;
2519 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2520 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2521 else
2522 opcode |= e.X_add_number << 5;
2523 }
2524 else
2525 as_bad (_("non-immediate OPF operand, ignored"));
2526 s = input_line_pointer;
2527 input_line_pointer = push;
2528 continue;
2529 }
2530
2531 case 'y':
2532 if (strncmp (s, "%y", 2) != 0)
2533 break;
2534 s += 2;
2535 continue;
2536
2537 case 'u':
2538 case 'U':
2539 {
2540 /* Parse a sparclet cpreg. */
2541 int cpreg;
2542 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2543 {
2544 error_message = _(": invalid cpreg name");
2545 goto error;
2546 }
2547 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2548 continue;
2549 }
2550
2551 default:
2552 as_fatal (_("failed sanity check."));
e0c6ed95 2553 } /* switch on arg code. */
252b5132
RH		 2554
2555 /* Break out of for() loop. */
2556 break;
e0c6ed95 2557 } /* For each arg that we expect. */
252b5132
RH		 2558
2559 error:
2560 if (match == 0)
2561 {
e0c6ed95 2562 /* Args don't match. */
252b5132
RH		 2563 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2564 && (insn->name == insn[1].name
2565 || !strcmp (insn->name, insn[1].name)))
2566 {
2567 ++insn;
2568 s = argsStart;
2569 continue;
2570 }
2571 else
2572 {
2573 as_bad (_("Illegal operands%s"), error_message);
a22b281c 2574 return special_case;
252b5132
RH		 2575 }
2576 }
2577 else
2578 {
e0c6ed95 2579 /* We have a match. Now see if the architecture is OK. */
252b5132
RH		 2580 int needed_arch_mask = insn->architecture;
2581
2582 if (v9_arg_p)
2583 {
19f7b010
JJ		 2584 needed_arch_mask &=
2585 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2586 if (! needed_arch_mask)
2587 needed_arch_mask =
2588 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
252b5132
RH		 2589 }
2590
e0c6ed95
AM		 2591 if (needed_arch_mask
2592 & SPARC_OPCODE_SUPPORTED (current_architecture))
2593 /* OK. */
2594 ;
252b5132 2595 /* Can we bump up the architecture? */
e0c6ed95
AM		 2596 else if (needed_arch_mask
2597 & SPARC_OPCODE_SUPPORTED (max_architecture))
252b5132
RH		 2598 {
2599 enum sparc_opcode_arch_val needed_architecture =
2600 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2601 & needed_arch_mask);
2602
2603 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2604 if (warn_on_bump
2605 && needed_architecture > warn_after_architecture)
2606 {
2607 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2608 sparc_opcode_archs[current_architecture].name,
2609 sparc_opcode_archs[needed_architecture].name,
2610 str);
2611 warn_after_architecture = needed_architecture;
2612 }
2613 current_architecture = needed_architecture;
2614 }
2615 /* Conflict. */
2616 /* ??? This seems to be a bit fragile. What if the next entry in
2617 the opcode table is the one we want and it is supported?
2618 It is possible to arrange the table today so that this can't
2619 happen but what about tomorrow? */
2620 else
2621 {
e0c6ed95 2622 int arch, printed_one_p = 0;
252b5132
RH		 2623 char *p;
2624 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2625
2626 /* Create a list of the architectures that support the insn. */
e0c6ed95 2627 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
252b5132
RH		 2628 p = required_archs;
2629 arch = sparc_ffs (needed_arch_mask);
2630 while ((1 << arch) <= needed_arch_mask)
2631 {
2632 if ((1 << arch) & needed_arch_mask)
2633 {
2634 if (printed_one_p)
2635 *p++ = '|';
2636 strcpy (p, sparc_opcode_archs[arch].name);
2637 p += strlen (p);
2638 printed_one_p = 1;
2639 }
2640 ++arch;
2641 }
2642
2643 as_bad (_("Architecture mismatch on \"%s\"."), str);
2644 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2645 required_archs,
2646 sparc_opcode_archs[max_architecture].name);
a22b281c 2647 return special_case;
252b5132 2648 }
e0c6ed95 2649 } /* If no match. */
252b5132
RH		 2650
2651 break;
e0c6ed95 2652 } /* Forever looking for a match. */
252b5132
RH		 2653
2654 the_insn.opcode = opcode;
a22b281c 2655 return special_case;
252b5132
RH		 2656}
2657
2658/* Parse an argument that can be expressed as a keyword.
2659 (eg: #StoreStore or %ccfr).
2660 The result is a boolean indicating success.
2661 If successful, INPUT_POINTER is updated. */
2662
2663static int
2664parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2665 int (*lookup_fn) PARAMS ((const char *));
2666 char **input_pointerP;
2667 int *valueP;
2668{
2669 int value;
2670 char c, *p, *q;
2671
2672 p = *input_pointerP;
2673 for (q = p + (*p == '#' || *p == '%');
3882b010 2674 ISALNUM (*q) || *q == '_';
252b5132
RH		 2675 ++q)
2676 continue;
2677 c = *q;
2678 *q = 0;
2679 value = (*lookup_fn) (p);
2680 *q = c;
2681 if (value == -1)
2682 return 0;
2683 *valueP = value;
2684 *input_pointerP = q;
2685 return 1;
2686}
2687
2688/* Parse an argument that is a constant expression.
2689 The result is a boolean indicating success. */
2690
2691static int
2692parse_const_expr_arg (input_pointerP, valueP)
2693 char **input_pointerP;
2694 int *valueP;
2695{
2696 char *save = input_line_pointer;
2697 expressionS exp;
2698
2699 input_line_pointer = *input_pointerP;
2700 /* The next expression may be something other than a constant
2701 (say if we're not processing the right variant of the insn).
2702 Don't call expression unless we're sure it will succeed as it will
2703 signal an error (which we want to defer until later). */
2704 /* FIXME: It might be better to define md_operand and have it recognize
2705 things like %asi, etc. but continuing that route through to the end
2706 is a lot of work. */
2707 if (*input_line_pointer == '%')
2708 {
2709 input_line_pointer = save;
2710 return 0;
2711 }
2712 expression (&exp);
2713 *input_pointerP = input_line_pointer;
2714 input_line_pointer = save;
2715 if (exp.X_op != O_constant)
2716 return 0;
2717 *valueP = exp.X_add_number;
2718 return 1;
2719}
2720
2721/* Subroutine of sparc_ip to parse an expression. */
2722
2723static int
2724get_expression (str)
2725 char *str;
2726{
2727 char *save_in;
2728 segT seg;
2729
2730 save_in = input_line_pointer;
2731 input_line_pointer = str;
2732 seg = expression (&the_insn.exp);
2733 if (seg != absolute_section
2734 && seg != text_section
2735 && seg != data_section
2736 && seg != bss_section
2737 && seg != undefined_section)
2738 {
2739 the_insn.error = _("bad segment");
2740 expr_end = input_line_pointer;
2741 input_line_pointer = save_in;
2742 return 1;
2743 }
2744 expr_end = input_line_pointer;
2745 input_line_pointer = save_in;
2746 return 0;
2747}
2748
2749/* Subroutine of md_assemble to output one insn. */
2750
2751static void
2752output_insn (insn, the_insn)
2753 const struct sparc_opcode *insn;
2754 struct sparc_it *the_insn;
2755{
2756 char *toP = frag_more (4);
2757
e0c6ed95 2758 /* Put out the opcode. */
252b5132
RH		 2759 if (INSN_BIG_ENDIAN)
2760 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2761 else
2762 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2763
e0c6ed95 2764 /* Put out the symbol-dependent stuff. */
252b5132
RH		 2765 if (the_insn->reloc != BFD_RELOC_NONE)
2766 {
e0c6ed95
AM		 2767 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2768 (toP - frag_now->fr_literal), /* Where. */
2769 4, /* Size. */
252b5132
RH		 2770 &the_insn->exp,
2771 the_insn->pcrel,
2772 the_insn->reloc);
2773 /* Turn off overflow checking in fixup_segment. We'll do our
2774 own overflow checking in md_apply_fix3. This is necessary because
2775 the insn size is 4 and fixup_segment will signal an overflow for
2776 large 8 byte quantities. */
2777 fixP->fx_no_overflow = 1;
dabe3bbc
RH		 2778 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2779 fixP->tc_fix_data = the_insn->exp2.X_add_number;
252b5132
RH		 2780 }
2781
2782 last_insn = insn;
2783 last_opcode = the_insn->opcode;
732d96b6
JJ		 2784
2785#ifdef OBJ_ELF
2786 dwarf2_emit_insn (4);
2787#endif
252b5132
RH		 2788}
2789\f
e0c6ed95
AM		 2790/* This is identical to the md_atof in m68k.c. I think this is right,
2791 but I'm not sure.
252b5132 2792
e0c6ed95
AM		 2793 Turn a string in input_line_pointer into a floating point constant
2794 of type TYPE, and store the appropriate bytes in *LITP. The number
2795 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2796 returned, or NULL on OK. */
252b5132 2797
e0c6ed95 2798/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 2799#define MAX_LITTLENUMS 6
2800
2801char *
2802md_atof (type, litP, sizeP)
2803 char type;
2804 char *litP;
2805 int *sizeP;
2806{
e0c6ed95 2807 int i, prec;
252b5132
RH		 2808 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2809 char *t;
2810
2811 switch (type)
2812 {
2813 case 'f':
2814 case 'F':
2815 case 's':
2816 case 'S':
2817 prec = 2;
2818 break;
2819
2820 case 'd':
2821 case 'D':
2822 case 'r':
2823 case 'R':
2824 prec = 4;
2825 break;
2826
2827 case 'x':
2828 case 'X':
2829 prec = 6;
2830 break;
2831
2832 case 'p':
2833 case 'P':
2834 prec = 6;
2835 break;
2836
2837 default:
2838 *sizeP = 0;
2839 return _("Bad call to MD_ATOF()");
2840 }
2841
2842 t = atof_ieee (input_line_pointer, type, words);
2843 if (t)
2844 input_line_pointer = t;
2845 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2846
2847 if (target_big_endian)
2848 {
2849 for (i = 0; i < prec; i++)
2850 {
ab3e48dc
KH		 2851 md_number_to_chars (litP, (valueT) words[i],
2852 sizeof (LITTLENUM_TYPE));
252b5132
RH		 2853 litP += sizeof (LITTLENUM_TYPE);
2854 }
2855 }
2856 else
2857 {
2858 for (i = prec - 1; i >= 0; i--)
2859 {
ab3e48dc
KH		 2860 md_number_to_chars (litP, (valueT) words[i],
2861 sizeof (LITTLENUM_TYPE));
252b5132
RH		 2862 litP += sizeof (LITTLENUM_TYPE);
2863 }
2864 }
e0c6ed95 2865
252b5132
RH		 2866 return 0;
2867}
2868
2869/* Write a value out to the object file, using the appropriate
2870 endianness. */
2871
2872void
2873md_number_to_chars (buf, val, n)
2874 char *buf;
2875 valueT val;
2876 int n;
2877{
2878 if (target_big_endian)
2879 number_to_chars_bigendian (buf, val, n);
2880 else if (target_little_endian_data
2881 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
e0c6ed95
AM		 2882 /* Output debug words, which are not in allocated sections, as big
2883 endian. */
252b5132
RH		 2884 number_to_chars_bigendian (buf, val, n);
2885 else if (target_little_endian_data || ! target_big_endian)
2886 number_to_chars_littleendian (buf, val, n);
2887}
2888\f
2889/* Apply a fixS to the frags, now that we know the value it ought to
81d4177b 2890 hold. */
252b5132 2891
94f592af
NC		 2892void
2893md_apply_fix3 (fixP, valP, segment)
252b5132 2894 fixS *fixP;
94f592af 2895 valueT *valP;
a7982600 2896 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 2897{
2898 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
94f592af 2899 offsetT val = * (offsetT *) valP;
252b5132
RH		 2900 long insn;
2901
252b5132
RH		 2902 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2903
e0c6ed95 2904 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 2905
2906#ifdef OBJ_ELF
a161fe53 2907 /* SPARC ELF relocations don't use an addend in the data field. */
252b5132 2908 if (fixP->fx_addsy != NULL)
a161fe53 2909 return;
252b5132
RH		 2910#endif
2911
2912 /* This is a hack. There should be a better way to
2913 handle this. Probably in terms of howto fields, once
2914 we can look at these fixups in terms of howtos. */
2915 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2916 val += fixP->fx_where + fixP->fx_frag->fr_address;
2917
2918#ifdef OBJ_AOUT
2919 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2920 generate a reloc, then we just want to let the reloc addend set
2921 the value. We do not want to also stuff the addend into the
2922 object file. Including the addend in the object file works when
2923 doing a static link, because the linker will ignore the object
2924 file contents. However, the dynamic linker does not ignore the
2925 object file contents. */
2926 if (fixP->fx_addsy != NULL
2927 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2928 val = 0;
2929
2930 /* When generating PIC code, we do not want an addend for a reloc
2931 against a local symbol. We adjust fx_addnumber to cancel out the
2932 value already included in val, and to also cancel out the
2933 adjustment which bfd_install_relocation will create. */
2934 if (sparc_pic_code
2935 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2936 && fixP->fx_addsy != NULL
2937 && ! S_IS_COMMON (fixP->fx_addsy)
49309057 2938 && symbol_section_p (fixP->fx_addsy))
252b5132
RH		 2939 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2940
2941 /* When generating PIC code, we need to fiddle to get
2942 bfd_install_relocation to do the right thing for a PC relative
2943 reloc against a local symbol which we are going to keep. */
2944 if (sparc_pic_code
2945 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2946 && fixP->fx_addsy != NULL
2947 && (S_IS_EXTERNAL (fixP->fx_addsy)
2948 || S_IS_WEAK (fixP->fx_addsy))
2949 && S_IS_DEFINED (fixP->fx_addsy)
2950 && ! S_IS_COMMON (fixP->fx_addsy))
2951 {
2952 val = 0;
2953 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2954 }
2955#endif
2956
2957 /* If this is a data relocation, just output VAL. */
2958
0f2712ed
NC		 2959 if (fixP->fx_r_type == BFD_RELOC_16
2960 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
252b5132
RH		 2961 {
2962 md_number_to_chars (buf, val, 2);
2963 }
2964 else if (fixP->fx_r_type == BFD_RELOC_32
0f2712ed 2965 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
252b5132
RH		 2966 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2967 {
2968 md_number_to_chars (buf, val, 4);
2969 }
0f2712ed
NC		 2970 else if (fixP->fx_r_type == BFD_RELOC_64
2971 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
252b5132
RH		 2972 {
2973 md_number_to_chars (buf, val, 8);
2974 }
e0c6ed95 2975 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
252b5132
RH		 2976 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2977 {
2978 fixP->fx_done = 0;
94f592af 2979 return;
252b5132
RH		 2980 }
2981 else
2982 {
2983 /* It's a relocation against an instruction. */
2984
2985 if (INSN_BIG_ENDIAN)
2986 insn = bfd_getb32 ((unsigned char *) buf);
2987 else
2988 insn = bfd_getl32 ((unsigned char *) buf);
e0c6ed95 2989
252b5132
RH		 2990 switch (fixP->fx_r_type)
2991 {
2992 case BFD_RELOC_32_PCREL_S2:
2993 val = val >> 2;
2994 /* FIXME: This increment-by-one deserves a comment of why it's
2995 being done! */
2996 if (! sparc_pic_code
2997 || fixP->fx_addsy == NULL
49309057 2998 || symbol_section_p (fixP->fx_addsy))
252b5132 2999 ++val;
6faf3d66 3000
252b5132 3001 insn |= val & 0x3fffffff;
6faf3d66 3002
e0c6ed95 3003 /* See if we have a delay slot. */
6faf3d66
JJ		 3004 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3005 {
3006#define G0 0
3007#define O7 15
3008#define XCC (2 << 20)
3009#define COND(x) (((x)&0xf)<<25)
3010#define CONDA COND(0x8)
3011#define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3012#define INSN_BA (F2(0,2) | CONDA)
3013#define INSN_OR F3(2, 0x2, 0)
3014#define INSN_NOP F2(0,4)
3015
3016 long delay;
3017
3018 /* If the instruction is a call with either:
3019 restore
3020 arithmetic instruction with rd == %o7
3021 where rs1 != %o7 and rs2 if it is register != %o7
3022 then we can optimize if the call destination is near
3023 by changing the call into a branch always. */
3024 if (INSN_BIG_ENDIAN)
3025 delay = bfd_getb32 ((unsigned char *) buf + 4);
3026 else
3027 delay = bfd_getl32 ((unsigned char *) buf + 4);
e0c6ed95 3028 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
6faf3d66 3029 break;
e0c6ed95
AM		 3030 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3031 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3032 || ((delay & RD (~0)) != RD (O7))))
6faf3d66 3033 break;
e0c6ed95
AM		 3034 if ((delay & RS1 (~0)) == RS1 (O7)
3035 || ((delay & F3I (~0)) == 0
3036 && (delay & RS2 (~0)) == RS2 (O7)))
6faf3d66
JJ		 3037 break;
3038 /* Ensure the branch will fit into simm22. */
3039 if ((val & 0x3fe00000)
3040 && (val & 0x3fe00000) != 0x3fe00000)
3041 break;
3042 /* Check if the arch is v9 and branch will fit
3043 into simm19. */
3044 if (((val & 0x3c0000) == 0
3045 || (val & 0x3c0000) == 0x3c0000)
3046 && (sparc_arch_size == 64
3047 || current_architecture >= SPARC_OPCODE_ARCH_V9))
e0c6ed95 3048 /* ba,pt %xcc */
6faf3d66
JJ		 3049 insn = INSN_BPA | (val & 0x7ffff);
3050 else
e0c6ed95 3051 /* ba */
6faf3d66
JJ		 3052 insn = INSN_BA | (val & 0x3fffff);
3053 if (fixP->fx_where >= 4
e0c6ed95
AM		 3054 && ((delay & (0xffffffff ^ RS1 (~0)))
3055 == (INSN_OR | RD (O7) | RS2 (G0))))
6faf3d66
JJ		 3056 {
3057 long setter;
3058 int reg;
3059
3060 if (INSN_BIG_ENDIAN)
3061 setter = bfd_getb32 ((unsigned char *) buf - 4);
3062 else
3063 setter = bfd_getl32 ((unsigned char *) buf - 4);
e0c6ed95 3064 if ((setter & (0xffffffff ^ RD (~0)))
ab3e48dc 3065 != (INSN_OR | RS1 (O7) | RS2 (G0)))
6faf3d66
JJ		 3066 break;
3067 /* The sequence was
3068 or %o7, %g0, %rN
3069 call foo
3070 or %rN, %g0, %o7
3071
3072 If call foo was replaced with ba, replace
3073 or %rN, %g0, %o7 with nop. */
e0c6ed95
AM		 3074 reg = (delay & RS1 (~0)) >> 14;
3075 if (reg != ((setter & RD (~0)) >> 25)
6faf3d66
JJ		 3076 || reg == G0 || reg == O7)
3077 break;
3078
3079 if (INSN_BIG_ENDIAN)
3080 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3081 else
3082 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3083 }
3084 }
252b5132
RH		 3085 break;
3086
3087 case BFD_RELOC_SPARC_11:
3088 if (! in_signed_range (val, 0x7ff))
3089 as_bad_where (fixP->fx_file, fixP->fx_line,
3090 _("relocation overflow"));
3091 insn |= val & 0x7ff;
3092 break;
3093
3094 case BFD_RELOC_SPARC_10:
3095 if (! in_signed_range (val, 0x3ff))
3096 as_bad_where (fixP->fx_file, fixP->fx_line,
3097 _("relocation overflow"));
3098 insn |= val & 0x3ff;
3099 break;
3100
3101 case BFD_RELOC_SPARC_7:
3102 if (! in_bitfield_range (val, 0x7f))
3103 as_bad_where (fixP->fx_file, fixP->fx_line,
3104 _("relocation overflow"));
3105 insn |= val & 0x7f;
3106 break;
3107
3108 case BFD_RELOC_SPARC_6:
3109 if (! in_bitfield_range (val, 0x3f))
3110 as_bad_where (fixP->fx_file, fixP->fx_line,
3111 _("relocation overflow"));
3112 insn |= val & 0x3f;
3113 break;
3114
3115 case BFD_RELOC_SPARC_5:
3116 if (! in_bitfield_range (val, 0x1f))
3117 as_bad_where (fixP->fx_file, fixP->fx_line,
3118 _("relocation overflow"));
3119 insn |= val & 0x1f;
3120 break;
3121
3122 case BFD_RELOC_SPARC_WDISP16:
e0c6ed95 3123 /* FIXME: simplify. */
252b5132
RH		 3124 if (((val > 0) && (val & ~0x3fffc))
3125 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3126 as_bad_where (fixP->fx_file, fixP->fx_line,
3127 _("relocation overflow"));
3128 /* FIXME: The +1 deserves a comment. */
3129 val = (val >> 2) + 1;
3130 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3131 break;
3132
3133 case BFD_RELOC_SPARC_WDISP19:
e0c6ed95 3134 /* FIXME: simplify. */
252b5132
RH		 3135 if (((val > 0) && (val & ~0x1ffffc))
3136 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3137 as_bad_where (fixP->fx_file, fixP->fx_line,
3138 _("relocation overflow"));
3139 /* FIXME: The +1 deserves a comment. */
3140 val = (val >> 2) + 1;
3141 insn |= val & 0x7ffff;
3142 break;
3143
3144 case BFD_RELOC_SPARC_HH22:
3145 val = BSR (val, 32);
e0c6ed95 3146 /* Fall through. */
252b5132
RH		 3147
3148 case BFD_RELOC_SPARC_LM22:
3149 case BFD_RELOC_HI22:
3150 if (!fixP->fx_addsy)
94f592af 3151 insn |= (val >> 10) & 0x3fffff;
252b5132 3152 else
94f592af
NC		 3153 /* FIXME: Need comment explaining why we do this. */
3154 insn &= ~0xffff;
252b5132
RH		 3155 break;
3156
3157 case BFD_RELOC_SPARC22:
3158 if (val & ~0x003fffff)
3159 as_bad_where (fixP->fx_file, fixP->fx_line,
3160 _("relocation overflow"));
3161 insn |= (val & 0x3fffff);
3162 break;
3163
3164 case BFD_RELOC_SPARC_HM10:
3165 val = BSR (val, 32);
e0c6ed95 3166 /* Fall through. */
252b5132
RH		 3167
3168 case BFD_RELOC_LO10:
3169 if (!fixP->fx_addsy)
94f592af 3170 insn |= val & 0x3ff;
252b5132 3171 else
94f592af
NC		 3172 /* FIXME: Need comment explaining why we do this. */
3173 insn &= ~0xff;
252b5132
RH		 3174 break;
3175
dabe3bbc
RH		 3176 case BFD_RELOC_SPARC_OLO10:
3177 val &= 0x3ff;
3178 val += fixP->tc_fix_data;
e0c6ed95 3179 /* Fall through. */
dabe3bbc 3180
252b5132
RH		 3181 case BFD_RELOC_SPARC13:
3182 if (! in_signed_range (val, 0x1fff))
3183 as_bad_where (fixP->fx_file, fixP->fx_line,
3184 _("relocation overflow"));
3185 insn |= val & 0x1fff;
3186 break;
3187
3188 case BFD_RELOC_SPARC_WDISP22:
3189 val = (val >> 2) + 1;
e0c6ed95 3190 /* Fall through. */
252b5132
RH		 3191 case BFD_RELOC_SPARC_BASE22:
3192 insn |= val & 0x3fffff;
3193 break;
3194
3195 case BFD_RELOC_SPARC_H44:
3196 if (!fixP->fx_addsy)
3197 {
3198 bfd_vma tval = val;
3199 tval >>= 22;
3200 insn |= tval & 0x3fffff;
3201 }
3202 break;
3203
3204 case BFD_RELOC_SPARC_M44:
3205 if (!fixP->fx_addsy)
3206 insn |= (val >> 12) & 0x3ff;
3207 break;
3208
3209 case BFD_RELOC_SPARC_L44:
3210 if (!fixP->fx_addsy)
3211 insn |= val & 0xfff;
3212 break;
3213
3214 case BFD_RELOC_SPARC_HIX22:
3215 if (!fixP->fx_addsy)
3216 {
ab3e48dc 3217 val ^= ~(offsetT) 0;
252b5132
RH		 3218 insn |= (val >> 10) & 0x3fffff;
3219 }
3220 break;
3221
3222 case BFD_RELOC_SPARC_LOX10:
3223 if (!fixP->fx_addsy)
3224 insn |= 0x1c00 | (val & 0x3ff);
3225 break;
3226
3227 case BFD_RELOC_NONE:
3228 default:
3229 as_bad_where (fixP->fx_file, fixP->fx_line,
3230 _("bad or unhandled relocation type: 0x%02x"),
3231 fixP->fx_r_type);
3232 break;
3233 }
3234
3235 if (INSN_BIG_ENDIAN)
3236 bfd_putb32 (insn, (unsigned char *) buf);
3237 else
3238 bfd_putl32 (insn, (unsigned char *) buf);
3239 }
3240
3241 /* Are we finished with this relocation now? */
3242 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3243 fixP->fx_done = 1;
252b5132
RH		 3244}
3245
3246/* Translate internal representation of relocation info to BFD target
3247 format. */
e0c6ed95 3248
dabe3bbc 3249arelent **
252b5132 3250tc_gen_reloc (section, fixp)
a7982600 3251 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 3252 fixS *fixp;
3253{
dabe3bbc 3254 static arelent *relocs[3];
252b5132
RH		 3255 arelent *reloc;
3256 bfd_reloc_code_real_type code;
3257
dabe3bbc
RH		 3258 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3259 relocs[1] = NULL;
252b5132 3260
49309057
ILT		 3261 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3262 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 3263 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3264
3265 switch (fixp->fx_r_type)
3266 {
3267 case BFD_RELOC_16:
3268 case BFD_RELOC_32:
3269 case BFD_RELOC_HI22:
3270 case BFD_RELOC_LO10:
3271 case BFD_RELOC_32_PCREL_S2:
3272 case BFD_RELOC_SPARC13:
63fab58c 3273 case BFD_RELOC_SPARC22:
252b5132
RH		 3274 case BFD_RELOC_SPARC_BASE13:
3275 case BFD_RELOC_SPARC_WDISP16:
3276 case BFD_RELOC_SPARC_WDISP19:
3277 case BFD_RELOC_SPARC_WDISP22:
3278 case BFD_RELOC_64:
3279 case BFD_RELOC_SPARC_5:
3280 case BFD_RELOC_SPARC_6:
3281 case BFD_RELOC_SPARC_7:
3282 case BFD_RELOC_SPARC_10:
3283 case BFD_RELOC_SPARC_11:
3284 case BFD_RELOC_SPARC_HH22:
3285 case BFD_RELOC_SPARC_HM10:
3286 case BFD_RELOC_SPARC_LM22:
3287 case BFD_RELOC_SPARC_PC_HH22:
3288 case BFD_RELOC_SPARC_PC_HM10:
3289 case BFD_RELOC_SPARC_PC_LM22:
3290 case BFD_RELOC_SPARC_H44:
3291 case BFD_RELOC_SPARC_M44:
3292 case BFD_RELOC_SPARC_L44:
3293 case BFD_RELOC_SPARC_HIX22:
3294 case BFD_RELOC_SPARC_LOX10:
3295 case BFD_RELOC_SPARC_REV32:
dabe3bbc 3296 case BFD_RELOC_SPARC_OLO10:
0f2712ed
NC		 3297 case BFD_RELOC_SPARC_UA16:
3298 case BFD_RELOC_SPARC_UA32:
3299 case BFD_RELOC_SPARC_UA64:
bd5e6e7e
JJ		 3300 case BFD_RELOC_8_PCREL:
3301 case BFD_RELOC_16_PCREL:
3302 case BFD_RELOC_32_PCREL:
3303 case BFD_RELOC_64_PCREL:
3304 case BFD_RELOC_SPARC_PLT32:
3305 case BFD_RELOC_SPARC_PLT64:
252b5132
RH		 3306 case BFD_RELOC_VTABLE_ENTRY:
3307 case BFD_RELOC_VTABLE_INHERIT:
3308 code = fixp->fx_r_type;
3309 break;
3310 default:
3311 abort ();
3312 return NULL;
3313 }
3314
3315#if defined (OBJ_ELF) || defined (OBJ_AOUT)
3316 /* If we are generating PIC code, we need to generate a different
3317 set of relocs. */
3318
3319#ifdef OBJ_ELF
3320#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3321#else
3322#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3323#endif
3324
153b546a
ILT		 3325 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3326
252b5132
RH		 3327 if (sparc_pic_code)
3328 {
3329 switch (code)
3330 {
3331 case BFD_RELOC_32_PCREL_S2:
ae6063d4 3332 if (generic_force_reloc (fixp))
252b5132
RH		 3333 code = BFD_RELOC_SPARC_WPLT30;
3334 break;
3335 case BFD_RELOC_HI22:
3336 if (fixp->fx_addsy != NULL
3337 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3338 code = BFD_RELOC_SPARC_PC22;
3339 else
3340 code = BFD_RELOC_SPARC_GOT22;
3341 break;
3342 case BFD_RELOC_LO10:
3343 if (fixp->fx_addsy != NULL
3344 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3345 code = BFD_RELOC_SPARC_PC10;
3346 else
3347 code = BFD_RELOC_SPARC_GOT10;
3348 break;
3349 case BFD_RELOC_SPARC13:
3350 code = BFD_RELOC_SPARC_GOT13;
3351 break;
3352 default:
3353 break;
3354 }
3355 }
e0c6ed95 3356#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
252b5132 3357
dabe3bbc
RH		 3358 if (code == BFD_RELOC_SPARC_OLO10)
3359 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3360 else
3361 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH		 3362 if (reloc->howto == 0)
3363 {
3364 as_bad_where (fixp->fx_file, fixp->fx_line,
3365 _("internal error: can't export reloc type %d (`%s')"),
3366 fixp->fx_r_type, bfd_get_reloc_code_name (code));
dabe3bbc
RH		 3367 xfree (reloc);
3368 relocs[0] = NULL;
3369 return relocs;
252b5132
RH		 3370 }
3371
3372 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3373#ifdef OBJ_AOUT
3374
3375 if (reloc->howto->pc_relative == 0
3376 || code == BFD_RELOC_SPARC_PC10
3377 || code == BFD_RELOC_SPARC_PC22)
3378 reloc->addend = fixp->fx_addnumber;
3379 else if (sparc_pic_code
3380 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3381 && fixp->fx_addsy != NULL
3382 && (S_IS_EXTERNAL (fixp->fx_addsy)
3383 || S_IS_WEAK (fixp->fx_addsy))
3384 && S_IS_DEFINED (fixp->fx_addsy)
3385 && ! S_IS_COMMON (fixp->fx_addsy))
3386 reloc->addend = fixp->fx_addnumber;
3387 else
3388 reloc->addend = fixp->fx_offset - reloc->address;
3389
e0c6ed95 3390#else /* elf or coff */
252b5132 3391
bd5e6e7e
JJ		 3392 if (code != BFD_RELOC_32_PCREL_S2
3393 && code != BFD_RELOC_SPARC_WDISP22
3394 && code != BFD_RELOC_SPARC_WDISP16
3395 && code != BFD_RELOC_SPARC_WDISP19
3396 && code != BFD_RELOC_SPARC_WPLT30)
252b5132 3397 reloc->addend = fixp->fx_addnumber;
49309057 3398 else if (symbol_section_p (fixp->fx_addsy))
252b5132
RH		 3399 reloc->addend = (section->vma
3400 + fixp->fx_addnumber
3401 + md_pcrel_from (fixp));
3402 else
3403 reloc->addend = fixp->fx_offset;
3404#endif
3405
dabe3bbc
RH		 3406 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3407 on the same location. */
3408 if (code == BFD_RELOC_SPARC_OLO10)
3409 {
3410 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3411 relocs[2] = NULL;
3412
3413 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
ab3e48dc
KH		 3414 *reloc->sym_ptr_ptr
3415 = symbol_get_bfdsym (section_symbol (absolute_section));
dabe3bbc
RH		 3416 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3417 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3418 reloc->addend = fixp->tc_fix_data;
3419 }
3420
3421 return relocs;
252b5132
RH		 3422}
3423\f
e0c6ed95 3424/* We have no need to default values of symbols. */
252b5132 3425
252b5132
RH		 3426symbolS *
3427md_undefined_symbol (name)
c2158c24 3428 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 3429{
3430 return 0;
e0c6ed95
AM		 3431}
3432
3433/* Round up a section size to the appropriate boundary. */
252b5132 3434
252b5132
RH		 3435valueT
3436md_section_align (segment, size)
c2158c24 3437 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 3438 valueT size;
3439{
3440#ifndef OBJ_ELF
3441 /* This is not right for ELF; a.out wants it, and COFF will force
3442 the alignment anyways. */
3443 valueT align = ((valueT) 1
3444 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3445 valueT newsize;
e0c6ed95
AM		 3446
3447 /* Turn alignment value into a mask. */
252b5132
RH		 3448 align--;
3449 newsize = (size + align) & ~align;
3450 return newsize;
3451#else
3452 return size;
3453#endif
3454}
3455
3456/* Exactly what point is a PC-relative offset relative TO?
3457 On the sparc, they're relative to the address of the offset, plus
3458 its size. This gets us to the following instruction.
e0c6ed95
AM		 3459 (??? Is this right? FIXME-SOON) */
3460long
252b5132
RH		 3461md_pcrel_from (fixP)
3462 fixS *fixP;
3463{
3464 long ret;
3465
3466 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3467 if (! sparc_pic_code
3468 || fixP->fx_addsy == NULL
49309057 3469 || symbol_section_p (fixP->fx_addsy))
252b5132
RH		 3470 ret += fixP->fx_size;
3471 return ret;
3472}
3473\f
3474/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3475 of two. */
3476
3477static int
3478log2 (value)
3479 int value;
3480{
3481 int shift;
3482
3483 if (value <= 0)
3484 return -1;
3485
3486 for (shift = 0; (value & 1) == 0; value >>= 1)
3487 ++shift;
3488
3489 return (value == 1) ? shift : -1;
3490}
3491
e0c6ed95 3492/* Sort of like s_lcomm. */
252b5132
RH		 3493
3494#ifndef OBJ_ELF
3495static int max_alignment = 15;
3496#endif
3497
3498static void
3499s_reserve (ignore)
c2158c24 3500 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3501{
3502 char *name;
3503 char *p;
3504 char c;
3505 int align;
3506 int size;
3507 int temp;
3508 symbolS *symbolP;
3509
3510 name = input_line_pointer;
3511 c = get_symbol_end ();
3512 p = input_line_pointer;
3513 *p = c;
3514 SKIP_WHITESPACE ();
3515
3516 if (*input_line_pointer != ',')
3517 {
3518 as_bad (_("Expected comma after name"));
3519 ignore_rest_of_line ();
3520 return;
3521 }
3522
3523 ++input_line_pointer;
3524
3525 if ((size = get_absolute_expression ()) < 0)
3526 {
3527 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3528 ignore_rest_of_line ();
3529 return;
e0c6ed95 3530 } /* Bad length. */
252b5132
RH		 3531
3532 *p = 0;
3533 symbolP = symbol_find_or_make (name);
3534 *p = c;
3535
3536 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3537 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3538 {
3539 as_bad (_("bad .reserve segment -- expected BSS segment"));
3540 return;
3541 }
3542
3543 if (input_line_pointer[2] == '.')
3544 input_line_pointer += 7;
3545 else
3546 input_line_pointer += 6;
3547 SKIP_WHITESPACE ();
3548
3549 if (*input_line_pointer == ',')
3550 {
3551 ++input_line_pointer;
3552
3553 SKIP_WHITESPACE ();
3554 if (*input_line_pointer == '\n')
3555 {
3556 as_bad (_("missing alignment"));
3557 ignore_rest_of_line ();
3558 return;
3559 }
3560
3561 align = (int) get_absolute_expression ();
3562
3563#ifndef OBJ_ELF
3564 if (align > max_alignment)
3565 {
3566 align = max_alignment;
3567 as_warn (_("alignment too large; assuming %d"), align);
3568 }
3569#endif
3570
3571 if (align < 0)
3572 {
3573 as_bad (_("negative alignment"));
3574 ignore_rest_of_line ();
3575 return;
3576 }
3577
3578 if (align != 0)
3579 {
3580 temp = log2 (align);
3581 if (temp < 0)
3582 {
3583 as_bad (_("alignment not a power of 2"));
3584 ignore_rest_of_line ();
3585 return;
3586 }
3587
3588 align = temp;
3589 }
3590
3591 record_alignment (bss_section, align);
3592 }
3593 else
3594 align = 0;
3595
3596 if (!S_IS_DEFINED (symbolP)
3597#ifdef OBJ_AOUT
3598 && S_GET_OTHER (symbolP) == 0
3599 && S_GET_DESC (symbolP) == 0
3600#endif
3601 )
3602 {
3603 if (! need_pass_2)
3604 {
3605 char *pfrag;
3606 segT current_seg = now_seg;
3607 subsegT current_subseg = now_subseg;
3608
e0c6ed95
AM		 3609 /* Switch to bss. */
3610 subseg_set (bss_section, 1);
252b5132
RH		 3611
3612 if (align)
e0c6ed95
AM		 3613 /* Do alignment. */
3614 frag_align (align, 0, 0);
252b5132 3615
e0c6ed95 3616 /* Detach from old frag. */
ab3e48dc 3617 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057 3618 symbol_get_frag (symbolP)->fr_symbol = NULL;
252b5132 3619
49309057 3620 symbol_set_frag (symbolP, frag_now);
e0c6ed95
AM		 3621 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3622 (offsetT) size, (char *) 0);
252b5132
RH		 3623 *pfrag = 0;
3624
3625 S_SET_SEGMENT (symbolP, bss_section);
3626
3627 subseg_set (current_seg, current_subseg);
3628
3629#ifdef OBJ_ELF
3630 S_SET_SIZE (symbolP, size);
3631#endif
3632 }
3633 }
3634 else
3635 {
ab3e48dc
KH		 3636 as_warn ("Ignoring attempt to re-define symbol %s",
3637 S_GET_NAME (symbolP));
e0c6ed95 3638 } /* if not redefining. */
252b5132
RH		 3639
3640 demand_empty_rest_of_line ();
3641}
3642
3643static void
3644s_common (ignore)
c2158c24 3645 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3646{
3647 char *name;
3648 char c;
3649 char *p;
3650 int temp, size;
3651 symbolS *symbolP;
3652
3653 name = input_line_pointer;
3654 c = get_symbol_end ();
e0c6ed95 3655 /* Just after name is now '\0'. */
252b5132
RH		 3656 p = input_line_pointer;
3657 *p = c;
3658 SKIP_WHITESPACE ();
3659 if (*input_line_pointer != ',')
3660 {
3661 as_bad (_("Expected comma after symbol-name"));
3662 ignore_rest_of_line ();
3663 return;
3664 }
e0c6ed95
AM		 3665
3666 /* Skip ','. */
3667 input_line_pointer++;
3668
252b5132
RH		 3669 if ((temp = get_absolute_expression ()) < 0)
3670 {
3671 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3672 ignore_rest_of_line ();
3673 return;
3674 }
3675 size = temp;
3676 *p = 0;
3677 symbolP = symbol_find_or_make (name);
3678 *p = c;
3679 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3680 {
3681 as_bad (_("Ignoring attempt to re-define symbol"));
3682 ignore_rest_of_line ();
3683 return;
3684 }
3685 if (S_GET_VALUE (symbolP) != 0)
3686 {
3687 if (S_GET_VALUE (symbolP) != (valueT) size)
3688 {
3689 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3690 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3691 }
3692 }
3693 else
3694 {
3695#ifndef OBJ_ELF
3696 S_SET_VALUE (symbolP, (valueT) size);
3697 S_SET_EXTERNAL (symbolP);
3698#endif
3699 }
7dcc9865 3700 know (symbol_get_frag (symbolP) == &zero_address_frag);
252b5132
RH		 3701 if (*input_line_pointer != ',')
3702 {
3703 as_bad (_("Expected comma after common length"));
3704 ignore_rest_of_line ();
3705 return;
3706 }
3707 input_line_pointer++;
3708 SKIP_WHITESPACE ();
3709 if (*input_line_pointer != '"')
3710 {
3711 temp = get_absolute_expression ();
3712
3713#ifndef OBJ_ELF
3714 if (temp > max_alignment)
3715 {
3716 temp = max_alignment;
3717 as_warn (_("alignment too large; assuming %d"), temp);
3718 }
3719#endif
3720
3721 if (temp < 0)
3722 {
3723 as_bad (_("negative alignment"));
3724 ignore_rest_of_line ();
3725 return;
3726 }
3727
3728#ifdef OBJ_ELF
49309057 3729 if (symbol_get_obj (symbolP)->local)
252b5132
RH		 3730 {
3731 segT old_sec;
3732 int old_subsec;
3733 char *p;
3734 int align;
3735
3736 old_sec = now_seg;
3737 old_subsec = now_subseg;
3738
3739 if (temp == 0)
3740 align = 0;
3741 else
3742 align = log2 (temp);
3743
3744 if (align < 0)
3745 {
3746 as_bad (_("alignment not a power of 2"));
3747 ignore_rest_of_line ();
3748 return;
3749 }
3750
3751 record_alignment (bss_section, align);
3752 subseg_set (bss_section, 0);
3753 if (align)
3754 frag_align (align, 0, 0);
3755 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057
ILT		 3756 symbol_get_frag (symbolP)->fr_symbol = 0;
3757 symbol_set_frag (symbolP, frag_now);
252b5132
RH		 3758 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3759 (offsetT) size, (char *) 0);
3760 *p = 0;
3761 S_SET_SEGMENT (symbolP, bss_section);
3762 S_CLEAR_EXTERNAL (symbolP);
3763 S_SET_SIZE (symbolP, size);
3764 subseg_set (old_sec, old_subsec);
3765 }
3766 else
e0c6ed95 3767#endif /* OBJ_ELF */
252b5132
RH		 3768 {
3769 allocate_common:
3770 S_SET_VALUE (symbolP, (valueT) size);
3771#ifdef OBJ_ELF
3772 S_SET_ALIGN (symbolP, temp);
3773 S_SET_SIZE (symbolP, size);
3774#endif
3775 S_SET_EXTERNAL (symbolP);
3776 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3777 }
3778 }
3779 else
3780 {
3781 input_line_pointer++;
3782 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3783 if (*input_line_pointer == '.')
3784 input_line_pointer++;
3785 /* @@ Some say data, some say bss. */
3786 if (strncmp (input_line_pointer, "bss\"", 4)
3787 && strncmp (input_line_pointer, "data\"", 5))
3788 {
3789 while (*--input_line_pointer != '"')
3790 ;
3791 input_line_pointer--;
3792 goto bad_common_segment;
3793 }
3794 while (*input_line_pointer++ != '"')
3795 ;
3796 goto allocate_common;
3797 }
3798
3799#ifdef BFD_ASSEMBLER
49309057 3800 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
252b5132
RH		 3801#endif
3802
3803 demand_empty_rest_of_line ();
3804 return;
3805
3806 {
3807 bad_common_segment:
3808 p = input_line_pointer;
3809 while (*p && *p != '\n')
3810 p++;
3811 c = *p;
3812 *p = '\0';
3813 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3814 *p = c;
3815 input_line_pointer = p;
3816 ignore_rest_of_line ();
3817 return;
3818 }
3819}
3820
3821/* Handle the .empty pseudo-op. This supresses the warnings about
3822 invalid delay slot usage. */
3823
3824static void
3825s_empty (ignore)
c2158c24 3826 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3827{
3828 /* The easy way to implement is to just forget about the last
3829 instruction. */
3830 last_insn = NULL;
3831}
3832
3833static void
3834s_seg (ignore)
c2158c24 3835 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3836{
3837
3838 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3839 {
3840 input_line_pointer += 6;
3841 s_text (0);
3842 return;
3843 }
3844 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3845 {
3846 input_line_pointer += 6;
3847 s_data (0);
3848 return;
3849 }
3850 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3851 {
3852 input_line_pointer += 7;
3853 s_data1 ();
3854 return;
3855 }
3856 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3857 {
3858 input_line_pointer += 5;
3859 /* We only support 2 segments -- text and data -- for now, so
3860 things in the "bss segment" will have to go into data for now.
e0c6ed95
AM		 3861 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3862 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
252b5132
RH		 3863 return;
3864 }
3865 as_bad (_("Unknown segment type"));
3866 demand_empty_rest_of_line ();
3867}
3868
3869static void
3870s_data1 ()
3871{
3872 subseg_set (data_section, 1);
3873 demand_empty_rest_of_line ();
3874}
3875
3876static void
3877s_proc (ignore)
c2158c24 3878 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 3879{
3880 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3881 {
3882 ++input_line_pointer;
3883 }
3884 ++input_line_pointer;
3885}
3886
3887/* This static variable is set by s_uacons to tell sparc_cons_align
3888 that the expession does not need to be aligned. */
3889
3890static int sparc_no_align_cons = 0;
3891
bd5e6e7e
JJ		 3892/* This static variable is set by sparc_cons to emit requested types
3893 of relocations in cons_fix_new_sparc. */
3894
3895static const char *sparc_cons_special_reloc;
3896
252b5132
RH		 3897/* This handles the unaligned space allocation pseudo-ops, such as
3898 .uaword. .uaword is just like .word, but the value does not need
3899 to be aligned. */
3900
3901static void
3902s_uacons (bytes)
3903 int bytes;
3904{
3905 /* Tell sparc_cons_align not to align this value. */
3906 sparc_no_align_cons = 1;
3907 cons (bytes);
4ffadb11 3908 sparc_no_align_cons = 0;
252b5132
RH		 3909}
3910
cf9a1301
RH		 3911/* This handles the native word allocation pseudo-op .nword.
3912 For sparc_arch_size 32 it is equivalent to .word, for
3913 sparc_arch_size 64 it is equivalent to .xword. */
3914
3915static void
3916s_ncons (bytes)
c2158c24 3917 int bytes ATTRIBUTE_UNUSED;
cf9a1301
RH		 3918{
3919 cons (sparc_arch_size == 32 ? 4 : 8);
3920}
3921
6d8809aa
RH		 3922#ifdef OBJ_ELF
3923/* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3924 global register.
3925 The syntax is:
e0c6ed95 3926
6d8809aa 3927 .register %g[2367],{#scratch|symbolname|#ignore}
e0c6ed95 3928*/
6d8809aa
RH		 3929
3930static void
3931s_register (ignore)
c2158c24 3932 int ignore ATTRIBUTE_UNUSED;
6d8809aa
RH		 3933{
3934 char c;
3935 int reg;
3936 int flags;
3937 const char *regname;
3938
3939 if (input_line_pointer[0] != '%'
3940 || input_line_pointer[1] != 'g'
3941 || ((input_line_pointer[2] & ~1) != '2'
3942 && (input_line_pointer[2] & ~1) != '6')
3943 || input_line_pointer[3] != ',')
3944 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3945 reg = input_line_pointer[2] - '0';
3946 input_line_pointer += 4;
3947
3948 if (*input_line_pointer == '#')
3949 {
3950 ++input_line_pointer;
3951 regname = input_line_pointer;
3952 c = get_symbol_end ();
3953 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
3954 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
ab3e48dc 3955 if (regname[0] == 'i')
6d8809aa
RH		 3956 regname = NULL;
3957 else
3958 regname = "";
3959 }
3960 else
3961 {
3962 regname = input_line_pointer;
3963 c = get_symbol_end ();
3964 }
3965 if (sparc_arch_size == 64)
3966 {
e0c6ed95 3967 if (globals[reg])
6d8809aa 3968 {
e0c6ed95
AM		 3969 if ((regname && globals[reg] != (symbolS *) 1
3970 && strcmp (S_GET_NAME (globals[reg]), regname))
3971 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
6d8809aa
RH		 3972 as_bad (_("redefinition of global register"));
3973 }
3974 else
3975 {
3976 if (regname == NULL)
e0c6ed95 3977 globals[reg] = (symbolS *) 1;
6d8809aa
RH		 3978 else
3979 {
3980 if (*regname)
3981 {
3982 if (symbol_find (regname))
3983 as_bad (_("Register symbol %s already defined."),
3984 regname);
3985 }
e0c6ed95
AM		 3986 globals[reg] = symbol_make (regname);
3987 flags = symbol_get_bfdsym (globals[reg])->flags;
6d8809aa
RH		 3988 if (! *regname)
3989 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
3990 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
3991 flags |= BSF_GLOBAL;
e0c6ed95
AM		 3992 symbol_get_bfdsym (globals[reg])->flags = flags;
3993 S_SET_VALUE (globals[reg], (valueT) reg);
3994 S_SET_ALIGN (globals[reg], reg);
3995 S_SET_SIZE (globals[reg], 0);
6d8809aa
RH		 3996 /* Although we actually want undefined_section here,
3997 we have to use absolute_section, because otherwise
3998 generic as code will make it a COM section.
3999 We fix this up in sparc_adjust_symtab. */
e0c6ed95
AM		 4000 S_SET_SEGMENT (globals[reg], absolute_section);
4001 S_SET_OTHER (globals[reg], 0);
4002 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 4003 ->internal_elf_sym.st_info =
4004 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
e0c6ed95 4005 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 4006 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4007 }
4008 }
4009 }
4010
4011 *input_line_pointer = c;
4012
4013 demand_empty_rest_of_line ();
4014}
4015
4016/* Adjust the symbol table. We set undefined sections for STT_REGISTER
4017 symbols which need it. */
e0c6ed95 4018
6d8809aa
RH		 4019void
4020sparc_adjust_symtab ()
4021{
4022 symbolS *sym;
e0c6ed95 4023
6d8809aa
RH		 4024 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4025 {
4026 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4027 ->internal_elf_sym.st_info) != STT_REGISTER)
4028 continue;
4029
4030 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4031 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4032 continue;
4033
4034 S_SET_SEGMENT (sym, undefined_section);
4035 }
4036}
4037#endif
4038
252b5132
RH		 4039/* If the --enforce-aligned-data option is used, we require .word,
4040 et. al., to be aligned correctly. We do it by setting up an
4041 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4042 no unexpected alignment was introduced.
4043
4044 The SunOS and Solaris native assemblers enforce aligned data by
4045 default. We don't want to do that, because gcc can deliberately
4046 generate misaligned data if the packed attribute is used. Instead,
4047 we permit misaligned data by default, and permit the user to set an
4048 option to check for it. */
4049
4050void
4051sparc_cons_align (nbytes)
4052 int nbytes;
4053{
4054 int nalign;
4055 char *p;
4056
4057 /* Only do this if we are enforcing aligned data. */
4058 if (! enforce_aligned_data)
4059 return;
4060
0f2712ed 4061 /* Don't align if this is an unaligned pseudo-op. */
252b5132 4062 if (sparc_no_align_cons)
0f2712ed 4063 return;
252b5132
RH		 4064
4065 nalign = log2 (nbytes);
4066 if (nalign == 0)
4067 return;
4068
4069 assert (nalign > 0);
4070
4071 if (now_seg == absolute_section)
4072 {
4073 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4074 as_bad (_("misaligned data"));
4075 return;
4076 }
4077
0a9ef439 4078 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
252b5132
RH		 4079 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4080
4081 record_alignment (now_seg, nalign);
4082}
4083
0a9ef439 4084/* This is called from HANDLE_ALIGN in tc-sparc.h. */
252b5132
RH		 4085
4086void
4087sparc_handle_align (fragp)
4088 fragS *fragp;
4089{
0a9ef439
RH		 4090 int count, fix;
4091 char *p;
4092
4093 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
bfb32b52 4094
0a9ef439 4095 switch (fragp->fr_type)
252b5132 4096 {
0a9ef439
RH		 4097 case rs_align_test:
4098 if (count != 0)
4099 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4100 break;
e0c6ed95 4101
0a9ef439
RH		 4102 case rs_align_code:
4103 p = fragp->fr_literal + fragp->fr_fix;
4104 fix = 0;
e0c6ed95 4105
0a9ef439
RH		 4106 if (count & 3)
4107 {
4108 fix = count & 3;
4109 memset (p, 0, fix);
4110 p += fix;
4111 count -= fix;
4112 }
e0c6ed95 4113
0a9ef439
RH		 4114 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4115 {
4116 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4117 if (INSN_BIG_ENDIAN)
4118 number_to_chars_bigendian (p, wval, 4);
4119 else
4120 number_to_chars_littleendian (p, wval, 4);
4121 p += 4;
4122 count -= 4;
4123 fix += 4;
e0c6ed95 4124 }
0a9ef439
RH		 4125
4126 if (INSN_BIG_ENDIAN)
4127 number_to_chars_bigendian (p, 0x01000000, 4);
4128 else
4129 number_to_chars_littleendian (p, 0x01000000, 4);
4130
4131 fragp->fr_fix += fix;
4132 fragp->fr_var = 4;
4133 break;
4134
4135 default:
4136 break;
252b5132
RH		 4137 }
4138}
4139
4140#ifdef OBJ_ELF
4141/* Some special processing for a Sparc ELF file. */
4142
4143void
4144sparc_elf_final_processing ()
4145{
4146 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4147 sort of BFD interface for this. */
4148 if (sparc_arch_size == 64)
4149 {
4150 switch (sparc_memory_model)
4151 {
4152 case MM_RMO:
4153 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4154 break;
4155 case MM_PSO:
4156 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4157 break;
4158 default:
4159 break;
4160 }
4161 }
4162 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4163 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4164 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4165 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
19f7b010
JJ		 4166 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4167 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
252b5132 4168}
bd5e6e7e
JJ		 4169
4170void
4171sparc_cons (exp, size)
4172 expressionS *exp;
4173 int size;
4174{
4175 char *save;
4176
4177 SKIP_WHITESPACE ();
4178 sparc_cons_special_reloc = NULL;
4179 save = input_line_pointer;
4180 if (input_line_pointer[0] == '%'
4181 && input_line_pointer[1] == 'r'
4182 && input_line_pointer[2] == '_')
4183 {
4184 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4185 {
4186 input_line_pointer += 7;
4187 sparc_cons_special_reloc = "disp";
4188 }
4189 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4190 {
4191 if (size != 4 && size != 8)
4192 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4193 else
4194 {
4195 input_line_pointer += 6;
4196 sparc_cons_special_reloc = "plt";
4197 }
4198 }
4199 if (sparc_cons_special_reloc)
4200 {
4201 int bad = 0;
4202
4203 switch (size)
4204 {
4205 case 1:
4206 if (*input_line_pointer != '8')
4207 bad = 1;
4208 input_line_pointer--;
4209 break;
4210 case 2:
4211 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4212 bad = 1;
4213 break;
4214 case 4:
4215 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4216 bad = 1;
4217 break;
4218 case 8:
4219 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4220 bad = 1;
4221 break;
4222 default:
4223 bad = 1;
4224 break;
4225 }
4226
4227 if (bad)
4228 {
4229 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4230 sparc_cons_special_reloc, size * 8, size);
4231 }
4232 else
4233 {
4234 input_line_pointer += 2;
4235 if (*input_line_pointer != '(')
4236 {
4237 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4238 sparc_cons_special_reloc, size * 8);
4239 bad = 1;
4240 }
4241 }
4242
4243 if (bad)
4244 {
4245 input_line_pointer = save;
4246 sparc_cons_special_reloc = NULL;
4247 }
4248 else
4249 {
4250 int c;
4251 char *end = ++input_line_pointer;
4252 int npar = 0;
4253
4254 while (! is_end_of_line[(c = *end)])
4255 {
4256 if (c == '(')
4257 npar++;
4258 else if (c == ')')
4259 {
4260 if (!npar)
4261 break;
4262 npar--;
4263 }
4264 end++;
4265 }
4266
4267 if (c != ')')
4268 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4269 sparc_cons_special_reloc, size * 8);
4270 else
4271 {
4272 *end = '\0';
4273 expression (exp);
4274 *end = c;
4275 if (input_line_pointer != end)
4276 {
4277 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4278 sparc_cons_special_reloc, size * 8);
4279 }
4280 else
4281 {
4282 input_line_pointer++;
4283 SKIP_WHITESPACE ();
4284 c = *input_line_pointer;
4285 if (! is_end_of_line[c] && c != ',')
4286 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4287 sparc_cons_special_reloc, size * 8);
4288 }
4289 }
4290 }
4291 }
4292 }
4293 if (sparc_cons_special_reloc == NULL)
4294 expression (exp);
4295}
4296
252b5132
RH		 4297#endif
4298
4299/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4300 reloc for a cons. We could use the definition there, except that
4301 we want to handle little endian relocs specially. */
4302
4303void
4304cons_fix_new_sparc (frag, where, nbytes, exp)
4305 fragS *frag;
4306 int where;
4307 unsigned int nbytes;
4308 expressionS *exp;
4309{
4310 bfd_reloc_code_real_type r;
4311
4312 r = (nbytes == 1 ? BFD_RELOC_8 :
4313 (nbytes == 2 ? BFD_RELOC_16 :
4314 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4315
0f2712ed
NC		 4316 if (target_little_endian_data
4317 && nbytes == 4
e0c6ed95 4318 && now_seg->flags & SEC_ALLOC)
252b5132 4319 r = BFD_RELOC_SPARC_REV32;
0f2712ed 4320
bd5e6e7e
JJ		 4321 if (sparc_cons_special_reloc)
4322 {
4323 if (*sparc_cons_special_reloc == 'd')
4324 switch (nbytes)
4325 {
4326 case 1: r = BFD_RELOC_8_PCREL; break;
4327 case 2: r = BFD_RELOC_16_PCREL; break;
4328 case 4: r = BFD_RELOC_32_PCREL; break;
4329 case 8: r = BFD_RELOC_64_PCREL; break;
4330 default: abort ();
4331 }
4332 else
4333 switch (nbytes)
4334 {
4335 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4336 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4337 }
4338 }
4339 else if (sparc_no_align_cons)
0f2712ed
NC		 4340 {
4341 switch (nbytes)
4342 {
4343 case 2: r = BFD_RELOC_SPARC_UA16; break;
4344 case 4: r = BFD_RELOC_SPARC_UA32; break;
4345 case 8: r = BFD_RELOC_SPARC_UA64; break;
4346 default: abort ();
4347 }
4ffadb11 4348 }
0f2712ed 4349
252b5132
RH		 4350 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4351}
GDB Binutils - Deliverables
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