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* config/tc-mips.c : support frame and regmask/fregmask when
[deliverable/binutils-gdb.git] / gas / config / tc-sparc.c
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fecd2382 1/* tc-sparc.c -- Assemble for the SPARC
48401fcf 2 Copyright (C) 1989, 90-96, 97, 1998 Free Software Foundation, Inc.
fecd2382 3 This file is part of GAS, the GNU Assembler.
355afbcd 4
fecd2382
RP		 5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
6321e9ea 7 the Free Software Foundation; either version 2, or (at your option)
fecd2382 8 any later version.
355afbcd 9
fecd2382
RP		 10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
355afbcd 14
8dd07a84
ILT		 15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
fecd2382 19
fecd2382
RP		 20#include <stdio.h>
21#include <ctype.h>
22
23#include "as.h"
7ab2e983 24#include "subsegs.h"
fecd2382 25
584a0f78 26#include "opcode/sparc.h"
fecd2382 27
48401fcf 28#ifdef OBJ_ELF
1bb6aaad 29#include "elf/sparc.h"
48401fcf 30#endif
1bb6aaad 31
54b9ebdd
DE		 32static struct sparc_arch *lookup_arch PARAMS ((char *));
33static void init_default_arch PARAMS ((void));
ed94c2b8 34static void sparc_ip PARAMS ((char *, const struct sparc_opcode **));
9f6da653 35static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
54b9ebdd 36static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
9f6da653
DE		 37static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
38static int sparc_ffs PARAMS ((unsigned int));
39static bfd_vma BSR PARAMS ((bfd_vma, int));
40static int cmp_reg_entry PARAMS ((const PTR, const PTR));
41static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
42static int parse_const_expr_arg PARAMS ((char **, int *));
af6f39b4 43static int get_expression PARAMS ((char *str));
fecd2382 44
54b9ebdd
DE		 45/* Default architecture. */
46/* ??? The default value should be V8, but sparclite support was added
47 by making it the default. GCC now passes -Asparclite, so maybe sometime in
48 the future we can set this to V8. */
49#ifndef DEFAULT_ARCH
50#define DEFAULT_ARCH "sparclite"
51#endif
52static char *default_arch = DEFAULT_ARCH;
53
54/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
55 have been set. */
56static int default_init_p;
57
e70ad5d5
DE		 58/* Current architecture. We don't bump up unless necessary. */
59static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
60
61/* The maximum architecture level we can bump up to.
62 In a 32 bit environment, don't allow bumping up to v9 by default.
2b063e6d 63 The native assembler works this way. The user is required to pass
e70ad5d5 64 an explicit argument before we'll create v9 object files. However, if
54b9ebdd
DE		 65 we don't see any v9 insns, a v8plus object file is not created. */
66static enum sparc_opcode_arch_val max_architecture;
67
68/* Either 32 or 64, selects file format. */
69static int sparc_arch_size;
595da85d
DE		 70/* Initial (default) value, recorded separately in case a user option
71 changes the value before md_show_usage is called. */
72static int default_arch_size;
6df07e7f 73
48401fcf
TT		 74#ifdef OBJ_ELF
75/* The currently selected v9 memory model. Currently only used for
76 ELF. */
77static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
78#endif
79
428d312b
KR		 80static int architecture_requested;
81static int warn_on_bump;
839df5c3 82
e70ad5d5
DE		 83/* If warn_on_bump and the needed architecture is higher than this
84 architecture, issue a warning. */
85static enum sparc_opcode_arch_val warn_after_architecture;
86
4c67b523
ILT		 87/* Non-zero if we are generating PIC code. */
88int sparc_pic_code;
89
2b063e6d
ILT		 90/* Non-zero if we should give an error when misaligned data is seen. */
91static int enforce_aligned_data;
92
ed9638af
KR		 93extern int target_big_endian;
94
fc23c14e
SC		 95static int target_little_endian_data;
96
48401fcf
TT		 97/* V9 and 86x have big and little endian data, but instructions are always big
98 endian. The sparclet has bi-endian support but both data and insns have
99 the same endianness. Global `target_big_endian' is used for data.
100 The following macro is used for instructions. */
101#ifndef INSN_BIG_ENDIAN
2b063e6d 102#define INSN_BIG_ENDIAN (target_big_endian \
48401fcf 103 || default_arch_type == sparc86x \
2b063e6d 104 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
48401fcf 105#endif
2b063e6d 106
fecd2382 107/* handle of the OPCODE hash table */
5e0a90a8 108static struct hash_control *op_hash;
fecd2382 109
4a07363f 110static int log2 PARAMS ((int));
7766838e
ILT		 111static void s_data1 PARAMS ((void));
112static void s_seg PARAMS ((int));
113static void s_proc PARAMS ((int));
114static void s_reserve PARAMS ((int));
115static void s_common PARAMS ((int));
8dd07a84
ILT		 116static void s_empty PARAMS ((int));
117static void s_uacons PARAMS ((int));
428d312b 118
355afbcd
KR		 119const pseudo_typeS md_pseudo_table[] =
120{
121 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */
122 {"common", s_common, 0},
8dd07a84 123 {"empty", s_empty, 0},
355afbcd
KR		 124 {"global", s_globl, 0},
125 {"half", cons, 2},
126 {"optim", s_ignore, 0},
127 {"proc", s_proc, 0},
128 {"reserve", s_reserve, 0},
129 {"seg", s_seg, 0},
130 {"skip", s_space, 0},
131 {"word", cons, 4},
7766838e 132 {"xword", cons, 8},
2b063e6d
ILT		 133 {"uahalf", s_uacons, 2},
134 {"uaword", s_uacons, 4},
135 {"uaxword", s_uacons, 8},
693b21e7 136#ifdef OBJ_ELF
693b21e7
KR		 137 /* these are specific to sparc/svr4 */
138 {"pushsection", obj_elf_section, 0},
139 {"popsection", obj_elf_previous, 0},
2b063e6d
ILT		 140 {"2byte", s_uacons, 2},
141 {"4byte", s_uacons, 4},
142 {"8byte", s_uacons, 8},
693b21e7 143#endif
355afbcd 144 {NULL, 0, 0},
fecd2382
RP		 145};
146
355afbcd 147const int md_reloc_size = 12; /* Size of relocation record */
fecd2382
RP		 148
149/* This array holds the chars that always start a comment. If the
150 pre-processor is disabled, these aren't very useful */
839df5c3 151const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */
fecd2382
RP		 152
153/* This array holds the chars that only start a comment at the beginning of
154 a line. If the line seems to have the form '# 123 filename'
155 .line and .file directives will appear in the pre-processed output */
156/* Note that input_file.c hand checks for '#' at the beginning of the
157 first line of the input file. This is because the compiler outputs
158 #NO_APP at the beginning of its output. */
839df5c3
RP		 159/* Also note that comments started like this one will always
160 work if '/' isn't otherwise defined. */
161const char line_comment_chars[] = "#";
fecd2382 162
355afbcd
KR		 163const char line_separator_chars[] = "";
164
fecd2382 165/* Chars that can be used to separate mant from exp in floating point nums */
839df5c3 166const char EXP_CHARS[] = "eE";
fecd2382
RP		 167
168/* Chars that mean this number is a floating point constant */
169/* As in 0f12.456 */
170/* or 0d1.2345e12 */
839df5c3 171const char FLT_CHARS[] = "rRsSfFdDxXpP";
fecd2382
RP		 172
173/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
9b6a882e
KR		 174 changed in read.c. Ideally it shouldn't have to know about it at all,
175 but nothing is ideal around here. */
fecd2382
RP		 176
177static unsigned char octal[256];
58d4951d 178#define isoctal(c) octal[(unsigned char) (c)]
355afbcd
KR		 179static unsigned char toHex[256];
180
181struct sparc_it
182 {
183 char *error;
184 unsigned long opcode;
185 struct nlist *nlistp;
186 expressionS exp;
187 int pcrel;
428d312b 188 bfd_reloc_code_real_type reloc;
428d312b
KR		 189 };
190
191struct sparc_it the_insn, set_insn;
192
9f6da653
DE		 193static void output_insn
194 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
af6f39b4 195\f
54b9ebdd
DE		 196/* Table of arguments to -A.
197 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
198 for this use. That table is for opcodes only. This table is for opcodes
199 and file formats. */
200
48401fcf
TT		 201enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
202 v8plusa, v9, v9a, v9_64};
203
54b9ebdd
DE		 204static struct sparc_arch {
205 char *name;
206 char *opcode_arch;
48401fcf 207 enum sparc_arch_types arch_type;
595da85d
DE		 208 /* Default word size, as specified during configuration.
209 A value of zero means can't be used to specify default architecture. */
210 int default_arch_size;
211 /* Allowable arg to -A? */
212 int user_option_p;
54b9ebdd 213} sparc_arch_table[] = {
48401fcf
TT		 214 { "v6", "v6", v6, 0, 1 },
215 { "v7", "v7", v7, 0, 1 },
216 { "v8", "v8", v8, 32, 1 },
217 { "sparclet", "sparclet", sparclet, 32, 1 },
218 { "sparclite", "sparclite", sparclite, 32, 1 },
219 { "sparc86x", "sparclite", sparc86x, 32, 1 },
220 { "v8plus", "v9", v9, 0, 1 },
221 { "v8plusa", "v9a", v9, 0, 1 },
222 { "v9", "v9", v9, 0, 1 },
223 { "v9a", "v9a", v9, 0, 1 },
595da85d
DE		 224 /* This exists to allow configure.in/Makefile.in to pass one
225 value to specify both the default machine and default word size. */
48401fcf
TT		 226 { "v9-64", "v9", v9, 64, 0 },
227 { NULL, NULL, v8, 0, 0 }
54b9ebdd
DE		 228};
229
48401fcf
TT		 230/* Variant of default_arch */
231static enum sparc_arch_types default_arch_type;
232
54b9ebdd
DE		 233static struct sparc_arch *
234lookup_arch (name)
235 char *name;
236{
237 struct sparc_arch *sa;
238
239 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
240 if (strcmp (sa->name, name) == 0)
241 break;
242 if (sa->name == NULL)
243 return NULL;
244 return sa;
245}
246
247/* Initialize the default opcode arch and word size from the default
248 architecture name. */
249
250static void
251init_default_arch ()
252{
253 struct sparc_arch *sa = lookup_arch (default_arch);
254
595da85d
DE		 255 if (sa == NULL
256 || sa->default_arch_size == 0)
48401fcf 257 as_fatal (_("Invalid default architecture, broken assembler."));
54b9ebdd
DE		 258
259 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
260 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
48401fcf 261 as_fatal (_("Bad opcode table, broken assembler."));
595da85d 262 default_arch_size = sparc_arch_size = sa->default_arch_size;
54b9ebdd 263 default_init_p = 1;
48401fcf 264 default_arch_type = sa->arch_type;
54b9ebdd
DE		 265}
266
267/* Called by TARGET_FORMAT. */
268
269const char *
270sparc_target_format ()
271{
272 /* We don't get a chance to initialize anything before we're called,
273 so handle that now. */
274 if (! default_init_p)
275 init_default_arch ();
276
277#ifdef OBJ_AOUT
278#ifdef TE_NetBSD
279 return "a.out-sparc-netbsd";
280#else
281#ifdef TE_SPARCAOUT
b9089139
RH		 282 if (target_big_endian)
283 return "a.out-sunos-big";
284 else if (default_arch_type == sparc86x && target_little_endian_data)
285 return "a.out-sunos-big";
286 else return "a.out-sparc-little";
54b9ebdd
DE		 287#else
288 return "a.out-sunos-big";
289#endif
290#endif
291#endif
292
293#ifdef OBJ_BOUT
294 return "b.out.big";
295#endif
296
297#ifdef OBJ_COFF
298#ifdef TE_LYNX
299 return "coff-sparc-lynx";
300#else
301 return "coff-sparc";
302#endif
303#endif
304
305#ifdef OBJ_ELF
306 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
307#endif
308
309 abort ();
310}
311\f
af6f39b4
DE		 312/*
313 * md_parse_option
314 * Invocation line includes a switch not recognized by the base assembler.
315 * See if it's a processor-specific option. These are:
316 *
317 * -bump
318 * Warn on architecture bumps. See also -A.
319 *
320 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
321 * Standard 32 bit architectures.
322 * -Av8plus, -Av8plusa
323 * Sparc64 in a 32 bit world.
324 * -Av9, -Av9a
595da85d
DE		 325 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
326 * This used to only mean 64 bits, but properly specifying it
327 * complicated gcc's ASM_SPECs, so now opcode selection is
328 * specified orthogonally to word size (except when specifying
329 * the default, but that is an internal implementation detail).
af6f39b4
DE		 330 * -xarch=v8plus, -xarch=v8plusa
331 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
332 *
333 * Select the architecture and possibly the file format.
334 * Instructions or features not supported by the selected
335 * architecture cause fatal errors.
336 *
337 * The default is to start at v6, and bump the architecture up
54b9ebdd
DE		 338 * whenever an instruction is seen at a higher level. In 32 bit
339 * environments, v9 is not bumped up to, the user must pass
340 * -Av8plus{,a}.
af6f39b4
DE		 341 *
342 * If -bump is specified, a warning is printing when bumping to
343 * higher levels.
344 *
345 * If an architecture is specified, all instructions must match
346 * that architecture. Any higher level instructions are flagged
347 * as errors. Note that in the 32 bit environment specifying
54b9ebdd
DE		 348 * -Av8plus does not automatically create a v8plus object file, a
349 * v9 insn must be seen.
af6f39b4
DE		 350 *
351 * If both an architecture and -bump are specified, the
352 * architecture starts at the specified level, but bumps are
353 * warnings. Note that we can't set `current_architecture' to
354 * the requested level in this case: in the 32 bit environment,
54b9ebdd
DE		 355 * we still must avoid creating v8plus object files unless v9
356 * insns are seen.
af6f39b4
DE		 357 *
358 * Note:
359 * Bumping between incompatible architectures is always an
360 * error. For example, from sparclite to v9.
361 */
9f6da653 362
af6f39b4
DE		 363#ifdef OBJ_ELF
364CONST char *md_shortopts = "A:K:VQ:sq";
365#else
366#ifdef OBJ_AOUT
367CONST char *md_shortopts = "A:k";
368#else
369CONST char *md_shortopts = "A:";
370#endif
371#endif
372struct option md_longopts[] = {
373#define OPTION_BUMP (OPTION_MD_BASE)
374 {"bump", no_argument, NULL, OPTION_BUMP},
375#define OPTION_SPARC (OPTION_MD_BASE + 1)
376 {"sparc", no_argument, NULL, OPTION_SPARC},
377#define OPTION_XARCH (OPTION_MD_BASE + 2)
378 {"xarch", required_argument, NULL, OPTION_XARCH},
595da85d
DE		 379#ifdef OBJ_ELF
380#define OPTION_32 (OPTION_MD_BASE + 3)
381 {"32", no_argument, NULL, OPTION_32},
382#define OPTION_64 (OPTION_MD_BASE + 4)
383 {"64", no_argument, NULL, OPTION_64},
1bb6aaad
RH		 384#define OPTION_TSO (OPTION_MD_BASE + 5)
385 {"TSO", no_argument, NULL, OPTION_TSO},
386#define OPTION_PSO (OPTION_MD_BASE + 6)
387 {"PSO", no_argument, NULL, OPTION_PSO},
388#define OPTION_RMO (OPTION_MD_BASE + 7)
389 {"RMO", no_argument, NULL, OPTION_RMO},
595da85d 390#endif
af6f39b4 391#ifdef SPARC_BIENDIAN
1bb6aaad 392#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
af6f39b4 393 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
1bb6aaad 394#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
af6f39b4
DE		 395 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
396#endif
1bb6aaad 397#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
af6f39b4 398 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
fc23c14e
SC		 399#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
400 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
af6f39b4
DE		 401 {NULL, no_argument, NULL, 0}
402};
403size_t md_longopts_size = sizeof(md_longopts);
8dd07a84 404
af6f39b4
DE		 405int
406md_parse_option (c, arg)
407 int c;
408 char *arg;
7ab2e983 409{
54b9ebdd
DE		 410 /* We don't get a chance to initialize anything before we're called,
411 so handle that now. */
412 if (! default_init_p)
413 init_default_arch ();
414
af6f39b4
DE		 415 switch (c)
416 {
417 case OPTION_BUMP:
418 warn_on_bump = 1;
419 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
420 break;
7ab2e983 421
af6f39b4 422 case OPTION_XARCH:
54b9ebdd
DE		 423 /* This is for compatibility with Sun's assembler. */
424 if (strcmp (arg, "v8plus") != 0
425 && strcmp (arg, "v8plusa") != 0)
af6f39b4 426 {
48401fcf 427 as_bad (_("invalid architecture -xarch=%s"), arg);
af6f39b4
DE		 428 return 0;
429 }
8dd07a84 430
af6f39b4 431 /* fall through */
8dd07a84 432
af6f39b4
DE		 433 case 'A':
434 {
54b9ebdd
DE		 435 struct sparc_arch *sa;
436 enum sparc_opcode_arch_val opcode_arch;
d8b42b96 437
54b9ebdd 438 sa = lookup_arch (arg);
595da85d
DE		 439 if (sa == NULL
440 || ! sa->user_option_p)
af6f39b4 441 {
48401fcf 442 as_bad (_("invalid architecture -A%s"), arg);
af6f39b4
DE		 443 return 0;
444 }
d8b42b96 445
54b9ebdd
DE		 446 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
447 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
48401fcf 448 as_fatal (_("Bad opcode table, broken assembler."));
54b9ebdd
DE		 449
450 max_architecture = opcode_arch;
af6f39b4
DE		 451 architecture_requested = 1;
452 }
453 break;
d8b42b96 454
af6f39b4
DE		 455 case OPTION_SPARC:
456 /* Ignore -sparc, used by SunOS make default .s.o rule. */
457 break;
2b063e6d 458
af6f39b4
DE		 459 case OPTION_ENFORCE_ALIGNED_DATA:
460 enforce_aligned_data = 1;
461 break;
a87b3269 462
af6f39b4
DE		 463#ifdef SPARC_BIENDIAN
464 case OPTION_LITTLE_ENDIAN:
fc23c14e
SC		 465 target_big_endian = 0;
466 if (default_arch_type != sparclet)
467 as_fatal ("This target does not support -EL");
468 break;
469 case OPTION_LITTLE_ENDIAN_DATA:
470 target_little_endian_data = 1;
af6f39b4 471 target_big_endian = 0;
48401fcf 472 if (default_arch_type != sparc86x
48401fcf 473 && default_arch_type != v9)
fc23c14e 474 as_fatal ("This target does not support --little-endian-data");
af6f39b4
DE		 475 break;
476 case OPTION_BIG_ENDIAN:
477 target_big_endian = 1;
478 break;
479#endif
fecd2382 480
af6f39b4
DE		 481#ifdef OBJ_AOUT
482 case 'k':
483 sparc_pic_code = 1;
484 break;
485#endif
2b063e6d 486
af6f39b4 487#ifdef OBJ_ELF
595da85d
DE		 488 case OPTION_32:
489 case OPTION_64:
490 {
491 const char **list, **l;
492
493 sparc_arch_size = c == OPTION_32 ? 32 : 64;
494 list = bfd_target_list ();
495 for (l = list; *l != NULL; l++)
496 {
497 if (sparc_arch_size == 32)
498 {
499 if (strcmp (*l, "elf32-sparc") == 0)
500 break;
501 }
502 else
503 {
504 if (strcmp (*l, "elf64-sparc") == 0)
505 break;
506 }
507 }
508 if (*l == NULL)
48401fcf 509 as_fatal (_("No compiled in support for %d bit object file format"),
595da85d
DE		 510 sparc_arch_size);
511 free (list);
512 }
513 break;
514
1bb6aaad
RH		 515 case OPTION_TSO:
516 sparc_memory_model = MM_TSO;
517 break;
518
519 case OPTION_PSO:
520 sparc_memory_model = MM_PSO;
521 break;
522
523 case OPTION_RMO:
524 sparc_memory_model = MM_RMO;
525 break;
526
af6f39b4
DE		 527 case 'V':
528 print_version_id ();
529 break;
fecd2382 530
af6f39b4
DE		 531 case 'Q':
532 /* Qy - do emit .comment
533 Qn - do not emit .comment */
534 break;
ed94c2b8 535
af6f39b4
DE		 536 case 's':
537 /* use .stab instead of .stab.excl */
538 break;
584a0f78 539
af6f39b4
DE		 540 case 'q':
541 /* quick -- native assembler does fewer checks */
542 break;
355afbcd 543
af6f39b4
DE		 544 case 'K':
545 if (strcmp (arg, "PIC") != 0)
48401fcf 546 as_warn (_("Unrecognized option following -K"));
af6f39b4
DE		 547 else
548 sparc_pic_code = 1;
549 break;
550#endif
355afbcd 551
af6f39b4
DE		 552 default:
553 return 0;
355afbcd
KR		 554 }
555
af6f39b4
DE		 556 return 1;
557}
355afbcd 558
af6f39b4
DE		 559void
560md_show_usage (stream)
561 FILE *stream;
562{
54b9ebdd 563 const struct sparc_arch *arch;
355afbcd 564
595da85d
DE		 565 /* We don't get a chance to initialize anything before we're called,
566 so handle that now. */
567 if (! default_init_p)
568 init_default_arch ();
569
48401fcf 570 fprintf(stream, _("SPARC options:\n"));
54b9ebdd 571 for (arch = &sparc_arch_table[0]; arch->name; arch++)
355afbcd 572 {
54b9ebdd 573 if (arch != &sparc_arch_table[0])
af6f39b4 574 fprintf (stream, " | ");
595da85d
DE		 575 if (arch->user_option_p)
576 fprintf (stream, "-A%s", arch->name);
9b6a882e 577 }
48401fcf
TT		 578 fprintf (stream, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
579 fprintf (stream, _("\
af6f39b4
DE		 580 specify variant of SPARC architecture\n\
581-bump warn when assembler switches architectures\n\
582-sparc ignored\n\
48401fcf 583--enforce-aligned-data force .long, etc., to be aligned correctly\n"));
af6f39b4 584#ifdef OBJ_AOUT
48401fcf
TT		 585 fprintf (stream, _("\
586-k generate PIC\n"));
af6f39b4
DE		 587#endif
588#ifdef OBJ_ELF
48401fcf 589 fprintf (stream, _("\
595da85d 590-32 create 32 bit object file\n\
48401fcf
TT		 591-64 create 64 bit object file\n"));
592 fprintf (stream, _("\
593 [default is %d]\n"), default_arch_size);
594 fprintf (stream, _("\
1bb6aaad
RH		 595-TSO use Total Store Ordering\n\
596-PSO use Partial Store Ordering\n\
48401fcf
TT		 597-RMO use Relaxed Memory Ordering\n"));
598 fprintf (stream, _("\
599 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
600 fprintf (stream, _("\
af6f39b4
DE		 601-KPIC generate PIC\n\
602-V print assembler version number\n\
603-q ignored\n\
604-Qy, -Qn ignored\n\
48401fcf 605-s ignored\n"));
af6f39b4
DE		 606#endif
607#ifdef SPARC_BIENDIAN
48401fcf 608 fprintf (stream, _("\
af6f39b4 609-EL generate code for a little endian machine\n\
fc23c14e 610-EB generate code for a big endian machine\n\
04a92367 611--little-endian-data generate code for a machine having big endian\n\
fc23c14e 612 instructions and little endian data."));
af6f39b4
DE		 613#endif
614}
615\f
616/* sparc64 priviledged registers */
355afbcd 617
af6f39b4
DE		 618struct priv_reg_entry
619 {
620 char *name;
621 int regnum;
622 };
355afbcd 623
af6f39b4
DE		 624struct priv_reg_entry priv_reg_table[] =
625{
626 {"tpc", 0},
627 {"tnpc", 1},
628 {"tstate", 2},
629 {"tt", 3},
630 {"tick", 4},
631 {"tba", 5},
632 {"pstate", 6},
633 {"tl", 7},
634 {"pil", 8},
635 {"cwp", 9},
636 {"cansave", 10},
637 {"canrestore", 11},
638 {"cleanwin", 12},
639 {"otherwin", 13},
640 {"wstate", 14},
641 {"fq", 15},
642 {"ver", 31},
643 {"", -1}, /* end marker */
644};
355afbcd 645
1277cdda
RH		 646/* v9a specific asrs */
647
648struct priv_reg_entry v9a_asr_table[] =
649{
650 {"tick_cmpr", 23},
651 {"softint", 22},
652 {"set_softint", 20},
653 {"pic", 17},
654 {"pcr", 16},
655 {"gsr", 19},
656 {"dcr", 18},
657 {"clear_softint", 21},
658 {"", -1}, /* end marker */
659};
660
af6f39b4
DE		 661static int
662cmp_reg_entry (parg, qarg)
663 const PTR parg;
664 const PTR qarg;
665{
666 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
667 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
355afbcd 668
af6f39b4
DE		 669 return strcmp (q->name, p->name);
670}
671\f
672/* This function is called once, at assembler startup time. It should
673 set up all the tables, etc. that the MD part of the assembler will need. */
674
675void
676md_begin ()
677{
678 register const char *retval = NULL;
679 int lose = 0;
680 register unsigned int i = 0;
681
54b9ebdd
DE		 682 /* We don't get a chance to initialize anything before md_parse_option
683 is called, and it may not be called, so handle default initialization
684 now if not already done. */
685 if (! default_init_p)
686 init_default_arch ();
687
af6f39b4
DE		 688 op_hash = hash_new ();
689
48401fcf 690 while (i < (unsigned int) sparc_num_opcodes)
af6f39b4
DE		 691 {
692 const char *name = sparc_opcodes[i].name;
693 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
694 if (retval != NULL)
355afbcd 695 {
48401fcf 696 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
af6f39b4
DE		 697 sparc_opcodes[i].name, retval);
698 lose = 1;
355afbcd 699 }
af6f39b4 700 do
355afbcd 701 {
af6f39b4
DE		 702 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
703 {
48401fcf 704 fprintf (stderr, _("internal error: losing opcode: `%s' \"%s\"\n"),
af6f39b4
DE		 705 sparc_opcodes[i].name, sparc_opcodes[i].args);
706 lose = 1;
707 }
708 ++i;
fecd2382 709 }
48401fcf 710 while (i < (unsigned int) sparc_num_opcodes
af6f39b4
DE		 711 && !strcmp (sparc_opcodes[i].name, name));
712 }
428d312b 713
af6f39b4 714 if (lose)
48401fcf 715 as_fatal (_("Broken assembler. No assembly attempted."));
355afbcd 716
af6f39b4
DE		 717 for (i = '0'; i < '8'; ++i)
718 octal[i] = 1;
719 for (i = '0'; i <= '9'; ++i)
720 toHex[i] = i - '0';
721 for (i = 'a'; i <= 'f'; ++i)
722 toHex[i] = i + 10 - 'a';
723 for (i = 'A'; i <= 'F'; ++i)
724 toHex[i] = i + 10 - 'A';
355afbcd 725
af6f39b4
DE		 726 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
727 sizeof (priv_reg_table[0]), cmp_reg_entry);
355afbcd 728
af6f39b4
DE		 729 /* If -bump, record the architecture level at which we start issuing
730 warnings. The behaviour is different depending upon whether an
731 architecture was explicitly specified. If it wasn't, we issue warnings
732 for all upwards bumps. If it was, we don't start issuing warnings until
733 we need to bump beyond the requested architecture or when we bump between
734 conflicting architectures. */
355afbcd 735
af6f39b4
DE		 736 if (warn_on_bump
737 && architecture_requested)
355afbcd 738 {
af6f39b4
DE		 739 /* `max_architecture' records the requested architecture.
740 Issue warnings if we go above it. */
741 warn_after_architecture = max_architecture;
428d312b 742
af6f39b4
DE		 743 /* Find the highest architecture level that doesn't conflict with
744 the requested one. */
745 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
746 max_architecture > warn_after_architecture;
747 --max_architecture)
748 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
749 warn_after_architecture))
750 break;
751 }
752}
428d312b 753
af6f39b4 754/* Called after all assembly has been done. */
428d312b 755
af6f39b4
DE		 756void
757sparc_md_end ()
758{
54b9ebdd
DE		 759 if (sparc_arch_size == 64)
760 {
761 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
762 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
763 else
764 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
765 }
355afbcd
KR		 766 else
767 {
54b9ebdd
DE		 768 if (current_architecture == SPARC_OPCODE_ARCH_V9)
769 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
770 else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
771 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
772 else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
773 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
fc23c14e
SC		 774 else if (default_arch_type == sparc86x && target_little_endian_data)
775 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le);
54b9ebdd
DE		 776 else
777 {
778 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
779 be but for now it is (since that's the way it's always been
780 treated). */
781 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
782 }
af6f39b4 783 }
428d312b 784}
af6f39b4
DE		 785\f
786/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
355afbcd 787
af6f39b4
DE		 788static INLINE int
789in_signed_range (val, max)
790 bfd_signed_vma val, max;
355afbcd 791{
af6f39b4
DE		 792 if (max <= 0)
793 abort ();
794 if (val > max)
795 return 0;
796 if (val < ~max)
797 return 0;
798 return 1;
799}
355afbcd 800
54b9ebdd
DE		 801/* Return non-zero if VAL is in the range 0 to MAX. */
802
803static INLINE int
804in_unsigned_range (val, max)
805 bfd_vma val, max;
806{
807 if (val > max)
808 return 0;
809 return 1;
810}
811
af6f39b4
DE		 812/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
813 (e.g. -15 to +31). */
8dd07a84 814
af6f39b4
DE		 815static INLINE int
816in_bitfield_range (val, max)
817 bfd_signed_vma val, max;
8dd07a84 818{
af6f39b4
DE		 819 if (max <= 0)
820 abort ();
821 if (val > max)
822 return 0;
823 if (val < ~(max >> 1))
824 return 0;
825 return 1;
8dd07a84
ILT		 826}
827
af6f39b4
DE		 828static int
829sparc_ffs (mask)
830 unsigned int mask;
355afbcd 831{
af6f39b4 832 int i;
355afbcd 833
af6f39b4
DE		 834 if (mask == 0)
835 return -1;
355afbcd 836
af6f39b4
DE		 837 for (i = 0; (mask & 1) == 0; ++i)
838 mask >>= 1;
839 return i;
c999fd9f 840}
fecd2382 841
af6f39b4
DE		 842/* Implement big shift right. */
843static bfd_vma
844BSR (val, amount)
845 bfd_vma val;
846 int amount;
355afbcd 847{
af6f39b4 848 if (sizeof (bfd_vma) <= 4 && amount >= 32)
48401fcf 849 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
af6f39b4 850 return val >> amount;
c999fd9f 851}
af6f39b4
DE		 852\f
853/* For communication between sparc_ip and get_expression. */
854static char *expr_end;
fecd2382 855
af6f39b4
DE		 856/* For communication between md_assemble and sparc_ip. */
857static int special_case;
8dd07a84 858
af6f39b4
DE		 859/* Values for `special_case'.
860 Instructions that require wierd handling because they're longer than
861 4 bytes. */
862#define SPECIAL_CASE_NONE 0
863#define SPECIAL_CASE_SET 1
864#define SPECIAL_CASE_SETSW 2
865#define SPECIAL_CASE_SETX 3
866/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
867#define SPECIAL_CASE_FDIV 4
8dd07a84 868
af6f39b4
DE		 869/* Bit masks of various insns. */
870#define NOP_INSN 0x01000000
871#define OR_INSN 0x80100000
872#define FMOVS_INSN 0x81A00020
873#define SETHI_INSN 0x01000000
874#define SLLX_INSN 0x81281000
875#define SRA_INSN 0x81380000
8dd07a84 876
af6f39b4
DE		 877/* The last instruction to be assembled. */
878static const struct sparc_opcode *last_insn;
879/* The assembled opcode of `last_insn'. */
880static unsigned long last_opcode;
881\f
882/* Main entry point to assemble one instruction. */
883
884void
885md_assemble (str)
886 char *str;
8dd07a84 887{
af6f39b4 888 const struct sparc_opcode *insn;
355afbcd
KR		 889
890 know (str);
af6f39b4 891 special_case = SPECIAL_CASE_NONE;
ed94c2b8
ILT		 892 sparc_ip (str, &insn);
893
9f6da653
DE		 894 /* We warn about attempts to put a floating point branch in a delay slot,
895 unless the delay slot has been annulled. */
ed94c2b8
ILT		 896 if (insn != NULL
897 && last_insn != NULL
898 && (insn->flags & F_FBR) != 0
9f6da653
DE		 899 && (last_insn->flags & F_DELAYED) != 0
900 /* ??? This test isn't completely accurate. We assume anything with
901 F_{UNBR,CONDBR,FBR} set is annullable. */
902 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
903 || (last_opcode & ANNUL) == 0))
48401fcf 904 as_warn (_("FP branch in delay slot"));
ed94c2b8
ILT		 905
906 /* SPARC before v9 requires a nop instruction between a floating
907 point instruction and a floating point branch. We insert one
908 automatically, with a warning. */
909 if (max_architecture < SPARC_OPCODE_ARCH_V9
910 && insn != NULL
911 && last_insn != NULL
912 && (insn->flags & F_FBR) != 0
913 && (last_insn->flags & F_FLOAT) != 0)
914 {
2b063e6d
ILT		 915 struct sparc_it nop_insn;
916
917 nop_insn.opcode = NOP_INSN;
918 nop_insn.reloc = BFD_RELOC_NONE;
919 output_insn (insn, &nop_insn);
48401fcf 920 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
ed94c2b8 921 }
355afbcd 922
2b063e6d 923 switch (special_case)
355afbcd 924 {
af6f39b4 925 case SPECIAL_CASE_NONE:
2b063e6d
ILT		 926 /* normal insn */
927 output_insn (insn, &the_insn);
928 break;
355afbcd 929
2b063e6d
ILT		 930 case SPECIAL_CASE_SET:
931 {
932 int need_hi22_p = 0;
355afbcd 933
2b063e6d
ILT		 934 /* "set" is not defined for negative numbers in v9: it doesn't yield
935 what you expect it to. */
936 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)
937 && the_insn.exp.X_op == O_constant)
938 {
939 if (the_insn.exp.X_add_number < 0)
48401fcf
TT		 940 as_warn (_("set: used with negative number"));
941 else if (the_insn.exp.X_add_number > (offsetT) 0xffffffff)
942 as_warn (_("set: number larger than 4294967295"));
2b063e6d 943 }
428d312b 944
2b063e6d
ILT		 945 /* See if operand is absolute and small; skip sethi if so. */
946 if (the_insn.exp.X_op != O_constant
947 || the_insn.exp.X_add_number >= (1 << 12)
948 || the_insn.exp.X_add_number < -(1 << 12))
949 {
950 output_insn (insn, &the_insn);
951 need_hi22_p = 1;
952 }
953 /* See if operand has no low-order bits; skip OR if so. */
954 if (the_insn.exp.X_op != O_constant
955 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
956 || ! need_hi22_p)
957 {
958 int rd = (the_insn.opcode & RD (~0)) >> 25;
959 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
960 | RD (rd)
961 | IMMED
962 | (the_insn.exp.X_add_number
963 & (need_hi22_p ? 0x3ff : 0x1fff)));
964 the_insn.reloc = (the_insn.exp.X_op != O_constant
965 ? BFD_RELOC_LO10
966 : BFD_RELOC_NONE);
967 output_insn (insn, &the_insn);
968 }
969 break;
970 }
ed94c2b8 971
2b063e6d
ILT		 972 case SPECIAL_CASE_SETSW:
973 {
974 /* FIXME: Not finished. */
975 break;
976 }
355afbcd 977
2b063e6d
ILT		 978 case SPECIAL_CASE_SETX:
979 {
980#define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
981 int upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
982 int lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
983#undef SIGNEXT32
984 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
985 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
986 /* Output directly to dst reg if lower 32 bits are all zero. */
987 int upper_dstreg = (the_insn.exp.X_op == O_constant
988 && lower32 == 0) ? dstreg : tmpreg;
989 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
990
991 /* The tmp reg should not be the dst reg. */
992 if (tmpreg == dstreg)
48401fcf 993 as_warn (_("setx: temporary register same as destination register"));
2b063e6d
ILT		 994
995 /* Reset X_add_number, we've extracted it as upper32/lower32.
996 Otherwise fixup_segment will complain about not being able to
997 write an 8 byte number in a 4 byte field. */
998 the_insn.exp.X_add_number = 0;
999
1000 /* ??? Obviously there are other optimizations we can do
1001 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1002 doing some of these. Later. If you do change things, try to
1003 change all of this to be table driven as well. */
1004
1005 /* What to output depends on the number if it's constant.
1006 Compute that first, then output what we've decided upon. */
1007 if (the_insn.exp.X_op != O_constant)
1008 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1009 else
1010 {
1011 /* Only need hh22 if `or' insn can't handle constant. */
1012 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1013 need_hh22_p = 1;
1014
1015 /* Does bottom part (after sethi) have bits? */
1016 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1017 /* No hh22, but does upper32 still have bits we can't set
1018 from lower32? */
1019 || (! need_hh22_p
1020 && upper32 != 0
1021 && (upper32 != -1 || lower32 >= 0)))
1022 need_hm10_p = 1;
1023
1024 /* If the lower half is all zero, we build the upper half directly
1025 into the dst reg. */
1026 if (lower32 != 0
1027 /* Need lower half if number is zero. */
1028 || (! need_hh22_p && ! need_hm10_p))
1029 {
1030 /* No need for sethi if `or' insn can handle constant. */
1031 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1032 /* Note that we can't use a negative constant in the `or'
1033 insn unless the upper 32 bits are all ones. */
1034 || (lower32 < 0 && upper32 != -1))
1035 need_hi22_p = 1;
1036
1037 /* Does bottom part (after sethi) have bits? */
1038 if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1039 /* No sethi. */
1040 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1041 /* Need `or' if we didn't set anything else. */
1042 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1043 need_lo10_p = 1;
1044 }
1045 }
355afbcd 1046
2b063e6d
ILT		 1047 if (need_hh22_p)
1048 {
1049 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1050 | ((upper32 >> 10) & 0x3fffff));
1051 the_insn.reloc = (the_insn.exp.X_op != O_constant
1052 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1053 output_insn (insn, &the_insn);
1054 }
1055
1056 if (need_hm10_p)
1057 {
1058 the_insn.opcode = (OR_INSN
1059 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1060 | RD (upper_dstreg)
1061 | IMMED
1062 | (upper32
1063 & (need_hh22_p ? 0x3ff : 0x1fff)));
1064 the_insn.reloc = (the_insn.exp.X_op != O_constant
1065 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1066 output_insn (insn, &the_insn);
1067 }
1068
1069 if (need_hi22_p)
1070 {
1071 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1072 | ((lower32 >> 10) & 0x3fffff));
1073 the_insn.reloc = BFD_RELOC_HI22;
1074 output_insn (insn, &the_insn);
1075 }
1076
1077 if (need_lo10_p)
1078 {
1079 /* FIXME: One nice optimization to do here is to OR the low part
1080 with the highpart if hi22 isn't needed and the low part is
1081 positive. */
1082 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1083 | RD (dstreg)
1084 | IMMED
1085 | (lower32
1086 & (need_hi22_p ? 0x3ff : 0x1fff)));
1087 the_insn.reloc = BFD_RELOC_LO10;
1088 output_insn (insn, &the_insn);
1089 }
1090
1091 /* If we needed to build the upper part, shift it into place. */
1092 if (need_hh22_p || need_hm10_p)
1093 {
1094 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1095 | IMMED | 32);
1096 the_insn.reloc = BFD_RELOC_NONE;
1097 output_insn (insn, &the_insn);
1098 }
1099
1100 /* If we needed to build both upper and lower parts, OR them together. */
1101 if ((need_hh22_p || need_hm10_p)
1102 && (need_hi22_p || need_lo10_p))
1103 {
1104 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1105 | RD (dstreg));
1106 the_insn.reloc = BFD_RELOC_NONE;
1107 output_insn (insn, &the_insn);
1108 }
1109 /* We didn't need both regs, but we may have to sign extend lower32. */
1110 else if (need_hi22_p && upper32 == -1)
1111 {
1112 the_insn.opcode = (SRA_INSN | RS1 (dstreg) | RD (dstreg)
1113 | IMMED | 0);
1114 the_insn.reloc = BFD_RELOC_NONE;
1115 output_insn (insn, &the_insn);
1116 }
1117 break;
1118 }
1119
1120 case SPECIAL_CASE_FDIV:
1121 {
1122 int rd = (the_insn.opcode >> 25) & 0x1f;
1123
1124 output_insn (insn, &the_insn);
1125
1126 /* According to information leaked from Sun, the "fdiv" instructions
1127 on early SPARC machines would produce incorrect results sometimes.
1128 The workaround is to add an fmovs of the destination register to
1129 itself just after the instruction. This was true on machines
1130 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1131 assert (the_insn.reloc == BFD_RELOC_NONE);
1132 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1133 output_insn (insn, &the_insn);
1134 break;
1135 }
355afbcd
KR		 1136
1137 default:
48401fcf 1138 as_fatal (_("failed special case insn sanity check"));
355afbcd 1139 }
9b6a882e 1140}
355afbcd 1141
af6f39b4 1142/* Subroutine of md_assemble to do the actual parsing. */
6df07e7f 1143
af6f39b4
DE		 1144static void
1145sparc_ip (str, pinsn)
1146 char *str;
1147 const struct sparc_opcode **pinsn;
fecd2382 1148{
355afbcd
KR		 1149 char *error_message = "";
1150 char *s;
1151 const char *args;
1152 char c;
a7aa7a2b 1153 const struct sparc_opcode *insn;
355afbcd
KR		 1154 char *argsStart;
1155 unsigned long opcode;
1156 unsigned int mask = 0;
1157 int match = 0;
1158 int comma = 0;
6df07e7f 1159 int v9_arg_p;
355afbcd 1160
b9089139
RH		 1161 s = str;
1162 if (islower ((unsigned char) *s))
1163 {
1164 do
1165 ++s;
1166 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s));
1167 }
6df07e7f 1168
355afbcd
KR		 1169 switch (*s)
1170 {
355afbcd
KR		 1171 case '\0':
1172 break;
1173
1174 case ',':
1175 comma = 1;
1176
1177 /*FALLTHROUGH */
1178
1179 case ' ':
1180 *s++ = '\0';
1181 break;
1182
1183 default:
48401fcf 1184 as_fatal (_("Unknown opcode: `%s'"), str);
355afbcd 1185 }
a7aa7a2b 1186 insn = (struct sparc_opcode *) hash_find (op_hash, str);
ed94c2b8 1187 *pinsn = insn;
a7aa7a2b 1188 if (insn == NULL)
355afbcd 1189 {
48401fcf 1190 as_bad (_("Unknown opcode: `%s'"), str);
355afbcd
KR		 1191 return;
1192 }
1193 if (comma)
1194 {
1195 *--s = ',';
1196 }
6df07e7f 1197
355afbcd
KR		 1198 argsStart = s;
1199 for (;;)
1200 {
1201 opcode = insn->match;
1202 memset (&the_insn, '\0', sizeof (the_insn));
428d312b 1203 the_insn.reloc = BFD_RELOC_NONE;
6df07e7f 1204 v9_arg_p = 0;
355afbcd
KR		 1205
1206 /*
8fc0776d
JW		 1207 * Build the opcode, checking as we go to make
1208 * sure that the operands match
1209 */
355afbcd
KR		 1210 for (args = insn->args;; ++args)
1211 {
1212 switch (*args)
1213 {
355afbcd
KR		 1214 case 'K':
1215 {
7766838e 1216 int kmask = 0;
ed9638af
KR		 1217
1218 /* Parse a series of masks. */
1219 if (*s == '#')
355afbcd 1220 {
ed9638af 1221 while (*s == '#')
355afbcd 1222 {
6df07e7f
DE		 1223 int mask;
1224
1225 if (! parse_keyword_arg (sparc_encode_membar, &s,
1226 &mask))
ed9638af 1227 {
48401fcf 1228 error_message = _(": invalid membar mask name");
ed9638af
KR		 1229 goto error;
1230 }
6df07e7f
DE		 1231 kmask |= mask;
1232 while (*s == ' ') { ++s; continue; }
1233 if (*s == '|' || *s == '+')
ed9638af 1234 ++s;
6df07e7f 1235 while (*s == ' ') { ++s; continue; }
355afbcd 1236 }
ed9638af 1237 }
c999fd9f 1238 else
ed9638af 1239 {
6df07e7f
DE		 1240 if (! parse_const_expr_arg (&s, &kmask))
1241 {
48401fcf 1242 error_message = _(": invalid membar mask expression");
6df07e7f
DE		 1243 goto error;
1244 }
1245 if (kmask < 0 || kmask > 127)
ed9638af 1246 {
48401fcf 1247 error_message = _(": invalid membar mask number");
ed9638af 1248 goto error;
355afbcd 1249 }
355afbcd 1250 }
c999fd9f 1251
6df07e7f 1252 opcode |= MEMBAR (kmask);
355afbcd
KR		 1253 continue;
1254 }
1255
1256 case '*':
ed9638af 1257 {
6df07e7f 1258 int fcn = 0;
355afbcd 1259
ed9638af
KR		 1260 /* Parse a prefetch function. */
1261 if (*s == '#')
1262 {
6df07e7f 1263 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
ed9638af 1264 {
48401fcf 1265 error_message = _(": invalid prefetch function name");
ed9638af
KR		 1266 goto error;
1267 }
1268 }
6df07e7f 1269 else
ed9638af 1270 {
6df07e7f 1271 if (! parse_const_expr_arg (&s, &fcn))
ed9638af 1272 {
48401fcf 1273 error_message = _(": invalid prefetch function expression");
6df07e7f 1274 goto error;
ed9638af 1275 }
6df07e7f 1276 if (fcn < 0 || fcn > 31)
ed9638af 1277 {
48401fcf 1278 error_message = _(": invalid prefetch function number");
ed9638af
KR		 1279 goto error;
1280 }
1281 }
6df07e7f 1282 opcode |= RD (fcn);
ed9638af
KR		 1283 continue;
1284 }
355afbcd
KR		 1285
1286 case '!':
1287 case '?':
6df07e7f 1288 /* Parse a sparc64 privileged register. */
355afbcd
KR		 1289 if (*s == '%')
1290 {
1291 struct priv_reg_entry *p = priv_reg_table;
7766838e 1292 unsigned int len = 9999999; /* init to make gcc happy */
355afbcd
KR		 1293
1294 s += 1;
1295 while (p->name[0] > s[0])
1296 p++;
1297 while (p->name[0] == s[0])
1298 {
1299 len = strlen (p->name);
1300 if (strncmp (p->name, s, len) == 0)
1301 break;
1302 p++;
1303 }
1304 if (p->name[0] != s[0])
1305 {
48401fcf 1306 error_message = _(": unrecognizable privileged register");
355afbcd
KR		 1307 goto error;
1308 }
1309 if (*args == '?')
1310 opcode |= (p->regnum << 14);
1311 else
1312 opcode |= (p->regnum << 25);
1313 s += len;
1314 continue;
1315 }
1316 else
1317 {
48401fcf 1318 error_message = _(": unrecognizable privileged register");
355afbcd
KR		 1319 goto error;
1320 }
680227f3 1321
1277cdda
RH		 1322 case '_':
1323 case '/':
1324 /* Parse a v9a ancillary state register. */
1325 if (*s == '%')
1326 {
1327 struct priv_reg_entry *p = v9a_asr_table;
1328 unsigned int len = 9999999; /* init to make gcc happy */
1329
1330 s += 1;
1331 while (p->name[0] > s[0])
1332 p++;
1333 while (p->name[0] == s[0])
1334 {
1335 len = strlen (p->name);
1336 if (strncmp (p->name, s, len) == 0)
1337 break;
1338 p++;
1339 }
1340 if (p->name[0] != s[0])
1341 {
48401fcf 1342 error_message = _(": unrecognizable v9a ancillary state register");
1277cdda
RH		 1343 goto error;
1344 }
1345 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1346 {
48401fcf 1347 error_message = _(": rd on write only ancillary state register");
1277cdda
RH		 1348 goto error;
1349 }
1350 if (*args == '/')
1351 opcode |= (p->regnum << 14);
1352 else
1353 opcode |= (p->regnum << 25);
1354 s += len;
1355 continue;
1356 }
1357 else
1358 {
48401fcf 1359 error_message = _(": unrecognizable v9a ancillary state register");
1277cdda
RH		 1360 goto error;
1361 }
1362
355afbcd
KR		 1363 case 'M':
1364 case 'm':
1365 if (strncmp (s, "%asr", 4) == 0)
1366 {
1367 s += 4;
680227f3 1368
48401fcf 1369 if (isdigit ((unsigned char) *s))
355afbcd
KR		 1370 {
1371 long num = 0;
1372
48401fcf 1373 while (isdigit ((unsigned char) *s))
355afbcd
KR		 1374 {
1375 num = num * 10 + *s - '0';
1376 ++s;
1377 }
1378
e86d5cf3 1379 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
355afbcd 1380 {
e86d5cf3
DE		 1381 if (num < 16 || 31 < num)
1382 {
48401fcf 1383 error_message = _(": asr number must be between 16 and 31");
e86d5cf3
DE		 1384 goto error;
1385 }
1386 }
1387 else
1388 {
2cb1807e 1389 if (num < 0 || 31 < num)
e86d5cf3 1390 {
48401fcf 1391 error_message = _(": asr number must be between 0 and 31");
e86d5cf3
DE		 1392 goto error;
1393 }
1394 }
355afbcd
KR		 1395
1396 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1397 continue;
1398 }
1399 else
1400 {
48401fcf 1401 error_message = _(": expecting %asrN");
355afbcd 1402 goto error;
e86d5cf3
DE		 1403 }
1404 } /* if %asr */
355afbcd
KR		 1405 break;
1406
355afbcd 1407 case 'I':
125f0b0d 1408 the_insn.reloc = BFD_RELOC_SPARC_11;
355afbcd
KR		 1409 goto immediate;
1410
1411 case 'j':
125f0b0d 1412 the_insn.reloc = BFD_RELOC_SPARC_10;
355afbcd
KR		 1413 goto immediate;
1414
8dd07a84
ILT		 1415 case 'X':
1416 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1417 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1418 the_insn.reloc = BFD_RELOC_SPARC_5;
1419 else
1420 the_insn.reloc = BFD_RELOC_SPARC13;
1421 /* These fields are unsigned, but for upward compatibility,
1422 allow negative values as well. */
8dd07a84
ILT		 1423 goto immediate;
1424
1425 case 'Y':
1426 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1427 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1428 the_insn.reloc = BFD_RELOC_SPARC_6;
1429 else
1430 the_insn.reloc = BFD_RELOC_SPARC13;
1431 /* These fields are unsigned, but for upward compatibility,
1432 allow negative values as well. */
8dd07a84
ILT		 1433 goto immediate;
1434
355afbcd 1435 case 'k':
125f0b0d 1436 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
355afbcd
KR		 1437 the_insn.pcrel = 1;
1438 goto immediate;
1439
1440 case 'G':
125f0b0d 1441 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
355afbcd
KR		 1442 the_insn.pcrel = 1;
1443 goto immediate;
1444
1445 case 'N':
1446 if (*s == 'p' && s[1] == 'n')
1447 {
1448 s += 2;
1449 continue;
1450 }
1451 break;
1452
1453 case 'T':
1454 if (*s == 'p' && s[1] == 't')
1455 {
1456 s += 2;
1457 continue;
1458 }
1459 break;
1460
1461 case 'z':
1462 if (*s == ' ')
1463 {
1464 ++s;
1465 }
0d44b3d1 1466 if (strncmp (s, "%icc", 4) == 0)
355afbcd 1467 {
0d44b3d1 1468 s += 4;
355afbcd
KR		 1469 continue;
1470 }
1471 break;
1472
1473 case 'Z':
1474 if (*s == ' ')
1475 {
1476 ++s;
1477 }
0d44b3d1 1478 if (strncmp (s, "%xcc", 4) == 0)
355afbcd 1479 {
0d44b3d1 1480 s += 4;
355afbcd
KR		 1481 continue;
1482 }
1483 break;
1484
1485 case '6':
1486 if (*s == ' ')
1487 {
1488 ++s;
1489 }
0d44b3d1 1490 if (strncmp (s, "%fcc0", 5) == 0)
355afbcd 1491 {
0d44b3d1 1492 s += 5;
355afbcd
KR		 1493 continue;
1494 }
1495 break;
1496
1497 case '7':
1498 if (*s == ' ')
1499 {
1500 ++s;
1501 }
0d44b3d1 1502 if (strncmp (s, "%fcc1", 5) == 0)
355afbcd 1503 {
0d44b3d1 1504 s += 5;
355afbcd
KR		 1505 continue;
1506 }
1507 break;
1508
1509 case '8':
1510 if (*s == ' ')
1511 {
1512 ++s;
1513 }
0d44b3d1 1514 if (strncmp (s, "%fcc2", 5) == 0)
355afbcd 1515 {
0d44b3d1 1516 s += 5;
355afbcd
KR		 1517 continue;
1518 }
1519 break;
1520
1521 case '9':
1522 if (*s == ' ')
1523 {
1524 ++s;
1525 }
0d44b3d1 1526 if (strncmp (s, "%fcc3", 5) == 0)
355afbcd 1527 {
0d44b3d1 1528 s += 5;
355afbcd
KR		 1529 continue;
1530 }
1531 break;
1532
1533 case 'P':
1534 if (strncmp (s, "%pc", 3) == 0)
1535 {
1536 s += 3;
1537 continue;
1538 }
1539 break;
1540
1541 case 'W':
1542 if (strncmp (s, "%tick", 5) == 0)
1543 {
1544 s += 5;
1545 continue;
1546 }
1547 break;
355afbcd
KR		 1548
1549 case '\0': /* end of args */
1550 if (*s == '\0')
1551 {
1552 match = 1;
1553 }
1554 break;
1555
1556 case '+':
1557 if (*s == '+')
1558 {
1559 ++s;
1560 continue;
1561 }
1562 if (*s == '-')
1563 {
1564 continue;
1565 }
1566 break;
1567
1568 case '[': /* these must match exactly */
1569 case ']':
1570 case ',':
1571 case ' ':
1572 if (*s++ == *args)
1573 continue;
1574 break;
1575
1576 case '#': /* must be at least one digit */
48401fcf 1577 if (isdigit ((unsigned char) *s++))
355afbcd 1578 {
48401fcf 1579 while (isdigit ((unsigned char) *s))
355afbcd
KR		 1580 {
1581 ++s;
1582 }
1583 continue;
1584 }
1585 break;
1586
1587 case 'C': /* coprocessor state register */
1588 if (strncmp (s, "%csr", 4) == 0)
1589 {
1590 s += 4;
1591 continue;
1592 }
1593 break;
1594
1595 case 'b': /* next operand is a coprocessor register */
1596 case 'c':
1597 case 'D':
48401fcf 1598 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
355afbcd
KR		 1599 {
1600 mask = *s++;
48401fcf 1601 if (isdigit ((unsigned char) *s))
355afbcd
KR		 1602 {
1603 mask = 10 * (mask - '0') + (*s++ - '0');
1604 if (mask >= 32)
1605 {
1606 break;
1607 }
1608 }
1609 else
1610 {
1611 mask -= '0';
1612 }
1613 switch (*args)
1614 {
1615
1616 case 'b':
1617 opcode |= mask << 14;
1618 continue;
1619
1620 case 'c':
1621 opcode |= mask;
1622 continue;
1623
1624 case 'D':
1625 opcode |= mask << 25;
1626 continue;
1627 }
1628 }
1629 break;
1630
1631 case 'r': /* next operand must be a register */
ed94c2b8 1632 case 'O':
355afbcd
KR		 1633 case '1':
1634 case '2':
1635 case 'd':
1636 if (*s++ == '%')
1637 {
1638 switch (c = *s++)
1639 {
1640
1641 case 'f': /* frame pointer */
1642 if (*s++ == 'p')
1643 {
1644 mask = 0x1e;
1645 break;
1646 }
1647 goto error;
1648
1649 case 'g': /* global register */
1650 if (isoctal (c = *s++))
1651 {
1652 mask = c - '0';
1653 break;
1654 }
1655 goto error;
1656
1657 case 'i': /* in register */
1658 if (isoctal (c = *s++))
1659 {
1660 mask = c - '0' + 24;
1661 break;
1662 }
1663 goto error;
1664
1665 case 'l': /* local register */
1666 if (isoctal (c = *s++))
1667 {
1668 mask = (c - '0' + 16);
1669 break;
1670 }
1671 goto error;
1672
1673 case 'o': /* out register */
1674 if (isoctal (c = *s++))
1675 {
1676 mask = (c - '0' + 8);
1677 break;
1678 }
1679 goto error;
1680
1681 case 's': /* stack pointer */
1682 if (*s++ == 'p')
1683 {
1684 mask = 0xe;
1685 break;
1686 }
1687 goto error;
1688
1689 case 'r': /* any register */
48401fcf 1690 if (!isdigit ((unsigned char) (c = *s++)))
355afbcd
KR		 1691 {
1692 goto error;
1693 }
1694 /* FALLTHROUGH */
1695 case '0':
1696 case '1':
1697 case '2':
1698 case '3':
1699 case '4':
1700 case '5':
1701 case '6':
1702 case '7':
1703 case '8':
1704 case '9':
48401fcf 1705 if (isdigit ((unsigned char) *s))
355afbcd
KR		 1706 {
1707 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
680227f3 1708 {
680227f3
KR		 1709 goto error;
1710 }
355afbcd
KR		 1711 }
1712 else
1713 {
1714 c -= '0';
1715 }
1716 mask = c;
1717 break;
1718
1719 default:
1720 goto error;
1721 }
6df07e7f
DE		 1722
1723 /* Got the register, now figure out where
1724 it goes in the opcode. */
355afbcd
KR		 1725 switch (*args)
1726 {
355afbcd
KR		 1727 case '1':
1728 opcode |= mask << 14;
1729 continue;
1730
1731 case '2':
1732 opcode |= mask;
1733 continue;
1734
1735 case 'd':
1736 opcode |= mask << 25;
1737 continue;
1738
1739 case 'r':
1740 opcode |= (mask << 25) | (mask << 14);
1741 continue;
ed94c2b8
ILT		 1742
1743 case 'O':
1744 opcode |= (mask << 25) | (mask << 0);
1745 continue;
355afbcd
KR		 1746 }
1747 }
1748 break;
1749
1750 case 'e': /* next operand is a floating point register */
1751 case 'v':
1752 case 'V':
1753
1754 case 'f':
1755 case 'B':
1756 case 'R':
1757
1758 case 'g':
1759 case 'H':
1760 case 'J':
1761 {
1762 char format;
1763
1764 if (*s++ == '%'
355afbcd 1765 && ((format = *s) == 'f')
48401fcf 1766 && isdigit ((unsigned char) *++s))
355afbcd 1767 {
48401fcf 1768 for (mask = 0; isdigit ((unsigned char) *s); ++s)
355afbcd
KR		 1769 {
1770 mask = 10 * mask + (*s - '0');
1771 } /* read the number */
1772
1773 if ((*args == 'v'
1774 || *args == 'B'
1775 || *args == 'H')
1776 && (mask & 1))
1777 {
1778 break;
1779 } /* register must be even numbered */
1780
1781 if ((*args == 'V'
1782 || *args == 'R'
1783 || *args == 'J')
1784 && (mask & 3))
1785 {
1786 break;
1787 } /* register must be multiple of 4 */
1788
125f0b0d 1789 if (mask >= 64)
355afbcd 1790 {
8dd07a84 1791 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
48401fcf 1792 error_message = _(": There are only 64 f registers; [0-63]");
6df07e7f 1793 else
48401fcf 1794 error_message = _(": There are only 32 f registers; [0-31]");
125f0b0d
KR		 1795 goto error;
1796 } /* on error */
6df07e7f 1797 else if (mask >= 32)
125f0b0d 1798 {
8dd07a84 1799 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
6df07e7f
DE		 1800 {
1801 v9_arg_p = 1;
1802 mask -= 31; /* wrap high bit */
1803 }
1804 else
1805 {
48401fcf 1806 error_message = _(": There are only 32 f registers; [0-31]");
6df07e7f
DE		 1807 goto error;
1808 }
1809 }
125f0b0d
KR		 1810 }
1811 else
1812 {
1813 break;
1814 } /* if not an 'f' register. */
355afbcd
KR		 1815
1816 switch (*args)
1817 {
355afbcd
KR		 1818 case 'v':
1819 case 'V':
1820 case 'e':
1821 opcode |= RS1 (mask);
1822 continue;
1823
1824
1825 case 'f':
1826 case 'B':
1827 case 'R':
1828 opcode |= RS2 (mask);
1829 continue;
1830
1831 case 'g':
1832 case 'H':
1833 case 'J':
1834 opcode |= RD (mask);
1835 continue;
1836 } /* pack it in. */
1837
1838 know (0);
1839 break;
1840 } /* float arg */
1841
1842 case 'F':
1843 if (strncmp (s, "%fsr", 4) == 0)
1844 {
1845 s += 4;
1846 continue;
1847 }
1848 break;
1849
2b063e6d
ILT		 1850 case '0': /* 64 bit immediate (setx insn) */
1851 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
1852 goto immediate;
1853
355afbcd 1854 case 'h': /* high 22 bits */
428d312b 1855 the_insn.reloc = BFD_RELOC_HI22;
355afbcd
KR		 1856 goto immediate;
1857
1858 case 'l': /* 22 bit PC relative immediate */
428d312b 1859 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
355afbcd
KR		 1860 the_insn.pcrel = 1;
1861 goto immediate;
1862
1863 case 'L': /* 30 bit immediate */
428d312b 1864 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
355afbcd
KR		 1865 the_insn.pcrel = 1;
1866 goto immediate;
1867
1868 case 'n': /* 22 bit immediate */
428d312b 1869 the_insn.reloc = BFD_RELOC_SPARC22;
355afbcd
KR		 1870 goto immediate;
1871
1872 case 'i': /* 13 bit immediate */
7ab2e983 1873 the_insn.reloc = BFD_RELOC_SPARC13;
355afbcd 1874
54b9ebdd 1875 /* fallthrough */
355afbcd
KR		 1876
1877 immediate:
1878 if (*s == ' ')
1879 s++;
54b9ebdd
DE		 1880
1881 /* Check for %hi, etc. */
355afbcd
KR		 1882 if (*s == '%')
1883 {
54b9ebdd
DE		 1884 static struct ops {
1885 /* The name as it appears in assembler. */
1886 char *name;
1887 /* strlen (name), precomputed for speed */
1888 int len;
1889 /* The reloc this pseudo-op translates to. */
1890 int reloc;
1891 /* Non-zero if for v9 only. */
1892 int v9_p;
1893 /* Non-zero if can be used in pc-relative contexts. */
1894 int pcrel_p;/*FIXME:wip*/
1895 } ops[] = {
1896 /* hix/lox must appear before hi/lo so %hix won't be
1897 mistaken for %hi. */
1898 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
1899 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
1900 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
1901 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
1902 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
1903 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
1904 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
1905 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
1906 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
1907 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
1908 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
1909 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
1910 { NULL }
1911 };
1912 struct ops *o;
1913
1914 for (o = ops; o->name; o++)
1915 if (strncmp (s + 1, o->name, o->len) == 0)
1916 break;
1917 if (o->name == NULL)
355afbcd 1918 break;
54b9ebdd
DE		 1919
1920 the_insn.reloc = o->reloc;
1921 s += o->len + 1;
1922 v9_arg_p = o->v9_p;
355afbcd 1923 }
54b9ebdd 1924
af6f39b4 1925 /* Note that if the get_expression() fails, we will still
9b6a882e
KR		 1926 have created U entries in the symbol table for the
1927 'symbols' in the input string. Try not to create U
1928 symbols for registers, etc. */
355afbcd 1929 {
9b6a882e
KR		 1930 /* This stuff checks to see if the expression ends in
1931 +%reg. If it does, it removes the register from
1932 the expression, and re-sets 's' to point to the
1933 right place. */
355afbcd
KR		 1934
1935 char *s1;
1936
2b063e6d 1937 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ;
355afbcd 1938
48401fcf 1939 if (s1 != s && isdigit ((unsigned char) s1[-1]))
355afbcd
KR		 1940 {
1941 if (s1[-2] == '%' && s1[-3] == '+')
1942 {
1943 s1 -= 3;
1944 *s1 = '\0';
af6f39b4 1945 (void) get_expression (s);
355afbcd
KR		 1946 *s1 = '+';
1947 s = s1;
1948 continue;
1949 }
1950 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
1951 {
1952 s1 -= 4;
1953 *s1 = '\0';
af6f39b4 1954 (void) get_expression (s);
355afbcd
KR		 1955 *s1 = '+';
1956 s = s1;
1957 continue;
1958 }
1959 }
1960 }
af6f39b4 1961 (void) get_expression (s);
355afbcd
KR		 1962 s = expr_end;
1963
54b9ebdd 1964 /* Check for constants that don't require emitting a reloc. */
9b6a882e
KR		 1965 if (the_insn.exp.X_op == O_constant
1966 && the_insn.exp.X_add_symbol == 0
1967 && the_insn.exp.X_op_symbol == 0)
1968 {
7ab2e983
ILT		 1969 /* For pc-relative call instructions, we reject
1970 constants to get better code. */
1971 if (the_insn.pcrel
1972 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
54b9ebdd 1973 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
7ab2e983 1974 {
48401fcf 1975 error_message = _(": PC-relative operand can't be a constant");
7ab2e983
ILT		 1976 goto error;
1977 }
9b6a882e 1978
54b9ebdd
DE		 1979 /* Constants that won't fit are checked in md_apply_fix3
1980 and bfd_install_relocation.
1981 ??? It would be preferable to install the constants
1982 into the insn here and save having to create a fixS
1983 for each one. There already exists code to handle
1984 all the various cases (e.g. in md_apply_fix3 and
1985 bfd_install_relocation) so duplicating all that code
1986 here isn't right. */
1987 }
355afbcd
KR		 1988
1989 continue;
1990
1991 case 'a':
1992 if (*s++ == 'a')
1993 {
1994 opcode |= ANNUL;
1995 continue;
1996 }
1997 break;
1998
1999 case 'A':
2000 {
ed9638af
KR		 2001 int asi = 0;
2002
2003 /* Parse an asi. */
2004 if (*s == '#')
2005 {
6df07e7f 2006 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
ed9638af 2007 {
48401fcf 2008 error_message = _(": invalid ASI name");
ed9638af
KR		 2009 goto error;
2010 }
2011 }
a7aa7a2b 2012 else
ed9638af 2013 {
6df07e7f 2014 if (! parse_const_expr_arg (&s, &asi))
a7aa7a2b 2015 {
48401fcf 2016 error_message = _(": invalid ASI expression");
a7aa7a2b
ILT		 2017 goto error;
2018 }
ed9638af
KR		 2019 if (asi < 0 || asi > 255)
2020 {
48401fcf 2021 error_message = _(": invalid ASI number");
ed9638af
KR		 2022 goto error;
2023 }
2024 }
ed9638af
KR		 2025 opcode |= ASI (asi);
2026 continue;
355afbcd
KR		 2027 } /* alternate space */
2028
2029 case 'p':
2030 if (strncmp (s, "%psr", 4) == 0)
2031 {
2032 s += 4;
2033 continue;
2034 }
2035 break;
2036
2037 case 'q': /* floating point queue */
2038 if (strncmp (s, "%fq", 3) == 0)
2039 {
2040 s += 3;
2041 continue;
2042 }
2043 break;
2044
2045 case 'Q': /* coprocessor queue */
2046 if (strncmp (s, "%cq", 3) == 0)
2047 {
2048 s += 3;
2049 continue;
2050 }
2051 break;
2052
2053 case 'S':
2b063e6d
ILT		 2054 if (strcmp (str, "set") == 0
2055 || strcmp (str, "setuw") == 0)
355afbcd
KR		 2056 {
2057 special_case = SPECIAL_CASE_SET;
2058 continue;
2059 }
2b063e6d
ILT		 2060 else if (strcmp (str, "setsw") == 0)
2061 {
2062 special_case = SPECIAL_CASE_SETSW;
2063 continue;
2064 }
2065 else if (strcmp (str, "setx") == 0)
2066 {
2067 special_case = SPECIAL_CASE_SETX;
2068 continue;
2069 }
355afbcd
KR		 2070 else if (strncmp (str, "fdiv", 4) == 0)
2071 {
2072 special_case = SPECIAL_CASE_FDIV;
2073 continue;
2074 }
2075 break;
2076
355afbcd
KR		 2077 case 'o':
2078 if (strncmp (s, "%asi", 4) != 0)
2079 break;
2080 s += 4;
2081 continue;
2082
2083 case 's':
2084 if (strncmp (s, "%fprs", 5) != 0)
2085 break;
2086 s += 5;
2087 continue;
2088
2089 case 'E':
2090 if (strncmp (s, "%ccr", 4) != 0)
2091 break;
2092 s += 4;
2093 continue;
680227f3 2094
355afbcd
KR		 2095 case 't':
2096 if (strncmp (s, "%tbr", 4) != 0)
2097 break;
2098 s += 4;
2099 continue;
2100
2101 case 'w':
2102 if (strncmp (s, "%wim", 4) != 0)
2103 break;
2104 s += 4;
2105 continue;
2106
5e0a90a8
KR		 2107 case 'x':
2108 {
2109 char *push = input_line_pointer;
2110 expressionS e;
2111
2112 input_line_pointer = s;
2113 expression (&e);
2114 if (e.X_op == O_constant)
2115 {
2116 int n = e.X_add_number;
2117 if (n != e.X_add_number || (n & ~0x1ff) != 0)
48401fcf 2118 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
5e0a90a8
KR		 2119 else
2120 opcode |= e.X_add_number << 5;
2121 }
2122 else
48401fcf 2123 as_bad (_("non-immediate OPF operand, ignored"));
5e0a90a8
KR		 2124 s = input_line_pointer;
2125 input_line_pointer = push;
2126 continue;
2127 }
5e0a90a8 2128
355afbcd
KR		 2129 case 'y':
2130 if (strncmp (s, "%y", 2) != 0)
2131 break;
2132 s += 2;
2133 continue;
2134
e86d5cf3
DE		 2135 case 'u':
2136 case 'U':
2137 {
2138 /* Parse a sparclet cpreg. */
2139 int cpreg;
2140 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2141 {
48401fcf 2142 error_message = _(": invalid cpreg name");
e86d5cf3
DE		 2143 goto error;
2144 }
2145 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2146 continue;
2147 }
2148
355afbcd 2149 default:
48401fcf 2150 as_fatal (_("failed sanity check."));
355afbcd 2151 } /* switch on arg code */
6df07e7f
DE		 2152
2153 /* Break out of for() loop. */
355afbcd
KR		 2154 break;
2155 } /* for each arg that we expect */
6df07e7f 2156
355afbcd
KR		 2157 error:
2158 if (match == 0)
2159 {
2160 /* Args don't match. */
48401fcf 2161 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
a7aa7a2b
ILT		 2162 && (insn->name == insn[1].name
2163 || !strcmp (insn->name, insn[1].name)))
355afbcd
KR		 2164 {
2165 ++insn;
2166 s = argsStart;
2167 continue;
2168 }
2169 else
2170 {
48401fcf 2171 as_bad (_("Illegal operands%s"), error_message);
355afbcd
KR		 2172 return;
2173 }
2174 }
2175 else
2176 {
e70ad5d5 2177 /* We have a match. Now see if the architecture is ok. */
d8b42b96 2178 int needed_arch_mask = insn->architecture;
e70ad5d5 2179
d8b42b96 2180 if (v9_arg_p)
355afbcd 2181 {
d8b42b96
DE		 2182 needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9)
2183 | (1 << SPARC_OPCODE_ARCH_V9A));
2184 needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
e70ad5d5 2185 }
d8b42b96
DE		 2186
2187 if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture))
2188 ; /* ok */
2189 /* Can we bump up the architecture? */
2190 else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture))
e70ad5d5 2191 {
d8b42b96
DE		 2192 enum sparc_opcode_arch_val needed_architecture =
2193 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2194 & needed_arch_mask);
2195
2196 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
e70ad5d5
DE		 2197 if (warn_on_bump
2198 && needed_architecture > warn_after_architecture)
355afbcd 2199 {
48401fcf 2200 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
e70ad5d5
DE		 2201 sparc_opcode_archs[current_architecture].name,
2202 sparc_opcode_archs[needed_architecture].name,
2203 str);
d8b42b96 2204 warn_after_architecture = needed_architecture;
355afbcd 2205 }
e70ad5d5
DE		 2206 current_architecture = needed_architecture;
2207 }
d8b42b96 2208 /* Conflict. */
110b814d
DE		 2209 /* ??? This seems to be a bit fragile. What if the next entry in
2210 the opcode table is the one we want and it is supported?
2211 It is possible to arrange the table today so that this can't
2212 happen but what about tomorrow? */
d8b42b96
DE		 2213 else
2214 {
110b814d
DE		 2215 int arch,printed_one_p = 0;
2216 char *p;
2217 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2218
2219 /* Create a list of the architectures that support the insn. */
2220 needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture);
2221 p = required_archs;
2222 arch = sparc_ffs (needed_arch_mask);
2223 while ((1 << arch) <= needed_arch_mask)
2224 {
2225 if ((1 << arch) & needed_arch_mask)
2226 {
2227 if (printed_one_p)
2228 *p++ = '|';
2229 strcpy (p, sparc_opcode_archs[arch].name);
2230 p += strlen (p);
2231 printed_one_p = 1;
2232 }
2233 ++arch;
2234 }
d8b42b96 2235
48401fcf
TT		 2236 as_bad (_("Architecture mismatch on \"%s\"."), str);
2237 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
110b814d 2238 required_archs,
d8b42b96
DE		 2239 sparc_opcode_archs[max_architecture].name);
2240 return;
2241 }
e70ad5d5 2242 } /* if no match */
355afbcd
KR		 2243
2244 break;
e70ad5d5 2245 } /* forever looking for a match */
355afbcd
KR		 2246
2247 the_insn.opcode = opcode;
c999fd9f 2248}
355afbcd 2249
af6f39b4
DE		 2250/* Parse an argument that can be expressed as a keyword.
2251 (eg: #StoreStore or %ccfr).
2252 The result is a boolean indicating success.
2253 If successful, INPUT_POINTER is updated. */
2254
2255static int
2256parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2257 int (*lookup_fn) PARAMS ((const char *));
2258 char **input_pointerP;
2259 int *valueP;
2260{
2261 int value;
2262 char c, *p, *q;
2263
2264 p = *input_pointerP;
48401fcf
TT		 2265 for (q = p + (*p == '#' || *p == '%');
2266 isalnum ((unsigned char) *q) || *q == '_';
2267 ++q)
af6f39b4
DE		 2268 continue;
2269 c = *q;
2270 *q = 0;
2271 value = (*lookup_fn) (p);
2272 *q = c;
2273 if (value == -1)
2274 return 0;
2275 *valueP = value;
2276 *input_pointerP = q;
2277 return 1;
2278}
2279
2280/* Parse an argument that is a constant expression.
2281 The result is a boolean indicating success. */
2282
2283static int
2284parse_const_expr_arg (input_pointerP, valueP)
2285 char **input_pointerP;
2286 int *valueP;
2287{
2288 char *save = input_line_pointer;
2289 expressionS exp;
2290
2291 input_line_pointer = *input_pointerP;
2292 /* The next expression may be something other than a constant
2293 (say if we're not processing the right variant of the insn).
2294 Don't call expression unless we're sure it will succeed as it will
2295 signal an error (which we want to defer until later). */
2296 /* FIXME: It might be better to define md_operand and have it recognize
2297 things like %asi, etc. but continuing that route through to the end
2298 is a lot of work. */
2299 if (*input_line_pointer == '%')
2300 {
2301 input_line_pointer = save;
2302 return 0;
2303 }
2304 expression (&exp);
2305 *input_pointerP = input_line_pointer;
2306 input_line_pointer = save;
2307 if (exp.X_op != O_constant)
2308 return 0;
2309 *valueP = exp.X_add_number;
2310 return 1;
2311}
2312
2313/* Subroutine of sparc_ip to parse an expression. */
2314
355afbcd 2315static int
af6f39b4 2316get_expression (str)
355afbcd 2317 char *str;
fecd2382 2318{
355afbcd
KR		 2319 char *save_in;
2320 segT seg;
2321
2322 save_in = input_line_pointer;
2323 input_line_pointer = str;
428d312b 2324 seg = expression (&the_insn.exp);
58d4951d
ILT		 2325 if (seg != absolute_section
2326 && seg != text_section
2327 && seg != data_section
2328 && seg != bss_section
2329 && seg != undefined_section)
355afbcd 2330 {
48401fcf 2331 the_insn.error = _("bad segment");
355afbcd
KR		 2332 expr_end = input_line_pointer;
2333 input_line_pointer = save_in;
2334 return 1;
2335 }
2336 expr_end = input_line_pointer;
2337 input_line_pointer = save_in;
2338 return 0;
af6f39b4
DE		 2339}
2340
2341/* Subroutine of md_assemble to output one insn. */
2342
2343static void
2344output_insn (insn, the_insn)
2345 const struct sparc_opcode *insn;
2346 struct sparc_it *the_insn;
2347{
2348 char *toP = frag_more (4);
2349
2350 /* put out the opcode */
2351 if (INSN_BIG_ENDIAN)
2352 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2353 else
2354 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
fecd2382 2355
af6f39b4
DE		 2356 /* put out the symbol-dependent stuff */
2357 if (the_insn->reloc != BFD_RELOC_NONE)
2358 {
54b9ebdd
DE		 2359 fixS *fixP = fix_new_exp (frag_now, /* which frag */
2360 (toP - frag_now->fr_literal), /* where */
2361 4, /* size */
2362 &the_insn->exp,
2363 the_insn->pcrel,
2364 the_insn->reloc);
2365 /* Turn off overflow checking in fixup_segment. We'll do our
2366 own overflow checking in md_apply_fix3. This is necessary because
2367 the insn size is 4 and fixup_segment will signal an overflow for
2368 large 8 byte quantities. */
2369 fixP->fx_no_overflow = 1;
af6f39b4 2370 }
fecd2382 2371
af6f39b4
DE		 2372 last_insn = insn;
2373 last_opcode = the_insn->opcode;
2374}
2375\f
fecd2382
RP		 2376/*
2377 This is identical to the md_atof in m68k.c. I think this is right,
2378 but I'm not sure.
355afbcd 2379
fecd2382
RP		 2380 Turn a string in input_line_pointer into a floating point constant of type
2381 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2382 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2383 */
2384
2385/* Equal to MAX_PRECISION in atof-ieee.c */
2386#define MAX_LITTLENUMS 6
2387
355afbcd
KR		 2388char *
2389md_atof (type, litP, sizeP)
2390 char type;
2391 char *litP;
2392 int *sizeP;
fecd2382 2393{
2b063e6d 2394 int i,prec;
355afbcd 2395 LITTLENUM_TYPE words[MAX_LITTLENUMS];
355afbcd 2396 char *t;
355afbcd
KR		 2397
2398 switch (type)
2399 {
355afbcd
KR		 2400 case 'f':
2401 case 'F':
2402 case 's':
2403 case 'S':
2404 prec = 2;
2405 break;
2406
2407 case 'd':
2408 case 'D':
2409 case 'r':
2410 case 'R':
2411 prec = 4;
2412 break;
2413
2414 case 'x':
2415 case 'X':
2416 prec = 6;
2417 break;
2418
2419 case 'p':
2420 case 'P':
2421 prec = 6;
2422 break;
2423
2424 default:
2425 *sizeP = 0;
48401fcf 2426 return _("Bad call to MD_ATOF()");
355afbcd 2427 }
2b063e6d 2428
355afbcd
KR		 2429 t = atof_ieee (input_line_pointer, type, words);
2430 if (t)
2431 input_line_pointer = t;
2432 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2b063e6d
ILT		 2433
2434 if (target_big_endian)
355afbcd 2435 {
2b063e6d
ILT		 2436 for (i = 0; i < prec; i++)
2437 {
2438 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2439 litP += sizeof (LITTLENUM_TYPE);
2440 }
2441 }
2442 else
2443 {
2444 for (i = prec - 1; i >= 0; i--)
2445 {
2446 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2447 litP += sizeof (LITTLENUM_TYPE);
2448 }
355afbcd 2449 }
2b063e6d 2450
ed9638af
KR		 2451 return 0;
2452}
fecd2382 2453
2b063e6d
ILT		 2454/* Write a value out to the object file, using the appropriate
2455 endianness. */
2456
355afbcd
KR		 2457void
2458md_number_to_chars (buf, val, n)
2459 char *buf;
125f0b0d 2460 valueT val;
355afbcd 2461 int n;
fecd2382 2462{
2b063e6d
ILT		 2463 if (target_big_endian)
2464 number_to_chars_bigendian (buf, val, n);
b9089139
RH		 2465 else if (target_little_endian_data
2466 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2467 /* Output debug words, which are not in allocated sections, as big endian */
2468 number_to_chars_bigendian (buf, val, n);
2469 else if (target_little_endian_data || ! target_big_endian)
2b063e6d 2470 number_to_chars_littleendian (buf, val, n);
c999fd9f 2471}
af6f39b4 2472\f
fecd2382
RP		 2473/* Apply a fixS to the frags, now that we know the value it ought to
2474 hold. */
2475
428d312b 2476int
2b063e6d 2477md_apply_fix3 (fixP, value, segment)
355afbcd 2478 fixS *fixP;
125f0b0d 2479 valueT *value;
2b063e6d 2480 segT segment;
fecd2382 2481{
355afbcd 2482 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
125f0b0d 2483 offsetT val;
2b063e6d 2484 long insn;
428d312b 2485
428d312b 2486 val = *value;
355afbcd 2487
428d312b 2488 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
355afbcd
KR		 2489
2490 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
2491
7766838e
ILT		 2492#ifdef OBJ_ELF
2493 /* FIXME: SPARC ELF relocations don't use an addend in the data
2494 field itself. This whole approach should be somehow combined
9e6f4c6b 2495 with the calls to bfd_install_relocation. Also, the value passed
a7aa7a2b
ILT		 2496 in by fixup_segment includes the value of a defined symbol. We
2497 don't want to include the value of an externally visible symbol. */
7766838e 2498 if (fixP->fx_addsy != NULL)
a7aa7a2b 2499 {
2b063e6d
ILT		 2500 if (fixP->fx_addsy->sy_used_in_reloc
2501 && (S_IS_EXTERNAL (fixP->fx_addsy)
2502 || S_IS_WEAK (fixP->fx_addsy)
2503 || (sparc_pic_code && ! fixP->fx_pcrel)
2504 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2505 && ((bfd_get_section_flags (stdoutput,
2506 S_GET_SEGMENT (fixP->fx_addsy))
2507 & SEC_LINK_ONCE) != 0
2508 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2509 ".gnu.linkonce",
2510 sizeof ".gnu.linkonce" - 1) == 0)))
a7aa7a2b
ILT		 2511 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2512 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2513 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2514 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2515 return 1;
2516 }
7766838e
ILT		 2517#endif
2518
c999fd9f
KR		 2519 /* This is a hack. There should be a better way to
2520 handle this. Probably in terms of howto fields, once
2521 we can look at these fixups in terms of howtos. */
428d312b 2522 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
c999fd9f 2523 val += fixP->fx_where + fixP->fx_frag->fr_address;
355afbcd 2524
ade614d5
KR		 2525#ifdef OBJ_AOUT
2526 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2527 generate a reloc, then we just want to let the reloc addend set
2528 the value. We do not want to also stuff the addend into the
2529 object file. Including the addend in the object file works when
2530 doing a static link, because the linker will ignore the object
2531 file contents. However, the dynamic linker does not ignore the
2532 object file contents. */
2533 if (fixP->fx_addsy != NULL
2534 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2535 val = 0;
4c67b523
ILT		 2536
2537 /* When generating PIC code, we do not want an addend for a reloc
2538 against a local symbol. We adjust fx_addnumber to cancel out the
2539 value already included in val, and to also cancel out the
2540 adjustment which bfd_install_relocation will create. */
2541 if (sparc_pic_code
2542 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2543 && fixP->fx_addsy != NULL
2544 && ! S_IS_COMMON (fixP->fx_addsy)
2545 && (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0)
2546 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
a5002978
CM		 2547
2548 /* When generating PIC code, we need to fiddle to get
2549 bfd_install_relocation to do the right thing for a PC relative
2550 reloc against a local symbol which we are going to keep. */
2551 if (sparc_pic_code
2552 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2553 && fixP->fx_addsy != NULL
2554 && (S_IS_EXTERNAL (fixP->fx_addsy)
2555 || S_IS_WEAK (fixP->fx_addsy))
2556 && S_IS_DEFINED (fixP->fx_addsy)
2557 && ! S_IS_COMMON (fixP->fx_addsy))
2558 {
2559 val = 0;
2560 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2561 }
ade614d5
KR		 2562#endif
2563
2b063e6d 2564 /* If this is a data relocation, just output VAL. */
58d4951d 2565
2b063e6d
ILT		 2566 if (fixP->fx_r_type == BFD_RELOC_16)
2567 {
2568 md_number_to_chars (buf, val, 2);
2569 }
fc23c14e 2570 else if (fixP->fx_r_type == BFD_RELOC_32
b9089139 2571 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2b063e6d
ILT		 2572 {
2573 md_number_to_chars (buf, val, 4);
2574 }
2575 else if (fixP->fx_r_type == BFD_RELOC_64)
2576 {
2577 md_number_to_chars (buf, val, 8);
2578 }
2579 else
2580 {
2581 /* It's a relocation against an instruction. */
355afbcd 2582
2b063e6d
ILT		 2583 if (INSN_BIG_ENDIAN)
2584 insn = bfd_getb32 ((unsigned char *) buf);
2585 else
2586 insn = bfd_getl32 ((unsigned char *) buf);
2587
2588 switch (fixP->fx_r_type)
2589 {
2590 case BFD_RELOC_32_PCREL_S2:
2591 val = val >> 2;
2592 /* FIXME: This increment-by-one deserves a comment of why it's
2593 being done! */
2594 if (! sparc_pic_code
2595 || fixP->fx_addsy == NULL
2596 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2597 ++val;
2598 insn |= val & 0x3fffffff;
2599 break;
693b21e7 2600
2b063e6d
ILT		 2601 case BFD_RELOC_SPARC_11:
2602 if (! in_signed_range (val, 0x7ff))
48401fcf
TT		 2603 as_bad_where (fixP->fx_file, fixP->fx_line,
2604 _("relocation overflow"));
2b063e6d
ILT		 2605 insn |= val & 0x7ff;
2606 break;
355afbcd 2607
2b063e6d
ILT		 2608 case BFD_RELOC_SPARC_10:
2609 if (! in_signed_range (val, 0x3ff))
48401fcf
TT		 2610 as_bad_where (fixP->fx_file, fixP->fx_line,
2611 _("relocation overflow"));
2b063e6d
ILT		 2612 insn |= val & 0x3ff;
2613 break;
355afbcd 2614
54b9ebdd
DE		 2615 case BFD_RELOC_SPARC_7:
2616 if (! in_bitfield_range (val, 0x7f))
48401fcf
TT		 2617 as_bad_where (fixP->fx_file, fixP->fx_line,
2618 _("relocation overflow"));
54b9ebdd
DE		 2619 insn |= val & 0x7f;
2620 break;
2621
2b063e6d
ILT		 2622 case BFD_RELOC_SPARC_6:
2623 if (! in_bitfield_range (val, 0x3f))
48401fcf
TT		 2624 as_bad_where (fixP->fx_file, fixP->fx_line,
2625 _("relocation overflow"));
2b063e6d
ILT		 2626 insn |= val & 0x3f;
2627 break;
355afbcd 2628
2b063e6d
ILT		 2629 case BFD_RELOC_SPARC_5:
2630 if (! in_bitfield_range (val, 0x1f))
48401fcf
TT		 2631 as_bad_where (fixP->fx_file, fixP->fx_line,
2632 _("relocation overflow"));
2b063e6d
ILT		 2633 insn |= val & 0x1f;
2634 break;
8dd07a84 2635
2b063e6d
ILT		 2636 case BFD_RELOC_SPARC_WDISP16:
2637 /* FIXME: simplify */
2638 if (((val > 0) && (val & ~0x3fffc))
2639 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
48401fcf
TT		 2640 as_bad_where (fixP->fx_file, fixP->fx_line,
2641 _("relocation overflow"));
2b063e6d
ILT		 2642 /* FIXME: The +1 deserves a comment. */
2643 val = (val >> 2) + 1;
2644 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
2645 break;
8dd07a84 2646
2b063e6d
ILT		 2647 case BFD_RELOC_SPARC_WDISP19:
2648 /* FIXME: simplify */
2649 if (((val > 0) && (val & ~0x1ffffc))
2650 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
48401fcf
TT		 2651 as_bad_where (fixP->fx_file, fixP->fx_line,
2652 _("relocation overflow"));
2b063e6d
ILT		 2653 /* FIXME: The +1 deserves a comment. */
2654 val = (val >> 2) + 1;
2655 insn |= val & 0x7ffff;
2656 break;
8dd07a84 2657
2b063e6d
ILT		 2658 case BFD_RELOC_SPARC_HH22:
2659 val = BSR (val, 32);
2660 /* intentional fallthrough */
8dd07a84 2661
2b063e6d
ILT		 2662 case BFD_RELOC_SPARC_LM22:
2663 case BFD_RELOC_HI22:
2664 if (!fixP->fx_addsy)
2665 {
2666 insn |= (val >> 10) & 0x3fffff;
2667 }
2668 else
2669 {
2670 /* FIXME: Need comment explaining why we do this. */
2671 insn &= ~0xffff;
2672 }
2673 break;
355afbcd 2674
2b063e6d
ILT		 2675 case BFD_RELOC_SPARC22:
2676 if (val & ~0x003fffff)
48401fcf
TT		 2677 as_bad_where (fixP->fx_file, fixP->fx_line,
2678 _("relocation overflow"));
2b063e6d
ILT		 2679 insn |= (val & 0x3fffff);
2680 break;
355afbcd 2681
2b063e6d
ILT		 2682 case BFD_RELOC_SPARC_HM10:
2683 val = BSR (val, 32);
2684 /* intentional fallthrough */
355afbcd 2685
2b063e6d
ILT		 2686 case BFD_RELOC_LO10:
2687 if (!fixP->fx_addsy)
2688 {
2689 insn |= val & 0x3ff;
2690 }
2691 else
2692 {
2693 /* FIXME: Need comment explaining why we do this. */
2694 insn &= ~0xff;
2695 }
2696 break;
355afbcd 2697
2b063e6d
ILT		 2698 case BFD_RELOC_SPARC13:
2699 if (! in_signed_range (val, 0x1fff))
48401fcf
TT		 2700 as_bad_where (fixP->fx_file, fixP->fx_line,
2701 _("relocation overflow"));
2b063e6d
ILT		 2702 insn |= val & 0x1fff;
2703 break;
355afbcd 2704
2b063e6d
ILT		 2705 case BFD_RELOC_SPARC_WDISP22:
2706 val = (val >> 2) + 1;
2707 /* FALLTHROUGH */
2708 case BFD_RELOC_SPARC_BASE22:
2709 insn |= val & 0x3fffff;
2710 break;
355afbcd 2711
54b9ebdd
DE		 2712 case BFD_RELOC_SPARC_H44:
2713 if (!fixP->fx_addsy)
2714 {
2715 bfd_vma tval = val;
2716 tval >>= 22;
54b9ebdd
DE		 2717 insn |= tval & 0x3fffff;
2718 }
2719 break;
2720
2721 case BFD_RELOC_SPARC_M44:
2722 if (!fixP->fx_addsy)
2723 insn |= (val >> 12) & 0x3ff;
2724 break;
2725
2726 case BFD_RELOC_SPARC_L44:
2727 if (!fixP->fx_addsy)
2728 insn |= val & 0xfff;
2729 break;
2730
2731 case BFD_RELOC_SPARC_HIX22:
2732 if (!fixP->fx_addsy)
2733 {
2734 val ^= ~ (offsetT) 0;
54b9ebdd
DE		 2735 insn |= (val >> 10) & 0x3fffff;
2736 }
2737 break;
2738
2739 case BFD_RELOC_SPARC_LOX10:
2740 if (!fixP->fx_addsy)
2741 insn |= 0x1c00 | (val & 0x3ff);
2742 break;
2743
2b063e6d
ILT		 2744 case BFD_RELOC_NONE:
2745 default:
54b9ebdd 2746 as_bad_where (fixP->fx_file, fixP->fx_line,
48401fcf 2747 _("bad or unhandled relocation type: 0x%02x"),
54b9ebdd 2748 fixP->fx_r_type);
2b063e6d 2749 break;
355afbcd 2750 }
355afbcd 2751
2b063e6d
ILT		 2752 if (INSN_BIG_ENDIAN)
2753 bfd_putb32 (insn, (unsigned char *) buf);
355afbcd 2754 else
2b063e6d 2755 bfd_putl32 (insn, (unsigned char *) buf);
355afbcd 2756 }
428d312b 2757
7ab2e983
ILT		 2758 /* Are we finished with this relocation now? */
2759 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
2760 fixP->fx_done = 1;
2761
428d312b 2762 return 1;
428d312b 2763}
fecd2382 2764
428d312b
KR		 2765/* Translate internal representation of relocation info to BFD target
2766 format. */
2767arelent *
2768tc_gen_reloc (section, fixp)
2769 asection *section;
2770 fixS *fixp;
2771{
2772 arelent *reloc;
2773 bfd_reloc_code_real_type code;
2774
590c50d8 2775 reloc = (arelent *) xmalloc (sizeof (arelent));
428d312b
KR		 2776
2777 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
2778 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
428d312b 2779
428d312b
KR		 2780 switch (fixp->fx_r_type)
2781 {
58d4951d 2782 case BFD_RELOC_16:
428d312b
KR		 2783 case BFD_RELOC_32:
2784 case BFD_RELOC_HI22:
2785 case BFD_RELOC_LO10:
2786 case BFD_RELOC_32_PCREL_S2:
7ab2e983 2787 case BFD_RELOC_SPARC13:
428d312b 2788 case BFD_RELOC_SPARC_BASE13:
a7aa7a2b
ILT		 2789 case BFD_RELOC_SPARC_WDISP16:
2790 case BFD_RELOC_SPARC_WDISP19:
ed9638af 2791 case BFD_RELOC_SPARC_WDISP22:
693b21e7 2792 case BFD_RELOC_64:
8dd07a84
ILT		 2793 case BFD_RELOC_SPARC_5:
2794 case BFD_RELOC_SPARC_6:
54b9ebdd 2795 case BFD_RELOC_SPARC_7:
125f0b0d
KR		 2796 case BFD_RELOC_SPARC_10:
2797 case BFD_RELOC_SPARC_11:
2798 case BFD_RELOC_SPARC_HH22:
2799 case BFD_RELOC_SPARC_HM10:
2800 case BFD_RELOC_SPARC_LM22:
2801 case BFD_RELOC_SPARC_PC_HH22:
2802 case BFD_RELOC_SPARC_PC_HM10:
2803 case BFD_RELOC_SPARC_PC_LM22:
54b9ebdd
DE		 2804 case BFD_RELOC_SPARC_H44:
2805 case BFD_RELOC_SPARC_M44:
2806 case BFD_RELOC_SPARC_L44:
2807 case BFD_RELOC_SPARC_HIX22:
2808 case BFD_RELOC_SPARC_LOX10:
b9089139 2809 case BFD_RELOC_SPARC_REV32:
428d312b
KR		 2810 code = fixp->fx_r_type;
2811 break;
2812 default:
2813 abort ();
48401fcf 2814 return NULL;
428d312b 2815 }
4c67b523
ILT		 2816
2817#if defined (OBJ_ELF) || defined (OBJ_AOUT)
2818 /* If we are generating PIC code, we need to generate a different
2819 set of relocs. */
2820
2821#ifdef OBJ_ELF
2822#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
2823#else
2824#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
2825#endif
2826
2827 if (sparc_pic_code)
2828 {
2829 switch (code)
2830 {
2831 case BFD_RELOC_32_PCREL_S2:
2832 if (! S_IS_DEFINED (fixp->fx_addsy)
9f6da653 2833 || S_IS_COMMON (fixp->fx_addsy)
21965655
ILT		 2834 || S_IS_EXTERNAL (fixp->fx_addsy)
2835 || S_IS_WEAK (fixp->fx_addsy))
4c67b523
ILT		 2836 code = BFD_RELOC_SPARC_WPLT30;
2837 break;
2838 case BFD_RELOC_HI22:
2839 if (fixp->fx_addsy != NULL
2840 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2841 code = BFD_RELOC_SPARC_PC22;
2842 else
2843 code = BFD_RELOC_SPARC_GOT22;
2844 break;
2845 case BFD_RELOC_LO10:
2846 if (fixp->fx_addsy != NULL
2847 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2848 code = BFD_RELOC_SPARC_PC10;
2849 else
2850 code = BFD_RELOC_SPARC_GOT10;
2851 break;
2852 case BFD_RELOC_SPARC13:
2853 code = BFD_RELOC_SPARC_GOT13;
2854 break;
2855 default:
2856 break;
2857 }
2858 }
2859#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
2860
428d312b 2861 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
a7129c48
KR		 2862 if (reloc->howto == 0)
2863 {
2864 as_bad_where (fixp->fx_file, fixp->fx_line,
48401fcf 2865 _("internal error: can't export reloc type %d (`%s')"),
ade614d5 2866 fixp->fx_r_type, bfd_get_reloc_code_name (code));
a7129c48
KR		 2867 return 0;
2868 }
c999fd9f
KR		 2869
2870 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
a7aa7a2b
ILT		 2871#ifdef OBJ_AOUT
2872
4c67b523
ILT		 2873 if (reloc->howto->pc_relative == 0
2874 || code == BFD_RELOC_SPARC_PC10
2875 || code == BFD_RELOC_SPARC_PC22)
a7aa7a2b 2876 reloc->addend = fixp->fx_addnumber;
a5002978
CM		 2877 else if (sparc_pic_code
2878 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
2879 && fixp->fx_addsy != NULL
2880 && (S_IS_EXTERNAL (fixp->fx_addsy)
2881 || S_IS_WEAK (fixp->fx_addsy))
2882 && S_IS_DEFINED (fixp->fx_addsy)
2883 && ! S_IS_COMMON (fixp->fx_addsy))
2884 reloc->addend = fixp->fx_addnumber;
a7aa7a2b
ILT		 2885 else
2886 reloc->addend = fixp->fx_offset - reloc->address;
2887
2888#else /* elf or coff */
2889
4c67b523
ILT		 2890 if (reloc->howto->pc_relative == 0
2891 || code == BFD_RELOC_SPARC_PC10
2892 || code == BFD_RELOC_SPARC_PC22)
c999fd9f 2893 reloc->addend = fixp->fx_addnumber;
7ab2e983
ILT		 2894 else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2895 reloc->addend = (section->vma
2896 + fixp->fx_addnumber
2897 + md_pcrel_from (fixp));
c999fd9f 2898 else
a7aa7a2b 2899 reloc->addend = fixp->fx_offset;
a7aa7a2b 2900#endif
428d312b
KR		 2901
2902 return reloc;
2903}
af6f39b4
DE		 2904\f
2905/* We have no need to default values of symbols. */
428d312b 2906
af6f39b4
DE		 2907/* ARGSUSED */
2908symbolS *
2909md_undefined_symbol (name)
2910 char *name;
2911{
2912 return 0;
2913} /* md_undefined_symbol() */
fecd2382 2914
af6f39b4
DE		 2915/* Round up a section size to the appropriate boundary. */
2916valueT
2917md_section_align (segment, size)
2918 segT segment;
2919 valueT size;
fecd2382 2920{
af6f39b4
DE		 2921#ifndef OBJ_ELF
2922 /* This is not right for ELF; a.out wants it, and COFF will force
2923 the alignment anyways. */
2924 valueT align = ((valueT) 1
2925 << (valueT) bfd_get_section_alignment (stdoutput, segment));
2926 valueT newsize;
2927 /* turn alignment value into a mask */
2928 align--;
2929 newsize = (size + align) & ~align;
2930 return newsize;
2931#else
2932 return size;
2933#endif
2934}
2935
2936/* Exactly what point is a PC-relative offset relative TO?
2937 On the sparc, they're relative to the address of the offset, plus
2938 its size. This gets us to the following instruction.
2939 (??? Is this right? FIXME-SOON) */
2940long
2941md_pcrel_from (fixP)
2942 fixS *fixP;
2943{
2944 long ret;
355afbcd 2945
af6f39b4
DE		 2946 ret = fixP->fx_where + fixP->fx_frag->fr_address;
2947 if (! sparc_pic_code
2948 || fixP->fx_addsy == NULL
2949 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2950 ret += fixP->fx_size;
2951 return ret;
c999fd9f 2952}
f3d817d8 2953\f
4a07363f
ILT		 2954/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
2955 of two. */
2956
2957static int
2958log2 (value)
2959 int value;
2960{
2961 int shift;
2962
2963 if (value <= 0)
2964 return -1;
2965
2966 for (shift = 0; (value & 1) == 0; value >>= 1)
2967 ++shift;
2968
2969 return (value == 1) ? shift : -1;
2970}
2971
839df5c3 2972/*
af6f39b4 2973 * sort of like s_lcomm
839df5c3 2974 */
162e3485 2975
af6f39b4
DE		 2976#ifndef OBJ_ELF
2977static int max_alignment = 15;
2b063e6d 2978#endif
355afbcd 2979
af6f39b4
DE		 2980static void
2981s_reserve (ignore)
2982 int ignore;
f3d817d8 2983{
af6f39b4
DE		 2984 char *name;
2985 char *p;
2986 char c;
2987 int align;
2988 int size;
2989 int temp;
2990 symbolS *symbolP;
2991
2992 name = input_line_pointer;
2993 c = get_symbol_end ();
2994 p = input_line_pointer;
2995 *p = c;
2996 SKIP_WHITESPACE ();
2997
2998 if (*input_line_pointer != ',')
355afbcd 2999 {
48401fcf 3000 as_bad (_("Expected comma after name"));
af6f39b4
DE		 3001 ignore_rest_of_line ();
3002 return;
3003 }
355afbcd 3004
af6f39b4
DE		 3005 ++input_line_pointer;
3006
3007 if ((size = get_absolute_expression ()) < 0)
3008 {
48401fcf 3009 as_bad (_("BSS length (%d.) <0! Ignored."), size);
af6f39b4
DE		 3010 ignore_rest_of_line ();
3011 return;
3012 } /* bad length */
3013
3014 *p = 0;
3015 symbolP = symbol_find_or_make (name);
3016 *p = c;
3017
3018 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3019 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3020 {
48401fcf 3021 as_bad (_("bad .reserve segment -- expected BSS segment"));
af6f39b4
DE		 3022 return;
3023 }
3024
3025 if (input_line_pointer[2] == '.')
3026 input_line_pointer += 7;
3027 else
3028 input_line_pointer += 6;
3029 SKIP_WHITESPACE ();
3030
3031 if (*input_line_pointer == ',')
3032 {
3033 ++input_line_pointer;
3034
3035 SKIP_WHITESPACE ();
3036 if (*input_line_pointer == '\n')
e70ad5d5 3037 {
4a07363f
ILT		 3038 as_bad (_("missing alignment"));
3039 ignore_rest_of_line ();
af6f39b4 3040 return;
e70ad5d5
DE		 3041 }
3042
4a07363f
ILT		 3043 align = (int) get_absolute_expression ();
3044
af6f39b4
DE		 3045#ifndef OBJ_ELF
3046 if (align > max_alignment)
3047 {
3048 align = max_alignment;
4a07363f 3049 as_warn (_("alignment too large; assuming %d"), align);
af6f39b4
DE		 3050 }
3051#endif
4a07363f 3052
af6f39b4
DE		 3053 if (align < 0)
3054 {
4a07363f
ILT		 3055 as_bad (_("negative alignment"));
3056 ignore_rest_of_line ();
3057 return;
af6f39b4 3058 }
e70ad5d5 3059
4a07363f 3060 if (align != 0)
af6f39b4 3061 {
4a07363f
ILT		 3062 temp = log2 (align);
3063 if (temp < 0)
3064 {
3065 as_bad (_("alignment not a power of 2"));
3066 ignore_rest_of_line ();
3067 return;
3068 }
355afbcd 3069
4a07363f
ILT		 3070 align = temp;
3071 }
3072
3073 record_alignment (bss_section, align);
3074 }
af6f39b4
DE		 3075 else
3076 align = 0;
2b063e6d 3077
af6f39b4
DE		 3078 if (!S_IS_DEFINED (symbolP)
3079#ifdef OBJ_AOUT
3080 && S_GET_OTHER (symbolP) == 0
3081 && S_GET_DESC (symbolP) == 0
3082#endif
3083 )
3084 {
3085 if (! need_pass_2)
3086 {
3087 char *pfrag;
3088 segT current_seg = now_seg;
3089 subsegT current_subseg = now_subseg;
3090
3091 subseg_set (bss_section, 1); /* switch to bss */
3092
3093 if (align)
3094 frag_align (align, 0, 0); /* do alignment */
3095
3096 /* detach from old frag */
3097 if (S_GET_SEGMENT(symbolP) == bss_section)
3098 symbolP->sy_frag->fr_symbol = NULL;
3099
3100 symbolP->sy_frag = frag_now;
3101 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP,
3102 (offsetT) size, (char *)0);
3103 *pfrag = 0;
3104
3105 S_SET_SEGMENT (symbolP, bss_section);
3106
3107 subseg_set (current_seg, current_subseg);
b9089139
RH		 3108
3109#ifdef OBJ_ELF
3110 S_SET_SIZE (symbolP, size);
3111#endif
af6f39b4
DE		 3112 }
3113 }
3114 else
3115 {
3116 as_warn("Ignoring attempt to re-define symbol %s",
3117 S_GET_NAME (symbolP));
3118 } /* if not redefining */
3119
3120 demand_empty_rest_of_line ();
3121}
3122
3123static void
3124s_common (ignore)
3125 int ignore;
3126{
3127 char *name;
3128 char c;
3129 char *p;
3130 int temp, size;
3131 symbolS *symbolP;
3132
3133 name = input_line_pointer;
3134 c = get_symbol_end ();
3135 /* just after name is now '\0' */
3136 p = input_line_pointer;
3137 *p = c;
3138 SKIP_WHITESPACE ();
3139 if (*input_line_pointer != ',')
3140 {
48401fcf 3141 as_bad (_("Expected comma after symbol-name"));
af6f39b4
DE		 3142 ignore_rest_of_line ();
3143 return;
3144 }
3145 input_line_pointer++; /* skip ',' */
3146 if ((temp = get_absolute_expression ()) < 0)
3147 {
48401fcf 3148 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
af6f39b4
DE		 3149 ignore_rest_of_line ();
3150 return;
3151 }
3152 size = temp;
3153 *p = 0;
3154 symbolP = symbol_find_or_make (name);
3155 *p = c;
3156 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3157 {
48401fcf 3158 as_bad (_("Ignoring attempt to re-define symbol"));
af6f39b4
DE		 3159 ignore_rest_of_line ();
3160 return;
3161 }
3162 if (S_GET_VALUE (symbolP) != 0)
3163 {
48401fcf 3164 if (S_GET_VALUE (symbolP) != (valueT) size)
af6f39b4 3165 {
48401fcf 3166 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
af6f39b4
DE		 3167 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3168 }
3169 }
3170 else
3171 {
3172#ifndef OBJ_ELF
3173 S_SET_VALUE (symbolP, (valueT) size);
3174 S_SET_EXTERNAL (symbolP);
3175#endif
3176 }
3177 know (symbolP->sy_frag == &zero_address_frag);
3178 if (*input_line_pointer != ',')
3179 {
48401fcf 3180 as_bad (_("Expected comma after common length"));
af6f39b4
DE		 3181 ignore_rest_of_line ();
3182 return;
3183 }
3184 input_line_pointer++;
3185 SKIP_WHITESPACE ();
3186 if (*input_line_pointer != '"')
3187 {
3188 temp = get_absolute_expression ();
4a07363f 3189
af6f39b4
DE		 3190#ifndef OBJ_ELF
3191 if (temp > max_alignment)
3192 {
3193 temp = max_alignment;
4a07363f 3194 as_warn (_("alignment too large; assuming %d"), temp);
af6f39b4
DE		 3195 }
3196#endif
4a07363f 3197
af6f39b4
DE		 3198 if (temp < 0)
3199 {
4a07363f
ILT		 3200 as_bad (_("negative alignment"));
3201 ignore_rest_of_line ();
3202 return;
af6f39b4 3203 }
4a07363f 3204
af6f39b4
DE		 3205#ifdef OBJ_ELF
3206 if (symbolP->local)
3207 {
3208 segT old_sec;
3209 int old_subsec;
3210 char *p;
3211 int align;
3212
3213 old_sec = now_seg;
3214 old_subsec = now_subseg;
4a07363f
ILT		 3215
3216 if (temp == 0)
3217 align = 0;
3218 else
3219 align = log2 (temp);
3220
3221 if (align < 0)
3222 {
3223 as_bad (_("alignment not a power of 2"));
3224 ignore_rest_of_line ();
3225 return;
3226 }
3227
af6f39b4
DE		 3228 record_alignment (bss_section, align);
3229 subseg_set (bss_section, 0);
3230 if (align)
3231 frag_align (align, 0, 0);
3232 if (S_GET_SEGMENT (symbolP) == bss_section)
3233 symbolP->sy_frag->fr_symbol = 0;
3234 symbolP->sy_frag = frag_now;
3235 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3236 (offsetT) size, (char *) 0);
3237 *p = 0;
3238 S_SET_SEGMENT (symbolP, bss_section);
3239 S_CLEAR_EXTERNAL (symbolP);
b9089139 3240 S_SET_SIZE (symbolP, size);
af6f39b4
DE		 3241 subseg_set (old_sec, old_subsec);
3242 }
3243 else
4a07363f 3244#endif /* OBJ_ELF */
af6f39b4
DE		 3245 {
3246 allocate_common:
3247 S_SET_VALUE (symbolP, (valueT) size);
3248#ifdef OBJ_ELF
3249 S_SET_ALIGN (symbolP, temp);
b9089139 3250 S_SET_SIZE (symbolP, size);
af6f39b4
DE		 3251#endif
3252 S_SET_EXTERNAL (symbolP);
3253 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3254 }
3255 }
3256 else
3257 {
3258 input_line_pointer++;
3259 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3260 if (*input_line_pointer == '.')
3261 input_line_pointer++;
3262 /* @@ Some say data, some say bss. */
3263 if (strncmp (input_line_pointer, "bss\"", 4)
3264 && strncmp (input_line_pointer, "data\"", 5))
3265 {
3266 while (*--input_line_pointer != '"')
3267 ;
3268 input_line_pointer--;
3269 goto bad_common_segment;
3270 }
3271 while (*input_line_pointer++ != '"')
3272 ;
3273 goto allocate_common;
3274 }
2b063e6d 3275
af6f39b4
DE		 3276#ifdef BFD_ASSEMBLER
3277 symbolP->bsym->flags |= BSF_OBJECT;
4c67b523
ILT		 3278#endif
3279
af6f39b4
DE		 3280 demand_empty_rest_of_line ();
3281 return;
f3d817d8 3282
af6f39b4
DE		 3283 {
3284 bad_common_segment:
3285 p = input_line_pointer;
3286 while (*p && *p != '\n')
3287 p++;
3288 c = *p;
3289 *p = '\0';
48401fcf 3290 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
af6f39b4
DE		 3291 *p = c;
3292 input_line_pointer = p;
3293 ignore_rest_of_line ();
3294 return;
3295 }
3296}
f3d817d8 3297
af6f39b4
DE		 3298/* Handle the .empty pseudo-op. This supresses the warnings about
3299 invalid delay slot usage. */
f3d817d8 3300
af6f39b4
DE		 3301static void
3302s_empty (ignore)
3303 int ignore;
3304{
3305 /* The easy way to implement is to just forget about the last
3306 instruction. */
3307 last_insn = NULL;
3308}
a7aa7a2b 3309
af6f39b4
DE		 3310static void
3311s_seg (ignore)
3312 int ignore;
3313{
f3d817d8 3314
af6f39b4
DE		 3315 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3316 {
3317 input_line_pointer += 6;
3318 s_text (0);
3319 return;
355afbcd 3320 }
af6f39b4
DE		 3321 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3322 {
3323 input_line_pointer += 6;
3324 s_data (0);
3325 return;
3326 }
3327 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3328 {
3329 input_line_pointer += 7;
3330 s_data1 ();
3331 return;
3332 }
3333 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3334 {
3335 input_line_pointer += 5;
3336 /* We only support 2 segments -- text and data -- for now, so
3337 things in the "bss segment" will have to go into data for now.
3338 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3339 subseg_set (data_section, 255); /* FIXME-SOMEDAY */
3340 return;
3341 }
48401fcf 3342 as_bad (_("Unknown segment type"));
af6f39b4 3343 demand_empty_rest_of_line ();
f3d817d8
DM		 3344}
3345
af6f39b4
DE		 3346static void
3347s_data1 ()
f3d817d8 3348{
af6f39b4
DE		 3349 subseg_set (data_section, 1);
3350 demand_empty_rest_of_line ();
3351}
e70ad5d5 3352
af6f39b4
DE		 3353static void
3354s_proc (ignore)
3355 int ignore;
3356{
3357 while (!is_end_of_line[(unsigned char) *input_line_pointer])
5e0a90a8 3358 {
af6f39b4 3359 ++input_line_pointer;
5e0a90a8 3360 }
af6f39b4 3361 ++input_line_pointer;
f3d817d8 3362}
fecd2382 3363
af6f39b4
DE		 3364/* This static variable is set by s_uacons to tell sparc_cons_align
3365 that the expession does not need to be aligned. */
fecd2382 3366
af6f39b4
DE		 3367static int sparc_no_align_cons = 0;
3368
3369/* This handles the unaligned space allocation pseudo-ops, such as
3370 .uaword. .uaword is just like .word, but the value does not need
3371 to be aligned. */
3372
3373static void
3374s_uacons (bytes)
3375 int bytes;
fecd2382 3376{
af6f39b4
DE		 3377 /* Tell sparc_cons_align not to align this value. */
3378 sparc_no_align_cons = 1;
3379 cons (bytes);
428d312b 3380}
fecd2382 3381
af6f39b4
DE		 3382/* If the --enforce-aligned-data option is used, we require .word,
3383 et. al., to be aligned correctly. We do it by setting up an
3384 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3385 no unexpected alignment was introduced.
3386
3387 The SunOS and Solaris native assemblers enforce aligned data by
3388 default. We don't want to do that, because gcc can deliberately
3389 generate misaligned data if the packed attribute is used. Instead,
3390 we permit misaligned data by default, and permit the user to set an
3391 option to check for it. */
3392
3393void
3394sparc_cons_align (nbytes)
3395 int nbytes;
fecd2382 3396{
af6f39b4
DE		 3397 int nalign;
3398 char *p;
4c67b523 3399
af6f39b4
DE		 3400 /* Only do this if we are enforcing aligned data. */
3401 if (! enforce_aligned_data)
3402 return;
3403
3404 if (sparc_no_align_cons)
3405 {
3406 /* This is an unaligned pseudo-op. */
3407 sparc_no_align_cons = 0;
3408 return;
3409 }
3410
4a07363f 3411 nalign = log2 (nbytes);
af6f39b4
DE		 3412 if (nalign == 0)
3413 return;
3414
4a07363f
ILT		 3415 assert (nalign > 0);
3416
af6f39b4
DE		 3417 if (now_seg == absolute_section)
3418 {
3419 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
48401fcf 3420 as_bad (_("misaligned data"));
af6f39b4
DE		 3421 return;
3422 }
3423
3424 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
3425 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
3426
3427 record_alignment (now_seg, nalign);
428d312b 3428}
fecd2382 3429
af6f39b4
DE		 3430/* This is where we do the unexpected alignment check.
3431 This is called from HANDLE_ALIGN in tc-sparc.h. */
3432
3433void
3434sparc_handle_align (fragp)
3435 fragS *fragp;
3436{
7532235c 3437 if (fragp->fr_type == rs_align_code && !fragp->fr_subtype
af6f39b4 3438 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
48401fcf 3439 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
7532235c
RH		 3440 if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
3441 {
3442 int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
3443
04a92367
ILT		 3444 if (count >= 4
3445 && !(count & 3)
3446 && count <= 1024
3447 && !((long)(fragp->fr_literal + fragp->fr_fix) & 3))
7532235c
RH		 3448 {
3449 unsigned *p = (unsigned *)(fragp->fr_literal + fragp->fr_fix);
3450 int i;
3451
a5002978
CM		 3452 for (i = 0; i < count; i += 4, p++)
3453 if (INSN_BIG_ENDIAN)
3454 number_to_chars_bigendian ((char *)p, 0x01000000, 4); /* emit nops */
3455 else
3456 number_to_chars_littleendian ((char *)p, 0x10000000, 4);
3457
7532235c 3458 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
a5002978 3459 {
04a92367
ILT		 3460 char *waddr = &fragp->fr_literal[fragp->fr_fix];
3461 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
3462 if (INSN_BIG_ENDIAN)
3463 number_to_chars_bigendian (waddr, wval, 4);
3464 else
3465 number_to_chars_littleendian (waddr, wval, 4);
a5002978 3466 }
7532235c
RH		 3467 fragp->fr_var = count;
3468 }
3469 }
af6f39b4 3470}
1bb6aaad
RH		 3471
3472#ifdef OBJ_ELF
3473/* Some special processing for a Sparc ELF file. */
3474
3475void
3476sparc_elf_final_processing ()
3477{
3478 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
3479 sort of BFD interface for this. */
3480 if (sparc_arch_size == 64)
04a92367
ILT		 3481 {
3482 switch (sparc_memory_model)
3483 {
3484 case MM_RMO:
3485 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
3486 break;
3487 case MM_PSO:
3488 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
3489 break;
3490 default:
3491 break;
3492 }
3493 }
1bb6aaad
RH		 3494 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
3495 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
3496 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
3497 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
3498}
3499#endif
fc23c14e
SC		 3500
3501/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3502 reloc for a cons. We could use the definition there, except that
3503 we want to handle little endian relocs specially. */
3504
3505void
3506cons_fix_new_sparc (frag, where, nbytes, exp)
3507 fragS *frag;
3508 int where;
3509 unsigned int nbytes;
3510 expressionS *exp;
3511{
3512 bfd_reloc_code_real_type r;
3513
3514 r = (nbytes == 1 ? BFD_RELOC_8 :
3515 (nbytes == 2 ? BFD_RELOC_16 :
3516 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
3517
b9089139
RH		 3518 if (target_little_endian_data && nbytes == 4
3519 && now_seg->flags & SEC_ALLOC)
3520 r = BFD_RELOC_SPARC_REV32;
fc23c14e
SC		 3521 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
3522}
GDB Binutils - Deliverables
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