Commit | Line | Data |
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fecd2382 | 1 | /* tc-sparc.c -- Assemble for the SPARC |
48401fcf | 2 | Copyright (C) 1989, 90-96, 97, 1998 Free Software Foundation, Inc. |
fecd2382 | 3 | This file is part of GAS, the GNU Assembler. |
355afbcd | 4 | |
fecd2382 RP |
5 | GAS is free software; you can redistribute it and/or modify |
6 | it under the terms of the GNU General Public License as published by | |
6321e9ea | 7 | the Free Software Foundation; either version 2, or (at your option) |
fecd2382 | 8 | any later version. |
355afbcd | 9 | |
fecd2382 RP |
10 | GAS is distributed in the hope that it will be useful, |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
355afbcd | 14 | |
8dd07a84 ILT |
15 | You should have received a copy of the GNU General Public |
16 | License along with GAS; see the file COPYING. If not, write | |
17 | to the Free Software Foundation, 59 Temple Place - Suite 330, | |
18 | Boston, MA 02111-1307, USA. */ | |
fecd2382 | 19 | |
fecd2382 RP |
20 | #include <stdio.h> |
21 | #include <ctype.h> | |
22 | ||
23 | #include "as.h" | |
7ab2e983 | 24 | #include "subsegs.h" |
fecd2382 | 25 | |
584a0f78 | 26 | #include "opcode/sparc.h" |
fecd2382 | 27 | |
48401fcf | 28 | #ifdef OBJ_ELF |
1bb6aaad | 29 | #include "elf/sparc.h" |
48401fcf | 30 | #endif |
1bb6aaad | 31 | |
54b9ebdd DE |
32 | static struct sparc_arch *lookup_arch PARAMS ((char *)); |
33 | static void init_default_arch PARAMS ((void)); | |
ed94c2b8 | 34 | static void sparc_ip PARAMS ((char *, const struct sparc_opcode **)); |
9f6da653 | 35 | static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); |
54b9ebdd | 36 | static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma)); |
9f6da653 DE |
37 | static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); |
38 | static int sparc_ffs PARAMS ((unsigned int)); | |
39 | static bfd_vma BSR PARAMS ((bfd_vma, int)); | |
40 | static int cmp_reg_entry PARAMS ((const PTR, const PTR)); | |
41 | static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *)); | |
42 | static int parse_const_expr_arg PARAMS ((char **, int *)); | |
af6f39b4 | 43 | static int get_expression PARAMS ((char *str)); |
fecd2382 | 44 | |
54b9ebdd DE |
45 | /* Default architecture. */ |
46 | /* ??? The default value should be V8, but sparclite support was added | |
47 | by making it the default. GCC now passes -Asparclite, so maybe sometime in | |
48 | the future we can set this to V8. */ | |
49 | #ifndef DEFAULT_ARCH | |
50 | #define DEFAULT_ARCH "sparclite" | |
51 | #endif | |
52 | static char *default_arch = DEFAULT_ARCH; | |
53 | ||
54 | /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' | |
55 | have been set. */ | |
56 | static int default_init_p; | |
57 | ||
e70ad5d5 DE |
58 | /* Current architecture. We don't bump up unless necessary. */ |
59 | static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; | |
60 | ||
61 | /* The maximum architecture level we can bump up to. | |
62 | In a 32 bit environment, don't allow bumping up to v9 by default. | |
2b063e6d | 63 | The native assembler works this way. The user is required to pass |
e70ad5d5 | 64 | an explicit argument before we'll create v9 object files. However, if |
54b9ebdd DE |
65 | we don't see any v9 insns, a v8plus object file is not created. */ |
66 | static enum sparc_opcode_arch_val max_architecture; | |
67 | ||
68 | /* Either 32 or 64, selects file format. */ | |
69 | static int sparc_arch_size; | |
595da85d DE |
70 | /* Initial (default) value, recorded separately in case a user option |
71 | changes the value before md_show_usage is called. */ | |
72 | static int default_arch_size; | |
6df07e7f | 73 | |
48401fcf TT |
74 | #ifdef OBJ_ELF |
75 | /* The currently selected v9 memory model. Currently only used for | |
76 | ELF. */ | |
77 | static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; | |
78 | #endif | |
79 | ||
428d312b KR |
80 | static int architecture_requested; |
81 | static int warn_on_bump; | |
839df5c3 | 82 | |
e70ad5d5 DE |
83 | /* If warn_on_bump and the needed architecture is higher than this |
84 | architecture, issue a warning. */ | |
85 | static enum sparc_opcode_arch_val warn_after_architecture; | |
86 | ||
4c67b523 ILT |
87 | /* Non-zero if we are generating PIC code. */ |
88 | int sparc_pic_code; | |
89 | ||
2b063e6d ILT |
90 | /* Non-zero if we should give an error when misaligned data is seen. */ |
91 | static int enforce_aligned_data; | |
92 | ||
ed9638af KR |
93 | extern int target_big_endian; |
94 | ||
fc23c14e SC |
95 | static int target_little_endian_data; |
96 | ||
48401fcf TT |
97 | /* V9 and 86x have big and little endian data, but instructions are always big |
98 | endian. The sparclet has bi-endian support but both data and insns have | |
99 | the same endianness. Global `target_big_endian' is used for data. | |
100 | The following macro is used for instructions. */ | |
101 | #ifndef INSN_BIG_ENDIAN | |
2b063e6d | 102 | #define INSN_BIG_ENDIAN (target_big_endian \ |
48401fcf | 103 | || default_arch_type == sparc86x \ |
2b063e6d | 104 | || SPARC_OPCODE_ARCH_V9_P (max_architecture)) |
48401fcf | 105 | #endif |
2b063e6d | 106 | |
fecd2382 | 107 | /* handle of the OPCODE hash table */ |
5e0a90a8 | 108 | static struct hash_control *op_hash; |
fecd2382 | 109 | |
4a07363f | 110 | static int log2 PARAMS ((int)); |
7766838e ILT |
111 | static void s_data1 PARAMS ((void)); |
112 | static void s_seg PARAMS ((int)); | |
113 | static void s_proc PARAMS ((int)); | |
114 | static void s_reserve PARAMS ((int)); | |
115 | static void s_common PARAMS ((int)); | |
8dd07a84 ILT |
116 | static void s_empty PARAMS ((int)); |
117 | static void s_uacons PARAMS ((int)); | |
428d312b | 118 | |
355afbcd KR |
119 | const pseudo_typeS md_pseudo_table[] = |
120 | { | |
121 | {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */ | |
122 | {"common", s_common, 0}, | |
8dd07a84 | 123 | {"empty", s_empty, 0}, |
355afbcd KR |
124 | {"global", s_globl, 0}, |
125 | {"half", cons, 2}, | |
126 | {"optim", s_ignore, 0}, | |
127 | {"proc", s_proc, 0}, | |
128 | {"reserve", s_reserve, 0}, | |
129 | {"seg", s_seg, 0}, | |
130 | {"skip", s_space, 0}, | |
131 | {"word", cons, 4}, | |
7766838e | 132 | {"xword", cons, 8}, |
2b063e6d ILT |
133 | {"uahalf", s_uacons, 2}, |
134 | {"uaword", s_uacons, 4}, | |
135 | {"uaxword", s_uacons, 8}, | |
693b21e7 | 136 | #ifdef OBJ_ELF |
693b21e7 KR |
137 | /* these are specific to sparc/svr4 */ |
138 | {"pushsection", obj_elf_section, 0}, | |
139 | {"popsection", obj_elf_previous, 0}, | |
2b063e6d ILT |
140 | {"2byte", s_uacons, 2}, |
141 | {"4byte", s_uacons, 4}, | |
142 | {"8byte", s_uacons, 8}, | |
693b21e7 | 143 | #endif |
355afbcd | 144 | {NULL, 0, 0}, |
fecd2382 RP |
145 | }; |
146 | ||
355afbcd | 147 | const int md_reloc_size = 12; /* Size of relocation record */ |
fecd2382 RP |
148 | |
149 | /* This array holds the chars that always start a comment. If the | |
150 | pre-processor is disabled, these aren't very useful */ | |
839df5c3 | 151 | const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */ |
fecd2382 RP |
152 | |
153 | /* This array holds the chars that only start a comment at the beginning of | |
154 | a line. If the line seems to have the form '# 123 filename' | |
155 | .line and .file directives will appear in the pre-processed output */ | |
156 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
157 | first line of the input file. This is because the compiler outputs | |
158 | #NO_APP at the beginning of its output. */ | |
839df5c3 RP |
159 | /* Also note that comments started like this one will always |
160 | work if '/' isn't otherwise defined. */ | |
161 | const char line_comment_chars[] = "#"; | |
fecd2382 | 162 | |
355afbcd KR |
163 | const char line_separator_chars[] = ""; |
164 | ||
fecd2382 | 165 | /* Chars that can be used to separate mant from exp in floating point nums */ |
839df5c3 | 166 | const char EXP_CHARS[] = "eE"; |
fecd2382 RP |
167 | |
168 | /* Chars that mean this number is a floating point constant */ | |
169 | /* As in 0f12.456 */ | |
170 | /* or 0d1.2345e12 */ | |
839df5c3 | 171 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
fecd2382 RP |
172 | |
173 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
9b6a882e KR |
174 | changed in read.c. Ideally it shouldn't have to know about it at all, |
175 | but nothing is ideal around here. */ | |
fecd2382 RP |
176 | |
177 | static unsigned char octal[256]; | |
58d4951d | 178 | #define isoctal(c) octal[(unsigned char) (c)] |
355afbcd KR |
179 | static unsigned char toHex[256]; |
180 | ||
181 | struct sparc_it | |
182 | { | |
183 | char *error; | |
184 | unsigned long opcode; | |
185 | struct nlist *nlistp; | |
186 | expressionS exp; | |
187 | int pcrel; | |
428d312b | 188 | bfd_reloc_code_real_type reloc; |
428d312b KR |
189 | }; |
190 | ||
191 | struct sparc_it the_insn, set_insn; | |
192 | ||
9f6da653 DE |
193 | static void output_insn |
194 | PARAMS ((const struct sparc_opcode *, struct sparc_it *)); | |
af6f39b4 | 195 | \f |
54b9ebdd DE |
196 | /* Table of arguments to -A. |
197 | The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect | |
198 | for this use. That table is for opcodes only. This table is for opcodes | |
199 | and file formats. */ | |
200 | ||
48401fcf TT |
201 | enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, |
202 | v8plusa, v9, v9a, v9_64}; | |
203 | ||
54b9ebdd DE |
204 | static struct sparc_arch { |
205 | char *name; | |
206 | char *opcode_arch; | |
48401fcf | 207 | enum sparc_arch_types arch_type; |
595da85d DE |
208 | /* Default word size, as specified during configuration. |
209 | A value of zero means can't be used to specify default architecture. */ | |
210 | int default_arch_size; | |
211 | /* Allowable arg to -A? */ | |
212 | int user_option_p; | |
54b9ebdd | 213 | } sparc_arch_table[] = { |
48401fcf TT |
214 | { "v6", "v6", v6, 0, 1 }, |
215 | { "v7", "v7", v7, 0, 1 }, | |
216 | { "v8", "v8", v8, 32, 1 }, | |
217 | { "sparclet", "sparclet", sparclet, 32, 1 }, | |
218 | { "sparclite", "sparclite", sparclite, 32, 1 }, | |
219 | { "sparc86x", "sparclite", sparc86x, 32, 1 }, | |
220 | { "v8plus", "v9", v9, 0, 1 }, | |
221 | { "v8plusa", "v9a", v9, 0, 1 }, | |
222 | { "v9", "v9", v9, 0, 1 }, | |
223 | { "v9a", "v9a", v9, 0, 1 }, | |
595da85d DE |
224 | /* This exists to allow configure.in/Makefile.in to pass one |
225 | value to specify both the default machine and default word size. */ | |
48401fcf TT |
226 | { "v9-64", "v9", v9, 64, 0 }, |
227 | { NULL, NULL, v8, 0, 0 } | |
54b9ebdd DE |
228 | }; |
229 | ||
48401fcf TT |
230 | /* Variant of default_arch */ |
231 | static enum sparc_arch_types default_arch_type; | |
232 | ||
54b9ebdd DE |
233 | static struct sparc_arch * |
234 | lookup_arch (name) | |
235 | char *name; | |
236 | { | |
237 | struct sparc_arch *sa; | |
238 | ||
239 | for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) | |
240 | if (strcmp (sa->name, name) == 0) | |
241 | break; | |
242 | if (sa->name == NULL) | |
243 | return NULL; | |
244 | return sa; | |
245 | } | |
246 | ||
247 | /* Initialize the default opcode arch and word size from the default | |
248 | architecture name. */ | |
249 | ||
250 | static void | |
251 | init_default_arch () | |
252 | { | |
253 | struct sparc_arch *sa = lookup_arch (default_arch); | |
254 | ||
595da85d DE |
255 | if (sa == NULL |
256 | || sa->default_arch_size == 0) | |
48401fcf | 257 | as_fatal (_("Invalid default architecture, broken assembler.")); |
54b9ebdd DE |
258 | |
259 | max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); | |
260 | if (max_architecture == SPARC_OPCODE_ARCH_BAD) | |
48401fcf | 261 | as_fatal (_("Bad opcode table, broken assembler.")); |
595da85d | 262 | default_arch_size = sparc_arch_size = sa->default_arch_size; |
54b9ebdd | 263 | default_init_p = 1; |
48401fcf | 264 | default_arch_type = sa->arch_type; |
54b9ebdd DE |
265 | } |
266 | ||
267 | /* Called by TARGET_FORMAT. */ | |
268 | ||
269 | const char * | |
270 | sparc_target_format () | |
271 | { | |
272 | /* We don't get a chance to initialize anything before we're called, | |
273 | so handle that now. */ | |
274 | if (! default_init_p) | |
275 | init_default_arch (); | |
276 | ||
277 | #ifdef OBJ_AOUT | |
278 | #ifdef TE_NetBSD | |
279 | return "a.out-sparc-netbsd"; | |
280 | #else | |
281 | #ifdef TE_SPARCAOUT | |
282 | return target_big_endian ? "a.out-sunos-big" : "a.out-sparc-little"; | |
283 | #else | |
284 | return "a.out-sunos-big"; | |
285 | #endif | |
286 | #endif | |
287 | #endif | |
288 | ||
289 | #ifdef OBJ_BOUT | |
290 | return "b.out.big"; | |
291 | #endif | |
292 | ||
293 | #ifdef OBJ_COFF | |
294 | #ifdef TE_LYNX | |
295 | return "coff-sparc-lynx"; | |
296 | #else | |
297 | return "coff-sparc"; | |
298 | #endif | |
299 | #endif | |
300 | ||
301 | #ifdef OBJ_ELF | |
302 | return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc"; | |
303 | #endif | |
304 | ||
305 | abort (); | |
306 | } | |
307 | \f | |
af6f39b4 DE |
308 | /* |
309 | * md_parse_option | |
310 | * Invocation line includes a switch not recognized by the base assembler. | |
311 | * See if it's a processor-specific option. These are: | |
312 | * | |
313 | * -bump | |
314 | * Warn on architecture bumps. See also -A. | |
315 | * | |
316 | * -Av6, -Av7, -Av8, -Asparclite, -Asparclet | |
317 | * Standard 32 bit architectures. | |
318 | * -Av8plus, -Av8plusa | |
319 | * Sparc64 in a 32 bit world. | |
320 | * -Av9, -Av9a | |
595da85d DE |
321 | * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). |
322 | * This used to only mean 64 bits, but properly specifying it | |
323 | * complicated gcc's ASM_SPECs, so now opcode selection is | |
324 | * specified orthogonally to word size (except when specifying | |
325 | * the default, but that is an internal implementation detail). | |
af6f39b4 DE |
326 | * -xarch=v8plus, -xarch=v8plusa |
327 | * Same as -Av8plus{,a}, for compatibility with Sun's assembler. | |
328 | * | |
329 | * Select the architecture and possibly the file format. | |
330 | * Instructions or features not supported by the selected | |
331 | * architecture cause fatal errors. | |
332 | * | |
333 | * The default is to start at v6, and bump the architecture up | |
54b9ebdd DE |
334 | * whenever an instruction is seen at a higher level. In 32 bit |
335 | * environments, v9 is not bumped up to, the user must pass | |
336 | * -Av8plus{,a}. | |
af6f39b4 DE |
337 | * |
338 | * If -bump is specified, a warning is printing when bumping to | |
339 | * higher levels. | |
340 | * | |
341 | * If an architecture is specified, all instructions must match | |
342 | * that architecture. Any higher level instructions are flagged | |
343 | * as errors. Note that in the 32 bit environment specifying | |
54b9ebdd DE |
344 | * -Av8plus does not automatically create a v8plus object file, a |
345 | * v9 insn must be seen. | |
af6f39b4 DE |
346 | * |
347 | * If both an architecture and -bump are specified, the | |
348 | * architecture starts at the specified level, but bumps are | |
349 | * warnings. Note that we can't set `current_architecture' to | |
350 | * the requested level in this case: in the 32 bit environment, | |
54b9ebdd DE |
351 | * we still must avoid creating v8plus object files unless v9 |
352 | * insns are seen. | |
af6f39b4 DE |
353 | * |
354 | * Note: | |
355 | * Bumping between incompatible architectures is always an | |
356 | * error. For example, from sparclite to v9. | |
357 | */ | |
9f6da653 | 358 | |
af6f39b4 DE |
359 | #ifdef OBJ_ELF |
360 | CONST char *md_shortopts = "A:K:VQ:sq"; | |
361 | #else | |
362 | #ifdef OBJ_AOUT | |
363 | CONST char *md_shortopts = "A:k"; | |
364 | #else | |
365 | CONST char *md_shortopts = "A:"; | |
366 | #endif | |
367 | #endif | |
368 | struct option md_longopts[] = { | |
369 | #define OPTION_BUMP (OPTION_MD_BASE) | |
370 | {"bump", no_argument, NULL, OPTION_BUMP}, | |
371 | #define OPTION_SPARC (OPTION_MD_BASE + 1) | |
372 | {"sparc", no_argument, NULL, OPTION_SPARC}, | |
373 | #define OPTION_XARCH (OPTION_MD_BASE + 2) | |
374 | {"xarch", required_argument, NULL, OPTION_XARCH}, | |
595da85d DE |
375 | #ifdef OBJ_ELF |
376 | #define OPTION_32 (OPTION_MD_BASE + 3) | |
377 | {"32", no_argument, NULL, OPTION_32}, | |
378 | #define OPTION_64 (OPTION_MD_BASE + 4) | |
379 | {"64", no_argument, NULL, OPTION_64}, | |
1bb6aaad RH |
380 | #define OPTION_TSO (OPTION_MD_BASE + 5) |
381 | {"TSO", no_argument, NULL, OPTION_TSO}, | |
382 | #define OPTION_PSO (OPTION_MD_BASE + 6) | |
383 | {"PSO", no_argument, NULL, OPTION_PSO}, | |
384 | #define OPTION_RMO (OPTION_MD_BASE + 7) | |
385 | {"RMO", no_argument, NULL, OPTION_RMO}, | |
595da85d | 386 | #endif |
af6f39b4 | 387 | #ifdef SPARC_BIENDIAN |
1bb6aaad | 388 | #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) |
af6f39b4 | 389 | {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, |
1bb6aaad | 390 | #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) |
af6f39b4 DE |
391 | {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, |
392 | #endif | |
1bb6aaad | 393 | #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) |
af6f39b4 | 394 | {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, |
fc23c14e SC |
395 | #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) |
396 | {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, | |
af6f39b4 DE |
397 | {NULL, no_argument, NULL, 0} |
398 | }; | |
399 | size_t md_longopts_size = sizeof(md_longopts); | |
8dd07a84 | 400 | |
af6f39b4 DE |
401 | int |
402 | md_parse_option (c, arg) | |
403 | int c; | |
404 | char *arg; | |
7ab2e983 | 405 | { |
54b9ebdd DE |
406 | /* We don't get a chance to initialize anything before we're called, |
407 | so handle that now. */ | |
408 | if (! default_init_p) | |
409 | init_default_arch (); | |
410 | ||
af6f39b4 DE |
411 | switch (c) |
412 | { | |
413 | case OPTION_BUMP: | |
414 | warn_on_bump = 1; | |
415 | warn_after_architecture = SPARC_OPCODE_ARCH_V6; | |
416 | break; | |
7ab2e983 | 417 | |
af6f39b4 | 418 | case OPTION_XARCH: |
54b9ebdd DE |
419 | /* This is for compatibility with Sun's assembler. */ |
420 | if (strcmp (arg, "v8plus") != 0 | |
421 | && strcmp (arg, "v8plusa") != 0) | |
af6f39b4 | 422 | { |
48401fcf | 423 | as_bad (_("invalid architecture -xarch=%s"), arg); |
af6f39b4 DE |
424 | return 0; |
425 | } | |
8dd07a84 | 426 | |
af6f39b4 | 427 | /* fall through */ |
8dd07a84 | 428 | |
af6f39b4 DE |
429 | case 'A': |
430 | { | |
54b9ebdd DE |
431 | struct sparc_arch *sa; |
432 | enum sparc_opcode_arch_val opcode_arch; | |
d8b42b96 | 433 | |
54b9ebdd | 434 | sa = lookup_arch (arg); |
595da85d DE |
435 | if (sa == NULL |
436 | || ! sa->user_option_p) | |
af6f39b4 | 437 | { |
48401fcf | 438 | as_bad (_("invalid architecture -A%s"), arg); |
af6f39b4 DE |
439 | return 0; |
440 | } | |
d8b42b96 | 441 | |
54b9ebdd DE |
442 | opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); |
443 | if (opcode_arch == SPARC_OPCODE_ARCH_BAD) | |
48401fcf | 444 | as_fatal (_("Bad opcode table, broken assembler.")); |
54b9ebdd DE |
445 | |
446 | max_architecture = opcode_arch; | |
af6f39b4 DE |
447 | architecture_requested = 1; |
448 | } | |
449 | break; | |
d8b42b96 | 450 | |
af6f39b4 DE |
451 | case OPTION_SPARC: |
452 | /* Ignore -sparc, used by SunOS make default .s.o rule. */ | |
453 | break; | |
2b063e6d | 454 | |
af6f39b4 DE |
455 | case OPTION_ENFORCE_ALIGNED_DATA: |
456 | enforce_aligned_data = 1; | |
457 | break; | |
a87b3269 | 458 | |
af6f39b4 DE |
459 | #ifdef SPARC_BIENDIAN |
460 | case OPTION_LITTLE_ENDIAN: | |
fc23c14e SC |
461 | target_big_endian = 0; |
462 | if (default_arch_type != sparclet) | |
463 | as_fatal ("This target does not support -EL"); | |
464 | break; | |
465 | case OPTION_LITTLE_ENDIAN_DATA: | |
466 | target_little_endian_data = 1; | |
af6f39b4 | 467 | target_big_endian = 0; |
48401fcf | 468 | if (default_arch_type != sparc86x |
48401fcf | 469 | && default_arch_type != v9) |
fc23c14e | 470 | as_fatal ("This target does not support --little-endian-data"); |
af6f39b4 DE |
471 | break; |
472 | case OPTION_BIG_ENDIAN: | |
473 | target_big_endian = 1; | |
474 | break; | |
475 | #endif | |
fecd2382 | 476 | |
af6f39b4 DE |
477 | #ifdef OBJ_AOUT |
478 | case 'k': | |
479 | sparc_pic_code = 1; | |
480 | break; | |
481 | #endif | |
2b063e6d | 482 | |
af6f39b4 | 483 | #ifdef OBJ_ELF |
595da85d DE |
484 | case OPTION_32: |
485 | case OPTION_64: | |
486 | { | |
487 | const char **list, **l; | |
488 | ||
489 | sparc_arch_size = c == OPTION_32 ? 32 : 64; | |
490 | list = bfd_target_list (); | |
491 | for (l = list; *l != NULL; l++) | |
492 | { | |
493 | if (sparc_arch_size == 32) | |
494 | { | |
495 | if (strcmp (*l, "elf32-sparc") == 0) | |
496 | break; | |
497 | } | |
498 | else | |
499 | { | |
500 | if (strcmp (*l, "elf64-sparc") == 0) | |
501 | break; | |
502 | } | |
503 | } | |
504 | if (*l == NULL) | |
48401fcf | 505 | as_fatal (_("No compiled in support for %d bit object file format"), |
595da85d DE |
506 | sparc_arch_size); |
507 | free (list); | |
508 | } | |
509 | break; | |
510 | ||
1bb6aaad RH |
511 | case OPTION_TSO: |
512 | sparc_memory_model = MM_TSO; | |
513 | break; | |
514 | ||
515 | case OPTION_PSO: | |
516 | sparc_memory_model = MM_PSO; | |
517 | break; | |
518 | ||
519 | case OPTION_RMO: | |
520 | sparc_memory_model = MM_RMO; | |
521 | break; | |
522 | ||
af6f39b4 DE |
523 | case 'V': |
524 | print_version_id (); | |
525 | break; | |
fecd2382 | 526 | |
af6f39b4 DE |
527 | case 'Q': |
528 | /* Qy - do emit .comment | |
529 | Qn - do not emit .comment */ | |
530 | break; | |
ed94c2b8 | 531 | |
af6f39b4 DE |
532 | case 's': |
533 | /* use .stab instead of .stab.excl */ | |
534 | break; | |
584a0f78 | 535 | |
af6f39b4 DE |
536 | case 'q': |
537 | /* quick -- native assembler does fewer checks */ | |
538 | break; | |
355afbcd | 539 | |
af6f39b4 DE |
540 | case 'K': |
541 | if (strcmp (arg, "PIC") != 0) | |
48401fcf | 542 | as_warn (_("Unrecognized option following -K")); |
af6f39b4 DE |
543 | else |
544 | sparc_pic_code = 1; | |
545 | break; | |
546 | #endif | |
355afbcd | 547 | |
af6f39b4 DE |
548 | default: |
549 | return 0; | |
355afbcd KR |
550 | } |
551 | ||
af6f39b4 DE |
552 | return 1; |
553 | } | |
355afbcd | 554 | |
af6f39b4 DE |
555 | void |
556 | md_show_usage (stream) | |
557 | FILE *stream; | |
558 | { | |
54b9ebdd | 559 | const struct sparc_arch *arch; |
355afbcd | 560 | |
595da85d DE |
561 | /* We don't get a chance to initialize anything before we're called, |
562 | so handle that now. */ | |
563 | if (! default_init_p) | |
564 | init_default_arch (); | |
565 | ||
48401fcf | 566 | fprintf(stream, _("SPARC options:\n")); |
54b9ebdd | 567 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
355afbcd | 568 | { |
54b9ebdd | 569 | if (arch != &sparc_arch_table[0]) |
af6f39b4 | 570 | fprintf (stream, " | "); |
595da85d DE |
571 | if (arch->user_option_p) |
572 | fprintf (stream, "-A%s", arch->name); | |
9b6a882e | 573 | } |
48401fcf TT |
574 | fprintf (stream, _("\n-xarch=v8plus | -xarch=v8plusa\n")); |
575 | fprintf (stream, _("\ | |
af6f39b4 DE |
576 | specify variant of SPARC architecture\n\ |
577 | -bump warn when assembler switches architectures\n\ | |
578 | -sparc ignored\n\ | |
48401fcf | 579 | --enforce-aligned-data force .long, etc., to be aligned correctly\n")); |
af6f39b4 | 580 | #ifdef OBJ_AOUT |
48401fcf TT |
581 | fprintf (stream, _("\ |
582 | -k generate PIC\n")); | |
af6f39b4 DE |
583 | #endif |
584 | #ifdef OBJ_ELF | |
48401fcf | 585 | fprintf (stream, _("\ |
595da85d | 586 | -32 create 32 bit object file\n\ |
48401fcf TT |
587 | -64 create 64 bit object file\n")); |
588 | fprintf (stream, _("\ | |
589 | [default is %d]\n"), default_arch_size); | |
590 | fprintf (stream, _("\ | |
1bb6aaad RH |
591 | -TSO use Total Store Ordering\n\ |
592 | -PSO use Partial Store Ordering\n\ | |
48401fcf TT |
593 | -RMO use Relaxed Memory Ordering\n")); |
594 | fprintf (stream, _("\ | |
595 | [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); | |
596 | fprintf (stream, _("\ | |
af6f39b4 DE |
597 | -KPIC generate PIC\n\ |
598 | -V print assembler version number\n\ | |
599 | -q ignored\n\ | |
600 | -Qy, -Qn ignored\n\ | |
48401fcf | 601 | -s ignored\n")); |
af6f39b4 DE |
602 | #endif |
603 | #ifdef SPARC_BIENDIAN | |
48401fcf | 604 | fprintf (stream, _("\ |
af6f39b4 | 605 | -EL generate code for a little endian machine\n\ |
fc23c14e | 606 | -EB generate code for a big endian machine\n\ |
04a92367 | 607 | --little-endian-data generate code for a machine having big endian\n\ |
fc23c14e | 608 | instructions and little endian data.")); |
af6f39b4 DE |
609 | #endif |
610 | } | |
611 | \f | |
612 | /* sparc64 priviledged registers */ | |
355afbcd | 613 | |
af6f39b4 DE |
614 | struct priv_reg_entry |
615 | { | |
616 | char *name; | |
617 | int regnum; | |
618 | }; | |
355afbcd | 619 | |
af6f39b4 DE |
620 | struct priv_reg_entry priv_reg_table[] = |
621 | { | |
622 | {"tpc", 0}, | |
623 | {"tnpc", 1}, | |
624 | {"tstate", 2}, | |
625 | {"tt", 3}, | |
626 | {"tick", 4}, | |
627 | {"tba", 5}, | |
628 | {"pstate", 6}, | |
629 | {"tl", 7}, | |
630 | {"pil", 8}, | |
631 | {"cwp", 9}, | |
632 | {"cansave", 10}, | |
633 | {"canrestore", 11}, | |
634 | {"cleanwin", 12}, | |
635 | {"otherwin", 13}, | |
636 | {"wstate", 14}, | |
637 | {"fq", 15}, | |
638 | {"ver", 31}, | |
639 | {"", -1}, /* end marker */ | |
640 | }; | |
355afbcd | 641 | |
1277cdda RH |
642 | /* v9a specific asrs */ |
643 | ||
644 | struct priv_reg_entry v9a_asr_table[] = | |
645 | { | |
646 | {"tick_cmpr", 23}, | |
647 | {"softint", 22}, | |
648 | {"set_softint", 20}, | |
649 | {"pic", 17}, | |
650 | {"pcr", 16}, | |
651 | {"gsr", 19}, | |
652 | {"dcr", 18}, | |
653 | {"clear_softint", 21}, | |
654 | {"", -1}, /* end marker */ | |
655 | }; | |
656 | ||
af6f39b4 DE |
657 | static int |
658 | cmp_reg_entry (parg, qarg) | |
659 | const PTR parg; | |
660 | const PTR qarg; | |
661 | { | |
662 | const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; | |
663 | const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; | |
355afbcd | 664 | |
af6f39b4 DE |
665 | return strcmp (q->name, p->name); |
666 | } | |
667 | \f | |
668 | /* This function is called once, at assembler startup time. It should | |
669 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
670 | ||
671 | void | |
672 | md_begin () | |
673 | { | |
674 | register const char *retval = NULL; | |
675 | int lose = 0; | |
676 | register unsigned int i = 0; | |
677 | ||
54b9ebdd DE |
678 | /* We don't get a chance to initialize anything before md_parse_option |
679 | is called, and it may not be called, so handle default initialization | |
680 | now if not already done. */ | |
681 | if (! default_init_p) | |
682 | init_default_arch (); | |
683 | ||
af6f39b4 DE |
684 | op_hash = hash_new (); |
685 | ||
48401fcf | 686 | while (i < (unsigned int) sparc_num_opcodes) |
af6f39b4 DE |
687 | { |
688 | const char *name = sparc_opcodes[i].name; | |
689 | retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]); | |
690 | if (retval != NULL) | |
355afbcd | 691 | { |
48401fcf | 692 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), |
af6f39b4 DE |
693 | sparc_opcodes[i].name, retval); |
694 | lose = 1; | |
355afbcd | 695 | } |
af6f39b4 | 696 | do |
355afbcd | 697 | { |
af6f39b4 DE |
698 | if (sparc_opcodes[i].match & sparc_opcodes[i].lose) |
699 | { | |
48401fcf | 700 | fprintf (stderr, _("internal error: losing opcode: `%s' \"%s\"\n"), |
af6f39b4 DE |
701 | sparc_opcodes[i].name, sparc_opcodes[i].args); |
702 | lose = 1; | |
703 | } | |
704 | ++i; | |
fecd2382 | 705 | } |
48401fcf | 706 | while (i < (unsigned int) sparc_num_opcodes |
af6f39b4 DE |
707 | && !strcmp (sparc_opcodes[i].name, name)); |
708 | } | |
428d312b | 709 | |
af6f39b4 | 710 | if (lose) |
48401fcf | 711 | as_fatal (_("Broken assembler. No assembly attempted.")); |
355afbcd | 712 | |
af6f39b4 DE |
713 | for (i = '0'; i < '8'; ++i) |
714 | octal[i] = 1; | |
715 | for (i = '0'; i <= '9'; ++i) | |
716 | toHex[i] = i - '0'; | |
717 | for (i = 'a'; i <= 'f'; ++i) | |
718 | toHex[i] = i + 10 - 'a'; | |
719 | for (i = 'A'; i <= 'F'; ++i) | |
720 | toHex[i] = i + 10 - 'A'; | |
355afbcd | 721 | |
af6f39b4 DE |
722 | qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), |
723 | sizeof (priv_reg_table[0]), cmp_reg_entry); | |
355afbcd | 724 | |
af6f39b4 DE |
725 | /* If -bump, record the architecture level at which we start issuing |
726 | warnings. The behaviour is different depending upon whether an | |
727 | architecture was explicitly specified. If it wasn't, we issue warnings | |
728 | for all upwards bumps. If it was, we don't start issuing warnings until | |
729 | we need to bump beyond the requested architecture or when we bump between | |
730 | conflicting architectures. */ | |
355afbcd | 731 | |
af6f39b4 DE |
732 | if (warn_on_bump |
733 | && architecture_requested) | |
355afbcd | 734 | { |
af6f39b4 DE |
735 | /* `max_architecture' records the requested architecture. |
736 | Issue warnings if we go above it. */ | |
737 | warn_after_architecture = max_architecture; | |
428d312b | 738 | |
af6f39b4 DE |
739 | /* Find the highest architecture level that doesn't conflict with |
740 | the requested one. */ | |
741 | for (max_architecture = SPARC_OPCODE_ARCH_MAX; | |
742 | max_architecture > warn_after_architecture; | |
743 | --max_architecture) | |
744 | if (! SPARC_OPCODE_CONFLICT_P (max_architecture, | |
745 | warn_after_architecture)) | |
746 | break; | |
747 | } | |
748 | } | |
428d312b | 749 | |
af6f39b4 | 750 | /* Called after all assembly has been done. */ |
428d312b | 751 | |
af6f39b4 DE |
752 | void |
753 | sparc_md_end () | |
754 | { | |
54b9ebdd DE |
755 | if (sparc_arch_size == 64) |
756 | { | |
757 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
758 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a); | |
759 | else | |
760 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9); | |
761 | } | |
355afbcd KR |
762 | else |
763 | { | |
54b9ebdd DE |
764 | if (current_architecture == SPARC_OPCODE_ARCH_V9) |
765 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus); | |
766 | else if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
767 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa); | |
768 | else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET) | |
769 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet); | |
fc23c14e SC |
770 | else if (default_arch_type == sparc86x && target_little_endian_data) |
771 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le); | |
54b9ebdd DE |
772 | else |
773 | { | |
774 | /* The sparclite is treated like a normal sparc. Perhaps it shouldn't | |
775 | be but for now it is (since that's the way it's always been | |
776 | treated). */ | |
777 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc); | |
778 | } | |
af6f39b4 | 779 | } |
428d312b | 780 | } |
af6f39b4 DE |
781 | \f |
782 | /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ | |
355afbcd | 783 | |
af6f39b4 DE |
784 | static INLINE int |
785 | in_signed_range (val, max) | |
786 | bfd_signed_vma val, max; | |
355afbcd | 787 | { |
af6f39b4 DE |
788 | if (max <= 0) |
789 | abort (); | |
790 | if (val > max) | |
791 | return 0; | |
792 | if (val < ~max) | |
793 | return 0; | |
794 | return 1; | |
795 | } | |
355afbcd | 796 | |
54b9ebdd DE |
797 | /* Return non-zero if VAL is in the range 0 to MAX. */ |
798 | ||
799 | static INLINE int | |
800 | in_unsigned_range (val, max) | |
801 | bfd_vma val, max; | |
802 | { | |
803 | if (val > max) | |
804 | return 0; | |
805 | return 1; | |
806 | } | |
807 | ||
af6f39b4 DE |
808 | /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. |
809 | (e.g. -15 to +31). */ | |
8dd07a84 | 810 | |
af6f39b4 DE |
811 | static INLINE int |
812 | in_bitfield_range (val, max) | |
813 | bfd_signed_vma val, max; | |
8dd07a84 | 814 | { |
af6f39b4 DE |
815 | if (max <= 0) |
816 | abort (); | |
817 | if (val > max) | |
818 | return 0; | |
819 | if (val < ~(max >> 1)) | |
820 | return 0; | |
821 | return 1; | |
8dd07a84 ILT |
822 | } |
823 | ||
af6f39b4 DE |
824 | static int |
825 | sparc_ffs (mask) | |
826 | unsigned int mask; | |
355afbcd | 827 | { |
af6f39b4 | 828 | int i; |
355afbcd | 829 | |
af6f39b4 DE |
830 | if (mask == 0) |
831 | return -1; | |
355afbcd | 832 | |
af6f39b4 DE |
833 | for (i = 0; (mask & 1) == 0; ++i) |
834 | mask >>= 1; | |
835 | return i; | |
c999fd9f | 836 | } |
fecd2382 | 837 | |
af6f39b4 DE |
838 | /* Implement big shift right. */ |
839 | static bfd_vma | |
840 | BSR (val, amount) | |
841 | bfd_vma val; | |
842 | int amount; | |
355afbcd | 843 | { |
af6f39b4 | 844 | if (sizeof (bfd_vma) <= 4 && amount >= 32) |
48401fcf | 845 | as_fatal (_("Support for 64-bit arithmetic not compiled in.")); |
af6f39b4 | 846 | return val >> amount; |
c999fd9f | 847 | } |
af6f39b4 DE |
848 | \f |
849 | /* For communication between sparc_ip and get_expression. */ | |
850 | static char *expr_end; | |
fecd2382 | 851 | |
af6f39b4 DE |
852 | /* For communication between md_assemble and sparc_ip. */ |
853 | static int special_case; | |
8dd07a84 | 854 | |
af6f39b4 DE |
855 | /* Values for `special_case'. |
856 | Instructions that require wierd handling because they're longer than | |
857 | 4 bytes. */ | |
858 | #define SPECIAL_CASE_NONE 0 | |
859 | #define SPECIAL_CASE_SET 1 | |
860 | #define SPECIAL_CASE_SETSW 2 | |
861 | #define SPECIAL_CASE_SETX 3 | |
862 | /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ | |
863 | #define SPECIAL_CASE_FDIV 4 | |
8dd07a84 | 864 | |
af6f39b4 DE |
865 | /* Bit masks of various insns. */ |
866 | #define NOP_INSN 0x01000000 | |
867 | #define OR_INSN 0x80100000 | |
868 | #define FMOVS_INSN 0x81A00020 | |
869 | #define SETHI_INSN 0x01000000 | |
870 | #define SLLX_INSN 0x81281000 | |
871 | #define SRA_INSN 0x81380000 | |
8dd07a84 | 872 | |
af6f39b4 DE |
873 | /* The last instruction to be assembled. */ |
874 | static const struct sparc_opcode *last_insn; | |
875 | /* The assembled opcode of `last_insn'. */ | |
876 | static unsigned long last_opcode; | |
877 | \f | |
878 | /* Main entry point to assemble one instruction. */ | |
879 | ||
880 | void | |
881 | md_assemble (str) | |
882 | char *str; | |
8dd07a84 | 883 | { |
af6f39b4 | 884 | const struct sparc_opcode *insn; |
355afbcd KR |
885 | |
886 | know (str); | |
af6f39b4 | 887 | special_case = SPECIAL_CASE_NONE; |
ed94c2b8 ILT |
888 | sparc_ip (str, &insn); |
889 | ||
9f6da653 DE |
890 | /* We warn about attempts to put a floating point branch in a delay slot, |
891 | unless the delay slot has been annulled. */ | |
ed94c2b8 ILT |
892 | if (insn != NULL |
893 | && last_insn != NULL | |
894 | && (insn->flags & F_FBR) != 0 | |
9f6da653 DE |
895 | && (last_insn->flags & F_DELAYED) != 0 |
896 | /* ??? This test isn't completely accurate. We assume anything with | |
897 | F_{UNBR,CONDBR,FBR} set is annullable. */ | |
898 | && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 | |
899 | || (last_opcode & ANNUL) == 0)) | |
48401fcf | 900 | as_warn (_("FP branch in delay slot")); |
ed94c2b8 ILT |
901 | |
902 | /* SPARC before v9 requires a nop instruction between a floating | |
903 | point instruction and a floating point branch. We insert one | |
904 | automatically, with a warning. */ | |
905 | if (max_architecture < SPARC_OPCODE_ARCH_V9 | |
906 | && insn != NULL | |
907 | && last_insn != NULL | |
908 | && (insn->flags & F_FBR) != 0 | |
909 | && (last_insn->flags & F_FLOAT) != 0) | |
910 | { | |
2b063e6d ILT |
911 | struct sparc_it nop_insn; |
912 | ||
913 | nop_insn.opcode = NOP_INSN; | |
914 | nop_insn.reloc = BFD_RELOC_NONE; | |
915 | output_insn (insn, &nop_insn); | |
48401fcf | 916 | as_warn (_("FP branch preceded by FP instruction; NOP inserted")); |
ed94c2b8 | 917 | } |
355afbcd | 918 | |
2b063e6d | 919 | switch (special_case) |
355afbcd | 920 | { |
af6f39b4 | 921 | case SPECIAL_CASE_NONE: |
2b063e6d ILT |
922 | /* normal insn */ |
923 | output_insn (insn, &the_insn); | |
924 | break; | |
355afbcd | 925 | |
2b063e6d ILT |
926 | case SPECIAL_CASE_SET: |
927 | { | |
928 | int need_hi22_p = 0; | |
355afbcd | 929 | |
2b063e6d ILT |
930 | /* "set" is not defined for negative numbers in v9: it doesn't yield |
931 | what you expect it to. */ | |
932 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture) | |
933 | && the_insn.exp.X_op == O_constant) | |
934 | { | |
935 | if (the_insn.exp.X_add_number < 0) | |
48401fcf TT |
936 | as_warn (_("set: used with negative number")); |
937 | else if (the_insn.exp.X_add_number > (offsetT) 0xffffffff) | |
938 | as_warn (_("set: number larger than 4294967295")); | |
2b063e6d | 939 | } |
428d312b | 940 | |
2b063e6d ILT |
941 | /* See if operand is absolute and small; skip sethi if so. */ |
942 | if (the_insn.exp.X_op != O_constant | |
943 | || the_insn.exp.X_add_number >= (1 << 12) | |
944 | || the_insn.exp.X_add_number < -(1 << 12)) | |
945 | { | |
946 | output_insn (insn, &the_insn); | |
947 | need_hi22_p = 1; | |
948 | } | |
949 | /* See if operand has no low-order bits; skip OR if so. */ | |
950 | if (the_insn.exp.X_op != O_constant | |
951 | || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) | |
952 | || ! need_hi22_p) | |
953 | { | |
954 | int rd = (the_insn.opcode & RD (~0)) >> 25; | |
955 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) | |
956 | | RD (rd) | |
957 | | IMMED | |
958 | | (the_insn.exp.X_add_number | |
959 | & (need_hi22_p ? 0x3ff : 0x1fff))); | |
960 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
961 | ? BFD_RELOC_LO10 | |
962 | : BFD_RELOC_NONE); | |
963 | output_insn (insn, &the_insn); | |
964 | } | |
965 | break; | |
966 | } | |
ed94c2b8 | 967 | |
2b063e6d ILT |
968 | case SPECIAL_CASE_SETSW: |
969 | { | |
970 | /* FIXME: Not finished. */ | |
971 | break; | |
972 | } | |
355afbcd | 973 | |
2b063e6d ILT |
974 | case SPECIAL_CASE_SETX: |
975 | { | |
976 | #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000) | |
977 | int upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); | |
978 | int lower32 = SIGNEXT32 (the_insn.exp.X_add_number); | |
979 | #undef SIGNEXT32 | |
980 | int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; | |
981 | int dstreg = (the_insn.opcode & RD (~0)) >> 25; | |
982 | /* Output directly to dst reg if lower 32 bits are all zero. */ | |
983 | int upper_dstreg = (the_insn.exp.X_op == O_constant | |
984 | && lower32 == 0) ? dstreg : tmpreg; | |
985 | int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; | |
986 | ||
987 | /* The tmp reg should not be the dst reg. */ | |
988 | if (tmpreg == dstreg) | |
48401fcf | 989 | as_warn (_("setx: temporary register same as destination register")); |
2b063e6d ILT |
990 | |
991 | /* Reset X_add_number, we've extracted it as upper32/lower32. | |
992 | Otherwise fixup_segment will complain about not being able to | |
993 | write an 8 byte number in a 4 byte field. */ | |
994 | the_insn.exp.X_add_number = 0; | |
995 | ||
996 | /* ??? Obviously there are other optimizations we can do | |
997 | (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be | |
998 | doing some of these. Later. If you do change things, try to | |
999 | change all of this to be table driven as well. */ | |
1000 | ||
1001 | /* What to output depends on the number if it's constant. | |
1002 | Compute that first, then output what we've decided upon. */ | |
1003 | if (the_insn.exp.X_op != O_constant) | |
1004 | need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; | |
1005 | else | |
1006 | { | |
1007 | /* Only need hh22 if `or' insn can't handle constant. */ | |
1008 | if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) | |
1009 | need_hh22_p = 1; | |
1010 | ||
1011 | /* Does bottom part (after sethi) have bits? */ | |
1012 | if ((need_hh22_p && (upper32 & 0x3ff) != 0) | |
1013 | /* No hh22, but does upper32 still have bits we can't set | |
1014 | from lower32? */ | |
1015 | || (! need_hh22_p | |
1016 | && upper32 != 0 | |
1017 | && (upper32 != -1 || lower32 >= 0))) | |
1018 | need_hm10_p = 1; | |
1019 | ||
1020 | /* If the lower half is all zero, we build the upper half directly | |
1021 | into the dst reg. */ | |
1022 | if (lower32 != 0 | |
1023 | /* Need lower half if number is zero. */ | |
1024 | || (! need_hh22_p && ! need_hm10_p)) | |
1025 | { | |
1026 | /* No need for sethi if `or' insn can handle constant. */ | |
1027 | if (lower32 < -(1 << 12) || lower32 >= (1 << 12) | |
1028 | /* Note that we can't use a negative constant in the `or' | |
1029 | insn unless the upper 32 bits are all ones. */ | |
1030 | || (lower32 < 0 && upper32 != -1)) | |
1031 | need_hi22_p = 1; | |
1032 | ||
1033 | /* Does bottom part (after sethi) have bits? */ | |
1034 | if ((need_hi22_p && (lower32 & 0x3ff) != 0) | |
1035 | /* No sethi. */ | |
1036 | || (! need_hi22_p && (lower32 & 0x1fff) != 0) | |
1037 | /* Need `or' if we didn't set anything else. */ | |
1038 | || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) | |
1039 | need_lo10_p = 1; | |
1040 | } | |
1041 | } | |
355afbcd | 1042 | |
2b063e6d ILT |
1043 | if (need_hh22_p) |
1044 | { | |
1045 | the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) | |
1046 | | ((upper32 >> 10) & 0x3fffff)); | |
1047 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1048 | ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); | |
1049 | output_insn (insn, &the_insn); | |
1050 | } | |
1051 | ||
1052 | if (need_hm10_p) | |
1053 | { | |
1054 | the_insn.opcode = (OR_INSN | |
1055 | | (need_hh22_p ? RS1 (upper_dstreg) : 0) | |
1056 | | RD (upper_dstreg) | |
1057 | | IMMED | |
1058 | | (upper32 | |
1059 | & (need_hh22_p ? 0x3ff : 0x1fff))); | |
1060 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1061 | ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); | |
1062 | output_insn (insn, &the_insn); | |
1063 | } | |
1064 | ||
1065 | if (need_hi22_p) | |
1066 | { | |
1067 | the_insn.opcode = (SETHI_INSN | RD (dstreg) | |
1068 | | ((lower32 >> 10) & 0x3fffff)); | |
1069 | the_insn.reloc = BFD_RELOC_HI22; | |
1070 | output_insn (insn, &the_insn); | |
1071 | } | |
1072 | ||
1073 | if (need_lo10_p) | |
1074 | { | |
1075 | /* FIXME: One nice optimization to do here is to OR the low part | |
1076 | with the highpart if hi22 isn't needed and the low part is | |
1077 | positive. */ | |
1078 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) | |
1079 | | RD (dstreg) | |
1080 | | IMMED | |
1081 | | (lower32 | |
1082 | & (need_hi22_p ? 0x3ff : 0x1fff))); | |
1083 | the_insn.reloc = BFD_RELOC_LO10; | |
1084 | output_insn (insn, &the_insn); | |
1085 | } | |
1086 | ||
1087 | /* If we needed to build the upper part, shift it into place. */ | |
1088 | if (need_hh22_p || need_hm10_p) | |
1089 | { | |
1090 | the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) | |
1091 | | IMMED | 32); | |
1092 | the_insn.reloc = BFD_RELOC_NONE; | |
1093 | output_insn (insn, &the_insn); | |
1094 | } | |
1095 | ||
1096 | /* If we needed to build both upper and lower parts, OR them together. */ | |
1097 | if ((need_hh22_p || need_hm10_p) | |
1098 | && (need_hi22_p || need_lo10_p)) | |
1099 | { | |
1100 | the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) | |
1101 | | RD (dstreg)); | |
1102 | the_insn.reloc = BFD_RELOC_NONE; | |
1103 | output_insn (insn, &the_insn); | |
1104 | } | |
1105 | /* We didn't need both regs, but we may have to sign extend lower32. */ | |
1106 | else if (need_hi22_p && upper32 == -1) | |
1107 | { | |
1108 | the_insn.opcode = (SRA_INSN | RS1 (dstreg) | RD (dstreg) | |
1109 | | IMMED | 0); | |
1110 | the_insn.reloc = BFD_RELOC_NONE; | |
1111 | output_insn (insn, &the_insn); | |
1112 | } | |
1113 | break; | |
1114 | } | |
1115 | ||
1116 | case SPECIAL_CASE_FDIV: | |
1117 | { | |
1118 | int rd = (the_insn.opcode >> 25) & 0x1f; | |
1119 | ||
1120 | output_insn (insn, &the_insn); | |
1121 | ||
1122 | /* According to information leaked from Sun, the "fdiv" instructions | |
1123 | on early SPARC machines would produce incorrect results sometimes. | |
1124 | The workaround is to add an fmovs of the destination register to | |
1125 | itself just after the instruction. This was true on machines | |
1126 | with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ | |
1127 | assert (the_insn.reloc == BFD_RELOC_NONE); | |
1128 | the_insn.opcode = FMOVS_INSN | rd | RD (rd); | |
1129 | output_insn (insn, &the_insn); | |
1130 | break; | |
1131 | } | |
355afbcd KR |
1132 | |
1133 | default: | |
48401fcf | 1134 | as_fatal (_("failed special case insn sanity check")); |
355afbcd | 1135 | } |
9b6a882e | 1136 | } |
355afbcd | 1137 | |
af6f39b4 | 1138 | /* Subroutine of md_assemble to do the actual parsing. */ |
6df07e7f | 1139 | |
af6f39b4 DE |
1140 | static void |
1141 | sparc_ip (str, pinsn) | |
1142 | char *str; | |
1143 | const struct sparc_opcode **pinsn; | |
fecd2382 | 1144 | { |
355afbcd KR |
1145 | char *error_message = ""; |
1146 | char *s; | |
1147 | const char *args; | |
1148 | char c; | |
a7aa7a2b | 1149 | const struct sparc_opcode *insn; |
355afbcd KR |
1150 | char *argsStart; |
1151 | unsigned long opcode; | |
1152 | unsigned int mask = 0; | |
1153 | int match = 0; | |
1154 | int comma = 0; | |
6df07e7f | 1155 | int v9_arg_p; |
355afbcd | 1156 | |
48401fcf | 1157 | for (s = str; islower ((unsigned char) *s) || (*s >= '0' && *s <= '3'); ++s) |
355afbcd | 1158 | ; |
6df07e7f | 1159 | |
355afbcd KR |
1160 | switch (*s) |
1161 | { | |
355afbcd KR |
1162 | case '\0': |
1163 | break; | |
1164 | ||
1165 | case ',': | |
1166 | comma = 1; | |
1167 | ||
1168 | /*FALLTHROUGH */ | |
1169 | ||
1170 | case ' ': | |
1171 | *s++ = '\0'; | |
1172 | break; | |
1173 | ||
1174 | default: | |
48401fcf | 1175 | as_fatal (_("Unknown opcode: `%s'"), str); |
355afbcd | 1176 | } |
a7aa7a2b | 1177 | insn = (struct sparc_opcode *) hash_find (op_hash, str); |
ed94c2b8 | 1178 | *pinsn = insn; |
a7aa7a2b | 1179 | if (insn == NULL) |
355afbcd | 1180 | { |
48401fcf | 1181 | as_bad (_("Unknown opcode: `%s'"), str); |
355afbcd KR |
1182 | return; |
1183 | } | |
1184 | if (comma) | |
1185 | { | |
1186 | *--s = ','; | |
1187 | } | |
6df07e7f | 1188 | |
355afbcd KR |
1189 | argsStart = s; |
1190 | for (;;) | |
1191 | { | |
1192 | opcode = insn->match; | |
1193 | memset (&the_insn, '\0', sizeof (the_insn)); | |
428d312b | 1194 | the_insn.reloc = BFD_RELOC_NONE; |
6df07e7f | 1195 | v9_arg_p = 0; |
355afbcd KR |
1196 | |
1197 | /* | |
8fc0776d JW |
1198 | * Build the opcode, checking as we go to make |
1199 | * sure that the operands match | |
1200 | */ | |
355afbcd KR |
1201 | for (args = insn->args;; ++args) |
1202 | { | |
1203 | switch (*args) | |
1204 | { | |
355afbcd KR |
1205 | case 'K': |
1206 | { | |
7766838e | 1207 | int kmask = 0; |
ed9638af KR |
1208 | |
1209 | /* Parse a series of masks. */ | |
1210 | if (*s == '#') | |
355afbcd | 1211 | { |
ed9638af | 1212 | while (*s == '#') |
355afbcd | 1213 | { |
6df07e7f DE |
1214 | int mask; |
1215 | ||
1216 | if (! parse_keyword_arg (sparc_encode_membar, &s, | |
1217 | &mask)) | |
ed9638af | 1218 | { |
48401fcf | 1219 | error_message = _(": invalid membar mask name"); |
ed9638af KR |
1220 | goto error; |
1221 | } | |
6df07e7f DE |
1222 | kmask |= mask; |
1223 | while (*s == ' ') { ++s; continue; } | |
1224 | if (*s == '|' || *s == '+') | |
ed9638af | 1225 | ++s; |
6df07e7f | 1226 | while (*s == ' ') { ++s; continue; } |
355afbcd | 1227 | } |
ed9638af | 1228 | } |
c999fd9f | 1229 | else |
ed9638af | 1230 | { |
6df07e7f DE |
1231 | if (! parse_const_expr_arg (&s, &kmask)) |
1232 | { | |
48401fcf | 1233 | error_message = _(": invalid membar mask expression"); |
6df07e7f DE |
1234 | goto error; |
1235 | } | |
1236 | if (kmask < 0 || kmask > 127) | |
ed9638af | 1237 | { |
48401fcf | 1238 | error_message = _(": invalid membar mask number"); |
ed9638af | 1239 | goto error; |
355afbcd | 1240 | } |
355afbcd | 1241 | } |
c999fd9f | 1242 | |
6df07e7f | 1243 | opcode |= MEMBAR (kmask); |
355afbcd KR |
1244 | continue; |
1245 | } | |
1246 | ||
1247 | case '*': | |
ed9638af | 1248 | { |
6df07e7f | 1249 | int fcn = 0; |
355afbcd | 1250 | |
ed9638af KR |
1251 | /* Parse a prefetch function. */ |
1252 | if (*s == '#') | |
1253 | { | |
6df07e7f | 1254 | if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) |
ed9638af | 1255 | { |
48401fcf | 1256 | error_message = _(": invalid prefetch function name"); |
ed9638af KR |
1257 | goto error; |
1258 | } | |
1259 | } | |
6df07e7f | 1260 | else |
ed9638af | 1261 | { |
6df07e7f | 1262 | if (! parse_const_expr_arg (&s, &fcn)) |
ed9638af | 1263 | { |
48401fcf | 1264 | error_message = _(": invalid prefetch function expression"); |
6df07e7f | 1265 | goto error; |
ed9638af | 1266 | } |
6df07e7f | 1267 | if (fcn < 0 || fcn > 31) |
ed9638af | 1268 | { |
48401fcf | 1269 | error_message = _(": invalid prefetch function number"); |
ed9638af KR |
1270 | goto error; |
1271 | } | |
1272 | } | |
6df07e7f | 1273 | opcode |= RD (fcn); |
ed9638af KR |
1274 | continue; |
1275 | } | |
355afbcd KR |
1276 | |
1277 | case '!': | |
1278 | case '?': | |
6df07e7f | 1279 | /* Parse a sparc64 privileged register. */ |
355afbcd KR |
1280 | if (*s == '%') |
1281 | { | |
1282 | struct priv_reg_entry *p = priv_reg_table; | |
7766838e | 1283 | unsigned int len = 9999999; /* init to make gcc happy */ |
355afbcd KR |
1284 | |
1285 | s += 1; | |
1286 | while (p->name[0] > s[0]) | |
1287 | p++; | |
1288 | while (p->name[0] == s[0]) | |
1289 | { | |
1290 | len = strlen (p->name); | |
1291 | if (strncmp (p->name, s, len) == 0) | |
1292 | break; | |
1293 | p++; | |
1294 | } | |
1295 | if (p->name[0] != s[0]) | |
1296 | { | |
48401fcf | 1297 | error_message = _(": unrecognizable privileged register"); |
355afbcd KR |
1298 | goto error; |
1299 | } | |
1300 | if (*args == '?') | |
1301 | opcode |= (p->regnum << 14); | |
1302 | else | |
1303 | opcode |= (p->regnum << 25); | |
1304 | s += len; | |
1305 | continue; | |
1306 | } | |
1307 | else | |
1308 | { | |
48401fcf | 1309 | error_message = _(": unrecognizable privileged register"); |
355afbcd KR |
1310 | goto error; |
1311 | } | |
680227f3 | 1312 | |
1277cdda RH |
1313 | case '_': |
1314 | case '/': | |
1315 | /* Parse a v9a ancillary state register. */ | |
1316 | if (*s == '%') | |
1317 | { | |
1318 | struct priv_reg_entry *p = v9a_asr_table; | |
1319 | unsigned int len = 9999999; /* init to make gcc happy */ | |
1320 | ||
1321 | s += 1; | |
1322 | while (p->name[0] > s[0]) | |
1323 | p++; | |
1324 | while (p->name[0] == s[0]) | |
1325 | { | |
1326 | len = strlen (p->name); | |
1327 | if (strncmp (p->name, s, len) == 0) | |
1328 | break; | |
1329 | p++; | |
1330 | } | |
1331 | if (p->name[0] != s[0]) | |
1332 | { | |
48401fcf | 1333 | error_message = _(": unrecognizable v9a ancillary state register"); |
1277cdda RH |
1334 | goto error; |
1335 | } | |
1336 | if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) | |
1337 | { | |
48401fcf | 1338 | error_message = _(": rd on write only ancillary state register"); |
1277cdda RH |
1339 | goto error; |
1340 | } | |
1341 | if (*args == '/') | |
1342 | opcode |= (p->regnum << 14); | |
1343 | else | |
1344 | opcode |= (p->regnum << 25); | |
1345 | s += len; | |
1346 | continue; | |
1347 | } | |
1348 | else | |
1349 | { | |
48401fcf | 1350 | error_message = _(": unrecognizable v9a ancillary state register"); |
1277cdda RH |
1351 | goto error; |
1352 | } | |
1353 | ||
355afbcd KR |
1354 | case 'M': |
1355 | case 'm': | |
1356 | if (strncmp (s, "%asr", 4) == 0) | |
1357 | { | |
1358 | s += 4; | |
680227f3 | 1359 | |
48401fcf | 1360 | if (isdigit ((unsigned char) *s)) |
355afbcd KR |
1361 | { |
1362 | long num = 0; | |
1363 | ||
48401fcf | 1364 | while (isdigit ((unsigned char) *s)) |
355afbcd KR |
1365 | { |
1366 | num = num * 10 + *s - '0'; | |
1367 | ++s; | |
1368 | } | |
1369 | ||
e86d5cf3 | 1370 | if (current_architecture >= SPARC_OPCODE_ARCH_V9) |
355afbcd | 1371 | { |
e86d5cf3 DE |
1372 | if (num < 16 || 31 < num) |
1373 | { | |
48401fcf | 1374 | error_message = _(": asr number must be between 16 and 31"); |
e86d5cf3 DE |
1375 | goto error; |
1376 | } | |
1377 | } | |
1378 | else | |
1379 | { | |
2cb1807e | 1380 | if (num < 0 || 31 < num) |
e86d5cf3 | 1381 | { |
48401fcf | 1382 | error_message = _(": asr number must be between 0 and 31"); |
e86d5cf3 DE |
1383 | goto error; |
1384 | } | |
1385 | } | |
355afbcd KR |
1386 | |
1387 | opcode |= (*args == 'M' ? RS1 (num) : RD (num)); | |
1388 | continue; | |
1389 | } | |
1390 | else | |
1391 | { | |
48401fcf | 1392 | error_message = _(": expecting %asrN"); |
355afbcd | 1393 | goto error; |
e86d5cf3 DE |
1394 | } |
1395 | } /* if %asr */ | |
355afbcd KR |
1396 | break; |
1397 | ||
355afbcd | 1398 | case 'I': |
125f0b0d | 1399 | the_insn.reloc = BFD_RELOC_SPARC_11; |
355afbcd KR |
1400 | goto immediate; |
1401 | ||
1402 | case 'j': | |
125f0b0d | 1403 | the_insn.reloc = BFD_RELOC_SPARC_10; |
355afbcd KR |
1404 | goto immediate; |
1405 | ||
8dd07a84 ILT |
1406 | case 'X': |
1407 | /* V8 systems don't understand BFD_RELOC_SPARC_5. */ | |
1408 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1409 | the_insn.reloc = BFD_RELOC_SPARC_5; | |
1410 | else | |
1411 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1412 | /* These fields are unsigned, but for upward compatibility, | |
1413 | allow negative values as well. */ | |
8dd07a84 ILT |
1414 | goto immediate; |
1415 | ||
1416 | case 'Y': | |
1417 | /* V8 systems don't understand BFD_RELOC_SPARC_6. */ | |
1418 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1419 | the_insn.reloc = BFD_RELOC_SPARC_6; | |
1420 | else | |
1421 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1422 | /* These fields are unsigned, but for upward compatibility, | |
1423 | allow negative values as well. */ | |
8dd07a84 ILT |
1424 | goto immediate; |
1425 | ||
355afbcd | 1426 | case 'k': |
125f0b0d | 1427 | the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; |
355afbcd KR |
1428 | the_insn.pcrel = 1; |
1429 | goto immediate; | |
1430 | ||
1431 | case 'G': | |
125f0b0d | 1432 | the_insn.reloc = BFD_RELOC_SPARC_WDISP19; |
355afbcd KR |
1433 | the_insn.pcrel = 1; |
1434 | goto immediate; | |
1435 | ||
1436 | case 'N': | |
1437 | if (*s == 'p' && s[1] == 'n') | |
1438 | { | |
1439 | s += 2; | |
1440 | continue; | |
1441 | } | |
1442 | break; | |
1443 | ||
1444 | case 'T': | |
1445 | if (*s == 'p' && s[1] == 't') | |
1446 | { | |
1447 | s += 2; | |
1448 | continue; | |
1449 | } | |
1450 | break; | |
1451 | ||
1452 | case 'z': | |
1453 | if (*s == ' ') | |
1454 | { | |
1455 | ++s; | |
1456 | } | |
0d44b3d1 | 1457 | if (strncmp (s, "%icc", 4) == 0) |
355afbcd | 1458 | { |
0d44b3d1 | 1459 | s += 4; |
355afbcd KR |
1460 | continue; |
1461 | } | |
1462 | break; | |
1463 | ||
1464 | case 'Z': | |
1465 | if (*s == ' ') | |
1466 | { | |
1467 | ++s; | |
1468 | } | |
0d44b3d1 | 1469 | if (strncmp (s, "%xcc", 4) == 0) |
355afbcd | 1470 | { |
0d44b3d1 | 1471 | s += 4; |
355afbcd KR |
1472 | continue; |
1473 | } | |
1474 | break; | |
1475 | ||
1476 | case '6': | |
1477 | if (*s == ' ') | |
1478 | { | |
1479 | ++s; | |
1480 | } | |
0d44b3d1 | 1481 | if (strncmp (s, "%fcc0", 5) == 0) |
355afbcd | 1482 | { |
0d44b3d1 | 1483 | s += 5; |
355afbcd KR |
1484 | continue; |
1485 | } | |
1486 | break; | |
1487 | ||
1488 | case '7': | |
1489 | if (*s == ' ') | |
1490 | { | |
1491 | ++s; | |
1492 | } | |
0d44b3d1 | 1493 | if (strncmp (s, "%fcc1", 5) == 0) |
355afbcd | 1494 | { |
0d44b3d1 | 1495 | s += 5; |
355afbcd KR |
1496 | continue; |
1497 | } | |
1498 | break; | |
1499 | ||
1500 | case '8': | |
1501 | if (*s == ' ') | |
1502 | { | |
1503 | ++s; | |
1504 | } | |
0d44b3d1 | 1505 | if (strncmp (s, "%fcc2", 5) == 0) |
355afbcd | 1506 | { |
0d44b3d1 | 1507 | s += 5; |
355afbcd KR |
1508 | continue; |
1509 | } | |
1510 | break; | |
1511 | ||
1512 | case '9': | |
1513 | if (*s == ' ') | |
1514 | { | |
1515 | ++s; | |
1516 | } | |
0d44b3d1 | 1517 | if (strncmp (s, "%fcc3", 5) == 0) |
355afbcd | 1518 | { |
0d44b3d1 | 1519 | s += 5; |
355afbcd KR |
1520 | continue; |
1521 | } | |
1522 | break; | |
1523 | ||
1524 | case 'P': | |
1525 | if (strncmp (s, "%pc", 3) == 0) | |
1526 | { | |
1527 | s += 3; | |
1528 | continue; | |
1529 | } | |
1530 | break; | |
1531 | ||
1532 | case 'W': | |
1533 | if (strncmp (s, "%tick", 5) == 0) | |
1534 | { | |
1535 | s += 5; | |
1536 | continue; | |
1537 | } | |
1538 | break; | |
355afbcd KR |
1539 | |
1540 | case '\0': /* end of args */ | |
1541 | if (*s == '\0') | |
1542 | { | |
1543 | match = 1; | |
1544 | } | |
1545 | break; | |
1546 | ||
1547 | case '+': | |
1548 | if (*s == '+') | |
1549 | { | |
1550 | ++s; | |
1551 | continue; | |
1552 | } | |
1553 | if (*s == '-') | |
1554 | { | |
1555 | continue; | |
1556 | } | |
1557 | break; | |
1558 | ||
1559 | case '[': /* these must match exactly */ | |
1560 | case ']': | |
1561 | case ',': | |
1562 | case ' ': | |
1563 | if (*s++ == *args) | |
1564 | continue; | |
1565 | break; | |
1566 | ||
1567 | case '#': /* must be at least one digit */ | |
48401fcf | 1568 | if (isdigit ((unsigned char) *s++)) |
355afbcd | 1569 | { |
48401fcf | 1570 | while (isdigit ((unsigned char) *s)) |
355afbcd KR |
1571 | { |
1572 | ++s; | |
1573 | } | |
1574 | continue; | |
1575 | } | |
1576 | break; | |
1577 | ||
1578 | case 'C': /* coprocessor state register */ | |
1579 | if (strncmp (s, "%csr", 4) == 0) | |
1580 | { | |
1581 | s += 4; | |
1582 | continue; | |
1583 | } | |
1584 | break; | |
1585 | ||
1586 | case 'b': /* next operand is a coprocessor register */ | |
1587 | case 'c': | |
1588 | case 'D': | |
48401fcf | 1589 | if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s)) |
355afbcd KR |
1590 | { |
1591 | mask = *s++; | |
48401fcf | 1592 | if (isdigit ((unsigned char) *s)) |
355afbcd KR |
1593 | { |
1594 | mask = 10 * (mask - '0') + (*s++ - '0'); | |
1595 | if (mask >= 32) | |
1596 | { | |
1597 | break; | |
1598 | } | |
1599 | } | |
1600 | else | |
1601 | { | |
1602 | mask -= '0'; | |
1603 | } | |
1604 | switch (*args) | |
1605 | { | |
1606 | ||
1607 | case 'b': | |
1608 | opcode |= mask << 14; | |
1609 | continue; | |
1610 | ||
1611 | case 'c': | |
1612 | opcode |= mask; | |
1613 | continue; | |
1614 | ||
1615 | case 'D': | |
1616 | opcode |= mask << 25; | |
1617 | continue; | |
1618 | } | |
1619 | } | |
1620 | break; | |
1621 | ||
1622 | case 'r': /* next operand must be a register */ | |
ed94c2b8 | 1623 | case 'O': |
355afbcd KR |
1624 | case '1': |
1625 | case '2': | |
1626 | case 'd': | |
1627 | if (*s++ == '%') | |
1628 | { | |
1629 | switch (c = *s++) | |
1630 | { | |
1631 | ||
1632 | case 'f': /* frame pointer */ | |
1633 | if (*s++ == 'p') | |
1634 | { | |
1635 | mask = 0x1e; | |
1636 | break; | |
1637 | } | |
1638 | goto error; | |
1639 | ||
1640 | case 'g': /* global register */ | |
1641 | if (isoctal (c = *s++)) | |
1642 | { | |
1643 | mask = c - '0'; | |
1644 | break; | |
1645 | } | |
1646 | goto error; | |
1647 | ||
1648 | case 'i': /* in register */ | |
1649 | if (isoctal (c = *s++)) | |
1650 | { | |
1651 | mask = c - '0' + 24; | |
1652 | break; | |
1653 | } | |
1654 | goto error; | |
1655 | ||
1656 | case 'l': /* local register */ | |
1657 | if (isoctal (c = *s++)) | |
1658 | { | |
1659 | mask = (c - '0' + 16); | |
1660 | break; | |
1661 | } | |
1662 | goto error; | |
1663 | ||
1664 | case 'o': /* out register */ | |
1665 | if (isoctal (c = *s++)) | |
1666 | { | |
1667 | mask = (c - '0' + 8); | |
1668 | break; | |
1669 | } | |
1670 | goto error; | |
1671 | ||
1672 | case 's': /* stack pointer */ | |
1673 | if (*s++ == 'p') | |
1674 | { | |
1675 | mask = 0xe; | |
1676 | break; | |
1677 | } | |
1678 | goto error; | |
1679 | ||
1680 | case 'r': /* any register */ | |
48401fcf | 1681 | if (!isdigit ((unsigned char) (c = *s++))) |
355afbcd KR |
1682 | { |
1683 | goto error; | |
1684 | } | |
1685 | /* FALLTHROUGH */ | |
1686 | case '0': | |
1687 | case '1': | |
1688 | case '2': | |
1689 | case '3': | |
1690 | case '4': | |
1691 | case '5': | |
1692 | case '6': | |
1693 | case '7': | |
1694 | case '8': | |
1695 | case '9': | |
48401fcf | 1696 | if (isdigit ((unsigned char) *s)) |
355afbcd KR |
1697 | { |
1698 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) | |
680227f3 | 1699 | { |
680227f3 KR |
1700 | goto error; |
1701 | } | |
355afbcd KR |
1702 | } |
1703 | else | |
1704 | { | |
1705 | c -= '0'; | |
1706 | } | |
1707 | mask = c; | |
1708 | break; | |
1709 | ||
1710 | default: | |
1711 | goto error; | |
1712 | } | |
6df07e7f DE |
1713 | |
1714 | /* Got the register, now figure out where | |
1715 | it goes in the opcode. */ | |
355afbcd KR |
1716 | switch (*args) |
1717 | { | |
355afbcd KR |
1718 | case '1': |
1719 | opcode |= mask << 14; | |
1720 | continue; | |
1721 | ||
1722 | case '2': | |
1723 | opcode |= mask; | |
1724 | continue; | |
1725 | ||
1726 | case 'd': | |
1727 | opcode |= mask << 25; | |
1728 | continue; | |
1729 | ||
1730 | case 'r': | |
1731 | opcode |= (mask << 25) | (mask << 14); | |
1732 | continue; | |
ed94c2b8 ILT |
1733 | |
1734 | case 'O': | |
1735 | opcode |= (mask << 25) | (mask << 0); | |
1736 | continue; | |
355afbcd KR |
1737 | } |
1738 | } | |
1739 | break; | |
1740 | ||
1741 | case 'e': /* next operand is a floating point register */ | |
1742 | case 'v': | |
1743 | case 'V': | |
1744 | ||
1745 | case 'f': | |
1746 | case 'B': | |
1747 | case 'R': | |
1748 | ||
1749 | case 'g': | |
1750 | case 'H': | |
1751 | case 'J': | |
1752 | { | |
1753 | char format; | |
1754 | ||
1755 | if (*s++ == '%' | |
355afbcd | 1756 | && ((format = *s) == 'f') |
48401fcf | 1757 | && isdigit ((unsigned char) *++s)) |
355afbcd | 1758 | { |
48401fcf | 1759 | for (mask = 0; isdigit ((unsigned char) *s); ++s) |
355afbcd KR |
1760 | { |
1761 | mask = 10 * mask + (*s - '0'); | |
1762 | } /* read the number */ | |
1763 | ||
1764 | if ((*args == 'v' | |
1765 | || *args == 'B' | |
1766 | || *args == 'H') | |
1767 | && (mask & 1)) | |
1768 | { | |
1769 | break; | |
1770 | } /* register must be even numbered */ | |
1771 | ||
1772 | if ((*args == 'V' | |
1773 | || *args == 'R' | |
1774 | || *args == 'J') | |
1775 | && (mask & 3)) | |
1776 | { | |
1777 | break; | |
1778 | } /* register must be multiple of 4 */ | |
1779 | ||
125f0b0d | 1780 | if (mask >= 64) |
355afbcd | 1781 | { |
8dd07a84 | 1782 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) |
48401fcf | 1783 | error_message = _(": There are only 64 f registers; [0-63]"); |
6df07e7f | 1784 | else |
48401fcf | 1785 | error_message = _(": There are only 32 f registers; [0-31]"); |
125f0b0d KR |
1786 | goto error; |
1787 | } /* on error */ | |
6df07e7f | 1788 | else if (mask >= 32) |
125f0b0d | 1789 | { |
8dd07a84 | 1790 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) |
6df07e7f DE |
1791 | { |
1792 | v9_arg_p = 1; | |
1793 | mask -= 31; /* wrap high bit */ | |
1794 | } | |
1795 | else | |
1796 | { | |
48401fcf | 1797 | error_message = _(": There are only 32 f registers; [0-31]"); |
6df07e7f DE |
1798 | goto error; |
1799 | } | |
1800 | } | |
125f0b0d KR |
1801 | } |
1802 | else | |
1803 | { | |
1804 | break; | |
1805 | } /* if not an 'f' register. */ | |
355afbcd KR |
1806 | |
1807 | switch (*args) | |
1808 | { | |
355afbcd KR |
1809 | case 'v': |
1810 | case 'V': | |
1811 | case 'e': | |
1812 | opcode |= RS1 (mask); | |
1813 | continue; | |
1814 | ||
1815 | ||
1816 | case 'f': | |
1817 | case 'B': | |
1818 | case 'R': | |
1819 | opcode |= RS2 (mask); | |
1820 | continue; | |
1821 | ||
1822 | case 'g': | |
1823 | case 'H': | |
1824 | case 'J': | |
1825 | opcode |= RD (mask); | |
1826 | continue; | |
1827 | } /* pack it in. */ | |
1828 | ||
1829 | know (0); | |
1830 | break; | |
1831 | } /* float arg */ | |
1832 | ||
1833 | case 'F': | |
1834 | if (strncmp (s, "%fsr", 4) == 0) | |
1835 | { | |
1836 | s += 4; | |
1837 | continue; | |
1838 | } | |
1839 | break; | |
1840 | ||
2b063e6d ILT |
1841 | case '0': /* 64 bit immediate (setx insn) */ |
1842 | the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ | |
1843 | goto immediate; | |
1844 | ||
355afbcd | 1845 | case 'h': /* high 22 bits */ |
428d312b | 1846 | the_insn.reloc = BFD_RELOC_HI22; |
355afbcd KR |
1847 | goto immediate; |
1848 | ||
1849 | case 'l': /* 22 bit PC relative immediate */ | |
428d312b | 1850 | the_insn.reloc = BFD_RELOC_SPARC_WDISP22; |
355afbcd KR |
1851 | the_insn.pcrel = 1; |
1852 | goto immediate; | |
1853 | ||
1854 | case 'L': /* 30 bit immediate */ | |
428d312b | 1855 | the_insn.reloc = BFD_RELOC_32_PCREL_S2; |
355afbcd KR |
1856 | the_insn.pcrel = 1; |
1857 | goto immediate; | |
1858 | ||
1859 | case 'n': /* 22 bit immediate */ | |
428d312b | 1860 | the_insn.reloc = BFD_RELOC_SPARC22; |
355afbcd KR |
1861 | goto immediate; |
1862 | ||
1863 | case 'i': /* 13 bit immediate */ | |
7ab2e983 | 1864 | the_insn.reloc = BFD_RELOC_SPARC13; |
355afbcd | 1865 | |
54b9ebdd | 1866 | /* fallthrough */ |
355afbcd KR |
1867 | |
1868 | immediate: | |
1869 | if (*s == ' ') | |
1870 | s++; | |
54b9ebdd DE |
1871 | |
1872 | /* Check for %hi, etc. */ | |
355afbcd KR |
1873 | if (*s == '%') |
1874 | { | |
54b9ebdd DE |
1875 | static struct ops { |
1876 | /* The name as it appears in assembler. */ | |
1877 | char *name; | |
1878 | /* strlen (name), precomputed for speed */ | |
1879 | int len; | |
1880 | /* The reloc this pseudo-op translates to. */ | |
1881 | int reloc; | |
1882 | /* Non-zero if for v9 only. */ | |
1883 | int v9_p; | |
1884 | /* Non-zero if can be used in pc-relative contexts. */ | |
1885 | int pcrel_p;/*FIXME:wip*/ | |
1886 | } ops[] = { | |
1887 | /* hix/lox must appear before hi/lo so %hix won't be | |
1888 | mistaken for %hi. */ | |
1889 | { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, | |
1890 | { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, | |
1891 | { "hi", 2, BFD_RELOC_HI22, 0, 1 }, | |
1892 | { "lo", 2, BFD_RELOC_LO10, 0, 1 }, | |
1893 | { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, | |
1894 | { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, | |
1895 | { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, | |
1896 | { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, | |
1897 | { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, | |
1898 | { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, | |
1899 | { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, | |
1900 | { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, | |
1901 | { NULL } | |
1902 | }; | |
1903 | struct ops *o; | |
1904 | ||
1905 | for (o = ops; o->name; o++) | |
1906 | if (strncmp (s + 1, o->name, o->len) == 0) | |
1907 | break; | |
1908 | if (o->name == NULL) | |
355afbcd | 1909 | break; |
54b9ebdd DE |
1910 | |
1911 | the_insn.reloc = o->reloc; | |
1912 | s += o->len + 1; | |
1913 | v9_arg_p = o->v9_p; | |
355afbcd | 1914 | } |
54b9ebdd | 1915 | |
af6f39b4 | 1916 | /* Note that if the get_expression() fails, we will still |
9b6a882e KR |
1917 | have created U entries in the symbol table for the |
1918 | 'symbols' in the input string. Try not to create U | |
1919 | symbols for registers, etc. */ | |
355afbcd | 1920 | { |
9b6a882e KR |
1921 | /* This stuff checks to see if the expression ends in |
1922 | +%reg. If it does, it removes the register from | |
1923 | the expression, and re-sets 's' to point to the | |
1924 | right place. */ | |
355afbcd KR |
1925 | |
1926 | char *s1; | |
1927 | ||
2b063e6d | 1928 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ; |
355afbcd | 1929 | |
48401fcf | 1930 | if (s1 != s && isdigit ((unsigned char) s1[-1])) |
355afbcd KR |
1931 | { |
1932 | if (s1[-2] == '%' && s1[-3] == '+') | |
1933 | { | |
1934 | s1 -= 3; | |
1935 | *s1 = '\0'; | |
af6f39b4 | 1936 | (void) get_expression (s); |
355afbcd KR |
1937 | *s1 = '+'; |
1938 | s = s1; | |
1939 | continue; | |
1940 | } | |
1941 | else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') | |
1942 | { | |
1943 | s1 -= 4; | |
1944 | *s1 = '\0'; | |
af6f39b4 | 1945 | (void) get_expression (s); |
355afbcd KR |
1946 | *s1 = '+'; |
1947 | s = s1; | |
1948 | continue; | |
1949 | } | |
1950 | } | |
1951 | } | |
af6f39b4 | 1952 | (void) get_expression (s); |
355afbcd KR |
1953 | s = expr_end; |
1954 | ||
54b9ebdd | 1955 | /* Check for constants that don't require emitting a reloc. */ |
9b6a882e KR |
1956 | if (the_insn.exp.X_op == O_constant |
1957 | && the_insn.exp.X_add_symbol == 0 | |
1958 | && the_insn.exp.X_op_symbol == 0) | |
1959 | { | |
7ab2e983 ILT |
1960 | /* For pc-relative call instructions, we reject |
1961 | constants to get better code. */ | |
1962 | if (the_insn.pcrel | |
1963 | && the_insn.reloc == BFD_RELOC_32_PCREL_S2 | |
54b9ebdd | 1964 | && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) |
7ab2e983 | 1965 | { |
48401fcf | 1966 | error_message = _(": PC-relative operand can't be a constant"); |
7ab2e983 ILT |
1967 | goto error; |
1968 | } | |
9b6a882e | 1969 | |
54b9ebdd DE |
1970 | /* Constants that won't fit are checked in md_apply_fix3 |
1971 | and bfd_install_relocation. | |
1972 | ??? It would be preferable to install the constants | |
1973 | into the insn here and save having to create a fixS | |
1974 | for each one. There already exists code to handle | |
1975 | all the various cases (e.g. in md_apply_fix3 and | |
1976 | bfd_install_relocation) so duplicating all that code | |
1977 | here isn't right. */ | |
1978 | } | |
355afbcd KR |
1979 | |
1980 | continue; | |
1981 | ||
1982 | case 'a': | |
1983 | if (*s++ == 'a') | |
1984 | { | |
1985 | opcode |= ANNUL; | |
1986 | continue; | |
1987 | } | |
1988 | break; | |
1989 | ||
1990 | case 'A': | |
1991 | { | |
ed9638af KR |
1992 | int asi = 0; |
1993 | ||
1994 | /* Parse an asi. */ | |
1995 | if (*s == '#') | |
1996 | { | |
6df07e7f | 1997 | if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) |
ed9638af | 1998 | { |
48401fcf | 1999 | error_message = _(": invalid ASI name"); |
ed9638af KR |
2000 | goto error; |
2001 | } | |
2002 | } | |
a7aa7a2b | 2003 | else |
ed9638af | 2004 | { |
6df07e7f | 2005 | if (! parse_const_expr_arg (&s, &asi)) |
a7aa7a2b | 2006 | { |
48401fcf | 2007 | error_message = _(": invalid ASI expression"); |
a7aa7a2b ILT |
2008 | goto error; |
2009 | } | |
ed9638af KR |
2010 | if (asi < 0 || asi > 255) |
2011 | { | |
48401fcf | 2012 | error_message = _(": invalid ASI number"); |
ed9638af KR |
2013 | goto error; |
2014 | } | |
2015 | } | |
ed9638af KR |
2016 | opcode |= ASI (asi); |
2017 | continue; | |
355afbcd KR |
2018 | } /* alternate space */ |
2019 | ||
2020 | case 'p': | |
2021 | if (strncmp (s, "%psr", 4) == 0) | |
2022 | { | |
2023 | s += 4; | |
2024 | continue; | |
2025 | } | |
2026 | break; | |
2027 | ||
2028 | case 'q': /* floating point queue */ | |
2029 | if (strncmp (s, "%fq", 3) == 0) | |
2030 | { | |
2031 | s += 3; | |
2032 | continue; | |
2033 | } | |
2034 | break; | |
2035 | ||
2036 | case 'Q': /* coprocessor queue */ | |
2037 | if (strncmp (s, "%cq", 3) == 0) | |
2038 | { | |
2039 | s += 3; | |
2040 | continue; | |
2041 | } | |
2042 | break; | |
2043 | ||
2044 | case 'S': | |
2b063e6d ILT |
2045 | if (strcmp (str, "set") == 0 |
2046 | || strcmp (str, "setuw") == 0) | |
355afbcd KR |
2047 | { |
2048 | special_case = SPECIAL_CASE_SET; | |
2049 | continue; | |
2050 | } | |
2b063e6d ILT |
2051 | else if (strcmp (str, "setsw") == 0) |
2052 | { | |
2053 | special_case = SPECIAL_CASE_SETSW; | |
2054 | continue; | |
2055 | } | |
2056 | else if (strcmp (str, "setx") == 0) | |
2057 | { | |
2058 | special_case = SPECIAL_CASE_SETX; | |
2059 | continue; | |
2060 | } | |
355afbcd KR |
2061 | else if (strncmp (str, "fdiv", 4) == 0) |
2062 | { | |
2063 | special_case = SPECIAL_CASE_FDIV; | |
2064 | continue; | |
2065 | } | |
2066 | break; | |
2067 | ||
355afbcd KR |
2068 | case 'o': |
2069 | if (strncmp (s, "%asi", 4) != 0) | |
2070 | break; | |
2071 | s += 4; | |
2072 | continue; | |
2073 | ||
2074 | case 's': | |
2075 | if (strncmp (s, "%fprs", 5) != 0) | |
2076 | break; | |
2077 | s += 5; | |
2078 | continue; | |
2079 | ||
2080 | case 'E': | |
2081 | if (strncmp (s, "%ccr", 4) != 0) | |
2082 | break; | |
2083 | s += 4; | |
2084 | continue; | |
680227f3 | 2085 | |
355afbcd KR |
2086 | case 't': |
2087 | if (strncmp (s, "%tbr", 4) != 0) | |
2088 | break; | |
2089 | s += 4; | |
2090 | continue; | |
2091 | ||
2092 | case 'w': | |
2093 | if (strncmp (s, "%wim", 4) != 0) | |
2094 | break; | |
2095 | s += 4; | |
2096 | continue; | |
2097 | ||
5e0a90a8 KR |
2098 | case 'x': |
2099 | { | |
2100 | char *push = input_line_pointer; | |
2101 | expressionS e; | |
2102 | ||
2103 | input_line_pointer = s; | |
2104 | expression (&e); | |
2105 | if (e.X_op == O_constant) | |
2106 | { | |
2107 | int n = e.X_add_number; | |
2108 | if (n != e.X_add_number || (n & ~0x1ff) != 0) | |
48401fcf | 2109 | as_bad (_("OPF immediate operand out of range (0-0x1ff)")); |
5e0a90a8 KR |
2110 | else |
2111 | opcode |= e.X_add_number << 5; | |
2112 | } | |
2113 | else | |
48401fcf | 2114 | as_bad (_("non-immediate OPF operand, ignored")); |
5e0a90a8 KR |
2115 | s = input_line_pointer; |
2116 | input_line_pointer = push; | |
2117 | continue; | |
2118 | } | |
5e0a90a8 | 2119 | |
355afbcd KR |
2120 | case 'y': |
2121 | if (strncmp (s, "%y", 2) != 0) | |
2122 | break; | |
2123 | s += 2; | |
2124 | continue; | |
2125 | ||
e86d5cf3 DE |
2126 | case 'u': |
2127 | case 'U': | |
2128 | { | |
2129 | /* Parse a sparclet cpreg. */ | |
2130 | int cpreg; | |
2131 | if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) | |
2132 | { | |
48401fcf | 2133 | error_message = _(": invalid cpreg name"); |
e86d5cf3 DE |
2134 | goto error; |
2135 | } | |
2136 | opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); | |
2137 | continue; | |
2138 | } | |
2139 | ||
355afbcd | 2140 | default: |
48401fcf | 2141 | as_fatal (_("failed sanity check.")); |
355afbcd | 2142 | } /* switch on arg code */ |
6df07e7f DE |
2143 | |
2144 | /* Break out of for() loop. */ | |
355afbcd KR |
2145 | break; |
2146 | } /* for each arg that we expect */ | |
6df07e7f | 2147 | |
355afbcd KR |
2148 | error: |
2149 | if (match == 0) | |
2150 | { | |
2151 | /* Args don't match. */ | |
48401fcf | 2152 | if (&insn[1] - sparc_opcodes < sparc_num_opcodes |
a7aa7a2b ILT |
2153 | && (insn->name == insn[1].name |
2154 | || !strcmp (insn->name, insn[1].name))) | |
355afbcd KR |
2155 | { |
2156 | ++insn; | |
2157 | s = argsStart; | |
2158 | continue; | |
2159 | } | |
2160 | else | |
2161 | { | |
48401fcf | 2162 | as_bad (_("Illegal operands%s"), error_message); |
355afbcd KR |
2163 | return; |
2164 | } | |
2165 | } | |
2166 | else | |
2167 | { | |
e70ad5d5 | 2168 | /* We have a match. Now see if the architecture is ok. */ |
d8b42b96 | 2169 | int needed_arch_mask = insn->architecture; |
e70ad5d5 | 2170 | |
d8b42b96 | 2171 | if (v9_arg_p) |
355afbcd | 2172 | { |
d8b42b96 DE |
2173 | needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9) |
2174 | | (1 << SPARC_OPCODE_ARCH_V9A)); | |
2175 | needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9); | |
e70ad5d5 | 2176 | } |
d8b42b96 DE |
2177 | |
2178 | if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture)) | |
2179 | ; /* ok */ | |
2180 | /* Can we bump up the architecture? */ | |
2181 | else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture)) | |
e70ad5d5 | 2182 | { |
d8b42b96 DE |
2183 | enum sparc_opcode_arch_val needed_architecture = |
2184 | sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) | |
2185 | & needed_arch_mask); | |
2186 | ||
2187 | assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); | |
e70ad5d5 DE |
2188 | if (warn_on_bump |
2189 | && needed_architecture > warn_after_architecture) | |
355afbcd | 2190 | { |
48401fcf | 2191 | as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), |
e70ad5d5 DE |
2192 | sparc_opcode_archs[current_architecture].name, |
2193 | sparc_opcode_archs[needed_architecture].name, | |
2194 | str); | |
d8b42b96 | 2195 | warn_after_architecture = needed_architecture; |
355afbcd | 2196 | } |
e70ad5d5 DE |
2197 | current_architecture = needed_architecture; |
2198 | } | |
d8b42b96 | 2199 | /* Conflict. */ |
110b814d DE |
2200 | /* ??? This seems to be a bit fragile. What if the next entry in |
2201 | the opcode table is the one we want and it is supported? | |
2202 | It is possible to arrange the table today so that this can't | |
2203 | happen but what about tomorrow? */ | |
d8b42b96 DE |
2204 | else |
2205 | { | |
110b814d DE |
2206 | int arch,printed_one_p = 0; |
2207 | char *p; | |
2208 | char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; | |
2209 | ||
2210 | /* Create a list of the architectures that support the insn. */ | |
2211 | needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture); | |
2212 | p = required_archs; | |
2213 | arch = sparc_ffs (needed_arch_mask); | |
2214 | while ((1 << arch) <= needed_arch_mask) | |
2215 | { | |
2216 | if ((1 << arch) & needed_arch_mask) | |
2217 | { | |
2218 | if (printed_one_p) | |
2219 | *p++ = '|'; | |
2220 | strcpy (p, sparc_opcode_archs[arch].name); | |
2221 | p += strlen (p); | |
2222 | printed_one_p = 1; | |
2223 | } | |
2224 | ++arch; | |
2225 | } | |
d8b42b96 | 2226 | |
48401fcf TT |
2227 | as_bad (_("Architecture mismatch on \"%s\"."), str); |
2228 | as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), | |
110b814d | 2229 | required_archs, |
d8b42b96 DE |
2230 | sparc_opcode_archs[max_architecture].name); |
2231 | return; | |
2232 | } | |
e70ad5d5 | 2233 | } /* if no match */ |
355afbcd KR |
2234 | |
2235 | break; | |
e70ad5d5 | 2236 | } /* forever looking for a match */ |
355afbcd KR |
2237 | |
2238 | the_insn.opcode = opcode; | |
c999fd9f | 2239 | } |
355afbcd | 2240 | |
af6f39b4 DE |
2241 | /* Parse an argument that can be expressed as a keyword. |
2242 | (eg: #StoreStore or %ccfr). | |
2243 | The result is a boolean indicating success. | |
2244 | If successful, INPUT_POINTER is updated. */ | |
2245 | ||
2246 | static int | |
2247 | parse_keyword_arg (lookup_fn, input_pointerP, valueP) | |
2248 | int (*lookup_fn) PARAMS ((const char *)); | |
2249 | char **input_pointerP; | |
2250 | int *valueP; | |
2251 | { | |
2252 | int value; | |
2253 | char c, *p, *q; | |
2254 | ||
2255 | p = *input_pointerP; | |
48401fcf TT |
2256 | for (q = p + (*p == '#' || *p == '%'); |
2257 | isalnum ((unsigned char) *q) || *q == '_'; | |
2258 | ++q) | |
af6f39b4 DE |
2259 | continue; |
2260 | c = *q; | |
2261 | *q = 0; | |
2262 | value = (*lookup_fn) (p); | |
2263 | *q = c; | |
2264 | if (value == -1) | |
2265 | return 0; | |
2266 | *valueP = value; | |
2267 | *input_pointerP = q; | |
2268 | return 1; | |
2269 | } | |
2270 | ||
2271 | /* Parse an argument that is a constant expression. | |
2272 | The result is a boolean indicating success. */ | |
2273 | ||
2274 | static int | |
2275 | parse_const_expr_arg (input_pointerP, valueP) | |
2276 | char **input_pointerP; | |
2277 | int *valueP; | |
2278 | { | |
2279 | char *save = input_line_pointer; | |
2280 | expressionS exp; | |
2281 | ||
2282 | input_line_pointer = *input_pointerP; | |
2283 | /* The next expression may be something other than a constant | |
2284 | (say if we're not processing the right variant of the insn). | |
2285 | Don't call expression unless we're sure it will succeed as it will | |
2286 | signal an error (which we want to defer until later). */ | |
2287 | /* FIXME: It might be better to define md_operand and have it recognize | |
2288 | things like %asi, etc. but continuing that route through to the end | |
2289 | is a lot of work. */ | |
2290 | if (*input_line_pointer == '%') | |
2291 | { | |
2292 | input_line_pointer = save; | |
2293 | return 0; | |
2294 | } | |
2295 | expression (&exp); | |
2296 | *input_pointerP = input_line_pointer; | |
2297 | input_line_pointer = save; | |
2298 | if (exp.X_op != O_constant) | |
2299 | return 0; | |
2300 | *valueP = exp.X_add_number; | |
2301 | return 1; | |
2302 | } | |
2303 | ||
2304 | /* Subroutine of sparc_ip to parse an expression. */ | |
2305 | ||
355afbcd | 2306 | static int |
af6f39b4 | 2307 | get_expression (str) |
355afbcd | 2308 | char *str; |
fecd2382 | 2309 | { |
355afbcd KR |
2310 | char *save_in; |
2311 | segT seg; | |
2312 | ||
2313 | save_in = input_line_pointer; | |
2314 | input_line_pointer = str; | |
428d312b | 2315 | seg = expression (&the_insn.exp); |
58d4951d ILT |
2316 | if (seg != absolute_section |
2317 | && seg != text_section | |
2318 | && seg != data_section | |
2319 | && seg != bss_section | |
2320 | && seg != undefined_section) | |
355afbcd | 2321 | { |
48401fcf | 2322 | the_insn.error = _("bad segment"); |
355afbcd KR |
2323 | expr_end = input_line_pointer; |
2324 | input_line_pointer = save_in; | |
2325 | return 1; | |
2326 | } | |
2327 | expr_end = input_line_pointer; | |
2328 | input_line_pointer = save_in; | |
2329 | return 0; | |
af6f39b4 DE |
2330 | } |
2331 | ||
2332 | /* Subroutine of md_assemble to output one insn. */ | |
2333 | ||
2334 | static void | |
2335 | output_insn (insn, the_insn) | |
2336 | const struct sparc_opcode *insn; | |
2337 | struct sparc_it *the_insn; | |
2338 | { | |
2339 | char *toP = frag_more (4); | |
2340 | ||
2341 | /* put out the opcode */ | |
2342 | if (INSN_BIG_ENDIAN) | |
2343 | number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4); | |
2344 | else | |
2345 | number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4); | |
fecd2382 | 2346 | |
af6f39b4 DE |
2347 | /* put out the symbol-dependent stuff */ |
2348 | if (the_insn->reloc != BFD_RELOC_NONE) | |
2349 | { | |
54b9ebdd DE |
2350 | fixS *fixP = fix_new_exp (frag_now, /* which frag */ |
2351 | (toP - frag_now->fr_literal), /* where */ | |
2352 | 4, /* size */ | |
2353 | &the_insn->exp, | |
2354 | the_insn->pcrel, | |
2355 | the_insn->reloc); | |
2356 | /* Turn off overflow checking in fixup_segment. We'll do our | |
2357 | own overflow checking in md_apply_fix3. This is necessary because | |
2358 | the insn size is 4 and fixup_segment will signal an overflow for | |
2359 | large 8 byte quantities. */ | |
2360 | fixP->fx_no_overflow = 1; | |
af6f39b4 | 2361 | } |
fecd2382 | 2362 | |
af6f39b4 DE |
2363 | last_insn = insn; |
2364 | last_opcode = the_insn->opcode; | |
2365 | } | |
2366 | \f | |
fecd2382 RP |
2367 | /* |
2368 | This is identical to the md_atof in m68k.c. I think this is right, | |
2369 | but I'm not sure. | |
355afbcd | 2370 | |
fecd2382 RP |
2371 | Turn a string in input_line_pointer into a floating point constant of type |
2372 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
2373 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
2374 | */ | |
2375 | ||
2376 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
2377 | #define MAX_LITTLENUMS 6 | |
2378 | ||
355afbcd KR |
2379 | char * |
2380 | md_atof (type, litP, sizeP) | |
2381 | char type; | |
2382 | char *litP; | |
2383 | int *sizeP; | |
fecd2382 | 2384 | { |
2b063e6d | 2385 | int i,prec; |
355afbcd | 2386 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
355afbcd | 2387 | char *t; |
355afbcd KR |
2388 | |
2389 | switch (type) | |
2390 | { | |
355afbcd KR |
2391 | case 'f': |
2392 | case 'F': | |
2393 | case 's': | |
2394 | case 'S': | |
2395 | prec = 2; | |
2396 | break; | |
2397 | ||
2398 | case 'd': | |
2399 | case 'D': | |
2400 | case 'r': | |
2401 | case 'R': | |
2402 | prec = 4; | |
2403 | break; | |
2404 | ||
2405 | case 'x': | |
2406 | case 'X': | |
2407 | prec = 6; | |
2408 | break; | |
2409 | ||
2410 | case 'p': | |
2411 | case 'P': | |
2412 | prec = 6; | |
2413 | break; | |
2414 | ||
2415 | default: | |
2416 | *sizeP = 0; | |
48401fcf | 2417 | return _("Bad call to MD_ATOF()"); |
355afbcd | 2418 | } |
2b063e6d | 2419 | |
355afbcd KR |
2420 | t = atof_ieee (input_line_pointer, type, words); |
2421 | if (t) | |
2422 | input_line_pointer = t; | |
2423 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
2b063e6d ILT |
2424 | |
2425 | if (target_big_endian) | |
355afbcd | 2426 | { |
2b063e6d ILT |
2427 | for (i = 0; i < prec; i++) |
2428 | { | |
2429 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
2430 | litP += sizeof (LITTLENUM_TYPE); | |
2431 | } | |
2432 | } | |
2433 | else | |
2434 | { | |
2435 | for (i = prec - 1; i >= 0; i--) | |
2436 | { | |
2437 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
2438 | litP += sizeof (LITTLENUM_TYPE); | |
2439 | } | |
355afbcd | 2440 | } |
2b063e6d | 2441 | |
ed9638af KR |
2442 | return 0; |
2443 | } | |
fecd2382 | 2444 | |
2b063e6d ILT |
2445 | /* Write a value out to the object file, using the appropriate |
2446 | endianness. */ | |
2447 | ||
355afbcd KR |
2448 | void |
2449 | md_number_to_chars (buf, val, n) | |
2450 | char *buf; | |
125f0b0d | 2451 | valueT val; |
355afbcd | 2452 | int n; |
fecd2382 | 2453 | { |
2b063e6d ILT |
2454 | if (target_big_endian) |
2455 | number_to_chars_bigendian (buf, val, n); | |
2456 | else | |
2457 | number_to_chars_littleendian (buf, val, n); | |
c999fd9f | 2458 | } |
af6f39b4 | 2459 | \f |
fecd2382 RP |
2460 | /* Apply a fixS to the frags, now that we know the value it ought to |
2461 | hold. */ | |
2462 | ||
428d312b | 2463 | int |
2b063e6d | 2464 | md_apply_fix3 (fixP, value, segment) |
355afbcd | 2465 | fixS *fixP; |
125f0b0d | 2466 | valueT *value; |
2b063e6d | 2467 | segT segment; |
fecd2382 | 2468 | { |
355afbcd | 2469 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; |
125f0b0d | 2470 | offsetT val; |
2b063e6d | 2471 | long insn; |
428d312b | 2472 | |
428d312b | 2473 | val = *value; |
355afbcd | 2474 | |
428d312b | 2475 | assert (fixP->fx_r_type < BFD_RELOC_UNUSED); |
355afbcd KR |
2476 | |
2477 | fixP->fx_addnumber = val; /* Remember value for emit_reloc */ | |
2478 | ||
7766838e ILT |
2479 | #ifdef OBJ_ELF |
2480 | /* FIXME: SPARC ELF relocations don't use an addend in the data | |
2481 | field itself. This whole approach should be somehow combined | |
9e6f4c6b | 2482 | with the calls to bfd_install_relocation. Also, the value passed |
a7aa7a2b ILT |
2483 | in by fixup_segment includes the value of a defined symbol. We |
2484 | don't want to include the value of an externally visible symbol. */ | |
7766838e | 2485 | if (fixP->fx_addsy != NULL) |
a7aa7a2b | 2486 | { |
2b063e6d ILT |
2487 | if (fixP->fx_addsy->sy_used_in_reloc |
2488 | && (S_IS_EXTERNAL (fixP->fx_addsy) | |
2489 | || S_IS_WEAK (fixP->fx_addsy) | |
2490 | || (sparc_pic_code && ! fixP->fx_pcrel) | |
2491 | || (S_GET_SEGMENT (fixP->fx_addsy) != segment | |
2492 | && ((bfd_get_section_flags (stdoutput, | |
2493 | S_GET_SEGMENT (fixP->fx_addsy)) | |
2494 | & SEC_LINK_ONCE) != 0 | |
2495 | || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
2496 | ".gnu.linkonce", | |
2497 | sizeof ".gnu.linkonce" - 1) == 0))) | |
a7aa7a2b ILT |
2498 | && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section |
2499 | && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section | |
2500 | && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy))) | |
2501 | fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy); | |
2502 | return 1; | |
2503 | } | |
7766838e ILT |
2504 | #endif |
2505 | ||
c999fd9f KR |
2506 | /* This is a hack. There should be a better way to |
2507 | handle this. Probably in terms of howto fields, once | |
2508 | we can look at these fixups in terms of howtos. */ | |
428d312b | 2509 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) |
c999fd9f | 2510 | val += fixP->fx_where + fixP->fx_frag->fr_address; |
355afbcd | 2511 | |
ade614d5 KR |
2512 | #ifdef OBJ_AOUT |
2513 | /* FIXME: More ridiculous gas reloc hacking. If we are going to | |
2514 | generate a reloc, then we just want to let the reloc addend set | |
2515 | the value. We do not want to also stuff the addend into the | |
2516 | object file. Including the addend in the object file works when | |
2517 | doing a static link, because the linker will ignore the object | |
2518 | file contents. However, the dynamic linker does not ignore the | |
2519 | object file contents. */ | |
2520 | if (fixP->fx_addsy != NULL | |
2521 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) | |
2522 | val = 0; | |
4c67b523 ILT |
2523 | |
2524 | /* When generating PIC code, we do not want an addend for a reloc | |
2525 | against a local symbol. We adjust fx_addnumber to cancel out the | |
2526 | value already included in val, and to also cancel out the | |
2527 | adjustment which bfd_install_relocation will create. */ | |
2528 | if (sparc_pic_code | |
2529 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 | |
2530 | && fixP->fx_addsy != NULL | |
2531 | && ! S_IS_COMMON (fixP->fx_addsy) | |
2532 | && (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
2533 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
a5002978 CM |
2534 | |
2535 | /* When generating PIC code, we need to fiddle to get | |
2536 | bfd_install_relocation to do the right thing for a PC relative | |
2537 | reloc against a local symbol which we are going to keep. */ | |
2538 | if (sparc_pic_code | |
2539 | && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
2540 | && fixP->fx_addsy != NULL | |
2541 | && (S_IS_EXTERNAL (fixP->fx_addsy) | |
2542 | || S_IS_WEAK (fixP->fx_addsy)) | |
2543 | && S_IS_DEFINED (fixP->fx_addsy) | |
2544 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
2545 | { | |
2546 | val = 0; | |
2547 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
2548 | } | |
ade614d5 KR |
2549 | #endif |
2550 | ||
2b063e6d | 2551 | /* If this is a data relocation, just output VAL. */ |
58d4951d | 2552 | |
2b063e6d ILT |
2553 | if (fixP->fx_r_type == BFD_RELOC_16) |
2554 | { | |
2555 | md_number_to_chars (buf, val, 2); | |
2556 | } | |
fc23c14e SC |
2557 | else if (fixP->fx_r_type == BFD_RELOC_32 |
2558 | || fixP->fx_r_type == BFD_RELOC_SPARC_32LE) | |
2b063e6d ILT |
2559 | { |
2560 | md_number_to_chars (buf, val, 4); | |
2561 | } | |
2562 | else if (fixP->fx_r_type == BFD_RELOC_64) | |
2563 | { | |
2564 | md_number_to_chars (buf, val, 8); | |
2565 | } | |
2566 | else | |
2567 | { | |
2568 | /* It's a relocation against an instruction. */ | |
355afbcd | 2569 | |
2b063e6d ILT |
2570 | if (INSN_BIG_ENDIAN) |
2571 | insn = bfd_getb32 ((unsigned char *) buf); | |
2572 | else | |
2573 | insn = bfd_getl32 ((unsigned char *) buf); | |
2574 | ||
2575 | switch (fixP->fx_r_type) | |
2576 | { | |
2577 | case BFD_RELOC_32_PCREL_S2: | |
2578 | val = val >> 2; | |
2579 | /* FIXME: This increment-by-one deserves a comment of why it's | |
2580 | being done! */ | |
2581 | if (! sparc_pic_code | |
2582 | || fixP->fx_addsy == NULL | |
2583 | || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0) | |
2584 | ++val; | |
2585 | insn |= val & 0x3fffffff; | |
2586 | break; | |
693b21e7 | 2587 | |
2b063e6d ILT |
2588 | case BFD_RELOC_SPARC_11: |
2589 | if (! in_signed_range (val, 0x7ff)) | |
48401fcf TT |
2590 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2591 | _("relocation overflow")); | |
2b063e6d ILT |
2592 | insn |= val & 0x7ff; |
2593 | break; | |
355afbcd | 2594 | |
2b063e6d ILT |
2595 | case BFD_RELOC_SPARC_10: |
2596 | if (! in_signed_range (val, 0x3ff)) | |
48401fcf TT |
2597 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2598 | _("relocation overflow")); | |
2b063e6d ILT |
2599 | insn |= val & 0x3ff; |
2600 | break; | |
355afbcd | 2601 | |
54b9ebdd DE |
2602 | case BFD_RELOC_SPARC_7: |
2603 | if (! in_bitfield_range (val, 0x7f)) | |
48401fcf TT |
2604 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2605 | _("relocation overflow")); | |
54b9ebdd DE |
2606 | insn |= val & 0x7f; |
2607 | break; | |
2608 | ||
2b063e6d ILT |
2609 | case BFD_RELOC_SPARC_6: |
2610 | if (! in_bitfield_range (val, 0x3f)) | |
48401fcf TT |
2611 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2612 | _("relocation overflow")); | |
2b063e6d ILT |
2613 | insn |= val & 0x3f; |
2614 | break; | |
355afbcd | 2615 | |
2b063e6d ILT |
2616 | case BFD_RELOC_SPARC_5: |
2617 | if (! in_bitfield_range (val, 0x1f)) | |
48401fcf TT |
2618 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2619 | _("relocation overflow")); | |
2b063e6d ILT |
2620 | insn |= val & 0x1f; |
2621 | break; | |
8dd07a84 | 2622 | |
2b063e6d ILT |
2623 | case BFD_RELOC_SPARC_WDISP16: |
2624 | /* FIXME: simplify */ | |
2625 | if (((val > 0) && (val & ~0x3fffc)) | |
2626 | || ((val < 0) && (~(val - 1) & ~0x3fffc))) | |
48401fcf TT |
2627 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2628 | _("relocation overflow")); | |
2b063e6d ILT |
2629 | /* FIXME: The +1 deserves a comment. */ |
2630 | val = (val >> 2) + 1; | |
2631 | insn |= ((val & 0xc000) << 6) | (val & 0x3fff); | |
2632 | break; | |
8dd07a84 | 2633 | |
2b063e6d ILT |
2634 | case BFD_RELOC_SPARC_WDISP19: |
2635 | /* FIXME: simplify */ | |
2636 | if (((val > 0) && (val & ~0x1ffffc)) | |
2637 | || ((val < 0) && (~(val - 1) & ~0x1ffffc))) | |
48401fcf TT |
2638 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2639 | _("relocation overflow")); | |
2b063e6d ILT |
2640 | /* FIXME: The +1 deserves a comment. */ |
2641 | val = (val >> 2) + 1; | |
2642 | insn |= val & 0x7ffff; | |
2643 | break; | |
8dd07a84 | 2644 | |
2b063e6d ILT |
2645 | case BFD_RELOC_SPARC_HH22: |
2646 | val = BSR (val, 32); | |
2647 | /* intentional fallthrough */ | |
8dd07a84 | 2648 | |
2b063e6d ILT |
2649 | case BFD_RELOC_SPARC_LM22: |
2650 | case BFD_RELOC_HI22: | |
2651 | if (!fixP->fx_addsy) | |
2652 | { | |
2653 | insn |= (val >> 10) & 0x3fffff; | |
2654 | } | |
2655 | else | |
2656 | { | |
2657 | /* FIXME: Need comment explaining why we do this. */ | |
2658 | insn &= ~0xffff; | |
2659 | } | |
2660 | break; | |
355afbcd | 2661 | |
2b063e6d ILT |
2662 | case BFD_RELOC_SPARC22: |
2663 | if (val & ~0x003fffff) | |
48401fcf TT |
2664 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2665 | _("relocation overflow")); | |
2b063e6d ILT |
2666 | insn |= (val & 0x3fffff); |
2667 | break; | |
355afbcd | 2668 | |
2b063e6d ILT |
2669 | case BFD_RELOC_SPARC_HM10: |
2670 | val = BSR (val, 32); | |
2671 | /* intentional fallthrough */ | |
355afbcd | 2672 | |
2b063e6d ILT |
2673 | case BFD_RELOC_LO10: |
2674 | if (!fixP->fx_addsy) | |
2675 | { | |
2676 | insn |= val & 0x3ff; | |
2677 | } | |
2678 | else | |
2679 | { | |
2680 | /* FIXME: Need comment explaining why we do this. */ | |
2681 | insn &= ~0xff; | |
2682 | } | |
2683 | break; | |
355afbcd | 2684 | |
2b063e6d ILT |
2685 | case BFD_RELOC_SPARC13: |
2686 | if (! in_signed_range (val, 0x1fff)) | |
48401fcf TT |
2687 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2688 | _("relocation overflow")); | |
2b063e6d ILT |
2689 | insn |= val & 0x1fff; |
2690 | break; | |
355afbcd | 2691 | |
2b063e6d ILT |
2692 | case BFD_RELOC_SPARC_WDISP22: |
2693 | val = (val >> 2) + 1; | |
2694 | /* FALLTHROUGH */ | |
2695 | case BFD_RELOC_SPARC_BASE22: | |
2696 | insn |= val & 0x3fffff; | |
2697 | break; | |
355afbcd | 2698 | |
54b9ebdd DE |
2699 | case BFD_RELOC_SPARC_H44: |
2700 | if (!fixP->fx_addsy) | |
2701 | { | |
2702 | bfd_vma tval = val; | |
2703 | tval >>= 22; | |
54b9ebdd DE |
2704 | insn |= tval & 0x3fffff; |
2705 | } | |
2706 | break; | |
2707 | ||
2708 | case BFD_RELOC_SPARC_M44: | |
2709 | if (!fixP->fx_addsy) | |
2710 | insn |= (val >> 12) & 0x3ff; | |
2711 | break; | |
2712 | ||
2713 | case BFD_RELOC_SPARC_L44: | |
2714 | if (!fixP->fx_addsy) | |
2715 | insn |= val & 0xfff; | |
2716 | break; | |
2717 | ||
2718 | case BFD_RELOC_SPARC_HIX22: | |
2719 | if (!fixP->fx_addsy) | |
2720 | { | |
2721 | val ^= ~ (offsetT) 0; | |
54b9ebdd DE |
2722 | insn |= (val >> 10) & 0x3fffff; |
2723 | } | |
2724 | break; | |
2725 | ||
2726 | case BFD_RELOC_SPARC_LOX10: | |
2727 | if (!fixP->fx_addsy) | |
2728 | insn |= 0x1c00 | (val & 0x3ff); | |
2729 | break; | |
2730 | ||
2b063e6d ILT |
2731 | case BFD_RELOC_NONE: |
2732 | default: | |
54b9ebdd | 2733 | as_bad_where (fixP->fx_file, fixP->fx_line, |
48401fcf | 2734 | _("bad or unhandled relocation type: 0x%02x"), |
54b9ebdd | 2735 | fixP->fx_r_type); |
2b063e6d | 2736 | break; |
355afbcd | 2737 | } |
355afbcd | 2738 | |
2b063e6d ILT |
2739 | if (INSN_BIG_ENDIAN) |
2740 | bfd_putb32 (insn, (unsigned char *) buf); | |
355afbcd | 2741 | else |
2b063e6d | 2742 | bfd_putl32 (insn, (unsigned char *) buf); |
355afbcd | 2743 | } |
428d312b | 2744 | |
7ab2e983 ILT |
2745 | /* Are we finished with this relocation now? */ |
2746 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
2747 | fixP->fx_done = 1; | |
2748 | ||
428d312b | 2749 | return 1; |
428d312b | 2750 | } |
fecd2382 | 2751 | |
428d312b KR |
2752 | /* Translate internal representation of relocation info to BFD target |
2753 | format. */ | |
2754 | arelent * | |
2755 | tc_gen_reloc (section, fixp) | |
2756 | asection *section; | |
2757 | fixS *fixp; | |
2758 | { | |
2759 | arelent *reloc; | |
2760 | bfd_reloc_code_real_type code; | |
2761 | ||
590c50d8 | 2762 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
428d312b KR |
2763 | |
2764 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
2765 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
428d312b | 2766 | |
428d312b KR |
2767 | switch (fixp->fx_r_type) |
2768 | { | |
58d4951d | 2769 | case BFD_RELOC_16: |
428d312b KR |
2770 | case BFD_RELOC_32: |
2771 | case BFD_RELOC_HI22: | |
2772 | case BFD_RELOC_LO10: | |
2773 | case BFD_RELOC_32_PCREL_S2: | |
7ab2e983 | 2774 | case BFD_RELOC_SPARC13: |
428d312b | 2775 | case BFD_RELOC_SPARC_BASE13: |
a7aa7a2b ILT |
2776 | case BFD_RELOC_SPARC_WDISP16: |
2777 | case BFD_RELOC_SPARC_WDISP19: | |
ed9638af | 2778 | case BFD_RELOC_SPARC_WDISP22: |
693b21e7 | 2779 | case BFD_RELOC_64: |
8dd07a84 ILT |
2780 | case BFD_RELOC_SPARC_5: |
2781 | case BFD_RELOC_SPARC_6: | |
54b9ebdd | 2782 | case BFD_RELOC_SPARC_7: |
125f0b0d KR |
2783 | case BFD_RELOC_SPARC_10: |
2784 | case BFD_RELOC_SPARC_11: | |
2785 | case BFD_RELOC_SPARC_HH22: | |
2786 | case BFD_RELOC_SPARC_HM10: | |
2787 | case BFD_RELOC_SPARC_LM22: | |
2788 | case BFD_RELOC_SPARC_PC_HH22: | |
2789 | case BFD_RELOC_SPARC_PC_HM10: | |
2790 | case BFD_RELOC_SPARC_PC_LM22: | |
54b9ebdd DE |
2791 | case BFD_RELOC_SPARC_H44: |
2792 | case BFD_RELOC_SPARC_M44: | |
2793 | case BFD_RELOC_SPARC_L44: | |
2794 | case BFD_RELOC_SPARC_HIX22: | |
2795 | case BFD_RELOC_SPARC_LOX10: | |
fc23c14e | 2796 | case BFD_RELOC_SPARC_32LE: |
428d312b KR |
2797 | code = fixp->fx_r_type; |
2798 | break; | |
2799 | default: | |
2800 | abort (); | |
48401fcf | 2801 | return NULL; |
428d312b | 2802 | } |
4c67b523 ILT |
2803 | |
2804 | #if defined (OBJ_ELF) || defined (OBJ_AOUT) | |
2805 | /* If we are generating PIC code, we need to generate a different | |
2806 | set of relocs. */ | |
2807 | ||
2808 | #ifdef OBJ_ELF | |
2809 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" | |
2810 | #else | |
2811 | #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" | |
2812 | #endif | |
2813 | ||
2814 | if (sparc_pic_code) | |
2815 | { | |
2816 | switch (code) | |
2817 | { | |
2818 | case BFD_RELOC_32_PCREL_S2: | |
2819 | if (! S_IS_DEFINED (fixp->fx_addsy) | |
9f6da653 | 2820 | || S_IS_COMMON (fixp->fx_addsy) |
21965655 ILT |
2821 | || S_IS_EXTERNAL (fixp->fx_addsy) |
2822 | || S_IS_WEAK (fixp->fx_addsy)) | |
4c67b523 ILT |
2823 | code = BFD_RELOC_SPARC_WPLT30; |
2824 | break; | |
2825 | case BFD_RELOC_HI22: | |
2826 | if (fixp->fx_addsy != NULL | |
2827 | && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
2828 | code = BFD_RELOC_SPARC_PC22; | |
2829 | else | |
2830 | code = BFD_RELOC_SPARC_GOT22; | |
2831 | break; | |
2832 | case BFD_RELOC_LO10: | |
2833 | if (fixp->fx_addsy != NULL | |
2834 | && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
2835 | code = BFD_RELOC_SPARC_PC10; | |
2836 | else | |
2837 | code = BFD_RELOC_SPARC_GOT10; | |
2838 | break; | |
2839 | case BFD_RELOC_SPARC13: | |
2840 | code = BFD_RELOC_SPARC_GOT13; | |
2841 | break; | |
2842 | default: | |
2843 | break; | |
2844 | } | |
2845 | } | |
2846 | #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ | |
2847 | ||
428d312b | 2848 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
a7129c48 KR |
2849 | if (reloc->howto == 0) |
2850 | { | |
2851 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
48401fcf | 2852 | _("internal error: can't export reloc type %d (`%s')"), |
ade614d5 | 2853 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); |
a7129c48 KR |
2854 | return 0; |
2855 | } | |
c999fd9f KR |
2856 | |
2857 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ | |
a7aa7a2b ILT |
2858 | #ifdef OBJ_AOUT |
2859 | ||
4c67b523 ILT |
2860 | if (reloc->howto->pc_relative == 0 |
2861 | || code == BFD_RELOC_SPARC_PC10 | |
2862 | || code == BFD_RELOC_SPARC_PC22) | |
a7aa7a2b | 2863 | reloc->addend = fixp->fx_addnumber; |
a5002978 CM |
2864 | else if (sparc_pic_code |
2865 | && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
2866 | && fixp->fx_addsy != NULL | |
2867 | && (S_IS_EXTERNAL (fixp->fx_addsy) | |
2868 | || S_IS_WEAK (fixp->fx_addsy)) | |
2869 | && S_IS_DEFINED (fixp->fx_addsy) | |
2870 | && ! S_IS_COMMON (fixp->fx_addsy)) | |
2871 | reloc->addend = fixp->fx_addnumber; | |
a7aa7a2b ILT |
2872 | else |
2873 | reloc->addend = fixp->fx_offset - reloc->address; | |
2874 | ||
2875 | #else /* elf or coff */ | |
2876 | ||
4c67b523 ILT |
2877 | if (reloc->howto->pc_relative == 0 |
2878 | || code == BFD_RELOC_SPARC_PC10 | |
2879 | || code == BFD_RELOC_SPARC_PC22) | |
c999fd9f | 2880 | reloc->addend = fixp->fx_addnumber; |
7ab2e983 ILT |
2881 | else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0) |
2882 | reloc->addend = (section->vma | |
2883 | + fixp->fx_addnumber | |
2884 | + md_pcrel_from (fixp)); | |
c999fd9f | 2885 | else |
a7aa7a2b | 2886 | reloc->addend = fixp->fx_offset; |
a7aa7a2b | 2887 | #endif |
428d312b KR |
2888 | |
2889 | return reloc; | |
2890 | } | |
af6f39b4 DE |
2891 | \f |
2892 | /* We have no need to default values of symbols. */ | |
428d312b | 2893 | |
af6f39b4 DE |
2894 | /* ARGSUSED */ |
2895 | symbolS * | |
2896 | md_undefined_symbol (name) | |
2897 | char *name; | |
2898 | { | |
2899 | return 0; | |
2900 | } /* md_undefined_symbol() */ | |
fecd2382 | 2901 | |
af6f39b4 DE |
2902 | /* Round up a section size to the appropriate boundary. */ |
2903 | valueT | |
2904 | md_section_align (segment, size) | |
2905 | segT segment; | |
2906 | valueT size; | |
fecd2382 | 2907 | { |
af6f39b4 DE |
2908 | #ifndef OBJ_ELF |
2909 | /* This is not right for ELF; a.out wants it, and COFF will force | |
2910 | the alignment anyways. */ | |
2911 | valueT align = ((valueT) 1 | |
2912 | << (valueT) bfd_get_section_alignment (stdoutput, segment)); | |
2913 | valueT newsize; | |
2914 | /* turn alignment value into a mask */ | |
2915 | align--; | |
2916 | newsize = (size + align) & ~align; | |
2917 | return newsize; | |
2918 | #else | |
2919 | return size; | |
2920 | #endif | |
2921 | } | |
2922 | ||
2923 | /* Exactly what point is a PC-relative offset relative TO? | |
2924 | On the sparc, they're relative to the address of the offset, plus | |
2925 | its size. This gets us to the following instruction. | |
2926 | (??? Is this right? FIXME-SOON) */ | |
2927 | long | |
2928 | md_pcrel_from (fixP) | |
2929 | fixS *fixP; | |
2930 | { | |
2931 | long ret; | |
355afbcd | 2932 | |
af6f39b4 DE |
2933 | ret = fixP->fx_where + fixP->fx_frag->fr_address; |
2934 | if (! sparc_pic_code | |
2935 | || fixP->fx_addsy == NULL | |
2936 | || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0) | |
2937 | ret += fixP->fx_size; | |
2938 | return ret; | |
c999fd9f | 2939 | } |
f3d817d8 | 2940 | \f |
4a07363f ILT |
2941 | /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power |
2942 | of two. */ | |
2943 | ||
2944 | static int | |
2945 | log2 (value) | |
2946 | int value; | |
2947 | { | |
2948 | int shift; | |
2949 | ||
2950 | if (value <= 0) | |
2951 | return -1; | |
2952 | ||
2953 | for (shift = 0; (value & 1) == 0; value >>= 1) | |
2954 | ++shift; | |
2955 | ||
2956 | return (value == 1) ? shift : -1; | |
2957 | } | |
2958 | ||
839df5c3 | 2959 | /* |
af6f39b4 | 2960 | * sort of like s_lcomm |
839df5c3 | 2961 | */ |
162e3485 | 2962 | |
af6f39b4 DE |
2963 | #ifndef OBJ_ELF |
2964 | static int max_alignment = 15; | |
2b063e6d | 2965 | #endif |
355afbcd | 2966 | |
af6f39b4 DE |
2967 | static void |
2968 | s_reserve (ignore) | |
2969 | int ignore; | |
f3d817d8 | 2970 | { |
af6f39b4 DE |
2971 | char *name; |
2972 | char *p; | |
2973 | char c; | |
2974 | int align; | |
2975 | int size; | |
2976 | int temp; | |
2977 | symbolS *symbolP; | |
2978 | ||
2979 | name = input_line_pointer; | |
2980 | c = get_symbol_end (); | |
2981 | p = input_line_pointer; | |
2982 | *p = c; | |
2983 | SKIP_WHITESPACE (); | |
2984 | ||
2985 | if (*input_line_pointer != ',') | |
355afbcd | 2986 | { |
48401fcf | 2987 | as_bad (_("Expected comma after name")); |
af6f39b4 DE |
2988 | ignore_rest_of_line (); |
2989 | return; | |
2990 | } | |
355afbcd | 2991 | |
af6f39b4 DE |
2992 | ++input_line_pointer; |
2993 | ||
2994 | if ((size = get_absolute_expression ()) < 0) | |
2995 | { | |
48401fcf | 2996 | as_bad (_("BSS length (%d.) <0! Ignored."), size); |
af6f39b4 DE |
2997 | ignore_rest_of_line (); |
2998 | return; | |
2999 | } /* bad length */ | |
3000 | ||
3001 | *p = 0; | |
3002 | symbolP = symbol_find_or_make (name); | |
3003 | *p = c; | |
3004 | ||
3005 | if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 | |
3006 | && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) | |
3007 | { | |
48401fcf | 3008 | as_bad (_("bad .reserve segment -- expected BSS segment")); |
af6f39b4 DE |
3009 | return; |
3010 | } | |
3011 | ||
3012 | if (input_line_pointer[2] == '.') | |
3013 | input_line_pointer += 7; | |
3014 | else | |
3015 | input_line_pointer += 6; | |
3016 | SKIP_WHITESPACE (); | |
3017 | ||
3018 | if (*input_line_pointer == ',') | |
3019 | { | |
3020 | ++input_line_pointer; | |
3021 | ||
3022 | SKIP_WHITESPACE (); | |
3023 | if (*input_line_pointer == '\n') | |
e70ad5d5 | 3024 | { |
4a07363f ILT |
3025 | as_bad (_("missing alignment")); |
3026 | ignore_rest_of_line (); | |
af6f39b4 | 3027 | return; |
e70ad5d5 DE |
3028 | } |
3029 | ||
4a07363f ILT |
3030 | align = (int) get_absolute_expression (); |
3031 | ||
af6f39b4 DE |
3032 | #ifndef OBJ_ELF |
3033 | if (align > max_alignment) | |
3034 | { | |
3035 | align = max_alignment; | |
4a07363f | 3036 | as_warn (_("alignment too large; assuming %d"), align); |
af6f39b4 DE |
3037 | } |
3038 | #endif | |
4a07363f | 3039 | |
af6f39b4 DE |
3040 | if (align < 0) |
3041 | { | |
4a07363f ILT |
3042 | as_bad (_("negative alignment")); |
3043 | ignore_rest_of_line (); | |
3044 | return; | |
af6f39b4 | 3045 | } |
e70ad5d5 | 3046 | |
4a07363f | 3047 | if (align != 0) |
af6f39b4 | 3048 | { |
4a07363f ILT |
3049 | temp = log2 (align); |
3050 | if (temp < 0) | |
3051 | { | |
3052 | as_bad (_("alignment not a power of 2")); | |
3053 | ignore_rest_of_line (); | |
3054 | return; | |
3055 | } | |
355afbcd | 3056 | |
4a07363f ILT |
3057 | align = temp; |
3058 | } | |
3059 | ||
3060 | record_alignment (bss_section, align); | |
3061 | } | |
af6f39b4 DE |
3062 | else |
3063 | align = 0; | |
2b063e6d | 3064 | |
af6f39b4 DE |
3065 | if (!S_IS_DEFINED (symbolP) |
3066 | #ifdef OBJ_AOUT | |
3067 | && S_GET_OTHER (symbolP) == 0 | |
3068 | && S_GET_DESC (symbolP) == 0 | |
3069 | #endif | |
3070 | ) | |
3071 | { | |
3072 | if (! need_pass_2) | |
3073 | { | |
3074 | char *pfrag; | |
3075 | segT current_seg = now_seg; | |
3076 | subsegT current_subseg = now_subseg; | |
3077 | ||
3078 | subseg_set (bss_section, 1); /* switch to bss */ | |
3079 | ||
3080 | if (align) | |
3081 | frag_align (align, 0, 0); /* do alignment */ | |
3082 | ||
3083 | /* detach from old frag */ | |
3084 | if (S_GET_SEGMENT(symbolP) == bss_section) | |
3085 | symbolP->sy_frag->fr_symbol = NULL; | |
3086 | ||
3087 | symbolP->sy_frag = frag_now; | |
3088 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP, | |
3089 | (offsetT) size, (char *)0); | |
3090 | *pfrag = 0; | |
3091 | ||
3092 | S_SET_SEGMENT (symbolP, bss_section); | |
3093 | ||
3094 | subseg_set (current_seg, current_subseg); | |
3095 | } | |
3096 | } | |
3097 | else | |
3098 | { | |
3099 | as_warn("Ignoring attempt to re-define symbol %s", | |
3100 | S_GET_NAME (symbolP)); | |
3101 | } /* if not redefining */ | |
3102 | ||
3103 | demand_empty_rest_of_line (); | |
3104 | } | |
3105 | ||
3106 | static void | |
3107 | s_common (ignore) | |
3108 | int ignore; | |
3109 | { | |
3110 | char *name; | |
3111 | char c; | |
3112 | char *p; | |
3113 | int temp, size; | |
3114 | symbolS *symbolP; | |
3115 | ||
3116 | name = input_line_pointer; | |
3117 | c = get_symbol_end (); | |
3118 | /* just after name is now '\0' */ | |
3119 | p = input_line_pointer; | |
3120 | *p = c; | |
3121 | SKIP_WHITESPACE (); | |
3122 | if (*input_line_pointer != ',') | |
3123 | { | |
48401fcf | 3124 | as_bad (_("Expected comma after symbol-name")); |
af6f39b4 DE |
3125 | ignore_rest_of_line (); |
3126 | return; | |
3127 | } | |
3128 | input_line_pointer++; /* skip ',' */ | |
3129 | if ((temp = get_absolute_expression ()) < 0) | |
3130 | { | |
48401fcf | 3131 | as_bad (_(".COMMon length (%d.) <0! Ignored."), temp); |
af6f39b4 DE |
3132 | ignore_rest_of_line (); |
3133 | return; | |
3134 | } | |
3135 | size = temp; | |
3136 | *p = 0; | |
3137 | symbolP = symbol_find_or_make (name); | |
3138 | *p = c; | |
3139 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
3140 | { | |
48401fcf | 3141 | as_bad (_("Ignoring attempt to re-define symbol")); |
af6f39b4 DE |
3142 | ignore_rest_of_line (); |
3143 | return; | |
3144 | } | |
3145 | if (S_GET_VALUE (symbolP) != 0) | |
3146 | { | |
48401fcf | 3147 | if (S_GET_VALUE (symbolP) != (valueT) size) |
af6f39b4 | 3148 | { |
48401fcf | 3149 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."), |
af6f39b4 DE |
3150 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); |
3151 | } | |
3152 | } | |
3153 | else | |
3154 | { | |
3155 | #ifndef OBJ_ELF | |
3156 | S_SET_VALUE (symbolP, (valueT) size); | |
3157 | S_SET_EXTERNAL (symbolP); | |
3158 | #endif | |
3159 | } | |
3160 | know (symbolP->sy_frag == &zero_address_frag); | |
3161 | if (*input_line_pointer != ',') | |
3162 | { | |
48401fcf | 3163 | as_bad (_("Expected comma after common length")); |
af6f39b4 DE |
3164 | ignore_rest_of_line (); |
3165 | return; | |
3166 | } | |
3167 | input_line_pointer++; | |
3168 | SKIP_WHITESPACE (); | |
3169 | if (*input_line_pointer != '"') | |
3170 | { | |
3171 | temp = get_absolute_expression (); | |
4a07363f | 3172 | |
af6f39b4 DE |
3173 | #ifndef OBJ_ELF |
3174 | if (temp > max_alignment) | |
3175 | { | |
3176 | temp = max_alignment; | |
4a07363f | 3177 | as_warn (_("alignment too large; assuming %d"), temp); |
af6f39b4 DE |
3178 | } |
3179 | #endif | |
4a07363f | 3180 | |
af6f39b4 DE |
3181 | if (temp < 0) |
3182 | { | |
4a07363f ILT |
3183 | as_bad (_("negative alignment")); |
3184 | ignore_rest_of_line (); | |
3185 | return; | |
af6f39b4 | 3186 | } |
4a07363f | 3187 | |
af6f39b4 DE |
3188 | #ifdef OBJ_ELF |
3189 | if (symbolP->local) | |
3190 | { | |
3191 | segT old_sec; | |
3192 | int old_subsec; | |
3193 | char *p; | |
3194 | int align; | |
3195 | ||
3196 | old_sec = now_seg; | |
3197 | old_subsec = now_subseg; | |
4a07363f ILT |
3198 | |
3199 | if (temp == 0) | |
3200 | align = 0; | |
3201 | else | |
3202 | align = log2 (temp); | |
3203 | ||
3204 | if (align < 0) | |
3205 | { | |
3206 | as_bad (_("alignment not a power of 2")); | |
3207 | ignore_rest_of_line (); | |
3208 | return; | |
3209 | } | |
3210 | ||
af6f39b4 DE |
3211 | record_alignment (bss_section, align); |
3212 | subseg_set (bss_section, 0); | |
3213 | if (align) | |
3214 | frag_align (align, 0, 0); | |
3215 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
3216 | symbolP->sy_frag->fr_symbol = 0; | |
3217 | symbolP->sy_frag = frag_now; | |
3218 | p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, | |
3219 | (offsetT) size, (char *) 0); | |
3220 | *p = 0; | |
3221 | S_SET_SEGMENT (symbolP, bss_section); | |
3222 | S_CLEAR_EXTERNAL (symbolP); | |
3223 | subseg_set (old_sec, old_subsec); | |
3224 | } | |
3225 | else | |
4a07363f | 3226 | #endif /* OBJ_ELF */ |
af6f39b4 DE |
3227 | { |
3228 | allocate_common: | |
3229 | S_SET_VALUE (symbolP, (valueT) size); | |
3230 | #ifdef OBJ_ELF | |
3231 | S_SET_ALIGN (symbolP, temp); | |
3232 | #endif | |
3233 | S_SET_EXTERNAL (symbolP); | |
3234 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); | |
3235 | } | |
3236 | } | |
3237 | else | |
3238 | { | |
3239 | input_line_pointer++; | |
3240 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ | |
3241 | if (*input_line_pointer == '.') | |
3242 | input_line_pointer++; | |
3243 | /* @@ Some say data, some say bss. */ | |
3244 | if (strncmp (input_line_pointer, "bss\"", 4) | |
3245 | && strncmp (input_line_pointer, "data\"", 5)) | |
3246 | { | |
3247 | while (*--input_line_pointer != '"') | |
3248 | ; | |
3249 | input_line_pointer--; | |
3250 | goto bad_common_segment; | |
3251 | } | |
3252 | while (*input_line_pointer++ != '"') | |
3253 | ; | |
3254 | goto allocate_common; | |
3255 | } | |
2b063e6d | 3256 | |
af6f39b4 DE |
3257 | #ifdef BFD_ASSEMBLER |
3258 | symbolP->bsym->flags |= BSF_OBJECT; | |
4c67b523 ILT |
3259 | #endif |
3260 | ||
af6f39b4 DE |
3261 | demand_empty_rest_of_line (); |
3262 | return; | |
f3d817d8 | 3263 | |
af6f39b4 DE |
3264 | { |
3265 | bad_common_segment: | |
3266 | p = input_line_pointer; | |
3267 | while (*p && *p != '\n') | |
3268 | p++; | |
3269 | c = *p; | |
3270 | *p = '\0'; | |
48401fcf | 3271 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); |
af6f39b4 DE |
3272 | *p = c; |
3273 | input_line_pointer = p; | |
3274 | ignore_rest_of_line (); | |
3275 | return; | |
3276 | } | |
3277 | } | |
f3d817d8 | 3278 | |
af6f39b4 DE |
3279 | /* Handle the .empty pseudo-op. This supresses the warnings about |
3280 | invalid delay slot usage. */ | |
f3d817d8 | 3281 | |
af6f39b4 DE |
3282 | static void |
3283 | s_empty (ignore) | |
3284 | int ignore; | |
3285 | { | |
3286 | /* The easy way to implement is to just forget about the last | |
3287 | instruction. */ | |
3288 | last_insn = NULL; | |
3289 | } | |
a7aa7a2b | 3290 | |
af6f39b4 DE |
3291 | static void |
3292 | s_seg (ignore) | |
3293 | int ignore; | |
3294 | { | |
f3d817d8 | 3295 | |
af6f39b4 DE |
3296 | if (strncmp (input_line_pointer, "\"text\"", 6) == 0) |
3297 | { | |
3298 | input_line_pointer += 6; | |
3299 | s_text (0); | |
3300 | return; | |
355afbcd | 3301 | } |
af6f39b4 DE |
3302 | if (strncmp (input_line_pointer, "\"data\"", 6) == 0) |
3303 | { | |
3304 | input_line_pointer += 6; | |
3305 | s_data (0); | |
3306 | return; | |
3307 | } | |
3308 | if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) | |
3309 | { | |
3310 | input_line_pointer += 7; | |
3311 | s_data1 (); | |
3312 | return; | |
3313 | } | |
3314 | if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) | |
3315 | { | |
3316 | input_line_pointer += 5; | |
3317 | /* We only support 2 segments -- text and data -- for now, so | |
3318 | things in the "bss segment" will have to go into data for now. | |
3319 | You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ | |
3320 | subseg_set (data_section, 255); /* FIXME-SOMEDAY */ | |
3321 | return; | |
3322 | } | |
48401fcf | 3323 | as_bad (_("Unknown segment type")); |
af6f39b4 | 3324 | demand_empty_rest_of_line (); |
f3d817d8 DM |
3325 | } |
3326 | ||
af6f39b4 DE |
3327 | static void |
3328 | s_data1 () | |
f3d817d8 | 3329 | { |
af6f39b4 DE |
3330 | subseg_set (data_section, 1); |
3331 | demand_empty_rest_of_line (); | |
3332 | } | |
e70ad5d5 | 3333 | |
af6f39b4 DE |
3334 | static void |
3335 | s_proc (ignore) | |
3336 | int ignore; | |
3337 | { | |
3338 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
5e0a90a8 | 3339 | { |
af6f39b4 | 3340 | ++input_line_pointer; |
5e0a90a8 | 3341 | } |
af6f39b4 | 3342 | ++input_line_pointer; |
f3d817d8 | 3343 | } |
fecd2382 | 3344 | |
af6f39b4 DE |
3345 | /* This static variable is set by s_uacons to tell sparc_cons_align |
3346 | that the expession does not need to be aligned. */ | |
fecd2382 | 3347 | |
af6f39b4 DE |
3348 | static int sparc_no_align_cons = 0; |
3349 | ||
3350 | /* This handles the unaligned space allocation pseudo-ops, such as | |
3351 | .uaword. .uaword is just like .word, but the value does not need | |
3352 | to be aligned. */ | |
3353 | ||
3354 | static void | |
3355 | s_uacons (bytes) | |
3356 | int bytes; | |
fecd2382 | 3357 | { |
af6f39b4 DE |
3358 | /* Tell sparc_cons_align not to align this value. */ |
3359 | sparc_no_align_cons = 1; | |
3360 | cons (bytes); | |
428d312b | 3361 | } |
fecd2382 | 3362 | |
af6f39b4 DE |
3363 | /* If the --enforce-aligned-data option is used, we require .word, |
3364 | et. al., to be aligned correctly. We do it by setting up an | |
3365 | rs_align_code frag, and checking in HANDLE_ALIGN to make sure that | |
3366 | no unexpected alignment was introduced. | |
3367 | ||
3368 | The SunOS and Solaris native assemblers enforce aligned data by | |
3369 | default. We don't want to do that, because gcc can deliberately | |
3370 | generate misaligned data if the packed attribute is used. Instead, | |
3371 | we permit misaligned data by default, and permit the user to set an | |
3372 | option to check for it. */ | |
3373 | ||
3374 | void | |
3375 | sparc_cons_align (nbytes) | |
3376 | int nbytes; | |
fecd2382 | 3377 | { |
af6f39b4 DE |
3378 | int nalign; |
3379 | char *p; | |
4c67b523 | 3380 | |
af6f39b4 DE |
3381 | /* Only do this if we are enforcing aligned data. */ |
3382 | if (! enforce_aligned_data) | |
3383 | return; | |
3384 | ||
3385 | if (sparc_no_align_cons) | |
3386 | { | |
3387 | /* This is an unaligned pseudo-op. */ | |
3388 | sparc_no_align_cons = 0; | |
3389 | return; | |
3390 | } | |
3391 | ||
4a07363f | 3392 | nalign = log2 (nbytes); |
af6f39b4 DE |
3393 | if (nalign == 0) |
3394 | return; | |
3395 | ||
4a07363f ILT |
3396 | assert (nalign > 0); |
3397 | ||
af6f39b4 DE |
3398 | if (now_seg == absolute_section) |
3399 | { | |
3400 | if ((abs_section_offset & ((1 << nalign) - 1)) != 0) | |
48401fcf | 3401 | as_bad (_("misaligned data")); |
af6f39b4 DE |
3402 | return; |
3403 | } | |
3404 | ||
3405 | p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0, | |
3406 | (symbolS *) NULL, (offsetT) nalign, (char *) NULL); | |
3407 | ||
3408 | record_alignment (now_seg, nalign); | |
428d312b | 3409 | } |
fecd2382 | 3410 | |
af6f39b4 DE |
3411 | /* This is where we do the unexpected alignment check. |
3412 | This is called from HANDLE_ALIGN in tc-sparc.h. */ | |
3413 | ||
3414 | void | |
3415 | sparc_handle_align (fragp) | |
3416 | fragS *fragp; | |
3417 | { | |
7532235c | 3418 | if (fragp->fr_type == rs_align_code && !fragp->fr_subtype |
af6f39b4 | 3419 | && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0) |
48401fcf | 3420 | as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); |
7532235c RH |
3421 | if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024) |
3422 | { | |
3423 | int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
3424 | ||
04a92367 ILT |
3425 | if (count >= 4 |
3426 | && !(count & 3) | |
3427 | && count <= 1024 | |
3428 | && !((long)(fragp->fr_literal + fragp->fr_fix) & 3)) | |
7532235c RH |
3429 | { |
3430 | unsigned *p = (unsigned *)(fragp->fr_literal + fragp->fr_fix); | |
3431 | int i; | |
3432 | ||
a5002978 CM |
3433 | for (i = 0; i < count; i += 4, p++) |
3434 | if (INSN_BIG_ENDIAN) | |
3435 | number_to_chars_bigendian ((char *)p, 0x01000000, 4); /* emit nops */ | |
3436 | else | |
3437 | number_to_chars_littleendian ((char *)p, 0x10000000, 4); | |
3438 | ||
7532235c | 3439 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) |
a5002978 | 3440 | { |
04a92367 ILT |
3441 | char *waddr = &fragp->fr_literal[fragp->fr_fix]; |
3442 | unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ | |
3443 | if (INSN_BIG_ENDIAN) | |
3444 | number_to_chars_bigendian (waddr, wval, 4); | |
3445 | else | |
3446 | number_to_chars_littleendian (waddr, wval, 4); | |
a5002978 | 3447 | } |
7532235c RH |
3448 | fragp->fr_var = count; |
3449 | } | |
3450 | } | |
af6f39b4 | 3451 | } |
1bb6aaad RH |
3452 | |
3453 | #ifdef OBJ_ELF | |
3454 | /* Some special processing for a Sparc ELF file. */ | |
3455 | ||
3456 | void | |
3457 | sparc_elf_final_processing () | |
3458 | { | |
3459 | /* Set the Sparc ELF flag bits. FIXME: There should probably be some | |
3460 | sort of BFD interface for this. */ | |
3461 | if (sparc_arch_size == 64) | |
04a92367 ILT |
3462 | { |
3463 | switch (sparc_memory_model) | |
3464 | { | |
3465 | case MM_RMO: | |
3466 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; | |
3467 | break; | |
3468 | case MM_PSO: | |
3469 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; | |
3470 | break; | |
3471 | default: | |
3472 | break; | |
3473 | } | |
3474 | } | |
1bb6aaad RH |
3475 | else if (current_architecture >= SPARC_OPCODE_ARCH_V9) |
3476 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; | |
3477 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
3478 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; | |
3479 | } | |
3480 | #endif | |
fc23c14e SC |
3481 | |
3482 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
3483 | reloc for a cons. We could use the definition there, except that | |
3484 | we want to handle little endian relocs specially. */ | |
3485 | ||
3486 | void | |
3487 | cons_fix_new_sparc (frag, where, nbytes, exp) | |
3488 | fragS *frag; | |
3489 | int where; | |
3490 | unsigned int nbytes; | |
3491 | expressionS *exp; | |
3492 | { | |
3493 | bfd_reloc_code_real_type r; | |
3494 | ||
3495 | r = (nbytes == 1 ? BFD_RELOC_8 : | |
3496 | (nbytes == 2 ? BFD_RELOC_16 : | |
3497 | (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
3498 | ||
3499 | #ifdef OBJ_ELF | |
3500 | if (target_little_endian_data && nbytes == 4) | |
3501 | r = BFD_RELOC_SPARC_32LE; | |
3502 | #endif | |
3503 | fix_new_exp (frag, where, (int) nbytes, exp, 0, r); | |
3504 | } |