Commit | Line | Data |
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252b5132 | 1 | /* tc-sparc.c -- Assemble for the SPARC |
2571583a | 2 | Copyright (C) 1989-2017 Free Software Foundation, Inc. |
252b5132 RH |
3 | This file is part of GAS, the GNU Assembler. |
4 | ||
5 | GAS is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 7 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
8 | any later version. |
9 | ||
10 | GAS is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public | |
16 | License along with GAS; see the file COPYING. If not, write | |
4b4da160 NC |
17 | to the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
18 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 19 | |
252b5132 | 20 | #include "as.h" |
3882b010 | 21 | #include "safe-ctype.h" |
252b5132 RH |
22 | #include "subsegs.h" |
23 | ||
24 | #include "opcode/sparc.h" | |
364b6d8b | 25 | #include "dw2gencfi.h" |
252b5132 RH |
26 | |
27 | #ifdef OBJ_ELF | |
28 | #include "elf/sparc.h" | |
732d96b6 | 29 | #include "dwarf2dbg.h" |
252b5132 RH |
30 | #endif |
31 | ||
6c1b24e4 AO |
32 | /* Some ancient Sun C compilers would not take such hex constants as |
33 | unsigned, and would end up sign-extending them to form an offsetT, | |
34 | so use these constants instead. */ | |
35 | #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) | |
36 | #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) | |
37 | ||
5a49b8ac AM |
38 | static int sparc_ip (char *, const struct sparc_opcode **); |
39 | static int parse_keyword_arg (int (*) (const char *), char **, int *); | |
40 | static int parse_const_expr_arg (char **, int *); | |
41 | static int get_expression (char *); | |
252b5132 RH |
42 | |
43 | /* Default architecture. */ | |
44 | /* ??? The default value should be V8, but sparclite support was added | |
45 | by making it the default. GCC now passes -Asparclite, so maybe sometime in | |
46 | the future we can set this to V8. */ | |
47 | #ifndef DEFAULT_ARCH | |
48 | #define DEFAULT_ARCH "sparclite" | |
49 | #endif | |
e0471c16 | 50 | static const char *default_arch = DEFAULT_ARCH; |
252b5132 RH |
51 | |
52 | /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' | |
53 | have been set. */ | |
54 | static int default_init_p; | |
55 | ||
56 | /* Current architecture. We don't bump up unless necessary. */ | |
57 | static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; | |
58 | ||
59 | /* The maximum architecture level we can bump up to. | |
60 | In a 32 bit environment, don't allow bumping up to v9 by default. | |
61 | The native assembler works this way. The user is required to pass | |
62 | an explicit argument before we'll create v9 object files. However, if | |
63 | we don't see any v9 insns, a v8plus object file is not created. */ | |
64 | static enum sparc_opcode_arch_val max_architecture; | |
65 | ||
66 | /* Either 32 or 64, selects file format. */ | |
67 | static int sparc_arch_size; | |
68 | /* Initial (default) value, recorded separately in case a user option | |
69 | changes the value before md_show_usage is called. */ | |
70 | static int default_arch_size; | |
71 | ||
72 | #ifdef OBJ_ELF | |
73 | /* The currently selected v9 memory model. Currently only used for | |
74 | ELF. */ | |
75 | static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; | |
9e8c70f9 DM |
76 | |
77 | #ifndef TE_SOLARIS | |
78 | /* Bitmask of instruction types seen so far, used to populate the | |
79 | GNU attributes section with hwcap information. */ | |
3d68f91c | 80 | static bfd_uint64_t hwcap_seen; |
9e8c70f9 | 81 | #endif |
252b5132 RH |
82 | #endif |
83 | ||
3d68f91c | 84 | static bfd_uint64_t hwcap_allowed; |
4bafe00e | 85 | |
252b5132 RH |
86 | static int architecture_requested; |
87 | static int warn_on_bump; | |
88 | ||
89 | /* If warn_on_bump and the needed architecture is higher than this | |
90 | architecture, issue a warning. */ | |
91 | static enum sparc_opcode_arch_val warn_after_architecture; | |
92 | ||
46a2d504 JM |
93 | /* Non-zero if the assembler should generate error if an undeclared |
94 | g[23] register has been used in -64. */ | |
6d8809aa RH |
95 | static int no_undeclared_regs; |
96 | ||
46a2d504 JM |
97 | /* Non-zero if the assembler should generate a warning if an |
98 | unpredictable DCTI (delayed control transfer instruction) couple is | |
99 | found. */ | |
100 | static int dcti_couples_detect; | |
101 | ||
6faf3d66 JJ |
102 | /* Non-zero if we should try to relax jumps and calls. */ |
103 | static int sparc_relax; | |
104 | ||
252b5132 RH |
105 | /* Non-zero if we are generating PIC code. */ |
106 | int sparc_pic_code; | |
107 | ||
108 | /* Non-zero if we should give an error when misaligned data is seen. */ | |
109 | static int enforce_aligned_data; | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
113 | static int target_little_endian_data; | |
114 | ||
6d8809aa RH |
115 | /* Symbols for global registers on v9. */ |
116 | static symbolS *globals[8]; | |
117 | ||
364b6d8b JJ |
118 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ |
119 | int sparc_cie_data_alignment; | |
120 | ||
252b5132 RH |
121 | /* V9 and 86x have big and little endian data, but instructions are always big |
122 | endian. The sparclet has bi-endian support but both data and insns have | |
123 | the same endianness. Global `target_big_endian' is used for data. | |
124 | The following macro is used for instructions. */ | |
125 | #ifndef INSN_BIG_ENDIAN | |
126 | #define INSN_BIG_ENDIAN (target_big_endian \ | |
127 | || default_arch_type == sparc86x \ | |
128 | || SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
129 | #endif | |
130 | ||
e0c6ed95 | 131 | /* Handle of the OPCODE hash table. */ |
252b5132 RH |
132 | static struct hash_control *op_hash; |
133 | ||
5a49b8ac AM |
134 | static void s_data1 (void); |
135 | static void s_seg (int); | |
136 | static void s_proc (int); | |
137 | static void s_reserve (int); | |
138 | static void s_common (int); | |
139 | static void s_empty (int); | |
140 | static void s_uacons (int); | |
141 | static void s_ncons (int); | |
a7982600 | 142 | #ifdef OBJ_ELF |
5a49b8ac | 143 | static void s_register (int); |
a7982600 | 144 | #endif |
252b5132 RH |
145 | |
146 | const pseudo_typeS md_pseudo_table[] = | |
147 | { | |
e0c6ed95 | 148 | {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ |
252b5132 RH |
149 | {"common", s_common, 0}, |
150 | {"empty", s_empty, 0}, | |
151 | {"global", s_globl, 0}, | |
152 | {"half", cons, 2}, | |
cf9a1301 | 153 | {"nword", s_ncons, 0}, |
252b5132 RH |
154 | {"optim", s_ignore, 0}, |
155 | {"proc", s_proc, 0}, | |
156 | {"reserve", s_reserve, 0}, | |
157 | {"seg", s_seg, 0}, | |
158 | {"skip", s_space, 0}, | |
159 | {"word", cons, 4}, | |
160 | {"xword", cons, 8}, | |
161 | {"uahalf", s_uacons, 2}, | |
162 | {"uaword", s_uacons, 4}, | |
163 | {"uaxword", s_uacons, 8}, | |
164 | #ifdef OBJ_ELF | |
e0c6ed95 | 165 | /* These are specific to sparc/svr4. */ |
252b5132 RH |
166 | {"2byte", s_uacons, 2}, |
167 | {"4byte", s_uacons, 4}, | |
168 | {"8byte", s_uacons, 8}, | |
6d8809aa | 169 | {"register", s_register, 0}, |
252b5132 RH |
170 | #endif |
171 | {NULL, 0, 0}, | |
172 | }; | |
173 | ||
252b5132 | 174 | /* This array holds the chars that always start a comment. If the |
e0c6ed95 AM |
175 | pre-processor is disabled, these aren't very useful. */ |
176 | const char comment_chars[] = "!"; /* JF removed '|' from | |
177 | comment_chars. */ | |
252b5132 RH |
178 | |
179 | /* This array holds the chars that only start a comment at the beginning of | |
180 | a line. If the line seems to have the form '# 123 filename' | |
e0c6ed95 | 181 | .line and .file directives will appear in the pre-processed output. */ |
252b5132 RH |
182 | /* Note that input_file.c hand checks for '#' at the beginning of the |
183 | first line of the input file. This is because the compiler outputs | |
e0c6ed95 | 184 | #NO_APP at the beginning of its output. */ |
252b5132 | 185 | /* Also note that comments started like this one will always |
e0c6ed95 | 186 | work if '/' isn't otherwise defined. */ |
252b5132 RH |
187 | const char line_comment_chars[] = "#"; |
188 | ||
63a0b638 | 189 | const char line_separator_chars[] = ";"; |
252b5132 | 190 | |
e0c6ed95 AM |
191 | /* Chars that can be used to separate mant from exp in floating point |
192 | nums. */ | |
252b5132 RH |
193 | const char EXP_CHARS[] = "eE"; |
194 | ||
e0c6ed95 AM |
195 | /* Chars that mean this number is a floating point constant. |
196 | As in 0f12.456 | |
197 | or 0d1.2345e12 */ | |
252b5132 RH |
198 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
199 | ||
200 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
201 | changed in read.c. Ideally it shouldn't have to know about it at all, | |
202 | but nothing is ideal around here. */ | |
203 | ||
74b56d1f | 204 | #define isoctal(c) ((unsigned) ((c) - '0') < 8) |
252b5132 RH |
205 | |
206 | struct sparc_it | |
207 | { | |
6d4af3c2 | 208 | const char *error; |
252b5132 RH |
209 | unsigned long opcode; |
210 | struct nlist *nlistp; | |
211 | expressionS exp; | |
cf9a1301 | 212 | expressionS exp2; |
252b5132 RH |
213 | int pcrel; |
214 | bfd_reloc_code_real_type reloc; | |
215 | }; | |
216 | ||
217 | struct sparc_it the_insn, set_insn; | |
218 | ||
5a49b8ac | 219 | static void output_insn (const struct sparc_opcode *, struct sparc_it *); |
252b5132 RH |
220 | \f |
221 | /* Table of arguments to -A. | |
222 | The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect | |
223 | for this use. That table is for opcodes only. This table is for opcodes | |
224 | and file formats. */ | |
225 | ||
d6787ef9 | 226 | enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus, |
19f7b010 | 227 | v8plusa, v9, v9a, v9b, v9_64}; |
252b5132 RH |
228 | |
229 | static struct sparc_arch { | |
e0471c16 TS |
230 | const char *name; |
231 | const char *opcode_arch; | |
252b5132 RH |
232 | enum sparc_arch_types arch_type; |
233 | /* Default word size, as specified during configuration. | |
234 | A value of zero means can't be used to specify default architecture. */ | |
235 | int default_arch_size; | |
236 | /* Allowable arg to -A? */ | |
237 | int user_option_p; | |
6884417a JM |
238 | /* Extra hardware capabilities allowed. These are added to the |
239 | hardware capabilities associated with the opcode | |
240 | architecture. */ | |
4bafe00e | 241 | int hwcap_allowed; |
3d68f91c | 242 | int hwcap2_allowed; |
252b5132 | 243 | } sparc_arch_table[] = { |
3d68f91c JM |
244 | { "v6", "v6", v6, 0, 1, 0, 0 }, |
245 | { "v7", "v7", v7, 0, 1, 0, 0 }, | |
6884417a JM |
246 | { "v8", "v8", v8, 32, 1, 0, 0 }, |
247 | { "v8a", "v8", v8, 32, 1, 0, 0 }, | |
248 | { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
249 | { "sparcvis", "v9a", v9, 0, 1, 0, 0 }, | |
250 | { "sparcvis2", "v9b", v9, 0, 1, 0, 0 }, | |
251 | { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_FMAF, 0 }, | |
252 | { "sparcima", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_IMA, 0 }, | |
253 | { "sparcvis3", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 }, | |
254 | { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 }, | |
255 | ||
256 | { "sparc4", "v9v", v9, 0, 1, 0, 0 }, | |
257 | { "sparc5", "v9m", v9, 0, 1, 0, 0 }, | |
258 | ||
259 | { "leon", "leon", leon, 32, 1, 0, 0 }, | |
260 | { "sparclet", "sparclet", sparclet, 32, 1, 0, 0 }, | |
261 | { "sparclite", "sparclite", sparclite, 32, 1, 0, 0 }, | |
262 | { "sparc86x", "sparclite", sparc86x, 32, 1, 0, 0 }, | |
263 | ||
264 | { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
265 | { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
266 | { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
267 | { "v8plusc", "v9c", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
268 | { "v8plusd", "v9d", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
269 | { "v8pluse", "v9e", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
270 | { "v8plusv", "v9v", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
271 | { "v8plusm", "v9m", v9, 0, 1, HWCAP_V8PLUS, 0 }, | |
272 | ||
273 | { "v9", "v9", v9, 0, 1, 0, 0 }, | |
274 | { "v9a", "v9a", v9, 0, 1, 0, 0 }, | |
275 | { "v9b", "v9b", v9, 0, 1, 0, 0 }, | |
276 | { "v9c", "v9c", v9, 0, 1, 0, 0 }, | |
277 | { "v9d", "v9d", v9, 0, 1, 0, 0 }, | |
278 | { "v9e", "v9e", v9, 0, 1, 0, 0 }, | |
279 | { "v9v", "v9v", v9, 0, 1, 0, 0 }, | |
280 | { "v9m", "v9m", v9, 0, 1, 0, 0 }, | |
3d68f91c | 281 | |
1110793a | 282 | /* This exists to allow configure.tgt to pass one |
252b5132 | 283 | value to specify both the default machine and default word size. */ |
6884417a | 284 | { "v9-64", "v9", v9, 64, 0, 0, 0 }, |
3d68f91c | 285 | { NULL, NULL, v8, 0, 0, 0, 0 } |
252b5132 RH |
286 | }; |
287 | ||
288 | /* Variant of default_arch */ | |
289 | static enum sparc_arch_types default_arch_type; | |
290 | ||
291 | static struct sparc_arch * | |
e0471c16 | 292 | lookup_arch (const char *name) |
252b5132 RH |
293 | { |
294 | struct sparc_arch *sa; | |
295 | ||
296 | for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) | |
297 | if (strcmp (sa->name, name) == 0) | |
298 | break; | |
299 | if (sa->name == NULL) | |
300 | return NULL; | |
301 | return sa; | |
302 | } | |
303 | ||
304 | /* Initialize the default opcode arch and word size from the default | |
305 | architecture name. */ | |
306 | ||
307 | static void | |
5a49b8ac | 308 | init_default_arch (void) |
252b5132 RH |
309 | { |
310 | struct sparc_arch *sa = lookup_arch (default_arch); | |
311 | ||
312 | if (sa == NULL | |
313 | || sa->default_arch_size == 0) | |
314 | as_fatal (_("Invalid default architecture, broken assembler.")); | |
315 | ||
316 | max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); | |
317 | if (max_architecture == SPARC_OPCODE_ARCH_BAD) | |
318 | as_fatal (_("Bad opcode table, broken assembler.")); | |
319 | default_arch_size = sparc_arch_size = sa->default_arch_size; | |
320 | default_init_p = 1; | |
321 | default_arch_type = sa->arch_type; | |
322 | } | |
323 | ||
324 | /* Called by TARGET_FORMAT. */ | |
325 | ||
326 | const char * | |
5a49b8ac | 327 | sparc_target_format (void) |
252b5132 RH |
328 | { |
329 | /* We don't get a chance to initialize anything before we're called, | |
330 | so handle that now. */ | |
331 | if (! default_init_p) | |
332 | init_default_arch (); | |
333 | ||
334 | #ifdef OBJ_AOUT | |
335 | #ifdef TE_NetBSD | |
336 | return "a.out-sparc-netbsd"; | |
337 | #else | |
338 | #ifdef TE_SPARCAOUT | |
339 | if (target_big_endian) | |
340 | return "a.out-sunos-big"; | |
341 | else if (default_arch_type == sparc86x && target_little_endian_data) | |
342 | return "a.out-sunos-big"; | |
ab3e48dc KH |
343 | else |
344 | return "a.out-sparc-little"; | |
252b5132 RH |
345 | #else |
346 | return "a.out-sunos-big"; | |
347 | #endif | |
348 | #endif | |
349 | #endif | |
350 | ||
351 | #ifdef OBJ_BOUT | |
352 | return "b.out.big"; | |
353 | #endif | |
354 | ||
355 | #ifdef OBJ_COFF | |
356 | #ifdef TE_LYNX | |
357 | return "coff-sparc-lynx"; | |
358 | #else | |
359 | return "coff-sparc"; | |
360 | #endif | |
361 | #endif | |
362 | ||
910600e9 RS |
363 | #ifdef TE_VXWORKS |
364 | return "elf32-sparc-vxworks"; | |
365 | #endif | |
366 | ||
252b5132 | 367 | #ifdef OBJ_ELF |
71a75f6f | 368 | return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; |
252b5132 RH |
369 | #endif |
370 | ||
371 | abort (); | |
372 | } | |
373 | \f | |
e0c6ed95 | 374 | /* md_parse_option |
252b5132 RH |
375 | * Invocation line includes a switch not recognized by the base assembler. |
376 | * See if it's a processor-specific option. These are: | |
377 | * | |
378 | * -bump | |
379 | * Warn on architecture bumps. See also -A. | |
380 | * | |
d6787ef9 | 381 | * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet |
252b5132 | 382 | * Standard 32 bit architectures. |
19f7b010 | 383 | * -Av9, -Av9a, -Av9b |
252b5132 RH |
384 | * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). |
385 | * This used to only mean 64 bits, but properly specifying it | |
386 | * complicated gcc's ASM_SPECs, so now opcode selection is | |
387 | * specified orthogonally to word size (except when specifying | |
388 | * the default, but that is an internal implementation detail). | |
19f7b010 JJ |
389 | * -Av8plus, -Av8plusa, -Av8plusb |
390 | * Same as -Av9{,a,b}. | |
391 | * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb | |
392 | * Same as -Av8plus{,a,b} -32, for compatibility with Sun's | |
393 | * assembler. | |
394 | * -xarch=v9, -xarch=v9a, -xarch=v9b | |
395 | * Same as -Av9{,a,b} -64, for compatibility with Sun's | |
c2158c24 | 396 | * assembler. |
252b5132 RH |
397 | * |
398 | * Select the architecture and possibly the file format. | |
399 | * Instructions or features not supported by the selected | |
400 | * architecture cause fatal errors. | |
401 | * | |
402 | * The default is to start at v6, and bump the architecture up | |
403 | * whenever an instruction is seen at a higher level. In 32 bit | |
404 | * environments, v9 is not bumped up to, the user must pass | |
19f7b010 | 405 | * -Av8plus{,a,b}. |
252b5132 RH |
406 | * |
407 | * If -bump is specified, a warning is printing when bumping to | |
408 | * higher levels. | |
409 | * | |
410 | * If an architecture is specified, all instructions must match | |
411 | * that architecture. Any higher level instructions are flagged | |
412 | * as errors. Note that in the 32 bit environment specifying | |
413 | * -Av8plus does not automatically create a v8plus object file, a | |
414 | * v9 insn must be seen. | |
415 | * | |
416 | * If both an architecture and -bump are specified, the | |
417 | * architecture starts at the specified level, but bumps are | |
418 | * warnings. Note that we can't set `current_architecture' to | |
419 | * the requested level in this case: in the 32 bit environment, | |
420 | * we still must avoid creating v8plus object files unless v9 | |
421 | * insns are seen. | |
422 | * | |
423 | * Note: | |
424 | * Bumping between incompatible architectures is always an | |
425 | * error. For example, from sparclite to v9. | |
426 | */ | |
427 | ||
428 | #ifdef OBJ_ELF | |
5a38dc70 | 429 | const char *md_shortopts = "A:K:VQ:sq"; |
252b5132 RH |
430 | #else |
431 | #ifdef OBJ_AOUT | |
5a38dc70 | 432 | const char *md_shortopts = "A:k"; |
252b5132 | 433 | #else |
5a38dc70 | 434 | const char *md_shortopts = "A:"; |
252b5132 RH |
435 | #endif |
436 | #endif | |
437 | struct option md_longopts[] = { | |
438 | #define OPTION_BUMP (OPTION_MD_BASE) | |
439 | {"bump", no_argument, NULL, OPTION_BUMP}, | |
440 | #define OPTION_SPARC (OPTION_MD_BASE + 1) | |
441 | {"sparc", no_argument, NULL, OPTION_SPARC}, | |
442 | #define OPTION_XARCH (OPTION_MD_BASE + 2) | |
443 | {"xarch", required_argument, NULL, OPTION_XARCH}, | |
444 | #ifdef OBJ_ELF | |
445 | #define OPTION_32 (OPTION_MD_BASE + 3) | |
446 | {"32", no_argument, NULL, OPTION_32}, | |
447 | #define OPTION_64 (OPTION_MD_BASE + 4) | |
448 | {"64", no_argument, NULL, OPTION_64}, | |
449 | #define OPTION_TSO (OPTION_MD_BASE + 5) | |
450 | {"TSO", no_argument, NULL, OPTION_TSO}, | |
451 | #define OPTION_PSO (OPTION_MD_BASE + 6) | |
452 | {"PSO", no_argument, NULL, OPTION_PSO}, | |
453 | #define OPTION_RMO (OPTION_MD_BASE + 7) | |
454 | {"RMO", no_argument, NULL, OPTION_RMO}, | |
455 | #endif | |
456 | #ifdef SPARC_BIENDIAN | |
457 | #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) | |
458 | {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, | |
459 | #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) | |
460 | {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, | |
461 | #endif | |
462 | #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) | |
463 | {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, | |
464 | #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) | |
465 | {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, | |
6d8809aa RH |
466 | #ifdef OBJ_ELF |
467 | #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) | |
468 | {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, | |
a25fe906 ILT |
469 | #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) |
470 | {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, | |
6d8809aa | 471 | #endif |
6faf3d66 JJ |
472 | #define OPTION_RELAX (OPTION_MD_BASE + 14) |
473 | {"relax", no_argument, NULL, OPTION_RELAX}, | |
474 | #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) | |
475 | {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
46a2d504 JM |
476 | #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16) |
477 | {"dcti-couples-detect", no_argument, NULL, OPTION_DCTI_COUPLES_DETECT}, | |
252b5132 RH |
478 | {NULL, no_argument, NULL, 0} |
479 | }; | |
e0c6ed95 AM |
480 | |
481 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
482 | |
483 | int | |
17b9d67d | 484 | md_parse_option (int c, const char *arg) |
252b5132 RH |
485 | { |
486 | /* We don't get a chance to initialize anything before we're called, | |
487 | so handle that now. */ | |
488 | if (! default_init_p) | |
489 | init_default_arch (); | |
490 | ||
491 | switch (c) | |
492 | { | |
493 | case OPTION_BUMP: | |
494 | warn_on_bump = 1; | |
495 | warn_after_architecture = SPARC_OPCODE_ARCH_V6; | |
496 | break; | |
497 | ||
498 | case OPTION_XARCH: | |
c2158c24 | 499 | #ifdef OBJ_ELF |
668b27ea | 500 | if (!strncmp (arg, "v9", 2)) |
c2158c24 | 501 | md_parse_option (OPTION_64, NULL); |
668b27ea DM |
502 | else |
503 | { | |
504 | if (!strncmp (arg, "v8", 2) | |
505 | || !strncmp (arg, "v7", 2) | |
506 | || !strncmp (arg, "v6", 2) | |
507 | || !strcmp (arg, "sparclet") | |
508 | || !strcmp (arg, "sparclite") | |
509 | || !strcmp (arg, "sparc86x")) | |
510 | md_parse_option (OPTION_32, NULL); | |
511 | } | |
c2158c24 | 512 | #endif |
e0c6ed95 | 513 | /* Fall through. */ |
252b5132 RH |
514 | |
515 | case 'A': | |
516 | { | |
517 | struct sparc_arch *sa; | |
518 | enum sparc_opcode_arch_val opcode_arch; | |
519 | ||
520 | sa = lookup_arch (arg); | |
521 | if (sa == NULL | |
522 | || ! sa->user_option_p) | |
523 | { | |
c2158c24 JJ |
524 | if (c == OPTION_XARCH) |
525 | as_bad (_("invalid architecture -xarch=%s"), arg); | |
526 | else | |
527 | as_bad (_("invalid architecture -A%s"), arg); | |
252b5132 RH |
528 | return 0; |
529 | } | |
530 | ||
531 | opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); | |
532 | if (opcode_arch == SPARC_OPCODE_ARCH_BAD) | |
533 | as_fatal (_("Bad opcode table, broken assembler.")); | |
534 | ||
4bafe00e DM |
535 | if (!architecture_requested |
536 | || opcode_arch > max_architecture) | |
537 | max_architecture = opcode_arch; | |
6884417a JM |
538 | |
539 | /* The allowed hardware capabilities are the implied by the | |
540 | opcodes arch plus any extra capabilities defined in the GAS | |
541 | arch. */ | |
542 | hwcap_allowed | |
543 | = (hwcap_allowed | |
544 | | (((bfd_uint64_t) sparc_opcode_archs[opcode_arch].hwcaps2) << 32) | |
545 | | (((bfd_uint64_t) sa->hwcap2_allowed) << 32) | |
546 | | sparc_opcode_archs[opcode_arch].hwcaps | |
547 | | sa->hwcap_allowed); | |
252b5132 RH |
548 | architecture_requested = 1; |
549 | } | |
550 | break; | |
551 | ||
552 | case OPTION_SPARC: | |
553 | /* Ignore -sparc, used by SunOS make default .s.o rule. */ | |
554 | break; | |
555 | ||
556 | case OPTION_ENFORCE_ALIGNED_DATA: | |
557 | enforce_aligned_data = 1; | |
558 | break; | |
559 | ||
560 | #ifdef SPARC_BIENDIAN | |
561 | case OPTION_LITTLE_ENDIAN: | |
562 | target_big_endian = 0; | |
563 | if (default_arch_type != sparclet) | |
564 | as_fatal ("This target does not support -EL"); | |
565 | break; | |
566 | case OPTION_LITTLE_ENDIAN_DATA: | |
567 | target_little_endian_data = 1; | |
568 | target_big_endian = 0; | |
569 | if (default_arch_type != sparc86x | |
570 | && default_arch_type != v9) | |
571 | as_fatal ("This target does not support --little-endian-data"); | |
572 | break; | |
573 | case OPTION_BIG_ENDIAN: | |
574 | target_big_endian = 1; | |
575 | break; | |
576 | #endif | |
577 | ||
578 | #ifdef OBJ_AOUT | |
579 | case 'k': | |
580 | sparc_pic_code = 1; | |
581 | break; | |
582 | #endif | |
583 | ||
584 | #ifdef OBJ_ELF | |
585 | case OPTION_32: | |
586 | case OPTION_64: | |
587 | { | |
588 | const char **list, **l; | |
589 | ||
590 | sparc_arch_size = c == OPTION_32 ? 32 : 64; | |
591 | list = bfd_target_list (); | |
592 | for (l = list; *l != NULL; l++) | |
593 | { | |
594 | if (sparc_arch_size == 32) | |
595 | { | |
71a75f6f | 596 | if (CONST_STRNEQ (*l, "elf32-sparc")) |
252b5132 RH |
597 | break; |
598 | } | |
599 | else | |
600 | { | |
71a75f6f | 601 | if (CONST_STRNEQ (*l, "elf64-sparc")) |
252b5132 RH |
602 | break; |
603 | } | |
604 | } | |
605 | if (*l == NULL) | |
606 | as_fatal (_("No compiled in support for %d bit object file format"), | |
607 | sparc_arch_size); | |
608 | free (list); | |
b7cac25f DM |
609 | |
610 | if (sparc_arch_size == 64 | |
611 | && max_architecture < SPARC_OPCODE_ARCH_V9) | |
612 | max_architecture = SPARC_OPCODE_ARCH_V9; | |
252b5132 RH |
613 | } |
614 | break; | |
615 | ||
616 | case OPTION_TSO: | |
617 | sparc_memory_model = MM_TSO; | |
618 | break; | |
619 | ||
620 | case OPTION_PSO: | |
621 | sparc_memory_model = MM_PSO; | |
622 | break; | |
623 | ||
624 | case OPTION_RMO: | |
625 | sparc_memory_model = MM_RMO; | |
626 | break; | |
627 | ||
628 | case 'V': | |
629 | print_version_id (); | |
630 | break; | |
631 | ||
632 | case 'Q': | |
633 | /* Qy - do emit .comment | |
e0c6ed95 | 634 | Qn - do not emit .comment. */ |
252b5132 RH |
635 | break; |
636 | ||
637 | case 's': | |
e0c6ed95 | 638 | /* Use .stab instead of .stab.excl. */ |
252b5132 RH |
639 | break; |
640 | ||
641 | case 'q': | |
e0c6ed95 | 642 | /* quick -- Native assembler does fewer checks. */ |
252b5132 RH |
643 | break; |
644 | ||
645 | case 'K': | |
646 | if (strcmp (arg, "PIC") != 0) | |
647 | as_warn (_("Unrecognized option following -K")); | |
648 | else | |
649 | sparc_pic_code = 1; | |
650 | break; | |
6d8809aa RH |
651 | |
652 | case OPTION_NO_UNDECLARED_REGS: | |
653 | no_undeclared_regs = 1; | |
654 | break; | |
a25fe906 ILT |
655 | |
656 | case OPTION_UNDECLARED_REGS: | |
657 | no_undeclared_regs = 0; | |
658 | break; | |
252b5132 RH |
659 | #endif |
660 | ||
6faf3d66 JJ |
661 | case OPTION_RELAX: |
662 | sparc_relax = 1; | |
663 | break; | |
664 | ||
665 | case OPTION_NO_RELAX: | |
666 | sparc_relax = 0; | |
667 | break; | |
668 | ||
46a2d504 JM |
669 | case OPTION_DCTI_COUPLES_DETECT: |
670 | dcti_couples_detect = 1; | |
671 | break; | |
672 | ||
252b5132 RH |
673 | default: |
674 | return 0; | |
675 | } | |
676 | ||
677 | return 1; | |
678 | } | |
679 | ||
680 | void | |
5a49b8ac | 681 | md_show_usage (FILE *stream) |
252b5132 RH |
682 | { |
683 | const struct sparc_arch *arch; | |
c2158c24 | 684 | int column; |
252b5132 RH |
685 | |
686 | /* We don't get a chance to initialize anything before we're called, | |
687 | so handle that now. */ | |
688 | if (! default_init_p) | |
689 | init_default_arch (); | |
690 | ||
e0c6ed95 | 691 | fprintf (stream, _("SPARC options:\n")); |
c2158c24 | 692 | column = 0; |
252b5132 RH |
693 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
694 | { | |
c2158c24 JJ |
695 | if (!arch->user_option_p) |
696 | continue; | |
252b5132 RH |
697 | if (arch != &sparc_arch_table[0]) |
698 | fprintf (stream, " | "); | |
07726851 | 699 | if (column + strlen (arch->name) > 70) |
c2158c24 JJ |
700 | { |
701 | column = 0; | |
702 | fputc ('\n', stream); | |
703 | } | |
07726851 | 704 | column += 5 + 2 + strlen (arch->name); |
c2158c24 | 705 | fprintf (stream, "-A%s", arch->name); |
252b5132 | 706 | } |
c2158c24 JJ |
707 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
708 | { | |
709 | if (!arch->user_option_p) | |
710 | continue; | |
711 | fprintf (stream, " | "); | |
07726851 | 712 | if (column + strlen (arch->name) > 65) |
c2158c24 JJ |
713 | { |
714 | column = 0; | |
715 | fputc ('\n', stream); | |
716 | } | |
07726851 | 717 | column += 5 + 7 + strlen (arch->name); |
c2158c24 JJ |
718 | fprintf (stream, "-xarch=%s", arch->name); |
719 | } | |
720 | fprintf (stream, _("\n\ | |
252b5132 RH |
721 | specify variant of SPARC architecture\n\ |
722 | -bump warn when assembler switches architectures\n\ | |
723 | -sparc ignored\n\ | |
6faf3d66 JJ |
724 | --enforce-aligned-data force .long, etc., to be aligned correctly\n\ |
725 | -relax relax jumps and branches (default)\n\ | |
726 | -no-relax avoid changing any jumps and branches\n")); | |
252b5132 RH |
727 | #ifdef OBJ_AOUT |
728 | fprintf (stream, _("\ | |
729 | -k generate PIC\n")); | |
730 | #endif | |
731 | #ifdef OBJ_ELF | |
732 | fprintf (stream, _("\ | |
733 | -32 create 32 bit object file\n\ | |
734 | -64 create 64 bit object file\n")); | |
735 | fprintf (stream, _("\ | |
736 | [default is %d]\n"), default_arch_size); | |
737 | fprintf (stream, _("\ | |
738 | -TSO use Total Store Ordering\n\ | |
739 | -PSO use Partial Store Ordering\n\ | |
740 | -RMO use Relaxed Memory Ordering\n")); | |
741 | fprintf (stream, _("\ | |
742 | [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); | |
743 | fprintf (stream, _("\ | |
744 | -KPIC generate PIC\n\ | |
745 | -V print assembler version number\n\ | |
a25fe906 ILT |
746 | -undeclared-regs ignore application global register usage without\n\ |
747 | appropriate .register directive (default)\n\ | |
748 | -no-undeclared-regs force error on application global register usage\n\ | |
749 | without appropriate .register directive\n\ | |
46a2d504 | 750 | --dcti-couples-detect warn when an unpredictable DCTI couple is found\n\ |
252b5132 RH |
751 | -q ignored\n\ |
752 | -Qy, -Qn ignored\n\ | |
753 | -s ignored\n")); | |
754 | #endif | |
755 | #ifdef SPARC_BIENDIAN | |
756 | fprintf (stream, _("\ | |
757 | -EL generate code for a little endian machine\n\ | |
758 | -EB generate code for a big endian machine\n\ | |
759 | --little-endian-data generate code for a machine having big endian\n\ | |
c20f4f8c | 760 | instructions and little endian data.\n")); |
252b5132 RH |
761 | #endif |
762 | } | |
763 | \f | |
e0c6ed95 | 764 | /* Native operand size opcode translation. */ |
4f2a7b51 | 765 | static struct |
cf9a1301 | 766 | { |
e0471c16 TS |
767 | const char *name; |
768 | const char *name32; | |
769 | const char *name64; | |
cf9a1301 RH |
770 | } native_op_table[] = |
771 | { | |
772 | {"ldn", "ld", "ldx"}, | |
773 | {"ldna", "lda", "ldxa"}, | |
774 | {"stn", "st", "stx"}, | |
775 | {"stna", "sta", "stxa"}, | |
776 | {"slln", "sll", "sllx"}, | |
777 | {"srln", "srl", "srlx"}, | |
778 | {"sran", "sra", "srax"}, | |
779 | {"casn", "cas", "casx"}, | |
780 | {"casna", "casa", "casxa"}, | |
781 | {"clrn", "clr", "clrx"}, | |
782 | {NULL, NULL, NULL}, | |
783 | }; | |
784 | \f | |
10156f83 | 785 | /* sparc64 privileged and hyperprivileged registers. */ |
252b5132 RH |
786 | |
787 | struct priv_reg_entry | |
ab3e48dc | 788 | { |
e0471c16 | 789 | const char *name; |
ab3e48dc KH |
790 | int regnum; |
791 | }; | |
252b5132 RH |
792 | |
793 | struct priv_reg_entry priv_reg_table[] = | |
794 | { | |
795 | {"tpc", 0}, | |
796 | {"tnpc", 1}, | |
797 | {"tstate", 2}, | |
798 | {"tt", 3}, | |
799 | {"tick", 4}, | |
800 | {"tba", 5}, | |
801 | {"pstate", 6}, | |
802 | {"tl", 7}, | |
803 | {"pil", 8}, | |
804 | {"cwp", 9}, | |
805 | {"cansave", 10}, | |
806 | {"canrestore", 11}, | |
807 | {"cleanwin", 12}, | |
808 | {"otherwin", 13}, | |
809 | {"wstate", 14}, | |
810 | {"fq", 15}, | |
10156f83 | 811 | {"gl", 16}, |
38074311 | 812 | {"pmcdper", 23}, |
252b5132 | 813 | {"ver", 31}, |
8b8c7c9f | 814 | {NULL, -1}, /* End marker. */ |
252b5132 RH |
815 | }; |
816 | ||
10156f83 DM |
817 | struct priv_reg_entry hpriv_reg_table[] = |
818 | { | |
819 | {"hpstate", 0}, | |
820 | {"htstate", 1}, | |
821 | {"hintp", 3}, | |
822 | {"htba", 5}, | |
823 | {"hver", 6}, | |
96074adc JM |
824 | {"hmcdper", 23}, |
825 | {"hmcddfr", 24}, | |
826 | {"hva_mask_nz", 27}, | |
ec92c392 JM |
827 | {"hstick_offset", 28}, |
828 | {"hstick_enable", 29}, | |
10156f83 | 829 | {"hstick_cmpr", 31}, |
8b8c7c9f | 830 | {NULL, -1}, /* End marker. */ |
10156f83 DM |
831 | }; |
832 | ||
8b8c7c9f | 833 | /* v9a or later specific ancillary state registers. */ |
252b5132 RH |
834 | |
835 | struct priv_reg_entry v9a_asr_table[] = | |
836 | { | |
837 | {"tick_cmpr", 23}, | |
19f7b010 JJ |
838 | {"sys_tick_cmpr", 25}, |
839 | {"sys_tick", 24}, | |
1a6b486f DM |
840 | {"stick_cmpr", 25}, |
841 | {"stick", 24}, | |
f04d18b7 DM |
842 | {"softint_clear", 21}, |
843 | {"softint_set", 20}, | |
2b661f3d | 844 | {"softint", 22}, |
252b5132 | 845 | {"set_softint", 20}, |
58004e23 | 846 | {"pause", 27}, |
252b5132 RH |
847 | {"pic", 17}, |
848 | {"pcr", 16}, | |
3d68f91c | 849 | {"mwait", 28}, |
252b5132 RH |
850 | {"gsr", 19}, |
851 | {"dcr", 18}, | |
2e52845b | 852 | {"cfr", 26}, |
252b5132 | 853 | {"clear_softint", 21}, |
8b8c7c9f | 854 | {NULL, -1}, /* End marker. */ |
252b5132 RH |
855 | }; |
856 | ||
857 | static int | |
5a49b8ac | 858 | cmp_reg_entry (const void *parg, const void *qarg) |
252b5132 RH |
859 | { |
860 | const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; | |
861 | const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; | |
862 | ||
8b8c7c9f JM |
863 | if (p->name == q->name) |
864 | return 0; | |
865 | else if (p->name == NULL) | |
866 | return 1; | |
867 | else if (q->name == NULL) | |
868 | return -1; | |
869 | else | |
870 | return strcmp (q->name, p->name); | |
871 | } | |
872 | \f | |
873 | /* sparc %-pseudo-operations. */ | |
874 | ||
875 | ||
876 | #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */ | |
877 | #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative | |
878 | contexts. */ | |
879 | #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */ | |
880 | #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the | |
881 | last operand of an | |
882 | instruction. (Generally they can appear | |
883 | anywhere an immediate operand is | |
884 | expected. */ | |
885 | struct pop_entry | |
886 | { | |
887 | /* The name as it appears in assembler. */ | |
888 | const char *name; | |
889 | /* The reloc this pseudo-op translates to. */ | |
9bceab41 | 890 | bfd_reloc_code_real_type reloc; |
8b8c7c9f JM |
891 | /* Flags. See F_POP_* above. */ |
892 | int flags; | |
893 | }; | |
894 | ||
895 | struct pop_entry pop_table[] = | |
896 | { | |
897 | { "hix", BFD_RELOC_SPARC_HIX22, F_POP_V9 }, | |
898 | { "lox", BFD_RELOC_SPARC_LOX10, F_POP_V9 }, | |
899 | { "hi", BFD_RELOC_HI22, F_POP_PCREL }, | |
900 | { "lo", BFD_RELOC_LO10, F_POP_PCREL }, | |
901 | { "pc22", BFD_RELOC_SPARC_PC22, F_POP_PCREL }, | |
902 | { "pc10", BFD_RELOC_SPARC_PC10, F_POP_PCREL }, | |
903 | { "hh", BFD_RELOC_SPARC_HH22, F_POP_V9|F_POP_PCREL }, | |
904 | { "hm", BFD_RELOC_SPARC_HM10, F_POP_V9|F_POP_PCREL }, | |
905 | { "lm", BFD_RELOC_SPARC_LM22, F_POP_V9|F_POP_PCREL }, | |
906 | { "h34", BFD_RELOC_SPARC_H34, F_POP_V9 }, | |
907 | { "l34", BFD_RELOC_SPARC_L44, F_POP_V9 }, | |
908 | { "h44", BFD_RELOC_SPARC_H44, F_POP_V9 }, | |
909 | { "m44", BFD_RELOC_SPARC_M44, F_POP_V9 }, | |
910 | { "l44", BFD_RELOC_SPARC_L44, F_POP_V9 }, | |
911 | { "uhi", BFD_RELOC_SPARC_HH22, F_POP_V9 }, | |
912 | { "ulo", BFD_RELOC_SPARC_HM10, F_POP_V9 }, | |
913 | { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22, 0 }, | |
914 | { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10, 0 }, | |
915 | { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22, 0 }, | |
916 | { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10, 0 }, | |
917 | { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22, 0 }, | |
918 | { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10, 0 }, | |
919 | { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22, 0 }, | |
920 | { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10, 0 }, | |
921 | { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22, 0 }, | |
922 | { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10, 0 }, | |
923 | { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22, 0 }, | |
924 | { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10, 0 }, | |
925 | { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD, F_POP_POSTFIX }, | |
926 | { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, | |
927 | { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD, F_POP_POSTFIX }, | |
928 | { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, | |
929 | { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD, F_POP_POSTFIX }, | |
930 | { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX, F_POP_POSTFIX }, | |
931 | { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD, F_POP_POSTFIX }, | |
932 | { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD, F_POP_POSTFIX }, | |
cf80913a | 933 | { "gdop", BFD_RELOC_SPARC_GOTDATA_OP, F_POP_POSTFIX } |
8b8c7c9f JM |
934 | }; |
935 | \f | |
936 | /* Table of %-names that can appear in a sparc assembly program. This | |
937 | table is initialized in md_begin and contains entries for each | |
938 | privileged/hyperprivileged/alternate register and %-pseudo-op. */ | |
939 | ||
940 | enum perc_entry_type | |
941 | { | |
942 | perc_entry_none = 0, | |
943 | perc_entry_reg, | |
944 | perc_entry_post_pop, | |
945 | perc_entry_imm_pop | |
946 | }; | |
947 | ||
948 | struct perc_entry | |
949 | { | |
950 | /* Entry type. */ | |
951 | enum perc_entry_type type; | |
952 | /* Name of the %-entity. */ | |
953 | const char *name; | |
954 | /* strlen (name). */ | |
955 | int len; | |
956 | /* Value. Either a pop or a reg depending on type.*/ | |
957 | union | |
958 | { | |
959 | struct pop_entry *pop; | |
960 | struct priv_reg_entry *reg; | |
961 | }; | |
962 | }; | |
963 | ||
964 | #define NUM_PERC_ENTRIES \ | |
965 | (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \ | |
966 | + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \ | |
967 | + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \ | |
cf80913a | 968 | + ARRAY_SIZE (pop_table) \ |
8b8c7c9f JM |
969 | + 1) |
970 | ||
971 | struct perc_entry perc_table[NUM_PERC_ENTRIES]; | |
972 | ||
973 | static int | |
974 | cmp_perc_entry (const void *parg, const void *qarg) | |
975 | { | |
976 | const struct perc_entry *p = (const struct perc_entry *) parg; | |
977 | const struct perc_entry *q = (const struct perc_entry *) qarg; | |
978 | ||
979 | if (p->name == q->name) | |
980 | return 0; | |
981 | else if (p->name == NULL) | |
982 | return 1; | |
983 | else if (q->name == NULL) | |
984 | return -1; | |
985 | else | |
986 | return strcmp (q->name, p->name); | |
252b5132 RH |
987 | } |
988 | \f | |
989 | /* This function is called once, at assembler startup time. It should | |
e0c6ed95 AM |
990 | set up all the tables, etc. that the MD part of the assembler will |
991 | need. */ | |
252b5132 RH |
992 | |
993 | void | |
5a49b8ac | 994 | md_begin (void) |
252b5132 | 995 | { |
ed9e98c2 | 996 | const char *retval = NULL; |
252b5132 | 997 | int lose = 0; |
ed9e98c2 | 998 | unsigned int i = 0; |
252b5132 RH |
999 | |
1000 | /* We don't get a chance to initialize anything before md_parse_option | |
1001 | is called, and it may not be called, so handle default initialization | |
1002 | now if not already done. */ | |
1003 | if (! default_init_p) | |
1004 | init_default_arch (); | |
1005 | ||
364b6d8b | 1006 | sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; |
252b5132 RH |
1007 | op_hash = hash_new (); |
1008 | ||
1009 | while (i < (unsigned int) sparc_num_opcodes) | |
1010 | { | |
1011 | const char *name = sparc_opcodes[i].name; | |
5a49b8ac | 1012 | retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); |
252b5132 RH |
1013 | if (retval != NULL) |
1014 | { | |
cf9a1301 RH |
1015 | as_bad (_("Internal error: can't hash `%s': %s\n"), |
1016 | sparc_opcodes[i].name, retval); | |
252b5132 RH |
1017 | lose = 1; |
1018 | } | |
1019 | do | |
1020 | { | |
1021 | if (sparc_opcodes[i].match & sparc_opcodes[i].lose) | |
1022 | { | |
cf9a1301 RH |
1023 | as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), |
1024 | sparc_opcodes[i].name, sparc_opcodes[i].args); | |
252b5132 RH |
1025 | lose = 1; |
1026 | } | |
1027 | ++i; | |
1028 | } | |
1029 | while (i < (unsigned int) sparc_num_opcodes | |
1030 | && !strcmp (sparc_opcodes[i].name, name)); | |
1031 | } | |
1032 | ||
cf9a1301 RH |
1033 | for (i = 0; native_op_table[i].name; i++) |
1034 | { | |
1035 | const struct sparc_opcode *insn; | |
e0471c16 | 1036 | const char *name = ((sparc_arch_size == 32) |
3d4ae3c0 NC |
1037 | ? native_op_table[i].name32 |
1038 | : native_op_table[i].name64); | |
e0c6ed95 | 1039 | insn = (struct sparc_opcode *) hash_find (op_hash, name); |
cf9a1301 | 1040 | if (insn == NULL) |
e0c6ed95 AM |
1041 | { |
1042 | as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), | |
1043 | name, native_op_table[i].name); | |
1044 | lose = 1; | |
1045 | } | |
cf9a1301 RH |
1046 | else |
1047 | { | |
5a49b8ac AM |
1048 | retval = hash_insert (op_hash, native_op_table[i].name, |
1049 | (void *) insn); | |
cf9a1301 RH |
1050 | if (retval != NULL) |
1051 | { | |
1052 | as_bad (_("Internal error: can't hash `%s': %s\n"), | |
1053 | sparc_opcodes[i].name, retval); | |
1054 | lose = 1; | |
1055 | } | |
1056 | } | |
1057 | } | |
1058 | ||
252b5132 RH |
1059 | if (lose) |
1060 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1061 | ||
252b5132 RH |
1062 | qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), |
1063 | sizeof (priv_reg_table[0]), cmp_reg_entry); | |
8b8c7c9f JM |
1064 | qsort (hpriv_reg_table, sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0]), |
1065 | sizeof (hpriv_reg_table[0]), cmp_reg_entry); | |
1066 | qsort (v9a_asr_table, sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0]), | |
1067 | sizeof (v9a_asr_table[0]), cmp_reg_entry); | |
1068 | ||
252b5132 RH |
1069 | /* If -bump, record the architecture level at which we start issuing |
1070 | warnings. The behaviour is different depending upon whether an | |
1071 | architecture was explicitly specified. If it wasn't, we issue warnings | |
1072 | for all upwards bumps. If it was, we don't start issuing warnings until | |
1073 | we need to bump beyond the requested architecture or when we bump between | |
1074 | conflicting architectures. */ | |
1075 | ||
1076 | if (warn_on_bump | |
1077 | && architecture_requested) | |
1078 | { | |
1079 | /* `max_architecture' records the requested architecture. | |
1080 | Issue warnings if we go above it. */ | |
1081 | warn_after_architecture = max_architecture; | |
252b5132 | 1082 | } |
75ac3a7f JM |
1083 | |
1084 | /* Find the highest architecture level that doesn't conflict with | |
1085 | the requested one. */ | |
1086 | ||
1087 | if (warn_on_bump | |
1088 | || !architecture_requested) | |
1089 | { | |
1090 | enum sparc_opcode_arch_val current_max_architecture | |
1091 | = max_architecture; | |
1092 | ||
1093 | for (max_architecture = SPARC_OPCODE_ARCH_MAX; | |
1094 | max_architecture > warn_after_architecture; | |
1095 | --max_architecture) | |
1096 | if (! SPARC_OPCODE_CONFLICT_P (max_architecture, | |
1097 | current_max_architecture)) | |
1098 | break; | |
1099 | } | |
8b8c7c9f JM |
1100 | |
1101 | /* Prepare the tables of %-pseudo-ops. */ | |
1102 | { | |
1103 | struct priv_reg_entry *reg_tables[] | |
1104 | = {priv_reg_table, hpriv_reg_table, v9a_asr_table, NULL}; | |
1105 | struct priv_reg_entry **reg_table; | |
1106 | int entry = 0; | |
1107 | ||
1108 | /* Add registers. */ | |
1109 | for (reg_table = reg_tables; reg_table[0]; reg_table++) | |
1110 | { | |
1111 | struct priv_reg_entry *reg; | |
1112 | for (reg = *reg_table; reg->name; reg++) | |
1113 | { | |
1114 | struct perc_entry *p = &perc_table[entry++]; | |
1115 | p->type = perc_entry_reg; | |
1116 | p->name = reg->name; | |
1117 | p->len = strlen (reg->name); | |
1118 | p->reg = reg; | |
1119 | } | |
1120 | } | |
1121 | ||
1122 | /* Add %-pseudo-ops. */ | |
cf80913a TS |
1123 | for (i = 0; i < ARRAY_SIZE (pop_table); i++) |
1124 | { | |
1125 | struct perc_entry *p = &perc_table[entry++]; | |
1126 | p->type = (pop_table[i].flags & F_POP_POSTFIX | |
1127 | ? perc_entry_post_pop : perc_entry_imm_pop); | |
1128 | p->name = pop_table[i].name; | |
1129 | p->len = strlen (pop_table[i].name); | |
1130 | p->pop = &pop_table[i]; | |
1131 | } | |
8b8c7c9f JM |
1132 | |
1133 | /* Last entry is the centinel. */ | |
1134 | perc_table[entry].type = perc_entry_none; | |
1135 | ||
1136 | qsort (perc_table, sizeof (perc_table) / sizeof (perc_table[0]), | |
1137 | sizeof (perc_table[0]), cmp_perc_entry); | |
1138 | ||
1139 | } | |
252b5132 RH |
1140 | } |
1141 | ||
1142 | /* Called after all assembly has been done. */ | |
1143 | ||
1144 | void | |
5a49b8ac | 1145 | sparc_md_end (void) |
252b5132 | 1146 | { |
19f7b010 | 1147 | unsigned long mach = bfd_mach_sparc; |
daf5e10e | 1148 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) |
3d68f91c | 1149 | int hwcaps, hwcaps2; |
daf5e10e | 1150 | #endif |
19f7b010 | 1151 | |
252b5132 | 1152 | if (sparc_arch_size == 64) |
19f7b010 JJ |
1153 | switch (current_architecture) |
1154 | { | |
1155 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; | |
1156 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; | |
7a10c22f JM |
1157 | case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v9c; break; |
1158 | case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v9d; break; | |
1159 | case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v9e; break; | |
1160 | case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v9v; break; | |
1161 | case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v9m; break; | |
19f7b010 JJ |
1162 | default: mach = bfd_mach_sparc_v9; break; |
1163 | } | |
252b5132 | 1164 | else |
19f7b010 JJ |
1165 | switch (current_architecture) |
1166 | { | |
1167 | case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; | |
1168 | case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; | |
1169 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; | |
1170 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; | |
7a10c22f JM |
1171 | case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v8plusc; break; |
1172 | case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v8plusd; break; | |
1173 | case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v8pluse; break; | |
1174 | case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v8plusv; break; | |
1175 | case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v8plusm; break; | |
19f7b010 JJ |
1176 | /* The sparclite is treated like a normal sparc. Perhaps it shouldn't |
1177 | be but for now it is (since that's the way it's always been | |
1178 | treated). */ | |
1179 | default: break; | |
1180 | } | |
1181 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); | |
9e8c70f9 DM |
1182 | |
1183 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) | |
3d68f91c JM |
1184 | hwcaps = hwcap_seen & U0xffffffff; |
1185 | hwcaps2 = hwcap_seen >> 32; | |
1186 | ||
1187 | if (hwcaps) | |
1188 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcaps); | |
1189 | if (hwcaps2) | |
1190 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS2, hwcaps2); | |
9e8c70f9 | 1191 | #endif |
252b5132 RH |
1192 | } |
1193 | \f | |
1194 | /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ | |
1195 | ||
5a49b8ac AM |
1196 | static inline int |
1197 | in_signed_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
1198 | { |
1199 | if (max <= 0) | |
1200 | abort (); | |
1201 | /* Sign-extend the value from the architecture word size, so that | |
1202 | 0xffffffff is always considered -1 on sparc32. */ | |
1203 | if (sparc_arch_size == 32) | |
1204 | { | |
e0c6ed95 | 1205 | bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; |
6c1b24e4 | 1206 | val = ((val & U0xffffffff) ^ sign) - sign; |
252b5132 RH |
1207 | } |
1208 | if (val > max) | |
1209 | return 0; | |
1210 | if (val < ~max) | |
1211 | return 0; | |
1212 | return 1; | |
1213 | } | |
1214 | ||
1215 | /* Return non-zero if VAL is in the range 0 to MAX. */ | |
1216 | ||
5a49b8ac AM |
1217 | static inline int |
1218 | in_unsigned_range (bfd_vma val, bfd_vma max) | |
252b5132 RH |
1219 | { |
1220 | if (val > max) | |
1221 | return 0; | |
1222 | return 1; | |
1223 | } | |
1224 | ||
1225 | /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. | |
1226 | (e.g. -15 to +31). */ | |
1227 | ||
5a49b8ac AM |
1228 | static inline int |
1229 | in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
1230 | { |
1231 | if (max <= 0) | |
1232 | abort (); | |
1233 | if (val > max) | |
1234 | return 0; | |
1235 | if (val < ~(max >> 1)) | |
1236 | return 0; | |
1237 | return 1; | |
1238 | } | |
1239 | ||
1240 | static int | |
5a49b8ac | 1241 | sparc_ffs (unsigned int mask) |
252b5132 RH |
1242 | { |
1243 | int i; | |
1244 | ||
1245 | if (mask == 0) | |
1246 | return -1; | |
1247 | ||
1248 | for (i = 0; (mask & 1) == 0; ++i) | |
1249 | mask >>= 1; | |
1250 | return i; | |
1251 | } | |
1252 | ||
1253 | /* Implement big shift right. */ | |
1254 | static bfd_vma | |
5a49b8ac | 1255 | BSR (bfd_vma val, int amount) |
252b5132 RH |
1256 | { |
1257 | if (sizeof (bfd_vma) <= 4 && amount >= 32) | |
1258 | as_fatal (_("Support for 64-bit arithmetic not compiled in.")); | |
1259 | return val >> amount; | |
1260 | } | |
1261 | \f | |
1262 | /* For communication between sparc_ip and get_expression. */ | |
1263 | static char *expr_end; | |
1264 | ||
252b5132 | 1265 | /* Values for `special_case'. |
2b0f3761 | 1266 | Instructions that require weird handling because they're longer than |
252b5132 RH |
1267 | 4 bytes. */ |
1268 | #define SPECIAL_CASE_NONE 0 | |
1269 | #define SPECIAL_CASE_SET 1 | |
1270 | #define SPECIAL_CASE_SETSW 2 | |
1271 | #define SPECIAL_CASE_SETX 3 | |
1272 | /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ | |
1273 | #define SPECIAL_CASE_FDIV 4 | |
1274 | ||
1275 | /* Bit masks of various insns. */ | |
1276 | #define NOP_INSN 0x01000000 | |
1277 | #define OR_INSN 0x80100000 | |
63fab58c | 1278 | #define XOR_INSN 0x80180000 |
252b5132 RH |
1279 | #define FMOVS_INSN 0x81A00020 |
1280 | #define SETHI_INSN 0x01000000 | |
1281 | #define SLLX_INSN 0x81281000 | |
1282 | #define SRA_INSN 0x81380000 | |
1283 | ||
1284 | /* The last instruction to be assembled. */ | |
1285 | static const struct sparc_opcode *last_insn; | |
1286 | /* The assembled opcode of `last_insn'. */ | |
1287 | static unsigned long last_opcode; | |
1288 | \f | |
a22b281c | 1289 | /* Handle the set and setuw synthetic instructions. */ |
e0c6ed95 | 1290 | |
a22b281c | 1291 | static void |
5a49b8ac | 1292 | synthetize_setuw (const struct sparc_opcode *insn) |
a22b281c RH |
1293 | { |
1294 | int need_hi22_p = 0; | |
1295 | int rd = (the_insn.opcode & RD (~0)) >> 25; | |
1296 | ||
1297 | if (the_insn.exp.X_op == O_constant) | |
1298 | { | |
1299 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1300 | { | |
e0c6ed95 | 1301 | if (sizeof (offsetT) > 4 |
a22b281c | 1302 | && (the_insn.exp.X_add_number < 0 |
6c1b24e4 | 1303 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) |
a22b281c RH |
1304 | as_warn (_("set: number not in 0..4294967295 range")); |
1305 | } | |
1306 | else | |
1307 | { | |
e0c6ed95 | 1308 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1309 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1310 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c | 1311 | as_warn (_("set: number not in -2147483648..4294967295 range")); |
e0c6ed95 | 1312 | the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; |
a22b281c RH |
1313 | } |
1314 | } | |
1315 | ||
1316 | /* See if operand is absolute and small; skip sethi if so. */ | |
1317 | if (the_insn.exp.X_op != O_constant | |
1318 | || the_insn.exp.X_add_number >= (1 << 12) | |
1319 | || the_insn.exp.X_add_number < -(1 << 12)) | |
1320 | { | |
1321 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1322 | | ((the_insn.exp.X_add_number >> 10) | |
ab3e48dc KH |
1323 | & (the_insn.exp.X_op == O_constant |
1324 | ? 0x3fffff : 0))); | |
a22b281c | 1325 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1326 | ? BFD_RELOC_HI22 : BFD_RELOC_NONE); |
a22b281c RH |
1327 | output_insn (insn, &the_insn); |
1328 | need_hi22_p = 1; | |
1329 | } | |
1330 | ||
1331 | /* See if operand has no low-order bits; skip OR if so. */ | |
1332 | if (the_insn.exp.X_op != O_constant | |
1333 | || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) | |
1334 | || ! need_hi22_p) | |
1335 | { | |
1336 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) | |
1337 | | RD (rd) | IMMED | |
1338 | | (the_insn.exp.X_add_number | |
ab3e48dc KH |
1339 | & (the_insn.exp.X_op != O_constant |
1340 | ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); | |
a22b281c | 1341 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1342 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); |
a22b281c RH |
1343 | output_insn (insn, &the_insn); |
1344 | } | |
1345 | } | |
e0c6ed95 | 1346 | |
a22b281c | 1347 | /* Handle the setsw synthetic instruction. */ |
e0c6ed95 | 1348 | |
a22b281c | 1349 | static void |
5a49b8ac | 1350 | synthetize_setsw (const struct sparc_opcode *insn) |
a22b281c RH |
1351 | { |
1352 | int low32, rd, opc; | |
1353 | ||
1354 | rd = (the_insn.opcode & RD (~0)) >> 25; | |
1355 | ||
1356 | if (the_insn.exp.X_op != O_constant) | |
1357 | { | |
1358 | synthetize_setuw (insn); | |
1359 | ||
1360 | /* Need to sign extend it. */ | |
1361 | the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); | |
1362 | the_insn.reloc = BFD_RELOC_NONE; | |
1363 | output_insn (insn, &the_insn); | |
1364 | return; | |
1365 | } | |
1366 | ||
e0c6ed95 | 1367 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1368 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1369 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c RH |
1370 | as_warn (_("setsw: number not in -2147483648..4294967295 range")); |
1371 | ||
e0c6ed95 AM |
1372 | low32 = the_insn.exp.X_add_number; |
1373 | ||
a22b281c RH |
1374 | if (low32 >= 0) |
1375 | { | |
1376 | synthetize_setuw (insn); | |
1377 | return; | |
1378 | } | |
1379 | ||
1380 | opc = OR_INSN; | |
e0c6ed95 | 1381 | |
a22b281c RH |
1382 | the_insn.reloc = BFD_RELOC_NONE; |
1383 | /* See if operand is absolute and small; skip sethi if so. */ | |
1384 | if (low32 < -(1 << 12)) | |
1385 | { | |
1386 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1387 | | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); | |
1388 | output_insn (insn, &the_insn); | |
1389 | low32 = 0x1c00 | (low32 & 0x3ff); | |
1390 | opc = RS1 (rd) | XOR_INSN; | |
1391 | } | |
1392 | ||
1393 | the_insn.opcode = (opc | RD (rd) | IMMED | |
1394 | | (low32 & 0x1fff)); | |
1395 | output_insn (insn, &the_insn); | |
1396 | } | |
1397 | ||
0d495746 | 1398 | /* Handle the setx synthetic instruction. */ |
e0c6ed95 | 1399 | |
a22b281c | 1400 | static void |
5a49b8ac | 1401 | synthetize_setx (const struct sparc_opcode *insn) |
a22b281c RH |
1402 | { |
1403 | int upper32, lower32; | |
1404 | int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; | |
1405 | int dstreg = (the_insn.opcode & RD (~0)) >> 25; | |
1406 | int upper_dstreg; | |
1407 | int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; | |
1408 | int need_xor10_p = 0; | |
e0c6ed95 | 1409 | |
6c1b24e4 | 1410 | #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) |
a22b281c RH |
1411 | lower32 = SIGNEXT32 (the_insn.exp.X_add_number); |
1412 | upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); | |
1413 | #undef SIGNEXT32 | |
1414 | ||
1415 | upper_dstreg = tmpreg; | |
1416 | /* The tmp reg should not be the dst reg. */ | |
1417 | if (tmpreg == dstreg) | |
1418 | as_warn (_("setx: temporary register same as destination register")); | |
1419 | ||
1420 | /* ??? Obviously there are other optimizations we can do | |
1421 | (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be | |
1422 | doing some of these. Later. If you do change things, try to | |
1423 | change all of this to be table driven as well. */ | |
1424 | /* What to output depends on the number if it's constant. | |
1425 | Compute that first, then output what we've decided upon. */ | |
1426 | if (the_insn.exp.X_op != O_constant) | |
1427 | { | |
1428 | if (sparc_arch_size == 32) | |
1429 | { | |
1430 | /* When arch size is 32, we want setx to be equivalent | |
1431 | to setuw for anything but constants. */ | |
1432 | the_insn.exp.X_add_number &= 0xffffffff; | |
1433 | synthetize_setuw (insn); | |
1434 | return; | |
1435 | } | |
1436 | need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; | |
ab3e48dc KH |
1437 | lower32 = 0; |
1438 | upper32 = 0; | |
a22b281c RH |
1439 | } |
1440 | else | |
1441 | { | |
1442 | /* Reset X_add_number, we've extracted it as upper32/lower32. | |
1443 | Otherwise fixup_segment will complain about not being able to | |
1444 | write an 8 byte number in a 4 byte field. */ | |
1445 | the_insn.exp.X_add_number = 0; | |
e0c6ed95 | 1446 | |
a22b281c RH |
1447 | /* Only need hh22 if `or' insn can't handle constant. */ |
1448 | if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) | |
1449 | need_hh22_p = 1; | |
e0c6ed95 | 1450 | |
a22b281c RH |
1451 | /* Does bottom part (after sethi) have bits? */ |
1452 | if ((need_hh22_p && (upper32 & 0x3ff) != 0) | |
1453 | /* No hh22, but does upper32 still have bits we can't set | |
1454 | from lower32? */ | |
1455 | || (! need_hh22_p && upper32 != 0 && upper32 != -1)) | |
1456 | need_hm10_p = 1; | |
e0c6ed95 | 1457 | |
a22b281c RH |
1458 | /* If the lower half is all zero, we build the upper half directly |
1459 | into the dst reg. */ | |
1460 | if (lower32 != 0 | |
1461 | /* Need lower half if number is zero or 0xffffffff00000000. */ | |
1462 | || (! need_hh22_p && ! need_hm10_p)) | |
1463 | { | |
1464 | /* No need for sethi if `or' insn can handle constant. */ | |
1465 | if (lower32 < -(1 << 12) || lower32 >= (1 << 12) | |
1466 | /* Note that we can't use a negative constant in the `or' | |
1467 | insn unless the upper 32 bits are all ones. */ | |
1468 | || (lower32 < 0 && upper32 != -1) | |
1469 | || (lower32 >= 0 && upper32 == -1)) | |
1470 | need_hi22_p = 1; | |
e0c6ed95 | 1471 | |
a22b281c RH |
1472 | if (need_hi22_p && upper32 == -1) |
1473 | need_xor10_p = 1; | |
1474 | ||
1475 | /* Does bottom part (after sethi) have bits? */ | |
1476 | else if ((need_hi22_p && (lower32 & 0x3ff) != 0) | |
1477 | /* No sethi. */ | |
1478 | || (! need_hi22_p && (lower32 & 0x1fff) != 0) | |
1479 | /* Need `or' if we didn't set anything else. */ | |
1480 | || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) | |
1481 | need_lo10_p = 1; | |
1482 | } | |
1483 | else | |
1484 | /* Output directly to dst reg if lower 32 bits are all zero. */ | |
1485 | upper_dstreg = dstreg; | |
1486 | } | |
e0c6ed95 | 1487 | |
a22b281c RH |
1488 | if (!upper_dstreg && dstreg) |
1489 | as_warn (_("setx: illegal temporary register g0")); | |
1490 | ||
1491 | if (need_hh22_p) | |
1492 | { | |
1493 | the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) | |
1494 | | ((upper32 >> 10) & 0x3fffff)); | |
1495 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1496 | ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); | |
1497 | output_insn (insn, &the_insn); | |
1498 | } | |
e0c6ed95 | 1499 | |
a22b281c RH |
1500 | if (need_hi22_p) |
1501 | { | |
1502 | the_insn.opcode = (SETHI_INSN | RD (dstreg) | |
1503 | | (((need_xor10_p ? ~lower32 : lower32) | |
ab3e48dc | 1504 | >> 10) & 0x3fffff)); |
a22b281c RH |
1505 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
1506 | ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); | |
1507 | output_insn (insn, &the_insn); | |
1508 | } | |
1509 | ||
1510 | if (need_hm10_p) | |
1511 | { | |
1512 | the_insn.opcode = (OR_INSN | |
1513 | | (need_hh22_p ? RS1 (upper_dstreg) : 0) | |
1514 | | RD (upper_dstreg) | |
1515 | | IMMED | |
1516 | | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); | |
1517 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1518 | ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); | |
1519 | output_insn (insn, &the_insn); | |
1520 | } | |
e0c6ed95 | 1521 | |
a22b281c RH |
1522 | if (need_lo10_p) |
1523 | { | |
1524 | /* FIXME: One nice optimization to do here is to OR the low part | |
1525 | with the highpart if hi22 isn't needed and the low part is | |
1526 | positive. */ | |
1527 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) | |
1528 | | RD (dstreg) | |
1529 | | IMMED | |
1530 | | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); | |
1531 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1532 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); | |
1533 | output_insn (insn, &the_insn); | |
1534 | } | |
e0c6ed95 | 1535 | |
a22b281c RH |
1536 | /* If we needed to build the upper part, shift it into place. */ |
1537 | if (need_hh22_p || need_hm10_p) | |
1538 | { | |
1539 | the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) | |
1540 | | IMMED | 32); | |
1541 | the_insn.reloc = BFD_RELOC_NONE; | |
1542 | output_insn (insn, &the_insn); | |
1543 | } | |
e0c6ed95 | 1544 | |
a22b281c RH |
1545 | /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ |
1546 | if (need_xor10_p) | |
1547 | { | |
1548 | the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED | |
1549 | | 0x1c00 | (lower32 & 0x3ff)); | |
1550 | the_insn.reloc = BFD_RELOC_NONE; | |
1551 | output_insn (insn, &the_insn); | |
1552 | } | |
1553 | ||
1554 | /* If we needed to build both upper and lower parts, OR them together. */ | |
1555 | else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) | |
1556 | { | |
1557 | the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) | |
1558 | | RD (dstreg)); | |
1559 | the_insn.reloc = BFD_RELOC_NONE; | |
1560 | output_insn (insn, &the_insn); | |
1561 | } | |
1562 | } | |
1563 | \f | |
252b5132 RH |
1564 | /* Main entry point to assemble one instruction. */ |
1565 | ||
1566 | void | |
5a49b8ac | 1567 | md_assemble (char *str) |
252b5132 RH |
1568 | { |
1569 | const struct sparc_opcode *insn; | |
a22b281c | 1570 | int special_case; |
252b5132 RH |
1571 | |
1572 | know (str); | |
a22b281c | 1573 | special_case = sparc_ip (str, &insn); |
b0825cc2 DM |
1574 | if (insn == NULL) |
1575 | return; | |
252b5132 | 1576 | |
46a2d504 JM |
1577 | /* Certain instructions may not appear on delay slots. Check for |
1578 | these situations. */ | |
b0825cc2 | 1579 | if (last_insn != NULL |
46a2d504 JM |
1580 | && (last_insn->flags & F_DELAYED) != 0) |
1581 | { | |
1582 | /* Before SPARC V9 the effect of having a delayed branch | |
1583 | instruction in the delay slot of a conditional delayed branch | |
1584 | was undefined. | |
1585 | ||
1586 | In SPARC V9 DCTI couples are well defined. | |
1587 | ||
1588 | However, starting with the UltraSPARC Architecture 2005, DCTI | |
1589 | couples (of all kind) are deprecated and should not be used, | |
1590 | as they may be slow or behave differently to what the | |
1591 | programmer expects. */ | |
1592 | if (dcti_couples_detect | |
1593 | && (insn->flags & F_DELAYED) != 0 | |
1594 | && ((max_architecture < SPARC_OPCODE_ARCH_V9 | |
1595 | && (last_insn->flags & F_CONDBR) != 0) | |
1596 | || max_architecture >= SPARC_OPCODE_ARCH_V9C)) | |
1597 | as_warn (_("unpredictable DCTI couple")); | |
1598 | ||
1599 | ||
1600 | /* We warn about attempts to put a floating point branch in a | |
1601 | delay slot, unless the delay slot has been annulled. */ | |
1602 | if ((insn->flags & F_FBR) != 0 | |
1603 | /* ??? This test isn't completely accurate. We assume anything with | |
1604 | F_{UNBR,CONDBR,FBR} set is annullable. */ | |
1605 | && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 | |
1606 | || (last_opcode & ANNUL) == 0)) | |
1607 | as_warn (_("FP branch in delay slot")); | |
1608 | } | |
252b5132 RH |
1609 | |
1610 | /* SPARC before v9 requires a nop instruction between a floating | |
1611 | point instruction and a floating point branch. We insert one | |
1612 | automatically, with a warning. */ | |
1613 | if (max_architecture < SPARC_OPCODE_ARCH_V9 | |
252b5132 RH |
1614 | && last_insn != NULL |
1615 | && (insn->flags & F_FBR) != 0 | |
1616 | && (last_insn->flags & F_FLOAT) != 0) | |
1617 | { | |
1618 | struct sparc_it nop_insn; | |
1619 | ||
1620 | nop_insn.opcode = NOP_INSN; | |
1621 | nop_insn.reloc = BFD_RELOC_NONE; | |
1622 | output_insn (insn, &nop_insn); | |
1623 | as_warn (_("FP branch preceded by FP instruction; NOP inserted")); | |
1624 | } | |
1625 | ||
a22b281c RH |
1626 | switch (special_case) |
1627 | { | |
1628 | case SPECIAL_CASE_NONE: | |
e0c6ed95 | 1629 | /* Normal insn. */ |
a22b281c RH |
1630 | output_insn (insn, &the_insn); |
1631 | break; | |
252b5132 | 1632 | |
a22b281c RH |
1633 | case SPECIAL_CASE_SETSW: |
1634 | synthetize_setsw (insn); | |
1635 | break; | |
e0c6ed95 | 1636 | |
a22b281c RH |
1637 | case SPECIAL_CASE_SET: |
1638 | synthetize_setuw (insn); | |
1639 | break; | |
252b5132 | 1640 | |
a22b281c RH |
1641 | case SPECIAL_CASE_SETX: |
1642 | synthetize_setx (insn); | |
1643 | break; | |
e0c6ed95 | 1644 | |
a22b281c RH |
1645 | case SPECIAL_CASE_FDIV: |
1646 | { | |
1647 | int rd = (the_insn.opcode >> 25) & 0x1f; | |
e0c6ed95 | 1648 | |
a22b281c | 1649 | output_insn (insn, &the_insn); |
e0c6ed95 | 1650 | |
a22b281c RH |
1651 | /* According to information leaked from Sun, the "fdiv" instructions |
1652 | on early SPARC machines would produce incorrect results sometimes. | |
1653 | The workaround is to add an fmovs of the destination register to | |
1654 | itself just after the instruction. This was true on machines | |
e0c6ed95 | 1655 | with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ |
9c2799c2 | 1656 | gas_assert (the_insn.reloc == BFD_RELOC_NONE); |
a22b281c RH |
1657 | the_insn.opcode = FMOVS_INSN | rd | RD (rd); |
1658 | output_insn (insn, &the_insn); | |
1659 | return; | |
1660 | } | |
e0c6ed95 | 1661 | |
a22b281c RH |
1662 | default: |
1663 | as_fatal (_("failed special case insn sanity check")); | |
252b5132 RH |
1664 | } |
1665 | } | |
1666 | ||
4bafe00e | 1667 | static const char * |
3d68f91c | 1668 | get_hwcap_name (bfd_uint64_t mask) |
4bafe00e | 1669 | { |
ec668d69 | 1670 | if (mask & HWCAP_MUL32) |
4bafe00e | 1671 | return "mul32"; |
ec668d69 | 1672 | if (mask & HWCAP_DIV32) |
4bafe00e | 1673 | return "div32"; |
ec668d69 | 1674 | if (mask & HWCAP_FSMULD) |
4bafe00e | 1675 | return "fsmuld"; |
ec668d69 | 1676 | if (mask & HWCAP_V8PLUS) |
4bafe00e | 1677 | return "v8plus"; |
ec668d69 | 1678 | if (mask & HWCAP_POPC) |
4bafe00e | 1679 | return "popc"; |
ec668d69 | 1680 | if (mask & HWCAP_VIS) |
4bafe00e | 1681 | return "vis"; |
ec668d69 | 1682 | if (mask & HWCAP_VIS2) |
4bafe00e | 1683 | return "vis2"; |
ec668d69 | 1684 | if (mask & HWCAP_ASI_BLK_INIT) |
4bafe00e | 1685 | return "ASIBlkInit"; |
ec668d69 | 1686 | if (mask & HWCAP_FMAF) |
4bafe00e | 1687 | return "fmaf"; |
ec668d69 | 1688 | if (mask & HWCAP_VIS3) |
4bafe00e | 1689 | return "vis3"; |
ec668d69 | 1690 | if (mask & HWCAP_HPC) |
4bafe00e | 1691 | return "hpc"; |
ec668d69 | 1692 | if (mask & HWCAP_RANDOM) |
4bafe00e | 1693 | return "random"; |
ec668d69 | 1694 | if (mask & HWCAP_TRANS) |
4bafe00e | 1695 | return "trans"; |
ec668d69 | 1696 | if (mask & HWCAP_FJFMAU) |
4bafe00e | 1697 | return "fjfmau"; |
ec668d69 | 1698 | if (mask & HWCAP_IMA) |
4bafe00e | 1699 | return "ima"; |
ec668d69 | 1700 | if (mask & HWCAP_ASI_CACHE_SPARING) |
4bafe00e | 1701 | return "cspare"; |
ec668d69 DM |
1702 | if (mask & HWCAP_AES) |
1703 | return "aes"; | |
1704 | if (mask & HWCAP_DES) | |
1705 | return "des"; | |
1706 | if (mask & HWCAP_KASUMI) | |
1707 | return "kasumi"; | |
1708 | if (mask & HWCAP_CAMELLIA) | |
1709 | return "camellia"; | |
1710 | if (mask & HWCAP_MD5) | |
1711 | return "md5"; | |
1712 | if (mask & HWCAP_SHA1) | |
1713 | return "sha1"; | |
1714 | if (mask & HWCAP_SHA256) | |
1715 | return "sha256"; | |
1716 | if (mask & HWCAP_SHA512) | |
1717 | return "sha512"; | |
1718 | if (mask & HWCAP_MPMUL) | |
1719 | return "mpmul"; | |
1720 | if (mask & HWCAP_MONT) | |
1721 | return "mont"; | |
1722 | if (mask & HWCAP_PAUSE) | |
1723 | return "pause"; | |
1724 | if (mask & HWCAP_CBCOND) | |
1725 | return "cbcond"; | |
1726 | if (mask & HWCAP_CRC32C) | |
1727 | return "crc32c"; | |
3d68f91c JM |
1728 | |
1729 | mask = mask >> 32; | |
1730 | if (mask & HWCAP2_FJATHPLUS) | |
1731 | return "fjathplus"; | |
1732 | if (mask & HWCAP2_VIS3B) | |
1733 | return "vis3b"; | |
1734 | if (mask & HWCAP2_ADP) | |
1735 | return "adp"; | |
1736 | if (mask & HWCAP2_SPARC5) | |
1737 | return "sparc5"; | |
1738 | if (mask & HWCAP2_MWAIT) | |
1739 | return "mwait"; | |
1740 | if (mask & HWCAP2_XMPMUL) | |
1741 | return "xmpmul"; | |
1742 | if (mask & HWCAP2_XMONT) | |
1743 | return "xmont"; | |
1744 | if (mask & HWCAP2_NSEC) | |
1745 | return "nsec"; | |
1746 | ||
4bafe00e DM |
1747 | return "UNKNOWN"; |
1748 | } | |
1749 | ||
252b5132 RH |
1750 | /* Subroutine of md_assemble to do the actual parsing. */ |
1751 | ||
a22b281c | 1752 | static int |
5a49b8ac | 1753 | sparc_ip (char *str, const struct sparc_opcode **pinsn) |
252b5132 | 1754 | { |
e0471c16 | 1755 | const char *error_message = ""; |
252b5132 RH |
1756 | char *s; |
1757 | const char *args; | |
1758 | char c; | |
1759 | const struct sparc_opcode *insn; | |
1760 | char *argsStart; | |
1761 | unsigned long opcode; | |
1762 | unsigned int mask = 0; | |
1763 | int match = 0; | |
1764 | int comma = 0; | |
1765 | int v9_arg_p; | |
a22b281c | 1766 | int special_case = SPECIAL_CASE_NONE; |
252b5132 RH |
1767 | |
1768 | s = str; | |
3882b010 | 1769 | if (ISLOWER (*s)) |
252b5132 RH |
1770 | { |
1771 | do | |
1772 | ++s; | |
6cda1326 | 1773 | while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_'); |
252b5132 RH |
1774 | } |
1775 | ||
1776 | switch (*s) | |
1777 | { | |
1778 | case '\0': | |
1779 | break; | |
1780 | ||
1781 | case ',': | |
1782 | comma = 1; | |
e0c6ed95 | 1783 | /* Fall through. */ |
252b5132 RH |
1784 | |
1785 | case ' ': | |
1786 | *s++ = '\0'; | |
1787 | break; | |
1788 | ||
1789 | default: | |
b0825cc2 DM |
1790 | as_bad (_("Unknown opcode: `%s'"), str); |
1791 | *pinsn = NULL; | |
1792 | return special_case; | |
252b5132 RH |
1793 | } |
1794 | insn = (struct sparc_opcode *) hash_find (op_hash, str); | |
1795 | *pinsn = insn; | |
1796 | if (insn == NULL) | |
1797 | { | |
1798 | as_bad (_("Unknown opcode: `%s'"), str); | |
a22b281c | 1799 | return special_case; |
252b5132 RH |
1800 | } |
1801 | if (comma) | |
1802 | { | |
1803 | *--s = ','; | |
1804 | } | |
1805 | ||
1806 | argsStart = s; | |
1807 | for (;;) | |
1808 | { | |
1809 | opcode = insn->match; | |
1810 | memset (&the_insn, '\0', sizeof (the_insn)); | |
1811 | the_insn.reloc = BFD_RELOC_NONE; | |
1812 | v9_arg_p = 0; | |
1813 | ||
e0c6ed95 AM |
1814 | /* Build the opcode, checking as we go to make sure that the |
1815 | operands match. */ | |
252b5132 RH |
1816 | for (args = insn->args;; ++args) |
1817 | { | |
1818 | switch (*args) | |
1819 | { | |
1820 | case 'K': | |
1821 | { | |
1822 | int kmask = 0; | |
1823 | ||
1824 | /* Parse a series of masks. */ | |
1825 | if (*s == '#') | |
1826 | { | |
1827 | while (*s == '#') | |
1828 | { | |
91d6fa6a | 1829 | int jmask; |
252b5132 RH |
1830 | |
1831 | if (! parse_keyword_arg (sparc_encode_membar, &s, | |
91d6fa6a | 1832 | &jmask)) |
252b5132 RH |
1833 | { |
1834 | error_message = _(": invalid membar mask name"); | |
1835 | goto error; | |
1836 | } | |
91d6fa6a | 1837 | kmask |= jmask; |
47926f60 KH |
1838 | while (*s == ' ') |
1839 | ++s; | |
252b5132 RH |
1840 | if (*s == '|' || *s == '+') |
1841 | ++s; | |
47926f60 KH |
1842 | while (*s == ' ') |
1843 | ++s; | |
252b5132 RH |
1844 | } |
1845 | } | |
1846 | else | |
1847 | { | |
1848 | if (! parse_const_expr_arg (&s, &kmask)) | |
1849 | { | |
1850 | error_message = _(": invalid membar mask expression"); | |
1851 | goto error; | |
1852 | } | |
1853 | if (kmask < 0 || kmask > 127) | |
1854 | { | |
1855 | error_message = _(": invalid membar mask number"); | |
1856 | goto error; | |
1857 | } | |
1858 | } | |
1859 | ||
1860 | opcode |= MEMBAR (kmask); | |
1861 | continue; | |
1862 | } | |
1863 | ||
19f7b010 JJ |
1864 | case '3': |
1865 | { | |
1866 | int smask = 0; | |
1867 | ||
1868 | if (! parse_const_expr_arg (&s, &smask)) | |
1869 | { | |
1870 | error_message = _(": invalid siam mode expression"); | |
1871 | goto error; | |
1872 | } | |
1873 | if (smask < 0 || smask > 7) | |
1874 | { | |
1875 | error_message = _(": invalid siam mode number"); | |
1876 | goto error; | |
1877 | } | |
1878 | opcode |= smask; | |
1879 | continue; | |
1880 | } | |
1881 | ||
252b5132 RH |
1882 | case '*': |
1883 | { | |
1884 | int fcn = 0; | |
1885 | ||
1886 | /* Parse a prefetch function. */ | |
1887 | if (*s == '#') | |
1888 | { | |
1889 | if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) | |
1890 | { | |
1891 | error_message = _(": invalid prefetch function name"); | |
1892 | goto error; | |
1893 | } | |
1894 | } | |
1895 | else | |
1896 | { | |
1897 | if (! parse_const_expr_arg (&s, &fcn)) | |
1898 | { | |
1899 | error_message = _(": invalid prefetch function expression"); | |
1900 | goto error; | |
1901 | } | |
1902 | if (fcn < 0 || fcn > 31) | |
1903 | { | |
1904 | error_message = _(": invalid prefetch function number"); | |
1905 | goto error; | |
1906 | } | |
1907 | } | |
1908 | opcode |= RD (fcn); | |
1909 | continue; | |
1910 | } | |
1911 | ||
1912 | case '!': | |
1913 | case '?': | |
1914 | /* Parse a sparc64 privileged register. */ | |
1915 | if (*s == '%') | |
1916 | { | |
8b8c7c9f | 1917 | struct priv_reg_entry *p; |
e0c6ed95 | 1918 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1919 | |
1920 | s += 1; | |
8b8c7c9f JM |
1921 | for (p = priv_reg_table; p->name; p++) |
1922 | if (p->name[0] == s[0]) | |
1923 | { | |
1924 | len = strlen (p->name); | |
1925 | if (strncmp (p->name, s, len) == 0) | |
1926 | break; | |
1927 | } | |
1928 | ||
1929 | if (!p->name) | |
252b5132 RH |
1930 | { |
1931 | error_message = _(": unrecognizable privileged register"); | |
1932 | goto error; | |
1933 | } | |
96074adc JM |
1934 | |
1935 | if (((opcode >> (*args == '?' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) | |
1936 | { | |
1937 | error_message = _(": unrecognizable privileged register"); | |
1938 | goto error; | |
1939 | } | |
1940 | ||
252b5132 RH |
1941 | s += len; |
1942 | continue; | |
1943 | } | |
1944 | else | |
1945 | { | |
1946 | error_message = _(": unrecognizable privileged register"); | |
1947 | goto error; | |
1948 | } | |
1949 | ||
10156f83 DM |
1950 | case '$': |
1951 | case '%': | |
1952 | /* Parse a sparc64 hyperprivileged register. */ | |
1953 | if (*s == '%') | |
1954 | { | |
8b8c7c9f | 1955 | struct priv_reg_entry *p; |
10156f83 DM |
1956 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
1957 | ||
1958 | s += 1; | |
8b8c7c9f JM |
1959 | for (p = hpriv_reg_table; p->name; p++) |
1960 | if (p->name[0] == s[0]) | |
1961 | { | |
1962 | len = strlen (p->name); | |
1963 | if (strncmp (p->name, s, len) == 0) | |
1964 | break; | |
1965 | } | |
1966 | ||
1967 | if (!p->name) | |
10156f83 DM |
1968 | { |
1969 | error_message = _(": unrecognizable hyperprivileged register"); | |
1970 | goto error; | |
1971 | } | |
96074adc JM |
1972 | |
1973 | if (((opcode >> (*args == '$' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) | |
1974 | { | |
1975 | error_message = _(": unrecognizable hyperprivileged register"); | |
1976 | goto error; | |
1977 | } | |
1978 | ||
1979 | s += len; | |
10156f83 DM |
1980 | continue; |
1981 | } | |
1982 | else | |
1983 | { | |
1984 | error_message = _(": unrecognizable hyperprivileged register"); | |
1985 | goto error; | |
1986 | } | |
1987 | ||
252b5132 RH |
1988 | case '_': |
1989 | case '/': | |
7a10c22f | 1990 | /* Parse a v9a or later ancillary state register. */ |
252b5132 RH |
1991 | if (*s == '%') |
1992 | { | |
8b8c7c9f | 1993 | struct priv_reg_entry *p; |
e0c6ed95 | 1994 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1995 | |
1996 | s += 1; | |
8b8c7c9f JM |
1997 | for (p = v9a_asr_table; p->name; p++) |
1998 | if (p->name[0] == s[0]) | |
1999 | { | |
2000 | len = strlen (p->name); | |
2001 | if (strncmp (p->name, s, len) == 0) | |
2002 | break; | |
2003 | } | |
2004 | ||
2005 | if (!p->name) | |
252b5132 | 2006 | { |
7a10c22f | 2007 | error_message = _(": unrecognizable ancillary state register"); |
252b5132 RH |
2008 | goto error; |
2009 | } | |
96074adc JM |
2010 | |
2011 | if (((opcode >> (*args == '/' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) | |
2012 | { | |
2013 | error_message = _(": unrecognizable ancillary state register"); | |
2014 | goto error; | |
2015 | } | |
2016 | ||
252b5132 RH |
2017 | s += len; |
2018 | continue; | |
2019 | } | |
2020 | else | |
2021 | { | |
7a10c22f | 2022 | error_message = _(": unrecognizable ancillary state register"); |
252b5132 RH |
2023 | goto error; |
2024 | } | |
2025 | ||
2026 | case 'M': | |
2027 | case 'm': | |
2028 | if (strncmp (s, "%asr", 4) == 0) | |
2029 | { | |
2030 | s += 4; | |
2031 | ||
3882b010 | 2032 | if (ISDIGIT (*s)) |
252b5132 RH |
2033 | { |
2034 | long num = 0; | |
2035 | ||
3882b010 | 2036 | while (ISDIGIT (*s)) |
252b5132 RH |
2037 | { |
2038 | num = num * 10 + *s - '0'; | |
2039 | ++s; | |
2040 | } | |
2041 | ||
f65c3d1b JM |
2042 | /* We used to check here for the asr number to |
2043 | be between 16 and 31 in V9 and later, as | |
2044 | mandated by the section C.1.1 "Register | |
2045 | Names" in the SPARC spec. However, we | |
2046 | decided to remove this restriction as a) it | |
2047 | introduces problems when new V9 asr registers | |
2048 | are introduced, b) the Solaris assembler | |
2049 | doesn't implement this restriction and c) the | |
2050 | restriction will go away in future revisions | |
2051 | of the Oracle SPARC Architecture. */ | |
2052 | ||
2053 | if (num < 0 || 31 < num) | |
2054 | { | |
2055 | error_message = _(": asr number must be between 0 and 31"); | |
2056 | goto error; | |
2057 | } | |
252b5132 RH |
2058 | |
2059 | opcode |= (*args == 'M' ? RS1 (num) : RD (num)); | |
2060 | continue; | |
2061 | } | |
2062 | else | |
2063 | { | |
2064 | error_message = _(": expecting %asrN"); | |
2065 | goto error; | |
2066 | } | |
e0c6ed95 | 2067 | } /* if %asr */ |
252b5132 RH |
2068 | break; |
2069 | ||
2070 | case 'I': | |
2071 | the_insn.reloc = BFD_RELOC_SPARC_11; | |
2072 | goto immediate; | |
2073 | ||
2074 | case 'j': | |
2075 | the_insn.reloc = BFD_RELOC_SPARC_10; | |
2076 | goto immediate; | |
2077 | ||
6cda1326 DM |
2078 | case ')': |
2079 | if (*s == ' ') | |
2080 | s++; | |
2081 | if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2])) | |
2082 | || ISDIGIT (*s)) | |
2083 | { | |
2084 | long num = 0; | |
2085 | ||
2086 | if (s[0] == '0' && s[1] == 'x') | |
2087 | { | |
2088 | s += 2; | |
2089 | while (ISXDIGIT (*s)) | |
2090 | { | |
2091 | num <<= 4; | |
2092 | num |= hex_value (*s); | |
2093 | ++s; | |
2094 | } | |
2095 | } | |
2096 | else | |
2097 | { | |
2098 | while (ISDIGIT (*s)) | |
2099 | { | |
2100 | num = num * 10 + *s - '0'; | |
2101 | ++s; | |
2102 | } | |
2103 | } | |
2104 | if (num < 0 || num > 31) | |
2105 | { | |
2106 | error_message = _(": crypto immediate must be between 0 and 31"); | |
2107 | goto error; | |
2108 | } | |
2109 | ||
2110 | opcode |= RS3 (num); | |
2111 | continue; | |
2112 | } | |
2113 | else | |
2114 | { | |
2115 | error_message = _(": expecting crypto immediate"); | |
2116 | goto error; | |
2117 | } | |
2118 | ||
252b5132 RH |
2119 | case 'X': |
2120 | /* V8 systems don't understand BFD_RELOC_SPARC_5. */ | |
2121 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2122 | the_insn.reloc = BFD_RELOC_SPARC_5; | |
2123 | else | |
2124 | the_insn.reloc = BFD_RELOC_SPARC13; | |
2125 | /* These fields are unsigned, but for upward compatibility, | |
2126 | allow negative values as well. */ | |
2127 | goto immediate; | |
2128 | ||
2129 | case 'Y': | |
2130 | /* V8 systems don't understand BFD_RELOC_SPARC_6. */ | |
2131 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2132 | the_insn.reloc = BFD_RELOC_SPARC_6; | |
2133 | else | |
2134 | the_insn.reloc = BFD_RELOC_SPARC13; | |
2135 | /* These fields are unsigned, but for upward compatibility, | |
2136 | allow negative values as well. */ | |
2137 | goto immediate; | |
2138 | ||
2139 | case 'k': | |
2140 | the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; | |
2141 | the_insn.pcrel = 1; | |
2142 | goto immediate; | |
2143 | ||
2615994e DM |
2144 | case '=': |
2145 | the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10; | |
2146 | the_insn.pcrel = 1; | |
2147 | goto immediate; | |
2148 | ||
252b5132 RH |
2149 | case 'G': |
2150 | the_insn.reloc = BFD_RELOC_SPARC_WDISP19; | |
2151 | the_insn.pcrel = 1; | |
2152 | goto immediate; | |
2153 | ||
2154 | case 'N': | |
2155 | if (*s == 'p' && s[1] == 'n') | |
2156 | { | |
2157 | s += 2; | |
2158 | continue; | |
2159 | } | |
2160 | break; | |
2161 | ||
2162 | case 'T': | |
2163 | if (*s == 'p' && s[1] == 't') | |
2164 | { | |
2165 | s += 2; | |
2166 | continue; | |
2167 | } | |
2168 | break; | |
2169 | ||
2170 | case 'z': | |
2171 | if (*s == ' ') | |
2172 | { | |
2173 | ++s; | |
2174 | } | |
f9911beb JM |
2175 | if ((strncmp (s, "%icc", 4) == 0) |
2176 | || (sparc_arch_size == 32 && strncmp (s, "%ncc", 4) == 0)) | |
252b5132 RH |
2177 | { |
2178 | s += 4; | |
2179 | continue; | |
2180 | } | |
2181 | break; | |
2182 | ||
2183 | case 'Z': | |
2184 | if (*s == ' ') | |
2185 | { | |
2186 | ++s; | |
2187 | } | |
f9911beb JM |
2188 | if ((strncmp (s, "%xcc", 4) == 0) |
2189 | || (sparc_arch_size == 64 && strncmp (s, "%ncc", 4) == 0)) | |
252b5132 RH |
2190 | { |
2191 | s += 4; | |
2192 | continue; | |
2193 | } | |
2194 | break; | |
2195 | ||
2196 | case '6': | |
2197 | if (*s == ' ') | |
2198 | { | |
2199 | ++s; | |
2200 | } | |
2201 | if (strncmp (s, "%fcc0", 5) == 0) | |
2202 | { | |
2203 | s += 5; | |
2204 | continue; | |
2205 | } | |
2206 | break; | |
2207 | ||
2208 | case '7': | |
2209 | if (*s == ' ') | |
2210 | { | |
2211 | ++s; | |
2212 | } | |
2213 | if (strncmp (s, "%fcc1", 5) == 0) | |
2214 | { | |
2215 | s += 5; | |
2216 | continue; | |
2217 | } | |
2218 | break; | |
2219 | ||
2220 | case '8': | |
2221 | if (*s == ' ') | |
2222 | { | |
2223 | ++s; | |
2224 | } | |
2225 | if (strncmp (s, "%fcc2", 5) == 0) | |
2226 | { | |
2227 | s += 5; | |
2228 | continue; | |
2229 | } | |
2230 | break; | |
2231 | ||
2232 | case '9': | |
2233 | if (*s == ' ') | |
2234 | { | |
2235 | ++s; | |
2236 | } | |
2237 | if (strncmp (s, "%fcc3", 5) == 0) | |
2238 | { | |
2239 | s += 5; | |
2240 | continue; | |
2241 | } | |
2242 | break; | |
2243 | ||
2244 | case 'P': | |
2245 | if (strncmp (s, "%pc", 3) == 0) | |
2246 | { | |
2247 | s += 3; | |
2248 | continue; | |
2249 | } | |
2250 | break; | |
2251 | ||
2252 | case 'W': | |
2253 | if (strncmp (s, "%tick", 5) == 0) | |
2254 | { | |
2255 | s += 5; | |
2256 | continue; | |
2257 | } | |
2258 | break; | |
2259 | ||
e0c6ed95 | 2260 | case '\0': /* End of args. */ |
b9734f35 | 2261 | if (s[0] == ',' && s[1] == '%') |
252b5132 | 2262 | { |
b9734f35 JJ |
2263 | char *s1; |
2264 | int npar = 0; | |
8b8c7c9f | 2265 | const struct perc_entry *p; |
b9734f35 | 2266 | |
8b8c7c9f JM |
2267 | for (p = perc_table; p->type != perc_entry_none; p++) |
2268 | if ((p->type == perc_entry_post_pop || p->type == perc_entry_reg) | |
2269 | && strncmp (s + 2, p->name, p->len) == 0) | |
2270 | break; | |
2271 | if (p->type == perc_entry_none || p->type == perc_entry_reg) | |
2272 | break; | |
b9734f35 | 2273 | |
8b8c7c9f | 2274 | if (s[p->len + 2] != '(') |
b9734f35 | 2275 | { |
8b8c7c9f | 2276 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); |
b9734f35 JJ |
2277 | return special_case; |
2278 | } | |
2279 | ||
8b8c7c9f JM |
2280 | if (! (p->pop->flags & F_POP_TLS_CALL) |
2281 | && the_insn.reloc != BFD_RELOC_NONE) | |
b9734f35 JJ |
2282 | { |
2283 | as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), | |
8b8c7c9f | 2284 | p->name); |
b9734f35 JJ |
2285 | return special_case; |
2286 | } | |
2287 | ||
8b8c7c9f | 2288 | if ((p->pop->flags & F_POP_TLS_CALL) |
b9734f35 JJ |
2289 | && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 |
2290 | || the_insn.exp.X_add_number != 0 | |
2291 | || the_insn.exp.X_add_symbol | |
2292 | != symbol_find_or_make ("__tls_get_addr"))) | |
2293 | { | |
2294 | as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), | |
8b8c7c9f | 2295 | p->name); |
b9734f35 JJ |
2296 | return special_case; |
2297 | } | |
2298 | ||
8b8c7c9f | 2299 | the_insn.reloc = p->pop->reloc; |
b9734f35 | 2300 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
8b8c7c9f | 2301 | s += p->len + 3; |
b9734f35 JJ |
2302 | |
2303 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2304 | if (*s1 == '(') | |
2305 | npar++; | |
2306 | else if (*s1 == ')') | |
2307 | { | |
2308 | if (!npar) | |
2309 | break; | |
2310 | npar--; | |
2311 | } | |
2312 | ||
2313 | if (*s1 != ')') | |
2314 | { | |
8b8c7c9f | 2315 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); |
b9734f35 JJ |
2316 | return special_case; |
2317 | } | |
2318 | ||
2319 | *s1 = '\0'; | |
2320 | (void) get_expression (s); | |
2321 | *s1 = ')'; | |
2322 | s = s1 + 1; | |
252b5132 | 2323 | } |
b9734f35 JJ |
2324 | if (*s == '\0') |
2325 | match = 1; | |
252b5132 RH |
2326 | break; |
2327 | ||
2328 | case '+': | |
2329 | if (*s == '+') | |
2330 | { | |
2331 | ++s; | |
2332 | continue; | |
2333 | } | |
2334 | if (*s == '-') | |
2335 | { | |
2336 | continue; | |
2337 | } | |
2338 | break; | |
2339 | ||
e0c6ed95 | 2340 | case '[': /* These must match exactly. */ |
252b5132 RH |
2341 | case ']': |
2342 | case ',': | |
2343 | case ' ': | |
2344 | if (*s++ == *args) | |
2345 | continue; | |
2346 | break; | |
2347 | ||
e0c6ed95 | 2348 | case '#': /* Must be at least one digit. */ |
3882b010 | 2349 | if (ISDIGIT (*s++)) |
252b5132 | 2350 | { |
3882b010 | 2351 | while (ISDIGIT (*s)) |
252b5132 RH |
2352 | { |
2353 | ++s; | |
2354 | } | |
2355 | continue; | |
2356 | } | |
2357 | break; | |
2358 | ||
e0c6ed95 | 2359 | case 'C': /* Coprocessor state register. */ |
252b5132 RH |
2360 | if (strncmp (s, "%csr", 4) == 0) |
2361 | { | |
2362 | s += 4; | |
2363 | continue; | |
2364 | } | |
2365 | break; | |
2366 | ||
e0c6ed95 | 2367 | case 'b': /* Next operand is a coprocessor register. */ |
252b5132 RH |
2368 | case 'c': |
2369 | case 'D': | |
3882b010 | 2370 | if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) |
252b5132 RH |
2371 | { |
2372 | mask = *s++; | |
3882b010 | 2373 | if (ISDIGIT (*s)) |
252b5132 RH |
2374 | { |
2375 | mask = 10 * (mask - '0') + (*s++ - '0'); | |
2376 | if (mask >= 32) | |
2377 | { | |
2378 | break; | |
2379 | } | |
2380 | } | |
2381 | else | |
2382 | { | |
2383 | mask -= '0'; | |
2384 | } | |
2385 | switch (*args) | |
2386 | { | |
2387 | ||
2388 | case 'b': | |
2389 | opcode |= mask << 14; | |
2390 | continue; | |
2391 | ||
2392 | case 'c': | |
2393 | opcode |= mask; | |
2394 | continue; | |
2395 | ||
2396 | case 'D': | |
2397 | opcode |= mask << 25; | |
2398 | continue; | |
2399 | } | |
2400 | } | |
2401 | break; | |
2402 | ||
2403 | case 'r': /* next operand must be a register */ | |
2404 | case 'O': | |
2405 | case '1': | |
2406 | case '2': | |
2407 | case 'd': | |
2408 | if (*s++ == '%') | |
2409 | { | |
2410 | switch (c = *s++) | |
2411 | { | |
2412 | ||
2413 | case 'f': /* frame pointer */ | |
2414 | if (*s++ == 'p') | |
2415 | { | |
2416 | mask = 0x1e; | |
2417 | break; | |
2418 | } | |
2419 | goto error; | |
2420 | ||
2421 | case 'g': /* global register */ | |
a22b281c RH |
2422 | c = *s++; |
2423 | if (isoctal (c)) | |
252b5132 RH |
2424 | { |
2425 | mask = c - '0'; | |
2426 | break; | |
2427 | } | |
2428 | goto error; | |
2429 | ||
2430 | case 'i': /* in register */ | |
a22b281c RH |
2431 | c = *s++; |
2432 | if (isoctal (c)) | |
252b5132 RH |
2433 | { |
2434 | mask = c - '0' + 24; | |
2435 | break; | |
2436 | } | |
2437 | goto error; | |
2438 | ||
2439 | case 'l': /* local register */ | |
a22b281c RH |
2440 | c = *s++; |
2441 | if (isoctal (c)) | |
252b5132 RH |
2442 | { |
2443 | mask = (c - '0' + 16); | |
2444 | break; | |
2445 | } | |
2446 | goto error; | |
2447 | ||
2448 | case 'o': /* out register */ | |
a22b281c RH |
2449 | c = *s++; |
2450 | if (isoctal (c)) | |
252b5132 RH |
2451 | { |
2452 | mask = (c - '0' + 8); | |
2453 | break; | |
2454 | } | |
2455 | goto error; | |
2456 | ||
2457 | case 's': /* stack pointer */ | |
2458 | if (*s++ == 'p') | |
2459 | { | |
2460 | mask = 0xe; | |
2461 | break; | |
2462 | } | |
2463 | goto error; | |
2464 | ||
2465 | case 'r': /* any register */ | |
3882b010 | 2466 | if (!ISDIGIT ((c = *s++))) |
252b5132 RH |
2467 | { |
2468 | goto error; | |
2469 | } | |
2470 | /* FALLTHROUGH */ | |
2471 | case '0': | |
2472 | case '1': | |
2473 | case '2': | |
2474 | case '3': | |
2475 | case '4': | |
2476 | case '5': | |
2477 | case '6': | |
2478 | case '7': | |
2479 | case '8': | |
2480 | case '9': | |
3882b010 | 2481 | if (ISDIGIT (*s)) |
252b5132 RH |
2482 | { |
2483 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) | |
2484 | { | |
2485 | goto error; | |
2486 | } | |
2487 | } | |
2488 | else | |
2489 | { | |
2490 | c -= '0'; | |
2491 | } | |
2492 | mask = c; | |
2493 | break; | |
2494 | ||
2495 | default: | |
2496 | goto error; | |
2497 | } | |
2498 | ||
6d8809aa | 2499 | if ((mask & ~1) == 2 && sparc_arch_size == 64 |
e0c6ed95 | 2500 | && no_undeclared_regs && ! globals[mask]) |
79bd78be | 2501 | as_bad (_("detected global register use not covered by .register pseudo-op")); |
6d8809aa | 2502 | |
252b5132 RH |
2503 | /* Got the register, now figure out where |
2504 | it goes in the opcode. */ | |
2505 | switch (*args) | |
2506 | { | |
2507 | case '1': | |
2508 | opcode |= mask << 14; | |
2509 | continue; | |
2510 | ||
2511 | case '2': | |
2512 | opcode |= mask; | |
2513 | continue; | |
2514 | ||
2515 | case 'd': | |
2516 | opcode |= mask << 25; | |
2517 | continue; | |
2518 | ||
2519 | case 'r': | |
2520 | opcode |= (mask << 25) | (mask << 14); | |
2521 | continue; | |
2522 | ||
2523 | case 'O': | |
2524 | opcode |= (mask << 25) | (mask << 0); | |
2525 | continue; | |
2526 | } | |
2527 | } | |
2528 | break; | |
2529 | ||
2530 | case 'e': /* next operand is a floating point register */ | |
2531 | case 'v': | |
2532 | case 'V': | |
2533 | ||
2534 | case 'f': | |
2535 | case 'B': | |
2536 | case 'R': | |
2537 | ||
ea783ef3 DM |
2538 | case '4': |
2539 | case '5': | |
2540 | ||
252b5132 RH |
2541 | case 'g': |
2542 | case 'H': | |
2543 | case 'J': | |
3d68f91c | 2544 | case '}': |
252b5132 RH |
2545 | { |
2546 | char format; | |
2547 | ||
2548 | if (*s++ == '%' | |
ec892a07 JM |
2549 | && ((format = *s) == 'f' |
2550 | || format == 'd' | |
2551 | || format == 'q') | |
3882b010 | 2552 | && ISDIGIT (*++s)) |
252b5132 | 2553 | { |
3882b010 | 2554 | for (mask = 0; ISDIGIT (*s); ++s) |
252b5132 RH |
2555 | { |
2556 | mask = 10 * mask + (*s - '0'); | |
2557 | } /* read the number */ | |
2558 | ||
2559 | if ((*args == 'v' | |
2560 | || *args == 'B' | |
ea783ef3 | 2561 | || *args == '5' |
ec892a07 JM |
2562 | || *args == 'H' |
2563 | || format == 'd') | |
252b5132 RH |
2564 | && (mask & 1)) |
2565 | { | |
ec892a07 | 2566 | /* register must be even numbered */ |
252b5132 | 2567 | break; |
ec892a07 | 2568 | } |
252b5132 RH |
2569 | |
2570 | if ((*args == 'V' | |
2571 | || *args == 'R' | |
ec892a07 JM |
2572 | || *args == 'J' |
2573 | || format == 'q') | |
252b5132 RH |
2574 | && (mask & 3)) |
2575 | { | |
ec892a07 | 2576 | /* register must be multiple of 4 */ |
252b5132 | 2577 | break; |
ec892a07 | 2578 | } |
252b5132 RH |
2579 | |
2580 | if (mask >= 64) | |
2581 | { | |
2582 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2583 | error_message = _(": There are only 64 f registers; [0-63]"); | |
2584 | else | |
2585 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2586 | goto error; | |
2587 | } /* on error */ | |
2588 | else if (mask >= 32) | |
2589 | { | |
2590 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2591 | { | |
26664553 JJ |
2592 | if (*args == 'e' || *args == 'f' || *args == 'g') |
2593 | { | |
2594 | error_message | |
2595 | = _(": There are only 32 single precision f registers; [0-31]"); | |
2596 | goto error; | |
2597 | } | |
252b5132 RH |
2598 | v9_arg_p = 1; |
2599 | mask -= 31; /* wrap high bit */ | |
2600 | } | |
2601 | else | |
2602 | { | |
2603 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2604 | goto error; | |
2605 | } | |
2606 | } | |
2607 | } | |
2608 | else | |
2609 | { | |
2610 | break; | |
ab3e48dc | 2611 | } /* if not an 'f' register. */ |
252b5132 | 2612 | |
3d68f91c JM |
2613 | if (*args == '}' && mask != RS2 (opcode)) |
2614 | { | |
2615 | error_message | |
2616 | = _(": Instruction requires frs2 and frsd must be the same register"); | |
2617 | goto error; | |
2618 | } | |
2619 | ||
252b5132 RH |
2620 | switch (*args) |
2621 | { | |
2622 | case 'v': | |
2623 | case 'V': | |
2624 | case 'e': | |
2625 | opcode |= RS1 (mask); | |
2626 | continue; | |
2627 | ||
252b5132 RH |
2628 | case 'f': |
2629 | case 'B': | |
2630 | case 'R': | |
2631 | opcode |= RS2 (mask); | |
2632 | continue; | |
2633 | ||
ea783ef3 DM |
2634 | case '4': |
2635 | case '5': | |
2636 | opcode |= RS3 (mask); | |
2637 | continue; | |
2638 | ||
252b5132 RH |
2639 | case 'g': |
2640 | case 'H': | |
2641 | case 'J': | |
3d68f91c | 2642 | case '}': |
252b5132 RH |
2643 | opcode |= RD (mask); |
2644 | continue; | |
ab3e48dc | 2645 | } /* Pack it in. */ |
252b5132 RH |
2646 | |
2647 | know (0); | |
2648 | break; | |
ab3e48dc | 2649 | } /* float arg */ |
252b5132 RH |
2650 | |
2651 | case 'F': | |
2652 | if (strncmp (s, "%fsr", 4) == 0) | |
2653 | { | |
2654 | s += 4; | |
2655 | continue; | |
2656 | } | |
2657 | break; | |
2658 | ||
ea783ef3 DM |
2659 | case '(': |
2660 | if (strncmp (s, "%efsr", 5) == 0) | |
2661 | { | |
2662 | s += 5; | |
2663 | continue; | |
2664 | } | |
2665 | break; | |
2666 | ||
ab3e48dc KH |
2667 | case '0': /* 64 bit immediate (set, setsw, setx insn) */ |
2668 | the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ | |
252b5132 RH |
2669 | goto immediate; |
2670 | ||
ab3e48dc | 2671 | case 'l': /* 22 bit PC relative immediate */ |
252b5132 RH |
2672 | the_insn.reloc = BFD_RELOC_SPARC_WDISP22; |
2673 | the_insn.pcrel = 1; | |
2674 | goto immediate; | |
2675 | ||
ab3e48dc | 2676 | case 'L': /* 30 bit immediate */ |
252b5132 RH |
2677 | the_insn.reloc = BFD_RELOC_32_PCREL_S2; |
2678 | the_insn.pcrel = 1; | |
2679 | goto immediate; | |
2680 | ||
63fab58c | 2681 | case 'h': |
ab3e48dc | 2682 | case 'n': /* 22 bit immediate */ |
252b5132 RH |
2683 | the_insn.reloc = BFD_RELOC_SPARC22; |
2684 | goto immediate; | |
2685 | ||
ab3e48dc | 2686 | case 'i': /* 13 bit immediate */ |
252b5132 RH |
2687 | the_insn.reloc = BFD_RELOC_SPARC13; |
2688 | ||
2689 | /* fallthrough */ | |
2690 | ||
2691 | immediate: | |
2692 | if (*s == ' ') | |
2693 | s++; | |
2694 | ||
cf9a1301 RH |
2695 | { |
2696 | char *s1; | |
e0471c16 | 2697 | const char *op_arg = NULL; |
30eb9c17 | 2698 | static expressionS op_exp; |
cf9a1301 RH |
2699 | bfd_reloc_code_real_type old_reloc = the_insn.reloc; |
2700 | ||
2701 | /* Check for %hi, etc. */ | |
2702 | if (*s == '%') | |
2703 | { | |
8b8c7c9f JM |
2704 | const struct perc_entry *p; |
2705 | ||
2706 | for (p = perc_table; p->type != perc_entry_none; p++) | |
2707 | if ((p->type == perc_entry_imm_pop || p->type == perc_entry_reg) | |
2708 | && strncmp (s + 1, p->name, p->len) == 0) | |
2709 | break; | |
2710 | if (p->type == perc_entry_none || p->type == perc_entry_reg) | |
2711 | break; | |
2712 | ||
2713 | if (s[p->len + 1] != '(') | |
cf9a1301 | 2714 | { |
8b8c7c9f | 2715 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); |
a22b281c | 2716 | return special_case; |
cf9a1301 | 2717 | } |
252b5132 | 2718 | |
8b8c7c9f JM |
2719 | op_arg = p->name; |
2720 | the_insn.reloc = p->pop->reloc; | |
2721 | s += p->len + 2; | |
2722 | v9_arg_p = p->pop->flags & F_POP_V9; | |
cf9a1301 RH |
2723 | } |
2724 | ||
2725 | /* Note that if the get_expression() fails, we will still | |
2726 | have created U entries in the symbol table for the | |
2727 | 'symbols' in the input string. Try not to create U | |
2728 | symbols for registers, etc. */ | |
252b5132 | 2729 | |
252b5132 RH |
2730 | /* This stuff checks to see if the expression ends in |
2731 | +%reg. If it does, it removes the register from | |
2732 | the expression, and re-sets 's' to point to the | |
2733 | right place. */ | |
2734 | ||
cf9a1301 RH |
2735 | if (op_arg) |
2736 | { | |
2737 | int npar = 0; | |
2738 | ||
2739 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2740 | if (*s1 == '(') | |
2741 | npar++; | |
2742 | else if (*s1 == ')') | |
2743 | { | |
2744 | if (!npar) | |
2745 | break; | |
2746 | npar--; | |
2747 | } | |
2748 | ||
2749 | if (*s1 != ')') | |
2750 | { | |
2751 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); | |
a22b281c | 2752 | return special_case; |
cf9a1301 | 2753 | } |
e0c6ed95 | 2754 | |
cf9a1301 RH |
2755 | *s1 = '\0'; |
2756 | (void) get_expression (s); | |
2757 | *s1 = ')'; | |
e140100a NC |
2758 | if (expr_end != s1) |
2759 | { | |
2760 | as_bad (_("Expression inside %%%s could not be parsed"), op_arg); | |
2761 | return special_case; | |
2762 | } | |
cf9a1301 RH |
2763 | s = s1 + 1; |
2764 | if (*s == ',' || *s == ']' || !*s) | |
2765 | continue; | |
2766 | if (*s != '+' && *s != '-') | |
2767 | { | |
2768 | as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); | |
a22b281c | 2769 | return special_case; |
cf9a1301 RH |
2770 | } |
2771 | *s1 = '0'; | |
2772 | s = s1; | |
2773 | op_exp = the_insn.exp; | |
e0c6ed95 | 2774 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
cf9a1301 | 2775 | } |
252b5132 | 2776 | |
e0c6ed95 AM |
2777 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) |
2778 | ; | |
252b5132 | 2779 | |
3882b010 | 2780 | if (s1 != s && ISDIGIT (s1[-1])) |
252b5132 RH |
2781 | { |
2782 | if (s1[-2] == '%' && s1[-3] == '+') | |
cf9a1301 | 2783 | s1 -= 3; |
f124dd4f | 2784 | else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') |
cf9a1301 | 2785 | s1 -= 4; |
f124dd4f DM |
2786 | else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+') |
2787 | s1 -= 5; | |
cf9a1301 RH |
2788 | else |
2789 | s1 = NULL; | |
2790 | if (s1) | |
252b5132 | 2791 | { |
252b5132 | 2792 | *s1 = '\0'; |
1eb7027c RH |
2793 | if (op_arg && s1 == s + 1) |
2794 | the_insn.exp.X_op = O_absent; | |
2795 | else | |
2796 | (void) get_expression (s); | |
252b5132 | 2797 | *s1 = '+'; |
cf9a1301 RH |
2798 | if (op_arg) |
2799 | *s = ')'; | |
252b5132 | 2800 | s = s1; |
252b5132 | 2801 | } |
cf9a1301 RH |
2802 | } |
2803 | else | |
2804 | s1 = NULL; | |
2805 | ||
2806 | if (!s1) | |
2807 | { | |
2808 | (void) get_expression (s); | |
2809 | if (op_arg) | |
2810 | *s = ')'; | |
2811 | s = expr_end; | |
2812 | } | |
2813 | ||
2814 | if (op_arg) | |
2815 | { | |
2816 | the_insn.exp2 = the_insn.exp; | |
2817 | the_insn.exp = op_exp; | |
2818 | if (the_insn.exp2.X_op == O_absent) | |
2819 | the_insn.exp2.X_op = O_illegal; | |
2820 | else if (the_insn.exp.X_op == O_absent) | |
252b5132 | 2821 | { |
cf9a1301 RH |
2822 | the_insn.exp = the_insn.exp2; |
2823 | the_insn.exp2.X_op = O_illegal; | |
2824 | } | |
2825 | else if (the_insn.exp.X_op == O_constant) | |
2826 | { | |
2827 | valueT val = the_insn.exp.X_add_number; | |
2828 | switch (the_insn.reloc) | |
2829 | { | |
1b50c718 ILT |
2830 | default: |
2831 | break; | |
2832 | ||
cf9a1301 RH |
2833 | case BFD_RELOC_SPARC_HH22: |
2834 | val = BSR (val, 32); | |
e0c6ed95 | 2835 | /* Fall through. */ |
cf9a1301 RH |
2836 | |
2837 | case BFD_RELOC_SPARC_LM22: | |
2838 | case BFD_RELOC_HI22: | |
2839 | val = (val >> 10) & 0x3fffff; | |
2840 | break; | |
2841 | ||
2842 | case BFD_RELOC_SPARC_HM10: | |
2843 | val = BSR (val, 32); | |
e0c6ed95 | 2844 | /* Fall through. */ |
cf9a1301 RH |
2845 | |
2846 | case BFD_RELOC_LO10: | |
2847 | val &= 0x3ff; | |
2848 | break; | |
2849 | ||
2615994e DM |
2850 | case BFD_RELOC_SPARC_H34: |
2851 | val >>= 12; | |
2852 | val &= 0x3fffff; | |
2853 | break; | |
2854 | ||
cf9a1301 RH |
2855 | case BFD_RELOC_SPARC_H44: |
2856 | val >>= 22; | |
2857 | val &= 0x3fffff; | |
2858 | break; | |
2859 | ||
2860 | case BFD_RELOC_SPARC_M44: | |
2861 | val >>= 12; | |
2862 | val &= 0x3ff; | |
2863 | break; | |
2864 | ||
2865 | case BFD_RELOC_SPARC_L44: | |
2866 | val &= 0xfff; | |
2867 | break; | |
2868 | ||
2869 | case BFD_RELOC_SPARC_HIX22: | |
ab3e48dc | 2870 | val = ~val; |
cf9a1301 RH |
2871 | val = (val >> 10) & 0x3fffff; |
2872 | break; | |
2873 | ||
2874 | case BFD_RELOC_SPARC_LOX10: | |
2875 | val = (val & 0x3ff) | 0x1c00; | |
2876 | break; | |
2877 | } | |
2878 | the_insn.exp = the_insn.exp2; | |
2879 | the_insn.exp.X_add_number += val; | |
2880 | the_insn.exp2.X_op = O_illegal; | |
2881 | the_insn.reloc = old_reloc; | |
2882 | } | |
2883 | else if (the_insn.exp2.X_op != O_constant) | |
2884 | { | |
2885 | as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); | |
a22b281c | 2886 | return special_case; |
cf9a1301 RH |
2887 | } |
2888 | else | |
2889 | { | |
dabe3bbc | 2890 | if (old_reloc != BFD_RELOC_SPARC13 |
cf9a1301 RH |
2891 | || the_insn.reloc != BFD_RELOC_LO10 |
2892 | || sparc_arch_size != 64 | |
2893 | || sparc_pic_code) | |
2894 | { | |
2895 | as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); | |
a22b281c | 2896 | return special_case; |
cf9a1301 RH |
2897 | } |
2898 | the_insn.reloc = BFD_RELOC_SPARC_OLO10; | |
252b5132 RH |
2899 | } |
2900 | } | |
2901 | } | |
252b5132 RH |
2902 | /* Check for constants that don't require emitting a reloc. */ |
2903 | if (the_insn.exp.X_op == O_constant | |
2904 | && the_insn.exp.X_add_symbol == 0 | |
2905 | && the_insn.exp.X_op_symbol == 0) | |
2906 | { | |
2907 | /* For pc-relative call instructions, we reject | |
2908 | constants to get better code. */ | |
2909 | if (the_insn.pcrel | |
2910 | && the_insn.reloc == BFD_RELOC_32_PCREL_S2 | |
2911 | && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) | |
2912 | { | |
2913 | error_message = _(": PC-relative operand can't be a constant"); | |
2914 | goto error; | |
2915 | } | |
2916 | ||
b9734f35 JJ |
2917 | if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 |
2918 | && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) | |
2919 | { | |
2920 | error_message = _(": TLS operand can't be a constant"); | |
2921 | goto error; | |
2922 | } | |
2923 | ||
55cf6793 | 2924 | /* Constants that won't fit are checked in md_apply_fix |
252b5132 RH |
2925 | and bfd_install_relocation. |
2926 | ??? It would be preferable to install the constants | |
2927 | into the insn here and save having to create a fixS | |
2928 | for each one. There already exists code to handle | |
55cf6793 | 2929 | all the various cases (e.g. in md_apply_fix and |
252b5132 RH |
2930 | bfd_install_relocation) so duplicating all that code |
2931 | here isn't right. */ | |
698544e1 DM |
2932 | |
2933 | /* This is a special case to handle cbcond instructions | |
2934 | properly, which can need two relocations. The first | |
2935 | one is for the 5-bit immediate field and the latter | |
2936 | is going to be for the WDISP10 branch part. We | |
2937 | handle the R_SPARC_5 immediate directly here so that | |
2938 | we don't need to add support for multiple relocations | |
2939 | in one instruction just yet. */ | |
65d1cff9 JM |
2940 | if (the_insn.reloc == BFD_RELOC_SPARC_5 |
2941 | && ((insn->match & OP(0x3)) == 0)) | |
698544e1 DM |
2942 | { |
2943 | valueT val = the_insn.exp.X_add_number; | |
2944 | ||
65d1cff9 | 2945 | the_insn.reloc = BFD_RELOC_NONE; |
698544e1 DM |
2946 | if (! in_bitfield_range (val, 0x1f)) |
2947 | { | |
2948 | error_message = _(": Immediate value in cbcond is out of range."); | |
2949 | goto error; | |
2950 | } | |
2951 | opcode |= val & 0x1f; | |
698544e1 | 2952 | } |
252b5132 RH |
2953 | } |
2954 | ||
2955 | continue; | |
2956 | ||
2957 | case 'a': | |
2958 | if (*s++ == 'a') | |
2959 | { | |
2960 | opcode |= ANNUL; | |
2961 | continue; | |
2962 | } | |
2963 | break; | |
2964 | ||
2965 | case 'A': | |
2966 | { | |
2967 | int asi = 0; | |
2968 | ||
2969 | /* Parse an asi. */ | |
2970 | if (*s == '#') | |
2971 | { | |
2972 | if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) | |
2973 | { | |
2974 | error_message = _(": invalid ASI name"); | |
2975 | goto error; | |
2976 | } | |
2977 | } | |
2978 | else | |
2979 | { | |
2980 | if (! parse_const_expr_arg (&s, &asi)) | |
2981 | { | |
2982 | error_message = _(": invalid ASI expression"); | |
2983 | goto error; | |
2984 | } | |
2985 | if (asi < 0 || asi > 255) | |
2986 | { | |
2987 | error_message = _(": invalid ASI number"); | |
2988 | goto error; | |
2989 | } | |
2990 | } | |
2991 | opcode |= ASI (asi); | |
2992 | continue; | |
e0c6ed95 | 2993 | } /* Alternate space. */ |
252b5132 RH |
2994 | |
2995 | case 'p': | |
2996 | if (strncmp (s, "%psr", 4) == 0) | |
2997 | { | |
2998 | s += 4; | |
2999 | continue; | |
3000 | } | |
3001 | break; | |
3002 | ||
e0c6ed95 | 3003 | case 'q': /* Floating point queue. */ |
252b5132 RH |
3004 | if (strncmp (s, "%fq", 3) == 0) |
3005 | { | |
3006 | s += 3; | |
3007 | continue; | |
3008 | } | |
3009 | break; | |
3010 | ||
e0c6ed95 | 3011 | case 'Q': /* Coprocessor queue. */ |
252b5132 RH |
3012 | if (strncmp (s, "%cq", 3) == 0) |
3013 | { | |
3014 | s += 3; | |
3015 | continue; | |
3016 | } | |
3017 | break; | |
3018 | ||
3019 | case 'S': | |
3020 | if (strcmp (str, "set") == 0 | |
3021 | || strcmp (str, "setuw") == 0) | |
3022 | { | |
3023 | special_case = SPECIAL_CASE_SET; | |
3024 | continue; | |
3025 | } | |
3026 | else if (strcmp (str, "setsw") == 0) | |
3027 | { | |
3028 | special_case = SPECIAL_CASE_SETSW; | |
3029 | continue; | |
3030 | } | |
3031 | else if (strcmp (str, "setx") == 0) | |
3032 | { | |
3033 | special_case = SPECIAL_CASE_SETX; | |
3034 | continue; | |
3035 | } | |
3036 | else if (strncmp (str, "fdiv", 4) == 0) | |
3037 | { | |
3038 | special_case = SPECIAL_CASE_FDIV; | |
3039 | continue; | |
3040 | } | |
3041 | break; | |
3042 | ||
3043 | case 'o': | |
3044 | if (strncmp (s, "%asi", 4) != 0) | |
3045 | break; | |
3046 | s += 4; | |
3047 | continue; | |
3048 | ||
3049 | case 's': | |
3050 | if (strncmp (s, "%fprs", 5) != 0) | |
3051 | break; | |
3052 | s += 5; | |
3053 | continue; | |
3054 | ||
3d68f91c JM |
3055 | case '{': |
3056 | if (strncmp (s, "%mcdper",7) != 0) | |
3057 | break; | |
3058 | s += 7; | |
3059 | continue; | |
3060 | ||
252b5132 RH |
3061 | case 'E': |
3062 | if (strncmp (s, "%ccr", 4) != 0) | |
3063 | break; | |
3064 | s += 4; | |
3065 | continue; | |
3066 | ||
3067 | case 't': | |
3068 | if (strncmp (s, "%tbr", 4) != 0) | |
3069 | break; | |
3070 | s += 4; | |
3071 | continue; | |
3072 | ||
3073 | case 'w': | |
3074 | if (strncmp (s, "%wim", 4) != 0) | |
3075 | break; | |
3076 | s += 4; | |
3077 | continue; | |
3078 | ||
3079 | case 'x': | |
3080 | { | |
3081 | char *push = input_line_pointer; | |
3082 | expressionS e; | |
3083 | ||
3084 | input_line_pointer = s; | |
3085 | expression (&e); | |
3086 | if (e.X_op == O_constant) | |
3087 | { | |
3088 | int n = e.X_add_number; | |
3089 | if (n != e.X_add_number || (n & ~0x1ff) != 0) | |
3090 | as_bad (_("OPF immediate operand out of range (0-0x1ff)")); | |
3091 | else | |
3092 | opcode |= e.X_add_number << 5; | |
3093 | } | |
3094 | else | |
3095 | as_bad (_("non-immediate OPF operand, ignored")); | |
3096 | s = input_line_pointer; | |
3097 | input_line_pointer = push; | |
3098 | continue; | |
3099 | } | |
3100 | ||
3101 | case 'y': | |
3102 | if (strncmp (s, "%y", 2) != 0) | |
3103 | break; | |
3104 | s += 2; | |
3105 | continue; | |
3106 | ||
3107 | case 'u': | |
3108 | case 'U': | |
3109 | { | |
3110 | /* Parse a sparclet cpreg. */ | |
3111 | int cpreg; | |
3112 | if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) | |
3113 | { | |
3114 | error_message = _(": invalid cpreg name"); | |
3115 | goto error; | |
3116 | } | |
3117 | opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); | |
3118 | continue; | |
3119 | } | |
3120 | ||
3121 | default: | |
3122 | as_fatal (_("failed sanity check.")); | |
e0c6ed95 | 3123 | } /* switch on arg code. */ |
252b5132 RH |
3124 | |
3125 | /* Break out of for() loop. */ | |
3126 | break; | |
e0c6ed95 | 3127 | } /* For each arg that we expect. */ |
252b5132 RH |
3128 | |
3129 | error: | |
3130 | if (match == 0) | |
3131 | { | |
e0c6ed95 | 3132 | /* Args don't match. */ |
252b5132 RH |
3133 | if (&insn[1] - sparc_opcodes < sparc_num_opcodes |
3134 | && (insn->name == insn[1].name | |
3135 | || !strcmp (insn->name, insn[1].name))) | |
3136 | { | |
3137 | ++insn; | |
3138 | s = argsStart; | |
3139 | continue; | |
3140 | } | |
3141 | else | |
3142 | { | |
3143 | as_bad (_("Illegal operands%s"), error_message); | |
a22b281c | 3144 | return special_case; |
252b5132 RH |
3145 | } |
3146 | } | |
3147 | else | |
3148 | { | |
e0c6ed95 | 3149 | /* We have a match. Now see if the architecture is OK. */ |
252b5132 | 3150 | int needed_arch_mask = insn->architecture; |
3d68f91c JM |
3151 | bfd_uint64_t hwcaps |
3152 | = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps; | |
252b5132 | 3153 | |
4bafe00e | 3154 | #if defined(OBJ_ELF) && !defined(TE_SOLARIS) |
9e8c70f9 DM |
3155 | if (hwcaps) |
3156 | hwcap_seen |= hwcaps; | |
3157 | #endif | |
252b5132 RH |
3158 | if (v9_arg_p) |
3159 | { | |
19f7b010 JJ |
3160 | needed_arch_mask &= |
3161 | ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); | |
3162 | if (! needed_arch_mask) | |
3163 | needed_arch_mask = | |
3164 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); | |
252b5132 RH |
3165 | } |
3166 | ||
e0c6ed95 AM |
3167 | if (needed_arch_mask |
3168 | & SPARC_OPCODE_SUPPORTED (current_architecture)) | |
3169 | /* OK. */ | |
3170 | ; | |
252b5132 | 3171 | /* Can we bump up the architecture? */ |
e0c6ed95 AM |
3172 | else if (needed_arch_mask |
3173 | & SPARC_OPCODE_SUPPORTED (max_architecture)) | |
252b5132 RH |
3174 | { |
3175 | enum sparc_opcode_arch_val needed_architecture = | |
3176 | sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) | |
3177 | & needed_arch_mask); | |
3178 | ||
9c2799c2 | 3179 | gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); |
252b5132 RH |
3180 | if (warn_on_bump |
3181 | && needed_architecture > warn_after_architecture) | |
3182 | { | |
3183 | as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), | |
3184 | sparc_opcode_archs[current_architecture].name, | |
3185 | sparc_opcode_archs[needed_architecture].name, | |
3186 | str); | |
3187 | warn_after_architecture = needed_architecture; | |
3188 | } | |
3189 | current_architecture = needed_architecture; | |
6884417a JM |
3190 | hwcap_allowed |
3191 | = (hwcap_allowed | |
3192 | | hwcaps | |
3193 | | (((bfd_uint64_t) sparc_opcode_archs[current_architecture].hwcaps2) << 32) | |
3194 | | sparc_opcode_archs[current_architecture].hwcaps); | |
252b5132 RH |
3195 | } |
3196 | /* Conflict. */ | |
3197 | /* ??? This seems to be a bit fragile. What if the next entry in | |
3198 | the opcode table is the one we want and it is supported? | |
3199 | It is possible to arrange the table today so that this can't | |
3200 | happen but what about tomorrow? */ | |
3201 | else | |
3202 | { | |
e0c6ed95 | 3203 | int arch, printed_one_p = 0; |
252b5132 RH |
3204 | char *p; |
3205 | char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; | |
3206 | ||
3207 | /* Create a list of the architectures that support the insn. */ | |
e0c6ed95 | 3208 | needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); |
252b5132 RH |
3209 | p = required_archs; |
3210 | arch = sparc_ffs (needed_arch_mask); | |
3211 | while ((1 << arch) <= needed_arch_mask) | |
3212 | { | |
3213 | if ((1 << arch) & needed_arch_mask) | |
3214 | { | |
3215 | if (printed_one_p) | |
3216 | *p++ = '|'; | |
3217 | strcpy (p, sparc_opcode_archs[arch].name); | |
3218 | p += strlen (p); | |
3219 | printed_one_p = 1; | |
3220 | } | |
3221 | ++arch; | |
3222 | } | |
3223 | ||
fc7514d6 | 3224 | as_bad (_("Architecture mismatch on \"%s %s\"."), str, argsStart); |
252b5132 RH |
3225 | as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), |
3226 | required_archs, | |
3227 | sparc_opcode_archs[max_architecture].name); | |
a22b281c | 3228 | return special_case; |
252b5132 | 3229 | } |
4bafe00e | 3230 | |
9aff4b7a | 3231 | /* Make sure the hwcaps used by the instruction are |
4bafe00e DM |
3232 | currently enabled. */ |
3233 | if (hwcaps & ~hwcap_allowed) | |
3234 | { | |
3235 | const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed); | |
3236 | ||
3237 | as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."), | |
3238 | hwcap_name, str); | |
3239 | return special_case; | |
3240 | } | |
e0c6ed95 | 3241 | } /* If no match. */ |
252b5132 RH |
3242 | |
3243 | break; | |
e0c6ed95 | 3244 | } /* Forever looking for a match. */ |
252b5132 RH |
3245 | |
3246 | the_insn.opcode = opcode; | |
a22b281c | 3247 | return special_case; |
252b5132 RH |
3248 | } |
3249 | ||
3250 | /* Parse an argument that can be expressed as a keyword. | |
3251 | (eg: #StoreStore or %ccfr). | |
3252 | The result is a boolean indicating success. | |
3253 | If successful, INPUT_POINTER is updated. */ | |
3254 | ||
3255 | static int | |
5a49b8ac AM |
3256 | parse_keyword_arg (int (*lookup_fn) (const char *), |
3257 | char **input_pointerP, | |
3258 | int *valueP) | |
252b5132 RH |
3259 | { |
3260 | int value; | |
3261 | char c, *p, *q; | |
3262 | ||
3263 | p = *input_pointerP; | |
3264 | for (q = p + (*p == '#' || *p == '%'); | |
3882b010 | 3265 | ISALNUM (*q) || *q == '_'; |
252b5132 RH |
3266 | ++q) |
3267 | continue; | |
3268 | c = *q; | |
3269 | *q = 0; | |
3270 | value = (*lookup_fn) (p); | |
3271 | *q = c; | |
3272 | if (value == -1) | |
3273 | return 0; | |
3274 | *valueP = value; | |
3275 | *input_pointerP = q; | |
3276 | return 1; | |
3277 | } | |
3278 | ||
3279 | /* Parse an argument that is a constant expression. | |
3280 | The result is a boolean indicating success. */ | |
3281 | ||
3282 | static int | |
5a49b8ac | 3283 | parse_const_expr_arg (char **input_pointerP, int *valueP) |
252b5132 RH |
3284 | { |
3285 | char *save = input_line_pointer; | |
3286 | expressionS exp; | |
3287 | ||
3288 | input_line_pointer = *input_pointerP; | |
3289 | /* The next expression may be something other than a constant | |
3290 | (say if we're not processing the right variant of the insn). | |
3291 | Don't call expression unless we're sure it will succeed as it will | |
3292 | signal an error (which we want to defer until later). */ | |
3293 | /* FIXME: It might be better to define md_operand and have it recognize | |
3294 | things like %asi, etc. but continuing that route through to the end | |
3295 | is a lot of work. */ | |
3296 | if (*input_line_pointer == '%') | |
3297 | { | |
3298 | input_line_pointer = save; | |
3299 | return 0; | |
3300 | } | |
3301 | expression (&exp); | |
3302 | *input_pointerP = input_line_pointer; | |
3303 | input_line_pointer = save; | |
3304 | if (exp.X_op != O_constant) | |
3305 | return 0; | |
3306 | *valueP = exp.X_add_number; | |
3307 | return 1; | |
3308 | } | |
3309 | ||
3310 | /* Subroutine of sparc_ip to parse an expression. */ | |
3311 | ||
3312 | static int | |
5a49b8ac | 3313 | get_expression (char *str) |
252b5132 RH |
3314 | { |
3315 | char *save_in; | |
3316 | segT seg; | |
3317 | ||
3318 | save_in = input_line_pointer; | |
3319 | input_line_pointer = str; | |
3320 | seg = expression (&the_insn.exp); | |
3321 | if (seg != absolute_section | |
3322 | && seg != text_section | |
3323 | && seg != data_section | |
3324 | && seg != bss_section | |
3325 | && seg != undefined_section) | |
3326 | { | |
3327 | the_insn.error = _("bad segment"); | |
3328 | expr_end = input_line_pointer; | |
3329 | input_line_pointer = save_in; | |
3330 | return 1; | |
3331 | } | |
3332 | expr_end = input_line_pointer; | |
3333 | input_line_pointer = save_in; | |
3334 | return 0; | |
3335 | } | |
3336 | ||
3337 | /* Subroutine of md_assemble to output one insn. */ | |
3338 | ||
3339 | static void | |
91d6fa6a | 3340 | output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn) |
252b5132 RH |
3341 | { |
3342 | char *toP = frag_more (4); | |
3343 | ||
e0c6ed95 | 3344 | /* Put out the opcode. */ |
252b5132 | 3345 | if (INSN_BIG_ENDIAN) |
91d6fa6a | 3346 | number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 3347 | else |
91d6fa6a | 3348 | number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 3349 | |
e0c6ed95 | 3350 | /* Put out the symbol-dependent stuff. */ |
91d6fa6a | 3351 | if (theinsn->reloc != BFD_RELOC_NONE) |
252b5132 | 3352 | { |
e0c6ed95 AM |
3353 | fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ |
3354 | (toP - frag_now->fr_literal), /* Where. */ | |
3355 | 4, /* Size. */ | |
91d6fa6a NC |
3356 | &theinsn->exp, |
3357 | theinsn->pcrel, | |
3358 | theinsn->reloc); | |
252b5132 | 3359 | /* Turn off overflow checking in fixup_segment. We'll do our |
55cf6793 | 3360 | own overflow checking in md_apply_fix. This is necessary because |
252b5132 RH |
3361 | the insn size is 4 and fixup_segment will signal an overflow for |
3362 | large 8 byte quantities. */ | |
3363 | fixP->fx_no_overflow = 1; | |
91d6fa6a NC |
3364 | if (theinsn->reloc == BFD_RELOC_SPARC_OLO10) |
3365 | fixP->tc_fix_data = theinsn->exp2.X_add_number; | |
252b5132 RH |
3366 | } |
3367 | ||
3368 | last_insn = insn; | |
91d6fa6a | 3369 | last_opcode = theinsn->opcode; |
732d96b6 JJ |
3370 | |
3371 | #ifdef OBJ_ELF | |
3372 | dwarf2_emit_insn (4); | |
3373 | #endif | |
252b5132 RH |
3374 | } |
3375 | \f | |
6d4af3c2 | 3376 | const char * |
499ac353 | 3377 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 3378 | { |
499ac353 | 3379 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
3380 | } |
3381 | ||
3382 | /* Write a value out to the object file, using the appropriate | |
3383 | endianness. */ | |
3384 | ||
3385 | void | |
5a49b8ac | 3386 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
3387 | { |
3388 | if (target_big_endian) | |
3389 | number_to_chars_bigendian (buf, val, n); | |
3390 | else if (target_little_endian_data | |
3391 | && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) | |
e0c6ed95 AM |
3392 | /* Output debug words, which are not in allocated sections, as big |
3393 | endian. */ | |
252b5132 RH |
3394 | number_to_chars_bigendian (buf, val, n); |
3395 | else if (target_little_endian_data || ! target_big_endian) | |
3396 | number_to_chars_littleendian (buf, val, n); | |
3397 | } | |
3398 | \f | |
3399 | /* Apply a fixS to the frags, now that we know the value it ought to | |
81d4177b | 3400 | hold. */ |
252b5132 | 3401 | |
94f592af | 3402 | void |
5a49b8ac | 3403 | md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) |
252b5132 RH |
3404 | { |
3405 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
94f592af | 3406 | offsetT val = * (offsetT *) valP; |
252b5132 RH |
3407 | long insn; |
3408 | ||
9c2799c2 | 3409 | gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); |
252b5132 | 3410 | |
e0c6ed95 | 3411 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
252b5132 RH |
3412 | |
3413 | #ifdef OBJ_ELF | |
a161fe53 | 3414 | /* SPARC ELF relocations don't use an addend in the data field. */ |
252b5132 | 3415 | if (fixP->fx_addsy != NULL) |
7c1d0959 L |
3416 | { |
3417 | switch (fixP->fx_r_type) | |
3418 | { | |
3419 | case BFD_RELOC_SPARC_TLS_GD_HI22: | |
3420 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3421 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3422 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3423 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3424 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3425 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3426 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3427 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3428 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3429 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3430 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3431 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3432 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3433 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3434 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3435 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3436 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3437 | case BFD_RELOC_SPARC_TLS_DTPMOD32: | |
3438 | case BFD_RELOC_SPARC_TLS_DTPMOD64: | |
3439 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3440 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
3441 | case BFD_RELOC_SPARC_TLS_TPOFF32: | |
3442 | case BFD_RELOC_SPARC_TLS_TPOFF64: | |
3443 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
3444 | ||
3445 | default: | |
3446 | break; | |
3447 | } | |
3448 | ||
3449 | return; | |
3450 | } | |
252b5132 RH |
3451 | #endif |
3452 | ||
3453 | /* This is a hack. There should be a better way to | |
3454 | handle this. Probably in terms of howto fields, once | |
3455 | we can look at these fixups in terms of howtos. */ | |
3456 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) | |
3457 | val += fixP->fx_where + fixP->fx_frag->fr_address; | |
3458 | ||
3459 | #ifdef OBJ_AOUT | |
3460 | /* FIXME: More ridiculous gas reloc hacking. If we are going to | |
3461 | generate a reloc, then we just want to let the reloc addend set | |
3462 | the value. We do not want to also stuff the addend into the | |
3463 | object file. Including the addend in the object file works when | |
3464 | doing a static link, because the linker will ignore the object | |
3465 | file contents. However, the dynamic linker does not ignore the | |
3466 | object file contents. */ | |
3467 | if (fixP->fx_addsy != NULL | |
3468 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) | |
3469 | val = 0; | |
3470 | ||
3471 | /* When generating PIC code, we do not want an addend for a reloc | |
3472 | against a local symbol. We adjust fx_addnumber to cancel out the | |
3473 | value already included in val, and to also cancel out the | |
3474 | adjustment which bfd_install_relocation will create. */ | |
3475 | if (sparc_pic_code | |
3476 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 | |
3477 | && fixP->fx_addsy != NULL | |
3478 | && ! S_IS_COMMON (fixP->fx_addsy) | |
49309057 | 3479 | && symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3480 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); |
3481 | ||
3482 | /* When generating PIC code, we need to fiddle to get | |
3483 | bfd_install_relocation to do the right thing for a PC relative | |
3484 | reloc against a local symbol which we are going to keep. */ | |
3485 | if (sparc_pic_code | |
3486 | && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3487 | && fixP->fx_addsy != NULL | |
3488 | && (S_IS_EXTERNAL (fixP->fx_addsy) | |
3489 | || S_IS_WEAK (fixP->fx_addsy)) | |
3490 | && S_IS_DEFINED (fixP->fx_addsy) | |
3491 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
3492 | { | |
3493 | val = 0; | |
3494 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
3495 | } | |
3496 | #endif | |
3497 | ||
3498 | /* If this is a data relocation, just output VAL. */ | |
3499 | ||
a7bbf4e9 DM |
3500 | if (fixP->fx_r_type == BFD_RELOC_8) |
3501 | { | |
3502 | md_number_to_chars (buf, val, 1); | |
3503 | } | |
3504 | else if (fixP->fx_r_type == BFD_RELOC_16 | |
3505 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) | |
252b5132 RH |
3506 | { |
3507 | md_number_to_chars (buf, val, 2); | |
3508 | } | |
3509 | else if (fixP->fx_r_type == BFD_RELOC_32 | |
0f2712ed | 3510 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 |
252b5132 RH |
3511 | || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) |
3512 | { | |
3513 | md_number_to_chars (buf, val, 4); | |
3514 | } | |
0f2712ed NC |
3515 | else if (fixP->fx_r_type == BFD_RELOC_64 |
3516 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) | |
252b5132 RH |
3517 | { |
3518 | md_number_to_chars (buf, val, 8); | |
3519 | } | |
e0c6ed95 | 3520 | else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
252b5132 RH |
3521 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
3522 | { | |
3523 | fixP->fx_done = 0; | |
94f592af | 3524 | return; |
252b5132 RH |
3525 | } |
3526 | else | |
3527 | { | |
3528 | /* It's a relocation against an instruction. */ | |
3529 | ||
3530 | if (INSN_BIG_ENDIAN) | |
3531 | insn = bfd_getb32 ((unsigned char *) buf); | |
3532 | else | |
3533 | insn = bfd_getl32 ((unsigned char *) buf); | |
e0c6ed95 | 3534 | |
252b5132 RH |
3535 | switch (fixP->fx_r_type) |
3536 | { | |
3537 | case BFD_RELOC_32_PCREL_S2: | |
3538 | val = val >> 2; | |
3539 | /* FIXME: This increment-by-one deserves a comment of why it's | |
3540 | being done! */ | |
3541 | if (! sparc_pic_code | |
3542 | || fixP->fx_addsy == NULL | |
49309057 | 3543 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 | 3544 | ++val; |
6faf3d66 | 3545 | |
252b5132 | 3546 | insn |= val & 0x3fffffff; |
6faf3d66 | 3547 | |
e0c6ed95 | 3548 | /* See if we have a delay slot. */ |
6faf3d66 JJ |
3549 | if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) |
3550 | { | |
3551 | #define G0 0 | |
3552 | #define O7 15 | |
3553 | #define XCC (2 << 20) | |
3554 | #define COND(x) (((x)&0xf)<<25) | |
3555 | #define CONDA COND(0x8) | |
3556 | #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) | |
3557 | #define INSN_BA (F2(0,2) | CONDA) | |
3558 | #define INSN_OR F3(2, 0x2, 0) | |
3559 | #define INSN_NOP F2(0,4) | |
3560 | ||
3561 | long delay; | |
3562 | ||
3563 | /* If the instruction is a call with either: | |
3564 | restore | |
3565 | arithmetic instruction with rd == %o7 | |
3566 | where rs1 != %o7 and rs2 if it is register != %o7 | |
3567 | then we can optimize if the call destination is near | |
3568 | by changing the call into a branch always. */ | |
3569 | if (INSN_BIG_ENDIAN) | |
3570 | delay = bfd_getb32 ((unsigned char *) buf + 4); | |
3571 | else | |
3572 | delay = bfd_getl32 ((unsigned char *) buf + 4); | |
e0c6ed95 | 3573 | if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) |
6faf3d66 | 3574 | break; |
e0c6ed95 AM |
3575 | if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ |
3576 | && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ | |
3577 | || ((delay & RD (~0)) != RD (O7)))) | |
6faf3d66 | 3578 | break; |
e0c6ed95 AM |
3579 | if ((delay & RS1 (~0)) == RS1 (O7) |
3580 | || ((delay & F3I (~0)) == 0 | |
3581 | && (delay & RS2 (~0)) == RS2 (O7))) | |
6faf3d66 JJ |
3582 | break; |
3583 | /* Ensure the branch will fit into simm22. */ | |
3584 | if ((val & 0x3fe00000) | |
3585 | && (val & 0x3fe00000) != 0x3fe00000) | |
3586 | break; | |
3587 | /* Check if the arch is v9 and branch will fit | |
3588 | into simm19. */ | |
3589 | if (((val & 0x3c0000) == 0 | |
3590 | || (val & 0x3c0000) == 0x3c0000) | |
3591 | && (sparc_arch_size == 64 | |
3592 | || current_architecture >= SPARC_OPCODE_ARCH_V9)) | |
e0c6ed95 | 3593 | /* ba,pt %xcc */ |
6faf3d66 JJ |
3594 | insn = INSN_BPA | (val & 0x7ffff); |
3595 | else | |
e0c6ed95 | 3596 | /* ba */ |
6faf3d66 JJ |
3597 | insn = INSN_BA | (val & 0x3fffff); |
3598 | if (fixP->fx_where >= 4 | |
e0c6ed95 AM |
3599 | && ((delay & (0xffffffff ^ RS1 (~0))) |
3600 | == (INSN_OR | RD (O7) | RS2 (G0)))) | |
6faf3d66 JJ |
3601 | { |
3602 | long setter; | |
3603 | int reg; | |
3604 | ||
3605 | if (INSN_BIG_ENDIAN) | |
3606 | setter = bfd_getb32 ((unsigned char *) buf - 4); | |
3607 | else | |
3608 | setter = bfd_getl32 ((unsigned char *) buf - 4); | |
e0c6ed95 | 3609 | if ((setter & (0xffffffff ^ RD (~0))) |
ab3e48dc | 3610 | != (INSN_OR | RS1 (O7) | RS2 (G0))) |
6faf3d66 JJ |
3611 | break; |
3612 | /* The sequence was | |
3613 | or %o7, %g0, %rN | |
3614 | call foo | |
3615 | or %rN, %g0, %o7 | |
3616 | ||
3617 | If call foo was replaced with ba, replace | |
3618 | or %rN, %g0, %o7 with nop. */ | |
e0c6ed95 AM |
3619 | reg = (delay & RS1 (~0)) >> 14; |
3620 | if (reg != ((setter & RD (~0)) >> 25) | |
6faf3d66 JJ |
3621 | || reg == G0 || reg == O7) |
3622 | break; | |
3623 | ||
3624 | if (INSN_BIG_ENDIAN) | |
3625 | bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); | |
3626 | else | |
3627 | bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); | |
3628 | } | |
3629 | } | |
252b5132 RH |
3630 | break; |
3631 | ||
3632 | case BFD_RELOC_SPARC_11: | |
3633 | if (! in_signed_range (val, 0x7ff)) | |
3634 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3635 | _("relocation overflow")); | |
3636 | insn |= val & 0x7ff; | |
3637 | break; | |
3638 | ||
3639 | case BFD_RELOC_SPARC_10: | |
3640 | if (! in_signed_range (val, 0x3ff)) | |
3641 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3642 | _("relocation overflow")); | |
3643 | insn |= val & 0x3ff; | |
3644 | break; | |
3645 | ||
3646 | case BFD_RELOC_SPARC_7: | |
3647 | if (! in_bitfield_range (val, 0x7f)) | |
3648 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3649 | _("relocation overflow")); | |
3650 | insn |= val & 0x7f; | |
3651 | break; | |
3652 | ||
3653 | case BFD_RELOC_SPARC_6: | |
3654 | if (! in_bitfield_range (val, 0x3f)) | |
3655 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3656 | _("relocation overflow")); | |
3657 | insn |= val & 0x3f; | |
3658 | break; | |
3659 | ||
3660 | case BFD_RELOC_SPARC_5: | |
3661 | if (! in_bitfield_range (val, 0x1f)) | |
3662 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3663 | _("relocation overflow")); | |
3664 | insn |= val & 0x1f; | |
3665 | break; | |
3666 | ||
2615994e DM |
3667 | case BFD_RELOC_SPARC_WDISP10: |
3668 | if ((val & 3) | |
3669 | || val >= 0x007fc | |
3670 | || val <= -(offsetT) 0x808) | |
3671 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3672 | _("relocation overflow")); | |
3673 | /* FIXME: The +1 deserves a comment. */ | |
3674 | val = (val >> 2) + 1; | |
3675 | insn |= ((val & 0x300) << 11) | |
3676 | | ((val & 0xff) << 5); | |
3677 | break; | |
3678 | ||
252b5132 | 3679 | case BFD_RELOC_SPARC_WDISP16: |
c699f087 JJ |
3680 | if ((val & 3) |
3681 | || val >= 0x1fffc | |
3682 | || val <= -(offsetT) 0x20008) | |
252b5132 RH |
3683 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3684 | _("relocation overflow")); | |
3685 | /* FIXME: The +1 deserves a comment. */ | |
3686 | val = (val >> 2) + 1; | |
3687 | insn |= ((val & 0xc000) << 6) | (val & 0x3fff); | |
3688 | break; | |
3689 | ||
3690 | case BFD_RELOC_SPARC_WDISP19: | |
c699f087 JJ |
3691 | if ((val & 3) |
3692 | || val >= 0xffffc | |
3693 | || val <= -(offsetT) 0x100008) | |
252b5132 RH |
3694 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3695 | _("relocation overflow")); | |
3696 | /* FIXME: The +1 deserves a comment. */ | |
3697 | val = (val >> 2) + 1; | |
3698 | insn |= val & 0x7ffff; | |
3699 | break; | |
3700 | ||
3701 | case BFD_RELOC_SPARC_HH22: | |
3702 | val = BSR (val, 32); | |
e0c6ed95 | 3703 | /* Fall through. */ |
252b5132 RH |
3704 | |
3705 | case BFD_RELOC_SPARC_LM22: | |
3706 | case BFD_RELOC_HI22: | |
3707 | if (!fixP->fx_addsy) | |
94f592af | 3708 | insn |= (val >> 10) & 0x3fffff; |
252b5132 | 3709 | else |
94f592af NC |
3710 | /* FIXME: Need comment explaining why we do this. */ |
3711 | insn &= ~0xffff; | |
252b5132 RH |
3712 | break; |
3713 | ||
3714 | case BFD_RELOC_SPARC22: | |
3715 | if (val & ~0x003fffff) | |
3716 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3717 | _("relocation overflow")); | |
3718 | insn |= (val & 0x3fffff); | |
3719 | break; | |
3720 | ||
3721 | case BFD_RELOC_SPARC_HM10: | |
3722 | val = BSR (val, 32); | |
e0c6ed95 | 3723 | /* Fall through. */ |
252b5132 RH |
3724 | |
3725 | case BFD_RELOC_LO10: | |
3726 | if (!fixP->fx_addsy) | |
94f592af | 3727 | insn |= val & 0x3ff; |
252b5132 | 3728 | else |
94f592af NC |
3729 | /* FIXME: Need comment explaining why we do this. */ |
3730 | insn &= ~0xff; | |
252b5132 RH |
3731 | break; |
3732 | ||
dabe3bbc RH |
3733 | case BFD_RELOC_SPARC_OLO10: |
3734 | val &= 0x3ff; | |
3735 | val += fixP->tc_fix_data; | |
e0c6ed95 | 3736 | /* Fall through. */ |
dabe3bbc | 3737 | |
252b5132 RH |
3738 | case BFD_RELOC_SPARC13: |
3739 | if (! in_signed_range (val, 0x1fff)) | |
3740 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3741 | _("relocation overflow")); | |
3742 | insn |= val & 0x1fff; | |
3743 | break; | |
3744 | ||
3745 | case BFD_RELOC_SPARC_WDISP22: | |
3746 | val = (val >> 2) + 1; | |
e0c6ed95 | 3747 | /* Fall through. */ |
252b5132 RH |
3748 | case BFD_RELOC_SPARC_BASE22: |
3749 | insn |= val & 0x3fffff; | |
3750 | break; | |
3751 | ||
2615994e DM |
3752 | case BFD_RELOC_SPARC_H34: |
3753 | if (!fixP->fx_addsy) | |
3754 | { | |
3755 | bfd_vma tval = val; | |
3756 | tval >>= 12; | |
3757 | insn |= tval & 0x3fffff; | |
3758 | } | |
3759 | break; | |
3760 | ||
252b5132 RH |
3761 | case BFD_RELOC_SPARC_H44: |
3762 | if (!fixP->fx_addsy) | |
3763 | { | |
3764 | bfd_vma tval = val; | |
3765 | tval >>= 22; | |
3766 | insn |= tval & 0x3fffff; | |
3767 | } | |
3768 | break; | |
3769 | ||
3770 | case BFD_RELOC_SPARC_M44: | |
3771 | if (!fixP->fx_addsy) | |
3772 | insn |= (val >> 12) & 0x3ff; | |
3773 | break; | |
3774 | ||
3775 | case BFD_RELOC_SPARC_L44: | |
3776 | if (!fixP->fx_addsy) | |
3777 | insn |= val & 0xfff; | |
3778 | break; | |
3779 | ||
3780 | case BFD_RELOC_SPARC_HIX22: | |
3781 | if (!fixP->fx_addsy) | |
3782 | { | |
ab3e48dc | 3783 | val ^= ~(offsetT) 0; |
252b5132 RH |
3784 | insn |= (val >> 10) & 0x3fffff; |
3785 | } | |
3786 | break; | |
3787 | ||
3788 | case BFD_RELOC_SPARC_LOX10: | |
3789 | if (!fixP->fx_addsy) | |
3790 | insn |= 0x1c00 | (val & 0x3ff); | |
3791 | break; | |
3792 | ||
3793 | case BFD_RELOC_NONE: | |
3794 | default: | |
3795 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3796 | _("bad or unhandled relocation type: 0x%02x"), | |
3797 | fixP->fx_r_type); | |
3798 | break; | |
3799 | } | |
3800 | ||
3801 | if (INSN_BIG_ENDIAN) | |
3802 | bfd_putb32 (insn, (unsigned char *) buf); | |
3803 | else | |
3804 | bfd_putl32 (insn, (unsigned char *) buf); | |
3805 | } | |
3806 | ||
3807 | /* Are we finished with this relocation now? */ | |
3808 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
3809 | fixP->fx_done = 1; | |
252b5132 RH |
3810 | } |
3811 | ||
3812 | /* Translate internal representation of relocation info to BFD target | |
3813 | format. */ | |
e0c6ed95 | 3814 | |
dabe3bbc | 3815 | arelent ** |
5a49b8ac | 3816 | tc_gen_reloc (asection *section, fixS *fixp) |
252b5132 | 3817 | { |
dabe3bbc | 3818 | static arelent *relocs[3]; |
252b5132 RH |
3819 | arelent *reloc; |
3820 | bfd_reloc_code_real_type code; | |
3821 | ||
add39d23 | 3822 | relocs[0] = reloc = XNEW (arelent); |
dabe3bbc | 3823 | relocs[1] = NULL; |
252b5132 | 3824 | |
add39d23 | 3825 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
49309057 | 3826 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
3827 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3828 | ||
3829 | switch (fixp->fx_r_type) | |
3830 | { | |
3831 | case BFD_RELOC_16: | |
3832 | case BFD_RELOC_32: | |
3833 | case BFD_RELOC_HI22: | |
3834 | case BFD_RELOC_LO10: | |
3835 | case BFD_RELOC_32_PCREL_S2: | |
3836 | case BFD_RELOC_SPARC13: | |
63fab58c | 3837 | case BFD_RELOC_SPARC22: |
1a6b486f DM |
3838 | case BFD_RELOC_SPARC_PC22: |
3839 | case BFD_RELOC_SPARC_PC10: | |
252b5132 | 3840 | case BFD_RELOC_SPARC_BASE13: |
2615994e | 3841 | case BFD_RELOC_SPARC_WDISP10: |
252b5132 RH |
3842 | case BFD_RELOC_SPARC_WDISP16: |
3843 | case BFD_RELOC_SPARC_WDISP19: | |
3844 | case BFD_RELOC_SPARC_WDISP22: | |
3845 | case BFD_RELOC_64: | |
3846 | case BFD_RELOC_SPARC_5: | |
3847 | case BFD_RELOC_SPARC_6: | |
3848 | case BFD_RELOC_SPARC_7: | |
3849 | case BFD_RELOC_SPARC_10: | |
3850 | case BFD_RELOC_SPARC_11: | |
3851 | case BFD_RELOC_SPARC_HH22: | |
3852 | case BFD_RELOC_SPARC_HM10: | |
3853 | case BFD_RELOC_SPARC_LM22: | |
3854 | case BFD_RELOC_SPARC_PC_HH22: | |
3855 | case BFD_RELOC_SPARC_PC_HM10: | |
3856 | case BFD_RELOC_SPARC_PC_LM22: | |
2615994e | 3857 | case BFD_RELOC_SPARC_H34: |
252b5132 RH |
3858 | case BFD_RELOC_SPARC_H44: |
3859 | case BFD_RELOC_SPARC_M44: | |
3860 | case BFD_RELOC_SPARC_L44: | |
3861 | case BFD_RELOC_SPARC_HIX22: | |
3862 | case BFD_RELOC_SPARC_LOX10: | |
3863 | case BFD_RELOC_SPARC_REV32: | |
dabe3bbc | 3864 | case BFD_RELOC_SPARC_OLO10: |
0f2712ed NC |
3865 | case BFD_RELOC_SPARC_UA16: |
3866 | case BFD_RELOC_SPARC_UA32: | |
3867 | case BFD_RELOC_SPARC_UA64: | |
bd5e6e7e JJ |
3868 | case BFD_RELOC_8_PCREL: |
3869 | case BFD_RELOC_16_PCREL: | |
3870 | case BFD_RELOC_32_PCREL: | |
3871 | case BFD_RELOC_64_PCREL: | |
3872 | case BFD_RELOC_SPARC_PLT32: | |
3873 | case BFD_RELOC_SPARC_PLT64: | |
252b5132 RH |
3874 | case BFD_RELOC_VTABLE_ENTRY: |
3875 | case BFD_RELOC_VTABLE_INHERIT: | |
b9734f35 JJ |
3876 | case BFD_RELOC_SPARC_TLS_GD_HI22: |
3877 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3878 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3879 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3880 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3881 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3882 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3883 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3884 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3885 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3886 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3887 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3888 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3889 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3890 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3891 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3892 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3893 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3894 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3895 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
739f7f82 DM |
3896 | case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: |
3897 | case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: | |
3898 | case BFD_RELOC_SPARC_GOTDATA_OP: | |
252b5132 RH |
3899 | code = fixp->fx_r_type; |
3900 | break; | |
3901 | default: | |
3902 | abort (); | |
3903 | return NULL; | |
3904 | } | |
3905 | ||
3906 | #if defined (OBJ_ELF) || defined (OBJ_AOUT) | |
3907 | /* If we are generating PIC code, we need to generate a different | |
3908 | set of relocs. */ | |
3909 | ||
3910 | #ifdef OBJ_ELF | |
3911 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" | |
3912 | #else | |
3913 | #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" | |
910600e9 RS |
3914 | #endif |
3915 | #ifdef TE_VXWORKS | |
3916 | #define GOTT_BASE "__GOTT_BASE__" | |
3917 | #define GOTT_INDEX "__GOTT_INDEX__" | |
252b5132 RH |
3918 | #endif |
3919 | ||
153b546a ILT |
3920 | /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ |
3921 | ||
252b5132 RH |
3922 | if (sparc_pic_code) |
3923 | { | |
3924 | switch (code) | |
3925 | { | |
3926 | case BFD_RELOC_32_PCREL_S2: | |
ae6063d4 | 3927 | if (generic_force_reloc (fixp)) |
252b5132 RH |
3928 | code = BFD_RELOC_SPARC_WPLT30; |
3929 | break; | |
3930 | case BFD_RELOC_HI22: | |
910600e9 RS |
3931 | code = BFD_RELOC_SPARC_GOT22; |
3932 | if (fixp->fx_addsy != NULL) | |
3933 | { | |
3934 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3935 | code = BFD_RELOC_SPARC_PC22; | |
3936 | #ifdef TE_VXWORKS | |
3937 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3938 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3939 | code = BFD_RELOC_HI22; /* Unchanged. */ | |
3940 | #endif | |
3941 | } | |
252b5132 RH |
3942 | break; |
3943 | case BFD_RELOC_LO10: | |
910600e9 RS |
3944 | code = BFD_RELOC_SPARC_GOT10; |
3945 | if (fixp->fx_addsy != NULL) | |
3946 | { | |
3947 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3948 | code = BFD_RELOC_SPARC_PC10; | |
3949 | #ifdef TE_VXWORKS | |
3950 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3951 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3952 | code = BFD_RELOC_LO10; /* Unchanged. */ | |
3953 | #endif | |
3954 | } | |
252b5132 RH |
3955 | break; |
3956 | case BFD_RELOC_SPARC13: | |
3957 | code = BFD_RELOC_SPARC_GOT13; | |
3958 | break; | |
3959 | default: | |
3960 | break; | |
3961 | } | |
3962 | } | |
e0c6ed95 | 3963 | #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ |
252b5132 | 3964 | |
062cf837 EB |
3965 | /* Nothing is aligned in DWARF debugging sections. */ |
3966 | if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) | |
3967 | switch (code) | |
3968 | { | |
3969 | case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; | |
3970 | case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; | |
3971 | case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; | |
3972 | default: break; | |
3973 | } | |
3974 | ||
dabe3bbc RH |
3975 | if (code == BFD_RELOC_SPARC_OLO10) |
3976 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); | |
3977 | else | |
3978 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
252b5132 RH |
3979 | if (reloc->howto == 0) |
3980 | { | |
3981 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3982 | _("internal error: can't export reloc type %d (`%s')"), | |
3983 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); | |
dabe3bbc RH |
3984 | xfree (reloc); |
3985 | relocs[0] = NULL; | |
3986 | return relocs; | |
252b5132 RH |
3987 | } |
3988 | ||
3989 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ | |
3990 | #ifdef OBJ_AOUT | |
3991 | ||
3992 | if (reloc->howto->pc_relative == 0 | |
3993 | || code == BFD_RELOC_SPARC_PC10 | |
3994 | || code == BFD_RELOC_SPARC_PC22) | |
3995 | reloc->addend = fixp->fx_addnumber; | |
3996 | else if (sparc_pic_code | |
3997 | && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3998 | && fixp->fx_addsy != NULL | |
3999 | && (S_IS_EXTERNAL (fixp->fx_addsy) | |
4000 | || S_IS_WEAK (fixp->fx_addsy)) | |
4001 | && S_IS_DEFINED (fixp->fx_addsy) | |
4002 | && ! S_IS_COMMON (fixp->fx_addsy)) | |
4003 | reloc->addend = fixp->fx_addnumber; | |
4004 | else | |
4005 | reloc->addend = fixp->fx_offset - reloc->address; | |
4006 | ||
e0c6ed95 | 4007 | #else /* elf or coff */ |
252b5132 | 4008 | |
bd5e6e7e JJ |
4009 | if (code != BFD_RELOC_32_PCREL_S2 |
4010 | && code != BFD_RELOC_SPARC_WDISP22 | |
4011 | && code != BFD_RELOC_SPARC_WDISP16 | |
4012 | && code != BFD_RELOC_SPARC_WDISP19 | |
2615994e | 4013 | && code != BFD_RELOC_SPARC_WDISP10 |
b9734f35 JJ |
4014 | && code != BFD_RELOC_SPARC_WPLT30 |
4015 | && code != BFD_RELOC_SPARC_TLS_GD_CALL | |
4016 | && code != BFD_RELOC_SPARC_TLS_LDM_CALL) | |
252b5132 | 4017 | reloc->addend = fixp->fx_addnumber; |
49309057 | 4018 | else if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
4019 | reloc->addend = (section->vma |
4020 | + fixp->fx_addnumber | |
4021 | + md_pcrel_from (fixp)); | |
4022 | else | |
4023 | reloc->addend = fixp->fx_offset; | |
4024 | #endif | |
4025 | ||
dabe3bbc RH |
4026 | /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 |
4027 | on the same location. */ | |
4028 | if (code == BFD_RELOC_SPARC_OLO10) | |
4029 | { | |
add39d23 | 4030 | relocs[1] = reloc = XNEW (arelent); |
dabe3bbc RH |
4031 | relocs[2] = NULL; |
4032 | ||
add39d23 | 4033 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
ab3e48dc KH |
4034 | *reloc->sym_ptr_ptr |
4035 | = symbol_get_bfdsym (section_symbol (absolute_section)); | |
dabe3bbc RH |
4036 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
4037 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); | |
4038 | reloc->addend = fixp->tc_fix_data; | |
4039 | } | |
4040 | ||
4041 | return relocs; | |
252b5132 RH |
4042 | } |
4043 | \f | |
e0c6ed95 | 4044 | /* We have no need to default values of symbols. */ |
252b5132 | 4045 | |
252b5132 | 4046 | symbolS * |
5a49b8ac | 4047 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
4048 | { |
4049 | return 0; | |
e0c6ed95 AM |
4050 | } |
4051 | ||
4052 | /* Round up a section size to the appropriate boundary. */ | |
252b5132 | 4053 | |
252b5132 | 4054 | valueT |
5a49b8ac | 4055 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 RH |
4056 | { |
4057 | #ifndef OBJ_ELF | |
4058 | /* This is not right for ELF; a.out wants it, and COFF will force | |
4059 | the alignment anyways. */ | |
4060 | valueT align = ((valueT) 1 | |
4061 | << (valueT) bfd_get_section_alignment (stdoutput, segment)); | |
4062 | valueT newsize; | |
e0c6ed95 AM |
4063 | |
4064 | /* Turn alignment value into a mask. */ | |
252b5132 RH |
4065 | align--; |
4066 | newsize = (size + align) & ~align; | |
4067 | return newsize; | |
4068 | #else | |
4069 | return size; | |
4070 | #endif | |
4071 | } | |
4072 | ||
4073 | /* Exactly what point is a PC-relative offset relative TO? | |
4074 | On the sparc, they're relative to the address of the offset, plus | |
4075 | its size. This gets us to the following instruction. | |
e0c6ed95 AM |
4076 | (??? Is this right? FIXME-SOON) */ |
4077 | long | |
5a49b8ac | 4078 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
4079 | { |
4080 | long ret; | |
4081 | ||
4082 | ret = fixP->fx_where + fixP->fx_frag->fr_address; | |
4083 | if (! sparc_pic_code | |
4084 | || fixP->fx_addsy == NULL | |
49309057 | 4085 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
4086 | ret += fixP->fx_size; |
4087 | return ret; | |
4088 | } | |
4089 | \f | |
4090 | /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power | |
4091 | of two. */ | |
4092 | ||
4093 | static int | |
5a49b8ac | 4094 | mylog2 (int value) |
252b5132 RH |
4095 | { |
4096 | int shift; | |
4097 | ||
4098 | if (value <= 0) | |
4099 | return -1; | |
4100 | ||
4101 | for (shift = 0; (value & 1) == 0; value >>= 1) | |
4102 | ++shift; | |
4103 | ||
4104 | return (value == 1) ? shift : -1; | |
4105 | } | |
4106 | ||
e0c6ed95 | 4107 | /* Sort of like s_lcomm. */ |
252b5132 RH |
4108 | |
4109 | #ifndef OBJ_ELF | |
4110 | static int max_alignment = 15; | |
4111 | #endif | |
4112 | ||
4113 | static void | |
5a49b8ac | 4114 | s_reserve (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4115 | { |
4116 | char *name; | |
4117 | char *p; | |
4118 | char c; | |
4119 | int align; | |
4120 | int size; | |
4121 | int temp; | |
4122 | symbolS *symbolP; | |
4123 | ||
d02603dc | 4124 | c = get_symbol_name (&name); |
252b5132 RH |
4125 | p = input_line_pointer; |
4126 | *p = c; | |
d02603dc | 4127 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
4128 | |
4129 | if (*input_line_pointer != ',') | |
4130 | { | |
4131 | as_bad (_("Expected comma after name")); | |
4132 | ignore_rest_of_line (); | |
4133 | return; | |
4134 | } | |
4135 | ||
4136 | ++input_line_pointer; | |
4137 | ||
4138 | if ((size = get_absolute_expression ()) < 0) | |
4139 | { | |
4140 | as_bad (_("BSS length (%d.) <0! Ignored."), size); | |
4141 | ignore_rest_of_line (); | |
4142 | return; | |
e0c6ed95 | 4143 | } /* Bad length. */ |
252b5132 RH |
4144 | |
4145 | *p = 0; | |
4146 | symbolP = symbol_find_or_make (name); | |
4147 | *p = c; | |
4148 | ||
4149 | if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 | |
4150 | && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) | |
4151 | { | |
4152 | as_bad (_("bad .reserve segment -- expected BSS segment")); | |
4153 | return; | |
4154 | } | |
4155 | ||
4156 | if (input_line_pointer[2] == '.') | |
4157 | input_line_pointer += 7; | |
4158 | else | |
4159 | input_line_pointer += 6; | |
4160 | SKIP_WHITESPACE (); | |
4161 | ||
4162 | if (*input_line_pointer == ',') | |
4163 | { | |
4164 | ++input_line_pointer; | |
4165 | ||
4166 | SKIP_WHITESPACE (); | |
4167 | if (*input_line_pointer == '\n') | |
4168 | { | |
4169 | as_bad (_("missing alignment")); | |
4170 | ignore_rest_of_line (); | |
4171 | return; | |
4172 | } | |
4173 | ||
4174 | align = (int) get_absolute_expression (); | |
4175 | ||
4176 | #ifndef OBJ_ELF | |
4177 | if (align > max_alignment) | |
4178 | { | |
4179 | align = max_alignment; | |
4180 | as_warn (_("alignment too large; assuming %d"), align); | |
4181 | } | |
4182 | #endif | |
4183 | ||
4184 | if (align < 0) | |
4185 | { | |
4186 | as_bad (_("negative alignment")); | |
4187 | ignore_rest_of_line (); | |
4188 | return; | |
4189 | } | |
4190 | ||
4191 | if (align != 0) | |
4192 | { | |
f17c130b | 4193 | temp = mylog2 (align); |
252b5132 RH |
4194 | if (temp < 0) |
4195 | { | |
4196 | as_bad (_("alignment not a power of 2")); | |
4197 | ignore_rest_of_line (); | |
4198 | return; | |
4199 | } | |
4200 | ||
4201 | align = temp; | |
4202 | } | |
4203 | ||
4204 | record_alignment (bss_section, align); | |
4205 | } | |
4206 | else | |
4207 | align = 0; | |
4208 | ||
4209 | if (!S_IS_DEFINED (symbolP) | |
4210 | #ifdef OBJ_AOUT | |
4211 | && S_GET_OTHER (symbolP) == 0 | |
4212 | && S_GET_DESC (symbolP) == 0 | |
4213 | #endif | |
4214 | ) | |
4215 | { | |
4216 | if (! need_pass_2) | |
4217 | { | |
4218 | char *pfrag; | |
4219 | segT current_seg = now_seg; | |
4220 | subsegT current_subseg = now_subseg; | |
4221 | ||
e0c6ed95 AM |
4222 | /* Switch to bss. */ |
4223 | subseg_set (bss_section, 1); | |
252b5132 RH |
4224 | |
4225 | if (align) | |
e0c6ed95 AM |
4226 | /* Do alignment. */ |
4227 | frag_align (align, 0, 0); | |
252b5132 | 4228 | |
e0c6ed95 | 4229 | /* Detach from old frag. */ |
ab3e48dc | 4230 | if (S_GET_SEGMENT (symbolP) == bss_section) |
49309057 | 4231 | symbol_get_frag (symbolP)->fr_symbol = NULL; |
252b5132 | 4232 | |
49309057 | 4233 | symbol_set_frag (symbolP, frag_now); |
e0c6ed95 AM |
4234 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
4235 | (offsetT) size, (char *) 0); | |
252b5132 RH |
4236 | *pfrag = 0; |
4237 | ||
4238 | S_SET_SEGMENT (symbolP, bss_section); | |
4239 | ||
4240 | subseg_set (current_seg, current_subseg); | |
4241 | ||
4242 | #ifdef OBJ_ELF | |
4243 | S_SET_SIZE (symbolP, size); | |
4244 | #endif | |
4245 | } | |
4246 | } | |
4247 | else | |
4248 | { | |
20203fb9 | 4249 | as_warn (_("Ignoring attempt to re-define symbol %s"), |
ab3e48dc | 4250 | S_GET_NAME (symbolP)); |
20203fb9 | 4251 | } |
252b5132 RH |
4252 | |
4253 | demand_empty_rest_of_line (); | |
4254 | } | |
4255 | ||
4256 | static void | |
5a49b8ac | 4257 | s_common (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4258 | { |
4259 | char *name; | |
4260 | char c; | |
4261 | char *p; | |
685736be | 4262 | offsetT temp, size; |
252b5132 RH |
4263 | symbolS *symbolP; |
4264 | ||
d02603dc | 4265 | c = get_symbol_name (&name); |
e0c6ed95 | 4266 | /* Just after name is now '\0'. */ |
252b5132 RH |
4267 | p = input_line_pointer; |
4268 | *p = c; | |
d02603dc | 4269 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
4270 | if (*input_line_pointer != ',') |
4271 | { | |
4272 | as_bad (_("Expected comma after symbol-name")); | |
4273 | ignore_rest_of_line (); | |
4274 | return; | |
4275 | } | |
e0c6ed95 AM |
4276 | |
4277 | /* Skip ','. */ | |
4278 | input_line_pointer++; | |
4279 | ||
252b5132 RH |
4280 | if ((temp = get_absolute_expression ()) < 0) |
4281 | { | |
685736be NC |
4282 | as_bad (_(".COMMon length (%lu) out of range ignored"), |
4283 | (unsigned long) temp); | |
252b5132 RH |
4284 | ignore_rest_of_line (); |
4285 | return; | |
4286 | } | |
4287 | size = temp; | |
4288 | *p = 0; | |
4289 | symbolP = symbol_find_or_make (name); | |
4290 | *p = c; | |
4291 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
4292 | { | |
4293 | as_bad (_("Ignoring attempt to re-define symbol")); | |
4294 | ignore_rest_of_line (); | |
4295 | return; | |
4296 | } | |
4297 | if (S_GET_VALUE (symbolP) != 0) | |
4298 | { | |
4299 | if (S_GET_VALUE (symbolP) != (valueT) size) | |
4300 | { | |
364b6d8b JJ |
4301 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), |
4302 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); | |
252b5132 RH |
4303 | } |
4304 | } | |
4305 | else | |
4306 | { | |
4307 | #ifndef OBJ_ELF | |
4308 | S_SET_VALUE (symbolP, (valueT) size); | |
4309 | S_SET_EXTERNAL (symbolP); | |
4310 | #endif | |
4311 | } | |
7dcc9865 | 4312 | know (symbol_get_frag (symbolP) == &zero_address_frag); |
252b5132 RH |
4313 | if (*input_line_pointer != ',') |
4314 | { | |
4315 | as_bad (_("Expected comma after common length")); | |
4316 | ignore_rest_of_line (); | |
4317 | return; | |
4318 | } | |
4319 | input_line_pointer++; | |
4320 | SKIP_WHITESPACE (); | |
4321 | if (*input_line_pointer != '"') | |
4322 | { | |
4323 | temp = get_absolute_expression (); | |
4324 | ||
4325 | #ifndef OBJ_ELF | |
4326 | if (temp > max_alignment) | |
4327 | { | |
4328 | temp = max_alignment; | |
f17c130b | 4329 | as_warn (_("alignment too large; assuming %ld"), (long) temp); |
252b5132 RH |
4330 | } |
4331 | #endif | |
4332 | ||
4333 | if (temp < 0) | |
4334 | { | |
4335 | as_bad (_("negative alignment")); | |
4336 | ignore_rest_of_line (); | |
4337 | return; | |
4338 | } | |
4339 | ||
4340 | #ifdef OBJ_ELF | |
49309057 | 4341 | if (symbol_get_obj (symbolP)->local) |
252b5132 RH |
4342 | { |
4343 | segT old_sec; | |
4344 | int old_subsec; | |
252b5132 RH |
4345 | int align; |
4346 | ||
4347 | old_sec = now_seg; | |
4348 | old_subsec = now_subseg; | |
4349 | ||
4350 | if (temp == 0) | |
4351 | align = 0; | |
4352 | else | |
f17c130b | 4353 | align = mylog2 (temp); |
252b5132 RH |
4354 | |
4355 | if (align < 0) | |
4356 | { | |
4357 | as_bad (_("alignment not a power of 2")); | |
4358 | ignore_rest_of_line (); | |
4359 | return; | |
4360 | } | |
4361 | ||
4362 | record_alignment (bss_section, align); | |
4363 | subseg_set (bss_section, 0); | |
4364 | if (align) | |
4365 | frag_align (align, 0, 0); | |
4366 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
4367 | symbol_get_frag (symbolP)->fr_symbol = 0; |
4368 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
4369 | p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
4370 | (offsetT) size, (char *) 0); | |
4371 | *p = 0; | |
4372 | S_SET_SEGMENT (symbolP, bss_section); | |
4373 | S_CLEAR_EXTERNAL (symbolP); | |
4374 | S_SET_SIZE (symbolP, size); | |
4375 | subseg_set (old_sec, old_subsec); | |
4376 | } | |
4377 | else | |
e0c6ed95 | 4378 | #endif /* OBJ_ELF */ |
252b5132 RH |
4379 | { |
4380 | allocate_common: | |
4381 | S_SET_VALUE (symbolP, (valueT) size); | |
4382 | #ifdef OBJ_ELF | |
4383 | S_SET_ALIGN (symbolP, temp); | |
4384 | S_SET_SIZE (symbolP, size); | |
4385 | #endif | |
4386 | S_SET_EXTERNAL (symbolP); | |
4387 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); | |
4388 | } | |
4389 | } | |
4390 | else | |
4391 | { | |
4392 | input_line_pointer++; | |
4393 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ | |
4394 | if (*input_line_pointer == '.') | |
4395 | input_line_pointer++; | |
4396 | /* @@ Some say data, some say bss. */ | |
4397 | if (strncmp (input_line_pointer, "bss\"", 4) | |
4398 | && strncmp (input_line_pointer, "data\"", 5)) | |
4399 | { | |
4400 | while (*--input_line_pointer != '"') | |
4401 | ; | |
4402 | input_line_pointer--; | |
4403 | goto bad_common_segment; | |
4404 | } | |
4405 | while (*input_line_pointer++ != '"') | |
4406 | ; | |
4407 | goto allocate_common; | |
4408 | } | |
4409 | ||
49309057 | 4410 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; |
252b5132 RH |
4411 | |
4412 | demand_empty_rest_of_line (); | |
4413 | return; | |
4414 | ||
4415 | { | |
4416 | bad_common_segment: | |
4417 | p = input_line_pointer; | |
4418 | while (*p && *p != '\n') | |
4419 | p++; | |
4420 | c = *p; | |
4421 | *p = '\0'; | |
4422 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); | |
4423 | *p = c; | |
4424 | input_line_pointer = p; | |
4425 | ignore_rest_of_line (); | |
4426 | return; | |
4427 | } | |
4428 | } | |
4429 | ||
67c1ffbe | 4430 | /* Handle the .empty pseudo-op. This suppresses the warnings about |
252b5132 RH |
4431 | invalid delay slot usage. */ |
4432 | ||
4433 | static void | |
5a49b8ac | 4434 | s_empty (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4435 | { |
4436 | /* The easy way to implement is to just forget about the last | |
4437 | instruction. */ | |
4438 | last_insn = NULL; | |
4439 | } | |
4440 | ||
4441 | static void | |
5a49b8ac | 4442 | s_seg (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4443 | { |
4444 | ||
4445 | if (strncmp (input_line_pointer, "\"text\"", 6) == 0) | |
4446 | { | |
4447 | input_line_pointer += 6; | |
4448 | s_text (0); | |
4449 | return; | |
4450 | } | |
4451 | if (strncmp (input_line_pointer, "\"data\"", 6) == 0) | |
4452 | { | |
4453 | input_line_pointer += 6; | |
4454 | s_data (0); | |
4455 | return; | |
4456 | } | |
4457 | if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) | |
4458 | { | |
4459 | input_line_pointer += 7; | |
4460 | s_data1 (); | |
4461 | return; | |
4462 | } | |
4463 | if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) | |
4464 | { | |
4465 | input_line_pointer += 5; | |
4466 | /* We only support 2 segments -- text and data -- for now, so | |
4467 | things in the "bss segment" will have to go into data for now. | |
e0c6ed95 AM |
4468 | You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ |
4469 | subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ | |
252b5132 RH |
4470 | return; |
4471 | } | |
4472 | as_bad (_("Unknown segment type")); | |
4473 | demand_empty_rest_of_line (); | |
4474 | } | |
4475 | ||
4476 | static void | |
5a49b8ac | 4477 | s_data1 (void) |
252b5132 RH |
4478 | { |
4479 | subseg_set (data_section, 1); | |
4480 | demand_empty_rest_of_line (); | |
4481 | } | |
4482 | ||
4483 | static void | |
5a49b8ac | 4484 | s_proc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4485 | { |
4486 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4487 | { | |
4488 | ++input_line_pointer; | |
4489 | } | |
4490 | ++input_line_pointer; | |
4491 | } | |
4492 | ||
4493 | /* This static variable is set by s_uacons to tell sparc_cons_align | |
67c1ffbe | 4494 | that the expression does not need to be aligned. */ |
252b5132 RH |
4495 | |
4496 | static int sparc_no_align_cons = 0; | |
4497 | ||
4498 | /* This handles the unaligned space allocation pseudo-ops, such as | |
4499 | .uaword. .uaword is just like .word, but the value does not need | |
4500 | to be aligned. */ | |
4501 | ||
4502 | static void | |
5a49b8ac | 4503 | s_uacons (int bytes) |
252b5132 RH |
4504 | { |
4505 | /* Tell sparc_cons_align not to align this value. */ | |
4506 | sparc_no_align_cons = 1; | |
4507 | cons (bytes); | |
4ffadb11 | 4508 | sparc_no_align_cons = 0; |
252b5132 RH |
4509 | } |
4510 | ||
cf9a1301 RH |
4511 | /* This handles the native word allocation pseudo-op .nword. |
4512 | For sparc_arch_size 32 it is equivalent to .word, for | |
4513 | sparc_arch_size 64 it is equivalent to .xword. */ | |
4514 | ||
4515 | static void | |
5a49b8ac | 4516 | s_ncons (int bytes ATTRIBUTE_UNUSED) |
cf9a1301 RH |
4517 | { |
4518 | cons (sparc_arch_size == 32 ? 4 : 8); | |
4519 | } | |
4520 | ||
6d8809aa RH |
4521 | #ifdef OBJ_ELF |
4522 | /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a | |
4523 | global register. | |
4524 | The syntax is: | |
e0c6ed95 | 4525 | |
6d8809aa | 4526 | .register %g[2367],{#scratch|symbolname|#ignore} |
e0c6ed95 | 4527 | */ |
6d8809aa RH |
4528 | |
4529 | static void | |
5a49b8ac | 4530 | s_register (int ignore ATTRIBUTE_UNUSED) |
6d8809aa RH |
4531 | { |
4532 | char c; | |
4533 | int reg; | |
4534 | int flags; | |
d02603dc | 4535 | char *regname; |
6d8809aa RH |
4536 | |
4537 | if (input_line_pointer[0] != '%' | |
4538 | || input_line_pointer[1] != 'g' | |
4539 | || ((input_line_pointer[2] & ~1) != '2' | |
4540 | && (input_line_pointer[2] & ~1) != '6') | |
4541 | || input_line_pointer[3] != ',') | |
4542 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
4543 | reg = input_line_pointer[2] - '0'; | |
4544 | input_line_pointer += 4; | |
4545 | ||
4546 | if (*input_line_pointer == '#') | |
4547 | { | |
4548 | ++input_line_pointer; | |
d02603dc | 4549 | c = get_symbol_name (®name); |
6d8809aa RH |
4550 | if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) |
4551 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
ab3e48dc | 4552 | if (regname[0] == 'i') |
6d8809aa RH |
4553 | regname = NULL; |
4554 | else | |
e87de513 | 4555 | regname = (char *) ""; |
6d8809aa RH |
4556 | } |
4557 | else | |
4558 | { | |
d02603dc | 4559 | c = get_symbol_name (®name); |
6d8809aa | 4560 | } |
d02603dc | 4561 | |
6d8809aa RH |
4562 | if (sparc_arch_size == 64) |
4563 | { | |
e0c6ed95 | 4564 | if (globals[reg]) |
6d8809aa | 4565 | { |
e0c6ed95 AM |
4566 | if ((regname && globals[reg] != (symbolS *) 1 |
4567 | && strcmp (S_GET_NAME (globals[reg]), regname)) | |
4568 | || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) | |
6d8809aa RH |
4569 | as_bad (_("redefinition of global register")); |
4570 | } | |
4571 | else | |
4572 | { | |
4573 | if (regname == NULL) | |
e0c6ed95 | 4574 | globals[reg] = (symbolS *) 1; |
6d8809aa RH |
4575 | else |
4576 | { | |
4577 | if (*regname) | |
4578 | { | |
4579 | if (symbol_find (regname)) | |
4580 | as_bad (_("Register symbol %s already defined."), | |
4581 | regname); | |
4582 | } | |
e0c6ed95 AM |
4583 | globals[reg] = symbol_make (regname); |
4584 | flags = symbol_get_bfdsym (globals[reg])->flags; | |
6d8809aa RH |
4585 | if (! *regname) |
4586 | flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); | |
4587 | if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) | |
4588 | flags |= BSF_GLOBAL; | |
e0c6ed95 AM |
4589 | symbol_get_bfdsym (globals[reg])->flags = flags; |
4590 | S_SET_VALUE (globals[reg], (valueT) reg); | |
4591 | S_SET_ALIGN (globals[reg], reg); | |
4592 | S_SET_SIZE (globals[reg], 0); | |
6d8809aa RH |
4593 | /* Although we actually want undefined_section here, |
4594 | we have to use absolute_section, because otherwise | |
4595 | generic as code will make it a COM section. | |
4596 | We fix this up in sparc_adjust_symtab. */ | |
e0c6ed95 AM |
4597 | S_SET_SEGMENT (globals[reg], absolute_section); |
4598 | S_SET_OTHER (globals[reg], 0); | |
4599 | elf_symbol (symbol_get_bfdsym (globals[reg])) | |
6d8809aa RH |
4600 | ->internal_elf_sym.st_info = |
4601 | ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); | |
e0c6ed95 | 4602 | elf_symbol (symbol_get_bfdsym (globals[reg])) |
6d8809aa RH |
4603 | ->internal_elf_sym.st_shndx = SHN_UNDEF; |
4604 | } | |
4605 | } | |
4606 | } | |
4607 | ||
d02603dc | 4608 | (void) restore_line_pointer (c); |
6d8809aa RH |
4609 | |
4610 | demand_empty_rest_of_line (); | |
4611 | } | |
4612 | ||
4613 | /* Adjust the symbol table. We set undefined sections for STT_REGISTER | |
4614 | symbols which need it. */ | |
e0c6ed95 | 4615 | |
6d8809aa | 4616 | void |
5a49b8ac | 4617 | sparc_adjust_symtab (void) |
6d8809aa RH |
4618 | { |
4619 | symbolS *sym; | |
e0c6ed95 | 4620 | |
6d8809aa RH |
4621 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
4622 | { | |
4623 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4624 | ->internal_elf_sym.st_info) != STT_REGISTER) | |
4625 | continue; | |
4626 | ||
4627 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4628 | ->internal_elf_sym.st_shndx != SHN_UNDEF)) | |
4629 | continue; | |
4630 | ||
4631 | S_SET_SEGMENT (sym, undefined_section); | |
4632 | } | |
4633 | } | |
4634 | #endif | |
4635 | ||
252b5132 RH |
4636 | /* If the --enforce-aligned-data option is used, we require .word, |
4637 | et. al., to be aligned correctly. We do it by setting up an | |
4638 | rs_align_code frag, and checking in HANDLE_ALIGN to make sure that | |
4639 | no unexpected alignment was introduced. | |
4640 | ||
4641 | The SunOS and Solaris native assemblers enforce aligned data by | |
4642 | default. We don't want to do that, because gcc can deliberately | |
4643 | generate misaligned data if the packed attribute is used. Instead, | |
4644 | we permit misaligned data by default, and permit the user to set an | |
4645 | option to check for it. */ | |
4646 | ||
4647 | void | |
5a49b8ac | 4648 | sparc_cons_align (int nbytes) |
252b5132 RH |
4649 | { |
4650 | int nalign; | |
252b5132 RH |
4651 | |
4652 | /* Only do this if we are enforcing aligned data. */ | |
4653 | if (! enforce_aligned_data) | |
4654 | return; | |
4655 | ||
0f2712ed | 4656 | /* Don't align if this is an unaligned pseudo-op. */ |
252b5132 | 4657 | if (sparc_no_align_cons) |
0f2712ed | 4658 | return; |
252b5132 | 4659 | |
f17c130b | 4660 | nalign = mylog2 (nbytes); |
252b5132 RH |
4661 | if (nalign == 0) |
4662 | return; | |
4663 | ||
9c2799c2 | 4664 | gas_assert (nalign > 0); |
252b5132 RH |
4665 | |
4666 | if (now_seg == absolute_section) | |
4667 | { | |
4668 | if ((abs_section_offset & ((1 << nalign) - 1)) != 0) | |
4669 | as_bad (_("misaligned data")); | |
4670 | return; | |
4671 | } | |
4672 | ||
87975d2a AM |
4673 | frag_var (rs_align_test, 1, 1, (relax_substateT) 0, |
4674 | (symbolS *) NULL, (offsetT) nalign, (char *) NULL); | |
252b5132 RH |
4675 | |
4676 | record_alignment (now_seg, nalign); | |
4677 | } | |
4678 | ||
0a9ef439 | 4679 | /* This is called from HANDLE_ALIGN in tc-sparc.h. */ |
252b5132 RH |
4680 | |
4681 | void | |
5a49b8ac | 4682 | sparc_handle_align (fragS *fragp) |
252b5132 | 4683 | { |
0a9ef439 RH |
4684 | int count, fix; |
4685 | char *p; | |
4686 | ||
4687 | count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
bfb32b52 | 4688 | |
0a9ef439 | 4689 | switch (fragp->fr_type) |
252b5132 | 4690 | { |
0a9ef439 RH |
4691 | case rs_align_test: |
4692 | if (count != 0) | |
4693 | as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); | |
4694 | break; | |
e0c6ed95 | 4695 | |
0a9ef439 RH |
4696 | case rs_align_code: |
4697 | p = fragp->fr_literal + fragp->fr_fix; | |
4698 | fix = 0; | |
e0c6ed95 | 4699 | |
0a9ef439 RH |
4700 | if (count & 3) |
4701 | { | |
4702 | fix = count & 3; | |
4703 | memset (p, 0, fix); | |
4704 | p += fix; | |
4705 | count -= fix; | |
4706 | } | |
e0c6ed95 | 4707 | |
0a9ef439 RH |
4708 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) |
4709 | { | |
4710 | unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ | |
4711 | if (INSN_BIG_ENDIAN) | |
4712 | number_to_chars_bigendian (p, wval, 4); | |
4713 | else | |
4714 | number_to_chars_littleendian (p, wval, 4); | |
4715 | p += 4; | |
4716 | count -= 4; | |
4717 | fix += 4; | |
e0c6ed95 | 4718 | } |
0a9ef439 RH |
4719 | |
4720 | if (INSN_BIG_ENDIAN) | |
4721 | number_to_chars_bigendian (p, 0x01000000, 4); | |
4722 | else | |
4723 | number_to_chars_littleendian (p, 0x01000000, 4); | |
4724 | ||
4725 | fragp->fr_fix += fix; | |
4726 | fragp->fr_var = 4; | |
4727 | break; | |
4728 | ||
4729 | default: | |
4730 | break; | |
252b5132 RH |
4731 | } |
4732 | } | |
4733 | ||
4734 | #ifdef OBJ_ELF | |
4735 | /* Some special processing for a Sparc ELF file. */ | |
4736 | ||
4737 | void | |
5a49b8ac | 4738 | sparc_elf_final_processing (void) |
252b5132 RH |
4739 | { |
4740 | /* Set the Sparc ELF flag bits. FIXME: There should probably be some | |
4741 | sort of BFD interface for this. */ | |
4742 | if (sparc_arch_size == 64) | |
4743 | { | |
4744 | switch (sparc_memory_model) | |
4745 | { | |
4746 | case MM_RMO: | |
4747 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; | |
4748 | break; | |
4749 | case MM_PSO: | |
4750 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; | |
4751 | break; | |
4752 | default: | |
4753 | break; | |
4754 | } | |
4755 | } | |
4756 | else if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
4757 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; | |
4758 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
4759 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; | |
19f7b010 JJ |
4760 | else if (current_architecture == SPARC_OPCODE_ARCH_V9B) |
4761 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; | |
252b5132 | 4762 | } |
bd5e6e7e | 4763 | |
62ebcb5c | 4764 | const char * |
5a49b8ac | 4765 | sparc_cons (expressionS *exp, int size) |
bd5e6e7e JJ |
4766 | { |
4767 | char *save; | |
62ebcb5c | 4768 | const char *sparc_cons_special_reloc = NULL; |
bd5e6e7e JJ |
4769 | |
4770 | SKIP_WHITESPACE (); | |
bd5e6e7e JJ |
4771 | save = input_line_pointer; |
4772 | if (input_line_pointer[0] == '%' | |
4773 | && input_line_pointer[1] == 'r' | |
4774 | && input_line_pointer[2] == '_') | |
4775 | { | |
4776 | if (strncmp (input_line_pointer + 3, "disp", 4) == 0) | |
4777 | { | |
4778 | input_line_pointer += 7; | |
4779 | sparc_cons_special_reloc = "disp"; | |
4780 | } | |
4781 | else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) | |
4782 | { | |
4783 | if (size != 4 && size != 8) | |
4784 | as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); | |
4785 | else | |
4786 | { | |
4787 | input_line_pointer += 6; | |
4788 | sparc_cons_special_reloc = "plt"; | |
4789 | } | |
4790 | } | |
b9734f35 JJ |
4791 | else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) |
4792 | { | |
4793 | if (size != 4 && size != 8) | |
4794 | as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); | |
4795 | else | |
4796 | { | |
4797 | input_line_pointer += 13; | |
4798 | sparc_cons_special_reloc = "tls_dtpoff"; | |
4799 | } | |
4800 | } | |
bd5e6e7e JJ |
4801 | if (sparc_cons_special_reloc) |
4802 | { | |
4803 | int bad = 0; | |
4804 | ||
4805 | switch (size) | |
4806 | { | |
4807 | case 1: | |
4808 | if (*input_line_pointer != '8') | |
4809 | bad = 1; | |
4810 | input_line_pointer--; | |
4811 | break; | |
4812 | case 2: | |
4813 | if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') | |
4814 | bad = 1; | |
4815 | break; | |
4816 | case 4: | |
4817 | if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') | |
4818 | bad = 1; | |
4819 | break; | |
4820 | case 8: | |
4821 | if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') | |
4822 | bad = 1; | |
4823 | break; | |
4824 | default: | |
4825 | bad = 1; | |
4826 | break; | |
4827 | } | |
4828 | ||
4829 | if (bad) | |
4830 | { | |
4831 | as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), | |
4832 | sparc_cons_special_reloc, size * 8, size); | |
4833 | } | |
4834 | else | |
4835 | { | |
4836 | input_line_pointer += 2; | |
4837 | if (*input_line_pointer != '(') | |
4838 | { | |
4839 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4840 | sparc_cons_special_reloc, size * 8); | |
4841 | bad = 1; | |
4842 | } | |
4843 | } | |
4844 | ||
4845 | if (bad) | |
4846 | { | |
4847 | input_line_pointer = save; | |
4848 | sparc_cons_special_reloc = NULL; | |
4849 | } | |
4850 | else | |
4851 | { | |
4852 | int c; | |
4853 | char *end = ++input_line_pointer; | |
4854 | int npar = 0; | |
4855 | ||
4856 | while (! is_end_of_line[(c = *end)]) | |
4857 | { | |
4858 | if (c == '(') | |
4859 | npar++; | |
4860 | else if (c == ')') | |
4861 | { | |
4862 | if (!npar) | |
4863 | break; | |
4864 | npar--; | |
4865 | } | |
4866 | end++; | |
4867 | } | |
4868 | ||
4869 | if (c != ')') | |
4870 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4871 | sparc_cons_special_reloc, size * 8); | |
4872 | else | |
4873 | { | |
4874 | *end = '\0'; | |
4875 | expression (exp); | |
4876 | *end = c; | |
4877 | if (input_line_pointer != end) | |
4878 | { | |
4879 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4880 | sparc_cons_special_reloc, size * 8); | |
4881 | } | |
4882 | else | |
4883 | { | |
4884 | input_line_pointer++; | |
4885 | SKIP_WHITESPACE (); | |
4886 | c = *input_line_pointer; | |
4887 | if (! is_end_of_line[c] && c != ',') | |
4888 | as_bad (_("Illegal operands: garbage after %%r_%s%d()"), | |
4889 | sparc_cons_special_reloc, size * 8); | |
4890 | } | |
4891 | } | |
4892 | } | |
4893 | } | |
4894 | } | |
4895 | if (sparc_cons_special_reloc == NULL) | |
4896 | expression (exp); | |
62ebcb5c | 4897 | return sparc_cons_special_reloc; |
bd5e6e7e JJ |
4898 | } |
4899 | ||
252b5132 RH |
4900 | #endif |
4901 | ||
4902 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
4903 | reloc for a cons. We could use the definition there, except that | |
4904 | we want to handle little endian relocs specially. */ | |
4905 | ||
4906 | void | |
5a49b8ac AM |
4907 | cons_fix_new_sparc (fragS *frag, |
4908 | int where, | |
4909 | unsigned int nbytes, | |
62ebcb5c AM |
4910 | expressionS *exp, |
4911 | const char *sparc_cons_special_reloc) | |
252b5132 RH |
4912 | { |
4913 | bfd_reloc_code_real_type r; | |
4914 | ||
4915 | r = (nbytes == 1 ? BFD_RELOC_8 : | |
4916 | (nbytes == 2 ? BFD_RELOC_16 : | |
4917 | (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
4918 | ||
0f2712ed NC |
4919 | if (target_little_endian_data |
4920 | && nbytes == 4 | |
e0c6ed95 | 4921 | && now_seg->flags & SEC_ALLOC) |
252b5132 | 4922 | r = BFD_RELOC_SPARC_REV32; |
0f2712ed | 4923 | |
02442566 ST |
4924 | #ifdef TE_SOLARIS |
4925 | /* The Solaris linker does not allow R_SPARC_UA64 | |
4926 | relocations for 32-bit executables. */ | |
4927 | if (!target_little_endian_data | |
4928 | && sparc_arch_size != 64 | |
4929 | && r == BFD_RELOC_64) | |
4930 | r = BFD_RELOC_32; | |
4931 | #endif | |
4932 | ||
bd5e6e7e JJ |
4933 | if (sparc_cons_special_reloc) |
4934 | { | |
4935 | if (*sparc_cons_special_reloc == 'd') | |
4936 | switch (nbytes) | |
4937 | { | |
4938 | case 1: r = BFD_RELOC_8_PCREL; break; | |
4939 | case 2: r = BFD_RELOC_16_PCREL; break; | |
4940 | case 4: r = BFD_RELOC_32_PCREL; break; | |
4941 | case 8: r = BFD_RELOC_64_PCREL; break; | |
4942 | default: abort (); | |
4943 | } | |
b9734f35 | 4944 | else if (*sparc_cons_special_reloc == 'p') |
bd5e6e7e JJ |
4945 | switch (nbytes) |
4946 | { | |
4947 | case 4: r = BFD_RELOC_SPARC_PLT32; break; | |
4948 | case 8: r = BFD_RELOC_SPARC_PLT64; break; | |
4949 | } | |
b9734f35 JJ |
4950 | else |
4951 | switch (nbytes) | |
4952 | { | |
4953 | case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; | |
4954 | case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; | |
4955 | } | |
bd5e6e7e | 4956 | } |
93ca3936 NC |
4957 | else if (sparc_no_align_cons |
4958 | || /* PR 20803 - relocs in the .eh_frame section | |
4959 | need to support unaligned access. */ | |
4960 | strcmp (now_seg->name, ".eh_frame") == 0) | |
0f2712ed NC |
4961 | { |
4962 | switch (nbytes) | |
4963 | { | |
4964 | case 2: r = BFD_RELOC_SPARC_UA16; break; | |
4965 | case 4: r = BFD_RELOC_SPARC_UA32; break; | |
02442566 ST |
4966 | #ifdef TE_SOLARIS |
4967 | /* The Solaris linker does not allow R_SPARC_UA64 | |
4968 | relocations for 32-bit executables. */ | |
4969 | case 8: r = sparc_arch_size == 64 ? | |
4970 | BFD_RELOC_SPARC_UA64 : BFD_RELOC_SPARC_UA32; break; | |
4971 | #else | |
0f2712ed | 4972 | case 8: r = BFD_RELOC_SPARC_UA64; break; |
02442566 | 4973 | #endif |
0f2712ed NC |
4974 | default: abort (); |
4975 | } | |
4ffadb11 | 4976 | } |
0f2712ed | 4977 | |
252b5132 | 4978 | fix_new_exp (frag, where, (int) nbytes, exp, 0, r); |
364b6d8b JJ |
4979 | } |
4980 | ||
4981 | void | |
5a49b8ac | 4982 | sparc_cfi_frame_initial_instructions (void) |
364b6d8b JJ |
4983 | { |
4984 | cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); | |
4985 | } | |
4986 | ||
4987 | int | |
1df69f4f | 4988 | sparc_regname_to_dw2regnum (char *regname) |
364b6d8b | 4989 | { |
74b4e47a TS |
4990 | char *q; |
4991 | int i; | |
364b6d8b JJ |
4992 | |
4993 | if (!regname[0]) | |
4994 | return -1; | |
4995 | ||
74b4e47a TS |
4996 | switch (regname[0]) |
4997 | { | |
4998 | case 'g': i = 0; break; | |
4999 | case 'o': i = 1; break; | |
5000 | case 'l': i = 2; break; | |
5001 | case 'i': i = 3; break; | |
5002 | default: i = -1; break; | |
5003 | } | |
5004 | if (i != -1) | |
364b6d8b JJ |
5005 | { |
5006 | if (regname[1] < '0' || regname[1] > '8' || regname[2]) | |
5007 | return -1; | |
74b4e47a | 5008 | return i * 8 + regname[1] - '0'; |
364b6d8b JJ |
5009 | } |
5010 | if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) | |
5011 | return 14; | |
5012 | if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) | |
5013 | return 30; | |
5014 | if (regname[0] == 'f' || regname[0] == 'r') | |
5015 | { | |
5016 | unsigned int regnum; | |
5017 | ||
5018 | regnum = strtoul (regname + 1, &q, 10); | |
74b4e47a | 5019 | if (q == NULL || *q) |
364b6d8b JJ |
5020 | return -1; |
5021 | if (regnum >= ((regname[0] == 'f' | |
5022 | && SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
5023 | ? 64 : 32)) | |
5024 | return -1; | |
5025 | if (regname[0] == 'f') | |
5026 | { | |
5027 | regnum += 32; | |
5028 | if (regnum >= 64 && (regnum & 1)) | |
5029 | return -1; | |
5030 | } | |
5031 | return regnum; | |
5032 | } | |
5033 | return -1; | |
5034 | } | |
5035 | ||
5036 | void | |
5037 | sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) | |
5038 | { | |
364b6d8b | 5039 | sparc_no_align_cons = 1; |
62ebcb5c | 5040 | emit_expr_with_reloc (exp, nbytes, "disp"); |
364b6d8b | 5041 | sparc_no_align_cons = 0; |
252b5132 | 5042 | } |