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* config/tc-sparc.c (sparc_handle_align): Reindent a bit. Correct
[deliverable/binutils-gdb.git] / gas / config / tc-sparc.c
CommitLineData
fecd2382 1/* tc-sparc.c -- Assemble for the SPARC
48401fcf 2 Copyright (C) 1989, 90-96, 97, 1998 Free Software Foundation, Inc.
fecd2382 3 This file is part of GAS, the GNU Assembler.
355afbcd 4
fecd2382
RP		 5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
6321e9ea 7 the Free Software Foundation; either version 2, or (at your option)
fecd2382 8 any later version.
355afbcd 9
fecd2382
RP		 10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
355afbcd 14
8dd07a84
ILT		 15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
fecd2382 19
fecd2382
RP		 20#include <stdio.h>
21#include <ctype.h>
22
23#include "as.h"
7ab2e983 24#include "subsegs.h"
fecd2382 25
584a0f78 26#include "opcode/sparc.h"
fecd2382 27
48401fcf 28#ifdef OBJ_ELF
1bb6aaad 29#include "elf/sparc.h"
48401fcf 30#endif
1bb6aaad 31
54b9ebdd
DE		 32static struct sparc_arch *lookup_arch PARAMS ((char *));
33static void init_default_arch PARAMS ((void));
ed94c2b8 34static void sparc_ip PARAMS ((char *, const struct sparc_opcode **));
9f6da653 35static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
54b9ebdd 36static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
9f6da653
DE		 37static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
38static int sparc_ffs PARAMS ((unsigned int));
39static bfd_vma BSR PARAMS ((bfd_vma, int));
40static int cmp_reg_entry PARAMS ((const PTR, const PTR));
41static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
42static int parse_const_expr_arg PARAMS ((char **, int *));
af6f39b4 43static int get_expression PARAMS ((char *str));
fecd2382 44
54b9ebdd
DE		 45/* Default architecture. */
46/* ??? The default value should be V8, but sparclite support was added
47 by making it the default. GCC now passes -Asparclite, so maybe sometime in
48 the future we can set this to V8. */
49#ifndef DEFAULT_ARCH
50#define DEFAULT_ARCH "sparclite"
51#endif
52static char *default_arch = DEFAULT_ARCH;
53
54/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
55 have been set. */
56static int default_init_p;
57
e70ad5d5
DE		 58/* Current architecture. We don't bump up unless necessary. */
59static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
60
61/* The maximum architecture level we can bump up to.
62 In a 32 bit environment, don't allow bumping up to v9 by default.
2b063e6d 63 The native assembler works this way. The user is required to pass
e70ad5d5 64 an explicit argument before we'll create v9 object files. However, if
54b9ebdd
DE		 65 we don't see any v9 insns, a v8plus object file is not created. */
66static enum sparc_opcode_arch_val max_architecture;
67
68/* Either 32 or 64, selects file format. */
69static int sparc_arch_size;
595da85d
DE		 70/* Initial (default) value, recorded separately in case a user option
71 changes the value before md_show_usage is called. */
72static int default_arch_size;
6df07e7f 73
48401fcf
TT		 74#ifdef OBJ_ELF
75/* The currently selected v9 memory model. Currently only used for
76 ELF. */
77static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
78#endif
79
428d312b
KR		 80static int architecture_requested;
81static int warn_on_bump;
839df5c3 82
e70ad5d5
DE		 83/* If warn_on_bump and the needed architecture is higher than this
84 architecture, issue a warning. */
85static enum sparc_opcode_arch_val warn_after_architecture;
86
4c67b523
ILT		 87/* Non-zero if we are generating PIC code. */
88int sparc_pic_code;
89
2b063e6d
ILT		 90/* Non-zero if we should give an error when misaligned data is seen. */
91static int enforce_aligned_data;
92
ed9638af
KR		 93extern int target_big_endian;
94
fc23c14e
SC		 95static int target_little_endian_data;
96
48401fcf
TT		 97/* V9 and 86x have big and little endian data, but instructions are always big
98 endian. The sparclet has bi-endian support but both data and insns have
99 the same endianness. Global `target_big_endian' is used for data.
100 The following macro is used for instructions. */
101#ifndef INSN_BIG_ENDIAN
2b063e6d 102#define INSN_BIG_ENDIAN (target_big_endian \
48401fcf 103 || default_arch_type == sparc86x \
2b063e6d 104 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
48401fcf 105#endif
2b063e6d 106
fecd2382 107/* handle of the OPCODE hash table */
5e0a90a8 108static struct hash_control *op_hash;
fecd2382 109
7766838e
ILT		 110static void s_data1 PARAMS ((void));
111static void s_seg PARAMS ((int));
112static void s_proc PARAMS ((int));
113static void s_reserve PARAMS ((int));
114static void s_common PARAMS ((int));
8dd07a84
ILT		 115static void s_empty PARAMS ((int));
116static void s_uacons PARAMS ((int));
428d312b 117
355afbcd
KR		 118const pseudo_typeS md_pseudo_table[] =
119{
120 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */
121 {"common", s_common, 0},
8dd07a84 122 {"empty", s_empty, 0},
355afbcd
KR		 123 {"global", s_globl, 0},
124 {"half", cons, 2},
125 {"optim", s_ignore, 0},
126 {"proc", s_proc, 0},
127 {"reserve", s_reserve, 0},
128 {"seg", s_seg, 0},
129 {"skip", s_space, 0},
130 {"word", cons, 4},
7766838e 131 {"xword", cons, 8},
2b063e6d
ILT		 132 {"uahalf", s_uacons, 2},
133 {"uaword", s_uacons, 4},
134 {"uaxword", s_uacons, 8},
693b21e7 135#ifdef OBJ_ELF
693b21e7
KR		 136 /* these are specific to sparc/svr4 */
137 {"pushsection", obj_elf_section, 0},
138 {"popsection", obj_elf_previous, 0},
2b063e6d
ILT		 139 {"2byte", s_uacons, 2},
140 {"4byte", s_uacons, 4},
141 {"8byte", s_uacons, 8},
693b21e7 142#endif
355afbcd 143 {NULL, 0, 0},
fecd2382
RP		 144};
145
355afbcd 146const int md_reloc_size = 12; /* Size of relocation record */
fecd2382
RP		 147
148/* This array holds the chars that always start a comment. If the
149 pre-processor is disabled, these aren't very useful */
839df5c3 150const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */
fecd2382
RP		 151
152/* This array holds the chars that only start a comment at the beginning of
153 a line. If the line seems to have the form '# 123 filename'
154 .line and .file directives will appear in the pre-processed output */
155/* Note that input_file.c hand checks for '#' at the beginning of the
156 first line of the input file. This is because the compiler outputs
157 #NO_APP at the beginning of its output. */
839df5c3
RP		 158/* Also note that comments started like this one will always
159 work if '/' isn't otherwise defined. */
160const char line_comment_chars[] = "#";
fecd2382 161
355afbcd
KR		 162const char line_separator_chars[] = "";
163
fecd2382 164/* Chars that can be used to separate mant from exp in floating point nums */
839df5c3 165const char EXP_CHARS[] = "eE";
fecd2382
RP		 166
167/* Chars that mean this number is a floating point constant */
168/* As in 0f12.456 */
169/* or 0d1.2345e12 */
839df5c3 170const char FLT_CHARS[] = "rRsSfFdDxXpP";
fecd2382
RP		 171
172/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
9b6a882e
KR		 173 changed in read.c. Ideally it shouldn't have to know about it at all,
174 but nothing is ideal around here. */
fecd2382
RP		 175
176static unsigned char octal[256];
58d4951d 177#define isoctal(c) octal[(unsigned char) (c)]
355afbcd
KR		 178static unsigned char toHex[256];
179
180struct sparc_it
181 {
182 char *error;
183 unsigned long opcode;
184 struct nlist *nlistp;
185 expressionS exp;
186 int pcrel;
428d312b 187 bfd_reloc_code_real_type reloc;
428d312b
KR		 188 };
189
190struct sparc_it the_insn, set_insn;
191
9f6da653
DE		 192static void output_insn
193 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
af6f39b4 194\f
54b9ebdd
DE		 195/* Table of arguments to -A.
196 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
197 for this use. That table is for opcodes only. This table is for opcodes
198 and file formats. */
199
48401fcf
TT		 200enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
201 v8plusa, v9, v9a, v9_64};
202
54b9ebdd
DE		 203static struct sparc_arch {
204 char *name;
205 char *opcode_arch;
48401fcf 206 enum sparc_arch_types arch_type;
595da85d
DE		 207 /* Default word size, as specified during configuration.
208 A value of zero means can't be used to specify default architecture. */
209 int default_arch_size;
210 /* Allowable arg to -A? */
211 int user_option_p;
54b9ebdd 212} sparc_arch_table[] = {
48401fcf
TT		 213 { "v6", "v6", v6, 0, 1 },
214 { "v7", "v7", v7, 0, 1 },
215 { "v8", "v8", v8, 32, 1 },
216 { "sparclet", "sparclet", sparclet, 32, 1 },
217 { "sparclite", "sparclite", sparclite, 32, 1 },
218 { "sparc86x", "sparclite", sparc86x, 32, 1 },
219 { "v8plus", "v9", v9, 0, 1 },
220 { "v8plusa", "v9a", v9, 0, 1 },
221 { "v9", "v9", v9, 0, 1 },
222 { "v9a", "v9a", v9, 0, 1 },
595da85d
DE		 223 /* This exists to allow configure.in/Makefile.in to pass one
224 value to specify both the default machine and default word size. */
48401fcf
TT		 225 { "v9-64", "v9", v9, 64, 0 },
226 { NULL, NULL, v8, 0, 0 }
54b9ebdd
DE		 227};
228
48401fcf
TT		 229/* Variant of default_arch */
230static enum sparc_arch_types default_arch_type;
231
54b9ebdd
DE		 232static struct sparc_arch *
233lookup_arch (name)
234 char *name;
235{
236 struct sparc_arch *sa;
237
238 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
239 if (strcmp (sa->name, name) == 0)
240 break;
241 if (sa->name == NULL)
242 return NULL;
243 return sa;
244}
245
246/* Initialize the default opcode arch and word size from the default
247 architecture name. */
248
249static void
250init_default_arch ()
251{
252 struct sparc_arch *sa = lookup_arch (default_arch);
253
595da85d
DE		 254 if (sa == NULL
255 || sa->default_arch_size == 0)
48401fcf 256 as_fatal (_("Invalid default architecture, broken assembler."));
54b9ebdd
DE		 257
258 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
259 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
48401fcf 260 as_fatal (_("Bad opcode table, broken assembler."));
595da85d 261 default_arch_size = sparc_arch_size = sa->default_arch_size;
54b9ebdd 262 default_init_p = 1;
48401fcf 263 default_arch_type = sa->arch_type;
54b9ebdd
DE		 264}
265
266/* Called by TARGET_FORMAT. */
267
268const char *
269sparc_target_format ()
270{
271 /* We don't get a chance to initialize anything before we're called,
272 so handle that now. */
273 if (! default_init_p)
274 init_default_arch ();
275
276#ifdef OBJ_AOUT
277#ifdef TE_NetBSD
278 return "a.out-sparc-netbsd";
279#else
280#ifdef TE_SPARCAOUT
281 return target_big_endian ? "a.out-sunos-big" : "a.out-sparc-little";
282#else
283 return "a.out-sunos-big";
284#endif
285#endif
286#endif
287
288#ifdef OBJ_BOUT
289 return "b.out.big";
290#endif
291
292#ifdef OBJ_COFF
293#ifdef TE_LYNX
294 return "coff-sparc-lynx";
295#else
296 return "coff-sparc";
297#endif
298#endif
299
300#ifdef OBJ_ELF
301 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
302#endif
303
304 abort ();
305}
306\f
af6f39b4
DE		 307/*
308 * md_parse_option
309 * Invocation line includes a switch not recognized by the base assembler.
310 * See if it's a processor-specific option. These are:
311 *
312 * -bump
313 * Warn on architecture bumps. See also -A.
314 *
315 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
316 * Standard 32 bit architectures.
317 * -Av8plus, -Av8plusa
318 * Sparc64 in a 32 bit world.
319 * -Av9, -Av9a
595da85d
DE		 320 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
321 * This used to only mean 64 bits, but properly specifying it
322 * complicated gcc's ASM_SPECs, so now opcode selection is
323 * specified orthogonally to word size (except when specifying
324 * the default, but that is an internal implementation detail).
af6f39b4
DE		 325 * -xarch=v8plus, -xarch=v8plusa
326 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
327 *
328 * Select the architecture and possibly the file format.
329 * Instructions or features not supported by the selected
330 * architecture cause fatal errors.
331 *
332 * The default is to start at v6, and bump the architecture up
54b9ebdd
DE		 333 * whenever an instruction is seen at a higher level. In 32 bit
334 * environments, v9 is not bumped up to, the user must pass
335 * -Av8plus{,a}.
af6f39b4
DE		 336 *
337 * If -bump is specified, a warning is printing when bumping to
338 * higher levels.
339 *
340 * If an architecture is specified, all instructions must match
341 * that architecture. Any higher level instructions are flagged
342 * as errors. Note that in the 32 bit environment specifying
54b9ebdd
DE		 343 * -Av8plus does not automatically create a v8plus object file, a
344 * v9 insn must be seen.
af6f39b4
DE		 345 *
346 * If both an architecture and -bump are specified, the
347 * architecture starts at the specified level, but bumps are
348 * warnings. Note that we can't set `current_architecture' to
349 * the requested level in this case: in the 32 bit environment,
54b9ebdd
DE		 350 * we still must avoid creating v8plus object files unless v9
351 * insns are seen.
af6f39b4
DE		 352 *
353 * Note:
354 * Bumping between incompatible architectures is always an
355 * error. For example, from sparclite to v9.
356 */
9f6da653 357
af6f39b4
DE		 358#ifdef OBJ_ELF
359CONST char *md_shortopts = "A:K:VQ:sq";
360#else
361#ifdef OBJ_AOUT
362CONST char *md_shortopts = "A:k";
363#else
364CONST char *md_shortopts = "A:";
365#endif
366#endif
367struct option md_longopts[] = {
368#define OPTION_BUMP (OPTION_MD_BASE)
369 {"bump", no_argument, NULL, OPTION_BUMP},
370#define OPTION_SPARC (OPTION_MD_BASE + 1)
371 {"sparc", no_argument, NULL, OPTION_SPARC},
372#define OPTION_XARCH (OPTION_MD_BASE + 2)
373 {"xarch", required_argument, NULL, OPTION_XARCH},
595da85d
DE		 374#ifdef OBJ_ELF
375#define OPTION_32 (OPTION_MD_BASE + 3)
376 {"32", no_argument, NULL, OPTION_32},
377#define OPTION_64 (OPTION_MD_BASE + 4)
378 {"64", no_argument, NULL, OPTION_64},
1bb6aaad
RH		 379#define OPTION_TSO (OPTION_MD_BASE + 5)
380 {"TSO", no_argument, NULL, OPTION_TSO},
381#define OPTION_PSO (OPTION_MD_BASE + 6)
382 {"PSO", no_argument, NULL, OPTION_PSO},
383#define OPTION_RMO (OPTION_MD_BASE + 7)
384 {"RMO", no_argument, NULL, OPTION_RMO},
595da85d 385#endif
af6f39b4 386#ifdef SPARC_BIENDIAN
1bb6aaad 387#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
af6f39b4 388 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
1bb6aaad 389#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
af6f39b4
DE		 390 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
391#endif
1bb6aaad 392#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
af6f39b4 393 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
fc23c14e
SC		 394#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
395 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
af6f39b4
DE		 396 {NULL, no_argument, NULL, 0}
397};
398size_t md_longopts_size = sizeof(md_longopts);
8dd07a84 399
af6f39b4
DE		 400int
401md_parse_option (c, arg)
402 int c;
403 char *arg;
7ab2e983 404{
54b9ebdd
DE		 405 /* We don't get a chance to initialize anything before we're called,
406 so handle that now. */
407 if (! default_init_p)
408 init_default_arch ();
409
af6f39b4
DE		 410 switch (c)
411 {
412 case OPTION_BUMP:
413 warn_on_bump = 1;
414 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
415 break;
7ab2e983 416
af6f39b4 417 case OPTION_XARCH:
54b9ebdd
DE		 418 /* This is for compatibility with Sun's assembler. */
419 if (strcmp (arg, "v8plus") != 0
420 && strcmp (arg, "v8plusa") != 0)
af6f39b4 421 {
48401fcf 422 as_bad (_("invalid architecture -xarch=%s"), arg);
af6f39b4
DE		 423 return 0;
424 }
8dd07a84 425
af6f39b4 426 /* fall through */
8dd07a84 427
af6f39b4
DE		 428 case 'A':
429 {
54b9ebdd
DE		 430 struct sparc_arch *sa;
431 enum sparc_opcode_arch_val opcode_arch;
d8b42b96 432
54b9ebdd 433 sa = lookup_arch (arg);
595da85d
DE		 434 if (sa == NULL
435 || ! sa->user_option_p)
af6f39b4 436 {
48401fcf 437 as_bad (_("invalid architecture -A%s"), arg);
af6f39b4
DE		 438 return 0;
439 }
d8b42b96 440
54b9ebdd
DE		 441 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
442 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
48401fcf 443 as_fatal (_("Bad opcode table, broken assembler."));
54b9ebdd
DE		 444
445 max_architecture = opcode_arch;
af6f39b4
DE		 446 architecture_requested = 1;
447 }
448 break;
d8b42b96 449
af6f39b4
DE		 450 case OPTION_SPARC:
451 /* Ignore -sparc, used by SunOS make default .s.o rule. */
452 break;
2b063e6d 453
af6f39b4
DE		 454 case OPTION_ENFORCE_ALIGNED_DATA:
455 enforce_aligned_data = 1;
456 break;
a87b3269 457
af6f39b4
DE		 458#ifdef SPARC_BIENDIAN
459 case OPTION_LITTLE_ENDIAN:
fc23c14e
SC		 460 target_big_endian = 0;
461 if (default_arch_type != sparclet)
462 as_fatal ("This target does not support -EL");
463 break;
464 case OPTION_LITTLE_ENDIAN_DATA:
465 target_little_endian_data = 1;
af6f39b4 466 target_big_endian = 0;
48401fcf 467 if (default_arch_type != sparc86x
48401fcf 468 && default_arch_type != v9)
fc23c14e 469 as_fatal ("This target does not support --little-endian-data");
af6f39b4
DE		 470 break;
471 case OPTION_BIG_ENDIAN:
472 target_big_endian = 1;
473 break;
474#endif
fecd2382 475
af6f39b4
DE		 476#ifdef OBJ_AOUT
477 case 'k':
478 sparc_pic_code = 1;
479 break;
480#endif
2b063e6d 481
af6f39b4 482#ifdef OBJ_ELF
595da85d
DE		 483 case OPTION_32:
484 case OPTION_64:
485 {
486 const char **list, **l;
487
488 sparc_arch_size = c == OPTION_32 ? 32 : 64;
489 list = bfd_target_list ();
490 for (l = list; *l != NULL; l++)
491 {
492 if (sparc_arch_size == 32)
493 {
494 if (strcmp (*l, "elf32-sparc") == 0)
495 break;
496 }
497 else
498 {
499 if (strcmp (*l, "elf64-sparc") == 0)
500 break;
501 }
502 }
503 if (*l == NULL)
48401fcf 504 as_fatal (_("No compiled in support for %d bit object file format"),
595da85d
DE		 505 sparc_arch_size);
506 free (list);
507 }
508 break;
509
1bb6aaad
RH		 510 case OPTION_TSO:
511 sparc_memory_model = MM_TSO;
512 break;
513
514 case OPTION_PSO:
515 sparc_memory_model = MM_PSO;
516 break;
517
518 case OPTION_RMO:
519 sparc_memory_model = MM_RMO;
520 break;
521
af6f39b4
DE		 522 case 'V':
523 print_version_id ();
524 break;
fecd2382 525
af6f39b4
DE		 526 case 'Q':
527 /* Qy - do emit .comment
528 Qn - do not emit .comment */
529 break;
ed94c2b8 530
af6f39b4
DE		 531 case 's':
532 /* use .stab instead of .stab.excl */
533 break;
584a0f78 534
af6f39b4
DE		 535 case 'q':
536 /* quick -- native assembler does fewer checks */
537 break;
355afbcd 538
af6f39b4
DE		 539 case 'K':
540 if (strcmp (arg, "PIC") != 0)
48401fcf 541 as_warn (_("Unrecognized option following -K"));
af6f39b4
DE		 542 else
543 sparc_pic_code = 1;
544 break;
545#endif
355afbcd 546
af6f39b4
DE		 547 default:
548 return 0;
355afbcd
KR		 549 }
550
af6f39b4
DE		 551 return 1;
552}
355afbcd 553
af6f39b4
DE		 554void
555md_show_usage (stream)
556 FILE *stream;
557{
54b9ebdd 558 const struct sparc_arch *arch;
355afbcd 559
595da85d
DE		 560 /* We don't get a chance to initialize anything before we're called,
561 so handle that now. */
562 if (! default_init_p)
563 init_default_arch ();
564
48401fcf 565 fprintf(stream, _("SPARC options:\n"));
54b9ebdd 566 for (arch = &sparc_arch_table[0]; arch->name; arch++)
355afbcd 567 {
54b9ebdd 568 if (arch != &sparc_arch_table[0])
af6f39b4 569 fprintf (stream, " | ");
595da85d
DE		 570 if (arch->user_option_p)
571 fprintf (stream, "-A%s", arch->name);
9b6a882e 572 }
48401fcf
TT		 573 fprintf (stream, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
574 fprintf (stream, _("\
af6f39b4
DE		 575 specify variant of SPARC architecture\n\
576-bump warn when assembler switches architectures\n\
577-sparc ignored\n\
48401fcf 578--enforce-aligned-data force .long, etc., to be aligned correctly\n"));
af6f39b4 579#ifdef OBJ_AOUT
48401fcf
TT		 580 fprintf (stream, _("\
581-k generate PIC\n"));
af6f39b4
DE		 582#endif
583#ifdef OBJ_ELF
48401fcf 584 fprintf (stream, _("\
595da85d 585-32 create 32 bit object file\n\
48401fcf
TT		 586-64 create 64 bit object file\n"));
587 fprintf (stream, _("\
588 [default is %d]\n"), default_arch_size);
589 fprintf (stream, _("\
1bb6aaad
RH		 590-TSO use Total Store Ordering\n\
591-PSO use Partial Store Ordering\n\
48401fcf
TT		 592-RMO use Relaxed Memory Ordering\n"));
593 fprintf (stream, _("\
594 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
595 fprintf (stream, _("\
af6f39b4
DE		 596-KPIC generate PIC\n\
597-V print assembler version number\n\
598-q ignored\n\
599-Qy, -Qn ignored\n\
48401fcf 600-s ignored\n"));
af6f39b4
DE		 601#endif
602#ifdef SPARC_BIENDIAN
48401fcf 603 fprintf (stream, _("\
af6f39b4 604-EL generate code for a little endian machine\n\
fc23c14e 605-EB generate code for a big endian machine\n\
04a92367 606--little-endian-data generate code for a machine having big endian\n\
fc23c14e 607 instructions and little endian data."));
af6f39b4
DE		 608#endif
609}
610\f
611/* sparc64 priviledged registers */
355afbcd 612
af6f39b4
DE		 613struct priv_reg_entry
614 {
615 char *name;
616 int regnum;
617 };
355afbcd 618
af6f39b4
DE		 619struct priv_reg_entry priv_reg_table[] =
620{
621 {"tpc", 0},
622 {"tnpc", 1},
623 {"tstate", 2},
624 {"tt", 3},
625 {"tick", 4},
626 {"tba", 5},
627 {"pstate", 6},
628 {"tl", 7},
629 {"pil", 8},
630 {"cwp", 9},
631 {"cansave", 10},
632 {"canrestore", 11},
633 {"cleanwin", 12},
634 {"otherwin", 13},
635 {"wstate", 14},
636 {"fq", 15},
637 {"ver", 31},
638 {"", -1}, /* end marker */
639};
355afbcd 640
1277cdda
RH		 641/* v9a specific asrs */
642
643struct priv_reg_entry v9a_asr_table[] =
644{
645 {"tick_cmpr", 23},
646 {"softint", 22},
647 {"set_softint", 20},
648 {"pic", 17},
649 {"pcr", 16},
650 {"gsr", 19},
651 {"dcr", 18},
652 {"clear_softint", 21},
653 {"", -1}, /* end marker */
654};
655
af6f39b4
DE		 656static int
657cmp_reg_entry (parg, qarg)
658 const PTR parg;
659 const PTR qarg;
660{
661 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
662 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
355afbcd 663
af6f39b4
DE		 664 return strcmp (q->name, p->name);
665}
666\f
667/* This function is called once, at assembler startup time. It should
668 set up all the tables, etc. that the MD part of the assembler will need. */
669
670void
671md_begin ()
672{
673 register const char *retval = NULL;
674 int lose = 0;
675 register unsigned int i = 0;
676
54b9ebdd
DE		 677 /* We don't get a chance to initialize anything before md_parse_option
678 is called, and it may not be called, so handle default initialization
679 now if not already done. */
680 if (! default_init_p)
681 init_default_arch ();
682
af6f39b4
DE		 683 op_hash = hash_new ();
684
48401fcf 685 while (i < (unsigned int) sparc_num_opcodes)
af6f39b4
DE		 686 {
687 const char *name = sparc_opcodes[i].name;
688 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
689 if (retval != NULL)
355afbcd 690 {
48401fcf 691 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
af6f39b4
DE		 692 sparc_opcodes[i].name, retval);
693 lose = 1;
355afbcd 694 }
af6f39b4 695 do
355afbcd 696 {
af6f39b4
DE		 697 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
698 {
48401fcf 699 fprintf (stderr, _("internal error: losing opcode: `%s' \"%s\"\n"),
af6f39b4
DE		 700 sparc_opcodes[i].name, sparc_opcodes[i].args);
701 lose = 1;
702 }
703 ++i;
fecd2382 704 }
48401fcf 705 while (i < (unsigned int) sparc_num_opcodes
af6f39b4
DE		 706 && !strcmp (sparc_opcodes[i].name, name));
707 }
428d312b 708
af6f39b4 709 if (lose)
48401fcf 710 as_fatal (_("Broken assembler. No assembly attempted."));
355afbcd 711
af6f39b4
DE		 712 for (i = '0'; i < '8'; ++i)
713 octal[i] = 1;
714 for (i = '0'; i <= '9'; ++i)
715 toHex[i] = i - '0';
716 for (i = 'a'; i <= 'f'; ++i)
717 toHex[i] = i + 10 - 'a';
718 for (i = 'A'; i <= 'F'; ++i)
719 toHex[i] = i + 10 - 'A';
355afbcd 720
af6f39b4
DE		 721 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
722 sizeof (priv_reg_table[0]), cmp_reg_entry);
355afbcd 723
af6f39b4
DE		 724 /* If -bump, record the architecture level at which we start issuing
725 warnings. The behaviour is different depending upon whether an
726 architecture was explicitly specified. If it wasn't, we issue warnings
727 for all upwards bumps. If it was, we don't start issuing warnings until
728 we need to bump beyond the requested architecture or when we bump between
729 conflicting architectures. */
355afbcd 730
af6f39b4
DE		 731 if (warn_on_bump
732 && architecture_requested)
355afbcd 733 {
af6f39b4
DE		 734 /* `max_architecture' records the requested architecture.
735 Issue warnings if we go above it. */
736 warn_after_architecture = max_architecture;
428d312b 737
af6f39b4
DE		 738 /* Find the highest architecture level that doesn't conflict with
739 the requested one. */
740 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
741 max_architecture > warn_after_architecture;
742 --max_architecture)
743 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
744 warn_after_architecture))
745 break;
746 }
747}
428d312b 748
af6f39b4 749/* Called after all assembly has been done. */
428d312b 750
af6f39b4
DE		 751void
752sparc_md_end ()
753{
54b9ebdd
DE		 754 if (sparc_arch_size == 64)
755 {
756 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
757 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
758 else
759 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
760 }
355afbcd
KR		 761 else
762 {
54b9ebdd
DE		 763 if (current_architecture == SPARC_OPCODE_ARCH_V9)
764 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
765 else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
766 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
767 else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
768 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
fc23c14e
SC		 769 else if (default_arch_type == sparc86x && target_little_endian_data)
770 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le);
54b9ebdd
DE		 771 else
772 {
773 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
774 be but for now it is (since that's the way it's always been
775 treated). */
776 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
777 }
af6f39b4 778 }
428d312b 779}
af6f39b4
DE		 780\f
781/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
355afbcd 782
af6f39b4
DE		 783static INLINE int
784in_signed_range (val, max)
785 bfd_signed_vma val, max;
355afbcd 786{
af6f39b4
DE		 787 if (max <= 0)
788 abort ();
789 if (val > max)
790 return 0;
791 if (val < ~max)
792 return 0;
793 return 1;
794}
355afbcd 795
54b9ebdd
DE		 796/* Return non-zero if VAL is in the range 0 to MAX. */
797
798static INLINE int
799in_unsigned_range (val, max)
800 bfd_vma val, max;
801{
802 if (val > max)
803 return 0;
804 return 1;
805}
806
af6f39b4
DE		 807/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
808 (e.g. -15 to +31). */
8dd07a84 809
af6f39b4
DE		 810static INLINE int
811in_bitfield_range (val, max)
812 bfd_signed_vma val, max;
8dd07a84 813{
af6f39b4
DE		 814 if (max <= 0)
815 abort ();
816 if (val > max)
817 return 0;
818 if (val < ~(max >> 1))
819 return 0;
820 return 1;
8dd07a84
ILT		 821}
822
af6f39b4
DE		 823static int
824sparc_ffs (mask)
825 unsigned int mask;
355afbcd 826{
af6f39b4 827 int i;
355afbcd 828
af6f39b4
DE		 829 if (mask == 0)
830 return -1;
355afbcd 831
af6f39b4
DE		 832 for (i = 0; (mask & 1) == 0; ++i)
833 mask >>= 1;
834 return i;
c999fd9f 835}
fecd2382 836
af6f39b4
DE		 837/* Implement big shift right. */
838static bfd_vma
839BSR (val, amount)
840 bfd_vma val;
841 int amount;
355afbcd 842{
af6f39b4 843 if (sizeof (bfd_vma) <= 4 && amount >= 32)
48401fcf 844 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
af6f39b4 845 return val >> amount;
c999fd9f 846}
af6f39b4
DE		 847\f
848/* For communication between sparc_ip and get_expression. */
849static char *expr_end;
fecd2382 850
af6f39b4
DE		 851/* For communication between md_assemble and sparc_ip. */
852static int special_case;
8dd07a84 853
af6f39b4
DE		 854/* Values for `special_case'.
855 Instructions that require wierd handling because they're longer than
856 4 bytes. */
857#define SPECIAL_CASE_NONE 0
858#define SPECIAL_CASE_SET 1
859#define SPECIAL_CASE_SETSW 2
860#define SPECIAL_CASE_SETX 3
861/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
862#define SPECIAL_CASE_FDIV 4
8dd07a84 863
af6f39b4
DE		 864/* Bit masks of various insns. */
865#define NOP_INSN 0x01000000
866#define OR_INSN 0x80100000
867#define FMOVS_INSN 0x81A00020
868#define SETHI_INSN 0x01000000
869#define SLLX_INSN 0x81281000
870#define SRA_INSN 0x81380000
8dd07a84 871
af6f39b4
DE		 872/* The last instruction to be assembled. */
873static const struct sparc_opcode *last_insn;
874/* The assembled opcode of `last_insn'. */
875static unsigned long last_opcode;
876\f
877/* Main entry point to assemble one instruction. */
878
879void
880md_assemble (str)
881 char *str;
8dd07a84 882{
af6f39b4 883 const struct sparc_opcode *insn;
355afbcd
KR		 884
885 know (str);
af6f39b4 886 special_case = SPECIAL_CASE_NONE;
ed94c2b8
ILT		 887 sparc_ip (str, &insn);
888
9f6da653
DE		 889 /* We warn about attempts to put a floating point branch in a delay slot,
890 unless the delay slot has been annulled. */
ed94c2b8
ILT		 891 if (insn != NULL
892 && last_insn != NULL
893 && (insn->flags & F_FBR) != 0
9f6da653
DE		 894 && (last_insn->flags & F_DELAYED) != 0
895 /* ??? This test isn't completely accurate. We assume anything with
896 F_{UNBR,CONDBR,FBR} set is annullable. */
897 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
898 || (last_opcode & ANNUL) == 0))
48401fcf 899 as_warn (_("FP branch in delay slot"));
ed94c2b8
ILT		 900
901 /* SPARC before v9 requires a nop instruction between a floating
902 point instruction and a floating point branch. We insert one
903 automatically, with a warning. */
904 if (max_architecture < SPARC_OPCODE_ARCH_V9
905 && insn != NULL
906 && last_insn != NULL
907 && (insn->flags & F_FBR) != 0
908 && (last_insn->flags & F_FLOAT) != 0)
909 {
2b063e6d
ILT		 910 struct sparc_it nop_insn;
911
912 nop_insn.opcode = NOP_INSN;
913 nop_insn.reloc = BFD_RELOC_NONE;
914 output_insn (insn, &nop_insn);
48401fcf 915 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
ed94c2b8 916 }
355afbcd 917
2b063e6d 918 switch (special_case)
355afbcd 919 {
af6f39b4 920 case SPECIAL_CASE_NONE:
2b063e6d
ILT		 921 /* normal insn */
922 output_insn (insn, &the_insn);
923 break;
355afbcd 924
2b063e6d
ILT		 925 case SPECIAL_CASE_SET:
926 {
927 int need_hi22_p = 0;
355afbcd 928
2b063e6d
ILT		 929 /* "set" is not defined for negative numbers in v9: it doesn't yield
930 what you expect it to. */
931 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)
932 && the_insn.exp.X_op == O_constant)
933 {
934 if (the_insn.exp.X_add_number < 0)
48401fcf
TT		 935 as_warn (_("set: used with negative number"));
936 else if (the_insn.exp.X_add_number > (offsetT) 0xffffffff)
937 as_warn (_("set: number larger than 4294967295"));
2b063e6d 938 }
428d312b 939
2b063e6d
ILT		 940 /* See if operand is absolute and small; skip sethi if so. */
941 if (the_insn.exp.X_op != O_constant
942 || the_insn.exp.X_add_number >= (1 << 12)
943 || the_insn.exp.X_add_number < -(1 << 12))
944 {
945 output_insn (insn, &the_insn);
946 need_hi22_p = 1;
947 }
948 /* See if operand has no low-order bits; skip OR if so. */
949 if (the_insn.exp.X_op != O_constant
950 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
951 || ! need_hi22_p)
952 {
953 int rd = (the_insn.opcode & RD (~0)) >> 25;
954 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
955 | RD (rd)
956 | IMMED
957 | (the_insn.exp.X_add_number
958 & (need_hi22_p ? 0x3ff : 0x1fff)));
959 the_insn.reloc = (the_insn.exp.X_op != O_constant
960 ? BFD_RELOC_LO10
961 : BFD_RELOC_NONE);
962 output_insn (insn, &the_insn);
963 }
964 break;
965 }
ed94c2b8 966
2b063e6d
ILT		 967 case SPECIAL_CASE_SETSW:
968 {
969 /* FIXME: Not finished. */
970 break;
971 }
355afbcd 972
2b063e6d
ILT		 973 case SPECIAL_CASE_SETX:
974 {
975#define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
976 int upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
977 int lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
978#undef SIGNEXT32
979 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
980 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
981 /* Output directly to dst reg if lower 32 bits are all zero. */
982 int upper_dstreg = (the_insn.exp.X_op == O_constant
983 && lower32 == 0) ? dstreg : tmpreg;
984 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
985
986 /* The tmp reg should not be the dst reg. */
987 if (tmpreg == dstreg)
48401fcf 988 as_warn (_("setx: temporary register same as destination register"));
2b063e6d
ILT		 989
990 /* Reset X_add_number, we've extracted it as upper32/lower32.
991 Otherwise fixup_segment will complain about not being able to
992 write an 8 byte number in a 4 byte field. */
993 the_insn.exp.X_add_number = 0;
994
995 /* ??? Obviously there are other optimizations we can do
996 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
997 doing some of these. Later. If you do change things, try to
998 change all of this to be table driven as well. */
999
1000 /* What to output depends on the number if it's constant.
1001 Compute that first, then output what we've decided upon. */
1002 if (the_insn.exp.X_op != O_constant)
1003 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1004 else
1005 {
1006 /* Only need hh22 if `or' insn can't handle constant. */
1007 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1008 need_hh22_p = 1;
1009
1010 /* Does bottom part (after sethi) have bits? */
1011 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1012 /* No hh22, but does upper32 still have bits we can't set
1013 from lower32? */
1014 || (! need_hh22_p
1015 && upper32 != 0
1016 && (upper32 != -1 || lower32 >= 0)))
1017 need_hm10_p = 1;
1018
1019 /* If the lower half is all zero, we build the upper half directly
1020 into the dst reg. */
1021 if (lower32 != 0
1022 /* Need lower half if number is zero. */
1023 || (! need_hh22_p && ! need_hm10_p))
1024 {
1025 /* No need for sethi if `or' insn can handle constant. */
1026 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1027 /* Note that we can't use a negative constant in the `or'
1028 insn unless the upper 32 bits are all ones. */
1029 || (lower32 < 0 && upper32 != -1))
1030 need_hi22_p = 1;
1031
1032 /* Does bottom part (after sethi) have bits? */
1033 if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1034 /* No sethi. */
1035 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1036 /* Need `or' if we didn't set anything else. */
1037 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1038 need_lo10_p = 1;
1039 }
1040 }
355afbcd 1041
2b063e6d
ILT		 1042 if (need_hh22_p)
1043 {
1044 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1045 | ((upper32 >> 10) & 0x3fffff));
1046 the_insn.reloc = (the_insn.exp.X_op != O_constant
1047 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1048 output_insn (insn, &the_insn);
1049 }
1050
1051 if (need_hm10_p)
1052 {
1053 the_insn.opcode = (OR_INSN
1054 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1055 | RD (upper_dstreg)
1056 | IMMED
1057 | (upper32
1058 & (need_hh22_p ? 0x3ff : 0x1fff)));
1059 the_insn.reloc = (the_insn.exp.X_op != O_constant
1060 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1061 output_insn (insn, &the_insn);
1062 }
1063
1064 if (need_hi22_p)
1065 {
1066 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1067 | ((lower32 >> 10) & 0x3fffff));
1068 the_insn.reloc = BFD_RELOC_HI22;
1069 output_insn (insn, &the_insn);
1070 }
1071
1072 if (need_lo10_p)
1073 {
1074 /* FIXME: One nice optimization to do here is to OR the low part
1075 with the highpart if hi22 isn't needed and the low part is
1076 positive. */
1077 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1078 | RD (dstreg)
1079 | IMMED
1080 | (lower32
1081 & (need_hi22_p ? 0x3ff : 0x1fff)));
1082 the_insn.reloc = BFD_RELOC_LO10;
1083 output_insn (insn, &the_insn);
1084 }
1085
1086 /* If we needed to build the upper part, shift it into place. */
1087 if (need_hh22_p || need_hm10_p)
1088 {
1089 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1090 | IMMED | 32);
1091 the_insn.reloc = BFD_RELOC_NONE;
1092 output_insn (insn, &the_insn);
1093 }
1094
1095 /* If we needed to build both upper and lower parts, OR them together. */
1096 if ((need_hh22_p || need_hm10_p)
1097 && (need_hi22_p || need_lo10_p))
1098 {
1099 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1100 | RD (dstreg));
1101 the_insn.reloc = BFD_RELOC_NONE;
1102 output_insn (insn, &the_insn);
1103 }
1104 /* We didn't need both regs, but we may have to sign extend lower32. */
1105 else if (need_hi22_p && upper32 == -1)
1106 {
1107 the_insn.opcode = (SRA_INSN | RS1 (dstreg) | RD (dstreg)
1108 | IMMED | 0);
1109 the_insn.reloc = BFD_RELOC_NONE;
1110 output_insn (insn, &the_insn);
1111 }
1112 break;
1113 }
1114
1115 case SPECIAL_CASE_FDIV:
1116 {
1117 int rd = (the_insn.opcode >> 25) & 0x1f;
1118
1119 output_insn (insn, &the_insn);
1120
1121 /* According to information leaked from Sun, the "fdiv" instructions
1122 on early SPARC machines would produce incorrect results sometimes.
1123 The workaround is to add an fmovs of the destination register to
1124 itself just after the instruction. This was true on machines
1125 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1126 assert (the_insn.reloc == BFD_RELOC_NONE);
1127 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1128 output_insn (insn, &the_insn);
1129 break;
1130 }
355afbcd
KR		 1131
1132 default:
48401fcf 1133 as_fatal (_("failed special case insn sanity check"));
355afbcd 1134 }
9b6a882e 1135}
355afbcd 1136
af6f39b4 1137/* Subroutine of md_assemble to do the actual parsing. */
6df07e7f 1138
af6f39b4
DE		 1139static void
1140sparc_ip (str, pinsn)
1141 char *str;
1142 const struct sparc_opcode **pinsn;
fecd2382 1143{
355afbcd
KR		 1144 char *error_message = "";
1145 char *s;
1146 const char *args;
1147 char c;
a7aa7a2b 1148 const struct sparc_opcode *insn;
355afbcd
KR		 1149 char *argsStart;
1150 unsigned long opcode;
1151 unsigned int mask = 0;
1152 int match = 0;
1153 int comma = 0;
6df07e7f 1154 int v9_arg_p;
355afbcd 1155
48401fcf 1156 for (s = str; islower ((unsigned char) *s) || (*s >= '0' && *s <= '3'); ++s)
355afbcd 1157 ;
6df07e7f 1158
355afbcd
KR		 1159 switch (*s)
1160 {
355afbcd
KR		 1161 case '\0':
1162 break;
1163
1164 case ',':
1165 comma = 1;
1166
1167 /*FALLTHROUGH */
1168
1169 case ' ':
1170 *s++ = '\0';
1171 break;
1172
1173 default:
48401fcf 1174 as_fatal (_("Unknown opcode: `%s'"), str);
355afbcd 1175 }
a7aa7a2b 1176 insn = (struct sparc_opcode *) hash_find (op_hash, str);
ed94c2b8 1177 *pinsn = insn;
a7aa7a2b 1178 if (insn == NULL)
355afbcd 1179 {
48401fcf 1180 as_bad (_("Unknown opcode: `%s'"), str);
355afbcd
KR		 1181 return;
1182 }
1183 if (comma)
1184 {
1185 *--s = ',';
1186 }
6df07e7f 1187
355afbcd
KR		 1188 argsStart = s;
1189 for (;;)
1190 {
1191 opcode = insn->match;
1192 memset (&the_insn, '\0', sizeof (the_insn));
428d312b 1193 the_insn.reloc = BFD_RELOC_NONE;
6df07e7f 1194 v9_arg_p = 0;
355afbcd
KR		 1195
1196 /*
8fc0776d
JW		 1197 * Build the opcode, checking as we go to make
1198 * sure that the operands match
1199 */
355afbcd
KR		 1200 for (args = insn->args;; ++args)
1201 {
1202 switch (*args)
1203 {
355afbcd
KR		 1204 case 'K':
1205 {
7766838e 1206 int kmask = 0;
ed9638af
KR		 1207
1208 /* Parse a series of masks. */
1209 if (*s == '#')
355afbcd 1210 {
ed9638af 1211 while (*s == '#')
355afbcd 1212 {
6df07e7f
DE		 1213 int mask;
1214
1215 if (! parse_keyword_arg (sparc_encode_membar, &s,
1216 &mask))
ed9638af 1217 {
48401fcf 1218 error_message = _(": invalid membar mask name");
ed9638af
KR		 1219 goto error;
1220 }
6df07e7f
DE		 1221 kmask |= mask;
1222 while (*s == ' ') { ++s; continue; }
1223 if (*s == '|' || *s == '+')
ed9638af 1224 ++s;
6df07e7f 1225 while (*s == ' ') { ++s; continue; }
355afbcd 1226 }
ed9638af 1227 }
c999fd9f 1228 else
ed9638af 1229 {
6df07e7f
DE		 1230 if (! parse_const_expr_arg (&s, &kmask))
1231 {
48401fcf 1232 error_message = _(": invalid membar mask expression");
6df07e7f
DE		 1233 goto error;
1234 }
1235 if (kmask < 0 || kmask > 127)
ed9638af 1236 {
48401fcf 1237 error_message = _(": invalid membar mask number");
ed9638af 1238 goto error;
355afbcd 1239 }
355afbcd 1240 }
c999fd9f 1241
6df07e7f 1242 opcode |= MEMBAR (kmask);
355afbcd
KR		 1243 continue;
1244 }
1245
1246 case '*':
ed9638af 1247 {
6df07e7f 1248 int fcn = 0;
355afbcd 1249
ed9638af
KR		 1250 /* Parse a prefetch function. */
1251 if (*s == '#')
1252 {
6df07e7f 1253 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
ed9638af 1254 {
48401fcf 1255 error_message = _(": invalid prefetch function name");
ed9638af
KR		 1256 goto error;
1257 }
1258 }
6df07e7f 1259 else
ed9638af 1260 {
6df07e7f 1261 if (! parse_const_expr_arg (&s, &fcn))
ed9638af 1262 {
48401fcf 1263 error_message = _(": invalid prefetch function expression");
6df07e7f 1264 goto error;
ed9638af 1265 }
6df07e7f 1266 if (fcn < 0 || fcn > 31)
ed9638af 1267 {
48401fcf 1268 error_message = _(": invalid prefetch function number");
ed9638af
KR		 1269 goto error;
1270 }
1271 }
6df07e7f 1272 opcode |= RD (fcn);
ed9638af
KR		 1273 continue;
1274 }
355afbcd
KR		 1275
1276 case '!':
1277 case '?':
6df07e7f 1278 /* Parse a sparc64 privileged register. */
355afbcd
KR		 1279 if (*s == '%')
1280 {
1281 struct priv_reg_entry *p = priv_reg_table;
7766838e 1282 unsigned int len = 9999999; /* init to make gcc happy */
355afbcd
KR		 1283
1284 s += 1;
1285 while (p->name[0] > s[0])
1286 p++;
1287 while (p->name[0] == s[0])
1288 {
1289 len = strlen (p->name);
1290 if (strncmp (p->name, s, len) == 0)
1291 break;
1292 p++;
1293 }
1294 if (p->name[0] != s[0])
1295 {
48401fcf 1296 error_message = _(": unrecognizable privileged register");
355afbcd
KR		 1297 goto error;
1298 }
1299 if (*args == '?')
1300 opcode |= (p->regnum << 14);
1301 else
1302 opcode |= (p->regnum << 25);
1303 s += len;
1304 continue;
1305 }
1306 else
1307 {
48401fcf 1308 error_message = _(": unrecognizable privileged register");
355afbcd
KR		 1309 goto error;
1310 }
680227f3 1311
1277cdda
RH		 1312 case '_':
1313 case '/':
1314 /* Parse a v9a ancillary state register. */
1315 if (*s == '%')
1316 {
1317 struct priv_reg_entry *p = v9a_asr_table;
1318 unsigned int len = 9999999; /* init to make gcc happy */
1319
1320 s += 1;
1321 while (p->name[0] > s[0])
1322 p++;
1323 while (p->name[0] == s[0])
1324 {
1325 len = strlen (p->name);
1326 if (strncmp (p->name, s, len) == 0)
1327 break;
1328 p++;
1329 }
1330 if (p->name[0] != s[0])
1331 {
48401fcf 1332 error_message = _(": unrecognizable v9a ancillary state register");
1277cdda
RH		 1333 goto error;
1334 }
1335 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1336 {
48401fcf 1337 error_message = _(": rd on write only ancillary state register");
1277cdda
RH		 1338 goto error;
1339 }
1340 if (*args == '/')
1341 opcode |= (p->regnum << 14);
1342 else
1343 opcode |= (p->regnum << 25);
1344 s += len;
1345 continue;
1346 }
1347 else
1348 {
48401fcf 1349 error_message = _(": unrecognizable v9a ancillary state register");
1277cdda
RH		 1350 goto error;
1351 }
1352
355afbcd
KR		 1353 case 'M':
1354 case 'm':
1355 if (strncmp (s, "%asr", 4) == 0)
1356 {
1357 s += 4;
680227f3 1358
48401fcf 1359 if (isdigit ((unsigned char) *s))
355afbcd
KR		 1360 {
1361 long num = 0;
1362
48401fcf 1363 while (isdigit ((unsigned char) *s))
355afbcd
KR		 1364 {
1365 num = num * 10 + *s - '0';
1366 ++s;
1367 }
1368
e86d5cf3 1369 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
355afbcd 1370 {
e86d5cf3
DE		 1371 if (num < 16 || 31 < num)
1372 {
48401fcf 1373 error_message = _(": asr number must be between 16 and 31");
e86d5cf3
DE		 1374 goto error;
1375 }
1376 }
1377 else
1378 {
2cb1807e 1379 if (num < 0 || 31 < num)
e86d5cf3 1380 {
48401fcf 1381 error_message = _(": asr number must be between 0 and 31");
e86d5cf3
DE		 1382 goto error;
1383 }
1384 }
355afbcd
KR		 1385
1386 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1387 continue;
1388 }
1389 else
1390 {
48401fcf 1391 error_message = _(": expecting %asrN");
355afbcd 1392 goto error;
e86d5cf3
DE		 1393 }
1394 } /* if %asr */
355afbcd
KR		 1395 break;
1396
355afbcd 1397 case 'I':
125f0b0d 1398 the_insn.reloc = BFD_RELOC_SPARC_11;
355afbcd
KR		 1399 goto immediate;
1400
1401 case 'j':
125f0b0d 1402 the_insn.reloc = BFD_RELOC_SPARC_10;
355afbcd
KR		 1403 goto immediate;
1404
8dd07a84
ILT		 1405 case 'X':
1406 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1407 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1408 the_insn.reloc = BFD_RELOC_SPARC_5;
1409 else
1410 the_insn.reloc = BFD_RELOC_SPARC13;
1411 /* These fields are unsigned, but for upward compatibility,
1412 allow negative values as well. */
8dd07a84
ILT		 1413 goto immediate;
1414
1415 case 'Y':
1416 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1417 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1418 the_insn.reloc = BFD_RELOC_SPARC_6;
1419 else
1420 the_insn.reloc = BFD_RELOC_SPARC13;
1421 /* These fields are unsigned, but for upward compatibility,
1422 allow negative values as well. */
8dd07a84
ILT		 1423 goto immediate;
1424
355afbcd 1425 case 'k':
125f0b0d 1426 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
355afbcd
KR		 1427 the_insn.pcrel = 1;
1428 goto immediate;
1429
1430 case 'G':
125f0b0d 1431 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
355afbcd
KR		 1432 the_insn.pcrel = 1;
1433 goto immediate;
1434
1435 case 'N':
1436 if (*s == 'p' && s[1] == 'n')
1437 {
1438 s += 2;
1439 continue;
1440 }
1441 break;
1442
1443 case 'T':
1444 if (*s == 'p' && s[1] == 't')
1445 {
1446 s += 2;
1447 continue;
1448 }
1449 break;
1450
1451 case 'z':
1452 if (*s == ' ')
1453 {
1454 ++s;
1455 }
0d44b3d1 1456 if (strncmp (s, "%icc", 4) == 0)
355afbcd 1457 {
0d44b3d1 1458 s += 4;
355afbcd
KR		 1459 continue;
1460 }
1461 break;
1462
1463 case 'Z':
1464 if (*s == ' ')
1465 {
1466 ++s;
1467 }
0d44b3d1 1468 if (strncmp (s, "%xcc", 4) == 0)
355afbcd 1469 {
0d44b3d1 1470 s += 4;
355afbcd
KR		 1471 continue;
1472 }
1473 break;
1474
1475 case '6':
1476 if (*s == ' ')
1477 {
1478 ++s;
1479 }
0d44b3d1 1480 if (strncmp (s, "%fcc0", 5) == 0)
355afbcd 1481 {
0d44b3d1 1482 s += 5;
355afbcd
KR		 1483 continue;
1484 }
1485 break;
1486
1487 case '7':
1488 if (*s == ' ')
1489 {
1490 ++s;
1491 }
0d44b3d1 1492 if (strncmp (s, "%fcc1", 5) == 0)
355afbcd 1493 {
0d44b3d1 1494 s += 5;
355afbcd
KR		 1495 continue;
1496 }
1497 break;
1498
1499 case '8':
1500 if (*s == ' ')
1501 {
1502 ++s;
1503 }
0d44b3d1 1504 if (strncmp (s, "%fcc2", 5) == 0)
355afbcd 1505 {
0d44b3d1 1506 s += 5;
355afbcd
KR		 1507 continue;
1508 }
1509 break;
1510
1511 case '9':
1512 if (*s == ' ')
1513 {
1514 ++s;
1515 }
0d44b3d1 1516 if (strncmp (s, "%fcc3", 5) == 0)
355afbcd 1517 {
0d44b3d1 1518 s += 5;
355afbcd
KR		 1519 continue;
1520 }
1521 break;
1522
1523 case 'P':
1524 if (strncmp (s, "%pc", 3) == 0)
1525 {
1526 s += 3;
1527 continue;
1528 }
1529 break;
1530
1531 case 'W':
1532 if (strncmp (s, "%tick", 5) == 0)
1533 {
1534 s += 5;
1535 continue;
1536 }
1537 break;
355afbcd
KR		 1538
1539 case '\0': /* end of args */
1540 if (*s == '\0')
1541 {
1542 match = 1;
1543 }
1544 break;
1545
1546 case '+':
1547 if (*s == '+')
1548 {
1549 ++s;
1550 continue;
1551 }
1552 if (*s == '-')
1553 {
1554 continue;
1555 }
1556 break;
1557
1558 case '[': /* these must match exactly */
1559 case ']':
1560 case ',':
1561 case ' ':
1562 if (*s++ == *args)
1563 continue;
1564 break;
1565
1566 case '#': /* must be at least one digit */
48401fcf 1567 if (isdigit ((unsigned char) *s++))
355afbcd 1568 {
48401fcf 1569 while (isdigit ((unsigned char) *s))
355afbcd
KR		 1570 {
1571 ++s;
1572 }
1573 continue;
1574 }
1575 break;
1576
1577 case 'C': /* coprocessor state register */
1578 if (strncmp (s, "%csr", 4) == 0)
1579 {
1580 s += 4;
1581 continue;
1582 }
1583 break;
1584
1585 case 'b': /* next operand is a coprocessor register */
1586 case 'c':
1587 case 'D':
48401fcf 1588 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
355afbcd
KR		 1589 {
1590 mask = *s++;
48401fcf 1591 if (isdigit ((unsigned char) *s))
355afbcd
KR		 1592 {
1593 mask = 10 * (mask - '0') + (*s++ - '0');
1594 if (mask >= 32)
1595 {
1596 break;
1597 }
1598 }
1599 else
1600 {
1601 mask -= '0';
1602 }
1603 switch (*args)
1604 {
1605
1606 case 'b':
1607 opcode |= mask << 14;
1608 continue;
1609
1610 case 'c':
1611 opcode |= mask;
1612 continue;
1613
1614 case 'D':
1615 opcode |= mask << 25;
1616 continue;
1617 }
1618 }
1619 break;
1620
1621 case 'r': /* next operand must be a register */
ed94c2b8 1622 case 'O':
355afbcd
KR		 1623 case '1':
1624 case '2':
1625 case 'd':
1626 if (*s++ == '%')
1627 {
1628 switch (c = *s++)
1629 {
1630
1631 case 'f': /* frame pointer */
1632 if (*s++ == 'p')
1633 {
1634 mask = 0x1e;
1635 break;
1636 }
1637 goto error;
1638
1639 case 'g': /* global register */
1640 if (isoctal (c = *s++))
1641 {
1642 mask = c - '0';
1643 break;
1644 }
1645 goto error;
1646
1647 case 'i': /* in register */
1648 if (isoctal (c = *s++))
1649 {
1650 mask = c - '0' + 24;
1651 break;
1652 }
1653 goto error;
1654
1655 case 'l': /* local register */
1656 if (isoctal (c = *s++))
1657 {
1658 mask = (c - '0' + 16);
1659 break;
1660 }
1661 goto error;
1662
1663 case 'o': /* out register */
1664 if (isoctal (c = *s++))
1665 {
1666 mask = (c - '0' + 8);
1667 break;
1668 }
1669 goto error;
1670
1671 case 's': /* stack pointer */
1672 if (*s++ == 'p')
1673 {
1674 mask = 0xe;
1675 break;
1676 }
1677 goto error;
1678
1679 case 'r': /* any register */
48401fcf 1680 if (!isdigit ((unsigned char) (c = *s++)))
355afbcd
KR		 1681 {
1682 goto error;
1683 }
1684 /* FALLTHROUGH */
1685 case '0':
1686 case '1':
1687 case '2':
1688 case '3':
1689 case '4':
1690 case '5':
1691 case '6':
1692 case '7':
1693 case '8':
1694 case '9':
48401fcf 1695 if (isdigit ((unsigned char) *s))
355afbcd
KR		 1696 {
1697 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
680227f3 1698 {
680227f3
KR		 1699 goto error;
1700 }
355afbcd
KR		 1701 }
1702 else
1703 {
1704 c -= '0';
1705 }
1706 mask = c;
1707 break;
1708
1709 default:
1710 goto error;
1711 }
6df07e7f
DE		 1712
1713 /* Got the register, now figure out where
1714 it goes in the opcode. */
355afbcd
KR		 1715 switch (*args)
1716 {
355afbcd
KR		 1717 case '1':
1718 opcode |= mask << 14;
1719 continue;
1720
1721 case '2':
1722 opcode |= mask;
1723 continue;
1724
1725 case 'd':
1726 opcode |= mask << 25;
1727 continue;
1728
1729 case 'r':
1730 opcode |= (mask << 25) | (mask << 14);
1731 continue;
ed94c2b8
ILT		 1732
1733 case 'O':
1734 opcode |= (mask << 25) | (mask << 0);
1735 continue;
355afbcd
KR		 1736 }
1737 }
1738 break;
1739
1740 case 'e': /* next operand is a floating point register */
1741 case 'v':
1742 case 'V':
1743
1744 case 'f':
1745 case 'B':
1746 case 'R':
1747
1748 case 'g':
1749 case 'H':
1750 case 'J':
1751 {
1752 char format;
1753
1754 if (*s++ == '%'
355afbcd 1755 && ((format = *s) == 'f')
48401fcf 1756 && isdigit ((unsigned char) *++s))
355afbcd 1757 {
48401fcf 1758 for (mask = 0; isdigit ((unsigned char) *s); ++s)
355afbcd
KR		 1759 {
1760 mask = 10 * mask + (*s - '0');
1761 } /* read the number */
1762
1763 if ((*args == 'v'
1764 || *args == 'B'
1765 || *args == 'H')
1766 && (mask & 1))
1767 {
1768 break;
1769 } /* register must be even numbered */
1770
1771 if ((*args == 'V'
1772 || *args == 'R'
1773 || *args == 'J')
1774 && (mask & 3))
1775 {
1776 break;
1777 } /* register must be multiple of 4 */
1778
125f0b0d 1779 if (mask >= 64)
355afbcd 1780 {
8dd07a84 1781 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
48401fcf 1782 error_message = _(": There are only 64 f registers; [0-63]");
6df07e7f 1783 else
48401fcf 1784 error_message = _(": There are only 32 f registers; [0-31]");
125f0b0d
KR		 1785 goto error;
1786 } /* on error */
6df07e7f 1787 else if (mask >= 32)
125f0b0d 1788 {
8dd07a84 1789 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
6df07e7f
DE		 1790 {
1791 v9_arg_p = 1;
1792 mask -= 31; /* wrap high bit */
1793 }
1794 else
1795 {
48401fcf 1796 error_message = _(": There are only 32 f registers; [0-31]");
6df07e7f
DE		 1797 goto error;
1798 }
1799 }
125f0b0d
KR		 1800 }
1801 else
1802 {
1803 break;
1804 } /* if not an 'f' register. */
355afbcd
KR		 1805
1806 switch (*args)
1807 {
355afbcd
KR		 1808 case 'v':
1809 case 'V':
1810 case 'e':
1811 opcode |= RS1 (mask);
1812 continue;
1813
1814
1815 case 'f':
1816 case 'B':
1817 case 'R':
1818 opcode |= RS2 (mask);
1819 continue;
1820
1821 case 'g':
1822 case 'H':
1823 case 'J':
1824 opcode |= RD (mask);
1825 continue;
1826 } /* pack it in. */
1827
1828 know (0);
1829 break;
1830 } /* float arg */
1831
1832 case 'F':
1833 if (strncmp (s, "%fsr", 4) == 0)
1834 {
1835 s += 4;
1836 continue;
1837 }
1838 break;
1839
2b063e6d
ILT		 1840 case '0': /* 64 bit immediate (setx insn) */
1841 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
1842 goto immediate;
1843
355afbcd 1844 case 'h': /* high 22 bits */
428d312b 1845 the_insn.reloc = BFD_RELOC_HI22;
355afbcd
KR		 1846 goto immediate;
1847
1848 case 'l': /* 22 bit PC relative immediate */
428d312b 1849 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
355afbcd
KR		 1850 the_insn.pcrel = 1;
1851 goto immediate;
1852
1853 case 'L': /* 30 bit immediate */
428d312b 1854 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
355afbcd
KR		 1855 the_insn.pcrel = 1;
1856 goto immediate;
1857
1858 case 'n': /* 22 bit immediate */
428d312b 1859 the_insn.reloc = BFD_RELOC_SPARC22;
355afbcd
KR		 1860 goto immediate;
1861
1862 case 'i': /* 13 bit immediate */
7ab2e983 1863 the_insn.reloc = BFD_RELOC_SPARC13;
355afbcd 1864
54b9ebdd 1865 /* fallthrough */
355afbcd
KR		 1866
1867 immediate:
1868 if (*s == ' ')
1869 s++;
54b9ebdd
DE		 1870
1871 /* Check for %hi, etc. */
355afbcd
KR		 1872 if (*s == '%')
1873 {
54b9ebdd
DE		 1874 static struct ops {
1875 /* The name as it appears in assembler. */
1876 char *name;
1877 /* strlen (name), precomputed for speed */
1878 int len;
1879 /* The reloc this pseudo-op translates to. */
1880 int reloc;
1881 /* Non-zero if for v9 only. */
1882 int v9_p;
1883 /* Non-zero if can be used in pc-relative contexts. */
1884 int pcrel_p;/*FIXME:wip*/
1885 } ops[] = {
1886 /* hix/lox must appear before hi/lo so %hix won't be
1887 mistaken for %hi. */
1888 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
1889 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
1890 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
1891 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
1892 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
1893 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
1894 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
1895 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
1896 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
1897 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
1898 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
1899 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
1900 { NULL }
1901 };
1902 struct ops *o;
1903
1904 for (o = ops; o->name; o++)
1905 if (strncmp (s + 1, o->name, o->len) == 0)
1906 break;
1907 if (o->name == NULL)
355afbcd 1908 break;
54b9ebdd
DE		 1909
1910 the_insn.reloc = o->reloc;
1911 s += o->len + 1;
1912 v9_arg_p = o->v9_p;
355afbcd 1913 }
54b9ebdd 1914
af6f39b4 1915 /* Note that if the get_expression() fails, we will still
9b6a882e
KR		 1916 have created U entries in the symbol table for the
1917 'symbols' in the input string. Try not to create U
1918 symbols for registers, etc. */
355afbcd 1919 {
9b6a882e
KR		 1920 /* This stuff checks to see if the expression ends in
1921 +%reg. If it does, it removes the register from
1922 the expression, and re-sets 's' to point to the
1923 right place. */
355afbcd
KR		 1924
1925 char *s1;
1926
2b063e6d 1927 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ;
355afbcd 1928
48401fcf 1929 if (s1 != s && isdigit ((unsigned char) s1[-1]))
355afbcd
KR		 1930 {
1931 if (s1[-2] == '%' && s1[-3] == '+')
1932 {
1933 s1 -= 3;
1934 *s1 = '\0';
af6f39b4 1935 (void) get_expression (s);
355afbcd
KR		 1936 *s1 = '+';
1937 s = s1;
1938 continue;
1939 }
1940 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
1941 {
1942 s1 -= 4;
1943 *s1 = '\0';
af6f39b4 1944 (void) get_expression (s);
355afbcd
KR		 1945 *s1 = '+';
1946 s = s1;
1947 continue;
1948 }
1949 }
1950 }
af6f39b4 1951 (void) get_expression (s);
355afbcd
KR		 1952 s = expr_end;
1953
54b9ebdd 1954 /* Check for constants that don't require emitting a reloc. */
9b6a882e
KR		 1955 if (the_insn.exp.X_op == O_constant
1956 && the_insn.exp.X_add_symbol == 0
1957 && the_insn.exp.X_op_symbol == 0)
1958 {
7ab2e983
ILT		 1959 /* For pc-relative call instructions, we reject
1960 constants to get better code. */
1961 if (the_insn.pcrel
1962 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
54b9ebdd 1963 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
7ab2e983 1964 {
48401fcf 1965 error_message = _(": PC-relative operand can't be a constant");
7ab2e983
ILT		 1966 goto error;
1967 }
9b6a882e 1968
54b9ebdd
DE		 1969 /* Constants that won't fit are checked in md_apply_fix3
1970 and bfd_install_relocation.
1971 ??? It would be preferable to install the constants
1972 into the insn here and save having to create a fixS
1973 for each one. There already exists code to handle
1974 all the various cases (e.g. in md_apply_fix3 and
1975 bfd_install_relocation) so duplicating all that code
1976 here isn't right. */
1977 }
355afbcd
KR		 1978
1979 continue;
1980
1981 case 'a':
1982 if (*s++ == 'a')
1983 {
1984 opcode |= ANNUL;
1985 continue;
1986 }
1987 break;
1988
1989 case 'A':
1990 {
ed9638af
KR		 1991 int asi = 0;
1992
1993 /* Parse an asi. */
1994 if (*s == '#')
1995 {
6df07e7f 1996 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
ed9638af 1997 {
48401fcf 1998 error_message = _(": invalid ASI name");
ed9638af
KR		 1999 goto error;
2000 }
2001 }
a7aa7a2b 2002 else
ed9638af 2003 {
6df07e7f 2004 if (! parse_const_expr_arg (&s, &asi))
a7aa7a2b 2005 {
48401fcf 2006 error_message = _(": invalid ASI expression");
a7aa7a2b
ILT		 2007 goto error;
2008 }
ed9638af
KR		 2009 if (asi < 0 || asi > 255)
2010 {
48401fcf 2011 error_message = _(": invalid ASI number");
ed9638af
KR		 2012 goto error;
2013 }
2014 }
ed9638af
KR		 2015 opcode |= ASI (asi);
2016 continue;
355afbcd
KR		 2017 } /* alternate space */
2018
2019 case 'p':
2020 if (strncmp (s, "%psr", 4) == 0)
2021 {
2022 s += 4;
2023 continue;
2024 }
2025 break;
2026
2027 case 'q': /* floating point queue */
2028 if (strncmp (s, "%fq", 3) == 0)
2029 {
2030 s += 3;
2031 continue;
2032 }
2033 break;
2034
2035 case 'Q': /* coprocessor queue */
2036 if (strncmp (s, "%cq", 3) == 0)
2037 {
2038 s += 3;
2039 continue;
2040 }
2041 break;
2042
2043 case 'S':
2b063e6d
ILT		 2044 if (strcmp (str, "set") == 0
2045 || strcmp (str, "setuw") == 0)
355afbcd
KR		 2046 {
2047 special_case = SPECIAL_CASE_SET;
2048 continue;
2049 }
2b063e6d
ILT		 2050 else if (strcmp (str, "setsw") == 0)
2051 {
2052 special_case = SPECIAL_CASE_SETSW;
2053 continue;
2054 }
2055 else if (strcmp (str, "setx") == 0)
2056 {
2057 special_case = SPECIAL_CASE_SETX;
2058 continue;
2059 }
355afbcd
KR		 2060 else if (strncmp (str, "fdiv", 4) == 0)
2061 {
2062 special_case = SPECIAL_CASE_FDIV;
2063 continue;
2064 }
2065 break;
2066
355afbcd
KR		 2067 case 'o':
2068 if (strncmp (s, "%asi", 4) != 0)
2069 break;
2070 s += 4;
2071 continue;
2072
2073 case 's':
2074 if (strncmp (s, "%fprs", 5) != 0)
2075 break;
2076 s += 5;
2077 continue;
2078
2079 case 'E':
2080 if (strncmp (s, "%ccr", 4) != 0)
2081 break;
2082 s += 4;
2083 continue;
680227f3 2084
355afbcd
KR		 2085 case 't':
2086 if (strncmp (s, "%tbr", 4) != 0)
2087 break;
2088 s += 4;
2089 continue;
2090
2091 case 'w':
2092 if (strncmp (s, "%wim", 4) != 0)
2093 break;
2094 s += 4;
2095 continue;
2096
5e0a90a8
KR		 2097 case 'x':
2098 {
2099 char *push = input_line_pointer;
2100 expressionS e;
2101
2102 input_line_pointer = s;
2103 expression (&e);
2104 if (e.X_op == O_constant)
2105 {
2106 int n = e.X_add_number;
2107 if (n != e.X_add_number || (n & ~0x1ff) != 0)
48401fcf 2108 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
5e0a90a8
KR		 2109 else
2110 opcode |= e.X_add_number << 5;
2111 }
2112 else
48401fcf 2113 as_bad (_("non-immediate OPF operand, ignored"));
5e0a90a8
KR		 2114 s = input_line_pointer;
2115 input_line_pointer = push;
2116 continue;
2117 }
5e0a90a8 2118
355afbcd
KR		 2119 case 'y':
2120 if (strncmp (s, "%y", 2) != 0)
2121 break;
2122 s += 2;
2123 continue;
2124
e86d5cf3
DE		 2125 case 'u':
2126 case 'U':
2127 {
2128 /* Parse a sparclet cpreg. */
2129 int cpreg;
2130 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2131 {
48401fcf 2132 error_message = _(": invalid cpreg name");
e86d5cf3
DE		 2133 goto error;
2134 }
2135 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2136 continue;
2137 }
2138
355afbcd 2139 default:
48401fcf 2140 as_fatal (_("failed sanity check."));
355afbcd 2141 } /* switch on arg code */
6df07e7f
DE		 2142
2143 /* Break out of for() loop. */
355afbcd
KR		 2144 break;
2145 } /* for each arg that we expect */
6df07e7f 2146
355afbcd
KR		 2147 error:
2148 if (match == 0)
2149 {
2150 /* Args don't match. */
48401fcf 2151 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
a7aa7a2b
ILT		 2152 && (insn->name == insn[1].name
2153 || !strcmp (insn->name, insn[1].name)))
355afbcd
KR		 2154 {
2155 ++insn;
2156 s = argsStart;
2157 continue;
2158 }
2159 else
2160 {
48401fcf 2161 as_bad (_("Illegal operands%s"), error_message);
355afbcd
KR		 2162 return;
2163 }
2164 }
2165 else
2166 {
e70ad5d5 2167 /* We have a match. Now see if the architecture is ok. */
d8b42b96 2168 int needed_arch_mask = insn->architecture;
e70ad5d5 2169
d8b42b96 2170 if (v9_arg_p)
355afbcd 2171 {
d8b42b96
DE		 2172 needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9)
2173 | (1 << SPARC_OPCODE_ARCH_V9A));
2174 needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
e70ad5d5 2175 }
d8b42b96
DE		 2176
2177 if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture))
2178 ; /* ok */
2179 /* Can we bump up the architecture? */
2180 else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture))
e70ad5d5 2181 {
d8b42b96
DE		 2182 enum sparc_opcode_arch_val needed_architecture =
2183 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2184 & needed_arch_mask);
2185
2186 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
e70ad5d5
DE		 2187 if (warn_on_bump
2188 && needed_architecture > warn_after_architecture)
355afbcd 2189 {
48401fcf 2190 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
e70ad5d5
DE		 2191 sparc_opcode_archs[current_architecture].name,
2192 sparc_opcode_archs[needed_architecture].name,
2193 str);
d8b42b96 2194 warn_after_architecture = needed_architecture;
355afbcd 2195 }
e70ad5d5
DE		 2196 current_architecture = needed_architecture;
2197 }
d8b42b96 2198 /* Conflict. */
110b814d
DE		 2199 /* ??? This seems to be a bit fragile. What if the next entry in
2200 the opcode table is the one we want and it is supported?
2201 It is possible to arrange the table today so that this can't
2202 happen but what about tomorrow? */
d8b42b96
DE		 2203 else
2204 {
110b814d
DE		 2205 int arch,printed_one_p = 0;
2206 char *p;
2207 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2208
2209 /* Create a list of the architectures that support the insn. */
2210 needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture);
2211 p = required_archs;
2212 arch = sparc_ffs (needed_arch_mask);
2213 while ((1 << arch) <= needed_arch_mask)
2214 {
2215 if ((1 << arch) & needed_arch_mask)
2216 {
2217 if (printed_one_p)
2218 *p++ = '|';
2219 strcpy (p, sparc_opcode_archs[arch].name);
2220 p += strlen (p);
2221 printed_one_p = 1;
2222 }
2223 ++arch;
2224 }
d8b42b96 2225
48401fcf
TT		 2226 as_bad (_("Architecture mismatch on \"%s\"."), str);
2227 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
110b814d 2228 required_archs,
d8b42b96
DE		 2229 sparc_opcode_archs[max_architecture].name);
2230 return;
2231 }
e70ad5d5 2232 } /* if no match */
355afbcd
KR		 2233
2234 break;
e70ad5d5 2235 } /* forever looking for a match */
355afbcd
KR		 2236
2237 the_insn.opcode = opcode;
c999fd9f 2238}
355afbcd 2239
af6f39b4
DE		 2240/* Parse an argument that can be expressed as a keyword.
2241 (eg: #StoreStore or %ccfr).
2242 The result is a boolean indicating success.
2243 If successful, INPUT_POINTER is updated. */
2244
2245static int
2246parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2247 int (*lookup_fn) PARAMS ((const char *));
2248 char **input_pointerP;
2249 int *valueP;
2250{
2251 int value;
2252 char c, *p, *q;
2253
2254 p = *input_pointerP;
48401fcf
TT		 2255 for (q = p + (*p == '#' || *p == '%');
2256 isalnum ((unsigned char) *q) || *q == '_';
2257 ++q)
af6f39b4
DE		 2258 continue;
2259 c = *q;
2260 *q = 0;
2261 value = (*lookup_fn) (p);
2262 *q = c;
2263 if (value == -1)
2264 return 0;
2265 *valueP = value;
2266 *input_pointerP = q;
2267 return 1;
2268}
2269
2270/* Parse an argument that is a constant expression.
2271 The result is a boolean indicating success. */
2272
2273static int
2274parse_const_expr_arg (input_pointerP, valueP)
2275 char **input_pointerP;
2276 int *valueP;
2277{
2278 char *save = input_line_pointer;
2279 expressionS exp;
2280
2281 input_line_pointer = *input_pointerP;
2282 /* The next expression may be something other than a constant
2283 (say if we're not processing the right variant of the insn).
2284 Don't call expression unless we're sure it will succeed as it will
2285 signal an error (which we want to defer until later). */
2286 /* FIXME: It might be better to define md_operand and have it recognize
2287 things like %asi, etc. but continuing that route through to the end
2288 is a lot of work. */
2289 if (*input_line_pointer == '%')
2290 {
2291 input_line_pointer = save;
2292 return 0;
2293 }
2294 expression (&exp);
2295 *input_pointerP = input_line_pointer;
2296 input_line_pointer = save;
2297 if (exp.X_op != O_constant)
2298 return 0;
2299 *valueP = exp.X_add_number;
2300 return 1;
2301}
2302
2303/* Subroutine of sparc_ip to parse an expression. */
2304
355afbcd 2305static int
af6f39b4 2306get_expression (str)
355afbcd 2307 char *str;
fecd2382 2308{
355afbcd
KR		 2309 char *save_in;
2310 segT seg;
2311
2312 save_in = input_line_pointer;
2313 input_line_pointer = str;
428d312b 2314 seg = expression (&the_insn.exp);
58d4951d
ILT		 2315 if (seg != absolute_section
2316 && seg != text_section
2317 && seg != data_section
2318 && seg != bss_section
2319 && seg != undefined_section)
355afbcd 2320 {
48401fcf 2321 the_insn.error = _("bad segment");
355afbcd
KR		 2322 expr_end = input_line_pointer;
2323 input_line_pointer = save_in;
2324 return 1;
2325 }
2326 expr_end = input_line_pointer;
2327 input_line_pointer = save_in;
2328 return 0;
af6f39b4
DE		 2329}
2330
2331/* Subroutine of md_assemble to output one insn. */
2332
2333static void
2334output_insn (insn, the_insn)
2335 const struct sparc_opcode *insn;
2336 struct sparc_it *the_insn;
2337{
2338 char *toP = frag_more (4);
2339
2340 /* put out the opcode */
2341 if (INSN_BIG_ENDIAN)
2342 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2343 else
2344 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
fecd2382 2345
af6f39b4
DE		 2346 /* put out the symbol-dependent stuff */
2347 if (the_insn->reloc != BFD_RELOC_NONE)
2348 {
54b9ebdd
DE		 2349 fixS *fixP = fix_new_exp (frag_now, /* which frag */
2350 (toP - frag_now->fr_literal), /* where */
2351 4, /* size */
2352 &the_insn->exp,
2353 the_insn->pcrel,
2354 the_insn->reloc);
2355 /* Turn off overflow checking in fixup_segment. We'll do our
2356 own overflow checking in md_apply_fix3. This is necessary because
2357 the insn size is 4 and fixup_segment will signal an overflow for
2358 large 8 byte quantities. */
2359 fixP->fx_no_overflow = 1;
af6f39b4 2360 }
fecd2382 2361
af6f39b4
DE		 2362 last_insn = insn;
2363 last_opcode = the_insn->opcode;
2364}
2365\f
fecd2382
RP		 2366/*
2367 This is identical to the md_atof in m68k.c. I think this is right,
2368 but I'm not sure.
355afbcd 2369
fecd2382
RP		 2370 Turn a string in input_line_pointer into a floating point constant of type
2371 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2372 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2373 */
2374
2375/* Equal to MAX_PRECISION in atof-ieee.c */
2376#define MAX_LITTLENUMS 6
2377
355afbcd
KR		 2378char *
2379md_atof (type, litP, sizeP)
2380 char type;
2381 char *litP;
2382 int *sizeP;
fecd2382 2383{
2b063e6d 2384 int i,prec;
355afbcd 2385 LITTLENUM_TYPE words[MAX_LITTLENUMS];
355afbcd 2386 char *t;
355afbcd
KR		 2387
2388 switch (type)
2389 {
355afbcd
KR		 2390 case 'f':
2391 case 'F':
2392 case 's':
2393 case 'S':
2394 prec = 2;
2395 break;
2396
2397 case 'd':
2398 case 'D':
2399 case 'r':
2400 case 'R':
2401 prec = 4;
2402 break;
2403
2404 case 'x':
2405 case 'X':
2406 prec = 6;
2407 break;
2408
2409 case 'p':
2410 case 'P':
2411 prec = 6;
2412 break;
2413
2414 default:
2415 *sizeP = 0;
48401fcf 2416 return _("Bad call to MD_ATOF()");
355afbcd 2417 }
2b063e6d 2418
355afbcd
KR		 2419 t = atof_ieee (input_line_pointer, type, words);
2420 if (t)
2421 input_line_pointer = t;
2422 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2b063e6d
ILT		 2423
2424 if (target_big_endian)
355afbcd 2425 {
2b063e6d
ILT		 2426 for (i = 0; i < prec; i++)
2427 {
2428 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2429 litP += sizeof (LITTLENUM_TYPE);
2430 }
2431 }
2432 else
2433 {
2434 for (i = prec - 1; i >= 0; i--)
2435 {
2436 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2437 litP += sizeof (LITTLENUM_TYPE);
2438 }
355afbcd 2439 }
2b063e6d 2440
ed9638af
KR		 2441 return 0;
2442}
fecd2382 2443
2b063e6d
ILT		 2444/* Write a value out to the object file, using the appropriate
2445 endianness. */
2446
355afbcd
KR		 2447void
2448md_number_to_chars (buf, val, n)
2449 char *buf;
125f0b0d 2450 valueT val;
355afbcd 2451 int n;
fecd2382 2452{
2b063e6d
ILT		 2453 if (target_big_endian)
2454 number_to_chars_bigendian (buf, val, n);
2455 else
2456 number_to_chars_littleendian (buf, val, n);
c999fd9f 2457}
af6f39b4 2458\f
fecd2382
RP		 2459/* Apply a fixS to the frags, now that we know the value it ought to
2460 hold. */
2461
428d312b 2462int
2b063e6d 2463md_apply_fix3 (fixP, value, segment)
355afbcd 2464 fixS *fixP;
125f0b0d 2465 valueT *value;
2b063e6d 2466 segT segment;
fecd2382 2467{
355afbcd 2468 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
125f0b0d 2469 offsetT val;
2b063e6d 2470 long insn;
428d312b 2471
428d312b 2472 val = *value;
355afbcd 2473
428d312b 2474 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
355afbcd
KR		 2475
2476 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
2477
7766838e
ILT		 2478#ifdef OBJ_ELF
2479 /* FIXME: SPARC ELF relocations don't use an addend in the data
2480 field itself. This whole approach should be somehow combined
9e6f4c6b 2481 with the calls to bfd_install_relocation. Also, the value passed
a7aa7a2b
ILT		 2482 in by fixup_segment includes the value of a defined symbol. We
2483 don't want to include the value of an externally visible symbol. */
7766838e 2484 if (fixP->fx_addsy != NULL)
a7aa7a2b 2485 {
2b063e6d
ILT		 2486 if (fixP->fx_addsy->sy_used_in_reloc
2487 && (S_IS_EXTERNAL (fixP->fx_addsy)
2488 || S_IS_WEAK (fixP->fx_addsy)
2489 || (sparc_pic_code && ! fixP->fx_pcrel)
2490 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2491 && ((bfd_get_section_flags (stdoutput,
2492 S_GET_SEGMENT (fixP->fx_addsy))
2493 & SEC_LINK_ONCE) != 0
2494 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2495 ".gnu.linkonce",
2496 sizeof ".gnu.linkonce" - 1) == 0)))
a7aa7a2b
ILT		 2497 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2498 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2499 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2500 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2501 return 1;
2502 }
7766838e
ILT		 2503#endif
2504
c999fd9f
KR		 2505 /* This is a hack. There should be a better way to
2506 handle this. Probably in terms of howto fields, once
2507 we can look at these fixups in terms of howtos. */
428d312b 2508 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
c999fd9f 2509 val += fixP->fx_where + fixP->fx_frag->fr_address;
355afbcd 2510
ade614d5
KR		 2511#ifdef OBJ_AOUT
2512 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2513 generate a reloc, then we just want to let the reloc addend set
2514 the value. We do not want to also stuff the addend into the
2515 object file. Including the addend in the object file works when
2516 doing a static link, because the linker will ignore the object
2517 file contents. However, the dynamic linker does not ignore the
2518 object file contents. */
2519 if (fixP->fx_addsy != NULL
2520 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2521 val = 0;
4c67b523
ILT		 2522
2523 /* When generating PIC code, we do not want an addend for a reloc
2524 against a local symbol. We adjust fx_addnumber to cancel out the
2525 value already included in val, and to also cancel out the
2526 adjustment which bfd_install_relocation will create. */
2527 if (sparc_pic_code
2528 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2529 && fixP->fx_addsy != NULL
2530 && ! S_IS_COMMON (fixP->fx_addsy)
2531 && (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0)
2532 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
a5002978
CM		 2533
2534 /* When generating PIC code, we need to fiddle to get
2535 bfd_install_relocation to do the right thing for a PC relative
2536 reloc against a local symbol which we are going to keep. */
2537 if (sparc_pic_code
2538 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2539 && fixP->fx_addsy != NULL
2540 && (S_IS_EXTERNAL (fixP->fx_addsy)
2541 || S_IS_WEAK (fixP->fx_addsy))
2542 && S_IS_DEFINED (fixP->fx_addsy)
2543 && ! S_IS_COMMON (fixP->fx_addsy))
2544 {
2545 val = 0;
2546 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2547 }
ade614d5
KR		 2548#endif
2549
2b063e6d 2550 /* If this is a data relocation, just output VAL. */
58d4951d 2551
2b063e6d
ILT		 2552 if (fixP->fx_r_type == BFD_RELOC_16)
2553 {
2554 md_number_to_chars (buf, val, 2);
2555 }
fc23c14e
SC		 2556 else if (fixP->fx_r_type == BFD_RELOC_32
2557 || fixP->fx_r_type == BFD_RELOC_SPARC_32LE)
2b063e6d
ILT		 2558 {
2559 md_number_to_chars (buf, val, 4);
2560 }
2561 else if (fixP->fx_r_type == BFD_RELOC_64)
2562 {
2563 md_number_to_chars (buf, val, 8);
2564 }
2565 else
2566 {
2567 /* It's a relocation against an instruction. */
355afbcd 2568
2b063e6d
ILT		 2569 if (INSN_BIG_ENDIAN)
2570 insn = bfd_getb32 ((unsigned char *) buf);
2571 else
2572 insn = bfd_getl32 ((unsigned char *) buf);
2573
2574 switch (fixP->fx_r_type)
2575 {
2576 case BFD_RELOC_32_PCREL_S2:
2577 val = val >> 2;
2578 /* FIXME: This increment-by-one deserves a comment of why it's
2579 being done! */
2580 if (! sparc_pic_code
2581 || fixP->fx_addsy == NULL
2582 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2583 ++val;
2584 insn |= val & 0x3fffffff;
2585 break;
693b21e7 2586
2b063e6d
ILT		 2587 case BFD_RELOC_SPARC_11:
2588 if (! in_signed_range (val, 0x7ff))
48401fcf
TT		 2589 as_bad_where (fixP->fx_file, fixP->fx_line,
2590 _("relocation overflow"));
2b063e6d
ILT		 2591 insn |= val & 0x7ff;
2592 break;
355afbcd 2593
2b063e6d
ILT		 2594 case BFD_RELOC_SPARC_10:
2595 if (! in_signed_range (val, 0x3ff))
48401fcf
TT		 2596 as_bad_where (fixP->fx_file, fixP->fx_line,
2597 _("relocation overflow"));
2b063e6d
ILT		 2598 insn |= val & 0x3ff;
2599 break;
355afbcd 2600
54b9ebdd
DE		 2601 case BFD_RELOC_SPARC_7:
2602 if (! in_bitfield_range (val, 0x7f))
48401fcf
TT		 2603 as_bad_where (fixP->fx_file, fixP->fx_line,
2604 _("relocation overflow"));
54b9ebdd
DE		 2605 insn |= val & 0x7f;
2606 break;
2607
2b063e6d
ILT		 2608 case BFD_RELOC_SPARC_6:
2609 if (! in_bitfield_range (val, 0x3f))
48401fcf
TT		 2610 as_bad_where (fixP->fx_file, fixP->fx_line,
2611 _("relocation overflow"));
2b063e6d
ILT		 2612 insn |= val & 0x3f;
2613 break;
355afbcd 2614
2b063e6d
ILT		 2615 case BFD_RELOC_SPARC_5:
2616 if (! in_bitfield_range (val, 0x1f))
48401fcf
TT		 2617 as_bad_where (fixP->fx_file, fixP->fx_line,
2618 _("relocation overflow"));
2b063e6d
ILT		 2619 insn |= val & 0x1f;
2620 break;
8dd07a84 2621
2b063e6d
ILT		 2622 case BFD_RELOC_SPARC_WDISP16:
2623 /* FIXME: simplify */
2624 if (((val > 0) && (val & ~0x3fffc))
2625 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
48401fcf
TT		 2626 as_bad_where (fixP->fx_file, fixP->fx_line,
2627 _("relocation overflow"));
2b063e6d
ILT		 2628 /* FIXME: The +1 deserves a comment. */
2629 val = (val >> 2) + 1;
2630 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
2631 break;
8dd07a84 2632
2b063e6d
ILT		 2633 case BFD_RELOC_SPARC_WDISP19:
2634 /* FIXME: simplify */
2635 if (((val > 0) && (val & ~0x1ffffc))
2636 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
48401fcf
TT		 2637 as_bad_where (fixP->fx_file, fixP->fx_line,
2638 _("relocation overflow"));
2b063e6d
ILT		 2639 /* FIXME: The +1 deserves a comment. */
2640 val = (val >> 2) + 1;
2641 insn |= val & 0x7ffff;
2642 break;
8dd07a84 2643
2b063e6d
ILT		 2644 case BFD_RELOC_SPARC_HH22:
2645 val = BSR (val, 32);
2646 /* intentional fallthrough */
8dd07a84 2647
2b063e6d
ILT		 2648 case BFD_RELOC_SPARC_LM22:
2649 case BFD_RELOC_HI22:
2650 if (!fixP->fx_addsy)
2651 {
2652 insn |= (val >> 10) & 0x3fffff;
2653 }
2654 else
2655 {
2656 /* FIXME: Need comment explaining why we do this. */
2657 insn &= ~0xffff;
2658 }
2659 break;
355afbcd 2660
2b063e6d
ILT		 2661 case BFD_RELOC_SPARC22:
2662 if (val & ~0x003fffff)
48401fcf
TT		 2663 as_bad_where (fixP->fx_file, fixP->fx_line,
2664 _("relocation overflow"));
2b063e6d
ILT		 2665 insn |= (val & 0x3fffff);
2666 break;
355afbcd 2667
2b063e6d
ILT		 2668 case BFD_RELOC_SPARC_HM10:
2669 val = BSR (val, 32);
2670 /* intentional fallthrough */
355afbcd 2671
2b063e6d
ILT		 2672 case BFD_RELOC_LO10:
2673 if (!fixP->fx_addsy)
2674 {
2675 insn |= val & 0x3ff;
2676 }
2677 else
2678 {
2679 /* FIXME: Need comment explaining why we do this. */
2680 insn &= ~0xff;
2681 }
2682 break;
355afbcd 2683
2b063e6d
ILT		 2684 case BFD_RELOC_SPARC13:
2685 if (! in_signed_range (val, 0x1fff))
48401fcf
TT		 2686 as_bad_where (fixP->fx_file, fixP->fx_line,
2687 _("relocation overflow"));
2b063e6d
ILT		 2688 insn |= val & 0x1fff;
2689 break;
355afbcd 2690
2b063e6d
ILT		 2691 case BFD_RELOC_SPARC_WDISP22:
2692 val = (val >> 2) + 1;
2693 /* FALLTHROUGH */
2694 case BFD_RELOC_SPARC_BASE22:
2695 insn |= val & 0x3fffff;
2696 break;
355afbcd 2697
54b9ebdd
DE		 2698 case BFD_RELOC_SPARC_H44:
2699 if (!fixP->fx_addsy)
2700 {
2701 bfd_vma tval = val;
2702 tval >>= 22;
54b9ebdd
DE		 2703 insn |= tval & 0x3fffff;
2704 }
2705 break;
2706
2707 case BFD_RELOC_SPARC_M44:
2708 if (!fixP->fx_addsy)
2709 insn |= (val >> 12) & 0x3ff;
2710 break;
2711
2712 case BFD_RELOC_SPARC_L44:
2713 if (!fixP->fx_addsy)
2714 insn |= val & 0xfff;
2715 break;
2716
2717 case BFD_RELOC_SPARC_HIX22:
2718 if (!fixP->fx_addsy)
2719 {
2720 val ^= ~ (offsetT) 0;
54b9ebdd
DE		 2721 insn |= (val >> 10) & 0x3fffff;
2722 }
2723 break;
2724
2725 case BFD_RELOC_SPARC_LOX10:
2726 if (!fixP->fx_addsy)
2727 insn |= 0x1c00 | (val & 0x3ff);
2728 break;
2729
2b063e6d
ILT		 2730 case BFD_RELOC_NONE:
2731 default:
54b9ebdd 2732 as_bad_where (fixP->fx_file, fixP->fx_line,
48401fcf 2733 _("bad or unhandled relocation type: 0x%02x"),
54b9ebdd 2734 fixP->fx_r_type);
2b063e6d 2735 break;
355afbcd 2736 }
355afbcd 2737
2b063e6d
ILT		 2738 if (INSN_BIG_ENDIAN)
2739 bfd_putb32 (insn, (unsigned char *) buf);
355afbcd 2740 else
2b063e6d 2741 bfd_putl32 (insn, (unsigned char *) buf);
355afbcd 2742 }
428d312b 2743
7ab2e983
ILT		 2744 /* Are we finished with this relocation now? */
2745 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
2746 fixP->fx_done = 1;
2747
428d312b 2748 return 1;
428d312b 2749}
fecd2382 2750
428d312b
KR		 2751/* Translate internal representation of relocation info to BFD target
2752 format. */
2753arelent *
2754tc_gen_reloc (section, fixp)
2755 asection *section;
2756 fixS *fixp;
2757{
2758 arelent *reloc;
2759 bfd_reloc_code_real_type code;
2760
590c50d8 2761 reloc = (arelent *) xmalloc (sizeof (arelent));
428d312b
KR		 2762
2763 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
2764 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
428d312b 2765
428d312b
KR		 2766 switch (fixp->fx_r_type)
2767 {
58d4951d 2768 case BFD_RELOC_16:
428d312b
KR		 2769 case BFD_RELOC_32:
2770 case BFD_RELOC_HI22:
2771 case BFD_RELOC_LO10:
2772 case BFD_RELOC_32_PCREL_S2:
7ab2e983 2773 case BFD_RELOC_SPARC13:
428d312b 2774 case BFD_RELOC_SPARC_BASE13:
a7aa7a2b
ILT		 2775 case BFD_RELOC_SPARC_WDISP16:
2776 case BFD_RELOC_SPARC_WDISP19:
ed9638af 2777 case BFD_RELOC_SPARC_WDISP22:
693b21e7 2778 case BFD_RELOC_64:
8dd07a84
ILT		 2779 case BFD_RELOC_SPARC_5:
2780 case BFD_RELOC_SPARC_6:
54b9ebdd 2781 case BFD_RELOC_SPARC_7:
125f0b0d
KR		 2782 case BFD_RELOC_SPARC_10:
2783 case BFD_RELOC_SPARC_11:
2784 case BFD_RELOC_SPARC_HH22:
2785 case BFD_RELOC_SPARC_HM10:
2786 case BFD_RELOC_SPARC_LM22:
2787 case BFD_RELOC_SPARC_PC_HH22:
2788 case BFD_RELOC_SPARC_PC_HM10:
2789 case BFD_RELOC_SPARC_PC_LM22:
54b9ebdd
DE		 2790 case BFD_RELOC_SPARC_H44:
2791 case BFD_RELOC_SPARC_M44:
2792 case BFD_RELOC_SPARC_L44:
2793 case BFD_RELOC_SPARC_HIX22:
2794 case BFD_RELOC_SPARC_LOX10:
fc23c14e 2795 case BFD_RELOC_SPARC_32LE:
428d312b
KR		 2796 code = fixp->fx_r_type;
2797 break;
2798 default:
2799 abort ();
48401fcf 2800 return NULL;
428d312b 2801 }
4c67b523
ILT		 2802
2803#if defined (OBJ_ELF) || defined (OBJ_AOUT)
2804 /* If we are generating PIC code, we need to generate a different
2805 set of relocs. */
2806
2807#ifdef OBJ_ELF
2808#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
2809#else
2810#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
2811#endif
2812
2813 if (sparc_pic_code)
2814 {
2815 switch (code)
2816 {
2817 case BFD_RELOC_32_PCREL_S2:
2818 if (! S_IS_DEFINED (fixp->fx_addsy)
9f6da653 2819 || S_IS_COMMON (fixp->fx_addsy)
21965655
ILT		 2820 || S_IS_EXTERNAL (fixp->fx_addsy)
2821 || S_IS_WEAK (fixp->fx_addsy))
4c67b523
ILT		 2822 code = BFD_RELOC_SPARC_WPLT30;
2823 break;
2824 case BFD_RELOC_HI22:
2825 if (fixp->fx_addsy != NULL
2826 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2827 code = BFD_RELOC_SPARC_PC22;
2828 else
2829 code = BFD_RELOC_SPARC_GOT22;
2830 break;
2831 case BFD_RELOC_LO10:
2832 if (fixp->fx_addsy != NULL
2833 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2834 code = BFD_RELOC_SPARC_PC10;
2835 else
2836 code = BFD_RELOC_SPARC_GOT10;
2837 break;
2838 case BFD_RELOC_SPARC13:
2839 code = BFD_RELOC_SPARC_GOT13;
2840 break;
2841 default:
2842 break;
2843 }
2844 }
2845#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
2846
428d312b 2847 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
a7129c48
KR		 2848 if (reloc->howto == 0)
2849 {
2850 as_bad_where (fixp->fx_file, fixp->fx_line,
48401fcf 2851 _("internal error: can't export reloc type %d (`%s')"),
ade614d5 2852 fixp->fx_r_type, bfd_get_reloc_code_name (code));
a7129c48
KR		 2853 return 0;
2854 }
c999fd9f
KR		 2855
2856 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
a7aa7a2b
ILT		 2857#ifdef OBJ_AOUT
2858
4c67b523
ILT		 2859 if (reloc->howto->pc_relative == 0
2860 || code == BFD_RELOC_SPARC_PC10
2861 || code == BFD_RELOC_SPARC_PC22)
a7aa7a2b 2862 reloc->addend = fixp->fx_addnumber;
a5002978
CM		 2863 else if (sparc_pic_code
2864 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
2865 && fixp->fx_addsy != NULL
2866 && (S_IS_EXTERNAL (fixp->fx_addsy)
2867 || S_IS_WEAK (fixp->fx_addsy))
2868 && S_IS_DEFINED (fixp->fx_addsy)
2869 && ! S_IS_COMMON (fixp->fx_addsy))
2870 reloc->addend = fixp->fx_addnumber;
a7aa7a2b
ILT		 2871 else
2872 reloc->addend = fixp->fx_offset - reloc->address;
2873
2874#else /* elf or coff */
2875
4c67b523
ILT		 2876 if (reloc->howto->pc_relative == 0
2877 || code == BFD_RELOC_SPARC_PC10
2878 || code == BFD_RELOC_SPARC_PC22)
c999fd9f 2879 reloc->addend = fixp->fx_addnumber;
7ab2e983
ILT		 2880 else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2881 reloc->addend = (section->vma
2882 + fixp->fx_addnumber
2883 + md_pcrel_from (fixp));
c999fd9f 2884 else
a7aa7a2b 2885 reloc->addend = fixp->fx_offset;
a7aa7a2b 2886#endif
428d312b
KR		 2887
2888 return reloc;
2889}
af6f39b4
DE		 2890\f
2891/* We have no need to default values of symbols. */
428d312b 2892
af6f39b4
DE		 2893/* ARGSUSED */
2894symbolS *
2895md_undefined_symbol (name)
2896 char *name;
2897{
2898 return 0;
2899} /* md_undefined_symbol() */
fecd2382 2900
af6f39b4
DE		 2901/* Round up a section size to the appropriate boundary. */
2902valueT
2903md_section_align (segment, size)
2904 segT segment;
2905 valueT size;
fecd2382 2906{
af6f39b4
DE		 2907#ifndef OBJ_ELF
2908 /* This is not right for ELF; a.out wants it, and COFF will force
2909 the alignment anyways. */
2910 valueT align = ((valueT) 1
2911 << (valueT) bfd_get_section_alignment (stdoutput, segment));
2912 valueT newsize;
2913 /* turn alignment value into a mask */
2914 align--;
2915 newsize = (size + align) & ~align;
2916 return newsize;
2917#else
2918 return size;
2919#endif
2920}
2921
2922/* Exactly what point is a PC-relative offset relative TO?
2923 On the sparc, they're relative to the address of the offset, plus
2924 its size. This gets us to the following instruction.
2925 (??? Is this right? FIXME-SOON) */
2926long
2927md_pcrel_from (fixP)
2928 fixS *fixP;
2929{
2930 long ret;
355afbcd 2931
af6f39b4
DE		 2932 ret = fixP->fx_where + fixP->fx_frag->fr_address;
2933 if (! sparc_pic_code
2934 || fixP->fx_addsy == NULL
2935 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2936 ret += fixP->fx_size;
2937 return ret;
c999fd9f 2938}
f3d817d8 2939\f
839df5c3 2940/*
af6f39b4 2941 * sort of like s_lcomm
839df5c3 2942 */
162e3485 2943
af6f39b4
DE		 2944#ifndef OBJ_ELF
2945static int max_alignment = 15;
2b063e6d 2946#endif
355afbcd 2947
af6f39b4
DE		 2948static void
2949s_reserve (ignore)
2950 int ignore;
f3d817d8 2951{
af6f39b4
DE		 2952 char *name;
2953 char *p;
2954 char c;
2955 int align;
2956 int size;
2957 int temp;
2958 symbolS *symbolP;
2959
2960 name = input_line_pointer;
2961 c = get_symbol_end ();
2962 p = input_line_pointer;
2963 *p = c;
2964 SKIP_WHITESPACE ();
2965
2966 if (*input_line_pointer != ',')
355afbcd 2967 {
48401fcf 2968 as_bad (_("Expected comma after name"));
af6f39b4
DE		 2969 ignore_rest_of_line ();
2970 return;
2971 }
355afbcd 2972
af6f39b4
DE		 2973 ++input_line_pointer;
2974
2975 if ((size = get_absolute_expression ()) < 0)
2976 {
48401fcf 2977 as_bad (_("BSS length (%d.) <0! Ignored."), size);
af6f39b4
DE		 2978 ignore_rest_of_line ();
2979 return;
2980 } /* bad length */
2981
2982 *p = 0;
2983 symbolP = symbol_find_or_make (name);
2984 *p = c;
2985
2986 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
2987 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
2988 {
48401fcf 2989 as_bad (_("bad .reserve segment -- expected BSS segment"));
af6f39b4
DE		 2990 return;
2991 }
2992
2993 if (input_line_pointer[2] == '.')
2994 input_line_pointer += 7;
2995 else
2996 input_line_pointer += 6;
2997 SKIP_WHITESPACE ();
2998
2999 if (*input_line_pointer == ',')
3000 {
3001 ++input_line_pointer;
3002
3003 SKIP_WHITESPACE ();
3004 if (*input_line_pointer == '\n')
e70ad5d5 3005 {
48401fcf 3006 as_bad (_("Missing alignment"));
af6f39b4 3007 return;
e70ad5d5
DE		 3008 }
3009
af6f39b4
DE		 3010 align = get_absolute_expression ();
3011#ifndef OBJ_ELF
3012 if (align > max_alignment)
3013 {
3014 align = max_alignment;
48401fcf 3015 as_warn (_("Alignment too large: %d. assumed."), align);
af6f39b4
DE		 3016 }
3017#endif
3018 if (align < 0)
3019 {
3020 align = 0;
48401fcf 3021 as_warn (_("Alignment negative. 0 assumed."));
af6f39b4 3022 }
e70ad5d5 3023
af6f39b4 3024 record_alignment (bss_section, align);
f3d817d8 3025
af6f39b4
DE		 3026 /* convert to a power of 2 alignment */
3027 for (temp = 0; (align & 1) == 0; align >>= 1, ++temp);;
f3d817d8 3028
af6f39b4
DE		 3029 if (align != 1)
3030 {
48401fcf 3031 as_bad (_("Alignment not a power of 2"));
af6f39b4
DE		 3032 ignore_rest_of_line ();
3033 return;
3034 } /* not a power of two */
355afbcd 3035
af6f39b4
DE		 3036 align = temp;
3037 } /* if has optional alignment */
3038 else
3039 align = 0;
2b063e6d 3040
af6f39b4
DE		 3041 if (!S_IS_DEFINED (symbolP)
3042#ifdef OBJ_AOUT
3043 && S_GET_OTHER (symbolP) == 0
3044 && S_GET_DESC (symbolP) == 0
3045#endif
3046 )
3047 {
3048 if (! need_pass_2)
3049 {
3050 char *pfrag;
3051 segT current_seg = now_seg;
3052 subsegT current_subseg = now_subseg;
3053
3054 subseg_set (bss_section, 1); /* switch to bss */
3055
3056 if (align)
3057 frag_align (align, 0, 0); /* do alignment */
3058
3059 /* detach from old frag */
3060 if (S_GET_SEGMENT(symbolP) == bss_section)
3061 symbolP->sy_frag->fr_symbol = NULL;
3062
3063 symbolP->sy_frag = frag_now;
3064 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP,
3065 (offsetT) size, (char *)0);
3066 *pfrag = 0;
3067
3068 S_SET_SEGMENT (symbolP, bss_section);
3069
3070 subseg_set (current_seg, current_subseg);
3071 }
3072 }
3073 else
3074 {
3075 as_warn("Ignoring attempt to re-define symbol %s",
3076 S_GET_NAME (symbolP));
3077 } /* if not redefining */
3078
3079 demand_empty_rest_of_line ();
3080}
3081
3082static void
3083s_common (ignore)
3084 int ignore;
3085{
3086 char *name;
3087 char c;
3088 char *p;
3089 int temp, size;
3090 symbolS *symbolP;
3091
3092 name = input_line_pointer;
3093 c = get_symbol_end ();
3094 /* just after name is now '\0' */
3095 p = input_line_pointer;
3096 *p = c;
3097 SKIP_WHITESPACE ();
3098 if (*input_line_pointer != ',')
3099 {
48401fcf 3100 as_bad (_("Expected comma after symbol-name"));
af6f39b4
DE		 3101 ignore_rest_of_line ();
3102 return;
3103 }
3104 input_line_pointer++; /* skip ',' */
3105 if ((temp = get_absolute_expression ()) < 0)
3106 {
48401fcf 3107 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
af6f39b4
DE		 3108 ignore_rest_of_line ();
3109 return;
3110 }
3111 size = temp;
3112 *p = 0;
3113 symbolP = symbol_find_or_make (name);
3114 *p = c;
3115 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3116 {
48401fcf 3117 as_bad (_("Ignoring attempt to re-define symbol"));
af6f39b4
DE		 3118 ignore_rest_of_line ();
3119 return;
3120 }
3121 if (S_GET_VALUE (symbolP) != 0)
3122 {
48401fcf 3123 if (S_GET_VALUE (symbolP) != (valueT) size)
af6f39b4 3124 {
48401fcf 3125 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
af6f39b4
DE		 3126 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3127 }
3128 }
3129 else
3130 {
3131#ifndef OBJ_ELF
3132 S_SET_VALUE (symbolP, (valueT) size);
3133 S_SET_EXTERNAL (symbolP);
3134#endif
3135 }
3136 know (symbolP->sy_frag == &zero_address_frag);
3137 if (*input_line_pointer != ',')
3138 {
48401fcf 3139 as_bad (_("Expected comma after common length"));
af6f39b4
DE		 3140 ignore_rest_of_line ();
3141 return;
3142 }
3143 input_line_pointer++;
3144 SKIP_WHITESPACE ();
3145 if (*input_line_pointer != '"')
3146 {
3147 temp = get_absolute_expression ();
3148#ifndef OBJ_ELF
3149 if (temp > max_alignment)
3150 {
3151 temp = max_alignment;
48401fcf 3152 as_warn (_("Common alignment too large: %d. assumed"), temp);
af6f39b4
DE		 3153 }
3154#endif
3155 if (temp < 0)
3156 {
3157 temp = 0;
48401fcf 3158 as_warn (_("Common alignment negative; 0 assumed"));
af6f39b4
DE		 3159 }
3160#ifdef OBJ_ELF
3161 if (symbolP->local)
3162 {
3163 segT old_sec;
3164 int old_subsec;
3165 char *p;
3166 int align;
3167
3168 old_sec = now_seg;
3169 old_subsec = now_subseg;
3170 align = temp;
3171 record_alignment (bss_section, align);
3172 subseg_set (bss_section, 0);
3173 if (align)
3174 frag_align (align, 0, 0);
3175 if (S_GET_SEGMENT (symbolP) == bss_section)
3176 symbolP->sy_frag->fr_symbol = 0;
3177 symbolP->sy_frag = frag_now;
3178 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3179 (offsetT) size, (char *) 0);
3180 *p = 0;
3181 S_SET_SEGMENT (symbolP, bss_section);
3182 S_CLEAR_EXTERNAL (symbolP);
3183 subseg_set (old_sec, old_subsec);
3184 }
3185 else
2b063e6d 3186#endif
af6f39b4
DE		 3187 {
3188 allocate_common:
3189 S_SET_VALUE (symbolP, (valueT) size);
3190#ifdef OBJ_ELF
3191 S_SET_ALIGN (symbolP, temp);
3192#endif
3193 S_SET_EXTERNAL (symbolP);
3194 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3195 }
3196 }
3197 else
3198 {
3199 input_line_pointer++;
3200 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3201 if (*input_line_pointer == '.')
3202 input_line_pointer++;
3203 /* @@ Some say data, some say bss. */
3204 if (strncmp (input_line_pointer, "bss\"", 4)
3205 && strncmp (input_line_pointer, "data\"", 5))
3206 {
3207 while (*--input_line_pointer != '"')
3208 ;
3209 input_line_pointer--;
3210 goto bad_common_segment;
3211 }
3212 while (*input_line_pointer++ != '"')
3213 ;
3214 goto allocate_common;
3215 }
2b063e6d 3216
af6f39b4
DE		 3217#ifdef BFD_ASSEMBLER
3218 symbolP->bsym->flags |= BSF_OBJECT;
4c67b523
ILT		 3219#endif
3220
af6f39b4
DE		 3221 demand_empty_rest_of_line ();
3222 return;
f3d817d8 3223
af6f39b4
DE		 3224 {
3225 bad_common_segment:
3226 p = input_line_pointer;
3227 while (*p && *p != '\n')
3228 p++;
3229 c = *p;
3230 *p = '\0';
48401fcf 3231 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
af6f39b4
DE		 3232 *p = c;
3233 input_line_pointer = p;
3234 ignore_rest_of_line ();
3235 return;
3236 }
3237}
f3d817d8 3238
af6f39b4
DE		 3239/* Handle the .empty pseudo-op. This supresses the warnings about
3240 invalid delay slot usage. */
f3d817d8 3241
af6f39b4
DE		 3242static void
3243s_empty (ignore)
3244 int ignore;
3245{
3246 /* The easy way to implement is to just forget about the last
3247 instruction. */
3248 last_insn = NULL;
3249}
a7aa7a2b 3250
af6f39b4
DE		 3251static void
3252s_seg (ignore)
3253 int ignore;
3254{
f3d817d8 3255
af6f39b4
DE		 3256 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3257 {
3258 input_line_pointer += 6;
3259 s_text (0);
3260 return;
355afbcd 3261 }
af6f39b4
DE		 3262 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3263 {
3264 input_line_pointer += 6;
3265 s_data (0);
3266 return;
3267 }
3268 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3269 {
3270 input_line_pointer += 7;
3271 s_data1 ();
3272 return;
3273 }
3274 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3275 {
3276 input_line_pointer += 5;
3277 /* We only support 2 segments -- text and data -- for now, so
3278 things in the "bss segment" will have to go into data for now.
3279 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3280 subseg_set (data_section, 255); /* FIXME-SOMEDAY */
3281 return;
3282 }
48401fcf 3283 as_bad (_("Unknown segment type"));
af6f39b4 3284 demand_empty_rest_of_line ();
f3d817d8
DM		 3285}
3286
af6f39b4
DE		 3287static void
3288s_data1 ()
f3d817d8 3289{
af6f39b4
DE		 3290 subseg_set (data_section, 1);
3291 demand_empty_rest_of_line ();
3292}
e70ad5d5 3293
af6f39b4
DE		 3294static void
3295s_proc (ignore)
3296 int ignore;
3297{
3298 while (!is_end_of_line[(unsigned char) *input_line_pointer])
5e0a90a8 3299 {
af6f39b4 3300 ++input_line_pointer;
5e0a90a8 3301 }
af6f39b4 3302 ++input_line_pointer;
f3d817d8 3303}
fecd2382 3304
af6f39b4
DE		 3305/* This static variable is set by s_uacons to tell sparc_cons_align
3306 that the expession does not need to be aligned. */
fecd2382 3307
af6f39b4
DE		 3308static int sparc_no_align_cons = 0;
3309
3310/* This handles the unaligned space allocation pseudo-ops, such as
3311 .uaword. .uaword is just like .word, but the value does not need
3312 to be aligned. */
3313
3314static void
3315s_uacons (bytes)
3316 int bytes;
fecd2382 3317{
af6f39b4
DE		 3318 /* Tell sparc_cons_align not to align this value. */
3319 sparc_no_align_cons = 1;
3320 cons (bytes);
428d312b 3321}
fecd2382 3322
af6f39b4
DE		 3323/* If the --enforce-aligned-data option is used, we require .word,
3324 et. al., to be aligned correctly. We do it by setting up an
3325 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3326 no unexpected alignment was introduced.
3327
3328 The SunOS and Solaris native assemblers enforce aligned data by
3329 default. We don't want to do that, because gcc can deliberately
3330 generate misaligned data if the packed attribute is used. Instead,
3331 we permit misaligned data by default, and permit the user to set an
3332 option to check for it. */
3333
3334void
3335sparc_cons_align (nbytes)
3336 int nbytes;
fecd2382 3337{
af6f39b4
DE		 3338 int nalign;
3339 char *p;
4c67b523 3340
af6f39b4
DE		 3341 /* Only do this if we are enforcing aligned data. */
3342 if (! enforce_aligned_data)
3343 return;
3344
3345 if (sparc_no_align_cons)
3346 {
3347 /* This is an unaligned pseudo-op. */
3348 sparc_no_align_cons = 0;
3349 return;
3350 }
3351
3352 nalign = 0;
3353 while ((nbytes & 1) == 0)
3354 {
3355 ++nalign;
3356 nbytes >>= 1;
3357 }
3358
3359 if (nalign == 0)
3360 return;
3361
3362 if (now_seg == absolute_section)
3363 {
3364 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
48401fcf 3365 as_bad (_("misaligned data"));
af6f39b4
DE		 3366 return;
3367 }
3368
3369 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
3370 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
3371
3372 record_alignment (now_seg, nalign);
428d312b 3373}
fecd2382 3374
af6f39b4
DE		 3375/* This is where we do the unexpected alignment check.
3376 This is called from HANDLE_ALIGN in tc-sparc.h. */
3377
3378void
3379sparc_handle_align (fragp)
3380 fragS *fragp;
3381{
7532235c 3382 if (fragp->fr_type == rs_align_code && !fragp->fr_subtype
af6f39b4 3383 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
48401fcf 3384 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
7532235c
RH		 3385 if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
3386 {
3387 int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
3388
04a92367
ILT		 3389 if (count >= 4
3390 && !(count & 3)
3391 && count <= 1024
3392 && !((long)(fragp->fr_literal + fragp->fr_fix) & 3))
7532235c
RH		 3393 {
3394 unsigned *p = (unsigned *)(fragp->fr_literal + fragp->fr_fix);
3395 int i;
3396
a5002978
CM		 3397 for (i = 0; i < count; i += 4, p++)
3398 if (INSN_BIG_ENDIAN)
3399 number_to_chars_bigendian ((char *)p, 0x01000000, 4); /* emit nops */
3400 else
3401 number_to_chars_littleendian ((char *)p, 0x10000000, 4);
3402
7532235c 3403 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
a5002978 3404 {
04a92367
ILT		 3405 char *waddr = &fragp->fr_literal[fragp->fr_fix];
3406 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
3407 if (INSN_BIG_ENDIAN)
3408 number_to_chars_bigendian (waddr, wval, 4);
3409 else
3410 number_to_chars_littleendian (waddr, wval, 4);
a5002978 3411 }
7532235c
RH		 3412 fragp->fr_var = count;
3413 }
3414 }
af6f39b4 3415}
1bb6aaad
RH		 3416
3417#ifdef OBJ_ELF
3418/* Some special processing for a Sparc ELF file. */
3419
3420void
3421sparc_elf_final_processing ()
3422{
3423 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
3424 sort of BFD interface for this. */
3425 if (sparc_arch_size == 64)
04a92367
ILT		 3426 {
3427 switch (sparc_memory_model)
3428 {
3429 case MM_RMO:
3430 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
3431 break;
3432 case MM_PSO:
3433 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
3434 break;
3435 default:
3436 break;
3437 }
3438 }
1bb6aaad
RH		 3439 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
3440 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
3441 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
3442 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
3443}
3444#endif
fc23c14e
SC		 3445
3446/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3447 reloc for a cons. We could use the definition there, except that
3448 we want to handle little endian relocs specially. */
3449
3450void
3451cons_fix_new_sparc (frag, where, nbytes, exp)
3452 fragS *frag;
3453 int where;
3454 unsigned int nbytes;
3455 expressionS *exp;
3456{
3457 bfd_reloc_code_real_type r;
3458
3459 r = (nbytes == 1 ? BFD_RELOC_8 :
3460 (nbytes == 2 ? BFD_RELOC_16 :
3461 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
3462
3463#ifdef OBJ_ELF
3464 if (target_little_endian_data && nbytes == 4)
3465 r = BFD_RELOC_SPARC_32LE;
3466#endif
3467 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
3468}
GDB Binutils - Deliverables
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