Commit | Line | Data |
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252b5132 | 1 | /* tc-sparc.c -- Assemble for the SPARC |
f7e42eb4 | 2 | Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
87975d2a | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
e0c6ed95 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | This file is part of GAS, the GNU Assembler. |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public | |
18 | License along with GAS; see the file COPYING. If not, write | |
4b4da160 NC |
19 | to the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
252b5132 RH |
24 | #include "subsegs.h" |
25 | ||
26 | #include "opcode/sparc.h" | |
364b6d8b | 27 | #include "dw2gencfi.h" |
252b5132 RH |
28 | |
29 | #ifdef OBJ_ELF | |
30 | #include "elf/sparc.h" | |
732d96b6 | 31 | #include "dwarf2dbg.h" |
252b5132 RH |
32 | #endif |
33 | ||
6c1b24e4 AO |
34 | /* Some ancient Sun C compilers would not take such hex constants as |
35 | unsigned, and would end up sign-extending them to form an offsetT, | |
36 | so use these constants instead. */ | |
37 | #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) | |
38 | #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) | |
39 | ||
5a49b8ac AM |
40 | static int sparc_ip (char *, const struct sparc_opcode **); |
41 | static int parse_keyword_arg (int (*) (const char *), char **, int *); | |
42 | static int parse_const_expr_arg (char **, int *); | |
43 | static int get_expression (char *); | |
252b5132 RH |
44 | |
45 | /* Default architecture. */ | |
46 | /* ??? The default value should be V8, but sparclite support was added | |
47 | by making it the default. GCC now passes -Asparclite, so maybe sometime in | |
48 | the future we can set this to V8. */ | |
49 | #ifndef DEFAULT_ARCH | |
50 | #define DEFAULT_ARCH "sparclite" | |
51 | #endif | |
52 | static char *default_arch = DEFAULT_ARCH; | |
53 | ||
54 | /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' | |
55 | have been set. */ | |
56 | static int default_init_p; | |
57 | ||
58 | /* Current architecture. We don't bump up unless necessary. */ | |
59 | static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; | |
60 | ||
61 | /* The maximum architecture level we can bump up to. | |
62 | In a 32 bit environment, don't allow bumping up to v9 by default. | |
63 | The native assembler works this way. The user is required to pass | |
64 | an explicit argument before we'll create v9 object files. However, if | |
65 | we don't see any v9 insns, a v8plus object file is not created. */ | |
66 | static enum sparc_opcode_arch_val max_architecture; | |
67 | ||
68 | /* Either 32 or 64, selects file format. */ | |
69 | static int sparc_arch_size; | |
70 | /* Initial (default) value, recorded separately in case a user option | |
71 | changes the value before md_show_usage is called. */ | |
72 | static int default_arch_size; | |
73 | ||
74 | #ifdef OBJ_ELF | |
75 | /* The currently selected v9 memory model. Currently only used for | |
76 | ELF. */ | |
77 | static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; | |
78 | #endif | |
79 | ||
80 | static int architecture_requested; | |
81 | static int warn_on_bump; | |
82 | ||
83 | /* If warn_on_bump and the needed architecture is higher than this | |
84 | architecture, issue a warning. */ | |
85 | static enum sparc_opcode_arch_val warn_after_architecture; | |
86 | ||
6d8809aa RH |
87 | /* Non-zero if as should generate error if an undeclared g[23] register |
88 | has been used in -64. */ | |
89 | static int no_undeclared_regs; | |
90 | ||
6faf3d66 JJ |
91 | /* Non-zero if we should try to relax jumps and calls. */ |
92 | static int sparc_relax; | |
93 | ||
252b5132 RH |
94 | /* Non-zero if we are generating PIC code. */ |
95 | int sparc_pic_code; | |
96 | ||
97 | /* Non-zero if we should give an error when misaligned data is seen. */ | |
98 | static int enforce_aligned_data; | |
99 | ||
100 | extern int target_big_endian; | |
101 | ||
102 | static int target_little_endian_data; | |
103 | ||
6d8809aa RH |
104 | /* Symbols for global registers on v9. */ |
105 | static symbolS *globals[8]; | |
106 | ||
364b6d8b JJ |
107 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ |
108 | int sparc_cie_data_alignment; | |
109 | ||
252b5132 RH |
110 | /* V9 and 86x have big and little endian data, but instructions are always big |
111 | endian. The sparclet has bi-endian support but both data and insns have | |
112 | the same endianness. Global `target_big_endian' is used for data. | |
113 | The following macro is used for instructions. */ | |
114 | #ifndef INSN_BIG_ENDIAN | |
115 | #define INSN_BIG_ENDIAN (target_big_endian \ | |
116 | || default_arch_type == sparc86x \ | |
117 | || SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
118 | #endif | |
119 | ||
e0c6ed95 | 120 | /* Handle of the OPCODE hash table. */ |
252b5132 RH |
121 | static struct hash_control *op_hash; |
122 | ||
5a49b8ac AM |
123 | static void s_data1 (void); |
124 | static void s_seg (int); | |
125 | static void s_proc (int); | |
126 | static void s_reserve (int); | |
127 | static void s_common (int); | |
128 | static void s_empty (int); | |
129 | static void s_uacons (int); | |
130 | static void s_ncons (int); | |
a7982600 | 131 | #ifdef OBJ_ELF |
5a49b8ac | 132 | static void s_register (int); |
a7982600 | 133 | #endif |
252b5132 RH |
134 | |
135 | const pseudo_typeS md_pseudo_table[] = | |
136 | { | |
e0c6ed95 | 137 | {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ |
252b5132 RH |
138 | {"common", s_common, 0}, |
139 | {"empty", s_empty, 0}, | |
140 | {"global", s_globl, 0}, | |
141 | {"half", cons, 2}, | |
cf9a1301 | 142 | {"nword", s_ncons, 0}, |
252b5132 RH |
143 | {"optim", s_ignore, 0}, |
144 | {"proc", s_proc, 0}, | |
145 | {"reserve", s_reserve, 0}, | |
146 | {"seg", s_seg, 0}, | |
147 | {"skip", s_space, 0}, | |
148 | {"word", cons, 4}, | |
149 | {"xword", cons, 8}, | |
150 | {"uahalf", s_uacons, 2}, | |
151 | {"uaword", s_uacons, 4}, | |
152 | {"uaxword", s_uacons, 8}, | |
153 | #ifdef OBJ_ELF | |
e0c6ed95 | 154 | /* These are specific to sparc/svr4. */ |
252b5132 RH |
155 | {"2byte", s_uacons, 2}, |
156 | {"4byte", s_uacons, 4}, | |
157 | {"8byte", s_uacons, 8}, | |
6d8809aa | 158 | {"register", s_register, 0}, |
252b5132 RH |
159 | #endif |
160 | {NULL, 0, 0}, | |
161 | }; | |
162 | ||
252b5132 | 163 | /* This array holds the chars that always start a comment. If the |
e0c6ed95 AM |
164 | pre-processor is disabled, these aren't very useful. */ |
165 | const char comment_chars[] = "!"; /* JF removed '|' from | |
166 | comment_chars. */ | |
252b5132 RH |
167 | |
168 | /* This array holds the chars that only start a comment at the beginning of | |
169 | a line. If the line seems to have the form '# 123 filename' | |
e0c6ed95 | 170 | .line and .file directives will appear in the pre-processed output. */ |
252b5132 RH |
171 | /* Note that input_file.c hand checks for '#' at the beginning of the |
172 | first line of the input file. This is because the compiler outputs | |
e0c6ed95 | 173 | #NO_APP at the beginning of its output. */ |
252b5132 | 174 | /* Also note that comments started like this one will always |
e0c6ed95 | 175 | work if '/' isn't otherwise defined. */ |
252b5132 RH |
176 | const char line_comment_chars[] = "#"; |
177 | ||
63a0b638 | 178 | const char line_separator_chars[] = ";"; |
252b5132 | 179 | |
e0c6ed95 AM |
180 | /* Chars that can be used to separate mant from exp in floating point |
181 | nums. */ | |
252b5132 RH |
182 | const char EXP_CHARS[] = "eE"; |
183 | ||
e0c6ed95 AM |
184 | /* Chars that mean this number is a floating point constant. |
185 | As in 0f12.456 | |
186 | or 0d1.2345e12 */ | |
252b5132 RH |
187 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
188 | ||
189 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
190 | changed in read.c. Ideally it shouldn't have to know about it at all, | |
191 | but nothing is ideal around here. */ | |
192 | ||
74b56d1f | 193 | #define isoctal(c) ((unsigned) ((c) - '0') < 8) |
252b5132 RH |
194 | |
195 | struct sparc_it | |
196 | { | |
197 | char *error; | |
198 | unsigned long opcode; | |
199 | struct nlist *nlistp; | |
200 | expressionS exp; | |
cf9a1301 | 201 | expressionS exp2; |
252b5132 RH |
202 | int pcrel; |
203 | bfd_reloc_code_real_type reloc; | |
204 | }; | |
205 | ||
206 | struct sparc_it the_insn, set_insn; | |
207 | ||
5a49b8ac | 208 | static void output_insn (const struct sparc_opcode *, struct sparc_it *); |
252b5132 RH |
209 | \f |
210 | /* Table of arguments to -A. | |
211 | The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect | |
212 | for this use. That table is for opcodes only. This table is for opcodes | |
213 | and file formats. */ | |
214 | ||
215 | enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, | |
19f7b010 | 216 | v8plusa, v9, v9a, v9b, v9_64}; |
252b5132 RH |
217 | |
218 | static struct sparc_arch { | |
219 | char *name; | |
220 | char *opcode_arch; | |
221 | enum sparc_arch_types arch_type; | |
222 | /* Default word size, as specified during configuration. | |
223 | A value of zero means can't be used to specify default architecture. */ | |
224 | int default_arch_size; | |
225 | /* Allowable arg to -A? */ | |
226 | int user_option_p; | |
227 | } sparc_arch_table[] = { | |
228 | { "v6", "v6", v6, 0, 1 }, | |
229 | { "v7", "v7", v7, 0, 1 }, | |
230 | { "v8", "v8", v8, 32, 1 }, | |
231 | { "sparclet", "sparclet", sparclet, 32, 1 }, | |
232 | { "sparclite", "sparclite", sparclite, 32, 1 }, | |
233 | { "sparc86x", "sparclite", sparc86x, 32, 1 }, | |
234 | { "v8plus", "v9", v9, 0, 1 }, | |
235 | { "v8plusa", "v9a", v9, 0, 1 }, | |
19f7b010 | 236 | { "v8plusb", "v9b", v9, 0, 1 }, |
252b5132 RH |
237 | { "v9", "v9", v9, 0, 1 }, |
238 | { "v9a", "v9a", v9, 0, 1 }, | |
19f7b010 | 239 | { "v9b", "v9b", v9, 0, 1 }, |
252b5132 RH |
240 | /* This exists to allow configure.in/Makefile.in to pass one |
241 | value to specify both the default machine and default word size. */ | |
242 | { "v9-64", "v9", v9, 64, 0 }, | |
243 | { NULL, NULL, v8, 0, 0 } | |
244 | }; | |
245 | ||
246 | /* Variant of default_arch */ | |
247 | static enum sparc_arch_types default_arch_type; | |
248 | ||
249 | static struct sparc_arch * | |
5a49b8ac | 250 | lookup_arch (char *name) |
252b5132 RH |
251 | { |
252 | struct sparc_arch *sa; | |
253 | ||
254 | for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) | |
255 | if (strcmp (sa->name, name) == 0) | |
256 | break; | |
257 | if (sa->name == NULL) | |
258 | return NULL; | |
259 | return sa; | |
260 | } | |
261 | ||
262 | /* Initialize the default opcode arch and word size from the default | |
263 | architecture name. */ | |
264 | ||
265 | static void | |
5a49b8ac | 266 | init_default_arch (void) |
252b5132 RH |
267 | { |
268 | struct sparc_arch *sa = lookup_arch (default_arch); | |
269 | ||
270 | if (sa == NULL | |
271 | || sa->default_arch_size == 0) | |
272 | as_fatal (_("Invalid default architecture, broken assembler.")); | |
273 | ||
274 | max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); | |
275 | if (max_architecture == SPARC_OPCODE_ARCH_BAD) | |
276 | as_fatal (_("Bad opcode table, broken assembler.")); | |
277 | default_arch_size = sparc_arch_size = sa->default_arch_size; | |
278 | default_init_p = 1; | |
279 | default_arch_type = sa->arch_type; | |
280 | } | |
281 | ||
282 | /* Called by TARGET_FORMAT. */ | |
283 | ||
284 | const char * | |
5a49b8ac | 285 | sparc_target_format (void) |
252b5132 RH |
286 | { |
287 | /* We don't get a chance to initialize anything before we're called, | |
288 | so handle that now. */ | |
289 | if (! default_init_p) | |
290 | init_default_arch (); | |
291 | ||
292 | #ifdef OBJ_AOUT | |
293 | #ifdef TE_NetBSD | |
294 | return "a.out-sparc-netbsd"; | |
295 | #else | |
296 | #ifdef TE_SPARCAOUT | |
297 | if (target_big_endian) | |
298 | return "a.out-sunos-big"; | |
299 | else if (default_arch_type == sparc86x && target_little_endian_data) | |
300 | return "a.out-sunos-big"; | |
ab3e48dc KH |
301 | else |
302 | return "a.out-sparc-little"; | |
252b5132 RH |
303 | #else |
304 | return "a.out-sunos-big"; | |
305 | #endif | |
306 | #endif | |
307 | #endif | |
308 | ||
309 | #ifdef OBJ_BOUT | |
310 | return "b.out.big"; | |
311 | #endif | |
312 | ||
313 | #ifdef OBJ_COFF | |
314 | #ifdef TE_LYNX | |
315 | return "coff-sparc-lynx"; | |
316 | #else | |
317 | return "coff-sparc"; | |
318 | #endif | |
319 | #endif | |
320 | ||
910600e9 RS |
321 | #ifdef TE_VXWORKS |
322 | return "elf32-sparc-vxworks"; | |
323 | #endif | |
324 | ||
252b5132 | 325 | #ifdef OBJ_ELF |
71a75f6f | 326 | return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; |
252b5132 RH |
327 | #endif |
328 | ||
329 | abort (); | |
330 | } | |
331 | \f | |
e0c6ed95 | 332 | /* md_parse_option |
252b5132 RH |
333 | * Invocation line includes a switch not recognized by the base assembler. |
334 | * See if it's a processor-specific option. These are: | |
335 | * | |
336 | * -bump | |
337 | * Warn on architecture bumps. See also -A. | |
338 | * | |
339 | * -Av6, -Av7, -Av8, -Asparclite, -Asparclet | |
340 | * Standard 32 bit architectures. | |
19f7b010 | 341 | * -Av9, -Av9a, -Av9b |
252b5132 RH |
342 | * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). |
343 | * This used to only mean 64 bits, but properly specifying it | |
344 | * complicated gcc's ASM_SPECs, so now opcode selection is | |
345 | * specified orthogonally to word size (except when specifying | |
346 | * the default, but that is an internal implementation detail). | |
19f7b010 JJ |
347 | * -Av8plus, -Av8plusa, -Av8plusb |
348 | * Same as -Av9{,a,b}. | |
349 | * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb | |
350 | * Same as -Av8plus{,a,b} -32, for compatibility with Sun's | |
351 | * assembler. | |
352 | * -xarch=v9, -xarch=v9a, -xarch=v9b | |
353 | * Same as -Av9{,a,b} -64, for compatibility with Sun's | |
c2158c24 | 354 | * assembler. |
252b5132 RH |
355 | * |
356 | * Select the architecture and possibly the file format. | |
357 | * Instructions or features not supported by the selected | |
358 | * architecture cause fatal errors. | |
359 | * | |
360 | * The default is to start at v6, and bump the architecture up | |
361 | * whenever an instruction is seen at a higher level. In 32 bit | |
362 | * environments, v9 is not bumped up to, the user must pass | |
19f7b010 | 363 | * -Av8plus{,a,b}. |
252b5132 RH |
364 | * |
365 | * If -bump is specified, a warning is printing when bumping to | |
366 | * higher levels. | |
367 | * | |
368 | * If an architecture is specified, all instructions must match | |
369 | * that architecture. Any higher level instructions are flagged | |
370 | * as errors. Note that in the 32 bit environment specifying | |
371 | * -Av8plus does not automatically create a v8plus object file, a | |
372 | * v9 insn must be seen. | |
373 | * | |
374 | * If both an architecture and -bump are specified, the | |
375 | * architecture starts at the specified level, but bumps are | |
376 | * warnings. Note that we can't set `current_architecture' to | |
377 | * the requested level in this case: in the 32 bit environment, | |
378 | * we still must avoid creating v8plus object files unless v9 | |
379 | * insns are seen. | |
380 | * | |
381 | * Note: | |
382 | * Bumping between incompatible architectures is always an | |
383 | * error. For example, from sparclite to v9. | |
384 | */ | |
385 | ||
386 | #ifdef OBJ_ELF | |
5a38dc70 | 387 | const char *md_shortopts = "A:K:VQ:sq"; |
252b5132 RH |
388 | #else |
389 | #ifdef OBJ_AOUT | |
5a38dc70 | 390 | const char *md_shortopts = "A:k"; |
252b5132 | 391 | #else |
5a38dc70 | 392 | const char *md_shortopts = "A:"; |
252b5132 RH |
393 | #endif |
394 | #endif | |
395 | struct option md_longopts[] = { | |
396 | #define OPTION_BUMP (OPTION_MD_BASE) | |
397 | {"bump", no_argument, NULL, OPTION_BUMP}, | |
398 | #define OPTION_SPARC (OPTION_MD_BASE + 1) | |
399 | {"sparc", no_argument, NULL, OPTION_SPARC}, | |
400 | #define OPTION_XARCH (OPTION_MD_BASE + 2) | |
401 | {"xarch", required_argument, NULL, OPTION_XARCH}, | |
402 | #ifdef OBJ_ELF | |
403 | #define OPTION_32 (OPTION_MD_BASE + 3) | |
404 | {"32", no_argument, NULL, OPTION_32}, | |
405 | #define OPTION_64 (OPTION_MD_BASE + 4) | |
406 | {"64", no_argument, NULL, OPTION_64}, | |
407 | #define OPTION_TSO (OPTION_MD_BASE + 5) | |
408 | {"TSO", no_argument, NULL, OPTION_TSO}, | |
409 | #define OPTION_PSO (OPTION_MD_BASE + 6) | |
410 | {"PSO", no_argument, NULL, OPTION_PSO}, | |
411 | #define OPTION_RMO (OPTION_MD_BASE + 7) | |
412 | {"RMO", no_argument, NULL, OPTION_RMO}, | |
413 | #endif | |
414 | #ifdef SPARC_BIENDIAN | |
415 | #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) | |
416 | {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, | |
417 | #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) | |
418 | {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, | |
419 | #endif | |
420 | #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) | |
421 | {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, | |
422 | #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) | |
423 | {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, | |
6d8809aa RH |
424 | #ifdef OBJ_ELF |
425 | #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) | |
426 | {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, | |
a25fe906 ILT |
427 | #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) |
428 | {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, | |
6d8809aa | 429 | #endif |
6faf3d66 JJ |
430 | #define OPTION_RELAX (OPTION_MD_BASE + 14) |
431 | {"relax", no_argument, NULL, OPTION_RELAX}, | |
432 | #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) | |
433 | {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
252b5132 RH |
434 | {NULL, no_argument, NULL, 0} |
435 | }; | |
e0c6ed95 AM |
436 | |
437 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
438 | |
439 | int | |
5a49b8ac | 440 | md_parse_option (int c, char *arg) |
252b5132 RH |
441 | { |
442 | /* We don't get a chance to initialize anything before we're called, | |
443 | so handle that now. */ | |
444 | if (! default_init_p) | |
445 | init_default_arch (); | |
446 | ||
447 | switch (c) | |
448 | { | |
449 | case OPTION_BUMP: | |
450 | warn_on_bump = 1; | |
451 | warn_after_architecture = SPARC_OPCODE_ARCH_V6; | |
452 | break; | |
453 | ||
454 | case OPTION_XARCH: | |
c2158c24 JJ |
455 | #ifdef OBJ_ELF |
456 | if (strncmp (arg, "v9", 2) != 0) | |
457 | md_parse_option (OPTION_32, NULL); | |
458 | else | |
459 | md_parse_option (OPTION_64, NULL); | |
460 | #endif | |
e0c6ed95 | 461 | /* Fall through. */ |
252b5132 RH |
462 | |
463 | case 'A': | |
464 | { | |
465 | struct sparc_arch *sa; | |
466 | enum sparc_opcode_arch_val opcode_arch; | |
467 | ||
468 | sa = lookup_arch (arg); | |
469 | if (sa == NULL | |
470 | || ! sa->user_option_p) | |
471 | { | |
c2158c24 JJ |
472 | if (c == OPTION_XARCH) |
473 | as_bad (_("invalid architecture -xarch=%s"), arg); | |
474 | else | |
475 | as_bad (_("invalid architecture -A%s"), arg); | |
252b5132 RH |
476 | return 0; |
477 | } | |
478 | ||
479 | opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); | |
480 | if (opcode_arch == SPARC_OPCODE_ARCH_BAD) | |
481 | as_fatal (_("Bad opcode table, broken assembler.")); | |
482 | ||
483 | max_architecture = opcode_arch; | |
484 | architecture_requested = 1; | |
485 | } | |
486 | break; | |
487 | ||
488 | case OPTION_SPARC: | |
489 | /* Ignore -sparc, used by SunOS make default .s.o rule. */ | |
490 | break; | |
491 | ||
492 | case OPTION_ENFORCE_ALIGNED_DATA: | |
493 | enforce_aligned_data = 1; | |
494 | break; | |
495 | ||
496 | #ifdef SPARC_BIENDIAN | |
497 | case OPTION_LITTLE_ENDIAN: | |
498 | target_big_endian = 0; | |
499 | if (default_arch_type != sparclet) | |
500 | as_fatal ("This target does not support -EL"); | |
501 | break; | |
502 | case OPTION_LITTLE_ENDIAN_DATA: | |
503 | target_little_endian_data = 1; | |
504 | target_big_endian = 0; | |
505 | if (default_arch_type != sparc86x | |
506 | && default_arch_type != v9) | |
507 | as_fatal ("This target does not support --little-endian-data"); | |
508 | break; | |
509 | case OPTION_BIG_ENDIAN: | |
510 | target_big_endian = 1; | |
511 | break; | |
512 | #endif | |
513 | ||
514 | #ifdef OBJ_AOUT | |
515 | case 'k': | |
516 | sparc_pic_code = 1; | |
517 | break; | |
518 | #endif | |
519 | ||
520 | #ifdef OBJ_ELF | |
521 | case OPTION_32: | |
522 | case OPTION_64: | |
523 | { | |
524 | const char **list, **l; | |
525 | ||
526 | sparc_arch_size = c == OPTION_32 ? 32 : 64; | |
527 | list = bfd_target_list (); | |
528 | for (l = list; *l != NULL; l++) | |
529 | { | |
530 | if (sparc_arch_size == 32) | |
531 | { | |
71a75f6f | 532 | if (CONST_STRNEQ (*l, "elf32-sparc")) |
252b5132 RH |
533 | break; |
534 | } | |
535 | else | |
536 | { | |
71a75f6f | 537 | if (CONST_STRNEQ (*l, "elf64-sparc")) |
252b5132 RH |
538 | break; |
539 | } | |
540 | } | |
541 | if (*l == NULL) | |
542 | as_fatal (_("No compiled in support for %d bit object file format"), | |
543 | sparc_arch_size); | |
544 | free (list); | |
b7cac25f DM |
545 | |
546 | if (sparc_arch_size == 64 | |
547 | && max_architecture < SPARC_OPCODE_ARCH_V9) | |
548 | max_architecture = SPARC_OPCODE_ARCH_V9; | |
252b5132 RH |
549 | } |
550 | break; | |
551 | ||
552 | case OPTION_TSO: | |
553 | sparc_memory_model = MM_TSO; | |
554 | break; | |
555 | ||
556 | case OPTION_PSO: | |
557 | sparc_memory_model = MM_PSO; | |
558 | break; | |
559 | ||
560 | case OPTION_RMO: | |
561 | sparc_memory_model = MM_RMO; | |
562 | break; | |
563 | ||
564 | case 'V': | |
565 | print_version_id (); | |
566 | break; | |
567 | ||
568 | case 'Q': | |
569 | /* Qy - do emit .comment | |
e0c6ed95 | 570 | Qn - do not emit .comment. */ |
252b5132 RH |
571 | break; |
572 | ||
573 | case 's': | |
e0c6ed95 | 574 | /* Use .stab instead of .stab.excl. */ |
252b5132 RH |
575 | break; |
576 | ||
577 | case 'q': | |
e0c6ed95 | 578 | /* quick -- Native assembler does fewer checks. */ |
252b5132 RH |
579 | break; |
580 | ||
581 | case 'K': | |
582 | if (strcmp (arg, "PIC") != 0) | |
583 | as_warn (_("Unrecognized option following -K")); | |
584 | else | |
585 | sparc_pic_code = 1; | |
586 | break; | |
6d8809aa RH |
587 | |
588 | case OPTION_NO_UNDECLARED_REGS: | |
589 | no_undeclared_regs = 1; | |
590 | break; | |
a25fe906 ILT |
591 | |
592 | case OPTION_UNDECLARED_REGS: | |
593 | no_undeclared_regs = 0; | |
594 | break; | |
252b5132 RH |
595 | #endif |
596 | ||
6faf3d66 JJ |
597 | case OPTION_RELAX: |
598 | sparc_relax = 1; | |
599 | break; | |
600 | ||
601 | case OPTION_NO_RELAX: | |
602 | sparc_relax = 0; | |
603 | break; | |
604 | ||
252b5132 RH |
605 | default: |
606 | return 0; | |
607 | } | |
608 | ||
609 | return 1; | |
610 | } | |
611 | ||
612 | void | |
5a49b8ac | 613 | md_show_usage (FILE *stream) |
252b5132 RH |
614 | { |
615 | const struct sparc_arch *arch; | |
c2158c24 | 616 | int column; |
252b5132 RH |
617 | |
618 | /* We don't get a chance to initialize anything before we're called, | |
619 | so handle that now. */ | |
620 | if (! default_init_p) | |
621 | init_default_arch (); | |
622 | ||
e0c6ed95 | 623 | fprintf (stream, _("SPARC options:\n")); |
c2158c24 | 624 | column = 0; |
252b5132 RH |
625 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
626 | { | |
c2158c24 JJ |
627 | if (!arch->user_option_p) |
628 | continue; | |
252b5132 RH |
629 | if (arch != &sparc_arch_table[0]) |
630 | fprintf (stream, " | "); | |
07726851 | 631 | if (column + strlen (arch->name) > 70) |
c2158c24 JJ |
632 | { |
633 | column = 0; | |
634 | fputc ('\n', stream); | |
635 | } | |
07726851 | 636 | column += 5 + 2 + strlen (arch->name); |
c2158c24 | 637 | fprintf (stream, "-A%s", arch->name); |
252b5132 | 638 | } |
c2158c24 JJ |
639 | for (arch = &sparc_arch_table[0]; arch->name; arch++) |
640 | { | |
641 | if (!arch->user_option_p) | |
642 | continue; | |
643 | fprintf (stream, " | "); | |
07726851 | 644 | if (column + strlen (arch->name) > 65) |
c2158c24 JJ |
645 | { |
646 | column = 0; | |
647 | fputc ('\n', stream); | |
648 | } | |
07726851 | 649 | column += 5 + 7 + strlen (arch->name); |
c2158c24 JJ |
650 | fprintf (stream, "-xarch=%s", arch->name); |
651 | } | |
652 | fprintf (stream, _("\n\ | |
252b5132 RH |
653 | specify variant of SPARC architecture\n\ |
654 | -bump warn when assembler switches architectures\n\ | |
655 | -sparc ignored\n\ | |
6faf3d66 JJ |
656 | --enforce-aligned-data force .long, etc., to be aligned correctly\n\ |
657 | -relax relax jumps and branches (default)\n\ | |
658 | -no-relax avoid changing any jumps and branches\n")); | |
252b5132 RH |
659 | #ifdef OBJ_AOUT |
660 | fprintf (stream, _("\ | |
661 | -k generate PIC\n")); | |
662 | #endif | |
663 | #ifdef OBJ_ELF | |
664 | fprintf (stream, _("\ | |
665 | -32 create 32 bit object file\n\ | |
666 | -64 create 64 bit object file\n")); | |
667 | fprintf (stream, _("\ | |
668 | [default is %d]\n"), default_arch_size); | |
669 | fprintf (stream, _("\ | |
670 | -TSO use Total Store Ordering\n\ | |
671 | -PSO use Partial Store Ordering\n\ | |
672 | -RMO use Relaxed Memory Ordering\n")); | |
673 | fprintf (stream, _("\ | |
674 | [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); | |
675 | fprintf (stream, _("\ | |
676 | -KPIC generate PIC\n\ | |
677 | -V print assembler version number\n\ | |
a25fe906 ILT |
678 | -undeclared-regs ignore application global register usage without\n\ |
679 | appropriate .register directive (default)\n\ | |
680 | -no-undeclared-regs force error on application global register usage\n\ | |
681 | without appropriate .register directive\n\ | |
252b5132 RH |
682 | -q ignored\n\ |
683 | -Qy, -Qn ignored\n\ | |
684 | -s ignored\n")); | |
685 | #endif | |
686 | #ifdef SPARC_BIENDIAN | |
687 | fprintf (stream, _("\ | |
688 | -EL generate code for a little endian machine\n\ | |
689 | -EB generate code for a big endian machine\n\ | |
690 | --little-endian-data generate code for a machine having big endian\n\ | |
c20f4f8c | 691 | instructions and little endian data.\n")); |
252b5132 RH |
692 | #endif |
693 | } | |
694 | \f | |
e0c6ed95 | 695 | /* Native operand size opcode translation. */ |
cf9a1301 RH |
696 | struct |
697 | { | |
698 | char *name; | |
699 | char *name32; | |
700 | char *name64; | |
701 | } native_op_table[] = | |
702 | { | |
703 | {"ldn", "ld", "ldx"}, | |
704 | {"ldna", "lda", "ldxa"}, | |
705 | {"stn", "st", "stx"}, | |
706 | {"stna", "sta", "stxa"}, | |
707 | {"slln", "sll", "sllx"}, | |
708 | {"srln", "srl", "srlx"}, | |
709 | {"sran", "sra", "srax"}, | |
710 | {"casn", "cas", "casx"}, | |
711 | {"casna", "casa", "casxa"}, | |
712 | {"clrn", "clr", "clrx"}, | |
713 | {NULL, NULL, NULL}, | |
714 | }; | |
715 | \f | |
10156f83 | 716 | /* sparc64 privileged and hyperprivileged registers. */ |
252b5132 RH |
717 | |
718 | struct priv_reg_entry | |
ab3e48dc KH |
719 | { |
720 | char *name; | |
721 | int regnum; | |
722 | }; | |
252b5132 RH |
723 | |
724 | struct priv_reg_entry priv_reg_table[] = | |
725 | { | |
726 | {"tpc", 0}, | |
727 | {"tnpc", 1}, | |
728 | {"tstate", 2}, | |
729 | {"tt", 3}, | |
730 | {"tick", 4}, | |
731 | {"tba", 5}, | |
732 | {"pstate", 6}, | |
733 | {"tl", 7}, | |
734 | {"pil", 8}, | |
735 | {"cwp", 9}, | |
736 | {"cansave", 10}, | |
737 | {"canrestore", 11}, | |
738 | {"cleanwin", 12}, | |
739 | {"otherwin", 13}, | |
740 | {"wstate", 14}, | |
741 | {"fq", 15}, | |
10156f83 | 742 | {"gl", 16}, |
252b5132 | 743 | {"ver", 31}, |
e0c6ed95 | 744 | {"", -1}, /* End marker. */ |
252b5132 RH |
745 | }; |
746 | ||
10156f83 DM |
747 | struct priv_reg_entry hpriv_reg_table[] = |
748 | { | |
749 | {"hpstate", 0}, | |
750 | {"htstate", 1}, | |
751 | {"hintp", 3}, | |
752 | {"htba", 5}, | |
753 | {"hver", 6}, | |
754 | {"hstick_cmpr", 31}, | |
755 | {"", -1}, /* End marker. */ | |
756 | }; | |
757 | ||
1a6b486f DM |
758 | /* v9a specific asrs. This table is ordered by initial |
759 | letter, in reverse. */ | |
252b5132 RH |
760 | |
761 | struct priv_reg_entry v9a_asr_table[] = | |
762 | { | |
763 | {"tick_cmpr", 23}, | |
19f7b010 JJ |
764 | {"sys_tick_cmpr", 25}, |
765 | {"sys_tick", 24}, | |
1a6b486f DM |
766 | {"stick_cmpr", 25}, |
767 | {"stick", 24}, | |
f04d18b7 DM |
768 | {"softint_clear", 21}, |
769 | {"softint_set", 20}, | |
2b661f3d | 770 | {"softint", 22}, |
252b5132 RH |
771 | {"set_softint", 20}, |
772 | {"pic", 17}, | |
773 | {"pcr", 16}, | |
774 | {"gsr", 19}, | |
775 | {"dcr", 18}, | |
776 | {"clear_softint", 21}, | |
e0c6ed95 | 777 | {"", -1}, /* End marker. */ |
252b5132 RH |
778 | }; |
779 | ||
780 | static int | |
5a49b8ac | 781 | cmp_reg_entry (const void *parg, const void *qarg) |
252b5132 RH |
782 | { |
783 | const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; | |
784 | const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; | |
785 | ||
786 | return strcmp (q->name, p->name); | |
787 | } | |
788 | \f | |
789 | /* This function is called once, at assembler startup time. It should | |
e0c6ed95 AM |
790 | set up all the tables, etc. that the MD part of the assembler will |
791 | need. */ | |
252b5132 RH |
792 | |
793 | void | |
5a49b8ac | 794 | md_begin (void) |
252b5132 RH |
795 | { |
796 | register const char *retval = NULL; | |
797 | int lose = 0; | |
798 | register unsigned int i = 0; | |
799 | ||
800 | /* We don't get a chance to initialize anything before md_parse_option | |
801 | is called, and it may not be called, so handle default initialization | |
802 | now if not already done. */ | |
803 | if (! default_init_p) | |
804 | init_default_arch (); | |
805 | ||
364b6d8b | 806 | sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; |
252b5132 RH |
807 | op_hash = hash_new (); |
808 | ||
809 | while (i < (unsigned int) sparc_num_opcodes) | |
810 | { | |
811 | const char *name = sparc_opcodes[i].name; | |
5a49b8ac | 812 | retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); |
252b5132 RH |
813 | if (retval != NULL) |
814 | { | |
cf9a1301 RH |
815 | as_bad (_("Internal error: can't hash `%s': %s\n"), |
816 | sparc_opcodes[i].name, retval); | |
252b5132 RH |
817 | lose = 1; |
818 | } | |
819 | do | |
820 | { | |
821 | if (sparc_opcodes[i].match & sparc_opcodes[i].lose) | |
822 | { | |
cf9a1301 RH |
823 | as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), |
824 | sparc_opcodes[i].name, sparc_opcodes[i].args); | |
252b5132 RH |
825 | lose = 1; |
826 | } | |
827 | ++i; | |
828 | } | |
829 | while (i < (unsigned int) sparc_num_opcodes | |
830 | && !strcmp (sparc_opcodes[i].name, name)); | |
831 | } | |
832 | ||
cf9a1301 RH |
833 | for (i = 0; native_op_table[i].name; i++) |
834 | { | |
835 | const struct sparc_opcode *insn; | |
3d4ae3c0 NC |
836 | char *name = ((sparc_arch_size == 32) |
837 | ? native_op_table[i].name32 | |
838 | : native_op_table[i].name64); | |
e0c6ed95 | 839 | insn = (struct sparc_opcode *) hash_find (op_hash, name); |
cf9a1301 | 840 | if (insn == NULL) |
e0c6ed95 AM |
841 | { |
842 | as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), | |
843 | name, native_op_table[i].name); | |
844 | lose = 1; | |
845 | } | |
cf9a1301 RH |
846 | else |
847 | { | |
5a49b8ac AM |
848 | retval = hash_insert (op_hash, native_op_table[i].name, |
849 | (void *) insn); | |
cf9a1301 RH |
850 | if (retval != NULL) |
851 | { | |
852 | as_bad (_("Internal error: can't hash `%s': %s\n"), | |
853 | sparc_opcodes[i].name, retval); | |
854 | lose = 1; | |
855 | } | |
856 | } | |
857 | } | |
858 | ||
252b5132 RH |
859 | if (lose) |
860 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
861 | ||
252b5132 RH |
862 | qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), |
863 | sizeof (priv_reg_table[0]), cmp_reg_entry); | |
864 | ||
865 | /* If -bump, record the architecture level at which we start issuing | |
866 | warnings. The behaviour is different depending upon whether an | |
867 | architecture was explicitly specified. If it wasn't, we issue warnings | |
868 | for all upwards bumps. If it was, we don't start issuing warnings until | |
869 | we need to bump beyond the requested architecture or when we bump between | |
870 | conflicting architectures. */ | |
871 | ||
872 | if (warn_on_bump | |
873 | && architecture_requested) | |
874 | { | |
875 | /* `max_architecture' records the requested architecture. | |
876 | Issue warnings if we go above it. */ | |
877 | warn_after_architecture = max_architecture; | |
878 | ||
879 | /* Find the highest architecture level that doesn't conflict with | |
880 | the requested one. */ | |
881 | for (max_architecture = SPARC_OPCODE_ARCH_MAX; | |
882 | max_architecture > warn_after_architecture; | |
883 | --max_architecture) | |
884 | if (! SPARC_OPCODE_CONFLICT_P (max_architecture, | |
885 | warn_after_architecture)) | |
886 | break; | |
887 | } | |
888 | } | |
889 | ||
890 | /* Called after all assembly has been done. */ | |
891 | ||
892 | void | |
5a49b8ac | 893 | sparc_md_end (void) |
252b5132 | 894 | { |
19f7b010 JJ |
895 | unsigned long mach = bfd_mach_sparc; |
896 | ||
252b5132 | 897 | if (sparc_arch_size == 64) |
19f7b010 JJ |
898 | switch (current_architecture) |
899 | { | |
900 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; | |
901 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; | |
902 | default: mach = bfd_mach_sparc_v9; break; | |
903 | } | |
252b5132 | 904 | else |
19f7b010 JJ |
905 | switch (current_architecture) |
906 | { | |
907 | case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; | |
908 | case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; | |
909 | case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; | |
910 | case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; | |
911 | /* The sparclite is treated like a normal sparc. Perhaps it shouldn't | |
912 | be but for now it is (since that's the way it's always been | |
913 | treated). */ | |
914 | default: break; | |
915 | } | |
916 | bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); | |
252b5132 RH |
917 | } |
918 | \f | |
919 | /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ | |
920 | ||
5a49b8ac AM |
921 | static inline int |
922 | in_signed_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
923 | { |
924 | if (max <= 0) | |
925 | abort (); | |
926 | /* Sign-extend the value from the architecture word size, so that | |
927 | 0xffffffff is always considered -1 on sparc32. */ | |
928 | if (sparc_arch_size == 32) | |
929 | { | |
e0c6ed95 | 930 | bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; |
6c1b24e4 | 931 | val = ((val & U0xffffffff) ^ sign) - sign; |
252b5132 RH |
932 | } |
933 | if (val > max) | |
934 | return 0; | |
935 | if (val < ~max) | |
936 | return 0; | |
937 | return 1; | |
938 | } | |
939 | ||
940 | /* Return non-zero if VAL is in the range 0 to MAX. */ | |
941 | ||
5a49b8ac AM |
942 | static inline int |
943 | in_unsigned_range (bfd_vma val, bfd_vma max) | |
252b5132 RH |
944 | { |
945 | if (val > max) | |
946 | return 0; | |
947 | return 1; | |
948 | } | |
949 | ||
950 | /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. | |
951 | (e.g. -15 to +31). */ | |
952 | ||
5a49b8ac AM |
953 | static inline int |
954 | in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) | |
252b5132 RH |
955 | { |
956 | if (max <= 0) | |
957 | abort (); | |
958 | if (val > max) | |
959 | return 0; | |
960 | if (val < ~(max >> 1)) | |
961 | return 0; | |
962 | return 1; | |
963 | } | |
964 | ||
965 | static int | |
5a49b8ac | 966 | sparc_ffs (unsigned int mask) |
252b5132 RH |
967 | { |
968 | int i; | |
969 | ||
970 | if (mask == 0) | |
971 | return -1; | |
972 | ||
973 | for (i = 0; (mask & 1) == 0; ++i) | |
974 | mask >>= 1; | |
975 | return i; | |
976 | } | |
977 | ||
978 | /* Implement big shift right. */ | |
979 | static bfd_vma | |
5a49b8ac | 980 | BSR (bfd_vma val, int amount) |
252b5132 RH |
981 | { |
982 | if (sizeof (bfd_vma) <= 4 && amount >= 32) | |
983 | as_fatal (_("Support for 64-bit arithmetic not compiled in.")); | |
984 | return val >> amount; | |
985 | } | |
986 | \f | |
987 | /* For communication between sparc_ip and get_expression. */ | |
988 | static char *expr_end; | |
989 | ||
252b5132 RH |
990 | /* Values for `special_case'. |
991 | Instructions that require wierd handling because they're longer than | |
992 | 4 bytes. */ | |
993 | #define SPECIAL_CASE_NONE 0 | |
994 | #define SPECIAL_CASE_SET 1 | |
995 | #define SPECIAL_CASE_SETSW 2 | |
996 | #define SPECIAL_CASE_SETX 3 | |
997 | /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ | |
998 | #define SPECIAL_CASE_FDIV 4 | |
999 | ||
1000 | /* Bit masks of various insns. */ | |
1001 | #define NOP_INSN 0x01000000 | |
1002 | #define OR_INSN 0x80100000 | |
63fab58c | 1003 | #define XOR_INSN 0x80180000 |
252b5132 RH |
1004 | #define FMOVS_INSN 0x81A00020 |
1005 | #define SETHI_INSN 0x01000000 | |
1006 | #define SLLX_INSN 0x81281000 | |
1007 | #define SRA_INSN 0x81380000 | |
1008 | ||
1009 | /* The last instruction to be assembled. */ | |
1010 | static const struct sparc_opcode *last_insn; | |
1011 | /* The assembled opcode of `last_insn'. */ | |
1012 | static unsigned long last_opcode; | |
1013 | \f | |
a22b281c | 1014 | /* Handle the set and setuw synthetic instructions. */ |
e0c6ed95 | 1015 | |
a22b281c | 1016 | static void |
5a49b8ac | 1017 | synthetize_setuw (const struct sparc_opcode *insn) |
a22b281c RH |
1018 | { |
1019 | int need_hi22_p = 0; | |
1020 | int rd = (the_insn.opcode & RD (~0)) >> 25; | |
1021 | ||
1022 | if (the_insn.exp.X_op == O_constant) | |
1023 | { | |
1024 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1025 | { | |
e0c6ed95 | 1026 | if (sizeof (offsetT) > 4 |
a22b281c | 1027 | && (the_insn.exp.X_add_number < 0 |
6c1b24e4 | 1028 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) |
a22b281c RH |
1029 | as_warn (_("set: number not in 0..4294967295 range")); |
1030 | } | |
1031 | else | |
1032 | { | |
e0c6ed95 | 1033 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1034 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1035 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c | 1036 | as_warn (_("set: number not in -2147483648..4294967295 range")); |
e0c6ed95 | 1037 | the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; |
a22b281c RH |
1038 | } |
1039 | } | |
1040 | ||
1041 | /* See if operand is absolute and small; skip sethi if so. */ | |
1042 | if (the_insn.exp.X_op != O_constant | |
1043 | || the_insn.exp.X_add_number >= (1 << 12) | |
1044 | || the_insn.exp.X_add_number < -(1 << 12)) | |
1045 | { | |
1046 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1047 | | ((the_insn.exp.X_add_number >> 10) | |
ab3e48dc KH |
1048 | & (the_insn.exp.X_op == O_constant |
1049 | ? 0x3fffff : 0))); | |
a22b281c | 1050 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1051 | ? BFD_RELOC_HI22 : BFD_RELOC_NONE); |
a22b281c RH |
1052 | output_insn (insn, &the_insn); |
1053 | need_hi22_p = 1; | |
1054 | } | |
1055 | ||
1056 | /* See if operand has no low-order bits; skip OR if so. */ | |
1057 | if (the_insn.exp.X_op != O_constant | |
1058 | || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) | |
1059 | || ! need_hi22_p) | |
1060 | { | |
1061 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) | |
1062 | | RD (rd) | IMMED | |
1063 | | (the_insn.exp.X_add_number | |
ab3e48dc KH |
1064 | & (the_insn.exp.X_op != O_constant |
1065 | ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); | |
a22b281c | 1066 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
ab3e48dc | 1067 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); |
a22b281c RH |
1068 | output_insn (insn, &the_insn); |
1069 | } | |
1070 | } | |
e0c6ed95 | 1071 | |
a22b281c | 1072 | /* Handle the setsw synthetic instruction. */ |
e0c6ed95 | 1073 | |
a22b281c | 1074 | static void |
5a49b8ac | 1075 | synthetize_setsw (const struct sparc_opcode *insn) |
a22b281c RH |
1076 | { |
1077 | int low32, rd, opc; | |
1078 | ||
1079 | rd = (the_insn.opcode & RD (~0)) >> 25; | |
1080 | ||
1081 | if (the_insn.exp.X_op != O_constant) | |
1082 | { | |
1083 | synthetize_setuw (insn); | |
1084 | ||
1085 | /* Need to sign extend it. */ | |
1086 | the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); | |
1087 | the_insn.reloc = BFD_RELOC_NONE; | |
1088 | output_insn (insn, &the_insn); | |
1089 | return; | |
1090 | } | |
1091 | ||
e0c6ed95 | 1092 | if (sizeof (offsetT) > 4 |
6c1b24e4 AO |
1093 | && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 |
1094 | || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) | |
a22b281c RH |
1095 | as_warn (_("setsw: number not in -2147483648..4294967295 range")); |
1096 | ||
e0c6ed95 AM |
1097 | low32 = the_insn.exp.X_add_number; |
1098 | ||
a22b281c RH |
1099 | if (low32 >= 0) |
1100 | { | |
1101 | synthetize_setuw (insn); | |
1102 | return; | |
1103 | } | |
1104 | ||
1105 | opc = OR_INSN; | |
e0c6ed95 | 1106 | |
a22b281c RH |
1107 | the_insn.reloc = BFD_RELOC_NONE; |
1108 | /* See if operand is absolute and small; skip sethi if so. */ | |
1109 | if (low32 < -(1 << 12)) | |
1110 | { | |
1111 | the_insn.opcode = (SETHI_INSN | RD (rd) | |
1112 | | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); | |
1113 | output_insn (insn, &the_insn); | |
1114 | low32 = 0x1c00 | (low32 & 0x3ff); | |
1115 | opc = RS1 (rd) | XOR_INSN; | |
1116 | } | |
1117 | ||
1118 | the_insn.opcode = (opc | RD (rd) | IMMED | |
1119 | | (low32 & 0x1fff)); | |
1120 | output_insn (insn, &the_insn); | |
1121 | } | |
1122 | ||
1123 | /* Handle the setsw synthetic instruction. */ | |
e0c6ed95 | 1124 | |
a22b281c | 1125 | static void |
5a49b8ac | 1126 | synthetize_setx (const struct sparc_opcode *insn) |
a22b281c RH |
1127 | { |
1128 | int upper32, lower32; | |
1129 | int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; | |
1130 | int dstreg = (the_insn.opcode & RD (~0)) >> 25; | |
1131 | int upper_dstreg; | |
1132 | int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; | |
1133 | int need_xor10_p = 0; | |
e0c6ed95 | 1134 | |
6c1b24e4 | 1135 | #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) |
a22b281c RH |
1136 | lower32 = SIGNEXT32 (the_insn.exp.X_add_number); |
1137 | upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); | |
1138 | #undef SIGNEXT32 | |
1139 | ||
1140 | upper_dstreg = tmpreg; | |
1141 | /* The tmp reg should not be the dst reg. */ | |
1142 | if (tmpreg == dstreg) | |
1143 | as_warn (_("setx: temporary register same as destination register")); | |
1144 | ||
1145 | /* ??? Obviously there are other optimizations we can do | |
1146 | (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be | |
1147 | doing some of these. Later. If you do change things, try to | |
1148 | change all of this to be table driven as well. */ | |
1149 | /* What to output depends on the number if it's constant. | |
1150 | Compute that first, then output what we've decided upon. */ | |
1151 | if (the_insn.exp.X_op != O_constant) | |
1152 | { | |
1153 | if (sparc_arch_size == 32) | |
1154 | { | |
1155 | /* When arch size is 32, we want setx to be equivalent | |
1156 | to setuw for anything but constants. */ | |
1157 | the_insn.exp.X_add_number &= 0xffffffff; | |
1158 | synthetize_setuw (insn); | |
1159 | return; | |
1160 | } | |
1161 | need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; | |
ab3e48dc KH |
1162 | lower32 = 0; |
1163 | upper32 = 0; | |
a22b281c RH |
1164 | } |
1165 | else | |
1166 | { | |
1167 | /* Reset X_add_number, we've extracted it as upper32/lower32. | |
1168 | Otherwise fixup_segment will complain about not being able to | |
1169 | write an 8 byte number in a 4 byte field. */ | |
1170 | the_insn.exp.X_add_number = 0; | |
e0c6ed95 | 1171 | |
a22b281c RH |
1172 | /* Only need hh22 if `or' insn can't handle constant. */ |
1173 | if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) | |
1174 | need_hh22_p = 1; | |
e0c6ed95 | 1175 | |
a22b281c RH |
1176 | /* Does bottom part (after sethi) have bits? */ |
1177 | if ((need_hh22_p && (upper32 & 0x3ff) != 0) | |
1178 | /* No hh22, but does upper32 still have bits we can't set | |
1179 | from lower32? */ | |
1180 | || (! need_hh22_p && upper32 != 0 && upper32 != -1)) | |
1181 | need_hm10_p = 1; | |
e0c6ed95 | 1182 | |
a22b281c RH |
1183 | /* If the lower half is all zero, we build the upper half directly |
1184 | into the dst reg. */ | |
1185 | if (lower32 != 0 | |
1186 | /* Need lower half if number is zero or 0xffffffff00000000. */ | |
1187 | || (! need_hh22_p && ! need_hm10_p)) | |
1188 | { | |
1189 | /* No need for sethi if `or' insn can handle constant. */ | |
1190 | if (lower32 < -(1 << 12) || lower32 >= (1 << 12) | |
1191 | /* Note that we can't use a negative constant in the `or' | |
1192 | insn unless the upper 32 bits are all ones. */ | |
1193 | || (lower32 < 0 && upper32 != -1) | |
1194 | || (lower32 >= 0 && upper32 == -1)) | |
1195 | need_hi22_p = 1; | |
e0c6ed95 | 1196 | |
a22b281c RH |
1197 | if (need_hi22_p && upper32 == -1) |
1198 | need_xor10_p = 1; | |
1199 | ||
1200 | /* Does bottom part (after sethi) have bits? */ | |
1201 | else if ((need_hi22_p && (lower32 & 0x3ff) != 0) | |
1202 | /* No sethi. */ | |
1203 | || (! need_hi22_p && (lower32 & 0x1fff) != 0) | |
1204 | /* Need `or' if we didn't set anything else. */ | |
1205 | || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) | |
1206 | need_lo10_p = 1; | |
1207 | } | |
1208 | else | |
1209 | /* Output directly to dst reg if lower 32 bits are all zero. */ | |
1210 | upper_dstreg = dstreg; | |
1211 | } | |
e0c6ed95 | 1212 | |
a22b281c RH |
1213 | if (!upper_dstreg && dstreg) |
1214 | as_warn (_("setx: illegal temporary register g0")); | |
1215 | ||
1216 | if (need_hh22_p) | |
1217 | { | |
1218 | the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) | |
1219 | | ((upper32 >> 10) & 0x3fffff)); | |
1220 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1221 | ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); | |
1222 | output_insn (insn, &the_insn); | |
1223 | } | |
e0c6ed95 | 1224 | |
a22b281c RH |
1225 | if (need_hi22_p) |
1226 | { | |
1227 | the_insn.opcode = (SETHI_INSN | RD (dstreg) | |
1228 | | (((need_xor10_p ? ~lower32 : lower32) | |
ab3e48dc | 1229 | >> 10) & 0x3fffff)); |
a22b281c RH |
1230 | the_insn.reloc = (the_insn.exp.X_op != O_constant |
1231 | ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); | |
1232 | output_insn (insn, &the_insn); | |
1233 | } | |
1234 | ||
1235 | if (need_hm10_p) | |
1236 | { | |
1237 | the_insn.opcode = (OR_INSN | |
1238 | | (need_hh22_p ? RS1 (upper_dstreg) : 0) | |
1239 | | RD (upper_dstreg) | |
1240 | | IMMED | |
1241 | | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); | |
1242 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1243 | ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); | |
1244 | output_insn (insn, &the_insn); | |
1245 | } | |
e0c6ed95 | 1246 | |
a22b281c RH |
1247 | if (need_lo10_p) |
1248 | { | |
1249 | /* FIXME: One nice optimization to do here is to OR the low part | |
1250 | with the highpart if hi22 isn't needed and the low part is | |
1251 | positive. */ | |
1252 | the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) | |
1253 | | RD (dstreg) | |
1254 | | IMMED | |
1255 | | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); | |
1256 | the_insn.reloc = (the_insn.exp.X_op != O_constant | |
1257 | ? BFD_RELOC_LO10 : BFD_RELOC_NONE); | |
1258 | output_insn (insn, &the_insn); | |
1259 | } | |
e0c6ed95 | 1260 | |
a22b281c RH |
1261 | /* If we needed to build the upper part, shift it into place. */ |
1262 | if (need_hh22_p || need_hm10_p) | |
1263 | { | |
1264 | the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) | |
1265 | | IMMED | 32); | |
1266 | the_insn.reloc = BFD_RELOC_NONE; | |
1267 | output_insn (insn, &the_insn); | |
1268 | } | |
e0c6ed95 | 1269 | |
a22b281c RH |
1270 | /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ |
1271 | if (need_xor10_p) | |
1272 | { | |
1273 | the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED | |
1274 | | 0x1c00 | (lower32 & 0x3ff)); | |
1275 | the_insn.reloc = BFD_RELOC_NONE; | |
1276 | output_insn (insn, &the_insn); | |
1277 | } | |
1278 | ||
1279 | /* If we needed to build both upper and lower parts, OR them together. */ | |
1280 | else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) | |
1281 | { | |
1282 | the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) | |
1283 | | RD (dstreg)); | |
1284 | the_insn.reloc = BFD_RELOC_NONE; | |
1285 | output_insn (insn, &the_insn); | |
1286 | } | |
1287 | } | |
1288 | \f | |
252b5132 RH |
1289 | /* Main entry point to assemble one instruction. */ |
1290 | ||
1291 | void | |
5a49b8ac | 1292 | md_assemble (char *str) |
252b5132 RH |
1293 | { |
1294 | const struct sparc_opcode *insn; | |
a22b281c | 1295 | int special_case; |
252b5132 RH |
1296 | |
1297 | know (str); | |
a22b281c | 1298 | special_case = sparc_ip (str, &insn); |
b0825cc2 DM |
1299 | if (insn == NULL) |
1300 | return; | |
252b5132 RH |
1301 | |
1302 | /* We warn about attempts to put a floating point branch in a delay slot, | |
1303 | unless the delay slot has been annulled. */ | |
b0825cc2 | 1304 | if (last_insn != NULL |
252b5132 RH |
1305 | && (insn->flags & F_FBR) != 0 |
1306 | && (last_insn->flags & F_DELAYED) != 0 | |
1307 | /* ??? This test isn't completely accurate. We assume anything with | |
1308 | F_{UNBR,CONDBR,FBR} set is annullable. */ | |
1309 | && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 | |
1310 | || (last_opcode & ANNUL) == 0)) | |
1311 | as_warn (_("FP branch in delay slot")); | |
1312 | ||
1313 | /* SPARC before v9 requires a nop instruction between a floating | |
1314 | point instruction and a floating point branch. We insert one | |
1315 | automatically, with a warning. */ | |
1316 | if (max_architecture < SPARC_OPCODE_ARCH_V9 | |
252b5132 RH |
1317 | && last_insn != NULL |
1318 | && (insn->flags & F_FBR) != 0 | |
1319 | && (last_insn->flags & F_FLOAT) != 0) | |
1320 | { | |
1321 | struct sparc_it nop_insn; | |
1322 | ||
1323 | nop_insn.opcode = NOP_INSN; | |
1324 | nop_insn.reloc = BFD_RELOC_NONE; | |
1325 | output_insn (insn, &nop_insn); | |
1326 | as_warn (_("FP branch preceded by FP instruction; NOP inserted")); | |
1327 | } | |
1328 | ||
a22b281c RH |
1329 | switch (special_case) |
1330 | { | |
1331 | case SPECIAL_CASE_NONE: | |
e0c6ed95 | 1332 | /* Normal insn. */ |
a22b281c RH |
1333 | output_insn (insn, &the_insn); |
1334 | break; | |
252b5132 | 1335 | |
a22b281c RH |
1336 | case SPECIAL_CASE_SETSW: |
1337 | synthetize_setsw (insn); | |
1338 | break; | |
e0c6ed95 | 1339 | |
a22b281c RH |
1340 | case SPECIAL_CASE_SET: |
1341 | synthetize_setuw (insn); | |
1342 | break; | |
252b5132 | 1343 | |
a22b281c RH |
1344 | case SPECIAL_CASE_SETX: |
1345 | synthetize_setx (insn); | |
1346 | break; | |
e0c6ed95 | 1347 | |
a22b281c RH |
1348 | case SPECIAL_CASE_FDIV: |
1349 | { | |
1350 | int rd = (the_insn.opcode >> 25) & 0x1f; | |
e0c6ed95 | 1351 | |
a22b281c | 1352 | output_insn (insn, &the_insn); |
e0c6ed95 | 1353 | |
a22b281c RH |
1354 | /* According to information leaked from Sun, the "fdiv" instructions |
1355 | on early SPARC machines would produce incorrect results sometimes. | |
1356 | The workaround is to add an fmovs of the destination register to | |
1357 | itself just after the instruction. This was true on machines | |
e0c6ed95 | 1358 | with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ |
9c2799c2 | 1359 | gas_assert (the_insn.reloc == BFD_RELOC_NONE); |
a22b281c RH |
1360 | the_insn.opcode = FMOVS_INSN | rd | RD (rd); |
1361 | output_insn (insn, &the_insn); | |
1362 | return; | |
1363 | } | |
e0c6ed95 | 1364 | |
a22b281c RH |
1365 | default: |
1366 | as_fatal (_("failed special case insn sanity check")); | |
252b5132 RH |
1367 | } |
1368 | } | |
1369 | ||
1370 | /* Subroutine of md_assemble to do the actual parsing. */ | |
1371 | ||
a22b281c | 1372 | static int |
5a49b8ac | 1373 | sparc_ip (char *str, const struct sparc_opcode **pinsn) |
252b5132 RH |
1374 | { |
1375 | char *error_message = ""; | |
1376 | char *s; | |
1377 | const char *args; | |
1378 | char c; | |
1379 | const struct sparc_opcode *insn; | |
1380 | char *argsStart; | |
1381 | unsigned long opcode; | |
1382 | unsigned int mask = 0; | |
1383 | int match = 0; | |
1384 | int comma = 0; | |
1385 | int v9_arg_p; | |
a22b281c | 1386 | int special_case = SPECIAL_CASE_NONE; |
252b5132 RH |
1387 | |
1388 | s = str; | |
3882b010 | 1389 | if (ISLOWER (*s)) |
252b5132 RH |
1390 | { |
1391 | do | |
1392 | ++s; | |
3882b010 | 1393 | while (ISLOWER (*s) || ISDIGIT (*s)); |
252b5132 RH |
1394 | } |
1395 | ||
1396 | switch (*s) | |
1397 | { | |
1398 | case '\0': | |
1399 | break; | |
1400 | ||
1401 | case ',': | |
1402 | comma = 1; | |
e0c6ed95 | 1403 | /* Fall through. */ |
252b5132 RH |
1404 | |
1405 | case ' ': | |
1406 | *s++ = '\0'; | |
1407 | break; | |
1408 | ||
1409 | default: | |
b0825cc2 DM |
1410 | as_bad (_("Unknown opcode: `%s'"), str); |
1411 | *pinsn = NULL; | |
1412 | return special_case; | |
252b5132 RH |
1413 | } |
1414 | insn = (struct sparc_opcode *) hash_find (op_hash, str); | |
1415 | *pinsn = insn; | |
1416 | if (insn == NULL) | |
1417 | { | |
1418 | as_bad (_("Unknown opcode: `%s'"), str); | |
a22b281c | 1419 | return special_case; |
252b5132 RH |
1420 | } |
1421 | if (comma) | |
1422 | { | |
1423 | *--s = ','; | |
1424 | } | |
1425 | ||
1426 | argsStart = s; | |
1427 | for (;;) | |
1428 | { | |
1429 | opcode = insn->match; | |
1430 | memset (&the_insn, '\0', sizeof (the_insn)); | |
1431 | the_insn.reloc = BFD_RELOC_NONE; | |
1432 | v9_arg_p = 0; | |
1433 | ||
e0c6ed95 AM |
1434 | /* Build the opcode, checking as we go to make sure that the |
1435 | operands match. */ | |
252b5132 RH |
1436 | for (args = insn->args;; ++args) |
1437 | { | |
1438 | switch (*args) | |
1439 | { | |
1440 | case 'K': | |
1441 | { | |
1442 | int kmask = 0; | |
1443 | ||
1444 | /* Parse a series of masks. */ | |
1445 | if (*s == '#') | |
1446 | { | |
1447 | while (*s == '#') | |
1448 | { | |
91d6fa6a | 1449 | int jmask; |
252b5132 RH |
1450 | |
1451 | if (! parse_keyword_arg (sparc_encode_membar, &s, | |
91d6fa6a | 1452 | &jmask)) |
252b5132 RH |
1453 | { |
1454 | error_message = _(": invalid membar mask name"); | |
1455 | goto error; | |
1456 | } | |
91d6fa6a | 1457 | kmask |= jmask; |
47926f60 KH |
1458 | while (*s == ' ') |
1459 | ++s; | |
252b5132 RH |
1460 | if (*s == '|' || *s == '+') |
1461 | ++s; | |
47926f60 KH |
1462 | while (*s == ' ') |
1463 | ++s; | |
252b5132 RH |
1464 | } |
1465 | } | |
1466 | else | |
1467 | { | |
1468 | if (! parse_const_expr_arg (&s, &kmask)) | |
1469 | { | |
1470 | error_message = _(": invalid membar mask expression"); | |
1471 | goto error; | |
1472 | } | |
1473 | if (kmask < 0 || kmask > 127) | |
1474 | { | |
1475 | error_message = _(": invalid membar mask number"); | |
1476 | goto error; | |
1477 | } | |
1478 | } | |
1479 | ||
1480 | opcode |= MEMBAR (kmask); | |
1481 | continue; | |
1482 | } | |
1483 | ||
19f7b010 JJ |
1484 | case '3': |
1485 | { | |
1486 | int smask = 0; | |
1487 | ||
1488 | if (! parse_const_expr_arg (&s, &smask)) | |
1489 | { | |
1490 | error_message = _(": invalid siam mode expression"); | |
1491 | goto error; | |
1492 | } | |
1493 | if (smask < 0 || smask > 7) | |
1494 | { | |
1495 | error_message = _(": invalid siam mode number"); | |
1496 | goto error; | |
1497 | } | |
1498 | opcode |= smask; | |
1499 | continue; | |
1500 | } | |
1501 | ||
252b5132 RH |
1502 | case '*': |
1503 | { | |
1504 | int fcn = 0; | |
1505 | ||
1506 | /* Parse a prefetch function. */ | |
1507 | if (*s == '#') | |
1508 | { | |
1509 | if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) | |
1510 | { | |
1511 | error_message = _(": invalid prefetch function name"); | |
1512 | goto error; | |
1513 | } | |
1514 | } | |
1515 | else | |
1516 | { | |
1517 | if (! parse_const_expr_arg (&s, &fcn)) | |
1518 | { | |
1519 | error_message = _(": invalid prefetch function expression"); | |
1520 | goto error; | |
1521 | } | |
1522 | if (fcn < 0 || fcn > 31) | |
1523 | { | |
1524 | error_message = _(": invalid prefetch function number"); | |
1525 | goto error; | |
1526 | } | |
1527 | } | |
1528 | opcode |= RD (fcn); | |
1529 | continue; | |
1530 | } | |
1531 | ||
1532 | case '!': | |
1533 | case '?': | |
1534 | /* Parse a sparc64 privileged register. */ | |
1535 | if (*s == '%') | |
1536 | { | |
1537 | struct priv_reg_entry *p = priv_reg_table; | |
e0c6ed95 | 1538 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1539 | |
1540 | s += 1; | |
1541 | while (p->name[0] > s[0]) | |
1542 | p++; | |
1543 | while (p->name[0] == s[0]) | |
1544 | { | |
1545 | len = strlen (p->name); | |
1546 | if (strncmp (p->name, s, len) == 0) | |
1547 | break; | |
1548 | p++; | |
1549 | } | |
1550 | if (p->name[0] != s[0]) | |
1551 | { | |
1552 | error_message = _(": unrecognizable privileged register"); | |
1553 | goto error; | |
1554 | } | |
1555 | if (*args == '?') | |
1556 | opcode |= (p->regnum << 14); | |
1557 | else | |
1558 | opcode |= (p->regnum << 25); | |
1559 | s += len; | |
1560 | continue; | |
1561 | } | |
1562 | else | |
1563 | { | |
1564 | error_message = _(": unrecognizable privileged register"); | |
1565 | goto error; | |
1566 | } | |
1567 | ||
10156f83 DM |
1568 | case '$': |
1569 | case '%': | |
1570 | /* Parse a sparc64 hyperprivileged register. */ | |
1571 | if (*s == '%') | |
1572 | { | |
1573 | struct priv_reg_entry *p = hpriv_reg_table; | |
1574 | unsigned int len = 9999999; /* Init to make gcc happy. */ | |
1575 | ||
1576 | s += 1; | |
1577 | while (p->name[0] > s[0]) | |
1578 | p++; | |
1579 | while (p->name[0] == s[0]) | |
1580 | { | |
1581 | len = strlen (p->name); | |
1582 | if (strncmp (p->name, s, len) == 0) | |
1583 | break; | |
1584 | p++; | |
1585 | } | |
1586 | if (p->name[0] != s[0]) | |
1587 | { | |
1588 | error_message = _(": unrecognizable hyperprivileged register"); | |
1589 | goto error; | |
1590 | } | |
1591 | if (*args == '$') | |
1592 | opcode |= (p->regnum << 14); | |
1593 | else | |
1594 | opcode |= (p->regnum << 25); | |
1595 | s += len; | |
1596 | continue; | |
1597 | } | |
1598 | else | |
1599 | { | |
1600 | error_message = _(": unrecognizable hyperprivileged register"); | |
1601 | goto error; | |
1602 | } | |
1603 | ||
252b5132 RH |
1604 | case '_': |
1605 | case '/': | |
19f7b010 | 1606 | /* Parse a v9a/v9b ancillary state register. */ |
252b5132 RH |
1607 | if (*s == '%') |
1608 | { | |
1609 | struct priv_reg_entry *p = v9a_asr_table; | |
e0c6ed95 | 1610 | unsigned int len = 9999999; /* Init to make gcc happy. */ |
252b5132 RH |
1611 | |
1612 | s += 1; | |
1613 | while (p->name[0] > s[0]) | |
1614 | p++; | |
1615 | while (p->name[0] == s[0]) | |
1616 | { | |
1617 | len = strlen (p->name); | |
1618 | if (strncmp (p->name, s, len) == 0) | |
1619 | break; | |
1620 | p++; | |
1621 | } | |
1622 | if (p->name[0] != s[0]) | |
1623 | { | |
19f7b010 | 1624 | error_message = _(": unrecognizable v9a or v9b ancillary state register"); |
252b5132 RH |
1625 | goto error; |
1626 | } | |
1627 | if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) | |
1628 | { | |
1629 | error_message = _(": rd on write only ancillary state register"); | |
1630 | goto error; | |
e0c6ed95 | 1631 | } |
19f7b010 JJ |
1632 | if (p->regnum >= 24 |
1633 | && (insn->architecture | |
1634 | & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) | |
1635 | { | |
1636 | /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ | |
1637 | error_message = _(": unrecognizable v9a ancillary state register"); | |
1638 | goto error; | |
1639 | } | |
252b5132 RH |
1640 | if (*args == '/') |
1641 | opcode |= (p->regnum << 14); | |
1642 | else | |
1643 | opcode |= (p->regnum << 25); | |
1644 | s += len; | |
1645 | continue; | |
1646 | } | |
1647 | else | |
1648 | { | |
19f7b010 | 1649 | error_message = _(": unrecognizable v9a or v9b ancillary state register"); |
252b5132 RH |
1650 | goto error; |
1651 | } | |
1652 | ||
1653 | case 'M': | |
1654 | case 'm': | |
1655 | if (strncmp (s, "%asr", 4) == 0) | |
1656 | { | |
1657 | s += 4; | |
1658 | ||
3882b010 | 1659 | if (ISDIGIT (*s)) |
252b5132 RH |
1660 | { |
1661 | long num = 0; | |
1662 | ||
3882b010 | 1663 | while (ISDIGIT (*s)) |
252b5132 RH |
1664 | { |
1665 | num = num * 10 + *s - '0'; | |
1666 | ++s; | |
1667 | } | |
1668 | ||
1669 | if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
1670 | { | |
1671 | if (num < 16 || 31 < num) | |
1672 | { | |
1673 | error_message = _(": asr number must be between 16 and 31"); | |
1674 | goto error; | |
1675 | } | |
1676 | } | |
1677 | else | |
1678 | { | |
1679 | if (num < 0 || 31 < num) | |
1680 | { | |
1681 | error_message = _(": asr number must be between 0 and 31"); | |
1682 | goto error; | |
1683 | } | |
1684 | } | |
1685 | ||
1686 | opcode |= (*args == 'M' ? RS1 (num) : RD (num)); | |
1687 | continue; | |
1688 | } | |
1689 | else | |
1690 | { | |
1691 | error_message = _(": expecting %asrN"); | |
1692 | goto error; | |
1693 | } | |
e0c6ed95 | 1694 | } /* if %asr */ |
252b5132 RH |
1695 | break; |
1696 | ||
1697 | case 'I': | |
1698 | the_insn.reloc = BFD_RELOC_SPARC_11; | |
1699 | goto immediate; | |
1700 | ||
1701 | case 'j': | |
1702 | the_insn.reloc = BFD_RELOC_SPARC_10; | |
1703 | goto immediate; | |
1704 | ||
1705 | case 'X': | |
1706 | /* V8 systems don't understand BFD_RELOC_SPARC_5. */ | |
1707 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1708 | the_insn.reloc = BFD_RELOC_SPARC_5; | |
1709 | else | |
1710 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1711 | /* These fields are unsigned, but for upward compatibility, | |
1712 | allow negative values as well. */ | |
1713 | goto immediate; | |
1714 | ||
1715 | case 'Y': | |
1716 | /* V8 systems don't understand BFD_RELOC_SPARC_6. */ | |
1717 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
1718 | the_insn.reloc = BFD_RELOC_SPARC_6; | |
1719 | else | |
1720 | the_insn.reloc = BFD_RELOC_SPARC13; | |
1721 | /* These fields are unsigned, but for upward compatibility, | |
1722 | allow negative values as well. */ | |
1723 | goto immediate; | |
1724 | ||
1725 | case 'k': | |
1726 | the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; | |
1727 | the_insn.pcrel = 1; | |
1728 | goto immediate; | |
1729 | ||
1730 | case 'G': | |
1731 | the_insn.reloc = BFD_RELOC_SPARC_WDISP19; | |
1732 | the_insn.pcrel = 1; | |
1733 | goto immediate; | |
1734 | ||
1735 | case 'N': | |
1736 | if (*s == 'p' && s[1] == 'n') | |
1737 | { | |
1738 | s += 2; | |
1739 | continue; | |
1740 | } | |
1741 | break; | |
1742 | ||
1743 | case 'T': | |
1744 | if (*s == 'p' && s[1] == 't') | |
1745 | { | |
1746 | s += 2; | |
1747 | continue; | |
1748 | } | |
1749 | break; | |
1750 | ||
1751 | case 'z': | |
1752 | if (*s == ' ') | |
1753 | { | |
1754 | ++s; | |
1755 | } | |
1756 | if (strncmp (s, "%icc", 4) == 0) | |
1757 | { | |
1758 | s += 4; | |
1759 | continue; | |
1760 | } | |
1761 | break; | |
1762 | ||
1763 | case 'Z': | |
1764 | if (*s == ' ') | |
1765 | { | |
1766 | ++s; | |
1767 | } | |
1768 | if (strncmp (s, "%xcc", 4) == 0) | |
1769 | { | |
1770 | s += 4; | |
1771 | continue; | |
1772 | } | |
1773 | break; | |
1774 | ||
1775 | case '6': | |
1776 | if (*s == ' ') | |
1777 | { | |
1778 | ++s; | |
1779 | } | |
1780 | if (strncmp (s, "%fcc0", 5) == 0) | |
1781 | { | |
1782 | s += 5; | |
1783 | continue; | |
1784 | } | |
1785 | break; | |
1786 | ||
1787 | case '7': | |
1788 | if (*s == ' ') | |
1789 | { | |
1790 | ++s; | |
1791 | } | |
1792 | if (strncmp (s, "%fcc1", 5) == 0) | |
1793 | { | |
1794 | s += 5; | |
1795 | continue; | |
1796 | } | |
1797 | break; | |
1798 | ||
1799 | case '8': | |
1800 | if (*s == ' ') | |
1801 | { | |
1802 | ++s; | |
1803 | } | |
1804 | if (strncmp (s, "%fcc2", 5) == 0) | |
1805 | { | |
1806 | s += 5; | |
1807 | continue; | |
1808 | } | |
1809 | break; | |
1810 | ||
1811 | case '9': | |
1812 | if (*s == ' ') | |
1813 | { | |
1814 | ++s; | |
1815 | } | |
1816 | if (strncmp (s, "%fcc3", 5) == 0) | |
1817 | { | |
1818 | s += 5; | |
1819 | continue; | |
1820 | } | |
1821 | break; | |
1822 | ||
1823 | case 'P': | |
1824 | if (strncmp (s, "%pc", 3) == 0) | |
1825 | { | |
1826 | s += 3; | |
1827 | continue; | |
1828 | } | |
1829 | break; | |
1830 | ||
1831 | case 'W': | |
1832 | if (strncmp (s, "%tick", 5) == 0) | |
1833 | { | |
1834 | s += 5; | |
1835 | continue; | |
1836 | } | |
1837 | break; | |
1838 | ||
e0c6ed95 | 1839 | case '\0': /* End of args. */ |
b9734f35 | 1840 | if (s[0] == ',' && s[1] == '%') |
252b5132 | 1841 | { |
739f7f82 | 1842 | static const struct ops |
dfeb0666 | 1843 | { |
b9734f35 JJ |
1844 | /* The name as it appears in assembler. */ |
1845 | char *name; | |
1846 | /* strlen (name), precomputed for speed */ | |
1847 | int len; | |
1848 | /* The reloc this pseudo-op translates to. */ | |
1849 | int reloc; | |
739f7f82 DM |
1850 | /* 1 if tls call. */ |
1851 | int tls_call; | |
dfeb0666 | 1852 | } |
739f7f82 | 1853 | ops[] = |
dfeb0666 | 1854 | { |
b9734f35 JJ |
1855 | { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 }, |
1856 | { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 }, | |
1857 | { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 }, | |
1858 | { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 }, | |
1859 | { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 }, | |
1860 | { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 }, | |
1861 | { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 }, | |
dfeb0666 | 1862 | { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }, |
739f7f82 | 1863 | { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 }, |
dfeb0666 | 1864 | { NULL, 0, 0, 0 } |
b9734f35 | 1865 | }; |
739f7f82 | 1866 | const struct ops *o; |
b9734f35 JJ |
1867 | char *s1; |
1868 | int npar = 0; | |
1869 | ||
739f7f82 | 1870 | for (o = ops; o->name; o++) |
b9734f35 JJ |
1871 | if (strncmp (s + 2, o->name, o->len) == 0) |
1872 | break; | |
1873 | if (o->name == NULL) | |
1874 | break; | |
1875 | ||
1876 | if (s[o->len + 2] != '(') | |
1877 | { | |
1878 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
1879 | return special_case; | |
1880 | } | |
1881 | ||
739f7f82 | 1882 | if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE) |
b9734f35 JJ |
1883 | { |
1884 | as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), | |
1885 | o->name); | |
1886 | return special_case; | |
1887 | } | |
1888 | ||
739f7f82 | 1889 | if (o->tls_call |
b9734f35 JJ |
1890 | && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 |
1891 | || the_insn.exp.X_add_number != 0 | |
1892 | || the_insn.exp.X_add_symbol | |
1893 | != symbol_find_or_make ("__tls_get_addr"))) | |
1894 | { | |
1895 | as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), | |
1896 | o->name); | |
1897 | return special_case; | |
1898 | } | |
1899 | ||
1900 | the_insn.reloc = o->reloc; | |
1901 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); | |
1902 | s += o->len + 3; | |
1903 | ||
1904 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
1905 | if (*s1 == '(') | |
1906 | npar++; | |
1907 | else if (*s1 == ')') | |
1908 | { | |
1909 | if (!npar) | |
1910 | break; | |
1911 | npar--; | |
1912 | } | |
1913 | ||
1914 | if (*s1 != ')') | |
1915 | { | |
1916 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
1917 | return special_case; | |
1918 | } | |
1919 | ||
1920 | *s1 = '\0'; | |
1921 | (void) get_expression (s); | |
1922 | *s1 = ')'; | |
1923 | s = s1 + 1; | |
252b5132 | 1924 | } |
b9734f35 JJ |
1925 | if (*s == '\0') |
1926 | match = 1; | |
252b5132 RH |
1927 | break; |
1928 | ||
1929 | case '+': | |
1930 | if (*s == '+') | |
1931 | { | |
1932 | ++s; | |
1933 | continue; | |
1934 | } | |
1935 | if (*s == '-') | |
1936 | { | |
1937 | continue; | |
1938 | } | |
1939 | break; | |
1940 | ||
e0c6ed95 | 1941 | case '[': /* These must match exactly. */ |
252b5132 RH |
1942 | case ']': |
1943 | case ',': | |
1944 | case ' ': | |
1945 | if (*s++ == *args) | |
1946 | continue; | |
1947 | break; | |
1948 | ||
e0c6ed95 | 1949 | case '#': /* Must be at least one digit. */ |
3882b010 | 1950 | if (ISDIGIT (*s++)) |
252b5132 | 1951 | { |
3882b010 | 1952 | while (ISDIGIT (*s)) |
252b5132 RH |
1953 | { |
1954 | ++s; | |
1955 | } | |
1956 | continue; | |
1957 | } | |
1958 | break; | |
1959 | ||
e0c6ed95 | 1960 | case 'C': /* Coprocessor state register. */ |
252b5132 RH |
1961 | if (strncmp (s, "%csr", 4) == 0) |
1962 | { | |
1963 | s += 4; | |
1964 | continue; | |
1965 | } | |
1966 | break; | |
1967 | ||
e0c6ed95 | 1968 | case 'b': /* Next operand is a coprocessor register. */ |
252b5132 RH |
1969 | case 'c': |
1970 | case 'D': | |
3882b010 | 1971 | if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) |
252b5132 RH |
1972 | { |
1973 | mask = *s++; | |
3882b010 | 1974 | if (ISDIGIT (*s)) |
252b5132 RH |
1975 | { |
1976 | mask = 10 * (mask - '0') + (*s++ - '0'); | |
1977 | if (mask >= 32) | |
1978 | { | |
1979 | break; | |
1980 | } | |
1981 | } | |
1982 | else | |
1983 | { | |
1984 | mask -= '0'; | |
1985 | } | |
1986 | switch (*args) | |
1987 | { | |
1988 | ||
1989 | case 'b': | |
1990 | opcode |= mask << 14; | |
1991 | continue; | |
1992 | ||
1993 | case 'c': | |
1994 | opcode |= mask; | |
1995 | continue; | |
1996 | ||
1997 | case 'D': | |
1998 | opcode |= mask << 25; | |
1999 | continue; | |
2000 | } | |
2001 | } | |
2002 | break; | |
2003 | ||
2004 | case 'r': /* next operand must be a register */ | |
2005 | case 'O': | |
2006 | case '1': | |
2007 | case '2': | |
2008 | case 'd': | |
2009 | if (*s++ == '%') | |
2010 | { | |
2011 | switch (c = *s++) | |
2012 | { | |
2013 | ||
2014 | case 'f': /* frame pointer */ | |
2015 | if (*s++ == 'p') | |
2016 | { | |
2017 | mask = 0x1e; | |
2018 | break; | |
2019 | } | |
2020 | goto error; | |
2021 | ||
2022 | case 'g': /* global register */ | |
a22b281c RH |
2023 | c = *s++; |
2024 | if (isoctal (c)) | |
252b5132 RH |
2025 | { |
2026 | mask = c - '0'; | |
2027 | break; | |
2028 | } | |
2029 | goto error; | |
2030 | ||
2031 | case 'i': /* in register */ | |
a22b281c RH |
2032 | c = *s++; |
2033 | if (isoctal (c)) | |
252b5132 RH |
2034 | { |
2035 | mask = c - '0' + 24; | |
2036 | break; | |
2037 | } | |
2038 | goto error; | |
2039 | ||
2040 | case 'l': /* local register */ | |
a22b281c RH |
2041 | c = *s++; |
2042 | if (isoctal (c)) | |
252b5132 RH |
2043 | { |
2044 | mask = (c - '0' + 16); | |
2045 | break; | |
2046 | } | |
2047 | goto error; | |
2048 | ||
2049 | case 'o': /* out register */ | |
a22b281c RH |
2050 | c = *s++; |
2051 | if (isoctal (c)) | |
252b5132 RH |
2052 | { |
2053 | mask = (c - '0' + 8); | |
2054 | break; | |
2055 | } | |
2056 | goto error; | |
2057 | ||
2058 | case 's': /* stack pointer */ | |
2059 | if (*s++ == 'p') | |
2060 | { | |
2061 | mask = 0xe; | |
2062 | break; | |
2063 | } | |
2064 | goto error; | |
2065 | ||
2066 | case 'r': /* any register */ | |
3882b010 | 2067 | if (!ISDIGIT ((c = *s++))) |
252b5132 RH |
2068 | { |
2069 | goto error; | |
2070 | } | |
2071 | /* FALLTHROUGH */ | |
2072 | case '0': | |
2073 | case '1': | |
2074 | case '2': | |
2075 | case '3': | |
2076 | case '4': | |
2077 | case '5': | |
2078 | case '6': | |
2079 | case '7': | |
2080 | case '8': | |
2081 | case '9': | |
3882b010 | 2082 | if (ISDIGIT (*s)) |
252b5132 RH |
2083 | { |
2084 | if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) | |
2085 | { | |
2086 | goto error; | |
2087 | } | |
2088 | } | |
2089 | else | |
2090 | { | |
2091 | c -= '0'; | |
2092 | } | |
2093 | mask = c; | |
2094 | break; | |
2095 | ||
2096 | default: | |
2097 | goto error; | |
2098 | } | |
2099 | ||
6d8809aa | 2100 | if ((mask & ~1) == 2 && sparc_arch_size == 64 |
e0c6ed95 | 2101 | && no_undeclared_regs && ! globals[mask]) |
79bd78be | 2102 | as_bad (_("detected global register use not covered by .register pseudo-op")); |
6d8809aa | 2103 | |
252b5132 RH |
2104 | /* Got the register, now figure out where |
2105 | it goes in the opcode. */ | |
2106 | switch (*args) | |
2107 | { | |
2108 | case '1': | |
2109 | opcode |= mask << 14; | |
2110 | continue; | |
2111 | ||
2112 | case '2': | |
2113 | opcode |= mask; | |
2114 | continue; | |
2115 | ||
2116 | case 'd': | |
2117 | opcode |= mask << 25; | |
2118 | continue; | |
2119 | ||
2120 | case 'r': | |
2121 | opcode |= (mask << 25) | (mask << 14); | |
2122 | continue; | |
2123 | ||
2124 | case 'O': | |
2125 | opcode |= (mask << 25) | (mask << 0); | |
2126 | continue; | |
2127 | } | |
2128 | } | |
2129 | break; | |
2130 | ||
2131 | case 'e': /* next operand is a floating point register */ | |
2132 | case 'v': | |
2133 | case 'V': | |
2134 | ||
2135 | case 'f': | |
2136 | case 'B': | |
2137 | case 'R': | |
2138 | ||
2139 | case 'g': | |
2140 | case 'H': | |
2141 | case 'J': | |
2142 | { | |
2143 | char format; | |
2144 | ||
2145 | if (*s++ == '%' | |
2146 | && ((format = *s) == 'f') | |
3882b010 | 2147 | && ISDIGIT (*++s)) |
252b5132 | 2148 | { |
3882b010 | 2149 | for (mask = 0; ISDIGIT (*s); ++s) |
252b5132 RH |
2150 | { |
2151 | mask = 10 * mask + (*s - '0'); | |
2152 | } /* read the number */ | |
2153 | ||
2154 | if ((*args == 'v' | |
2155 | || *args == 'B' | |
2156 | || *args == 'H') | |
2157 | && (mask & 1)) | |
2158 | { | |
2159 | break; | |
2160 | } /* register must be even numbered */ | |
2161 | ||
2162 | if ((*args == 'V' | |
2163 | || *args == 'R' | |
2164 | || *args == 'J') | |
2165 | && (mask & 3)) | |
2166 | { | |
2167 | break; | |
2168 | } /* register must be multiple of 4 */ | |
2169 | ||
2170 | if (mask >= 64) | |
2171 | { | |
2172 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2173 | error_message = _(": There are only 64 f registers; [0-63]"); | |
2174 | else | |
2175 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2176 | goto error; | |
2177 | } /* on error */ | |
2178 | else if (mask >= 32) | |
2179 | { | |
2180 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
2181 | { | |
26664553 JJ |
2182 | if (*args == 'e' || *args == 'f' || *args == 'g') |
2183 | { | |
2184 | error_message | |
2185 | = _(": There are only 32 single precision f registers; [0-31]"); | |
2186 | goto error; | |
2187 | } | |
252b5132 RH |
2188 | v9_arg_p = 1; |
2189 | mask -= 31; /* wrap high bit */ | |
2190 | } | |
2191 | else | |
2192 | { | |
2193 | error_message = _(": There are only 32 f registers; [0-31]"); | |
2194 | goto error; | |
2195 | } | |
2196 | } | |
2197 | } | |
2198 | else | |
2199 | { | |
2200 | break; | |
ab3e48dc | 2201 | } /* if not an 'f' register. */ |
252b5132 RH |
2202 | |
2203 | switch (*args) | |
2204 | { | |
2205 | case 'v': | |
2206 | case 'V': | |
2207 | case 'e': | |
2208 | opcode |= RS1 (mask); | |
2209 | continue; | |
2210 | ||
252b5132 RH |
2211 | case 'f': |
2212 | case 'B': | |
2213 | case 'R': | |
2214 | opcode |= RS2 (mask); | |
2215 | continue; | |
2216 | ||
2217 | case 'g': | |
2218 | case 'H': | |
2219 | case 'J': | |
2220 | opcode |= RD (mask); | |
2221 | continue; | |
ab3e48dc | 2222 | } /* Pack it in. */ |
252b5132 RH |
2223 | |
2224 | know (0); | |
2225 | break; | |
ab3e48dc | 2226 | } /* float arg */ |
252b5132 RH |
2227 | |
2228 | case 'F': | |
2229 | if (strncmp (s, "%fsr", 4) == 0) | |
2230 | { | |
2231 | s += 4; | |
2232 | continue; | |
2233 | } | |
2234 | break; | |
2235 | ||
ab3e48dc KH |
2236 | case '0': /* 64 bit immediate (set, setsw, setx insn) */ |
2237 | the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ | |
252b5132 RH |
2238 | goto immediate; |
2239 | ||
ab3e48dc | 2240 | case 'l': /* 22 bit PC relative immediate */ |
252b5132 RH |
2241 | the_insn.reloc = BFD_RELOC_SPARC_WDISP22; |
2242 | the_insn.pcrel = 1; | |
2243 | goto immediate; | |
2244 | ||
ab3e48dc | 2245 | case 'L': /* 30 bit immediate */ |
252b5132 RH |
2246 | the_insn.reloc = BFD_RELOC_32_PCREL_S2; |
2247 | the_insn.pcrel = 1; | |
2248 | goto immediate; | |
2249 | ||
63fab58c | 2250 | case 'h': |
ab3e48dc | 2251 | case 'n': /* 22 bit immediate */ |
252b5132 RH |
2252 | the_insn.reloc = BFD_RELOC_SPARC22; |
2253 | goto immediate; | |
2254 | ||
ab3e48dc | 2255 | case 'i': /* 13 bit immediate */ |
252b5132 RH |
2256 | the_insn.reloc = BFD_RELOC_SPARC13; |
2257 | ||
2258 | /* fallthrough */ | |
2259 | ||
2260 | immediate: | |
2261 | if (*s == ' ') | |
2262 | s++; | |
2263 | ||
cf9a1301 RH |
2264 | { |
2265 | char *s1; | |
2266 | char *op_arg = NULL; | |
30eb9c17 | 2267 | static expressionS op_exp; |
cf9a1301 RH |
2268 | bfd_reloc_code_real_type old_reloc = the_insn.reloc; |
2269 | ||
2270 | /* Check for %hi, etc. */ | |
2271 | if (*s == '%') | |
2272 | { | |
2273 | static const struct ops { | |
2274 | /* The name as it appears in assembler. */ | |
2275 | char *name; | |
2276 | /* strlen (name), precomputed for speed */ | |
2277 | int len; | |
2278 | /* The reloc this pseudo-op translates to. */ | |
2279 | int reloc; | |
2280 | /* Non-zero if for v9 only. */ | |
2281 | int v9_p; | |
2282 | /* Non-zero if can be used in pc-relative contexts. */ | |
2283 | int pcrel_p;/*FIXME:wip*/ | |
2284 | } ops[] = { | |
2285 | /* hix/lox must appear before hi/lo so %hix won't be | |
2286 | mistaken for %hi. */ | |
2287 | { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, | |
2288 | { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, | |
2289 | { "hi", 2, BFD_RELOC_HI22, 0, 1 }, | |
2290 | { "lo", 2, BFD_RELOC_LO10, 0, 1 }, | |
14865d76 DM |
2291 | { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 }, |
2292 | { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 }, | |
cf9a1301 RH |
2293 | { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, |
2294 | { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, | |
2295 | { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, | |
2296 | { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, | |
2297 | { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, | |
2298 | { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, | |
2299 | { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, | |
2300 | { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, | |
b9734f35 JJ |
2301 | { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 }, |
2302 | { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 }, | |
2303 | { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 }, | |
2304 | { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 }, | |
2305 | { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0, | |
2306 | 0 }, | |
2307 | { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0, | |
2308 | 0 }, | |
2309 | { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 }, | |
2310 | { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 }, | |
2311 | { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 }, | |
2312 | { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 }, | |
739f7f82 DM |
2313 | { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22, |
2314 | 0, 0 }, | |
2315 | { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10, | |
2316 | 0, 0 }, | |
c2158c24 | 2317 | { NULL, 0, 0, 0, 0 } |
cf9a1301 RH |
2318 | }; |
2319 | const struct ops *o; | |
e0c6ed95 | 2320 | |
cf9a1301 RH |
2321 | for (o = ops; o->name; o++) |
2322 | if (strncmp (s + 1, o->name, o->len) == 0) | |
2323 | break; | |
2324 | if (o->name == NULL) | |
252b5132 | 2325 | break; |
e0c6ed95 | 2326 | |
cf9a1301 RH |
2327 | if (s[o->len + 1] != '(') |
2328 | { | |
2329 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); | |
a22b281c | 2330 | return special_case; |
cf9a1301 | 2331 | } |
252b5132 | 2332 | |
cf9a1301 RH |
2333 | op_arg = o->name; |
2334 | the_insn.reloc = o->reloc; | |
2335 | s += o->len + 2; | |
2336 | v9_arg_p = o->v9_p; | |
2337 | } | |
2338 | ||
2339 | /* Note that if the get_expression() fails, we will still | |
2340 | have created U entries in the symbol table for the | |
2341 | 'symbols' in the input string. Try not to create U | |
2342 | symbols for registers, etc. */ | |
252b5132 | 2343 | |
252b5132 RH |
2344 | /* This stuff checks to see if the expression ends in |
2345 | +%reg. If it does, it removes the register from | |
2346 | the expression, and re-sets 's' to point to the | |
2347 | right place. */ | |
2348 | ||
cf9a1301 RH |
2349 | if (op_arg) |
2350 | { | |
2351 | int npar = 0; | |
2352 | ||
2353 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) | |
2354 | if (*s1 == '(') | |
2355 | npar++; | |
2356 | else if (*s1 == ')') | |
2357 | { | |
2358 | if (!npar) | |
2359 | break; | |
2360 | npar--; | |
2361 | } | |
2362 | ||
2363 | if (*s1 != ')') | |
2364 | { | |
2365 | as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); | |
a22b281c | 2366 | return special_case; |
cf9a1301 | 2367 | } |
e0c6ed95 | 2368 | |
cf9a1301 RH |
2369 | *s1 = '\0'; |
2370 | (void) get_expression (s); | |
2371 | *s1 = ')'; | |
2372 | s = s1 + 1; | |
2373 | if (*s == ',' || *s == ']' || !*s) | |
2374 | continue; | |
2375 | if (*s != '+' && *s != '-') | |
2376 | { | |
2377 | as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); | |
a22b281c | 2378 | return special_case; |
cf9a1301 RH |
2379 | } |
2380 | *s1 = '0'; | |
2381 | s = s1; | |
2382 | op_exp = the_insn.exp; | |
e0c6ed95 | 2383 | memset (&the_insn.exp, 0, sizeof (the_insn.exp)); |
cf9a1301 | 2384 | } |
252b5132 | 2385 | |
e0c6ed95 AM |
2386 | for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) |
2387 | ; | |
252b5132 | 2388 | |
3882b010 | 2389 | if (s1 != s && ISDIGIT (s1[-1])) |
252b5132 RH |
2390 | { |
2391 | if (s1[-2] == '%' && s1[-3] == '+') | |
cf9a1301 RH |
2392 | s1 -= 3; |
2393 | else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') | |
2394 | s1 -= 4; | |
2395 | else | |
2396 | s1 = NULL; | |
2397 | if (s1) | |
252b5132 | 2398 | { |
252b5132 | 2399 | *s1 = '\0'; |
1eb7027c RH |
2400 | if (op_arg && s1 == s + 1) |
2401 | the_insn.exp.X_op = O_absent; | |
2402 | else | |
2403 | (void) get_expression (s); | |
252b5132 | 2404 | *s1 = '+'; |
cf9a1301 RH |
2405 | if (op_arg) |
2406 | *s = ')'; | |
252b5132 | 2407 | s = s1; |
252b5132 | 2408 | } |
cf9a1301 RH |
2409 | } |
2410 | else | |
2411 | s1 = NULL; | |
2412 | ||
2413 | if (!s1) | |
2414 | { | |
2415 | (void) get_expression (s); | |
2416 | if (op_arg) | |
2417 | *s = ')'; | |
2418 | s = expr_end; | |
2419 | } | |
2420 | ||
2421 | if (op_arg) | |
2422 | { | |
2423 | the_insn.exp2 = the_insn.exp; | |
2424 | the_insn.exp = op_exp; | |
2425 | if (the_insn.exp2.X_op == O_absent) | |
2426 | the_insn.exp2.X_op = O_illegal; | |
2427 | else if (the_insn.exp.X_op == O_absent) | |
252b5132 | 2428 | { |
cf9a1301 RH |
2429 | the_insn.exp = the_insn.exp2; |
2430 | the_insn.exp2.X_op = O_illegal; | |
2431 | } | |
2432 | else if (the_insn.exp.X_op == O_constant) | |
2433 | { | |
2434 | valueT val = the_insn.exp.X_add_number; | |
2435 | switch (the_insn.reloc) | |
2436 | { | |
1b50c718 ILT |
2437 | default: |
2438 | break; | |
2439 | ||
cf9a1301 RH |
2440 | case BFD_RELOC_SPARC_HH22: |
2441 | val = BSR (val, 32); | |
e0c6ed95 | 2442 | /* Fall through. */ |
cf9a1301 RH |
2443 | |
2444 | case BFD_RELOC_SPARC_LM22: | |
2445 | case BFD_RELOC_HI22: | |
2446 | val = (val >> 10) & 0x3fffff; | |
2447 | break; | |
2448 | ||
2449 | case BFD_RELOC_SPARC_HM10: | |
2450 | val = BSR (val, 32); | |
e0c6ed95 | 2451 | /* Fall through. */ |
cf9a1301 RH |
2452 | |
2453 | case BFD_RELOC_LO10: | |
2454 | val &= 0x3ff; | |
2455 | break; | |
2456 | ||
2457 | case BFD_RELOC_SPARC_H44: | |
2458 | val >>= 22; | |
2459 | val &= 0x3fffff; | |
2460 | break; | |
2461 | ||
2462 | case BFD_RELOC_SPARC_M44: | |
2463 | val >>= 12; | |
2464 | val &= 0x3ff; | |
2465 | break; | |
2466 | ||
2467 | case BFD_RELOC_SPARC_L44: | |
2468 | val &= 0xfff; | |
2469 | break; | |
2470 | ||
2471 | case BFD_RELOC_SPARC_HIX22: | |
ab3e48dc | 2472 | val = ~val; |
cf9a1301 RH |
2473 | val = (val >> 10) & 0x3fffff; |
2474 | break; | |
2475 | ||
2476 | case BFD_RELOC_SPARC_LOX10: | |
2477 | val = (val & 0x3ff) | 0x1c00; | |
2478 | break; | |
2479 | } | |
2480 | the_insn.exp = the_insn.exp2; | |
2481 | the_insn.exp.X_add_number += val; | |
2482 | the_insn.exp2.X_op = O_illegal; | |
2483 | the_insn.reloc = old_reloc; | |
2484 | } | |
2485 | else if (the_insn.exp2.X_op != O_constant) | |
2486 | { | |
2487 | as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); | |
a22b281c | 2488 | return special_case; |
cf9a1301 RH |
2489 | } |
2490 | else | |
2491 | { | |
dabe3bbc | 2492 | if (old_reloc != BFD_RELOC_SPARC13 |
cf9a1301 RH |
2493 | || the_insn.reloc != BFD_RELOC_LO10 |
2494 | || sparc_arch_size != 64 | |
2495 | || sparc_pic_code) | |
2496 | { | |
2497 | as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); | |
a22b281c | 2498 | return special_case; |
cf9a1301 RH |
2499 | } |
2500 | the_insn.reloc = BFD_RELOC_SPARC_OLO10; | |
252b5132 RH |
2501 | } |
2502 | } | |
2503 | } | |
252b5132 RH |
2504 | /* Check for constants that don't require emitting a reloc. */ |
2505 | if (the_insn.exp.X_op == O_constant | |
2506 | && the_insn.exp.X_add_symbol == 0 | |
2507 | && the_insn.exp.X_op_symbol == 0) | |
2508 | { | |
2509 | /* For pc-relative call instructions, we reject | |
2510 | constants to get better code. */ | |
2511 | if (the_insn.pcrel | |
2512 | && the_insn.reloc == BFD_RELOC_32_PCREL_S2 | |
2513 | && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) | |
2514 | { | |
2515 | error_message = _(": PC-relative operand can't be a constant"); | |
2516 | goto error; | |
2517 | } | |
2518 | ||
b9734f35 JJ |
2519 | if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 |
2520 | && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) | |
2521 | { | |
2522 | error_message = _(": TLS operand can't be a constant"); | |
2523 | goto error; | |
2524 | } | |
2525 | ||
55cf6793 | 2526 | /* Constants that won't fit are checked in md_apply_fix |
252b5132 RH |
2527 | and bfd_install_relocation. |
2528 | ??? It would be preferable to install the constants | |
2529 | into the insn here and save having to create a fixS | |
2530 | for each one. There already exists code to handle | |
55cf6793 | 2531 | all the various cases (e.g. in md_apply_fix and |
252b5132 RH |
2532 | bfd_install_relocation) so duplicating all that code |
2533 | here isn't right. */ | |
2534 | } | |
2535 | ||
2536 | continue; | |
2537 | ||
2538 | case 'a': | |
2539 | if (*s++ == 'a') | |
2540 | { | |
2541 | opcode |= ANNUL; | |
2542 | continue; | |
2543 | } | |
2544 | break; | |
2545 | ||
2546 | case 'A': | |
2547 | { | |
2548 | int asi = 0; | |
2549 | ||
2550 | /* Parse an asi. */ | |
2551 | if (*s == '#') | |
2552 | { | |
2553 | if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) | |
2554 | { | |
2555 | error_message = _(": invalid ASI name"); | |
2556 | goto error; | |
2557 | } | |
2558 | } | |
2559 | else | |
2560 | { | |
2561 | if (! parse_const_expr_arg (&s, &asi)) | |
2562 | { | |
2563 | error_message = _(": invalid ASI expression"); | |
2564 | goto error; | |
2565 | } | |
2566 | if (asi < 0 || asi > 255) | |
2567 | { | |
2568 | error_message = _(": invalid ASI number"); | |
2569 | goto error; | |
2570 | } | |
2571 | } | |
2572 | opcode |= ASI (asi); | |
2573 | continue; | |
e0c6ed95 | 2574 | } /* Alternate space. */ |
252b5132 RH |
2575 | |
2576 | case 'p': | |
2577 | if (strncmp (s, "%psr", 4) == 0) | |
2578 | { | |
2579 | s += 4; | |
2580 | continue; | |
2581 | } | |
2582 | break; | |
2583 | ||
e0c6ed95 | 2584 | case 'q': /* Floating point queue. */ |
252b5132 RH |
2585 | if (strncmp (s, "%fq", 3) == 0) |
2586 | { | |
2587 | s += 3; | |
2588 | continue; | |
2589 | } | |
2590 | break; | |
2591 | ||
e0c6ed95 | 2592 | case 'Q': /* Coprocessor queue. */ |
252b5132 RH |
2593 | if (strncmp (s, "%cq", 3) == 0) |
2594 | { | |
2595 | s += 3; | |
2596 | continue; | |
2597 | } | |
2598 | break; | |
2599 | ||
2600 | case 'S': | |
2601 | if (strcmp (str, "set") == 0 | |
2602 | || strcmp (str, "setuw") == 0) | |
2603 | { | |
2604 | special_case = SPECIAL_CASE_SET; | |
2605 | continue; | |
2606 | } | |
2607 | else if (strcmp (str, "setsw") == 0) | |
2608 | { | |
2609 | special_case = SPECIAL_CASE_SETSW; | |
2610 | continue; | |
2611 | } | |
2612 | else if (strcmp (str, "setx") == 0) | |
2613 | { | |
2614 | special_case = SPECIAL_CASE_SETX; | |
2615 | continue; | |
2616 | } | |
2617 | else if (strncmp (str, "fdiv", 4) == 0) | |
2618 | { | |
2619 | special_case = SPECIAL_CASE_FDIV; | |
2620 | continue; | |
2621 | } | |
2622 | break; | |
2623 | ||
2624 | case 'o': | |
2625 | if (strncmp (s, "%asi", 4) != 0) | |
2626 | break; | |
2627 | s += 4; | |
2628 | continue; | |
2629 | ||
2630 | case 's': | |
2631 | if (strncmp (s, "%fprs", 5) != 0) | |
2632 | break; | |
2633 | s += 5; | |
2634 | continue; | |
2635 | ||
2636 | case 'E': | |
2637 | if (strncmp (s, "%ccr", 4) != 0) | |
2638 | break; | |
2639 | s += 4; | |
2640 | continue; | |
2641 | ||
2642 | case 't': | |
2643 | if (strncmp (s, "%tbr", 4) != 0) | |
2644 | break; | |
2645 | s += 4; | |
2646 | continue; | |
2647 | ||
2648 | case 'w': | |
2649 | if (strncmp (s, "%wim", 4) != 0) | |
2650 | break; | |
2651 | s += 4; | |
2652 | continue; | |
2653 | ||
2654 | case 'x': | |
2655 | { | |
2656 | char *push = input_line_pointer; | |
2657 | expressionS e; | |
2658 | ||
2659 | input_line_pointer = s; | |
2660 | expression (&e); | |
2661 | if (e.X_op == O_constant) | |
2662 | { | |
2663 | int n = e.X_add_number; | |
2664 | if (n != e.X_add_number || (n & ~0x1ff) != 0) | |
2665 | as_bad (_("OPF immediate operand out of range (0-0x1ff)")); | |
2666 | else | |
2667 | opcode |= e.X_add_number << 5; | |
2668 | } | |
2669 | else | |
2670 | as_bad (_("non-immediate OPF operand, ignored")); | |
2671 | s = input_line_pointer; | |
2672 | input_line_pointer = push; | |
2673 | continue; | |
2674 | } | |
2675 | ||
2676 | case 'y': | |
2677 | if (strncmp (s, "%y", 2) != 0) | |
2678 | break; | |
2679 | s += 2; | |
2680 | continue; | |
2681 | ||
2682 | case 'u': | |
2683 | case 'U': | |
2684 | { | |
2685 | /* Parse a sparclet cpreg. */ | |
2686 | int cpreg; | |
2687 | if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) | |
2688 | { | |
2689 | error_message = _(": invalid cpreg name"); | |
2690 | goto error; | |
2691 | } | |
2692 | opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); | |
2693 | continue; | |
2694 | } | |
2695 | ||
2696 | default: | |
2697 | as_fatal (_("failed sanity check.")); | |
e0c6ed95 | 2698 | } /* switch on arg code. */ |
252b5132 RH |
2699 | |
2700 | /* Break out of for() loop. */ | |
2701 | break; | |
e0c6ed95 | 2702 | } /* For each arg that we expect. */ |
252b5132 RH |
2703 | |
2704 | error: | |
2705 | if (match == 0) | |
2706 | { | |
e0c6ed95 | 2707 | /* Args don't match. */ |
252b5132 RH |
2708 | if (&insn[1] - sparc_opcodes < sparc_num_opcodes |
2709 | && (insn->name == insn[1].name | |
2710 | || !strcmp (insn->name, insn[1].name))) | |
2711 | { | |
2712 | ++insn; | |
2713 | s = argsStart; | |
2714 | continue; | |
2715 | } | |
2716 | else | |
2717 | { | |
2718 | as_bad (_("Illegal operands%s"), error_message); | |
a22b281c | 2719 | return special_case; |
252b5132 RH |
2720 | } |
2721 | } | |
2722 | else | |
2723 | { | |
e0c6ed95 | 2724 | /* We have a match. Now see if the architecture is OK. */ |
252b5132 RH |
2725 | int needed_arch_mask = insn->architecture; |
2726 | ||
2727 | if (v9_arg_p) | |
2728 | { | |
19f7b010 JJ |
2729 | needed_arch_mask &= |
2730 | ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); | |
2731 | if (! needed_arch_mask) | |
2732 | needed_arch_mask = | |
2733 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); | |
252b5132 RH |
2734 | } |
2735 | ||
e0c6ed95 AM |
2736 | if (needed_arch_mask |
2737 | & SPARC_OPCODE_SUPPORTED (current_architecture)) | |
2738 | /* OK. */ | |
2739 | ; | |
252b5132 | 2740 | /* Can we bump up the architecture? */ |
e0c6ed95 AM |
2741 | else if (needed_arch_mask |
2742 | & SPARC_OPCODE_SUPPORTED (max_architecture)) | |
252b5132 RH |
2743 | { |
2744 | enum sparc_opcode_arch_val needed_architecture = | |
2745 | sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) | |
2746 | & needed_arch_mask); | |
2747 | ||
9c2799c2 | 2748 | gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); |
252b5132 RH |
2749 | if (warn_on_bump |
2750 | && needed_architecture > warn_after_architecture) | |
2751 | { | |
2752 | as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), | |
2753 | sparc_opcode_archs[current_architecture].name, | |
2754 | sparc_opcode_archs[needed_architecture].name, | |
2755 | str); | |
2756 | warn_after_architecture = needed_architecture; | |
2757 | } | |
2758 | current_architecture = needed_architecture; | |
2759 | } | |
2760 | /* Conflict. */ | |
2761 | /* ??? This seems to be a bit fragile. What if the next entry in | |
2762 | the opcode table is the one we want and it is supported? | |
2763 | It is possible to arrange the table today so that this can't | |
2764 | happen but what about tomorrow? */ | |
2765 | else | |
2766 | { | |
e0c6ed95 | 2767 | int arch, printed_one_p = 0; |
252b5132 RH |
2768 | char *p; |
2769 | char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; | |
2770 | ||
2771 | /* Create a list of the architectures that support the insn. */ | |
e0c6ed95 | 2772 | needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); |
252b5132 RH |
2773 | p = required_archs; |
2774 | arch = sparc_ffs (needed_arch_mask); | |
2775 | while ((1 << arch) <= needed_arch_mask) | |
2776 | { | |
2777 | if ((1 << arch) & needed_arch_mask) | |
2778 | { | |
2779 | if (printed_one_p) | |
2780 | *p++ = '|'; | |
2781 | strcpy (p, sparc_opcode_archs[arch].name); | |
2782 | p += strlen (p); | |
2783 | printed_one_p = 1; | |
2784 | } | |
2785 | ++arch; | |
2786 | } | |
2787 | ||
2788 | as_bad (_("Architecture mismatch on \"%s\"."), str); | |
2789 | as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), | |
2790 | required_archs, | |
2791 | sparc_opcode_archs[max_architecture].name); | |
a22b281c | 2792 | return special_case; |
252b5132 | 2793 | } |
e0c6ed95 | 2794 | } /* If no match. */ |
252b5132 RH |
2795 | |
2796 | break; | |
e0c6ed95 | 2797 | } /* Forever looking for a match. */ |
252b5132 RH |
2798 | |
2799 | the_insn.opcode = opcode; | |
a22b281c | 2800 | return special_case; |
252b5132 RH |
2801 | } |
2802 | ||
2803 | /* Parse an argument that can be expressed as a keyword. | |
2804 | (eg: #StoreStore or %ccfr). | |
2805 | The result is a boolean indicating success. | |
2806 | If successful, INPUT_POINTER is updated. */ | |
2807 | ||
2808 | static int | |
5a49b8ac AM |
2809 | parse_keyword_arg (int (*lookup_fn) (const char *), |
2810 | char **input_pointerP, | |
2811 | int *valueP) | |
252b5132 RH |
2812 | { |
2813 | int value; | |
2814 | char c, *p, *q; | |
2815 | ||
2816 | p = *input_pointerP; | |
2817 | for (q = p + (*p == '#' || *p == '%'); | |
3882b010 | 2818 | ISALNUM (*q) || *q == '_'; |
252b5132 RH |
2819 | ++q) |
2820 | continue; | |
2821 | c = *q; | |
2822 | *q = 0; | |
2823 | value = (*lookup_fn) (p); | |
2824 | *q = c; | |
2825 | if (value == -1) | |
2826 | return 0; | |
2827 | *valueP = value; | |
2828 | *input_pointerP = q; | |
2829 | return 1; | |
2830 | } | |
2831 | ||
2832 | /* Parse an argument that is a constant expression. | |
2833 | The result is a boolean indicating success. */ | |
2834 | ||
2835 | static int | |
5a49b8ac | 2836 | parse_const_expr_arg (char **input_pointerP, int *valueP) |
252b5132 RH |
2837 | { |
2838 | char *save = input_line_pointer; | |
2839 | expressionS exp; | |
2840 | ||
2841 | input_line_pointer = *input_pointerP; | |
2842 | /* The next expression may be something other than a constant | |
2843 | (say if we're not processing the right variant of the insn). | |
2844 | Don't call expression unless we're sure it will succeed as it will | |
2845 | signal an error (which we want to defer until later). */ | |
2846 | /* FIXME: It might be better to define md_operand and have it recognize | |
2847 | things like %asi, etc. but continuing that route through to the end | |
2848 | is a lot of work. */ | |
2849 | if (*input_line_pointer == '%') | |
2850 | { | |
2851 | input_line_pointer = save; | |
2852 | return 0; | |
2853 | } | |
2854 | expression (&exp); | |
2855 | *input_pointerP = input_line_pointer; | |
2856 | input_line_pointer = save; | |
2857 | if (exp.X_op != O_constant) | |
2858 | return 0; | |
2859 | *valueP = exp.X_add_number; | |
2860 | return 1; | |
2861 | } | |
2862 | ||
2863 | /* Subroutine of sparc_ip to parse an expression. */ | |
2864 | ||
2865 | static int | |
5a49b8ac | 2866 | get_expression (char *str) |
252b5132 RH |
2867 | { |
2868 | char *save_in; | |
2869 | segT seg; | |
2870 | ||
2871 | save_in = input_line_pointer; | |
2872 | input_line_pointer = str; | |
2873 | seg = expression (&the_insn.exp); | |
2874 | if (seg != absolute_section | |
2875 | && seg != text_section | |
2876 | && seg != data_section | |
2877 | && seg != bss_section | |
2878 | && seg != undefined_section) | |
2879 | { | |
2880 | the_insn.error = _("bad segment"); | |
2881 | expr_end = input_line_pointer; | |
2882 | input_line_pointer = save_in; | |
2883 | return 1; | |
2884 | } | |
2885 | expr_end = input_line_pointer; | |
2886 | input_line_pointer = save_in; | |
2887 | return 0; | |
2888 | } | |
2889 | ||
2890 | /* Subroutine of md_assemble to output one insn. */ | |
2891 | ||
2892 | static void | |
91d6fa6a | 2893 | output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn) |
252b5132 RH |
2894 | { |
2895 | char *toP = frag_more (4); | |
2896 | ||
e0c6ed95 | 2897 | /* Put out the opcode. */ |
252b5132 | 2898 | if (INSN_BIG_ENDIAN) |
91d6fa6a | 2899 | number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 2900 | else |
91d6fa6a | 2901 | number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4); |
252b5132 | 2902 | |
e0c6ed95 | 2903 | /* Put out the symbol-dependent stuff. */ |
91d6fa6a | 2904 | if (theinsn->reloc != BFD_RELOC_NONE) |
252b5132 | 2905 | { |
e0c6ed95 AM |
2906 | fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ |
2907 | (toP - frag_now->fr_literal), /* Where. */ | |
2908 | 4, /* Size. */ | |
91d6fa6a NC |
2909 | &theinsn->exp, |
2910 | theinsn->pcrel, | |
2911 | theinsn->reloc); | |
252b5132 | 2912 | /* Turn off overflow checking in fixup_segment. We'll do our |
55cf6793 | 2913 | own overflow checking in md_apply_fix. This is necessary because |
252b5132 RH |
2914 | the insn size is 4 and fixup_segment will signal an overflow for |
2915 | large 8 byte quantities. */ | |
2916 | fixP->fx_no_overflow = 1; | |
91d6fa6a NC |
2917 | if (theinsn->reloc == BFD_RELOC_SPARC_OLO10) |
2918 | fixP->tc_fix_data = theinsn->exp2.X_add_number; | |
252b5132 RH |
2919 | } |
2920 | ||
2921 | last_insn = insn; | |
91d6fa6a | 2922 | last_opcode = theinsn->opcode; |
732d96b6 JJ |
2923 | |
2924 | #ifdef OBJ_ELF | |
2925 | dwarf2_emit_insn (4); | |
2926 | #endif | |
252b5132 RH |
2927 | } |
2928 | \f | |
252b5132 | 2929 | char * |
499ac353 | 2930 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 2931 | { |
499ac353 | 2932 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
2933 | } |
2934 | ||
2935 | /* Write a value out to the object file, using the appropriate | |
2936 | endianness. */ | |
2937 | ||
2938 | void | |
5a49b8ac | 2939 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
2940 | { |
2941 | if (target_big_endian) | |
2942 | number_to_chars_bigendian (buf, val, n); | |
2943 | else if (target_little_endian_data | |
2944 | && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) | |
e0c6ed95 AM |
2945 | /* Output debug words, which are not in allocated sections, as big |
2946 | endian. */ | |
252b5132 RH |
2947 | number_to_chars_bigendian (buf, val, n); |
2948 | else if (target_little_endian_data || ! target_big_endian) | |
2949 | number_to_chars_littleendian (buf, val, n); | |
2950 | } | |
2951 | \f | |
2952 | /* Apply a fixS to the frags, now that we know the value it ought to | |
81d4177b | 2953 | hold. */ |
252b5132 | 2954 | |
94f592af | 2955 | void |
5a49b8ac | 2956 | md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) |
252b5132 RH |
2957 | { |
2958 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
94f592af | 2959 | offsetT val = * (offsetT *) valP; |
252b5132 RH |
2960 | long insn; |
2961 | ||
9c2799c2 | 2962 | gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); |
252b5132 | 2963 | |
e0c6ed95 | 2964 | fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ |
252b5132 RH |
2965 | |
2966 | #ifdef OBJ_ELF | |
a161fe53 | 2967 | /* SPARC ELF relocations don't use an addend in the data field. */ |
252b5132 | 2968 | if (fixP->fx_addsy != NULL) |
7c1d0959 L |
2969 | { |
2970 | switch (fixP->fx_r_type) | |
2971 | { | |
2972 | case BFD_RELOC_SPARC_TLS_GD_HI22: | |
2973 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
2974 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
2975 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
2976 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
2977 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
2978 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
2979 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
2980 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
2981 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
2982 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
2983 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
2984 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
2985 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
2986 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
2987 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
2988 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
2989 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
2990 | case BFD_RELOC_SPARC_TLS_DTPMOD32: | |
2991 | case BFD_RELOC_SPARC_TLS_DTPMOD64: | |
2992 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
2993 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
2994 | case BFD_RELOC_SPARC_TLS_TPOFF32: | |
2995 | case BFD_RELOC_SPARC_TLS_TPOFF64: | |
2996 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
2997 | ||
2998 | default: | |
2999 | break; | |
3000 | } | |
3001 | ||
3002 | return; | |
3003 | } | |
252b5132 RH |
3004 | #endif |
3005 | ||
3006 | /* This is a hack. There should be a better way to | |
3007 | handle this. Probably in terms of howto fields, once | |
3008 | we can look at these fixups in terms of howtos. */ | |
3009 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) | |
3010 | val += fixP->fx_where + fixP->fx_frag->fr_address; | |
3011 | ||
3012 | #ifdef OBJ_AOUT | |
3013 | /* FIXME: More ridiculous gas reloc hacking. If we are going to | |
3014 | generate a reloc, then we just want to let the reloc addend set | |
3015 | the value. We do not want to also stuff the addend into the | |
3016 | object file. Including the addend in the object file works when | |
3017 | doing a static link, because the linker will ignore the object | |
3018 | file contents. However, the dynamic linker does not ignore the | |
3019 | object file contents. */ | |
3020 | if (fixP->fx_addsy != NULL | |
3021 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) | |
3022 | val = 0; | |
3023 | ||
3024 | /* When generating PIC code, we do not want an addend for a reloc | |
3025 | against a local symbol. We adjust fx_addnumber to cancel out the | |
3026 | value already included in val, and to also cancel out the | |
3027 | adjustment which bfd_install_relocation will create. */ | |
3028 | if (sparc_pic_code | |
3029 | && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 | |
3030 | && fixP->fx_addsy != NULL | |
3031 | && ! S_IS_COMMON (fixP->fx_addsy) | |
49309057 | 3032 | && symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3033 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); |
3034 | ||
3035 | /* When generating PIC code, we need to fiddle to get | |
3036 | bfd_install_relocation to do the right thing for a PC relative | |
3037 | reloc against a local symbol which we are going to keep. */ | |
3038 | if (sparc_pic_code | |
3039 | && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3040 | && fixP->fx_addsy != NULL | |
3041 | && (S_IS_EXTERNAL (fixP->fx_addsy) | |
3042 | || S_IS_WEAK (fixP->fx_addsy)) | |
3043 | && S_IS_DEFINED (fixP->fx_addsy) | |
3044 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
3045 | { | |
3046 | val = 0; | |
3047 | fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); | |
3048 | } | |
3049 | #endif | |
3050 | ||
3051 | /* If this is a data relocation, just output VAL. */ | |
3052 | ||
0f2712ed NC |
3053 | if (fixP->fx_r_type == BFD_RELOC_16 |
3054 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) | |
252b5132 RH |
3055 | { |
3056 | md_number_to_chars (buf, val, 2); | |
3057 | } | |
3058 | else if (fixP->fx_r_type == BFD_RELOC_32 | |
0f2712ed | 3059 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 |
252b5132 RH |
3060 | || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) |
3061 | { | |
3062 | md_number_to_chars (buf, val, 4); | |
3063 | } | |
0f2712ed NC |
3064 | else if (fixP->fx_r_type == BFD_RELOC_64 |
3065 | || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) | |
252b5132 RH |
3066 | { |
3067 | md_number_to_chars (buf, val, 8); | |
3068 | } | |
e0c6ed95 | 3069 | else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
252b5132 RH |
3070 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
3071 | { | |
3072 | fixP->fx_done = 0; | |
94f592af | 3073 | return; |
252b5132 RH |
3074 | } |
3075 | else | |
3076 | { | |
3077 | /* It's a relocation against an instruction. */ | |
3078 | ||
3079 | if (INSN_BIG_ENDIAN) | |
3080 | insn = bfd_getb32 ((unsigned char *) buf); | |
3081 | else | |
3082 | insn = bfd_getl32 ((unsigned char *) buf); | |
e0c6ed95 | 3083 | |
252b5132 RH |
3084 | switch (fixP->fx_r_type) |
3085 | { | |
3086 | case BFD_RELOC_32_PCREL_S2: | |
3087 | val = val >> 2; | |
3088 | /* FIXME: This increment-by-one deserves a comment of why it's | |
3089 | being done! */ | |
3090 | if (! sparc_pic_code | |
3091 | || fixP->fx_addsy == NULL | |
49309057 | 3092 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 | 3093 | ++val; |
6faf3d66 | 3094 | |
252b5132 | 3095 | insn |= val & 0x3fffffff; |
6faf3d66 | 3096 | |
e0c6ed95 | 3097 | /* See if we have a delay slot. */ |
6faf3d66 JJ |
3098 | if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) |
3099 | { | |
3100 | #define G0 0 | |
3101 | #define O7 15 | |
3102 | #define XCC (2 << 20) | |
3103 | #define COND(x) (((x)&0xf)<<25) | |
3104 | #define CONDA COND(0x8) | |
3105 | #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) | |
3106 | #define INSN_BA (F2(0,2) | CONDA) | |
3107 | #define INSN_OR F3(2, 0x2, 0) | |
3108 | #define INSN_NOP F2(0,4) | |
3109 | ||
3110 | long delay; | |
3111 | ||
3112 | /* If the instruction is a call with either: | |
3113 | restore | |
3114 | arithmetic instruction with rd == %o7 | |
3115 | where rs1 != %o7 and rs2 if it is register != %o7 | |
3116 | then we can optimize if the call destination is near | |
3117 | by changing the call into a branch always. */ | |
3118 | if (INSN_BIG_ENDIAN) | |
3119 | delay = bfd_getb32 ((unsigned char *) buf + 4); | |
3120 | else | |
3121 | delay = bfd_getl32 ((unsigned char *) buf + 4); | |
e0c6ed95 | 3122 | if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) |
6faf3d66 | 3123 | break; |
e0c6ed95 AM |
3124 | if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ |
3125 | && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ | |
3126 | || ((delay & RD (~0)) != RD (O7)))) | |
6faf3d66 | 3127 | break; |
e0c6ed95 AM |
3128 | if ((delay & RS1 (~0)) == RS1 (O7) |
3129 | || ((delay & F3I (~0)) == 0 | |
3130 | && (delay & RS2 (~0)) == RS2 (O7))) | |
6faf3d66 JJ |
3131 | break; |
3132 | /* Ensure the branch will fit into simm22. */ | |
3133 | if ((val & 0x3fe00000) | |
3134 | && (val & 0x3fe00000) != 0x3fe00000) | |
3135 | break; | |
3136 | /* Check if the arch is v9 and branch will fit | |
3137 | into simm19. */ | |
3138 | if (((val & 0x3c0000) == 0 | |
3139 | || (val & 0x3c0000) == 0x3c0000) | |
3140 | && (sparc_arch_size == 64 | |
3141 | || current_architecture >= SPARC_OPCODE_ARCH_V9)) | |
e0c6ed95 | 3142 | /* ba,pt %xcc */ |
6faf3d66 JJ |
3143 | insn = INSN_BPA | (val & 0x7ffff); |
3144 | else | |
e0c6ed95 | 3145 | /* ba */ |
6faf3d66 JJ |
3146 | insn = INSN_BA | (val & 0x3fffff); |
3147 | if (fixP->fx_where >= 4 | |
e0c6ed95 AM |
3148 | && ((delay & (0xffffffff ^ RS1 (~0))) |
3149 | == (INSN_OR | RD (O7) | RS2 (G0)))) | |
6faf3d66 JJ |
3150 | { |
3151 | long setter; | |
3152 | int reg; | |
3153 | ||
3154 | if (INSN_BIG_ENDIAN) | |
3155 | setter = bfd_getb32 ((unsigned char *) buf - 4); | |
3156 | else | |
3157 | setter = bfd_getl32 ((unsigned char *) buf - 4); | |
e0c6ed95 | 3158 | if ((setter & (0xffffffff ^ RD (~0))) |
ab3e48dc | 3159 | != (INSN_OR | RS1 (O7) | RS2 (G0))) |
6faf3d66 JJ |
3160 | break; |
3161 | /* The sequence was | |
3162 | or %o7, %g0, %rN | |
3163 | call foo | |
3164 | or %rN, %g0, %o7 | |
3165 | ||
3166 | If call foo was replaced with ba, replace | |
3167 | or %rN, %g0, %o7 with nop. */ | |
e0c6ed95 AM |
3168 | reg = (delay & RS1 (~0)) >> 14; |
3169 | if (reg != ((setter & RD (~0)) >> 25) | |
6faf3d66 JJ |
3170 | || reg == G0 || reg == O7) |
3171 | break; | |
3172 | ||
3173 | if (INSN_BIG_ENDIAN) | |
3174 | bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); | |
3175 | else | |
3176 | bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); | |
3177 | } | |
3178 | } | |
252b5132 RH |
3179 | break; |
3180 | ||
3181 | case BFD_RELOC_SPARC_11: | |
3182 | if (! in_signed_range (val, 0x7ff)) | |
3183 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3184 | _("relocation overflow")); | |
3185 | insn |= val & 0x7ff; | |
3186 | break; | |
3187 | ||
3188 | case BFD_RELOC_SPARC_10: | |
3189 | if (! in_signed_range (val, 0x3ff)) | |
3190 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3191 | _("relocation overflow")); | |
3192 | insn |= val & 0x3ff; | |
3193 | break; | |
3194 | ||
3195 | case BFD_RELOC_SPARC_7: | |
3196 | if (! in_bitfield_range (val, 0x7f)) | |
3197 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3198 | _("relocation overflow")); | |
3199 | insn |= val & 0x7f; | |
3200 | break; | |
3201 | ||
3202 | case BFD_RELOC_SPARC_6: | |
3203 | if (! in_bitfield_range (val, 0x3f)) | |
3204 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3205 | _("relocation overflow")); | |
3206 | insn |= val & 0x3f; | |
3207 | break; | |
3208 | ||
3209 | case BFD_RELOC_SPARC_5: | |
3210 | if (! in_bitfield_range (val, 0x1f)) | |
3211 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3212 | _("relocation overflow")); | |
3213 | insn |= val & 0x1f; | |
3214 | break; | |
3215 | ||
3216 | case BFD_RELOC_SPARC_WDISP16: | |
c699f087 JJ |
3217 | if ((val & 3) |
3218 | || val >= 0x1fffc | |
3219 | || val <= -(offsetT) 0x20008) | |
252b5132 RH |
3220 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3221 | _("relocation overflow")); | |
3222 | /* FIXME: The +1 deserves a comment. */ | |
3223 | val = (val >> 2) + 1; | |
3224 | insn |= ((val & 0xc000) << 6) | (val & 0x3fff); | |
3225 | break; | |
3226 | ||
3227 | case BFD_RELOC_SPARC_WDISP19: | |
c699f087 JJ |
3228 | if ((val & 3) |
3229 | || val >= 0xffffc | |
3230 | || val <= -(offsetT) 0x100008) | |
252b5132 RH |
3231 | as_bad_where (fixP->fx_file, fixP->fx_line, |
3232 | _("relocation overflow")); | |
3233 | /* FIXME: The +1 deserves a comment. */ | |
3234 | val = (val >> 2) + 1; | |
3235 | insn |= val & 0x7ffff; | |
3236 | break; | |
3237 | ||
3238 | case BFD_RELOC_SPARC_HH22: | |
3239 | val = BSR (val, 32); | |
e0c6ed95 | 3240 | /* Fall through. */ |
252b5132 RH |
3241 | |
3242 | case BFD_RELOC_SPARC_LM22: | |
3243 | case BFD_RELOC_HI22: | |
3244 | if (!fixP->fx_addsy) | |
94f592af | 3245 | insn |= (val >> 10) & 0x3fffff; |
252b5132 | 3246 | else |
94f592af NC |
3247 | /* FIXME: Need comment explaining why we do this. */ |
3248 | insn &= ~0xffff; | |
252b5132 RH |
3249 | break; |
3250 | ||
3251 | case BFD_RELOC_SPARC22: | |
3252 | if (val & ~0x003fffff) | |
3253 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3254 | _("relocation overflow")); | |
3255 | insn |= (val & 0x3fffff); | |
3256 | break; | |
3257 | ||
3258 | case BFD_RELOC_SPARC_HM10: | |
3259 | val = BSR (val, 32); | |
e0c6ed95 | 3260 | /* Fall through. */ |
252b5132 RH |
3261 | |
3262 | case BFD_RELOC_LO10: | |
3263 | if (!fixP->fx_addsy) | |
94f592af | 3264 | insn |= val & 0x3ff; |
252b5132 | 3265 | else |
94f592af NC |
3266 | /* FIXME: Need comment explaining why we do this. */ |
3267 | insn &= ~0xff; | |
252b5132 RH |
3268 | break; |
3269 | ||
dabe3bbc RH |
3270 | case BFD_RELOC_SPARC_OLO10: |
3271 | val &= 0x3ff; | |
3272 | val += fixP->tc_fix_data; | |
e0c6ed95 | 3273 | /* Fall through. */ |
dabe3bbc | 3274 | |
252b5132 RH |
3275 | case BFD_RELOC_SPARC13: |
3276 | if (! in_signed_range (val, 0x1fff)) | |
3277 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3278 | _("relocation overflow")); | |
3279 | insn |= val & 0x1fff; | |
3280 | break; | |
3281 | ||
3282 | case BFD_RELOC_SPARC_WDISP22: | |
3283 | val = (val >> 2) + 1; | |
e0c6ed95 | 3284 | /* Fall through. */ |
252b5132 RH |
3285 | case BFD_RELOC_SPARC_BASE22: |
3286 | insn |= val & 0x3fffff; | |
3287 | break; | |
3288 | ||
3289 | case BFD_RELOC_SPARC_H44: | |
3290 | if (!fixP->fx_addsy) | |
3291 | { | |
3292 | bfd_vma tval = val; | |
3293 | tval >>= 22; | |
3294 | insn |= tval & 0x3fffff; | |
3295 | } | |
3296 | break; | |
3297 | ||
3298 | case BFD_RELOC_SPARC_M44: | |
3299 | if (!fixP->fx_addsy) | |
3300 | insn |= (val >> 12) & 0x3ff; | |
3301 | break; | |
3302 | ||
3303 | case BFD_RELOC_SPARC_L44: | |
3304 | if (!fixP->fx_addsy) | |
3305 | insn |= val & 0xfff; | |
3306 | break; | |
3307 | ||
3308 | case BFD_RELOC_SPARC_HIX22: | |
3309 | if (!fixP->fx_addsy) | |
3310 | { | |
ab3e48dc | 3311 | val ^= ~(offsetT) 0; |
252b5132 RH |
3312 | insn |= (val >> 10) & 0x3fffff; |
3313 | } | |
3314 | break; | |
3315 | ||
3316 | case BFD_RELOC_SPARC_LOX10: | |
3317 | if (!fixP->fx_addsy) | |
3318 | insn |= 0x1c00 | (val & 0x3ff); | |
3319 | break; | |
3320 | ||
3321 | case BFD_RELOC_NONE: | |
3322 | default: | |
3323 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3324 | _("bad or unhandled relocation type: 0x%02x"), | |
3325 | fixP->fx_r_type); | |
3326 | break; | |
3327 | } | |
3328 | ||
3329 | if (INSN_BIG_ENDIAN) | |
3330 | bfd_putb32 (insn, (unsigned char *) buf); | |
3331 | else | |
3332 | bfd_putl32 (insn, (unsigned char *) buf); | |
3333 | } | |
3334 | ||
3335 | /* Are we finished with this relocation now? */ | |
3336 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) | |
3337 | fixP->fx_done = 1; | |
252b5132 RH |
3338 | } |
3339 | ||
3340 | /* Translate internal representation of relocation info to BFD target | |
3341 | format. */ | |
e0c6ed95 | 3342 | |
dabe3bbc | 3343 | arelent ** |
5a49b8ac | 3344 | tc_gen_reloc (asection *section, fixS *fixp) |
252b5132 | 3345 | { |
dabe3bbc | 3346 | static arelent *relocs[3]; |
252b5132 RH |
3347 | arelent *reloc; |
3348 | bfd_reloc_code_real_type code; | |
3349 | ||
dabe3bbc RH |
3350 | relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); |
3351 | relocs[1] = NULL; | |
252b5132 | 3352 | |
49309057 ILT |
3353 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
3354 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
3355 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3356 | ||
3357 | switch (fixp->fx_r_type) | |
3358 | { | |
3359 | case BFD_RELOC_16: | |
3360 | case BFD_RELOC_32: | |
3361 | case BFD_RELOC_HI22: | |
3362 | case BFD_RELOC_LO10: | |
3363 | case BFD_RELOC_32_PCREL_S2: | |
3364 | case BFD_RELOC_SPARC13: | |
63fab58c | 3365 | case BFD_RELOC_SPARC22: |
1a6b486f DM |
3366 | case BFD_RELOC_SPARC_PC22: |
3367 | case BFD_RELOC_SPARC_PC10: | |
252b5132 RH |
3368 | case BFD_RELOC_SPARC_BASE13: |
3369 | case BFD_RELOC_SPARC_WDISP16: | |
3370 | case BFD_RELOC_SPARC_WDISP19: | |
3371 | case BFD_RELOC_SPARC_WDISP22: | |
3372 | case BFD_RELOC_64: | |
3373 | case BFD_RELOC_SPARC_5: | |
3374 | case BFD_RELOC_SPARC_6: | |
3375 | case BFD_RELOC_SPARC_7: | |
3376 | case BFD_RELOC_SPARC_10: | |
3377 | case BFD_RELOC_SPARC_11: | |
3378 | case BFD_RELOC_SPARC_HH22: | |
3379 | case BFD_RELOC_SPARC_HM10: | |
3380 | case BFD_RELOC_SPARC_LM22: | |
3381 | case BFD_RELOC_SPARC_PC_HH22: | |
3382 | case BFD_RELOC_SPARC_PC_HM10: | |
3383 | case BFD_RELOC_SPARC_PC_LM22: | |
3384 | case BFD_RELOC_SPARC_H44: | |
3385 | case BFD_RELOC_SPARC_M44: | |
3386 | case BFD_RELOC_SPARC_L44: | |
3387 | case BFD_RELOC_SPARC_HIX22: | |
3388 | case BFD_RELOC_SPARC_LOX10: | |
3389 | case BFD_RELOC_SPARC_REV32: | |
dabe3bbc | 3390 | case BFD_RELOC_SPARC_OLO10: |
0f2712ed NC |
3391 | case BFD_RELOC_SPARC_UA16: |
3392 | case BFD_RELOC_SPARC_UA32: | |
3393 | case BFD_RELOC_SPARC_UA64: | |
bd5e6e7e JJ |
3394 | case BFD_RELOC_8_PCREL: |
3395 | case BFD_RELOC_16_PCREL: | |
3396 | case BFD_RELOC_32_PCREL: | |
3397 | case BFD_RELOC_64_PCREL: | |
3398 | case BFD_RELOC_SPARC_PLT32: | |
3399 | case BFD_RELOC_SPARC_PLT64: | |
252b5132 RH |
3400 | case BFD_RELOC_VTABLE_ENTRY: |
3401 | case BFD_RELOC_VTABLE_INHERIT: | |
b9734f35 JJ |
3402 | case BFD_RELOC_SPARC_TLS_GD_HI22: |
3403 | case BFD_RELOC_SPARC_TLS_GD_LO10: | |
3404 | case BFD_RELOC_SPARC_TLS_GD_ADD: | |
3405 | case BFD_RELOC_SPARC_TLS_GD_CALL: | |
3406 | case BFD_RELOC_SPARC_TLS_LDM_HI22: | |
3407 | case BFD_RELOC_SPARC_TLS_LDM_LO10: | |
3408 | case BFD_RELOC_SPARC_TLS_LDM_ADD: | |
3409 | case BFD_RELOC_SPARC_TLS_LDM_CALL: | |
3410 | case BFD_RELOC_SPARC_TLS_LDO_HIX22: | |
3411 | case BFD_RELOC_SPARC_TLS_LDO_LOX10: | |
3412 | case BFD_RELOC_SPARC_TLS_LDO_ADD: | |
3413 | case BFD_RELOC_SPARC_TLS_IE_HI22: | |
3414 | case BFD_RELOC_SPARC_TLS_IE_LO10: | |
3415 | case BFD_RELOC_SPARC_TLS_IE_LD: | |
3416 | case BFD_RELOC_SPARC_TLS_IE_LDX: | |
3417 | case BFD_RELOC_SPARC_TLS_IE_ADD: | |
3418 | case BFD_RELOC_SPARC_TLS_LE_HIX22: | |
3419 | case BFD_RELOC_SPARC_TLS_LE_LOX10: | |
3420 | case BFD_RELOC_SPARC_TLS_DTPOFF32: | |
3421 | case BFD_RELOC_SPARC_TLS_DTPOFF64: | |
739f7f82 DM |
3422 | case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: |
3423 | case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: | |
3424 | case BFD_RELOC_SPARC_GOTDATA_OP: | |
252b5132 RH |
3425 | code = fixp->fx_r_type; |
3426 | break; | |
3427 | default: | |
3428 | abort (); | |
3429 | return NULL; | |
3430 | } | |
3431 | ||
3432 | #if defined (OBJ_ELF) || defined (OBJ_AOUT) | |
3433 | /* If we are generating PIC code, we need to generate a different | |
3434 | set of relocs. */ | |
3435 | ||
3436 | #ifdef OBJ_ELF | |
3437 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" | |
3438 | #else | |
3439 | #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" | |
910600e9 RS |
3440 | #endif |
3441 | #ifdef TE_VXWORKS | |
3442 | #define GOTT_BASE "__GOTT_BASE__" | |
3443 | #define GOTT_INDEX "__GOTT_INDEX__" | |
252b5132 RH |
3444 | #endif |
3445 | ||
153b546a ILT |
3446 | /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ |
3447 | ||
252b5132 RH |
3448 | if (sparc_pic_code) |
3449 | { | |
3450 | switch (code) | |
3451 | { | |
3452 | case BFD_RELOC_32_PCREL_S2: | |
ae6063d4 | 3453 | if (generic_force_reloc (fixp)) |
252b5132 RH |
3454 | code = BFD_RELOC_SPARC_WPLT30; |
3455 | break; | |
3456 | case BFD_RELOC_HI22: | |
910600e9 RS |
3457 | code = BFD_RELOC_SPARC_GOT22; |
3458 | if (fixp->fx_addsy != NULL) | |
3459 | { | |
3460 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3461 | code = BFD_RELOC_SPARC_PC22; | |
3462 | #ifdef TE_VXWORKS | |
3463 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3464 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3465 | code = BFD_RELOC_HI22; /* Unchanged. */ | |
3466 | #endif | |
3467 | } | |
252b5132 RH |
3468 | break; |
3469 | case BFD_RELOC_LO10: | |
910600e9 RS |
3470 | code = BFD_RELOC_SPARC_GOT10; |
3471 | if (fixp->fx_addsy != NULL) | |
3472 | { | |
3473 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) | |
3474 | code = BFD_RELOC_SPARC_PC10; | |
3475 | #ifdef TE_VXWORKS | |
3476 | if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 | |
3477 | || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) | |
3478 | code = BFD_RELOC_LO10; /* Unchanged. */ | |
3479 | #endif | |
3480 | } | |
252b5132 RH |
3481 | break; |
3482 | case BFD_RELOC_SPARC13: | |
3483 | code = BFD_RELOC_SPARC_GOT13; | |
3484 | break; | |
3485 | default: | |
3486 | break; | |
3487 | } | |
3488 | } | |
e0c6ed95 | 3489 | #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ |
252b5132 | 3490 | |
062cf837 EB |
3491 | /* Nothing is aligned in DWARF debugging sections. */ |
3492 | if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) | |
3493 | switch (code) | |
3494 | { | |
3495 | case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; | |
3496 | case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; | |
3497 | case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; | |
3498 | default: break; | |
3499 | } | |
3500 | ||
dabe3bbc RH |
3501 | if (code == BFD_RELOC_SPARC_OLO10) |
3502 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); | |
3503 | else | |
3504 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
252b5132 RH |
3505 | if (reloc->howto == 0) |
3506 | { | |
3507 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
3508 | _("internal error: can't export reloc type %d (`%s')"), | |
3509 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); | |
dabe3bbc RH |
3510 | xfree (reloc); |
3511 | relocs[0] = NULL; | |
3512 | return relocs; | |
252b5132 RH |
3513 | } |
3514 | ||
3515 | /* @@ Why fx_addnumber sometimes and fx_offset other times? */ | |
3516 | #ifdef OBJ_AOUT | |
3517 | ||
3518 | if (reloc->howto->pc_relative == 0 | |
3519 | || code == BFD_RELOC_SPARC_PC10 | |
3520 | || code == BFD_RELOC_SPARC_PC22) | |
3521 | reloc->addend = fixp->fx_addnumber; | |
3522 | else if (sparc_pic_code | |
3523 | && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 | |
3524 | && fixp->fx_addsy != NULL | |
3525 | && (S_IS_EXTERNAL (fixp->fx_addsy) | |
3526 | || S_IS_WEAK (fixp->fx_addsy)) | |
3527 | && S_IS_DEFINED (fixp->fx_addsy) | |
3528 | && ! S_IS_COMMON (fixp->fx_addsy)) | |
3529 | reloc->addend = fixp->fx_addnumber; | |
3530 | else | |
3531 | reloc->addend = fixp->fx_offset - reloc->address; | |
3532 | ||
e0c6ed95 | 3533 | #else /* elf or coff */ |
252b5132 | 3534 | |
bd5e6e7e JJ |
3535 | if (code != BFD_RELOC_32_PCREL_S2 |
3536 | && code != BFD_RELOC_SPARC_WDISP22 | |
3537 | && code != BFD_RELOC_SPARC_WDISP16 | |
3538 | && code != BFD_RELOC_SPARC_WDISP19 | |
b9734f35 JJ |
3539 | && code != BFD_RELOC_SPARC_WPLT30 |
3540 | && code != BFD_RELOC_SPARC_TLS_GD_CALL | |
3541 | && code != BFD_RELOC_SPARC_TLS_LDM_CALL) | |
252b5132 | 3542 | reloc->addend = fixp->fx_addnumber; |
49309057 | 3543 | else if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
3544 | reloc->addend = (section->vma |
3545 | + fixp->fx_addnumber | |
3546 | + md_pcrel_from (fixp)); | |
3547 | else | |
3548 | reloc->addend = fixp->fx_offset; | |
3549 | #endif | |
3550 | ||
dabe3bbc RH |
3551 | /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 |
3552 | on the same location. */ | |
3553 | if (code == BFD_RELOC_SPARC_OLO10) | |
3554 | { | |
3555 | relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); | |
3556 | relocs[2] = NULL; | |
3557 | ||
3558 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
ab3e48dc KH |
3559 | *reloc->sym_ptr_ptr |
3560 | = symbol_get_bfdsym (section_symbol (absolute_section)); | |
dabe3bbc RH |
3561 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
3562 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); | |
3563 | reloc->addend = fixp->tc_fix_data; | |
3564 | } | |
3565 | ||
3566 | return relocs; | |
252b5132 RH |
3567 | } |
3568 | \f | |
e0c6ed95 | 3569 | /* We have no need to default values of symbols. */ |
252b5132 | 3570 | |
252b5132 | 3571 | symbolS * |
5a49b8ac | 3572 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
3573 | { |
3574 | return 0; | |
e0c6ed95 AM |
3575 | } |
3576 | ||
3577 | /* Round up a section size to the appropriate boundary. */ | |
252b5132 | 3578 | |
252b5132 | 3579 | valueT |
5a49b8ac | 3580 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 RH |
3581 | { |
3582 | #ifndef OBJ_ELF | |
3583 | /* This is not right for ELF; a.out wants it, and COFF will force | |
3584 | the alignment anyways. */ | |
3585 | valueT align = ((valueT) 1 | |
3586 | << (valueT) bfd_get_section_alignment (stdoutput, segment)); | |
3587 | valueT newsize; | |
e0c6ed95 AM |
3588 | |
3589 | /* Turn alignment value into a mask. */ | |
252b5132 RH |
3590 | align--; |
3591 | newsize = (size + align) & ~align; | |
3592 | return newsize; | |
3593 | #else | |
3594 | return size; | |
3595 | #endif | |
3596 | } | |
3597 | ||
3598 | /* Exactly what point is a PC-relative offset relative TO? | |
3599 | On the sparc, they're relative to the address of the offset, plus | |
3600 | its size. This gets us to the following instruction. | |
e0c6ed95 AM |
3601 | (??? Is this right? FIXME-SOON) */ |
3602 | long | |
5a49b8ac | 3603 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
3604 | { |
3605 | long ret; | |
3606 | ||
3607 | ret = fixP->fx_where + fixP->fx_frag->fr_address; | |
3608 | if (! sparc_pic_code | |
3609 | || fixP->fx_addsy == NULL | |
49309057 | 3610 | || symbol_section_p (fixP->fx_addsy)) |
252b5132 RH |
3611 | ret += fixP->fx_size; |
3612 | return ret; | |
3613 | } | |
3614 | \f | |
3615 | /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power | |
3616 | of two. */ | |
3617 | ||
3618 | static int | |
5a49b8ac | 3619 | mylog2 (int value) |
252b5132 RH |
3620 | { |
3621 | int shift; | |
3622 | ||
3623 | if (value <= 0) | |
3624 | return -1; | |
3625 | ||
3626 | for (shift = 0; (value & 1) == 0; value >>= 1) | |
3627 | ++shift; | |
3628 | ||
3629 | return (value == 1) ? shift : -1; | |
3630 | } | |
3631 | ||
e0c6ed95 | 3632 | /* Sort of like s_lcomm. */ |
252b5132 RH |
3633 | |
3634 | #ifndef OBJ_ELF | |
3635 | static int max_alignment = 15; | |
3636 | #endif | |
3637 | ||
3638 | static void | |
5a49b8ac | 3639 | s_reserve (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
3640 | { |
3641 | char *name; | |
3642 | char *p; | |
3643 | char c; | |
3644 | int align; | |
3645 | int size; | |
3646 | int temp; | |
3647 | symbolS *symbolP; | |
3648 | ||
3649 | name = input_line_pointer; | |
3650 | c = get_symbol_end (); | |
3651 | p = input_line_pointer; | |
3652 | *p = c; | |
3653 | SKIP_WHITESPACE (); | |
3654 | ||
3655 | if (*input_line_pointer != ',') | |
3656 | { | |
3657 | as_bad (_("Expected comma after name")); | |
3658 | ignore_rest_of_line (); | |
3659 | return; | |
3660 | } | |
3661 | ||
3662 | ++input_line_pointer; | |
3663 | ||
3664 | if ((size = get_absolute_expression ()) < 0) | |
3665 | { | |
3666 | as_bad (_("BSS length (%d.) <0! Ignored."), size); | |
3667 | ignore_rest_of_line (); | |
3668 | return; | |
e0c6ed95 | 3669 | } /* Bad length. */ |
252b5132 RH |
3670 | |
3671 | *p = 0; | |
3672 | symbolP = symbol_find_or_make (name); | |
3673 | *p = c; | |
3674 | ||
3675 | if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 | |
3676 | && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) | |
3677 | { | |
3678 | as_bad (_("bad .reserve segment -- expected BSS segment")); | |
3679 | return; | |
3680 | } | |
3681 | ||
3682 | if (input_line_pointer[2] == '.') | |
3683 | input_line_pointer += 7; | |
3684 | else | |
3685 | input_line_pointer += 6; | |
3686 | SKIP_WHITESPACE (); | |
3687 | ||
3688 | if (*input_line_pointer == ',') | |
3689 | { | |
3690 | ++input_line_pointer; | |
3691 | ||
3692 | SKIP_WHITESPACE (); | |
3693 | if (*input_line_pointer == '\n') | |
3694 | { | |
3695 | as_bad (_("missing alignment")); | |
3696 | ignore_rest_of_line (); | |
3697 | return; | |
3698 | } | |
3699 | ||
3700 | align = (int) get_absolute_expression (); | |
3701 | ||
3702 | #ifndef OBJ_ELF | |
3703 | if (align > max_alignment) | |
3704 | { | |
3705 | align = max_alignment; | |
3706 | as_warn (_("alignment too large; assuming %d"), align); | |
3707 | } | |
3708 | #endif | |
3709 | ||
3710 | if (align < 0) | |
3711 | { | |
3712 | as_bad (_("negative alignment")); | |
3713 | ignore_rest_of_line (); | |
3714 | return; | |
3715 | } | |
3716 | ||
3717 | if (align != 0) | |
3718 | { | |
f17c130b | 3719 | temp = mylog2 (align); |
252b5132 RH |
3720 | if (temp < 0) |
3721 | { | |
3722 | as_bad (_("alignment not a power of 2")); | |
3723 | ignore_rest_of_line (); | |
3724 | return; | |
3725 | } | |
3726 | ||
3727 | align = temp; | |
3728 | } | |
3729 | ||
3730 | record_alignment (bss_section, align); | |
3731 | } | |
3732 | else | |
3733 | align = 0; | |
3734 | ||
3735 | if (!S_IS_DEFINED (symbolP) | |
3736 | #ifdef OBJ_AOUT | |
3737 | && S_GET_OTHER (symbolP) == 0 | |
3738 | && S_GET_DESC (symbolP) == 0 | |
3739 | #endif | |
3740 | ) | |
3741 | { | |
3742 | if (! need_pass_2) | |
3743 | { | |
3744 | char *pfrag; | |
3745 | segT current_seg = now_seg; | |
3746 | subsegT current_subseg = now_subseg; | |
3747 | ||
e0c6ed95 AM |
3748 | /* Switch to bss. */ |
3749 | subseg_set (bss_section, 1); | |
252b5132 RH |
3750 | |
3751 | if (align) | |
e0c6ed95 AM |
3752 | /* Do alignment. */ |
3753 | frag_align (align, 0, 0); | |
252b5132 | 3754 | |
e0c6ed95 | 3755 | /* Detach from old frag. */ |
ab3e48dc | 3756 | if (S_GET_SEGMENT (symbolP) == bss_section) |
49309057 | 3757 | symbol_get_frag (symbolP)->fr_symbol = NULL; |
252b5132 | 3758 | |
49309057 | 3759 | symbol_set_frag (symbolP, frag_now); |
e0c6ed95 AM |
3760 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
3761 | (offsetT) size, (char *) 0); | |
252b5132 RH |
3762 | *pfrag = 0; |
3763 | ||
3764 | S_SET_SEGMENT (symbolP, bss_section); | |
3765 | ||
3766 | subseg_set (current_seg, current_subseg); | |
3767 | ||
3768 | #ifdef OBJ_ELF | |
3769 | S_SET_SIZE (symbolP, size); | |
3770 | #endif | |
3771 | } | |
3772 | } | |
3773 | else | |
3774 | { | |
20203fb9 | 3775 | as_warn (_("Ignoring attempt to re-define symbol %s"), |
ab3e48dc | 3776 | S_GET_NAME (symbolP)); |
20203fb9 | 3777 | } |
252b5132 RH |
3778 | |
3779 | demand_empty_rest_of_line (); | |
3780 | } | |
3781 | ||
3782 | static void | |
5a49b8ac | 3783 | s_common (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
3784 | { |
3785 | char *name; | |
3786 | char c; | |
3787 | char *p; | |
685736be | 3788 | offsetT temp, size; |
252b5132 RH |
3789 | symbolS *symbolP; |
3790 | ||
3791 | name = input_line_pointer; | |
3792 | c = get_symbol_end (); | |
e0c6ed95 | 3793 | /* Just after name is now '\0'. */ |
252b5132 RH |
3794 | p = input_line_pointer; |
3795 | *p = c; | |
3796 | SKIP_WHITESPACE (); | |
3797 | if (*input_line_pointer != ',') | |
3798 | { | |
3799 | as_bad (_("Expected comma after symbol-name")); | |
3800 | ignore_rest_of_line (); | |
3801 | return; | |
3802 | } | |
e0c6ed95 AM |
3803 | |
3804 | /* Skip ','. */ | |
3805 | input_line_pointer++; | |
3806 | ||
252b5132 RH |
3807 | if ((temp = get_absolute_expression ()) < 0) |
3808 | { | |
685736be NC |
3809 | as_bad (_(".COMMon length (%lu) out of range ignored"), |
3810 | (unsigned long) temp); | |
252b5132 RH |
3811 | ignore_rest_of_line (); |
3812 | return; | |
3813 | } | |
3814 | size = temp; | |
3815 | *p = 0; | |
3816 | symbolP = symbol_find_or_make (name); | |
3817 | *p = c; | |
3818 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
3819 | { | |
3820 | as_bad (_("Ignoring attempt to re-define symbol")); | |
3821 | ignore_rest_of_line (); | |
3822 | return; | |
3823 | } | |
3824 | if (S_GET_VALUE (symbolP) != 0) | |
3825 | { | |
3826 | if (S_GET_VALUE (symbolP) != (valueT) size) | |
3827 | { | |
364b6d8b JJ |
3828 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), |
3829 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); | |
252b5132 RH |
3830 | } |
3831 | } | |
3832 | else | |
3833 | { | |
3834 | #ifndef OBJ_ELF | |
3835 | S_SET_VALUE (symbolP, (valueT) size); | |
3836 | S_SET_EXTERNAL (symbolP); | |
3837 | #endif | |
3838 | } | |
7dcc9865 | 3839 | know (symbol_get_frag (symbolP) == &zero_address_frag); |
252b5132 RH |
3840 | if (*input_line_pointer != ',') |
3841 | { | |
3842 | as_bad (_("Expected comma after common length")); | |
3843 | ignore_rest_of_line (); | |
3844 | return; | |
3845 | } | |
3846 | input_line_pointer++; | |
3847 | SKIP_WHITESPACE (); | |
3848 | if (*input_line_pointer != '"') | |
3849 | { | |
3850 | temp = get_absolute_expression (); | |
3851 | ||
3852 | #ifndef OBJ_ELF | |
3853 | if (temp > max_alignment) | |
3854 | { | |
3855 | temp = max_alignment; | |
f17c130b | 3856 | as_warn (_("alignment too large; assuming %ld"), (long) temp); |
252b5132 RH |
3857 | } |
3858 | #endif | |
3859 | ||
3860 | if (temp < 0) | |
3861 | { | |
3862 | as_bad (_("negative alignment")); | |
3863 | ignore_rest_of_line (); | |
3864 | return; | |
3865 | } | |
3866 | ||
3867 | #ifdef OBJ_ELF | |
49309057 | 3868 | if (symbol_get_obj (symbolP)->local) |
252b5132 RH |
3869 | { |
3870 | segT old_sec; | |
3871 | int old_subsec; | |
252b5132 RH |
3872 | int align; |
3873 | ||
3874 | old_sec = now_seg; | |
3875 | old_subsec = now_subseg; | |
3876 | ||
3877 | if (temp == 0) | |
3878 | align = 0; | |
3879 | else | |
f17c130b | 3880 | align = mylog2 (temp); |
252b5132 RH |
3881 | |
3882 | if (align < 0) | |
3883 | { | |
3884 | as_bad (_("alignment not a power of 2")); | |
3885 | ignore_rest_of_line (); | |
3886 | return; | |
3887 | } | |
3888 | ||
3889 | record_alignment (bss_section, align); | |
3890 | subseg_set (bss_section, 0); | |
3891 | if (align) | |
3892 | frag_align (align, 0, 0); | |
3893 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
3894 | symbol_get_frag (symbolP)->fr_symbol = 0; |
3895 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
3896 | p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
3897 | (offsetT) size, (char *) 0); | |
3898 | *p = 0; | |
3899 | S_SET_SEGMENT (symbolP, bss_section); | |
3900 | S_CLEAR_EXTERNAL (symbolP); | |
3901 | S_SET_SIZE (symbolP, size); | |
3902 | subseg_set (old_sec, old_subsec); | |
3903 | } | |
3904 | else | |
e0c6ed95 | 3905 | #endif /* OBJ_ELF */ |
252b5132 RH |
3906 | { |
3907 | allocate_common: | |
3908 | S_SET_VALUE (symbolP, (valueT) size); | |
3909 | #ifdef OBJ_ELF | |
3910 | S_SET_ALIGN (symbolP, temp); | |
3911 | S_SET_SIZE (symbolP, size); | |
3912 | #endif | |
3913 | S_SET_EXTERNAL (symbolP); | |
3914 | S_SET_SEGMENT (symbolP, bfd_com_section_ptr); | |
3915 | } | |
3916 | } | |
3917 | else | |
3918 | { | |
3919 | input_line_pointer++; | |
3920 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ | |
3921 | if (*input_line_pointer == '.') | |
3922 | input_line_pointer++; | |
3923 | /* @@ Some say data, some say bss. */ | |
3924 | if (strncmp (input_line_pointer, "bss\"", 4) | |
3925 | && strncmp (input_line_pointer, "data\"", 5)) | |
3926 | { | |
3927 | while (*--input_line_pointer != '"') | |
3928 | ; | |
3929 | input_line_pointer--; | |
3930 | goto bad_common_segment; | |
3931 | } | |
3932 | while (*input_line_pointer++ != '"') | |
3933 | ; | |
3934 | goto allocate_common; | |
3935 | } | |
3936 | ||
49309057 | 3937 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; |
252b5132 RH |
3938 | |
3939 | demand_empty_rest_of_line (); | |
3940 | return; | |
3941 | ||
3942 | { | |
3943 | bad_common_segment: | |
3944 | p = input_line_pointer; | |
3945 | while (*p && *p != '\n') | |
3946 | p++; | |
3947 | c = *p; | |
3948 | *p = '\0'; | |
3949 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); | |
3950 | *p = c; | |
3951 | input_line_pointer = p; | |
3952 | ignore_rest_of_line (); | |
3953 | return; | |
3954 | } | |
3955 | } | |
3956 | ||
67c1ffbe | 3957 | /* Handle the .empty pseudo-op. This suppresses the warnings about |
252b5132 RH |
3958 | invalid delay slot usage. */ |
3959 | ||
3960 | static void | |
5a49b8ac | 3961 | s_empty (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
3962 | { |
3963 | /* The easy way to implement is to just forget about the last | |
3964 | instruction. */ | |
3965 | last_insn = NULL; | |
3966 | } | |
3967 | ||
3968 | static void | |
5a49b8ac | 3969 | s_seg (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
3970 | { |
3971 | ||
3972 | if (strncmp (input_line_pointer, "\"text\"", 6) == 0) | |
3973 | { | |
3974 | input_line_pointer += 6; | |
3975 | s_text (0); | |
3976 | return; | |
3977 | } | |
3978 | if (strncmp (input_line_pointer, "\"data\"", 6) == 0) | |
3979 | { | |
3980 | input_line_pointer += 6; | |
3981 | s_data (0); | |
3982 | return; | |
3983 | } | |
3984 | if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) | |
3985 | { | |
3986 | input_line_pointer += 7; | |
3987 | s_data1 (); | |
3988 | return; | |
3989 | } | |
3990 | if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) | |
3991 | { | |
3992 | input_line_pointer += 5; | |
3993 | /* We only support 2 segments -- text and data -- for now, so | |
3994 | things in the "bss segment" will have to go into data for now. | |
e0c6ed95 AM |
3995 | You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ |
3996 | subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ | |
252b5132 RH |
3997 | return; |
3998 | } | |
3999 | as_bad (_("Unknown segment type")); | |
4000 | demand_empty_rest_of_line (); | |
4001 | } | |
4002 | ||
4003 | static void | |
5a49b8ac | 4004 | s_data1 (void) |
252b5132 RH |
4005 | { |
4006 | subseg_set (data_section, 1); | |
4007 | demand_empty_rest_of_line (); | |
4008 | } | |
4009 | ||
4010 | static void | |
5a49b8ac | 4011 | s_proc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4012 | { |
4013 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4014 | { | |
4015 | ++input_line_pointer; | |
4016 | } | |
4017 | ++input_line_pointer; | |
4018 | } | |
4019 | ||
4020 | /* This static variable is set by s_uacons to tell sparc_cons_align | |
67c1ffbe | 4021 | that the expression does not need to be aligned. */ |
252b5132 RH |
4022 | |
4023 | static int sparc_no_align_cons = 0; | |
4024 | ||
bd5e6e7e JJ |
4025 | /* This static variable is set by sparc_cons to emit requested types |
4026 | of relocations in cons_fix_new_sparc. */ | |
4027 | ||
4028 | static const char *sparc_cons_special_reloc; | |
4029 | ||
252b5132 RH |
4030 | /* This handles the unaligned space allocation pseudo-ops, such as |
4031 | .uaword. .uaword is just like .word, but the value does not need | |
4032 | to be aligned. */ | |
4033 | ||
4034 | static void | |
5a49b8ac | 4035 | s_uacons (int bytes) |
252b5132 RH |
4036 | { |
4037 | /* Tell sparc_cons_align not to align this value. */ | |
4038 | sparc_no_align_cons = 1; | |
4039 | cons (bytes); | |
4ffadb11 | 4040 | sparc_no_align_cons = 0; |
252b5132 RH |
4041 | } |
4042 | ||
cf9a1301 RH |
4043 | /* This handles the native word allocation pseudo-op .nword. |
4044 | For sparc_arch_size 32 it is equivalent to .word, for | |
4045 | sparc_arch_size 64 it is equivalent to .xword. */ | |
4046 | ||
4047 | static void | |
5a49b8ac | 4048 | s_ncons (int bytes ATTRIBUTE_UNUSED) |
cf9a1301 RH |
4049 | { |
4050 | cons (sparc_arch_size == 32 ? 4 : 8); | |
4051 | } | |
4052 | ||
6d8809aa RH |
4053 | #ifdef OBJ_ELF |
4054 | /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a | |
4055 | global register. | |
4056 | The syntax is: | |
e0c6ed95 | 4057 | |
6d8809aa | 4058 | .register %g[2367],{#scratch|symbolname|#ignore} |
e0c6ed95 | 4059 | */ |
6d8809aa RH |
4060 | |
4061 | static void | |
5a49b8ac | 4062 | s_register (int ignore ATTRIBUTE_UNUSED) |
6d8809aa RH |
4063 | { |
4064 | char c; | |
4065 | int reg; | |
4066 | int flags; | |
4067 | const char *regname; | |
4068 | ||
4069 | if (input_line_pointer[0] != '%' | |
4070 | || input_line_pointer[1] != 'g' | |
4071 | || ((input_line_pointer[2] & ~1) != '2' | |
4072 | && (input_line_pointer[2] & ~1) != '6') | |
4073 | || input_line_pointer[3] != ',') | |
4074 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
4075 | reg = input_line_pointer[2] - '0'; | |
4076 | input_line_pointer += 4; | |
4077 | ||
4078 | if (*input_line_pointer == '#') | |
4079 | { | |
4080 | ++input_line_pointer; | |
4081 | regname = input_line_pointer; | |
4082 | c = get_symbol_end (); | |
4083 | if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) | |
4084 | as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); | |
ab3e48dc | 4085 | if (regname[0] == 'i') |
6d8809aa RH |
4086 | regname = NULL; |
4087 | else | |
4088 | regname = ""; | |
4089 | } | |
4090 | else | |
4091 | { | |
4092 | regname = input_line_pointer; | |
4093 | c = get_symbol_end (); | |
4094 | } | |
4095 | if (sparc_arch_size == 64) | |
4096 | { | |
e0c6ed95 | 4097 | if (globals[reg]) |
6d8809aa | 4098 | { |
e0c6ed95 AM |
4099 | if ((regname && globals[reg] != (symbolS *) 1 |
4100 | && strcmp (S_GET_NAME (globals[reg]), regname)) | |
4101 | || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) | |
6d8809aa RH |
4102 | as_bad (_("redefinition of global register")); |
4103 | } | |
4104 | else | |
4105 | { | |
4106 | if (regname == NULL) | |
e0c6ed95 | 4107 | globals[reg] = (symbolS *) 1; |
6d8809aa RH |
4108 | else |
4109 | { | |
4110 | if (*regname) | |
4111 | { | |
4112 | if (symbol_find (regname)) | |
4113 | as_bad (_("Register symbol %s already defined."), | |
4114 | regname); | |
4115 | } | |
e0c6ed95 AM |
4116 | globals[reg] = symbol_make (regname); |
4117 | flags = symbol_get_bfdsym (globals[reg])->flags; | |
6d8809aa RH |
4118 | if (! *regname) |
4119 | flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); | |
4120 | if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) | |
4121 | flags |= BSF_GLOBAL; | |
e0c6ed95 AM |
4122 | symbol_get_bfdsym (globals[reg])->flags = flags; |
4123 | S_SET_VALUE (globals[reg], (valueT) reg); | |
4124 | S_SET_ALIGN (globals[reg], reg); | |
4125 | S_SET_SIZE (globals[reg], 0); | |
6d8809aa RH |
4126 | /* Although we actually want undefined_section here, |
4127 | we have to use absolute_section, because otherwise | |
4128 | generic as code will make it a COM section. | |
4129 | We fix this up in sparc_adjust_symtab. */ | |
e0c6ed95 AM |
4130 | S_SET_SEGMENT (globals[reg], absolute_section); |
4131 | S_SET_OTHER (globals[reg], 0); | |
4132 | elf_symbol (symbol_get_bfdsym (globals[reg])) | |
6d8809aa RH |
4133 | ->internal_elf_sym.st_info = |
4134 | ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); | |
e0c6ed95 | 4135 | elf_symbol (symbol_get_bfdsym (globals[reg])) |
6d8809aa RH |
4136 | ->internal_elf_sym.st_shndx = SHN_UNDEF; |
4137 | } | |
4138 | } | |
4139 | } | |
4140 | ||
4141 | *input_line_pointer = c; | |
4142 | ||
4143 | demand_empty_rest_of_line (); | |
4144 | } | |
4145 | ||
4146 | /* Adjust the symbol table. We set undefined sections for STT_REGISTER | |
4147 | symbols which need it. */ | |
e0c6ed95 | 4148 | |
6d8809aa | 4149 | void |
5a49b8ac | 4150 | sparc_adjust_symtab (void) |
6d8809aa RH |
4151 | { |
4152 | symbolS *sym; | |
e0c6ed95 | 4153 | |
6d8809aa RH |
4154 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
4155 | { | |
4156 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4157 | ->internal_elf_sym.st_info) != STT_REGISTER) | |
4158 | continue; | |
4159 | ||
4160 | if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) | |
4161 | ->internal_elf_sym.st_shndx != SHN_UNDEF)) | |
4162 | continue; | |
4163 | ||
4164 | S_SET_SEGMENT (sym, undefined_section); | |
4165 | } | |
4166 | } | |
4167 | #endif | |
4168 | ||
252b5132 RH |
4169 | /* If the --enforce-aligned-data option is used, we require .word, |
4170 | et. al., to be aligned correctly. We do it by setting up an | |
4171 | rs_align_code frag, and checking in HANDLE_ALIGN to make sure that | |
4172 | no unexpected alignment was introduced. | |
4173 | ||
4174 | The SunOS and Solaris native assemblers enforce aligned data by | |
4175 | default. We don't want to do that, because gcc can deliberately | |
4176 | generate misaligned data if the packed attribute is used. Instead, | |
4177 | we permit misaligned data by default, and permit the user to set an | |
4178 | option to check for it. */ | |
4179 | ||
4180 | void | |
5a49b8ac | 4181 | sparc_cons_align (int nbytes) |
252b5132 RH |
4182 | { |
4183 | int nalign; | |
252b5132 RH |
4184 | |
4185 | /* Only do this if we are enforcing aligned data. */ | |
4186 | if (! enforce_aligned_data) | |
4187 | return; | |
4188 | ||
0f2712ed | 4189 | /* Don't align if this is an unaligned pseudo-op. */ |
252b5132 | 4190 | if (sparc_no_align_cons) |
0f2712ed | 4191 | return; |
252b5132 | 4192 | |
f17c130b | 4193 | nalign = mylog2 (nbytes); |
252b5132 RH |
4194 | if (nalign == 0) |
4195 | return; | |
4196 | ||
9c2799c2 | 4197 | gas_assert (nalign > 0); |
252b5132 RH |
4198 | |
4199 | if (now_seg == absolute_section) | |
4200 | { | |
4201 | if ((abs_section_offset & ((1 << nalign) - 1)) != 0) | |
4202 | as_bad (_("misaligned data")); | |
4203 | return; | |
4204 | } | |
4205 | ||
87975d2a AM |
4206 | frag_var (rs_align_test, 1, 1, (relax_substateT) 0, |
4207 | (symbolS *) NULL, (offsetT) nalign, (char *) NULL); | |
252b5132 RH |
4208 | |
4209 | record_alignment (now_seg, nalign); | |
4210 | } | |
4211 | ||
0a9ef439 | 4212 | /* This is called from HANDLE_ALIGN in tc-sparc.h. */ |
252b5132 RH |
4213 | |
4214 | void | |
5a49b8ac | 4215 | sparc_handle_align (fragS *fragp) |
252b5132 | 4216 | { |
0a9ef439 RH |
4217 | int count, fix; |
4218 | char *p; | |
4219 | ||
4220 | count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
bfb32b52 | 4221 | |
0a9ef439 | 4222 | switch (fragp->fr_type) |
252b5132 | 4223 | { |
0a9ef439 RH |
4224 | case rs_align_test: |
4225 | if (count != 0) | |
4226 | as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); | |
4227 | break; | |
e0c6ed95 | 4228 | |
0a9ef439 RH |
4229 | case rs_align_code: |
4230 | p = fragp->fr_literal + fragp->fr_fix; | |
4231 | fix = 0; | |
e0c6ed95 | 4232 | |
0a9ef439 RH |
4233 | if (count & 3) |
4234 | { | |
4235 | fix = count & 3; | |
4236 | memset (p, 0, fix); | |
4237 | p += fix; | |
4238 | count -= fix; | |
4239 | } | |
e0c6ed95 | 4240 | |
0a9ef439 RH |
4241 | if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) |
4242 | { | |
4243 | unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ | |
4244 | if (INSN_BIG_ENDIAN) | |
4245 | number_to_chars_bigendian (p, wval, 4); | |
4246 | else | |
4247 | number_to_chars_littleendian (p, wval, 4); | |
4248 | p += 4; | |
4249 | count -= 4; | |
4250 | fix += 4; | |
e0c6ed95 | 4251 | } |
0a9ef439 RH |
4252 | |
4253 | if (INSN_BIG_ENDIAN) | |
4254 | number_to_chars_bigendian (p, 0x01000000, 4); | |
4255 | else | |
4256 | number_to_chars_littleendian (p, 0x01000000, 4); | |
4257 | ||
4258 | fragp->fr_fix += fix; | |
4259 | fragp->fr_var = 4; | |
4260 | break; | |
4261 | ||
4262 | default: | |
4263 | break; | |
252b5132 RH |
4264 | } |
4265 | } | |
4266 | ||
4267 | #ifdef OBJ_ELF | |
4268 | /* Some special processing for a Sparc ELF file. */ | |
4269 | ||
4270 | void | |
5a49b8ac | 4271 | sparc_elf_final_processing (void) |
252b5132 RH |
4272 | { |
4273 | /* Set the Sparc ELF flag bits. FIXME: There should probably be some | |
4274 | sort of BFD interface for this. */ | |
4275 | if (sparc_arch_size == 64) | |
4276 | { | |
4277 | switch (sparc_memory_model) | |
4278 | { | |
4279 | case MM_RMO: | |
4280 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; | |
4281 | break; | |
4282 | case MM_PSO: | |
4283 | elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; | |
4284 | break; | |
4285 | default: | |
4286 | break; | |
4287 | } | |
4288 | } | |
4289 | else if (current_architecture >= SPARC_OPCODE_ARCH_V9) | |
4290 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; | |
4291 | if (current_architecture == SPARC_OPCODE_ARCH_V9A) | |
4292 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; | |
19f7b010 JJ |
4293 | else if (current_architecture == SPARC_OPCODE_ARCH_V9B) |
4294 | elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; | |
252b5132 | 4295 | } |
bd5e6e7e JJ |
4296 | |
4297 | void | |
5a49b8ac | 4298 | sparc_cons (expressionS *exp, int size) |
bd5e6e7e JJ |
4299 | { |
4300 | char *save; | |
4301 | ||
4302 | SKIP_WHITESPACE (); | |
4303 | sparc_cons_special_reloc = NULL; | |
4304 | save = input_line_pointer; | |
4305 | if (input_line_pointer[0] == '%' | |
4306 | && input_line_pointer[1] == 'r' | |
4307 | && input_line_pointer[2] == '_') | |
4308 | { | |
4309 | if (strncmp (input_line_pointer + 3, "disp", 4) == 0) | |
4310 | { | |
4311 | input_line_pointer += 7; | |
4312 | sparc_cons_special_reloc = "disp"; | |
4313 | } | |
4314 | else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) | |
4315 | { | |
4316 | if (size != 4 && size != 8) | |
4317 | as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); | |
4318 | else | |
4319 | { | |
4320 | input_line_pointer += 6; | |
4321 | sparc_cons_special_reloc = "plt"; | |
4322 | } | |
4323 | } | |
b9734f35 JJ |
4324 | else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) |
4325 | { | |
4326 | if (size != 4 && size != 8) | |
4327 | as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); | |
4328 | else | |
4329 | { | |
4330 | input_line_pointer += 13; | |
4331 | sparc_cons_special_reloc = "tls_dtpoff"; | |
4332 | } | |
4333 | } | |
bd5e6e7e JJ |
4334 | if (sparc_cons_special_reloc) |
4335 | { | |
4336 | int bad = 0; | |
4337 | ||
4338 | switch (size) | |
4339 | { | |
4340 | case 1: | |
4341 | if (*input_line_pointer != '8') | |
4342 | bad = 1; | |
4343 | input_line_pointer--; | |
4344 | break; | |
4345 | case 2: | |
4346 | if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') | |
4347 | bad = 1; | |
4348 | break; | |
4349 | case 4: | |
4350 | if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') | |
4351 | bad = 1; | |
4352 | break; | |
4353 | case 8: | |
4354 | if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') | |
4355 | bad = 1; | |
4356 | break; | |
4357 | default: | |
4358 | bad = 1; | |
4359 | break; | |
4360 | } | |
4361 | ||
4362 | if (bad) | |
4363 | { | |
4364 | as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), | |
4365 | sparc_cons_special_reloc, size * 8, size); | |
4366 | } | |
4367 | else | |
4368 | { | |
4369 | input_line_pointer += 2; | |
4370 | if (*input_line_pointer != '(') | |
4371 | { | |
4372 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4373 | sparc_cons_special_reloc, size * 8); | |
4374 | bad = 1; | |
4375 | } | |
4376 | } | |
4377 | ||
4378 | if (bad) | |
4379 | { | |
4380 | input_line_pointer = save; | |
4381 | sparc_cons_special_reloc = NULL; | |
4382 | } | |
4383 | else | |
4384 | { | |
4385 | int c; | |
4386 | char *end = ++input_line_pointer; | |
4387 | int npar = 0; | |
4388 | ||
4389 | while (! is_end_of_line[(c = *end)]) | |
4390 | { | |
4391 | if (c == '(') | |
4392 | npar++; | |
4393 | else if (c == ')') | |
4394 | { | |
4395 | if (!npar) | |
4396 | break; | |
4397 | npar--; | |
4398 | } | |
4399 | end++; | |
4400 | } | |
4401 | ||
4402 | if (c != ')') | |
4403 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4404 | sparc_cons_special_reloc, size * 8); | |
4405 | else | |
4406 | { | |
4407 | *end = '\0'; | |
4408 | expression (exp); | |
4409 | *end = c; | |
4410 | if (input_line_pointer != end) | |
4411 | { | |
4412 | as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), | |
4413 | sparc_cons_special_reloc, size * 8); | |
4414 | } | |
4415 | else | |
4416 | { | |
4417 | input_line_pointer++; | |
4418 | SKIP_WHITESPACE (); | |
4419 | c = *input_line_pointer; | |
4420 | if (! is_end_of_line[c] && c != ',') | |
4421 | as_bad (_("Illegal operands: garbage after %%r_%s%d()"), | |
4422 | sparc_cons_special_reloc, size * 8); | |
4423 | } | |
4424 | } | |
4425 | } | |
4426 | } | |
4427 | } | |
4428 | if (sparc_cons_special_reloc == NULL) | |
4429 | expression (exp); | |
4430 | } | |
4431 | ||
252b5132 RH |
4432 | #endif |
4433 | ||
4434 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
4435 | reloc for a cons. We could use the definition there, except that | |
4436 | we want to handle little endian relocs specially. */ | |
4437 | ||
4438 | void | |
5a49b8ac AM |
4439 | cons_fix_new_sparc (fragS *frag, |
4440 | int where, | |
4441 | unsigned int nbytes, | |
4442 | expressionS *exp) | |
252b5132 RH |
4443 | { |
4444 | bfd_reloc_code_real_type r; | |
4445 | ||
4446 | r = (nbytes == 1 ? BFD_RELOC_8 : | |
4447 | (nbytes == 2 ? BFD_RELOC_16 : | |
4448 | (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
4449 | ||
0f2712ed NC |
4450 | if (target_little_endian_data |
4451 | && nbytes == 4 | |
e0c6ed95 | 4452 | && now_seg->flags & SEC_ALLOC) |
252b5132 | 4453 | r = BFD_RELOC_SPARC_REV32; |
0f2712ed | 4454 | |
bd5e6e7e JJ |
4455 | if (sparc_cons_special_reloc) |
4456 | { | |
4457 | if (*sparc_cons_special_reloc == 'd') | |
4458 | switch (nbytes) | |
4459 | { | |
4460 | case 1: r = BFD_RELOC_8_PCREL; break; | |
4461 | case 2: r = BFD_RELOC_16_PCREL; break; | |
4462 | case 4: r = BFD_RELOC_32_PCREL; break; | |
4463 | case 8: r = BFD_RELOC_64_PCREL; break; | |
4464 | default: abort (); | |
4465 | } | |
b9734f35 | 4466 | else if (*sparc_cons_special_reloc == 'p') |
bd5e6e7e JJ |
4467 | switch (nbytes) |
4468 | { | |
4469 | case 4: r = BFD_RELOC_SPARC_PLT32; break; | |
4470 | case 8: r = BFD_RELOC_SPARC_PLT64; break; | |
4471 | } | |
b9734f35 JJ |
4472 | else |
4473 | switch (nbytes) | |
4474 | { | |
4475 | case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; | |
4476 | case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; | |
4477 | } | |
bd5e6e7e JJ |
4478 | } |
4479 | else if (sparc_no_align_cons) | |
0f2712ed NC |
4480 | { |
4481 | switch (nbytes) | |
4482 | { | |
4483 | case 2: r = BFD_RELOC_SPARC_UA16; break; | |
4484 | case 4: r = BFD_RELOC_SPARC_UA32; break; | |
4485 | case 8: r = BFD_RELOC_SPARC_UA64; break; | |
4486 | default: abort (); | |
4487 | } | |
4ffadb11 | 4488 | } |
0f2712ed | 4489 | |
252b5132 | 4490 | fix_new_exp (frag, where, (int) nbytes, exp, 0, r); |
364b6d8b JJ |
4491 | sparc_cons_special_reloc = NULL; |
4492 | } | |
4493 | ||
4494 | void | |
5a49b8ac | 4495 | sparc_cfi_frame_initial_instructions (void) |
364b6d8b JJ |
4496 | { |
4497 | cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); | |
4498 | } | |
4499 | ||
4500 | int | |
1df69f4f | 4501 | sparc_regname_to_dw2regnum (char *regname) |
364b6d8b JJ |
4502 | { |
4503 | char *p, *q; | |
4504 | ||
4505 | if (!regname[0]) | |
4506 | return -1; | |
4507 | ||
4508 | q = "goli"; | |
4509 | p = strchr (q, regname[0]); | |
4510 | if (p) | |
4511 | { | |
4512 | if (regname[1] < '0' || regname[1] > '8' || regname[2]) | |
4513 | return -1; | |
4514 | return (p - q) * 8 + regname[1] - '0'; | |
4515 | } | |
4516 | if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) | |
4517 | return 14; | |
4518 | if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) | |
4519 | return 30; | |
4520 | if (regname[0] == 'f' || regname[0] == 'r') | |
4521 | { | |
4522 | unsigned int regnum; | |
4523 | ||
4524 | regnum = strtoul (regname + 1, &q, 10); | |
4525 | if (p == q || *q) | |
4526 | return -1; | |
4527 | if (regnum >= ((regname[0] == 'f' | |
4528 | && SPARC_OPCODE_ARCH_V9_P (max_architecture)) | |
4529 | ? 64 : 32)) | |
4530 | return -1; | |
4531 | if (regname[0] == 'f') | |
4532 | { | |
4533 | regnum += 32; | |
4534 | if (regnum >= 64 && (regnum & 1)) | |
4535 | return -1; | |
4536 | } | |
4537 | return regnum; | |
4538 | } | |
4539 | return -1; | |
4540 | } | |
4541 | ||
4542 | void | |
4543 | sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) | |
4544 | { | |
4545 | sparc_cons_special_reloc = "disp"; | |
4546 | sparc_no_align_cons = 1; | |
4547 | emit_expr (exp, nbytes); | |
4548 | sparc_no_align_cons = 0; | |
4549 | sparc_cons_special_reloc = NULL; | |
252b5132 | 4550 | } |