Commit | Line | Data |
---|---|---|
64556643 | 1 | /* tc-tic80.c -- Assemble for the TI TMS320C80 (MV) |
414a1069 | 2 | Copyright (C) 1996, 1997 Free Software Foundation, Inc. |
64556643 FF |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
18 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
19 | 02111-1307, USA. */ | |
20 | ||
21 | #include "as.h" | |
22 | #include "opcode/tic80.h" | |
23 | ||
11e08196 FF |
24 | #define internal_error(what) \ |
25 | as_fatal("internal error:%s:%d: %s\n",__FILE__,__LINE__,what) | |
26 | #define internal_error_a(what,arg) \ | |
27 | as_fatal("internal error:%s:%d: %s %d\n",__FILE__,__LINE__,what,arg) | |
28 | ||
64556643 FF |
29 | \f |
30 | /* Generic assembler global variables which must be defined by all targets. */ | |
31 | ||
32 | /* Characters which always start a comment. */ | |
33 | const char comment_chars[] = ";"; | |
34 | ||
35 | /* Characters which start a comment at the beginning of a line. */ | |
36 | const char line_comment_chars[] = ";*"; | |
37 | ||
16171d71 FF |
38 | /* Characters which may be used to separate multiple commands on a single |
39 | line. The semicolon is such a character by default and should not be | |
40 | explicitly listed. */ | |
11e08196 | 41 | const char line_separator_chars[] = ""; |
64556643 FF |
42 | |
43 | /* Characters which are used to indicate an exponent in a floating | |
44 | point number. */ | |
45 | const char EXP_CHARS[] = "eE"; | |
46 | ||
47 | /* Characters which mean that a number is a floating point constant, | |
1e12595d FF |
48 | as in 0f1.0. */ |
49 | const char FLT_CHARS[] = "fF"; | |
64556643 | 50 | |
f1ce6af4 FF |
51 | /* This table describes all the machine specific pseudo-ops the assembler |
52 | has to support. The fields are: | |
16171d71 | 53 | |
f1ce6af4 FF |
54 | pseudo-op name without dot |
55 | function to call to execute this pseudo-op | |
16171d71 | 56 | integer arg to pass to the function */ |
f1ce6af4 FF |
57 | |
58 | const pseudo_typeS md_pseudo_table[] = | |
59 | { | |
ec72a266 FF |
60 | { "word", cons, 4 }, /* FIXME: Should this be machine independent? */ |
61 | { "bss", s_lcomm, 1 }, | |
62 | { NULL, NULL, 0 } | |
f1ce6af4 FF |
63 | }; |
64 | ||
65 | /* Opcode hash table. */ | |
66 | static struct hash_control *tic80_hash; | |
67 | ||
68 | static struct tic80_opcode * find_opcode PARAMS ((struct tic80_opcode *, expressionS [])); | |
11e08196 | 69 | static void build_insn PARAMS ((struct tic80_opcode *, expressionS *)); |
f1ce6af4 | 70 | static int get_operands PARAMS ((expressionS exp[])); |
11e08196 | 71 | static int const_overflow PARAMS ((unsigned long num, int bits, int flags)); |
f1ce6af4 | 72 | |
64556643 | 73 | \f |
f1ce6af4 FF |
74 | int |
75 | md_estimate_size_before_relax (fragP, segment_type) | |
76 | fragS *fragP; | |
77 | segT segment_type; | |
78 | { | |
11e08196 | 79 | internal_error ("Relaxation is a luxury we can't afford"); |
f1ce6af4 FF |
80 | return (-1); |
81 | } | |
82 | ||
83 | /* We have no need to default values of symbols. */ | |
84 | ||
85 | /* ARGSUSED */ | |
86 | symbolS * | |
87 | md_undefined_symbol (name) | |
88 | char *name; | |
89 | { | |
90 | return 0; | |
91 | } | |
92 | ||
93 | /* Turn a string in input_line_pointer into a floating point constant of type | |
94 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
95 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
96 | */ | |
97 | ||
98 | #define MAX_LITTLENUMS 4 | |
99 | ||
100 | char * | |
101 | md_atof (type, litP, sizeP) | |
102 | int type; | |
103 | char *litP; | |
104 | int *sizeP; | |
105 | { | |
106 | int prec; | |
107 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
108 | LITTLENUM_TYPE *wordP; | |
109 | char *t; | |
110 | char *atof_ieee (); | |
111 | ||
112 | switch (type) | |
113 | { | |
114 | case 'f': | |
115 | case 'F': | |
116 | case 's': | |
117 | case 'S': | |
118 | prec = 2; | |
119 | break; | |
120 | ||
121 | case 'd': | |
122 | case 'D': | |
123 | case 'r': | |
124 | case 'R': | |
125 | prec = 4; | |
126 | break; | |
127 | ||
128 | default: | |
129 | *sizeP = 0; | |
130 | return "bad call to md_atof ()"; | |
131 | } | |
132 | ||
133 | t = atof_ieee (input_line_pointer, type, words); | |
134 | if (t) | |
135 | { | |
136 | input_line_pointer = t; | |
137 | } | |
138 | ||
139 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
140 | ||
141 | for (wordP = words; prec--;) | |
142 | { | |
143 | md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE)); | |
144 | litP += sizeof (LITTLENUM_TYPE); | |
145 | } | |
146 | return (NULL); | |
147 | } | |
148 | ||
11e08196 FF |
149 | /* Check to see if the constant value in NUM will fit in a field of |
150 | width BITS if it has flags FLAGS. */ | |
151 | ||
152 | static int | |
153 | const_overflow (num, bits, flags) | |
154 | unsigned long num; | |
155 | int bits; | |
156 | int flags; | |
157 | { | |
158 | long min, max; | |
159 | int retval = 0; | |
160 | ||
161 | /* Only need to check fields less than 32 bits wide */ | |
162 | if (bits < 32) | |
163 | if (flags & TIC80_OPERAND_SIGNED) | |
164 | { | |
165 | max = (1 << (bits - 1)) - 1; | |
166 | min = - (1 << (bits - 1)); | |
167 | retval = ((long) num > max) || ((long) num < min); | |
168 | } | |
169 | else | |
170 | { | |
171 | max = (1 << bits) - 1; | |
172 | min = 0; | |
173 | retval = (num > max) || (num < min); | |
174 | } | |
175 | return (retval); | |
176 | } | |
177 | ||
f1ce6af4 FF |
178 | /* get_operands() parses a string of operands and fills in a passed array of |
179 | expressions in EXP. | |
180 | ||
181 | Note that we use O_absent expressions to record additional information | |
182 | about the previous non-O_absent expression, such as ":m" or ":s" | |
183 | modifiers or register numbers enclosed in parens like "(r10)". | |
184 | ||
185 | Returns the number of expressions that were placed in EXP. | |
186 | ||
187 | */ | |
188 | ||
189 | static int | |
190 | get_operands (exp) | |
191 | expressionS exp[]; | |
192 | { | |
193 | char *p = input_line_pointer; | |
194 | int numexp = 0; | |
195 | int mflag = 0; | |
196 | int sflag = 0; | |
197 | int parens = 0; | |
198 | ||
199 | while (*p) | |
200 | { | |
201 | /* Skip leading whitespace */ | |
202 | while (*p == ' ' || *p == '\t' || *p == ',') | |
203 | { | |
204 | p++; | |
205 | } | |
206 | ||
207 | /* Check to see if we have any operands left to parse */ | |
208 | if (*p == 0 || *p == '\n' || *p == '\r') | |
209 | { | |
210 | break; | |
211 | } | |
212 | ||
213 | /* Notice scaling or direct memory operand modifiers and save them in | |
214 | an O_absent expression after the expression that they modify. */ | |
215 | ||
216 | if (*p == ':') | |
217 | { | |
218 | p++; | |
219 | exp[numexp].X_op = O_absent; | |
220 | if (*p == 'm') | |
221 | { | |
222 | p++; | |
f92f247b | 223 | /* This is a ":m" modifier */ |
f1ce6af4 FF |
224 | exp[numexp].X_add_number = TIC80_OPERAND_M_SI | TIC80_OPERAND_M_LI; |
225 | } | |
226 | else if (*p == 's') | |
227 | { | |
228 | p++; | |
f92f247b | 229 | /* This is a ":s" modifier */ |
f1ce6af4 FF |
230 | exp[numexp].X_add_number = TIC80_OPERAND_SCALED; |
231 | } | |
232 | else | |
233 | { | |
234 | as_bad ("':' not followed by 'm' or 's'"); | |
235 | } | |
236 | numexp++; | |
237 | continue; | |
238 | } | |
239 | ||
240 | /* Handle leading '(' on operands that use them, by recording that we | |
241 | have entered a paren nesting level and then continuing. We complain | |
242 | about multiple nesting. */ | |
243 | ||
244 | if (*p == '(') | |
245 | { | |
246 | if (++parens != 1) | |
247 | { | |
248 | as_bad ("paren nesting"); | |
249 | } | |
250 | p++; | |
251 | continue; | |
252 | } | |
253 | ||
254 | /* Handle trailing ')' on operands that use them, by reducing the | |
255 | nesting level and then continuing. We complain if there were too | |
256 | many closures. */ | |
257 | ||
258 | if (*p == ')') | |
259 | { | |
260 | /* Record that we have left a paren group and continue */ | |
261 | if (--parens < 0) | |
262 | { | |
263 | as_bad ("mismatched parenthesis"); | |
264 | } | |
265 | p++; | |
266 | continue; | |
267 | } | |
268 | ||
269 | /* Begin operand parsing at the current scan point. */ | |
270 | ||
271 | input_line_pointer = p; | |
16171d71 | 272 | expression (&exp[numexp]); |
f1ce6af4 FF |
273 | |
274 | if (exp[numexp].X_op == O_illegal) | |
275 | { | |
276 | as_bad ("illegal operand"); | |
277 | } | |
278 | else if (exp[numexp].X_op == O_absent) | |
279 | { | |
280 | as_bad ("missing operand"); | |
281 | } | |
282 | ||
283 | numexp++; | |
284 | p = input_line_pointer; | |
285 | } | |
286 | ||
287 | if (parens) | |
288 | { | |
289 | exp[numexp].X_op = O_absent; | |
290 | exp[numexp++].X_add_number = TIC80_OPERAND_PARENS; | |
291 | } | |
292 | ||
11e08196 FF |
293 | /* Mark the end of the valid operands with an illegal expression. */ |
294 | exp[numexp].X_op = O_illegal; | |
295 | ||
f1ce6af4 FF |
296 | return (numexp); |
297 | } | |
298 | ||
299 | /* find_opcode() gets a pointer to the entry in the opcode table that | |
300 | matches the instruction being assembled, or returns NULL if no such match | |
301 | is found. | |
302 | ||
303 | First it parses all the operands and save them as expressions. Note that | |
304 | we use O_absent expressions to record additional information about the | |
305 | previous non-O_absent expression, such as ":m" or ":s" modifiers or | |
306 | register numbers enclosed in parens like "(r10)". | |
307 | ||
11e08196 | 308 | It then looks at all opcodes with the same name and uses the operands to |
f1ce6af4 FF |
309 | choose the correct opcode. */ |
310 | ||
f1ce6af4 FF |
311 | static struct tic80_opcode * |
312 | find_opcode (opcode, myops) | |
313 | struct tic80_opcode *opcode; | |
314 | expressionS myops[]; | |
315 | { | |
11e08196 FF |
316 | int numexp; /* Number of expressions from parsing operands */ |
317 | int expi; /* Index of current expression to match */ | |
318 | int opi; /* Index of current operand to match */ | |
319 | int match = 0; /* Set to 1 when an operand match is found */ | |
320 | struct tic80_opcode *opc = opcode; /* Pointer to current opcode table entry */ | |
321 | const struct tic80_opcode *end; /* Pointer to end of opcode table */ | |
322 | ||
323 | /* First parse all the operands so we only have to do it once. There may | |
324 | be more expressions generated than there are operands. */ | |
325 | ||
326 | numexp = get_operands (myops); | |
327 | ||
328 | /* For each opcode with the same name, try to match it against the parsed | |
329 | operands. */ | |
330 | ||
331 | end = tic80_opcodes + tic80_num_opcodes; | |
332 | while (!match && (opc < end) && (strcmp (opc -> name, opcode -> name) == 0)) | |
333 | { | |
334 | /* Start off assuming a match. If we find a mismatch, then this is | |
335 | reset and the operand/expr matching loop terminates with match | |
336 | equal to zero, which allows us to try the next opcode. */ | |
337 | ||
338 | match = 1; | |
339 | ||
340 | /* For each expression, try to match it against the current operand | |
341 | for the current opcode. Upon any mismatch, we abandon further | |
342 | matching for the current opcode table entry. */ | |
f1ce6af4 | 343 | |
11e08196 FF |
344 | for (expi = 0, opi = -1; (expi < numexp) && match; expi++) |
345 | { | |
346 | int bits, flags, X_op, num; | |
f1ce6af4 | 347 | |
11e08196 FF |
348 | X_op = myops[expi].X_op; |
349 | num = myops[expi].X_add_number; | |
f92f247b FF |
350 | |
351 | /* The O_absent expressions apply to the same operand as the most | |
352 | recent non O_absent expression. So only increment the operand | |
353 | index when the current expression is not one of these special | |
354 | expressions. */ | |
355 | ||
11e08196 FF |
356 | if (X_op != O_absent) |
357 | { | |
11e08196 FF |
358 | opi++; |
359 | } | |
f92f247b | 360 | |
11e08196 FF |
361 | flags = tic80_operands[opc -> operands[opi]].flags; |
362 | bits = tic80_operands[opc -> operands[opi]].bits; | |
f1ce6af4 | 363 | |
11e08196 FF |
364 | switch (X_op) |
365 | { | |
366 | case O_register: | |
367 | /* Also check that registers that are supposed to be even actually | |
368 | are even. */ | |
369 | if (((flags & TIC80_OPERAND_GPR) != (num & TIC80_OPERAND_GPR)) || | |
370 | ((flags & TIC80_OPERAND_FPA) != (num & TIC80_OPERAND_FPA)) || | |
371 | ((flags & TIC80_OPERAND_CR) != (num & TIC80_OPERAND_CR)) || | |
372 | ((flags & TIC80_OPERAND_EVEN) && (num & 1)) || | |
373 | const_overflow (num & ~TIC80_OPERAND_MASK, bits, flags)) | |
374 | { | |
375 | match = 0; | |
376 | } | |
377 | break; | |
378 | case O_constant: | |
379 | if ((flags & TIC80_OPERAND_ENDMASK) && (num == 32)) | |
380 | { | |
381 | /* Endmask values of 0 and 32 give identical results */ | |
382 | num = 0; | |
383 | } | |
384 | if ((flags & (TIC80_OPERAND_FPA | TIC80_OPERAND_GPR)) || | |
385 | const_overflow (num, bits, flags)) | |
386 | { | |
387 | match = 0; | |
388 | } | |
389 | break; | |
d160b69e FF |
390 | case O_symbol: |
391 | if ((bits < 32) && (flags & TIC80_OPERAND_PCREL)) | |
392 | { | |
393 | /* For now we only allow PC relative relocations in the | |
394 | short immediate fields, like the TI assembler. | |
395 | FIXME: Should be able to choose "best-fit". */ | |
396 | } | |
ec72a266 | 397 | else if ((bits == 32) /* && (flags & TIC80_OPERAND_BASEREL) */) |
d160b69e FF |
398 | { |
399 | /* For now we only allow base relative relocations in | |
400 | the long immediate fields, like the TI assembler. | |
401 | FIXME: Should be able to choose "best-fit". */ | |
402 | } | |
403 | else | |
404 | { | |
405 | /* Symbols that don't match one of the above cases are | |
406 | rejected as an operand. */ | |
407 | match = 0; | |
408 | } | |
409 | break; | |
11e08196 | 410 | case O_absent: |
f92f247b FF |
411 | /* If this is an O_absent expression, then it may be an expression that |
412 | supplies additional information about the operand, such as ":m" or | |
413 | ":s" modifiers. Check to see that the operand matches this requirement. */ | |
414 | if (!((num & TIC80_OPERAND_M_SI) && (flags & TIC80_OPERAND_M_SI) || | |
415 | (num & TIC80_OPERAND_M_LI) && (flags & TIC80_OPERAND_M_LI) || | |
416 | (num & TIC80_OPERAND_SCALED) && (flags & TIC80_OPERAND_SCALED))) | |
417 | { | |
418 | match = 0; | |
419 | } | |
420 | break; | |
1e12595d FF |
421 | case O_big: |
422 | if ((num > 0) || !(flags & TIC80_OPERAND_FLOAT)) | |
423 | { | |
424 | match = 0; | |
425 | } | |
426 | break; | |
f92f247b | 427 | case O_illegal: |
11e08196 | 428 | case O_symbol_rva: |
11e08196 FF |
429 | case O_uminus: |
430 | case O_bit_not: | |
431 | case O_logical_not: | |
432 | case O_multiply: | |
433 | case O_divide: | |
434 | case O_modulus: | |
435 | case O_left_shift: | |
436 | case O_right_shift: | |
437 | case O_bit_inclusive_or: | |
438 | case O_bit_or_not: | |
439 | case O_bit_exclusive_or: | |
440 | case O_bit_and: | |
441 | case O_add: | |
442 | case O_subtract: | |
443 | case O_eq: | |
444 | case O_ne: | |
445 | case O_lt: | |
446 | case O_le: | |
447 | case O_ge: | |
448 | case O_gt: | |
449 | case O_logical_and: | |
450 | case O_logical_or: | |
451 | case O_max: | |
452 | default: | |
453 | internal_error_a ("unhandled expression type", X_op); | |
454 | } | |
455 | } | |
456 | if (!match) | |
457 | { | |
458 | opc++; | |
459 | } | |
460 | } | |
461 | ||
462 | return (match ? opc : NULL); | |
463 | ||
464 | #if 0 | |
f1ce6af4 FF |
465 | |
466 | /* Now search the opcode table table for one with operands that | |
467 | matches what we've got. */ | |
468 | ||
469 | while (!match) | |
470 | { | |
471 | match = 1; | |
472 | for (i = 0; opcode -> operands[i]; i++) | |
473 | { | |
474 | int flags = tic80_operands[opcode->operands[i]].flags; | |
475 | int X_op = myops[i].X_op; | |
476 | int num = myops[i].X_add_number; | |
477 | ||
478 | if (X_op == 0) | |
479 | { | |
480 | match = 0; | |
481 | break; | |
482 | } | |
483 | ||
11e08196 | 484 | if (flags & (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR)) |
f1ce6af4 FF |
485 | { |
486 | if ((X_op != O_register) || | |
11e08196 FF |
487 | ((flags & TIC80_OPERAND_GPR) != (num & TIC80_OPERAND_GPR)) || |
488 | ((flags & TIC80_OPERAND_FPA) != (num & TIC80_OPERAND_FPA)) || | |
489 | ((flags & TIC80_OPERAND_CR) != (num & TIC80_OPERAND_CR))) | |
f1ce6af4 FF |
490 | { |
491 | match=0; | |
492 | break; | |
493 | } | |
494 | } | |
495 | ||
11e08196 FF |
496 | if (((flags & TIC80_OPERAND_MINUS) && ((X_op != O_absent) || (num != TIC80_OPERAND_MINUS))) || |
497 | ((flags & TIC80_OPERAND_PLUS) && ((X_op != O_absent) || (num != TIC80_OPERAND_PLUS))) || | |
498 | ((flags & TIC80_OPERAND_ATMINUS) && ((X_op != O_absent) || (num != TIC80_OPERAND_ATMINUS))) || | |
499 | ((flags & TIC80_OPERAND_ATPAR) && ((X_op != O_absent) || (num != TIC80_OPERAND_ATPAR))) || | |
500 | ((flags & TIC80_OPERAND_ATSIGN) && ((X_op != O_absent) || (num != TIC80_OPERAND_ATSIGN)))) | |
f1ce6af4 FF |
501 | { |
502 | match=0; | |
503 | break; | |
504 | } | |
505 | } | |
506 | /* we're only done if the operands matched so far AND there | |
507 | are no more to check */ | |
508 | if (match && myops[i].X_op==0) | |
509 | break; | |
510 | else | |
511 | match = 0; | |
512 | ||
513 | next_opcode = opcode+1; | |
514 | if (next_opcode->opcode == 0) | |
515 | break; | |
516 | if (strcmp(next_opcode->name, opcode->name)) | |
517 | break; | |
518 | opcode = next_opcode; | |
519 | } | |
520 | ||
521 | if (!match) | |
522 | { | |
523 | as_bad ("bad opcode or operands"); | |
524 | return (0); | |
525 | } | |
526 | ||
527 | /* Check that all registers that are required to be even are. */ | |
528 | /* Also, if any operands were marked as registers, but were really symbols */ | |
529 | /* fix that here. */ | |
530 | for (i=0; opcode->operands[i]; i++) | |
531 | { | |
11e08196 | 532 | if ((tic80_operands[opcode->operands[i]].flags & TIC80_OPERAND_EVEN) && |
f1ce6af4 | 533 | (myops[i].X_add_number & 1)) |
11e08196 | 534 | as_fatal ("Register number must be EVEN"); |
f1ce6af4 FF |
535 | if (myops[i].X_op == O_register) |
536 | { | |
11e08196 | 537 | if (!(tic80_operands[opcode->operands[i]].flags & TIC80_OPERAND_REG)) |
f1ce6af4 FF |
538 | { |
539 | myops[i].X_op = O_symbol; | |
540 | myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol); | |
541 | myops[i].X_add_number = 0; | |
542 | myops[i].X_op_symbol = NULL; | |
543 | } | |
544 | } | |
545 | } | |
11e08196 FF |
546 | |
547 | #endif | |
f1ce6af4 FF |
548 | } |
549 | ||
550 | /* build_insn takes a pointer to the opcode entry in the opcode table | |
11e08196 | 551 | and the array of operand expressions and writes out the instruction. */ |
f1ce6af4 | 552 | |
11e08196 FF |
553 | static void |
554 | build_insn (opcode, opers) | |
f1ce6af4 FF |
555 | struct tic80_opcode *opcode; |
556 | expressionS *opers; | |
f1ce6af4 | 557 | { |
11e08196 FF |
558 | int expi; /* Index of current expression to match */ |
559 | int opi; /* Index of current operand to match */ | |
560 | unsigned long insn[2]; /* Instruction and long immediate (if any) */ | |
561 | int extended = 0; /* Nonzero if instruction is 8 bytes */ | |
562 | char *f; /* Temporary pointer to output location */ | |
563 | ||
564 | /* Start with the raw opcode bits from the opcode table. */ | |
565 | insn[0] = opcode -> opcode; | |
566 | ||
d160b69e FF |
567 | /* We are going to insert at least one 32 bit opcode so get the |
568 | frag now. */ | |
569 | ||
570 | f = frag_more (4); | |
571 | ||
11e08196 FF |
572 | /* For each operand expression, insert the appropriate bits into the |
573 | instruction . */ | |
574 | for (expi = 0, opi = -1; opers[expi].X_op != O_illegal; expi++) | |
575 | { | |
576 | int bits, shift, flags, X_op, num; | |
577 | ||
578 | X_op = opers[expi].X_op; | |
579 | num = opers[expi].X_add_number; | |
f92f247b FF |
580 | |
581 | /* The O_absent expressions apply to the same operand as the most | |
582 | recent non O_absent expression. So only increment the operand | |
583 | index when the current expression is not one of these special | |
584 | expressions. */ | |
585 | ||
11e08196 FF |
586 | if (X_op != O_absent) |
587 | { | |
11e08196 FF |
588 | opi++; |
589 | } | |
f92f247b | 590 | |
11e08196 FF |
591 | flags = tic80_operands[opcode -> operands[opi]].flags; |
592 | bits = tic80_operands[opcode -> operands[opi]].bits; | |
593 | shift = tic80_operands[opcode -> operands[opi]].shift; | |
594 | ||
595 | switch (X_op) | |
596 | { | |
597 | case O_register: | |
598 | num &= ~TIC80_OPERAND_MASK; | |
599 | insn[0] = insn[0] | (num << shift); | |
600 | break; | |
601 | case O_constant: | |
602 | if ((flags & TIC80_OPERAND_ENDMASK) && (num == 32)) | |
603 | { | |
604 | /* Endmask values of 0 and 32 give identical results */ | |
605 | num = 0; | |
606 | } | |
d160b69e FF |
607 | else if ((flags & TIC80_OPERAND_BITNUM)) |
608 | { | |
609 | /* BITNUM values are stored in one's complement form */ | |
610 | num = (~num & 0x1F); | |
611 | } | |
11e08196 FF |
612 | /* Mask off upper bits, just it case it is signed and is negative */ |
613 | if (bits < 32) | |
614 | { | |
615 | num &= (1 << bits) - 1; | |
616 | insn[0] = insn[0] | (num << shift); | |
617 | } | |
618 | else | |
619 | { | |
620 | extended++; | |
621 | insn[1] = num; | |
622 | } | |
623 | break; | |
d160b69e FF |
624 | case O_symbol: |
625 | if (flags & TIC80_OPERAND_PCREL) | |
626 | { | |
627 | fix_new_exp (frag_now, | |
628 | f - (frag_now -> fr_literal), | |
629 | 4, /* FIXME! how is this used? */ | |
630 | &opers[expi], | |
631 | 1, | |
632 | R_MPPCR); | |
633 | } | |
ec72a266 | 634 | else if (bits == 32) /* was (flags & TIC80_OPERAND_BASEREL) */ |
d160b69e FF |
635 | { |
636 | extended++; | |
637 | fix_new_exp (frag_now, | |
638 | (f + 4) - (frag_now -> fr_literal), | |
639 | 4, | |
640 | &opers[expi], | |
ec72a266 FF |
641 | 0, |
642 | R_RELLONGX); | |
d160b69e FF |
643 | } |
644 | else | |
645 | { | |
ec72a266 | 646 | internal_error ("symbol reloc that is not PC relative or 32 bits"); |
d160b69e FF |
647 | } |
648 | break; | |
11e08196 | 649 | case O_absent: |
f92f247b FF |
650 | /* Each O_absent expression can indicate exactly one possible modifier. */ |
651 | if ((num & TIC80_OPERAND_M_SI) && (flags & TIC80_OPERAND_M_SI)) | |
652 | { | |
653 | insn[0] = insn[0] | (1 << 17); | |
654 | } | |
655 | else if ((num & TIC80_OPERAND_M_LI) && (flags & TIC80_OPERAND_M_LI)) | |
656 | { | |
657 | insn[0] = insn[0] | (1 << 15); | |
658 | } | |
659 | else if ((num & TIC80_OPERAND_SCALED) && (flags & TIC80_OPERAND_SCALED)) | |
660 | { | |
661 | insn[0] = insn[0] | (1 << 11); | |
662 | } | |
663 | else if ((num & TIC80_OPERAND_PARENS) && (flags & TIC80_OPERAND_PARENS)) | |
664 | { | |
665 | /* No code to generate, just accept and discard this expression */ | |
666 | } | |
667 | else | |
668 | { | |
669 | internal_error_a ("unhandled operand modifier", opers[expi].X_add_number); | |
670 | } | |
671 | break; | |
1e12595d FF |
672 | case O_big: |
673 | extended++; | |
674 | { | |
675 | union { | |
676 | unsigned long l; | |
677 | LITTLENUM_TYPE words[10]; | |
678 | } u; | |
679 | gen_to_words (u.words, 2, 8L); /* FIXME: magic numbers */ | |
680 | /* FIXME: More magic, swap the littlenums */ | |
681 | u.words[2] = u.words[0]; | |
682 | u.words[0] = u.words [1]; | |
683 | u.words[1] = u.words [2]; | |
684 | insn[1] = u.l; | |
685 | } | |
686 | break; | |
f92f247b | 687 | case O_illegal: |
11e08196 | 688 | case O_symbol_rva: |
11e08196 FF |
689 | case O_uminus: |
690 | case O_bit_not: | |
691 | case O_logical_not: | |
692 | case O_multiply: | |
693 | case O_divide: | |
694 | case O_modulus: | |
695 | case O_left_shift: | |
696 | case O_right_shift: | |
697 | case O_bit_inclusive_or: | |
698 | case O_bit_or_not: | |
699 | case O_bit_exclusive_or: | |
700 | case O_bit_and: | |
701 | case O_add: | |
702 | case O_subtract: | |
703 | case O_eq: | |
704 | case O_ne: | |
705 | case O_lt: | |
706 | case O_le: | |
707 | case O_ge: | |
708 | case O_gt: | |
709 | case O_logical_and: | |
710 | case O_logical_or: | |
711 | case O_max: | |
712 | default: | |
713 | internal_error_a ("unhandled expression", X_op); | |
714 | break; | |
715 | } | |
716 | } | |
717 | ||
718 | /* Write out the instruction, either 4 or 8 bytes. */ | |
719 | ||
11e08196 FF |
720 | md_number_to_chars (f, insn[0], 4); |
721 | if (extended) | |
722 | { | |
723 | f = frag_more (4); | |
724 | md_number_to_chars (f, insn[1], 4); | |
725 | } | |
f1ce6af4 FF |
726 | } |
727 | ||
16171d71 FF |
728 | /* This is the main entry point for the machine-dependent assembler. Gas |
729 | calls this function for each input line which does not contain a | |
730 | pseudoop. | |
731 | ||
732 | STR points to a NULL terminated machine dependent instruction. This | |
733 | function is supposed to emit the frags/bytes it assembles to. */ | |
f1ce6af4 FF |
734 | |
735 | void | |
736 | md_assemble (str) | |
737 | char *str; | |
738 | { | |
739 | char *scan; | |
740 | unsigned char *input_line_save; | |
741 | struct tic80_opcode *opcode; | |
11e08196 | 742 | expressionS myops[16]; |
f1ce6af4 FF |
743 | unsigned long insn; |
744 | ||
745 | /* Ensure there is something there to assemble. */ | |
746 | assert (str); | |
747 | ||
748 | /* Drop any leading whitespace. */ | |
749 | while (isspace (*str)) | |
750 | { | |
751 | str++; | |
752 | } | |
753 | ||
754 | /* Isolate the mnemonic from the rest of the string by finding the first | |
755 | whitespace character and zapping it to a null byte. */ | |
756 | for (scan = str; *scan != '\000' && !isspace (*scan); scan++) {;} | |
757 | if (*scan != '\000') | |
758 | { | |
759 | *scan++ = '\000'; | |
760 | } | |
761 | ||
762 | /* Try to find this mnemonic in the hash table */ | |
763 | if ((opcode = (struct tic80_opcode *) hash_find (tic80_hash, str)) == NULL) | |
764 | { | |
765 | as_bad ("Invalid mnemonic: '%s'", str); | |
766 | return; | |
767 | } | |
768 | ||
769 | str = scan; | |
770 | while (isspace (*scan)) | |
771 | { | |
772 | scan++; | |
773 | } | |
774 | ||
775 | input_line_save = input_line_pointer; | |
776 | input_line_pointer = str; | |
777 | ||
778 | opcode = find_opcode (opcode, myops); | |
779 | if (opcode == NULL) | |
780 | { | |
11e08196 | 781 | as_bad ("Invalid operands: '%s'", input_line_save); |
f1ce6af4 FF |
782 | } |
783 | ||
784 | input_line_pointer = input_line_save; | |
11e08196 | 785 | build_insn (opcode, myops); |
f1ce6af4 FF |
786 | } |
787 | ||
16171d71 FF |
788 | /* This function is called once at the start of assembly, after the command |
789 | line arguments have been parsed and all the machine independent | |
790 | initializations have been completed. | |
791 | ||
792 | It should set up all the tables, etc., that the machine dependent part of | |
793 | the assembler will need. */ | |
f1ce6af4 FF |
794 | |
795 | void | |
796 | md_begin () | |
797 | { | |
798 | char *prev_name = ""; | |
799 | register const struct tic80_opcode *op; | |
800 | register const struct tic80_opcode *op_end; | |
16171d71 | 801 | const struct predefined_symbol *pdsp; |
f1ce6af4 | 802 | |
16171d71 | 803 | tic80_hash = hash_new (); |
f1ce6af4 FF |
804 | |
805 | /* Insert unique names into hash table. The TIc80 instruction set | |
806 | has many identical opcode names that have different opcodes based | |
807 | on the operands. This hash table then provides a quick index to | |
808 | the first opcode with a particular name in the opcode table. */ | |
809 | ||
810 | op_end = tic80_opcodes + tic80_num_opcodes; | |
811 | for (op = tic80_opcodes; op < op_end; op++) | |
812 | { | |
813 | if (strcmp (prev_name, op -> name) != 0) | |
814 | { | |
815 | prev_name = (char *) op -> name; | |
816 | hash_insert (tic80_hash, op -> name, (char *) op); | |
817 | } | |
818 | } | |
16171d71 FF |
819 | |
820 | /* Insert the predefined symbols into the symbol table. We use symbol_create | |
821 | rather than symbol_new so that these symbols don't end up in the object | |
822 | files' symbol table. Note that the values of the predefined symbols include | |
823 | some upper bits that distinguish the type of the symbol (register, bitnum, | |
824 | condition code, etc) and these bits must be masked away before actually | |
825 | inserting the values into the instruction stream. For registers we put | |
826 | these bits in the symbol table since we use them later and there is no | |
827 | question that they aren't part of the register number. For constants we | |
828 | can't do that since the constant can be any value, so they are masked off | |
829 | before putting them into the symbol table. */ | |
830 | ||
831 | pdsp = NULL; | |
832 | while ((pdsp = tic80_next_predefined_symbol (pdsp)) != NULL) | |
833 | { | |
834 | segT segment; | |
835 | valueT valu; | |
836 | int symtype; | |
837 | ||
838 | symtype = PDS_VALUE (pdsp) & TIC80_OPERAND_MASK; | |
839 | switch (symtype) | |
840 | { | |
841 | case TIC80_OPERAND_GPR: | |
842 | case TIC80_OPERAND_FPA: | |
843 | case TIC80_OPERAND_CR: | |
844 | segment = reg_section; | |
845 | valu = PDS_VALUE (pdsp); | |
846 | break; | |
847 | case TIC80_OPERAND_CC: | |
848 | case TIC80_OPERAND_BITNUM: | |
849 | segment = absolute_section; | |
850 | valu = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK; | |
851 | break; | |
852 | default: | |
853 | internal_error_a ("unhandled predefined symbol bits", symtype); | |
854 | break; | |
855 | } | |
856 | symbol_table_insert (symbol_create (PDS_NAME (pdsp), segment, valu, | |
857 | &zero_address_frag)); | |
858 | } | |
f1ce6af4 FF |
859 | } |
860 | ||
861 | \f | |
862 | ||
16171d71 FF |
863 | /* The assembler adds md_shortopts to the string passed to getopt. */ |
864 | ||
f1ce6af4 FF |
865 | CONST char *md_shortopts = ""; |
866 | ||
16171d71 FF |
867 | /* The assembler adds md_longopts to the machine independent long options |
868 | that are passed to getopt. */ | |
869 | ||
f1ce6af4 FF |
870 | struct option md_longopts[] = { |
871 | {NULL, no_argument, NULL, 0} | |
872 | }; | |
873 | ||
874 | size_t md_longopts_size = sizeof(md_longopts); | |
875 | ||
16171d71 FF |
876 | /* The md_parse_option function will be called whenever getopt returns an |
877 | unrecognized code, presumably indicating a special code value which | |
878 | appears in md_longopts for machine specific command line options. */ | |
f1ce6af4 FF |
879 | |
880 | int | |
881 | md_parse_option (c, arg) | |
882 | int c; | |
883 | char *arg; | |
884 | { | |
885 | return (0); | |
886 | } | |
887 | ||
16171d71 FF |
888 | /* The md_show_usage function will be called whenever a usage message is |
889 | printed. It should print a description of the machine specific options | |
890 | found in md_longopts. */ | |
f1ce6af4 FF |
891 | |
892 | void | |
893 | md_show_usage (stream) | |
894 | FILE *stream; | |
895 | { | |
896 | } | |
897 | ||
898 | \f | |
899 | /* Attempt to simplify or even eliminate a fixup. The return value is | |
900 | ignored; perhaps it was once meaningful, but now it is historical. | |
901 | To indicate that a fixup has been eliminated, set fixP->fx_done. | |
902 | */ | |
903 | ||
904 | void | |
905 | md_apply_fix (fixP, val) | |
906 | fixS *fixP; | |
907 | long val; | |
908 | { | |
d160b69e FF |
909 | char *dest = fixP -> fx_frag -> fr_literal + fixP -> fx_where; |
910 | ||
911 | switch (fixP -> fx_r_type) | |
912 | { | |
913 | case R_RELLONGX: | |
914 | md_number_to_chars (dest, (valueT) val, 4); | |
915 | break; | |
916 | case R_MPPCR: | |
917 | /* FIXME! - should check for overflow of the 15 bit field */ | |
918 | *dest++ = val >> 2; | |
919 | *dest = (*dest & 0x80) | val >> 10; | |
920 | break; | |
b16a8c8e FF |
921 | case R_ABS: |
922 | md_number_to_chars (dest, (valueT) val, fixP -> fx_size); | |
923 | break; | |
d160b69e FF |
924 | default: |
925 | internal_error_a ("unhandled relocation type in fixup", fixP -> fx_r_type); | |
926 | break; | |
927 | } | |
f1ce6af4 FF |
928 | } |
929 | ||
930 | \f | |
931 | /* Functions concerning relocs. */ | |
932 | ||
933 | /* The location from which a PC relative jump should be calculated, | |
d160b69e FF |
934 | given a PC relative reloc. |
935 | ||
936 | For the TIc80, this is the address of the 32 bit opcode containing | |
937 | the PC relative field. */ | |
f1ce6af4 FF |
938 | |
939 | long | |
940 | md_pcrel_from (fixP) | |
941 | fixS *fixP; | |
942 | { | |
d160b69e | 943 | return (fixP -> fx_frag -> fr_address + fixP -> fx_where) ; |
f1ce6af4 FF |
944 | } |
945 | ||
946 | /* | |
947 | * Called after relax() is finished. | |
948 | * In: Address of frag. | |
949 | * fr_type == rs_machine_dependent. | |
950 | * fr_subtype is what the address relaxed to. | |
951 | * | |
952 | * Out: Any fixSs and constants are set up. | |
953 | * Caller will turn frag into a ".space 0". | |
954 | */ | |
955 | ||
956 | void | |
957 | md_convert_frag (headers, seg, fragP) | |
958 | object_headers *headers; | |
959 | segT seg; | |
960 | fragS *fragP; | |
961 | { | |
11e08196 | 962 | internal_error ("md_convert_frag() not implemented yet"); |
f1ce6af4 FF |
963 | abort (); |
964 | } | |
965 | ||
966 | \f | |
967 | /*ARGSUSED*/ | |
968 | void | |
969 | tc_coff_symbol_emit_hook (ignore) | |
970 | symbolS *ignore; | |
971 | { | |
972 | } | |
973 | ||
974 | #if defined OBJ_COFF | |
975 | ||
976 | short | |
977 | tc_coff_fix2rtype (fixP) | |
978 | fixS *fixP; | |
979 | { | |
d160b69e | 980 | return (fixP -> fx_r_type); |
f1ce6af4 FF |
981 | } |
982 | ||
983 | #endif /* OBJ_COFF */ | |
984 | ||
64556643 | 985 | /* end of tc-tic80.c */ |