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Adds support for generating notes in V850 binaries.
[deliverable/binutils-gdb.git] / gas / config / tc-v850.c
CommitLineData
252b5132 1/* tc-v850.c -- Assembler code for the NEC V850
b90efa5b 2 Copyright (C) 1996-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
4b4da160
NC		 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
19 Boston, MA 02110-1301, USA. */
252b5132 20
252b5132 21#include "as.h"
3882b010 22#include "safe-ctype.h"
28e4f854 23#include "subsegs.h"
252b5132 24#include "opcode/v850.h"
a8761a19 25#include "dwarf2dbg.h"
252b5132 26
28e4f854
KH		 27/* Sign-extend a 16-bit number. */
28#define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000)
252b5132 29
252b5132 30/* Set to TRUE if we want to be pedantic about signed overflows. */
b34976b6
AM		 31static bfd_boolean warn_signed_overflows = FALSE;
32static bfd_boolean warn_unsigned_overflows = FALSE;
252b5132 33
685080f2
NC		 34/* Non-zero if floating point insns are not being used. */
35static signed int soft_float = -1;
36
252b5132 37/* Indicates the target BFD machine number. */
28e4f854 38static int machine = -1;
252b5132 39
de863c74
NC		 40
41/* Indiciates the target BFD architecture. */
42int v850_target_arch = bfd_arch_v850_rh850;
43const char * v850_target_format = "elf32-v850-rh850";
44static flagword v850_e_flags = 0;
45
252b5132 46/* Indicates the target processor(s) for the assemble. */
1cd986c5 47static int processor_mask = 0;
252b5132
RH		 48\f
49/* Structure to hold information about predefined registers. */
ea1562b3
NC		 50struct reg_name
51{
28e4f854
KH		 52 const char *name;
53 int value;
1cd986c5 54 unsigned int processors;
252b5132
RH		 55};
56
28e4f854
KH		 57/* Generic assembler global variables which must be defined by all
58 targets. */
252b5132 59
28e4f854 60/* Characters which always start a comment. */
252b5132
RH		 61const char comment_chars[] = "#";
62
63/* Characters which start a comment at the beginning of a line. */
64const char line_comment_chars[] = ";#";
65
28e4f854 66/* Characters which may be used to separate multiple commands on a
252b5132
RH		 67 single line. */
68const char line_separator_chars[] = ";";
69
28e4f854 70/* Characters which are used to indicate an exponent in a floating
252b5132
RH		 71 point number. */
72const char EXP_CHARS[] = "eE";
73
28e4f854 74/* Characters which mean that a number is a floating point constant,
252b5132
RH		 75 as in 0d1.0. */
76const char FLT_CHARS[] = "dD";
77\f
ea1562b3
NC		 78const relax_typeS md_relax_table[] =
79{
1cd986c5
NC		 80 /* Conditional branches.(V850/V850E, max 22bit) */
81#define SUBYPTE_COND_9_22 0
82 {0xfe, -0x100, 2, SUBYPTE_COND_9_22 + 1},
83 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
84 /* Conditional branches.(V850/V850E, max 22bit) */
85#define SUBYPTE_SA_9_22 2
86 {0xfe, -0x100, 2, SUBYPTE_SA_9_22 + 1},
87 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
88 /* Unconditional branches.(V850/V850E, max 22bit) */
89#define SUBYPTE_UNCOND_9_22 4
90 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22 + 1},
91 {0x1ffffe, -0x200000, 4, 0},
92 /* Conditional branches.(V850E2, max 32bit) */
93#define SUBYPTE_COND_9_22_32 6
94 {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32 + 1},
95 {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32 + 2},
96 {0x7ffffffe, -0x80000000, 8, 0},
97 /* Conditional branches.(V850E2, max 32bit) */
98#define SUBYPTE_SA_9_22_32 9
99 {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32 + 1},
100 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32 + 2},
101 {0x7ffffffe, -0x80000000, 10, 0},
102 /* Unconditional branches.(V850E2, max 32bit) */
103#define SUBYPTE_UNCOND_9_22_32 12
104 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32 + 1},
105 {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32 + 2},
106 {0x7ffffffe, -0x80000000, 6, 0},
107 /* Conditional branches.(V850E2R max 22bit) */
108#define SUBYPTE_COND_9_17_22 15
109 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22 + 1},
110 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22 + 2},
111 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
112 /* Conditional branches.(V850E2R max 22bit) */
113#define SUBYPTE_SA_9_17_22 18
114 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22 + 1},
115 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22 + 2},
116 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
117 /* Conditional branches.(V850E2R max 32bit) */
118#define SUBYPTE_COND_9_17_22_32 21
119 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32 + 1},
120 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32 + 2},
121 {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32 + 3},
122 {0x7ffffffe, -0x80000000, 8, 0},
123 /* Conditional branches.(V850E2R max 32bit) */
124#define SUBYPTE_SA_9_17_22_32 25
125 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32 + 1},
126 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32 + 2},
127 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3},
128 {0x7ffffffe, -0x80000000, 10, 0},
78c8d46c
NC		 129 /* Loop. (V850E2V4_UP, max 22-bit). */
130#define SUBYPTE_LOOP_16_22 29
131 {0x0, -0x0fffe, 4, SUBYPTE_LOOP_16_22 + 1},
132 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
252b5132
RH		 133};
134
1cd986c5
NC		 135static int v850_relax = 0;
136
137/* Default branch disp size 22 or 32. */
138static int default_disp_size = 22;
139
140/* Default no using bcond17. */
141static int no_bcond17 = 0;
142
143/* Default no using ld/st 23bit offset. */
144static int no_stld23 = 0;
86aba9db 145
28e4f854 146/* Fixups. */
ea1562b3
NC		 147#define MAX_INSN_FIXUPS 5
148
149struct v850_fixup
150{
28e4f854
KH		 151 expressionS exp;
152 int opindex;
252b5132
RH		 153 bfd_reloc_code_real_type reloc;
154};
155
28e4f854 156struct v850_fixup fixups[MAX_INSN_FIXUPS];
252b5132 157static int fc;
252b5132 158
9e0665bc 159struct v850_seg_entry
252b5132 160{
9e0665bc
AM		 161 segT s;
162 const char *name;
163 flagword flags;
164};
252b5132 165
9e0665bc 166struct v850_seg_entry v850_seg_table[] =
252b5132 167{
9e0665bc
AM		 168 { NULL, ".sdata",
169 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
170 | SEC_SMALL_DATA },
171 { NULL, ".tdata",
172 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
173 { NULL, ".zdata",
174 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
175 { NULL, ".sbss",
176 SEC_ALLOC | SEC_SMALL_DATA },
177 { NULL, ".tbss",
178 SEC_ALLOC },
179 { NULL, ".zbss",
180 SEC_ALLOC},
181 { NULL, ".rosdata",
182 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA
183 | SEC_HAS_CONTENTS | SEC_SMALL_DATA },
184 { NULL, ".rozdata",
185 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA
186 | SEC_HAS_CONTENTS },
187 { NULL, ".scommon",
188 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
189 | SEC_SMALL_DATA | SEC_IS_COMMON },
190 { NULL, ".tcommon",
191 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
192 | SEC_IS_COMMON },
193 { NULL, ".zcommon",
194 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
195 | SEC_IS_COMMON },
196 { NULL, ".call_table_data",
197 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
198 { NULL, ".call_table_text",
199 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_CODE
200 | SEC_HAS_CONTENTS},
201 { NULL, ".bss",
202 SEC_ALLOC }
203};
28e4f854 204
9e0665bc
AM		 205#define SDATA_SECTION 0
206#define TDATA_SECTION 1
207#define ZDATA_SECTION 2
208#define SBSS_SECTION 3
209#define TBSS_SECTION 4
210#define ZBSS_SECTION 5
211#define ROSDATA_SECTION 6
212#define ROZDATA_SECTION 7
213#define SCOMMON_SECTION 8
214#define TCOMMON_SECTION 9
215#define ZCOMMON_SECTION 10
216#define CALL_TABLE_DATA_SECTION 11
217#define CALL_TABLE_TEXT_SECTION 12
218#define BSS_SECTION 13
219
9e0665bc 220static void
ea1562b3 221do_v850_seg (int i, subsegT sub)
252b5132 222{
9e0665bc 223 struct v850_seg_entry *seg = v850_seg_table + i;
28e4f854 224
28e4f854 225 obj_elf_section_change_hook ();
ea1562b3 226
9e0665bc 227 if (seg->s != NULL)
ea1562b3 228 subseg_set (seg->s, sub);
9e0665bc
AM		 229 else
230 {
231 seg->s = subseg_new (seg->name, sub);
232 bfd_set_section_flags (stdoutput, seg->s, seg->flags);
233 if ((seg->flags & SEC_LOAD) == 0)
234 seg_info (seg->s)->bss = 1;
235 }
252b5132
RH		 236}
237
9e0665bc 238static void
ea1562b3 239v850_seg (int i)
252b5132 240{
9e0665bc 241 subsegT sub = get_absolute_expression ();
28e4f854 242
9e0665bc 243 do_v850_seg (i, sub);
252b5132
RH		 244 demand_empty_rest_of_line ();
245}
246
9e0665bc 247static void
ea1562b3 248v850_offset (int ignore ATTRIBUTE_UNUSED)
252b5132 249{
825487fa 250 char *pfrag;
252b5132 251 int temp = get_absolute_expression ();
685736be 252
825487fa 253 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, (symbolS *)0,
ec178e1b 254 (offsetT) temp, (char *) 0);
825487fa 255 *pfrag = 0;
28e4f854 256
252b5132
RH		 257 demand_empty_rest_of_line ();
258}
259
28e4f854
KH		 260/* Copied from obj_elf_common() in gas/config/obj-elf.c. */
261
252b5132 262static void
ea1562b3 263v850_comm (int area)
252b5132 264{
28e4f854
KH		 265 char *name;
266 char c;
267 char *p;
268 int temp;
269 unsigned int size;
270 symbolS *symbolP;
271 int have_align;
252b5132
RH		 272
273 name = input_line_pointer;
274 c = get_symbol_end ();
28e4f854
KH		 275
276 /* Just after name is now '\0'. */
252b5132
RH		 277 p = input_line_pointer;
278 *p = c;
28e4f854 279
252b5132 280 SKIP_WHITESPACE ();
28e4f854 281
252b5132
RH		 282 if (*input_line_pointer != ',')
283 {
284 as_bad (_("Expected comma after symbol-name"));
285 ignore_rest_of_line ();
286 return;
287 }
28e4f854
KH		 288
289 /* Skip ','. */
290 input_line_pointer++;
291
252b5132
RH		 292 if ((temp = get_absolute_expression ()) < 0)
293 {
28e4f854 294 /* xgettext:c-format */
252b5132
RH		 295 as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp);
296 ignore_rest_of_line ();
297 return;
298 }
28e4f854 299
252b5132
RH		 300 size = temp;
301 *p = 0;
302 symbolP = symbol_find_or_make (name);
303 *p = c;
28e4f854 304
252b5132
RH		 305 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
306 {
307 as_bad (_("Ignoring attempt to re-define symbol"));
308 ignore_rest_of_line ();
309 return;
310 }
28e4f854 311
252b5132
RH		 312 if (S_GET_VALUE (symbolP) != 0)
313 {
314 if (S_GET_VALUE (symbolP) != size)
ea1562b3
NC		 315 /* xgettext:c-format */
316 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
317 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
252b5132 318 }
28e4f854
KH		 319
320 know (symbol_get_frag (symbolP) == &zero_address_frag);
321
252b5132
RH		 322 if (*input_line_pointer != ',')
323 have_align = 0;
324 else
325 {
326 have_align = 1;
327 input_line_pointer++;
328 SKIP_WHITESPACE ();
329 }
28e4f854 330
252b5132
RH		 331 if (! have_align || *input_line_pointer != '"')
332 {
333 if (! have_align)
334 temp = 0;
335 else
336 {
337 temp = get_absolute_expression ();
28e4f854 338
252b5132
RH		 339 if (temp < 0)
340 {
341 temp = 0;
342 as_warn (_("Common alignment negative; 0 assumed"));
343 }
344 }
28e4f854 345
cac58fa6 346 if (symbol_get_obj (symbolP)->local)
252b5132 347 {
28e4f854
KH		 348 segT old_sec;
349 int old_subsec;
350 char *pfrag;
351 int align;
352 flagword applicable;
252b5132
RH		 353
354 old_sec = now_seg;
355 old_subsec = now_subseg;
28e4f854 356
252b5132 357 applicable = bfd_applicable_section_flags (stdoutput);
28e4f854 358
252b5132 359 applicable &= SEC_ALLOC;
28e4f854 360
252b5132
RH		 361 switch (area)
362 {
9e0665bc
AM		 363 case SCOMMON_SECTION:
364 do_v850_seg (SBSS_SECTION, 0);
252b5132 365 break;
28e4f854 366
9e0665bc
AM		 367 case ZCOMMON_SECTION:
368 do_v850_seg (ZBSS_SECTION, 0);
252b5132 369 break;
28e4f854 370
9e0665bc
AM		 371 case TCOMMON_SECTION:
372 do_v850_seg (TBSS_SECTION, 0);
252b5132
RH		 373 break;
374 }
375
376 if (temp)
377 {
28e4f854 378 /* Convert to a power of 2 alignment. */
252b5132
RH		 379 for (align = 0; (temp & 1) == 0; temp >>= 1, ++align)
380 ;
28e4f854 381
252b5132
RH		 382 if (temp != 1)
383 {
384 as_bad (_("Common alignment not a power of 2"));
385 ignore_rest_of_line ();
386 return;
387 }
388 }
389 else
390 align = 0;
28e4f854 391
9e0665bc 392 record_alignment (now_seg, align);
28e4f854 393
252b5132
RH		 394 if (align)
395 frag_align (align, 0, 0);
396
397 switch (area)
398 {
9e0665bc
AM		 399 case SCOMMON_SECTION:
400 if (S_GET_SEGMENT (symbolP) == v850_seg_table[SBSS_SECTION].s)
7dcc9865 401 symbol_get_frag (symbolP)->fr_symbol = 0;
252b5132
RH		 402 break;
403
9e0665bc
AM		 404 case ZCOMMON_SECTION:
405 if (S_GET_SEGMENT (symbolP) == v850_seg_table[ZBSS_SECTION].s)
7dcc9865 406 symbol_get_frag (symbolP)->fr_symbol = 0;
252b5132
RH		 407 break;
408
9e0665bc
AM		 409 case TCOMMON_SECTION:
410 if (S_GET_SEGMENT (symbolP) == v850_seg_table[TBSS_SECTION].s)
7dcc9865 411 symbol_get_frag (symbolP)->fr_symbol = 0;
252b5132
RH		 412 break;
413
414 default:
cac58fa6 415 abort ();
252b5132 416 }
28e4f854 417
7dcc9865 418 symbol_set_frag (symbolP, frag_now);
252b5132
RH		 419 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
420 (offsetT) size, (char *) 0);
421 *pfrag = 0;
422 S_SET_SIZE (symbolP, size);
28e4f854 423
252b5132
RH		 424 switch (area)
425 {
9e0665bc
AM		 426 case SCOMMON_SECTION:
427 S_SET_SEGMENT (symbolP, v850_seg_table[SBSS_SECTION].s);
252b5132 428 break;
28e4f854 429
9e0665bc
AM		 430 case ZCOMMON_SECTION:
431 S_SET_SEGMENT (symbolP, v850_seg_table[ZBSS_SECTION].s);
252b5132 432 break;
28e4f854 433
9e0665bc
AM		 434 case TCOMMON_SECTION:
435 S_SET_SEGMENT (symbolP, v850_seg_table[TBSS_SECTION].s);
252b5132 436 break;
28e4f854 437
252b5132 438 default:
28e4f854 439 abort ();
252b5132 440 }
28e4f854 441
252b5132 442 S_CLEAR_EXTERNAL (symbolP);
28e4f854 443 obj_elf_section_change_hook ();
252b5132
RH		 444 subseg_set (old_sec, old_subsec);
445 }
446 else
447 {
ec178e1b
AM		 448 segT old_sec;
449 int old_subsec;
86aba9db 450
252b5132 451 allocate_common:
ec178e1b
AM		 452 old_sec = now_seg;
453 old_subsec = now_subseg;
86aba9db 454
252b5132
RH		 455 S_SET_VALUE (symbolP, (valueT) size);
456 S_SET_ALIGN (symbolP, temp);
457 S_SET_EXTERNAL (symbolP);
28e4f854 458
252b5132
RH		 459 switch (area)
460 {
9e0665bc
AM		 461 case SCOMMON_SECTION:
462 case ZCOMMON_SECTION:
463 case TCOMMON_SECTION:
464 do_v850_seg (area, 0);
465 S_SET_SEGMENT (symbolP, v850_seg_table[area].s);
252b5132 466 break;
28e4f854 467
252b5132 468 default:
28e4f854 469 abort ();
252b5132 470 }
86aba9db
NC		 471
472 obj_elf_section_change_hook ();
473 subseg_set (old_sec, old_subsec);
252b5132
RH		 474 }
475 }
476 else
477 {
478 input_line_pointer++;
28e4f854 479
252b5132
RH		 480 /* @@ Some use the dot, some don't. Can we get some consistency?? */
481 if (*input_line_pointer == '.')
482 input_line_pointer++;
28e4f854 483
252b5132
RH		 484 /* @@ Some say data, some say bss. */
485 if (strncmp (input_line_pointer, "bss\"", 4)
486 && strncmp (input_line_pointer, "data\"", 5))
487 {
488 while (*--input_line_pointer != '"')
489 ;
490 input_line_pointer--;
491 goto bad_common_segment;
492 }
ea1562b3 493
252b5132
RH		 494 while (*input_line_pointer++ != '"')
495 ;
ea1562b3 496
252b5132
RH		 497 goto allocate_common;
498 }
499
fed9b18a 500 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
252b5132
RH		 501
502 demand_empty_rest_of_line ();
503 return;
504
505 {
506 bad_common_segment:
507 p = input_line_pointer;
508 while (*p && *p != '\n')
509 p++;
510 c = *p;
511 *p = '\0';
512 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
513 *p = c;
514 input_line_pointer = p;
515 ignore_rest_of_line ();
516 return;
517 }
518}
519
9e0665bc 520static void
ea1562b3 521set_machine (int number)
252b5132
RH		 522{
523 machine = number;
de863c74 524 bfd_set_arch_mach (stdoutput, v850_target_arch, machine);
252b5132
RH		 525
526 switch (machine)
527 {
1cd986c5
NC		 528 case 0: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break;
529 case bfd_mach_v850: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break;
530 case bfd_mach_v850e: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break;
531 case bfd_mach_v850e1: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break;
532 case bfd_mach_v850e2: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); break;
533 case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break;
78c8d46c 534 case bfd_mach_v850e3v5: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); break;
252b5132
RH		 535 }
536}
537
86aba9db 538static void
ea1562b3 539v850_longcode (int type)
86aba9db
NC		 540{
541 expressionS ex;
542
543 if (! v850_relax)
544 {
545 if (type == 1)
20203fb9 546 as_warn (_(".longcall pseudo-op seen when not relaxing"));
86aba9db 547 else
20203fb9 548 as_warn (_(".longjump pseudo-op seen when not relaxing"));
86aba9db
NC		 549 }
550
551 expression (&ex);
552
553 if (ex.X_op != O_symbol || ex.X_add_number != 0)
554 {
20203fb9 555 as_bad (_("bad .longcall format"));
86aba9db
NC		 556 ignore_rest_of_line ();
557
558 return;
559 }
560
ec178e1b 561 if (type == 1)
86aba9db
NC		 562 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1,
563 BFD_RELOC_V850_LONGCALL);
564 else
565 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1,
566 BFD_RELOC_V850_LONGJUMP);
567
568 demand_empty_rest_of_line ();
569}
570
252b5132 571/* The target specific pseudo-ops which we support. */
77c6dd37
NC		 572const pseudo_typeS md_pseudo_table[] =
573{
9e0665bc
AM		 574 { "sdata", v850_seg, SDATA_SECTION },
575 { "tdata", v850_seg, TDATA_SECTION },
576 { "zdata", v850_seg, ZDATA_SECTION },
577 { "sbss", v850_seg, SBSS_SECTION },
578 { "tbss", v850_seg, TBSS_SECTION },
579 { "zbss", v850_seg, ZBSS_SECTION },
580 { "rosdata", v850_seg, ROSDATA_SECTION },
581 { "rozdata", v850_seg, ROZDATA_SECTION },
582 { "bss", v850_seg, BSS_SECTION },
583 { "offset", v850_offset, 0 },
584 { "word", cons, 4 },
585 { "zcomm", v850_comm, ZCOMMON_SECTION },
586 { "scomm", v850_comm, SCOMMON_SECTION },
587 { "tcomm", v850_comm, TCOMMON_SECTION },
588 { "v850", set_machine, 0 },
589 { "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION },
590 { "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION },
591 { "v850e", set_machine, bfd_mach_v850e },
1cd986c5
NC		 592 { "v850e1", set_machine, bfd_mach_v850e1 },
593 { "v850e2", set_machine, bfd_mach_v850e2 },
594 { "v850e2v3", set_machine, bfd_mach_v850e2v3 },
78c8d46c
NC		 595 { "v850e2v4", set_machine, bfd_mach_v850e3v5 },
596 { "v850e3v5", set_machine, bfd_mach_v850e3v5 },
ec178e1b
AM		 597 { "longcall", v850_longcode, 1 },
598 { "longjump", v850_longcode, 2 },
9e0665bc 599 { NULL, NULL, 0 }
252b5132
RH		 600};
601
602/* Opcode hash table. */
603static struct hash_control *v850_hash;
604
28e4f854 605/* This table is sorted. Suitable for searching by a binary search. */
77c6dd37
NC		 606static const struct reg_name pre_defined_registers[] =
607{
1cd986c5
NC		 608 { "ep", 30, PROCESSOR_ALL }, /* ep - element ptr. */
609 { "gp", 4, PROCESSOR_ALL }, /* gp - global ptr. */
610 { "hp", 2, PROCESSOR_ALL }, /* hp - handler stack ptr. */
611 { "lp", 31, PROCESSOR_ALL }, /* lp - link ptr. */
612 { "r0", 0, PROCESSOR_ALL },
613 { "r1", 1, PROCESSOR_ALL },
614 { "r10", 10, PROCESSOR_ALL },
615 { "r11", 11, PROCESSOR_ALL },
616 { "r12", 12, PROCESSOR_ALL },
617 { "r13", 13, PROCESSOR_ALL },
618 { "r14", 14, PROCESSOR_ALL },
619 { "r15", 15, PROCESSOR_ALL },
620 { "r16", 16, PROCESSOR_ALL },
621 { "r17", 17, PROCESSOR_ALL },
622 { "r18", 18, PROCESSOR_ALL },
623 { "r19", 19, PROCESSOR_ALL },
624 { "r2", 2, PROCESSOR_ALL },
625 { "r20", 20, PROCESSOR_ALL },
626 { "r21", 21, PROCESSOR_ALL },
627 { "r22", 22, PROCESSOR_ALL },
628 { "r23", 23, PROCESSOR_ALL },
629 { "r24", 24, PROCESSOR_ALL },
630 { "r25", 25, PROCESSOR_ALL },
631 { "r26", 26, PROCESSOR_ALL },
632 { "r27", 27, PROCESSOR_ALL },
633 { "r28", 28, PROCESSOR_ALL },
634 { "r29", 29, PROCESSOR_ALL },
635 { "r3", 3, PROCESSOR_ALL },
636 { "r30", 30, PROCESSOR_ALL },
637 { "r31", 31, PROCESSOR_ALL },
638 { "r4", 4, PROCESSOR_ALL },
639 { "r5", 5, PROCESSOR_ALL },
640 { "r6", 6, PROCESSOR_ALL },
641 { "r7", 7, PROCESSOR_ALL },
642 { "r8", 8, PROCESSOR_ALL },
643 { "r9", 9, PROCESSOR_ALL },
644 { "sp", 3, PROCESSOR_ALL }, /* sp - stack ptr. */
645 { "tp", 5, PROCESSOR_ALL }, /* tp - text ptr. */
646 { "zero", 0, PROCESSOR_ALL },
252b5132 647};
252b5132 648
28e4f854
KH		 649#define REG_NAME_CNT \
650 (sizeof (pre_defined_registers) / sizeof (struct reg_name))
252b5132 651
77c6dd37
NC		 652static const struct reg_name system_registers[] =
653{
1cd986c5
NC		 654 { "asid", 23, PROCESSOR_NOT_V850 },
655 { "bpam", 25, PROCESSOR_NOT_V850 },
656 { "bpav", 24, PROCESSOR_NOT_V850 },
657 { "bpc", 22, PROCESSOR_NOT_V850 },
658 { "bpdm", 27, PROCESSOR_NOT_V850 },
659 { "bpdv", 26, PROCESSOR_NOT_V850 },
78c8d46c
NC		 660 { "bsel", 31, PROCESSOR_V850E2_UP },
661 { "cfg", 7, PROCESSOR_V850E2V3_UP },
1cd986c5
NC		 662 { "ctbp", 20, PROCESSOR_NOT_V850 },
663 { "ctpc", 16, PROCESSOR_NOT_V850 },
664 { "ctpsw", 17, PROCESSOR_NOT_V850 },
78c8d46c 665 { "dbic", 15, PROCESSOR_V850E2_UP },
1cd986c5
NC		 666 { "dbpc", 18, PROCESSOR_NOT_V850 },
667 { "dbpsw", 19, PROCESSOR_NOT_V850 },
78c8d46c 668 { "dbwr", 30, PROCESSOR_V850E2_UP },
1cd986c5 669 { "dir", 21, PROCESSOR_NOT_V850 },
78c8d46c
NC		 670 { "dpa0l", 16, PROCESSOR_V850E2V3_UP },
671 { "dpa0u", 17, PROCESSOR_V850E2V3_UP },
672 { "dpa1l", 18, PROCESSOR_V850E2V3_UP },
673 { "dpa1u", 19, PROCESSOR_V850E2V3_UP },
674 { "dpa2l", 20, PROCESSOR_V850E2V3_UP },
675 { "dpa2u", 21, PROCESSOR_V850E2V3_UP },
676 { "dpa3l", 22, PROCESSOR_V850E2V3_UP },
677 { "dpa3u", 23, PROCESSOR_V850E2V3_UP },
678 { "dpa4l", 24, PROCESSOR_V850E2V3_UP },
679 { "dpa4u", 25, PROCESSOR_V850E2V3_UP },
680 { "dpa5l", 26, PROCESSOR_V850E2V3_UP },
681 { "dpa5u", 27, PROCESSOR_V850E2V3_UP },
1cd986c5 682 { "ecr", 4, PROCESSOR_ALL },
78c8d46c
NC		 683 { "eh_base", 3, PROCESSOR_V850E2V3_UP },
684 { "eh_cfg", 1, PROCESSOR_V850E2V3_UP },
685 { "eh_reset", 2, PROCESSOR_V850E2V3_UP },
686 { "eiic", 13, PROCESSOR_V850E2_UP },
1cd986c5
NC		 687 { "eipc", 0, PROCESSOR_ALL },
688 { "eipsw", 1, PROCESSOR_ALL },
78c8d46c
NC		 689 { "eiwr", 28, PROCESSOR_V850E2_UP },
690 { "feic", 14, PROCESSOR_V850E2_UP },
1cd986c5
NC		 691 { "fepc", 2, PROCESSOR_ALL },
692 { "fepsw", 3, PROCESSOR_ALL },
78c8d46c
NC		 693 { "fewr", 29, PROCESSOR_V850E2_UP },
694 { "fpcc", 9, PROCESSOR_V850E2V3_UP },
695 { "fpcfg", 10, PROCESSOR_V850E2V3_UP },
696 { "fpec", 11, PROCESSOR_V850E2V3_UP },
697 { "fpepc", 7, PROCESSOR_V850E2V3_UP },
698 { "fpspc", 27, PROCESSOR_V850E2V3_UP },
699 { "fpsr", 6, PROCESSOR_V850E2V3_UP },
700 { "fpst", 8, PROCESSOR_V850E2V3_UP },
701 { "ipa0l", 6, PROCESSOR_V850E2V3_UP },
702 { "ipa0u", 7, PROCESSOR_V850E2V3_UP },
703 { "ipa1l", 8, PROCESSOR_V850E2V3_UP },
704 { "ipa1u", 9, PROCESSOR_V850E2V3_UP },
705 { "ipa2l", 10, PROCESSOR_V850E2V3_UP },
706 { "ipa2u", 11, PROCESSOR_V850E2V3_UP },
707 { "ipa3l", 12, PROCESSOR_V850E2V3_UP },
708 { "ipa3u", 13, PROCESSOR_V850E2V3_UP },
709 { "ipa4l", 14, PROCESSOR_V850E2V3_UP },
710 { "ipa4u", 15, PROCESSOR_V850E2V3_UP },
711 { "mca", 24, PROCESSOR_V850E2V3_UP },
712 { "mcc", 26, PROCESSOR_V850E2V3_UP },
713 { "mcr", 27, PROCESSOR_V850E2V3_UP },
714 { "mcs", 25, PROCESSOR_V850E2V3_UP },
715 { "mpc", 1, PROCESSOR_V850E2V3_UP },
716 { "mpm", 0, PROCESSOR_V850E2V3_UP },
717 { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3_UP },
718 { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3_UP },
719 { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3_UP },
720 { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3_UP },
721 { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3_UP },
722 { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3_UP },
723 { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3_UP },
724 { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3_UP },
725 { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3_UP },
726 { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3_UP },
727 { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3_UP },
728 { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3_UP },
729 { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3_UP },
730 { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3_UP },
731 { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3_UP },
732 { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3_UP },
733 { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3_UP },
734 { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3_UP },
735 { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3_UP },
736 { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3_UP },
737 { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3_UP },
738 { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3_UP },
739 { "mpu10_mpc", 1, PROCESSOR_V850E2V3_UP },
740 { "mpu10_mpm", 0, PROCESSOR_V850E2V3_UP },
741 { "mpu10_tid", 2, PROCESSOR_V850E2V3_UP },
742 { "mpu10_vmadr", 5, PROCESSOR_V850E2V3_UP },
743 { "mpu10_vmecr", 3, PROCESSOR_V850E2V3_UP },
744 { "mpu10_vmtid", 4, PROCESSOR_V850E2V3_UP },
745 { "pid", 6, PROCESSOR_V850E2V3_UP },
746 { "pmcr0", 4, PROCESSOR_V850E2V3_UP },
747 { "pmis2", 14, PROCESSOR_V850E2V3_UP },
1cd986c5 748 { "psw", 5, PROCESSOR_ALL },
78c8d46c
NC		 749 { "scbp", 12, PROCESSOR_V850E2V3_UP },
750 { "sccfg", 11, PROCESSOR_V850E2V3_UP },
1cd986c5
NC		 751 { "sr0", 0, PROCESSOR_ALL },
752 { "sr1", 1, PROCESSOR_ALL },
753 { "sr10", 10, PROCESSOR_ALL },
754 { "sr11", 11, PROCESSOR_ALL },
755 { "sr12", 12, PROCESSOR_ALL },
756 { "sr13", 13, PROCESSOR_ALL },
757 { "sr14", 14, PROCESSOR_ALL },
758 { "sr15", 15, PROCESSOR_ALL },
759 { "sr16", 16, PROCESSOR_ALL },
760 { "sr17", 17, PROCESSOR_ALL },
761 { "sr18", 18, PROCESSOR_ALL },
762 { "sr19", 19, PROCESSOR_ALL },
763 { "sr2", 2, PROCESSOR_ALL },
764 { "sr20", 20, PROCESSOR_ALL },
765 { "sr21", 21, PROCESSOR_ALL },
766 { "sr22", 22, PROCESSOR_ALL },
767 { "sr23", 23, PROCESSOR_ALL },
768 { "sr24", 24, PROCESSOR_ALL },
769 { "sr25", 25, PROCESSOR_ALL },
770 { "sr26", 26, PROCESSOR_ALL },
771 { "sr27", 27, PROCESSOR_ALL },
772 { "sr28", 28, PROCESSOR_ALL },
773 { "sr29", 29, PROCESSOR_ALL },
774 { "sr3", 3, PROCESSOR_ALL },
775 { "sr30", 30, PROCESSOR_ALL },
776 { "sr31", 31, PROCESSOR_ALL },
777 { "sr4", 4, PROCESSOR_ALL },
778 { "sr5", 5, PROCESSOR_ALL },
779 { "sr6", 6, PROCESSOR_ALL },
780 { "sr7", 7, PROCESSOR_ALL },
781 { "sr8", 8, PROCESSOR_ALL },
782 { "sr9", 9, PROCESSOR_ALL },
78c8d46c
NC		 783 { "sw_base", 3, PROCESSOR_V850E2V3_UP },
784 { "sw_cfg", 1, PROCESSOR_V850E2V3_UP },
785 { "sw_ctl", 0, PROCESSOR_V850E2V3_UP },
786 { "tid", 2, PROCESSOR_V850E2V3_UP },
787 { "vmadr", 6, PROCESSOR_V850E2V3_UP },
788 { "vmecr", 4, PROCESSOR_V850E2V3_UP },
789 { "vmtid", 5, PROCESSOR_V850E2V3_UP },
790 { "vsadr", 2, PROCESSOR_V850E2V3_UP },
791 { "vsecr", 0, PROCESSOR_V850E2V3_UP },
792 { "vstid", 1, PROCESSOR_V850E2V3_UP },
252b5132 793};
28e4f854
KH		 794
795#define SYSREG_NAME_CNT \
796 (sizeof (system_registers) / sizeof (struct reg_name))
252b5132 797
252b5132 798
77c6dd37
NC		 799static const struct reg_name cc_names[] =
800{
1cd986c5
NC		 801 { "c", 0x1, PROCESSOR_ALL },
802 { "e", 0x2, PROCESSOR_ALL },
803 { "ge", 0xe, PROCESSOR_ALL },
804 { "gt", 0xf, PROCESSOR_ALL },
805 { "h", 0xb, PROCESSOR_ALL },
806 { "l", 0x1, PROCESSOR_ALL },
807 { "le", 0x7, PROCESSOR_ALL },
808 { "lt", 0x6, PROCESSOR_ALL },
809 { "n", 0x4, PROCESSOR_ALL },
810 { "nc", 0x9, PROCESSOR_ALL },
811 { "ne", 0xa, PROCESSOR_ALL },
812 { "nh", 0x3, PROCESSOR_ALL },
813 { "nl", 0x9, PROCESSOR_ALL },
814 { "ns", 0xc, PROCESSOR_ALL },
815 { "nv", 0x8, PROCESSOR_ALL },
816 { "nz", 0xa, PROCESSOR_ALL },
817 { "p", 0xc, PROCESSOR_ALL },
818 { "s", 0x4, PROCESSOR_ALL },
819#define COND_SA_NUM 0xd
820 { "sa", COND_SA_NUM, PROCESSOR_ALL },
821 { "t", 0x5, PROCESSOR_ALL },
822 { "v", 0x0, PROCESSOR_ALL },
823 { "z", 0x2, PROCESSOR_ALL },
252b5132 824};
252b5132 825
28e4f854
KH		 826#define CC_NAME_CNT \
827 (sizeof (cc_names) / sizeof (struct reg_name))
828
1cd986c5
NC		 829static const struct reg_name float_cc_names[] =
830{
78c8d46c
NC		 831 { "eq", 0x2, PROCESSOR_V850E2V3_UP }, /* true. */
832 { "f", 0x0, PROCESSOR_V850E2V3_UP }, /* true. */
833 { "ge", 0xd, PROCESSOR_V850E2V3_UP }, /* false. */
834 { "gl", 0xb, PROCESSOR_V850E2V3_UP }, /* false. */
835 { "gle", 0x9, PROCESSOR_V850E2V3_UP }, /* false. */
836 { "gt", 0xf, PROCESSOR_V850E2V3_UP }, /* false. */
837 { "le", 0xe, PROCESSOR_V850E2V3_UP }, /* true. */
838 { "lt", 0xc, PROCESSOR_V850E2V3_UP }, /* true. */
839 { "neq", 0x2, PROCESSOR_V850E2V3_UP }, /* false. */
840 { "nge", 0xd, PROCESSOR_V850E2V3_UP }, /* true. */
841 { "ngl", 0xb, PROCESSOR_V850E2V3_UP }, /* true. */
842 { "ngle",0x9, PROCESSOR_V850E2V3_UP }, /* true. */
843 { "ngt", 0xf, PROCESSOR_V850E2V3_UP }, /* true. */
844 { "nle", 0xe, PROCESSOR_V850E2V3_UP }, /* false. */
845 { "nlt", 0xc, PROCESSOR_V850E2V3_UP }, /* false. */
846 { "oge", 0x5, PROCESSOR_V850E2V3_UP }, /* false. */
847 { "ogl", 0x3, PROCESSOR_V850E2V3_UP }, /* false. */
848 { "ogt", 0x7, PROCESSOR_V850E2V3_UP }, /* false. */
849 { "ole", 0x6, PROCESSOR_V850E2V3_UP }, /* true. */
850 { "olt", 0x4, PROCESSOR_V850E2V3_UP }, /* true. */
851 { "or", 0x1, PROCESSOR_V850E2V3_UP }, /* false. */
852 { "seq", 0xa, PROCESSOR_V850E2V3_UP }, /* true. */
853 { "sf", 0x8, PROCESSOR_V850E2V3_UP }, /* true. */
854 { "sne", 0xa, PROCESSOR_V850E2V3_UP }, /* false. */
855 { "st", 0x8, PROCESSOR_V850E2V3_UP }, /* false. */
856 { "t", 0x0, PROCESSOR_V850E2V3_UP }, /* false. */
857 { "ueq", 0x3, PROCESSOR_V850E2V3_UP }, /* true. */
858 { "uge", 0x4, PROCESSOR_V850E2V3_UP }, /* false. */
859 { "ugt", 0x6, PROCESSOR_V850E2V3_UP }, /* false. */
860 { "ule", 0x7, PROCESSOR_V850E2V3_UP }, /* true. */
861 { "ult", 0x5, PROCESSOR_V850E2V3_UP }, /* true. */
862 { "un", 0x1, PROCESSOR_V850E2V3_UP }, /* true. */
1cd986c5
NC		 863};
864
865#define FLOAT_CC_NAME_CNT \
866 (sizeof (float_cc_names) / sizeof (struct reg_name))
867
78c8d46c
NC		 868
869static const struct reg_name cacheop_names[] =
870{
871 { "cfald", 0x44, PROCESSOR_V850E3V5_UP },
872 { "cfali", 0x40, PROCESSOR_V850E3V5_UP },
873 { "chbid", 0x04, PROCESSOR_V850E3V5_UP },
874 { "chbii", 0x00, PROCESSOR_V850E3V5_UP },
875 { "chbiwbd", 0x06, PROCESSOR_V850E3V5_UP },
876 { "chbwbd", 0x07, PROCESSOR_V850E3V5_UP },
877 { "cibid", 0x24, PROCESSOR_V850E3V5_UP },
878 { "cibii", 0x20, PROCESSOR_V850E3V5_UP },
879 { "cibiwbd", 0x26, PROCESSOR_V850E3V5_UP },
880 { "cibwbd", 0x27, PROCESSOR_V850E3V5_UP },
881 { "cildd", 0x65, PROCESSOR_V850E3V5_UP },
882 { "cildi", 0x61, PROCESSOR_V850E3V5_UP },
883 { "cistd", 0x64, PROCESSOR_V850E3V5_UP },
884 { "cisti", 0x60, PROCESSOR_V850E3V5_UP },
885};
886
887#define CACHEOP_NAME_CNT \
888 (sizeof (cacheop_names) / sizeof (struct reg_name))
889
890static const struct reg_name prefop_names[] =
891{
892 { "prefd", 0x04, PROCESSOR_V850E3V5_UP },
893 { "prefi", 0x00, PROCESSOR_V850E3V5_UP },
894};
895
896#define PREFOP_NAME_CNT \
897 (sizeof (prefop_names) / sizeof (struct reg_name))
898
899static const struct reg_name vector_registers[] =
900{
901 { "vr0", 0, PROCESSOR_V850E3V5_UP },
902 { "vr1", 1, PROCESSOR_V850E3V5_UP },
903 { "vr10", 10, PROCESSOR_V850E3V5_UP },
904 { "vr11", 11, PROCESSOR_V850E3V5_UP },
905 { "vr12", 12, PROCESSOR_V850E3V5_UP },
906 { "vr13", 13, PROCESSOR_V850E3V5_UP },
907 { "vr14", 14, PROCESSOR_V850E3V5_UP },
908 { "vr15", 15, PROCESSOR_V850E3V5_UP },
909 { "vr16", 16, PROCESSOR_V850E3V5_UP },
910 { "vr17", 17, PROCESSOR_V850E3V5_UP },
911 { "vr18", 18, PROCESSOR_V850E3V5_UP },
912 { "vr19", 19, PROCESSOR_V850E3V5_UP },
913 { "vr2", 2, PROCESSOR_V850E3V5_UP },
914 { "vr20", 20, PROCESSOR_V850E3V5_UP },
915 { "vr21", 21, PROCESSOR_V850E3V5_UP },
916 { "vr22", 22, PROCESSOR_V850E3V5_UP },
917 { "vr23", 23, PROCESSOR_V850E3V5_UP },
918 { "vr24", 24, PROCESSOR_V850E3V5_UP },
919 { "vr25", 25, PROCESSOR_V850E3V5_UP },
920 { "vr26", 26, PROCESSOR_V850E3V5_UP },
921 { "vr27", 27, PROCESSOR_V850E3V5_UP },
922 { "vr28", 28, PROCESSOR_V850E3V5_UP },
923 { "vr29", 29, PROCESSOR_V850E3V5_UP },
924 { "vr3", 3, PROCESSOR_V850E3V5_UP },
925 { "vr30", 30, PROCESSOR_V850E3V5_UP },
926 { "vr31", 31, PROCESSOR_V850E3V5_UP },
927 { "vr4", 4, PROCESSOR_V850E3V5_UP },
928 { "vr5", 5, PROCESSOR_V850E3V5_UP },
929 { "vr6", 6, PROCESSOR_V850E3V5_UP },
930 { "vr7", 7, PROCESSOR_V850E3V5_UP },
931 { "vr8", 8, PROCESSOR_V850E3V5_UP },
932 { "vr9", 9, PROCESSOR_V850E3V5_UP },
933};
934
935#define VREG_NAME_CNT \
936 (sizeof (vector_registers) / sizeof (struct reg_name))
937
28e4f854
KH		 938/* Do a binary search of the given register table to see if NAME is a
939 valid regiter name. Return the register number from the array on
940 success, or -1 on failure. */
252b5132
RH		 941
942static int
ea1562b3
NC		 943reg_name_search (const struct reg_name *regs,
944 int regcount,
945 const char *name,
946 bfd_boolean accept_numbers)
252b5132
RH		 947{
948 int middle, low, high;
949 int cmp;
28e4f854 950 symbolS *symbolP;
252b5132
RH		 951
952 /* If the register name is a symbol, then evaluate it. */
953 if ((symbolP = symbol_find (name)) != NULL)
954 {
955 /* If the symbol is an alias for another name then use that.
956 If the symbol is an alias for a number, then return the number. */
a77f5182 957 if (symbol_equated_p (symbolP))
ea1562b3
NC		 958 name
959 = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol);
252b5132
RH		 960 else if (accept_numbers)
961 {
962 int reg = S_GET_VALUE (symbolP);
1cd986c5 963 return reg;
252b5132
RH		 964 }
965
966 /* Otherwise drop through and try parsing name normally. */
967 }
28e4f854 968
252b5132
RH		 969 low = 0;
970 high = regcount - 1;
971
972 do
973 {
974 middle = (low + high) / 2;
975 cmp = strcasecmp (name, regs[middle].name);
976 if (cmp < 0)
977 high = middle - 1;
978 else if (cmp > 0)
979 low = middle + 1;
980 else
1cd986c5
NC		 981 return ((regs[middle].processors & processor_mask)
982 ? regs[middle].value
983 : -1);
252b5132
RH		 984 }
985 while (low <= high);
986 return -1;
987}
988
252b5132 989/* Summary of register_name().
ec178e1b 990
77c6dd37 991 in: Input_line_pointer points to 1st char of operand.
ec178e1b 992
77c6dd37
NC		 993 out: An expressionS.
994 The operand may have been a register: in this case, X_op == O_register,
995 X_add_number is set to the register number, and truth is returned.
996 Input_line_pointer->(next non-blank) char after operand, or is in
997 its original state. */
28e4f854 998
b34976b6 999static bfd_boolean
ea1562b3 1000register_name (expressionS *expressionP)
252b5132 1001{
28e4f854
KH		 1002 int reg_number;
1003 char *name;
1004 char *start;
1005 char c;
252b5132 1006
28e4f854 1007 /* Find the spelling of the operand. */
252b5132
RH		 1008 start = name = input_line_pointer;
1009
1010 c = get_symbol_end ();
1011
1012 reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT,
1013 name, FALSE);
1014
28e4f854
KH		 1015 /* Put back the delimiting char. */
1016 *input_line_pointer = c;
1017
1cd986c5
NC		 1018 expressionP->X_add_symbol = NULL;
1019 expressionP->X_op_symbol = NULL;
1020
28e4f854
KH		 1021 /* Look to see if it's in the register table. */
1022 if (reg_number >= 0)
252b5132 1023 {
ec178e1b 1024 expressionP->X_op = O_register;
252b5132
RH		 1025 expressionP->X_add_number = reg_number;
1026
b34976b6 1027 return TRUE;
252b5132 1028 }
28e4f854 1029
1cd986c5
NC		 1030 /* Reset the line as if we had not done anything. */
1031 input_line_pointer = start;
1032
1033 expressionP->X_op = O_illegal;
1034
1035 return FALSE;
252b5132
RH		 1036}
1037
1038/* Summary of system_register_name().
ec178e1b 1039
77c6dd37 1040 in: INPUT_LINE_POINTER points to 1st char of operand.
ec178e1b
AM		 1041 EXPRESSIONP points to an expression structure to be filled in.
1042 ACCEPT_NUMBERS is true iff numerical register names may be used.
ec178e1b 1043
77c6dd37
NC		 1044 out: An expressionS structure in expressionP.
1045 The operand may have been a register: in this case, X_op == O_register,
1046 X_add_number is set to the register number, and truth is returned.
1047 Input_line_pointer->(next non-blank) char after operand, or is in
1048 its original state. */
28e4f854 1049
b34976b6 1050static bfd_boolean
ea1562b3 1051system_register_name (expressionS *expressionP,
1cd986c5 1052 bfd_boolean accept_numbers)
252b5132 1053{
28e4f854
KH		 1054 int reg_number;
1055 char *name;
1056 char *start;
1057 char c;
252b5132 1058
28e4f854 1059 /* Find the spelling of the operand. */
252b5132
RH		 1060 start = name = input_line_pointer;
1061
1062 c = get_symbol_end ();
1063 reg_number = reg_name_search (system_registers, SYSREG_NAME_CNT, name,
1064 accept_numbers);
1065
28e4f854
KH		 1066 /* Put back the delimiting char. */
1067 *input_line_pointer = c;
1068
252b5132
RH		 1069 if (reg_number < 0
1070 && accept_numbers)
1071 {
28e4f854
KH		 1072 /* Reset input_line pointer. */
1073 input_line_pointer = start;
252b5132 1074
3882b010 1075 if (ISDIGIT (*input_line_pointer))
252b5132 1076 {
1cd986c5 1077 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
252b5132
RH		 1078 }
1079 }
28e4f854 1080
1cd986c5
NC		 1081 expressionP->X_add_symbol = NULL;
1082 expressionP->X_op_symbol = NULL;
1083
28e4f854
KH		 1084 /* Look to see if it's in the register table. */
1085 if (reg_number >= 0)
252b5132 1086 {
ec178e1b 1087 expressionP->X_op = O_register;
252b5132
RH		 1088 expressionP->X_add_number = reg_number;
1089
b34976b6 1090 return TRUE;
252b5132 1091 }
28e4f854 1092
1cd986c5
NC		 1093 /* Reset the line as if we had not done anything. */
1094 input_line_pointer = start;
1095
1096 expressionP->X_op = O_illegal;
1097
1098 return FALSE;
252b5132
RH		 1099}
1100
1101/* Summary of cc_name().
ec178e1b 1102
77c6dd37 1103 in: INPUT_LINE_POINTER points to 1st char of operand.
ec178e1b 1104
77c6dd37
NC		 1105 out: An expressionS.
1106 The operand may have been a register: in this case, X_op == O_register,
1107 X_add_number is set to the register number, and truth is returned.
1108 Input_line_pointer->(next non-blank) char after operand, or is in
1109 its original state. */
28e4f854 1110
b34976b6 1111static bfd_boolean
1cd986c5
NC		 1112cc_name (expressionS *expressionP,
1113 bfd_boolean accept_numbers)
252b5132 1114{
28e4f854
KH		 1115 int reg_number;
1116 char *name;
1117 char *start;
1118 char c;
252b5132 1119
28e4f854 1120 /* Find the spelling of the operand. */
252b5132
RH		 1121 start = name = input_line_pointer;
1122
1123 c = get_symbol_end ();
1cd986c5 1124 reg_number = reg_name_search (cc_names, CC_NAME_CNT, name, accept_numbers);
252b5132 1125
28e4f854
KH		 1126 /* Put back the delimiting char. */
1127 *input_line_pointer = c;
1128
1cd986c5
NC		 1129 if (reg_number < 0
1130 && accept_numbers)
1131 {
1132 /* Reset input_line pointer. */
1133 input_line_pointer = start;
1134
1135 if (ISDIGIT (*input_line_pointer))
1136 {
1137 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1138 }
1139 }
1140
1141 expressionP->X_add_symbol = NULL;
1142 expressionP->X_op_symbol = NULL;
1143
28e4f854
KH		 1144 /* Look to see if it's in the register table. */
1145 if (reg_number >= 0)
252b5132 1146 {
ec178e1b 1147 expressionP->X_op = O_constant;
252b5132
RH		 1148 expressionP->X_add_number = reg_number;
1149
b34976b6 1150 return TRUE;
252b5132 1151 }
1cd986c5
NC		 1152
1153 /* Reset the line as if we had not done anything. */
1154 input_line_pointer = start;
1155
1156 expressionP->X_op = O_illegal;
1157 expressionP->X_add_number = 0;
1158
1159 return FALSE;
1160}
1161
1162static bfd_boolean
1163float_cc_name (expressionS *expressionP,
1164 bfd_boolean accept_numbers)
1165{
1166 int reg_number;
1167 char *name;
1168 char *start;
1169 char c;
1170
1171 /* Find the spelling of the operand. */
1172 start = name = input_line_pointer;
1173
1174 c = get_symbol_end ();
1175 reg_number = reg_name_search (float_cc_names, FLOAT_CC_NAME_CNT, name, accept_numbers);
1176
1177 /* Put back the delimiting char. */
1178 *input_line_pointer = c;
1179
1180 if (reg_number < 0
1181 && accept_numbers)
252b5132 1182 {
1cd986c5 1183 /* Reset input_line pointer. */
252b5132 1184 input_line_pointer = start;
28e4f854 1185
1cd986c5
NC		 1186 if (ISDIGIT (*input_line_pointer))
1187 {
1188 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1189 }
1190 }
1191
1192 expressionP->X_add_symbol = NULL;
1193 expressionP->X_op_symbol = NULL;
1194
1195 /* Look to see if it's in the register table. */
1196 if (reg_number >= 0)
1197 {
1198 expressionP->X_op = O_constant;
1199 expressionP->X_add_number = reg_number;
1200
1201 return TRUE;
252b5132 1202 }
1cd986c5
NC		 1203
1204 /* Reset the line as if we had not done anything. */
1205 input_line_pointer = start;
1206
1207 expressionP->X_op = O_illegal;
1208 expressionP->X_add_number = 0;
1209
1210 return FALSE;
252b5132
RH		 1211}
1212
78c8d46c
NC		 1213static bfd_boolean
1214cacheop_name (expressionS * expressionP,
1215 bfd_boolean accept_numbers)
1216{
1217 int reg_number;
1218 char *name;
1219 char *start;
1220 char c;
1221
1222 /* Find the spelling of the operand. */
1223 start = name = input_line_pointer;
1224
1225 c = get_symbol_end ();
1226 reg_number = reg_name_search (cacheop_names, CACHEOP_NAME_CNT, name, accept_numbers);
1227
1228 /* Put back the delimiting char. */
1229 *input_line_pointer = c;
1230
1231 if (reg_number < 0
1232 && accept_numbers)
1233 {
1234 /* Reset input_line pointer. */
1235 input_line_pointer = start;
1236
1237 if (ISDIGIT (*input_line_pointer))
1238 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1239 }
1240
1241 expressionP->X_add_symbol = NULL;
1242 expressionP->X_op_symbol = NULL;
1243
1244 /* Look to see if it's in the register table. */
1245 if (reg_number >= 0)
1246 {
1247 expressionP->X_op = O_constant;
1248 expressionP->X_add_number = reg_number;
1249
1250 return TRUE;
1251 }
1252
1253 /* Reset the line as if we had not done anything. */
1254 input_line_pointer = start;
1255
1256 expressionP->X_op = O_illegal;
1257 expressionP->X_add_number = 0;
1258
1259 return FALSE;
1260}
1261
1262static bfd_boolean
1263prefop_name (expressionS * expressionP,
1264 bfd_boolean accept_numbers)
1265{
1266 int reg_number;
1267 char *name;
1268 char *start;
1269 char c;
1270
1271 /* Find the spelling of the operand. */
1272 start = name = input_line_pointer;
1273
1274 c = get_symbol_end ();
1275 reg_number = reg_name_search (prefop_names, PREFOP_NAME_CNT, name, accept_numbers);
1276
1277 /* Put back the delimiting char. */
1278 *input_line_pointer = c;
1279
1280 if (reg_number < 0
1281 && accept_numbers)
1282 {
1283 /* Reset input_line pointer. */
1284 input_line_pointer = start;
1285
1286 if (ISDIGIT (*input_line_pointer))
1287 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1288 }
1289
1290 expressionP->X_add_symbol = NULL;
1291 expressionP->X_op_symbol = NULL;
1292
1293 /* Look to see if it's in the register table. */
1294 if (reg_number >= 0)
1295 {
1296 expressionP->X_op = O_constant;
1297 expressionP->X_add_number = reg_number;
1298
1299 return TRUE;
1300 }
1301
1302 /* Reset the line as if we had not done anything. */
1303 input_line_pointer = start;
1304
1305 expressionP->X_op = O_illegal;
1306 expressionP->X_add_number = 0;
1307
1308 return FALSE;
1309}
1310
1311static bfd_boolean
1312vector_register_name (expressionS *expressionP)
1313{
1314 int reg_number;
1315 char *name;
1316 char *start;
1317 char c;
1318
1319 /* Find the spelling of the operand. */
1320 start = name = input_line_pointer;
1321
1322 c = get_symbol_end ();
1323
1324 reg_number = reg_name_search (vector_registers, VREG_NAME_CNT,
1325 name, FALSE);
1326
1327 /* Put back the delimiting char. */
1328 *input_line_pointer = c;
1329
1330 expressionP->X_add_symbol = NULL;
1331 expressionP->X_op_symbol = NULL;
1332
1333 /* Look to see if it's in the register table. */
1334 if (reg_number >= 0)
1335 {
1336 expressionP->X_op = O_register;
1337 expressionP->X_add_number = reg_number;
1338
1339 return TRUE;
1340 }
1341
1342 /* Reset the line as if we had not done anything. */
1343 input_line_pointer = start;
1344
1345 expressionP->X_op = O_illegal;
1346
1347 return FALSE;
1348}
1349
252b5132 1350static void
ea1562b3 1351skip_white_space (void)
252b5132 1352{
28e4f854
KH		 1353 while (*input_line_pointer == ' '
1354 || *input_line_pointer == '\t')
1355 ++input_line_pointer;
252b5132
RH		 1356}
1357
1358/* Summary of parse_register_list ().
ec178e1b 1359
77c6dd37 1360 in: INPUT_LINE_POINTER points to 1st char of a list of registers.
ec178e1b
AM		 1361 INSN is the partially constructed instruction.
1362 OPERAND is the operand being inserted.
1363
77c6dd37 1364 out: NULL if the parse completed successfully, otherwise a
ec178e1b
AM		 1365 pointer to an error message is returned. If the parse
1366 completes the correct bit fields in the instruction
1367 will be filled in.
1368
77c6dd37 1369 Parses register lists with the syntax:
ec178e1b 1370
77c6dd37
NC		 1371 { rX }
1372 { rX, rY }
1373 { rX - rY }
1374 { rX - rY, rZ }
1375 etc
ec178e1b 1376
33b7f697 1377 and also parses constant expressions whoes bits indicate the
77c6dd37 1378 registers in the lists. The LSB in the expression refers to
33b7f697 1379 the lowest numbered permissible register in the register list,
77c6dd37
NC		 1380 and so on upwards. System registers are considered to be very
1381 high numbers. */
28e4f854 1382
252b5132 1383static char *
ea1562b3
NC		 1384parse_register_list (unsigned long *insn,
1385 const struct v850_operand *operand)
252b5132 1386{
ea1562b3
NC		 1387 static int type1_regs[32] =
1388 {
28e4f854
KH		 1389 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1390 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24
1391 };
1cd986c5 1392
28e4f854 1393 int *regs;
252b5132
RH		 1394 expressionS exp;
1395
28e4f854 1396 /* Select a register array to parse. */
252b5132
RH		 1397 switch (operand->shift)
1398 {
1399 case 0xffe00001: regs = type1_regs; break;
252b5132
RH		 1400 default:
1401 as_bad (_("unknown operand shift: %x\n"), operand->shift);
1402 return _("internal failure in parse_register_list");
1403 }
1404
1405 skip_white_space ();
1406
1407 /* If the expression starts with a curly brace it is a register list.
1408 Otherwise it is a constant expression, whoes bits indicate which
1409 registers are to be included in the list. */
28e4f854 1410 if (*input_line_pointer != '{')
252b5132 1411 {
252b5132
RH		 1412 int reg;
1413 int i;
28e4f854
KH		 1414
1415 expression (&exp);
1416
252b5132
RH		 1417 if (exp.X_op != O_constant)
1418 return _("constant expression or register list expected");
1419
1420 if (regs == type1_regs)
1421 {
1422 if (exp.X_add_number & 0xFFFFF000)
1423 return _("high bits set in register list expression");
28e4f854
KH		 1424
1425 for (reg = 20; reg < 32; reg++)
252b5132
RH		 1426 if (exp.X_add_number & (1 << (reg - 20)))
1427 {
1428 for (i = 0; i < 32; i++)
1429 if (regs[i] == reg)
28e4f854 1430 *insn |= (1 << i);
252b5132
RH		 1431 }
1432 }
252b5132
RH		 1433
1434 return NULL;
1435 }
1436
28e4f854 1437 input_line_pointer++;
252b5132
RH		 1438
1439 /* Parse the register list until a terminator (closing curly brace or
1440 new-line) is found. */
1441 for (;;)
1442 {
1cd986c5
NC		 1443 skip_white_space ();
1444
28e4f854 1445 if (register_name (&exp))
252b5132 1446 {
28e4f854
KH		 1447 int i;
1448
252b5132
RH		 1449 /* Locate the given register in the list, and if it is there,
1450 insert the corresponding bit into the instruction. */
1451 for (i = 0; i < 32; i++)
1452 {
28e4f854 1453 if (regs[i] == exp.X_add_number)
252b5132 1454 {
28e4f854 1455 *insn |= (1 << i);
252b5132
RH		 1456 break;
1457 }
1458 }
1459
1460 if (i == 32)
77c6dd37 1461 return _("illegal register included in list");
252b5132 1462 }
1cd986c5 1463 else if (system_register_name (&exp, TRUE))
252b5132
RH		 1464 {
1465 if (regs == type1_regs)
1466 {
1467 return _("system registers cannot be included in list");
1468 }
252b5132 1469 }
1cd986c5
NC		 1470
1471 if (*input_line_pointer == '}')
252b5132 1472 {
28e4f854 1473 input_line_pointer++;
252b5132
RH		 1474 break;
1475 }
28e4f854 1476 else if (*input_line_pointer == ',')
252b5132 1477 {
28e4f854 1478 input_line_pointer++;
252b5132
RH		 1479 continue;
1480 }
28e4f854 1481 else if (*input_line_pointer == '-')
252b5132 1482 {
28e4f854
KH		 1483 /* We have encountered a range of registers: rX - rY. */
1484 int j;
252b5132
RH		 1485 expressionS exp2;
1486
1487 /* Skip the dash. */
28e4f854 1488 ++input_line_pointer;
252b5132
RH		 1489
1490 /* Get the second register in the range. */
28e4f854 1491 if (! register_name (&exp2))
252b5132
RH		 1492 {
1493 return _("second register should follow dash in register list");
1cd986c5
NC		 1494 }
1495
1496 if (exp.X_add_number > exp2.X_add_number)
1497 {
5648d7c7 1498 return _("second register should be greater than first register");
252b5132
RH		 1499 }
1500
1501 /* Add the rest of the registers in the range. */
1502 for (j = exp.X_add_number + 1; j <= exp2.X_add_number; j++)
1503 {
28e4f854
KH		 1504 int i;
1505
252b5132
RH		 1506 /* Locate the given register in the list, and if it is there,
1507 insert the corresponding bit into the instruction. */
1508 for (i = 0; i < 32; i++)
1509 {
28e4f854 1510 if (regs[i] == j)
252b5132 1511 {
28e4f854 1512 *insn |= (1 << i);
252b5132
RH		 1513 break;
1514 }
1515 }
1516
1517 if (i == 32)
1518 return _("illegal register included in list");
1519 }
1cd986c5
NC		 1520
1521 exp = exp2;
252b5132
RH		 1522 }
1523 else
77c6dd37 1524 break;
252b5132
RH		 1525 }
1526
1527 return NULL;
1528}
1529
5a38dc70 1530const char *md_shortopts = "m:";
252b5132 1531
ea1562b3
NC		 1532struct option md_longopts[] =
1533{
1cd986c5
NC		 1534#define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE)
1535 {"disp-size-default-22", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_22},
1536#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1)
1537 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
252b5132
RH		 1538 {NULL, no_argument, NULL, 0}
1539};
252b5132 1540
28e4f854 1541size_t md_longopts_size = sizeof (md_longopts);
252b5132 1542
685080f2
NC		 1543static bfd_boolean v850_data_8 = FALSE;
1544
252b5132 1545void
ea1562b3 1546md_show_usage (FILE *stream)
252b5132
RH		 1547{
1548 fprintf (stream, _(" V850 options:\n"));
1549 fprintf (stream, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n"));
1550 fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n"));
1551 fprintf (stream, _(" -mv850 The code is targeted at the v850\n"));
1552 fprintf (stream, _(" -mv850e The code is targeted at the v850e\n"));
8ad30312 1553 fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n"));
1cd986c5
NC		 1554 fprintf (stream, _(" -mv850e2 The code is targeted at the v850e2\n"));
1555 fprintf (stream, _(" -mv850e2v3 The code is targeted at the v850e2v3\n"));
78c8d46c
NC		 1556 fprintf (stream, _(" -mv850e2v4 Alias for -mv850e3v5\n"));
1557 fprintf (stream, _(" -mv850e3v5 The code is targeted at the v850e3v5\n"));
86aba9db 1558 fprintf (stream, _(" -mrelax Enable relaxation\n"));
1cd986c5
NC		 1559 fprintf (stream, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n"));
1560 fprintf (stream, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n"));
1561 fprintf (stream, _(" -mextension enable extension opcode support\n"));
1562 fprintf (stream, _(" -mno-bcond17 disable b<cond> disp17 instruction\n"));
1563 fprintf (stream, _(" -mno-stld23 disable st/ld offset23 instruction\n"));
de863c74
NC		 1564 fprintf (stream, _(" -mgcc-abi Mark the binary as using the old GCC ABI\n"));
1565 fprintf (stream, _(" -mrh850-abi Mark the binary as using the RH850 ABI (default)\n"));
1566 fprintf (stream, _(" -m8byte-align Mark the binary as using 64-bit alignment\n"));
1567 fprintf (stream, _(" -m4byte-align Mark the binary as using 32-bit alignment (default)\n"));
685080f2
NC		 1568 fprintf (stream, _(" -msoft-float Mark the binary as not using FP insns (default for pre e2v3)\n"));
1569 fprintf (stream, _(" -mhard-float Mark the binary as using FP insns (default for e2v3 and up)\n"));
252b5132
RH		 1570}
1571
1572int
ea1562b3 1573md_parse_option (int c, char *arg)
252b5132
RH		 1574{
1575 if (c != 'm')
1cd986c5
NC		 1576 {
1577 switch (c)
1578 {
1579 case OPTION_DISP_SIZE_DEFAULT_22:
1580 default_disp_size = 22;
1581 return 1;
1582
1583 case OPTION_DISP_SIZE_DEFAULT_32:
1584 default_disp_size = 32;
1585 return 1;
1586 }
1587 return 0;
1588 }
252b5132
RH		 1589
1590 if (strcmp (arg, "warn-signed-overflow") == 0)
329e276d
NC		 1591 warn_signed_overflows = TRUE;
1592
252b5132 1593 else if (strcmp (arg, "warn-unsigned-overflow") == 0)
329e276d
NC		 1594 warn_unsigned_overflows = TRUE;
1595
252b5132
RH		 1596 else if (strcmp (arg, "v850") == 0)
1597 {
1598 machine = 0;
1cd986c5 1599 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850);
252b5132
RH		 1600 }
1601 else if (strcmp (arg, "v850e") == 0)
1602 {
1603 machine = bfd_mach_v850e;
1cd986c5 1604 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E);
252b5132 1605 }
8ad30312
NC		 1606 else if (strcmp (arg, "v850e1") == 0)
1607 {
1608 machine = bfd_mach_v850e1;
1cd986c5 1609 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1);
8ad30312 1610 }
1cd986c5 1611 else if (strcmp (arg, "v850e2") == 0)
252b5132 1612 {
1cd986c5
NC		 1613 machine = bfd_mach_v850e2;
1614 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2);
1615 }
1616 else if (strcmp (arg, "v850e2v3") == 0)
1617 {
1618 machine = bfd_mach_v850e2v3;
1619 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3);
1620 }
78c8d46c
NC		 1621 else if (strcmp (arg, "v850e2v4") == 0)
1622 {
1623 machine = bfd_mach_v850e3v5;
1624 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1625 }
1626 else if (strcmp (arg, "v850e3v5") == 0)
1627 {
1628 machine = bfd_mach_v850e3v5;
1629 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1630 }
1cd986c5
NC		 1631 else if (strcmp (arg, "extension") == 0)
1632 {
5bb3703f 1633 processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS;
1cd986c5
NC		 1634 }
1635 else if (strcmp (arg, "no-bcond17") == 0)
1636 {
1637 no_bcond17 = 1;
1638 }
1639 else if (strcmp (arg, "no-stld23") == 0)
1640 {
1641 no_stld23 = 1;
252b5132 1642 }
86aba9db
NC		 1643 else if (strcmp (arg, "relax") == 0)
1644 v850_relax = 1;
de863c74
NC		 1645 else if (strcmp (arg, "gcc-abi") == 0)
1646 {
1647 v850_target_arch = bfd_arch_v850;
1648 v850_target_format = "elf32-v850";
1649 }
1650 else if (strcmp (arg, "rh850-abi") == 0)
1651 {
1652 v850_target_arch = bfd_arch_v850_rh850;
1653 v850_target_format = "elf32-v850-rh850";
1654 }
685080f2
NC		 1655 else if (strcmp (arg, "8byte-align") == 0)
1656 v850_data_8 = TRUE;
1657 else if (strcmp (arg, "4byte-align") == 0)
1658 v850_data_8 = FALSE;
1659 else if (strcmp (arg, "soft-float") == 0)
1660 soft_float = 1;
1661 else if (strcmp (arg, "hard-float") == 0)
1662 soft_float = 0;
de863c74
NC		 1663 else if (strcmp (arg, "8byte-align") == 0)
1664 v850_e_flags |= EF_RH850_DATA_ALIGN8;
1665 else if (strcmp (arg, "4byte-align") == 0)
1666 v850_e_flags &= ~ EF_RH850_DATA_ALIGN8;
252b5132 1667 else
329e276d 1668 return 0;
28e4f854 1669
252b5132
RH		 1670 return 1;
1671}
1672
1673symbolS *
ea1562b3 1674md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 1675{
1676 return 0;
1677}
1678
1679char *
ea1562b3 1680md_atof (int type, char *litp, int *sizep)
252b5132 1681{
499ac353 1682 return ieee_md_atof (type, litp, sizep, FALSE);
252b5132
RH		 1683}
1684
252b5132 1685/* Very gross. */
28e4f854 1686
252b5132 1687void
ea1562b3
NC		 1688md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
1689 asection *sec,
1690 fragS *fragP)
252b5132 1691{
8ad7c533
NC		 1692 union u
1693 {
1694 bfd_reloc_code_real_type fx_r_type;
1695 char * fr_opcode;
1696 }
1697 opcode_converter;
252b5132 1698 subseg_change (sec, 0);
28e4f854 1699
8ad7c533 1700 opcode_converter.fr_opcode = fragP->fr_opcode;
1cd986c5
NC		 1701
1702 subseg_change (sec, 0);
1703
78c8d46c
NC		 1704 if (fragP->fr_subtype == SUBYPTE_LOOP_16_22)
1705 {
1706 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1707 fragP->fr_offset, 1,
1708 BFD_RELOC_UNUSED + opcode_converter.fx_r_type);
1709 fragP->fr_fix += 4;
1710 }
1711 else if (fragP->fr_subtype == SUBYPTE_LOOP_16_22 + 1)
1712 {
1713 unsigned char * buffer =
1714 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1715 int loop_reg = (buffer[0] & 0x1f);
1716
1717 /* Add -1.reg. */
1718 md_number_to_chars ((char *) buffer, 0x025f | (loop_reg << 11), 2);
1719 /* Now create the conditional branch + fixup to the final target. */
1720 /* 0x000107ea = bne LBL(disp17). */
1721 md_number_to_chars ((char *) buffer + 2, 0x000107ea, 4);
1722 fix_new (fragP, fragP->fr_fix+2, 4, fragP->fr_symbol,
1723 fragP->fr_offset, 1,
1724 BFD_RELOC_V850_17_PCREL);
1725 fragP->fr_fix += 6;
1726 }
252b5132 1727 /* In range conditional or unconditional branch. */
78c8d46c 1728 else if (fragP->fr_subtype == SUBYPTE_COND_9_22
1cd986c5
NC		 1729 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22
1730 || fragP->fr_subtype == SUBYPTE_COND_9_22_32
1731 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32
1732 || fragP->fr_subtype == SUBYPTE_COND_9_17_22
1733 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32
1734 || fragP->fr_subtype == SUBYPTE_SA_9_22
1735 || fragP->fr_subtype == SUBYPTE_SA_9_22_32
1736 || fragP->fr_subtype == SUBYPTE_SA_9_17_22
1737 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32)
1738
252b5132
RH		 1739 {
1740 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
8ad7c533
NC		 1741 fragP->fr_offset, 1,
1742 BFD_RELOC_UNUSED + opcode_converter.fx_r_type);
252b5132
RH		 1743 fragP->fr_fix += 2;
1744 }
1cd986c5
NC		 1745 /* V850e2r-v3 17bit conditional branch. */
1746 else if (fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 1
1747 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 1
1748 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 1
1749 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 1)
1750 {
1751 unsigned char *buffer =
1752 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1753
1754 buffer[0] &= 0x0f; /* Use condition. */
1755 buffer[0] |= 0xe0;
1756 buffer[1] = 0x07;
1757
1758 /* Now create the unconditional branch + fixup to the final
1759 target. */
1760 md_number_to_chars ((char *) buffer + 2, 0x0001, 2);
1761 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1762 fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL);
1763 fragP->fr_fix += 4;
1764 }
1765 /* Out of range conditional branch. Emit a branch around a 22bit jump. */
1766 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1
1767 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1
1768 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2
1769 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2)
252b5132 1770 {
28e4f854 1771 unsigned char *buffer =
252b5132
RH		 1772 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1773
1774 /* Reverse the condition of the first branch. */
1775 buffer[0] ^= 0x08;
1776 /* Mask off all the displacement bits. */
1777 buffer[0] &= 0x8f;
1778 buffer[1] &= 0x07;
1779 /* Now set the displacement bits so that we branch
1780 around the unconditional branch. */
1781 buffer[0] |= 0x30;
1782
1783 /* Now create the unconditional branch + fixup to the final
1784 target. */
2132e3a3 1785 md_number_to_chars ((char *) buffer + 2, 0x00000780, 4);
252b5132 1786 fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol,
1cd986c5 1787 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL);
252b5132
RH		 1788 fragP->fr_fix += 6;
1789 }
1cd986c5
NC		 1790 /* Out of range conditional branch. Emit a branch around a 32bit jump. */
1791 else if (fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 2
1792 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 3)
1793 {
1794 unsigned char *buffer =
1795 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1796
1797 /* Reverse the condition of the first branch. */
1798 buffer[0] ^= 0x08;
1799 /* Mask off all the displacement bits. */
1800 buffer[0] &= 0x8f;
1801 buffer[1] &= 0x07;
1802 /* Now set the displacement bits so that we branch
1803 around the unconditional branch. */
1804 buffer[0] |= 0x40;
1805
1806 /* Now create the unconditional branch + fixup to the final
1807 target. */
1808 md_number_to_chars ((char *) buffer + 2, 0x02e0, 2);
1809 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1810 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1811 fragP->fr_fix += 8;
1812 }
1813 /* Out of range unconditional branch. Emit a 22bit jump. */
1814 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22 + 1
1815 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 1)
252b5132
RH		 1816 {
1817 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4);
1818 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1cd986c5 1819 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL);
252b5132
RH		 1820 fragP->fr_fix += 4;
1821 }
1cd986c5
NC		 1822 /* Out of range unconditional branch. Emit a 32bit jump. */
1823 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 2)
1824 {
1825 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x02e0, 2);
1826 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1827 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1828 fragP->fr_fix += 6;
1829 }
1830 /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */
1831 else if (fragP->fr_subtype == SUBYPTE_SA_9_22 + 1
1832 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 1
1833 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 2
1834 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 2)
1835 {
1836 unsigned char *buffer =
1837 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1838
1839 /* bsa .+4 */
1840 buffer[0] &= 0x8f;
1841 buffer[0] |= 0x20;
1842 buffer[1] &= 0x07;
1843
1844 /* br .+6 */
1845 md_number_to_chars ((char *) buffer + 2, 0x05b5, 2);
1846
1847 /* Now create the unconditional branch + fixup to the final
1848 target. */
1849 /* jr SYM */
1850 md_number_to_chars ((char *) buffer + 4, 0x00000780, 4);
1851 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1852 fragP->fr_offset, 1,
1853 BFD_RELOC_V850_22_PCREL);
1854 fragP->fr_fix += 8;
1855 }
1856 /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */
1857 else if (fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 2
1858 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 3)
1859 {
1860 unsigned char *buffer =
1861 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1862
1863 /* bsa .+2 */
1864 buffer[0] &= 0x8f;
1865 buffer[0] |= 0x20;
1866 buffer[1] &= 0x07;
1867
1868 /* br .+8 */
1869 md_number_to_chars ((char *) buffer + 2, 0x05c5, 2);
1870
1871 /* Now create the unconditional branch + fixup to the final
1872 target. */
1873 /* jr SYM */
1874 md_number_to_chars ((char *) buffer + 4, 0x02e0, 2);
1875 fix_new (fragP, fragP->fr_fix + 6, 4, fragP->fr_symbol,
1876 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1877
1878 fragP->fr_fix += 10;
1879 }
252b5132
RH		 1880 else
1881 abort ();
1882}
1883
1884valueT
ea1562b3 1885md_section_align (asection *seg, valueT addr)
252b5132
RH		 1886{
1887 int align = bfd_get_section_alignment (stdoutput, seg);
1888 return ((addr + (1 << align) - 1) & (-1 << align));
1889}
1890
1891void
ea1562b3 1892md_begin (void)
252b5132 1893{
28e4f854 1894 char *prev_name = "";
86aba9db 1895 const struct v850_opcode *op;
28e4f854 1896
78c8d46c
NC		 1897 if (strncmp (TARGET_CPU, "v850e3v5", 8) == 0)
1898 {
1899 if (machine == -1)
1900 machine = bfd_mach_v850e3v5;
1901
1902 if (!processor_mask)
1903 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1904 }
1905 else if (strncmp (TARGET_CPU, "v850e2v4", 8) == 0)
1906 {
1907 if (machine == -1)
1908 machine = bfd_mach_v850e3v5;
1909
1910 if (!processor_mask)
1911 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1912 }
1913 else if (strncmp (TARGET_CPU, "v850e2v3", 8) == 0)
1cd986c5
NC		 1914 {
1915 if (machine == -1)
1916 machine = bfd_mach_v850e2v3;
1917
1918 if (!processor_mask)
1919 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3);
1920 }
1921 else if (strncmp (TARGET_CPU, "v850e2", 6) == 0)
1922 {
1923 if (machine == -1)
1924 machine = bfd_mach_v850e2;
1925
1926 if (!processor_mask)
1927 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2);
1928 }
1929 else if (strncmp (TARGET_CPU, "v850e1", 6) == 0)
8ad30312
NC		 1930 {
1931 if (machine == -1)
1cd986c5 1932 machine = bfd_mach_v850e1;
8ad30312 1933
1cd986c5
NC		 1934 if (!processor_mask)
1935 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1);
8ad30312
NC		 1936 }
1937 else if (strncmp (TARGET_CPU, "v850e", 5) == 0)
252b5132
RH		 1938 {
1939 if (machine == -1)
28e4f854
KH		 1940 machine = bfd_mach_v850e;
1941
1cd986c5
NC		 1942 if (!processor_mask)
1943 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E);
252b5132 1944 }
28e4f854 1945 else if (strncmp (TARGET_CPU, "v850", 4) == 0)
252b5132
RH		 1946 {
1947 if (machine == -1)
28e4f854
KH		 1948 machine = 0;
1949
1cd986c5
NC		 1950 if (!processor_mask)
1951 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850);
252b5132
RH		 1952 }
1953 else
28e4f854
KH		 1954 /* xgettext:c-format */
1955 as_bad (_("Unable to determine default target processor from string: %s"),
ec178e1b 1956 TARGET_CPU);
252b5132 1957
685080f2
NC		 1958 if (soft_float == -1)
1959 soft_float = machine < bfd_mach_v850e2v3;
1960
19d63e5d 1961 v850_hash = hash_new ();
252b5132
RH		 1962
1963 /* Insert unique names into hash table. The V850 instruction set
1964 has many identical opcode names that have different opcodes based
1965 on the operands. This hash table then provides a quick index to
1966 the first opcode with a particular name in the opcode table. */
252b5132
RH		 1967 op = v850_opcodes;
1968 while (op->name)
1969 {
28e4f854 1970 if (strcmp (prev_name, op->name))
252b5132
RH		 1971 {
1972 prev_name = (char *) op->name;
1973 hash_insert (v850_hash, op->name, (char *) op);
1974 }
1975 op++;
1976 }
1977
9e0665bc 1978 v850_seg_table[BSS_SECTION].s = bss_section;
de863c74
NC		 1979 bfd_set_arch_mach (stdoutput, v850_target_arch, machine);
1980 bfd_set_private_flags (stdoutput, v850_e_flags);
252b5132
RH		 1981}
1982
1cd986c5 1983
1e50d24d 1984static bfd_reloc_code_real_type
1cd986c5 1985handle_hi016 (const struct v850_operand *operand, const char **errmsg)
1e50d24d 1986{
1cd986c5
NC		 1987 if (operand == NULL)
1988 return BFD_RELOC_HI16;
1e50d24d 1989
1cd986c5
NC		 1990 if (operand->default_reloc == BFD_RELOC_HI16)
1991 return BFD_RELOC_HI16;
1992
1993 if (operand->default_reloc == BFD_RELOC_HI16_S)
1994 return BFD_RELOC_HI16;
1995
1996 if (operand->default_reloc == BFD_RELOC_16)
1997 return BFD_RELOC_HI16;
1998
1999 *errmsg = _("hi0() relocation used on an instruction which does "
2000 "not support it");
2001 return BFD_RELOC_64; /* Used to indicate an error condition. */
1e50d24d
RS		 2002}
2003
252b5132 2004static bfd_reloc_code_real_type
1cd986c5 2005handle_hi16 (const struct v850_operand *operand, const char **errmsg)
252b5132
RH		 2006{
2007 if (operand == NULL)
1cd986c5 2008 return BFD_RELOC_HI16_S;
252b5132 2009
1cd986c5
NC		 2010 if (operand->default_reloc == BFD_RELOC_HI16_S)
2011 return BFD_RELOC_HI16_S;
2012
2013 if (operand->default_reloc == BFD_RELOC_HI16)
2014 return BFD_RELOC_HI16_S;
2015
2016 if (operand->default_reloc == BFD_RELOC_16)
2017 return BFD_RELOC_HI16_S;
28e4f854 2018
1cd986c5
NC		 2019 *errmsg = _("hi() relocation used on an instruction which does "
2020 "not support it");
2021 return BFD_RELOC_64; /* Used to indicate an error condition. */
252b5132
RH		 2022}
2023
2024static bfd_reloc_code_real_type
1cd986c5 2025handle_lo16 (const struct v850_operand *operand, const char **errmsg)
252b5132 2026{
28e4f854 2027 if (operand == NULL)
1cd986c5 2028 return BFD_RELOC_LO16;
28e4f854 2029
1cd986c5
NC		 2030 if (operand->default_reloc == BFD_RELOC_LO16)
2031 return BFD_RELOC_LO16;
28e4f854 2032
1cd986c5
NC		 2033 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
2034 return BFD_RELOC_V850_LO16_SPLIT_OFFSET;
28e4f854 2035
1cd986c5
NC		 2036 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2037 return BFD_RELOC_V850_LO16_S1;
2038
2039 if (operand->default_reloc == BFD_RELOC_16)
2040 return BFD_RELOC_LO16;
28e4f854 2041
1cd986c5
NC		 2042 *errmsg = _("lo() relocation used on an instruction which does "
2043 "not support it");
2044 return BFD_RELOC_64; /* Used to indicate an error condition. */
252b5132
RH		 2045}
2046
2047static bfd_reloc_code_real_type
1cd986c5 2048handle_ctoff (const struct v850_operand *operand, const char **errmsg)
252b5132 2049{
77f730a2
NC		 2050 if (v850_target_arch == bfd_arch_v850_rh850)
2051 {
2052 *errmsg = _("ctoff() is not supported by the rh850 ABI. Use -mgcc-abi instead");
2053 return BFD_RELOC_64; /* Used to indicate an error condition. */
2054 }
2055
28e4f854 2056 if (operand == NULL)
1cd986c5 2057 return BFD_RELOC_V850_CALLT_16_16_OFFSET;
28e4f854 2058
1cd986c5
NC		 2059 if (operand->default_reloc == BFD_RELOC_V850_CALLT_6_7_OFFSET)
2060 return operand->default_reloc;
252b5132 2061
1cd986c5
NC		 2062 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2063 return BFD_RELOC_V850_CALLT_15_16_OFFSET;
28e4f854 2064
1cd986c5
NC		 2065 if (operand->default_reloc == BFD_RELOC_16)
2066 return BFD_RELOC_V850_CALLT_16_16_OFFSET;
28e4f854 2067
1cd986c5
NC		 2068 *errmsg = _("ctoff() relocation used on an instruction which does not support it");
2069 return BFD_RELOC_64; /* Used to indicate an error condition. */
252b5132
RH		 2070}
2071
2072static bfd_reloc_code_real_type
1cd986c5 2073handle_sdaoff (const struct v850_operand *operand, const char **errmsg)
252b5132 2074{
28e4f854 2075 if (operand == NULL)
1cd986c5 2076 return BFD_RELOC_V850_SDA_16_16_OFFSET;
28e4f854 2077
1cd986c5
NC		 2078 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
2079 return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET;
28e4f854 2080
1cd986c5
NC		 2081 if (operand->default_reloc == BFD_RELOC_16)
2082 return BFD_RELOC_V850_SDA_16_16_OFFSET;
28e4f854 2083
1cd986c5
NC		 2084 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2085 return BFD_RELOC_V850_SDA_15_16_OFFSET;
28e4f854 2086
1cd986c5
NC		 2087 *errmsg = _("sdaoff() relocation used on an instruction which does not support it");
2088 return BFD_RELOC_64; /* Used to indicate an error condition. */
252b5132
RH		 2089}
2090
252b5132 2091static bfd_reloc_code_real_type
1cd986c5 2092handle_zdaoff (const struct v850_operand *operand, const char **errmsg)
252b5132 2093{
1cd986c5
NC		 2094 if (operand == NULL)
2095 return BFD_RELOC_V850_ZDA_16_16_OFFSET;
252b5132 2096
1cd986c5
NC		 2097 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
2098 return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET;
252b5132 2099
1cd986c5
NC		 2100 if (operand->default_reloc == BFD_RELOC_16)
2101 return BFD_RELOC_V850_ZDA_16_16_OFFSET;
2102
2103 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2104 return BFD_RELOC_V850_ZDA_15_16_OFFSET;
2105
2106 *errmsg = _("zdaoff() relocation used on an instruction which does not support it");
2107 return BFD_RELOC_64; /* Used to indicate an error condition. */
2108}
2109
2110static bfd_reloc_code_real_type
2111handle_tdaoff (const struct v850_operand *operand, const char **errmsg)
2112{
2113 if (operand == NULL)
2114 /* Data item, not an instruction. */
2115 return BFD_RELOC_V850_TDA_16_16_OFFSET;
2116
2117 switch (operand->default_reloc)
2118 {
2119 /* sld.hu, operand: D5-4. */
2120 case BFD_RELOC_V850_TDA_4_5_OFFSET:
2121 /* sld.bu, operand: D4. */
2122 case BFD_RELOC_V850_TDA_4_4_OFFSET:
2123 /* sld.w/sst.w, operand: D8_6. */
2124 case BFD_RELOC_V850_TDA_6_8_OFFSET:
2125 /* sld.h/sst.h, operand: D8_7. */
2126 case BFD_RELOC_V850_TDA_7_8_OFFSET:
2127 /* sld.b/sst.b, operand: D7. */
2128 case BFD_RELOC_V850_TDA_7_7_OFFSET:
2129 return operand->default_reloc;
2130 default:
2131 break;
2132 }
2133
2134 if (operand->default_reloc == BFD_RELOC_16 && operand->shift == 16)
2135 /* set1 & chums, operands: D16. */
2136 return BFD_RELOC_V850_TDA_16_16_OFFSET;
2137
2138 *errmsg = _("tdaoff() relocation used on an instruction which does not support it");
2139 /* Used to indicate an error condition. */
2140 return BFD_RELOC_64;
2141}
2142
2143/* Warning: The code in this function relies upon the definitions
2144 in the v850_operands[] array (defined in opcodes/v850-opc.c)
2145 matching the hard coded values contained herein. */
2146
2147static bfd_reloc_code_real_type
2148v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg)
2149{
2150 bfd_boolean paren_skipped = FALSE;
2151
2152 /* Skip leading opening parenthesis. */
2153 if (*input_line_pointer == '(')
2154 {
2155 ++input_line_pointer;
2156 paren_skipped = TRUE;
2157 }
2158
2159#define CHECK_(name, reloc) \
ec266e19 2160 if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \
252b5132
RH		 2161 { \
2162 input_line_pointer += strlen (name); \
2163 return reloc; \
2164 }
28e4f854 2165
1cd986c5
NC		 2166 CHECK_ ("hi0", handle_hi016(operand, errmsg) );
2167 CHECK_ ("hi", handle_hi16(operand, errmsg) );
2168 CHECK_ ("lo", handle_lo16 (operand, errmsg) );
2169 CHECK_ ("sdaoff", handle_sdaoff (operand, errmsg));
2170 CHECK_ ("zdaoff", handle_zdaoff (operand, errmsg));
2171 CHECK_ ("tdaoff", handle_tdaoff (operand, errmsg));
2172 CHECK_ ("hilo", BFD_RELOC_32);
2173 CHECK_ ("lo23", BFD_RELOC_V850_23);
2174 CHECK_ ("ctoff", handle_ctoff (operand, errmsg) );
28e4f854 2175
252b5132
RH		 2176 /* Restore skipped parenthesis. */
2177 if (paren_skipped)
28e4f854
KH		 2178 --input_line_pointer;
2179
62ebcb5c 2180 return BFD_RELOC_NONE;
252b5132
RH		 2181}
2182
2183/* Insert an operand value into an instruction. */
2184
2185static unsigned long
ea1562b3
NC		 2186v850_insert_operand (unsigned long insn,
2187 const struct v850_operand *operand,
2188 offsetT val,
1cd986c5 2189 const char **errmsg)
252b5132
RH		 2190{
2191 if (operand->insert)
2192 {
28e4f854
KH		 2193 const char *message = NULL;
2194
2195 insn = operand->insert (insn, val, &message);
252b5132
RH		 2196 if (message != NULL)
2197 {
2198 if ((operand->flags & V850_OPERAND_SIGNED)
2199 && ! warn_signed_overflows
1cd986c5 2200 && v850_msg_is_out_of_range (message))
252b5132 2201 {
28e4f854 2202 /* Skip warning... */
252b5132
RH		 2203 }
2204 else if ((operand->flags & V850_OPERAND_SIGNED) == 0
2205 && ! warn_unsigned_overflows
1cd986c5 2206 && v850_msg_is_out_of_range (message))
252b5132 2207 {
28e4f854 2208 /* Skip warning... */
252b5132 2209 }
252b5132
RH		 2210 else
2211 {
1cd986c5
NC		 2212 if (errmsg != NULL)
2213 *errmsg = message;
252b5132
RH		 2214 }
2215 }
2216 }
1cd986c5
NC		 2217 else if (operand->bits == -1
2218 || operand->flags & V850E_IMMEDIATE16
2219 || operand->flags & V850E_IMMEDIATE23
2220 || operand->flags & V850E_IMMEDIATE32)
2221 {
2222 abort ();
2223 }
252b5132
RH		 2224 else
2225 {
1cd986c5 2226 if (operand->bits < 32)
252b5132 2227 {
28e4f854 2228 long min, max;
252b5132
RH		 2229
2230 if ((operand->flags & V850_OPERAND_SIGNED) != 0)
2231 {
2232 if (! warn_signed_overflows)
2233 max = (1 << operand->bits) - 1;
2234 else
2235 max = (1 << (operand->bits - 1)) - 1;
28e4f854
KH		 2236
2237 min = -(1 << (operand->bits - 1));
252b5132
RH		 2238 }
2239 else
2240 {
2241 max = (1 << operand->bits) - 1;
28e4f854 2242
252b5132 2243 if (! warn_unsigned_overflows)
28e4f854 2244 min = -(1 << (operand->bits - 1));
252b5132
RH		 2245 else
2246 min = 0;
2247 }
28e4f854 2248
dc86b458
SB		 2249 /* Some people write constants with the sign extension done by
2250 hand but only up to 32 bits. This shouldn't really be valid,
2251 but, to permit this code to assemble on a 64-bit host, we
2252 sign extend the 32-bit value to 64 bits if so doing makes the
2253 value valid. */
2254 if (val > max
2255 && (offsetT) (val - 0x80000000 - 0x80000000) >= min
2256 && (offsetT) (val - 0x80000000 - 0x80000000) <= max)
2257 val = val - 0x80000000 - 0x80000000;
2258
2259 /* Similarly, people write expressions like ~(1<<15), and expect
2260 this to be OK for a 32-bit unsigned value. */
2261 else if (val < min
2262 && (offsetT) (val + 0x80000000 + 0x80000000) >= min
2263 && (offsetT) (val + 0x80000000 + 0x80000000) <= max)
2264 val = val + 0x80000000 + 0x80000000;
2265
2266 else if (val < (offsetT) min || val > (offsetT) max)
252b5132 2267 {
04ee5257 2268 static char buf [128];
28e4f854 2269
252b5132
RH		 2270 /* Restore min and mix to expected values for decimal ranges. */
2271 if ((operand->flags & V850_OPERAND_SIGNED)
2272 && ! warn_signed_overflows)
2273 max = (1 << (operand->bits - 1)) - 1;
2274
2275 if (! (operand->flags & V850_OPERAND_SIGNED)
2276 && ! warn_unsigned_overflows)
2277 min = 0;
2278
1cd986c5
NC		 2279 sprintf (buf, _("operand out of range (%d is not between %d and %d)"),
2280 (int) val, (int) min, (int) max);
2281 *errmsg = buf;
252b5132 2282 }
252b5132 2283
1cd986c5
NC		 2284 insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift);
2285 }
2286 else
2287 {
2288 insn |= (((long) val) << operand->shift);
2289 }
252b5132 2290 }
28e4f854 2291
252b5132
RH		 2292 return insn;
2293}
252b5132 2294\f
28e4f854 2295static char copy_of_instruction[128];
252b5132
RH		 2296
2297void
ea1562b3 2298md_assemble (char *str)
252b5132 2299{
28e4f854
KH		 2300 char *s;
2301 char *start_of_operands;
2302 struct v850_opcode *opcode;
2303 struct v850_opcode *next_opcode;
2304 const unsigned char *opindex_ptr;
2305 int next_opindex;
2306 int relaxable = 0;
2307 unsigned long insn;
2308 unsigned long insn_size;
de863c74 2309 char *f = NULL;
28e4f854
KH		 2310 int i;
2311 int match;
b34976b6 2312 bfd_boolean extra_data_after_insn = FALSE;
28e4f854
KH		 2313 unsigned extra_data_len = 0;
2314 unsigned long extra_data = 0;
2315 char *saved_input_line_pointer;
1cd986c5
NC		 2316 char most_match_errmsg[1024];
2317 int most_match_count = -1;
28e4f854 2318
252b5132 2319 strncpy (copy_of_instruction, str, sizeof (copy_of_instruction) - 1);
1cd986c5 2320 most_match_errmsg[0] = 0;
28e4f854 2321
252b5132 2322 /* Get the opcode. */
3882b010 2323 for (s = str; *s != '\0' && ! ISSPACE (*s); s++)
252b5132 2324 continue;
28e4f854 2325
252b5132
RH		 2326 if (*s != '\0')
2327 *s++ = '\0';
2328
28e4f854 2329 /* Find the first opcode with the proper name. */
252b5132
RH		 2330 opcode = (struct v850_opcode *) hash_find (v850_hash, str);
2331 if (opcode == NULL)
2332 {
28e4f854 2333 /* xgettext:c-format */
252b5132
RH		 2334 as_bad (_("Unrecognized opcode: `%s'"), str);
2335 ignore_rest_of_line ();
2336 return;
2337 }
2338
2339 str = s;
3882b010 2340 while (ISSPACE (*str))
28e4f854 2341 ++str;
252b5132
RH		 2342
2343 start_of_operands = str;
2344
2345 saved_input_line_pointer = input_line_pointer;
28e4f854 2346
252b5132
RH		 2347 for (;;)
2348 {
28e4f854 2349 const char *errmsg = NULL;
1cd986c5 2350 const char *warningmsg = NULL;
252b5132
RH		 2351
2352 match = 0;
1cd986c5 2353 opindex_ptr = opcode->operands;
28e4f854 2354
1cd986c5
NC		 2355 if (no_stld23)
2356 {
2357 if ((strncmp (opcode->name, "st.", 3) == 0
2358 && v850_operands[opcode->operands[1]].bits == 23)
2359 || (strncmp (opcode->name, "ld.", 3) == 0
2360 && v850_operands[opcode->operands[0]].bits == 23))
2361 {
2362 errmsg = _("st/ld offset 23 instruction was disabled .");
2363 goto error;
2364 }
2365 }
2366
2367 if ((opcode->processors & processor_mask & PROCESSOR_MASK) == 0
2368 || (((opcode->processors & ~PROCESSOR_MASK) != 0)
2369 && ((opcode->processors & processor_mask & ~PROCESSOR_MASK) == 0)))
252b5132
RH		 2370 {
2371 errmsg = _("Target processor does not support this instruction.");
2372 goto error;
2373 }
28e4f854 2374
252b5132
RH		 2375 relaxable = 0;
2376 fc = 0;
2377 next_opindex = 0;
2378 insn = opcode->opcode;
1cd986c5 2379 extra_data_len = 0;
b34976b6 2380 extra_data_after_insn = FALSE;
252b5132
RH		 2381
2382 input_line_pointer = str = start_of_operands;
2383
28e4f854 2384 for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
252b5132 2385 {
28e4f854
KH		 2386 const struct v850_operand *operand;
2387 char *hold;
2388 expressionS ex;
2389 bfd_reloc_code_real_type reloc;
252b5132
RH		 2390
2391 if (next_opindex == 0)
ea1562b3 2392 operand = &v850_operands[*opindex_ptr];
252b5132
RH		 2393 else
2394 {
28e4f854 2395 operand = &v850_operands[next_opindex];
252b5132
RH		 2396 next_opindex = 0;
2397 }
2398
2399 errmsg = NULL;
2400
1cd986c5
NC		 2401 while (*str == ' ')
2402 ++str;
2403
2404 if (operand->flags & V850_OPERAND_BANG
2405 && *str == '!')
2406 ++str;
2407 else if (operand->flags & V850_OPERAND_PERCENT
2408 && *str == '%')
2409 ++str;
2410
2411 if (*str == ',' || *str == '[' || *str == ']')
2412 ++str;
2413
2414 while (*str == ' ')
28e4f854 2415 ++str;
252b5132 2416
78c8d46c
NC		 2417 if ( (strcmp (opcode->name, "pushsp") == 0
2418 || strcmp (opcode->name, "popsp") == 0
2419 || strcmp (opcode->name, "dbpush") == 0)
2420 && (*str == '-'))
2421 ++str;
2422
252b5132
RH		 2423 if (operand->flags & V850_OPERAND_RELAX)
2424 relaxable = 1;
2425
28e4f854 2426 /* Gather the operand. */
252b5132
RH		 2427 hold = input_line_pointer;
2428 input_line_pointer = str;
28e4f854
KH		 2429
2430 /* lo(), hi(), hi0(), etc... */
62ebcb5c 2431 if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_NONE)
252b5132
RH		 2432 {
2433 /* This is a fake reloc, used to indicate an error condition. */
2434 if (reloc == BFD_RELOC_64)
2435 {
1cd986c5 2436 /* match = 1; */
252b5132
RH		 2437 goto error;
2438 }
28e4f854
KH		 2439
2440 expression (&ex);
252b5132
RH		 2441
2442 if (ex.X_op == O_constant)
2443 {
2444 switch (reloc)
2445 {
2446 case BFD_RELOC_V850_ZDA_16_16_OFFSET:
1cd986c5
NC		 2447 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET:
2448 case BFD_RELOC_V850_ZDA_15_16_OFFSET:
252b5132
RH		 2449 /* To cope with "not1 7, zdaoff(0xfffff006)[r0]"
2450 and the like. */
2451 /* Fall through. */
28e4f854 2452
252b5132 2453 case BFD_RELOC_LO16:
1cd986c5 2454 case BFD_RELOC_V850_LO16_S1:
1e50d24d 2455 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
252b5132
RH		 2456 {
2457 /* Truncate, then sign extend the value. */
2458 ex.X_add_number = SEXT16 (ex.X_add_number);
2459 break;
2460 }
2461
2462 case BFD_RELOC_HI16:
2463 {
2464 /* Truncate, then sign extend the value. */
2465 ex.X_add_number = SEXT16 (ex.X_add_number >> 16);
2466 break;
2467 }
2468
2469 case BFD_RELOC_HI16_S:
2470 {
2471 /* Truncate, then sign extend the value. */
28e4f854 2472 int temp = (ex.X_add_number >> 16) & 0xffff;
252b5132
RH		 2473
2474 temp += (ex.X_add_number >> 15) & 1;
2475
2476 ex.X_add_number = SEXT16 (temp);
2477 break;
2478 }
28e4f854 2479
1cd986c5
NC		 2480 case BFD_RELOC_V850_23:
2481 if ((operand->flags & V850E_IMMEDIATE23) == 0)
2482 {
2483 errmsg = _("immediate operand is too large");
2484 goto error;
2485 }
2486 break;
2487
252b5132 2488 case BFD_RELOC_32:
1cd986c5
NC		 2489 case BFD_RELOC_V850_32_ABS:
2490 case BFD_RELOC_V850_32_PCREL:
252b5132
RH		 2491 if ((operand->flags & V850E_IMMEDIATE32) == 0)
2492 {
2493 errmsg = _("immediate operand is too large");
2494 goto error;
2495 }
28e4f854 2496
252b5132 2497 break;
28e4f854 2498
252b5132 2499 default:
78c8d46c 2500 as_bad (_("AAARG -> unhandled constant reloc: %d"), reloc);
252b5132
RH		 2501 break;
2502 }
2503
1cd986c5
NC		 2504 if (operand->flags & V850E_IMMEDIATE32)
2505 {
2506 extra_data_after_insn = TRUE;
2507 extra_data_len = 4;
2508 extra_data = 0;
2509 }
2510 else if (operand->flags & V850E_IMMEDIATE23)
2511 {
2512 if (reloc != BFD_RELOC_V850_23)
2513 {
2514 errmsg = _("immediate operand is too large");
2515 goto error;
2516 }
2517 extra_data_after_insn = TRUE;
2518 extra_data_len = 2;
2519 extra_data = 0;
2520 }
2521 else if ((operand->flags & V850E_IMMEDIATE16)
2522 || (operand->flags & V850E_IMMEDIATE16HI))
2523 {
2524 if (operand->flags & V850E_IMMEDIATE16HI
2525 && reloc != BFD_RELOC_HI16
2526 && reloc != BFD_RELOC_HI16_S)
2527 {
2528 errmsg = _("immediate operand is too large");
2529 goto error;
2530 }
2531 else if (operand->flags & V850E_IMMEDIATE16
2532 && reloc != BFD_RELOC_LO16)
2533 {
2534 errmsg = _("immediate operand is too large");
2535 goto error;
2536 }
2537
2538 extra_data_after_insn = TRUE;
2539 extra_data_len = 2;
2540 extra_data = 0;
2541 }
2542
252b5132
RH		 2543 if (fc > MAX_INSN_FIXUPS)
2544 as_fatal (_("too many fixups"));
28e4f854
KH		 2545
2546 fixups[fc].exp = ex;
2547 fixups[fc].opindex = *opindex_ptr;
2548 fixups[fc].reloc = reloc;
252b5132
RH		 2549 fc++;
2550 }
1cd986c5 2551 else /* ex.X_op != O_constant. */
252b5132 2552 {
1cd986c5
NC		 2553 if ((reloc == BFD_RELOC_32
2554 || reloc == BFD_RELOC_V850_32_ABS
2555 || reloc == BFD_RELOC_V850_32_PCREL)
2556 && operand->bits < 32)
252b5132 2557 {
1cd986c5
NC		 2558 errmsg = _("immediate operand is too large");
2559 goto error;
2560 }
2561 else if (reloc == BFD_RELOC_V850_23
2562 && (operand->flags & V850E_IMMEDIATE23) == 0)
2563 {
2564 errmsg = _("immediate operand is too large");
2565 goto error;
2566 }
2567 else if ((reloc == BFD_RELOC_HI16
2568 || reloc == BFD_RELOC_HI16_S)
2569 && operand->bits < 16)
2570 {
2571 errmsg = _("immediate operand is too large");
2572 goto error;
2573 }
2574
2575 if (operand->flags & V850E_IMMEDIATE32)
2576 {
2577 extra_data_after_insn = TRUE;
2578 extra_data_len = 4;
2579 extra_data = 0;
2580 }
2581 else if (operand->flags & V850E_IMMEDIATE23)
2582 {
2583 if (reloc != BFD_RELOC_V850_23)
2584 {
2585 errmsg = _("immediate operand is too large");
2586 goto error;
2587 }
2588 extra_data_after_insn = TRUE;
2589 extra_data_len = 2;
2590 extra_data = 0;
2591 }
2592 else if ((operand->flags & V850E_IMMEDIATE16)
2593 || (operand->flags & V850E_IMMEDIATE16HI))
2594 {
2595 if (operand->flags & V850E_IMMEDIATE16HI
2596 && reloc != BFD_RELOC_HI16
2597 && reloc != BFD_RELOC_HI16_S)
2598 {
2599 errmsg = _("immediate operand is too large");
2600 goto error;
2601 }
2602 else if (operand->flags & V850E_IMMEDIATE16
2603 && reloc != BFD_RELOC_LO16)
252b5132
RH		 2604 {
2605 errmsg = _("immediate operand is too large");
2606 goto error;
2607 }
28e4f854 2608
b34976b6 2609 extra_data_after_insn = TRUE;
1cd986c5
NC		 2610 extra_data_len = 2;
2611 extra_data = 0;
252b5132 2612 }
28e4f854 2613
252b5132
RH		 2614 if (fc > MAX_INSN_FIXUPS)
2615 as_fatal (_("too many fixups"));
2616
28e4f854
KH		 2617 fixups[fc].exp = ex;
2618 fixups[fc].opindex = *opindex_ptr;
2619 fixups[fc].reloc = reloc;
252b5132
RH		 2620 fc++;
2621 }
2622 }
1cd986c5
NC		 2623 else if (operand->flags & V850E_IMMEDIATE16
2624 || operand->flags & V850E_IMMEDIATE16HI)
2625 {
2626 expression (&ex);
2627
2628 switch (ex.X_op)
2629 {
2630 case O_constant:
2631 if (operand->flags & V850E_IMMEDIATE16HI)
2632 {
2633 if (ex.X_add_number & 0xffff)
2634 {
2635 errmsg = _("constant too big to fit into instruction");
2636 goto error;
2637 }
2638
2639 ex.X_add_number >>= 16;
2640 }
2641 if (operand->flags & V850E_IMMEDIATE16)
2642 {
78c8d46c
NC		 2643 if ((ex.X_add_number & 0xffff8000)
2644 && ((ex.X_add_number & 0xffff8000) != 0xffff8000))
1cd986c5
NC		 2645 {
2646 errmsg = _("constant too big to fit into instruction");
2647 goto error;
2648 }
2649 }
2650 break;
2651
2652 case O_illegal:
2653 errmsg = _("illegal operand");
2654 goto error;
2655
2656 case O_absent:
2657 errmsg = _("missing operand");
2658 goto error;
2659
2660 default:
2661 if (fc >= MAX_INSN_FIXUPS)
2662 as_fatal (_("too many fixups"));
2663
2664 fixups[fc].exp = ex;
2665 fixups[fc].opindex = *opindex_ptr;
2666 fixups[fc].reloc = operand->default_reloc;
2667 ++fc;
2668
2669 ex.X_add_number = 0;
2670 break;
2671 }
2672
2673 extra_data_after_insn = TRUE;
2674 extra_data_len = 2;
2675 extra_data = ex.X_add_number;
2676 }
2677 else if (operand->flags & V850E_IMMEDIATE23)
2678 {
2679 expression (&ex);
2680
2681 switch (ex.X_op)
2682 {
2683 case O_constant:
2684 break;
2685
2686 case O_illegal:
2687 errmsg = _("illegal operand");
2688 goto error;
2689
2690 case O_absent:
2691 errmsg = _("missing operand");
2692 goto error;
2693
2694 default:
2695 break;
2696 }
2697
2698 if (fc >= MAX_INSN_FIXUPS)
2699 as_fatal (_("too many fixups"));
2700
2701 fixups[fc].exp = ex;
2702 fixups[fc].opindex = *opindex_ptr;
2703 fixups[fc].reloc = operand->default_reloc;
2704 ++fc;
2705
2706 extra_data_after_insn = TRUE;
2707 extra_data_len = 2;
2708 extra_data = 0;
2709 }
2710 else if (operand->flags & V850E_IMMEDIATE32)
2711 {
2712 expression (&ex);
2713
2714 switch (ex.X_op)
2715 {
2716 case O_constant:
2717 if ((operand->default_reloc == BFD_RELOC_V850_32_ABS
2718 || operand->default_reloc == BFD_RELOC_V850_32_PCREL)
2719 && (ex.X_add_number & 1))
2720 {
2721 errmsg = _("odd number cannot be used here");
2722 goto error;
2723 }
2724 break;
2725
2726 case O_illegal:
2727 errmsg = _("illegal operand");
2728 goto error;
2729
2730 case O_absent:
2731 errmsg = _("missing operand");
2732 goto error;
2733
2734 default:
2735 if (fc >= MAX_INSN_FIXUPS)
2736 as_fatal (_("too many fixups"));
2737
2738 fixups[fc].exp = ex;
2739 fixups[fc].opindex = *opindex_ptr;
2740 fixups[fc].reloc = operand->default_reloc;
2741 ++fc;
2742
2743 ex.X_add_number = 0;
2744 break;
2745 }
2746
2747 extra_data_after_insn = TRUE;
2748 extra_data_len = 4;
2749 extra_data = ex.X_add_number;
2750 }
2751 else if (operand->flags & V850E_OPERAND_REG_LIST)
2752 {
2753 errmsg = parse_register_list (&insn, operand);
2754
2755 if (errmsg)
2756 goto error;
2757 }
252b5132
RH		 2758 else
2759 {
2760 errmsg = NULL;
28e4f854
KH		 2761
2762 if ((operand->flags & V850_OPERAND_REG) != 0)
252b5132 2763 {
28e4f854 2764 if (!register_name (&ex))
1cd986c5
NC		 2765 {
2766 errmsg = _("invalid register name");
2767 }
2768
2769 if ((operand->flags & V850_NOT_R0)
28e4f854 2770 && ex.X_add_number == 0)
252b5132
RH		 2771 {
2772 errmsg = _("register r0 cannot be used here");
1cd986c5 2773 }
28e4f854 2774
1cd986c5
NC		 2775 if (operand->flags & V850_REG_EVEN)
2776 {
2777 if (ex.X_add_number % 2)
2778 errmsg = _("odd register cannot be used here");
2779 ex.X_add_number = ex.X_add_number / 2;
252b5132 2780 }
1cd986c5 2781
252b5132 2782 }
28e4f854 2783 else if ((operand->flags & V850_OPERAND_SRG) != 0)
252b5132 2784 {
1cd986c5
NC		 2785 if (!system_register_name (&ex, TRUE))
2786 {
2787 errmsg = _("invalid system register name");
2788 }
252b5132
RH		 2789 }
2790 else if ((operand->flags & V850_OPERAND_EP) != 0)
2791 {
28e4f854
KH		 2792 char *start = input_line_pointer;
2793 char c = get_symbol_end ();
2794
252b5132
RH		 2795 if (strcmp (start, "ep") != 0 && strcmp (start, "r30") != 0)
2796 {
2797 /* Put things back the way we found them. */
2798 *input_line_pointer = c;
2799 input_line_pointer = start;
2800 errmsg = _("expected EP register");
2801 goto error;
2802 }
28e4f854 2803
252b5132
RH		 2804 *input_line_pointer = c;
2805 str = input_line_pointer;
2806 input_line_pointer = hold;
28e4f854
KH		 2807
2808 while (*str == ' ' || *str == ','
2809 || *str == '[' || *str == ']')
2810 ++str;
252b5132
RH		 2811 continue;
2812 }
28e4f854 2813 else if ((operand->flags & V850_OPERAND_CC) != 0)
252b5132 2814 {
1cd986c5 2815 if (!cc_name (&ex, TRUE))
252b5132 2816 {
1cd986c5 2817 errmsg = _("invalid condition code name");
252b5132 2818 }
28e4f854 2819
1cd986c5
NC		 2820 if ((operand->flags & V850_NOT_SA)
2821 && ex.X_add_number == COND_SA_NUM)
2822 {
2823 errmsg = _("condition sa cannot be used here");
2824 }
252b5132 2825 }
1cd986c5 2826 else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0)
252b5132 2827 {
1cd986c5
NC		 2828 if (!float_cc_name (&ex, TRUE))
2829 {
2830 errmsg = _("invalid condition code name");
2831 }
252b5132 2832 }
78c8d46c
NC		 2833 else if ((operand->flags & V850_OPERAND_CACHEOP) != 0)
2834 {
2835 if (!cacheop_name (&ex, TRUE))
2836 errmsg = _("invalid cache oparation name");
2837 }
2838 else if ((operand->flags & V850_OPERAND_PREFOP) != 0)
2839 {
2840 if (!prefop_name (&ex, TRUE))
2841 errmsg = _("invalid pref oparation name");
2842 }
2843 else if ((operand->flags & V850_OPERAND_VREG) != 0)
2844 {
2845 if (!vector_register_name (&ex))
2846 errmsg = _("invalid vector register name");
2847 }
1cd986c5
NC		 2848 else if ((register_name (&ex)
2849 && (operand->flags & V850_OPERAND_REG) == 0))
252b5132
RH		 2850 {
2851 char c;
28e4f854
KH		 2852 int exists = 0;
2853
252b5132
RH		 2854 /* It is possible that an alias has been defined that
2855 matches a register name. For example the code may
2856 include a ".set ZERO, 0" directive, which matches
2857 the register name "zero". Attempt to reparse the
2858 field as an expression, and only complain if we
2859 cannot generate a constant. */
2860
2861 input_line_pointer = str;
2862
2863 c = get_symbol_end ();
28e4f854 2864
252b5132
RH		 2865 if (symbol_find (str) != NULL)
2866 exists = 1;
28e4f854
KH		 2867
2868 *input_line_pointer = c;
252b5132 2869 input_line_pointer = str;
28e4f854
KH		 2870
2871 expression (&ex);
252b5132
RH		 2872
2873 if (ex.X_op != O_constant)
2874 {
33b7f697 2875 /* If this register is actually occurring too early on
252b5132
RH		 2876 the parsing of the instruction, (because another
2877 field is missing) then report this. */
2878 if (opindex_ptr[1] != 0
1cd986c5
NC		 2879 && ((v850_operands[opindex_ptr[1]].flags
2880 & V850_OPERAND_REG)
2881 ||(v850_operands[opindex_ptr[1]].flags
2882 & V850_OPERAND_VREG)))
252b5132
RH		 2883 errmsg = _("syntax error: value is missing before the register name");
2884 else
2885 errmsg = _("syntax error: register not expected");
2886
28e4f854
KH		 2887 /* If we created a symbol in the process of this
2888 test then delete it now, so that it will not
2889 be output with the real symbols... */
252b5132
RH		 2890 if (exists == 0
2891 && ex.X_op == O_symbol)
2892 symbol_remove (ex.X_add_symbol,
28e4f854 2893 &symbol_rootP, &symbol_lastP);
252b5132
RH		 2894 }
2895 }
1cd986c5 2896 else if (system_register_name (&ex, FALSE)
252b5132 2897 && (operand->flags & V850_OPERAND_SRG) == 0)
1cd986c5
NC		 2898 {
2899 errmsg = _("syntax error: system register not expected");
2900 }
2901 else if (cc_name (&ex, FALSE)
252b5132 2902 && (operand->flags & V850_OPERAND_CC) == 0)
1cd986c5
NC		 2903 {
2904 errmsg = _("syntax error: condition code not expected");
2905 }
2906 else if (float_cc_name (&ex, FALSE)
2907 && (operand->flags & V850_OPERAND_FLOAT_CC) == 0)
2908 {
2909 errmsg = _("syntax error: condition code not expected");
2910 }
78c8d46c
NC		 2911 else if (vector_register_name (&ex)
2912 && (operand->flags & V850_OPERAND_VREG) == 0)
2913 {
2914 errmsg = _("syntax error: vector register not expected");
2915 }
252b5132
RH		 2916 else
2917 {
28e4f854 2918 expression (&ex);
1cd986c5
NC		 2919
2920 if ((operand->flags & V850_NOT_IMM0)
2921 && ex.X_op == O_constant
2922 && ex.X_add_number == 0)
2923 {
2924 errmsg = _("immediate 0 cannot be used here");
2925 }
2926
252b5132 2927 /* Special case:
1cd986c5 2928 If we are assembling a MOV/JARL/JR instruction and the immediate
50b15da2 2929 value does not fit into the bits available then create a
1cd986c5 2930 fake error so that the next MOV/JARL/JR instruction will be
50b15da2 2931 selected. This one has a 32 bit immediate field. */
252b5132 2932
1cd986c5
NC		 2933 if ((strcmp (opcode->name, "mov") == 0
2934 || strcmp (opcode->name, "jarl") == 0
2935 || strcmp (opcode->name, "jr") == 0)
252b5132 2936 && ex.X_op == O_constant
28e4f854 2937 && (ex.X_add_number < (-(1 << (operand->bits - 1)))
03223580 2938 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1)))
1cd986c5
NC		 2939 {
2940 errmsg = _("immediate operand is too large");
2941 }
2942
2943 if ((strcmp (opcode->name, "jarl") == 0
2944 || strcmp (opcode->name, "jr") == 0)
2945 && ex.X_op != O_constant
2946 && operand->bits != default_disp_size)
2947 {
2948 errmsg = _("immediate operand is not match");
2949 }
78c8d46c
NC		 2950
2951 /* Special case2 :
2952 If we are assembling a ld/st instruction and the immediate
2953 value does not fit into the bits available then create a
2954 fake error so that the next ld/st instruction will be
2955 selected. */
2956 if ( ( (strncmp (opcode->name, "st.", 3) == 0)
2957 || (strncmp (opcode->name, "ld.", 3) == 0))
2958 && ex.X_op == O_constant
2959 && (ex.X_add_number < (-(1 << (operand->bits - 1)))
2960 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1)))
2961 errmsg = _("displacement is too large");
252b5132
RH		 2962 }
2963
2964 if (errmsg)
2965 goto error;
252b5132 2966
28e4f854 2967 switch (ex.X_op)
252b5132
RH		 2968 {
2969 case O_illegal:
2970 errmsg = _("illegal operand");
2971 goto error;
2972 case O_absent:
2973 errmsg = _("missing operand");
2974 goto error;
2975 case O_register:
28e4f854 2976 if ((operand->flags
1cd986c5 2977 & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_VREG)) == 0)
252b5132
RH		 2978 {
2979 errmsg = _("invalid operand");
2980 goto error;
2981 }
1cd986c5
NC		 2982
2983 insn = v850_insert_operand (insn, operand,
2984 ex.X_add_number,
2985 &warningmsg);
2986
252b5132
RH		 2987 break;
2988
2989 case O_constant:
2990 insn = v850_insert_operand (insn, operand, ex.X_add_number,
1cd986c5 2991 &warningmsg);
252b5132
RH		 2992 break;
2993
2994 default:
2995 /* We need to generate a fixup for this expression. */
2996 if (fc >= MAX_INSN_FIXUPS)
2997 as_fatal (_("too many fixups"));
2998
28e4f854
KH		 2999 fixups[fc].exp = ex;
3000 fixups[fc].opindex = *opindex_ptr;
62ebcb5c 3001 fixups[fc].reloc = BFD_RELOC_NONE;
252b5132
RH		 3002 ++fc;
3003 break;
3004 }
3005 }
3006
3007 str = input_line_pointer;
3008 input_line_pointer = hold;
3009
3010 while (*str == ' ' || *str == ',' || *str == '[' || *str == ']'
3011 || *str == ')')
3012 ++str;
3013 }
1cd986c5
NC		 3014
3015 while (ISSPACE (*str))
3016 ++str;
3017
3018 if (*str == '\0')
3019 match = 1;
252b5132
RH		 3020
3021 error:
3022 if (match == 0)
28e4f854 3023 {
1cd986c5
NC		 3024 if ((opindex_ptr - opcode->operands) >= most_match_count)
3025 {
3026 most_match_count = opindex_ptr - opcode->operands;
3027 if (errmsg != NULL)
3028 strncpy (most_match_errmsg, errmsg, sizeof (most_match_errmsg)-1);
3029 }
3030
252b5132
RH		 3031 next_opcode = opcode + 1;
3032 if (next_opcode->name != NULL
3033 && strcmp (next_opcode->name, opcode->name) == 0)
3034 {
3035 opcode = next_opcode;
3036
3037 /* Skip versions that are not supported by the target
3038 processor. */
3039 if ((opcode->processors & processor_mask) == 0)
3040 goto error;
28e4f854 3041
252b5132
RH		 3042 continue;
3043 }
28e4f854 3044
1cd986c5
NC		 3045 if (most_match_errmsg[0] == 0)
3046 /* xgettext:c-format. */
3047 as_bad (_("junk at end of line: `%s'"), str);
3048 else
3049 as_bad ("%s: %s", copy_of_instruction, most_match_errmsg);
28e4f854
KH		 3050
3051 if (*input_line_pointer == ']')
3052 ++input_line_pointer;
3053
252b5132
RH		 3054 ignore_rest_of_line ();
3055 input_line_pointer = saved_input_line_pointer;
3056 return;
28e4f854 3057 }
1cd986c5
NC		 3058
3059 if (warningmsg != NULL)
cd94c7fb 3060 as_warn ("%s", warningmsg);
252b5132
RH		 3061 break;
3062 }
28e4f854 3063
252b5132
RH		 3064 input_line_pointer = str;
3065
9fcc94b6
AM		 3066 /* Tie dwarf2 debug info to the address at the start of the insn.
3067 We can't do this after the insn has been output as the current
3068 frag may have been closed off. eg. by frag_var. */
3069 dwarf2_emit_insn (0);
3070
28e4f854
KH		 3071 /* Write out the instruction. */
3072
252b5132
RH		 3073 if (relaxable && fc > 0)
3074 {
3075 insn_size = 2;
3076 fc = 0;
3077
78c8d46c
NC		 3078 if (strcmp (opcode->name, "loop") == 0)
3079 {
3080 if (((processor_mask & PROCESSOR_V850E3V5_UP) == 0) || default_disp_size == 22)
3081 {
3082 insn_size = 4;
3083 f = frag_var (rs_machine_dependent, 6, 2, SUBYPTE_LOOP_16_22,
3084 fixups[0].exp.X_add_symbol,
3085 fixups[0].exp.X_add_number,
3086 (char *)(size_t) fixups[0].opindex);
3087 md_number_to_chars (f, insn, insn_size);
3088 md_number_to_chars (f+4, 0, 4);
3089 }
3090 else
3091 {
3092 as_bad (_("loop: 32-bit displacement not supported"));
3093 }
3094 }
3095 else if (strcmp (opcode->name, "br") == 0
3096 || strcmp (opcode->name, "jbr") == 0)
252b5132 3097 {
78c8d46c 3098 if ((processor_mask & PROCESSOR_V850E2_UP) == 0 || default_disp_size == 22)
1cd986c5
NC		 3099 {
3100 f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22,
3101 fixups[0].exp.X_add_symbol,
3102 fixups[0].exp.X_add_number,
3103 (char *)(size_t) fixups[0].opindex);
3104 md_number_to_chars (f, insn, insn_size);
3105 md_number_to_chars (f + 2, 0, 2);
3106 }
3107 else
3108 {
3109 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_UNCOND_9_22_32,
3110 fixups[0].exp.X_add_symbol,
3111 fixups[0].exp.X_add_number,
3112 (char *)(size_t) fixups[0].opindex);
3113 md_number_to_chars (f, insn, insn_size);
3114 md_number_to_chars (f + 2, 0, 4);
3115 }
252b5132 3116 }
1cd986c5 3117 else /* b<cond>, j<cond>. */
252b5132 3118 {
1cd986c5 3119 if (default_disp_size == 22
78c8d46c 3120 || (processor_mask & PROCESSOR_V850E2_UP) == 0)
1cd986c5 3121 {
78c8d46c 3122 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17)
1cd986c5
NC		 3123 {
3124 if (strcmp (opcode->name, "bsa") == 0)
3125 {
3126 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_17_22,
3127 fixups[0].exp.X_add_symbol,
3128 fixups[0].exp.X_add_number,
3129 (char *)(size_t) fixups[0].opindex);
3130 md_number_to_chars (f, insn, insn_size);
3131 md_number_to_chars (f + 2, 0, 6);
3132 }
3133 else
3134 {
3135 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_17_22,
3136 fixups[0].exp.X_add_symbol,
3137 fixups[0].exp.X_add_number,
3138 (char *)(size_t) fixups[0].opindex);
3139 md_number_to_chars (f, insn, insn_size);
3140 md_number_to_chars (f + 2, 0, 4);
3141 }
3142 }
3143 else
3144 {
3145 if (strcmp (opcode->name, "bsa") == 0)
3146 {
3147 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_22,
3148 fixups[0].exp.X_add_symbol,
3149 fixups[0].exp.X_add_number,
3150 (char *)(size_t) fixups[0].opindex);
3151 md_number_to_chars (f, insn, insn_size);
3152 md_number_to_chars (f + 2, 0, 6);
3153 }
3154 else
3155 {
3156 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_22,
3157 fixups[0].exp.X_add_symbol,
3158 fixups[0].exp.X_add_number,
3159 (char *)(size_t) fixups[0].opindex);
3160 md_number_to_chars (f, insn, insn_size);
3161 md_number_to_chars (f + 2, 0, 4);
3162 }
3163 }
3164 }
3165 else
3166 {
78c8d46c 3167 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17)
1cd986c5
NC		 3168 {
3169 if (strcmp (opcode->name, "bsa") == 0)
3170 {
3171 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_17_22_32,
3172 fixups[0].exp.X_add_symbol,
3173 fixups[0].exp.X_add_number,
3174 (char *)(size_t) fixups[0].opindex);
3175 md_number_to_chars (f, insn, insn_size);
3176 md_number_to_chars (f + 2, 0, 8);
3177 }
3178 else
3179 {
3180 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_17_22_32,
3181 fixups[0].exp.X_add_symbol,
3182 fixups[0].exp.X_add_number,
3183 (char *)(size_t) fixups[0].opindex);
3184 md_number_to_chars (f, insn, insn_size);
3185 md_number_to_chars (f + 2, 0, 6);
3186 }
3187 }
3188 else
3189 {
3190 if (strcmp (opcode->name, "bsa") == 0)
3191 {
3192 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_22_32,
3193 fixups[0].exp.X_add_symbol,
3194 fixups[0].exp.X_add_number,
3195 (char *)(size_t) fixups[0].opindex);
3196 md_number_to_chars (f, insn, insn_size);
3197 md_number_to_chars (f + 2, 0, 8);
3198 }
3199 else
3200 {
3201 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_22_32,
3202 fixups[0].exp.X_add_symbol,
3203 fixups[0].exp.X_add_number,
3204 (char *)(size_t) fixups[0].opindex);
3205 md_number_to_chars (f, insn, insn_size);
3206 md_number_to_chars (f + 2, 0, 6);
3207 }
3208 }
3209 }
252b5132
RH		 3210 }
3211 }
28e4f854 3212 else
252b5132
RH		 3213 {
3214 /* Four byte insns have an opcode with the two high bits on. */
3215 if ((insn & 0x0600) == 0x0600)
3216 insn_size = 4;
3217 else
3218 insn_size = 2;
3219
28e4f854 3220 /* Special case: 32 bit MOV. */
252b5132
RH		 3221 if ((insn & 0xffe0) == 0x0620)
3222 insn_size = 2;
28e4f854 3223
1cd986c5
NC		 3224 /* Special case: 32 bit JARL,JMP,JR. */
3225 if ((insn & 0x1ffe0) == 0x2e0 /* JARL. */
3226 || (insn & 0x1ffe0) == 0x6e0 /* JMP. */
3227 || (insn & 0x1ffff) == 0x2e0) /* JR. */
3228 insn_size = 2;
3229
78c8d46c
NC		 3230 if (obstack_room (& frchain_now->frch_obstack) < (insn_size + extra_data_len))
3231 {
3232 frag_wane (frag_now);
3233 frag_new (0);
3234 }
3235
252b5132 3236 f = frag_more (insn_size);
252b5132
RH		 3237 md_number_to_chars (f, insn, insn_size);
3238
3239 if (extra_data_after_insn)
3240 {
3241 f = frag_more (extra_data_len);
252b5132
RH		 3242 md_number_to_chars (f, extra_data, extra_data_len);
3243
b34976b6 3244 extra_data_after_insn = FALSE;
252b5132
RH		 3245 }
3246 }
3247
3248 /* Create any fixups. At this point we do not use a
3249 bfd_reloc_code_real_type, but instead just use the
3250 BFD_RELOC_UNUSED plus the operand index. This lets us easily
3251 handle fixups for any operand type, although that is admittedly
3252 not a very exciting feature. We pick a BFD reloc type in
55cf6793 3253 md_apply_fix. */
252b5132
RH		 3254 for (i = 0; i < fc; i++)
3255 {
28e4f854
KH		 3256 const struct v850_operand *operand;
3257 bfd_reloc_code_real_type reloc;
3258
3259 operand = &v850_operands[fixups[i].opindex];
252b5132
RH		 3260
3261 reloc = fixups[i].reloc;
28e4f854 3262
62ebcb5c 3263 if (reloc != BFD_RELOC_NONE)
252b5132 3264 {
28e4f854
KH		 3265 reloc_howto_type *reloc_howto =
3266 bfd_reloc_type_lookup (stdoutput, reloc);
3267 int size;
3268 int address;
3269 fixS *fixP;
252b5132
RH		 3270
3271 if (!reloc_howto)
28e4f854
KH		 3272 abort ();
3273
252b5132
RH		 3274 size = bfd_get_reloc_size (reloc_howto);
3275
3276 /* XXX This will abort on an R_V850_8 reloc -
28e4f854
KH		 3277 is this reloc actually used? */
3278 if (size != 2 && size != 4)
252b5132
RH		 3279 abort ();
3280
1cd986c5
NC		 3281 if (extra_data_len == 0)
3282 {
3283 address = (f - frag_now->fr_literal) + insn_size - size;
3284 }
3285 else
3286 {
3287 address = (f - frag_now->fr_literal) + extra_data_len - size;
3288 }
252b5132 3289
1cd986c5
NC		 3290 if ((operand->flags & V850E_IMMEDIATE32) && (operand->flags & V850_PCREL))
3291 {
3292 fixups[i].exp.X_add_number += 2;
3293 }
3294 else if (operand->default_reloc == BFD_RELOC_V850_16_PCREL)
3295 {
3296 fixups[i].exp.X_add_number += 2;
3297 address += 2;
3298 }
28e4f854 3299
1cd986c5 3300 /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */
252b5132 3301 fixP = fix_new_exp (frag_now, address, size,
28e4f854 3302 &fixups[i].exp,
252b5132
RH		 3303 reloc_howto->pc_relative,
3304 reloc);
3305
2d034539
NC		 3306 fixP->tc_fix_data = (void *) operand;
3307
252b5132
RH		 3308 switch (reloc)
3309 {
3310 case BFD_RELOC_LO16:
1cd986c5 3311 case BFD_RELOC_V850_LO16_S1:
1e50d24d 3312 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
252b5132
RH		 3313 case BFD_RELOC_HI16:
3314 case BFD_RELOC_HI16_S:
3315 fixP->fx_no_overflow = 1;
3316 break;
5480ccf3
NC		 3317 default:
3318 break;
252b5132
RH		 3319 }
3320 }
3321 else
3322 {
78c8d46c 3323 gas_assert (f != NULL);
28e4f854 3324 fix_new_exp (frag_now,
252b5132
RH		 3325 f - frag_now->fr_literal, 4,
3326 & fixups[i].exp,
1cd986c5 3327 (operand->flags & V850_PCREL) != 0,
252b5132 3328 (bfd_reloc_code_real_type) (fixups[i].opindex
28e4f854 3329 + (int) BFD_RELOC_UNUSED));
252b5132
RH		 3330 }
3331 }
3332
3333 input_line_pointer = saved_input_line_pointer;
3334}
3335
28e4f854
KH		 3336/* If while processing a fixup, a reloc really needs to be created
3337 then it is done here. */
252b5132 3338
252b5132 3339arelent *
ea1562b3 3340tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
252b5132 3341{
28e4f854
KH		 3342 arelent *reloc;
3343
ea1562b3
NC		 3344 reloc = xmalloc (sizeof (arelent));
3345 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
28e4f854
KH		 3346 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3347 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
e30ddb24
NC		 3348
3349 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
3350 || fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3351 || fixp->fx_r_type == BFD_RELOC_V850_LONGCALL
3352 || fixp->fx_r_type == BFD_RELOC_V850_LONGJUMP
3353 || fixp->fx_r_type == BFD_RELOC_V850_ALIGN)
3354 reloc->addend = fixp->fx_offset;
3355 else
3356 {
1cd986c5 3357#if 0
e30ddb24
NC		 3358 if (fixp->fx_r_type == BFD_RELOC_32
3359 && fixp->fx_pcrel)
3360 fixp->fx_r_type = BFD_RELOC_32_PCREL;
1cd986c5 3361#endif
e30ddb24
NC		 3362
3363 reloc->addend = fixp->fx_addnumber;
3364 }
3365
ec178e1b 3366 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
252b5132 3367
ea1562b3 3368 if (reloc->howto == NULL)
252b5132
RH		 3369 {
3370 as_bad_where (fixp->fx_file, fixp->fx_line,
28e4f854
KH		 3371 /* xgettext:c-format */
3372 _("reloc %d not supported by object file format"),
252b5132
RH		 3373 (int) fixp->fx_r_type);
3374
3375 xfree (reloc);
28e4f854 3376
252b5132
RH		 3377 return NULL;
3378 }
28e4f854 3379
252b5132
RH		 3380 return reloc;
3381}
3382
86aba9db 3383void
ea1562b3 3384v850_handle_align (fragS * frag)
86aba9db
NC		 3385{
3386 if (v850_relax
3387 && frag->fr_type == rs_align
3388 && frag->fr_address + frag->fr_fix > 0
3389 && frag->fr_offset > 1
3390 && now_seg != bss_section
3391 && now_seg != v850_seg_table[SBSS_SECTION].s
3392 && now_seg != v850_seg_table[TBSS_SECTION].s
3393 && now_seg != v850_seg_table[ZBSS_SECTION].s)
3394 fix_new (frag, frag->fr_fix, 2, & abs_symbol, frag->fr_offset, 0,
ec178e1b 3395 BFD_RELOC_V850_ALIGN);
86aba9db
NC		 3396}
3397
606ab118 3398/* Return current size of variable part of frag. */
28e4f854 3399
252b5132 3400int
ea1562b3 3401md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED)
252b5132 3402{
606ab118 3403 if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0]))
252b5132 3404 abort ();
606ab118
AM		 3405
3406 return md_relax_table[fragp->fr_subtype].rlx_length;
28e4f854 3407}
252b5132
RH		 3408
3409long
ea1562b3 3410v850_pcrel_from_section (fixS *fixp, segT section)
252b5132
RH		 3411{
3412 /* If the symbol is undefined, or in a section other than our own,
d6c497c7 3413 or it is weak (in which case it may well be in another section,
252b5132
RH		 3414 then let the linker figure it out. */
3415 if (fixp->fx_addsy != (symbolS *) NULL
3416 && (! S_IS_DEFINED (fixp->fx_addsy)
d6c497c7 3417 || S_IS_WEAK (fixp->fx_addsy)
252b5132 3418 || (S_GET_SEGMENT (fixp->fx_addsy) != section)))
d6c497c7 3419 return 0;
28e4f854 3420
252b5132
RH		 3421 return fixp->fx_frag->fr_address + fixp->fx_where;
3422}
3423
94f592af 3424void
55cf6793 3425md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
252b5132 3426{
94f592af 3427 valueT value = * valueP;
28e4f854 3428 char *where;
252b5132 3429
94f592af 3430 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
86aba9db
NC		 3431 || fixP->fx_r_type == BFD_RELOC_V850_LONGCALL
3432 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP
94f592af 3433 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
252b5132 3434 {
94f592af
NC		 3435 fixP->fx_done = 0;
3436 return;
252b5132
RH		 3437 }
3438
94f592af 3439 if (fixP->fx_addsy == (symbolS *) NULL)
86aba9db 3440 fixP->fx_addnumber = value,
94f592af
NC		 3441 fixP->fx_done = 1;
3442
3443 else if (fixP->fx_pcrel)
86aba9db 3444 fixP->fx_addnumber = fixP->fx_offset;
94f592af 3445
252b5132
RH		 3446 else
3447 {
94f592af
NC		 3448 value = fixP->fx_offset;
3449 if (fixP->fx_subsy != (symbolS *) NULL)
252b5132 3450 {
94f592af
NC		 3451 if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section)
3452 value -= S_GET_VALUE (fixP->fx_subsy);
252b5132 3453 else
ea1562b3
NC		 3454 /* We don't actually support subtracting a symbol. */
3455 as_bad_where (fixP->fx_file, fixP->fx_line,
3456 _("expression too complex"));
252b5132 3457 }
86aba9db 3458 fixP->fx_addnumber = value;
252b5132
RH		 3459 }
3460
94f592af 3461 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
252b5132 3462 {
28e4f854
KH		 3463 int opindex;
3464 const struct v850_operand *operand;
3465 unsigned long insn;
1cd986c5 3466 const char *errmsg = NULL;
252b5132 3467
94f592af 3468 opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
28e4f854 3469 operand = &v850_operands[opindex];
252b5132
RH		 3470
3471 /* Fetch the instruction, insert the fully resolved operand
ec178e1b 3472 value, and stuff the instruction back again.
252b5132
RH		 3473
3474 Note the instruction has been stored in little endian
3475 format! */
94f592af 3476 where = fixP->fx_frag->fr_literal + fixP->fx_where;
252b5132 3477
1cd986c5
NC		 3478 if (fixP->fx_size > 2)
3479 insn = bfd_getl32 ((unsigned char *) where);
3480 else
3481 insn = bfd_getl16 ((unsigned char *) where);
3482
86d27af6
NC		 3483 /* When inserting loop offets a backwards displacement
3484 is encoded as a positive value. */
3485 if (operand->flags & V850_INVERSE_PCREL)
3486 value = - value;
3487
252b5132 3488 insn = v850_insert_operand (insn, operand, (offsetT) value,
1cd986c5
NC		 3489 &errmsg);
3490 if (errmsg)
cd94c7fb 3491 as_warn_where (fixP->fx_file, fixP->fx_line, "%s", errmsg);
1cd986c5
NC		 3492
3493 if (fixP->fx_size > 2)
3494 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
3495 else
3496 bfd_putl16 ((bfd_vma) insn, (unsigned char *) where);
252b5132 3497
94f592af
NC		 3498 if (fixP->fx_done)
3499 /* Nothing else to do here. */
3500 return;
252b5132 3501
28e4f854
KH		 3502 /* Determine a BFD reloc value based on the operand information.
3503 We are only prepared to turn a few of the operands into relocs. */
252b5132 3504
1cd986c5 3505 if (operand->default_reloc == BFD_RELOC_NONE)
252b5132 3506 {
94f592af 3507 as_bad_where (fixP->fx_file, fixP->fx_line,
28e4f854 3508 _("unresolved expression that must be resolved"));
94f592af
NC		 3509 fixP->fx_done = 1;
3510 return;
252b5132 3511 }
1cd986c5
NC		 3512
3513 {
3514 fixP->fx_r_type = operand->default_reloc;
3515 if (operand->default_reloc == BFD_RELOC_V850_16_PCREL)
3516 {
3517 fixP->fx_where += 2;
3518 fixP->fx_size = 2;
3519 fixP->fx_addnumber += 2;
3520 }
3521 }
252b5132 3522 }
94f592af 3523 else if (fixP->fx_done)
252b5132
RH		 3524 {
3525 /* We still have to insert the value into memory! */
94f592af 3526 where = fixP->fx_frag->fr_literal + fixP->fx_where;
252b5132 3527
a0ef61f7 3528 if (fixP->tc_fix_data != NULL
1cd986c5
NC		 3529 && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL)
3530 {
3531 const char * message = NULL;
3532 struct v850_operand * operand = (struct v850_operand *) fixP->tc_fix_data;
3533 unsigned long insn;
3534
3535 /* The variable "where" currently points at the exact point inside
3536 the insn where we need to insert the value. But we need to
3537 extract the entire insn so we probably need to move "where"
3538 back a few bytes. */
3539
3540 if (fixP->fx_size == 2)
3541 where -= 2;
3542 else if (fixP->fx_size == 1)
3543 where -= 3;
3544
3545 insn = bfd_getl32 ((unsigned char *) where);
3546
3547 /* Use the operand's insertion procedure, if present, in order to
3548 make sure that the value is correctly stored in the insn. */
3549 insn = operand->insert (insn, (offsetT) value, & message);
3550 /* Ignore message even if it is set. */
3551
3552 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
3553 }
2d034539 3554 else
1cd986c5
NC		 3555 {
3556 switch (fixP->fx_r_type)
3557 {
3558 case BFD_RELOC_V850_32_ABS:
3559 case BFD_RELOC_V850_32_PCREL:
3560 bfd_putl32 (value & 0xfffffffe, (unsigned char *) where);
3561 break;
3562
3563 case BFD_RELOC_32:
3564 bfd_putl32 (value, (unsigned char *) where);
3565 break;
3566
3567 case BFD_RELOC_V850_23:
3568 bfd_putl32 (((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7))
3569 | (bfd_getl32 (where) & ~((0x7f << 4) | (0xffff << 16))),
3570 (unsigned char *) where);
3571 break;
3572
3573 case BFD_RELOC_16:
3574 case BFD_RELOC_HI16:
3575 case BFD_RELOC_HI16_S:
3576 case BFD_RELOC_LO16:
3577 case BFD_RELOC_V850_ZDA_16_16_OFFSET:
3578 case BFD_RELOC_V850_SDA_16_16_OFFSET:
3579 case BFD_RELOC_V850_TDA_16_16_OFFSET:
3580 case BFD_RELOC_V850_CALLT_16_16_OFFSET:
3581 bfd_putl16 (value & 0xffff, (unsigned char *) where);
3582 break;
3583
3584 case BFD_RELOC_8:
3585 *where = value & 0xff;
3586 break;
3587
3588 case BFD_RELOC_V850_9_PCREL:
3589 bfd_putl16 (((value & 0x1f0) << 7) | ((value & 0x0e) << 3)
3590 | (bfd_getl16 (where) & ~((0x1f0 << 7) | (0x0e << 3))), where);
3591 break;
3592
3593 case BFD_RELOC_V850_17_PCREL:
3594 bfd_putl32 (((value & 0x10000) >> (16 - 4)) | ((value & 0xfffe) << 16)
3595 | (bfd_getl32 (where) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where);
3596 break;
3597
3598 case BFD_RELOC_V850_16_PCREL:
de863c74
NC		 3599 bfd_putl16 ((-value & 0xfffe) | (bfd_getl16 (where + 2) & 0x0001),
3600 (unsigned char *) (where + 2));
1cd986c5
NC		 3601 break;
3602
3603 case BFD_RELOC_V850_22_PCREL:
3604 bfd_putl32 (((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16)
3605 | (bfd_getl32 (where) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where);
3606 break;
3607
3608 case BFD_RELOC_V850_16_S1:
3609 case BFD_RELOC_V850_LO16_S1:
3610 case BFD_RELOC_V850_ZDA_15_16_OFFSET:
3611 case BFD_RELOC_V850_SDA_15_16_OFFSET:
3612 bfd_putl16 (value & 0xfffe, (unsigned char *) where);
3613 break;
3614
3615 case BFD_RELOC_V850_16_SPLIT_OFFSET:
3616 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
3617 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET:
3618 case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET:
3619 bfd_putl32 (((value << 16) & 0xfffe0000)
3620 | ((value << 5) & 0x20)
3621 | (bfd_getl32 (where) & ~0xfffe0020), where);
3622 break;
3623
3624 case BFD_RELOC_V850_TDA_6_8_OFFSET:
3625 *where = (*where & ~0x7e) | ((value >> 1) & 0x7e);
3626 break;
3627
3628 case BFD_RELOC_V850_TDA_7_8_OFFSET:
3629 *where = (*where & ~0x7f) | ((value >> 1) & 0x7f);
3630 break;
3631
3632 case BFD_RELOC_V850_TDA_7_7_OFFSET:
3633 *where = (*where & ~0x7f) | (value & 0x7f);
3634 break;
3635
3636 case BFD_RELOC_V850_TDA_4_5_OFFSET:
3637 *where = (*where & ~0xf) | ((value >> 1) & 0xf);
3638 break;
3639
3640 case BFD_RELOC_V850_TDA_4_4_OFFSET:
3641 *where = (*where & ~0xf) | (value & 0xf);
3642 break;
3643
3644 case BFD_RELOC_V850_CALLT_6_7_OFFSET:
3645 *where = (*where & ~0x3f) | (value & 0x3f);
3646 break;
3647
3648 default:
3649 abort ();
3650 }
3651 }
252b5132 3652 }
252b5132 3653}
1cd986c5 3654
252b5132
RH		 3655/* Parse a cons expression. We have to handle hi(), lo(), etc
3656 on the v850. */
28e4f854 3657
62ebcb5c 3658bfd_reloc_code_real_type
ea1562b3 3659parse_cons_expression_v850 (expressionS *exp)
252b5132 3660{
1cd986c5 3661 const char *errmsg;
62ebcb5c
AM		 3662 bfd_reloc_code_real_type r;
3663
252b5132 3664 /* See if there's a reloc prefix like hi() we have to handle. */
62ebcb5c 3665 r = v850_reloc_prefix (NULL, &errmsg);
252b5132
RH		 3666
3667 /* Do normal expression parsing. */
3668 expression (exp);
62ebcb5c 3669 return r;
252b5132
RH		 3670}
3671
3672/* Create a fixup for a cons expression. If parse_cons_expression_v850
3673 found a reloc prefix, then we use that reloc, else we choose an
3674 appropriate one based on the size of the expression. */
28e4f854 3675
252b5132 3676void
ea1562b3
NC		 3677cons_fix_new_v850 (fragS *frag,
3678 int where,
3679 int size,
62ebcb5c
AM		 3680 expressionS *exp,
3681 bfd_reloc_code_real_type r)
252b5132 3682{
62ebcb5c 3683 if (r == BFD_RELOC_NONE)
252b5132
RH		 3684 {
3685 if (size == 4)
62ebcb5c 3686 r = BFD_RELOC_32;
252b5132 3687 if (size == 2)
62ebcb5c 3688 r = BFD_RELOC_16;
252b5132 3689 if (size == 1)
62ebcb5c 3690 r = BFD_RELOC_8;
252b5132
RH		 3691 }
3692
3693 if (exp != NULL)
62ebcb5c 3694 fix_new_exp (frag, where, size, exp, 0, r);
252b5132 3695 else
62ebcb5c 3696 fix_new (frag, where, size, NULL, 0, 0, r);
252b5132 3697}
d6c497c7 3698
b34976b6 3699bfd_boolean
ea1562b3 3700v850_fix_adjustable (fixS *fixP)
252b5132 3701{
252b5132
RH		 3702 if (fixP->fx_addsy == NULL)
3703 return 1;
28e4f854 3704
28e4f854 3705 /* Don't adjust function names. */
252b5132
RH		 3706 if (S_IS_FUNCTION (fixP->fx_addsy))
3707 return 0;
3708
28e4f854
KH		 3709 /* We need the symbol name for the VTABLE entries. */
3710 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
252b5132
RH		 3711 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3712 return 0;
28e4f854 3713
252b5132
RH		 3714 return 1;
3715}
28e4f854 3716
252b5132 3717int
ea1562b3 3718v850_force_relocation (struct fix *fixP)
252b5132 3719{
a161fe53 3720 if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL
86aba9db
NC		 3721 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP)
3722 return 1;
3723
3724 if (v850_relax
3725 && (fixP->fx_pcrel
a161fe53 3726 || fixP->fx_r_type == BFD_RELOC_V850_ALIGN
a161fe53 3727 || fixP->fx_r_type == BFD_RELOC_V850_9_PCREL
1cd986c5
NC		 3728 || fixP->fx_r_type == BFD_RELOC_V850_16_PCREL
3729 || fixP->fx_r_type == BFD_RELOC_V850_17_PCREL
3730 || fixP->fx_r_type == BFD_RELOC_V850_22_PCREL
3731 || fixP->fx_r_type == BFD_RELOC_V850_32_PCREL
a161fe53 3732 || fixP->fx_r_type >= BFD_RELOC_UNUSED))
86aba9db
NC		 3733 return 1;
3734
ae6063d4 3735 return generic_force_reloc (fixP);
252b5132 3736}
685080f2
NC		 3737
3738/* Create a v850 note section. */
3739void
3740v850_md_end (void)
3741{
3742 segT note_sec;
3743 segT orig_seg = now_seg;
3744 subsegT orig_subseg = now_subseg;
3745 enum v850_notes id;
3746
3747 note_sec = subseg_new (V850_NOTE_SECNAME, 0);
3748 bfd_set_section_flags (stdoutput, note_sec, SEC_HAS_CONTENTS | SEC_READONLY | SEC_MERGE);
3749 bfd_set_section_alignment (stdoutput, note_sec, 2);
3750
3751 /* Provide default values for all of the notes. */
3752 for (id = V850_NOTE_ALIGNMENT; id <= NUM_V850_NOTES; id++)
3753 {
3754 int val = 0;
3755 char * p;
3756
3757 /* Follow the standard note section layout:
3758 First write the length of the name string. */
3759 p = frag_more (4);
3760 md_number_to_chars (p, 4, 4);
3761
3762 /* Next comes the length of the "descriptor", i.e., the actual data. */
3763 p = frag_more (4);
3764 md_number_to_chars (p, 4, 4);
3765
3766 /* Write the note type. */
3767 p = frag_more (4);
3768 md_number_to_chars (p, (valueT) id, 4);
3769
3770 /* Write the name field. */
3771 p = frag_more (4);
3772 memcpy (p, V850_NOTE_NAME, 4);
3773
3774 /* Finally, write the descriptor. */
3775 p = frag_more (4);
3776 switch (id)
3777 {
3778 case V850_NOTE_ALIGNMENT:
3779 val = v850_data_8 ? EF_RH850_DATA_ALIGN8 : EF_RH850_DATA_ALIGN4;
3780 break;
3781
3782 case V850_NOTE_DATA_SIZE:
3783 /* GCC does not currently support an option
3784 for 32-bit doubles with the V850 backend. */
3785 val = EF_RH850_DOUBLE64;
3786 break;
3787
3788 case V850_NOTE_FPU_INFO:
3789 if (! soft_float)
3790 switch (machine)
3791 {
3792 case bfd_mach_v850e3v5: val = EF_RH850_FPU30; break;
3793 case bfd_mach_v850e2v3: val = EF_RH850_FPU20; break;
3794 default: break;
3795 }
3796 break;
3797
3798 default:
3799 break;
3800 }
3801 md_number_to_chars (p, val, 4);
3802 }
3803
3804 /* Paranoia - we probably do not need this. */
3805 subseg_set (orig_seg, orig_subseg);
3806}
GDB Binutils - Deliverables
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