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b6605ddd EB |
1 | /* This is the machine dependent code of the Visium Assembler. |
2 | ||
6f2750fe | 3 | Copyright (C) 2005-2016 Free Software Foundation, Inc. |
b6605ddd EB |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include "as.h" | |
23 | #include "safe-ctype.h" | |
24 | #include "subsegs.h" | |
25 | #include "obstack.h" | |
26 | ||
27 | #include "opcode/visium.h" | |
28 | #include "elf/visium.h" | |
29 | #include "dwarf2dbg.h" | |
30 | #include "dw2gencfi.h" | |
31 | ||
32 | /* Relocations and fixups: | |
33 | ||
34 | There are two different cases where an instruction or data | |
35 | directive operand requires relocation, or fixup. | |
36 | ||
37 | 1. Relative branch instructions, take an 16-bit signed word | |
38 | offset. The formula for computing the offset is this: | |
39 | ||
40 | offset = (destination - pc) / 4 | |
41 | ||
42 | Branch instructions never branch to a label not declared | |
43 | locally, so the actual offset can always be computed by the assembler. | |
44 | However, we provide a relocation type to support this. | |
45 | ||
46 | 2. Load literal instructions, such as MOVIU, which take a 16-bit | |
47 | literal operand. The literal may be the top or bottom half of | |
48 | a 32-bit value computed by the assembler, or by the linker. We provide | |
49 | two relocation types here. | |
50 | ||
51 | 3. Data items (long, word and byte) preset with a value computed by | |
52 | the linker. */ | |
53 | ||
54 | ||
55 | /* This string holds the chars that always start a comment. If the | |
56 | pre-processor is disabled, these aren't very useful. The macro | |
57 | tc_comment_chars points to this. */ | |
58 | const char *visium_comment_chars = "!;"; | |
59 | ||
60 | /* This array holds the chars that only start a comment at the beginning | |
61 | of a line. If the line seems to have the form '# 123 filename' .line | |
62 | and .file directives will appear in the pre-processed output. Note that | |
63 | input_file.c hand checks for '#' at the beginning of the first line of | |
64 | the input file. This is because the compiler outputs #NO_APP at the | |
65 | beginning of its output. Also note that comments like this one will | |
66 | always work. */ | |
67 | const char line_comment_chars[] = "#!;"; | |
68 | const char line_separator_chars[] = ""; | |
69 | ||
70 | /* Chars that can be used to separate mantissa from exponent in floating point | |
71 | numbers. */ | |
72 | const char EXP_CHARS[] = "eE"; | |
73 | ||
74 | /* Chars that mean this number is a floating point constant, as in | |
75 | "0f12.456" or "0d1.2345e12". | |
76 | ||
77 | ...Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
78 | changed in read.c. Ideally it shouldn't have to know about it at all, | |
79 | but nothing is ideal around here. */ | |
80 | const char FLT_CHARS[] = "rRsSfFdDxXeE"; | |
81 | ||
82 | /* The size of a relocation record. */ | |
83 | const int md_reloc_size = 8; | |
84 | ||
85 | /* The architecture for which we are assembling. */ | |
86 | enum visium_arch_val | |
87 | { | |
88 | VISIUM_ARCH_DEF, | |
89 | VISIUM_ARCH_MCM24, | |
90 | VISIUM_ARCH_MCM, | |
91 | VISIUM_ARCH_GR6 | |
92 | }; | |
93 | ||
94 | static enum visium_arch_val visium_arch = VISIUM_ARCH_DEF; | |
95 | ||
96 | /* The opcode architecture for which we are assembling. In contrast to the | |
97 | previous one, this only determines which instructions are supported. */ | |
98 | static enum visium_opcode_arch_val visium_opcode_arch = VISIUM_OPCODE_ARCH_DEF; | |
99 | ||
100 | /* Flags to set in the ELF header e_flags field. */ | |
101 | static flagword visium_flags = 0; | |
102 | ||
103 | /* More than this number of nops in an alignment op gets a branch instead. */ | |
104 | static unsigned int nop_limit = 5; | |
105 | ||
106 | ||
107 | /* Translate internal representation of relocation info to BFD target | |
108 | format. */ | |
109 | arelent * | |
110 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) | |
111 | { | |
112 | arelent *reloc; | |
113 | bfd_reloc_code_real_type code; | |
114 | ||
add39d23 | 115 | reloc = XNEW (arelent); |
b6605ddd | 116 | |
add39d23 | 117 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
b6605ddd EB |
118 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
119 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
120 | ||
121 | switch (fixp->fx_r_type) | |
122 | { | |
123 | case BFD_RELOC_8: | |
124 | case BFD_RELOC_16: | |
125 | case BFD_RELOC_32: | |
126 | case BFD_RELOC_8_PCREL: | |
127 | case BFD_RELOC_16_PCREL: | |
128 | case BFD_RELOC_32_PCREL: | |
129 | case BFD_RELOC_VISIUM_HI16: | |
130 | case BFD_RELOC_VISIUM_LO16: | |
131 | case BFD_RELOC_VISIUM_IM16: | |
132 | case BFD_RELOC_VISIUM_REL16: | |
133 | case BFD_RELOC_VISIUM_HI16_PCREL: | |
134 | case BFD_RELOC_VISIUM_LO16_PCREL: | |
135 | case BFD_RELOC_VISIUM_IM16_PCREL: | |
136 | case BFD_RELOC_VTABLE_INHERIT: | |
137 | case BFD_RELOC_VTABLE_ENTRY: | |
138 | code = fixp->fx_r_type; | |
139 | break; | |
140 | default: | |
141 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
142 | "internal error: unknown relocation type %d (`%s')", | |
143 | fixp->fx_r_type, | |
144 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
145 | return 0; | |
146 | } | |
147 | ||
148 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
149 | if (reloc->howto == 0) | |
150 | { | |
151 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
152 | "internal error: can't export reloc type %d (`%s')", | |
153 | fixp->fx_r_type, bfd_get_reloc_code_name (code)); | |
154 | return 0; | |
155 | } | |
156 | ||
157 | /* Write the addend. */ | |
158 | if (reloc->howto->pc_relative == 0) | |
159 | reloc->addend = fixp->fx_addnumber; | |
160 | else | |
161 | reloc->addend = fixp->fx_offset; | |
162 | ||
163 | return reloc; | |
164 | } | |
165 | ||
166 | extern char *input_line_pointer; | |
167 | ||
168 | ||
169 | static void s_bss (int); | |
170 | static void visium_rdata (int); | |
171 | ||
172 | static void visium_update_parity_bit (char *); | |
173 | static char *parse_exp (char *, expressionS *); | |
174 | ||
175 | /* These are the back-ends for the various machine dependent pseudo-ops. */ | |
176 | void demand_empty_rest_of_line (void); | |
177 | ||
178 | ||
179 | static void | |
180 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
181 | { | |
182 | /* We don't support putting frags in the BSS segment, we fake it | |
183 | by marking in_bss, then looking at s_skip for clues. */ | |
184 | ||
185 | subseg_set (bss_section, 0); | |
186 | demand_empty_rest_of_line (); | |
187 | } | |
188 | ||
189 | ||
190 | /* This table describes all the machine specific pseudo-ops the assembler | |
191 | has to support. The fields are: | |
192 | ||
193 | 1: Pseudo-op name without dot. | |
194 | 2: Function to call to execute this pseudo-op. | |
195 | 3: Integer arg to pass to the function. */ | |
196 | const pseudo_typeS md_pseudo_table[] = | |
197 | { | |
198 | {"bss", s_bss, 0}, | |
199 | {"skip", s_space, 0}, | |
200 | {"align", s_align_bytes, 0}, | |
201 | {"noopt", s_ignore, 0}, | |
202 | {"optim", s_ignore, 0}, | |
203 | {"rdata", visium_rdata, 0}, | |
204 | {"rodata", visium_rdata, 0}, | |
205 | {0, 0, 0} | |
206 | }; | |
207 | ||
208 | ||
209 | static void | |
210 | visium_rdata (int xxx) | |
211 | { | |
212 | char *save_line = input_line_pointer; | |
213 | static char section[] = ".rodata\n"; | |
214 | ||
215 | /* Just pretend this is .section .rodata */ | |
216 | input_line_pointer = section; | |
217 | obj_elf_section (xxx); | |
218 | input_line_pointer = save_line; | |
219 | } | |
220 | ||
221 | /* Align a section. */ | |
222 | valueT | |
223 | md_section_align (asection *seg, valueT addr) | |
224 | { | |
225 | int align = bfd_get_section_alignment (stdoutput, seg); | |
226 | ||
8d3842cd | 227 | return ((addr + (1 << align) - 1) & -(1 << align)); |
b6605ddd EB |
228 | } |
229 | ||
230 | void | |
231 | md_number_to_chars (char *buf, valueT val, int n) | |
232 | { | |
233 | number_to_chars_bigendian (buf, val, n); | |
234 | } | |
235 | ||
236 | symbolS * | |
237 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) | |
238 | { | |
239 | return 0; | |
240 | } | |
241 | ||
242 | /* The parse options. */ | |
243 | const char *md_shortopts = "m:"; | |
244 | ||
245 | struct option md_longopts[] = | |
246 | { | |
247 | {NULL, no_argument, NULL, 0} | |
248 | }; | |
249 | ||
250 | size_t md_longopts_size = sizeof (md_longopts); | |
251 | ||
252 | struct visium_option_table | |
253 | { | |
254 | char *option; /* Option name to match. */ | |
255 | char *help; /* Help information. */ | |
256 | int *var; /* Variable to change. */ | |
257 | int value; /* To what to change it. */ | |
258 | char *deprecated; /* If non-null, print this message. */ | |
259 | }; | |
260 | ||
261 | static struct visium_option_table visium_opts[] = | |
262 | { | |
263 | {NULL, NULL, NULL, 0, NULL} | |
264 | }; | |
265 | ||
266 | struct visium_arch_option_table | |
267 | { | |
e0471c16 | 268 | const char *name; |
b6605ddd EB |
269 | enum visium_arch_val value; |
270 | }; | |
271 | ||
272 | static struct visium_arch_option_table visium_archs[] = | |
273 | { | |
274 | {"mcm24", VISIUM_ARCH_MCM24}, | |
275 | {"mcm", VISIUM_ARCH_MCM}, | |
276 | {"gr5", VISIUM_ARCH_MCM}, | |
277 | {"gr6", VISIUM_ARCH_GR6}, | |
278 | {NULL, 0} | |
279 | }; | |
280 | ||
281 | struct visium_long_option_table | |
282 | { | |
e0471c16 TS |
283 | const char *option; /* Substring to match. */ |
284 | const char *help; /* Help information. */ | |
17b9d67d | 285 | int (*func) (const char *subopt); /* Function to decode sub-option. */ |
e0471c16 | 286 | const char *deprecated; /* If non-null, print this message. */ |
b6605ddd EB |
287 | }; |
288 | ||
289 | static int | |
17b9d67d | 290 | visium_parse_arch (const char *str) |
b6605ddd EB |
291 | { |
292 | struct visium_arch_option_table *opt; | |
293 | ||
294 | if (strlen (str) == 0) | |
295 | { | |
296 | as_bad ("missing architecture name `%s'", str); | |
297 | return 0; | |
298 | } | |
299 | ||
300 | ||
301 | for (opt = visium_archs; opt->name != NULL; opt++) | |
302 | if (strcmp (opt->name, str) == 0) | |
303 | { | |
304 | visium_arch = opt->value; | |
305 | return 1; | |
306 | } | |
307 | ||
308 | as_bad ("unknown architecture `%s'\n", str); | |
309 | return 0; | |
310 | } | |
311 | ||
312 | static struct visium_long_option_table visium_long_opts[] = | |
313 | { | |
314 | {"mtune=", "<arch_name>\t assemble for architecture <arch name>", | |
315 | visium_parse_arch, NULL}, | |
316 | {NULL, NULL, NULL, NULL} | |
317 | }; | |
318 | ||
319 | int | |
17b9d67d | 320 | md_parse_option (int c, const char *arg) |
b6605ddd EB |
321 | { |
322 | struct visium_option_table *opt; | |
323 | struct visium_long_option_table *lopt; | |
324 | ||
325 | switch (c) | |
326 | { | |
327 | case 'a': | |
328 | /* Listing option. Just ignore these, we don't support additional | |
329 | ones. */ | |
330 | return 0; | |
331 | ||
332 | default: | |
333 | for (opt = visium_opts; opt->option != NULL; opt++) | |
334 | { | |
335 | if (c == opt->option[0] | |
336 | && ((arg == NULL && opt->option[1] == 0) | |
337 | || strcmp (arg, opt->option + 1) == 0)) | |
338 | { | |
339 | /* If the option is deprecated, tell the user. */ | |
340 | if (opt->deprecated != NULL) | |
341 | as_tsktsk ("option `-%c%s' is deprecated: %s", c, | |
342 | arg ? arg : "", opt->deprecated); | |
343 | ||
344 | if (opt->var != NULL) | |
345 | *opt->var = opt->value; | |
346 | ||
347 | return 1; | |
348 | } | |
349 | } | |
350 | ||
351 | for (lopt = visium_long_opts; lopt->option != NULL; lopt++) | |
352 | { | |
353 | /* These options are expected to have an argument. */ | |
354 | if (c == lopt->option[0] | |
355 | && arg != NULL | |
356 | && strncmp (arg, lopt->option + 1, | |
357 | strlen (lopt->option + 1)) == 0) | |
358 | { | |
359 | /* If the option is deprecated, tell the user. */ | |
360 | if (lopt->deprecated != NULL) | |
361 | as_tsktsk ("option `-%c%s' is deprecated: %s", c, arg, | |
362 | lopt->deprecated); | |
363 | ||
364 | /* Call the sup-option parser. */ | |
365 | return lopt->func (arg + strlen (lopt->option) - 1); | |
366 | } | |
367 | } | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | return 1; | |
373 | } | |
374 | ||
375 | void | |
376 | md_show_usage (FILE * fp) | |
377 | { | |
378 | struct visium_option_table *opt; | |
379 | struct visium_long_option_table *lopt; | |
380 | ||
381 | fprintf (fp, " Visium-specific assembler options:\n"); | |
382 | ||
383 | for (opt = visium_opts; opt->option != NULL; opt++) | |
384 | if (opt->help != NULL) | |
385 | fprintf (fp, " -%-23s%s\n", opt->option, opt->help); | |
386 | ||
387 | for (lopt = visium_long_opts; lopt->option != NULL; lopt++) | |
388 | if (lopt->help != NULL) | |
389 | fprintf (fp, " -%s%s\n", lopt->option, lopt->help); | |
390 | ||
391 | } | |
392 | ||
393 | /* Interface to relax_segment. */ | |
394 | ||
395 | /* Return the estimate of the size of a machine dependent frag | |
396 | before any relaxing is done. It may also create any necessary | |
397 | relocations. */ | |
398 | int | |
399 | md_estimate_size_before_relax (fragS * fragP, | |
400 | segT segment ATTRIBUTE_UNUSED) | |
401 | { | |
402 | fragP->fr_var = 4; | |
403 | return 4; | |
404 | } | |
405 | ||
406 | /* Get the address of a symbol during relaxation. From tc-arm.c. */ | |
407 | static addressT | |
408 | relaxed_symbol_addr (fragS *fragp, long stretch) | |
409 | { | |
410 | fragS *sym_frag; | |
411 | addressT addr; | |
412 | symbolS *sym; | |
413 | ||
414 | sym = fragp->fr_symbol; | |
415 | sym_frag = symbol_get_frag (sym); | |
416 | know (S_GET_SEGMENT (sym) != absolute_section | |
417 | || sym_frag == &zero_address_frag); | |
418 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
419 | ||
420 | /* If frag has yet to be reached on this pass, assume it will | |
421 | move by STRETCH just as we did. If this is not so, it will | |
422 | be because some frag between grows, and that will force | |
423 | another pass. */ | |
424 | if (stretch != 0 | |
425 | && sym_frag->relax_marker != fragp->relax_marker) | |
426 | { | |
427 | fragS *f; | |
428 | ||
429 | /* Adjust stretch for any alignment frag. Note that if have | |
430 | been expanding the earlier code, the symbol may be | |
431 | defined in what appears to be an earlier frag. FIXME: | |
432 | This doesn't handle the fr_subtype field, which specifies | |
433 | a maximum number of bytes to skip when doing an | |
434 | alignment. */ | |
435 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
436 | { | |
437 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
438 | { | |
439 | if (stretch < 0) | |
440 | stretch = - ((- stretch) | |
441 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
442 | else | |
443 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
444 | if (stretch == 0) | |
445 | break; | |
446 | } | |
447 | } | |
448 | if (f != NULL) | |
449 | addr += stretch; | |
450 | } | |
451 | ||
452 | return addr; | |
453 | } | |
454 | ||
455 | /* Relax a machine dependent frag. This returns the amount by which | |
456 | the current size of the frag should change. */ | |
457 | int | |
458 | visium_relax_frag (asection *sec, fragS *fragP, long stretch) | |
459 | { | |
460 | int old_size, new_size; | |
461 | addressT addr; | |
462 | ||
463 | /* We only handle relaxation for the BRR instruction. */ | |
464 | gas_assert (fragP->fr_subtype == mode_ci); | |
465 | ||
466 | if (!S_IS_DEFINED (fragP->fr_symbol) | |
467 | || sec != S_GET_SEGMENT (fragP->fr_symbol) | |
468 | || S_IS_WEAK (fragP->fr_symbol)) | |
469 | return 0; | |
470 | ||
471 | old_size = fragP->fr_var; | |
472 | addr = relaxed_symbol_addr (fragP, stretch); | |
473 | ||
474 | /* If the target is the address of the instruction, we'll insert a NOP. */ | |
475 | if (addr == fragP->fr_address + fragP->fr_fix) | |
476 | new_size = 8; | |
477 | else | |
478 | new_size = 4; | |
479 | ||
480 | fragP->fr_var = new_size; | |
481 | return new_size - old_size; | |
482 | } | |
483 | ||
484 | /* Convert a machine dependent frag. */ | |
485 | void | |
486 | md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, | |
487 | fragS * fragP) | |
488 | { | |
489 | char *buf = fragP->fr_literal + fragP->fr_fix; | |
490 | expressionS exp; | |
491 | fixS *fixP; | |
492 | ||
493 | /* We only handle relaxation for the BRR instruction. */ | |
494 | gas_assert (fragP->fr_subtype == mode_ci); | |
495 | ||
496 | /* Insert the NOP if requested. */ | |
497 | if (fragP->fr_var == 8) | |
498 | { | |
499 | memcpy (buf + 4, buf, 4); | |
500 | memset (buf, 0, 4); | |
501 | fragP->fr_fix += 4; | |
502 | } | |
503 | ||
504 | exp.X_op = O_symbol; | |
505 | exp.X_add_symbol = fragP->fr_symbol; | |
506 | exp.X_add_number = fragP->fr_offset; | |
507 | ||
508 | /* Now we can create the relocation at the correct offset. */ | |
509 | fixP = fix_new_exp (fragP, fragP->fr_fix, 4, &exp, 1, BFD_RELOC_VISIUM_REL16); | |
510 | fixP->fx_file = fragP->fr_file; | |
511 | fixP->fx_line = fragP->fr_line; | |
512 | fragP->fr_fix += 4; | |
513 | fragP->fr_var = 0; | |
514 | } | |
515 | ||
516 | /* The location from which a PC relative jump should be calculated, | |
517 | given a PC relative jump reloc. */ | |
518 | long | |
519 | visium_pcrel_from_section (fixS *fixP, segT sec) | |
520 | { | |
521 | if (fixP->fx_addsy != (symbolS *) NULL | |
522 | && (!S_IS_DEFINED (fixP->fx_addsy) | |
523 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
524 | { | |
525 | /* The symbol is undefined (or is defined but not in this section). | |
526 | Let the linker figure it out. */ | |
527 | return 0; | |
528 | } | |
529 | ||
530 | /* Return the address of the instruction. */ | |
531 | return fixP->fx_where + fixP->fx_frag->fr_address; | |
532 | } | |
533 | ||
534 | /* Indicate whether a fixup against a locally defined | |
535 | symbol should be adjusted to be against the section | |
536 | symbol. */ | |
537 | bfd_boolean | |
538 | visium_fix_adjustable (fixS *fix) | |
539 | { | |
540 | /* We need the symbol name for the VTABLE entries. */ | |
541 | return (fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT | |
542 | && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY); | |
543 | } | |
544 | ||
545 | /* Update the parity bit of the 4-byte instruction in BUF. */ | |
546 | static void | |
547 | visium_update_parity_bit (char *buf) | |
548 | { | |
549 | int p1 = (buf[0] & 0x7f) ^ buf[1] ^ buf[2] ^ buf[3]; | |
550 | int p2 = 0; | |
551 | int i; | |
552 | ||
553 | for (i = 1; i <= 8; i++) | |
554 | { | |
555 | p2 ^= (p1 & 1); | |
556 | p1 >>= 1; | |
557 | } | |
558 | ||
559 | buf[0] = (buf[0] & 0x7f) | ((p2 << 7) & 0x80); | |
560 | } | |
561 | ||
562 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents | |
563 | of an rs_align_code fragment. */ | |
564 | void | |
565 | visium_handle_align (fragS *fragP) | |
566 | { | |
567 | valueT count | |
568 | = fragP->fr_next->fr_address - (fragP->fr_address + fragP->fr_fix); | |
569 | valueT fix = count & 3; | |
570 | char *p = fragP->fr_literal + fragP->fr_fix; | |
571 | ||
572 | if (fix) | |
573 | { | |
574 | memset (p, 0, fix); | |
575 | p += fix; | |
576 | count -= fix; | |
577 | fragP->fr_fix += fix; | |
578 | } | |
579 | ||
580 | if (count == 0) | |
581 | return; | |
582 | ||
583 | fragP->fr_var = 4; | |
584 | ||
585 | if (count > 4 * nop_limit && count <= 131068) | |
586 | { | |
587 | struct frag *rest; | |
588 | ||
589 | /* Make a branch, then follow with nops. Insert another | |
590 | frag to handle the nops. */ | |
591 | md_number_to_chars (p, 0x78000000 + (count >> 2), 4); | |
592 | visium_update_parity_bit (p); | |
593 | ||
594 | rest = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
595 | memcpy (rest, fragP, SIZEOF_STRUCT_FRAG); | |
596 | fragP->fr_next = rest; | |
597 | rest->fr_address += rest->fr_fix + 4; | |
598 | rest->fr_fix = 0; | |
599 | /* If we leave the next frag as rs_align_code we'll come here | |
600 | again, resulting in a bunch of branches rather than a | |
601 | branch followed by nops. */ | |
602 | rest->fr_type = rs_align; | |
603 | p = rest->fr_literal; | |
604 | } | |
605 | ||
606 | memset (p, 0, 4); | |
607 | } | |
608 | ||
609 | /* Apply a fixS to the frags, now that we know the value it ought to | |
610 | hold. */ | |
611 | void | |
612 | md_apply_fix (fixS * fixP, valueT * value, segT segment) | |
613 | { | |
614 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
615 | offsetT val; | |
616 | long insn; | |
617 | ||
618 | val = *value; | |
619 | ||
620 | gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); | |
621 | ||
622 | /* Remember value for tc_gen_reloc. */ | |
623 | fixP->fx_addnumber = val; | |
624 | ||
625 | /* Since DIFF_EXPR_OK is defined, .-foo gets turned into PC | |
626 | relative relocs. If this has happened, a non-PC relative | |
627 | reloc must be reinstalled with its PC relative version here. */ | |
628 | if (fixP->fx_pcrel) | |
629 | { | |
630 | switch (fixP->fx_r_type) | |
631 | { | |
632 | case BFD_RELOC_8: | |
633 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
634 | break; | |
635 | case BFD_RELOC_16: | |
636 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
637 | break; | |
638 | case BFD_RELOC_32: | |
639 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
640 | break; | |
641 | case BFD_RELOC_VISIUM_HI16: | |
642 | fixP->fx_r_type = BFD_RELOC_VISIUM_HI16_PCREL; | |
643 | break; | |
644 | case BFD_RELOC_VISIUM_LO16: | |
645 | fixP->fx_r_type = BFD_RELOC_VISIUM_LO16_PCREL; | |
646 | break; | |
647 | case BFD_RELOC_VISIUM_IM16: | |
648 | fixP->fx_r_type = BFD_RELOC_VISIUM_IM16_PCREL; | |
649 | break; | |
650 | default: | |
651 | break; | |
652 | } | |
653 | } | |
654 | ||
655 | /* If this is a data relocation, just output VAL. */ | |
656 | switch (fixP->fx_r_type) | |
657 | { | |
658 | case BFD_RELOC_8: | |
659 | case BFD_RELOC_8_PCREL: | |
660 | md_number_to_chars (buf, val, 1); | |
661 | break; | |
662 | case BFD_RELOC_16: | |
663 | case BFD_RELOC_16_PCREL: | |
664 | md_number_to_chars (buf, val, 2); | |
665 | break; | |
666 | case BFD_RELOC_32: | |
667 | case BFD_RELOC_32_PCREL: | |
668 | md_number_to_chars (buf, val, 4); | |
669 | break; | |
670 | case BFD_RELOC_VTABLE_INHERIT: | |
671 | case BFD_RELOC_VTABLE_ENTRY: | |
672 | fixP->fx_done = 0; | |
673 | break; | |
674 | default: | |
675 | /* It's a relocation against an instruction. */ | |
676 | insn = bfd_getb32 ((unsigned char *) buf); | |
677 | ||
678 | switch (fixP->fx_r_type) | |
679 | { | |
680 | case BFD_RELOC_VISIUM_REL16: | |
681 | if (fixP->fx_addsy == NULL | |
682 | || (S_IS_DEFINED (fixP->fx_addsy) | |
683 | && S_GET_SEGMENT (fixP->fx_addsy) == segment)) | |
684 | { | |
685 | if (val > 0x1fffc || val < -0x20000) | |
686 | as_bad_where | |
687 | (fixP->fx_file, fixP->fx_line, | |
688 | "16-bit word displacement out of range: value = %d", | |
689 | (int) val); | |
690 | val = (val >> 2); | |
691 | ||
692 | insn = (insn & 0xffff0000) | (val & 0x0000ffff); | |
693 | } | |
694 | break; | |
695 | ||
696 | case BFD_RELOC_VISIUM_HI16: | |
697 | case BFD_RELOC_VISIUM_HI16_PCREL: | |
698 | if (fixP->fx_addsy == NULL) | |
699 | insn = (insn & 0xffff0000) | ((val >> 16) & 0x0000ffff); | |
700 | break; | |
701 | ||
702 | case BFD_RELOC_VISIUM_LO16: | |
703 | case BFD_RELOC_VISIUM_LO16_PCREL: | |
704 | if (fixP->fx_addsy == NULL) | |
705 | insn = (insn & 0xffff0000) | (val & 0x0000ffff); | |
706 | break; | |
707 | ||
708 | case BFD_RELOC_VISIUM_IM16: | |
709 | case BFD_RELOC_VISIUM_IM16_PCREL: | |
710 | if (fixP->fx_addsy == NULL) | |
711 | { | |
712 | if ((val & 0xffff0000) != 0) | |
713 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
714 | "16-bit immediate out of range: value = %d", | |
715 | (int) val); | |
716 | ||
717 | insn = (insn & 0xffff0000) | val; | |
718 | } | |
719 | break; | |
720 | ||
721 | case BFD_RELOC_NONE: | |
722 | default: | |
723 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
724 | "bad or unhandled relocation type: 0x%02x", | |
725 | fixP->fx_r_type); | |
726 | break; | |
727 | } | |
728 | ||
729 | bfd_putb32 (insn, (unsigned char *) buf); | |
730 | visium_update_parity_bit (buf); | |
731 | break; | |
732 | } | |
733 | ||
734 | /* Are we finished with this relocation now? */ | |
735 | if (fixP->fx_addsy == NULL) | |
736 | fixP->fx_done = 1; | |
737 | } | |
738 | ||
739 | char * | |
740 | parse_exp (char *s, expressionS * op) | |
741 | { | |
742 | char *save = input_line_pointer; | |
743 | char *new; | |
744 | ||
745 | if (!s) | |
746 | { | |
747 | return s; | |
748 | } | |
749 | ||
750 | input_line_pointer = s; | |
751 | expression (op); | |
752 | new = input_line_pointer; | |
753 | input_line_pointer = save; | |
754 | return new; | |
755 | } | |
756 | ||
757 | /* If the given string is a Visium opcode mnemonic return the code | |
758 | otherwise return -1. Use binary chop to find matching entry. */ | |
759 | static int | |
760 | get_opcode (int *code, enum addressing_mode *mode, char *flags, char *mnem) | |
761 | { | |
762 | int l = 0; | |
763 | int r = sizeof (opcode_table) / sizeof (struct opcode_entry) - 1; | |
764 | ||
765 | do | |
766 | { | |
767 | int mid = (l + r) / 2; | |
768 | int ans = strcmp (mnem, opcode_table[mid].mnem); | |
769 | ||
770 | if (ans < 0) | |
771 | r = mid - 1; | |
772 | else if (ans > 0) | |
773 | l = mid + 1; | |
774 | else | |
775 | { | |
776 | *code = opcode_table[mid].code; | |
777 | *mode = opcode_table[mid].mode; | |
778 | *flags = opcode_table[mid].flags; | |
779 | ||
780 | return 0; | |
781 | } | |
782 | } | |
783 | while (l <= r); | |
784 | ||
785 | return -1; | |
786 | } | |
787 | ||
788 | /* This function is called when the assembler starts up. It is called | |
789 | after the options have been parsed and the output file has been | |
790 | opened. */ | |
791 | void | |
792 | md_begin (void) | |
793 | { | |
794 | switch (visium_arch) | |
795 | { | |
796 | case VISIUM_ARCH_DEF: | |
797 | break; | |
798 | case VISIUM_ARCH_MCM24: | |
799 | visium_opcode_arch = VISIUM_OPCODE_ARCH_GR5; | |
800 | visium_flags |= EF_VISIUM_ARCH_MCM24; | |
801 | break; | |
802 | case VISIUM_ARCH_MCM: | |
803 | visium_opcode_arch = VISIUM_OPCODE_ARCH_GR5; | |
804 | visium_flags |= EF_VISIUM_ARCH_MCM; | |
805 | break; | |
806 | case VISIUM_ARCH_GR6: | |
807 | visium_opcode_arch = VISIUM_OPCODE_ARCH_GR6; | |
808 | visium_flags |= EF_VISIUM_ARCH_MCM | EF_VISIUM_ARCH_GR6; | |
809 | nop_limit = 2; | |
810 | break; | |
811 | default: | |
812 | gas_assert (0); | |
813 | } | |
814 | ||
815 | bfd_set_private_flags (stdoutput, visium_flags); | |
816 | } | |
817 | ||
818 | /* This is identical to the md_atof in m68k.c. I think this is right, | |
819 | but I'm not sure. | |
820 | ||
821 | Turn a string in input_line_pointer into a floating point constant of type | |
822 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
823 | emitted is stored in *sizeP . An error message is returned, | |
824 | or NULL on OK. */ | |
825 | ||
826 | /* Equal to MAX_PRECISION in atof-ieee.c. */ | |
827 | #define MAX_LITTLENUMS 6 | |
828 | ||
6d4af3c2 | 829 | const char * |
b6605ddd EB |
830 | md_atof (int type, char *litP, int *sizeP) |
831 | { | |
832 | int i, prec; | |
833 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
834 | char *t; | |
835 | ||
836 | switch (type) | |
837 | { | |
838 | case 'f': | |
839 | case 'F': | |
840 | case 's': | |
841 | case 'S': | |
842 | prec = 2; | |
843 | break; | |
844 | ||
845 | case 'd': | |
846 | case 'D': | |
847 | case 'r': | |
848 | case 'R': | |
849 | prec = 4; | |
850 | break; | |
851 | ||
852 | case 'x': | |
853 | case 'X': | |
854 | prec = 6; | |
855 | break; | |
856 | ||
857 | case 'p': | |
858 | case 'P': | |
859 | prec = 6; | |
860 | break; | |
861 | ||
862 | default: | |
863 | *sizeP = 0; | |
eda6e9a4 | 864 | return _("Bad call to MD_ATOF()"); |
b6605ddd EB |
865 | } |
866 | ||
867 | t = atof_ieee (input_line_pointer, type, words); | |
868 | if (t) | |
869 | input_line_pointer = t; | |
870 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
871 | ||
872 | if (target_big_endian) | |
873 | { | |
874 | for (i = 0; i < prec; i++) | |
875 | { | |
876 | md_number_to_chars (litP, (valueT) words[i], | |
877 | sizeof (LITTLENUM_TYPE)); | |
878 | litP += sizeof (LITTLENUM_TYPE); | |
879 | } | |
880 | } | |
881 | else | |
882 | { | |
883 | for (i = prec - 1; i >= 0; i--) | |
884 | { | |
885 | md_number_to_chars (litP, (valueT) words[i], | |
886 | sizeof (LITTLENUM_TYPE)); | |
887 | litP += sizeof (LITTLENUM_TYPE); | |
888 | } | |
889 | } | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
894 | static inline char * | |
895 | skip_space (char *s) | |
896 | { | |
897 | while (*s == ' ' || *s == '\t') | |
898 | ++s; | |
899 | ||
900 | return s; | |
901 | } | |
902 | ||
903 | static int | |
904 | parse_gen_reg (char **sptr, int *rptr) | |
905 | { | |
906 | char *s = skip_space (*sptr); | |
907 | char buf[10]; | |
908 | int cnt; | |
909 | int l, r; | |
910 | ||
911 | cnt = 0; | |
912 | memset (buf, '\0', 10); | |
913 | while ((ISALNUM (*s)) && cnt < 10) | |
914 | buf[cnt++] = TOLOWER (*s++); | |
915 | ||
916 | l = 0; | |
917 | r = sizeof (gen_reg_table) / sizeof (struct reg_entry) - 1; | |
918 | ||
919 | do | |
920 | { | |
921 | int mid = (l + r) / 2; | |
922 | int ans = strcmp (buf, gen_reg_table[mid].name); | |
923 | ||
924 | if (ans < 0) | |
925 | r = mid - 1; | |
926 | else if (ans > 0) | |
927 | l = mid + 1; | |
928 | else | |
929 | { | |
930 | *rptr = gen_reg_table[mid].code; | |
931 | *sptr = s; | |
932 | return 0; | |
933 | } | |
934 | } | |
935 | while (l <= r); | |
936 | ||
937 | return -1; | |
938 | } | |
939 | ||
940 | static int | |
941 | parse_fp_reg (char **sptr, int *rptr) | |
942 | { | |
943 | char *s = skip_space (*sptr); | |
944 | char buf[10]; | |
945 | int cnt; | |
946 | int l, r; | |
947 | ||
948 | cnt = 0; | |
949 | memset (buf, '\0', 10); | |
950 | while ((ISALNUM (*s)) && cnt < 10) | |
951 | buf[cnt++] = TOLOWER (*s++); | |
952 | ||
953 | l = 0; | |
954 | r = sizeof (fp_reg_table) / sizeof (struct reg_entry) - 1; | |
955 | ||
956 | do | |
957 | { | |
958 | int mid = (l + r) / 2; | |
959 | int ans = strcmp (buf, fp_reg_table[mid].name); | |
960 | ||
961 | if (ans < 0) | |
962 | r = mid - 1; | |
963 | else if (ans > 0) | |
964 | l = mid + 1; | |
965 | else | |
966 | { | |
967 | *rptr = fp_reg_table[mid].code; | |
968 | *sptr = s; | |
969 | return 0; | |
970 | } | |
971 | } | |
972 | while (l <= r); | |
973 | ||
974 | return -1; | |
975 | } | |
976 | ||
977 | static int | |
978 | parse_cc (char **sptr, int *rptr) | |
979 | { | |
980 | char *s = skip_space (*sptr); | |
981 | char buf[10]; | |
982 | int cnt; | |
983 | int l, r; | |
984 | ||
985 | cnt = 0; | |
986 | memset (buf, '\0', 10); | |
987 | while ((ISALNUM (*s)) && cnt < 10) | |
988 | buf[cnt++] = TOLOWER (*s++); | |
989 | ||
990 | l = 0; | |
991 | r = sizeof (cc_table) / sizeof (struct cc_entry) - 1; | |
992 | ||
993 | do | |
994 | { | |
995 | int mid = (l + r) / 2; | |
996 | int ans = strcmp (buf, cc_table[mid].name); | |
997 | ||
998 | if (ans < 0) | |
999 | r = mid - 1; | |
1000 | else if (ans > 0) | |
1001 | l = mid + 1; | |
1002 | else | |
1003 | { | |
1004 | *rptr = cc_table[mid].code; | |
1005 | *sptr = s; | |
1006 | return 0; | |
1007 | } | |
1008 | } | |
1009 | while (l <= r); | |
1010 | ||
1011 | return -1; | |
1012 | } | |
1013 | ||
1014 | /* Previous dest is the destination register number of the instruction | |
1015 | before the current one. */ | |
1016 | static int previous_dest = 0; | |
1017 | static int previous_mode = 0; | |
1018 | static int condition_code = 0; | |
1019 | static int this_dest = 0; | |
1020 | static int this_mode = 0; | |
1021 | ||
1022 | ||
1023 | /* This is the main function in this file. It takes a line of assembly language | |
1024 | source code and assembles it. Note, labels and pseudo ops have already | |
1025 | been removed, so too has leading white space. */ | |
1026 | void | |
1027 | md_assemble (char *str0) | |
1028 | { | |
1029 | char *str = str0; | |
1030 | int cnt; | |
1031 | char mnem[10]; | |
1032 | int opcode; | |
1033 | enum addressing_mode amode; | |
1034 | char arch_flags; | |
1035 | int ans; | |
1036 | ||
1037 | char *output; | |
1038 | int reloc = 0; | |
1039 | relax_substateT relax = 0; | |
1040 | expressionS e1; | |
1041 | int r1, r2, r3; | |
1042 | int cc; | |
1043 | int indx; | |
1044 | ||
1045 | /* Initialize the expression. */ | |
1046 | e1.X_op = O_absent; | |
1047 | ||
1048 | /* Initialize destination register. | |
1049 | If the instruction we just looked at is in the delay slot of an | |
1050 | unconditional branch, then there is no index hazard. */ | |
1051 | if ((previous_mode == mode_cad || previous_mode == mode_ci) | |
1052 | && condition_code == 15) | |
1053 | this_dest = 0; | |
1054 | ||
1055 | previous_dest = this_dest; | |
1056 | previous_mode = this_mode; | |
1057 | this_dest = 0; | |
1058 | ||
1059 | /* Drop leading whitespace (probably not required). */ | |
1060 | while (*str == ' ') | |
1061 | str++; | |
1062 | ||
1063 | /* Get opcode mnemonic and make sure it's in lower case. */ | |
1064 | cnt = 0; | |
1065 | memset (mnem, '\0', 10); | |
1066 | while ((ISALNUM (*str) || *str == '.' || *str == '_') && cnt < 10) | |
1067 | mnem[cnt++] = TOLOWER (*str++); | |
1068 | ||
1069 | /* Look up mnemonic in opcode table, and get the code, | |
1070 | the instruction format, and the flags that indicate | |
1071 | which family members support this mnenonic. */ | |
1072 | if (get_opcode (&opcode, &amode, &arch_flags, mnem) < 0) | |
1073 | { | |
1074 | as_bad ("Unknown instruction mnenonic `%s'", mnem); | |
1075 | return; | |
1076 | } | |
1077 | ||
1078 | if ((VISIUM_OPCODE_ARCH_MASK (visium_opcode_arch) & arch_flags) == 0) | |
1079 | { | |
1080 | as_bad ("Architecture mismatch on `%s'", mnem); | |
1081 | return; | |
1082 | } | |
1083 | ||
1084 | this_mode = amode; | |
1085 | ||
1086 | switch (amode) | |
1087 | { | |
1088 | case mode_d: | |
1089 | /* register := | |
1090 | Example: | |
1091 | readmda r1 */ | |
1092 | ans = parse_gen_reg (&str, &r1); | |
1093 | if (ans < 0) | |
1094 | { | |
1095 | as_bad ("Dest register required"); | |
1096 | return; | |
1097 | } | |
1098 | opcode |= (r1 << 10); | |
1099 | this_dest = r1; | |
1100 | break; | |
1101 | ||
1102 | case mode_a: | |
1103 | /* op= register | |
1104 | Example: asld r1 */ | |
1105 | ans = parse_gen_reg (&str, &r1); | |
1106 | if (ans < 0) | |
1107 | { | |
1108 | as_bad ("SourceA register required"); | |
1109 | return; | |
1110 | } | |
1111 | opcode |= (r1 << 16); | |
1112 | break; | |
1113 | ||
1114 | case mode_ab: | |
1115 | /* register * register | |
1116 | Example: | |
1117 | mults r1,r2 */ | |
1118 | ans = parse_gen_reg (&str, &r1); | |
1119 | if (ans < 0) | |
1120 | { | |
1121 | as_bad ("SourceA register required"); | |
1122 | return; | |
1123 | } | |
1124 | str = skip_space (str); | |
1125 | if (*str == ',') | |
1126 | { | |
1127 | str++; | |
1128 | ans = parse_gen_reg (&str, &r2); | |
1129 | if (ans < 0) | |
1130 | { | |
1131 | as_bad ("SourceB register required"); | |
1132 | return; | |
1133 | } | |
1134 | opcode |= (r1 << 16) | (r2 << 4); | |
1135 | } | |
1136 | else | |
1137 | { | |
1138 | as_bad ("SourceB register required"); | |
1139 | return; | |
1140 | } | |
1141 | break; | |
1142 | ||
1143 | case mode_da: | |
1144 | /* register := register | |
1145 | Example: | |
1146 | extb.l r1,r2 */ | |
1147 | ans = parse_gen_reg (&str, &r1); | |
1148 | if (ans < 0) | |
1149 | { | |
1150 | as_bad ("Dest register required"); | |
1151 | return; | |
1152 | } | |
1153 | str = skip_space (str); | |
1154 | if (*str == ',') | |
1155 | { | |
1156 | str++; | |
1157 | ans = parse_gen_reg (&str, &r2); | |
1158 | if (ans < 0) | |
1159 | { | |
1160 | as_bad ("SourceA register required"); | |
1161 | return; | |
1162 | } | |
1163 | opcode |= (r1 << 10) | (r2 << 16); | |
1164 | } | |
1165 | else | |
1166 | { | |
1167 | as_bad ("SourceB register required"); | |
1168 | return; | |
1169 | } | |
1170 | this_dest = r1; | |
1171 | break; | |
1172 | ||
1173 | case mode_dab: | |
1174 | /* register := register * register | |
1175 | Example: | |
1176 | add.l r1,r2,r3 */ | |
1177 | ans = parse_gen_reg (&str, &r1); | |
1178 | if (ans < 0) | |
1179 | { | |
1180 | as_bad ("Dest register required"); | |
1181 | return; | |
1182 | } | |
1183 | str = skip_space (str); | |
1184 | if (*str == ',') | |
1185 | { | |
1186 | str++; | |
1187 | ans = parse_gen_reg (&str, &r2); | |
1188 | if (ans < 0) | |
1189 | { | |
1190 | as_bad ("SourceA register required"); | |
1191 | return; | |
1192 | } | |
1193 | str = skip_space (str); | |
1194 | if (*str == ',') | |
1195 | { | |
1196 | str++; | |
1197 | ans = parse_gen_reg (&str, &r3); | |
1198 | if (ans < 0) | |
1199 | { | |
1200 | as_bad ("SourceB register required"); | |
1201 | return; | |
1202 | } | |
1203 | ||
1204 | /* Got three regs, assemble instruction. */ | |
1205 | opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4); | |
1206 | } | |
1207 | else | |
1208 | { | |
1209 | as_bad ("SourceA register required"); | |
1210 | return; | |
1211 | } | |
1212 | } | |
1213 | else | |
1214 | { | |
1215 | as_bad ("Dest register required"); | |
1216 | return; | |
1217 | } | |
1218 | this_dest = r1; | |
1219 | break; | |
1220 | ||
1221 | case mode_iab: | |
1222 | /* 5-bit immediate * register * register | |
1223 | Example: | |
1224 | eamwrite 3,r1,r2 */ | |
1225 | str = parse_exp (str, &e1); | |
1226 | str = skip_space (str); | |
1227 | if (e1.X_op != O_absent && *str == ',') | |
1228 | { | |
1229 | int eam_op = e1.X_add_number; | |
1230 | ||
1231 | str = skip_space (str + 1); | |
1232 | ans = parse_gen_reg (&str, &r2); | |
1233 | if (ans < 0) | |
1234 | { | |
1235 | as_bad ("SourceA register required"); | |
1236 | return; | |
1237 | } | |
1238 | str = skip_space (str); | |
1239 | if (*str == ',') | |
1240 | { | |
1241 | str++; | |
1242 | ans = parse_gen_reg (&str, &r3); | |
1243 | if (ans < 0) | |
1244 | { | |
1245 | as_bad ("SourceB register required"); | |
1246 | return; | |
1247 | } | |
1248 | ||
1249 | /* Got three operands, assemble instruction. */ | |
1250 | if (eam_op < 0 || eam_op > 31) | |
1251 | { | |
1252 | as_bad ("eam_op out of range"); | |
1253 | } | |
1254 | opcode |= ((eam_op & 0x1f) << 10) | (r2 << 16) | (r3 << 4); | |
1255 | } | |
1256 | } | |
1257 | else | |
1258 | { | |
1259 | as_bad ("EAM_OP required"); | |
1260 | return; | |
1261 | } | |
1262 | break; | |
1263 | ||
1264 | case mode_0ab: | |
1265 | /* zero * register * register | |
1266 | Example: | |
1267 | cmp.l r1,r2 */ | |
1268 | ans = parse_gen_reg (&str, &r1); | |
1269 | if (ans < 0) | |
1270 | { | |
1271 | as_bad ("SourceA register required"); | |
1272 | return; | |
1273 | } | |
1274 | str = skip_space (str); | |
1275 | if (*str == ',') | |
1276 | { | |
1277 | str++; | |
1278 | ans = parse_gen_reg (&str, &r2); | |
1279 | if (ans < 0) | |
1280 | { | |
1281 | as_bad ("SourceB register required"); | |
1282 | return; | |
1283 | } | |
1284 | opcode |= (r1 << 16) | (r2 << 4); | |
1285 | } | |
1286 | else | |
1287 | { | |
1288 | as_bad ("SourceB register required"); | |
1289 | return; | |
1290 | } | |
1291 | break; | |
1292 | ||
1293 | case mode_da0: | |
1294 | /* register * register * zero | |
1295 | Example: | |
1296 | move.l r1,r2 */ | |
1297 | ans = parse_gen_reg (&str, &r1); | |
1298 | if (ans < 0) | |
1299 | { | |
1300 | as_bad ("Dest register required"); | |
1301 | return; | |
1302 | } | |
1303 | str = skip_space (str); | |
1304 | if (*str == ',') | |
1305 | { | |
1306 | str++; | |
1307 | ans = parse_gen_reg (&str, &r2); | |
1308 | if (ans < 0) | |
1309 | { | |
1310 | as_bad ("SourceA register required"); | |
1311 | return; | |
1312 | } | |
1313 | opcode |= (r1 << 10) | (r2 << 16); | |
1314 | } | |
1315 | else | |
1316 | { | |
1317 | as_bad ("SourceA register required"); | |
1318 | return; | |
1319 | } | |
1320 | this_dest = r1; | |
1321 | break; | |
1322 | ||
1323 | case mode_cad: | |
1324 | /* condition * register * register | |
1325 | Example: | |
1326 | bra tr,r1,r2 */ | |
1327 | ans = parse_cc (&str, &cc); | |
1328 | if (ans < 0) | |
1329 | { | |
1330 | as_bad ("condition code required"); | |
1331 | return; | |
1332 | } | |
1333 | ||
1334 | str = skip_space (str); | |
1335 | if (*str == ',') | |
1336 | { | |
1337 | str = skip_space (str + 1); | |
1338 | ans = parse_gen_reg (&str, &r2); | |
1339 | if (ans < 0) | |
1340 | { | |
1341 | as_bad ("SourceA register required"); | |
1342 | return; | |
1343 | } | |
1344 | str = skip_space (str); | |
1345 | if (*str == ',') | |
1346 | { | |
1347 | str++; | |
1348 | ans = parse_gen_reg (&str, &r3); | |
1349 | if (ans < 0) | |
1350 | { | |
1351 | as_bad ("Dest register required"); | |
1352 | return; | |
1353 | } | |
1354 | ||
1355 | /* Got three operands, assemble instruction. */ | |
1356 | opcode |= (cc << 27) | (r2 << 16) | (r3 << 10); | |
1357 | } | |
1358 | else | |
1359 | { | |
1360 | as_bad ("Dest register required"); | |
1361 | return; | |
1362 | } | |
1363 | } | |
1364 | else | |
1365 | { | |
1366 | as_bad ("SourceA register required"); | |
1367 | return; | |
1368 | } | |
1369 | ||
1370 | if (previous_mode == mode_cad || previous_mode == mode_ci) | |
1371 | as_bad ("branch instruction in delay slot"); | |
1372 | ||
1373 | this_dest = r3; | |
1374 | condition_code = cc; | |
1375 | break; | |
1376 | ||
1377 | case mode_das: | |
1378 | /* register := register * 5-bit imediate/register shift count | |
1379 | Example: | |
1380 | asl.l r1,r2,4 */ | |
1381 | ans = parse_gen_reg (&str, &r1); | |
1382 | if (ans < 0) | |
1383 | { | |
1384 | as_bad ("Dest register required"); | |
1385 | return; | |
1386 | } | |
1387 | str = skip_space (str); | |
1388 | if (*str == ',') | |
1389 | { | |
1390 | str++; | |
1391 | ans = parse_gen_reg (&str, &r2); | |
1392 | if (ans < 0) | |
1393 | { | |
1394 | as_bad ("SourceA register required"); | |
1395 | return; | |
1396 | } | |
1397 | str = skip_space (str); | |
1398 | if (*str == ',') | |
1399 | { | |
1400 | str++; | |
1401 | ans = parse_gen_reg (&str, &r3); | |
1402 | if (ans == 0) | |
1403 | { | |
1404 | opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4); | |
1405 | } | |
1406 | else | |
1407 | { | |
1408 | str = parse_exp (str, &e1); | |
1409 | if (e1.X_op == O_constant) | |
1410 | { | |
1411 | int imm = e1.X_add_number; | |
1412 | ||
1413 | if (imm < 0 || imm > 31) | |
1414 | as_bad ("immediate value out of range"); | |
1415 | ||
1416 | opcode |= | |
1417 | (r1 << 10) | (r2 << 16) | (1 << 9) | ((imm & 0x1f) << | |
1418 | 4); | |
1419 | } | |
1420 | else | |
1421 | { | |
1422 | as_bad ("immediate operand required"); | |
1423 | return; | |
1424 | } | |
1425 | } | |
1426 | } | |
1427 | } | |
1428 | else | |
1429 | { | |
1430 | as_bad ("SourceA register required"); | |
1431 | return; | |
1432 | } | |
1433 | this_dest = r1; | |
1434 | break; | |
1435 | ||
1436 | case mode_di: | |
1437 | /* register := 5-bit immediate | |
1438 | Example: | |
1439 | eamread r1,3 */ | |
1440 | ans = parse_gen_reg (&str, &r1); | |
1441 | if (ans < 0) | |
1442 | { | |
1443 | as_bad ("Dest register required"); | |
1444 | return; | |
1445 | } | |
1446 | str = skip_space (str); | |
1447 | if (*str == ',') | |
1448 | { | |
1449 | str++; | |
1450 | str = parse_exp (str, &e1); | |
1451 | if (e1.X_op == O_constant) | |
1452 | { | |
1453 | int opnd2 = e1.X_add_number; | |
1454 | ||
1455 | if (opnd2 < 0 || opnd2 > 31) | |
1456 | { | |
1457 | as_bad ("immediate operand out of range"); | |
1458 | return; | |
1459 | } | |
1460 | opcode |= (r1 << 10) | ((opnd2 & 0x1f) << 4); | |
1461 | } | |
1462 | else | |
1463 | { | |
1464 | as_bad ("immediate operand required"); | |
1465 | return; | |
1466 | } | |
1467 | } | |
1468 | else | |
1469 | { | |
1470 | as_bad ("immediate operand required"); | |
1471 | return; | |
1472 | } | |
1473 | this_dest = r1; | |
1474 | break; | |
1475 | ||
1476 | case mode_ir: | |
1477 | /* 5-bit immediate * register, e.g. trace 1,r1 */ | |
1478 | str = parse_exp (str, &e1); | |
1479 | str = skip_space (str); | |
1480 | if (e1.X_op == O_constant && *str == ',') | |
1481 | { | |
1482 | int opnd1 = e1.X_add_number; | |
1483 | ||
1484 | str = skip_space (str + 1); | |
1485 | ans = parse_gen_reg (&str, &r2); | |
1486 | if (ans < 0) | |
1487 | { | |
1488 | as_bad ("SourceA register required"); | |
1489 | return; | |
1490 | } | |
1491 | ||
1492 | /* Got two operands, assemble instruction. */ | |
1493 | if (opnd1 < 0 || opnd1 > 31) | |
1494 | { | |
1495 | as_bad ("1st operand out of range"); | |
1496 | } | |
1497 | opcode |= ((opnd1 & 0x1f) << 10) | (r2 << 16); | |
1498 | } | |
1499 | else | |
1500 | { | |
1501 | as_bad ("Immediate operand required"); | |
1502 | return; | |
1503 | } | |
1504 | break; | |
1505 | ||
1506 | case mode_ai: | |
1507 | /* register *= 16-bit unsigned immediate | |
1508 | Example: | |
1509 | addi r1,123 */ | |
1510 | ans = parse_gen_reg (&str, &r1); | |
1511 | if (ans < 0) | |
1512 | { | |
1513 | as_bad ("Dest register required"); | |
1514 | return; | |
1515 | } | |
1516 | opcode |= (r1 << 16); | |
1517 | ||
1518 | str = skip_space (str); | |
1519 | if (*str != ',') | |
1520 | { | |
1521 | as_bad ("immediate value missing"); | |
1522 | return; | |
1523 | } | |
1524 | this_dest = r1; | |
1525 | ||
1526 | /* fall through... */ | |
1527 | ||
1528 | case mode_i: | |
1529 | /* MOVIL/WRTL traditionally get an implicit "%l" applied | |
1530 | to their immediate value. For other opcodes, unless | |
1531 | the immediate value is decorated with "%u" or "%l" | |
1532 | it must be in the range 0 .. 65535. */ | |
1533 | if ((opcode & 0x7fe00000) == 0x04800000 | |
1534 | || (opcode & 0x7fe00000) == 0x05000000) | |
1535 | reloc = BFD_RELOC_VISIUM_LO16; | |
1536 | else | |
1537 | reloc = BFD_RELOC_VISIUM_IM16; | |
1538 | ||
1539 | str = skip_space (str + 1); | |
1540 | ||
1541 | if (*str == '%') | |
1542 | { | |
1543 | if (str[1] == 'u') | |
1544 | reloc = BFD_RELOC_VISIUM_HI16; | |
1545 | else if (str[1] == 'l') | |
1546 | reloc = BFD_RELOC_VISIUM_LO16; | |
1547 | else | |
1548 | { | |
1549 | as_bad ("bad char after %%"); | |
1550 | return; | |
1551 | } | |
1552 | ||
1553 | str += 2; | |
1554 | } | |
1555 | str = parse_exp (str, &e1); | |
1556 | if (e1.X_op != O_absent) | |
1557 | { | |
1558 | if (e1.X_op == O_constant) | |
1559 | { | |
1560 | int imm = e1.X_add_number; | |
1561 | ||
1562 | if (reloc == BFD_RELOC_VISIUM_HI16) | |
1563 | opcode |= ((imm >> 16) & 0xffff); | |
1564 | else if (reloc == BFD_RELOC_VISIUM_LO16) | |
1565 | opcode |= (imm & 0xffff); | |
1566 | else | |
1567 | { | |
1568 | if (imm < 0 || imm > 0xffff) | |
1569 | as_bad ("immediate value out of range"); | |
1570 | ||
1571 | opcode |= (imm & 0xffff); | |
1572 | } | |
1573 | /* No relocation is needed. */ | |
1574 | reloc = 0; | |
1575 | } | |
1576 | } | |
1577 | else | |
1578 | { | |
1579 | as_bad ("immediate value missing"); | |
1580 | return; | |
1581 | } | |
1582 | break; | |
1583 | ||
1584 | case mode_bax: | |
1585 | /* register * register * 5-bit immediate, | |
1586 | SourceB * SourceA * Index | |
1587 | Examples | |
1588 | write.l (r1),r2 | |
1589 | write.l 3(r1),r2 */ | |
1590 | str = skip_space (str); | |
1591 | ||
1592 | indx = 0; | |
1593 | if (*str != '(') | |
1594 | { | |
1595 | str = parse_exp (str, &e1); | |
1596 | if (e1.X_op == O_constant) | |
1597 | { | |
1598 | indx = e1.X_add_number; | |
1599 | ||
1600 | if (indx < 0 || indx > 31) | |
1601 | { | |
1602 | as_bad ("Index out of range"); | |
1603 | return; | |
1604 | } | |
1605 | } | |
1606 | else | |
1607 | { | |
1608 | as_bad ("Index(SourceA) required"); | |
1609 | return; | |
1610 | } | |
1611 | } | |
1612 | ||
1613 | str = skip_space (str); | |
1614 | ||
1615 | if (*str != '(') | |
1616 | { | |
1617 | as_bad ("Index(SourceA) required"); | |
1618 | return; | |
1619 | } | |
1620 | ||
1621 | str = skip_space (str + 1); | |
1622 | ||
1623 | ans = parse_gen_reg (&str, &r1); | |
1624 | if (ans < 0) | |
1625 | { | |
1626 | as_bad ("SourceA register required"); | |
1627 | return; | |
1628 | } | |
1629 | str = skip_space (str); | |
1630 | if (*str != ')') | |
1631 | { | |
1632 | as_bad ("(SourceA) required"); | |
1633 | return; | |
1634 | } | |
1635 | str = skip_space (str + 1); | |
1636 | ||
1637 | if (*str == ',') | |
1638 | { | |
1639 | str = skip_space (str + 1); | |
1640 | ans = parse_gen_reg (&str, &r2); | |
1641 | if (ans < 0) | |
1642 | { | |
1643 | as_bad ("SourceB register required"); | |
1644 | return; | |
1645 | } | |
1646 | } | |
1647 | else | |
1648 | { | |
1649 | as_bad ("SourceB register required"); | |
1650 | return; | |
1651 | } | |
1652 | ||
1653 | opcode |= (r1 << 16) | (r2 << 4) | ((indx & 0x1f) << 10); | |
1654 | ||
1655 | if (indx != 0 && previous_mode == mode_cad) | |
1656 | { | |
1657 | /* We're in a delay slot. | |
1658 | If the base reg is the destination of the branch, then issue | |
1659 | an error message. | |
1660 | Otherwise it is safe to use the base and index. */ | |
1661 | if (previous_dest != 0 && r1 == previous_dest) | |
1662 | { | |
1663 | as_bad ("base register not ready"); | |
1664 | return; | |
1665 | } | |
1666 | } | |
1667 | else if (previous_dest != 0 | |
1668 | && r1 == previous_dest | |
1669 | && (visium_arch == VISIUM_ARCH_MCM | |
1670 | || visium_arch == VISIUM_ARCH_MCM24 | |
1671 | || (visium_arch == VISIUM_ARCH_DEF && indx != 0))) | |
1672 | { | |
1673 | as_warn ("base register not ready, NOP inserted."); | |
1674 | /* Insert a NOP before the write instruction. */ | |
1675 | output = frag_more (4); | |
1676 | memset (output, 0, 4); | |
1677 | } | |
1678 | break; | |
1679 | ||
1680 | case mode_dax: | |
1681 | /* register := register * 5-bit immediate | |
1682 | Examples: | |
1683 | read.b r1,(r2) | |
1684 | read.w r1,3(r2) */ | |
1685 | ans = parse_gen_reg (&str, &r1); | |
1686 | if (ans < 0) | |
1687 | { | |
1688 | as_bad ("Dest register required"); | |
1689 | return; | |
1690 | } | |
1691 | str = skip_space (str); | |
1692 | if (*str != ',') | |
1693 | { | |
1694 | as_bad ("SourceA required"); | |
1695 | return; | |
1696 | } | |
1697 | str = skip_space (str + 1); | |
1698 | ||
1699 | indx = 0; | |
1700 | if (*str != '(') | |
1701 | { | |
1702 | str = parse_exp (str, &e1); | |
1703 | if (e1.X_op == O_constant) | |
1704 | { | |
1705 | indx = e1.X_add_number; | |
1706 | ||
1707 | if (indx < 0 || indx > 31) | |
1708 | { | |
1709 | as_bad ("Index out of range"); | |
1710 | return; | |
1711 | } | |
1712 | } | |
1713 | else | |
1714 | { | |
1715 | as_bad ("Immediate 0 to 31 required"); | |
1716 | return; | |
1717 | } | |
1718 | } | |
1719 | if (*str != '(') | |
1720 | { | |
1721 | as_bad ("(SourceA) required"); | |
1722 | return; | |
1723 | } | |
1724 | str++; | |
1725 | ans = parse_gen_reg (&str, &r2); | |
1726 | if (ans < 0) | |
1727 | { | |
1728 | as_bad ("SourceA register required"); | |
1729 | return; | |
1730 | } | |
1731 | str = skip_space (str); | |
1732 | if (*str != ')') | |
1733 | { | |
1734 | as_bad ("(SourceA) required"); | |
1735 | return; | |
1736 | } | |
1737 | str++; | |
1738 | opcode |= (r1 << 10) | (r2 << 16) | ((indx & 0x1f) << 4); | |
1739 | this_dest = r1; | |
1740 | ||
1741 | if (indx != 0 && previous_mode == mode_cad) | |
1742 | { | |
1743 | /* We're in a delay slot. | |
1744 | If the base reg is the destination of the branch, then issue | |
1745 | an error message. | |
1746 | Otherwise it is safe to use the base and index. */ | |
1747 | if (previous_dest != 0 && r2 == previous_dest) | |
1748 | { | |
1749 | as_bad ("base register not ready"); | |
1750 | return; | |
1751 | } | |
1752 | } | |
1753 | else if (previous_dest != 0 | |
1754 | && r2 == previous_dest | |
1755 | && (visium_arch == VISIUM_ARCH_MCM | |
1756 | || visium_arch == VISIUM_ARCH_MCM24 | |
1757 | || (visium_arch == VISIUM_ARCH_DEF && indx != 0))) | |
1758 | { | |
1759 | as_warn ("base register not ready, NOP inserted."); | |
1760 | /* Insert a NOP before the read instruction. */ | |
1761 | output = frag_more (4); | |
1762 | memset (output, 0, 4); | |
1763 | } | |
1764 | break; | |
1765 | ||
1766 | case mode_s: | |
1767 | /* special mode | |
1768 | Example: | |
1769 | nop */ | |
1770 | str = skip_space (str); | |
1771 | break; | |
1772 | ||
1773 | case mode_ci: | |
1774 | /* condition * 16-bit signed word displacement | |
1775 | Example: | |
1776 | brr L1 */ | |
1777 | ans = parse_cc (&str, &cc); | |
1778 | if (ans < 0) | |
1779 | { | |
1780 | as_bad ("condition code required"); | |
1781 | return; | |
1782 | } | |
1783 | opcode |= (cc << 27); | |
1784 | ||
1785 | str = skip_space (str); | |
1786 | if (*str == ',') | |
1787 | { | |
1788 | str = skip_space (str + 1); | |
1789 | str = parse_exp (str, &e1); | |
1790 | if (e1.X_op != O_absent) | |
1791 | { | |
1792 | if (e1.X_op == O_constant) | |
1793 | { | |
1794 | int imm = e1.X_add_number; | |
1795 | ||
1796 | if (imm < -32768 || imm > 32767) | |
1797 | as_bad ("immediate value out of range"); | |
1798 | ||
1799 | /* The GR6 doesn't correctly handle a 0 displacement | |
1800 | so we insert a NOP and change it to -1. */ | |
1801 | if (imm == 0 && cc != 0 && visium_arch == VISIUM_ARCH_GR6) | |
1802 | { | |
1803 | output = frag_more (4); | |
1804 | memset (output, 0, 4); | |
1805 | imm = -1; | |
1806 | } | |
1807 | ||
1808 | opcode |= (imm & 0xffff); | |
1809 | } | |
1810 | else if (e1.X_op == O_symbol) | |
1811 | { | |
1812 | /* The GR6 doesn't correctly handle a 0 displacement | |
1813 | so the instruction requires relaxation. */ | |
1814 | if (cc != 0 && visium_arch == VISIUM_ARCH_GR6) | |
1815 | relax = amode; | |
1816 | else | |
1817 | reloc = BFD_RELOC_VISIUM_REL16; | |
1818 | } | |
1819 | else | |
1820 | { | |
1821 | as_bad ("immediate value missing"); | |
1822 | return; | |
1823 | } | |
1824 | } | |
1825 | else | |
1826 | { | |
1827 | as_bad ("immediate value missing"); | |
1828 | return; | |
1829 | } | |
1830 | } | |
1831 | else | |
1832 | { | |
1833 | as_bad ("immediate value missing"); | |
1834 | return; | |
1835 | } | |
1836 | ||
1837 | if (previous_mode == mode_cad || previous_mode == mode_ci) | |
1838 | as_bad ("branch instruction in delay slot"); | |
1839 | ||
1840 | condition_code = cc; | |
1841 | break; | |
1842 | ||
1843 | case mode_fdab: | |
1844 | /* float := float * float | |
1845 | Example | |
1846 | fadd f4,f3,f2 */ | |
1847 | ans = parse_fp_reg (&str, &r1); | |
1848 | if (ans < 0) | |
1849 | { | |
1850 | as_bad ("floating point destination register required"); | |
1851 | return; | |
1852 | } | |
1853 | str = skip_space (str); | |
1854 | if (*str == ',') | |
1855 | { | |
1856 | str++; | |
1857 | ans = parse_fp_reg (&str, &r2); | |
1858 | if (ans < 0) | |
1859 | { | |
1860 | as_bad ("floating point SourceA register required"); | |
1861 | return; | |
1862 | } | |
1863 | str = skip_space (str); | |
1864 | if (*str == ',') | |
1865 | { | |
1866 | str++; | |
1867 | ans = parse_fp_reg (&str, &r3); | |
1868 | if (ans < 0) | |
1869 | { | |
1870 | as_bad ("floating point SourceB register required"); | |
1871 | return; | |
1872 | } | |
1873 | ||
1874 | /* Got 3 floating regs, assemble instruction. */ | |
1875 | opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4); | |
1876 | } | |
1877 | else | |
1878 | { | |
1879 | as_bad ("floating point SourceB register required"); | |
1880 | return; | |
1881 | } | |
1882 | } | |
1883 | else | |
1884 | { | |
1885 | as_bad ("floating point SourceA register required"); | |
1886 | return; | |
1887 | } | |
1888 | break; | |
1889 | ||
1890 | case mode_ifdab: | |
1891 | /* 4-bit immediate * float * float * float | |
1892 | Example | |
1893 | fpinst 10,f1,f2,f3 */ | |
1894 | str = parse_exp (str, &e1); | |
1895 | str = skip_space (str); | |
1896 | if (e1.X_op != O_absent && *str == ',') | |
1897 | { | |
1898 | int finst = e1.X_add_number; | |
1899 | ||
1900 | str = skip_space (str + 1); | |
1901 | ans = parse_fp_reg (&str, &r1); | |
1902 | if (ans < 0) | |
1903 | { | |
1904 | as_bad ("floating point destination register required"); | |
1905 | return; | |
1906 | } | |
1907 | str = skip_space (str); | |
1908 | if (*str == ',') | |
1909 | { | |
1910 | str++; | |
1911 | ans = parse_fp_reg (&str, &r2); | |
1912 | if (ans < 0) | |
1913 | { | |
1914 | as_bad ("floating point SourceA register required"); | |
1915 | return; | |
1916 | } | |
1917 | str = skip_space (str); | |
1918 | if (*str == ',') | |
1919 | { | |
1920 | str++; | |
1921 | ans = parse_fp_reg (&str, &r3); | |
1922 | if (ans < 0) | |
1923 | { | |
1924 | as_bad ("floating point SourceB register required"); | |
1925 | return; | |
1926 | } | |
1927 | ||
1928 | /* Got immediate and 3 floating regs, | |
1929 | assemble instruction. */ | |
1930 | if (finst < 0 || finst > 15) | |
1931 | as_bad ("finst out of range"); | |
1932 | ||
1933 | opcode |= | |
1934 | ((finst & 0xf) << 27) | (r1 << 10) | (r2 << 16) | (r3 << | |
1935 | 4); | |
1936 | } | |
1937 | else | |
1938 | { | |
1939 | as_bad ("floating point SourceB register required"); | |
1940 | return; | |
1941 | } | |
1942 | } | |
1943 | else | |
1944 | { | |
1945 | as_bad ("floating point SourceA register required"); | |
1946 | return; | |
1947 | } | |
1948 | } | |
1949 | else | |
1950 | { | |
1951 | as_bad ("finst missing"); | |
1952 | return; | |
1953 | } | |
1954 | break; | |
1955 | ||
1956 | case mode_idfab: | |
1957 | /* 4-bit immediate * register * float * float | |
1958 | Example | |
1959 | fpuread 4,r25,f2,f3 */ | |
1960 | str = parse_exp (str, &e1); | |
1961 | str = skip_space (str); | |
1962 | if (e1.X_op != O_absent && *str == ',') | |
1963 | { | |
1964 | int finst = e1.X_add_number; | |
1965 | ||
1966 | str = skip_space (str + 1); | |
1967 | ans = parse_gen_reg (&str, &r1); | |
1968 | if (ans < 0) | |
1969 | { | |
1970 | as_bad ("destination general register required"); | |
1971 | return; | |
1972 | } | |
1973 | str = skip_space (str); | |
1974 | if (*str == ',') | |
1975 | { | |
1976 | str++; | |
1977 | ans = parse_fp_reg (&str, &r2); | |
1978 | if (ans < 0) | |
1979 | { | |
1980 | as_bad ("floating point SourceA register required"); | |
1981 | return; | |
1982 | } | |
1983 | str = skip_space (str); | |
1984 | if (*str == ',') | |
1985 | { | |
1986 | str++; | |
1987 | ans = parse_fp_reg (&str, &r3); | |
1988 | if (ans < 0) | |
1989 | { | |
1990 | as_bad ("floating point SourceB register required"); | |
1991 | return; | |
1992 | } | |
1993 | ||
1994 | /* Got immediate and 3 floating regs, | |
1995 | assemble instruction. */ | |
1996 | if (finst < 0 || finst > 15) | |
1997 | as_bad ("finst out of range"); | |
1998 | ||
1999 | opcode |= | |
2000 | ((finst & 0xf) << 27) | (r1 << 10) | (r2 << 16) | (r3 << | |
2001 | 4); | |
2002 | } | |
2003 | else | |
2004 | { | |
2005 | as_bad ("floating point SourceB register required"); | |
2006 | return; | |
2007 | } | |
2008 | } | |
2009 | else | |
2010 | { | |
2011 | as_bad ("floating point SourceA register required"); | |
2012 | return; | |
2013 | } | |
2014 | } | |
2015 | else | |
2016 | { | |
2017 | as_bad ("finst missing"); | |
2018 | return; | |
2019 | } | |
2020 | break; | |
2021 | ||
2022 | case mode_fda: | |
2023 | /* float := float | |
2024 | Example | |
2025 | fsqrt f4,f3 */ | |
2026 | ans = parse_fp_reg (&str, &r1); | |
2027 | if (ans < 0) | |
2028 | { | |
2029 | as_bad ("floating point destination register required"); | |
2030 | return; | |
2031 | } | |
2032 | str = skip_space (str); | |
2033 | if (*str == ',') | |
2034 | { | |
2035 | str++; | |
2036 | ans = parse_fp_reg (&str, &r2); | |
2037 | if (ans < 0) | |
2038 | { | |
2039 | as_bad ("floating point source register required"); | |
2040 | return; | |
2041 | } | |
2042 | ||
2043 | /* Got 2 floating regs, assemble instruction. */ | |
2044 | opcode |= (r1 << 10) | (r2 << 16); | |
2045 | } | |
2046 | else | |
2047 | { | |
2048 | as_bad ("floating point source register required"); | |
2049 | return; | |
2050 | } | |
2051 | break; | |
2052 | ||
2053 | case mode_fdra: | |
2054 | /* float := register | |
2055 | Example | |
2056 | fload f15,r6 */ | |
2057 | ans = parse_fp_reg (&str, &r1); | |
2058 | if (ans < 0) | |
2059 | { | |
2060 | as_bad ("floating point destination register required"); | |
2061 | return; | |
2062 | } | |
2063 | str = skip_space (str); | |
2064 | if (*str == ',') | |
2065 | { | |
2066 | str++; | |
2067 | ans = parse_gen_reg (&str, &r2); | |
2068 | if (ans < 0) | |
2069 | { | |
2070 | as_bad ("SourceA general register required"); | |
2071 | return; | |
2072 | } | |
2073 | ||
2074 | /* Got 2 regs, assemble instruction. */ | |
2075 | opcode |= (r1 << 10) | (r2 << 16); | |
2076 | } | |
2077 | else | |
2078 | { | |
2079 | as_bad ("SourceA general register required"); | |
2080 | return; | |
2081 | } | |
2082 | break; | |
2083 | ||
2084 | case mode_rdfab: | |
2085 | /* register := float * float | |
2086 | Example | |
2087 | fcmp r0,f4,f8 | |
2088 | For the GR6, register must be r0 and can be omitted. */ | |
2089 | ans = parse_gen_reg (&str, &r1); | |
2090 | if (ans < 0) | |
2091 | { | |
2092 | if (visium_opcode_arch == VISIUM_OPCODE_ARCH_GR5) | |
2093 | { | |
2094 | as_bad ("Dest general register required"); | |
2095 | return; | |
2096 | } | |
2097 | r1 = 0; | |
2098 | } | |
2099 | else | |
2100 | { | |
2101 | if (r1 != 0 && visium_opcode_arch != VISIUM_OPCODE_ARCH_GR5) | |
2102 | { | |
2103 | as_bad ("FCMP/FCMPE can only use r0 as Dest register"); | |
2104 | return; | |
2105 | } | |
2106 | ||
2107 | str = skip_space (str); | |
2108 | if (*str == ',') | |
2109 | str++; | |
2110 | else | |
2111 | { | |
2112 | as_bad ("floating point SourceA register required"); | |
2113 | return; | |
2114 | } | |
2115 | } | |
2116 | ||
2117 | ans = parse_fp_reg (&str, &r2); | |
2118 | if (ans < 0) | |
2119 | { | |
2120 | as_bad ("floating point SourceA register required"); | |
2121 | return; | |
2122 | } | |
2123 | str = skip_space (str); | |
2124 | if (*str == ',') | |
2125 | { | |
2126 | str++; | |
2127 | ans = parse_fp_reg (&str, &r3); | |
2128 | if (ans < 0) | |
2129 | { | |
2130 | as_bad ("floating point SourceB register required"); | |
2131 | return; | |
2132 | } | |
2133 | ||
2134 | /* Got 3 regs, assemble instruction. */ | |
2135 | opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4); | |
2136 | } | |
2137 | ||
2138 | this_dest = r1; | |
2139 | break; | |
2140 | ||
2141 | case mode_rdfa: | |
2142 | /* register := float | |
2143 | Example | |
2144 | fstore r5,f12 */ | |
2145 | ans = parse_gen_reg (&str, &r1); | |
2146 | if (ans < 0) | |
2147 | { | |
2148 | as_bad ("Dest general register required"); | |
2149 | return; | |
2150 | } | |
2151 | str = skip_space (str); | |
2152 | if (*str == ',') | |
2153 | { | |
2154 | str++; | |
2155 | ans = parse_fp_reg (&str, &r2); | |
2156 | if (ans < 0) | |
2157 | { | |
2158 | as_bad ("floating point source register required"); | |
2159 | return; | |
2160 | } | |
2161 | ||
2162 | /* Got 2 regs, assemble instruction. */ | |
2163 | opcode |= (r1 << 10) | (r2 << 16); | |
2164 | } | |
2165 | else | |
2166 | { | |
2167 | as_bad ("floating point source register required"); | |
2168 | return; | |
2169 | } | |
2170 | ||
2171 | this_dest = r1; | |
2172 | break; | |
2173 | ||
2174 | case mode_rrr: | |
2175 | /* register register register, all sources and destinations | |
2176 | Example: | |
2177 | bmd r1,r2,r3 */ | |
2178 | ||
2179 | ans = parse_gen_reg (&str, &r1); | |
2180 | if (ans < 0) | |
2181 | { | |
2182 | as_bad ("destination address register required"); | |
2183 | return; | |
2184 | } | |
2185 | str = skip_space (str); | |
2186 | if (*str == ',') | |
2187 | { | |
2188 | str++; | |
2189 | ans = parse_gen_reg (&str, &r2); | |
2190 | if (ans < 0) | |
2191 | { | |
2192 | as_bad ("source address register required"); | |
2193 | return; | |
2194 | } | |
2195 | str = skip_space (str); | |
2196 | if (*str == ',') | |
2197 | { | |
2198 | str++; | |
2199 | ans = parse_gen_reg (&str, &r3); | |
2200 | if (ans < 0) | |
2201 | { | |
2202 | as_bad ("count register required"); | |
2203 | return; | |
2204 | } | |
2205 | ||
2206 | /* We insist on three registers but the opcode can only use | |
2207 | r1,r2,r3. */ | |
2208 | if (r1 != 1 || r2 != 2 || r3 != 3) | |
2209 | { | |
2210 | as_bad ("BMI/BMD can only use format op r1,r2,r3"); | |
2211 | return; | |
2212 | } | |
2213 | ||
2214 | /* Opcode is unmodified by what comes out of the table. */ | |
2215 | } | |
2216 | else | |
2217 | { | |
2218 | as_bad ("register required"); | |
2219 | return; | |
2220 | } | |
2221 | } | |
2222 | else | |
2223 | { | |
2224 | as_bad ("register required"); | |
2225 | return; | |
2226 | } | |
2227 | ||
2228 | this_dest = r1; | |
2229 | break; | |
2230 | ||
2231 | default: | |
2232 | break; | |
2233 | } | |
2234 | ||
2235 | if (relax) | |
2236 | output = frag_var (rs_machine_dependent, 8, 4, relax, e1.X_add_symbol, | |
2237 | e1.X_add_number, NULL); | |
2238 | else | |
2239 | output = frag_more (4); | |
2240 | ||
2241 | /* Build the 32-bit instruction in a host-endian-neutral fashion. */ | |
2242 | output[0] = (opcode >> 24) & 0xff; | |
2243 | output[1] = (opcode >> 16) & 0xff; | |
2244 | output[2] = (opcode >> 8) & 0xff; | |
2245 | output[3] = (opcode >> 0) & 0xff; | |
2246 | ||
2247 | if (relax) | |
2248 | /* The size of the instruction is unknown, so tie the debug info to the | |
2249 | start of the instruction. */ | |
2250 | dwarf2_emit_insn (0); | |
2251 | else | |
2252 | { | |
2253 | if (reloc) | |
2254 | fix_new_exp (frag_now, output - frag_now->fr_literal, 4, &e1, | |
2255 | reloc == BFD_RELOC_VISIUM_REL16, reloc); | |
2256 | else | |
2257 | visium_update_parity_bit (output); | |
2258 | ||
2259 | dwarf2_emit_insn (4); | |
2260 | } | |
2261 | ||
2262 | if (*str != '\0') | |
2263 | as_bad ("junk after instruction"); | |
2264 | } | |
2265 | ||
2266 | void | |
2267 | visium_cfi_frame_initial_instructions (void) | |
2268 | { | |
2269 | /* The CFA is in SP on function entry. */ | |
2270 | cfi_add_CFA_def_cfa (23, 0); | |
2271 | } | |
2272 | ||
2273 | int | |
2274 | visium_regname_to_dw2regnum (char *regname) | |
2275 | { | |
2276 | if (!regname[0]) | |
2277 | return -1; | |
2278 | ||
2279 | if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) | |
2280 | return 22; | |
2281 | ||
2282 | if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) | |
2283 | return 23; | |
2284 | ||
2285 | if (regname[0] == 'm' && regname[1] == 'd' && !regname[3]) | |
2286 | switch (regname[2]) | |
2287 | { | |
2288 | case 'b': return 32; | |
2289 | case 'a': return 33; | |
2290 | case 'c': return 34; | |
2291 | default : return -1; | |
2292 | } | |
2293 | ||
2294 | if (regname[0] == 'f' || regname[0] == 'r') | |
2295 | { | |
2296 | char *p; | |
2297 | unsigned int regnum = strtoul (regname + 1, &p, 10); | |
2298 | if (*p) | |
2299 | return -1; | |
2300 | if (regnum >= (regname[0] == 'f' ? 16 : 32)) | |
2301 | return -1; | |
2302 | if (regname[0] == 'f') | |
2303 | regnum += 35; | |
2304 | return regnum; | |
2305 | } | |
2306 | ||
2307 | return -1; | |
2308 | } |