Commit | Line | Data |
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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
2571583a | 2 | Copyright (C) 2003-2017 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
e0001a05 NC |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 | 20 | |
e0001a05 | 21 | #include "as.h" |
df7b86aa | 22 | #include <limits.h> |
e0001a05 NC |
23 | #include "sb.h" |
24 | #include "safe-ctype.h" | |
25 | #include "tc-xtensa.h" | |
e0001a05 NC |
26 | #include "subsegs.h" |
27 | #include "xtensa-relax.h" | |
cda2eb9e | 28 | #include "dwarf2dbg.h" |
b224e962 | 29 | #include "xtensa-istack.h" |
e0001a05 NC |
30 | #include "struc-symbol.h" |
31 | #include "xtensa-config.h" | |
b0b79343 | 32 | #include "elf/xtensa.h" |
e0001a05 | 33 | |
2caa7ca0 BW |
34 | /* Provide default values for new configuration settings. */ |
35 | #ifndef XSHAL_ABI | |
36 | #define XSHAL_ABI 0 | |
37 | #endif | |
38 | ||
e0001a05 NC |
39 | #ifndef uint32 |
40 | #define uint32 unsigned int | |
41 | #endif | |
42 | #ifndef int32 | |
43 | #define int32 signed int | |
44 | #endif | |
45 | ||
46 | /* Notes: | |
47 | ||
e0001a05 NC |
48 | Naming conventions (used somewhat inconsistently): |
49 | The xtensa_ functions are exported | |
50 | The xg_ functions are internal | |
51 | ||
52 | We also have a couple of different extensibility mechanisms. | |
53 | 1) The idiom replacement: | |
54 | This is used when a line is first parsed to | |
55 | replace an instruction pattern with another instruction | |
56 | It is currently limited to replacements of instructions | |
57 | with constant operands. | |
58 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
59 | replacement patterns. When an instruction's immediate field | |
60 | does not fit the next instruction sequence is attempted. | |
61 | In addition, "narrow" opcodes are supported this way. */ | |
62 | ||
63 | ||
64 | /* Define characters with special meanings to GAS. */ | |
65 | const char comment_chars[] = "#"; | |
66 | const char line_comment_chars[] = "#"; | |
67 | const char line_separator_chars[] = ";"; | |
68 | const char EXP_CHARS[] = "eE"; | |
69 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
70 | ||
71 | ||
43cd72b9 BW |
72 | /* Flags to indicate whether the hardware supports the density and |
73 | absolute literals options. */ | |
e0001a05 | 74 | |
f7e16c2a MF |
75 | bfd_boolean density_supported; |
76 | bfd_boolean absolute_literals_supported; | |
43cd72b9 | 77 | |
43cd72b9 BW |
78 | static vliw_insn cur_vinsn; |
79 | ||
77cba8a3 | 80 | unsigned xtensa_num_pipe_stages; |
f7e16c2a | 81 | unsigned xtensa_fetch_width; |
43cd72b9 BW |
82 | |
83 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
84 | ||
85 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 86 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
87 | back end. */ |
88 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
89 | |
90 | /* Flags for properties of the last instruction in a segment. */ | |
91 | #define FLAG_IS_A0_WRITER 0x1 | |
92 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
93 | ||
94 | ||
95 | /* We define a special segment names ".literal" to place literals | |
96 | into. The .fini and .init sections are special because they | |
97 | contain code that is moved together by the linker. We give them | |
98 | their own special .fini.literal and .init.literal sections. */ | |
99 | ||
100 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 101 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 | 102 | #define INIT_SECTION_NAME xtensa_section_rename (".init") |
74869ac7 | 103 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
e0001a05 NC |
104 | |
105 | ||
43cd72b9 | 106 | /* This type is used for the directive_stack to keep track of the |
74869ac7 BW |
107 | state of the literal collection pools. If lit_prefix is set, it is |
108 | used to determine the literal section names; otherwise, the literal | |
109 | sections are determined based on the current text section. The | |
110 | lit_seg and lit4_seg fields cache these literal sections, with the | |
111 | current_text_seg field used a tag to indicate whether the cached | |
112 | values are valid. */ | |
e0001a05 NC |
113 | |
114 | typedef struct lit_state_struct | |
115 | { | |
74869ac7 BW |
116 | char *lit_prefix; |
117 | segT current_text_seg; | |
e0001a05 | 118 | segT lit_seg; |
43cd72b9 | 119 | segT lit4_seg; |
e0001a05 NC |
120 | } lit_state; |
121 | ||
122 | static lit_state default_lit_sections; | |
123 | ||
124 | ||
74869ac7 BW |
125 | /* We keep a list of literal segments. The seg_list type is the node |
126 | for this list. The literal_head pointer is the head of the list, | |
127 | with the literal_head_h dummy node at the start. */ | |
e0001a05 NC |
128 | |
129 | typedef struct seg_list_struct | |
130 | { | |
131 | struct seg_list_struct *next; | |
132 | segT seg; | |
133 | } seg_list; | |
134 | ||
135 | static seg_list literal_head_h; | |
136 | static seg_list *literal_head = &literal_head_h; | |
e0001a05 NC |
137 | |
138 | ||
82e7541d BW |
139 | /* Lists of symbols. We keep a list of symbols that label the current |
140 | instruction, so that we can adjust the symbols when inserting alignment | |
141 | for various instructions. We also keep a list of all the symbols on | |
142 | literals, so that we can fix up those symbols when the literals are | |
143 | later moved into the text sections. */ | |
144 | ||
145 | typedef struct sym_list_struct | |
146 | { | |
147 | struct sym_list_struct *next; | |
148 | symbolS *sym; | |
149 | } sym_list; | |
150 | ||
151 | static sym_list *insn_labels = NULL; | |
152 | static sym_list *free_insn_labels = NULL; | |
153 | static sym_list *saved_insn_labels = NULL; | |
154 | ||
155 | static sym_list *literal_syms; | |
156 | ||
157 | ||
43cd72b9 BW |
158 | /* Flags to determine whether to prefer const16 or l32r |
159 | if both options are available. */ | |
160 | int prefer_const16 = 0; | |
161 | int prefer_l32r = 0; | |
162 | ||
e0001a05 NC |
163 | /* Global flag to indicate when we are emitting literals. */ |
164 | int generating_literals = 0; | |
165 | ||
43cd72b9 BW |
166 | /* The following PROPERTY table definitions are copied from |
167 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
168 | ||
169 | /* Flags in the property tables to specify whether blocks of memory | |
170 | are literals, instructions, data, or unreachable. For | |
171 | instructions, blocks that begin loop targets and branch targets are | |
172 | designated. Blocks that do not allow density, instruction | |
173 | reordering or transformation are also specified. Finally, for | |
174 | branch targets, branch target alignment priority is included. | |
175 | Alignment of the next block is specified in the current block | |
176 | and the size of the current block does not include any fill required | |
177 | to align to the next block. */ | |
178 | ||
179 | #define XTENSA_PROP_LITERAL 0x00000001 | |
180 | #define XTENSA_PROP_INSN 0x00000002 | |
181 | #define XTENSA_PROP_DATA 0x00000004 | |
182 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
183 | /* Instruction only properties at beginning of code. */ | |
184 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
185 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
186 | /* Instruction only properties about code. */ | |
187 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
188 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
99ded152 BW |
189 | /* Historically, NO_TRANSFORM was a property of instructions, |
190 | but it should apply to literals under certain circumstances. */ | |
191 | #define XTENSA_PROP_NO_TRANSFORM 0x00000100 | |
43cd72b9 BW |
192 | |
193 | /* Branch target alignment information. This transmits information | |
194 | to the linker optimization about the priority of aligning a | |
195 | particular block for branch target alignment: None, low priority, | |
196 | high priority, or required. These only need to be checked in | |
197 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
198 | Common usage is | |
199 | ||
200 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
201 | case XTENSA_PROP_BT_ALIGN_NONE: | |
202 | case XTENSA_PROP_BT_ALIGN_LOW: | |
203 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
204 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
205 | */ | |
206 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
207 | ||
208 | /* No branch target alignment. */ | |
209 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
210 | /* Low priority branch target alignment. */ | |
211 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
212 | /* High priority branch target alignment. */ | |
213 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
214 | /* Required branch target alignment. */ | |
215 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
216 | ||
43cd72b9 BW |
217 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ |
218 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
219 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
220 | ||
221 | ||
222 | /* Alignment is specified in the block BEFORE the one that needs | |
223 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
224 | get the required alignment specified as a power of 2. Use | |
225 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
226 | alignment. Be careful of side effects since the SET will evaluate | |
227 | flags twice. Also, note that the SIZE of a block in the property | |
228 | table does not include the alignment size, so the alignment fill | |
229 | must be calculated to determine if two blocks are contiguous. | |
230 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
231 | possible future implementation. */ | |
232 | ||
233 | #define XTENSA_PROP_ALIGN 0x00000800 | |
234 | ||
235 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
236 | ||
43cd72b9 BW |
237 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ |
238 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
239 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
240 | ||
241 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
242 | ||
243 | ||
244 | /* Structure for saving instruction and alignment per-fragment data | |
245 | that will be written to the object file. This structure is | |
246 | equivalent to the actual data that will be written out to the file | |
247 | but is easier to use. We provide a conversion to file flags | |
248 | in frag_flags_to_number. */ | |
249 | ||
250 | typedef struct frag_flags_struct frag_flags; | |
251 | ||
252 | struct frag_flags_struct | |
253 | { | |
254 | /* is_literal should only be used after xtensa_move_literals. | |
255 | If you need to check if you are generating a literal fragment, | |
256 | then use the generating_literals global. */ | |
257 | ||
258 | unsigned is_literal : 1; | |
259 | unsigned is_insn : 1; | |
260 | unsigned is_data : 1; | |
261 | unsigned is_unreachable : 1; | |
262 | ||
99ded152 BW |
263 | /* is_specific_opcode implies no_transform. */ |
264 | unsigned is_no_transform : 1; | |
265 | ||
43cd72b9 BW |
266 | struct |
267 | { | |
268 | unsigned is_loop_target : 1; | |
269 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
270 | unsigned bt_align_priority : 2; | |
271 | ||
272 | unsigned is_no_density : 1; | |
273 | /* no_longcalls flag does not need to be placed in the object file. */ | |
43cd72b9 BW |
274 | |
275 | unsigned is_no_reorder : 1; | |
276 | ||
277 | /* Uses absolute literal addressing for l32r. */ | |
278 | unsigned is_abslit : 1; | |
279 | } insn; | |
280 | unsigned is_align : 1; | |
281 | unsigned alignment : 5; | |
282 | }; | |
283 | ||
284 | ||
285 | /* Structure for saving information about a block of property data | |
286 | for frags that have the same flags. */ | |
287 | struct xtensa_block_info_struct | |
288 | { | |
289 | segT sec; | |
290 | bfd_vma offset; | |
291 | size_t size; | |
292 | frag_flags flags; | |
293 | struct xtensa_block_info_struct *next; | |
294 | }; | |
295 | ||
e0001a05 NC |
296 | |
297 | /* Structure for saving the current state before emitting literals. */ | |
298 | typedef struct emit_state_struct | |
299 | { | |
300 | const char *name; | |
301 | segT now_seg; | |
302 | subsegT now_subseg; | |
303 | int generating_literals; | |
304 | } emit_state; | |
305 | ||
306 | ||
43cd72b9 BW |
307 | /* Opcode placement information */ |
308 | ||
309 | typedef unsigned long long bitfield; | |
310 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
311 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
312 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
313 | ||
314 | #define MAX_FORMATS 32 | |
315 | ||
316 | typedef struct op_placement_info_struct | |
317 | { | |
318 | int num_formats; | |
319 | /* A number describing how restrictive the issue is for this | |
320 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 321 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 322 | only one format but many slots in that format. The most |
c138bc38 | 323 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
324 | format. */ |
325 | int issuef; | |
43cd72b9 | 326 | xtensa_format narrowest; |
43cd72b9 | 327 | char narrowest_size; |
b2d179be | 328 | char narrowest_slot; |
43cd72b9 BW |
329 | |
330 | /* formats is a bitfield with the Nth bit set | |
331 | if the opcode fits in the Nth xtensa_format. */ | |
332 | bitfield formats; | |
333 | ||
334 | /* slots[N]'s Mth bit is set if the op fits in the | |
335 | Mth slot of the Nth xtensa_format. */ | |
336 | bitfield slots[MAX_FORMATS]; | |
337 | ||
338 | /* A count of the number of slots in a given format | |
339 | an op can fit (i.e., the bitcount of the slot field above). */ | |
340 | char slots_in_format[MAX_FORMATS]; | |
341 | ||
342 | } op_placement_info, *op_placement_info_table; | |
343 | ||
344 | op_placement_info_table op_placement_table; | |
345 | ||
346 | ||
347 | /* Extra expression types. */ | |
348 | ||
349 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
350 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
351 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
1bbb5f21 | 352 | #define O_pcrel O_md4 /* value is a PC-relative offset */ |
28dbbc02 BW |
353 | #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */ |
354 | #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */ | |
355 | #define O_tlscall O_md7 /* TLS_CALL relocation */ | |
356 | #define O_tpoff O_md8 /* TPOFF relocation */ | |
357 | #define O_dtpoff O_md9 /* DTPOFF relocation */ | |
43cd72b9 | 358 | |
bbdd25a8 BW |
359 | struct suffix_reloc_map |
360 | { | |
b9bb4a93 | 361 | const char *suffix; |
bbdd25a8 BW |
362 | int length; |
363 | bfd_reloc_code_real_type reloc; | |
cc34adb2 | 364 | operatorT operator; |
bbdd25a8 BW |
365 | }; |
366 | ||
367 | #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } | |
368 | ||
369 | static struct suffix_reloc_map suffix_relocs[] = | |
370 | { | |
371 | SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), | |
372 | SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), | |
373 | SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), | |
1bbb5f21 | 374 | SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel), |
28dbbc02 BW |
375 | SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC, O_tlsfunc), |
376 | SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG, O_tlsarg), | |
377 | SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL, O_tlscall), | |
378 | SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF, O_tpoff), | |
379 | SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF, O_dtpoff), | |
bbdd25a8 BW |
380 | }; |
381 | ||
43cd72b9 | 382 | |
e0001a05 NC |
383 | /* Directives. */ |
384 | ||
385 | typedef enum | |
386 | { | |
387 | directive_none = 0, | |
388 | directive_literal, | |
389 | directive_density, | |
43cd72b9 | 390 | directive_transform, |
e0001a05 NC |
391 | directive_freeregs, |
392 | directive_longcalls, | |
43cd72b9 BW |
393 | directive_literal_prefix, |
394 | directive_schedule, | |
395 | directive_absolute_literals, | |
396 | directive_last_directive | |
e0001a05 NC |
397 | } directiveE; |
398 | ||
399 | typedef struct | |
400 | { | |
401 | const char *name; | |
402 | bfd_boolean can_be_negated; | |
403 | } directive_infoS; | |
404 | ||
405 | const directive_infoS directive_info[] = | |
406 | { | |
43cd72b9 BW |
407 | { "none", FALSE }, |
408 | { "literal", FALSE }, | |
409 | { "density", TRUE }, | |
410 | { "transform", TRUE }, | |
411 | { "freeregs", FALSE }, | |
412 | { "longcalls", TRUE }, | |
413 | { "literal_prefix", FALSE }, | |
414 | { "schedule", TRUE }, | |
415 | { "absolute-literals", TRUE } | |
e0001a05 NC |
416 | }; |
417 | ||
418 | bfd_boolean directive_state[] = | |
419 | { | |
420 | FALSE, /* none */ | |
421 | FALSE, /* literal */ | |
e0001a05 | 422 | FALSE, /* density */ |
43cd72b9 | 423 | TRUE, /* transform */ |
e0001a05 NC |
424 | FALSE, /* freeregs */ |
425 | FALSE, /* longcalls */ | |
43cd72b9 | 426 | FALSE, /* literal_prefix */ |
2caa7ca0 | 427 | FALSE, /* schedule */ |
43cd72b9 | 428 | FALSE /* absolute_literals */ |
e0001a05 NC |
429 | }; |
430 | ||
b46824bd MF |
431 | /* A circular list of all potential and actual literal pool locations |
432 | in a segment. */ | |
433 | struct litpool_frag | |
434 | { | |
435 | struct litpool_frag *next; | |
436 | struct litpool_frag *prev; | |
437 | fragS *fragP; | |
438 | addressT addr; | |
439 | short priority; /* 1, 2, or 3 -- 1 is highest */ | |
440 | short original_priority; | |
441 | }; | |
442 | ||
443 | /* Map a segment to its litpool_frag list. */ | |
444 | struct litpool_seg | |
445 | { | |
446 | struct litpool_seg *next; | |
447 | asection *seg; | |
448 | struct litpool_frag frag_list; | |
449 | int frag_count; /* since last litpool location */ | |
450 | }; | |
451 | ||
452 | static struct litpool_seg litpool_seg_list; | |
453 | ||
e0001a05 NC |
454 | |
455 | /* Directive functions. */ | |
456 | ||
7fa3d080 BW |
457 | static void xtensa_begin_directive (int); |
458 | static void xtensa_end_directive (int); | |
74869ac7 | 459 | static void xtensa_literal_prefix (void); |
7fa3d080 BW |
460 | static void xtensa_literal_position (int); |
461 | static void xtensa_literal_pseudo (int); | |
462 | static void xtensa_frequency_pseudo (int); | |
463 | static void xtensa_elf_cons (int); | |
fb227da0 | 464 | static void xtensa_leb128 (int); |
e0001a05 | 465 | |
7fa3d080 | 466 | /* Parsing and Idiom Translation. */ |
e0001a05 | 467 | |
7fa3d080 | 468 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 469 | |
e0001a05 NC |
470 | /* Various Other Internal Functions. */ |
471 | ||
84b08ed9 BW |
472 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
473 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
474 | static void xtensa_mark_literal_pool_location (void); |
475 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
476 | static fragS *get_literal_pool_location (segT); | |
477 | static void set_literal_pool_location (segT, fragS *); | |
478 | static void xtensa_set_frag_assembly_state (fragS *); | |
479 | static void finish_vinsn (vliw_insn *); | |
480 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 481 | static int total_frag_text_expansion (fragS *); |
a82c7d90 DW |
482 | static bfd_boolean use_trampolines = TRUE; |
483 | static void xtensa_check_frag_count (void); | |
484 | static void xtensa_create_trampoline_frag (bfd_boolean); | |
485 | static void xtensa_maybe_create_trampoline_frag (void); | |
486 | struct trampoline_frag; | |
487 | static int init_trampoline_frag (struct trampoline_frag *); | |
b46824bd MF |
488 | static void xtensa_maybe_create_literal_pool_frag (bfd_boolean, bfd_boolean); |
489 | static bfd_boolean auto_litpools = FALSE; | |
490 | static int auto_litpool_limit = 10000; | |
e0001a05 NC |
491 | |
492 | /* Alignment Functions. */ | |
493 | ||
d77b99c9 BW |
494 | static int get_text_align_power (unsigned); |
495 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 496 | static int branch_align_power (segT); |
e0001a05 NC |
497 | |
498 | /* Helpers for xtensa_relax_frag(). */ | |
499 | ||
7fa3d080 | 500 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 501 | |
b08b5071 | 502 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 503 | |
7fa3d080 BW |
504 | static unsigned get_last_insn_flags (segT, subsegT); |
505 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
506 | static float get_subseg_total_freq (segT, subsegT); |
507 | static float get_subseg_target_freq (segT, subsegT); | |
508 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
509 | |
510 | /* Segment list functions. */ | |
511 | ||
7fa3d080 BW |
512 | static void xtensa_move_literals (void); |
513 | static void xtensa_reorder_segments (void); | |
514 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
515 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
516 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
517 | static void xtensa_restore_emit_state (emit_state *); | |
74869ac7 | 518 | static segT cache_literal_section (bfd_boolean); |
e0001a05 | 519 | |
43cd72b9 BW |
520 | /* op_placement_info functions. */ |
521 | ||
7fa3d080 BW |
522 | static void init_op_placement_info_table (void); |
523 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
524 | static int xg_get_single_size (xtensa_opcode); | |
525 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 526 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 527 | |
e0001a05 | 528 | /* TInsn and IStack functions. */ |
43cd72b9 | 529 | |
7fa3d080 BW |
530 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
531 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
532 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
533 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
534 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
535 | static void tinsn_from_chars (TInsn *, char *, int); | |
536 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
537 | static int get_num_stack_text_bytes (IStack *); | |
538 | static int get_num_stack_literal_bytes (IStack *); | |
a82c7d90 | 539 | static bfd_boolean tinsn_to_slotbuf (xtensa_format, int, TInsn *, xtensa_insnbuf); |
e0001a05 | 540 | |
43cd72b9 BW |
541 | /* vliw_insn functions. */ |
542 | ||
7fa3d080 | 543 | static void xg_init_vinsn (vliw_insn *); |
d8392fd9 | 544 | static void xg_copy_vinsn (vliw_insn *, vliw_insn *); |
7fa3d080 BW |
545 | static void xg_clear_vinsn (vliw_insn *); |
546 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
547 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 548 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
549 | (vliw_insn *, char *, fragS *, bfd_boolean); |
550 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 551 | |
e0001a05 | 552 | /* Expression Utilities. */ |
43cd72b9 | 553 | |
7fa3d080 BW |
554 | bfd_boolean expr_is_const (const expressionS *); |
555 | offsetT get_expr_const (const expressionS *); | |
556 | void set_expr_const (expressionS *, offsetT); | |
557 | bfd_boolean expr_is_register (const expressionS *); | |
558 | offsetT get_expr_register (const expressionS *); | |
559 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
560 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
561 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 562 | |
9456465c BW |
563 | /* Section renaming. */ |
564 | ||
7fa3d080 | 565 | static void build_section_rename (const char *); |
e0001a05 | 566 | |
e0001a05 NC |
567 | |
568 | /* ISA imported from bfd. */ | |
569 | extern xtensa_isa xtensa_default_isa; | |
570 | ||
571 | extern int target_big_endian; | |
572 | ||
573 | static xtensa_opcode xtensa_addi_opcode; | |
574 | static xtensa_opcode xtensa_addmi_opcode; | |
575 | static xtensa_opcode xtensa_call0_opcode; | |
576 | static xtensa_opcode xtensa_call4_opcode; | |
577 | static xtensa_opcode xtensa_call8_opcode; | |
578 | static xtensa_opcode xtensa_call12_opcode; | |
579 | static xtensa_opcode xtensa_callx0_opcode; | |
580 | static xtensa_opcode xtensa_callx4_opcode; | |
581 | static xtensa_opcode xtensa_callx8_opcode; | |
582 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 583 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 584 | static xtensa_opcode xtensa_entry_opcode; |
d12f9798 | 585 | static xtensa_opcode xtensa_extui_opcode; |
43cd72b9 BW |
586 | static xtensa_opcode xtensa_movi_opcode; |
587 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 588 | static xtensa_opcode xtensa_isync_opcode; |
19e8f41a | 589 | static xtensa_opcode xtensa_j_opcode; |
e0001a05 | 590 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 591 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
592 | static xtensa_opcode xtensa_loop_opcode; |
593 | static xtensa_opcode xtensa_loopnez_opcode; | |
594 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 595 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
596 | static xtensa_opcode xtensa_nop_n_opcode; |
597 | static xtensa_opcode xtensa_or_opcode; | |
598 | static xtensa_opcode xtensa_ret_opcode; | |
599 | static xtensa_opcode xtensa_ret_n_opcode; | |
600 | static xtensa_opcode xtensa_retw_opcode; | |
601 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 602 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 | 603 | static xtensa_opcode xtensa_waiti_opcode; |
62af60e2 | 604 | static int config_max_slots = 0; |
e0001a05 NC |
605 | |
606 | \f | |
607 | /* Command-line Options. */ | |
608 | ||
609 | bfd_boolean use_literal_section = TRUE; | |
19fc3723 | 610 | enum flix_level produce_flix = FLIX_ALL; |
e0001a05 | 611 | static bfd_boolean align_targets = TRUE; |
43cd72b9 | 612 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 613 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
614 | static bfd_boolean workaround_a0_b_retw = FALSE; |
615 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
616 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 617 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 618 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 619 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 620 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
e0001a05 | 621 | |
43cd72b9 BW |
622 | /* When workaround_short_loops is TRUE, all loops with early exits must |
623 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
624 | to the workaround_short_loop flag. In addition to the | |
625 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
626 | must have at least 3 instructions. */ | |
e0001a05 | 627 | |
43cd72b9 | 628 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 629 | |
7fa3d080 BW |
630 | |
631 | static void | |
632 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
633 | { | |
634 | if (earliest > latest) | |
635 | as_fatal (_("illegal range of target hardware versions")); | |
636 | ||
637 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
638 | if (earliest < 105000 || latest < 105000) | |
639 | { | |
640 | workaround_a0_b_retw |= TRUE; | |
641 | workaround_b_j_loop_end |= TRUE; | |
642 | workaround_short_loop |= TRUE; | |
643 | workaround_close_loop_end |= TRUE; | |
644 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 645 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
646 | } |
647 | } | |
648 | ||
649 | ||
e0001a05 NC |
650 | enum |
651 | { | |
652 | option_density = OPTION_MD_BASE, | |
653 | option_no_density, | |
654 | ||
19fc3723 SA |
655 | option_flix, |
656 | option_no_generate_flix, | |
657 | option_no_flix, | |
658 | ||
e0001a05 NC |
659 | option_relax, |
660 | option_no_relax, | |
661 | ||
43cd72b9 BW |
662 | option_link_relax, |
663 | option_no_link_relax, | |
664 | ||
e0001a05 NC |
665 | option_generics, |
666 | option_no_generics, | |
667 | ||
43cd72b9 BW |
668 | option_transform, |
669 | option_no_transform, | |
670 | ||
e0001a05 NC |
671 | option_text_section_literals, |
672 | option_no_text_section_literals, | |
673 | ||
43cd72b9 BW |
674 | option_absolute_literals, |
675 | option_no_absolute_literals, | |
676 | ||
e0001a05 NC |
677 | option_align_targets, |
678 | option_no_align_targets, | |
679 | ||
43cd72b9 | 680 | option_warn_unaligned_targets, |
e0001a05 NC |
681 | |
682 | option_longcalls, | |
683 | option_no_longcalls, | |
684 | ||
685 | option_workaround_a0_b_retw, | |
686 | option_no_workaround_a0_b_retw, | |
687 | ||
688 | option_workaround_b_j_loop_end, | |
689 | option_no_workaround_b_j_loop_end, | |
690 | ||
691 | option_workaround_short_loop, | |
692 | option_no_workaround_short_loop, | |
693 | ||
694 | option_workaround_all_short_loops, | |
695 | option_no_workaround_all_short_loops, | |
696 | ||
697 | option_workaround_close_loop_end, | |
698 | option_no_workaround_close_loop_end, | |
699 | ||
700 | option_no_workarounds, | |
701 | ||
e0001a05 | 702 | option_rename_section_name, |
e0001a05 | 703 | |
43cd72b9 BW |
704 | option_prefer_l32r, |
705 | option_prefer_const16, | |
706 | ||
a82c7d90 DW |
707 | option_target_hardware, |
708 | ||
709 | option_trampolines, | |
710 | option_no_trampolines, | |
b46824bd MF |
711 | |
712 | option_auto_litpools, | |
713 | option_no_auto_litpools, | |
714 | option_auto_litpool_limit, | |
e0001a05 NC |
715 | }; |
716 | ||
717 | const char *md_shortopts = ""; | |
718 | ||
719 | struct option md_longopts[] = | |
720 | { | |
43cd72b9 BW |
721 | { "density", no_argument, NULL, option_density }, |
722 | { "no-density", no_argument, NULL, option_no_density }, | |
723 | ||
19fc3723 SA |
724 | { "flix", no_argument, NULL, option_flix }, |
725 | { "no-generate-flix", no_argument, NULL, option_no_generate_flix }, | |
726 | { "no-allow-flix", no_argument, NULL, option_no_flix }, | |
727 | ||
43cd72b9 BW |
728 | /* Both "relax" and "generics" are deprecated and treated as equivalent |
729 | to the "transform" option. */ | |
730 | { "relax", no_argument, NULL, option_relax }, | |
731 | { "no-relax", no_argument, NULL, option_no_relax }, | |
732 | { "generics", no_argument, NULL, option_generics }, | |
733 | { "no-generics", no_argument, NULL, option_no_generics }, | |
734 | ||
735 | { "transform", no_argument, NULL, option_transform }, | |
736 | { "no-transform", no_argument, NULL, option_no_transform }, | |
737 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
738 | { "no-text-section-literals", no_argument, NULL, | |
739 | option_no_text_section_literals }, | |
740 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
741 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
742 | /* This option was changed from -align-target to -target-align |
743 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 744 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
745 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
746 | { "warn-unaligned-targets", no_argument, NULL, | |
747 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
748 | { "longcalls", no_argument, NULL, option_longcalls }, |
749 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
750 | ||
751 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
752 | option_no_workaround_a0_b_retw }, | |
753 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 754 | |
43cd72b9 BW |
755 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
756 | option_no_workaround_b_j_loop_end }, | |
757 | { "workaround-b-j-loop-end", no_argument, NULL, | |
758 | option_workaround_b_j_loop_end }, | |
e0001a05 | 759 | |
43cd72b9 BW |
760 | { "no-workaround-short-loops", no_argument, NULL, |
761 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
762 | { "workaround-short-loops", no_argument, NULL, |
763 | option_workaround_short_loop }, | |
e0001a05 | 764 | |
43cd72b9 BW |
765 | { "no-workaround-all-short-loops", no_argument, NULL, |
766 | option_no_workaround_all_short_loops }, | |
767 | { "workaround-all-short-loop", no_argument, NULL, | |
768 | option_workaround_all_short_loops }, | |
769 | ||
770 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
771 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
772 | ||
773 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
774 | ||
775 | { "no-workaround-close-loop-end", no_argument, NULL, | |
776 | option_no_workaround_close_loop_end }, | |
777 | { "workaround-close-loop-end", no_argument, NULL, | |
778 | option_workaround_close_loop_end }, | |
e0001a05 | 779 | |
7fa3d080 | 780 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 781 | |
43cd72b9 BW |
782 | { "link-relax", no_argument, NULL, option_link_relax }, |
783 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
784 | ||
785 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
786 | ||
a82c7d90 DW |
787 | { "trampolines", no_argument, NULL, option_trampolines }, |
788 | { "no-trampolines", no_argument, NULL, option_no_trampolines }, | |
789 | ||
b46824bd MF |
790 | { "auto-litpools", no_argument, NULL, option_auto_litpools }, |
791 | { "no-auto-litpools", no_argument, NULL, option_no_auto_litpools }, | |
792 | { "auto-litpool-limit", required_argument, NULL, option_auto_litpool_limit }, | |
793 | ||
43cd72b9 | 794 | { NULL, no_argument, NULL, 0 } |
e0001a05 NC |
795 | }; |
796 | ||
797 | size_t md_longopts_size = sizeof md_longopts; | |
798 | ||
799 | ||
800 | int | |
17b9d67d | 801 | md_parse_option (int c, const char *arg) |
e0001a05 NC |
802 | { |
803 | switch (c) | |
804 | { | |
805 | case option_density: | |
43cd72b9 | 806 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
807 | return 1; |
808 | case option_no_density: | |
43cd72b9 | 809 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 810 | return 1; |
43cd72b9 BW |
811 | case option_link_relax: |
812 | linkrelax = 1; | |
e0001a05 | 813 | return 1; |
43cd72b9 BW |
814 | case option_no_link_relax: |
815 | linkrelax = 0; | |
e0001a05 | 816 | return 1; |
19fc3723 SA |
817 | case option_flix: |
818 | produce_flix = FLIX_ALL; | |
819 | return 1; | |
820 | case option_no_generate_flix: | |
821 | produce_flix = FLIX_NO_GENERATE; | |
822 | return 1; | |
823 | case option_no_flix: | |
824 | produce_flix = FLIX_NONE; | |
825 | return 1; | |
43cd72b9 BW |
826 | case option_generics: |
827 | as_warn (_("--generics is deprecated; use --transform instead")); | |
828 | return md_parse_option (option_transform, arg); | |
829 | case option_no_generics: | |
830 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
831 | return md_parse_option (option_no_transform, arg); | |
832 | case option_relax: | |
833 | as_warn (_("--relax is deprecated; use --transform instead")); | |
834 | return md_parse_option (option_transform, arg); | |
835 | case option_no_relax: | |
836 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
837 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
838 | case option_longcalls: |
839 | directive_state[directive_longcalls] = TRUE; | |
840 | return 1; | |
841 | case option_no_longcalls: | |
842 | directive_state[directive_longcalls] = FALSE; | |
843 | return 1; | |
844 | case option_text_section_literals: | |
845 | use_literal_section = FALSE; | |
846 | return 1; | |
847 | case option_no_text_section_literals: | |
848 | use_literal_section = TRUE; | |
849 | return 1; | |
43cd72b9 BW |
850 | case option_absolute_literals: |
851 | if (!absolute_literals_supported) | |
852 | { | |
853 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
854 | return 0; | |
855 | } | |
856 | directive_state[directive_absolute_literals] = TRUE; | |
857 | return 1; | |
858 | case option_no_absolute_literals: | |
859 | directive_state[directive_absolute_literals] = FALSE; | |
860 | return 1; | |
861 | ||
e0001a05 NC |
862 | case option_workaround_a0_b_retw: |
863 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
864 | return 1; |
865 | case option_no_workaround_a0_b_retw: | |
866 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
867 | return 1; |
868 | case option_workaround_b_j_loop_end: | |
869 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
870 | return 1; |
871 | case option_no_workaround_b_j_loop_end: | |
872 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
873 | return 1; |
874 | ||
875 | case option_workaround_short_loop: | |
876 | workaround_short_loop = TRUE; | |
e0001a05 NC |
877 | return 1; |
878 | case option_no_workaround_short_loop: | |
879 | workaround_short_loop = FALSE; | |
e0001a05 NC |
880 | return 1; |
881 | ||
882 | case option_workaround_all_short_loops: | |
883 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
884 | return 1; |
885 | case option_no_workaround_all_short_loops: | |
886 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
887 | return 1; |
888 | ||
889 | case option_workaround_close_loop_end: | |
890 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
891 | return 1; |
892 | case option_no_workaround_close_loop_end: | |
893 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
894 | return 1; |
895 | ||
896 | case option_no_workarounds: | |
897 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 898 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 899 | workaround_short_loop = FALSE; |
e0001a05 | 900 | workaround_all_short_loops = FALSE; |
e0001a05 | 901 | workaround_close_loop_end = FALSE; |
e0001a05 | 902 | return 1; |
43cd72b9 | 903 | |
e0001a05 NC |
904 | case option_align_targets: |
905 | align_targets = TRUE; | |
906 | return 1; | |
907 | case option_no_align_targets: | |
908 | align_targets = FALSE; | |
909 | return 1; | |
910 | ||
43cd72b9 BW |
911 | case option_warn_unaligned_targets: |
912 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
913 | return 1; |
914 | ||
e0001a05 NC |
915 | case option_rename_section_name: |
916 | build_section_rename (arg); | |
917 | return 1; | |
e0001a05 NC |
918 | |
919 | case 'Q': | |
920 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
921 | should be emitted or not. FIXME: Not implemented. */ | |
922 | return 1; | |
c138bc38 | 923 | |
43cd72b9 BW |
924 | case option_prefer_l32r: |
925 | if (prefer_const16) | |
926 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
927 | prefer_l32r = 1; | |
928 | return 1; | |
929 | ||
930 | case option_prefer_const16: | |
931 | if (prefer_l32r) | |
932 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
933 | prefer_const16 = 1; | |
934 | return 1; | |
935 | ||
c138bc38 | 936 | case option_target_hardware: |
43cd72b9 BW |
937 | { |
938 | int earliest, latest = 0; | |
17b9d67d | 939 | char *end; |
43cd72b9 BW |
940 | if (*arg == 0 || *arg == '-') |
941 | as_fatal (_("invalid target hardware version")); | |
942 | ||
17b9d67d | 943 | earliest = strtol (arg, &end, 0); |
43cd72b9 | 944 | |
17b9d67d | 945 | if (*end == 0) |
43cd72b9 | 946 | latest = earliest; |
17b9d67d | 947 | else if (*end == '-') |
43cd72b9 | 948 | { |
17b9d67d | 949 | if (*++end == 0) |
43cd72b9 | 950 | as_fatal (_("invalid target hardware version")); |
17b9d67d | 951 | latest = strtol (end, &end, 0); |
43cd72b9 | 952 | } |
17b9d67d | 953 | if (*end != 0) |
43cd72b9 BW |
954 | as_fatal (_("invalid target hardware version")); |
955 | ||
956 | xtensa_setup_hw_workarounds (earliest, latest); | |
957 | return 1; | |
958 | } | |
959 | ||
960 | case option_transform: | |
961 | /* This option has no affect other than to use the defaults, | |
962 | which are already set. */ | |
963 | return 1; | |
964 | ||
965 | case option_no_transform: | |
966 | /* This option turns off all transformations of any kind. | |
967 | However, because we want to preserve the state of other | |
968 | directives, we only change its own field. Thus, before | |
969 | you perform any transformation, always check if transform | |
970 | is available. If you use the functions we provide for this | |
971 | purpose, you will be ok. */ | |
972 | directive_state[directive_transform] = FALSE; | |
973 | return 1; | |
974 | ||
a82c7d90 DW |
975 | case option_trampolines: |
976 | use_trampolines = TRUE; | |
977 | return 1; | |
978 | ||
979 | case option_no_trampolines: | |
980 | use_trampolines = FALSE; | |
981 | return 1; | |
982 | ||
b46824bd MF |
983 | case option_auto_litpools: |
984 | auto_litpools = TRUE; | |
985 | use_literal_section = FALSE; | |
986 | return 1; | |
987 | ||
988 | case option_no_auto_litpools: | |
989 | auto_litpools = FALSE; | |
990 | auto_litpool_limit = -1; | |
991 | return 1; | |
992 | ||
993 | case option_auto_litpool_limit: | |
994 | { | |
995 | int value = 0; | |
17b9d67d | 996 | char *end; |
b46824bd MF |
997 | if (auto_litpool_limit < 0) |
998 | as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit")); | |
999 | if (*arg == 0 || *arg == '-') | |
1000 | as_fatal (_("invalid auto-litpool-limit argument")); | |
17b9d67d TS |
1001 | value = strtol (arg, &end, 10); |
1002 | if (*end != 0) | |
b46824bd MF |
1003 | as_fatal (_("invalid auto-litpool-limit argument")); |
1004 | if (value < 100 || value > 10000) | |
1005 | as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)")); | |
1006 | auto_litpool_limit = value; | |
1007 | auto_litpools = TRUE; | |
1008 | use_literal_section = FALSE; | |
1009 | return 1; | |
1010 | } | |
1011 | ||
e0001a05 NC |
1012 | default: |
1013 | return 0; | |
1014 | } | |
1015 | } | |
1016 | ||
1017 | ||
1018 | void | |
7fa3d080 | 1019 | md_show_usage (FILE *stream) |
e0001a05 | 1020 | { |
43cd72b9 BW |
1021 | fputs ("\n\ |
1022 | Xtensa options:\n\ | |
9456465c BW |
1023 | --[no-]text-section-literals\n\ |
1024 | [Do not] put literals in the text section\n\ | |
1025 | --[no-]absolute-literals\n\ | |
1026 | [Do not] default to use non-PC-relative literals\n\ | |
1027 | --[no-]target-align [Do not] try to align branch targets\n\ | |
1028 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
1029 | --[no-]transform [Do not] transform instructions\n\ | |
19fc3723 SA |
1030 | --flix both allow hand-written and generate flix bundles\n\ |
1031 | --no-generate-flix allow hand-written but do not generate\n\ | |
1032 | flix bundles\n\ | |
1033 | --no-allow-flix neither allow hand-written nor generate\n\ | |
1034 | flix bundles\n\ | |
a82c7d90 DW |
1035 | --rename-section old=new Rename section 'old' to 'new'\n\ |
1036 | --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\ | |
b46824bd MF |
1037 | when jumps do not reach their targets\n\ |
1038 | --[no-]auto-litpools [Do not] automatically create literal pools\n\ | |
1039 | --auto-litpool-limit=<value>\n\ | |
1040 | (range 100-10000) Maximum number of blocks of\n\ | |
1041 | instructions to emit between literal pool\n\ | |
1042 | locations; implies --auto-litpools flag\n", stream); | |
e0001a05 NC |
1043 | } |
1044 | ||
7fa3d080 BW |
1045 | \f |
1046 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
1047 | |
1048 | static void | |
7fa3d080 | 1049 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 1050 | { |
7fa3d080 | 1051 | sym_list *l; |
43cd72b9 | 1052 | |
7fa3d080 | 1053 | if (!free_insn_labels) |
325801bd | 1054 | l = XNEW (sym_list); |
7fa3d080 | 1055 | else |
43cd72b9 | 1056 | { |
7fa3d080 BW |
1057 | l = free_insn_labels; |
1058 | free_insn_labels = l->next; | |
1059 | } | |
1060 | ||
1061 | l->sym = sym; | |
1062 | l->next = insn_labels; | |
1063 | insn_labels = l; | |
1064 | } | |
1065 | ||
1066 | ||
1067 | static void | |
1068 | xtensa_clear_insn_labels (void) | |
1069 | { | |
1070 | sym_list **pl; | |
1071 | ||
1072 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1073 | ; | |
1074 | *pl = insn_labels; | |
1075 | insn_labels = NULL; | |
1076 | } | |
1077 | ||
1078 | ||
7fa3d080 | 1079 | static void |
c3ea6048 | 1080 | xtensa_move_labels (fragS *new_frag, valueT new_offset) |
7fa3d080 BW |
1081 | { |
1082 | sym_list *lit; | |
1083 | ||
1084 | for (lit = insn_labels; lit; lit = lit->next) | |
1085 | { | |
1086 | symbolS *lit_sym = lit->sym; | |
c3ea6048 BW |
1087 | S_SET_VALUE (lit_sym, new_offset); |
1088 | symbol_set_frag (lit_sym, new_frag); | |
43cd72b9 BW |
1089 | } |
1090 | } | |
1091 | ||
e0001a05 NC |
1092 | \f |
1093 | /* Directive data and functions. */ | |
1094 | ||
1095 | typedef struct state_stackS_struct | |
1096 | { | |
1097 | directiveE directive; | |
1098 | bfd_boolean negated; | |
1099 | bfd_boolean old_state; | |
1100 | const char *file; | |
1101 | unsigned int line; | |
1102 | const void *datum; | |
1103 | struct state_stackS_struct *prev; | |
1104 | } state_stackS; | |
1105 | ||
1106 | state_stackS *directive_state_stack; | |
1107 | ||
1108 | const pseudo_typeS md_pseudo_table[] = | |
1109 | { | |
43cd72b9 BW |
1110 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1111 | { "literal_position", xtensa_literal_position, 0 }, | |
1112 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1113 | { "long", xtensa_elf_cons, 4 }, | |
1114 | { "word", xtensa_elf_cons, 4 }, | |
1bbb5f21 | 1115 | { "4byte", xtensa_elf_cons, 4 }, |
43cd72b9 | 1116 | { "short", xtensa_elf_cons, 2 }, |
1bbb5f21 | 1117 | { "2byte", xtensa_elf_cons, 2 }, |
fb227da0 BW |
1118 | { "sleb128", xtensa_leb128, 1}, |
1119 | { "uleb128", xtensa_leb128, 0}, | |
43cd72b9 BW |
1120 | { "begin", xtensa_begin_directive, 0 }, |
1121 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1122 | { "literal", xtensa_literal_pseudo, 0 }, |
1123 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1124 | { NULL, 0, 0 }, | |
e0001a05 NC |
1125 | }; |
1126 | ||
1127 | ||
7fa3d080 BW |
1128 | static bfd_boolean |
1129 | use_transform (void) | |
e0001a05 | 1130 | { |
43cd72b9 BW |
1131 | /* After md_end, you should be checking frag by frag, rather |
1132 | than state directives. */ | |
9c2799c2 | 1133 | gas_assert (!past_xtensa_end); |
43cd72b9 | 1134 | return directive_state[directive_transform]; |
e0001a05 NC |
1135 | } |
1136 | ||
1137 | ||
7fa3d080 BW |
1138 | static bfd_boolean |
1139 | do_align_targets (void) | |
e0001a05 | 1140 | { |
7b1cc377 BW |
1141 | /* Do not use this function after md_end; just look at align_targets |
1142 | instead. There is no target-align directive, so alignment is either | |
1143 | enabled for all frags or not done at all. */ | |
9c2799c2 | 1144 | gas_assert (!past_xtensa_end); |
43cd72b9 | 1145 | return align_targets && use_transform (); |
e0001a05 NC |
1146 | } |
1147 | ||
1148 | ||
1149 | static void | |
7fa3d080 | 1150 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 | 1151 | { |
3b4dbbbf | 1152 | const char *file; |
e0001a05 | 1153 | unsigned int line; |
325801bd | 1154 | state_stackS *stack = XNEW (state_stackS); |
e0001a05 | 1155 | |
3b4dbbbf | 1156 | file = as_where (&line); |
e0001a05 NC |
1157 | |
1158 | stack->directive = directive; | |
1159 | stack->negated = negated; | |
1160 | stack->old_state = directive_state[directive]; | |
1161 | stack->file = file; | |
1162 | stack->line = line; | |
1163 | stack->datum = datum; | |
1164 | stack->prev = directive_state_stack; | |
1165 | directive_state_stack = stack; | |
1166 | ||
1167 | directive_state[directive] = !negated; | |
1168 | } | |
1169 | ||
7fa3d080 | 1170 | |
e0001a05 | 1171 | static void |
7fa3d080 BW |
1172 | directive_pop (directiveE *directive, |
1173 | bfd_boolean *negated, | |
1174 | const char **file, | |
1175 | unsigned int *line, | |
1176 | const void **datum) | |
e0001a05 NC |
1177 | { |
1178 | state_stackS *top = directive_state_stack; | |
1179 | ||
1180 | if (!directive_state_stack) | |
1181 | { | |
33eaf5de | 1182 | as_bad (_("unmatched .end directive")); |
e0001a05 NC |
1183 | *directive = directive_none; |
1184 | return; | |
1185 | } | |
1186 | ||
1187 | directive_state[directive_state_stack->directive] = top->old_state; | |
1188 | *directive = top->directive; | |
1189 | *negated = top->negated; | |
1190 | *file = top->file; | |
1191 | *line = top->line; | |
1192 | *datum = top->datum; | |
1193 | directive_state_stack = top->prev; | |
1194 | free (top); | |
1195 | } | |
1196 | ||
1197 | ||
1198 | static void | |
7fa3d080 | 1199 | directive_balance (void) |
e0001a05 NC |
1200 | { |
1201 | while (directive_state_stack) | |
1202 | { | |
1203 | directiveE directive; | |
1204 | bfd_boolean negated; | |
1205 | const char *file; | |
1206 | unsigned int line; | |
1207 | const void *datum; | |
1208 | ||
1209 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1210 | as_warn_where ((char *) file, line, | |
1211 | _(".begin directive with no matching .end directive")); | |
1212 | } | |
1213 | } | |
1214 | ||
1215 | ||
1216 | static bfd_boolean | |
7fa3d080 | 1217 | inside_directive (directiveE dir) |
e0001a05 NC |
1218 | { |
1219 | state_stackS *top = directive_state_stack; | |
1220 | ||
1221 | while (top && top->directive != dir) | |
1222 | top = top->prev; | |
1223 | ||
1224 | return (top != NULL); | |
1225 | } | |
1226 | ||
1227 | ||
1228 | static void | |
7fa3d080 | 1229 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1230 | { |
1231 | int len; | |
1232 | unsigned i; | |
b9bb4a93 | 1233 | const char *directive_string; |
e0001a05 NC |
1234 | |
1235 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1236 | *negated = FALSE; | |
1237 | else | |
1238 | { | |
1239 | *negated = TRUE; | |
1240 | input_line_pointer += 3; | |
1241 | } | |
1242 | ||
1243 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1244 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1245 | ||
1246 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1247 | equivalent to .begin [no-]transform. We should remove it when | |
1248 | we stop accepting those options. */ | |
c138bc38 | 1249 | |
43cd72b9 BW |
1250 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1251 | { | |
1252 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1253 | directive_string = "transform"; | |
1254 | } | |
1255 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1256 | { | |
1257 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1258 | directive_string = "transform"; | |
c138bc38 | 1259 | } |
43cd72b9 BW |
1260 | else |
1261 | directive_string = input_line_pointer; | |
e0001a05 NC |
1262 | |
1263 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1264 | { | |
43cd72b9 | 1265 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1266 | { |
1267 | input_line_pointer += len; | |
1268 | *directive = (directiveE) i; | |
1269 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1270 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1271 | directive_info[i].name); |
1272 | return; | |
1273 | } | |
1274 | } | |
1275 | ||
1276 | as_bad (_("unknown directive")); | |
1277 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1278 | } | |
1279 | ||
1280 | ||
1281 | static void | |
7fa3d080 | 1282 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1283 | { |
1284 | directiveE directive; | |
1285 | bfd_boolean negated; | |
1286 | emit_state *state; | |
e0001a05 NC |
1287 | lit_state *ls; |
1288 | ||
1289 | get_directive (&directive, &negated); | |
1290 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1291 | { | |
1292 | discard_rest_of_line (); | |
1293 | return; | |
1294 | } | |
1295 | ||
43cd72b9 BW |
1296 | if (cur_vinsn.inside_bundle) |
1297 | as_bad (_("directives are not valid inside bundles")); | |
1298 | ||
e0001a05 NC |
1299 | switch (directive) |
1300 | { | |
1301 | case directive_literal: | |
82e7541d BW |
1302 | if (!inside_directive (directive_literal)) |
1303 | { | |
1304 | /* Previous labels go with whatever follows this directive, not with | |
1305 | the literal, so save them now. */ | |
1306 | saved_insn_labels = insn_labels; | |
1307 | insn_labels = NULL; | |
1308 | } | |
43cd72b9 | 1309 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
325801bd | 1310 | state = XNEW (emit_state); |
e0001a05 NC |
1311 | xtensa_switch_to_literal_fragment (state); |
1312 | directive_push (directive_literal, negated, state); | |
1313 | break; | |
1314 | ||
1315 | case directive_literal_prefix: | |
c138bc38 | 1316 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1317 | might produce a literal. */ |
1318 | md_flush_pending_output (); | |
e0001a05 NC |
1319 | /* Check to see if the current fragment is a literal |
1320 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1321 | if (generating_literals) |
e0001a05 NC |
1322 | { |
1323 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1324 | return; | |
1325 | } | |
1326 | ||
1327 | /* Allocate the literal state for this section and push | |
1328 | onto the directive stack. */ | |
325801bd | 1329 | ls = XNEW (lit_state); |
9c2799c2 | 1330 | gas_assert (ls); |
e0001a05 NC |
1331 | |
1332 | *ls = default_lit_sections; | |
e0001a05 NC |
1333 | directive_push (directive_literal_prefix, negated, ls); |
1334 | ||
e0001a05 | 1335 | /* Process the new prefix. */ |
74869ac7 | 1336 | xtensa_literal_prefix (); |
e0001a05 NC |
1337 | break; |
1338 | ||
1339 | case directive_freeregs: | |
1340 | /* This information is currently unused, but we'll accept the statement | |
1341 | and just discard the rest of the line. This won't check the syntax, | |
1342 | but it will accept every correct freeregs directive. */ | |
1343 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1344 | directive_push (directive_freeregs, negated, 0); | |
1345 | break; | |
1346 | ||
43cd72b9 BW |
1347 | case directive_schedule: |
1348 | md_flush_pending_output (); | |
1349 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1350 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1351 | directive_push (directive_schedule, negated, 0); | |
1352 | xtensa_set_frag_assembly_state (frag_now); | |
1353 | break; | |
1354 | ||
e0001a05 | 1355 | case directive_density: |
43cd72b9 BW |
1356 | as_warn (_(".begin [no-]density is ignored")); |
1357 | break; | |
1358 | ||
1359 | case directive_absolute_literals: | |
1360 | md_flush_pending_output (); | |
1361 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1362 | { |
43cd72b9 | 1363 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1364 | break; |
1365 | } | |
43cd72b9 BW |
1366 | xtensa_set_frag_assembly_state (frag_now); |
1367 | directive_push (directive, negated, 0); | |
1368 | break; | |
e0001a05 NC |
1369 | |
1370 | default: | |
43cd72b9 BW |
1371 | md_flush_pending_output (); |
1372 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1373 | directive_push (directive, negated, 0); |
1374 | break; | |
1375 | } | |
1376 | ||
1377 | demand_empty_rest_of_line (); | |
1378 | } | |
1379 | ||
1380 | ||
1381 | static void | |
7fa3d080 | 1382 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1383 | { |
1384 | directiveE begin_directive, end_directive; | |
1385 | bfd_boolean begin_negated, end_negated; | |
1386 | const char *file; | |
1387 | unsigned int line; | |
1388 | emit_state *state; | |
43cd72b9 | 1389 | emit_state **state_ptr; |
e0001a05 NC |
1390 | lit_state *s; |
1391 | ||
43cd72b9 BW |
1392 | if (cur_vinsn.inside_bundle) |
1393 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1394 | |
e0001a05 | 1395 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1396 | |
1397 | md_flush_pending_output (); | |
1398 | ||
87975d2a | 1399 | switch ((int) end_directive) |
e0001a05 | 1400 | { |
87975d2a | 1401 | case XTENSA_UNDEFINED: |
e0001a05 NC |
1402 | discard_rest_of_line (); |
1403 | return; | |
e0001a05 | 1404 | |
87975d2a | 1405 | case (int) directive_density: |
43cd72b9 | 1406 | as_warn (_(".end [no-]density is ignored")); |
e0001a05 | 1407 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1408 | break; |
1409 | ||
87975d2a | 1410 | case (int) directive_absolute_literals: |
43cd72b9 BW |
1411 | if (!absolute_literals_supported && !end_negated) |
1412 | { | |
1413 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1414 | demand_empty_rest_of_line (); | |
1415 | return; | |
1416 | } | |
1417 | break; | |
1418 | ||
1419 | default: | |
1420 | break; | |
e0001a05 NC |
1421 | } |
1422 | ||
43cd72b9 | 1423 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1424 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1425 | (const void **) state_ptr); |
e0001a05 NC |
1426 | |
1427 | if (begin_directive != directive_none) | |
1428 | { | |
1429 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1430 | { | |
1431 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1432 | begin_negated ? "no-" : "", | |
1433 | directive_info[begin_directive].name, file, line); | |
1434 | } | |
1435 | else | |
1436 | { | |
1437 | switch (end_directive) | |
1438 | { | |
1439 | case directive_literal: | |
1440 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1441 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1442 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1443 | free (state); |
82e7541d BW |
1444 | if (!inside_directive (directive_literal)) |
1445 | { | |
1446 | /* Restore the list of current labels. */ | |
1447 | xtensa_clear_insn_labels (); | |
1448 | insn_labels = saved_insn_labels; | |
1449 | } | |
e0001a05 NC |
1450 | break; |
1451 | ||
e0001a05 NC |
1452 | case directive_literal_prefix: |
1453 | /* Restore the default collection sections from saved state. */ | |
1454 | s = (lit_state *) state; | |
9c2799c2 | 1455 | gas_assert (s); |
e8247da7 | 1456 | default_lit_sections = *s; |
e0001a05 | 1457 | |
74869ac7 BW |
1458 | /* Free the state storage. */ |
1459 | free (s->lit_prefix); | |
e0001a05 NC |
1460 | free (s); |
1461 | break; | |
1462 | ||
43cd72b9 BW |
1463 | case directive_schedule: |
1464 | case directive_freeregs: | |
1465 | break; | |
1466 | ||
e0001a05 | 1467 | default: |
43cd72b9 | 1468 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1469 | break; |
1470 | } | |
1471 | } | |
1472 | } | |
1473 | ||
1474 | demand_empty_rest_of_line (); | |
1475 | } | |
1476 | ||
1477 | ||
1478 | /* Place an aligned literal fragment at the current location. */ | |
1479 | ||
1480 | static void | |
7fa3d080 | 1481 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1482 | { |
43cd72b9 BW |
1483 | md_flush_pending_output (); |
1484 | ||
e0001a05 NC |
1485 | if (inside_directive (directive_literal)) |
1486 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1487 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1488 | |
1489 | demand_empty_rest_of_line (); | |
82e7541d | 1490 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1491 | } |
1492 | ||
1493 | ||
43cd72b9 | 1494 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1495 | |
1496 | static void | |
7fa3d080 | 1497 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1498 | { |
1499 | emit_state state; | |
1745fcba | 1500 | char *p, *base_name; |
e0001a05 | 1501 | char c; |
e0001a05 NC |
1502 | segT dest_seg; |
1503 | ||
82e7541d BW |
1504 | if (inside_directive (directive_literal)) |
1505 | { | |
1506 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1507 | ignore_rest_of_line (); | |
1508 | return; | |
1509 | } | |
1510 | ||
43cd72b9 BW |
1511 | md_flush_pending_output (); |
1512 | ||
82e7541d BW |
1513 | /* Previous labels go with whatever follows this directive, not with |
1514 | the literal, so save them now. */ | |
1515 | saved_insn_labels = insn_labels; | |
1516 | insn_labels = NULL; | |
1517 | ||
e0001a05 NC |
1518 | /* If we are using text-section literals, then this is the right value... */ |
1519 | dest_seg = now_seg; | |
1520 | ||
1521 | base_name = input_line_pointer; | |
1522 | ||
1523 | xtensa_switch_to_literal_fragment (&state); | |
1524 | ||
43cd72b9 | 1525 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1526 | need to put them in the section we just switched to. */ |
43cd72b9 | 1527 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1528 | dest_seg = now_seg; |
1529 | ||
87975d2a AM |
1530 | /* FIXME, despite the previous comments, dest_seg is unused... */ |
1531 | (void) dest_seg; | |
1532 | ||
43cd72b9 BW |
1533 | /* All literals are aligned to four-byte boundaries. */ |
1534 | frag_align (2, 0, 0); | |
1535 | record_alignment (now_seg, 2); | |
e0001a05 | 1536 | |
d02603dc | 1537 | c = get_symbol_name (&base_name); |
e0001a05 NC |
1538 | /* Just after name is now '\0'. */ |
1539 | p = input_line_pointer; | |
1540 | *p = c; | |
d02603dc | 1541 | SKIP_WHITESPACE_AFTER_NAME (); |
e0001a05 NC |
1542 | |
1543 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1544 | { | |
1545 | as_bad (_("expected comma or colon after symbol name; " | |
1546 | "rest of line ignored")); | |
1547 | ignore_rest_of_line (); | |
1548 | xtensa_restore_emit_state (&state); | |
1549 | return; | |
1550 | } | |
e0001a05 | 1551 | |
d02603dc | 1552 | *p = 0; |
e0001a05 | 1553 | colon (base_name); |
e0001a05 | 1554 | *p = c; |
d02603dc | 1555 | |
43cd72b9 | 1556 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1557 | |
43cd72b9 | 1558 | xtensa_elf_cons (4); |
e0001a05 NC |
1559 | |
1560 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1561 | |
1562 | /* Restore the list of current labels. */ | |
1563 | xtensa_clear_insn_labels (); | |
1564 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1565 | } |
1566 | ||
1567 | ||
1568 | static void | |
74869ac7 | 1569 | xtensa_literal_prefix (void) |
e0001a05 | 1570 | { |
74869ac7 BW |
1571 | char *name; |
1572 | int len; | |
1573 | ||
1574 | /* Parse the new prefix from the input_line_pointer. */ | |
1575 | SKIP_WHITESPACE (); | |
1576 | len = strspn (input_line_pointer, | |
1577 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1578 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
e0001a05 NC |
1579 | |
1580 | /* Get a null-terminated copy of the name. */ | |
29a2809e | 1581 | name = xmemdup0 (input_line_pointer, len); |
e0001a05 | 1582 | |
74869ac7 BW |
1583 | /* Skip the name in the input line. */ |
1584 | input_line_pointer += len; | |
43cd72b9 | 1585 | |
74869ac7 | 1586 | default_lit_sections.lit_prefix = name; |
43cd72b9 | 1587 | |
74869ac7 | 1588 | /* Clear cached literal sections, since the prefix has changed. */ |
43cd72b9 BW |
1589 | default_lit_sections.lit_seg = NULL; |
1590 | default_lit_sections.lit4_seg = NULL; | |
43cd72b9 BW |
1591 | } |
1592 | ||
1593 | ||
1594 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1595 | ||
1596 | static void | |
7fa3d080 | 1597 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1598 | { |
1599 | float fall_through_f, target_f; | |
43cd72b9 BW |
1600 | |
1601 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1602 | if (fall_through_f < 0) | |
1603 | { | |
1604 | as_bad (_("fall through frequency must be greater than 0")); | |
1605 | ignore_rest_of_line (); | |
1606 | return; | |
1607 | } | |
1608 | ||
1609 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1610 | if (target_f < 0) | |
1611 | { | |
1612 | as_bad (_("branch target frequency must be greater than 0")); | |
1613 | ignore_rest_of_line (); | |
1614 | return; | |
1615 | } | |
1616 | ||
b08b5071 | 1617 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1618 | |
1619 | demand_empty_rest_of_line (); | |
1620 | } | |
1621 | ||
1622 | ||
1623 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1624 | Clobbers input_line_pointer, checks end-of-line. */ | |
1625 | ||
1626 | static void | |
7fa3d080 | 1627 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1628 | { |
1629 | expressionS exp; | |
1630 | bfd_reloc_code_real_type reloc; | |
1631 | ||
1632 | md_flush_pending_output (); | |
1633 | ||
1634 | if (cur_vinsn.inside_bundle) | |
1635 | as_bad (_("directives are not valid inside bundles")); | |
1636 | ||
1637 | if (is_it_end_of_statement ()) | |
1638 | { | |
1639 | demand_empty_rest_of_line (); | |
1640 | return; | |
1641 | } | |
1642 | ||
1643 | do | |
1644 | { | |
1645 | expression (&exp); | |
1646 | if (exp.X_op == O_symbol | |
1647 | && *input_line_pointer == '@' | |
1648 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1649 | != BFD_RELOC_NONE)) | |
1650 | { | |
1651 | reloc_howto_type *reloc_howto = | |
1652 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1653 | ||
1654 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1655 | as_bad (_("unsupported relocation")); | |
1656 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1657 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1658 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1659 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1660 | as_bad (_("opcode-specific %s relocation used outside " | |
1661 | "an instruction"), reloc_howto->name); | |
1662 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
992a06ee AM |
1663 | as_bad (ngettext ("%s relocations do not fit in %d byte", |
1664 | "%s relocations do not fit in %d bytes", | |
1665 | nbytes), | |
43cd72b9 | 1666 | reloc_howto->name, nbytes); |
28dbbc02 BW |
1667 | else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC |
1668 | || reloc == BFD_RELOC_XTENSA_TLS_ARG | |
1669 | || reloc == BFD_RELOC_XTENSA_TLS_CALL) | |
1670 | as_bad (_("invalid use of %s relocation"), reloc_howto->name); | |
43cd72b9 BW |
1671 | else |
1672 | { | |
1673 | char *p = frag_more ((int) nbytes); | |
1674 | xtensa_set_frag_assembly_state (frag_now); | |
1675 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 1676 | nbytes, &exp, reloc_howto->pc_relative, reloc); |
43cd72b9 BW |
1677 | } |
1678 | } | |
1679 | else | |
1f7efbae BW |
1680 | { |
1681 | xtensa_set_frag_assembly_state (frag_now); | |
1682 | emit_expr (&exp, (unsigned int) nbytes); | |
1683 | } | |
43cd72b9 BW |
1684 | } |
1685 | while (*input_line_pointer++ == ','); | |
1686 | ||
1687 | input_line_pointer--; /* Put terminator back into stream. */ | |
1688 | demand_empty_rest_of_line (); | |
1689 | } | |
1690 | ||
fb227da0 BW |
1691 | static bfd_boolean is_leb128_expr; |
1692 | ||
1693 | static void | |
1694 | xtensa_leb128 (int sign) | |
1695 | { | |
1696 | is_leb128_expr = TRUE; | |
1697 | s_leb128 (sign); | |
1698 | is_leb128_expr = FALSE; | |
1699 | } | |
1700 | ||
7fa3d080 BW |
1701 | \f |
1702 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1703 | |
1704 | /* Parse @plt, etc. and return the desired relocation. */ | |
1705 | static bfd_reloc_code_real_type | |
7fa3d080 | 1706 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 | 1707 | { |
43cd72b9 BW |
1708 | char ident[20]; |
1709 | char *str = *str_p; | |
1710 | char *str2; | |
1711 | int ch; | |
1712 | int len; | |
e066bf5f | 1713 | unsigned int i; |
43cd72b9 BW |
1714 | |
1715 | if (*str++ != '@') | |
1716 | return BFD_RELOC_NONE; | |
1717 | ||
1718 | for (ch = *str, str2 = ident; | |
1719 | (str2 < ident + sizeof (ident) - 1 | |
1720 | && (ISALNUM (ch) || ch == '@')); | |
1721 | ch = *++str) | |
1722 | { | |
1723 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1724 | } | |
1725 | ||
1726 | *str2 = '\0'; | |
1727 | len = str2 - ident; | |
1728 | ||
1729 | ch = ident[0]; | |
e066bf5f TS |
1730 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
1731 | if (ch == suffix_relocs[i].suffix[0] | |
1732 | && len == suffix_relocs[i].length | |
1733 | && memcmp (ident, suffix_relocs[i].suffix, suffix_relocs[i].length) == 0) | |
43cd72b9 BW |
1734 | { |
1735 | /* Now check for "identifier@suffix+constant". */ | |
1736 | if (*str == '-' || *str == '+') | |
1737 | { | |
1738 | char *orig_line = input_line_pointer; | |
1739 | expressionS new_exp; | |
1740 | ||
1741 | input_line_pointer = str; | |
1742 | expression (&new_exp); | |
1743 | if (new_exp.X_op == O_constant) | |
1744 | { | |
1745 | exp_p->X_add_number += new_exp.X_add_number; | |
1746 | str = input_line_pointer; | |
1747 | } | |
1748 | ||
1749 | if (&input_line_pointer != str_p) | |
1750 | input_line_pointer = orig_line; | |
1751 | } | |
1752 | ||
1753 | *str_p = str; | |
e066bf5f | 1754 | return suffix_relocs[i].reloc; |
43cd72b9 BW |
1755 | } |
1756 | ||
1757 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1758 | } |
1759 | ||
e0001a05 | 1760 | |
bbdd25a8 | 1761 | /* Find the matching operator type. */ |
cc34adb2 | 1762 | static operatorT |
bbdd25a8 BW |
1763 | map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) |
1764 | { | |
cc34adb2 | 1765 | operatorT operator = O_illegal; |
e066bf5f | 1766 | unsigned int i; |
3739860c | 1767 | |
e066bf5f | 1768 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
bbdd25a8 | 1769 | { |
e066bf5f | 1770 | if (suffix_relocs[i].reloc == reloc) |
bbdd25a8 | 1771 | { |
e066bf5f | 1772 | operator = suffix_relocs[i].operator; |
bbdd25a8 BW |
1773 | break; |
1774 | } | |
1775 | } | |
cc34adb2 | 1776 | gas_assert (operator != O_illegal); |
bbdd25a8 BW |
1777 | return operator; |
1778 | } | |
1779 | ||
1780 | ||
1781 | /* Find the matching reloc type. */ | |
1782 | static bfd_reloc_code_real_type | |
28dbbc02 | 1783 | map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal) |
bbdd25a8 | 1784 | { |
e066bf5f | 1785 | unsigned int i; |
bbdd25a8 BW |
1786 | bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; |
1787 | ||
e066bf5f | 1788 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
bbdd25a8 | 1789 | { |
e066bf5f | 1790 | if (suffix_relocs[i].operator == operator) |
bbdd25a8 | 1791 | { |
e066bf5f | 1792 | reloc = suffix_relocs[i].reloc; |
bbdd25a8 BW |
1793 | break; |
1794 | } | |
1795 | } | |
1796 | ||
28dbbc02 BW |
1797 | if (is_literal) |
1798 | { | |
1799 | if (reloc == BFD_RELOC_XTENSA_TLS_FUNC) | |
1800 | return BFD_RELOC_XTENSA_TLSDESC_FN; | |
1801 | else if (reloc == BFD_RELOC_XTENSA_TLS_ARG) | |
1802 | return BFD_RELOC_XTENSA_TLSDESC_ARG; | |
1803 | } | |
1804 | ||
bbdd25a8 BW |
1805 | if (reloc == BFD_RELOC_UNUSED) |
1806 | return BFD_RELOC_32; | |
1807 | ||
1808 | return reloc; | |
1809 | } | |
1810 | ||
1811 | ||
e0001a05 | 1812 | static const char * |
7fa3d080 | 1813 | expression_end (const char *name) |
e0001a05 NC |
1814 | { |
1815 | while (1) | |
1816 | { | |
1817 | switch (*name) | |
1818 | { | |
43cd72b9 | 1819 | case '}': |
e0001a05 NC |
1820 | case ';': |
1821 | case '\0': | |
1822 | case ',': | |
43cd72b9 | 1823 | case ':': |
e0001a05 NC |
1824 | return name; |
1825 | case ' ': | |
1826 | case '\t': | |
1827 | ++name; | |
1828 | continue; | |
1829 | default: | |
1830 | return 0; | |
1831 | } | |
1832 | } | |
1833 | } | |
1834 | ||
1835 | ||
1836 | #define ERROR_REG_NUM ((unsigned) -1) | |
1837 | ||
1838 | static unsigned | |
7fa3d080 | 1839 | tc_get_register (const char *prefix) |
e0001a05 NC |
1840 | { |
1841 | unsigned reg; | |
1842 | const char *next_expr; | |
1843 | const char *old_line_pointer; | |
1844 | ||
1845 | SKIP_WHITESPACE (); | |
1846 | old_line_pointer = input_line_pointer; | |
1847 | ||
1848 | if (*input_line_pointer == '$') | |
1849 | ++input_line_pointer; | |
1850 | ||
1851 | /* Accept "sp" as a synonym for "a1". */ | |
1852 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1853 | && expression_end (input_line_pointer + 2)) | |
1854 | { | |
1855 | input_line_pointer += 2; | |
1856 | return 1; /* AR[1] */ | |
1857 | } | |
1858 | ||
1859 | while (*input_line_pointer++ == *prefix++) | |
1860 | ; | |
1861 | --input_line_pointer; | |
1862 | --prefix; | |
1863 | ||
1864 | if (*prefix) | |
1865 | { | |
1866 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1867 | return ERROR_REG_NUM; | |
1868 | } | |
1869 | ||
1870 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1871 | { | |
1872 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1873 | return ERROR_REG_NUM; | |
1874 | } | |
1875 | ||
1876 | reg = 0; | |
1877 | ||
1878 | while (ISDIGIT ((int) *input_line_pointer)) | |
1879 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1880 | ||
1881 | if (!(next_expr = expression_end (input_line_pointer))) | |
1882 | { | |
1883 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1884 | return ERROR_REG_NUM; | |
1885 | } | |
1886 | ||
1887 | input_line_pointer = (char *) next_expr; | |
1888 | ||
1889 | return reg; | |
1890 | } | |
1891 | ||
1892 | ||
e0001a05 | 1893 | static void |
7fa3d080 | 1894 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1895 | { |
43cd72b9 | 1896 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1897 | |
43cd72b9 BW |
1898 | /* Check if this is an immediate operand. */ |
1899 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1900 | { |
43cd72b9 | 1901 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1902 | segT t = expression (tok); |
91d6fa6a | 1903 | |
43cd72b9 BW |
1904 | if (t == absolute_section |
1905 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 | 1906 | { |
9c2799c2 | 1907 | gas_assert (tok->X_op == O_constant); |
e0001a05 NC |
1908 | tok->X_op = O_symbol; |
1909 | tok->X_add_symbol = &abs_symbol; | |
1910 | } | |
43cd72b9 BW |
1911 | |
1912 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
bbdd25a8 BW |
1913 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) |
1914 | != BFD_RELOC_NONE)) | |
e0001a05 | 1915 | { |
1bbb5f21 | 1916 | switch (reloc) |
43cd72b9 | 1917 | { |
1bbb5f21 BW |
1918 | case BFD_RELOC_LO16: |
1919 | if (tok->X_op == O_constant) | |
bbdd25a8 | 1920 | { |
43cd72b9 | 1921 | tok->X_add_number &= 0xffff; |
bbdd25a8 | 1922 | return; |
1bbb5f21 BW |
1923 | } |
1924 | break; | |
1925 | case BFD_RELOC_HI16: | |
1926 | if (tok->X_op == O_constant) | |
1927 | { | |
43cd72b9 | 1928 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; |
bbdd25a8 | 1929 | return; |
bbdd25a8 | 1930 | } |
1bbb5f21 BW |
1931 | break; |
1932 | case BFD_RELOC_UNUSED: | |
1933 | as_bad (_("unsupported relocation")); | |
1934 | return; | |
1935 | case BFD_RELOC_32_PCREL: | |
1936 | as_bad (_("pcrel relocation not allowed in an instruction")); | |
1937 | return; | |
1938 | default: | |
1939 | break; | |
43cd72b9 | 1940 | } |
bbdd25a8 | 1941 | tok->X_op = map_suffix_reloc_to_operator (reloc); |
e0001a05 | 1942 | } |
e0001a05 NC |
1943 | } |
1944 | else | |
1945 | { | |
43cd72b9 BW |
1946 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1947 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1948 | |
1949 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1950 | { | |
1951 | uint32 buf = reg; | |
43cd72b9 | 1952 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1953 | as_bad (_("register number out of range")); |
1954 | } | |
1955 | ||
1956 | tok->X_op = O_register; | |
1957 | tok->X_add_symbol = 0; | |
1958 | tok->X_add_number = reg; | |
1959 | } | |
1960 | } | |
1961 | ||
1962 | ||
1963 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1964 | ||
1965 | static int | |
7fa3d080 | 1966 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1967 | { |
1968 | char *old_input_line_pointer; | |
1969 | bfd_boolean saw_comma = FALSE; | |
1970 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1971 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1972 | int num_args = 0; |
1973 | char *arg_end, *arg; | |
1974 | int arg_len; | |
43cd72b9 BW |
1975 | |
1976 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1977 | old_input_line_pointer = input_line_pointer; |
1978 | input_line_pointer = str; | |
1979 | ||
1980 | while (*input_line_pointer) | |
1981 | { | |
1982 | SKIP_WHITESPACE (); | |
1983 | switch (*input_line_pointer) | |
1984 | { | |
1985 | case '\0': | |
43cd72b9 | 1986 | case '}': |
e0001a05 NC |
1987 | goto fini; |
1988 | ||
43cd72b9 BW |
1989 | case ':': |
1990 | input_line_pointer++; | |
1991 | if (saw_comma || saw_colon || !saw_arg) | |
1992 | goto err; | |
1993 | saw_colon = TRUE; | |
1994 | break; | |
1995 | ||
e0001a05 NC |
1996 | case ',': |
1997 | input_line_pointer++; | |
43cd72b9 | 1998 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
1999 | goto err; |
2000 | saw_comma = TRUE; | |
2001 | break; | |
2002 | ||
2003 | default: | |
43cd72b9 | 2004 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
2005 | goto err; |
2006 | ||
2007 | arg_end = input_line_pointer + 1; | |
2008 | while (!expression_end (arg_end)) | |
2009 | arg_end += 1; | |
43cd72b9 | 2010 | |
e0001a05 | 2011 | arg_len = arg_end - input_line_pointer; |
325801bd | 2012 | arg = XNEWVEC (char, (saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
2013 | args[num_args] = arg; |
2014 | ||
43cd72b9 BW |
2015 | if (saw_colon) |
2016 | *arg++ = ':'; | |
e0001a05 NC |
2017 | strncpy (arg, input_line_pointer, arg_len); |
2018 | arg[arg_len] = '\0'; | |
43cd72b9 | 2019 | |
e0001a05 NC |
2020 | input_line_pointer = arg_end; |
2021 | num_args += 1; | |
c138bc38 | 2022 | saw_comma = FALSE; |
43cd72b9 | 2023 | saw_colon = FALSE; |
c138bc38 | 2024 | saw_arg = TRUE; |
e0001a05 NC |
2025 | break; |
2026 | } | |
2027 | } | |
2028 | ||
2029 | fini: | |
43cd72b9 | 2030 | if (saw_comma || saw_colon) |
e0001a05 NC |
2031 | goto err; |
2032 | input_line_pointer = old_input_line_pointer; | |
2033 | return num_args; | |
2034 | ||
2035 | err: | |
43cd72b9 BW |
2036 | if (saw_comma) |
2037 | as_bad (_("extra comma")); | |
2038 | else if (saw_colon) | |
2039 | as_bad (_("extra colon")); | |
2040 | else if (!saw_arg) | |
c138bc38 | 2041 | as_bad (_("missing argument")); |
43cd72b9 BW |
2042 | else |
2043 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
2044 | input_line_pointer = old_input_line_pointer; |
2045 | return -1; | |
2046 | } | |
2047 | ||
2048 | ||
43cd72b9 | 2049 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
2050 | |
2051 | static bfd_boolean | |
7fa3d080 | 2052 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 2053 | { |
43cd72b9 | 2054 | expressionS *tok, *last_tok; |
e0001a05 NC |
2055 | xtensa_opcode opcode = insn->opcode; |
2056 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
2057 | xtensa_isa isa = xtensa_default_isa; |
2058 | int n, num_regs = 0; | |
e0001a05 | 2059 | int opcode_operand_count; |
43cd72b9 BW |
2060 | int opnd_cnt, last_opnd_cnt; |
2061 | unsigned int next_reg = 0; | |
e0001a05 NC |
2062 | char *old_input_line_pointer; |
2063 | ||
2064 | if (insn->insn_type == ITYPE_LITERAL) | |
2065 | opcode_operand_count = 1; | |
2066 | else | |
43cd72b9 | 2067 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 2068 | |
43cd72b9 | 2069 | tok = insn->tok; |
e0001a05 NC |
2070 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
2071 | ||
2072 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
2073 | old_input_line_pointer = input_line_pointer; |
2074 | ||
2075 | last_tok = 0; | |
2076 | last_opnd_cnt = -1; | |
2077 | opnd_cnt = 0; | |
2078 | ||
2079 | /* Skip invisible operands. */ | |
2080 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
2081 | { | |
2082 | opnd_cnt += 1; | |
2083 | tok++; | |
2084 | } | |
e0001a05 NC |
2085 | |
2086 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 2087 | { |
e0001a05 | 2088 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
2089 | if (*input_line_pointer == ':') |
2090 | { | |
2091 | xtensa_regfile opnd_rf; | |
2092 | input_line_pointer++; | |
2093 | if (num_regs == 0) | |
2094 | goto err; | |
9c2799c2 | 2095 | gas_assert (opnd_cnt > 0); |
43cd72b9 BW |
2096 | num_regs--; |
2097 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
2098 | if (next_reg | |
2099 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
2100 | as_warn (_("incorrect register number, ignoring")); | |
2101 | next_reg++; | |
2102 | } | |
2103 | else | |
2104 | { | |
2105 | if (opnd_cnt >= opcode_operand_count) | |
2106 | { | |
2107 | as_warn (_("too many arguments")); | |
2108 | goto err; | |
2109 | } | |
9c2799c2 | 2110 | gas_assert (opnd_cnt < MAX_INSN_ARGS); |
43cd72b9 BW |
2111 | |
2112 | expression_maybe_register (opcode, opnd_cnt, tok); | |
2113 | next_reg = tok->X_add_number + 1; | |
2114 | ||
2115 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
2116 | goto err; | |
2117 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
2118 | { | |
2119 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
2120 | /* minus 1 because we are seeing one right now */ | |
2121 | } | |
2122 | else | |
2123 | num_regs = 0; | |
e0001a05 | 2124 | |
43cd72b9 BW |
2125 | last_tok = tok; |
2126 | last_opnd_cnt = opnd_cnt; | |
1ec520b7 | 2127 | demand_empty_rest_of_line (); |
e0001a05 | 2128 | |
43cd72b9 BW |
2129 | do |
2130 | { | |
2131 | opnd_cnt += 1; | |
2132 | tok++; | |
2133 | } | |
2134 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
2135 | } | |
2136 | } | |
e0001a05 | 2137 | |
43cd72b9 BW |
2138 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
2139 | goto err; | |
e0001a05 NC |
2140 | |
2141 | insn->ntok = tok - insn->tok; | |
c138bc38 | 2142 | had_error = FALSE; |
e0001a05 NC |
2143 | |
2144 | err: | |
43cd72b9 | 2145 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2146 | return had_error; |
2147 | } | |
2148 | ||
2149 | ||
43cd72b9 | 2150 | static int |
7fa3d080 | 2151 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2152 | { |
2153 | xtensa_isa isa = xtensa_default_isa; | |
2154 | static xtensa_insnbuf slotbuf = NULL; | |
2155 | xtensa_format fmt; | |
2156 | xtensa_opcode opc = insn->opcode; | |
2157 | int slot, opnd, fmt_found; | |
2158 | unsigned val; | |
2159 | ||
2160 | if (!slotbuf) | |
2161 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2162 | ||
2163 | /* Find format/slot where this can be encoded. */ | |
2164 | fmt_found = 0; | |
2165 | slot = 0; | |
2166 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2167 | { | |
2168 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2169 | { | |
2170 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2171 | { | |
2172 | fmt_found = 1; | |
2173 | break; | |
2174 | } | |
2175 | } | |
2176 | if (fmt_found) break; | |
2177 | } | |
2178 | ||
2179 | if (!fmt_found) | |
2180 | { | |
2181 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2182 | return -1; | |
2183 | } | |
2184 | ||
2185 | /* First encode all the visible operands | |
2186 | (to deal with shared field operands). */ | |
2187 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2188 | { | |
2189 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2190 | && (insn->tok[opnd].X_op == O_register | |
2191 | || insn->tok[opnd].X_op == O_constant)) | |
2192 | { | |
2193 | val = insn->tok[opnd].X_add_number; | |
2194 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2195 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2196 | } | |
2197 | } | |
2198 | ||
2199 | /* Then pull out the values for the invisible ones. */ | |
2200 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2201 | { | |
2202 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2203 | { | |
2204 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2205 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2206 | insn->tok[opnd].X_add_number = val; | |
2207 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2208 | insn->tok[opnd].X_op = O_register; | |
2209 | else | |
2210 | insn->tok[opnd].X_op = O_constant; | |
2211 | } | |
2212 | } | |
2213 | ||
2214 | return 0; | |
2215 | } | |
2216 | ||
2217 | ||
e0001a05 | 2218 | static void |
7fa3d080 | 2219 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2220 | { |
2221 | char *cnt_arg, *new_arg; | |
2222 | cnt_arg = *cnt_argp; | |
2223 | ||
2224 | /* replace the argument with "31-(argument)" */ | |
78fb7e37 | 2225 | new_arg = concat ("31-(", cnt_arg, ")", (char *) NULL); |
e0001a05 NC |
2226 | |
2227 | free (cnt_arg); | |
2228 | *cnt_argp = new_arg; | |
2229 | } | |
2230 | ||
2231 | ||
2232 | /* If "arg" is a constant expression, return non-zero with the value | |
2233 | in *valp. */ | |
2234 | ||
2235 | static int | |
7fa3d080 | 2236 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2237 | { |
2238 | expressionS exp; | |
2239 | char *save_ptr = input_line_pointer; | |
2240 | ||
2241 | input_line_pointer = arg; | |
2242 | expression (&exp); | |
2243 | input_line_pointer = save_ptr; | |
2244 | ||
2245 | if (exp.X_op == O_constant) | |
2246 | { | |
2247 | *valp = exp.X_add_number; | |
2248 | return 1; | |
2249 | } | |
2250 | ||
2251 | return 0; | |
2252 | } | |
2253 | ||
2254 | ||
2255 | static void | |
b9bb4a93 | 2256 | xg_replace_opname (char **popname, const char *newop) |
e0001a05 NC |
2257 | { |
2258 | free (*popname); | |
4ec9d7d5 | 2259 | *popname = xstrdup (newop); |
e0001a05 NC |
2260 | } |
2261 | ||
2262 | ||
2263 | static int | |
7fa3d080 BW |
2264 | xg_check_num_args (int *pnum_args, |
2265 | int expected_num, | |
2266 | char *opname, | |
2267 | char **arg_strings) | |
e0001a05 NC |
2268 | { |
2269 | int num_args = *pnum_args; | |
2270 | ||
43cd72b9 | 2271 | if (num_args < expected_num) |
e0001a05 NC |
2272 | { |
2273 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2274 | num_args, opname, expected_num); | |
2275 | return -1; | |
2276 | } | |
2277 | ||
2278 | if (num_args > expected_num) | |
2279 | { | |
2280 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2281 | num_args, opname, expected_num); | |
2282 | while (num_args-- > expected_num) | |
2283 | { | |
2284 | free (arg_strings[num_args]); | |
2285 | arg_strings[num_args] = 0; | |
2286 | } | |
2287 | *pnum_args = expected_num; | |
2288 | return -1; | |
2289 | } | |
2290 | ||
2291 | return 0; | |
2292 | } | |
2293 | ||
2294 | ||
43cd72b9 BW |
2295 | /* If the register is not specified as part of the opcode, |
2296 | then get it from the operand and move it to the opcode. */ | |
2297 | ||
e0001a05 | 2298 | static int |
7fa3d080 | 2299 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2300 | { |
43cd72b9 BW |
2301 | xtensa_isa isa = xtensa_default_isa; |
2302 | xtensa_sysreg sr; | |
e0001a05 | 2303 | char *opname, *new_opname; |
43cd72b9 BW |
2304 | const char *sr_name; |
2305 | int is_user, is_write; | |
e0001a05 NC |
2306 | |
2307 | opname = *popname; | |
2308 | if (*opname == '_') | |
80ca4e2c | 2309 | opname += 1; |
43cd72b9 BW |
2310 | is_user = (opname[1] == 'u'); |
2311 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2312 | |
43cd72b9 | 2313 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2314 | |
43cd72b9 BW |
2315 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2316 | return -1; | |
e0001a05 | 2317 | |
43cd72b9 BW |
2318 | /* Check if the argument is a symbolic register name. */ |
2319 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2320 | /* Handle WSR to "INTSET" as a special case. */ | |
2321 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2322 | && !strcasecmp (arg_strings[1], "intset")) | |
2323 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2324 | if (sr == XTENSA_UNDEFINED | |
2325 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2326 | { | |
2327 | /* Maybe it's a register number.... */ | |
2328 | offsetT val; | |
e0001a05 NC |
2329 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2330 | { | |
43cd72b9 BW |
2331 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2332 | arg_strings[1], opname); | |
e0001a05 NC |
2333 | return -1; |
2334 | } | |
43cd72b9 BW |
2335 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2336 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2337 | { |
43cd72b9 | 2338 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2339 | (long) val, opname); |
e0001a05 NC |
2340 | return -1; |
2341 | } | |
43cd72b9 | 2342 | } |
e0001a05 | 2343 | |
43cd72b9 BW |
2344 | /* Remove the last argument, which is now part of the opcode. */ |
2345 | free (arg_strings[1]); | |
2346 | arg_strings[1] = 0; | |
2347 | *pnum_args = 1; | |
2348 | ||
2349 | /* Translate the opcode. */ | |
2350 | sr_name = xtensa_sysreg_name (isa, sr); | |
2351 | /* Another special case for "WSR.INTSET".... */ | |
2352 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2353 | sr_name = "intset"; | |
4ec9d7d5 | 2354 | new_opname = concat (*popname, ".", sr_name, (char *) NULL); |
43cd72b9 BW |
2355 | free (*popname); |
2356 | *popname = new_opname; | |
2357 | ||
2358 | return 0; | |
2359 | } | |
2360 | ||
2361 | ||
2362 | static int | |
7fa3d080 | 2363 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2364 | { |
2365 | xtensa_isa isa = xtensa_default_isa; | |
2366 | xtensa_sysreg sr; | |
2367 | char *opname, *new_opname; | |
2368 | const char *sr_name; | |
2369 | bfd_boolean has_underbar = FALSE; | |
2370 | ||
2371 | opname = *popname; | |
2372 | if (opname[0] == '_') | |
2373 | { | |
2374 | has_underbar = TRUE; | |
2375 | opname += 1; | |
2376 | } | |
2377 | ||
2378 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2379 | if (sr != XTENSA_UNDEFINED) | |
2380 | { | |
2381 | /* The new default name ("nnn") is different from the old default | |
2382 | name ("URnnn"). The old default is handled below, and we don't | |
2383 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2384 | default. */ | |
2385 | static char namebuf[10]; | |
2386 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2387 | if (strcmp (namebuf, opname + 1) == 0) | |
2388 | return 0; | |
2389 | } | |
2390 | else | |
2391 | { | |
2392 | offsetT val; | |
2393 | char *end; | |
2394 | ||
2395 | /* Only continue if the reg name is "URnnn". */ | |
2396 | if (opname[1] != 'u' || opname[2] != 'r') | |
2397 | return 0; | |
2398 | val = strtoul (opname + 3, &end, 10); | |
2399 | if (*end != '\0') | |
2400 | return 0; | |
2401 | ||
2402 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2403 | if (sr == XTENSA_UNDEFINED) | |
2404 | { | |
2405 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2406 | (long) val, opname); |
43cd72b9 BW |
2407 | return -1; |
2408 | } | |
2409 | } | |
2410 | ||
2411 | /* Translate the opcode. */ | |
2412 | sr_name = xtensa_sysreg_name (isa, sr); | |
add39d23 | 2413 | new_opname = XNEWVEC (char, strlen (sr_name) + 6); |
43cd72b9 BW |
2414 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), |
2415 | opname[0], sr_name); | |
2416 | free (*popname); | |
2417 | *popname = new_opname; | |
2418 | ||
2419 | return 0; | |
2420 | } | |
2421 | ||
2422 | ||
2423 | static int | |
b9bb4a93 TS |
2424 | xtensa_translate_zero_immed (const char *old_op, |
2425 | const char *new_op, | |
7fa3d080 BW |
2426 | char **popname, |
2427 | int *pnum_args, | |
2428 | char **arg_strings) | |
43cd72b9 BW |
2429 | { |
2430 | char *opname; | |
2431 | offsetT val; | |
2432 | ||
2433 | opname = *popname; | |
9c2799c2 | 2434 | gas_assert (opname[0] != '_'); |
43cd72b9 BW |
2435 | |
2436 | if (strcmp (opname, old_op) != 0) | |
2437 | return 0; | |
e0001a05 | 2438 | |
43cd72b9 BW |
2439 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2440 | return -1; | |
2441 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2442 | { | |
2443 | xg_replace_opname (popname, new_op); | |
2444 | free (arg_strings[1]); | |
2445 | arg_strings[1] = arg_strings[2]; | |
2446 | arg_strings[2] = 0; | |
2447 | *pnum_args = 2; | |
e0001a05 NC |
2448 | } |
2449 | ||
2450 | return 0; | |
2451 | } | |
2452 | ||
2453 | ||
2454 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2455 | Returns non-zero if an error was found. */ | |
2456 | ||
2457 | static int | |
7fa3d080 | 2458 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2459 | { |
2460 | char *opname = *popname; | |
2461 | bfd_boolean has_underbar = FALSE; | |
2462 | ||
2463 | if (*opname == '_') | |
2464 | { | |
2465 | has_underbar = TRUE; | |
2466 | opname += 1; | |
2467 | } | |
2468 | ||
2469 | if (strcmp (opname, "mov") == 0) | |
2470 | { | |
43cd72b9 | 2471 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2472 | xg_replace_opname (popname, "mov.n"); |
2473 | else | |
2474 | { | |
2475 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2476 | return -1; | |
2477 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
4ec9d7d5 | 2478 | arg_strings[2] = xstrdup (arg_strings[1]); |
e0001a05 NC |
2479 | *pnum_args = 3; |
2480 | } | |
2481 | return 0; | |
2482 | } | |
2483 | ||
2484 | if (strcmp (opname, "bbsi.l") == 0) | |
2485 | { | |
2486 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2487 | return -1; | |
2488 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2489 | if (target_big_endian) | |
2490 | xg_reverse_shift_count (&arg_strings[1]); | |
2491 | return 0; | |
2492 | } | |
2493 | ||
2494 | if (strcmp (opname, "bbci.l") == 0) | |
2495 | { | |
2496 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2497 | return -1; | |
2498 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2499 | if (target_big_endian) | |
2500 | xg_reverse_shift_count (&arg_strings[1]); | |
2501 | return 0; | |
2502 | } | |
2503 | ||
eb6d9dce | 2504 | /* Don't do anything special with NOPs inside FLIX instructions. They |
3739860c | 2505 | are handled elsewhere. Real NOP instructions are always available |
eb6d9dce BW |
2506 | in configurations with FLIX, so this should never be an issue but |
2507 | check for it anyway. */ | |
2508 | if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED | |
43cd72b9 | 2509 | && strcmp (opname, "nop") == 0) |
e0001a05 | 2510 | { |
43cd72b9 | 2511 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2512 | xg_replace_opname (popname, "nop.n"); |
2513 | else | |
2514 | { | |
2515 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2516 | return -1; | |
2517 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
4ec9d7d5 TS |
2518 | arg_strings[0] = xstrdup ("a1"); |
2519 | arg_strings[1] = xstrdup ("a1"); | |
2520 | arg_strings[2] = xstrdup ("a1"); | |
e0001a05 NC |
2521 | *pnum_args = 3; |
2522 | } | |
2523 | return 0; | |
2524 | } | |
2525 | ||
43cd72b9 BW |
2526 | /* Recognize [RW]UR and [RWX]SR. */ |
2527 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2528 | && (opname[1] == 'u' || opname[1] == 's')) | |
2529 | || (opname[0] == 'x' && opname[1] == 's')) | |
2530 | && opname[2] == 'r' | |
2531 | && opname[3] == '\0') | |
e0001a05 NC |
2532 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2533 | ||
43cd72b9 BW |
2534 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2535 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2536 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2537 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2538 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2539 | |
43cd72b9 BW |
2540 | /* Relax branches that don't allow comparisons against an immediate value |
2541 | of zero to the corresponding branches with implicit zero immediates. */ | |
2542 | if (!has_underbar && use_transform ()) | |
2543 | { | |
2544 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2545 | pnum_args, arg_strings)) | |
2546 | return -1; | |
e0001a05 | 2547 | |
43cd72b9 BW |
2548 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2549 | pnum_args, arg_strings)) | |
2550 | return -1; | |
e0001a05 | 2551 | |
43cd72b9 BW |
2552 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2553 | pnum_args, arg_strings)) | |
2554 | return -1; | |
e0001a05 | 2555 | |
43cd72b9 BW |
2556 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2557 | pnum_args, arg_strings)) | |
2558 | return -1; | |
2559 | } | |
e0001a05 | 2560 | |
43cd72b9 BW |
2561 | return 0; |
2562 | } | |
e0001a05 | 2563 | |
43cd72b9 BW |
2564 | \f |
2565 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2566 | |
43cd72b9 BW |
2567 | /* Currently the assembler only allows us to use a single target per |
2568 | fragment. Because of this, only one operand for a given | |
2569 | instruction may be symbolic. If there is a PC-relative operand, | |
2570 | the last one is chosen. Otherwise, the result is the number of the | |
2571 | last immediate operand, and if there are none of those, we fail and | |
2572 | return -1. */ | |
e0001a05 | 2573 | |
7fa3d080 BW |
2574 | static int |
2575 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2576 | { |
2577 | int last_immed = -1; | |
2578 | int noperands, opi; | |
e0001a05 | 2579 | |
43cd72b9 BW |
2580 | if (opcode == XTENSA_UNDEFINED) |
2581 | return -1; | |
e0001a05 | 2582 | |
43cd72b9 BW |
2583 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2584 | for (opi = noperands - 1; opi >= 0; opi--) | |
2585 | { | |
2586 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2587 | continue; | |
2588 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2589 | return opi; | |
2590 | if (last_immed == -1 | |
2591 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2592 | last_immed = opi; | |
e0001a05 | 2593 | } |
43cd72b9 | 2594 | return last_immed; |
e0001a05 NC |
2595 | } |
2596 | ||
e0001a05 | 2597 | |
43cd72b9 | 2598 | static xtensa_opcode |
7fa3d080 | 2599 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2600 | { |
43cd72b9 BW |
2601 | static xtensa_insnbuf insnbuf = NULL; |
2602 | static xtensa_insnbuf slotbuf = NULL; | |
2603 | xtensa_isa isa = xtensa_default_isa; | |
2604 | xtensa_format fmt; | |
2605 | ||
2606 | if (!insnbuf) | |
e0001a05 | 2607 | { |
43cd72b9 BW |
2608 | insnbuf = xtensa_insnbuf_alloc (isa); |
2609 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2610 | } |
e0001a05 | 2611 | |
d77b99c9 | 2612 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2613 | fmt = xtensa_format_decode (isa, insnbuf); |
2614 | if (fmt == XTENSA_UNDEFINED) | |
2615 | return XTENSA_UNDEFINED; | |
e0001a05 | 2616 | |
43cd72b9 BW |
2617 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2618 | return XTENSA_UNDEFINED; | |
e0001a05 | 2619 | |
43cd72b9 BW |
2620 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2621 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2622 | } |
2623 | ||
2624 | ||
43cd72b9 | 2625 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2626 | |
43cd72b9 | 2627 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2628 | |
7fa3d080 BW |
2629 | static void |
2630 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2631 | { |
2632 | int num_opcodes, num_operands; | |
2633 | xtensa_opcode opcode; | |
2634 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2635 | |
43cd72b9 BW |
2636 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2637 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2638 | { |
43cd72b9 BW |
2639 | int opn; |
2640 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2641 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2642 | for (opn = 0; opn < num_operands; opn++) | |
2643 | { | |
2644 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2645 | continue; | |
2646 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2647 | { | |
2648 | xtensa_regfile opnd_rf = | |
2649 | xtensa_operand_regfile (isa, opcode, opn); | |
2650 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2651 | } | |
2652 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2653 | fputs ("[lLr] ", stderr); | |
2654 | else | |
2655 | fputs ("i ", stderr); | |
2656 | } | |
2657 | fprintf (stderr, "\n"); | |
e0001a05 | 2658 | } |
e0001a05 NC |
2659 | } |
2660 | ||
2661 | ||
43cd72b9 | 2662 | static void |
7fa3d080 | 2663 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2664 | { |
e0001a05 | 2665 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2666 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2667 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2668 | int op; | |
e0001a05 | 2669 | |
43cd72b9 | 2670 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2671 | |
43cd72b9 BW |
2672 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2673 | { | |
2674 | xtensa_opcode opcode; | |
2675 | const char *opname; | |
2676 | int operands; | |
2677 | ||
2678 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2679 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2680 | opname = xtensa_opcode_name (isa, opcode); | |
2681 | ||
2682 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2683 | fprintf (stderr, " operands = "); | |
2684 | for (operands = 0; | |
2685 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2686 | operands++) | |
2687 | { | |
2688 | unsigned int val; | |
2689 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2690 | continue; | |
2691 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2692 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2693 | fprintf (stderr, "%d ", val); | |
2694 | } | |
2695 | fprintf (stderr, "\n"); | |
2696 | } | |
2697 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2698 | } |
2699 | ||
43cd72b9 BW |
2700 | #endif /* TENSILICA_DEBUG */ |
2701 | ||
e0001a05 NC |
2702 | |
2703 | static bfd_boolean | |
7fa3d080 | 2704 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2705 | { |
43cd72b9 BW |
2706 | xtensa_isa isa = xtensa_default_isa; |
2707 | int n, num_operands; | |
e0001a05 | 2708 | |
64b607e6 | 2709 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
e0001a05 NC |
2710 | return FALSE; |
2711 | ||
43cd72b9 BW |
2712 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2713 | for (n = 0; n < num_operands; n++) | |
2714 | { | |
2715 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2716 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2717 | return TRUE; | |
2718 | } | |
2719 | return FALSE; | |
e0001a05 NC |
2720 | } |
2721 | ||
2722 | ||
43cd72b9 BW |
2723 | /* Convert from BFD relocation type code to slot and operand number. |
2724 | Returns non-zero on failure. */ | |
e0001a05 | 2725 | |
43cd72b9 | 2726 | static int |
7fa3d080 | 2727 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2728 | { |
43cd72b9 BW |
2729 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2730 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2731 | { |
43cd72b9 BW |
2732 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2733 | *is_alt = FALSE; | |
e0001a05 | 2734 | } |
43cd72b9 BW |
2735 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2736 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2737 | { |
43cd72b9 BW |
2738 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2739 | *is_alt = TRUE; | |
e0001a05 | 2740 | } |
43cd72b9 BW |
2741 | else |
2742 | return -1; | |
2743 | ||
2744 | return 0; | |
e0001a05 NC |
2745 | } |
2746 | ||
2747 | ||
43cd72b9 BW |
2748 | /* Convert from slot number to BFD relocation type code for the |
2749 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2750 | failure. */ | |
e0001a05 | 2751 | |
43cd72b9 | 2752 | static bfd_reloc_code_real_type |
7fa3d080 | 2753 | encode_reloc (int slot) |
e0001a05 | 2754 | { |
43cd72b9 BW |
2755 | if (slot < 0 || slot > 14) |
2756 | return BFD_RELOC_NONE; | |
2757 | ||
2758 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2759 | } |
2760 | ||
2761 | ||
43cd72b9 BW |
2762 | /* Convert from slot numbers to BFD relocation type code for the |
2763 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2764 | |
43cd72b9 | 2765 | static bfd_reloc_code_real_type |
7fa3d080 | 2766 | encode_alt_reloc (int slot) |
e0001a05 | 2767 | { |
43cd72b9 BW |
2768 | if (slot < 0 || slot > 14) |
2769 | return BFD_RELOC_NONE; | |
2770 | ||
2771 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2772 | } |
2773 | ||
2774 | ||
2775 | static void | |
7fa3d080 BW |
2776 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2777 | xtensa_format fmt, | |
2778 | int slot, | |
2779 | xtensa_opcode opcode, | |
2780 | int operand, | |
2781 | uint32 value, | |
2782 | const char *file, | |
2783 | unsigned int line) | |
e0001a05 | 2784 | { |
e0001a05 NC |
2785 | uint32 valbuf = value; |
2786 | ||
43cd72b9 | 2787 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2788 | { |
43cd72b9 BW |
2789 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2790 | == 1) | |
2791 | as_bad_where ((char *) file, line, | |
3739860c | 2792 | _("operand %d of '%s' has out of range value '%u'"), |
d7c531cd BW |
2793 | operand + 1, |
2794 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2795 | value); | |
43cd72b9 BW |
2796 | else |
2797 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2798 | _("operand %d of '%s' has invalid value '%u'"), |
2799 | operand + 1, | |
2800 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2801 | value); | |
43cd72b9 | 2802 | return; |
e0001a05 NC |
2803 | } |
2804 | ||
43cd72b9 BW |
2805 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2806 | slotbuf, valbuf); | |
e0001a05 NC |
2807 | } |
2808 | ||
2809 | ||
2810 | static uint32 | |
7fa3d080 BW |
2811 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2812 | xtensa_format fmt, | |
2813 | int slot, | |
2814 | xtensa_opcode opcode, | |
2815 | int opnum) | |
e0001a05 | 2816 | { |
43cd72b9 BW |
2817 | uint32 val = 0; |
2818 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2819 | fmt, slot, slotbuf, &val); | |
2820 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2821 | return val; | |
e0001a05 NC |
2822 | } |
2823 | ||
e0001a05 | 2824 | \f |
7fa3d080 | 2825 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2826 | |
7fa3d080 BW |
2827 | /* The routine xg_instruction_matches_option_term must return TRUE |
2828 | when a given option term is true. The meaning of all of the option | |
19e8f41a | 2829 | terms is given interpretation by this function. */ |
e0001a05 | 2830 | |
7fa3d080 | 2831 | static bfd_boolean |
19e8f41a | 2832 | xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option) |
e0001a05 | 2833 | { |
7fa3d080 BW |
2834 | if (strcmp (option->option_name, "realnop") == 0 |
2835 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2836 | { | |
2837 | /* These conditions were evaluated statically when building the | |
2838 | relaxation table. There's no need to reevaluate them now. */ | |
2839 | return TRUE; | |
2840 | } | |
19e8f41a BW |
2841 | else if (strcmp (option->option_name, "FREEREG") == 0) |
2842 | return insn->extra_arg.X_op == O_register; | |
7fa3d080 BW |
2843 | else |
2844 | { | |
2845 | as_fatal (_("internal error: unknown option name '%s'"), | |
2846 | option->option_name); | |
2847 | } | |
e0001a05 NC |
2848 | } |
2849 | ||
2850 | ||
7fa3d080 BW |
2851 | static bfd_boolean |
2852 | xg_instruction_matches_or_options (TInsn *insn, | |
2853 | const ReqOrOptionList *or_option) | |
e0001a05 | 2854 | { |
7fa3d080 BW |
2855 | const ReqOrOption *option; |
2856 | /* Must match each of the AND terms. */ | |
2857 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2858 | { |
7fa3d080 BW |
2859 | if (xg_instruction_matches_option_term (insn, option)) |
2860 | return TRUE; | |
e0001a05 | 2861 | } |
7fa3d080 | 2862 | return FALSE; |
e0001a05 NC |
2863 | } |
2864 | ||
2865 | ||
7fa3d080 BW |
2866 | static bfd_boolean |
2867 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2868 | { |
7fa3d080 BW |
2869 | const ReqOption *req_options; |
2870 | /* Must match each of the AND terms. */ | |
2871 | for (req_options = options; | |
2872 | req_options != NULL; | |
2873 | req_options = req_options->next) | |
e0001a05 | 2874 | { |
7fa3d080 BW |
2875 | /* Must match one of the OR clauses. */ |
2876 | if (!xg_instruction_matches_or_options (insn, | |
2877 | req_options->or_option_terms)) | |
2878 | return FALSE; | |
e0001a05 | 2879 | } |
7fa3d080 | 2880 | return TRUE; |
e0001a05 NC |
2881 | } |
2882 | ||
2883 | ||
7fa3d080 | 2884 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2885 | |
7fa3d080 BW |
2886 | static bfd_boolean |
2887 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2888 | { |
7fa3d080 | 2889 | PreconditionList *condition_l; |
e0001a05 | 2890 | |
7fa3d080 BW |
2891 | if (rule->opcode != insn->opcode) |
2892 | return FALSE; | |
e0001a05 | 2893 | |
7fa3d080 BW |
2894 | for (condition_l = rule->conditions; |
2895 | condition_l != NULL; | |
2896 | condition_l = condition_l->next) | |
e0001a05 | 2897 | { |
7fa3d080 BW |
2898 | expressionS *exp1; |
2899 | expressionS *exp2; | |
2900 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2901 | |
7fa3d080 | 2902 | switch (cond->typ) |
e0001a05 | 2903 | { |
7fa3d080 BW |
2904 | case OP_CONSTANT: |
2905 | /* The expression must be the constant. */ | |
9c2799c2 | 2906 | gas_assert (cond->op_num < insn->ntok); |
7fa3d080 BW |
2907 | exp1 = &insn->tok[cond->op_num]; |
2908 | if (expr_is_const (exp1)) | |
2909 | { | |
2910 | switch (cond->cmp) | |
2911 | { | |
2912 | case OP_EQUAL: | |
2913 | if (get_expr_const (exp1) != cond->op_data) | |
2914 | return FALSE; | |
2915 | break; | |
2916 | case OP_NOTEQUAL: | |
2917 | if (get_expr_const (exp1) == cond->op_data) | |
2918 | return FALSE; | |
2919 | break; | |
2920 | default: | |
2921 | return FALSE; | |
2922 | } | |
2923 | } | |
2924 | else if (expr_is_register (exp1)) | |
2925 | { | |
2926 | switch (cond->cmp) | |
2927 | { | |
2928 | case OP_EQUAL: | |
2929 | if (get_expr_register (exp1) != cond->op_data) | |
2930 | return FALSE; | |
2931 | break; | |
2932 | case OP_NOTEQUAL: | |
2933 | if (get_expr_register (exp1) == cond->op_data) | |
2934 | return FALSE; | |
2935 | break; | |
2936 | default: | |
2937 | return FALSE; | |
2938 | } | |
2939 | } | |
2940 | else | |
2941 | return FALSE; | |
2942 | break; | |
2943 | ||
2944 | case OP_OPERAND: | |
9c2799c2 NC |
2945 | gas_assert (cond->op_num < insn->ntok); |
2946 | gas_assert (cond->op_data < insn->ntok); | |
7fa3d080 BW |
2947 | exp1 = &insn->tok[cond->op_num]; |
2948 | exp2 = &insn->tok[cond->op_data]; | |
2949 | ||
2950 | switch (cond->cmp) | |
2951 | { | |
2952 | case OP_EQUAL: | |
2953 | if (!expr_is_equal (exp1, exp2)) | |
2954 | return FALSE; | |
2955 | break; | |
2956 | case OP_NOTEQUAL: | |
2957 | if (expr_is_equal (exp1, exp2)) | |
2958 | return FALSE; | |
2959 | break; | |
2960 | } | |
2961 | break; | |
2962 | ||
2963 | case OP_LITERAL: | |
2964 | case OP_LABEL: | |
2965 | default: | |
2966 | return FALSE; | |
2967 | } | |
2968 | } | |
2969 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2970 | return FALSE; | |
2971 | ||
2972 | return TRUE; | |
2973 | } | |
2974 | ||
2975 | ||
2976 | static int | |
2977 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2978 | { | |
2979 | bfd_boolean a_greater = FALSE; | |
2980 | bfd_boolean b_greater = FALSE; | |
2981 | ||
2982 | ReqOptionList *l_a = a->options; | |
2983 | ReqOptionList *l_b = b->options; | |
2984 | ||
2985 | /* We only care if they both are the same except for | |
2986 | a const16 vs. an l32r. */ | |
2987 | ||
2988 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2989 | { | |
2990 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2991 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2992 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2993 | { | |
2994 | if (l_or_a->is_true != l_or_b->is_true) | |
2995 | return 0; | |
2996 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2997 | { | |
2998 | /* This is the case we care about. */ | |
2999 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
3000 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
3001 | { | |
3002 | if (prefer_const16) | |
3003 | a_greater = TRUE; | |
3004 | else | |
3005 | b_greater = TRUE; | |
3006 | } | |
3007 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
3008 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
3009 | { | |
3010 | if (prefer_const16) | |
3011 | b_greater = TRUE; | |
3012 | else | |
3013 | a_greater = TRUE; | |
3014 | } | |
3015 | else | |
3016 | return 0; | |
3017 | } | |
3018 | l_or_a = l_or_a->next; | |
3019 | l_or_b = l_or_b->next; | |
3020 | } | |
3021 | if (l_or_a || l_or_b) | |
3022 | return 0; | |
3023 | ||
3024 | l_a = l_a->next; | |
3025 | l_b = l_b->next; | |
3026 | } | |
3027 | if (l_a || l_b) | |
3028 | return 0; | |
3029 | ||
3030 | /* Incomparable if the substitution was used differently in two cases. */ | |
3031 | if (a_greater && b_greater) | |
3032 | return 0; | |
3033 | ||
3034 | if (b_greater) | |
3035 | return 1; | |
3036 | if (a_greater) | |
3037 | return -1; | |
3038 | ||
3039 | return 0; | |
3040 | } | |
3041 | ||
3042 | ||
3043 | static TransitionRule * | |
3044 | xg_instruction_match (TInsn *insn) | |
3045 | { | |
3046 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
3047 | TransitionList *l; | |
9c2799c2 | 3048 | gas_assert (insn->opcode < table->num_opcodes); |
7fa3d080 BW |
3049 | |
3050 | /* Walk through all of the possible transitions. */ | |
3051 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3052 | { | |
3053 | TransitionRule *rule = l->rule; | |
3054 | if (xg_instruction_matches_rule (insn, rule)) | |
3055 | return rule; | |
3056 | } | |
3057 | return NULL; | |
3058 | } | |
3059 | ||
3060 | \f | |
3061 | /* Various Other Internal Functions. */ | |
3062 | ||
3063 | static bfd_boolean | |
3064 | is_unique_insn_expansion (TransitionRule *r) | |
3065 | { | |
3066 | if (!r->to_instr || r->to_instr->next != NULL) | |
3067 | return FALSE; | |
3068 | if (r->to_instr->typ != INSTR_INSTR) | |
3069 | return FALSE; | |
3070 | return TRUE; | |
3071 | } | |
3072 | ||
3073 | ||
84b08ed9 BW |
3074 | /* Check if there is exactly one relaxation for INSN that converts it to |
3075 | another instruction of equal or larger size. If so, and if TARG is | |
3076 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
3077 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
3078 | instruction, i.e., ignore relaxations that convert to an instruction of | |
3079 | equal size. In some contexts where this function is used, only | |
c138bc38 | 3080 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
3081 | exclude cases like ADDI being "widened" to an ADDMI, which may |
3082 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 3083 | |
84b08ed9 BW |
3084 | bfd_boolean |
3085 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
3086 | { |
3087 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3088 | TransitionList *l; | |
84b08ed9 | 3089 | TransitionRule *match = 0; |
7fa3d080 | 3090 | |
9c2799c2 NC |
3091 | gas_assert (insn->insn_type == ITYPE_INSN); |
3092 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3093 | |
3094 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3095 | { | |
3096 | TransitionRule *rule = l->rule; | |
3097 | ||
3098 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
3099 | && is_unique_insn_expansion (rule) |
3100 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
3101 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 3102 | { |
84b08ed9 BW |
3103 | if (match) |
3104 | return FALSE; | |
3105 | match = rule; | |
7fa3d080 BW |
3106 | } |
3107 | } | |
84b08ed9 BW |
3108 | if (!match) |
3109 | return FALSE; | |
3110 | ||
3111 | if (targ) | |
3112 | xg_build_to_insn (targ, insn, match->to_instr); | |
3113 | return TRUE; | |
7fa3d080 BW |
3114 | } |
3115 | ||
3116 | ||
3117 | /* Return the maximum number of bytes this opcode can expand to. */ | |
3118 | ||
3119 | static int | |
3120 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
3121 | { | |
3122 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3123 | TransitionList *l; | |
3124 | int max_size = xg_get_single_size (opcode); | |
3125 | ||
9c2799c2 | 3126 | gas_assert (opcode < table->num_opcodes); |
7fa3d080 BW |
3127 | |
3128 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3129 | { | |
3130 | TransitionRule *rule = l->rule; | |
3131 | BuildInstr *build_list; | |
3132 | int this_size = 0; | |
3133 | ||
3134 | if (!rule) | |
3135 | continue; | |
3136 | build_list = rule->to_instr; | |
3137 | if (is_unique_insn_expansion (rule)) | |
3138 | { | |
9c2799c2 | 3139 | gas_assert (build_list->typ == INSTR_INSTR); |
7fa3d080 BW |
3140 | this_size = xg_get_max_insn_widen_size (build_list->opcode); |
3141 | } | |
3142 | else | |
3143 | for (; build_list != NULL; build_list = build_list->next) | |
3144 | { | |
3145 | switch (build_list->typ) | |
3146 | { | |
3147 | case INSTR_INSTR: | |
3148 | this_size += xg_get_single_size (build_list->opcode); | |
3149 | break; | |
3150 | case INSTR_LITERAL_DEF: | |
3151 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3152 | default: |
3153 | break; | |
3154 | } | |
3155 | } | |
3156 | if (this_size > max_size) | |
3157 | max_size = this_size; | |
3158 | } | |
3159 | return max_size; | |
3160 | } | |
3161 | ||
3162 | ||
3163 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3164 | ||
7fa3d080 BW |
3165 | static int |
3166 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3167 | { |
43cd72b9 | 3168 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3169 | TransitionList *l; |
3170 | int max_size = 0; | |
3171 | ||
9c2799c2 | 3172 | gas_assert (opcode < table->num_opcodes); |
e0001a05 NC |
3173 | |
3174 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3175 | { | |
3176 | TransitionRule *rule = l->rule; | |
3177 | BuildInstr *build_list; | |
3178 | int this_size = 0; | |
3179 | ||
3180 | if (!rule) | |
3181 | continue; | |
3182 | build_list = rule->to_instr; | |
3183 | if (is_unique_insn_expansion (rule)) | |
3184 | { | |
9c2799c2 | 3185 | gas_assert (build_list->typ == INSTR_INSTR); |
e0001a05 NC |
3186 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); |
3187 | } | |
3188 | else | |
3189 | for (; build_list != NULL; build_list = build_list->next) | |
3190 | { | |
3191 | switch (build_list->typ) | |
3192 | { | |
3193 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3194 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3195 | this_size += 4; |
3196 | break; | |
3197 | case INSTR_INSTR: | |
3198 | case INSTR_LABEL_DEF: | |
3199 | default: | |
3200 | break; | |
3201 | } | |
3202 | } | |
3203 | if (this_size > max_size) | |
3204 | max_size = this_size; | |
3205 | } | |
3206 | return max_size; | |
3207 | } | |
3208 | ||
3209 | ||
7fa3d080 BW |
3210 | static bfd_boolean |
3211 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3212 | { | |
3213 | int steps_taken = 0; | |
3214 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3215 | TransitionList *l; | |
3216 | ||
9c2799c2 NC |
3217 | gas_assert (insn->insn_type == ITYPE_INSN); |
3218 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3219 | |
3220 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3221 | { | |
3222 | TransitionRule *rule = l->rule; | |
3223 | ||
3224 | if (xg_instruction_matches_rule (insn, rule)) | |
3225 | { | |
3226 | if (steps_taken == lateral_steps) | |
3227 | return TRUE; | |
3228 | steps_taken++; | |
3229 | } | |
3230 | } | |
3231 | return FALSE; | |
3232 | } | |
3233 | ||
3234 | ||
3235 | static symbolS * | |
3236 | get_special_literal_symbol (void) | |
3237 | { | |
3238 | static symbolS *sym = NULL; | |
3239 | ||
3240 | if (sym == NULL) | |
3241 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3242 | return sym; | |
3243 | } | |
3244 | ||
3245 | ||
3246 | static symbolS * | |
3247 | get_special_label_symbol (void) | |
3248 | { | |
3249 | static symbolS *sym = NULL; | |
3250 | ||
3251 | if (sym == NULL) | |
3252 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3253 | return sym; | |
3254 | } | |
3255 | ||
3256 | ||
3257 | static bfd_boolean | |
3258 | xg_valid_literal_expression (const expressionS *exp) | |
3259 | { | |
3260 | switch (exp->X_op) | |
3261 | { | |
3262 | case O_constant: | |
3263 | case O_symbol: | |
3264 | case O_big: | |
3265 | case O_uminus: | |
3266 | case O_subtract: | |
3267 | case O_pltrel: | |
1bbb5f21 | 3268 | case O_pcrel: |
28dbbc02 BW |
3269 | case O_tlsfunc: |
3270 | case O_tlsarg: | |
3271 | case O_tpoff: | |
3272 | case O_dtpoff: | |
7fa3d080 BW |
3273 | return TRUE; |
3274 | default: | |
3275 | return FALSE; | |
3276 | } | |
3277 | } | |
3278 | ||
3279 | ||
3280 | /* This will check to see if the value can be converted into the | |
3281 | operand type. It will return TRUE if it does not fit. */ | |
3282 | ||
3283 | static bfd_boolean | |
3284 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3285 | { | |
3286 | uint32 valbuf = value; | |
3287 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3288 | return TRUE; | |
3289 | return FALSE; | |
3290 | } | |
3291 | ||
3292 | ||
3293 | /* Assumes: All immeds are constants. Check that all constants fit | |
3294 | into their immeds; return FALSE if not. */ | |
3295 | ||
3296 | static bfd_boolean | |
3297 | xg_immeds_fit (const TInsn *insn) | |
3298 | { | |
3299 | xtensa_isa isa = xtensa_default_isa; | |
3300 | int i; | |
3301 | ||
3302 | int n = insn->ntok; | |
9c2799c2 | 3303 | gas_assert (insn->insn_type == ITYPE_INSN); |
7fa3d080 BW |
3304 | for (i = 0; i < n; ++i) |
3305 | { | |
91d6fa6a NC |
3306 | const expressionS *exp = &insn->tok[i]; |
3307 | ||
7fa3d080 BW |
3308 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) |
3309 | continue; | |
3310 | ||
91d6fa6a | 3311 | switch (exp->X_op) |
7fa3d080 BW |
3312 | { |
3313 | case O_register: | |
3314 | case O_constant: | |
91d6fa6a | 3315 | if (xg_check_operand (exp->X_add_number, insn->opcode, i)) |
7fa3d080 BW |
3316 | return FALSE; |
3317 | break; | |
3318 | ||
3319 | default: | |
3320 | /* The symbol should have a fixup associated with it. */ | |
9c2799c2 | 3321 | gas_assert (FALSE); |
7fa3d080 BW |
3322 | break; |
3323 | } | |
3324 | } | |
3325 | return TRUE; | |
3326 | } | |
3327 | ||
3328 | ||
3329 | /* This should only be called after we have an initial | |
3330 | estimate of the addresses. */ | |
3331 | ||
3332 | static bfd_boolean | |
3333 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3334 | segT pc_seg, | |
3335 | fragS *pc_frag, | |
3336 | offsetT pc_offset, | |
3337 | long stretch) | |
e0001a05 | 3338 | { |
7fa3d080 BW |
3339 | xtensa_isa isa = xtensa_default_isa; |
3340 | symbolS *symbolP; | |
3341 | fragS *sym_frag; | |
3342 | offsetT target, pc; | |
3343 | uint32 new_offset; | |
3344 | int i; | |
3345 | int n = insn->ntok; | |
e0001a05 | 3346 | |
9c2799c2 | 3347 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 | 3348 | |
7fa3d080 | 3349 | for (i = 0; i < n; ++i) |
e0001a05 | 3350 | { |
91d6fa6a NC |
3351 | const expressionS *exp = &insn->tok[i]; |
3352 | ||
7fa3d080 BW |
3353 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) |
3354 | continue; | |
e0001a05 | 3355 | |
91d6fa6a | 3356 | switch (exp->X_op) |
e0001a05 | 3357 | { |
7fa3d080 BW |
3358 | case O_register: |
3359 | case O_constant: | |
91d6fa6a | 3360 | if (xg_check_operand (exp->X_add_number, insn->opcode, i)) |
7fa3d080 BW |
3361 | return FALSE; |
3362 | break; | |
e0001a05 | 3363 | |
7fa3d080 BW |
3364 | case O_lo16: |
3365 | case O_hi16: | |
3366 | /* Check for the worst case. */ | |
3367 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3368 | return FALSE; | |
3369 | break; | |
e0001a05 | 3370 | |
7fa3d080 | 3371 | case O_symbol: |
7c834684 | 3372 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3373 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3374 | if (pc_frag == 0 |
3375 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3376 | return FALSE; |
e0001a05 | 3377 | |
8e6bc631 BW |
3378 | /* If it is a weak symbol or a symbol in a different section, |
3379 | it cannot be known to fit at assembly time. */ | |
91d6fa6a NC |
3380 | if (S_IS_WEAK (exp->X_add_symbol) |
3381 | || S_GET_SEGMENT (exp->X_add_symbol) != pc_seg) | |
7c834684 | 3382 | { |
8e6bc631 | 3383 | /* For a direct call with --no-longcalls, be optimistic and |
38f9cb7f BW |
3384 | assume it will be in range. If the symbol is weak and |
3385 | undefined, it may remain undefined at link-time, in which | |
3386 | case it will have a zero value and almost certainly be out | |
3387 | of range for a direct call; thus, relax for undefined weak | |
3388 | symbols even if longcalls is not enabled. */ | |
8e6bc631 | 3389 | if (is_direct_call_opcode (insn->opcode) |
38f9cb7f | 3390 | && ! pc_frag->tc_frag_data.use_longcalls |
91d6fa6a NC |
3391 | && (! S_IS_WEAK (exp->X_add_symbol) |
3392 | || S_IS_DEFINED (exp->X_add_symbol))) | |
7c834684 | 3393 | return TRUE; |
7c834684 | 3394 | |
8e6bc631 BW |
3395 | return FALSE; |
3396 | } | |
e0001a05 | 3397 | |
91d6fa6a | 3398 | symbolP = exp->X_add_symbol; |
7fa3d080 | 3399 | sym_frag = symbol_get_frag (symbolP); |
91d6fa6a | 3400 | target = S_GET_VALUE (symbolP) + exp->X_add_number; |
7fa3d080 | 3401 | pc = pc_frag->fr_address + pc_offset; |
e0001a05 | 3402 | |
7fa3d080 BW |
3403 | /* If frag has yet to be reached on this pass, assume it |
3404 | will move by STRETCH just as we did. If this is not so, | |
3405 | it will be because some frag between grows, and that will | |
3406 | force another pass. Beware zero-length frags. There | |
3407 | should be a faster way to do this. */ | |
3408 | ||
3409 | if (stretch != 0 | |
3410 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3411 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3412 | { | |
3413 | target += stretch; | |
3414 | } | |
c138bc38 | 3415 | |
7fa3d080 BW |
3416 | new_offset = target; |
3417 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3418 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3419 | return FALSE; | |
3420 | break; | |
3421 | ||
3422 | default: | |
3423 | /* The symbol should have a fixup associated with it. */ | |
3424 | return FALSE; | |
3425 | } | |
3426 | } | |
3427 | ||
3428 | return TRUE; | |
e0001a05 NC |
3429 | } |
3430 | ||
3431 | ||
43cd72b9 | 3432 | /* Return TRUE on success. */ |
e0001a05 | 3433 | |
7fa3d080 BW |
3434 | static bfd_boolean |
3435 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3436 | { |
3437 | BuildOp *op; | |
3438 | symbolS *sym; | |
3439 | ||
60242db2 | 3440 | tinsn_init (targ); |
b224e962 BW |
3441 | targ->debug_line = insn->debug_line; |
3442 | targ->loc_directive_seen = insn->loc_directive_seen; | |
e0001a05 NC |
3443 | switch (bi->typ) |
3444 | { | |
3445 | case INSTR_INSTR: | |
3446 | op = bi->ops; | |
3447 | targ->opcode = bi->opcode; | |
3448 | targ->insn_type = ITYPE_INSN; | |
3449 | targ->is_specific_opcode = FALSE; | |
3450 | ||
3451 | for (; op != NULL; op = op->next) | |
3452 | { | |
3453 | int op_num = op->op_num; | |
3454 | int op_data = op->op_data; | |
3455 | ||
9c2799c2 | 3456 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3457 | |
3458 | if (targ->ntok <= op_num) | |
3459 | targ->ntok = op_num + 1; | |
3460 | ||
3461 | switch (op->typ) | |
3462 | { | |
3463 | case OP_CONSTANT: | |
3464 | set_expr_const (&targ->tok[op_num], op_data); | |
3465 | break; | |
3466 | case OP_OPERAND: | |
9c2799c2 | 3467 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3468 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3469 | break; | |
19e8f41a BW |
3470 | case OP_FREEREG: |
3471 | if (insn->extra_arg.X_op != O_register) | |
3472 | return FALSE; | |
3473 | copy_expr (&targ->tok[op_num], &insn->extra_arg); | |
3474 | break; | |
e0001a05 NC |
3475 | case OP_LITERAL: |
3476 | sym = get_special_literal_symbol (); | |
3477 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
28dbbc02 BW |
3478 | if (insn->tok[op_data].X_op == O_tlsfunc |
3479 | || insn->tok[op_data].X_op == O_tlsarg) | |
19e8f41a | 3480 | copy_expr (&targ->extra_arg, &insn->tok[op_data]); |
e0001a05 NC |
3481 | break; |
3482 | case OP_LABEL: | |
3483 | sym = get_special_label_symbol (); | |
3484 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3485 | break; | |
43cd72b9 BW |
3486 | case OP_OPERAND_HI16U: |
3487 | case OP_OPERAND_LOW16U: | |
9c2799c2 | 3488 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3489 | if (expr_is_const (&insn->tok[op_data])) |
3490 | { | |
3491 | long val; | |
3492 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3493 | val = xg_apply_userdef_op_fn (op->typ, | |
3494 | targ->tok[op_num]. | |
3495 | X_add_number); | |
3496 | targ->tok[op_num].X_add_number = val; | |
3497 | } | |
3498 | else | |
3499 | { | |
3500 | /* For const16 we can create relocations for these. */ | |
3501 | if (targ->opcode == XTENSA_UNDEFINED | |
3502 | || (targ->opcode != xtensa_const16_opcode)) | |
3503 | return FALSE; | |
9c2799c2 | 3504 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3505 | /* Need to build a O_lo16 or O_hi16. */ |
3506 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3507 | if (targ->tok[op_num].X_op == O_symbol) | |
3508 | { | |
3509 | if (op->typ == OP_OPERAND_HI16U) | |
3510 | targ->tok[op_num].X_op = O_hi16; | |
3511 | else if (op->typ == OP_OPERAND_LOW16U) | |
3512 | targ->tok[op_num].X_op = O_lo16; | |
3513 | else | |
3514 | return FALSE; | |
3515 | } | |
3516 | } | |
3517 | break; | |
e0001a05 NC |
3518 | default: |
3519 | /* currently handles: | |
3520 | OP_OPERAND_LOW8 | |
3521 | OP_OPERAND_HI24S | |
3522 | OP_OPERAND_F32MINUS */ | |
3523 | if (xg_has_userdef_op_fn (op->typ)) | |
3524 | { | |
9c2799c2 | 3525 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3526 | if (expr_is_const (&insn->tok[op_data])) |
3527 | { | |
3528 | long val; | |
3529 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3530 | val = xg_apply_userdef_op_fn (op->typ, | |
3531 | targ->tok[op_num]. | |
3532 | X_add_number); | |
3533 | targ->tok[op_num].X_add_number = val; | |
3534 | } | |
3535 | else | |
3536 | return FALSE; /* We cannot use a relocation for this. */ | |
3537 | break; | |
3538 | } | |
9c2799c2 | 3539 | gas_assert (0); |
e0001a05 NC |
3540 | break; |
3541 | } | |
3542 | } | |
3543 | break; | |
3544 | ||
3545 | case INSTR_LITERAL_DEF: | |
3546 | op = bi->ops; | |
3547 | targ->opcode = XTENSA_UNDEFINED; | |
3548 | targ->insn_type = ITYPE_LITERAL; | |
3549 | targ->is_specific_opcode = FALSE; | |
3550 | for (; op != NULL; op = op->next) | |
3551 | { | |
3552 | int op_num = op->op_num; | |
3553 | int op_data = op->op_data; | |
9c2799c2 | 3554 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3555 | |
3556 | if (targ->ntok <= op_num) | |
3557 | targ->ntok = op_num + 1; | |
3558 | ||
3559 | switch (op->typ) | |
3560 | { | |
3561 | case OP_OPERAND: | |
9c2799c2 | 3562 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3563 | /* We can only pass resolvable literals through. */ |
3564 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3565 | return FALSE; | |
e0001a05 NC |
3566 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3567 | break; | |
3568 | case OP_LITERAL: | |
3569 | case OP_CONSTANT: | |
3570 | case OP_LABEL: | |
3571 | default: | |
9c2799c2 | 3572 | gas_assert (0); |
e0001a05 NC |
3573 | break; |
3574 | } | |
3575 | } | |
3576 | break; | |
3577 | ||
3578 | case INSTR_LABEL_DEF: | |
3579 | op = bi->ops; | |
3580 | targ->opcode = XTENSA_UNDEFINED; | |
3581 | targ->insn_type = ITYPE_LABEL; | |
3582 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3583 | /* Literal with no ops is a label? */ |
9c2799c2 | 3584 | gas_assert (op == NULL); |
e0001a05 NC |
3585 | break; |
3586 | ||
3587 | default: | |
9c2799c2 | 3588 | gas_assert (0); |
e0001a05 NC |
3589 | } |
3590 | ||
3591 | return TRUE; | |
3592 | } | |
3593 | ||
3594 | ||
43cd72b9 | 3595 | /* Return TRUE on success. */ |
e0001a05 | 3596 | |
7fa3d080 BW |
3597 | static bfd_boolean |
3598 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3599 | { |
3600 | for (; bi != NULL; bi = bi->next) | |
3601 | { | |
3602 | TInsn *next_insn = istack_push_space (istack); | |
3603 | ||
3604 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3605 | return FALSE; | |
3606 | } | |
3607 | return TRUE; | |
3608 | } | |
3609 | ||
3610 | ||
43cd72b9 | 3611 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3612 | |
7fa3d080 BW |
3613 | static bfd_boolean |
3614 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3615 | { |
3616 | int stack_size = istack->ninsn; | |
3617 | int steps_taken = 0; | |
43cd72b9 | 3618 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3619 | TransitionList *l; |
3620 | ||
9c2799c2 NC |
3621 | gas_assert (insn->insn_type == ITYPE_INSN); |
3622 | gas_assert (insn->opcode < table->num_opcodes); | |
e0001a05 NC |
3623 | |
3624 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3625 | { | |
3626 | TransitionRule *rule = l->rule; | |
3627 | ||
3628 | if (xg_instruction_matches_rule (insn, rule)) | |
3629 | { | |
3630 | if (lateral_steps == steps_taken) | |
3631 | { | |
3632 | int i; | |
3633 | ||
3634 | /* This is it. Expand the rule to the stack. */ | |
3635 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3636 | return FALSE; | |
3637 | ||
3638 | /* Check to see if it fits. */ | |
3639 | for (i = stack_size; i < istack->ninsn; i++) | |
3640 | { | |
91d6fa6a | 3641 | TInsn *tinsn = &istack->insn[i]; |
e0001a05 | 3642 | |
91d6fa6a NC |
3643 | if (tinsn->insn_type == ITYPE_INSN |
3644 | && !tinsn_has_symbolic_operands (tinsn) | |
3645 | && !xg_immeds_fit (tinsn)) | |
e0001a05 NC |
3646 | { |
3647 | istack->ninsn = stack_size; | |
3648 | return FALSE; | |
3649 | } | |
3650 | } | |
3651 | return TRUE; | |
3652 | } | |
3653 | steps_taken++; | |
3654 | } | |
3655 | } | |
3656 | return FALSE; | |
3657 | } | |
3658 | ||
43cd72b9 | 3659 | \f |
43cd72b9 | 3660 | /* Relax the assembly instruction at least "min_steps". |
b81bf389 BW |
3661 | Return the number of steps taken. |
3662 | ||
3663 | For relaxation to correctly terminate, every relaxation chain must | |
3664 | terminate in one of two ways: | |
3665 | ||
3666 | 1. If the chain from one instruction to the next consists entirely of | |
3667 | single instructions, then the chain *must* handle all possible | |
3668 | immediates without failing. It must not ever fail because an | |
3669 | immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation | |
3670 | chain is one example. L32R loads 32 bits, and there cannot be an | |
3671 | immediate larger than 32 bits, so it satisfies this condition. | |
3672 | Single instruction relaxation chains are as defined by | |
3673 | xg_is_single_relaxable_instruction. | |
3674 | ||
3675 | 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., | |
3676 | BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J | |
3677 | ||
3678 | Strictly speaking, in most cases you can violate condition 1 and be OK | |
3679 | -- in particular when the last two instructions have the same single | |
3680 | size. But nevertheless, you should guarantee the above two conditions. | |
3681 | ||
3682 | We could fix this so that single-instruction expansions correctly | |
3683 | terminate when they can't handle the range, but the error messages are | |
3684 | worse, and it actually turns out that in every case but one (18-bit wide | |
3685 | branches), you need a multi-instruction expansion to get the full range | |
3686 | anyway. And because 18-bit branches are handled identically to 15-bit | |
3687 | branches, there isn't any point in changing it. */ | |
e0001a05 | 3688 | |
7fa3d080 BW |
3689 | static int |
3690 | xg_assembly_relax (IStack *istack, | |
3691 | TInsn *insn, | |
3692 | segT pc_seg, | |
3693 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3694 | offsetT pc_offset, /* offset in fragment */ | |
3695 | int min_steps, /* minimum conversion steps */ | |
3696 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3697 | { |
3698 | int steps_taken = 0; | |
3699 | ||
b81bf389 BW |
3700 | /* Some of its immeds don't fit. Try to build a relaxed version. |
3701 | This may go through a couple of stages of single instruction | |
3702 | transformations before we get there. */ | |
e0001a05 NC |
3703 | |
3704 | TInsn single_target; | |
3705 | TInsn current_insn; | |
3706 | int lateral_steps = 0; | |
3707 | int istack_size = istack->ninsn; | |
3708 | ||
3709 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3710 | && steps_taken >= min_steps) | |
3711 | { | |
3712 | istack_push (istack, insn); | |
3713 | return steps_taken; | |
3714 | } | |
43cd72b9 | 3715 | current_insn = *insn; |
e0001a05 | 3716 | |
7c834684 | 3717 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3718 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3719 | { |
21af2bbd | 3720 | steps_taken++; |
e0001a05 NC |
3721 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3722 | stretch)) | |
3723 | { | |
e0001a05 NC |
3724 | if (steps_taken >= min_steps) |
3725 | { | |
3726 | istack_push (istack, &single_target); | |
3727 | return steps_taken; | |
3728 | } | |
3729 | } | |
43cd72b9 | 3730 | current_insn = single_target; |
e0001a05 NC |
3731 | } |
3732 | ||
3733 | /* Now check for a multi-instruction expansion. */ | |
3734 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3735 | { | |
3736 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3737 | stretch)) | |
3738 | { | |
3739 | if (steps_taken >= min_steps) | |
3740 | { | |
3741 | istack_push (istack, ¤t_insn); | |
3742 | return steps_taken; | |
3743 | } | |
3744 | } | |
3745 | steps_taken++; | |
3746 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3747 | { | |
3748 | if (steps_taken >= min_steps) | |
3749 | return steps_taken; | |
3750 | } | |
3751 | lateral_steps++; | |
3752 | istack->ninsn = istack_size; | |
3753 | } | |
3754 | ||
3755 | /* It's not going to work -- use the original. */ | |
3756 | istack_push (istack, insn); | |
3757 | return steps_taken; | |
3758 | } | |
3759 | ||
3760 | ||
7fa3d080 BW |
3761 | static void |
3762 | xg_finish_frag (char *last_insn, | |
3763 | enum xtensa_relax_statesE frag_state, | |
3764 | enum xtensa_relax_statesE slot0_state, | |
3765 | int max_growth, | |
3766 | bfd_boolean is_insn) | |
e0001a05 NC |
3767 | { |
3768 | /* Finish off this fragment so that it has at LEAST the desired | |
3769 | max_growth. If it doesn't fit in this fragment, close this one | |
3770 | and start a new one. In either case, return a pointer to the | |
3771 | beginning of the growth area. */ | |
3772 | ||
3773 | fragS *old_frag; | |
43cd72b9 | 3774 | |
542f8b94 | 3775 | frag_grow (max_growth); |
e0001a05 NC |
3776 | old_frag = frag_now; |
3777 | ||
3778 | frag_now->fr_opcode = last_insn; | |
3779 | if (is_insn) | |
3780 | frag_now->tc_frag_data.is_insn = TRUE; | |
3781 | ||
3782 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3783 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3784 | ||
3785 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3786 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3787 | |
3788 | /* Just to make sure that we did not split it up. */ | |
9c2799c2 | 3789 | gas_assert (old_frag->fr_next == frag_now); |
e0001a05 NC |
3790 | } |
3791 | ||
3792 | ||
7fa3d080 BW |
3793 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3794 | ||
3795 | static bfd_boolean | |
3796 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3797 | { | |
3798 | if (fragP == NULL) | |
3799 | return FALSE; | |
3800 | ||
3801 | for (; fragP; fragP = fragP->fr_next) | |
3802 | { | |
3803 | if (fragP == target) | |
3804 | return TRUE; | |
3805 | if (fragP->fr_fix != 0) | |
3806 | return FALSE; | |
3807 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3808 | return FALSE; | |
3809 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3810 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3811 | return FALSE; | |
3812 | if (fragP->fr_type == rs_space) | |
3813 | return FALSE; | |
3814 | } | |
3815 | return FALSE; | |
3816 | } | |
3817 | ||
3818 | ||
e0001a05 | 3819 | static bfd_boolean |
7fa3d080 | 3820 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3821 | { |
3822 | xtensa_isa isa = xtensa_default_isa; | |
3823 | int i; | |
43cd72b9 | 3824 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3825 | int target_op = -1; |
3826 | symbolS *sym; | |
3827 | fragS *target_frag; | |
3828 | ||
64b607e6 BW |
3829 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3830 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
e0001a05 NC |
3831 | return FALSE; |
3832 | ||
3833 | for (i = 0; i < num_ops; i++) | |
3834 | { | |
43cd72b9 | 3835 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3836 | { |
3837 | target_op = i; | |
3838 | break; | |
3839 | } | |
3840 | } | |
3841 | if (target_op == -1) | |
3842 | return FALSE; | |
3843 | ||
3844 | if (insn->ntok <= target_op) | |
3845 | return FALSE; | |
3846 | ||
3847 | if (insn->tok[target_op].X_op != O_symbol) | |
3848 | return FALSE; | |
3849 | ||
3850 | sym = insn->tok[target_op].X_add_symbol; | |
3851 | if (sym == NULL) | |
3852 | return FALSE; | |
3853 | ||
3854 | if (insn->tok[target_op].X_add_number != 0) | |
3855 | return FALSE; | |
3856 | ||
3857 | target_frag = symbol_get_frag (sym); | |
3858 | if (target_frag == NULL) | |
3859 | return FALSE; | |
3860 | ||
c138bc38 | 3861 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3862 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3863 | return TRUE; | |
3864 | ||
3865 | return FALSE; | |
3866 | } | |
3867 | ||
3868 | ||
3869 | static void | |
7fa3d080 | 3870 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3871 | { |
3872 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3873 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3874 | |
7fa3d080 BW |
3875 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3876 | { | |
3877 | int i = 1; | |
3878 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3879 | && insn->tok[i].X_op == O_symbol) | |
3880 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3881 | return; | |
3882 | } | |
e0001a05 | 3883 | |
7fa3d080 BW |
3884 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3885 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3886 | { |
7fa3d080 BW |
3887 | int i; |
3888 | ||
3889 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3890 | { | |
3891 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3892 | && insn->tok[i].X_op == O_symbol) | |
3893 | { | |
3894 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3895 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3896 | if (S_IS_DEFINED (sym)) | |
3897 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3898 | } | |
3899 | } | |
e0001a05 | 3900 | } |
e0001a05 NC |
3901 | } |
3902 | ||
3903 | ||
43cd72b9 | 3904 | /* Return FALSE if no error. */ |
e0001a05 | 3905 | |
7fa3d080 BW |
3906 | static bfd_boolean |
3907 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3908 | { |
3909 | int num_ops = 0; | |
3910 | BuildOp *b_op; | |
3911 | ||
3912 | switch (instr_spec->typ) | |
3913 | { | |
3914 | case INSTR_INSTR: | |
3915 | new_insn->insn_type = ITYPE_INSN; | |
3916 | new_insn->opcode = instr_spec->opcode; | |
e0001a05 NC |
3917 | break; |
3918 | case INSTR_LITERAL_DEF: | |
3919 | new_insn->insn_type = ITYPE_LITERAL; | |
3920 | new_insn->opcode = XTENSA_UNDEFINED; | |
e0001a05 NC |
3921 | break; |
3922 | case INSTR_LABEL_DEF: | |
b224e962 | 3923 | abort (); |
e0001a05 | 3924 | } |
b224e962 BW |
3925 | new_insn->is_specific_opcode = FALSE; |
3926 | new_insn->debug_line = old_insn->debug_line; | |
3927 | new_insn->loc_directive_seen = old_insn->loc_directive_seen; | |
e0001a05 NC |
3928 | |
3929 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3930 | { | |
3931 | expressionS *exp; | |
3932 | const expressionS *src_exp; | |
3933 | ||
3934 | num_ops++; | |
3935 | switch (b_op->typ) | |
3936 | { | |
3937 | case OP_CONSTANT: | |
3938 | /* The expression must be the constant. */ | |
9c2799c2 | 3939 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3940 | exp = &new_insn->tok[b_op->op_num]; |
3941 | set_expr_const (exp, b_op->op_data); | |
3942 | break; | |
3943 | ||
3944 | case OP_OPERAND: | |
9c2799c2 NC |
3945 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
3946 | gas_assert (b_op->op_data < (unsigned) old_insn->ntok); | |
e0001a05 NC |
3947 | src_exp = &old_insn->tok[b_op->op_data]; |
3948 | exp = &new_insn->tok[b_op->op_num]; | |
3949 | copy_expr (exp, src_exp); | |
3950 | break; | |
3951 | ||
3952 | case OP_LITERAL: | |
3953 | case OP_LABEL: | |
3954 | as_bad (_("can't handle generation of literal/labels yet")); | |
9c2799c2 | 3955 | gas_assert (0); |
e0001a05 NC |
3956 | |
3957 | default: | |
3958 | as_bad (_("can't handle undefined OP TYPE")); | |
9c2799c2 | 3959 | gas_assert (0); |
e0001a05 NC |
3960 | } |
3961 | } | |
3962 | ||
3963 | new_insn->ntok = num_ops; | |
3964 | return FALSE; | |
3965 | } | |
3966 | ||
3967 | ||
43cd72b9 | 3968 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3969 | |
7fa3d080 BW |
3970 | static bfd_boolean |
3971 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3972 | { |
43cd72b9 | 3973 | TransitionRule *rule; |
e0001a05 | 3974 | BuildInstr *insn_spec; |
43cd72b9 BW |
3975 | |
3976 | if (old_insn->is_specific_opcode || !density_supported) | |
3977 | return FALSE; | |
3978 | ||
3979 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3980 | if (rule == NULL) |
3981 | return FALSE; | |
3982 | ||
3983 | insn_spec = rule->to_instr; | |
3984 | /* There should only be one. */ | |
9c2799c2 NC |
3985 | gas_assert (insn_spec != NULL); |
3986 | gas_assert (insn_spec->next == NULL); | |
e0001a05 NC |
3987 | if (insn_spec->next != NULL) |
3988 | return FALSE; | |
3989 | ||
3990 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3991 | ||
3992 | return TRUE; | |
3993 | } | |
3994 | ||
3995 | ||
3996 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3997 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
3998 | tokens into the stack or relax it and place multiple |
3999 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
4000 | |
4001 | static bfd_boolean | |
7fa3d080 | 4002 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
4003 | { |
4004 | int noperands; | |
4005 | TInsn new_insn; | |
7c834684 BW |
4006 | bfd_boolean do_expand; |
4007 | ||
60242db2 | 4008 | tinsn_init (&new_insn); |
e0001a05 | 4009 | |
43cd72b9 BW |
4010 | /* Narrow it if we can. xg_simplify_insn now does all the |
4011 | appropriate checking (e.g., for the density option). */ | |
4012 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
4013 | orig_insn = &new_insn; | |
e0001a05 | 4014 | |
43cd72b9 BW |
4015 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
4016 | orig_insn->opcode); | |
e0001a05 NC |
4017 | if (orig_insn->ntok < noperands) |
4018 | { | |
992a06ee AM |
4019 | as_bad (ngettext ("found %d operand for '%s': Expected %d", |
4020 | "found %d operands for '%s': Expected %d", | |
4021 | orig_insn->ntok), | |
e0001a05 NC |
4022 | orig_insn->ntok, |
4023 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
4024 | noperands); | |
4025 | return TRUE; | |
4026 | } | |
4027 | if (orig_insn->ntok > noperands) | |
992a06ee AM |
4028 | as_warn (ngettext ("found %d operand for '%s': Expected %d", |
4029 | "found %d operands for '%s': Expected %d", | |
4030 | orig_insn->ntok), | |
e0001a05 NC |
4031 | orig_insn->ntok, |
4032 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
4033 | noperands); | |
4034 | ||
43cd72b9 | 4035 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 4036 | are too many, just cut out the extras here. */ |
e0001a05 NC |
4037 | orig_insn->ntok = noperands; |
4038 | ||
e0001a05 NC |
4039 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
4040 | return TRUE; | |
4041 | ||
d12f9798 BW |
4042 | /* Special case for extui opcode which has constraints not handled |
4043 | by the ordinary operand encoding checks. The number of operands | |
4044 | and related syntax issues have already been checked. */ | |
4045 | if (orig_insn->opcode == xtensa_extui_opcode) | |
4046 | { | |
4047 | int shiftimm = orig_insn->tok[2].X_add_number; | |
4048 | int maskimm = orig_insn->tok[3].X_add_number; | |
4049 | if (shiftimm + maskimm > 32) | |
4050 | { | |
4051 | as_bad (_("immediate operands sum to greater than 32")); | |
4052 | return TRUE; | |
4053 | } | |
4054 | } | |
4055 | ||
7c834684 BW |
4056 | /* If the instruction will definitely need to be relaxed, it is better |
4057 | to expand it now for better scheduling. Decide whether to expand | |
4058 | now.... */ | |
4059 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
4060 | ||
4061 | /* Calls should be expanded to longcalls only in the backend relaxation | |
4062 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
4063 | adjacent. */ | |
4064 | if (is_direct_call_opcode (orig_insn->opcode)) | |
4065 | do_expand = FALSE; | |
e0001a05 NC |
4066 | |
4067 | if (tinsn_has_symbolic_operands (orig_insn)) | |
4068 | { | |
7c834684 BW |
4069 | /* The values of symbolic operands are not known yet, so only expand |
4070 | now if an operand is "complex" (e.g., difference of symbols) and | |
4071 | will have to be stored as a literal regardless of the value. */ | |
4072 | if (!tinsn_has_complex_operands (orig_insn)) | |
4073 | do_expand = FALSE; | |
e0001a05 | 4074 | } |
7c834684 BW |
4075 | else if (xg_immeds_fit (orig_insn)) |
4076 | do_expand = FALSE; | |
4077 | ||
4078 | if (do_expand) | |
4079 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 4080 | else |
7c834684 | 4081 | istack_push (istack, orig_insn); |
e0001a05 | 4082 | |
e0001a05 NC |
4083 | return FALSE; |
4084 | } | |
4085 | ||
4086 | ||
7fa3d080 | 4087 | /* Return TRUE if the section flags are marked linkonce |
74869ac7 BW |
4088 | or the name is .gnu.linkonce.*. */ |
4089 | ||
4090 | static int linkonce_len = sizeof (".gnu.linkonce.") - 1; | |
7fa3d080 BW |
4091 | |
4092 | static bfd_boolean | |
4093 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
4094 | { | |
4095 | flagword flags, link_once_flags; | |
4096 | ||
4097 | flags = bfd_get_section_flags (abfd, sec); | |
4098 | link_once_flags = (flags & SEC_LINK_ONCE); | |
4099 | ||
4100 | /* Flags might not be set yet. */ | |
74869ac7 BW |
4101 | if (!link_once_flags |
4102 | && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) | |
4103 | link_once_flags = SEC_LINK_ONCE; | |
7fa3d080 | 4104 | |
7fa3d080 BW |
4105 | return (link_once_flags != 0); |
4106 | } | |
4107 | ||
4108 | ||
4109 | static void | |
4110 | xtensa_add_literal_sym (symbolS *sym) | |
4111 | { | |
4112 | sym_list *l; | |
4113 | ||
325801bd | 4114 | l = XNEW (sym_list); |
7fa3d080 BW |
4115 | l->sym = sym; |
4116 | l->next = literal_syms; | |
4117 | literal_syms = l; | |
4118 | } | |
4119 | ||
4120 | ||
4121 | static symbolS * | |
4122 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
4123 | { | |
4124 | static int lit_num = 0; | |
4125 | static char name[256]; | |
4126 | symbolS *symbolP; | |
4127 | ||
4128 | sprintf (name, ".L_lit_sym%d", lit_num); | |
4129 | ||
4130 | /* Create a local symbol. If it is in a linkonce section, we have to | |
4131 | be careful to make sure that if it is used in a relocation that the | |
4132 | symbol will be in the output file. */ | |
4133 | if (get_is_linkonce_section (stdoutput, sec)) | |
4134 | { | |
4135 | symbolP = symbol_new (name, sec, 0, frag); | |
4136 | S_CLEAR_EXTERNAL (symbolP); | |
4137 | /* symbolP->local = 1; */ | |
4138 | } | |
4139 | else | |
4140 | symbolP = symbol_new (name, sec, 0, frag); | |
4141 | ||
4142 | xtensa_add_literal_sym (symbolP); | |
4143 | ||
7fa3d080 BW |
4144 | lit_num++; |
4145 | return symbolP; | |
4146 | } | |
4147 | ||
4148 | ||
e0001a05 NC |
4149 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
4150 | ||
7fa3d080 BW |
4151 | static symbolS * |
4152 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
4153 | { |
4154 | emit_state state; | |
4155 | symbolS *lit_sym = NULL; | |
bbdd25a8 | 4156 | bfd_reloc_code_real_type reloc; |
1bbb5f21 | 4157 | bfd_boolean pcrel = FALSE; |
bbdd25a8 | 4158 | char *p; |
e0001a05 NC |
4159 | |
4160 | /* size = 4 for L32R. It could easily be larger when we move to | |
4161 | larger constants. Add a parameter later. */ | |
4162 | offsetT litsize = 4; | |
4163 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4164 | expressionS saved_loc; | |
43cd72b9 BW |
4165 | expressionS * emit_val; |
4166 | ||
e0001a05 NC |
4167 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4168 | ||
9c2799c2 NC |
4169 | gas_assert (insn->insn_type == ITYPE_LITERAL); |
4170 | gas_assert (insn->ntok == 1); /* must be only one token here */ | |
e0001a05 NC |
4171 | |
4172 | xtensa_switch_to_literal_fragment (&state); | |
4173 | ||
43cd72b9 BW |
4174 | emit_val = &insn->tok[0]; |
4175 | if (emit_val->X_op == O_big) | |
4176 | { | |
4177 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4178 | if (size > litsize) | |
4179 | { | |
4180 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4181 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4182 | _("invalid immediate")); |
4183 | xtensa_restore_emit_state (&state); | |
4184 | return NULL; | |
4185 | } | |
4186 | } | |
4187 | ||
e0001a05 NC |
4188 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4189 | literals done with this function have a frag to themselves. That's | |
4190 | important for the way text section literals work. */ | |
4191 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4192 | record_alignment (now_seg, litalign); |
e0001a05 | 4193 | |
bbdd25a8 | 4194 | switch (emit_val->X_op) |
43cd72b9 | 4195 | { |
1bbb5f21 BW |
4196 | case O_pcrel: |
4197 | pcrel = TRUE; | |
4198 | /* fall through */ | |
bbdd25a8 | 4199 | case O_pltrel: |
28dbbc02 BW |
4200 | case O_tlsfunc: |
4201 | case O_tlsarg: | |
4202 | case O_tpoff: | |
4203 | case O_dtpoff: | |
bbdd25a8 | 4204 | p = frag_more (litsize); |
43cd72b9 | 4205 | xtensa_set_frag_assembly_state (frag_now); |
28dbbc02 | 4206 | reloc = map_operator_to_reloc (emit_val->X_op, TRUE); |
43cd72b9 BW |
4207 | if (emit_val->X_add_symbol) |
4208 | emit_val->X_op = O_symbol; | |
4209 | else | |
4210 | emit_val->X_op = O_constant; | |
4211 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 4212 | litsize, emit_val, pcrel, reloc); |
bbdd25a8 BW |
4213 | break; |
4214 | ||
4215 | default: | |
4216 | emit_expr (emit_val, litsize); | |
4217 | break; | |
43cd72b9 | 4218 | } |
e0001a05 | 4219 | |
9c2799c2 | 4220 | gas_assert (frag_now->tc_frag_data.literal_frag == NULL); |
e0001a05 NC |
4221 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); |
4222 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4223 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4224 | |
4225 | /* Go back. */ | |
4226 | xtensa_restore_emit_state (&state); | |
4227 | return lit_sym; | |
4228 | } | |
4229 | ||
4230 | ||
4231 | static void | |
7fa3d080 | 4232 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4233 | { |
4234 | emit_state state; | |
43cd72b9 | 4235 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4236 | takes effect if something is placed here. */ |
4237 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4238 | fragS *lit_saved_frag; | |
4239 | ||
9c2799c2 | 4240 | gas_assert (size % 4 == 0); |
e0001a05 NC |
4241 | |
4242 | xtensa_switch_to_literal_fragment (&state); | |
4243 | ||
4244 | /* Force a 4-byte align here. */ | |
4245 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4246 | record_alignment (now_seg, litalign); |
e0001a05 | 4247 | |
542f8b94 | 4248 | frag_grow (size); |
e0001a05 NC |
4249 | |
4250 | lit_saved_frag = frag_now; | |
4251 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4252 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
43cd72b9 | 4253 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4254 | |
4255 | /* Go back. */ | |
4256 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4257 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4258 | } |
4259 | ||
4260 | ||
e0001a05 | 4261 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4262 | Return TRUE on success. */ |
e0001a05 | 4263 | |
7fa3d080 BW |
4264 | static bfd_boolean |
4265 | xg_add_opcode_fix (TInsn *tinsn, | |
4266 | int opnum, | |
4267 | xtensa_format fmt, | |
4268 | int slot, | |
91d6fa6a | 4269 | expressionS *exp, |
7fa3d080 BW |
4270 | fragS *fragP, |
4271 | offsetT offset) | |
43cd72b9 BW |
4272 | { |
4273 | xtensa_opcode opcode = tinsn->opcode; | |
4274 | bfd_reloc_code_real_type reloc; | |
4275 | reloc_howto_type *howto; | |
4276 | int fmt_length; | |
e0001a05 NC |
4277 | fixS *the_fix; |
4278 | ||
43cd72b9 BW |
4279 | reloc = BFD_RELOC_NONE; |
4280 | ||
4281 | /* First try the special cases for "alternate" relocs. */ | |
4282 | if (opcode == xtensa_l32r_opcode) | |
4283 | { | |
4284 | if (fragP->tc_frag_data.use_absolute_literals) | |
4285 | reloc = encode_alt_reloc (slot); | |
4286 | } | |
4287 | else if (opcode == xtensa_const16_opcode) | |
4288 | { | |
91d6fa6a | 4289 | if (exp->X_op == O_lo16) |
43cd72b9 BW |
4290 | { |
4291 | reloc = encode_reloc (slot); | |
91d6fa6a | 4292 | exp->X_op = O_symbol; |
43cd72b9 | 4293 | } |
91d6fa6a | 4294 | else if (exp->X_op == O_hi16) |
43cd72b9 BW |
4295 | { |
4296 | reloc = encode_alt_reloc (slot); | |
91d6fa6a | 4297 | exp->X_op = O_symbol; |
43cd72b9 BW |
4298 | } |
4299 | } | |
4300 | ||
4301 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4302 | { |
43cd72b9 | 4303 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4304 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4305 | return FALSE; |
4306 | } | |
4307 | ||
43cd72b9 BW |
4308 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4309 | into the symbol table where the generic portions of the assembler | |
4310 | won't know what to do with them. */ | |
91d6fa6a | 4311 | if (exp->X_op == O_lo16 || exp->X_op == O_hi16) |
43cd72b9 BW |
4312 | { |
4313 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4314 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4315 | return FALSE; |
4316 | } | |
4317 | ||
4318 | /* Next try the generic relocs. */ | |
4319 | if (reloc == BFD_RELOC_NONE) | |
4320 | reloc = encode_reloc (slot); | |
4321 | if (reloc == BFD_RELOC_NONE) | |
4322 | { | |
4323 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4324 | return FALSE; | |
4325 | } | |
e0001a05 | 4326 | |
43cd72b9 | 4327 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4328 | if (!howto) |
4329 | { | |
43cd72b9 | 4330 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4331 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4332 | return FALSE; | |
4333 | } | |
4334 | ||
43cd72b9 | 4335 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
91d6fa6a | 4336 | the_fix = fix_new_exp (fragP, offset, fmt_length, exp, |
e0001a05 | 4337 | howto->pc_relative, reloc); |
d9740523 | 4338 | the_fix->fx_no_overflow = 1; |
91d6fa6a NC |
4339 | the_fix->tc_fix_data.X_add_symbol = exp->X_add_symbol; |
4340 | the_fix->tc_fix_data.X_add_number = exp->X_add_number; | |
7fa3d080 | 4341 | the_fix->tc_fix_data.slot = slot; |
c138bc38 | 4342 | |
7fa3d080 BW |
4343 | return TRUE; |
4344 | } | |
4345 | ||
4346 | ||
4347 | static bfd_boolean | |
4348 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4349 | char *buf, |
4350 | fragS *fragP, | |
4351 | offsetT offset, | |
4352 | bfd_boolean build_fix) | |
4353 | { | |
4354 | static xtensa_insnbuf insnbuf = NULL; | |
4355 | bfd_boolean has_symbolic_immed = FALSE; | |
4356 | bfd_boolean ok = TRUE; | |
b2d179be | 4357 | |
7fa3d080 BW |
4358 | if (!insnbuf) |
4359 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4360 | ||
4361 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4362 | if (has_symbolic_immed && build_fix) | |
4363 | { | |
4364 | /* Add a fixup. */ | |
b2d179be BW |
4365 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4366 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4367 | int opnum = get_relaxable_immed (tinsn->opcode); |
4368 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4369 | |
b2d179be | 4370 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4371 | ok = FALSE; |
4372 | } | |
4373 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4374 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4375 | (unsigned char *) buf, 0); | |
7fa3d080 | 4376 | return ok; |
e0001a05 NC |
4377 | } |
4378 | ||
4379 | ||
7fa3d080 BW |
4380 | static void |
4381 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4382 | { |
4383 | symbolS *sym = get_special_literal_symbol (); | |
4384 | int i; | |
4385 | if (lit_sym == 0) | |
4386 | return; | |
9c2799c2 | 4387 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
4388 | for (i = 0; i < insn->ntok; i++) |
4389 | if (insn->tok[i].X_add_symbol == sym) | |
4390 | insn->tok[i].X_add_symbol = lit_sym; | |
4391 | ||
4392 | } | |
4393 | ||
4394 | ||
7fa3d080 BW |
4395 | static void |
4396 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4397 | { |
4398 | symbolS *sym = get_special_label_symbol (); | |
4399 | int i; | |
e0001a05 NC |
4400 | for (i = 0; i < insn->ntok; i++) |
4401 | if (insn->tok[i].X_add_symbol == sym) | |
4402 | insn->tok[i].X_add_symbol = label_sym; | |
4403 | ||
4404 | } | |
4405 | ||
4406 | ||
43cd72b9 | 4407 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4408 | integer register. */ |
4409 | ||
4410 | static bfd_boolean | |
7fa3d080 | 4411 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4412 | { |
4413 | int i; | |
4414 | int num_ops; | |
4415 | xtensa_isa isa = xtensa_default_isa; | |
4416 | ||
43cd72b9 | 4417 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4418 | |
4419 | for (i = 0; i < num_ops; i++) | |
4420 | { | |
43cd72b9 BW |
4421 | char inout; |
4422 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4423 | if ((inout == 'o' || inout == 'm') | |
4424 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4425 | { |
43cd72b9 BW |
4426 | xtensa_regfile opnd_rf = |
4427 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4428 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4429 | { |
4430 | if ((insn->tok[i].X_op == O_register) | |
4431 | && (insn->tok[i].X_add_number == regnum)) | |
4432 | return TRUE; | |
4433 | } | |
4434 | } | |
4435 | } | |
4436 | return FALSE; | |
4437 | } | |
4438 | ||
4439 | ||
4440 | static bfd_boolean | |
7fa3d080 | 4441 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4442 | { |
4443 | xtensa_opcode opcode = tinsn->opcode; | |
4444 | ||
4445 | if (opcode == XTENSA_UNDEFINED) | |
4446 | return FALSE; | |
4447 | ||
4448 | if (opcode == xtensa_call0_opcode | |
4449 | || opcode == xtensa_callx0_opcode | |
4450 | || opcode == xtensa_call4_opcode | |
4451 | || opcode == xtensa_callx4_opcode | |
4452 | || opcode == xtensa_call8_opcode | |
4453 | || opcode == xtensa_callx8_opcode | |
4454 | || opcode == xtensa_call12_opcode | |
4455 | || opcode == xtensa_callx12_opcode | |
4456 | || opcode == xtensa_isync_opcode | |
4457 | || opcode == xtensa_ret_opcode | |
4458 | || opcode == xtensa_ret_n_opcode | |
4459 | || opcode == xtensa_retw_opcode | |
4460 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4461 | || opcode == xtensa_waiti_opcode |
4462 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4463 | return TRUE; |
c138bc38 | 4464 | |
e0001a05 NC |
4465 | return FALSE; |
4466 | } | |
4467 | ||
4468 | ||
4469 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4470 | This allows the debugger to add unaligned labels. | |
4471 | Also, the assembler generates stabs labels that need | |
4472 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4473 | ||
7fa3d080 BW |
4474 | static bfd_boolean |
4475 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4476 | { |
4477 | const char *name = S_GET_NAME (sym); | |
4478 | static size_t fake_size = 0; | |
4479 | ||
4480 | if (name | |
4481 | && name[0] == '.' | |
4482 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4483 | return TRUE; | |
4484 | ||
4485 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4486 | if (fake_size == 0) | |
4487 | fake_size = strlen (FAKE_LABEL_NAME); | |
4488 | ||
43cd72b9 | 4489 | if (name |
e0001a05 NC |
4490 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4491 | && (name[fake_size] == 'F' | |
4492 | || name[fake_size] == 'L' | |
4493 | || (name[fake_size] == 'e' | |
4494 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4495 | return TRUE; | |
4496 | ||
4497 | return FALSE; | |
4498 | } | |
4499 | ||
4500 | ||
7fa3d080 BW |
4501 | static fragS * |
4502 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4503 | { |
4504 | fragS *next_fragP = fragP->fr_next; | |
4505 | ||
c138bc38 | 4506 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4507 | So we have to skip until we find something legit. */ |
4508 | while (next_fragP && next_fragP->fr_fix == 0) | |
4509 | next_fragP = next_fragP->fr_next; | |
4510 | ||
4511 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4512 | return NULL; | |
4513 | ||
4514 | return next_fragP; | |
4515 | } | |
4516 | ||
4517 | ||
43cd72b9 | 4518 | static bfd_boolean |
7fa3d080 | 4519 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4520 | { |
4521 | xtensa_opcode out_opcode; | |
4522 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4523 | ||
4524 | if (next_fragP == NULL) | |
4525 | return FALSE; | |
4526 | ||
4527 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4528 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4529 | { | |
4530 | *opcode = out_opcode; | |
4531 | return TRUE; | |
4532 | } | |
4533 | return FALSE; | |
4534 | } | |
4535 | ||
4536 | ||
4537 | static int | |
7fa3d080 | 4538 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4539 | { |
e0001a05 NC |
4540 | static xtensa_insnbuf insnbuf = NULL; |
4541 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4542 | xtensa_format fmt; |
c138bc38 | 4543 | int fmt_size; |
e0001a05 NC |
4544 | |
4545 | if (!insnbuf) | |
4546 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4547 | ||
43cd72b9 BW |
4548 | if (fragP == NULL) |
4549 | return XTENSA_UNDEFINED; | |
4550 | ||
d77b99c9 BW |
4551 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4552 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4553 | |
4554 | fmt = xtensa_format_decode (isa, insnbuf); | |
4555 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4556 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4557 | fmt_size = xtensa_format_length (isa, fmt); |
4558 | ||
4559 | /* If the next format won't be changing due to relaxation, just | |
4560 | return the length of the first format. */ | |
4561 | if (fragP->fr_opcode != fragP->fr_literal) | |
4562 | return fmt_size; | |
4563 | ||
c138bc38 | 4564 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4565 | multi-slot instruction, we will return the more conservative |
4566 | number. This works because alignment on bigger instructions | |
4567 | is more restrictive than alignment on smaller instructions. | |
4568 | This is more conservative than we would like, but it happens | |
4569 | infrequently. */ | |
4570 | ||
4571 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4572 | return fmt_size; | |
4573 | ||
4574 | /* If we aren't doing one of our own relaxations or it isn't | |
4575 | slot-based, then the insn size won't change. */ | |
4576 | if (fragP->fr_type != rs_machine_dependent) | |
4577 | return fmt_size; | |
4578 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4579 | return fmt_size; | |
4580 | ||
4581 | /* If an instruction is about to grow, return the longer size. */ | |
4582 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
b81bf389 BW |
4583 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 |
4584 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) | |
def13efb BW |
4585 | { |
4586 | /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first | |
4587 | instruction in the relaxed version is of length 3. (The case | |
4588 | where we have to pull the instruction out of a FLIX bundle | |
4589 | is handled conservatively above.) However, frags with opcodes | |
4590 | that are expanding to wide branches end up having formats that | |
4591 | are not determinable by the RELAX_IMMED_STEPX enumeration, and | |
4592 | we can't tell directly what format the relaxer picked. This | |
4593 | is a wart in the design of the relaxer that should someday be | |
4594 | fixed, but would require major changes, or at least should | |
4595 | be accompanied by major changes to make use of that data. | |
4596 | ||
4597 | In any event, we can tell that we are expanding from a single-slot | |
19ef5f3d | 4598 | format to a wider one with the logic below. */ |
def13efb | 4599 | |
19ef5f3d SA |
4600 | int i; |
4601 | int relaxed_size = fmt_size + fragP->tc_frag_data.text_expansion[0]; | |
4602 | ||
4603 | for (i = 0; i < xtensa_isa_num_formats (isa); i++) | |
4604 | { | |
4605 | if (relaxed_size == xtensa_format_length (isa, i)) | |
4606 | return relaxed_size; | |
4607 | } | |
4608 | ||
4609 | return 3; | |
def13efb | 4610 | } |
c138bc38 | 4611 | |
43cd72b9 BW |
4612 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4613 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4614 | |
43cd72b9 | 4615 | return fmt_size; |
e0001a05 NC |
4616 | } |
4617 | ||
4618 | ||
7fa3d080 BW |
4619 | static int |
4620 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4621 | { |
7fa3d080 BW |
4622 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4623 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4624 | } |
4625 | ||
4626 | ||
03aaa593 BW |
4627 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4628 | required two-byte instructions to be treated as three-byte instructions | |
4629 | for loop instruction alignment. This restriction was removed beginning | |
4630 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4631 | is that the first instruction of the loop must appear at an address that | |
4632 | does not cross a fetch boundary. */ | |
4633 | ||
4634 | static int | |
4635 | get_loop_align_size (int insn_size) | |
4636 | { | |
4637 | if (insn_size == XTENSA_UNDEFINED) | |
4638 | return xtensa_fetch_width; | |
4639 | ||
4640 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4641 | return 3; | |
4642 | ||
4643 | return insn_size; | |
4644 | } | |
4645 | ||
4646 | ||
e0001a05 NC |
4647 | /* If the next legit fragment is an end-of-loop marker, |
4648 | switch its state so it will instantiate a NOP. */ | |
4649 | ||
4650 | static void | |
1d19a770 | 4651 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4652 | { |
4653 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4654 | fragS *new_target = NULL; |
e0001a05 | 4655 | |
7b1cc377 | 4656 | if (align_targets) |
43cd72b9 BW |
4657 | { |
4658 | /* We are guaranteed there will be one of these... */ | |
4659 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4660 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4661 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4662 | next_fragP = next_fragP->fr_next; | |
4663 | ||
9c2799c2 | 4664 | gas_assert (next_fragP->fr_type == rs_machine_dependent |
43cd72b9 BW |
4665 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE |
4666 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4667 | ||
4668 | /* ...and one of these. */ | |
4669 | new_target = next_fragP->fr_next; | |
4670 | while (!(new_target->fr_type == rs_machine_dependent | |
4671 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4672 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4673 | new_target = new_target->fr_next; | |
4674 | ||
9c2799c2 | 4675 | gas_assert (new_target->fr_type == rs_machine_dependent |
43cd72b9 BW |
4676 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN |
4677 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4678 | } | |
43cd72b9 | 4679 | |
1d19a770 | 4680 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4681 | { |
1d19a770 BW |
4682 | if (next_fragP->fr_type == rs_machine_dependent |
4683 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4684 | { |
1d19a770 BW |
4685 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4686 | return; | |
e0001a05 | 4687 | } |
1d19a770 BW |
4688 | |
4689 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4690 | } |
4691 | } | |
4692 | ||
4693 | ||
4694 | static bfd_boolean | |
7fa3d080 | 4695 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4696 | { |
43cd72b9 | 4697 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4698 | so we have to skip until we find something legit. */ |
4699 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4700 | { | |
4701 | if (fragP->tc_frag_data.is_branch_target) | |
4702 | return TRUE; | |
4703 | if (fragP->fr_fix != 0) | |
4704 | break; | |
4705 | } | |
4706 | return FALSE; | |
4707 | } | |
4708 | ||
4709 | ||
4710 | static bfd_boolean | |
7fa3d080 | 4711 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4712 | { |
c138bc38 | 4713 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4714 | So we have to skip until we find something legit. */ |
4715 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4716 | { | |
4717 | if (fragP->tc_frag_data.is_loop_target) | |
4718 | return TRUE; | |
4719 | if (fragP->fr_fix != 0) | |
4720 | break; | |
4721 | } | |
4722 | return FALSE; | |
4723 | } | |
4724 | ||
4725 | ||
3a1e9c4a SA |
4726 | /* As specified in the relaxation table, when a loop instruction is |
4727 | relaxed, there are 24 bytes between the loop instruction itself and | |
4728 | the first instruction in the loop. */ | |
4729 | ||
4730 | #define RELAXED_LOOP_INSN_BYTES 24 | |
4731 | ||
e0001a05 | 4732 | static addressT |
7fa3d080 | 4733 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4734 | { |
4735 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4736 | xtensa_opcode next_opcode; |
e0001a05 | 4737 | |
43cd72b9 | 4738 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4739 | return 0; |
4740 | ||
43cd72b9 BW |
4741 | /* Sometimes an empty will end up here due to storage allocation issues, |
4742 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4743 | while (next_fragp->fr_fix == 0) |
4744 | next_fragp = next_fragp->fr_next; | |
4745 | ||
4746 | if (next_fragp->fr_type != rs_machine_dependent) | |
4747 | return 0; | |
4748 | ||
4749 | /* There is some implicit knowledge encoded in here. | |
4750 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4751 | been relaxed. Note that we can assume that the LOOP |
4752 | instruction is in slot 0 because loops aren't bundleable. */ | |
4753 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
3a1e9c4a | 4754 | return get_expanded_loop_offset (next_opcode) + RELAXED_LOOP_INSN_BYTES; |
e0001a05 NC |
4755 | |
4756 | return 0; | |
4757 | } | |
4758 | ||
4759 | ||
4760 | /* Mark a location where we can later insert literal frags. Update | |
4761 | the section's literal_pool_loc, so subsequent literals can be | |
4762 | placed nearest to their use. */ | |
4763 | ||
4764 | static void | |
7fa3d080 | 4765 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4766 | { |
4767 | /* Any labels pointing to the current location need | |
4768 | to be adjusted to after the literal pool. */ | |
4769 | emit_state s; | |
e0001a05 | 4770 | fragS *pool_location; |
e0001a05 | 4771 | |
1f2a7e38 | 4772 | if (use_literal_section) |
43cd72b9 BW |
4773 | return; |
4774 | ||
dd49a749 BW |
4775 | /* We stash info in these frags so we can later move the literal's |
4776 | fixes into this frchain's fix list. */ | |
e0001a05 | 4777 | pool_location = frag_now; |
dd49a749 | 4778 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
c48aaca0 | 4779 | frag_now->tc_frag_data.literal_frag = frag_now; |
b46824bd MF |
4780 | /* Just record this frag. */ |
4781 | xtensa_maybe_create_literal_pool_frag (FALSE, FALSE); | |
dd49a749 | 4782 | frag_variant (rs_machine_dependent, 0, 0, |
e0001a05 | 4783 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4784 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4785 | frag_now->tc_frag_data.lit_seg = now_seg; |
4786 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4787 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4788 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4789 | |
4790 | /* Now put a frag into the literal pool that points to this location. */ | |
4791 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4792 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4793 | frag_align (2, 0, 0); | |
4794 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4795 | |
4796 | /* Close whatever frag is there. */ | |
4797 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4798 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4799 | frag_now->tc_frag_data.literal_frag = pool_location; |
4800 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4801 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4802 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4803 | } |
4804 | ||
4805 | ||
43cd72b9 BW |
4806 | /* Build a nop of the correct size into tinsn. */ |
4807 | ||
4808 | static void | |
7fa3d080 | 4809 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4810 | { |
4811 | tinsn_init (tinsn); | |
4812 | switch (size) | |
4813 | { | |
4814 | case 2: | |
4815 | tinsn->opcode = xtensa_nop_n_opcode; | |
4816 | tinsn->ntok = 0; | |
4817 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4818 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4819 | break; | |
4820 | ||
4821 | case 3: | |
4822 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4823 | { | |
4824 | tinsn->opcode = xtensa_or_opcode; | |
4825 | set_expr_const (&tinsn->tok[0], 1); | |
4826 | set_expr_const (&tinsn->tok[1], 1); | |
4827 | set_expr_const (&tinsn->tok[2], 1); | |
4828 | tinsn->ntok = 3; | |
4829 | } | |
4830 | else | |
4831 | tinsn->opcode = xtensa_nop_opcode; | |
4832 | ||
9c2799c2 | 4833 | gas_assert (tinsn->opcode != XTENSA_UNDEFINED); |
43cd72b9 BW |
4834 | } |
4835 | } | |
4836 | ||
4837 | ||
e0001a05 NC |
4838 | /* Assemble a NOP of the requested size in the buffer. User must have |
4839 | allocated "buf" with at least "size" bytes. */ | |
4840 | ||
7fa3d080 | 4841 | static void |
d77b99c9 | 4842 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4843 | { |
4844 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4845 | TInsn tinsn; |
e0001a05 | 4846 | |
43cd72b9 | 4847 | build_nop (&tinsn, size); |
e0001a05 | 4848 | |
43cd72b9 BW |
4849 | if (!insnbuf) |
4850 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4851 | |
43cd72b9 | 4852 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4853 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4854 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4855 | } |
4856 | ||
4857 | ||
4858 | /* Return the number of bytes for the offset of the expanded loop | |
4859 | instruction. This should be incorporated into the relaxation | |
4860 | specification but is hard-coded here. This is used to auto-align | |
4861 | the loop instruction. It is invalid to call this function if the | |
4862 | configuration does not have loops or if the opcode is not a loop | |
4863 | opcode. */ | |
4864 | ||
4865 | static addressT | |
7fa3d080 | 4866 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4867 | { |
4868 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4869 | This MUST correspond directly to the specification of the loop | |
4870 | expansion. It will be validated on fragment conversion. */ | |
9c2799c2 | 4871 | gas_assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4872 | if (opcode == xtensa_loop_opcode) |
4873 | return 0; | |
4874 | if (opcode == xtensa_loopnez_opcode) | |
4875 | return 3; | |
4876 | if (opcode == xtensa_loopgtz_opcode) | |
4877 | return 6; | |
4878 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4879 | return 0; | |
4880 | } | |
4881 | ||
4882 | ||
7fa3d080 BW |
4883 | static fragS * |
4884 | get_literal_pool_location (segT seg) | |
e0001a05 | 4885 | { |
b46824bd MF |
4886 | struct litpool_seg *lps = litpool_seg_list.next; |
4887 | struct litpool_frag *lpf; | |
4888 | for ( ; lps && lps->seg->id != seg->id; lps = lps->next) | |
4889 | ; | |
4890 | if (lps) | |
4891 | { | |
4892 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) | |
4893 | { /* Skip "candidates" for now. */ | |
4894 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN && | |
4895 | lpf->priority == 1) | |
4896 | return lpf->fragP; | |
4897 | } | |
4898 | /* Must convert a lower-priority pool. */ | |
4899 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) | |
4900 | { | |
4901 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN) | |
4902 | return lpf->fragP; | |
4903 | } | |
4904 | /* Still no match -- try for a low priority pool. */ | |
4905 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) | |
4906 | { | |
4907 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
4908 | return lpf->fragP; | |
4909 | } | |
4910 | } | |
e0001a05 NC |
4911 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; |
4912 | } | |
4913 | ||
4914 | ||
4915 | static void | |
7fa3d080 | 4916 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4917 | { |
4918 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4919 | } | |
4920 | ||
43cd72b9 BW |
4921 | |
4922 | /* Set frag assembly state should be called when a new frag is | |
4923 | opened and after a frag has been closed. */ | |
4924 | ||
7fa3d080 BW |
4925 | static void |
4926 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4927 | { |
4928 | if (!density_supported) | |
4929 | fragP->tc_frag_data.is_no_density = TRUE; | |
4930 | ||
4931 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4932 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4933 | "use_schedule" here. */ |
4934 | if (!directive_state[directive_transform]) | |
4935 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4936 | if (directive_state[directive_longcalls]) |
4937 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4938 | fragP->tc_frag_data.use_absolute_literals = |
4939 | directive_state[directive_absolute_literals]; | |
4940 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4941 | } | |
4942 | ||
4943 | ||
7fa3d080 BW |
4944 | static bfd_boolean |
4945 | relaxable_section (asection *sec) | |
43cd72b9 | 4946 | { |
11ac2671 BW |
4947 | return ((sec->flags & SEC_DEBUGGING) == 0 |
4948 | && strcmp (sec->name, ".eh_frame") != 0); | |
43cd72b9 BW |
4949 | } |
4950 | ||
4951 | ||
99ded152 BW |
4952 | static void |
4953 | xtensa_mark_frags_for_org (void) | |
4954 | { | |
4955 | segT *seclist; | |
4956 | ||
4957 | /* Walk over each fragment of all of the current segments. If we find | |
4958 | a .org frag in any of the segments, mark all frags prior to it as | |
4959 | "no transform", which will prevent linker optimizations from messing | |
4960 | up the .org distance. This should be done after | |
4961 | xtensa_find_unmarked_state_frags, because we don't want to worry here | |
4962 | about that function trashing the data we save here. */ | |
4963 | ||
4964 | for (seclist = &stdoutput->sections; | |
4965 | seclist && *seclist; | |
4966 | seclist = &(*seclist)->next) | |
4967 | { | |
4968 | segT sec = *seclist; | |
4969 | segment_info_type *seginfo; | |
4970 | fragS *fragP; | |
4971 | flagword flags; | |
4972 | flags = bfd_get_section_flags (stdoutput, sec); | |
4973 | if (flags & SEC_DEBUGGING) | |
4974 | continue; | |
4975 | if (!(flags & SEC_ALLOC)) | |
4976 | continue; | |
4977 | ||
4978 | seginfo = seg_info (sec); | |
4979 | if (seginfo && seginfo->frchainP) | |
4980 | { | |
4981 | fragS *last_fragP = seginfo->frchainP->frch_root; | |
4982 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4983 | fragP = fragP->fr_next) | |
4984 | { | |
4985 | /* cvt_frag_to_fill has changed the fr_type of org frags to | |
4986 | rs_fill, so use the value as cached in rs_subtype here. */ | |
4987 | if (fragP->fr_subtype == RELAX_ORG) | |
4988 | { | |
4989 | while (last_fragP != fragP->fr_next) | |
4990 | { | |
4991 | last_fragP->tc_frag_data.is_no_transform = TRUE; | |
4992 | last_fragP = last_fragP->fr_next; | |
4993 | } | |
4994 | } | |
4995 | } | |
4996 | } | |
4997 | } | |
4998 | } | |
4999 | ||
5000 | ||
43cd72b9 | 5001 | static void |
7fa3d080 | 5002 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
5003 | { |
5004 | segT *seclist; | |
5005 | ||
5006 | /* Walk over each fragment of all of the current segments. For each | |
5007 | unmarked fragment, mark it with the same info as the previous | |
5008 | fragment. */ | |
5009 | for (seclist = &stdoutput->sections; | |
5010 | seclist && *seclist; | |
5011 | seclist = &(*seclist)->next) | |
5012 | { | |
5013 | segT sec = *seclist; | |
5014 | segment_info_type *seginfo; | |
5015 | fragS *fragP; | |
5016 | flagword flags; | |
5017 | flags = bfd_get_section_flags (stdoutput, sec); | |
5018 | if (flags & SEC_DEBUGGING) | |
5019 | continue; | |
5020 | if (!(flags & SEC_ALLOC)) | |
5021 | continue; | |
5022 | ||
5023 | seginfo = seg_info (sec); | |
5024 | if (seginfo && seginfo->frchainP) | |
5025 | { | |
5026 | fragS *last_fragP = 0; | |
5027 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
5028 | fragP = fragP->fr_next) | |
5029 | { | |
5030 | if (fragP->fr_fix != 0 | |
5031 | && !fragP->tc_frag_data.is_assembly_state_set) | |
5032 | { | |
5033 | if (last_fragP == 0) | |
5034 | { | |
5035 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
5036 | _("assembly state not set for first frag in section %s"), | |
5037 | sec->name); | |
5038 | } | |
5039 | else | |
5040 | { | |
5041 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
5042 | fragP->tc_frag_data.is_no_density = | |
5043 | last_fragP->tc_frag_data.is_no_density; | |
5044 | fragP->tc_frag_data.is_no_transform = | |
5045 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
5046 | fragP->tc_frag_data.use_longcalls = |
5047 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
5048 | fragP->tc_frag_data.use_absolute_literals = |
5049 | last_fragP->tc_frag_data.use_absolute_literals; | |
5050 | } | |
5051 | } | |
5052 | if (fragP->tc_frag_data.is_assembly_state_set) | |
5053 | last_fragP = fragP; | |
5054 | } | |
5055 | } | |
5056 | } | |
5057 | } | |
5058 | ||
5059 | ||
5060 | static void | |
7fa3d080 BW |
5061 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
5062 | asection *sec, | |
5063 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
5064 | { |
5065 | flagword flags = bfd_get_section_flags (abfd, sec); | |
5066 | segment_info_type *seginfo = seg_info (sec); | |
5067 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 5068 | |
43cd72b9 | 5069 | if (flags & SEC_CODE) |
c138bc38 | 5070 | { |
43cd72b9 BW |
5071 | xtensa_isa isa = xtensa_default_isa; |
5072 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
5073 | while (frag != NULL) | |
5074 | { | |
5075 | if (frag->tc_frag_data.is_branch_target) | |
5076 | { | |
5077 | int op_size; | |
664df4e4 | 5078 | addressT branch_align, frag_addr; |
43cd72b9 BW |
5079 | xtensa_format fmt; |
5080 | ||
d77b99c9 BW |
5081 | xtensa_insnbuf_from_chars |
5082 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
5083 | fmt = xtensa_format_decode (isa, insnbuf); |
5084 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
5085 | branch_align = 1 << branch_align_power (sec); |
5086 | frag_addr = frag->fr_address % branch_align; | |
5087 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
5088 | as_warn_where (frag->fr_file, frag->fr_line, |
5089 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 5090 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
5091 | } |
5092 | frag = frag->fr_next; | |
5093 | } | |
5094 | xtensa_insnbuf_free (isa, insnbuf); | |
5095 | } | |
5096 | } | |
5097 | ||
5098 | ||
5099 | static void | |
7fa3d080 BW |
5100 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
5101 | asection *sec, | |
5102 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
5103 | { |
5104 | flagword flags = bfd_get_section_flags (abfd, sec); | |
5105 | segment_info_type *seginfo = seg_info (sec); | |
5106 | fragS *frag = seginfo->frchainP->frch_root; | |
5107 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 5108 | |
43cd72b9 | 5109 | if (flags & SEC_CODE) |
c138bc38 | 5110 | { |
43cd72b9 BW |
5111 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
5112 | while (frag != NULL) | |
5113 | { | |
5114 | if (frag->tc_frag_data.is_first_loop_insn) | |
5115 | { | |
5116 | int op_size; | |
d77b99c9 | 5117 | addressT frag_addr; |
43cd72b9 BW |
5118 | xtensa_format fmt; |
5119 | ||
3c83b96e SA |
5120 | if (frag->fr_fix == 0) |
5121 | frag = next_non_empty_frag (frag); | |
3739860c | 5122 | |
3c83b96e SA |
5123 | if (frag) |
5124 | { | |
5125 | xtensa_insnbuf_from_chars | |
5126 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
5127 | fmt = xtensa_format_decode (isa, insnbuf); | |
5128 | op_size = xtensa_format_length (isa, fmt); | |
5129 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
3739860c | 5130 | |
3c83b96e SA |
5131 | if (frag_addr + op_size > xtensa_fetch_width) |
5132 | as_warn_where (frag->fr_file, frag->fr_line, | |
5133 | _("unaligned loop: %d bytes at 0x%lx"), | |
5134 | op_size, (long) frag->fr_address); | |
5135 | } | |
43cd72b9 BW |
5136 | } |
5137 | frag = frag->fr_next; | |
5138 | } | |
5139 | xtensa_insnbuf_free (isa, insnbuf); | |
5140 | } | |
5141 | } | |
5142 | ||
5143 | ||
30f725a1 BW |
5144 | static int |
5145 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
5146 | { |
5147 | xtensa_isa isa = xtensa_default_isa; | |
5148 | static xtensa_insnbuf insnbuf = NULL; | |
5149 | static xtensa_insnbuf slotbuf = NULL; | |
5150 | xtensa_format fmt; | |
5151 | int slot; | |
5152 | bfd_boolean alt_reloc; | |
5153 | xtensa_opcode opcode; | |
5154 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
5155 | ||
1b6e95c2 BW |
5156 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) |
5157 | || alt_reloc) | |
43cd72b9 BW |
5158 | as_fatal (_("unexpected fix")); |
5159 | ||
5160 | if (!insnbuf) | |
5161 | { | |
5162 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5163 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5164 | } | |
5165 | ||
d77b99c9 | 5166 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
5167 | fmt = xtensa_format_decode (isa, insnbuf); |
5168 | if (fmt == XTENSA_UNDEFINED) | |
5169 | as_fatal (_("undecodable fix")); | |
5170 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5171 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5172 | if (opcode == XTENSA_UNDEFINED) | |
5173 | as_fatal (_("undecodable fix")); | |
5174 | ||
5175 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
5176 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 5177 | of a CONST16 operand. */ |
43cd72b9 | 5178 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 5179 | return 0; |
43cd72b9 BW |
5180 | |
5181 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
5182 | get_relaxable_immed (opcode), val, | |
5183 | fixP->fx_file, fixP->fx_line); | |
5184 | ||
5185 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 5186 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
5187 | |
5188 | return 1; | |
43cd72b9 BW |
5189 | } |
5190 | ||
e0001a05 NC |
5191 | \f |
5192 | /* External Functions and Other GAS Hooks. */ | |
5193 | ||
5194 | const char * | |
7fa3d080 | 5195 | xtensa_target_format (void) |
e0001a05 NC |
5196 | { |
5197 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
5198 | } | |
5199 | ||
5200 | ||
5201 | void | |
7fa3d080 | 5202 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
5203 | { |
5204 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
5205 | } | |
5206 | ||
5207 | ||
5208 | void | |
7fa3d080 | 5209 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
5210 | { |
5211 | if (target_big_endian) | |
5212 | number_to_chars_bigendian (buf, val, n); | |
5213 | else | |
5214 | number_to_chars_littleendian (buf, val, n); | |
5215 | } | |
5216 | ||
f7e16c2a MF |
5217 | static void |
5218 | xg_init_global_config (void) | |
5219 | { | |
5220 | target_big_endian = XCHAL_HAVE_BE; | |
5221 | ||
5222 | density_supported = XCHAL_HAVE_DENSITY; | |
5223 | absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; | |
5224 | xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; | |
5225 | ||
5226 | directive_state[directive_density] = XCHAL_HAVE_DENSITY; | |
5227 | directive_state[directive_absolute_literals] = XSHAL_USE_ABSOLUTE_LITERALS; | |
5228 | } | |
5229 | ||
5230 | void | |
5231 | xtensa_init (int argc ATTRIBUTE_UNUSED, char **argv ATTRIBUTE_UNUSED) | |
5232 | { | |
5233 | xg_init_global_config (); | |
5234 | } | |
e0001a05 NC |
5235 | |
5236 | /* This function is called once, at assembler startup time. It should | |
5237 | set up all the tables, etc. that the MD part of the assembler will | |
5238 | need. */ | |
5239 | ||
5240 | void | |
7fa3d080 | 5241 | md_begin (void) |
e0001a05 NC |
5242 | { |
5243 | segT current_section = now_seg; | |
5244 | int current_subsec = now_subseg; | |
5245 | xtensa_isa isa; | |
62af60e2 | 5246 | int i; |
e0001a05 | 5247 | |
43cd72b9 | 5248 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 5249 | isa = xtensa_default_isa; |
e0001a05 | 5250 | |
43cd72b9 BW |
5251 | linkrelax = 1; |
5252 | ||
74869ac7 | 5253 | /* Set up the literal sections. */ |
e0001a05 | 5254 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
e0001a05 NC |
5255 | |
5256 | subseg_set (current_section, current_subsec); | |
5257 | ||
5258 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); | |
5259 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
5260 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
5261 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
5262 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
5263 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
5264 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
5265 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
5266 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
5267 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 5268 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 5269 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
d12f9798 | 5270 | xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); |
43cd72b9 BW |
5271 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
5272 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 5273 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
19e8f41a | 5274 | xtensa_j_opcode = xtensa_opcode_lookup (isa, "j"); |
e0001a05 | 5275 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 5276 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
5277 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
5278 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
5279 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 5280 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
5281 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
5282 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
5283 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
5284 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
5285 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
5286 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 5287 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 5288 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 | 5289 | |
3739860c | 5290 | for (i = 0; i < xtensa_isa_num_formats (isa); i++) |
62af60e2 SA |
5291 | { |
5292 | int format_slots = xtensa_format_num_slots (isa, i); | |
5293 | if (format_slots > config_max_slots) | |
5294 | config_max_slots = format_slots; | |
5295 | } | |
5296 | ||
5297 | xg_init_vinsn (&cur_vinsn); | |
5298 | ||
77cba8a3 BW |
5299 | xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa); |
5300 | ||
43cd72b9 BW |
5301 | init_op_placement_info_table (); |
5302 | ||
5303 | /* Set up the assembly state. */ | |
5304 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5305 | xtensa_set_frag_assembly_state (frag_now); | |
5306 | } | |
5307 | ||
5308 | ||
5309 | /* TC_INIT_FIX_DATA hook */ | |
5310 | ||
5311 | void | |
7fa3d080 | 5312 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5313 | { |
5314 | x->tc_fix_data.slot = 0; | |
5315 | x->tc_fix_data.X_add_symbol = NULL; | |
5316 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5317 | } |
5318 | ||
5319 | ||
5320 | /* tc_frob_label hook */ | |
5321 | ||
5322 | void | |
7fa3d080 | 5323 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5324 | { |
3ea38ac2 BW |
5325 | float freq; |
5326 | ||
5327 | if (cur_vinsn.inside_bundle) | |
5328 | { | |
5329 | as_bad (_("labels are not valid inside bundles")); | |
5330 | return; | |
5331 | } | |
5332 | ||
5333 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5334 | |
43cd72b9 BW |
5335 | /* Since the label was already attached to a frag associated with the |
5336 | previous basic block, it now needs to be reset to the current frag. */ | |
5337 | symbol_set_frag (sym, frag_now); | |
5338 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5339 | ||
82e7541d BW |
5340 | if (generating_literals) |
5341 | xtensa_add_literal_sym (sym); | |
5342 | else | |
5343 | xtensa_add_insn_label (sym); | |
5344 | ||
7b1cc377 BW |
5345 | if (symbol_get_tc (sym)->is_loop_target) |
5346 | { | |
5347 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5348 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5349 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5350 | ||
5351 | xtensa_set_frag_assembly_state (frag_now); | |
5352 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5353 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5354 | ||
5355 | xtensa_set_frag_assembly_state (frag_now); | |
c3ea6048 | 5356 | xtensa_move_labels (frag_now, 0); |
07a53e5c | 5357 | } |
e0001a05 NC |
5358 | |
5359 | /* No target aligning in the absolute section. */ | |
61846f28 | 5360 | if (now_seg != absolute_section |
61846f28 | 5361 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5362 | && !generating_literals) |
5363 | { | |
43cd72b9 BW |
5364 | xtensa_set_frag_assembly_state (frag_now); |
5365 | ||
b7afdeef SA |
5366 | if (do_align_targets ()) |
5367 | frag_var (rs_machine_dependent, 0, (int) freq, | |
5368 | RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol, | |
5369 | frag_now->fr_offset, NULL); | |
5370 | else | |
5371 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
5372 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5373 | xtensa_set_frag_assembly_state (frag_now); |
c3ea6048 | 5374 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
5375 | } |
5376 | ||
5377 | /* We need to mark the following properties even if we aren't aligning. */ | |
5378 | ||
5379 | /* If the label is already known to be a branch target, i.e., a | |
5380 | forward branch, mark the frag accordingly. Backward branches | |
5381 | are handled by xg_add_branch_and_loop_targets. */ | |
5382 | if (symbol_get_tc (sym)->is_branch_target) | |
5383 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5384 | ||
5385 | /* Loops only go forward, so they can be identified here. */ | |
5386 | if (symbol_get_tc (sym)->is_loop_target) | |
5387 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5388 | |
5389 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5390 | } |
5391 | ||
5392 | ||
5393 | /* tc_unrecognized_line hook */ | |
5394 | ||
5395 | int | |
7fa3d080 | 5396 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5397 | { |
5398 | switch (ch) | |
5399 | { | |
5400 | case '{' : | |
5401 | if (cur_vinsn.inside_bundle == 0) | |
5402 | { | |
5403 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5404 | when using --gstabs. Temporarily disable debug info. */ | |
5405 | generate_lineno_debug (); | |
5406 | if (debug_type == DEBUG_STABS) | |
5407 | { | |
5408 | xt_saved_debug_type = debug_type; | |
5409 | debug_type = DEBUG_NONE; | |
5410 | } | |
82e7541d | 5411 | |
43cd72b9 BW |
5412 | cur_vinsn.inside_bundle = 1; |
5413 | } | |
5414 | else | |
5415 | { | |
5416 | as_bad (_("extra opening brace")); | |
5417 | return 0; | |
5418 | } | |
5419 | break; | |
82e7541d | 5420 | |
43cd72b9 BW |
5421 | case '}' : |
5422 | if (cur_vinsn.inside_bundle) | |
5423 | finish_vinsn (&cur_vinsn); | |
5424 | else | |
5425 | { | |
5426 | as_bad (_("extra closing brace")); | |
5427 | return 0; | |
5428 | } | |
5429 | break; | |
5430 | default: | |
5431 | as_bad (_("syntax error")); | |
5432 | return 0; | |
e0001a05 | 5433 | } |
43cd72b9 | 5434 | return 1; |
e0001a05 NC |
5435 | } |
5436 | ||
5437 | ||
5438 | /* md_flush_pending_output hook */ | |
5439 | ||
5440 | void | |
7fa3d080 | 5441 | xtensa_flush_pending_output (void) |
e0001a05 | 5442 | { |
a3582eee BW |
5443 | /* This line fixes a bug where automatically generated gstabs info |
5444 | separates a function label from its entry instruction, ending up | |
5445 | with the literal position between the function label and the entry | |
5446 | instruction and crashing code. It only happens with --gstabs and | |
5447 | --text-section-literals, and when several other obscure relaxation | |
5448 | conditions are met. */ | |
5449 | if (outputting_stabs_line_debug) | |
5450 | return; | |
5451 | ||
43cd72b9 BW |
5452 | if (cur_vinsn.inside_bundle) |
5453 | as_bad (_("missing closing brace")); | |
5454 | ||
e0001a05 NC |
5455 | /* If there is a non-zero instruction fragment, close it. */ |
5456 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5457 | { | |
5458 | frag_wane (frag_now); | |
5459 | frag_new (0); | |
43cd72b9 | 5460 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5461 | } |
5462 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5463 | |
5464 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5465 | } |
5466 | ||
5467 | ||
43cd72b9 BW |
5468 | /* We had an error while parsing an instruction. The string might look |
5469 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5470 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5471 | and the num_slots field will grow past the end of the array of slots, | |
5472 | and bad things happen. */ | |
5473 | ||
5474 | static void | |
7fa3d080 | 5475 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5476 | { |
5477 | if (cur_vinsn.inside_bundle) | |
5478 | { | |
5479 | if (*input_line_pointer == '}' | |
5480 | || *(input_line_pointer - 1) == '}' | |
5481 | || *(input_line_pointer - 2) == '}') | |
5482 | xg_clear_vinsn (&cur_vinsn); | |
5483 | } | |
5484 | } | |
5485 | ||
5486 | ||
e0001a05 | 5487 | void |
7fa3d080 | 5488 | md_assemble (char *str) |
e0001a05 NC |
5489 | { |
5490 | xtensa_isa isa = xtensa_default_isa; | |
b224e962 | 5491 | char *opname; |
e0001a05 NC |
5492 | unsigned opnamelen; |
5493 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5494 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5495 | int num_args; |
e0001a05 | 5496 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5497 | |
e0001a05 NC |
5498 | tinsn_init (&orig_insn); |
5499 | ||
5500 | /* Split off the opcode. */ | |
5501 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
4ec9d7d5 | 5502 | opname = xstrndup (str, opnamelen); |
e0001a05 NC |
5503 | |
5504 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5505 | if (num_args == -1) | |
5506 | { | |
5507 | as_bad (_("syntax error")); | |
5508 | return; | |
5509 | } | |
5510 | ||
5511 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5512 | return; | |
5513 | ||
5514 | /* Check for an underbar prefix. */ | |
5515 | if (*opname == '_') | |
5516 | { | |
5517 | has_underbar = TRUE; | |
5518 | opname += 1; | |
5519 | } | |
5520 | ||
5521 | orig_insn.insn_type = ITYPE_INSN; | |
5522 | orig_insn.ntok = 0; | |
43cd72b9 | 5523 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 | 5524 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); |
28dbbc02 | 5525 | |
2b0f3761 | 5526 | /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its |
28dbbc02 BW |
5527 | extra argument and set the opcode to "CALLXn". */ |
5528 | if (orig_insn.opcode == XTENSA_UNDEFINED | |
5529 | && strncasecmp (opname, "callx", 5) == 0) | |
5530 | { | |
5531 | unsigned long window_size; | |
5532 | char *suffix; | |
5533 | ||
5534 | window_size = strtoul (opname + 5, &suffix, 10); | |
5535 | if (suffix != opname + 5 | |
5536 | && (window_size == 0 | |
5537 | || window_size == 4 | |
5538 | || window_size == 8 | |
5539 | || window_size == 12) | |
5540 | && strcasecmp (suffix, ".tls") == 0) | |
5541 | { | |
5542 | switch (window_size) | |
5543 | { | |
5544 | case 0: orig_insn.opcode = xtensa_callx0_opcode; break; | |
5545 | case 4: orig_insn.opcode = xtensa_callx4_opcode; break; | |
5546 | case 8: orig_insn.opcode = xtensa_callx8_opcode; break; | |
5547 | case 12: orig_insn.opcode = xtensa_callx12_opcode; break; | |
5548 | } | |
5549 | ||
5550 | if (num_args != 2) | |
5551 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5552 | else | |
5553 | { | |
5554 | bfd_reloc_code_real_type reloc; | |
5555 | char *old_input_line_pointer; | |
19e8f41a | 5556 | expressionS *tok = &orig_insn.extra_arg; |
28dbbc02 BW |
5557 | |
5558 | old_input_line_pointer = input_line_pointer; | |
5559 | input_line_pointer = arg_strings[num_args - 1]; | |
5560 | ||
87975d2a | 5561 | expression (tok); |
28dbbc02 BW |
5562 | if (tok->X_op == O_symbol |
5563 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) | |
5564 | == BFD_RELOC_XTENSA_TLS_CALL)) | |
5565 | tok->X_op = map_suffix_reloc_to_operator (reloc); | |
5566 | else | |
5567 | as_bad (_("bad relocation expression for '%s'"), opname); | |
5568 | ||
5569 | input_line_pointer = old_input_line_pointer; | |
5570 | num_args -= 1; | |
5571 | } | |
5572 | } | |
5573 | } | |
5574 | ||
2b0f3761 | 5575 | /* Special case: Check for "j.l" pseudo op. */ |
19e8f41a BW |
5576 | if (orig_insn.opcode == XTENSA_UNDEFINED |
5577 | && strncasecmp (opname, "j.l", 3) == 0) | |
5578 | { | |
5579 | if (num_args != 2) | |
5580 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5581 | else | |
5582 | { | |
5583 | char *old_input_line_pointer; | |
5584 | expressionS *tok = &orig_insn.extra_arg; | |
5585 | ||
5586 | old_input_line_pointer = input_line_pointer; | |
5587 | input_line_pointer = arg_strings[num_args - 1]; | |
5588 | ||
5589 | expression_maybe_register (xtensa_jx_opcode, 0, tok); | |
5590 | input_line_pointer = old_input_line_pointer; | |
5591 | ||
5592 | num_args -= 1; | |
5593 | orig_insn.opcode = xtensa_j_opcode; | |
5594 | } | |
5595 | } | |
5596 | ||
e0001a05 NC |
5597 | if (orig_insn.opcode == XTENSA_UNDEFINED) |
5598 | { | |
43cd72b9 BW |
5599 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5600 | if (fmt == XTENSA_UNDEFINED) | |
5601 | { | |
5602 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5603 | error_reset_cur_vinsn (); | |
5604 | return; | |
5605 | } | |
5606 | if (!cur_vinsn.inside_bundle) | |
5607 | { | |
5608 | as_bad (_("format names only valid inside bundles")); | |
5609 | error_reset_cur_vinsn (); | |
5610 | return; | |
5611 | } | |
5612 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5613 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5614 | opname); | |
5615 | cur_vinsn.format = fmt; | |
5616 | free (has_underbar ? opname - 1 : opname); | |
5617 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5618 | return; |
5619 | } | |
5620 | ||
e0001a05 NC |
5621 | /* Parse the arguments. */ |
5622 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5623 | { | |
5624 | as_bad (_("syntax error")); | |
43cd72b9 | 5625 | error_reset_cur_vinsn (); |
e0001a05 NC |
5626 | return; |
5627 | } | |
5628 | ||
5629 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5630 | free (has_underbar ? opname - 1 : opname); | |
5631 | opname = 0; | |
5632 | while (num_args-- > 0) | |
5633 | free (arg_strings[num_args]); | |
5634 | ||
43cd72b9 BW |
5635 | /* Get expressions for invisible operands. */ |
5636 | if (get_invisible_operands (&orig_insn)) | |
5637 | { | |
5638 | error_reset_cur_vinsn (); | |
5639 | return; | |
5640 | } | |
5641 | ||
e0001a05 NC |
5642 | /* Check for the right number and type of arguments. */ |
5643 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5644 | { |
43cd72b9 BW |
5645 | error_reset_cur_vinsn (); |
5646 | return; | |
e0001a05 NC |
5647 | } |
5648 | ||
b224e962 BW |
5649 | /* Record the line number for each TInsn, because a FLIX bundle may be |
5650 | spread across multiple input lines and individual instructions may be | |
5651 | moved around in some cases. */ | |
5652 | orig_insn.loc_directive_seen = dwarf2_loc_directive_seen; | |
5653 | dwarf2_where (&orig_insn.debug_line); | |
5654 | dwarf2_consume_line_info (); | |
c138bc38 | 5655 | |
43cd72b9 BW |
5656 | xg_add_branch_and_loop_targets (&orig_insn); |
5657 | ||
431ad2d0 BW |
5658 | /* Check that immediate value for ENTRY is >= 16. */ |
5659 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5660 | { |
431ad2d0 BW |
5661 | expressionS *exp = &orig_insn.tok[2]; |
5662 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5663 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5664 | } |
5665 | ||
e0001a05 | 5666 | /* Finish it off: |
43cd72b9 BW |
5667 | assemble_tokens (opcode, tok, ntok); |
5668 | expand the tokens from the orig_insn into the | |
5669 | stack of instructions that will not expand | |
e0001a05 | 5670 | unless required at relaxation time. */ |
e0001a05 | 5671 | |
43cd72b9 BW |
5672 | if (!cur_vinsn.inside_bundle) |
5673 | emit_single_op (&orig_insn); | |
5674 | else /* We are inside a bundle. */ | |
e0001a05 | 5675 | { |
43cd72b9 BW |
5676 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5677 | cur_vinsn.num_slots++; | |
5678 | if (*input_line_pointer == '}' | |
5679 | || *(input_line_pointer - 1) == '}' | |
5680 | || *(input_line_pointer - 2) == '}') | |
5681 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5682 | } |
5683 | ||
43cd72b9 BW |
5684 | /* We've just emitted a new instruction so clear the list of labels. */ |
5685 | xtensa_clear_insn_labels (); | |
a82c7d90 DW |
5686 | |
5687 | xtensa_check_frag_count (); | |
e0001a05 NC |
5688 | } |
5689 | ||
5690 | ||
43cd72b9 | 5691 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5692 | |
43cd72b9 BW |
5693 | /* For a .align directive, we mark the previous block with the alignment |
5694 | information. This will be placed in the object file in the | |
5695 | property section corresponding to this section. */ | |
e0001a05 | 5696 | |
43cd72b9 | 5697 | void |
7fa3d080 | 5698 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5699 | { |
5700 | if (linkrelax | |
b08b5071 | 5701 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5702 | && (fragP->fr_type == rs_align |
5703 | || fragP->fr_type == rs_align_code) | |
43cd72b9 BW |
5704 | && fragP->fr_offset > 0 |
5705 | && now_seg != bss_section) | |
e0001a05 | 5706 | { |
43cd72b9 BW |
5707 | fragP->tc_frag_data.is_align = TRUE; |
5708 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5709 | } |
5710 | ||
43cd72b9 | 5711 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5712 | { |
43cd72b9 BW |
5713 | int count; |
5714 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5715 | if (count != 0) | |
c138bc38 | 5716 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5717 | _("unaligned entry instruction")); |
e0001a05 | 5718 | } |
99ded152 BW |
5719 | |
5720 | if (linkrelax && fragP->fr_type == rs_org) | |
5721 | fragP->fr_subtype = RELAX_ORG; | |
e0001a05 | 5722 | } |
43cd72b9 | 5723 | |
e0001a05 NC |
5724 | |
5725 | /* TC_FRAG_INIT hook */ | |
5726 | ||
5727 | void | |
7fa3d080 | 5728 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5729 | { |
43cd72b9 | 5730 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5731 | } |
5732 | ||
5733 | ||
5734 | symbolS * | |
7fa3d080 | 5735 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5736 | { |
5737 | return NULL; | |
5738 | } | |
5739 | ||
5740 | ||
5741 | /* Round up a section size to the appropriate boundary. */ | |
5742 | ||
5743 | valueT | |
7fa3d080 | 5744 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5745 | { |
5746 | return size; /* Byte alignment is fine. */ | |
5747 | } | |
5748 | ||
5749 | ||
5750 | long | |
7fa3d080 | 5751 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5752 | { |
5753 | char *insn_p; | |
5754 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5755 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5756 | int opnum; |
43cd72b9 | 5757 | uint32 opnd_value; |
e0001a05 | 5758 | xtensa_opcode opcode; |
43cd72b9 BW |
5759 | xtensa_format fmt; |
5760 | int slot; | |
e0001a05 NC |
5761 | xtensa_isa isa = xtensa_default_isa; |
5762 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5763 | bfd_boolean alt_reloc; |
e0001a05 | 5764 | |
e0001a05 | 5765 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5766 | return 0; |
e0001a05 | 5767 | |
1bbb5f21 BW |
5768 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL) |
5769 | return addr; | |
5770 | ||
e0001a05 | 5771 | if (!insnbuf) |
43cd72b9 BW |
5772 | { |
5773 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5774 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5775 | } | |
e0001a05 NC |
5776 | |
5777 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5778 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5779 | fmt = xtensa_format_decode (isa, insnbuf); |
5780 | ||
5781 | if (fmt == XTENSA_UNDEFINED) | |
5782 | as_fatal (_("bad instruction format")); | |
5783 | ||
5784 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5785 | as_fatal (_("invalid relocation")); | |
5786 | ||
5787 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5788 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5789 | ||
30f725a1 BW |
5790 | /* Check for "alternate" relocations (operand not specified). None |
5791 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5792 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5793 | { | |
5794 | if (opcode != xtensa_l32r_opcode | |
5795 | && opcode != xtensa_const16_opcode) | |
5796 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5797 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5798 | return 0; |
e0001a05 NC |
5799 | } |
5800 | ||
43cd72b9 BW |
5801 | opnum = get_relaxable_immed (opcode); |
5802 | opnd_value = 0; | |
5803 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5804 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5805 | { |
5806 | as_bad_where (fixP->fx_file, | |
5807 | fixP->fx_line, | |
5808 | _("invalid relocation for operand %d of '%s'"), | |
5809 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5810 | return 0; |
e0001a05 | 5811 | } |
43cd72b9 BW |
5812 | return 0 - opnd_value; |
5813 | } | |
5814 | ||
5815 | ||
5816 | /* TC_FORCE_RELOCATION hook */ | |
5817 | ||
5818 | int | |
7fa3d080 | 5819 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5820 | { |
5821 | switch (fix->fx_r_type) | |
30f725a1 BW |
5822 | { |
5823 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5824 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5825 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5826 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5827 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5828 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5829 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5830 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5831 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5832 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5833 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5834 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5835 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5836 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5837 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5838 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5839 | return 1; |
5840 | default: | |
5841 | break; | |
e0001a05 NC |
5842 | } |
5843 | ||
43cd72b9 BW |
5844 | if (linkrelax && fix->fx_addsy |
5845 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5846 | return 1; | |
5847 | ||
5848 | return generic_force_reloc (fix); | |
5849 | } | |
5850 | ||
5851 | ||
30f725a1 BW |
5852 | /* TC_VALIDATE_FIX_SUB hook */ |
5853 | ||
5854 | int | |
5855 | xtensa_validate_fix_sub (fixS *fix) | |
5856 | { | |
5857 | segT add_symbol_segment, sub_symbol_segment; | |
5858 | ||
5859 | /* The difference of two symbols should be resolved by the assembler when | |
5860 | linkrelax is not set. If the linker may relax the section containing | |
5861 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5862 | the linker knows to adjust the difference value. */ | |
5863 | if (!linkrelax || fix->fx_addsy == NULL) | |
5864 | return 0; | |
5865 | ||
5866 | /* Make sure both symbols are in the same segment, and that segment is | |
5867 | "normal" and relaxable. If the segment is not "normal", then the | |
5868 | fix is not valid. If the segment is not "relaxable", then the fix | |
5869 | should have been handled earlier. */ | |
5870 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5871 | if (! SEG_NORMAL (add_symbol_segment) || | |
5872 | ! relaxable_section (add_symbol_segment)) | |
5873 | return 0; | |
5874 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5875 | return (sub_symbol_segment == add_symbol_segment); | |
5876 | } | |
5877 | ||
5878 | ||
43cd72b9 BW |
5879 | /* NO_PSEUDO_DOT hook */ |
5880 | ||
5881 | /* This function has nothing to do with pseudo dots, but this is the | |
5882 | nearest macro to where the check needs to take place. FIXME: This | |
5883 | seems wrong. */ | |
5884 | ||
5885 | bfd_boolean | |
7fa3d080 | 5886 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5887 | { |
5888 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5889 | as_bad (_("directives are not valid inside bundles")); | |
5890 | ||
5891 | /* This function must always return FALSE because it is called via a | |
5892 | macro that has nothing to do with bundling. */ | |
5893 | return FALSE; | |
e0001a05 NC |
5894 | } |
5895 | ||
5896 | ||
43cd72b9 | 5897 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5898 | |
5899 | void | |
7fa3d080 | 5900 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5901 | { |
43cd72b9 BW |
5902 | /* Set up the assembly state. */ |
5903 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5904 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5905 | } |
5906 | ||
5907 | ||
5908 | /* tc_fix_adjustable hook */ | |
5909 | ||
5910 | bfd_boolean | |
7fa3d080 | 5911 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 NC |
5912 | { |
5913 | /* We need the symbol name for the VTABLE entries. */ | |
5914 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5915 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5916 | return 0; | |
5917 | ||
5918 | return 1; | |
5919 | } | |
5920 | ||
5921 | ||
6a7eedfe BW |
5922 | /* tc_symbol_new_hook */ |
5923 | ||
5924 | symbolS *expr_symbols = NULL; | |
5925 | ||
3739860c | 5926 | void |
6a7eedfe BW |
5927 | xtensa_symbol_new_hook (symbolS *sym) |
5928 | { | |
fb227da0 | 5929 | if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section) |
6a7eedfe BW |
5930 | { |
5931 | symbol_get_tc (sym)->next_expr_symbol = expr_symbols; | |
5932 | expr_symbols = sym; | |
5933 | } | |
5934 | } | |
5935 | ||
5936 | ||
e0001a05 | 5937 | void |
55cf6793 | 5938 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5939 | { |
30f725a1 | 5940 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5941 | valueT val = 0; |
30f725a1 | 5942 | |
e7da6241 BW |
5943 | /* Subtracted symbols are only allowed for a few relocation types, and |
5944 | unless linkrelax is enabled, they should not make it to this point. */ | |
5945 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5946 | || fixP->fx_r_type == BFD_RELOC_16 | |
5947 | || fixP->fx_r_type == BFD_RELOC_8))) | |
5948 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
5949 | ||
30f725a1 | 5950 | switch (fixP->fx_r_type) |
e0001a05 | 5951 | { |
1bbb5f21 | 5952 | case BFD_RELOC_32_PCREL: |
30f725a1 BW |
5953 | case BFD_RELOC_32: |
5954 | case BFD_RELOC_16: | |
5955 | case BFD_RELOC_8: | |
e7da6241 | 5956 | if (fixP->fx_subsy) |
30f725a1 BW |
5957 | { |
5958 | switch (fixP->fx_r_type) | |
5959 | { | |
5960 | case BFD_RELOC_8: | |
5961 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
ea173078 | 5962 | fixP->fx_signed = 0; |
30f725a1 BW |
5963 | break; |
5964 | case BFD_RELOC_16: | |
5965 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
ea173078 | 5966 | fixP->fx_signed = 0; |
30f725a1 BW |
5967 | break; |
5968 | case BFD_RELOC_32: | |
5969 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
ea173078 | 5970 | fixP->fx_signed = 0; |
30f725a1 BW |
5971 | break; |
5972 | default: | |
5973 | break; | |
5974 | } | |
e0001a05 | 5975 | |
30f725a1 BW |
5976 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset |
5977 | - S_GET_VALUE (fixP->fx_subsy)); | |
5978 | ||
5979 | /* The difference value gets written out, and the DIFF reloc | |
5980 | identifies the address of the subtracted symbol (i.e., the one | |
5981 | with the lowest address). */ | |
5982 | *valP = val; | |
5983 | fixP->fx_offset -= val; | |
5984 | fixP->fx_subsy = NULL; | |
5985 | } | |
5986 | else if (! fixP->fx_addsy) | |
e0001a05 | 5987 | { |
30f725a1 | 5988 | val = *valP; |
e0001a05 | 5989 | fixP->fx_done = 1; |
30f725a1 | 5990 | } |
d47d412e BW |
5991 | /* fall through */ |
5992 | ||
5993 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
5994 | md_number_to_chars (fixpos, val, fixP->fx_size); |
5995 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5996 | break; | |
e0001a05 | 5997 | |
28dbbc02 BW |
5998 | case BFD_RELOC_XTENSA_TLSDESC_FN: |
5999 | case BFD_RELOC_XTENSA_TLSDESC_ARG: | |
6000 | case BFD_RELOC_XTENSA_TLS_TPOFF: | |
6001 | case BFD_RELOC_XTENSA_TLS_DTPOFF: | |
6002 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
6003 | md_number_to_chars (fixpos, 0, fixP->fx_size); | |
6004 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
6005 | break; | |
6006 | ||
30f725a1 BW |
6007 | case BFD_RELOC_XTENSA_SLOT0_OP: |
6008 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
6009 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
6010 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
6011 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
6012 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
6013 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
6014 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
6015 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
6016 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
6017 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
6018 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
6019 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
6020 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
6021 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
6022 | if (linkrelax) | |
6023 | { | |
6024 | /* Write the tentative value of a PC-relative relocation to a | |
6025 | local symbol into the instruction. The value will be ignored | |
6026 | by the linker, and it makes the object file disassembly | |
6027 | readable when all branch targets are encoded in relocations. */ | |
6028 | ||
9c2799c2 | 6029 | gas_assert (fixP->fx_addsy); |
20ee54e8 | 6030 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg |
30f725a1 BW |
6031 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) |
6032 | { | |
6033 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
6034 | - md_pcrel_from (fixP)); | |
6035 | (void) xg_apply_fix_value (fixP, val); | |
6036 | } | |
6037 | } | |
6038 | else if (! fixP->fx_addsy) | |
6039 | { | |
6040 | val = *valP; | |
6041 | if (xg_apply_fix_value (fixP, val)) | |
6042 | fixP->fx_done = 1; | |
6043 | } | |
6044 | break; | |
e0001a05 | 6045 | |
30f725a1 | 6046 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
28dbbc02 BW |
6047 | case BFD_RELOC_XTENSA_TLS_FUNC: |
6048 | case BFD_RELOC_XTENSA_TLS_ARG: | |
6049 | case BFD_RELOC_XTENSA_TLS_CALL: | |
30f725a1 BW |
6050 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
6051 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
6052 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
6053 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
6054 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
6055 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
6056 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
6057 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
6058 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
6059 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
6060 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
6061 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
6062 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
6063 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
6064 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
6065 | /* These all need to be resolved at link-time. Do nothing now. */ | |
6066 | break; | |
e0001a05 | 6067 | |
30f725a1 BW |
6068 | case BFD_RELOC_VTABLE_INHERIT: |
6069 | case BFD_RELOC_VTABLE_ENTRY: | |
6070 | fixP->fx_done = 0; | |
6071 | break; | |
e0001a05 | 6072 | |
30f725a1 BW |
6073 | default: |
6074 | as_bad (_("unhandled local relocation fix %s"), | |
6075 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
6076 | } |
6077 | } | |
6078 | ||
6079 | ||
6d4af3c2 | 6080 | const char * |
7fa3d080 | 6081 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 | 6082 | { |
499ac353 | 6083 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
e0001a05 NC |
6084 | } |
6085 | ||
6086 | ||
6087 | int | |
7fa3d080 | 6088 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 6089 | { |
34e41783 | 6090 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
6091 | } |
6092 | ||
6093 | ||
6094 | /* Translate internal representation of relocation info to BFD target | |
6095 | format. */ | |
6096 | ||
6097 | arelent * | |
30f725a1 | 6098 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
6099 | { |
6100 | arelent *reloc; | |
6101 | ||
325801bd TS |
6102 | reloc = XNEW (arelent); |
6103 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
e0001a05 NC |
6104 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
6105 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
6106 | ||
6107 | /* Make sure none of our internal relocations make it this far. | |
6108 | They'd better have been fully resolved by this point. */ | |
9c2799c2 | 6109 | gas_assert ((int) fixp->fx_r_type > 0); |
e0001a05 | 6110 | |
30f725a1 | 6111 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 6112 | |
e0001a05 NC |
6113 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
6114 | if (reloc->howto == NULL) | |
6115 | { | |
6116 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
6117 | _("cannot represent `%s' relocation in object file"), | |
6118 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
6119 | free (reloc->sym_ptr_ptr); |
6120 | free (reloc); | |
e0001a05 NC |
6121 | return NULL; |
6122 | } | |
6123 | ||
6124 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
1bbb5f21 | 6125 | as_fatal (_("internal error; cannot generate `%s' relocation"), |
43cd72b9 | 6126 | bfd_get_reloc_code_name (fixp->fx_r_type)); |
e0001a05 | 6127 | |
e0001a05 NC |
6128 | return reloc; |
6129 | } | |
6130 | ||
7fa3d080 BW |
6131 | \f |
6132 | /* Checks for resource conflicts between instructions. */ | |
6133 | ||
c138bc38 BW |
6134 | /* The func unit stuff could be implemented as bit-vectors rather |
6135 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
6136 | slow, we will switch it. */ |
6137 | ||
c138bc38 | 6138 | resource_table * |
7fa3d080 BW |
6139 | new_resource_table (void *data, |
6140 | int cycles, | |
6141 | int nu, | |
6142 | unit_num_copies_func uncf, | |
6143 | opcode_num_units_func onuf, | |
6144 | opcode_funcUnit_use_unit_func ouuf, | |
6145 | opcode_funcUnit_use_stage_func ousf) | |
6146 | { | |
6147 | int i; | |
325801bd | 6148 | resource_table *rt = XNEW (resource_table); |
7fa3d080 BW |
6149 | rt->data = data; |
6150 | rt->cycles = cycles; | |
6151 | rt->allocated_cycles = cycles; | |
6152 | rt->num_units = nu; | |
6153 | rt->unit_num_copies = uncf; | |
6154 | rt->opcode_num_units = onuf; | |
6155 | rt->opcode_unit_use = ouuf; | |
6156 | rt->opcode_unit_stage = ousf; | |
6157 | ||
add39d23 | 6158 | rt->units = XCNEWVEC (unsigned char *, cycles); |
7fa3d080 | 6159 | for (i = 0; i < cycles; i++) |
add39d23 | 6160 | rt->units[i] = XCNEWVEC (unsigned char, nu); |
7fa3d080 BW |
6161 | |
6162 | return rt; | |
6163 | } | |
6164 | ||
6165 | ||
c138bc38 | 6166 | void |
7fa3d080 BW |
6167 | clear_resource_table (resource_table *rt) |
6168 | { | |
6169 | int i, j; | |
6170 | for (i = 0; i < rt->allocated_cycles; i++) | |
6171 | for (j = 0; j < rt->num_units; j++) | |
6172 | rt->units[i][j] = 0; | |
6173 | } | |
6174 | ||
6175 | ||
6176 | /* We never shrink it, just fake it into thinking so. */ | |
6177 | ||
c138bc38 | 6178 | void |
7fa3d080 BW |
6179 | resize_resource_table (resource_table *rt, int cycles) |
6180 | { | |
6181 | int i, old_cycles; | |
6182 | ||
6183 | rt->cycles = cycles; | |
6184 | if (cycles <= rt->allocated_cycles) | |
6185 | return; | |
6186 | ||
6187 | old_cycles = rt->allocated_cycles; | |
6188 | rt->allocated_cycles = cycles; | |
6189 | ||
325801bd | 6190 | rt->units = XRESIZEVEC (unsigned char *, rt->units, rt->allocated_cycles); |
7fa3d080 | 6191 | for (i = 0; i < old_cycles; i++) |
325801bd | 6192 | rt->units[i] = XRESIZEVEC (unsigned char, rt->units[i], rt->num_units); |
7fa3d080 | 6193 | for (i = old_cycles; i < cycles; i++) |
add39d23 | 6194 | rt->units[i] = XCNEWVEC (unsigned char, rt->num_units); |
7fa3d080 BW |
6195 | } |
6196 | ||
6197 | ||
c138bc38 | 6198 | bfd_boolean |
7fa3d080 BW |
6199 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
6200 | { | |
6201 | int i; | |
6202 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6203 | ||
c138bc38 | 6204 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6205 | { |
6206 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6207 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
6208 | int copies_in_use = rt->units[stage + cycle][unit]; | |
6209 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
6210 | if (copies_in_use >= copies) | |
6211 | return FALSE; | |
6212 | } | |
6213 | return TRUE; | |
6214 | } | |
7fa3d080 | 6215 | |
c138bc38 BW |
6216 | |
6217 | void | |
7fa3d080 BW |
6218 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6219 | { | |
6220 | int i; | |
6221 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6222 | ||
c138bc38 | 6223 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6224 | { |
6225 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6226 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
6227 | /* Note that this allows resources to be oversubscribed. That's |
6228 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
6229 | resources_available reports when a resource is over-subscribed, |
6230 | so it's easy to tell. */ | |
6231 | rt->units[stage + cycle][unit]++; | |
6232 | } | |
6233 | } | |
6234 | ||
6235 | ||
c138bc38 | 6236 | void |
7fa3d080 BW |
6237 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6238 | { | |
6239 | int i; | |
6240 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6241 | ||
c138bc38 | 6242 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6243 | { |
6244 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6245 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
9c2799c2 | 6246 | gas_assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 6247 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
6248 | } |
6249 | } | |
c138bc38 | 6250 | |
7fa3d080 BW |
6251 | |
6252 | /* Wrapper functions make parameterized resource reservation | |
6253 | more convenient. */ | |
6254 | ||
c138bc38 | 6255 | int |
7fa3d080 BW |
6256 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
6257 | { | |
6258 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 6259 | return use->unit; |
7fa3d080 BW |
6260 | } |
6261 | ||
6262 | ||
c138bc38 | 6263 | int |
7fa3d080 BW |
6264 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
6265 | { | |
6266 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
6267 | return use->stage; | |
6268 | } | |
6269 | ||
6270 | ||
6271 | /* Note that this function does not check issue constraints, but | |
6272 | solely whether the hardware is available to execute the given | |
c138bc38 | 6273 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 6274 | write the same state, or access the same tieports. That is |
a1ace8d8 | 6275 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
6276 | |
6277 | static bfd_boolean | |
6278 | resources_conflict (vliw_insn *vinsn) | |
6279 | { | |
6280 | int i; | |
6281 | static resource_table *rt = NULL; | |
6282 | ||
6283 | /* This is the most common case by far. Optimize it. */ | |
6284 | if (vinsn->num_slots == 1) | |
6285 | return FALSE; | |
43cd72b9 | 6286 | |
c138bc38 | 6287 | if (rt == NULL) |
7fa3d080 BW |
6288 | { |
6289 | xtensa_isa isa = xtensa_default_isa; | |
6290 | rt = new_resource_table | |
77cba8a3 | 6291 | (isa, xtensa_num_pipe_stages, |
7fa3d080 BW |
6292 | xtensa_isa_num_funcUnits (isa), |
6293 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
6294 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
6295 | opcode_funcUnit_use_unit, | |
6296 | opcode_funcUnit_use_stage); | |
6297 | } | |
43cd72b9 | 6298 | |
7fa3d080 | 6299 | clear_resource_table (rt); |
43cd72b9 | 6300 | |
7fa3d080 BW |
6301 | for (i = 0; i < vinsn->num_slots; i++) |
6302 | { | |
6303 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
6304 | return TRUE; | |
6305 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
6306 | } | |
e0001a05 | 6307 | |
7fa3d080 BW |
6308 | return FALSE; |
6309 | } | |
e0001a05 | 6310 | |
7fa3d080 BW |
6311 | \f |
6312 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 6313 | |
7fa3d080 BW |
6314 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
6315 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 6316 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
6317 | |
6318 | ||
43cd72b9 BW |
6319 | /* We have reached the end of a bundle; emit into the frag. */ |
6320 | ||
e0001a05 | 6321 | static void |
7fa3d080 | 6322 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 6323 | { |
43cd72b9 BW |
6324 | IStack slotstack; |
6325 | int i; | |
bf3d1399 | 6326 | int slots; |
e0001a05 | 6327 | |
43cd72b9 | 6328 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
6329 | { |
6330 | xg_clear_vinsn (vinsn); | |
6331 | return; | |
6332 | } | |
43cd72b9 BW |
6333 | |
6334 | /* First, find a format that works. */ | |
6335 | if (vinsn->format == XTENSA_UNDEFINED) | |
6336 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6337 | ||
bf3d1399 AM |
6338 | slots = xtensa_format_num_slots (xtensa_default_isa, vinsn->format); |
6339 | if (slots > 1 | |
19fc3723 SA |
6340 | && produce_flix == FLIX_NONE) |
6341 | { | |
6342 | as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix.")); | |
6343 | xg_clear_vinsn (vinsn); | |
6344 | return; | |
6345 | } | |
6346 | ||
43cd72b9 BW |
6347 | if (vinsn->format == XTENSA_UNDEFINED) |
6348 | { | |
3b4dbbbf | 6349 | as_bad (_("couldn't find a valid instruction format")); |
43cd72b9 BW |
6350 | fprintf (stderr, _(" ops were: ")); |
6351 | for (i = 0; i < vinsn->num_slots; i++) | |
6352 | fprintf (stderr, _(" %s;"), | |
6353 | xtensa_opcode_name (xtensa_default_isa, | |
6354 | vinsn->slots[i].opcode)); | |
6355 | fprintf (stderr, _("\n")); | |
6356 | xg_clear_vinsn (vinsn); | |
6357 | return; | |
6358 | } | |
6359 | ||
bf3d1399 | 6360 | if (vinsn->num_slots != slots) |
e0001a05 | 6361 | { |
bf3d1399 AM |
6362 | as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"), |
6363 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
6e98b342 | 6364 | slots, vinsn->num_slots); |
43cd72b9 BW |
6365 | xg_clear_vinsn (vinsn); |
6366 | return; | |
6367 | } | |
e0001a05 | 6368 | |
c138bc38 | 6369 | if (resources_conflict (vinsn)) |
43cd72b9 | 6370 | { |
3b4dbbbf | 6371 | as_bad (_("illegal resource usage in bundle")); |
43cd72b9 BW |
6372 | fprintf (stderr, " ops were: "); |
6373 | for (i = 0; i < vinsn->num_slots; i++) | |
6374 | fprintf (stderr, " %s;", | |
6375 | xtensa_opcode_name (xtensa_default_isa, | |
6376 | vinsn->slots[i].opcode)); | |
6377 | fprintf (stderr, "\n"); | |
6378 | xg_clear_vinsn (vinsn); | |
6379 | return; | |
6380 | } | |
6381 | ||
6382 | for (i = 0; i < vinsn->num_slots; i++) | |
6383 | { | |
6384 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6385 | { |
43cd72b9 BW |
6386 | symbolS *lit_sym = NULL; |
6387 | int j; | |
6388 | bfd_boolean e = FALSE; | |
6389 | bfd_boolean saved_density = density_supported; | |
6390 | ||
6391 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6392 | if (vinsn->num_slots > 1) | |
6393 | density_supported = FALSE; | |
6394 | ||
6395 | istack_init (&slotstack); | |
6396 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6397 | { |
43cd72b9 BW |
6398 | vinsn->slots[i].opcode = |
6399 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6400 | vinsn->format, i); | |
6401 | vinsn->slots[i].ntok = 0; | |
6402 | } | |
e0001a05 | 6403 | |
43cd72b9 BW |
6404 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6405 | { | |
6406 | e = TRUE; | |
6407 | continue; | |
e0001a05 | 6408 | } |
e0001a05 | 6409 | |
43cd72b9 | 6410 | density_supported = saved_density; |
e0001a05 | 6411 | |
43cd72b9 BW |
6412 | if (e) |
6413 | { | |
6414 | xg_clear_vinsn (vinsn); | |
6415 | return; | |
6416 | } | |
e0001a05 | 6417 | |
0fa77c95 | 6418 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6419 | { |
6420 | TInsn *insn = &slotstack.insn[j]; | |
6421 | if (insn->insn_type == ITYPE_LITERAL) | |
6422 | { | |
9c2799c2 | 6423 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
6424 | lit_sym = xg_assemble_literal (insn); |
6425 | } | |
6426 | else | |
6427 | { | |
9c2799c2 | 6428 | gas_assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6429 | if (lit_sym) |
6430 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6431 | if (j != slotstack.ninsn - 1) |
6432 | emit_single_op (insn); | |
43cd72b9 BW |
6433 | } |
6434 | } | |
6435 | ||
6436 | if (vinsn->num_slots > 1) | |
6437 | { | |
6438 | if (opcode_fits_format_slot | |
6439 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6440 | vinsn->format, i)) | |
6441 | { | |
6442 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6443 | } | |
6444 | else | |
6445 | { | |
b2d179be | 6446 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6447 | if (vinsn->format == XTENSA_UNDEFINED) |
6448 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6449 | else | |
c138bc38 | 6450 | vinsn->slots[i].opcode |
43cd72b9 BW |
6451 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6452 | vinsn->format, i); | |
6453 | ||
6454 | vinsn->slots[i].ntok = 0; | |
6455 | } | |
6456 | } | |
6457 | else | |
6458 | { | |
6459 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6460 | vinsn->format = XTENSA_UNDEFINED; | |
6461 | } | |
6462 | } | |
6463 | } | |
6464 | ||
6465 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6466 | if (resources_conflict (vinsn)) |
43cd72b9 | 6467 | { |
3b4dbbbf | 6468 | as_bad (_("illegal resource usage in bundle")); |
43cd72b9 BW |
6469 | fprintf (stderr, " ops were: "); |
6470 | for (i = 0; i < vinsn->num_slots; i++) | |
6471 | fprintf (stderr, " %s;", | |
6472 | xtensa_opcode_name (xtensa_default_isa, | |
6473 | vinsn->slots[i].opcode)); | |
6474 | fprintf (stderr, "\n"); | |
6475 | xg_clear_vinsn (vinsn); | |
6476 | return; | |
6477 | } | |
6478 | ||
6479 | /* First, find a format that works. */ | |
6480 | if (vinsn->format == XTENSA_UNDEFINED) | |
6481 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6482 | ||
6483 | xg_assemble_vliw_tokens (vinsn); | |
6484 | ||
6485 | xg_clear_vinsn (vinsn); | |
a82c7d90 DW |
6486 | |
6487 | xtensa_check_frag_count (); | |
43cd72b9 BW |
6488 | } |
6489 | ||
6490 | ||
6491 | /* Given an vliw instruction, what conflicts are there in register | |
6492 | usage and in writes to states and queues? | |
6493 | ||
6494 | This function does two things: | |
6495 | 1. Reports an error when a vinsn contains illegal combinations | |
6496 | of writes to registers states or queues. | |
6497 | 2. Marks individual tinsns as not relaxable if the combination | |
6498 | contains antidependencies. | |
6499 | ||
6500 | Job 2 handles things like swap semantics in instructions that need | |
6501 | to be relaxed. For example, | |
6502 | ||
6503 | addi a0, a1, 100000 | |
6504 | ||
6505 | normally would be relaxed to | |
6506 | ||
6507 | l32r a0, some_label | |
6508 | add a0, a1, a0 | |
6509 | ||
6510 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6511 | ||
6512 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6513 | ||
6514 | then we can't relax it into | |
6515 | ||
6516 | l32r a0, some_label | |
6517 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6518 | ||
6519 | because the value of a0 is trashed before the second add can read it. */ | |
6520 | ||
7fa3d080 BW |
6521 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6522 | ||
43cd72b9 | 6523 | static bfd_boolean |
7fa3d080 | 6524 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6525 | { |
6526 | int i, j; | |
6527 | int branches = 0; | |
6528 | xtensa_isa isa = xtensa_default_isa; | |
6529 | ||
9c2799c2 | 6530 | gas_assert (!past_xtensa_end); |
43cd72b9 BW |
6531 | |
6532 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6533 | { | |
6534 | TInsn *op1 = &vinsn->slots[i]; | |
6535 | if (op1->is_specific_opcode) | |
6536 | op1->keep_wide = TRUE; | |
6537 | else | |
6538 | op1->keep_wide = FALSE; | |
6539 | } | |
6540 | ||
6541 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6542 | { | |
6543 | TInsn *op1 = &vinsn->slots[i]; | |
6544 | ||
6545 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6546 | branches++; | |
6547 | ||
6548 | for (j = 0; j < vinsn->num_slots; j++) | |
6549 | { | |
6550 | if (i != j) | |
6551 | { | |
6552 | TInsn *op2 = &vinsn->slots[j]; | |
6553 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6554 | switch (conflict_type) | |
6555 | { | |
6556 | case 'c': | |
6557 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6558 | xtensa_opcode_name (isa, op1->opcode), i, | |
6559 | xtensa_opcode_name (isa, op2->opcode), j); | |
6560 | return TRUE; | |
6561 | case 'd': | |
6562 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6563 | xtensa_opcode_name (isa, op1->opcode), i, | |
6564 | xtensa_opcode_name (isa, op2->opcode), j); | |
6565 | return TRUE; | |
6566 | case 'e': | |
53dfbcc7 | 6567 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6568 | xtensa_opcode_name (isa, op1->opcode), i, |
6569 | xtensa_opcode_name (isa, op2->opcode), j); | |
6570 | return TRUE; | |
6571 | case 'f': | |
53dfbcc7 | 6572 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6573 | xtensa_opcode_name (isa, op1->opcode), i, |
6574 | xtensa_opcode_name (isa, op2->opcode), j); | |
6575 | return TRUE; | |
6576 | default: | |
6577 | /* Everything is OK. */ | |
6578 | break; | |
6579 | } | |
6580 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6581 | || conflict_type == 'a'); | |
6582 | } | |
6583 | } | |
6584 | } | |
6585 | ||
6586 | if (branches > 1) | |
6587 | { | |
6588 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6589 | return TRUE; | |
6590 | } | |
6591 | ||
6592 | return FALSE; | |
6593 | } | |
6594 | ||
6595 | ||
a1ace8d8 | 6596 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6597 | Cases found are: |
6598 | ||
6599 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6600 | case B: no relationship between what is read and written (both could | |
6601 | read the same reg though) | |
c138bc38 | 6602 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6603 | bundle) |
6604 | case D: t1 writes a state that t2 also writes | |
6605 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6606 | case F: two volatile queue accesses |
43cd72b9 BW |
6607 | */ |
6608 | ||
6609 | static char | |
7fa3d080 | 6610 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6611 | { |
6612 | xtensa_isa isa = xtensa_default_isa; | |
6613 | xtensa_regfile t1_regfile, t2_regfile; | |
6614 | int t1_reg, t2_reg; | |
6615 | int t1_base_reg, t1_last_reg; | |
6616 | int t2_base_reg, t2_last_reg; | |
6617 | char t1_inout, t2_inout; | |
6618 | int i, j; | |
6619 | char conflict = 'b'; | |
6620 | int t1_states; | |
6621 | int t2_states; | |
6622 | int t1_interfaces; | |
6623 | int t2_interfaces; | |
6624 | bfd_boolean t1_volatile = FALSE; | |
6625 | bfd_boolean t2_volatile = FALSE; | |
6626 | ||
6627 | /* Check registers. */ | |
6628 | for (j = 0; j < t2->ntok; j++) | |
6629 | { | |
6630 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6631 | continue; | |
6632 | ||
6633 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6634 | t2_base_reg = t2->tok[j].X_add_number; | |
6635 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6636 | ||
6637 | for (i = 0; i < t1->ntok; i++) | |
6638 | { | |
6639 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6640 | continue; | |
6641 | ||
6642 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6643 | ||
6644 | if (t1_regfile != t2_regfile) | |
6645 | continue; | |
6646 | ||
6647 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6648 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6649 | ||
6650 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6651 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6652 | { | |
6653 | if (t1_inout == 'm' || t1_inout == 'o' | |
6654 | || t2_inout == 'm' || t2_inout == 'o') | |
6655 | { | |
6656 | conflict = 'a'; | |
6657 | continue; | |
6658 | } | |
6659 | } | |
6660 | ||
6661 | t1_base_reg = t1->tok[i].X_add_number; | |
6662 | t1_last_reg = (t1_base_reg | |
6663 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6664 | ||
6665 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6666 | { | |
6667 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6668 | { | |
6669 | if (t1_reg != t2_reg) | |
6670 | continue; | |
6671 | ||
6672 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6673 | { |
6674 | conflict = 'a'; | |
6675 | continue; | |
6676 | } | |
43cd72b9 | 6677 | |
7fa3d080 BW |
6678 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6679 | { | |
6680 | conflict = 'a'; | |
6681 | continue; | |
6682 | } | |
43cd72b9 | 6683 | |
7fa3d080 BW |
6684 | if (t1_inout != 'i' && t2_inout != 'i') |
6685 | return 'c'; | |
6686 | } | |
6687 | } | |
6688 | } | |
6689 | } | |
43cd72b9 | 6690 | |
7fa3d080 BW |
6691 | /* Check states. */ |
6692 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6693 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6694 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6695 | { |
7fa3d080 BW |
6696 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6697 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6698 | for (i = 0; i < t1_states; i++) | |
6699 | { | |
6700 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6701 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
1fa3cd83 | 6702 | if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1) |
7fa3d080 | 6703 | continue; |
43cd72b9 | 6704 | |
7fa3d080 BW |
6705 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6706 | { | |
6707 | conflict = 'a'; | |
6708 | continue; | |
6709 | } | |
c138bc38 | 6710 | |
7fa3d080 BW |
6711 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6712 | { | |
6713 | conflict = 'a'; | |
6714 | continue; | |
6715 | } | |
c138bc38 | 6716 | |
7fa3d080 BW |
6717 | if (t1_inout != 'i' && t2_inout != 'i') |
6718 | return 'd'; | |
c138bc38 | 6719 | } |
7fa3d080 | 6720 | } |
43cd72b9 | 6721 | |
7fa3d080 BW |
6722 | /* Check tieports. */ |
6723 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6724 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6725 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6726 | { |
7fa3d080 BW |
6727 | xtensa_interface t2_int |
6728 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6729 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6730 | ||
53dfbcc7 | 6731 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6732 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6733 | t2_volatile = TRUE; |
a1ace8d8 | 6734 | |
7fa3d080 BW |
6735 | for (i = 0; i < t1_interfaces; i++) |
6736 | { | |
6737 | xtensa_interface t1_int | |
6738 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6739 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6740 | |
53dfbcc7 | 6741 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6742 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6743 | t1_volatile = TRUE; |
a1ace8d8 BW |
6744 | |
6745 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6746 | return 'f'; | |
c138bc38 | 6747 | |
7fa3d080 BW |
6748 | if (t1_int != t2_int) |
6749 | continue; | |
c138bc38 | 6750 | |
7fa3d080 BW |
6751 | if (t2_inout == 'i' && t1_inout == 'o') |
6752 | { | |
6753 | conflict = 'a'; | |
6754 | continue; | |
6755 | } | |
c138bc38 | 6756 | |
7fa3d080 BW |
6757 | if (t1_inout == 'i' && t2_inout == 'o') |
6758 | { | |
6759 | conflict = 'a'; | |
6760 | continue; | |
6761 | } | |
c138bc38 | 6762 | |
7fa3d080 BW |
6763 | if (t1_inout != 'i' && t2_inout != 'i') |
6764 | return 'e'; | |
6765 | } | |
43cd72b9 | 6766 | } |
c138bc38 | 6767 | |
7fa3d080 | 6768 | return conflict; |
43cd72b9 BW |
6769 | } |
6770 | ||
6771 | ||
6772 | static xtensa_format | |
7fa3d080 | 6773 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6774 | { |
6775 | /* Right now we assume that the ops within the vinsn are properly | |
6776 | ordered for the slots that the programmer wanted them in. In | |
6777 | other words, we don't rearrange the ops in hopes of finding a | |
6778 | better format. The scheduler handles that. */ | |
6779 | ||
6780 | xtensa_isa isa = xtensa_default_isa; | |
6781 | xtensa_format format; | |
43cd72b9 BW |
6782 | xtensa_opcode nop_opcode = xtensa_nop_opcode; |
6783 | ||
65738a7d BW |
6784 | if (vinsn->num_slots == 1) |
6785 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6786 | ||
43cd72b9 BW |
6787 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6788 | { | |
d8392fd9 SA |
6789 | vliw_insn v_copy; |
6790 | xg_copy_vinsn (&v_copy, vinsn); | |
43cd72b9 BW |
6791 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) |
6792 | { | |
6793 | int slot; | |
6794 | int fit = 0; | |
6795 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6796 | { | |
6797 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6798 | { | |
6799 | v_copy.slots[slot].opcode = | |
6800 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6801 | v_copy.slots[slot].ntok = 0; | |
6802 | } | |
6803 | ||
6804 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6805 | format, slot)) | |
6806 | fit++; | |
7fa3d080 | 6807 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6808 | { |
7fa3d080 BW |
6809 | TInsn widened; |
6810 | /* Try the widened version. */ | |
6811 | if (!v_copy.slots[slot].keep_wide | |
6812 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6813 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6814 | &widened, TRUE) | |
7fa3d080 BW |
6815 | && opcode_fits_format_slot (widened.opcode, |
6816 | format, slot)) | |
43cd72b9 | 6817 | { |
7fa3d080 BW |
6818 | v_copy.slots[slot] = widened; |
6819 | fit++; | |
43cd72b9 BW |
6820 | } |
6821 | } | |
6822 | } | |
6823 | if (fit == v_copy.num_slots) | |
6824 | { | |
d8392fd9 | 6825 | xg_copy_vinsn (vinsn, &v_copy); |
43cd72b9 BW |
6826 | xtensa_format_encode (isa, format, vinsn->insnbuf); |
6827 | vinsn->format = format; | |
6828 | break; | |
6829 | } | |
6830 | } | |
6831 | } | |
6832 | ||
6833 | if (format == xtensa_isa_num_formats (isa)) | |
6834 | return XTENSA_UNDEFINED; | |
6835 | ||
6836 | return format; | |
6837 | } | |
6838 | ||
6839 | ||
6840 | /* Return the additional space needed in a frag | |
6841 | for possible relaxations of any ops in a VLIW insn. | |
6842 | Also fill out the relaxations that might be required of | |
6843 | each tinsn in the vinsn. */ | |
6844 | ||
6845 | static int | |
e7da6241 | 6846 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6847 | { |
e7da6241 | 6848 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6849 | int extra_space = 0; |
6850 | int slot; | |
6851 | ||
6852 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6853 | { | |
6854 | TInsn *tinsn = &vinsn->slots[slot]; | |
6855 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6856 | { | |
6857 | /* A narrow instruction could be widened later to help | |
6858 | alignment issues. */ | |
84b08ed9 | 6859 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6860 | && !tinsn->is_specific_opcode |
6861 | && vinsn->num_slots == 1) | |
6862 | { | |
6863 | /* Difference in bytes between narrow and wide insns... */ | |
6864 | extra_space += 1; | |
6865 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6866 | } |
6867 | } | |
6868 | else | |
6869 | { | |
b08b5071 BW |
6870 | if (workaround_b_j_loop_end |
6871 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6872 | && use_transform ()) |
6873 | { | |
6874 | /* Add 2 of these. */ | |
6875 | extra_space += 3; /* for the nop size */ | |
6876 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6877 | } | |
c138bc38 | 6878 | |
43cd72b9 BW |
6879 | /* Need to assemble it with space for the relocation. */ |
6880 | if (xg_is_relaxable_insn (tinsn, 0) | |
6881 | && !tinsn->is_specific_opcode) | |
6882 | { | |
6883 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6884 | int max_literal_size = | |
6885 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6886 | |
43cd72b9 | 6887 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6888 | |
43cd72b9 | 6889 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6890 | extra_space += max_size; |
6891 | } | |
6892 | else | |
6893 | { | |
e7da6241 BW |
6894 | /* A fix record will be added for this instruction prior |
6895 | to relaxation, so make it end the frag. */ | |
6896 | finish_frag = TRUE; | |
43cd72b9 BW |
6897 | } |
6898 | } | |
6899 | } | |
e7da6241 | 6900 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6901 | return extra_space; |
6902 | } | |
6903 | ||
6904 | ||
6905 | static void | |
b2d179be | 6906 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6907 | { |
6908 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6909 | int slot, chosen_slot; |
43cd72b9 | 6910 | |
b2d179be | 6911 | vinsn->format = xg_get_single_format (tinsn->opcode); |
9c2799c2 | 6912 | gas_assert (vinsn->format != XTENSA_UNDEFINED); |
b2d179be | 6913 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); |
43cd72b9 | 6914 | |
b2d179be BW |
6915 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6916 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6917 | { |
b2d179be BW |
6918 | if (slot == chosen_slot) |
6919 | vinsn->slots[slot] = *tinsn; | |
6920 | else | |
6921 | { | |
6922 | vinsn->slots[slot].opcode = | |
6923 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6924 | vinsn->slots[slot].ntok = 0; | |
6925 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6926 | } | |
43cd72b9 | 6927 | } |
43cd72b9 BW |
6928 | } |
6929 | ||
6930 | ||
6931 | static bfd_boolean | |
7fa3d080 | 6932 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6933 | { |
6934 | int i; | |
6935 | IStack istack; /* put instructions into here */ | |
6936 | symbolS *lit_sym = NULL; | |
6937 | symbolS *label_sym = NULL; | |
6938 | ||
6939 | istack_init (&istack); | |
6940 | ||
6941 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
6942 | Because the scheduling and bundling characteristics of movi and |
6943 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 6944 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 6945 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
6946 | || orig_insn->opcode == xtensa_movi_n_opcode) |
6947 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 6948 | && (orig_insn->tok[1].X_op == O_symbol |
28dbbc02 BW |
6949 | || orig_insn->tok[1].X_op == O_pltrel |
6950 | || orig_insn->tok[1].X_op == O_tlsfunc | |
6951 | || orig_insn->tok[1].X_op == O_tlsarg | |
6952 | || orig_insn->tok[1].X_op == O_tpoff | |
6953 | || orig_insn->tok[1].X_op == O_dtpoff) | |
482fd9f9 | 6954 | && !orig_insn->is_specific_opcode && use_transform ()) |
43cd72b9 BW |
6955 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
6956 | else | |
6957 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6958 | return TRUE; | |
6959 | ||
6960 | for (i = 0; i < istack.ninsn; i++) | |
6961 | { | |
6962 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 6963 | switch (insn->insn_type) |
43cd72b9 BW |
6964 | { |
6965 | case ITYPE_LITERAL: | |
9c2799c2 | 6966 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
6967 | lit_sym = xg_assemble_literal (insn); |
6968 | break; | |
6969 | case ITYPE_LABEL: | |
6970 | { | |
6971 | static int relaxed_sym_idx = 0; | |
325801bd | 6972 | char *label = XNEWVEC (char, strlen (FAKE_LABEL_NAME) + 12); |
43cd72b9 BW |
6973 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); |
6974 | colon (label); | |
9c2799c2 | 6975 | gas_assert (label_sym == NULL); |
43cd72b9 | 6976 | label_sym = symbol_find_or_make (label); |
9c2799c2 | 6977 | gas_assert (label_sym); |
43cd72b9 BW |
6978 | free (label); |
6979 | } | |
6980 | break; | |
6981 | case ITYPE_INSN: | |
b2d179be BW |
6982 | { |
6983 | vliw_insn v; | |
6984 | if (lit_sym) | |
6985 | xg_resolve_literals (insn, lit_sym); | |
6986 | if (label_sym) | |
6987 | xg_resolve_labels (insn, label_sym); | |
6988 | xg_init_vinsn (&v); | |
6989 | bundle_tinsn (insn, &v); | |
6990 | finish_vinsn (&v); | |
6991 | xg_free_vinsn (&v); | |
6992 | } | |
43cd72b9 BW |
6993 | break; |
6994 | default: | |
9c2799c2 | 6995 | gas_assert (0); |
43cd72b9 BW |
6996 | break; |
6997 | } | |
6998 | } | |
6999 | return FALSE; | |
7000 | } | |
7001 | ||
7002 | ||
34e41783 BW |
7003 | static int |
7004 | total_frag_text_expansion (fragS *fragP) | |
7005 | { | |
7006 | int slot; | |
7007 | int total_expansion = 0; | |
7008 | ||
62af60e2 | 7009 | for (slot = 0; slot < config_max_slots; slot++) |
34e41783 BW |
7010 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; |
7011 | ||
7012 | return total_expansion; | |
7013 | } | |
7014 | ||
7015 | ||
43cd72b9 BW |
7016 | /* Emit a vliw instruction to the current fragment. */ |
7017 | ||
7fa3d080 BW |
7018 | static void |
7019 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 7020 | { |
e7da6241 | 7021 | bfd_boolean finish_frag; |
43cd72b9 BW |
7022 | bfd_boolean is_jump = FALSE; |
7023 | bfd_boolean is_branch = FALSE; | |
7024 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 BW |
7025 | int insn_size; |
7026 | int extra_space; | |
7027 | char *f = NULL; | |
7028 | int slot; | |
b224e962 BW |
7029 | struct dwarf2_line_info debug_line; |
7030 | bfd_boolean loc_directive_seen = FALSE; | |
7031 | TInsn *tinsn; | |
43cd72b9 | 7032 | |
b224e962 | 7033 | memset (&debug_line, 0, sizeof (struct dwarf2_line_info)); |
43cd72b9 BW |
7034 | |
7035 | if (generating_literals) | |
7036 | { | |
7037 | static int reported = 0; | |
7038 | if (reported < 4) | |
7039 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
7040 | _("cannot assemble into a literal fragment")); | |
7041 | if (reported == 3) | |
7042 | as_bad (_("...")); | |
7043 | reported++; | |
7044 | return; | |
7045 | } | |
7046 | ||
7047 | if (frag_now_fix () != 0 | |
b08b5071 | 7048 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 7049 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
28a0da39 | 7050 | || (!use_transform ()) != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
7051 | || (directive_state[directive_longcalls] |
7052 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
7053 | || (directive_state[directive_absolute_literals] |
7054 | != frag_now->tc_frag_data.use_absolute_literals))) | |
7055 | { | |
7056 | frag_wane (frag_now); | |
7057 | frag_new (0); | |
7058 | xtensa_set_frag_assembly_state (frag_now); | |
7059 | } | |
7060 | ||
7061 | if (workaround_a0_b_retw | |
7062 | && vinsn->num_slots == 1 | |
7063 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
7064 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
7065 | && use_transform ()) | |
7066 | { | |
7067 | has_a0_b_retw = TRUE; | |
7068 | ||
7069 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
7070 | After the first assembly pass we will check all of them and | |
7071 | add a nop if needed. */ | |
7072 | frag_now->tc_frag_data.is_insn = TRUE; | |
7073 | frag_var (rs_machine_dependent, 4, 4, | |
7074 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
7075 | frag_now->fr_symbol, | |
7076 | frag_now->fr_offset, | |
7077 | NULL); | |
7078 | xtensa_set_frag_assembly_state (frag_now); | |
7079 | frag_now->tc_frag_data.is_insn = TRUE; | |
7080 | frag_var (rs_machine_dependent, 4, 4, | |
7081 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
7082 | frag_now->fr_symbol, | |
7083 | frag_now->fr_offset, | |
7084 | NULL); | |
7085 | xtensa_set_frag_assembly_state (frag_now); | |
7086 | } | |
7087 | ||
b224e962 | 7088 | for (slot = 0; slot < vinsn->num_slots; slot++) |
43cd72b9 | 7089 | { |
b224e962 BW |
7090 | tinsn = &vinsn->slots[slot]; |
7091 | ||
43cd72b9 | 7092 | /* See if the instruction implies an aligned section. */ |
b224e962 | 7093 | if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1) |
43cd72b9 | 7094 | record_alignment (now_seg, 2); |
c138bc38 | 7095 | |
b224e962 BW |
7096 | /* Determine the best line number for debug info. */ |
7097 | if ((tinsn->loc_directive_seen || !loc_directive_seen) | |
7098 | && (tinsn->debug_line.filenum != debug_line.filenum | |
7099 | || tinsn->debug_line.line < debug_line.line | |
7100 | || tinsn->debug_line.column < debug_line.column)) | |
7101 | debug_line = tinsn->debug_line; | |
7102 | if (tinsn->loc_directive_seen) | |
7103 | loc_directive_seen = TRUE; | |
43cd72b9 BW |
7104 | } |
7105 | ||
7106 | /* Special cases for instructions that force an alignment... */ | |
7107 | /* None of these opcodes are bundle-able. */ | |
7108 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
7109 | { | |
d77b99c9 | 7110 | int max_fill; |
c138bc38 | 7111 | |
05d58145 BW |
7112 | /* Remember the symbol that marks the end of the loop in the frag |
7113 | that marks the start of the loop. This way we can easily find | |
7114 | the end of the loop at the beginning, without adding special code | |
7115 | to mark the loop instructions themselves. */ | |
7116 | symbolS *target_sym = NULL; | |
7117 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
7118 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
7119 | ||
43cd72b9 BW |
7120 | xtensa_set_frag_assembly_state (frag_now); |
7121 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 7122 | |
43cd72b9 BW |
7123 | max_fill = get_text_align_max_fill_size |
7124 | (get_text_align_power (xtensa_fetch_width), | |
7125 | TRUE, frag_now->tc_frag_data.is_no_density); | |
7126 | ||
7127 | if (use_transform ()) | |
7128 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 7129 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7130 | else |
c138bc38 | 7131 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 7132 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7133 | xtensa_set_frag_assembly_state (frag_now); |
43cd72b9 BW |
7134 | } |
7135 | ||
b08b5071 | 7136 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
7137 | && !vinsn->slots[0].is_specific_opcode) |
7138 | { | |
7139 | xtensa_mark_literal_pool_location (); | |
c3ea6048 | 7140 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
7141 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); |
7142 | } | |
7143 | ||
7144 | if (vinsn->num_slots == 1) | |
7145 | { | |
7146 | if (workaround_a0_b_retw && use_transform ()) | |
7147 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
7148 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
7149 | ||
7150 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
7151 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
7152 | } | |
7153 | else | |
7154 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
7155 | ||
7156 | insn_size = xtensa_format_length (isa, vinsn->format); | |
7157 | ||
e7da6241 | 7158 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
7159 | |
7160 | /* vinsn_to_insnbuf will produce the error. */ | |
7161 | if (vinsn->format != XTENSA_UNDEFINED) | |
7162 | { | |
d77b99c9 | 7163 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
7164 | xtensa_set_frag_assembly_state (frag_now); |
7165 | frag_now->tc_frag_data.is_insn = TRUE; | |
7166 | } | |
7167 | ||
e7da6241 | 7168 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
7169 | if (vinsn->format == XTENSA_UNDEFINED) |
7170 | return; | |
7171 | ||
d77b99c9 | 7172 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 7173 | |
b224e962 BW |
7174 | if (debug_type == DEBUG_DWARF2 || loc_directive_seen) |
7175 | dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space), | |
7176 | &debug_line); | |
43cd72b9 BW |
7177 | |
7178 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
7179 | { | |
b224e962 | 7180 | tinsn = &vinsn->slots[slot]; |
43cd72b9 | 7181 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; |
7c834684 | 7182 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 7183 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 | 7184 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
b46824bd MF |
7185 | if (tinsn->opcode == xtensa_l32r_opcode) |
7186 | { | |
7187 | frag_now->tc_frag_data.literal_frags[slot] = | |
7188 | tinsn->tok[1].X_add_symbol->sy_frag; | |
7189 | } | |
43cd72b9 BW |
7190 | if (tinsn->literal_space != 0) |
7191 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
19e8f41a | 7192 | frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg; |
43cd72b9 BW |
7193 | |
7194 | if (tinsn->subtype == RELAX_NARROW) | |
9c2799c2 | 7195 | gas_assert (vinsn->num_slots == 1); |
43cd72b9 BW |
7196 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) |
7197 | is_jump = TRUE; | |
7198 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
7199 | is_branch = TRUE; | |
7200 | ||
e7da6241 BW |
7201 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
7202 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
7203 | finish_frag = TRUE; |
7204 | } | |
7205 | ||
7206 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 7207 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
7208 | |
7209 | if (finish_frag) | |
7210 | { | |
7211 | frag_variant (rs_machine_dependent, | |
7212 | extra_space, extra_space, RELAX_SLOTS, | |
7213 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
7214 | xtensa_set_frag_assembly_state (frag_now); | |
7215 | } | |
7216 | ||
7217 | /* Special cases for loops: | |
7218 | close_loop_end should be inserted AFTER short_loop. | |
7219 | Make sure that CLOSE loops are processed BEFORE short_loops | |
7220 | when converting them. */ | |
7221 | ||
7222 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 7223 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
7224 | && !vinsn->slots[0].is_specific_opcode) |
7225 | { | |
7226 | if (workaround_short_loop && use_transform ()) | |
7227 | { | |
7228 | maybe_has_short_loop = TRUE; | |
7229 | frag_now->tc_frag_data.is_insn = TRUE; | |
7230 | frag_var (rs_machine_dependent, 4, 4, | |
7231 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7232 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7233 | frag_now->tc_frag_data.is_insn = TRUE; | |
7234 | frag_var (rs_machine_dependent, 4, 4, | |
7235 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7236 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7237 | } | |
7238 | ||
7239 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
7240 | loop at least 12 bytes away from another loop's end. */ | |
7241 | if (workaround_close_loop_end && use_transform ()) | |
7242 | { | |
7243 | maybe_has_close_loop_end = TRUE; | |
7244 | frag_now->tc_frag_data.is_insn = TRUE; | |
7245 | frag_var (rs_machine_dependent, 12, 12, | |
7246 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
7247 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7248 | } | |
7249 | } | |
7250 | ||
7251 | if (use_transform ()) | |
7252 | { | |
7253 | if (is_jump) | |
7254 | { | |
9c2799c2 | 7255 | gas_assert (finish_frag); |
43cd72b9 | 7256 | frag_var (rs_machine_dependent, |
1beeb686 | 7257 | xtensa_fetch_width, xtensa_fetch_width, |
43cd72b9 BW |
7258 | RELAX_UNREACHABLE, |
7259 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7260 | xtensa_set_frag_assembly_state (frag_now); | |
a82c7d90 | 7261 | xtensa_maybe_create_trampoline_frag (); |
b46824bd MF |
7262 | /* Always create one here. */ |
7263 | xtensa_maybe_create_literal_pool_frag (TRUE, FALSE); | |
43cd72b9 | 7264 | } |
7b1cc377 | 7265 | else if (is_branch && do_align_targets ()) |
43cd72b9 | 7266 | { |
9c2799c2 | 7267 | gas_assert (finish_frag); |
43cd72b9 | 7268 | frag_var (rs_machine_dependent, |
1beeb686 | 7269 | xtensa_fetch_width, xtensa_fetch_width, |
43cd72b9 BW |
7270 | RELAX_MAYBE_UNREACHABLE, |
7271 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7272 | xtensa_set_frag_assembly_state (frag_now); | |
7273 | frag_var (rs_machine_dependent, | |
7274 | 0, 0, | |
7275 | RELAX_MAYBE_DESIRE_ALIGN, | |
7276 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7277 | xtensa_set_frag_assembly_state (frag_now); | |
7278 | } | |
7279 | } | |
7280 | ||
7281 | /* Now, if the original opcode was a call... */ | |
7282 | if (do_align_targets () | |
7283 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
7284 | { | |
b08b5071 | 7285 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
7286 | frag_now->tc_frag_data.is_insn = TRUE; |
7287 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
7288 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7289 | xtensa_set_frag_assembly_state (frag_now); | |
7290 | } | |
7291 | ||
7292 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
7293 | { | |
7294 | frag_wane (frag_now); | |
7295 | frag_new (0); | |
7296 | xtensa_set_frag_assembly_state (frag_now); | |
7297 | } | |
7298 | } | |
7299 | ||
7300 | \f | |
7fa3d080 BW |
7301 | /* xtensa_end and helper functions. */ |
7302 | ||
7303 | static void xtensa_cleanup_align_frags (void); | |
7304 | static void xtensa_fix_target_frags (void); | |
7305 | static void xtensa_mark_narrow_branches (void); | |
7306 | static void xtensa_mark_zcl_first_insns (void); | |
6a7eedfe | 7307 | static void xtensa_mark_difference_of_two_symbols (void); |
7fa3d080 BW |
7308 | static void xtensa_fix_a0_b_retw_frags (void); |
7309 | static void xtensa_fix_b_j_loop_end_frags (void); | |
7310 | static void xtensa_fix_close_loop_end_frags (void); | |
7311 | static void xtensa_fix_short_loop_frags (void); | |
7312 | static void xtensa_sanity_check (void); | |
2caa7ca0 | 7313 | static void xtensa_add_config_info (void); |
7fa3d080 | 7314 | |
43cd72b9 | 7315 | void |
7fa3d080 | 7316 | xtensa_end (void) |
43cd72b9 BW |
7317 | { |
7318 | directive_balance (); | |
7319 | xtensa_flush_pending_output (); | |
7320 | ||
7321 | past_xtensa_end = TRUE; | |
7322 | ||
7323 | xtensa_move_literals (); | |
7324 | ||
7325 | xtensa_reorder_segments (); | |
7326 | xtensa_cleanup_align_frags (); | |
7327 | xtensa_fix_target_frags (); | |
7328 | if (workaround_a0_b_retw && has_a0_b_retw) | |
7329 | xtensa_fix_a0_b_retw_frags (); | |
7330 | if (workaround_b_j_loop_end) | |
7331 | xtensa_fix_b_j_loop_end_frags (); | |
7332 | ||
7333 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
7334 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
7335 | xtensa_fix_close_loop_end_frags (); | |
7336 | ||
7337 | if (workaround_short_loop && maybe_has_short_loop) | |
7338 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
7339 | if (align_targets) |
7340 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
7341 | xtensa_mark_zcl_first_insns (); |
7342 | ||
7343 | xtensa_sanity_check (); | |
2caa7ca0 BW |
7344 | |
7345 | xtensa_add_config_info (); | |
a82c7d90 DW |
7346 | |
7347 | xtensa_check_frag_count (); | |
43cd72b9 BW |
7348 | } |
7349 | ||
7350 | ||
a82c7d90 DW |
7351 | struct trampoline_frag |
7352 | { | |
7353 | struct trampoline_frag *next; | |
7354 | bfd_boolean needs_jump_around; | |
7355 | fragS *fragP; | |
7356 | fixS *fixP; | |
7357 | }; | |
7358 | ||
7359 | struct trampoline_seg | |
7360 | { | |
7361 | struct trampoline_seg *next; | |
7362 | asection *seg; | |
7363 | struct trampoline_frag trampoline_list; | |
7364 | }; | |
7365 | ||
7366 | static struct trampoline_seg trampoline_seg_list; | |
7367 | #define J_RANGE (128 * 1024) | |
7368 | ||
7369 | static int unreachable_count = 0; | |
7370 | ||
7371 | ||
7372 | static void | |
7373 | xtensa_maybe_create_trampoline_frag (void) | |
7374 | { | |
7375 | if (!use_trampolines) | |
7376 | return; | |
7377 | ||
7378 | /* We create an area for possible trampolines every 10 unreachable frags. | |
7379 | These are preferred over the ones not preceded by an unreachable frag, | |
7380 | because we don't have to jump around them. This function is called after | |
7381 | each RELAX_UNREACHABLE frag is created. */ | |
7382 | ||
7383 | if (++unreachable_count > 10) | |
7384 | { | |
7385 | xtensa_create_trampoline_frag (FALSE); | |
7386 | clear_frag_count (); | |
7387 | unreachable_count = 0; | |
7388 | } | |
7389 | } | |
7390 | ||
7391 | static void | |
7392 | xtensa_check_frag_count (void) | |
7393 | { | |
7394 | if (!use_trampolines || frag_now->tc_frag_data.is_no_transform) | |
7395 | return; | |
7396 | ||
7397 | /* We create an area for possible trampolines every 8000 frags or so. This | |
7398 | is an estimate based on the max range of a "j" insn (+/-128K) divided | |
7399 | by a typical frag byte count (16), minus a few for safety. This function | |
7400 | is called after each source line is processed. */ | |
7401 | ||
7402 | if (get_frag_count () > 8000) | |
7403 | { | |
7404 | xtensa_create_trampoline_frag (TRUE); | |
7405 | clear_frag_count (); | |
7406 | unreachable_count = 0; | |
7407 | } | |
b46824bd MF |
7408 | |
7409 | /* We create an area for a possible literal pool every N (default 5000) | |
7410 | frags or so. */ | |
7411 | xtensa_maybe_create_literal_pool_frag (TRUE, TRUE); | |
a82c7d90 DW |
7412 | } |
7413 | ||
7414 | static xtensa_insnbuf trampoline_buf = NULL; | |
7415 | static xtensa_insnbuf trampoline_slotbuf = NULL; | |
7416 | ||
b46824bd MF |
7417 | static xtensa_insnbuf litpool_buf = NULL; |
7418 | static xtensa_insnbuf litpool_slotbuf = NULL; | |
7419 | ||
a82c7d90 DW |
7420 | #define TRAMPOLINE_FRAG_SIZE 3000 |
7421 | ||
7422 | static void | |
7423 | xtensa_create_trampoline_frag (bfd_boolean needs_jump_around) | |
7424 | { | |
7425 | /* Emit a frag where we can place intermediate jump instructions, | |
7426 | in case we need to jump farther than 128K bytes. | |
7427 | Each jump instruction takes three bytes. | |
7428 | We allocate enough for 1000 trampolines in each frag. | |
7429 | If that's not enough, oh well. */ | |
7430 | ||
7431 | struct trampoline_seg *ts = trampoline_seg_list.next; | |
7432 | struct trampoline_frag *tf; | |
7433 | char *varP; | |
7434 | fragS *fragP; | |
7435 | int size = TRAMPOLINE_FRAG_SIZE; | |
7436 | ||
7437 | for ( ; ts; ts = ts->next) | |
7438 | { | |
7439 | if (ts->seg == now_seg) | |
7440 | break; | |
7441 | } | |
7442 | ||
7443 | if (ts == NULL) | |
7444 | { | |
add39d23 | 7445 | ts = XCNEW(struct trampoline_seg); |
a82c7d90 DW |
7446 | ts->next = trampoline_seg_list.next; |
7447 | trampoline_seg_list.next = ts; | |
7448 | ts->seg = now_seg; | |
7449 | } | |
7450 | ||
7451 | frag_wane (frag_now); | |
7452 | frag_new (0); | |
7453 | xtensa_set_frag_assembly_state (frag_now); | |
7454 | varP = frag_var (rs_machine_dependent, size, size, RELAX_TRAMPOLINE, NULL, 0, NULL); | |
7455 | fragP = (fragS *)(varP - SIZEOF_STRUCT_FRAG); | |
7456 | if (trampoline_buf == NULL) | |
7457 | { | |
7458 | trampoline_buf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7459 | trampoline_slotbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7460 | } | |
325801bd | 7461 | tf = XNEW (struct trampoline_frag); |
a82c7d90 DW |
7462 | tf->next = ts->trampoline_list.next; |
7463 | ts->trampoline_list.next = tf; | |
7464 | tf->needs_jump_around = needs_jump_around; | |
7465 | tf->fragP = fragP; | |
7466 | tf->fixP = NULL; | |
7467 | } | |
7468 | ||
7469 | ||
7470 | static struct trampoline_seg * | |
7471 | find_trampoline_seg (asection *seg) | |
7472 | { | |
7473 | struct trampoline_seg *ts = trampoline_seg_list.next; | |
7474 | ||
7475 | for ( ; ts; ts = ts->next) | |
7476 | { | |
7477 | if (ts->seg == seg) | |
7478 | return ts; | |
7479 | } | |
7480 | ||
7481 | return NULL; | |
7482 | } | |
7483 | ||
7484 | ||
7485 | void dump_trampolines (void); | |
7486 | ||
7487 | void | |
7488 | dump_trampolines (void) | |
7489 | { | |
7490 | struct trampoline_seg *ts = trampoline_seg_list.next; | |
7491 | ||
7492 | for ( ; ts; ts = ts->next) | |
7493 | { | |
7494 | asection *seg = ts->seg; | |
7495 | ||
7496 | if (seg == NULL) | |
7497 | continue; | |
7498 | fprintf(stderr, "SECTION %s\n", seg->name); | |
7499 | struct trampoline_frag *tf = ts->trampoline_list.next; | |
7500 | for ( ; tf; tf = tf->next) | |
7501 | { | |
7502 | if (tf->fragP == NULL) | |
7503 | continue; | |
7504 | fprintf(stderr, " 0x%08x: fix=%d, jump_around=%s\n", | |
7505 | (int)tf->fragP->fr_address, (int)tf->fragP->fr_fix, | |
7506 | tf->needs_jump_around ? "T" : "F"); | |
7507 | } | |
7508 | } | |
7509 | } | |
7510 | ||
b46824bd MF |
7511 | static void dump_litpools (void) __attribute__ ((unused)); |
7512 | ||
7513 | static void | |
7514 | dump_litpools (void) | |
7515 | { | |
7516 | struct litpool_seg *lps = litpool_seg_list.next; | |
7517 | struct litpool_frag *lpf; | |
7518 | ||
7519 | for ( ; lps ; lps = lps->next ) | |
7520 | { | |
7521 | printf("litpool seg %s\n", lps->seg->name); | |
7522 | for ( lpf = lps->frag_list.next; lpf->fragP; lpf = lpf->next ) | |
7523 | { | |
7524 | fragS *litfrag = lpf->fragP->fr_next; | |
7525 | int count = 0; | |
7526 | while (litfrag && litfrag->fr_subtype != RELAX_LITERAL_POOL_END) | |
7527 | { | |
7528 | if (litfrag->fr_fix == 4) | |
7529 | count++; | |
7530 | litfrag = litfrag->fr_next; | |
7531 | } | |
7532 | printf(" %ld <%d:%d> (%d) [%d]: ", | |
7533 | lpf->addr, lpf->priority, lpf->original_priority, | |
7534 | lpf->fragP->fr_line, count); | |
7535 | //dump_frag(lpf->fragP); | |
7536 | } | |
7537 | } | |
7538 | } | |
7539 | ||
7540 | static void | |
7541 | xtensa_maybe_create_literal_pool_frag (bfd_boolean create, | |
7542 | bfd_boolean only_if_needed) | |
7543 | { | |
7544 | struct litpool_seg *lps = litpool_seg_list.next; | |
7545 | fragS *fragP; | |
7546 | struct litpool_frag *lpf; | |
7547 | bfd_boolean needed = FALSE; | |
7548 | ||
7549 | if (use_literal_section || !auto_litpools) | |
7550 | return; | |
7551 | ||
7552 | for ( ; lps ; lps = lps->next ) | |
7553 | { | |
7554 | if (lps->seg == now_seg) | |
7555 | break; | |
7556 | } | |
7557 | ||
7558 | if (lps == NULL) | |
7559 | { | |
add39d23 | 7560 | lps = XCNEW (struct litpool_seg); |
b46824bd MF |
7561 | lps->next = litpool_seg_list.next; |
7562 | litpool_seg_list.next = lps; | |
7563 | lps->seg = now_seg; | |
7564 | lps->frag_list.next = &lps->frag_list; | |
7565 | lps->frag_list.prev = &lps->frag_list; | |
947fa914 MF |
7566 | /* Put candidate literal pool at the beginning of every section, |
7567 | so that even when section starts with literal load there's a | |
7568 | literal pool available. */ | |
7569 | lps->frag_count = auto_litpool_limit; | |
b46824bd MF |
7570 | } |
7571 | ||
7572 | lps->frag_count++; | |
7573 | ||
7574 | if (create) | |
7575 | { | |
7576 | if (only_if_needed) | |
7577 | { | |
7578 | if (past_xtensa_end || !use_transform() || | |
7579 | frag_now->tc_frag_data.is_no_transform) | |
7580 | { | |
7581 | return; | |
7582 | } | |
7583 | if (auto_litpool_limit <= 0) | |
7584 | { | |
7585 | /* Don't create a litpool based only on frag count. */ | |
7586 | return; | |
7587 | } | |
7588 | else if (lps->frag_count > auto_litpool_limit) | |
7589 | { | |
7590 | needed = TRUE; | |
7591 | } | |
7592 | else | |
7593 | { | |
7594 | return; | |
7595 | } | |
7596 | } | |
7597 | else | |
7598 | { | |
7599 | needed = TRUE; | |
7600 | } | |
7601 | } | |
7602 | ||
7603 | if (needed) | |
7604 | { | |
7605 | int size = (only_if_needed) ? 3 : 0; /* Space for a "j" insn. */ | |
7606 | /* Create a potential site for a literal pool. */ | |
7607 | frag_wane (frag_now); | |
7608 | frag_new (0); | |
7609 | xtensa_set_frag_assembly_state (frag_now); | |
7610 | fragP = frag_now; | |
7611 | fragP->tc_frag_data.lit_frchain = frchain_now; | |
7612 | fragP->tc_frag_data.literal_frag = fragP; | |
7613 | frag_var (rs_machine_dependent, size, size, | |
7614 | (only_if_needed) ? | |
7615 | RELAX_LITERAL_POOL_CANDIDATE_BEGIN : | |
7616 | RELAX_LITERAL_POOL_BEGIN, | |
7617 | NULL, 0, NULL); | |
7618 | frag_now->tc_frag_data.lit_seg = now_seg; | |
7619 | frag_variant (rs_machine_dependent, 0, 0, | |
7620 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); | |
7621 | xtensa_set_frag_assembly_state (frag_now); | |
7622 | } | |
7623 | else | |
7624 | { | |
7625 | /* RELAX_LITERAL_POOL_BEGIN frag is being created; | |
7626 | just record it here. */ | |
7627 | fragP = frag_now; | |
7628 | } | |
7629 | ||
325801bd | 7630 | lpf = XNEW (struct litpool_frag); |
b46824bd MF |
7631 | /* Insert at tail of circular list. */ |
7632 | lpf->addr = 0; | |
7633 | lps->frag_list.prev->next = lpf; | |
7634 | lpf->next = &lps->frag_list; | |
7635 | lpf->prev = lps->frag_list.prev; | |
7636 | lps->frag_list.prev = lpf; | |
7637 | lpf->fragP = fragP; | |
7638 | lpf->priority = (needed) ? (only_if_needed) ? 3 : 2 : 1; | |
7639 | lpf->original_priority = lpf->priority; | |
7640 | ||
7641 | lps->frag_count = 0; | |
7642 | } | |
7643 | ||
43cd72b9 | 7644 | static void |
7fa3d080 | 7645 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
7646 | { |
7647 | frchainS *frchP; | |
c9049d30 | 7648 | asection *s; |
43cd72b9 | 7649 | |
c9049d30 AM |
7650 | for (s = stdoutput->sections; s; s = s->next) |
7651 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7652 | { | |
7653 | fragS *fragP; | |
7654 | /* Walk over all of the fragments in a subsection. */ | |
7655 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7656 | { | |
7657 | if ((fragP->fr_type == rs_align | |
7658 | || fragP->fr_type == rs_align_code | |
7659 | || (fragP->fr_type == rs_machine_dependent | |
7660 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
7661 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
7662 | && fragP->fr_fix == 0) | |
7663 | { | |
7664 | fragS *next = fragP->fr_next; | |
7665 | ||
7666 | while (next | |
7667 | && next->fr_fix == 0 | |
7668 | && next->fr_type == rs_machine_dependent | |
7669 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7670 | { | |
7671 | frag_wane (next); | |
7672 | next = next->fr_next; | |
7673 | } | |
7674 | } | |
7675 | /* If we don't widen branch targets, then they | |
7676 | will be easier to align. */ | |
7677 | if (fragP->tc_frag_data.is_branch_target | |
7678 | && fragP->fr_opcode == fragP->fr_literal | |
7679 | && fragP->fr_type == rs_machine_dependent | |
7680 | && fragP->fr_subtype == RELAX_SLOTS | |
7681 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
7682 | frag_wane (fragP); | |
7683 | if (fragP->fr_type == rs_machine_dependent | |
7684 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
7685 | fragP->tc_frag_data.is_unreachable = TRUE; | |
7686 | } | |
7687 | } | |
43cd72b9 BW |
7688 | } |
7689 | ||
7690 | ||
7691 | /* Re-process all of the fragments looking to convert all of the | |
7692 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
7693 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 7694 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 7695 | |
43cd72b9 | 7696 | static void |
7fa3d080 | 7697 | xtensa_fix_target_frags (void) |
e0001a05 NC |
7698 | { |
7699 | frchainS *frchP; | |
c9049d30 | 7700 | asection *s; |
e0001a05 NC |
7701 | |
7702 | /* When this routine is called, all of the subsections are still intact | |
7703 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7704 | for (s = stdoutput->sections; s; s = s->next) |
7705 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7706 | { | |
7707 | fragS *fragP; | |
e0001a05 | 7708 | |
c9049d30 AM |
7709 | /* Walk over all of the fragments in a subsection. */ |
7710 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7711 | { | |
7712 | if (fragP->fr_type == rs_machine_dependent | |
7713 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7714 | { | |
7715 | if (next_frag_is_branch_target (fragP)) | |
7716 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
7717 | else | |
7718 | frag_wane (fragP); | |
7719 | } | |
7720 | } | |
7721 | } | |
e0001a05 NC |
7722 | } |
7723 | ||
7724 | ||
7fa3d080 BW |
7725 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7726 | ||
43cd72b9 | 7727 | static void |
7fa3d080 | 7728 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
7729 | { |
7730 | frchainS *frchP; | |
c9049d30 | 7731 | asection *s; |
43cd72b9 | 7732 | |
c9049d30 AM |
7733 | for (s = stdoutput->sections; s; s = s->next) |
7734 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7735 | { | |
7736 | fragS *fragP; | |
7737 | /* Walk over all of the fragments in a subsection. */ | |
7738 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7739 | { | |
7740 | if (fragP->fr_type == rs_machine_dependent | |
7741 | && fragP->fr_subtype == RELAX_SLOTS | |
7742 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
7743 | { | |
7744 | vliw_insn vinsn; | |
7745 | ||
7746 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
7747 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
7748 | ||
7749 | if (vinsn.num_slots == 1 | |
7750 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 7751 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
7752 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
7753 | && is_narrow_branch_guaranteed_in_range (fragP, | |
7754 | &vinsn.slots[0])) | |
7755 | { | |
7756 | fragP->fr_subtype = RELAX_SLOTS; | |
7757 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
7758 | fragP->tc_frag_data.is_aligning_branch = 1; | |
7759 | } | |
7760 | } | |
7761 | } | |
7762 | } | |
43cd72b9 BW |
7763 | } |
7764 | ||
7765 | ||
7766 | /* A branch is typically widened only when its target is out of | |
7767 | range. However, we would like to widen them to align a subsequent | |
7768 | branch target when possible. | |
7769 | ||
7770 | Because the branch relaxation code is so convoluted, the optimal solution | |
7771 | (combining the two cases) is difficult to get right in all circumstances. | |
7772 | We therefore go with an "almost as good" solution, where we only | |
7773 | use for alignment narrow branches that definitely will not expand to a | |
7774 | jump and a branch. These functions find and mark these cases. */ | |
7775 | ||
a67517f4 BW |
7776 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
7777 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
7778 | We start counting beginning with the frag after the 2-byte branch, so the | |
7779 | maximum offset is (4 - 2) + 63 = 65. */ | |
7780 | #define MAX_IMMED6 65 | |
43cd72b9 | 7781 | |
d77b99c9 | 7782 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 7783 | |
43cd72b9 | 7784 | static bfd_boolean |
7fa3d080 | 7785 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 | 7786 | { |
91d6fa6a NC |
7787 | const expressionS *exp = &tinsn->tok[1]; |
7788 | symbolS *symbolP = exp->X_add_symbol; | |
7789 | offsetT max_distance = exp->X_add_number; | |
e7da6241 BW |
7790 | fragS *target_frag; |
7791 | ||
91d6fa6a | 7792 | if (exp->X_op != O_symbol) |
e7da6241 BW |
7793 | return FALSE; |
7794 | ||
7795 | target_frag = symbol_get_frag (symbolP); | |
7796 | ||
43cd72b9 BW |
7797 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
7798 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
7799 | return FALSE; | |
7800 | ||
7801 | /* The branch doesn't branch over it's own frag, | |
7802 | but over the subsequent ones. */ | |
7803 | fragP = fragP->fr_next; | |
7804 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
7805 | { | |
7806 | max_distance += unrelaxed_frag_max_size (fragP); | |
7807 | fragP = fragP->fr_next; | |
7808 | } | |
7809 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
7810 | return TRUE; | |
e0001a05 NC |
7811 | return FALSE; |
7812 | } | |
7813 | ||
7814 | ||
43cd72b9 | 7815 | static void |
7fa3d080 | 7816 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
7817 | { |
7818 | frchainS *frchP; | |
c9049d30 | 7819 | asection *s; |
43cd72b9 | 7820 | |
c9049d30 AM |
7821 | for (s = stdoutput->sections; s; s = s->next) |
7822 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7823 | { | |
7824 | fragS *fragP; | |
7825 | /* Walk over all of the fragments in a subsection. */ | |
7826 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7827 | { | |
7828 | if (fragP->fr_type == rs_machine_dependent | |
7829 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
7830 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
7831 | { | |
7832 | /* Find the loop frag. */ | |
3a1e9c4a | 7833 | fragS *loop_frag = next_non_empty_frag (fragP); |
c9049d30 | 7834 | /* Find the first insn frag. */ |
3a1e9c4a SA |
7835 | fragS *targ_frag = next_non_empty_frag (loop_frag); |
7836 | ||
7837 | /* Handle a corner case that comes up in hardware | |
7838 | diagnostics. The original assembly looks like this: | |
3739860c | 7839 | |
3a1e9c4a SA |
7840 | loop aX, LabelA |
7841 | <empty_frag>--not found by next_non_empty_frag | |
7842 | loop aY, LabelB | |
7843 | ||
7844 | Depending on the start address, the assembler may or | |
7845 | may not change it to look something like this: | |
7846 | ||
7847 | loop aX, LabelA | |
7848 | nop--frag isn't empty anymore | |
7849 | loop aY, LabelB | |
7850 | ||
7851 | So set up to check the alignment of the nop if it | |
7852 | exists */ | |
7853 | while (loop_frag != targ_frag) | |
7854 | { | |
7855 | if (loop_frag->fr_type == rs_machine_dependent | |
7856 | && (loop_frag->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
3739860c | 7857 | || loop_frag->fr_subtype |
3a1e9c4a SA |
7858 | == RELAX_CHECK_ALIGN_NEXT_OPCODE)) |
7859 | targ_frag = loop_frag; | |
7860 | else | |
7861 | loop_frag = loop_frag->fr_next; | |
7862 | } | |
c9049d30 AM |
7863 | |
7864 | /* Of course, sometimes (mostly for toy test cases) a | |
7865 | zero-cost loop instruction is the last in a section. */ | |
7866 | if (targ_frag) | |
7867 | { | |
7868 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
7869 | /* Do not widen a frag that is the first instruction of a | |
7870 | zero-cost loop. It makes that loop harder to align. */ | |
7871 | if (targ_frag->fr_type == rs_machine_dependent | |
7872 | && targ_frag->fr_subtype == RELAX_SLOTS | |
7873 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
7874 | == RELAX_NARROW)) | |
7875 | { | |
7876 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
7877 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
7878 | else | |
7879 | { | |
7880 | frag_wane (targ_frag); | |
7881 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
7882 | } | |
7883 | } | |
7884 | } | |
7885 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
7886 | frag_wane (fragP); | |
7887 | } | |
7888 | } | |
7889 | } | |
43cd72b9 BW |
7890 | } |
7891 | ||
7892 | ||
fb227da0 BW |
7893 | /* When a difference-of-symbols expression is encoded as a uleb128 or |
7894 | sleb128 value, the linker is unable to adjust that value to account for | |
7895 | link-time relaxation. Mark all the code between such symbols so that | |
7896 | its size cannot be changed by linker relaxation. */ | |
3739860c | 7897 | |
6a7eedfe BW |
7898 | static void |
7899 | xtensa_mark_difference_of_two_symbols (void) | |
7900 | { | |
7901 | symbolS *expr_sym; | |
7902 | ||
3739860c | 7903 | for (expr_sym = expr_symbols; expr_sym; |
6a7eedfe BW |
7904 | expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) |
7905 | { | |
91d6fa6a | 7906 | expressionS *exp = symbol_get_value_expression (expr_sym); |
6a7eedfe | 7907 | |
91d6fa6a | 7908 | if (exp->X_op == O_subtract) |
6a7eedfe | 7909 | { |
91d6fa6a NC |
7910 | symbolS *left = exp->X_add_symbol; |
7911 | symbolS *right = exp->X_op_symbol; | |
3739860c | 7912 | |
6a7eedfe BW |
7913 | /* Difference of two symbols not in the same section |
7914 | are handled with relocations in the linker. */ | |
7915 | if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) | |
7916 | { | |
7917 | fragS *start; | |
7918 | fragS *end; | |
983f90e3 | 7919 | fragS *walk; |
6a7eedfe | 7920 | |
3739860c | 7921 | if (symbol_get_frag (left)->fr_address |
6a7eedfe BW |
7922 | <= symbol_get_frag (right)->fr_address) |
7923 | { | |
7924 | start = symbol_get_frag (left); | |
7925 | end = symbol_get_frag (right); | |
7926 | } | |
7927 | else | |
7928 | { | |
7929 | start = symbol_get_frag (right); | |
7930 | end = symbol_get_frag (left); | |
7931 | } | |
983f90e3 SA |
7932 | |
7933 | if (start->tc_frag_data.no_transform_end != NULL) | |
7934 | walk = start->tc_frag_data.no_transform_end; | |
7935 | else | |
7936 | walk = start; | |
3739860c | 7937 | do |
6a7eedfe | 7938 | { |
983f90e3 SA |
7939 | walk->tc_frag_data.is_no_transform = 1; |
7940 | walk = walk->fr_next; | |
6a7eedfe | 7941 | } |
983f90e3 SA |
7942 | while (walk && walk->fr_address < end->fr_address); |
7943 | ||
7944 | start->tc_frag_data.no_transform_end = walk; | |
6a7eedfe BW |
7945 | } |
7946 | } | |
7947 | } | |
7948 | } | |
7949 | ||
7950 | ||
e0001a05 NC |
7951 | /* Re-process all of the fragments looking to convert all of the |
7952 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
7953 | conditional branch or a retw/retw.n, convert this frag to one that | |
7954 | will generate a NOP. In any case close it off with a .fill 0. */ | |
7955 | ||
7fa3d080 BW |
7956 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
7957 | ||
e0001a05 | 7958 | static void |
7fa3d080 | 7959 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
7960 | { |
7961 | frchainS *frchP; | |
c9049d30 | 7962 | asection *s; |
e0001a05 NC |
7963 | |
7964 | /* When this routine is called, all of the subsections are still intact | |
7965 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7966 | for (s = stdoutput->sections; s; s = s->next) |
7967 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7968 | { | |
7969 | fragS *fragP; | |
e0001a05 | 7970 | |
c9049d30 AM |
7971 | /* Walk over all of the fragments in a subsection. */ |
7972 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7973 | { | |
7974 | if (fragP->fr_type == rs_machine_dependent | |
7975 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
7976 | { | |
7977 | if (next_instrs_are_b_retw (fragP)) | |
7978 | { | |
7979 | if (fragP->tc_frag_data.is_no_transform) | |
7980 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
7981 | else | |
7982 | relax_frag_add_nop (fragP); | |
7983 | } | |
7984 | frag_wane (fragP); | |
7985 | } | |
7986 | } | |
7987 | } | |
e0001a05 NC |
7988 | } |
7989 | ||
7990 | ||
7fa3d080 BW |
7991 | static bfd_boolean |
7992 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
7993 | { |
7994 | xtensa_opcode opcode; | |
43cd72b9 | 7995 | xtensa_format fmt; |
e0001a05 NC |
7996 | const fragS *next_fragP = next_non_empty_frag (fragP); |
7997 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 7998 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
7999 | xtensa_isa isa = xtensa_default_isa; |
8000 | int offset = 0; | |
43cd72b9 BW |
8001 | int slot; |
8002 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
8003 | |
8004 | if (!insnbuf) | |
43cd72b9 BW |
8005 | { |
8006 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8007 | slotbuf = xtensa_insnbuf_alloc (isa); | |
8008 | } | |
e0001a05 NC |
8009 | |
8010 | if (next_fragP == NULL) | |
8011 | return FALSE; | |
8012 | ||
8013 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
8014 | xtensa_insnbuf_from_chars |
8015 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
8016 | fmt = xtensa_format_decode (isa, insnbuf); |
8017 | if (fmt == XTENSA_UNDEFINED) | |
8018 | return FALSE; | |
8019 | ||
8020 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
8021 | { | |
8022 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
8023 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
8024 | ||
8025 | branch_seen = (branch_seen | |
8026 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
8027 | } | |
e0001a05 | 8028 | |
43cd72b9 | 8029 | if (!branch_seen) |
e0001a05 NC |
8030 | return FALSE; |
8031 | ||
43cd72b9 | 8032 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8033 | if (offset == next_fragP->fr_fix) |
8034 | { | |
8035 | next_fragP = next_non_empty_frag (next_fragP); | |
8036 | offset = 0; | |
8037 | } | |
43cd72b9 | 8038 | |
e0001a05 NC |
8039 | if (next_fragP == NULL) |
8040 | return FALSE; | |
8041 | ||
8042 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
8043 | xtensa_insnbuf_from_chars |
8044 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
8045 | fmt = xtensa_format_decode (isa, insnbuf); |
8046 | ||
8047 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
8048 | have no problems. */ | |
8049 | if (fmt == XTENSA_UNDEFINED | |
8050 | || xtensa_format_num_slots (isa, fmt) != 1) | |
8051 | return FALSE; | |
8052 | ||
8053 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
8054 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 8055 | |
b08b5071 | 8056 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 8057 | return TRUE; |
43cd72b9 | 8058 | |
e0001a05 NC |
8059 | return FALSE; |
8060 | } | |
8061 | ||
8062 | ||
8063 | /* Re-process all of the fragments looking to convert all of the | |
8064 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
8065 | loop end label, convert this frag to one that will generate a NOP. | |
8066 | In any case close it off with a .fill 0. */ | |
8067 | ||
7fa3d080 BW |
8068 | static bfd_boolean next_instr_is_loop_end (fragS *); |
8069 | ||
e0001a05 | 8070 | static void |
7fa3d080 | 8071 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
8072 | { |
8073 | frchainS *frchP; | |
c9049d30 | 8074 | asection *s; |
e0001a05 NC |
8075 | |
8076 | /* When this routine is called, all of the subsections are still intact | |
8077 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8078 | for (s = stdoutput->sections; s; s = s->next) |
8079 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8080 | { | |
8081 | fragS *fragP; | |
e0001a05 | 8082 | |
c9049d30 AM |
8083 | /* Walk over all of the fragments in a subsection. */ |
8084 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8085 | { | |
8086 | if (fragP->fr_type == rs_machine_dependent | |
8087 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
8088 | { | |
8089 | if (next_instr_is_loop_end (fragP)) | |
8090 | { | |
8091 | if (fragP->tc_frag_data.is_no_transform) | |
8092 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
8093 | else | |
8094 | relax_frag_add_nop (fragP); | |
8095 | } | |
8096 | frag_wane (fragP); | |
8097 | } | |
8098 | } | |
8099 | } | |
e0001a05 NC |
8100 | } |
8101 | ||
8102 | ||
7fa3d080 BW |
8103 | static bfd_boolean |
8104 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
8105 | { |
8106 | const fragS *next_fragP; | |
8107 | ||
8108 | if (next_frag_is_loop_target (fragP)) | |
8109 | return FALSE; | |
8110 | ||
8111 | next_fragP = next_non_empty_frag (fragP); | |
8112 | if (next_fragP == NULL) | |
8113 | return FALSE; | |
8114 | ||
8115 | if (!next_frag_is_loop_target (next_fragP)) | |
8116 | return FALSE; | |
8117 | ||
8118 | /* If the size is >= 3 then there is more than one instruction here. | |
8119 | The hardware bug will not fire. */ | |
8120 | if (next_fragP->fr_fix > 3) | |
8121 | return FALSE; | |
8122 | ||
8123 | return TRUE; | |
8124 | } | |
8125 | ||
8126 | ||
8127 | /* Re-process all of the fragments looking to convert all of the | |
8128 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
8129 | not MY loop's loop end within 12 bytes, add enough nops here to | |
8130 | make it at least 12 bytes away. In any case close it off with a | |
8131 | .fill 0. */ | |
8132 | ||
d77b99c9 | 8133 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 8134 | (fragS *, fragS *, offsetT); |
7fa3d080 | 8135 | |
e0001a05 | 8136 | static void |
7fa3d080 | 8137 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
8138 | { |
8139 | frchainS *frchP; | |
c9049d30 | 8140 | asection *s; |
e0001a05 NC |
8141 | |
8142 | /* When this routine is called, all of the subsections are still intact | |
8143 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8144 | for (s = stdoutput->sections; s; s = s->next) |
8145 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8146 | { | |
8147 | fragS *fragP; | |
e0001a05 | 8148 | |
c9049d30 | 8149 | fragS *current_target = NULL; |
e0001a05 | 8150 | |
c9049d30 AM |
8151 | /* Walk over all of the fragments in a subsection. */ |
8152 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8153 | { | |
8154 | if (fragP->fr_type == rs_machine_dependent | |
8155 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
8156 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 8157 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 8158 | |
c9049d30 AM |
8159 | if (current_target |
8160 | && fragP->fr_type == rs_machine_dependent | |
8161 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
8162 | { | |
8163 | offsetT min_bytes; | |
8164 | int bytes_added = 0; | |
e0001a05 NC |
8165 | |
8166 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
8167 | /* Max out at 12. */ |
8168 | min_bytes = min_bytes_to_other_loop_end | |
8169 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
8170 | ||
8171 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
8172 | { | |
8173 | if (fragP->tc_frag_data.is_no_transform) | |
8174 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
8175 | else | |
8176 | { | |
8177 | while (min_bytes + bytes_added | |
8178 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
8179 | { | |
8180 | int length = 3; | |
8181 | ||
8182 | if (fragP->fr_var < length) | |
8183 | as_fatal (_("fr_var %lu < length %d"), | |
8184 | (long) fragP->fr_var, length); | |
8185 | else | |
8186 | { | |
8187 | assemble_nop (length, | |
8188 | fragP->fr_literal + fragP->fr_fix); | |
8189 | fragP->fr_fix += length; | |
8190 | fragP->fr_var -= length; | |
8191 | } | |
8192 | bytes_added += length; | |
8193 | } | |
8194 | } | |
8195 | } | |
8196 | frag_wane (fragP); | |
8197 | } | |
9c2799c2 | 8198 | gas_assert (fragP->fr_type != rs_machine_dependent |
c9049d30 AM |
8199 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); |
8200 | } | |
8201 | } | |
e0001a05 NC |
8202 | } |
8203 | ||
8204 | ||
d77b99c9 | 8205 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 8206 | |
d77b99c9 | 8207 | static offsetT |
7fa3d080 BW |
8208 | min_bytes_to_other_loop_end (fragS *fragP, |
8209 | fragS *current_target, | |
d77b99c9 | 8210 | offsetT max_size) |
e0001a05 | 8211 | { |
d77b99c9 | 8212 | offsetT offset = 0; |
e0001a05 NC |
8213 | fragS *current_fragP; |
8214 | ||
8215 | for (current_fragP = fragP; | |
8216 | current_fragP; | |
8217 | current_fragP = current_fragP->fr_next) | |
8218 | { | |
8219 | if (current_fragP->tc_frag_data.is_loop_target | |
8220 | && current_fragP != current_target) | |
05d58145 | 8221 | return offset; |
e0001a05 NC |
8222 | |
8223 | offset += unrelaxed_frag_min_size (current_fragP); | |
8224 | ||
05d58145 | 8225 | if (offset >= max_size) |
e0001a05 NC |
8226 | return max_size; |
8227 | } | |
8228 | return max_size; | |
8229 | } | |
8230 | ||
8231 | ||
d77b99c9 | 8232 | static offsetT |
7fa3d080 | 8233 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 8234 | { |
d77b99c9 | 8235 | offsetT size = fragP->fr_fix; |
e0001a05 | 8236 | |
d77b99c9 | 8237 | /* Add fill size. */ |
e0001a05 NC |
8238 | if (fragP->fr_type == rs_fill) |
8239 | size += fragP->fr_offset; | |
8240 | ||
8241 | return size; | |
8242 | } | |
8243 | ||
8244 | ||
d77b99c9 | 8245 | static offsetT |
7fa3d080 | 8246 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 8247 | { |
d77b99c9 | 8248 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
8249 | switch (fragP->fr_type) |
8250 | { | |
8251 | case 0: | |
c138bc38 | 8252 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
8253 | end up with type 0. */ |
8254 | break; | |
8255 | case rs_fill: | |
8256 | case rs_org: | |
8257 | case rs_space: | |
8258 | size += fragP->fr_offset; | |
8259 | break; | |
8260 | case rs_align: | |
8261 | case rs_align_code: | |
8262 | case rs_align_test: | |
8263 | case rs_leb128: | |
8264 | case rs_cfa: | |
8265 | case rs_dwarf2dbg: | |
8266 | /* No further adjustments needed. */ | |
8267 | break; | |
8268 | case rs_machine_dependent: | |
8269 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
8270 | size += fragP->fr_var; | |
8271 | break; | |
8272 | default: | |
8273 | /* We had darn well better know how big it is. */ | |
9c2799c2 | 8274 | gas_assert (0); |
43cd72b9 BW |
8275 | break; |
8276 | } | |
8277 | ||
8278 | return size; | |
8279 | } | |
8280 | ||
8281 | ||
e0001a05 NC |
8282 | /* Re-process all of the fragments looking to convert all |
8283 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
8284 | ||
8285 | A) | |
8286 | 1) the instruction size count to the loop end label | |
8287 | is too short (<= 2 instructions), | |
8288 | 2) loop has a jump or branch in it | |
8289 | ||
8290 | or B) | |
43cd72b9 | 8291 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
8292 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
8293 | 3) the instruction size count to the loop end label is too short | |
8294 | (<= 2 instructions) | |
8295 | then convert this frag (and maybe the next one) to generate a NOP. | |
8296 | In any case close it off with a .fill 0. */ | |
8297 | ||
d77b99c9 | 8298 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
8299 | static bfd_boolean branch_before_loop_end (fragS *); |
8300 | ||
e0001a05 | 8301 | static void |
7fa3d080 | 8302 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
8303 | { |
8304 | frchainS *frchP; | |
c9049d30 | 8305 | asection *s; |
e0001a05 NC |
8306 | |
8307 | /* When this routine is called, all of the subsections are still intact | |
8308 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8309 | for (s = stdoutput->sections; s; s = s->next) |
8310 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8311 | { | |
8312 | fragS *fragP; | |
c9049d30 | 8313 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; |
e0001a05 | 8314 | |
c9049d30 AM |
8315 | /* Walk over all of the fragments in a subsection. */ |
8316 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8317 | { | |
8318 | if (fragP->fr_type == rs_machine_dependent | |
8319 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
8320 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
8321 | { | |
8322 | TInsn t_insn; | |
8323 | fragS *loop_frag = next_non_empty_frag (fragP); | |
8324 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
c9049d30 | 8325 | current_opcode = t_insn.opcode; |
9c2799c2 | 8326 | gas_assert (xtensa_opcode_is_loop (xtensa_default_isa, |
64b607e6 | 8327 | current_opcode) == 1); |
c9049d30 | 8328 | } |
e0001a05 | 8329 | |
c9049d30 AM |
8330 | if (fragP->fr_type == rs_machine_dependent |
8331 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
8332 | { | |
8333 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 | |
8334 | && (branch_before_loop_end (fragP->fr_next) | |
8335 | || (workaround_all_short_loops | |
8336 | && current_opcode != XTENSA_UNDEFINED | |
8337 | && current_opcode != xtensa_loop_opcode))) | |
8338 | { | |
8339 | if (fragP->tc_frag_data.is_no_transform) | |
8340 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
8341 | else | |
8342 | relax_frag_add_nop (fragP); | |
8343 | } | |
8344 | frag_wane (fragP); | |
8345 | } | |
8346 | } | |
8347 | } | |
e0001a05 NC |
8348 | } |
8349 | ||
8350 | ||
d77b99c9 | 8351 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 8352 | |
d77b99c9 | 8353 | static int |
7fa3d080 BW |
8354 | count_insns_to_loop_end (fragS *base_fragP, |
8355 | bfd_boolean count_relax_add, | |
d77b99c9 | 8356 | int max_count) |
e0001a05 NC |
8357 | { |
8358 | fragS *fragP = NULL; | |
d77b99c9 | 8359 | int insn_count = 0; |
e0001a05 NC |
8360 | |
8361 | fragP = base_fragP; | |
8362 | ||
8363 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
8364 | { | |
8365 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
8366 | if (insn_count >= max_count) | |
8367 | return max_count; | |
8368 | ||
8369 | if (count_relax_add) | |
8370 | { | |
8371 | if (fragP->fr_type == rs_machine_dependent | |
8372 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
8373 | { | |
8374 | /* In order to add the appropriate number of | |
8375 | NOPs, we count an instruction for downstream | |
8376 | occurrences. */ | |
8377 | insn_count++; | |
8378 | if (insn_count >= max_count) | |
8379 | return max_count; | |
8380 | } | |
8381 | } | |
8382 | } | |
8383 | return insn_count; | |
8384 | } | |
8385 | ||
8386 | ||
d77b99c9 | 8387 | static int |
7fa3d080 | 8388 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 8389 | { |
43cd72b9 BW |
8390 | xtensa_isa isa = xtensa_default_isa; |
8391 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 8392 | int insn_count = 0; |
e0001a05 NC |
8393 | int offset = 0; |
8394 | ||
8395 | if (!fragP->tc_frag_data.is_insn) | |
8396 | return insn_count; | |
8397 | ||
43cd72b9 BW |
8398 | if (!insnbuf) |
8399 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8400 | ||
e0001a05 NC |
8401 | /* Decode the fixed instructions. */ |
8402 | while (offset < fragP->fr_fix) | |
8403 | { | |
43cd72b9 BW |
8404 | xtensa_format fmt; |
8405 | ||
d77b99c9 BW |
8406 | xtensa_insnbuf_from_chars |
8407 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
8408 | fmt = xtensa_format_decode (isa, insnbuf); |
8409 | ||
8410 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
8411 | { |
8412 | as_fatal (_("undecodable instruction in instruction frag")); | |
8413 | return insn_count; | |
8414 | } | |
43cd72b9 | 8415 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8416 | insn_count++; |
8417 | } | |
8418 | ||
8419 | return insn_count; | |
8420 | } | |
8421 | ||
8422 | ||
7fa3d080 BW |
8423 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
8424 | ||
43cd72b9 | 8425 | static bfd_boolean |
7fa3d080 | 8426 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
8427 | { |
8428 | fragS *fragP; | |
8429 | ||
8430 | for (fragP = base_fragP; | |
8431 | fragP && !fragP->tc_frag_data.is_loop_target; | |
8432 | fragP = fragP->fr_next) | |
8433 | { | |
8434 | if (unrelaxed_frag_has_b_j (fragP)) | |
8435 | return TRUE; | |
8436 | } | |
8437 | return FALSE; | |
8438 | } | |
8439 | ||
8440 | ||
43cd72b9 | 8441 | static bfd_boolean |
7fa3d080 | 8442 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 8443 | { |
43cd72b9 BW |
8444 | static xtensa_insnbuf insnbuf = NULL; |
8445 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
8446 | int offset = 0; |
8447 | ||
8448 | if (!fragP->tc_frag_data.is_insn) | |
8449 | return FALSE; | |
8450 | ||
43cd72b9 BW |
8451 | if (!insnbuf) |
8452 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8453 | ||
e0001a05 NC |
8454 | /* Decode the fixed instructions. */ |
8455 | while (offset < fragP->fr_fix) | |
8456 | { | |
43cd72b9 BW |
8457 | xtensa_format fmt; |
8458 | int slot; | |
8459 | ||
d77b99c9 BW |
8460 | xtensa_insnbuf_from_chars |
8461 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
8462 | fmt = xtensa_format_decode (isa, insnbuf); |
8463 | if (fmt == XTENSA_UNDEFINED) | |
8464 | return FALSE; | |
8465 | ||
8466 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 8467 | { |
43cd72b9 BW |
8468 | xtensa_opcode opcode = |
8469 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
8470 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
8471 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
8472 | return TRUE; | |
e0001a05 | 8473 | } |
43cd72b9 | 8474 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8475 | } |
8476 | return FALSE; | |
8477 | } | |
8478 | ||
8479 | ||
8480 | /* Checks to be made after initial assembly but before relaxation. */ | |
8481 | ||
7fa3d080 BW |
8482 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
8483 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
8484 | ||
e0001a05 | 8485 | static void |
7fa3d080 | 8486 | xtensa_sanity_check (void) |
e0001a05 | 8487 | { |
3b4dbbbf | 8488 | const char *file_name; |
d77b99c9 | 8489 | unsigned line; |
e0001a05 | 8490 | frchainS *frchP; |
c9049d30 | 8491 | asection *s; |
e0001a05 | 8492 | |
3b4dbbbf | 8493 | file_name = as_where (&line); |
c9049d30 AM |
8494 | for (s = stdoutput->sections; s; s = s->next) |
8495 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8496 | { | |
8497 | fragS *fragP; | |
e0001a05 | 8498 | |
c9049d30 AM |
8499 | /* Walk over all of the fragments in a subsection. */ |
8500 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8501 | { | |
c9049d30 | 8502 | if (fragP->fr_type == rs_machine_dependent |
3739860c | 8503 | && fragP->fr_subtype == RELAX_SLOTS |
a7284bf1 | 8504 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) |
c9049d30 AM |
8505 | { |
8506 | static xtensa_insnbuf insnbuf = NULL; | |
8507 | TInsn t_insn; | |
8508 | ||
8509 | if (fragP->fr_opcode != NULL) | |
8510 | { | |
8511 | if (!insnbuf) | |
8512 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
8513 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
8514 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
8515 | ||
8516 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
8517 | t_insn.opcode) == 1) | |
8518 | { | |
8519 | if (is_empty_loop (&t_insn, fragP)) | |
8520 | { | |
8521 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8522 | as_bad (_("invalid empty loop")); | |
8523 | } | |
8524 | if (!is_local_forward_loop (&t_insn, fragP)) | |
8525 | { | |
8526 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8527 | as_bad (_("loop target does not follow " | |
8528 | "loop instruction in section")); | |
8529 | } | |
8530 | } | |
8531 | } | |
8532 | } | |
8533 | } | |
8534 | } | |
e0001a05 NC |
8535 | new_logical_line (file_name, line); |
8536 | } | |
8537 | ||
8538 | ||
8539 | #define LOOP_IMMED_OPN 1 | |
8540 | ||
43cd72b9 | 8541 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 8542 | |
7fa3d080 BW |
8543 | static bfd_boolean |
8544 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 | 8545 | { |
91d6fa6a | 8546 | const expressionS *exp; |
e0001a05 NC |
8547 | symbolS *symbolP; |
8548 | fragS *next_fragP; | |
8549 | ||
8550 | if (insn->insn_type != ITYPE_INSN) | |
8551 | return FALSE; | |
8552 | ||
43cd72b9 | 8553 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8554 | return FALSE; |
8555 | ||
8556 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8557 | return FALSE; | |
8558 | ||
91d6fa6a | 8559 | exp = &insn->tok[LOOP_IMMED_OPN]; |
e0001a05 | 8560 | |
91d6fa6a | 8561 | if (exp->X_op != O_symbol) |
e0001a05 NC |
8562 | return FALSE; |
8563 | ||
91d6fa6a | 8564 | symbolP = exp->X_add_symbol; |
e0001a05 NC |
8565 | if (!symbolP) |
8566 | return FALSE; | |
8567 | ||
8568 | if (symbol_get_frag (symbolP) == NULL) | |
8569 | return FALSE; | |
8570 | ||
8571 | if (S_GET_VALUE (symbolP) != 0) | |
8572 | return FALSE; | |
8573 | ||
8574 | /* Walk through the zero-size fragments from this one. If we find | |
8575 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 8576 | |
e0001a05 NC |
8577 | for (next_fragP = fragP->fr_next; |
8578 | next_fragP != NULL; | |
8579 | next_fragP = next_fragP->fr_next) | |
8580 | { | |
8581 | if (next_fragP == symbol_get_frag (symbolP)) | |
8582 | return TRUE; | |
8583 | if (next_fragP->fr_fix != 0) | |
8584 | return FALSE; | |
8585 | } | |
8586 | return FALSE; | |
8587 | } | |
8588 | ||
8589 | ||
7fa3d080 BW |
8590 | static bfd_boolean |
8591 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 | 8592 | { |
91d6fa6a | 8593 | const expressionS *exp; |
e0001a05 NC |
8594 | symbolS *symbolP; |
8595 | fragS *next_fragP; | |
8596 | ||
8597 | if (insn->insn_type != ITYPE_INSN) | |
8598 | return FALSE; | |
8599 | ||
64b607e6 | 8600 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8601 | return FALSE; |
8602 | ||
8603 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8604 | return FALSE; | |
8605 | ||
91d6fa6a | 8606 | exp = &insn->tok[LOOP_IMMED_OPN]; |
e0001a05 | 8607 | |
91d6fa6a | 8608 | if (exp->X_op != O_symbol) |
e0001a05 NC |
8609 | return FALSE; |
8610 | ||
91d6fa6a | 8611 | symbolP = exp->X_add_symbol; |
e0001a05 NC |
8612 | if (!symbolP) |
8613 | return FALSE; | |
8614 | ||
8615 | if (symbol_get_frag (symbolP) == NULL) | |
8616 | return FALSE; | |
8617 | ||
8618 | /* Walk through fragments until we find the target. | |
8619 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 8620 | |
e0001a05 NC |
8621 | for (next_fragP = fragP->fr_next; |
8622 | next_fragP != NULL; | |
8623 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
8624 | { |
8625 | if (next_fragP == symbol_get_frag (symbolP)) | |
8626 | return TRUE; | |
8627 | } | |
e0001a05 NC |
8628 | |
8629 | return FALSE; | |
8630 | } | |
8631 | ||
2caa7ca0 BW |
8632 | |
8633 | #define XTINFO_NAME "Xtensa_Info" | |
8634 | #define XTINFO_NAMESZ 12 | |
8635 | #define XTINFO_TYPE 1 | |
8636 | ||
8637 | static void | |
8638 | xtensa_add_config_info (void) | |
8639 | { | |
8640 | asection *info_sec; | |
8641 | char *data, *p; | |
8642 | int sz; | |
8643 | ||
8644 | info_sec = subseg_new (".xtensa.info", 0); | |
8645 | bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY); | |
8646 | ||
325801bd | 8647 | data = XNEWVEC (char, 100); |
2caa7ca0 BW |
8648 | sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", |
8649 | XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI); | |
8650 | sz = strlen (data) + 1; | |
8651 | ||
8652 | /* Add enough null terminators to pad to a word boundary. */ | |
8653 | do | |
8654 | data[sz++] = 0; | |
8655 | while ((sz & 3) != 0); | |
8656 | ||
8657 | /* Follow the standard note section layout: | |
8658 | First write the length of the name string. */ | |
8659 | p = frag_more (4); | |
8660 | md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); | |
8661 | ||
8662 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
8663 | p = frag_more (4); | |
8664 | md_number_to_chars (p, (valueT) sz, 4); | |
8665 | ||
8666 | /* Write the note type. */ | |
8667 | p = frag_more (4); | |
8668 | md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); | |
8669 | ||
8670 | /* Write the name field. */ | |
8671 | p = frag_more (XTINFO_NAMESZ); | |
8672 | memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); | |
8673 | ||
8674 | /* Finally, write the descriptor. */ | |
8675 | p = frag_more (sz); | |
8676 | memcpy (p, data, sz); | |
8677 | ||
8678 | free (data); | |
8679 | } | |
8680 | ||
e0001a05 NC |
8681 | \f |
8682 | /* Alignment Functions. */ | |
8683 | ||
d77b99c9 BW |
8684 | static int |
8685 | get_text_align_power (unsigned target_size) | |
e0001a05 | 8686 | { |
03aaa593 BW |
8687 | if (target_size <= 4) |
8688 | return 2; | |
19ef5f3d SA |
8689 | |
8690 | if (target_size <= 8) | |
8691 | return 3; | |
8692 | ||
8693 | if (target_size <= 16) | |
8694 | return 4; | |
8695 | ||
8696 | if (target_size <= 32) | |
8697 | return 5; | |
8698 | ||
8699 | if (target_size <= 64) | |
8700 | return 6; | |
8701 | ||
8702 | if (target_size <= 128) | |
8703 | return 7; | |
8704 | ||
8705 | if (target_size <= 256) | |
8706 | return 8; | |
8707 | ||
8708 | if (target_size <= 512) | |
8709 | return 9; | |
8710 | ||
8711 | if (target_size <= 1024) | |
8712 | return 10; | |
8713 | ||
8714 | gas_assert (0); | |
8715 | return 0; | |
e0001a05 NC |
8716 | } |
8717 | ||
8718 | ||
d77b99c9 | 8719 | static int |
7fa3d080 BW |
8720 | get_text_align_max_fill_size (int align_pow, |
8721 | bfd_boolean use_nops, | |
8722 | bfd_boolean use_no_density) | |
e0001a05 NC |
8723 | { |
8724 | if (!use_nops) | |
8725 | return (1 << align_pow); | |
8726 | if (use_no_density) | |
8727 | return 3 * (1 << align_pow); | |
8728 | ||
8729 | return 1 + (1 << align_pow); | |
8730 | } | |
8731 | ||
8732 | ||
d77b99c9 BW |
8733 | /* Calculate the minimum bytes of fill needed at "address" to align a |
8734 | target instruction of size "target_size" so that it does not cross a | |
8735 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
8736 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
8737 | be filled by NOP instructions. */ | |
e0001a05 | 8738 | |
d77b99c9 | 8739 | static int |
7fa3d080 BW |
8740 | get_text_align_fill_size (addressT address, |
8741 | int align_pow, | |
8742 | int target_size, | |
8743 | bfd_boolean use_nops, | |
8744 | bfd_boolean use_no_density) | |
e0001a05 | 8745 | { |
d77b99c9 BW |
8746 | addressT alignment, fill, fill_limit, fill_step; |
8747 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 8748 | |
d77b99c9 | 8749 | alignment = (1 << align_pow); |
9c2799c2 | 8750 | gas_assert (target_size > 0 && alignment >= (addressT) target_size); |
c138bc38 | 8751 | |
e0001a05 NC |
8752 | if (!use_nops) |
8753 | { | |
d77b99c9 BW |
8754 | fill_limit = alignment; |
8755 | fill_step = 1; | |
e0001a05 | 8756 | } |
d77b99c9 | 8757 | else if (!use_no_density) |
e0001a05 | 8758 | { |
d77b99c9 BW |
8759 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
8760 | fill_limit = alignment * 2; | |
8761 | fill_step = 1; | |
8762 | skip_one = TRUE; | |
e0001a05 NC |
8763 | } |
8764 | else | |
8765 | { | |
d77b99c9 BW |
8766 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
8767 | fill_limit = alignment * 3; | |
8768 | fill_step = 3; | |
8769 | } | |
e0001a05 | 8770 | |
d77b99c9 BW |
8771 | /* Try all fill sizes until finding one that works. */ |
8772 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
8773 | { | |
8774 | if (skip_one && fill == 1) | |
8775 | continue; | |
8776 | if ((address + fill) >> align_pow | |
8777 | == (address + fill + target_size - 1) >> align_pow) | |
8778 | return fill; | |
e0001a05 | 8779 | } |
9c2799c2 | 8780 | gas_assert (0); |
e0001a05 NC |
8781 | return 0; |
8782 | } | |
8783 | ||
8784 | ||
664df4e4 BW |
8785 | static int |
8786 | branch_align_power (segT sec) | |
8787 | { | |
19ef5f3d SA |
8788 | /* If the Xtensa processor has a fetch width of X, and |
8789 | the section is aligned to at least that boundary, then a branch | |
8790 | target need only fit within that aligned block of memory to avoid | |
8791 | a stall. Otherwise, try to fit branch targets within 4-byte | |
8792 | aligned blocks (which may be insufficient, e.g., if the section | |
8793 | has no alignment, but it's good enough). */ | |
8794 | int fetch_align = get_text_align_power(xtensa_fetch_width); | |
8795 | int sec_align = get_recorded_alignment (sec); | |
8796 | ||
8797 | if (sec_align >= fetch_align) | |
8798 | return fetch_align; | |
664df4e4 BW |
8799 | |
8800 | return 2; | |
8801 | } | |
8802 | ||
8803 | ||
e0001a05 NC |
8804 | /* This will assert if it is not possible. */ |
8805 | ||
d77b99c9 BW |
8806 | static int |
8807 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 8808 | { |
d77b99c9 BW |
8809 | int count = 0; |
8810 | ||
e0001a05 NC |
8811 | if (use_no_density) |
8812 | { | |
9c2799c2 | 8813 | gas_assert (fill_size % 3 == 0); |
e0001a05 NC |
8814 | return (fill_size / 3); |
8815 | } | |
8816 | ||
9c2799c2 | 8817 | gas_assert (fill_size != 1); /* Bad argument. */ |
e0001a05 NC |
8818 | |
8819 | while (fill_size > 1) | |
8820 | { | |
d77b99c9 | 8821 | int insn_size = 3; |
e0001a05 NC |
8822 | if (fill_size == 2 || fill_size == 4) |
8823 | insn_size = 2; | |
8824 | fill_size -= insn_size; | |
8825 | count++; | |
8826 | } | |
9c2799c2 | 8827 | gas_assert (fill_size != 1); /* Bad algorithm. */ |
e0001a05 NC |
8828 | return count; |
8829 | } | |
8830 | ||
8831 | ||
d77b99c9 BW |
8832 | static int |
8833 | get_text_align_nth_nop_size (offsetT fill_size, | |
8834 | int n, | |
7fa3d080 | 8835 | bfd_boolean use_no_density) |
e0001a05 | 8836 | { |
d77b99c9 | 8837 | int count = 0; |
e0001a05 NC |
8838 | |
8839 | if (use_no_density) | |
8840 | return 3; | |
8841 | ||
9c2799c2 | 8842 | gas_assert (fill_size != 1); /* Bad argument. */ |
d77b99c9 | 8843 | |
e0001a05 NC |
8844 | while (fill_size > 1) |
8845 | { | |
d77b99c9 | 8846 | int insn_size = 3; |
e0001a05 NC |
8847 | if (fill_size == 2 || fill_size == 4) |
8848 | insn_size = 2; | |
8849 | fill_size -= insn_size; | |
8850 | count++; | |
8851 | if (n + 1 == count) | |
8852 | return insn_size; | |
8853 | } | |
9c2799c2 | 8854 | gas_assert (0); |
e0001a05 NC |
8855 | return 0; |
8856 | } | |
8857 | ||
8858 | ||
8859 | /* For the given fragment, find the appropriate address | |
8860 | for it to begin at if we are using NOPs to align it. */ | |
8861 | ||
8862 | static addressT | |
7fa3d080 | 8863 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 8864 | { |
43cd72b9 BW |
8865 | /* The rule is: get next fragment's FIRST instruction. Find |
8866 | the smallest number of bytes that need to be added to | |
8867 | ensure that the next fragment's FIRST instruction will fit | |
8868 | in a single word. | |
c138bc38 | 8869 | |
43cd72b9 BW |
8870 | E.G., 2 bytes : 0, 1, 2 mod 4 |
8871 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 8872 | |
43cd72b9 BW |
8873 | If the FIRST instruction MIGHT be relaxed, |
8874 | assume that it will become a 3-byte instruction. | |
c138bc38 | 8875 | |
43cd72b9 BW |
8876 | Note again here that LOOP instructions are not bundleable, |
8877 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 8878 | |
d77b99c9 | 8879 | int fill_size = 0; |
43cd72b9 BW |
8880 | int first_insn_size; |
8881 | int loop_insn_size; | |
8882 | addressT pre_opcode_bytes; | |
d77b99c9 | 8883 | int align_power; |
43cd72b9 BW |
8884 | fragS *first_insn; |
8885 | xtensa_opcode opcode; | |
8886 | bfd_boolean is_loop; | |
e0001a05 | 8887 | |
9c2799c2 NC |
8888 | gas_assert (fragP->fr_type == rs_machine_dependent); |
8889 | gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 8890 | |
43cd72b9 BW |
8891 | /* Find the loop frag. */ |
8892 | first_insn = next_non_empty_frag (fragP); | |
8893 | /* Now find the first insn frag. */ | |
8894 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 8895 | |
43cd72b9 | 8896 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
9c2799c2 | 8897 | gas_assert (is_loop); |
43cd72b9 | 8898 | loop_insn_size = xg_get_single_size (opcode); |
e0001a05 | 8899 | |
43cd72b9 BW |
8900 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
8901 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 8902 | |
43cd72b9 BW |
8903 | /* For loops, the alignment depends on the size of the |
8904 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 8905 | |
43cd72b9 | 8906 | if (first_insn == NULL) |
03aaa593 BW |
8907 | first_insn_size = xtensa_fetch_width; |
8908 | else | |
8909 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 8910 | |
43cd72b9 | 8911 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
8912 | align_power = get_text_align_power (first_insn_size); |
8913 | record_alignment (now_seg, align_power); | |
c138bc38 | 8914 | |
43cd72b9 | 8915 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
8916 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
8917 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
8918 | |
8919 | return address + fill_size; | |
8920 | } | |
8921 | ||
8922 | ||
43cd72b9 BW |
8923 | /* 3 mechanisms for relaxing an alignment: |
8924 | ||
8925 | Align to a power of 2. | |
8926 | Align so the next fragment's instruction does not cross a word boundary. | |
8927 | Align the current instruction so that if the next instruction | |
8928 | were 3 bytes, it would not cross a word boundary. | |
8929 | ||
e0001a05 NC |
8930 | We can align with: |
8931 | ||
43cd72b9 BW |
8932 | zeros - This is easy; always insert zeros. |
8933 | nops - 3-byte and 2-byte instructions | |
8934 | 2 - 2-byte nop | |
8935 | 3 - 3-byte nop | |
8936 | 4 - 2 2-byte nops | |
8937 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
8938 | widening - widen previous instructions. */ |
8939 | ||
d77b99c9 BW |
8940 | static offsetT |
8941 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 8942 | { |
43cd72b9 BW |
8943 | addressT target_address, loop_insn_offset; |
8944 | int target_size; | |
8945 | xtensa_opcode loop_opcode; | |
8946 | bfd_boolean is_loop; | |
d77b99c9 BW |
8947 | int align_power; |
8948 | offsetT opt_diff; | |
5f9084e9 | 8949 | offsetT branch_align; |
def13efb | 8950 | fragS *loop_frag; |
e0001a05 | 8951 | |
9c2799c2 | 8952 | gas_assert (fragP->fr_type == rs_machine_dependent); |
43cd72b9 | 8953 | switch (fragP->fr_subtype) |
e0001a05 | 8954 | { |
43cd72b9 BW |
8955 | case RELAX_DESIRE_ALIGN: |
8956 | target_size = next_frag_format_size (fragP); | |
8957 | if (target_size == XTENSA_UNDEFINED) | |
8958 | target_size = 3; | |
664df4e4 BW |
8959 | align_power = branch_align_power (now_seg); |
8960 | branch_align = 1 << align_power; | |
0e5cd789 BW |
8961 | /* Don't count on the section alignment being as large as the target. */ |
8962 | if (target_size > branch_align) | |
8963 | target_size = branch_align; | |
d77b99c9 | 8964 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
8965 | target_size, FALSE, FALSE); |
8966 | ||
664df4e4 BW |
8967 | *max_diff = (opt_diff + branch_align |
8968 | - (target_size + ((address + opt_diff) % branch_align))); | |
9c2799c2 | 8969 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 8970 | return opt_diff; |
e0001a05 | 8971 | |
43cd72b9 | 8972 | case RELAX_ALIGN_NEXT_OPCODE: |
def13efb BW |
8973 | /* The next non-empty frag after this one holds the LOOP instruction |
8974 | that needs to be aligned. The required alignment depends on the | |
8975 | size of the next non-empty frag after the loop frag, i.e., the | |
8976 | first instruction in the loop. */ | |
8977 | loop_frag = next_non_empty_frag (fragP); | |
8978 | target_size = get_loop_align_size (next_frag_format_size (loop_frag)); | |
43cd72b9 BW |
8979 | loop_insn_offset = 0; |
8980 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
9c2799c2 | 8981 | gas_assert (is_loop); |
43cd72b9 BW |
8982 | |
8983 | /* If the loop has been expanded then the LOOP instruction | |
8984 | could be at an offset from this fragment. */ | |
def13efb | 8985 | if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED) |
43cd72b9 BW |
8986 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); |
8987 | ||
43cd72b9 BW |
8988 | /* In an ideal world, which is what we are shooting for here, |
8989 | we wouldn't need to use any NOPs immediately prior to the | |
8990 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
8991 | will call get_noop_aligned_address. */ | |
8992 | target_address = | |
8993 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
def13efb | 8994 | align_power = get_text_align_power (target_size); |
d77b99c9 | 8995 | opt_diff = get_text_align_fill_size (target_address, align_power, |
43cd72b9 BW |
8996 | target_size, FALSE, FALSE); |
8997 | ||
8998 | *max_diff = xtensa_fetch_width | |
8999 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
9000 | - target_size + opt_diff; | |
9c2799c2 | 9001 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 9002 | return opt_diff; |
e0001a05 | 9003 | |
43cd72b9 BW |
9004 | default: |
9005 | break; | |
e0001a05 | 9006 | } |
9c2799c2 | 9007 | gas_assert (0); |
43cd72b9 | 9008 | return 0; |
e0001a05 NC |
9009 | } |
9010 | ||
9011 | \f | |
9012 | /* md_relax_frag Hook and Helper Functions. */ | |
9013 | ||
7fa3d080 BW |
9014 | static long relax_frag_loop_align (fragS *, long); |
9015 | static long relax_frag_for_align (fragS *, long); | |
9016 | static long relax_frag_immed | |
9017 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
9018 | ||
b76f99d7 MF |
9019 | typedef struct cached_fixup cached_fixupS; |
9020 | struct cached_fixup | |
9021 | { | |
9022 | int addr; | |
9023 | int target; | |
9024 | int delta; | |
9025 | fixS *fixP; | |
9026 | }; | |
9027 | ||
9028 | typedef struct fixup_cache fixup_cacheS; | |
9029 | struct fixup_cache | |
9030 | { | |
9031 | cached_fixupS *fixups; | |
9032 | unsigned n_fixups; | |
9033 | unsigned n_max; | |
9034 | ||
9035 | segT seg; | |
9036 | fragS *first_frag; | |
9037 | }; | |
9038 | ||
9039 | static int fixup_order (const void *a, const void *b) | |
9040 | { | |
9041 | const cached_fixupS *pa = a; | |
9042 | const cached_fixupS *pb = b; | |
9043 | ||
9044 | if (pa->addr == pb->addr) | |
9045 | { | |
9046 | if (pa->target == pb->target) | |
9047 | { | |
9048 | if (pa->fixP->fx_r_type == pb->fixP->fx_r_type) | |
9049 | return 0; | |
9050 | return pa->fixP->fx_r_type < pb->fixP->fx_r_type ? -1 : 1; | |
9051 | } | |
9052 | return pa->target - pb->target; | |
9053 | } | |
9054 | return pa->addr - pb->addr; | |
9055 | } | |
9056 | ||
9057 | static bfd_boolean xtensa_make_cached_fixup (cached_fixupS *o, fixS *fixP) | |
9058 | { | |
9059 | xtensa_isa isa = xtensa_default_isa; | |
9060 | int addr = fixP->fx_frag->fr_address; | |
9061 | int target; | |
9062 | int delta; | |
9063 | symbolS *s = fixP->fx_addsy; | |
9064 | int slot; | |
9065 | xtensa_format fmt; | |
9066 | xtensa_opcode opcode; | |
9067 | ||
9068 | if (fixP->fx_r_type < BFD_RELOC_XTENSA_SLOT0_OP || | |
9069 | fixP->fx_r_type > BFD_RELOC_XTENSA_SLOT14_OP) | |
9070 | return FALSE; | |
9071 | target = S_GET_VALUE (s); | |
9072 | delta = target - addr; | |
9073 | ||
9074 | if (abs(delta) < J_RANGE / 2) | |
9075 | return FALSE; | |
9076 | ||
9077 | xtensa_insnbuf_from_chars (isa, trampoline_buf, | |
9078 | (unsigned char *) fixP->fx_frag->fr_literal + | |
9079 | fixP->fx_where, 0); | |
9080 | fmt = xtensa_format_decode (isa, trampoline_buf); | |
9081 | gas_assert (fmt != XTENSA_UNDEFINED); | |
9082 | slot = fixP->tc_fix_data.slot; | |
9083 | xtensa_format_get_slot (isa, fmt, slot, trampoline_buf, trampoline_slotbuf); | |
9084 | opcode = xtensa_opcode_decode (isa, fmt, slot, trampoline_slotbuf); | |
9085 | if (opcode != xtensa_j_opcode) | |
9086 | return FALSE; | |
9087 | ||
9088 | o->addr = addr; | |
9089 | o->target = target; | |
9090 | o->delta = delta; | |
9091 | o->fixP = fixP; | |
9092 | ||
9093 | return TRUE; | |
9094 | } | |
9095 | ||
9096 | static void xtensa_realloc_fixup_cache (fixup_cacheS *cache, unsigned add) | |
9097 | { | |
9098 | if (cache->n_fixups + add > cache->n_max) | |
9099 | { | |
9100 | cache->n_max = (cache->n_fixups + add) * 2; | |
325801bd | 9101 | cache->fixups = XRESIZEVEC (cached_fixupS, cache->fixups, cache->n_max); |
b76f99d7 MF |
9102 | } |
9103 | } | |
9104 | ||
9105 | static void xtensa_cache_relaxable_fixups (fixup_cacheS *cache, | |
9106 | segment_info_type *seginfo) | |
9107 | { | |
9108 | fixS *fixP; | |
9109 | ||
9110 | cache->n_fixups = 0; | |
9111 | ||
9112 | for (fixP = seginfo->fix_root; fixP ; fixP = fixP->fx_next) | |
9113 | { | |
9114 | xtensa_realloc_fixup_cache (cache, 1); | |
9115 | ||
9116 | if (xtensa_make_cached_fixup (cache->fixups + cache->n_fixups, fixP)) | |
9117 | ++cache->n_fixups; | |
9118 | } | |
9119 | qsort (cache->fixups, cache->n_fixups, sizeof (*cache->fixups), fixup_order); | |
9120 | } | |
9121 | ||
9122 | static unsigned xtensa_find_first_cached_fixup (const fixup_cacheS *cache, | |
9123 | int addr) | |
9124 | { | |
9125 | unsigned a = 0; | |
9126 | unsigned b = cache->n_fixups; | |
9127 | ||
9128 | while (b - a > 1) | |
9129 | { | |
9130 | unsigned c = (a + b) / 2; | |
9131 | ||
9132 | if (cache->fixups[c].addr < addr) | |
9133 | a = c; | |
9134 | else | |
9135 | b = c; | |
9136 | } | |
9137 | return a; | |
9138 | } | |
9139 | ||
9140 | static void xtensa_delete_cached_fixup (fixup_cacheS *cache, unsigned i) | |
9141 | { | |
9142 | memmove (cache->fixups + i, cache->fixups + i + 1, | |
9143 | (cache->n_fixups - i - 1) * sizeof (*cache->fixups)); | |
9144 | --cache->n_fixups; | |
9145 | } | |
9146 | ||
9147 | static bfd_boolean xtensa_add_cached_fixup (fixup_cacheS *cache, fixS *fixP) | |
9148 | { | |
9149 | cached_fixupS o; | |
9150 | unsigned i; | |
9151 | ||
9152 | if (!xtensa_make_cached_fixup (&o, fixP)) | |
9153 | return FALSE; | |
9154 | xtensa_realloc_fixup_cache (cache, 1); | |
9155 | i = xtensa_find_first_cached_fixup (cache, o.addr); | |
9156 | if (i < cache->n_fixups) | |
9157 | { | |
9158 | ++i; | |
9159 | memmove (cache->fixups + i + 1, cache->fixups + i, | |
9160 | (cache->n_fixups - i) * sizeof (*cache->fixups)); | |
9161 | } | |
9162 | cache->fixups[i] = o; | |
9163 | ++cache->n_fixups; | |
9164 | return TRUE; | |
9165 | } | |
7fa3d080 | 9166 | |
120bc8b8 MF |
9167 | static void xg_relax_trampoline (fragS *fragP, long stretch, long *new_stretch) |
9168 | { | |
9169 | xtensa_isa isa = xtensa_default_isa; | |
9170 | static fixup_cacheS fixup_cache; | |
9171 | segment_info_type *seginfo = seg_info (now_seg); | |
9172 | int trampaddr = fragP->fr_address + fragP->fr_fix; | |
9173 | int searchaddr = trampaddr < J_RANGE ? 0 : trampaddr - J_RANGE; | |
9174 | int slot; | |
9175 | xtensa_format fmt; | |
9176 | unsigned i; | |
9177 | ||
9178 | if (now_seg != fixup_cache.seg || | |
9179 | fragP == fixup_cache.first_frag || | |
9180 | fixup_cache.first_frag == NULL) | |
9181 | { | |
9182 | xtensa_cache_relaxable_fixups (&fixup_cache, seginfo); | |
9183 | fixup_cache.seg = now_seg; | |
9184 | fixup_cache.first_frag = fragP; | |
9185 | } | |
9186 | ||
9187 | /* Scan for jumps that will not reach. */ | |
9188 | for (i = xtensa_find_first_cached_fixup (&fixup_cache, searchaddr); | |
9189 | i < fixup_cache.n_fixups; ++i) | |
9190 | ||
9191 | { | |
9192 | fixS *fixP = fixup_cache.fixups[i].fixP; | |
9193 | int target = fixup_cache.fixups[i].target; | |
9194 | int addr = fixup_cache.fixups[i].addr; | |
9195 | int delta = fixup_cache.fixups[i].delta + stretch; | |
9196 | ||
9197 | trampaddr = fragP->fr_address + fragP->fr_fix; | |
9198 | ||
9199 | if (addr + J_RANGE < trampaddr) | |
9200 | continue; | |
9201 | if (addr > trampaddr + J_RANGE) | |
9202 | break; | |
9203 | if (abs (delta) < J_RANGE) | |
9204 | continue; | |
9205 | ||
9206 | slot = fixP->tc_fix_data.slot; | |
9207 | ||
9208 | if (delta > J_RANGE || delta < -1 * J_RANGE) | |
9209 | { /* Found an out-of-range jump; scan the list of trampolines for the best match. */ | |
9210 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); | |
9211 | struct trampoline_frag *tf = ts->trampoline_list.next; | |
9212 | struct trampoline_frag *prev = &ts->trampoline_list; | |
9213 | int lower = (target < addr) ? target : addr; | |
9214 | int upper = (target > addr) ? target : addr; | |
9215 | int midpoint = lower + (upper - lower) / 2; | |
9216 | ||
9217 | if ((upper - lower) > 2 * J_RANGE) | |
9218 | { | |
9219 | /* One trampoline won't suffice; we need multiple jumps. | |
9220 | Jump to the trampoline that's farthest, but still in | |
9221 | range relative to the original "j" instruction. */ | |
9222 | for ( ; tf; prev = tf, tf = tf->next ) | |
9223 | { | |
9224 | int this_addr = tf->fragP->fr_address + tf->fragP->fr_fix; | |
9225 | int next_addr = (tf->next) ? tf->next->fragP->fr_address + tf->next->fragP->fr_fix : 0 ; | |
9226 | ||
9227 | if (addr == lower) | |
9228 | { | |
9229 | /* Forward jump. */ | |
9230 | if (this_addr - addr < J_RANGE) | |
9231 | break; | |
9232 | } | |
9233 | else | |
9234 | { | |
9235 | /* Backward jump. */ | |
9236 | if (next_addr == 0 || addr - next_addr > J_RANGE) | |
9237 | break; | |
9238 | } | |
9239 | } | |
9240 | } | |
9241 | else | |
9242 | { | |
9243 | struct trampoline_frag *best_tf = NULL; | |
9244 | struct trampoline_frag *best_tf_prev = NULL; | |
9245 | int best_delta = 0; | |
9246 | ||
9247 | for ( ; tf; prev = tf, tf = tf->next ) | |
9248 | { | |
9249 | int this_addr = tf->fragP->fr_address + tf->fragP->fr_fix; | |
9250 | int this_delta = abs (this_addr - midpoint); | |
9251 | ||
9252 | if (!best_tf || this_delta < best_delta) | |
9253 | { | |
9254 | best_tf = tf; | |
9255 | best_delta = this_delta; | |
9256 | best_tf_prev = prev; | |
9257 | } | |
9258 | } | |
9259 | tf = best_tf; | |
9260 | prev = best_tf_prev; | |
9261 | } | |
9262 | if (tf->fragP == fragP) | |
9263 | { | |
9264 | if (abs (addr - trampaddr) < J_RANGE) | |
9265 | { /* The trampoline is in range of original; fix it! */ | |
9266 | fixS *newfixP; | |
9267 | int offset; | |
9268 | TInsn insn; | |
9269 | symbolS *lsym; | |
9270 | fragS *fP; /* The out-of-range jump. */ | |
9271 | ||
9272 | new_stretch += init_trampoline_frag (tf); | |
9273 | offset = fragP->fr_fix; /* Where to assemble the j insn. */ | |
9274 | lsym = fragP->fr_symbol; | |
9275 | fP = fixP->fx_frag; | |
9276 | /* Assemble a jump to the target label here. */ | |
9277 | tinsn_init (&insn); | |
9278 | insn.insn_type = ITYPE_INSN; | |
9279 | insn.opcode = xtensa_j_opcode; | |
9280 | insn.ntok = 1; | |
9281 | set_expr_symbol_offset (&insn.tok[0], lsym, offset); | |
9282 | fmt = xg_get_single_format (xtensa_j_opcode); | |
9283 | tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf); | |
9284 | xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf); | |
9285 | xtensa_insnbuf_to_chars (isa, trampoline_buf, (unsigned char *)fragP->fr_literal + offset, 3); | |
9286 | fragP->fr_fix += 3; | |
9287 | fragP->fr_var -= 3; | |
9288 | /* Add a fix-up for the original j insn. */ | |
9289 | newfixP = fix_new (fP, fixP->fx_where, fixP->fx_size, lsym, fragP->fr_fix - 3, TRUE, fixP->fx_r_type); | |
9290 | newfixP->fx_no_overflow = 1; | |
9291 | newfixP->tc_fix_data.X_add_symbol = lsym; | |
9292 | newfixP->tc_fix_data.X_add_number = offset; | |
9293 | newfixP->tc_fix_data.slot = slot; | |
9294 | ||
9295 | xtensa_delete_cached_fixup (&fixup_cache, i); | |
9296 | xtensa_add_cached_fixup (&fixup_cache, newfixP); | |
9297 | ||
9298 | /* Move the fix-up from the original j insn to this one. */ | |
9299 | fixP->fx_frag = fragP; | |
9300 | fixP->fx_where = fragP->fr_fix - 3; | |
9301 | fixP->fx_size = 3; | |
9302 | fixP->tc_fix_data.slot = 0; | |
9303 | fixP->fx_r_type = BFD_RELOC_XTENSA_SLOT0_OP; | |
9304 | ||
9305 | xtensa_add_cached_fixup (&fixup_cache, fixP); | |
9306 | ||
9307 | /* re-do current fixup */ | |
9308 | --i; | |
9309 | ||
9310 | /* Adjust the jump around this trampoline (if present). */ | |
9311 | if (tf->fixP != NULL) | |
9312 | { | |
9313 | tf->fixP->fx_offset += 3; | |
9314 | } | |
9315 | new_stretch += 3; | |
9316 | fragP->tc_frag_data.relax_seen = FALSE; /* Need another pass. */ | |
9317 | /* Do we have room for more? */ | |
9318 | if (fragP->fr_var < 3) | |
9319 | { /* No, convert to fill. */ | |
9320 | frag_wane (fragP); | |
9321 | fragP->fr_subtype = 0; | |
9322 | /* Remove from the trampoline_list. */ | |
9323 | prev->next = tf->next; | |
9324 | if (fragP == fixup_cache.first_frag) | |
9325 | fixup_cache.first_frag = NULL; | |
9326 | break; | |
9327 | } | |
9328 | } | |
9329 | } | |
9330 | } | |
9331 | } | |
9332 | } | |
9333 | ||
e0001a05 NC |
9334 | /* Return the number of bytes added to this fragment, given that the |
9335 | input has been stretched already by "stretch". */ | |
9336 | ||
9337 | long | |
7fa3d080 | 9338 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 9339 | { |
43cd72b9 | 9340 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
9341 | int unreported = fragP->tc_frag_data.unreported_expansion; |
9342 | long new_stretch = 0; | |
3b4dbbbf | 9343 | const char *file_name; |
d77b99c9 BW |
9344 | unsigned line; |
9345 | int lit_size; | |
43cd72b9 BW |
9346 | static xtensa_insnbuf vbuf = NULL; |
9347 | int slot, num_slots; | |
9348 | xtensa_format fmt; | |
e0001a05 | 9349 | |
3b4dbbbf | 9350 | file_name = as_where (&line); |
e0001a05 NC |
9351 | new_logical_line (fragP->fr_file, fragP->fr_line); |
9352 | ||
9353 | fragP->tc_frag_data.unreported_expansion = 0; | |
9354 | ||
9355 | switch (fragP->fr_subtype) | |
9356 | { | |
9357 | case RELAX_ALIGN_NEXT_OPCODE: | |
9358 | /* Always convert. */ | |
43cd72b9 BW |
9359 | if (fragP->tc_frag_data.relax_seen) |
9360 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
9361 | break; |
9362 | ||
9363 | case RELAX_LOOP_END: | |
9364 | /* Do nothing. */ | |
9365 | break; | |
9366 | ||
9367 | case RELAX_LOOP_END_ADD_NOP: | |
9368 | /* Add a NOP and switch to .fill 0. */ | |
9369 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 9370 | frag_wane (fragP); |
e0001a05 NC |
9371 | break; |
9372 | ||
9373 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 9374 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
9375 | it or not. */ |
9376 | break; | |
9377 | ||
9378 | case RELAX_LITERAL: | |
9379 | case RELAX_LITERAL_FINAL: | |
9380 | return 0; | |
9381 | ||
9382 | case RELAX_LITERAL_NR: | |
9383 | lit_size = 4; | |
9384 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 9385 | gas_assert (unreported == lit_size); |
e0001a05 NC |
9386 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); |
9387 | fragP->fr_var -= lit_size; | |
9388 | fragP->fr_fix += lit_size; | |
9389 | new_stretch = 4; | |
9390 | break; | |
9391 | ||
43cd72b9 BW |
9392 | case RELAX_SLOTS: |
9393 | if (vbuf == NULL) | |
9394 | vbuf = xtensa_insnbuf_alloc (isa); | |
9395 | ||
d77b99c9 BW |
9396 | xtensa_insnbuf_from_chars |
9397 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
9398 | fmt = xtensa_format_decode (isa, vbuf); |
9399 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 9400 | |
43cd72b9 BW |
9401 | for (slot = 0; slot < num_slots; slot++) |
9402 | { | |
9403 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
9404 | { | |
9405 | case RELAX_NARROW: | |
9406 | if (fragP->tc_frag_data.relax_seen) | |
9407 | new_stretch += relax_frag_for_align (fragP, stretch); | |
9408 | break; | |
9409 | ||
9410 | case RELAX_IMMED: | |
9411 | case RELAX_IMMED_STEP1: | |
9412 | case RELAX_IMMED_STEP2: | |
b81bf389 | 9413 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
9414 | /* Place the immediate. */ |
9415 | new_stretch += relax_frag_immed | |
9416 | (now_seg, fragP, stretch, | |
9417 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
9418 | fmt, slot, stretched_p, FALSE); | |
9419 | break; | |
9420 | ||
9421 | default: | |
9422 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
9423 | break; | |
9424 | } | |
9425 | } | |
e0001a05 NC |
9426 | break; |
9427 | ||
9428 | case RELAX_LITERAL_POOL_BEGIN: | |
b46824bd MF |
9429 | if (fragP->fr_var != 0) |
9430 | { | |
9431 | /* We have a converted "candidate" literal pool; | |
9432 | assemble a jump around it. */ | |
9433 | TInsn insn; | |
9434 | if (!litpool_slotbuf) | |
9435 | { | |
9436 | litpool_buf = xtensa_insnbuf_alloc (isa); | |
9437 | litpool_slotbuf = xtensa_insnbuf_alloc (isa); | |
9438 | } | |
9439 | new_stretch += 3; | |
9440 | fragP->tc_frag_data.relax_seen = FALSE; /* Need another pass. */ | |
9441 | fragP->tc_frag_data.is_insn = TRUE; | |
9442 | tinsn_init (&insn); | |
9443 | insn.insn_type = ITYPE_INSN; | |
9444 | insn.opcode = xtensa_j_opcode; | |
9445 | insn.ntok = 1; | |
9446 | set_expr_symbol_offset (&insn.tok[0], fragP->fr_symbol, | |
9447 | fragP->fr_fix); | |
9448 | fmt = xg_get_single_format (xtensa_j_opcode); | |
9449 | tinsn_to_slotbuf (fmt, 0, &insn, litpool_slotbuf); | |
9450 | xtensa_format_set_slot (isa, fmt, 0, litpool_buf, litpool_slotbuf); | |
9451 | xtensa_insnbuf_to_chars (isa, litpool_buf, | |
9452 | (unsigned char *)fragP->fr_literal + | |
9453 | fragP->fr_fix, 3); | |
9454 | fragP->fr_fix += 3; | |
9455 | fragP->fr_var -= 3; | |
9456 | /* Add a fix-up. */ | |
9457 | fix_new (fragP, 0, 3, fragP->fr_symbol, 0, TRUE, | |
9458 | BFD_RELOC_XTENSA_SLOT0_OP); | |
9459 | } | |
9460 | break; | |
9461 | ||
e0001a05 | 9462 | case RELAX_LITERAL_POOL_END: |
b46824bd | 9463 | case RELAX_LITERAL_POOL_CANDIDATE_BEGIN: |
43cd72b9 BW |
9464 | case RELAX_MAYBE_UNREACHABLE: |
9465 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
9466 | /* No relaxation required. */ |
9467 | break; | |
9468 | ||
43cd72b9 BW |
9469 | case RELAX_FILL_NOP: |
9470 | case RELAX_UNREACHABLE: | |
9471 | if (fragP->tc_frag_data.relax_seen) | |
9472 | new_stretch += relax_frag_for_align (fragP, stretch); | |
9473 | break; | |
9474 | ||
a82c7d90 DW |
9475 | case RELAX_TRAMPOLINE: |
9476 | if (fragP->tc_frag_data.relax_seen) | |
120bc8b8 | 9477 | xg_relax_trampoline (fragP, stretch, &new_stretch); |
a82c7d90 DW |
9478 | break; |
9479 | ||
e0001a05 NC |
9480 | default: |
9481 | as_bad (_("bad relaxation state")); | |
9482 | } | |
9483 | ||
43cd72b9 | 9484 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 9485 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
9486 | { |
9487 | fragP->tc_frag_data.relax_seen = TRUE; | |
9488 | *stretched_p = 1; | |
9489 | } | |
9490 | ||
e0001a05 NC |
9491 | new_logical_line (file_name, line); |
9492 | return new_stretch; | |
9493 | } | |
9494 | ||
9495 | ||
9496 | static long | |
7fa3d080 | 9497 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
9498 | { |
9499 | addressT old_address, old_next_address, old_size; | |
9500 | addressT new_address, new_next_address, new_size; | |
9501 | addressT growth; | |
9502 | ||
43cd72b9 BW |
9503 | /* All the frags with relax_frag_for_alignment prior to this one in the |
9504 | section have been done, hopefully eliminating the need for a NOP here. | |
9505 | But, this will put it in if necessary. */ | |
e0001a05 NC |
9506 | |
9507 | /* Calculate the old address of this fragment and the next fragment. */ | |
9508 | old_address = fragP->fr_address - stretch; | |
9509 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 9510 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
9511 | old_size = old_next_address - old_address; |
9512 | ||
9513 | /* Calculate the new address of this fragment and the next fragment. */ | |
9514 | new_address = fragP->fr_address; | |
9515 | new_next_address = | |
9516 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
9517 | new_size = new_next_address - new_address; | |
9518 | ||
9519 | growth = new_size - old_size; | |
9520 | ||
9521 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 9522 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
9523 | return growth; |
9524 | } | |
9525 | ||
9526 | ||
43cd72b9 | 9527 | /* Add a NOP instruction. */ |
e0001a05 NC |
9528 | |
9529 | static long | |
7fa3d080 | 9530 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 9531 | { |
e0001a05 | 9532 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
9533 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
9534 | assemble_nop (length, nop_buf); | |
e0001a05 | 9535 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 9536 | |
e0001a05 NC |
9537 | if (fragP->fr_var < length) |
9538 | { | |
dd49a749 | 9539 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
9540 | return 0; |
9541 | } | |
9542 | ||
9543 | fragP->fr_fix += length; | |
9544 | fragP->fr_var -= length; | |
e0001a05 NC |
9545 | return length; |
9546 | } | |
9547 | ||
9548 | ||
7fa3d080 BW |
9549 | static long future_alignment_required (fragS *, long); |
9550 | ||
e0001a05 | 9551 | static long |
7fa3d080 | 9552 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 9553 | { |
43cd72b9 BW |
9554 | /* Overview of the relaxation procedure for alignment: |
9555 | We can widen with NOPs or by widening instructions or by filling | |
9556 | bytes after jump instructions. Find the opportune places and widen | |
9557 | them if necessary. */ | |
9558 | ||
9559 | long stretch_me; | |
9560 | long diff; | |
e0001a05 | 9561 | |
9c2799c2 | 9562 | gas_assert (fragP->fr_subtype == RELAX_FILL_NOP |
43cd72b9 BW |
9563 | || fragP->fr_subtype == RELAX_UNREACHABLE |
9564 | || (fragP->fr_subtype == RELAX_SLOTS | |
9565 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
9566 | ||
9567 | stretch_me = future_alignment_required (fragP, stretch); | |
9568 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
9569 | if (diff == 0) | |
9570 | return 0; | |
e0001a05 | 9571 | |
43cd72b9 | 9572 | if (diff < 0) |
e0001a05 | 9573 | { |
43cd72b9 BW |
9574 | /* We expanded on a previous pass. Can we shrink now? */ |
9575 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
9576 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 9577 | { |
43cd72b9 BW |
9578 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
9579 | return -shrink; | |
e0001a05 NC |
9580 | } |
9581 | return 0; | |
9582 | } | |
9583 | ||
43cd72b9 BW |
9584 | /* Below here, diff > 0. */ |
9585 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 9586 | |
43cd72b9 | 9587 | return diff; |
e0001a05 NC |
9588 | } |
9589 | ||
9590 | ||
43cd72b9 BW |
9591 | /* Return the address of the next frag that should be aligned. |
9592 | ||
9593 | By "address" we mean the address it _would_ be at if there | |
9594 | is no action taken to align it between here and the target frag. | |
9595 | In other words, if no narrows and no fill nops are used between | |
9596 | here and the frag to align, _even_if_ some of the frags we use | |
9597 | to align targets have already expanded on a previous relaxation | |
9598 | pass. | |
9599 | ||
9600 | Also, count each frag that may be used to help align the target. | |
9601 | ||
9602 | Return 0 if there are no frags left in the chain that need to be | |
9603 | aligned. */ | |
9604 | ||
9605 | static addressT | |
7fa3d080 BW |
9606 | find_address_of_next_align_frag (fragS **fragPP, |
9607 | int *wide_nops, | |
9608 | int *narrow_nops, | |
9609 | int *widens, | |
9610 | bfd_boolean *paddable) | |
e0001a05 | 9611 | { |
43cd72b9 BW |
9612 | fragS *fragP = *fragPP; |
9613 | addressT address = fragP->fr_address; | |
9614 | ||
9615 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
9616 | |
9617 | while (fragP) | |
9618 | { | |
9619 | /* Limit this to a small search. */ | |
b5e4a23d | 9620 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
9621 | { |
9622 | *fragPP = fragP; | |
9623 | return 0; | |
9624 | } | |
e0001a05 NC |
9625 | address += fragP->fr_fix; |
9626 | ||
43cd72b9 BW |
9627 | if (fragP->fr_type == rs_fill) |
9628 | address += fragP->fr_offset * fragP->fr_var; | |
9629 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 9630 | { |
e0001a05 NC |
9631 | switch (fragP->fr_subtype) |
9632 | { | |
43cd72b9 BW |
9633 | case RELAX_UNREACHABLE: |
9634 | *paddable = TRUE; | |
9635 | break; | |
9636 | ||
9637 | case RELAX_FILL_NOP: | |
9638 | (*wide_nops)++; | |
9639 | if (!fragP->tc_frag_data.is_no_density) | |
9640 | (*narrow_nops)++; | |
9641 | break; | |
9642 | ||
9643 | case RELAX_SLOTS: | |
9644 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
9645 | { | |
9646 | (*widens)++; | |
9647 | break; | |
9648 | } | |
5bb3703f | 9649 | address += total_frag_text_expansion (fragP); |
e0001a05 NC |
9650 | break; |
9651 | ||
9652 | case RELAX_IMMED: | |
43cd72b9 | 9653 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
9654 | break; |
9655 | ||
9656 | case RELAX_ALIGN_NEXT_OPCODE: | |
9657 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
9658 | *fragPP = fragP; |
9659 | return address; | |
9660 | ||
9661 | case RELAX_MAYBE_UNREACHABLE: | |
9662 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9663 | /* Do nothing. */ | |
e0001a05 NC |
9664 | break; |
9665 | ||
9666 | default: | |
43cd72b9 BW |
9667 | /* Just punt if we don't know the type. */ |
9668 | *fragPP = fragP; | |
9669 | return 0; | |
e0001a05 | 9670 | } |
43cd72b9 | 9671 | } |
c138bc38 | 9672 | else |
43cd72b9 BW |
9673 | { |
9674 | /* Just punt if we don't know the type. */ | |
9675 | *fragPP = fragP; | |
9676 | return 0; | |
9677 | } | |
9678 | fragP = fragP->fr_next; | |
9679 | } | |
9680 | ||
9681 | *fragPP = fragP; | |
9682 | return 0; | |
9683 | } | |
9684 | ||
9685 | ||
7fa3d080 BW |
9686 | static long bytes_to_stretch (fragS *, int, int, int, int); |
9687 | ||
43cd72b9 | 9688 | static long |
7fa3d080 | 9689 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
9690 | { |
9691 | fragS *this_frag = fragP; | |
9692 | long address; | |
9693 | int num_widens = 0; | |
9694 | int wide_nops = 0; | |
9695 | int narrow_nops = 0; | |
9696 | bfd_boolean paddable = FALSE; | |
9697 | offsetT local_opt_diff; | |
9698 | offsetT opt_diff; | |
9699 | offsetT max_diff; | |
9700 | int stretch_amount = 0; | |
9701 | int local_stretch_amount; | |
9702 | int global_stretch_amount; | |
9703 | ||
7fa3d080 BW |
9704 | address = find_address_of_next_align_frag |
9705 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 9706 | |
b5e4a23d BW |
9707 | if (!address) |
9708 | { | |
9709 | if (this_frag->tc_frag_data.is_aligning_branch) | |
9710 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
9711 | else | |
9712 | frag_wane (this_frag); | |
9713 | } | |
9714 | else | |
43cd72b9 BW |
9715 | { |
9716 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
9717 | opt_diff = local_opt_diff; | |
9c2799c2 NC |
9718 | gas_assert (opt_diff >= 0); |
9719 | gas_assert (max_diff >= opt_diff); | |
c138bc38 | 9720 | if (max_diff == 0) |
43cd72b9 | 9721 | return 0; |
d2a033cd | 9722 | |
43cd72b9 BW |
9723 | if (fragP) |
9724 | fragP = fragP->fr_next; | |
9725 | ||
9726 | while (fragP && opt_diff < max_diff && address) | |
9727 | { | |
9728 | /* We only use these to determine if we can exit early | |
c138bc38 | 9729 | because there will be plenty of ways to align future |
43cd72b9 | 9730 | align frags. */ |
d77b99c9 | 9731 | int glob_widens = 0; |
43cd72b9 BW |
9732 | int dnn = 0; |
9733 | int dw = 0; | |
9734 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
9735 | address = find_address_of_next_align_frag |
9736 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 9737 | /* If there is a padable portion, then skip. */ |
664df4e4 | 9738 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 9739 | address = 0; |
43cd72b9 | 9740 | |
c138bc38 | 9741 | if (address) |
43cd72b9 BW |
9742 | { |
9743 | offsetT next_m_diff; | |
9744 | offsetT next_o_diff; | |
9745 | ||
9746 | /* Downrange frags haven't had stretch added to them yet. */ | |
9747 | address += stretch; | |
9748 | ||
9749 | /* The address also includes any text expansion from this | |
9750 | frag in a previous pass, but we don't want that. */ | |
9751 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
9752 | ||
9753 | /* Assume we are going to move at least opt_diff. In | |
9754 | reality, we might not be able to, but assuming that | |
9755 | we will helps catch cases where moving opt_diff pushes | |
9756 | the next target from aligned to unaligned. */ | |
9757 | address += opt_diff; | |
9758 | ||
9759 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
9760 | ||
9761 | /* Now cleanup for the adjustments to address. */ | |
9762 | next_o_diff += opt_diff; | |
9763 | next_m_diff += opt_diff; | |
9764 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
9765 | opt_diff = next_o_diff; | |
9766 | if (next_m_diff < max_diff) | |
9767 | max_diff = next_m_diff; | |
9768 | fragP = fragP->fr_next; | |
9769 | } | |
9770 | } | |
d2a033cd | 9771 | |
43cd72b9 BW |
9772 | /* If there are enough wideners in between, do it. */ |
9773 | if (paddable) | |
9774 | { | |
9775 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
9776 | { | |
1beeb686 | 9777 | gas_assert (opt_diff <= (signed) xtensa_fetch_width); |
43cd72b9 BW |
9778 | return opt_diff; |
9779 | } | |
9780 | return 0; | |
9781 | } | |
c138bc38 | 9782 | local_stretch_amount |
43cd72b9 BW |
9783 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
9784 | num_widens, local_opt_diff); | |
c138bc38 BW |
9785 | global_stretch_amount |
9786 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 9787 | num_widens, opt_diff); |
c138bc38 BW |
9788 | /* If the condition below is true, then the frag couldn't |
9789 | stretch the correct amount for the global case, so we just | |
9790 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
9791 | the correct alignment in the global case. */ |
9792 | if (global_stretch_amount < local_stretch_amount) | |
9793 | stretch_amount = local_stretch_amount; | |
9794 | else | |
9795 | stretch_amount = global_stretch_amount; | |
d2a033cd | 9796 | |
43cd72b9 BW |
9797 | if (this_frag->fr_subtype == RELAX_SLOTS |
9798 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
9c2799c2 | 9799 | gas_assert (stretch_amount <= 1); |
43cd72b9 BW |
9800 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) |
9801 | { | |
9802 | if (this_frag->tc_frag_data.is_no_density) | |
9c2799c2 | 9803 | gas_assert (stretch_amount == 3 || stretch_amount == 0); |
43cd72b9 | 9804 | else |
9c2799c2 | 9805 | gas_assert (stretch_amount <= 3); |
43cd72b9 BW |
9806 | } |
9807 | } | |
9808 | return stretch_amount; | |
9809 | } | |
9810 | ||
9811 | ||
9812 | /* The idea: widen everything you can to get a target or loop aligned, | |
9813 | then start using NOPs. | |
9814 | ||
43cd72b9 BW |
9815 | wide_nops = the number of wide NOPs available for aligning |
9816 | narrow_nops = the number of narrow NOPs available for aligning | |
9817 | (a subset of wide_nops) | |
9818 | widens = the number of narrow instructions that should be widened | |
9819 | ||
43cd72b9 BW |
9820 | */ |
9821 | ||
9822 | static long | |
7fa3d080 BW |
9823 | bytes_to_stretch (fragS *this_frag, |
9824 | int wide_nops, | |
9825 | int narrow_nops, | |
9826 | int num_widens, | |
9827 | int desired_diff) | |
43cd72b9 | 9828 | { |
19ef5f3d SA |
9829 | int nops_needed; |
9830 | int nop_bytes; | |
9831 | int extra_bytes; | |
43cd72b9 BW |
9832 | int bytes_short = desired_diff - num_widens; |
9833 | ||
3739860c | 9834 | gas_assert (desired_diff >= 0 |
1beeb686 | 9835 | && desired_diff < (signed) xtensa_fetch_width); |
43cd72b9 BW |
9836 | if (desired_diff == 0) |
9837 | return 0; | |
c138bc38 | 9838 | |
9c2799c2 | 9839 | gas_assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 9840 | |
43cd72b9 BW |
9841 | /* Always prefer widening to NOP-filling. */ |
9842 | if (bytes_short < 0) | |
9843 | { | |
9844 | /* There are enough RELAX_NARROW frags after this one | |
9845 | to align the target without widening this frag in any way. */ | |
9846 | return 0; | |
9847 | } | |
c138bc38 | 9848 | |
43cd72b9 BW |
9849 | if (bytes_short == 0) |
9850 | { | |
9851 | /* Widen every narrow between here and the align target | |
9852 | and the align target will be properly aligned. */ | |
9853 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
9854 | return 0; | |
9855 | else | |
9856 | return 1; | |
9857 | } | |
c138bc38 | 9858 | |
43cd72b9 BW |
9859 | /* From here we will need at least one NOP to get an alignment. |
9860 | However, we may not be able to align at all, in which case, | |
9861 | don't widen. */ | |
19ef5f3d SA |
9862 | nops_needed = desired_diff / 3; |
9863 | ||
9864 | /* If there aren't enough nops, don't widen. */ | |
9865 | if (nops_needed > wide_nops) | |
9866 | return 0; | |
9867 | ||
9868 | /* First try it with all wide nops. */ | |
9869 | nop_bytes = nops_needed * 3; | |
9870 | extra_bytes = desired_diff - nop_bytes; | |
9871 | ||
9872 | if (nop_bytes + num_widens >= desired_diff) | |
43cd72b9 | 9873 | { |
19ef5f3d SA |
9874 | if (this_frag->fr_subtype == RELAX_FILL_NOP) |
9875 | return 3; | |
9876 | else if (num_widens == extra_bytes) | |
9877 | return 1; | |
9878 | return 0; | |
e0001a05 | 9879 | } |
19ef5f3d SA |
9880 | |
9881 | /* Add a narrow nop. */ | |
9882 | nops_needed++; | |
9883 | nop_bytes += 2; | |
9884 | extra_bytes -= 2; | |
9885 | if (narrow_nops == 0 || nops_needed > wide_nops) | |
9886 | return 0; | |
9887 | ||
9888 | if (nop_bytes + num_widens >= desired_diff && extra_bytes >= 0) | |
43cd72b9 | 9889 | { |
19ef5f3d SA |
9890 | if (this_frag->fr_subtype == RELAX_FILL_NOP) |
9891 | return !this_frag->tc_frag_data.is_no_density ? 2 : 3; | |
9892 | else if (num_widens == extra_bytes) | |
9893 | return 1; | |
9894 | return 0; | |
9895 | } | |
e0001a05 | 9896 | |
19ef5f3d SA |
9897 | /* Replace a wide nop with a narrow nop--we can get here if |
9898 | extra_bytes was negative in the previous conditional. */ | |
9899 | if (narrow_nops == 1) | |
9900 | return 0; | |
9901 | nop_bytes--; | |
9902 | extra_bytes++; | |
9903 | if (nop_bytes + num_widens >= desired_diff) | |
9904 | { | |
9905 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
9906 | return !this_frag->tc_frag_data.is_no_density ? 2 : 3; | |
9907 | else if (num_widens == extra_bytes) | |
9908 | return 1; | |
9909 | return 0; | |
43cd72b9 | 9910 | } |
19ef5f3d SA |
9911 | |
9912 | /* If we can't satisfy any of the above cases, then we can't align | |
9913 | using padding or fill nops. */ | |
43cd72b9 | 9914 | return 0; |
e0001a05 NC |
9915 | } |
9916 | ||
9917 | ||
a82c7d90 DW |
9918 | static struct trampoline_frag * |
9919 | search_trampolines (TInsn *tinsn, fragS *fragP, bfd_boolean unreachable_only) | |
9920 | { | |
9921 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); | |
9922 | struct trampoline_frag *tf = (ts) ? ts->trampoline_list.next : NULL; | |
9923 | struct trampoline_frag *best_tf = NULL; | |
9924 | int best_delta = 0; | |
9925 | int best_addr = 0; | |
9926 | symbolS *sym = tinsn->tok[0].X_add_symbol; | |
9927 | offsetT target = S_GET_VALUE (sym) + tinsn->tok[0].X_add_number; | |
9928 | offsetT addr = fragP->fr_address; | |
9929 | offsetT lower = (addr < target) ? addr : target; | |
9930 | offsetT upper = (addr > target) ? addr : target; | |
9931 | int delta = upper - lower; | |
9932 | offsetT midpoint = lower + delta / 2; | |
9933 | int this_delta = -1; | |
9934 | int this_addr = -1; | |
9935 | ||
9936 | if (delta > 2 * J_RANGE) | |
9937 | { | |
9938 | /* One trampoline won't do; we need multiple. | |
9939 | Choose the farthest trampoline that's still in range of the original | |
9940 | and let a later pass finish the job. */ | |
9941 | for ( ; tf; tf = tf->next) | |
9942 | { | |
9943 | int next_addr = (tf->next) ? tf->next->fragP->fr_address + tf->next->fragP->fr_fix : 0; | |
9944 | ||
9945 | this_addr = tf->fragP->fr_address + tf->fragP->fr_fix; | |
9946 | if (lower == addr) | |
9947 | { | |
9948 | /* Forward jump. */ | |
9949 | if (this_addr - addr < J_RANGE) | |
9950 | break; | |
9951 | } | |
9952 | else | |
9953 | { | |
9954 | /* Backward jump. */ | |
9955 | if (next_addr == 0 || addr - next_addr > J_RANGE) | |
9956 | break; | |
9957 | } | |
a82c7d90 | 9958 | } |
d92b6eec MF |
9959 | if (abs (addr - this_addr) < J_RANGE) |
9960 | return tf; | |
9961 | ||
9962 | return NULL; | |
a82c7d90 DW |
9963 | } |
9964 | for ( ; tf; tf = tf->next) | |
9965 | { | |
9966 | this_addr = tf->fragP->fr_address + tf->fragP->fr_fix; | |
9967 | this_delta = abs (this_addr - midpoint); | |
9968 | if (unreachable_only && tf->needs_jump_around) | |
9969 | continue; | |
9970 | if (!best_tf || this_delta < best_delta) | |
9971 | { | |
9972 | best_tf = tf; | |
9973 | best_delta = this_delta; | |
9974 | best_addr = this_addr; | |
9975 | } | |
9976 | } | |
9977 | ||
9978 | if (best_tf && | |
9979 | best_delta < J_RANGE && | |
9980 | abs(best_addr - lower) < J_RANGE && | |
9981 | abs(best_addr - upper) < J_RANGE) | |
9982 | return best_tf; | |
9983 | ||
9984 | return NULL; /* No suitable trampoline found. */ | |
9985 | } | |
9986 | ||
9987 | ||
9988 | static struct trampoline_frag * | |
9989 | get_best_trampoline (TInsn *tinsn, fragS *fragP) | |
9990 | { | |
9991 | struct trampoline_frag *tf = NULL; | |
9992 | ||
9993 | tf = search_trampolines (tinsn, fragP, TRUE); /* Try unreachable first. */ | |
9994 | ||
9995 | if (tf == NULL) | |
9996 | tf = search_trampolines (tinsn, fragP, FALSE); /* Try ones needing a jump-around, too. */ | |
9997 | ||
9998 | return tf; | |
9999 | } | |
10000 | ||
10001 | ||
10002 | static void | |
10003 | check_and_update_trampolines (void) | |
10004 | { | |
10005 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); | |
10006 | struct trampoline_frag *tf = ts->trampoline_list.next; | |
10007 | struct trampoline_frag *prev = &ts->trampoline_list; | |
10008 | ||
10009 | for ( ; tf; prev = tf, tf = tf->next) | |
10010 | { | |
10011 | if (tf->fragP->fr_var < 3) | |
10012 | { | |
10013 | frag_wane (tf->fragP); | |
10014 | prev->next = tf->next; | |
10015 | tf->fragP = NULL; | |
10016 | } | |
10017 | } | |
10018 | } | |
10019 | ||
10020 | ||
10021 | static int | |
10022 | init_trampoline_frag (struct trampoline_frag *trampP) | |
10023 | { | |
10024 | fragS *fp = trampP->fragP; | |
10025 | int growth = 0; | |
10026 | ||
10027 | if (fp->fr_fix == 0) | |
10028 | { | |
10029 | symbolS *lsym; | |
10030 | char label[10 + 2 * sizeof(fp)]; | |
10031 | sprintf (label, ".L0_TR_%p", fp); | |
10032 | ||
10033 | lsym = (symbolS *)local_symbol_make (label, now_seg, 0, fp); | |
10034 | fp->fr_symbol = lsym; | |
10035 | if (trampP->needs_jump_around) | |
10036 | { | |
10037 | /* Add a jump around this block of jumps, in case | |
10038 | control flows into this block. */ | |
10039 | fixS *fixP; | |
10040 | TInsn insn; | |
10041 | xtensa_format fmt; | |
10042 | xtensa_isa isa = xtensa_default_isa; | |
10043 | ||
10044 | fp->tc_frag_data.is_insn = 1; | |
10045 | /* Assemble a jump insn. */ | |
10046 | tinsn_init (&insn); | |
10047 | insn.insn_type = ITYPE_INSN; | |
10048 | insn.opcode = xtensa_j_opcode; | |
10049 | insn.ntok = 1; | |
10050 | set_expr_symbol_offset (&insn.tok[0], lsym, 3); | |
10051 | fmt = xg_get_single_format (xtensa_j_opcode); | |
10052 | tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf); | |
10053 | xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf); | |
10054 | xtensa_insnbuf_to_chars (isa, trampoline_buf, (unsigned char *)fp->fr_literal, 3); | |
10055 | fp->fr_fix += 3; | |
10056 | fp->fr_var -= 3; | |
10057 | growth = 3; | |
10058 | fixP = fix_new (fp, 0, 3, lsym, 3, TRUE, BFD_RELOC_XTENSA_SLOT0_OP); | |
10059 | trampP->fixP = fixP; | |
10060 | } | |
10061 | } | |
10062 | return growth; | |
10063 | } | |
10064 | ||
10065 | ||
10066 | static int | |
10067 | add_jump_to_trampoline (struct trampoline_frag *trampP, fragS *origfrag) | |
10068 | { | |
10069 | fragS *tramp = trampP->fragP; | |
10070 | fixS *fixP; | |
10071 | int offset = tramp->fr_fix; /* Where to assemble the j insn. */ | |
10072 | TInsn insn; | |
10073 | symbolS *lsym; | |
10074 | symbolS *tsym; | |
10075 | int toffset; | |
10076 | xtensa_format fmt; | |
10077 | xtensa_isa isa = xtensa_default_isa; | |
10078 | int growth = 0; | |
24e5b4e6 MF |
10079 | int i, slot = -1; |
10080 | ||
10081 | for (i = 0; i < MAX_SLOTS; ++i) | |
10082 | if (origfrag->tc_frag_data.slot_symbols[i]) | |
10083 | { | |
10084 | gas_assert (slot == -1); | |
10085 | slot = i; | |
10086 | } | |
10087 | ||
10088 | gas_assert (slot >= 0 && slot < MAX_SLOTS); | |
a82c7d90 DW |
10089 | |
10090 | lsym = tramp->fr_symbol; | |
10091 | /* Assemble a jump to the target label in the trampoline frag. */ | |
24e5b4e6 MF |
10092 | tsym = origfrag->tc_frag_data.slot_symbols[slot]; |
10093 | toffset = origfrag-> tc_frag_data.slot_offsets[slot]; | |
a82c7d90 DW |
10094 | tinsn_init (&insn); |
10095 | insn.insn_type = ITYPE_INSN; | |
10096 | insn.opcode = xtensa_j_opcode; | |
10097 | insn.ntok = 1; | |
10098 | set_expr_symbol_offset (&insn.tok[0], tsym, toffset); | |
10099 | fmt = xg_get_single_format (xtensa_j_opcode); | |
10100 | tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf); | |
10101 | xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf); | |
10102 | xtensa_insnbuf_to_chars (isa, trampoline_buf, (unsigned char *)tramp->fr_literal + offset, 3); | |
10103 | tramp->fr_fix += 3; | |
10104 | tramp->fr_var -= 3; | |
10105 | growth = 3; | |
10106 | /* add a fix-up for the trampoline jump. */ | |
10107 | fixP = fix_new (tramp, tramp->fr_fix - 3, 3, tsym, toffset, TRUE, BFD_RELOC_XTENSA_SLOT0_OP); | |
10108 | /* Modify the jump at the start of this trampoline to point past the newly-added jump. */ | |
10109 | fixP = trampP->fixP; | |
10110 | if (fixP) | |
10111 | fixP->fx_offset += 3; | |
10112 | /* Modify the original j to point here. */ | |
24e5b4e6 MF |
10113 | origfrag->tc_frag_data.slot_symbols[slot] = lsym; |
10114 | origfrag->tc_frag_data.slot_offsets[slot] = tramp->fr_fix - 3; | |
a82c7d90 DW |
10115 | /* If trampoline is full, remove it from the list. */ |
10116 | check_and_update_trampolines (); | |
10117 | ||
10118 | return growth; | |
10119 | } | |
10120 | ||
10121 | ||
e0001a05 | 10122 | static long |
7fa3d080 BW |
10123 | relax_frag_immed (segT segP, |
10124 | fragS *fragP, | |
10125 | long stretch, | |
10126 | int min_steps, | |
10127 | xtensa_format fmt, | |
10128 | int slot, | |
10129 | int *stretched_p, | |
10130 | bfd_boolean estimate_only) | |
e0001a05 | 10131 | { |
43cd72b9 | 10132 | TInsn tinsn; |
e0001a05 NC |
10133 | int old_size; |
10134 | bfd_boolean negatable_branch = FALSE; | |
10135 | bfd_boolean branch_jmp_to_next = FALSE; | |
def13efb | 10136 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 | 10137 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
10138 | IStack istack; |
10139 | offsetT frag_offset; | |
10140 | int num_steps; | |
e0001a05 | 10141 | int num_text_bytes, num_literal_bytes; |
2276bc20 | 10142 | int literal_diff, total_text_diff, this_text_diff; |
e0001a05 | 10143 | |
9c2799c2 | 10144 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 10145 | |
b5e4a23d BW |
10146 | xg_clear_vinsn (&cur_vinsn); |
10147 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 10148 | if (cur_vinsn.num_slots > 1) |
def13efb | 10149 | from_wide_insn = TRUE; |
43cd72b9 | 10150 | |
b5e4a23d | 10151 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 10152 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 10153 | |
64b607e6 | 10154 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 10155 | return 0; |
e0001a05 | 10156 | |
b08b5071 | 10157 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 10158 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 10159 | |
43cd72b9 | 10160 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 10161 | |
43cd72b9 | 10162 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
10163 | |
10164 | /* Special case: replace a branch to the next instruction with a NOP. | |
10165 | This is required to work around a hardware bug in T1040.0 and also | |
10166 | serves as an optimization. */ | |
10167 | ||
10168 | if (branch_jmp_to_next | |
10169 | && ((old_size == 2) || (old_size == 3)) | |
10170 | && !next_frag_is_loop_target (fragP)) | |
10171 | return 0; | |
10172 | ||
10173 | /* Here is the fun stuff: Get the immediate field from this | |
10174 | instruction. If it fits, we are done. If not, find the next | |
10175 | instruction sequence that fits. */ | |
10176 | ||
10177 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
10178 | istack_init (&istack); | |
43cd72b9 | 10179 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 | 10180 | min_steps, stretch); |
9c2799c2 | 10181 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
e0001a05 | 10182 | |
43cd72b9 | 10183 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
10184 | |
10185 | /* Figure out the number of bytes needed. */ | |
e0001a05 | 10186 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
2276bc20 BW |
10187 | literal_diff |
10188 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
43cd72b9 | 10189 | num_text_bytes = get_num_stack_text_bytes (&istack); |
def13efb BW |
10190 | |
10191 | if (from_wide_insn) | |
43cd72b9 | 10192 | { |
2276bc20 BW |
10193 | int first = 0; |
10194 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
10195 | first++; | |
10196 | ||
43cd72b9 BW |
10197 | num_text_bytes += old_size; |
10198 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
10199 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
2276bc20 BW |
10200 | else |
10201 | { | |
10202 | /* The first instruction in the relaxed sequence will go after | |
10203 | the current wide instruction, and thus its symbolic immediates | |
10204 | might not fit. */ | |
3739860c | 10205 | |
2276bc20 | 10206 | istack_init (&istack); |
3739860c | 10207 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, |
2276bc20 BW |
10208 | frag_offset + old_size, |
10209 | min_steps, stretch + old_size); | |
9c2799c2 | 10210 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
2276bc20 | 10211 | |
3739860c | 10212 | fragP->tc_frag_data.slot_subtypes[slot] |
2276bc20 BW |
10213 | = (int) RELAX_IMMED + num_steps; |
10214 | ||
10215 | num_literal_bytes = get_num_stack_literal_bytes (&istack); | |
3739860c | 10216 | literal_diff |
2276bc20 | 10217 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; |
3739860c | 10218 | |
2276bc20 BW |
10219 | num_text_bytes = get_num_stack_text_bytes (&istack) + old_size; |
10220 | } | |
43cd72b9 | 10221 | } |
def13efb | 10222 | |
43cd72b9 BW |
10223 | total_text_diff = num_text_bytes - old_size; |
10224 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
10225 | |
10226 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
9c2799c2 NC |
10227 | gas_assert (num_text_bytes >= 0); |
10228 | gas_assert (literal_diff >= 0); | |
10229 | gas_assert (total_text_diff >= 0); | |
e0001a05 | 10230 | |
43cd72b9 BW |
10231 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
10232 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
9c2799c2 NC |
10233 | gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0); |
10234 | gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
10235 | |
10236 | /* Find the associated expandable literal for this. */ | |
10237 | if (literal_diff != 0) | |
10238 | { | |
2276bc20 | 10239 | fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
10240 | if (lit_fragP) |
10241 | { | |
9c2799c2 | 10242 | gas_assert (literal_diff == 4); |
e0001a05 NC |
10243 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; |
10244 | ||
10245 | /* We expect that the literal section state has NOT been | |
10246 | modified yet. */ | |
9c2799c2 | 10247 | gas_assert (lit_fragP->fr_type == rs_machine_dependent |
e0001a05 NC |
10248 | && lit_fragP->fr_subtype == RELAX_LITERAL); |
10249 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
10250 | ||
10251 | /* We need to mark this section for another iteration | |
10252 | of relaxation. */ | |
10253 | (*stretched_p)++; | |
10254 | } | |
10255 | } | |
10256 | ||
43cd72b9 | 10257 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 10258 | update_next_frag_state (fragP); |
e0001a05 | 10259 | |
a82c7d90 DW |
10260 | /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */ |
10261 | if (istack.ninsn > 2 && | |
10262 | istack.insn[istack.ninsn - 1].insn_type == ITYPE_LABEL && | |
10263 | istack.insn[istack.ninsn - 2].insn_type == ITYPE_INSN && | |
10264 | istack.insn[istack.ninsn - 2].opcode == xtensa_j_opcode) | |
10265 | { | |
10266 | TInsn *jinsn = &istack.insn[istack.ninsn - 2]; | |
10267 | ||
10268 | if (!xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset, total_text_diff)) | |
10269 | { | |
10270 | struct trampoline_frag *tf = get_best_trampoline (jinsn, fragP); | |
10271 | ||
10272 | if (tf) | |
10273 | { | |
10274 | this_text_diff += init_trampoline_frag (tf); | |
10275 | this_text_diff += add_jump_to_trampoline (tf, fragP); | |
10276 | } | |
10277 | else | |
10278 | { | |
10279 | /* If target symbol is undefined, assume it will reach once linked. */ | |
10280 | expressionS *exp = &istack.insn[istack.ninsn - 2].tok[0]; | |
10281 | ||
10282 | if (exp->X_op == O_symbol && S_IS_DEFINED (exp->X_add_symbol)) | |
10283 | { | |
10284 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10285 | _("jump target out of range; no usable trampoline found")); | |
10286 | } | |
10287 | } | |
10288 | } | |
10289 | } | |
10290 | ||
43cd72b9 | 10291 | return this_text_diff; |
e0001a05 NC |
10292 | } |
10293 | ||
10294 | \f | |
10295 | /* md_convert_frag Hook and Helper Functions. */ | |
10296 | ||
7fa3d080 BW |
10297 | static void convert_frag_align_next_opcode (fragS *); |
10298 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
10299 | static void convert_frag_fill_nop (fragS *); | |
10300 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
10301 | ||
e0001a05 | 10302 | void |
7fa3d080 | 10303 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 10304 | { |
43cd72b9 BW |
10305 | static xtensa_insnbuf vbuf = NULL; |
10306 | xtensa_isa isa = xtensa_default_isa; | |
10307 | int slot; | |
10308 | int num_slots; | |
10309 | xtensa_format fmt; | |
3b4dbbbf | 10310 | const char *file_name; |
d77b99c9 | 10311 | unsigned line; |
e0001a05 | 10312 | |
3b4dbbbf | 10313 | file_name = as_where (&line); |
e0001a05 NC |
10314 | new_logical_line (fragp->fr_file, fragp->fr_line); |
10315 | ||
10316 | switch (fragp->fr_subtype) | |
10317 | { | |
10318 | case RELAX_ALIGN_NEXT_OPCODE: | |
10319 | /* Always convert. */ | |
10320 | convert_frag_align_next_opcode (fragp); | |
10321 | break; | |
10322 | ||
10323 | case RELAX_DESIRE_ALIGN: | |
10324 | /* Do nothing. If not aligned already, too bad. */ | |
10325 | break; | |
10326 | ||
43cd72b9 BW |
10327 | case RELAX_LITERAL: |
10328 | case RELAX_LITERAL_FINAL: | |
10329 | break; | |
10330 | ||
10331 | case RELAX_SLOTS: | |
10332 | if (vbuf == NULL) | |
10333 | vbuf = xtensa_insnbuf_alloc (isa); | |
10334 | ||
d77b99c9 BW |
10335 | xtensa_insnbuf_from_chars |
10336 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
10337 | fmt = xtensa_format_decode (isa, vbuf); |
10338 | num_slots = xtensa_format_num_slots (isa, fmt); | |
10339 | ||
10340 | for (slot = 0; slot < num_slots; slot++) | |
10341 | { | |
10342 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
10343 | { | |
10344 | case RELAX_NARROW: | |
10345 | convert_frag_narrow (sec, fragp, fmt, slot); | |
10346 | break; | |
10347 | ||
10348 | case RELAX_IMMED: | |
10349 | case RELAX_IMMED_STEP1: | |
10350 | case RELAX_IMMED_STEP2: | |
b81bf389 | 10351 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
10352 | /* Place the immediate. */ |
10353 | convert_frag_immed | |
10354 | (sec, fragp, | |
10355 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
10356 | fmt, slot); | |
10357 | break; | |
10358 | ||
10359 | default: | |
10360 | /* This is OK because some slots could have | |
10361 | relaxations and others have none. */ | |
10362 | break; | |
10363 | } | |
10364 | } | |
10365 | break; | |
10366 | ||
10367 | case RELAX_UNREACHABLE: | |
10368 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
10369 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
10370 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
10371 | frag_wane (fragp); | |
e0001a05 NC |
10372 | break; |
10373 | ||
43cd72b9 BW |
10374 | case RELAX_MAYBE_UNREACHABLE: |
10375 | case RELAX_MAYBE_DESIRE_ALIGN: | |
10376 | frag_wane (fragp); | |
e0001a05 NC |
10377 | break; |
10378 | ||
43cd72b9 BW |
10379 | case RELAX_FILL_NOP: |
10380 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
10381 | break; |
10382 | ||
10383 | case RELAX_LITERAL_NR: | |
10384 | if (use_literal_section) | |
10385 | { | |
10386 | /* This should have been handled during relaxation. When | |
10387 | relaxing a code segment, literals sometimes need to be | |
10388 | added to the corresponding literal segment. If that | |
10389 | literal segment has already been relaxed, then we end up | |
10390 | in this situation. Marking the literal segments as data | |
10391 | would make this happen less often (since GAS always relaxes | |
10392 | code before data), but we could still get into trouble if | |
10393 | there are instructions in a segment that is not marked as | |
10394 | containing code. Until we can implement a better solution, | |
10395 | cheat and adjust the addresses of all the following frags. | |
10396 | This could break subsequent alignments, but the linker's | |
10397 | literal coalescing will do that anyway. */ | |
10398 | ||
10399 | fragS *f; | |
10400 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 10401 | gas_assert (fragp->tc_frag_data.unreported_expansion == 4); |
e0001a05 NC |
10402 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); |
10403 | fragp->fr_var -= 4; | |
10404 | fragp->fr_fix += 4; | |
10405 | for (f = fragp->fr_next; f; f = f->fr_next) | |
10406 | f->fr_address += 4; | |
10407 | } | |
10408 | else | |
10409 | as_bad (_("invalid relaxation fragment result")); | |
10410 | break; | |
a82c7d90 DW |
10411 | |
10412 | case RELAX_TRAMPOLINE: | |
10413 | break; | |
e0001a05 NC |
10414 | } |
10415 | ||
10416 | fragp->fr_var = 0; | |
10417 | new_logical_line (file_name, line); | |
10418 | } | |
10419 | ||
10420 | ||
7fa3d080 BW |
10421 | static void |
10422 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
10423 | { |
10424 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
10425 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
10426 | addressT aligned_address; | |
d77b99c9 BW |
10427 | offsetT fill_size; |
10428 | int nop, nop_count; | |
e0001a05 NC |
10429 | |
10430 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
10431 | fragp->fr_fix); | |
10432 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
10433 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
10434 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
10435 | ||
d77b99c9 | 10436 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 10437 | { |
d77b99c9 BW |
10438 | int nop_size; |
10439 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
10440 | |
10441 | assemble_nop (nop_size, nop_buf); | |
10442 | nop_buf += nop_size; | |
10443 | } | |
10444 | ||
10445 | fragp->fr_fix += fill_size; | |
10446 | fragp->fr_var -= fill_size; | |
10447 | } | |
10448 | ||
10449 | ||
10450 | static void | |
7fa3d080 | 10451 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 10452 | { |
43cd72b9 | 10453 | TInsn tinsn, single_target; |
84b08ed9 | 10454 | int size, old_size, diff; |
e0001a05 NC |
10455 | offsetT frag_offset; |
10456 | ||
9c2799c2 | 10457 | gas_assert (slot == 0); |
43cd72b9 BW |
10458 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); |
10459 | ||
b5e4a23d | 10460 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 | 10461 | { |
9c2799c2 | 10462 | gas_assert (fragP->tc_frag_data.text_expansion[0] == 1 |
43cd72b9 BW |
10463 | || fragP->tc_frag_data.text_expansion[0] == 0); |
10464 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
10465 | fmt, slot); | |
10466 | return; | |
10467 | } | |
10468 | ||
10469 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
10470 | { |
10471 | /* No conversion. */ | |
10472 | fragP->fr_var = 0; | |
10473 | return; | |
10474 | } | |
10475 | ||
9c2799c2 | 10476 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 10477 | |
43cd72b9 BW |
10478 | /* Frags in this relaxation state should only contain |
10479 | single instruction bundles. */ | |
10480 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
10481 | |
10482 | /* Just convert it to a wide form.... */ | |
10483 | size = 0; | |
43cd72b9 | 10484 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
10485 | |
10486 | tinsn_init (&single_target); | |
10487 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
10488 | ||
84b08ed9 | 10489 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
10490 | { |
10491 | as_bad (_("unable to widen instruction")); | |
10492 | return; | |
10493 | } | |
10494 | ||
10495 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
10496 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
10497 | frag_offset, TRUE); | |
e0001a05 NC |
10498 | |
10499 | diff = size - old_size; | |
9c2799c2 NC |
10500 | gas_assert (diff >= 0); |
10501 | gas_assert (diff <= fragP->fr_var); | |
e0001a05 NC |
10502 | fragP->fr_var -= diff; |
10503 | fragP->fr_fix += diff; | |
10504 | ||
10505 | /* clean it up */ | |
10506 | fragP->fr_var = 0; | |
10507 | } | |
10508 | ||
10509 | ||
10510 | static void | |
7fa3d080 | 10511 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
10512 | { |
10513 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
10514 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 10515 | gas_assert ((unsigned) size == (fragP->fr_next->fr_address |
43cd72b9 BW |
10516 | - fragP->fr_address - fragP->fr_fix)); |
10517 | if (size == 0) | |
10518 | { | |
10519 | /* No conversion. */ | |
10520 | fragP->fr_var = 0; | |
10521 | return; | |
10522 | } | |
10523 | assemble_nop (size, loc); | |
10524 | fragP->tc_frag_data.is_insn = TRUE; | |
10525 | fragP->fr_var -= size; | |
10526 | fragP->fr_fix += size; | |
10527 | frag_wane (fragP); | |
10528 | } | |
10529 | ||
10530 | ||
7fa3d080 BW |
10531 | static fixS *fix_new_exp_in_seg |
10532 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
10533 | bfd_reloc_code_real_type); | |
10534 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
10535 | ||
43cd72b9 | 10536 | static void |
7fa3d080 BW |
10537 | convert_frag_immed (segT segP, |
10538 | fragS *fragP, | |
10539 | int min_steps, | |
10540 | xtensa_format fmt, | |
10541 | int slot) | |
e0001a05 NC |
10542 | { |
10543 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 10544 | TInsn orig_tinsn; |
e0001a05 | 10545 | bfd_boolean expanded = FALSE; |
e0001a05 | 10546 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 10547 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 | 10548 | xtensa_isa isa = xtensa_default_isa; |
def13efb | 10549 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 BW |
10550 | int bytes; |
10551 | bfd_boolean is_loop; | |
e0001a05 | 10552 | |
9c2799c2 | 10553 | gas_assert (fr_opcode != NULL); |
e0001a05 | 10554 | |
b5e4a23d | 10555 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 10556 | |
b5e4a23d | 10557 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 10558 | if (cur_vinsn.num_slots > 1) |
def13efb | 10559 | from_wide_insn = TRUE; |
e0001a05 | 10560 | |
b5e4a23d | 10561 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
10562 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
10563 | ||
10564 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 10565 | |
b08b5071 | 10566 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 10567 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
10568 | |
10569 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
10570 | { | |
10571 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
10572 | bytes = xtensa_format_length (isa, fmt); |
10573 | if (bytes >= 4) | |
10574 | { | |
b5e4a23d BW |
10575 | cur_vinsn.slots[slot].opcode = |
10576 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
10577 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
10578 | } |
10579 | else | |
10580 | { | |
10581 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 10582 | gas_assert (bytes == 2 || bytes == 3); |
b5e4a23d | 10583 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
10584 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
10585 | } | |
e7da6241 | 10586 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 10587 | xtensa_insnbuf_to_chars |
b5e4a23d | 10588 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
10589 | fragP->fr_var = 0; |
10590 | } | |
7c834684 | 10591 | else |
e0001a05 | 10592 | { |
43cd72b9 BW |
10593 | /* Here is the fun stuff: Get the immediate field from this |
10594 | instruction. If it fits, we're done. If not, find the next | |
10595 | instruction sequence that fits. */ | |
10596 | ||
e0001a05 NC |
10597 | IStack istack; |
10598 | int i; | |
10599 | symbolS *lit_sym = NULL; | |
10600 | int total_size = 0; | |
43cd72b9 | 10601 | int target_offset = 0; |
e0001a05 NC |
10602 | int old_size; |
10603 | int diff; | |
10604 | symbolS *gen_label = NULL; | |
10605 | offsetT frag_offset; | |
43cd72b9 | 10606 | bfd_boolean first = TRUE; |
e0001a05 | 10607 | |
43cd72b9 | 10608 | /* It does not fit. Find something that does and |
e0001a05 | 10609 | convert immediately. */ |
43cd72b9 | 10610 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 10611 | istack_init (&istack); |
43cd72b9 | 10612 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
10613 | segP, fragP, frag_offset, min_steps, 0); |
10614 | ||
43cd72b9 | 10615 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
10616 | |
10617 | /* Assemble this right inline. */ | |
10618 | ||
10619 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 10620 | target_offset = 0; |
e0001a05 NC |
10621 | for (i = 0; i < istack.ninsn; i++) |
10622 | { | |
43cd72b9 | 10623 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
10624 | fragS *lit_frag; |
10625 | ||
43cd72b9 | 10626 | switch (tinsn->insn_type) |
e0001a05 NC |
10627 | { |
10628 | case ITYPE_LITERAL: | |
10629 | if (lit_sym != NULL) | |
10630 | as_bad (_("multiple literals in expansion")); | |
10631 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 10632 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
10633 | if (lit_frag == NULL) |
10634 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 10635 | if (tinsn->ntok != 1) |
e0001a05 NC |
10636 | as_bad (_("number of literal tokens != 1")); |
10637 | ||
10638 | /* Set the literal symbol and add a fixup. */ | |
10639 | lit_sym = lit_frag->fr_symbol; | |
10640 | break; | |
10641 | ||
10642 | case ITYPE_LABEL: | |
43cd72b9 BW |
10643 | if (align_targets && !is_loop) |
10644 | { | |
10645 | fragS *unreach = fragP->fr_next; | |
10646 | while (!(unreach->fr_type == rs_machine_dependent | |
10647 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
10648 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
10649 | { | |
10650 | unreach = unreach->fr_next; | |
10651 | } | |
10652 | ||
9c2799c2 | 10653 | gas_assert (unreach->fr_type == rs_machine_dependent |
43cd72b9 BW |
10654 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE |
10655 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
10656 | ||
10657 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
10658 | } | |
9c2799c2 | 10659 | gas_assert (gen_label == NULL); |
e0001a05 | 10660 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, |
43cd72b9 BW |
10661 | fr_opcode - fragP->fr_literal |
10662 | + target_offset, fragP); | |
e0001a05 NC |
10663 | break; |
10664 | ||
10665 | case ITYPE_INSN: | |
def13efb | 10666 | if (first && from_wide_insn) |
43cd72b9 BW |
10667 | { |
10668 | target_offset += xtensa_format_length (isa, fmt); | |
10669 | first = FALSE; | |
10670 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
10671 | target_offset += xg_get_single_size (tinsn->opcode); | |
10672 | } | |
10673 | else | |
10674 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
10675 | break; |
10676 | } | |
10677 | } | |
10678 | ||
10679 | total_size = 0; | |
43cd72b9 | 10680 | first = TRUE; |
e0001a05 NC |
10681 | for (i = 0; i < istack.ninsn; i++) |
10682 | { | |
43cd72b9 | 10683 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
10684 | fragS *lit_frag; |
10685 | int size; | |
10686 | segT target_seg; | |
43cd72b9 | 10687 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 10688 | |
43cd72b9 | 10689 | switch (tinsn->insn_type) |
e0001a05 NC |
10690 | { |
10691 | case ITYPE_LITERAL: | |
43cd72b9 BW |
10692 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
10693 | /* Already checked. */ | |
9c2799c2 NC |
10694 | gas_assert (lit_frag != NULL); |
10695 | gas_assert (lit_sym != NULL); | |
10696 | gas_assert (tinsn->ntok == 1); | |
43cd72b9 | 10697 | /* Add a fixup. */ |
e0001a05 | 10698 | target_seg = S_GET_SEGMENT (lit_sym); |
9c2799c2 | 10699 | gas_assert (target_seg); |
28dbbc02 | 10700 | reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE); |
e0001a05 | 10701 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 10702 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
10703 | break; |
10704 | ||
10705 | case ITYPE_LABEL: | |
10706 | break; | |
10707 | ||
10708 | case ITYPE_INSN: | |
43cd72b9 BW |
10709 | xg_resolve_labels (tinsn, gen_label); |
10710 | xg_resolve_literals (tinsn, lit_sym); | |
def13efb | 10711 | if (from_wide_insn && first) |
43cd72b9 BW |
10712 | { |
10713 | first = FALSE; | |
10714 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
10715 | { | |
b5e4a23d | 10716 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
10717 | } |
10718 | else | |
10719 | { | |
b5e4a23d | 10720 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 10721 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 10722 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 10723 | } |
b5e4a23d BW |
10724 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
10725 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 10726 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
10727 | fragP->tc_frag_data.is_insn = TRUE; |
10728 | size = xtensa_format_length (isa, fmt); | |
10729 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
10730 | { | |
43cd72b9 | 10731 | xg_emit_insn_to_buf |
b2d179be | 10732 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
10733 | immed_instr - fragP->fr_literal + size, TRUE); |
10734 | size += xg_get_single_size (tinsn->opcode); | |
10735 | } | |
10736 | } | |
10737 | else | |
10738 | { | |
43cd72b9 | 10739 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 10740 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 10741 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 10742 | } |
e0001a05 | 10743 | immed_instr += size; |
43cd72b9 | 10744 | total_size += size; |
e0001a05 NC |
10745 | break; |
10746 | } | |
10747 | } | |
10748 | ||
10749 | diff = total_size - old_size; | |
9c2799c2 | 10750 | gas_assert (diff >= 0); |
e0001a05 NC |
10751 | if (diff != 0) |
10752 | expanded = TRUE; | |
9c2799c2 | 10753 | gas_assert (diff <= fragP->fr_var); |
e0001a05 NC |
10754 | fragP->fr_var -= diff; |
10755 | fragP->fr_fix += diff; | |
10756 | } | |
10757 | ||
e0001a05 | 10758 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 10759 | if (is_loop) |
e0001a05 NC |
10760 | { |
10761 | symbolS *sym; | |
43cd72b9 | 10762 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
10763 | if (sym != NULL && !S_IS_DEFINED (sym)) |
10764 | { | |
10765 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
10766 | return; | |
10767 | } | |
43cd72b9 | 10768 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
10769 | if (sym != NULL && !S_IS_DEFINED (sym)) |
10770 | { | |
10771 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
10772 | return; | |
10773 | } | |
10774 | } | |
10775 | ||
43cd72b9 BW |
10776 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
10777 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 10778 | |
43cd72b9 | 10779 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
10780 | { |
10781 | /* Add an expansion note on the expanded instruction. */ | |
10782 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 10783 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 10784 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
10785 | } |
10786 | } | |
10787 | ||
10788 | ||
10789 | /* Add a new fix expression into the desired segment. We have to | |
10790 | switch to that segment to do this. */ | |
10791 | ||
10792 | static fixS * | |
7fa3d080 BW |
10793 | fix_new_exp_in_seg (segT new_seg, |
10794 | subsegT new_subseg, | |
10795 | fragS *frag, | |
10796 | int where, | |
10797 | int size, | |
10798 | expressionS *exp, | |
10799 | int pcrel, | |
10800 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
10801 | { |
10802 | fixS *new_fix; | |
10803 | segT seg = now_seg; | |
10804 | subsegT subseg = now_subseg; | |
43cd72b9 | 10805 | |
9c2799c2 | 10806 | gas_assert (new_seg != 0); |
e0001a05 NC |
10807 | subseg_set (new_seg, new_subseg); |
10808 | ||
e0001a05 NC |
10809 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
10810 | subseg_set (seg, subseg); | |
10811 | return new_fix; | |
10812 | } | |
10813 | ||
10814 | ||
43cd72b9 BW |
10815 | /* Relax a loop instruction so that it can span loop >256 bytes. |
10816 | ||
10817 | loop as, .L1 | |
10818 | .L0: | |
10819 | rsr as, LEND | |
10820 | wsr as, LBEG | |
10821 | addi as, as, lo8 (label-.L1) | |
10822 | addmi as, as, mid8 (label-.L1) | |
10823 | wsr as, LEND | |
10824 | isync | |
10825 | rsr as, LCOUNT | |
10826 | addi as, as, 1 | |
10827 | .L1: | |
10828 | <<body>> | |
10829 | label: | |
10830 | */ | |
e0001a05 NC |
10831 | |
10832 | static void | |
7fa3d080 | 10833 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
10834 | { |
10835 | TInsn loop_insn; | |
10836 | TInsn addi_insn; | |
10837 | TInsn addmi_insn; | |
10838 | unsigned long target; | |
10839 | static xtensa_insnbuf insnbuf = NULL; | |
10840 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
10841 | xtensa_isa isa = xtensa_default_isa; | |
10842 | addressT loop_offset; | |
10843 | addressT addi_offset = 9; | |
10844 | addressT addmi_offset = 12; | |
43cd72b9 | 10845 | fragS *next_fragP; |
d77b99c9 | 10846 | int target_count; |
e0001a05 NC |
10847 | |
10848 | if (!insnbuf) | |
10849 | insnbuf = xtensa_insnbuf_alloc (isa); | |
10850 | ||
10851 | /* Get the loop offset. */ | |
43cd72b9 | 10852 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 10853 | |
43cd72b9 BW |
10854 | /* Validate that there really is a LOOP at the loop_offset. Because |
10855 | loops are not bundleable, we can assume that the instruction will be | |
10856 | in slot 0. */ | |
10857 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
10858 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
10859 | ||
9c2799c2 | 10860 | gas_assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); |
e0001a05 NC |
10861 | addi_offset += loop_offset; |
10862 | addmi_offset += loop_offset; | |
10863 | ||
9c2799c2 | 10864 | gas_assert (tinsn->ntok == 2); |
b08b5071 BW |
10865 | if (tinsn->tok[1].X_op == O_constant) |
10866 | target = tinsn->tok[1].X_add_number; | |
10867 | else if (tinsn->tok[1].X_op == O_symbol) | |
10868 | { | |
10869 | /* Find the fragment. */ | |
10870 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9c2799c2 | 10871 | gas_assert (S_GET_SEGMENT (sym) == segP |
b08b5071 BW |
10872 | || S_GET_SEGMENT (sym) == absolute_section); |
10873 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
10874 | } | |
10875 | else | |
10876 | { | |
10877 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
10878 | target = 0; | |
10879 | } | |
e0001a05 | 10880 | |
e0001a05 NC |
10881 | loop_length = target - (fragP->fr_address + fragP->fr_fix); |
10882 | loop_length_hi = loop_length & ~0x0ff; | |
10883 | loop_length_lo = loop_length & 0x0ff; | |
10884 | if (loop_length_lo >= 128) | |
10885 | { | |
10886 | loop_length_lo -= 256; | |
10887 | loop_length_hi += 256; | |
10888 | } | |
10889 | ||
43cd72b9 | 10890 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
10891 | 32512. If the loop is larger than that, then we just fail. */ |
10892 | if (loop_length_hi > 32512) | |
10893 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10894 | _("loop too long for LOOP instruction")); | |
10895 | ||
43cd72b9 | 10896 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
9c2799c2 | 10897 | gas_assert (addi_insn.opcode == xtensa_addi_opcode); |
e0001a05 | 10898 | |
43cd72b9 | 10899 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
9c2799c2 | 10900 | gas_assert (addmi_insn.opcode == xtensa_addmi_opcode); |
e0001a05 NC |
10901 | |
10902 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
10903 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 10904 | |
e0001a05 | 10905 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
10906 | xtensa_insnbuf_to_chars |
10907 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
10908 | |
10909 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
10910 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
10911 | xtensa_insnbuf_to_chars |
10912 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
10913 | |
10914 | /* Walk through all of the frags from here to the loop end | |
10915 | and mark them as no_transform to keep them from being modified | |
10916 | by the linker. If we ever have a relocation for the | |
10917 | addi/addmi of the difference of two symbols we can remove this. */ | |
10918 | ||
10919 | target_count = 0; | |
10920 | for (next_fragP = fragP; next_fragP != NULL; | |
10921 | next_fragP = next_fragP->fr_next) | |
10922 | { | |
b08b5071 | 10923 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
10924 | if (next_fragP->tc_frag_data.is_loop_target) |
10925 | target_count++; | |
10926 | if (target_count == 2) | |
10927 | break; | |
10928 | } | |
e0001a05 NC |
10929 | } |
10930 | ||
b08b5071 BW |
10931 | \f |
10932 | /* A map that keeps information on a per-subsegment basis. This is | |
10933 | maintained during initial assembly, but is invalid once the | |
10934 | subsegments are smashed together. I.E., it cannot be used during | |
10935 | the relaxation. */ | |
e0001a05 | 10936 | |
b08b5071 | 10937 | typedef struct subseg_map_struct |
e0001a05 | 10938 | { |
b08b5071 BW |
10939 | /* the key */ |
10940 | segT seg; | |
10941 | subsegT subseg; | |
e0001a05 | 10942 | |
b08b5071 BW |
10943 | /* the data */ |
10944 | unsigned flags; | |
10945 | float total_freq; /* fall-through + branch target frequency */ | |
10946 | float target_freq; /* branch target frequency alone */ | |
10947 | ||
10948 | struct subseg_map_struct *next; | |
10949 | } subseg_map; | |
e0001a05 | 10950 | |
e0001a05 | 10951 | |
e0001a05 NC |
10952 | static subseg_map *sseg_map = NULL; |
10953 | ||
43cd72b9 | 10954 | static subseg_map * |
7fa3d080 | 10955 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
10956 | { |
10957 | subseg_map *subseg_e; | |
10958 | ||
10959 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 10960 | { |
43cd72b9 | 10961 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 10962 | break; |
e0001a05 | 10963 | } |
b08b5071 BW |
10964 | return subseg_e; |
10965 | } | |
10966 | ||
10967 | ||
10968 | static subseg_map * | |
10969 | add_subseg_info (segT seg, subsegT subseg) | |
10970 | { | |
325801bd | 10971 | subseg_map *subseg_e = XNEW (subseg_map); |
43cd72b9 BW |
10972 | memset (subseg_e, 0, sizeof (subseg_map)); |
10973 | subseg_e->seg = seg; | |
10974 | subseg_e->subseg = subseg; | |
10975 | subseg_e->flags = 0; | |
10976 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
10977 | subseg_e->target_freq = 1.0; |
10978 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
10979 | subseg_e->next = sseg_map; |
10980 | sseg_map = subseg_e; | |
43cd72b9 BW |
10981 | return subseg_e; |
10982 | } | |
e0001a05 | 10983 | |
7fa3d080 BW |
10984 | |
10985 | static unsigned | |
10986 | get_last_insn_flags (segT seg, subsegT subseg) | |
10987 | { | |
10988 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
10989 | if (subseg_e) |
10990 | return subseg_e->flags; | |
10991 | return 0; | |
7fa3d080 BW |
10992 | } |
10993 | ||
10994 | ||
43cd72b9 | 10995 | static void |
7fa3d080 BW |
10996 | set_last_insn_flags (segT seg, |
10997 | subsegT subseg, | |
10998 | unsigned fl, | |
10999 | bfd_boolean val) | |
43cd72b9 BW |
11000 | { |
11001 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
11002 | if (! subseg_e) |
11003 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
11004 | if (val) |
11005 | subseg_e->flags |= fl; | |
11006 | else | |
11007 | subseg_e->flags &= ~fl; | |
11008 | } | |
11009 | ||
b08b5071 BW |
11010 | |
11011 | static float | |
11012 | get_subseg_total_freq (segT seg, subsegT subseg) | |
11013 | { | |
11014 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
11015 | if (subseg_e) | |
11016 | return subseg_e->total_freq; | |
11017 | return 1.0; | |
11018 | } | |
11019 | ||
11020 | ||
11021 | static float | |
11022 | get_subseg_target_freq (segT seg, subsegT subseg) | |
11023 | { | |
11024 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
11025 | if (subseg_e) | |
11026 | return subseg_e->target_freq; | |
11027 | return 1.0; | |
11028 | } | |
11029 | ||
11030 | ||
11031 | static void | |
11032 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
11033 | { | |
11034 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
11035 | if (! subseg_e) | |
11036 | subseg_e = add_subseg_info (seg, subseg); | |
11037 | subseg_e->total_freq = total_f; | |
11038 | subseg_e->target_freq = target_f; | |
11039 | } | |
11040 | ||
e0001a05 NC |
11041 | \f |
11042 | /* Segment Lists and emit_state Stuff. */ | |
11043 | ||
e0001a05 | 11044 | static void |
7fa3d080 | 11045 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
11046 | { |
11047 | head = head->next; | |
11048 | while (head) | |
11049 | { | |
11050 | segT literal_section = head->seg; | |
11051 | ||
11052 | /* Move the literal section to the front of the section list. */ | |
9c2799c2 | 11053 | gas_assert (literal_section); |
69852798 AM |
11054 | if (literal_section != stdoutput->sections) |
11055 | { | |
11056 | bfd_section_list_remove (stdoutput, literal_section); | |
11057 | bfd_section_list_prepend (stdoutput, literal_section); | |
11058 | } | |
e0001a05 NC |
11059 | head = head->next; |
11060 | } | |
11061 | } | |
11062 | ||
11063 | ||
7fa3d080 BW |
11064 | static void mark_literal_frags (seg_list *); |
11065 | ||
947fa914 MF |
11066 | static void |
11067 | xg_promote_candidate_litpool (struct litpool_seg *lps, | |
11068 | struct litpool_frag *lp) | |
11069 | { | |
11070 | fragS *poolbeg; | |
11071 | fragS *poolend; | |
11072 | symbolS *lsym; | |
11073 | char label[10 + 2 * sizeof (fragS *)]; | |
11074 | ||
11075 | poolbeg = lp->fragP; | |
11076 | lp->priority = 1; | |
11077 | poolbeg->fr_subtype = RELAX_LITERAL_POOL_BEGIN; | |
11078 | poolend = poolbeg->fr_next; | |
11079 | gas_assert (poolend->fr_type == rs_machine_dependent && | |
11080 | poolend->fr_subtype == RELAX_LITERAL_POOL_END); | |
11081 | /* Create a local symbol pointing to the | |
11082 | end of the pool. */ | |
11083 | sprintf (label, ".L0_LT_%p", poolbeg); | |
11084 | lsym = (symbolS *)local_symbol_make (label, lps->seg, | |
11085 | 0, poolend); | |
11086 | poolbeg->fr_symbol = lsym; | |
11087 | /* Rest is done in xtensa_relax_frag. */ | |
11088 | } | |
11089 | ||
7fa3d080 BW |
11090 | static void |
11091 | xtensa_move_literals (void) | |
e0001a05 NC |
11092 | { |
11093 | seg_list *segment; | |
11094 | frchainS *frchain_from, *frchain_to; | |
87975d2a | 11095 | fragS *search_frag, *next_frag, *literal_pool, *insert_after; |
e0001a05 NC |
11096 | fragS **frag_splice; |
11097 | emit_state state; | |
11098 | segT dest_seg; | |
11099 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 11100 | sym_list *lit; |
b46824bd | 11101 | struct litpool_seg *lps; |
4111950f MF |
11102 | const char *init_name = INIT_SECTION_NAME; |
11103 | const char *fini_name = FINI_SECTION_NAME; | |
11104 | int init_name_len = strlen(init_name); | |
11105 | int fini_name_len = strlen(fini_name); | |
e0001a05 | 11106 | |
a7877748 | 11107 | mark_literal_frags (literal_head->next); |
e0001a05 NC |
11108 | |
11109 | if (use_literal_section) | |
11110 | return; | |
11111 | ||
b46824bd MF |
11112 | /* Assign addresses (rough estimates) to the potential literal pool locations |
11113 | and create new ones if the gaps are too large. */ | |
11114 | ||
11115 | for (lps = litpool_seg_list.next; lps; lps = lps->next) | |
11116 | { | |
11117 | frchainS *frchP = seg_info (lps->seg)->frchainP; | |
11118 | struct litpool_frag *lpf = lps->frag_list.next; | |
11119 | addressT addr = 0; | |
11120 | ||
11121 | for ( ; frchP; frchP = frchP->frch_next) | |
11122 | { | |
11123 | fragS *fragP; | |
11124 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
11125 | { | |
11126 | if (lpf && fragP == lpf->fragP) | |
11127 | { | |
11128 | gas_assert(fragP->fr_type == rs_machine_dependent && | |
11129 | (fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN || | |
11130 | fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)); | |
11131 | /* Found a litpool location. */ | |
11132 | lpf->addr = addr; | |
11133 | lpf = lpf->next; | |
11134 | } | |
11135 | if (fragP->fr_type == rs_machine_dependent && | |
11136 | fragP->fr_subtype == RELAX_SLOTS) | |
11137 | { | |
11138 | int slot; | |
11139 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
11140 | { | |
11141 | if (fragP->tc_frag_data.literal_frags[slot]) | |
11142 | { | |
11143 | /* L32R; point its literal to the nearest litpool | |
11144 | preferring non-"candidate" positions to avoid | |
11145 | the jump-around. */ | |
11146 | fragS *litfrag = fragP->tc_frag_data.literal_frags[slot]; | |
11147 | struct litpool_frag *lp = lpf->prev; | |
11148 | if (!lp->fragP) | |
11149 | { | |
11150 | break; | |
11151 | } | |
11152 | while (lp->fragP->fr_subtype == | |
11153 | RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
11154 | { | |
11155 | lp = lp->prev; | |
11156 | if (lp->fragP == NULL) | |
11157 | { | |
11158 | /* End of list; have to bite the bullet. | |
11159 | Take the nearest. */ | |
11160 | lp = lpf->prev; | |
11161 | break; | |
11162 | } | |
11163 | /* Does it (conservatively) reach? */ | |
11164 | if (addr - lp->addr <= 128 * 1024) | |
11165 | { | |
11166 | if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN) | |
11167 | { | |
11168 | /* Found a good one. */ | |
11169 | break; | |
11170 | } | |
11171 | else if (lp->prev->fragP && | |
11172 | addr - lp->prev->addr > 128 * 1024) | |
11173 | { | |
11174 | /* This is still a "candidate" but the next one | |
11175 | will be too far away, so revert to the nearest | |
11176 | one, convert it and add the jump around. */ | |
b46824bd | 11177 | lp = lpf->prev; |
947fa914 | 11178 | break; |
b46824bd MF |
11179 | } |
11180 | } | |
11181 | } | |
947fa914 MF |
11182 | |
11183 | /* Convert candidate and add the jump around. */ | |
11184 | if (lp->fragP->fr_subtype == | |
11185 | RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
11186 | xg_promote_candidate_litpool (lps, lp); | |
11187 | ||
b46824bd MF |
11188 | if (! litfrag->tc_frag_data.literal_frag) |
11189 | { | |
11190 | /* Take earliest use of this literal to avoid | |
11191 | forward refs. */ | |
11192 | litfrag->tc_frag_data.literal_frag = lp->fragP; | |
11193 | } | |
11194 | } | |
11195 | } | |
11196 | } | |
11197 | addr += fragP->fr_fix; | |
11198 | if (fragP->fr_type == rs_fill) | |
11199 | addr += fragP->fr_offset; | |
11200 | } | |
11201 | } | |
11202 | } | |
11203 | ||
74869ac7 | 11204 | for (segment = literal_head->next; segment; segment = segment->next) |
e0001a05 | 11205 | { |
4111950f MF |
11206 | const char *seg_name = segment_name (segment->seg); |
11207 | ||
74869ac7 | 11208 | /* Keep the literals for .init and .fini in separate sections. */ |
4111950f MF |
11209 | if ((!memcmp (seg_name, init_name, init_name_len) && |
11210 | !strcmp (seg_name + init_name_len, ".literal")) || | |
11211 | (!memcmp (seg_name, fini_name, fini_name_len) && | |
11212 | !strcmp (seg_name + fini_name_len, ".literal"))) | |
74869ac7 BW |
11213 | continue; |
11214 | ||
e0001a05 NC |
11215 | frchain_from = seg_info (segment->seg)->frchainP; |
11216 | search_frag = frchain_from->frch_root; | |
11217 | literal_pool = NULL; | |
11218 | frchain_to = NULL; | |
11219 | frag_splice = &(frchain_from->frch_root); | |
11220 | ||
4de0562a | 11221 | while (search_frag && !search_frag->tc_frag_data.literal_frag) |
e0001a05 | 11222 | { |
9c2799c2 | 11223 | gas_assert (search_frag->fr_fix == 0 |
e0001a05 NC |
11224 | || search_frag->fr_type == rs_align); |
11225 | search_frag = search_frag->fr_next; | |
11226 | } | |
11227 | ||
4de0562a MF |
11228 | if (!search_frag) |
11229 | { | |
11230 | search_frag = frchain_from->frch_root; | |
11231 | as_bad_where (search_frag->fr_file, search_frag->fr_line, | |
11232 | _("literal pool location required for text-section-literals; specify with .literal_position")); | |
11233 | continue; | |
11234 | } | |
11235 | ||
9c2799c2 | 11236 | gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype |
e0001a05 NC |
11237 | == RELAX_LITERAL_POOL_BEGIN); |
11238 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
11239 | ||
11240 | /* Make sure that all the frags in this series are closed, and | |
11241 | that there is at least one left over of zero-size. This | |
11242 | prevents us from making a segment with an frchain without any | |
11243 | frags in it. */ | |
11244 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11245 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11246 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); |
43cd72b9 | 11247 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11248 | |
43cd72b9 | 11249 | while (search_frag != frag_now) |
e0001a05 NC |
11250 | { |
11251 | next_frag = search_frag->fr_next; | |
e0001a05 NC |
11252 | if (search_frag->tc_frag_data.literal_frag) |
11253 | { | |
11254 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9c2799c2 | 11255 | gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); |
dd49a749 | 11256 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9c2799c2 | 11257 | gas_assert (frchain_to); |
e0001a05 | 11258 | } |
b46824bd MF |
11259 | |
11260 | if (search_frag->fr_type == rs_fill && search_frag->fr_fix == 0) | |
11261 | { | |
11262 | /* Skip empty fill frags. */ | |
11263 | *frag_splice = next_frag; | |
11264 | search_frag = next_frag; | |
11265 | continue; | |
11266 | } | |
11267 | ||
11268 | if (search_frag->fr_type == rs_align) | |
11269 | { | |
11270 | /* Skip alignment frags, because the pool as a whole will be | |
11271 | aligned if used, and we don't want to force alignment if the | |
11272 | pool is unused. */ | |
11273 | *frag_splice = next_frag; | |
11274 | search_frag = next_frag; | |
11275 | continue; | |
11276 | } | |
11277 | ||
11278 | /* First, move the frag out of the literal section and | |
11279 | to the appropriate place. */ | |
11280 | ||
33eaf5de | 11281 | /* Insert an alignment frag at start of pool. */ |
b46824bd MF |
11282 | if (literal_pool->fr_next->fr_type == rs_machine_dependent && |
11283 | literal_pool->fr_next->fr_subtype == RELAX_LITERAL_POOL_END) | |
11284 | { | |
11285 | segT pool_seg = literal_pool->fr_next->tc_frag_data.lit_seg; | |
11286 | emit_state prev_state; | |
11287 | fragS *prev_frag; | |
11288 | fragS *align_frag; | |
11289 | xtensa_switch_section_emit_state (&prev_state, pool_seg, 0); | |
11290 | prev_frag = frag_now; | |
11291 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
11292 | align_frag = frag_now; | |
11293 | frag_align (2, 0, 0); | |
11294 | /* Splice it into the right place. */ | |
11295 | prev_frag->fr_next = align_frag->fr_next; | |
11296 | align_frag->fr_next = literal_pool->fr_next; | |
11297 | literal_pool->fr_next = align_frag; | |
11298 | /* Insert after this one. */ | |
11299 | literal_pool->tc_frag_data.literal_frag = align_frag; | |
11300 | xtensa_restore_emit_state (&prev_state); | |
11301 | } | |
c48aaca0 | 11302 | insert_after = literal_pool->tc_frag_data.literal_frag; |
dd49a749 | 11303 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
b46824bd MF |
11304 | /* Skip align frag. */ |
11305 | if (insert_after->fr_next->fr_type == rs_align) | |
11306 | { | |
11307 | insert_after = insert_after->fr_next; | |
11308 | } | |
43cd72b9 | 11309 | |
e0001a05 NC |
11310 | *frag_splice = next_frag; |
11311 | search_frag->fr_next = insert_after->fr_next; | |
11312 | insert_after->fr_next = search_frag; | |
11313 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
c48aaca0 | 11314 | literal_pool->tc_frag_data.literal_frag = search_frag; |
e0001a05 NC |
11315 | |
11316 | /* Now move any fixups associated with this frag to the | |
11317 | right section. */ | |
11318 | fix = frchain_from->fix_root; | |
11319 | fix_splice = &(frchain_from->fix_root); | |
11320 | while (fix) | |
11321 | { | |
11322 | next_fix = fix->fx_next; | |
11323 | if (fix->fx_frag == search_frag) | |
11324 | { | |
11325 | *fix_splice = next_fix; | |
11326 | fix->fx_next = frchain_to->fix_root; | |
11327 | frchain_to->fix_root = fix; | |
11328 | if (frchain_to->fix_tail == NULL) | |
11329 | frchain_to->fix_tail = fix; | |
11330 | } | |
11331 | else | |
11332 | fix_splice = &(fix->fx_next); | |
11333 | fix = next_fix; | |
11334 | } | |
11335 | search_frag = next_frag; | |
11336 | } | |
11337 | ||
11338 | if (frchain_from->fix_root != NULL) | |
11339 | { | |
11340 | frchain_from = seg_info (segment->seg)->frchainP; | |
11341 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
11342 | ||
9c2799c2 | 11343 | gas_assert (frchain_from->fix_root == NULL); |
e0001a05 NC |
11344 | } |
11345 | frchain_from->fix_tail = NULL; | |
11346 | xtensa_restore_emit_state (&state); | |
e0001a05 NC |
11347 | } |
11348 | ||
82e7541d BW |
11349 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
11350 | for (lit = literal_syms; lit; lit = lit->next) | |
11351 | { | |
11352 | symbolS *lit_sym = lit->sym; | |
91d6fa6a NC |
11353 | segT dseg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; |
11354 | if (dseg) | |
11355 | S_SET_SEGMENT (lit_sym, dseg); | |
82e7541d | 11356 | } |
e0001a05 NC |
11357 | } |
11358 | ||
11359 | ||
a7877748 BW |
11360 | /* Walk over all the frags for segments in a list and mark them as |
11361 | containing literals. As clunky as this is, we can't rely on frag_var | |
11362 | and frag_variant to get called in all situations. */ | |
11363 | ||
11364 | static void | |
7fa3d080 | 11365 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
11366 | { |
11367 | frchainS *frchain_from; | |
11368 | fragS *search_frag; | |
11369 | ||
11370 | while (segment) | |
11371 | { | |
11372 | frchain_from = seg_info (segment->seg)->frchainP; | |
11373 | search_frag = frchain_from->frch_root; | |
c138bc38 | 11374 | while (search_frag) |
a7877748 BW |
11375 | { |
11376 | search_frag->tc_frag_data.is_literal = TRUE; | |
11377 | search_frag = search_frag->fr_next; | |
11378 | } | |
11379 | segment = segment->next; | |
11380 | } | |
11381 | } | |
11382 | ||
11383 | ||
e0001a05 | 11384 | static void |
7fa3d080 | 11385 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
11386 | { |
11387 | /* Move all of the sections in the section list to come | |
11388 | after "after" in the gnu segment list. */ | |
11389 | ||
11390 | head = head->next; | |
11391 | while (head) | |
11392 | { | |
11393 | segT literal_section = head->seg; | |
11394 | ||
11395 | /* Move the literal section after "after". */ | |
9c2799c2 | 11396 | gas_assert (literal_section); |
e0001a05 NC |
11397 | if (literal_section != after) |
11398 | { | |
69852798 AM |
11399 | bfd_section_list_remove (stdoutput, literal_section); |
11400 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
11401 | } |
11402 | ||
11403 | head = head->next; | |
11404 | } | |
11405 | } | |
11406 | ||
11407 | ||
11408 | /* Push all the literal segments to the end of the gnu list. */ | |
11409 | ||
7fa3d080 BW |
11410 | static void |
11411 | xtensa_reorder_segments (void) | |
e0001a05 NC |
11412 | { |
11413 | segT sec; | |
b08b5071 | 11414 | segT last_sec = 0; |
e0001a05 NC |
11415 | int old_count = 0; |
11416 | int new_count = 0; | |
11417 | ||
11418 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
11419 | { |
11420 | last_sec = sec; | |
11421 | old_count++; | |
11422 | } | |
e0001a05 NC |
11423 | |
11424 | /* Now that we have the last section, push all the literal | |
11425 | sections to the end. */ | |
e0001a05 | 11426 | xtensa_reorder_seg_list (literal_head, last_sec); |
e0001a05 NC |
11427 | |
11428 | /* Now perform the final error check. */ | |
11429 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
11430 | new_count++; | |
9c2799c2 | 11431 | gas_assert (new_count == old_count); |
e0001a05 NC |
11432 | } |
11433 | ||
11434 | ||
e0001a05 NC |
11435 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
11436 | correct location. Return a emit_state which can be passed to | |
11437 | xtensa_restore_emit_state to return to current fragment. */ | |
11438 | ||
7fa3d080 BW |
11439 | static void |
11440 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
11441 | { |
11442 | if (directive_state[directive_absolute_literals]) | |
11443 | { | |
74869ac7 BW |
11444 | segT lit4_seg = cache_literal_section (TRUE); |
11445 | xtensa_switch_section_emit_state (result, lit4_seg, 0); | |
43cd72b9 BW |
11446 | } |
11447 | else | |
11448 | xtensa_switch_to_non_abs_literal_fragment (result); | |
11449 | ||
11450 | /* Do a 4-byte align here. */ | |
11451 | frag_align (2, 0, 0); | |
11452 | record_alignment (now_seg, 2); | |
11453 | } | |
11454 | ||
11455 | ||
7fa3d080 BW |
11456 | static void |
11457 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 | 11458 | { |
e0001a05 | 11459 | fragS *pool_location = get_literal_pool_location (now_seg); |
74869ac7 | 11460 | segT lit_seg; |
c138bc38 | 11461 | bfd_boolean is_init = |
e0001a05 | 11462 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); |
c138bc38 | 11463 | bfd_boolean is_fini = |
e0001a05 | 11464 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); |
e0001a05 | 11465 | |
43cd72b9 BW |
11466 | if (pool_location == NULL |
11467 | && !use_literal_section | |
e0001a05 NC |
11468 | && !is_init && ! is_fini) |
11469 | { | |
b46824bd MF |
11470 | if (!auto_litpools) |
11471 | { | |
11472 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); | |
11473 | } | |
947fa914 MF |
11474 | xtensa_maybe_create_literal_pool_frag (TRUE, TRUE); |
11475 | pool_location = get_literal_pool_location (now_seg); | |
e0001a05 NC |
11476 | } |
11477 | ||
74869ac7 BW |
11478 | lit_seg = cache_literal_section (FALSE); |
11479 | xtensa_switch_section_emit_state (result, lit_seg, 0); | |
e0001a05 | 11480 | |
43cd72b9 BW |
11481 | if (!use_literal_section |
11482 | && !is_init && !is_fini | |
11483 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
11484 | { |
11485 | /* Close whatever frag is there. */ | |
11486 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11487 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
11488 | frag_now->tc_frag_data.literal_frag = pool_location; |
11489 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11490 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11491 | } |
e0001a05 NC |
11492 | } |
11493 | ||
11494 | ||
11495 | /* Call this function before emitting data into the literal section. | |
11496 | This is a helper function for xtensa_switch_to_literal_fragment. | |
11497 | This is similar to a .section new_now_seg subseg. */ | |
11498 | ||
7fa3d080 BW |
11499 | static void |
11500 | xtensa_switch_section_emit_state (emit_state *state, | |
11501 | segT new_now_seg, | |
11502 | subsegT new_now_subseg) | |
e0001a05 NC |
11503 | { |
11504 | state->name = now_seg->name; | |
11505 | state->now_seg = now_seg; | |
11506 | state->now_subseg = now_subseg; | |
11507 | state->generating_literals = generating_literals; | |
11508 | generating_literals++; | |
2b0210eb | 11509 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
11510 | } |
11511 | ||
11512 | ||
11513 | /* Use to restore the emitting into the normal place. */ | |
11514 | ||
7fa3d080 BW |
11515 | static void |
11516 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
11517 | { |
11518 | generating_literals = state->generating_literals; | |
2b0210eb | 11519 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
11520 | } |
11521 | ||
11522 | ||
74869ac7 | 11523 | /* Predicate function used to look up a section in a particular group. */ |
e0001a05 | 11524 | |
74869ac7 BW |
11525 | static bfd_boolean |
11526 | match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) | |
e0001a05 | 11527 | { |
74869ac7 BW |
11528 | const char *gname = inf; |
11529 | const char *group_name = elf_group_name (sec); | |
3739860c | 11530 | |
74869ac7 BW |
11531 | return (group_name == gname |
11532 | || (group_name != NULL | |
11533 | && gname != NULL | |
11534 | && strcmp (group_name, gname) == 0)); | |
11535 | } | |
e0001a05 | 11536 | |
e0001a05 | 11537 | |
74869ac7 BW |
11538 | /* Get the literal section to be used for the current text section. |
11539 | The result may be cached in the default_lit_sections structure. */ | |
11540 | ||
11541 | static segT | |
11542 | cache_literal_section (bfd_boolean use_abs_literals) | |
11543 | { | |
11544 | const char *text_name, *group_name = 0; | |
b9bb4a93 TS |
11545 | const char *base_name, *suffix; |
11546 | char *name; | |
74869ac7 BW |
11547 | segT *pcached; |
11548 | segT seg, current_section; | |
11549 | int current_subsec; | |
11550 | bfd_boolean linkonce = FALSE; | |
11551 | ||
11552 | /* Save the current section/subsection. */ | |
11553 | current_section = now_seg; | |
11554 | current_subsec = now_subseg; | |
11555 | ||
11556 | /* Clear the cached values if they are no longer valid. */ | |
11557 | if (now_seg != default_lit_sections.current_text_seg) | |
b08b5071 | 11558 | { |
74869ac7 BW |
11559 | default_lit_sections.current_text_seg = now_seg; |
11560 | default_lit_sections.lit_seg = NULL; | |
11561 | default_lit_sections.lit4_seg = NULL; | |
11562 | } | |
11563 | ||
11564 | /* Check if the literal section is already cached. */ | |
11565 | if (use_abs_literals) | |
11566 | pcached = &default_lit_sections.lit4_seg; | |
11567 | else | |
11568 | pcached = &default_lit_sections.lit_seg; | |
11569 | ||
11570 | if (*pcached) | |
11571 | return *pcached; | |
3739860c | 11572 | |
74869ac7 BW |
11573 | text_name = default_lit_sections.lit_prefix; |
11574 | if (! text_name || ! *text_name) | |
11575 | { | |
11576 | text_name = segment_name (current_section); | |
11577 | group_name = elf_group_name (current_section); | |
11578 | linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; | |
11579 | } | |
11580 | ||
11581 | base_name = use_abs_literals ? ".lit4" : ".literal"; | |
11582 | if (group_name) | |
11583 | { | |
4ec9d7d5 | 11584 | name = concat (base_name, ".", group_name, (char *) NULL); |
74869ac7 BW |
11585 | } |
11586 | else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) | |
11587 | { | |
11588 | suffix = strchr (text_name + linkonce_len, '.'); | |
11589 | ||
4ec9d7d5 TS |
11590 | name = concat (".gnu.linkonce", base_name, suffix ? suffix : "", |
11591 | (char *) NULL); | |
74869ac7 BW |
11592 | linkonce = TRUE; |
11593 | } | |
11594 | else | |
11595 | { | |
a89c407e SA |
11596 | /* If the section name begins or ends with ".text", then replace |
11597 | that portion instead of appending an additional suffix. */ | |
74869ac7 | 11598 | size_t len = strlen (text_name); |
a89c407e SA |
11599 | if (len >= 5 |
11600 | && (strcmp (text_name + len - 5, ".text") == 0 | |
11601 | || strncmp (text_name, ".text", 5) == 0)) | |
74869ac7 BW |
11602 | len -= 5; |
11603 | ||
add39d23 | 11604 | name = XNEWVEC (char, len + strlen (base_name) + 1); |
a89c407e SA |
11605 | if (strncmp (text_name, ".text", 5) == 0) |
11606 | { | |
11607 | strcpy (name, base_name); | |
11608 | strcat (name, text_name + 5); | |
11609 | } | |
11610 | else | |
11611 | { | |
11612 | strcpy (name, text_name); | |
11613 | strcpy (name + len, base_name); | |
11614 | } | |
b08b5071 | 11615 | } |
e0001a05 | 11616 | |
74869ac7 BW |
11617 | /* Canonicalize section names to allow renaming literal sections. |
11618 | The group name, if any, came from the current text section and | |
11619 | has already been canonicalized. */ | |
11620 | name = tc_canonicalize_symbol_name (name); | |
11621 | ||
11622 | seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, | |
11623 | (void *) group_name); | |
11624 | if (! seg) | |
e0001a05 | 11625 | { |
74869ac7 BW |
11626 | flagword flags; |
11627 | ||
11628 | seg = subseg_force_new (name, 0); | |
11629 | ||
11630 | if (! use_abs_literals) | |
b08b5071 | 11631 | { |
74869ac7 | 11632 | /* Add the newly created literal segment to the list. */ |
325801bd | 11633 | seg_list *n = XNEW (seg_list); |
b08b5071 | 11634 | n->seg = seg; |
74869ac7 BW |
11635 | n->next = literal_head->next; |
11636 | literal_head->next = n; | |
b08b5071 | 11637 | } |
74869ac7 BW |
11638 | |
11639 | flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD | |
11640 | | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) | |
11641 | | (use_abs_literals ? SEC_DATA : SEC_CODE)); | |
11642 | ||
11643 | elf_group_name (seg) = group_name; | |
11644 | ||
11645 | bfd_set_section_flags (stdoutput, seg, flags); | |
b08b5071 | 11646 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
11647 | } |
11648 | ||
74869ac7 | 11649 | *pcached = seg; |
b08b5071 | 11650 | subseg_set (current_section, current_subsec); |
74869ac7 | 11651 | return seg; |
e0001a05 NC |
11652 | } |
11653 | ||
43cd72b9 BW |
11654 | \f |
11655 | /* Property Tables Stuff. */ | |
11656 | ||
7fa3d080 BW |
11657 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
11658 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
11659 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
11660 | ||
11661 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
11662 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
11663 | ||
b08b5071 | 11664 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
11665 | static void xtensa_create_property_segments |
11666 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
11667 | static void xtensa_create_xproperty_segments | |
11668 | (frag_flags_fn, const char *, xt_section_type); | |
532f93bd | 11669 | static bfd_boolean exclude_section_from_property_tables (segT); |
7fa3d080 BW |
11670 | static bfd_boolean section_has_property (segT, frag_predicate); |
11671 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
11672 | static void add_xt_block_frags | |
542f8b94 | 11673 | (segT, xtensa_block_info **, frag_predicate, frag_predicate); |
7fa3d080 BW |
11674 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); |
11675 | static void xtensa_frag_flags_init (frag_flags *); | |
11676 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
2f1bf5c1 | 11677 | static flagword frag_flags_to_number (const frag_flags *); |
542f8b94 | 11678 | static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn); |
7fa3d080 BW |
11679 | |
11680 | /* Set up property tables after relaxation. */ | |
11681 | ||
11682 | void | |
11683 | xtensa_post_relax_hook (void) | |
11684 | { | |
11685 | xtensa_move_seg_list_to_beginning (literal_head); | |
7fa3d080 BW |
11686 | |
11687 | xtensa_find_unmarked_state_frags (); | |
99ded152 | 11688 | xtensa_mark_frags_for_org (); |
6a7eedfe | 11689 | xtensa_mark_difference_of_two_symbols (); |
7fa3d080 | 11690 | |
b29757dc BW |
11691 | xtensa_create_property_segments (get_frag_is_literal, |
11692 | NULL, | |
11693 | XTENSA_LIT_SEC_NAME, | |
11694 | xt_literal_sec); | |
7fa3d080 BW |
11695 | xtensa_create_xproperty_segments (get_frag_property_flags, |
11696 | XTENSA_PROP_SEC_NAME, | |
11697 | xt_prop_sec); | |
11698 | ||
11699 | if (warn_unaligned_branch_targets) | |
11700 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
11701 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
11702 | } | |
11703 | ||
11704 | ||
43cd72b9 BW |
11705 | /* This function is only meaningful after xtensa_move_literals. */ |
11706 | ||
11707 | static bfd_boolean | |
7fa3d080 | 11708 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 | 11709 | { |
9c2799c2 | 11710 | gas_assert (fragP != NULL); |
43cd72b9 BW |
11711 | return fragP->tc_frag_data.is_literal; |
11712 | } | |
11713 | ||
11714 | ||
43cd72b9 | 11715 | static void |
7fa3d080 BW |
11716 | xtensa_create_property_segments (frag_predicate property_function, |
11717 | frag_predicate end_property_function, | |
11718 | const char *section_name_base, | |
11719 | xt_section_type sec_type) | |
43cd72b9 BW |
11720 | { |
11721 | segT *seclist; | |
11722 | ||
11723 | /* Walk over all of the current segments. | |
11724 | Walk over each fragment | |
11725 | For each non-empty fragment, | |
11726 | Build a property record (append where possible). */ | |
11727 | ||
11728 | for (seclist = &stdoutput->sections; | |
11729 | seclist && *seclist; | |
11730 | seclist = &(*seclist)->next) | |
11731 | { | |
11732 | segT sec = *seclist; | |
43cd72b9 | 11733 | |
532f93bd | 11734 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
11735 | continue; |
11736 | ||
11737 | if (section_has_property (sec, property_function)) | |
11738 | { | |
542f8b94 BW |
11739 | segment_info_type *xt_seg_info; |
11740 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 11741 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
11742 | |
11743 | prop_sec->output_section = prop_sec; | |
11744 | subseg_set (prop_sec, 0); | |
11745 | xt_seg_info = seg_info (prop_sec); | |
11746 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
11747 | ||
43cd72b9 | 11748 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 11749 | add_xt_block_frags (sec, xt_blocks, property_function, |
43cd72b9 BW |
11750 | end_property_function); |
11751 | } | |
11752 | } | |
11753 | ||
11754 | /* Now we fill them out.... */ | |
11755 | ||
11756 | for (seclist = &stdoutput->sections; | |
11757 | seclist && *seclist; | |
11758 | seclist = &(*seclist)->next) | |
11759 | { | |
11760 | segment_info_type *seginfo; | |
11761 | xtensa_block_info *block; | |
11762 | segT sec = *seclist; | |
11763 | ||
11764 | seginfo = seg_info (sec); | |
11765 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
11766 | ||
11767 | if (block) | |
11768 | { | |
11769 | xtensa_block_info *cur_block; | |
43cd72b9 | 11770 | int num_recs = 0; |
d77b99c9 | 11771 | bfd_size_type rec_size; |
43cd72b9 BW |
11772 | |
11773 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
11774 | num_recs++; | |
11775 | ||
11776 | rec_size = num_recs * 8; | |
11777 | bfd_set_section_size (stdoutput, sec, rec_size); | |
11778 | ||
43cd72b9 BW |
11779 | if (num_recs) |
11780 | { | |
43cd72b9 | 11781 | char *frag_data; |
542f8b94 | 11782 | int i; |
43cd72b9 | 11783 | |
542f8b94 BW |
11784 | subseg_set (sec, 0); |
11785 | frag_data = frag_more (rec_size); | |
43cd72b9 | 11786 | cur_block = block; |
43cd72b9 BW |
11787 | for (i = 0; i < num_recs; i++) |
11788 | { | |
542f8b94 | 11789 | fixS *fix; |
e0001a05 | 11790 | |
43cd72b9 | 11791 | /* Write the fixup. */ |
9c2799c2 | 11792 | gas_assert (cur_block); |
542f8b94 BW |
11793 | fix = fix_new (frag_now, i * 8, 4, |
11794 | section_symbol (cur_block->sec), | |
11795 | cur_block->offset, | |
11796 | FALSE, BFD_RELOC_32); | |
11797 | fix->fx_file = "<internal>"; | |
43cd72b9 | 11798 | fix->fx_line = 0; |
e0001a05 | 11799 | |
43cd72b9 | 11800 | /* Write the length. */ |
542f8b94 | 11801 | md_number_to_chars (&frag_data[4 + i * 8], |
43cd72b9 BW |
11802 | cur_block->size, 4); |
11803 | cur_block = cur_block->next; | |
11804 | } | |
542f8b94 BW |
11805 | frag_wane (frag_now); |
11806 | frag_new (0); | |
11807 | frag_wane (frag_now); | |
43cd72b9 BW |
11808 | } |
11809 | } | |
11810 | } | |
e0001a05 NC |
11811 | } |
11812 | ||
11813 | ||
7fa3d080 BW |
11814 | static void |
11815 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
11816 | const char *section_name_base, | |
11817 | xt_section_type sec_type) | |
e0001a05 NC |
11818 | { |
11819 | segT *seclist; | |
11820 | ||
11821 | /* Walk over all of the current segments. | |
43cd72b9 BW |
11822 | Walk over each fragment. |
11823 | For each fragment that has instructions, | |
11824 | build an instruction record (append where possible). */ | |
e0001a05 NC |
11825 | |
11826 | for (seclist = &stdoutput->sections; | |
11827 | seclist && *seclist; | |
11828 | seclist = &(*seclist)->next) | |
11829 | { | |
11830 | segT sec = *seclist; | |
43cd72b9 | 11831 | |
532f93bd | 11832 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
11833 | continue; |
11834 | ||
11835 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 11836 | { |
542f8b94 BW |
11837 | segment_info_type *xt_seg_info; |
11838 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 11839 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
11840 | |
11841 | prop_sec->output_section = prop_sec; | |
11842 | subseg_set (prop_sec, 0); | |
11843 | xt_seg_info = seg_info (prop_sec); | |
11844 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
11845 | ||
e0001a05 | 11846 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 11847 | add_xt_prop_frags (sec, xt_blocks, flag_fn); |
e0001a05 NC |
11848 | } |
11849 | } | |
11850 | ||
11851 | /* Now we fill them out.... */ | |
11852 | ||
11853 | for (seclist = &stdoutput->sections; | |
11854 | seclist && *seclist; | |
11855 | seclist = &(*seclist)->next) | |
11856 | { | |
11857 | segment_info_type *seginfo; | |
11858 | xtensa_block_info *block; | |
11859 | segT sec = *seclist; | |
43cd72b9 | 11860 | |
e0001a05 NC |
11861 | seginfo = seg_info (sec); |
11862 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
11863 | ||
11864 | if (block) | |
11865 | { | |
11866 | xtensa_block_info *cur_block; | |
43cd72b9 | 11867 | int num_recs = 0; |
d77b99c9 | 11868 | bfd_size_type rec_size; |
e0001a05 NC |
11869 | |
11870 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
11871 | num_recs++; | |
11872 | ||
43cd72b9 | 11873 | rec_size = num_recs * (8 + 4); |
e0001a05 | 11874 | bfd_set_section_size (stdoutput, sec, rec_size); |
43cd72b9 BW |
11875 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
11876 | ||
e0001a05 NC |
11877 | if (num_recs) |
11878 | { | |
e0001a05 | 11879 | char *frag_data; |
542f8b94 | 11880 | int i; |
e0001a05 | 11881 | |
542f8b94 BW |
11882 | subseg_set (sec, 0); |
11883 | frag_data = frag_more (rec_size); | |
e0001a05 | 11884 | cur_block = block; |
e0001a05 NC |
11885 | for (i = 0; i < num_recs; i++) |
11886 | { | |
542f8b94 | 11887 | fixS *fix; |
e0001a05 NC |
11888 | |
11889 | /* Write the fixup. */ | |
9c2799c2 | 11890 | gas_assert (cur_block); |
542f8b94 BW |
11891 | fix = fix_new (frag_now, i * 12, 4, |
11892 | section_symbol (cur_block->sec), | |
11893 | cur_block->offset, | |
11894 | FALSE, BFD_RELOC_32); | |
11895 | fix->fx_file = "<internal>"; | |
e0001a05 NC |
11896 | fix->fx_line = 0; |
11897 | ||
11898 | /* Write the length. */ | |
542f8b94 | 11899 | md_number_to_chars (&frag_data[4 + i * 12], |
e0001a05 | 11900 | cur_block->size, 4); |
542f8b94 | 11901 | md_number_to_chars (&frag_data[8 + i * 12], |
43cd72b9 | 11902 | frag_flags_to_number (&cur_block->flags), |
2f1bf5c1 | 11903 | sizeof (flagword)); |
e0001a05 NC |
11904 | cur_block = cur_block->next; |
11905 | } | |
542f8b94 BW |
11906 | frag_wane (frag_now); |
11907 | frag_new (0); | |
11908 | frag_wane (frag_now); | |
e0001a05 NC |
11909 | } |
11910 | } | |
11911 | } | |
11912 | } | |
11913 | ||
11914 | ||
532f93bd BW |
11915 | static bfd_boolean |
11916 | exclude_section_from_property_tables (segT sec) | |
11917 | { | |
11918 | flagword flags = bfd_get_section_flags (stdoutput, sec); | |
11919 | ||
11920 | /* Sections that don't contribute to the memory footprint are excluded. */ | |
11921 | if ((flags & SEC_DEBUGGING) | |
11922 | || !(flags & SEC_ALLOC) | |
11923 | || (flags & SEC_MERGE)) | |
11924 | return TRUE; | |
11925 | ||
11926 | /* Linker cie and fde optimizations mess up property entries for | |
11927 | eh_frame sections, but there is nothing inside them relevant to | |
11928 | property tables anyway. */ | |
11929 | if (strcmp (sec->name, ".eh_frame") == 0) | |
11930 | return TRUE; | |
11931 | ||
11932 | return FALSE; | |
11933 | } | |
11934 | ||
11935 | ||
7fa3d080 BW |
11936 | static bfd_boolean |
11937 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
11938 | { |
11939 | segment_info_type *seginfo = seg_info (sec); | |
11940 | fragS *fragP; | |
11941 | ||
11942 | if (seginfo && seginfo->frchainP) | |
11943 | { | |
11944 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
11945 | { | |
11946 | if (property_function (fragP) | |
11947 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
11948 | return TRUE; | |
11949 | } | |
11950 | } | |
11951 | return FALSE; | |
11952 | } | |
11953 | ||
11954 | ||
7fa3d080 BW |
11955 | static bfd_boolean |
11956 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
11957 | { |
11958 | segment_info_type *seginfo = seg_info (sec); | |
11959 | fragS *fragP; | |
11960 | ||
11961 | if (seginfo && seginfo->frchainP) | |
11962 | { | |
11963 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
11964 | { | |
11965 | frag_flags prop_flags; | |
11966 | property_function (fragP, &prop_flags); | |
11967 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
11968 | return TRUE; | |
11969 | } | |
11970 | } | |
11971 | return FALSE; | |
11972 | } | |
11973 | ||
11974 | ||
e0001a05 NC |
11975 | /* Two types of block sections exist right now: literal and insns. */ |
11976 | ||
7fa3d080 BW |
11977 | static void |
11978 | add_xt_block_frags (segT sec, | |
7fa3d080 BW |
11979 | xtensa_block_info **xt_block, |
11980 | frag_predicate property_function, | |
11981 | frag_predicate end_property_function) | |
e0001a05 | 11982 | { |
e0001a05 NC |
11983 | fragS *fragP; |
11984 | ||
e0001a05 NC |
11985 | /* Build it if needed. */ |
11986 | while (*xt_block != NULL) | |
11987 | xt_block = &(*xt_block)->next; | |
11988 | /* We are either at NULL at the beginning or at the end. */ | |
11989 | ||
11990 | /* Walk through the frags. */ | |
542f8b94 | 11991 | if (seg_info (sec)->frchainP) |
e0001a05 | 11992 | { |
542f8b94 | 11993 | for (fragP = seg_info (sec)->frchainP->frch_root; |
e0001a05 NC |
11994 | fragP; |
11995 | fragP = fragP->fr_next) | |
11996 | { | |
11997 | if (property_function (fragP) | |
11998 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
11999 | { | |
12000 | if (*xt_block != NULL) | |
12001 | { | |
12002 | if ((*xt_block)->offset + (*xt_block)->size | |
12003 | == fragP->fr_address) | |
12004 | (*xt_block)->size += fragP->fr_fix; | |
12005 | else | |
12006 | xt_block = &((*xt_block)->next); | |
12007 | } | |
12008 | if (*xt_block == NULL) | |
12009 | { | |
325801bd | 12010 | xtensa_block_info *new_block = XNEW (xtensa_block_info); |
43cd72b9 BW |
12011 | new_block->sec = sec; |
12012 | new_block->offset = fragP->fr_address; | |
12013 | new_block->size = fragP->fr_fix; | |
12014 | new_block->next = NULL; | |
12015 | xtensa_frag_flags_init (&new_block->flags); | |
12016 | *xt_block = new_block; | |
12017 | } | |
12018 | if (end_property_function | |
12019 | && end_property_function (fragP)) | |
12020 | { | |
12021 | xt_block = &((*xt_block)->next); | |
12022 | } | |
12023 | } | |
12024 | } | |
12025 | } | |
12026 | } | |
12027 | ||
12028 | ||
12029 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
12030 | ||
7fa3d080 BW |
12031 | static bfd_boolean |
12032 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
12033 | { |
12034 | if (prop_flags->is_literal | |
12035 | || prop_flags->is_insn | |
12036 | || prop_flags->is_data | |
12037 | || prop_flags->is_unreachable) | |
12038 | return FALSE; | |
12039 | return TRUE; | |
12040 | } | |
12041 | ||
12042 | ||
7fa3d080 BW |
12043 | static void |
12044 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
12045 | { |
12046 | memset (prop_flags, 0, sizeof (frag_flags)); | |
12047 | } | |
12048 | ||
12049 | ||
7fa3d080 BW |
12050 | static void |
12051 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
12052 | { |
12053 | xtensa_frag_flags_init (prop_flags); | |
12054 | if (fragP->tc_frag_data.is_literal) | |
12055 | prop_flags->is_literal = TRUE; | |
99ded152 BW |
12056 | if (fragP->tc_frag_data.is_specific_opcode |
12057 | || fragP->tc_frag_data.is_no_transform) | |
1f7efbae BW |
12058 | { |
12059 | prop_flags->is_no_transform = TRUE; | |
12060 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
12061 | prop_flags->is_data = TRUE; | |
12062 | } | |
43cd72b9 | 12063 | if (fragP->tc_frag_data.is_unreachable) |
7fa3d080 | 12064 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
12065 | else if (fragP->tc_frag_data.is_insn) |
12066 | { | |
12067 | prop_flags->is_insn = TRUE; | |
12068 | if (fragP->tc_frag_data.is_loop_target) | |
12069 | prop_flags->insn.is_loop_target = TRUE; | |
12070 | if (fragP->tc_frag_data.is_branch_target) | |
12071 | prop_flags->insn.is_branch_target = TRUE; | |
43cd72b9 BW |
12072 | if (fragP->tc_frag_data.is_no_density) |
12073 | prop_flags->insn.is_no_density = TRUE; | |
12074 | if (fragP->tc_frag_data.use_absolute_literals) | |
12075 | prop_flags->insn.is_abslit = TRUE; | |
12076 | } | |
12077 | if (fragP->tc_frag_data.is_align) | |
12078 | { | |
12079 | prop_flags->is_align = TRUE; | |
12080 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
12081 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
12082 | prop_flags->is_data = TRUE; | |
12083 | } | |
12084 | } | |
12085 | ||
12086 | ||
2f1bf5c1 | 12087 | static flagword |
7fa3d080 | 12088 | frag_flags_to_number (const frag_flags *prop_flags) |
43cd72b9 | 12089 | { |
2f1bf5c1 | 12090 | flagword num = 0; |
43cd72b9 BW |
12091 | if (prop_flags->is_literal) |
12092 | num |= XTENSA_PROP_LITERAL; | |
12093 | if (prop_flags->is_insn) | |
12094 | num |= XTENSA_PROP_INSN; | |
12095 | if (prop_flags->is_data) | |
12096 | num |= XTENSA_PROP_DATA; | |
12097 | if (prop_flags->is_unreachable) | |
12098 | num |= XTENSA_PROP_UNREACHABLE; | |
12099 | if (prop_flags->insn.is_loop_target) | |
12100 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
12101 | if (prop_flags->insn.is_branch_target) | |
12102 | { | |
12103 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
12104 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
12105 | } | |
12106 | ||
12107 | if (prop_flags->insn.is_no_density) | |
12108 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
99ded152 BW |
12109 | if (prop_flags->is_no_transform) |
12110 | num |= XTENSA_PROP_NO_TRANSFORM; | |
43cd72b9 BW |
12111 | if (prop_flags->insn.is_no_reorder) |
12112 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
12113 | if (prop_flags->insn.is_abslit) | |
12114 | num |= XTENSA_PROP_INSN_ABSLIT; | |
12115 | ||
12116 | if (prop_flags->is_align) | |
12117 | { | |
12118 | num |= XTENSA_PROP_ALIGN; | |
12119 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
12120 | } | |
12121 | ||
12122 | return num; | |
12123 | } | |
12124 | ||
12125 | ||
12126 | static bfd_boolean | |
7fa3d080 BW |
12127 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
12128 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
12129 | { |
12130 | /* Cannot combine with an end marker. */ | |
12131 | ||
12132 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
12133 | return FALSE; | |
12134 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
12135 | return FALSE; | |
12136 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
12137 | return FALSE; | |
12138 | ||
12139 | if (prop_flags_1->is_insn) | |
12140 | { | |
12141 | /* Properties of the beginning of the frag. */ | |
12142 | if (prop_flags_2->insn.is_loop_target) | |
12143 | return FALSE; | |
12144 | if (prop_flags_2->insn.is_branch_target) | |
12145 | return FALSE; | |
12146 | if (prop_flags_1->insn.is_no_density != | |
12147 | prop_flags_2->insn.is_no_density) | |
12148 | return FALSE; | |
99ded152 BW |
12149 | if (prop_flags_1->is_no_transform != |
12150 | prop_flags_2->is_no_transform) | |
43cd72b9 BW |
12151 | return FALSE; |
12152 | if (prop_flags_1->insn.is_no_reorder != | |
12153 | prop_flags_2->insn.is_no_reorder) | |
12154 | return FALSE; | |
12155 | if (prop_flags_1->insn.is_abslit != | |
12156 | prop_flags_2->insn.is_abslit) | |
12157 | return FALSE; | |
12158 | } | |
12159 | ||
12160 | if (prop_flags_1->is_align) | |
12161 | return FALSE; | |
12162 | ||
12163 | return TRUE; | |
12164 | } | |
12165 | ||
12166 | ||
7fa3d080 BW |
12167 | static bfd_vma |
12168 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
12169 | { |
12170 | bfd_vma end_addr; | |
d77b99c9 | 12171 | unsigned align_bits; |
43cd72b9 BW |
12172 | |
12173 | if (!xt_block->flags.is_align) | |
12174 | return xt_block->size; | |
12175 | ||
12176 | end_addr = xt_block->offset + xt_block->size; | |
12177 | align_bits = xt_block->flags.alignment; | |
12178 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
12179 | return end_addr - xt_block->offset; | |
12180 | } | |
12181 | ||
12182 | ||
12183 | static bfd_boolean | |
7fa3d080 BW |
12184 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
12185 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
12186 | { |
12187 | if (xt_block->sec != xt_block_2->sec) | |
12188 | return FALSE; | |
12189 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
12190 | != xt_block_2->offset) | |
12191 | return FALSE; | |
12192 | ||
12193 | if (xt_block_2->size == 0 | |
12194 | && (!xt_block_2->flags.is_unreachable | |
12195 | || xt_block->flags.is_unreachable)) | |
12196 | { | |
12197 | if (xt_block_2->flags.is_align | |
12198 | && xt_block->flags.is_align) | |
12199 | { | |
12200 | /* Nothing needed. */ | |
12201 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
12202 | return TRUE; | |
12203 | } | |
12204 | else | |
12205 | { | |
12206 | if (xt_block_2->flags.is_align) | |
12207 | { | |
12208 | /* Push alignment to previous entry. */ | |
12209 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
12210 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
12211 | } | |
12212 | return TRUE; | |
12213 | } | |
12214 | } | |
12215 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
12216 | &xt_block_2->flags)) | |
12217 | return FALSE; | |
12218 | ||
12219 | xt_block->size += xt_block_2->size; | |
12220 | ||
12221 | if (xt_block_2->flags.is_align) | |
12222 | { | |
12223 | xt_block->flags.is_align = TRUE; | |
12224 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
12225 | } | |
12226 | ||
12227 | return TRUE; | |
12228 | } | |
12229 | ||
12230 | ||
7fa3d080 BW |
12231 | static void |
12232 | add_xt_prop_frags (segT sec, | |
7fa3d080 BW |
12233 | xtensa_block_info **xt_block, |
12234 | frag_flags_fn property_function) | |
43cd72b9 | 12235 | { |
43cd72b9 BW |
12236 | fragS *fragP; |
12237 | ||
43cd72b9 BW |
12238 | /* Build it if needed. */ |
12239 | while (*xt_block != NULL) | |
12240 | { | |
12241 | xt_block = &(*xt_block)->next; | |
12242 | } | |
12243 | /* We are either at NULL at the beginning or at the end. */ | |
12244 | ||
12245 | /* Walk through the frags. */ | |
542f8b94 | 12246 | if (seg_info (sec)->frchainP) |
43cd72b9 | 12247 | { |
542f8b94 | 12248 | for (fragP = seg_info (sec)->frchainP->frch_root; fragP; |
43cd72b9 BW |
12249 | fragP = fragP->fr_next) |
12250 | { | |
12251 | xtensa_block_info tmp_block; | |
12252 | tmp_block.sec = sec; | |
12253 | tmp_block.offset = fragP->fr_address; | |
12254 | tmp_block.size = fragP->fr_fix; | |
12255 | tmp_block.next = NULL; | |
12256 | property_function (fragP, &tmp_block.flags); | |
12257 | ||
12258 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
12259 | /* && fragP->fr_fix != 0) */ | |
12260 | { | |
12261 | if ((*xt_block) == NULL | |
12262 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
12263 | { | |
12264 | xtensa_block_info *new_block; | |
12265 | if ((*xt_block) != NULL) | |
12266 | xt_block = &(*xt_block)->next; | |
325801bd | 12267 | new_block = XNEW (xtensa_block_info); |
43cd72b9 BW |
12268 | *new_block = tmp_block; |
12269 | *xt_block = new_block; | |
12270 | } | |
12271 | } | |
12272 | } | |
12273 | } | |
12274 | } | |
12275 | ||
12276 | \f | |
12277 | /* op_placement_info_table */ | |
12278 | ||
12279 | /* op_placement_info makes it easier to determine which | |
12280 | ops can go in which slots. */ | |
12281 | ||
12282 | static void | |
7fa3d080 | 12283 | init_op_placement_info_table (void) |
43cd72b9 BW |
12284 | { |
12285 | xtensa_isa isa = xtensa_default_isa; | |
12286 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
12287 | xtensa_opcode opcode; | |
12288 | xtensa_format fmt; | |
12289 | int slot; | |
12290 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
12291 | ||
325801bd | 12292 | op_placement_table = XNEWVEC (op_placement_info, num_opcodes); |
9c2799c2 | 12293 | gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); |
43cd72b9 BW |
12294 | |
12295 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
12296 | { | |
12297 | op_placement_info *opi = &op_placement_table[opcode]; | |
12298 | /* FIXME: Make tinsn allocation dynamic. */ | |
51add5c3 | 12299 | if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS) |
43cd72b9 | 12300 | as_fatal (_("too many operands in instruction")); |
43cd72b9 BW |
12301 | opi->narrowest = XTENSA_UNDEFINED; |
12302 | opi->narrowest_size = 0x7F; | |
b2d179be | 12303 | opi->narrowest_slot = 0; |
43cd72b9 BW |
12304 | opi->formats = 0; |
12305 | opi->num_formats = 0; | |
12306 | opi->issuef = 0; | |
12307 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
12308 | { | |
12309 | opi->slots[fmt] = 0; | |
12310 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
12311 | { | |
12312 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
12313 | { | |
12314 | int fmt_length = xtensa_format_length (isa, fmt); | |
12315 | opi->issuef++; | |
12316 | set_bit (fmt, opi->formats); | |
12317 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
12318 | if (fmt_length < opi->narrowest_size |
12319 | || (fmt_length == opi->narrowest_size | |
12320 | && (xtensa_format_num_slots (isa, fmt) | |
12321 | < xtensa_format_num_slots (isa, | |
12322 | opi->narrowest)))) | |
43cd72b9 BW |
12323 | { |
12324 | opi->narrowest = fmt; | |
12325 | opi->narrowest_size = fmt_length; | |
b2d179be | 12326 | opi->narrowest_slot = slot; |
43cd72b9 | 12327 | } |
e0001a05 NC |
12328 | } |
12329 | } | |
43cd72b9 BW |
12330 | if (opi->formats) |
12331 | opi->num_formats++; | |
e0001a05 NC |
12332 | } |
12333 | } | |
43cd72b9 BW |
12334 | xtensa_insnbuf_free (isa, ibuf); |
12335 | } | |
12336 | ||
12337 | ||
12338 | bfd_boolean | |
7fa3d080 | 12339 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
12340 | { |
12341 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
12342 | } | |
12343 | ||
12344 | ||
12345 | /* If the opcode is available in a single slot format, return its size. */ | |
12346 | ||
7fa3d080 BW |
12347 | static int |
12348 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 12349 | { |
b2d179be | 12350 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
12351 | } |
12352 | ||
12353 | ||
7fa3d080 BW |
12354 | static xtensa_format |
12355 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 12356 | { |
b2d179be BW |
12357 | return op_placement_table[opcode].narrowest; |
12358 | } | |
12359 | ||
12360 | ||
12361 | static int | |
12362 | xg_get_single_slot (xtensa_opcode opcode) | |
12363 | { | |
12364 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
12365 | } |
12366 | ||
12367 | \f | |
12368 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
12369 | ||
12370 | void | |
7fa3d080 | 12371 | istack_init (IStack *stack) |
e0001a05 | 12372 | { |
e0001a05 NC |
12373 | stack->ninsn = 0; |
12374 | } | |
12375 | ||
12376 | ||
12377 | bfd_boolean | |
7fa3d080 | 12378 | istack_empty (IStack *stack) |
e0001a05 NC |
12379 | { |
12380 | return (stack->ninsn == 0); | |
12381 | } | |
12382 | ||
12383 | ||
12384 | bfd_boolean | |
7fa3d080 | 12385 | istack_full (IStack *stack) |
e0001a05 NC |
12386 | { |
12387 | return (stack->ninsn == MAX_ISTACK); | |
12388 | } | |
12389 | ||
12390 | ||
12391 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 12392 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
12393 | |
12394 | TInsn * | |
7fa3d080 | 12395 | istack_top (IStack *stack) |
e0001a05 NC |
12396 | { |
12397 | int rec = stack->ninsn - 1; | |
9c2799c2 | 12398 | gas_assert (!istack_empty (stack)); |
e0001a05 NC |
12399 | return &stack->insn[rec]; |
12400 | } | |
12401 | ||
12402 | ||
12403 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 12404 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
12405 | |
12406 | void | |
7fa3d080 | 12407 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
12408 | { |
12409 | int rec = stack->ninsn; | |
9c2799c2 | 12410 | gas_assert (!istack_full (stack)); |
43cd72b9 | 12411 | stack->insn[rec] = *insn; |
e0001a05 NC |
12412 | stack->ninsn++; |
12413 | } | |
12414 | ||
12415 | ||
12416 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 12417 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
12418 | |
12419 | TInsn * | |
7fa3d080 | 12420 | istack_push_space (IStack *stack) |
e0001a05 NC |
12421 | { |
12422 | int rec = stack->ninsn; | |
12423 | TInsn *insn; | |
9c2799c2 | 12424 | gas_assert (!istack_full (stack)); |
e0001a05 | 12425 | insn = &stack->insn[rec]; |
60242db2 | 12426 | tinsn_init (insn); |
e0001a05 NC |
12427 | stack->ninsn++; |
12428 | return insn; | |
12429 | } | |
12430 | ||
12431 | ||
12432 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 12433 | istack_empty () returns TRUE. */ |
e0001a05 NC |
12434 | |
12435 | void | |
7fa3d080 | 12436 | istack_pop (IStack *stack) |
e0001a05 NC |
12437 | { |
12438 | int rec = stack->ninsn - 1; | |
9c2799c2 | 12439 | gas_assert (!istack_empty (stack)); |
e0001a05 | 12440 | stack->ninsn--; |
60242db2 | 12441 | tinsn_init (&stack->insn[rec]); |
e0001a05 NC |
12442 | } |
12443 | ||
12444 | \f | |
12445 | /* TInsn functions. */ | |
12446 | ||
12447 | void | |
7fa3d080 | 12448 | tinsn_init (TInsn *dst) |
e0001a05 NC |
12449 | { |
12450 | memset (dst, 0, sizeof (TInsn)); | |
12451 | } | |
12452 | ||
12453 | ||
43cd72b9 | 12454 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
12455 | |
12456 | static bfd_boolean | |
7fa3d080 | 12457 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
12458 | { |
12459 | int i; | |
12460 | int n = insn->ntok; | |
12461 | ||
9c2799c2 | 12462 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12463 | |
12464 | for (i = 0; i < n; ++i) | |
12465 | { | |
12466 | switch (insn->tok[i].X_op) | |
12467 | { | |
12468 | case O_register: | |
12469 | case O_constant: | |
12470 | break; | |
12471 | default: | |
12472 | return TRUE; | |
12473 | } | |
12474 | } | |
12475 | return FALSE; | |
12476 | } | |
12477 | ||
12478 | ||
12479 | bfd_boolean | |
7fa3d080 | 12480 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 12481 | { |
43cd72b9 | 12482 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
12483 | int i; |
12484 | int n = insn->ntok; | |
12485 | ||
9c2799c2 | 12486 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12487 | |
12488 | for (i = 0; i < n; ++i) | |
12489 | { | |
12490 | switch (insn->tok[i].X_op) | |
12491 | { | |
12492 | case O_register: | |
12493 | case O_constant: | |
12494 | break; | |
43cd72b9 BW |
12495 | case O_big: |
12496 | case O_illegal: | |
12497 | case O_absent: | |
12498 | /* Errors for these types are caught later. */ | |
12499 | break; | |
12500 | case O_hi16: | |
12501 | case O_lo16: | |
e0001a05 | 12502 | default: |
43cd72b9 BW |
12503 | /* Symbolic immediates are only allowed on the last immediate |
12504 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 12505 | support non-PC-relative relocations. */ |
43cd72b9 BW |
12506 | if (i != get_relaxable_immed (insn->opcode) |
12507 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
12508 | && insn->opcode != xtensa_const16_opcode)) | |
12509 | { | |
431ad2d0 | 12510 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
12511 | return TRUE; |
12512 | } | |
e0001a05 NC |
12513 | } |
12514 | } | |
12515 | return FALSE; | |
12516 | } | |
12517 | ||
12518 | ||
12519 | /* For assembly code with complex expressions (e.g. subtraction), | |
12520 | we have to build them in the literal pool so that | |
12521 | their results are calculated correctly after relaxation. | |
12522 | The relaxation only handles expressions that | |
12523 | boil down to SYMBOL + OFFSET. */ | |
12524 | ||
12525 | static bfd_boolean | |
7fa3d080 | 12526 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
12527 | { |
12528 | int i; | |
12529 | int n = insn->ntok; | |
9c2799c2 | 12530 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12531 | for (i = 0; i < n; ++i) |
12532 | { | |
12533 | switch (insn->tok[i].X_op) | |
12534 | { | |
12535 | case O_register: | |
12536 | case O_constant: | |
12537 | case O_symbol: | |
43cd72b9 BW |
12538 | case O_lo16: |
12539 | case O_hi16: | |
e0001a05 NC |
12540 | break; |
12541 | default: | |
12542 | return TRUE; | |
12543 | } | |
12544 | } | |
12545 | return FALSE; | |
12546 | } | |
12547 | ||
12548 | ||
b2d179be BW |
12549 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
12550 | Return TRUE if there is a symbol in the immediate field. This | |
12551 | function assumes that: | |
12552 | 1) The number of operands are correct. | |
12553 | 2) The insn_type is ITYPE_INSN. | |
12554 | 3) The opcode can be encoded in the specified format and slot. | |
12555 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
12556 | |
12557 | static bfd_boolean | |
7fa3d080 BW |
12558 | tinsn_to_slotbuf (xtensa_format fmt, |
12559 | int slot, | |
12560 | TInsn *tinsn, | |
12561 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
12562 | { |
12563 | xtensa_isa isa = xtensa_default_isa; | |
12564 | xtensa_opcode opcode = tinsn->opcode; | |
12565 | bfd_boolean has_fixup = FALSE; | |
12566 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
12567 | int i; | |
12568 | ||
9c2799c2 | 12569 | gas_assert (tinsn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
12570 | if (noperands != tinsn->ntok) |
12571 | as_fatal (_("operand number mismatch")); | |
12572 | ||
12573 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
12574 | { | |
12575 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
12576 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
12577 | return FALSE; | |
12578 | } | |
12579 | ||
12580 | for (i = 0; i < noperands; i++) | |
12581 | { | |
91d6fa6a | 12582 | expressionS *exp = &tinsn->tok[i]; |
d77b99c9 BW |
12583 | int rc; |
12584 | unsigned line; | |
3b4dbbbf | 12585 | const char *file_name; |
43cd72b9 BW |
12586 | uint32 opnd_value; |
12587 | ||
91d6fa6a | 12588 | switch (exp->X_op) |
43cd72b9 BW |
12589 | { |
12590 | case O_register: | |
12591 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
12592 | break; | |
12593 | /* The register number has already been checked in | |
12594 | expression_maybe_register, so we don't need to check here. */ | |
91d6fa6a | 12595 | opnd_value = exp->X_add_number; |
43cd72b9 BW |
12596 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); |
12597 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
12598 | opnd_value); | |
12599 | if (rc != 0) | |
12600 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
12601 | break; | |
12602 | ||
12603 | case O_constant: | |
12604 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
12605 | break; | |
3b4dbbbf | 12606 | file_name = as_where (&line); |
43cd72b9 BW |
12607 | /* It is a constant and we called this function |
12608 | then we have to try to fit it. */ | |
12609 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
91d6fa6a | 12610 | exp->X_add_number, file_name, line); |
e0001a05 NC |
12611 | break; |
12612 | ||
e0001a05 NC |
12613 | default: |
12614 | has_fixup = TRUE; | |
12615 | break; | |
12616 | } | |
12617 | } | |
43cd72b9 | 12618 | |
e0001a05 NC |
12619 | return has_fixup; |
12620 | } | |
12621 | ||
12622 | ||
b2d179be BW |
12623 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
12624 | into a multi-slot instruction, fill the other slots with NOPs. | |
12625 | Return TRUE if there is a symbol in the immediate field. See also the | |
12626 | assumptions listed for tinsn_to_slotbuf. */ | |
12627 | ||
12628 | static bfd_boolean | |
12629 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
12630 | { | |
12631 | static xtensa_insnbuf slotbuf = 0; | |
12632 | static vliw_insn vinsn; | |
12633 | xtensa_isa isa = xtensa_default_isa; | |
12634 | bfd_boolean has_fixup = FALSE; | |
12635 | int i; | |
12636 | ||
12637 | if (!slotbuf) | |
12638 | { | |
12639 | slotbuf = xtensa_insnbuf_alloc (isa); | |
12640 | xg_init_vinsn (&vinsn); | |
12641 | } | |
12642 | ||
12643 | xg_clear_vinsn (&vinsn); | |
12644 | ||
12645 | bundle_tinsn (tinsn, &vinsn); | |
12646 | ||
12647 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
12648 | ||
12649 | for (i = 0; i < vinsn.num_slots; i++) | |
12650 | { | |
12651 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
12652 | has_fixup |= | |
12653 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
12654 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
12655 | } | |
12656 | ||
12657 | return has_fixup; | |
12658 | } | |
12659 | ||
12660 | ||
43cd72b9 | 12661 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 12662 | |
7fa3d080 BW |
12663 | static bfd_boolean |
12664 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
12665 | { |
12666 | xtensa_isa isa = xtensa_default_isa; | |
12667 | xtensa_opcode opcode = insn->opcode; | |
6dc6b655 BW |
12668 | xtensa_regfile t1_regfile, t2_regfile; |
12669 | int t1_reg, t2_reg; | |
12670 | int t1_base_reg, t1_last_reg; | |
12671 | int t2_base_reg, t2_last_reg; | |
12672 | char t1_inout, t2_inout; | |
12673 | int i, j; | |
e0001a05 NC |
12674 | |
12675 | if (opcode == XTENSA_UNDEFINED) | |
12676 | { | |
12677 | as_bad (_("invalid opcode")); | |
12678 | return TRUE; | |
12679 | } | |
12680 | ||
43cd72b9 | 12681 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
12682 | { |
12683 | as_bad (_("too few operands")); | |
12684 | return TRUE; | |
12685 | } | |
12686 | ||
43cd72b9 | 12687 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
12688 | { |
12689 | as_bad (_("too many operands")); | |
12690 | return TRUE; | |
12691 | } | |
6dc6b655 BW |
12692 | |
12693 | /* Check registers. */ | |
12694 | for (j = 0; j < insn->ntok; j++) | |
12695 | { | |
12696 | if (xtensa_operand_is_register (isa, insn->opcode, j) != 1) | |
12697 | continue; | |
12698 | ||
12699 | t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j); | |
12700 | t2_base_reg = insn->tok[j].X_add_number; | |
12701 | t2_last_reg | |
12702 | = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j); | |
12703 | ||
12704 | for (i = 0; i < insn->ntok; i++) | |
12705 | { | |
12706 | if (i == j) | |
12707 | continue; | |
12708 | ||
12709 | if (xtensa_operand_is_register (isa, insn->opcode, i) != 1) | |
12710 | continue; | |
12711 | ||
12712 | t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i); | |
12713 | ||
12714 | if (t1_regfile != t2_regfile) | |
12715 | continue; | |
12716 | ||
12717 | t1_inout = xtensa_operand_inout (isa, insn->opcode, i); | |
12718 | t2_inout = xtensa_operand_inout (isa, insn->opcode, j); | |
12719 | ||
12720 | t1_base_reg = insn->tok[i].X_add_number; | |
12721 | t1_last_reg = (t1_base_reg | |
12722 | + xtensa_operand_num_regs (isa, insn->opcode, i)); | |
12723 | ||
12724 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
12725 | { | |
12726 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
12727 | { | |
12728 | if (t1_reg != t2_reg) | |
12729 | continue; | |
12730 | ||
12731 | if (t1_inout != 'i' && t2_inout != 'i') | |
12732 | { | |
12733 | as_bad (_("multiple writes to the same register")); | |
12734 | return TRUE; | |
12735 | } | |
12736 | } | |
12737 | } | |
12738 | } | |
12739 | } | |
e0001a05 NC |
12740 | return FALSE; |
12741 | } | |
12742 | ||
12743 | ||
12744 | /* Load an instruction from its encoded form. */ | |
12745 | ||
12746 | static void | |
7fa3d080 | 12747 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 12748 | { |
43cd72b9 | 12749 | vliw_insn vinsn; |
e0001a05 | 12750 | |
43cd72b9 BW |
12751 | xg_init_vinsn (&vinsn); |
12752 | vinsn_from_chars (&vinsn, f); | |
12753 | ||
12754 | *tinsn = vinsn.slots[slot]; | |
12755 | xg_free_vinsn (&vinsn); | |
12756 | } | |
e0001a05 | 12757 | |
43cd72b9 BW |
12758 | |
12759 | static void | |
7fa3d080 BW |
12760 | tinsn_from_insnbuf (TInsn *tinsn, |
12761 | xtensa_insnbuf slotbuf, | |
12762 | xtensa_format fmt, | |
12763 | int slot) | |
43cd72b9 BW |
12764 | { |
12765 | int i; | |
12766 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
12767 | |
12768 | /* Find the immed. */ | |
43cd72b9 BW |
12769 | tinsn_init (tinsn); |
12770 | tinsn->insn_type = ITYPE_INSN; | |
12771 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
12772 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
12773 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
12774 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 12775 | { |
43cd72b9 BW |
12776 | set_expr_const (&tinsn->tok[i], |
12777 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
12778 | tinsn->opcode, i)); | |
e0001a05 NC |
12779 | } |
12780 | } | |
12781 | ||
12782 | ||
12783 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
12784 | ||
12785 | static void | |
7fa3d080 | 12786 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 12787 | { |
43cd72b9 | 12788 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
12789 | int opnum; |
12790 | ||
43cd72b9 | 12791 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
12792 | { |
12793 | opnum = get_relaxable_immed (opcode); | |
9c2799c2 | 12794 | gas_assert (opnum >= 0); |
e7da6241 BW |
12795 | set_expr_symbol_offset (&tinsn->tok[opnum], |
12796 | fragP->tc_frag_data.slot_symbols[slot], | |
12797 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 | 12798 | } |
19e8f41a | 12799 | tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot]; |
e0001a05 NC |
12800 | } |
12801 | ||
12802 | ||
12803 | static int | |
7fa3d080 | 12804 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
12805 | { |
12806 | int i; | |
12807 | int text_bytes = 0; | |
12808 | ||
12809 | for (i = 0; i < istack->ninsn; i++) | |
12810 | { | |
43cd72b9 BW |
12811 | TInsn *tinsn = &istack->insn[i]; |
12812 | if (tinsn->insn_type == ITYPE_INSN) | |
12813 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
12814 | } |
12815 | return text_bytes; | |
12816 | } | |
12817 | ||
12818 | ||
12819 | static int | |
7fa3d080 | 12820 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
12821 | { |
12822 | int i; | |
12823 | int lit_bytes = 0; | |
12824 | ||
12825 | for (i = 0; i < istack->ninsn; i++) | |
12826 | { | |
43cd72b9 BW |
12827 | TInsn *tinsn = &istack->insn[i]; |
12828 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
12829 | lit_bytes += 4; |
12830 | } | |
12831 | return lit_bytes; | |
12832 | } | |
12833 | ||
43cd72b9 BW |
12834 | \f |
12835 | /* vliw_insn functions. */ | |
12836 | ||
7fa3d080 BW |
12837 | static void |
12838 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12839 | { |
12840 | int i; | |
12841 | xtensa_isa isa = xtensa_default_isa; | |
12842 | ||
12843 | xg_clear_vinsn (v); | |
12844 | ||
12845 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
12846 | if (v->insnbuf == NULL) | |
12847 | as_fatal (_("out of memory")); | |
12848 | ||
62af60e2 | 12849 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 | 12850 | { |
43cd72b9 BW |
12851 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
12852 | if (v->slotbuf[i] == NULL) | |
12853 | as_fatal (_("out of memory")); | |
12854 | } | |
12855 | } | |
12856 | ||
12857 | ||
7fa3d080 BW |
12858 | static void |
12859 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12860 | { |
12861 | int i; | |
65738a7d | 12862 | |
3739860c | 12863 | memset (v, 0, offsetof (vliw_insn, slots) |
62af60e2 | 12864 | + sizeof(TInsn) * config_max_slots); |
65738a7d | 12865 | |
43cd72b9 BW |
12866 | v->format = XTENSA_UNDEFINED; |
12867 | v->num_slots = 0; | |
12868 | v->inside_bundle = FALSE; | |
12869 | ||
12870 | if (xt_saved_debug_type != DEBUG_NONE) | |
12871 | debug_type = xt_saved_debug_type; | |
12872 | ||
62af60e2 | 12873 | for (i = 0; i < config_max_slots; i++) |
65738a7d | 12874 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
12875 | } |
12876 | ||
12877 | ||
d8392fd9 SA |
12878 | static void |
12879 | xg_copy_vinsn (vliw_insn *dst, vliw_insn *src) | |
12880 | { | |
3739860c | 12881 | memcpy (dst, src, |
d8392fd9 SA |
12882 | offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn)); |
12883 | dst->insnbuf = src->insnbuf; | |
12884 | memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf)); | |
12885 | } | |
12886 | ||
12887 | ||
7fa3d080 BW |
12888 | static bfd_boolean |
12889 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
12890 | { |
12891 | int i; | |
c138bc38 | 12892 | |
43cd72b9 BW |
12893 | for (i = 0; i < v->num_slots; i++) |
12894 | { | |
12895 | if (v->slots[i].is_specific_opcode) | |
12896 | return TRUE; | |
12897 | } | |
12898 | return FALSE; | |
12899 | } | |
12900 | ||
12901 | ||
7fa3d080 BW |
12902 | static void |
12903 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12904 | { |
12905 | int i; | |
12906 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
62af60e2 | 12907 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 BW |
12908 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); |
12909 | } | |
12910 | ||
12911 | ||
e7da6241 BW |
12912 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
12913 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
12914 | |
12915 | static bfd_boolean | |
7fa3d080 BW |
12916 | vinsn_to_insnbuf (vliw_insn *vinsn, |
12917 | char *frag_offset, | |
12918 | fragS *fragP, | |
12919 | bfd_boolean record_fixup) | |
43cd72b9 BW |
12920 | { |
12921 | xtensa_isa isa = xtensa_default_isa; | |
12922 | xtensa_format fmt = vinsn->format; | |
12923 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
12924 | int slot; | |
12925 | bfd_boolean has_fixup = FALSE; | |
12926 | ||
12927 | xtensa_format_encode (isa, fmt, insnbuf); | |
12928 | ||
12929 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
12930 | { | |
12931 | TInsn *tinsn = &vinsn->slots[slot]; | |
19e8f41a | 12932 | expressionS *extra_arg = &tinsn->extra_arg; |
43cd72b9 BW |
12933 | bfd_boolean tinsn_has_fixup = |
12934 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
12935 | vinsn->slotbuf[slot]); | |
12936 | ||
12937 | xtensa_format_set_slot (isa, fmt, slot, | |
12938 | insnbuf, vinsn->slotbuf[slot]); | |
19e8f41a | 12939 | if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register) |
28dbbc02 BW |
12940 | { |
12941 | if (vinsn->num_slots != 1) | |
12942 | as_bad (_("TLS relocation not allowed in FLIX bundle")); | |
12943 | else if (record_fixup) | |
12944 | /* Instructions that generate TLS relocations should always be | |
12945 | relaxed in the front-end. If "record_fixup" is set, then this | |
12946 | function is being called during back-end relaxation, so flag | |
12947 | the unexpected behavior as an error. */ | |
12948 | as_bad (_("unexpected TLS relocation")); | |
12949 | else | |
12950 | fix_new (fragP, frag_offset - fragP->fr_literal, | |
12951 | xtensa_format_length (isa, fmt), | |
19e8f41a BW |
12952 | extra_arg->X_add_symbol, extra_arg->X_add_number, |
12953 | FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE)); | |
28dbbc02 | 12954 | } |
e7da6241 | 12955 | if (tinsn_has_fixup) |
43cd72b9 BW |
12956 | { |
12957 | int i; | |
12958 | xtensa_opcode opcode = tinsn->opcode; | |
12959 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
12960 | has_fixup = TRUE; | |
12961 | ||
12962 | for (i = 0; i < noperands; i++) | |
12963 | { | |
91d6fa6a NC |
12964 | expressionS* exp = &tinsn->tok[i]; |
12965 | switch (exp->X_op) | |
43cd72b9 BW |
12966 | { |
12967 | case O_symbol: | |
12968 | case O_lo16: | |
12969 | case O_hi16: | |
12970 | if (get_relaxable_immed (opcode) == i) | |
12971 | { | |
e7da6241 BW |
12972 | /* Add a fix record for the instruction, except if this |
12973 | function is being called prior to relaxation, i.e., | |
12974 | if record_fixup is false, and the instruction might | |
12975 | be relaxed later. */ | |
12976 | if (record_fixup | |
12977 | || tinsn->is_specific_opcode | |
12978 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 12979 | { |
91d6fa6a | 12980 | xg_add_opcode_fix (tinsn, i, fmt, slot, exp, fragP, |
e7da6241 | 12981 | frag_offset - fragP->fr_literal); |
43cd72b9 BW |
12982 | } |
12983 | else | |
12984 | { | |
91d6fa6a | 12985 | if (exp->X_op != O_symbol) |
e7da6241 | 12986 | as_bad (_("invalid operand")); |
91d6fa6a NC |
12987 | tinsn->symbol = exp->X_add_symbol; |
12988 | tinsn->offset = exp->X_add_number; | |
43cd72b9 BW |
12989 | } |
12990 | } | |
12991 | else | |
e7da6241 | 12992 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
12993 | break; |
12994 | ||
12995 | case O_constant: | |
12996 | case O_register: | |
12997 | break; | |
12998 | ||
43cd72b9 | 12999 | default: |
e7da6241 | 13000 | as_bad (_("expression too complex")); |
43cd72b9 BW |
13001 | break; |
13002 | } | |
13003 | } | |
13004 | } | |
13005 | } | |
13006 | ||
13007 | return has_fixup; | |
13008 | } | |
13009 | ||
13010 | ||
13011 | static void | |
7fa3d080 | 13012 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
13013 | { |
13014 | static xtensa_insnbuf insnbuf = NULL; | |
13015 | static xtensa_insnbuf slotbuf = NULL; | |
13016 | int i; | |
13017 | xtensa_format fmt; | |
13018 | xtensa_isa isa = xtensa_default_isa; | |
13019 | ||
13020 | if (!insnbuf) | |
13021 | { | |
13022 | insnbuf = xtensa_insnbuf_alloc (isa); | |
13023 | slotbuf = xtensa_insnbuf_alloc (isa); | |
13024 | } | |
13025 | ||
d77b99c9 | 13026 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
13027 | fmt = xtensa_format_decode (isa, insnbuf); |
13028 | if (fmt == XTENSA_UNDEFINED) | |
13029 | as_fatal (_("cannot decode instruction format")); | |
13030 | vinsn->format = fmt; | |
13031 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
13032 | ||
13033 | for (i = 0; i < vinsn->num_slots; i++) | |
13034 | { | |
13035 | TInsn *tinsn = &vinsn->slots[i]; | |
13036 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
13037 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
13038 | } | |
13039 | } | |
13040 | ||
e0001a05 NC |
13041 | \f |
13042 | /* Expression utilities. */ | |
13043 | ||
43cd72b9 | 13044 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
13045 | |
13046 | bfd_boolean | |
7fa3d080 | 13047 | expr_is_const (const expressionS *s) |
e0001a05 NC |
13048 | { |
13049 | return (s->X_op == O_constant); | |
13050 | } | |
13051 | ||
13052 | ||
13053 | /* Get the expression constant. | |
43cd72b9 | 13054 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
13055 | |
13056 | offsetT | |
7fa3d080 | 13057 | get_expr_const (const expressionS *s) |
e0001a05 | 13058 | { |
9c2799c2 | 13059 | gas_assert (expr_is_const (s)); |
e0001a05 NC |
13060 | return s->X_add_number; |
13061 | } | |
13062 | ||
13063 | ||
13064 | /* Set the expression to a constant value. */ | |
13065 | ||
13066 | void | |
7fa3d080 | 13067 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
13068 | { |
13069 | s->X_op = O_constant; | |
13070 | s->X_add_number = val; | |
13071 | s->X_add_symbol = NULL; | |
13072 | s->X_op_symbol = NULL; | |
13073 | } | |
13074 | ||
13075 | ||
43cd72b9 | 13076 | bfd_boolean |
7fa3d080 | 13077 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
13078 | { |
13079 | return (s->X_op == O_register); | |
13080 | } | |
13081 | ||
13082 | ||
13083 | /* Get the expression constant. | |
13084 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
13085 | ||
13086 | offsetT | |
7fa3d080 | 13087 | get_expr_register (const expressionS *s) |
43cd72b9 | 13088 | { |
9c2799c2 | 13089 | gas_assert (expr_is_register (s)); |
43cd72b9 BW |
13090 | return s->X_add_number; |
13091 | } | |
13092 | ||
13093 | ||
e0001a05 NC |
13094 | /* Set the expression to a symbol + constant offset. */ |
13095 | ||
13096 | void | |
7fa3d080 | 13097 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
13098 | { |
13099 | s->X_op = O_symbol; | |
13100 | s->X_add_symbol = sym; | |
13101 | s->X_op_symbol = NULL; /* unused */ | |
13102 | s->X_add_number = offset; | |
13103 | } | |
13104 | ||
13105 | ||
43cd72b9 BW |
13106 | /* Return TRUE if the two expressions are equal. */ |
13107 | ||
e0001a05 | 13108 | bfd_boolean |
7fa3d080 | 13109 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
13110 | { |
13111 | if (s1->X_op != s2->X_op) | |
13112 | return FALSE; | |
13113 | if (s1->X_add_symbol != s2->X_add_symbol) | |
13114 | return FALSE; | |
13115 | if (s1->X_op_symbol != s2->X_op_symbol) | |
13116 | return FALSE; | |
13117 | if (s1->X_add_number != s2->X_add_number) | |
13118 | return FALSE; | |
13119 | return TRUE; | |
13120 | } | |
13121 | ||
13122 | ||
13123 | static void | |
7fa3d080 | 13124 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
13125 | { |
13126 | memcpy (dst, src, sizeof (expressionS)); | |
13127 | } | |
13128 | ||
13129 | \f | |
9456465c | 13130 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
13131 | |
13132 | struct rename_section_struct | |
13133 | { | |
e4a0c708 | 13134 | const char *old_name; |
e0001a05 NC |
13135 | char *new_name; |
13136 | struct rename_section_struct *next; | |
13137 | }; | |
13138 | ||
13139 | static struct rename_section_struct *section_rename; | |
13140 | ||
13141 | ||
9456465c BW |
13142 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
13143 | entries to the section_rename list. Note: Specifying multiple | |
13144 | renamings separated by colons is not documented and is retained only | |
13145 | for backward compatibility. */ | |
e0001a05 | 13146 | |
7fa3d080 BW |
13147 | static void |
13148 | build_section_rename (const char *arg) | |
e0001a05 | 13149 | { |
9456465c | 13150 | struct rename_section_struct *r; |
e0001a05 NC |
13151 | char *this_arg = NULL; |
13152 | char *next_arg = NULL; | |
13153 | ||
9456465c | 13154 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 13155 | { |
9456465c BW |
13156 | char *old_name, *new_name; |
13157 | ||
e0001a05 NC |
13158 | if (this_arg) |
13159 | { | |
13160 | next_arg = strchr (this_arg, ':'); | |
13161 | if (next_arg) | |
13162 | { | |
13163 | *next_arg = '\0'; | |
13164 | next_arg++; | |
13165 | } | |
13166 | } | |
e0001a05 | 13167 | |
9456465c BW |
13168 | old_name = this_arg; |
13169 | new_name = strchr (this_arg, '='); | |
e0001a05 | 13170 | |
9456465c BW |
13171 | if (*old_name == '\0') |
13172 | { | |
13173 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
13174 | continue; | |
13175 | } | |
13176 | if (!new_name || new_name[1] == '\0') | |
13177 | { | |
13178 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
13179 | old_name); | |
13180 | continue; | |
13181 | } | |
13182 | *new_name = '\0'; | |
13183 | new_name++; | |
e0001a05 | 13184 | |
9456465c BW |
13185 | /* Check for invalid section renaming. */ |
13186 | for (r = section_rename; r != NULL; r = r->next) | |
13187 | { | |
13188 | if (strcmp (r->old_name, old_name) == 0) | |
13189 | as_bad (_("section %s renamed multiple times"), old_name); | |
13190 | if (strcmp (r->new_name, new_name) == 0) | |
13191 | as_bad (_("multiple sections remapped to output section %s"), | |
13192 | new_name); | |
13193 | } | |
e0001a05 | 13194 | |
9456465c | 13195 | /* Now add it. */ |
325801bd | 13196 | r = XNEW (struct rename_section_struct); |
9456465c BW |
13197 | r->old_name = xstrdup (old_name); |
13198 | r->new_name = xstrdup (new_name); | |
13199 | r->next = section_rename; | |
13200 | section_rename = r; | |
e0001a05 | 13201 | } |
e0001a05 NC |
13202 | } |
13203 | ||
13204 | ||
9456465c | 13205 | char * |
e4a0c708 | 13206 | xtensa_section_rename (const char *name) |
e0001a05 NC |
13207 | { |
13208 | struct rename_section_struct *r = section_rename; | |
13209 | ||
13210 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
13211 | { |
13212 | if (strcmp (r->old_name, name) == 0) | |
13213 | return r->new_name; | |
13214 | } | |
e0001a05 | 13215 | |
e4a0c708 | 13216 | return (char *) name; |
e0001a05 | 13217 | } |