Commit | Line | Data |
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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
63a7429b | 2 | Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 | 20 | |
43cd72b9 | 21 | #include <limits.h> |
e0001a05 NC |
22 | #include "as.h" |
23 | #include "sb.h" | |
24 | #include "safe-ctype.h" | |
25 | #include "tc-xtensa.h" | |
e0001a05 NC |
26 | #include "subsegs.h" |
27 | #include "xtensa-relax.h" | |
28 | #include "xtensa-istack.h" | |
cda2eb9e | 29 | #include "dwarf2dbg.h" |
e0001a05 NC |
30 | #include "struc-symbol.h" |
31 | #include "xtensa-config.h" | |
32 | ||
2caa7ca0 BW |
33 | /* Provide default values for new configuration settings. */ |
34 | #ifndef XSHAL_ABI | |
35 | #define XSHAL_ABI 0 | |
36 | #endif | |
37 | ||
e0001a05 NC |
38 | #ifndef uint32 |
39 | #define uint32 unsigned int | |
40 | #endif | |
41 | #ifndef int32 | |
42 | #define int32 signed int | |
43 | #endif | |
44 | ||
45 | /* Notes: | |
46 | ||
e0001a05 NC |
47 | Naming conventions (used somewhat inconsistently): |
48 | The xtensa_ functions are exported | |
49 | The xg_ functions are internal | |
50 | ||
51 | We also have a couple of different extensibility mechanisms. | |
52 | 1) The idiom replacement: | |
53 | This is used when a line is first parsed to | |
54 | replace an instruction pattern with another instruction | |
55 | It is currently limited to replacements of instructions | |
56 | with constant operands. | |
57 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
58 | replacement patterns. When an instruction's immediate field | |
59 | does not fit the next instruction sequence is attempted. | |
60 | In addition, "narrow" opcodes are supported this way. */ | |
61 | ||
62 | ||
63 | /* Define characters with special meanings to GAS. */ | |
64 | const char comment_chars[] = "#"; | |
65 | const char line_comment_chars[] = "#"; | |
66 | const char line_separator_chars[] = ";"; | |
67 | const char EXP_CHARS[] = "eE"; | |
68 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
69 | ||
70 | ||
43cd72b9 BW |
71 | /* Flags to indicate whether the hardware supports the density and |
72 | absolute literals options. */ | |
e0001a05 | 73 | |
e0001a05 | 74 | bfd_boolean density_supported = XCHAL_HAVE_DENSITY; |
43cd72b9 BW |
75 | bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; |
76 | ||
77 | /* Maximum width we would pad an unreachable frag to get alignment. */ | |
78 | #define UNREACHABLE_MAX_WIDTH 8 | |
e0001a05 | 79 | |
43cd72b9 BW |
80 | static vliw_insn cur_vinsn; |
81 | ||
d77b99c9 | 82 | unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; |
43cd72b9 BW |
83 | |
84 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
85 | ||
86 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 87 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
88 | back end. */ |
89 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
90 | |
91 | /* Flags for properties of the last instruction in a segment. */ | |
92 | #define FLAG_IS_A0_WRITER 0x1 | |
93 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
94 | ||
95 | ||
96 | /* We define a special segment names ".literal" to place literals | |
97 | into. The .fini and .init sections are special because they | |
98 | contain code that is moved together by the linker. We give them | |
99 | their own special .fini.literal and .init.literal sections. */ | |
100 | ||
101 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 102 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 | 103 | #define INIT_SECTION_NAME xtensa_section_rename (".init") |
74869ac7 | 104 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
e0001a05 NC |
105 | |
106 | ||
43cd72b9 | 107 | /* This type is used for the directive_stack to keep track of the |
74869ac7 BW |
108 | state of the literal collection pools. If lit_prefix is set, it is |
109 | used to determine the literal section names; otherwise, the literal | |
110 | sections are determined based on the current text section. The | |
111 | lit_seg and lit4_seg fields cache these literal sections, with the | |
112 | current_text_seg field used a tag to indicate whether the cached | |
113 | values are valid. */ | |
e0001a05 NC |
114 | |
115 | typedef struct lit_state_struct | |
116 | { | |
74869ac7 BW |
117 | char *lit_prefix; |
118 | segT current_text_seg; | |
e0001a05 | 119 | segT lit_seg; |
43cd72b9 | 120 | segT lit4_seg; |
e0001a05 NC |
121 | } lit_state; |
122 | ||
123 | static lit_state default_lit_sections; | |
124 | ||
125 | ||
74869ac7 BW |
126 | /* We keep a list of literal segments. The seg_list type is the node |
127 | for this list. The literal_head pointer is the head of the list, | |
128 | with the literal_head_h dummy node at the start. */ | |
e0001a05 NC |
129 | |
130 | typedef struct seg_list_struct | |
131 | { | |
132 | struct seg_list_struct *next; | |
133 | segT seg; | |
134 | } seg_list; | |
135 | ||
136 | static seg_list literal_head_h; | |
137 | static seg_list *literal_head = &literal_head_h; | |
e0001a05 NC |
138 | |
139 | ||
82e7541d BW |
140 | /* Lists of symbols. We keep a list of symbols that label the current |
141 | instruction, so that we can adjust the symbols when inserting alignment | |
142 | for various instructions. We also keep a list of all the symbols on | |
143 | literals, so that we can fix up those symbols when the literals are | |
144 | later moved into the text sections. */ | |
145 | ||
146 | typedef struct sym_list_struct | |
147 | { | |
148 | struct sym_list_struct *next; | |
149 | symbolS *sym; | |
150 | } sym_list; | |
151 | ||
152 | static sym_list *insn_labels = NULL; | |
153 | static sym_list *free_insn_labels = NULL; | |
154 | static sym_list *saved_insn_labels = NULL; | |
155 | ||
156 | static sym_list *literal_syms; | |
157 | ||
158 | ||
43cd72b9 BW |
159 | /* Flags to determine whether to prefer const16 or l32r |
160 | if both options are available. */ | |
161 | int prefer_const16 = 0; | |
162 | int prefer_l32r = 0; | |
163 | ||
e0001a05 NC |
164 | /* Global flag to indicate when we are emitting literals. */ |
165 | int generating_literals = 0; | |
166 | ||
43cd72b9 BW |
167 | /* The following PROPERTY table definitions are copied from |
168 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
169 | ||
170 | /* Flags in the property tables to specify whether blocks of memory | |
171 | are literals, instructions, data, or unreachable. For | |
172 | instructions, blocks that begin loop targets and branch targets are | |
173 | designated. Blocks that do not allow density, instruction | |
174 | reordering or transformation are also specified. Finally, for | |
175 | branch targets, branch target alignment priority is included. | |
176 | Alignment of the next block is specified in the current block | |
177 | and the size of the current block does not include any fill required | |
178 | to align to the next block. */ | |
179 | ||
180 | #define XTENSA_PROP_LITERAL 0x00000001 | |
181 | #define XTENSA_PROP_INSN 0x00000002 | |
182 | #define XTENSA_PROP_DATA 0x00000004 | |
183 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
184 | /* Instruction only properties at beginning of code. */ | |
185 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
186 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
187 | /* Instruction only properties about code. */ | |
188 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
189 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
190 | #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100 | |
191 | ||
192 | /* Branch target alignment information. This transmits information | |
193 | to the linker optimization about the priority of aligning a | |
194 | particular block for branch target alignment: None, low priority, | |
195 | high priority, or required. These only need to be checked in | |
196 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
197 | Common usage is | |
198 | ||
199 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
200 | case XTENSA_PROP_BT_ALIGN_NONE: | |
201 | case XTENSA_PROP_BT_ALIGN_LOW: | |
202 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
203 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
204 | */ | |
205 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
206 | ||
207 | /* No branch target alignment. */ | |
208 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
209 | /* Low priority branch target alignment. */ | |
210 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
211 | /* High priority branch target alignment. */ | |
212 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
213 | /* Required branch target alignment. */ | |
214 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
215 | ||
216 | #define GET_XTENSA_PROP_BT_ALIGN(flag) \ | |
217 | (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) | |
218 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ | |
219 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
220 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
221 | ||
222 | ||
223 | /* Alignment is specified in the block BEFORE the one that needs | |
224 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
225 | get the required alignment specified as a power of 2. Use | |
226 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
227 | alignment. Be careful of side effects since the SET will evaluate | |
228 | flags twice. Also, note that the SIZE of a block in the property | |
229 | table does not include the alignment size, so the alignment fill | |
230 | must be calculated to determine if two blocks are contiguous. | |
231 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
232 | possible future implementation. */ | |
233 | ||
234 | #define XTENSA_PROP_ALIGN 0x00000800 | |
235 | ||
236 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
237 | ||
238 | #define GET_XTENSA_PROP_ALIGNMENT(flag) \ | |
239 | (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) | |
240 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ | |
241 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
242 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
243 | ||
244 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
245 | ||
246 | ||
247 | /* Structure for saving instruction and alignment per-fragment data | |
248 | that will be written to the object file. This structure is | |
249 | equivalent to the actual data that will be written out to the file | |
250 | but is easier to use. We provide a conversion to file flags | |
251 | in frag_flags_to_number. */ | |
252 | ||
253 | typedef struct frag_flags_struct frag_flags; | |
254 | ||
255 | struct frag_flags_struct | |
256 | { | |
257 | /* is_literal should only be used after xtensa_move_literals. | |
258 | If you need to check if you are generating a literal fragment, | |
259 | then use the generating_literals global. */ | |
260 | ||
261 | unsigned is_literal : 1; | |
262 | unsigned is_insn : 1; | |
263 | unsigned is_data : 1; | |
264 | unsigned is_unreachable : 1; | |
265 | ||
266 | struct | |
267 | { | |
268 | unsigned is_loop_target : 1; | |
269 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
270 | unsigned bt_align_priority : 2; | |
271 | ||
272 | unsigned is_no_density : 1; | |
273 | /* no_longcalls flag does not need to be placed in the object file. */ | |
274 | /* is_specific_opcode implies no_transform. */ | |
275 | unsigned is_no_transform : 1; | |
276 | ||
277 | unsigned is_no_reorder : 1; | |
278 | ||
279 | /* Uses absolute literal addressing for l32r. */ | |
280 | unsigned is_abslit : 1; | |
281 | } insn; | |
282 | unsigned is_align : 1; | |
283 | unsigned alignment : 5; | |
284 | }; | |
285 | ||
286 | ||
287 | /* Structure for saving information about a block of property data | |
288 | for frags that have the same flags. */ | |
289 | struct xtensa_block_info_struct | |
290 | { | |
291 | segT sec; | |
292 | bfd_vma offset; | |
293 | size_t size; | |
294 | frag_flags flags; | |
295 | struct xtensa_block_info_struct *next; | |
296 | }; | |
297 | ||
e0001a05 NC |
298 | |
299 | /* Structure for saving the current state before emitting literals. */ | |
300 | typedef struct emit_state_struct | |
301 | { | |
302 | const char *name; | |
303 | segT now_seg; | |
304 | subsegT now_subseg; | |
305 | int generating_literals; | |
306 | } emit_state; | |
307 | ||
308 | ||
43cd72b9 BW |
309 | /* Opcode placement information */ |
310 | ||
311 | typedef unsigned long long bitfield; | |
312 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
313 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
314 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
315 | ||
316 | #define MAX_FORMATS 32 | |
317 | ||
318 | typedef struct op_placement_info_struct | |
319 | { | |
320 | int num_formats; | |
321 | /* A number describing how restrictive the issue is for this | |
322 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 323 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 324 | only one format but many slots in that format. The most |
c138bc38 | 325 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
326 | format. */ |
327 | int issuef; | |
43cd72b9 | 328 | xtensa_format narrowest; |
43cd72b9 | 329 | char narrowest_size; |
b2d179be | 330 | char narrowest_slot; |
43cd72b9 BW |
331 | |
332 | /* formats is a bitfield with the Nth bit set | |
333 | if the opcode fits in the Nth xtensa_format. */ | |
334 | bitfield formats; | |
335 | ||
336 | /* slots[N]'s Mth bit is set if the op fits in the | |
337 | Mth slot of the Nth xtensa_format. */ | |
338 | bitfield slots[MAX_FORMATS]; | |
339 | ||
340 | /* A count of the number of slots in a given format | |
341 | an op can fit (i.e., the bitcount of the slot field above). */ | |
342 | char slots_in_format[MAX_FORMATS]; | |
343 | ||
344 | } op_placement_info, *op_placement_info_table; | |
345 | ||
346 | op_placement_info_table op_placement_table; | |
347 | ||
348 | ||
349 | /* Extra expression types. */ | |
350 | ||
351 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
352 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
353 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
354 | ||
bbdd25a8 BW |
355 | struct suffix_reloc_map |
356 | { | |
357 | char *suffix; | |
358 | int length; | |
359 | bfd_reloc_code_real_type reloc; | |
360 | unsigned char operator; | |
361 | }; | |
362 | ||
363 | #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } | |
364 | ||
365 | static struct suffix_reloc_map suffix_relocs[] = | |
366 | { | |
367 | SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), | |
368 | SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), | |
369 | SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), | |
370 | { (char *) 0, 0, BFD_RELOC_UNUSED, 0 } | |
371 | }; | |
372 | ||
43cd72b9 | 373 | |
e0001a05 NC |
374 | /* Directives. */ |
375 | ||
376 | typedef enum | |
377 | { | |
378 | directive_none = 0, | |
379 | directive_literal, | |
380 | directive_density, | |
43cd72b9 | 381 | directive_transform, |
e0001a05 NC |
382 | directive_freeregs, |
383 | directive_longcalls, | |
43cd72b9 BW |
384 | directive_literal_prefix, |
385 | directive_schedule, | |
386 | directive_absolute_literals, | |
387 | directive_last_directive | |
e0001a05 NC |
388 | } directiveE; |
389 | ||
390 | typedef struct | |
391 | { | |
392 | const char *name; | |
393 | bfd_boolean can_be_negated; | |
394 | } directive_infoS; | |
395 | ||
396 | const directive_infoS directive_info[] = | |
397 | { | |
43cd72b9 BW |
398 | { "none", FALSE }, |
399 | { "literal", FALSE }, | |
400 | { "density", TRUE }, | |
401 | { "transform", TRUE }, | |
402 | { "freeregs", FALSE }, | |
403 | { "longcalls", TRUE }, | |
404 | { "literal_prefix", FALSE }, | |
405 | { "schedule", TRUE }, | |
406 | { "absolute-literals", TRUE } | |
e0001a05 NC |
407 | }; |
408 | ||
409 | bfd_boolean directive_state[] = | |
410 | { | |
411 | FALSE, /* none */ | |
412 | FALSE, /* literal */ | |
43cd72b9 | 413 | #if !XCHAL_HAVE_DENSITY |
e0001a05 NC |
414 | FALSE, /* density */ |
415 | #else | |
416 | TRUE, /* density */ | |
417 | #endif | |
43cd72b9 | 418 | TRUE, /* transform */ |
e0001a05 NC |
419 | FALSE, /* freeregs */ |
420 | FALSE, /* longcalls */ | |
43cd72b9 | 421 | FALSE, /* literal_prefix */ |
2caa7ca0 | 422 | FALSE, /* schedule */ |
43cd72b9 BW |
423 | #if XSHAL_USE_ABSOLUTE_LITERALS |
424 | TRUE /* absolute_literals */ | |
425 | #else | |
426 | FALSE /* absolute_literals */ | |
427 | #endif | |
e0001a05 NC |
428 | }; |
429 | ||
e0001a05 NC |
430 | |
431 | /* Directive functions. */ | |
432 | ||
7fa3d080 BW |
433 | static void xtensa_begin_directive (int); |
434 | static void xtensa_end_directive (int); | |
74869ac7 | 435 | static void xtensa_literal_prefix (void); |
7fa3d080 BW |
436 | static void xtensa_literal_position (int); |
437 | static void xtensa_literal_pseudo (int); | |
438 | static void xtensa_frequency_pseudo (int); | |
439 | static void xtensa_elf_cons (int); | |
e0001a05 | 440 | |
7fa3d080 | 441 | /* Parsing and Idiom Translation. */ |
e0001a05 | 442 | |
7fa3d080 | 443 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 444 | |
e0001a05 NC |
445 | /* Various Other Internal Functions. */ |
446 | ||
84b08ed9 BW |
447 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
448 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
449 | static void xtensa_mark_literal_pool_location (void); |
450 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
451 | static fragS *get_literal_pool_location (segT); | |
452 | static void set_literal_pool_location (segT, fragS *); | |
453 | static void xtensa_set_frag_assembly_state (fragS *); | |
454 | static void finish_vinsn (vliw_insn *); | |
455 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 456 | static int total_frag_text_expansion (fragS *); |
e0001a05 NC |
457 | |
458 | /* Alignment Functions. */ | |
459 | ||
d77b99c9 BW |
460 | static int get_text_align_power (unsigned); |
461 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 462 | static int branch_align_power (segT); |
e0001a05 NC |
463 | |
464 | /* Helpers for xtensa_relax_frag(). */ | |
465 | ||
7fa3d080 | 466 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 467 | |
b08b5071 | 468 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 469 | |
7fa3d080 BW |
470 | static unsigned get_last_insn_flags (segT, subsegT); |
471 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
472 | static float get_subseg_total_freq (segT, subsegT); |
473 | static float get_subseg_target_freq (segT, subsegT); | |
474 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
475 | |
476 | /* Segment list functions. */ | |
477 | ||
7fa3d080 BW |
478 | static void xtensa_move_literals (void); |
479 | static void xtensa_reorder_segments (void); | |
480 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
481 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
482 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
483 | static void xtensa_restore_emit_state (emit_state *); | |
74869ac7 | 484 | static segT cache_literal_section (bfd_boolean); |
e0001a05 | 485 | |
e0001a05 | 486 | /* Import from elf32-xtensa.c in BFD library. */ |
43cd72b9 | 487 | |
74869ac7 | 488 | extern asection *xtensa_get_property_section (asection *, const char *); |
e0001a05 | 489 | |
43cd72b9 BW |
490 | /* op_placement_info functions. */ |
491 | ||
7fa3d080 BW |
492 | static void init_op_placement_info_table (void); |
493 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
494 | static int xg_get_single_size (xtensa_opcode); | |
495 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 496 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 497 | |
e0001a05 | 498 | /* TInsn and IStack functions. */ |
43cd72b9 | 499 | |
7fa3d080 BW |
500 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
501 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
502 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
503 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
504 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
505 | static void tinsn_from_chars (TInsn *, char *, int); | |
506 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
507 | static int get_num_stack_text_bytes (IStack *); | |
508 | static int get_num_stack_literal_bytes (IStack *); | |
e0001a05 | 509 | |
43cd72b9 BW |
510 | /* vliw_insn functions. */ |
511 | ||
7fa3d080 BW |
512 | static void xg_init_vinsn (vliw_insn *); |
513 | static void xg_clear_vinsn (vliw_insn *); | |
514 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
515 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 516 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
517 | (vliw_insn *, char *, fragS *, bfd_boolean); |
518 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 519 | |
e0001a05 | 520 | /* Expression Utilities. */ |
43cd72b9 | 521 | |
7fa3d080 BW |
522 | bfd_boolean expr_is_const (const expressionS *); |
523 | offsetT get_expr_const (const expressionS *); | |
524 | void set_expr_const (expressionS *, offsetT); | |
525 | bfd_boolean expr_is_register (const expressionS *); | |
526 | offsetT get_expr_register (const expressionS *); | |
527 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
528 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
529 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 530 | |
9456465c BW |
531 | /* Section renaming. */ |
532 | ||
7fa3d080 | 533 | static void build_section_rename (const char *); |
e0001a05 | 534 | |
e0001a05 NC |
535 | |
536 | /* ISA imported from bfd. */ | |
537 | extern xtensa_isa xtensa_default_isa; | |
538 | ||
539 | extern int target_big_endian; | |
540 | ||
541 | static xtensa_opcode xtensa_addi_opcode; | |
542 | static xtensa_opcode xtensa_addmi_opcode; | |
543 | static xtensa_opcode xtensa_call0_opcode; | |
544 | static xtensa_opcode xtensa_call4_opcode; | |
545 | static xtensa_opcode xtensa_call8_opcode; | |
546 | static xtensa_opcode xtensa_call12_opcode; | |
547 | static xtensa_opcode xtensa_callx0_opcode; | |
548 | static xtensa_opcode xtensa_callx4_opcode; | |
549 | static xtensa_opcode xtensa_callx8_opcode; | |
550 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 551 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 552 | static xtensa_opcode xtensa_entry_opcode; |
43cd72b9 BW |
553 | static xtensa_opcode xtensa_movi_opcode; |
554 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 555 | static xtensa_opcode xtensa_isync_opcode; |
e0001a05 | 556 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 557 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
558 | static xtensa_opcode xtensa_loop_opcode; |
559 | static xtensa_opcode xtensa_loopnez_opcode; | |
560 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 561 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
562 | static xtensa_opcode xtensa_nop_n_opcode; |
563 | static xtensa_opcode xtensa_or_opcode; | |
564 | static xtensa_opcode xtensa_ret_opcode; | |
565 | static xtensa_opcode xtensa_ret_n_opcode; | |
566 | static xtensa_opcode xtensa_retw_opcode; | |
567 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 568 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 NC |
569 | static xtensa_opcode xtensa_waiti_opcode; |
570 | ||
571 | \f | |
572 | /* Command-line Options. */ | |
573 | ||
574 | bfd_boolean use_literal_section = TRUE; | |
575 | static bfd_boolean align_targets = TRUE; | |
43cd72b9 | 576 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 577 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
578 | static bfd_boolean workaround_a0_b_retw = FALSE; |
579 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
580 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 581 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 582 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 583 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 584 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
e0001a05 | 585 | |
43cd72b9 BW |
586 | /* When workaround_short_loops is TRUE, all loops with early exits must |
587 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
588 | to the workaround_short_loop flag. In addition to the | |
589 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
590 | must have at least 3 instructions. */ | |
e0001a05 | 591 | |
43cd72b9 | 592 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 593 | |
7fa3d080 BW |
594 | |
595 | static void | |
596 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
597 | { | |
598 | if (earliest > latest) | |
599 | as_fatal (_("illegal range of target hardware versions")); | |
600 | ||
601 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
602 | if (earliest < 105000 || latest < 105000) | |
603 | { | |
604 | workaround_a0_b_retw |= TRUE; | |
605 | workaround_b_j_loop_end |= TRUE; | |
606 | workaround_short_loop |= TRUE; | |
607 | workaround_close_loop_end |= TRUE; | |
608 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 609 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
610 | } |
611 | } | |
612 | ||
613 | ||
e0001a05 NC |
614 | enum |
615 | { | |
616 | option_density = OPTION_MD_BASE, | |
617 | option_no_density, | |
618 | ||
619 | option_relax, | |
620 | option_no_relax, | |
621 | ||
43cd72b9 BW |
622 | option_link_relax, |
623 | option_no_link_relax, | |
624 | ||
e0001a05 NC |
625 | option_generics, |
626 | option_no_generics, | |
627 | ||
43cd72b9 BW |
628 | option_transform, |
629 | option_no_transform, | |
630 | ||
e0001a05 NC |
631 | option_text_section_literals, |
632 | option_no_text_section_literals, | |
633 | ||
43cd72b9 BW |
634 | option_absolute_literals, |
635 | option_no_absolute_literals, | |
636 | ||
e0001a05 NC |
637 | option_align_targets, |
638 | option_no_align_targets, | |
639 | ||
43cd72b9 | 640 | option_warn_unaligned_targets, |
e0001a05 NC |
641 | |
642 | option_longcalls, | |
643 | option_no_longcalls, | |
644 | ||
645 | option_workaround_a0_b_retw, | |
646 | option_no_workaround_a0_b_retw, | |
647 | ||
648 | option_workaround_b_j_loop_end, | |
649 | option_no_workaround_b_j_loop_end, | |
650 | ||
651 | option_workaround_short_loop, | |
652 | option_no_workaround_short_loop, | |
653 | ||
654 | option_workaround_all_short_loops, | |
655 | option_no_workaround_all_short_loops, | |
656 | ||
657 | option_workaround_close_loop_end, | |
658 | option_no_workaround_close_loop_end, | |
659 | ||
660 | option_no_workarounds, | |
661 | ||
e0001a05 | 662 | option_rename_section_name, |
e0001a05 | 663 | |
43cd72b9 BW |
664 | option_prefer_l32r, |
665 | option_prefer_const16, | |
666 | ||
667 | option_target_hardware | |
e0001a05 NC |
668 | }; |
669 | ||
670 | const char *md_shortopts = ""; | |
671 | ||
672 | struct option md_longopts[] = | |
673 | { | |
43cd72b9 BW |
674 | { "density", no_argument, NULL, option_density }, |
675 | { "no-density", no_argument, NULL, option_no_density }, | |
676 | ||
677 | /* Both "relax" and "generics" are deprecated and treated as equivalent | |
678 | to the "transform" option. */ | |
679 | { "relax", no_argument, NULL, option_relax }, | |
680 | { "no-relax", no_argument, NULL, option_no_relax }, | |
681 | { "generics", no_argument, NULL, option_generics }, | |
682 | { "no-generics", no_argument, NULL, option_no_generics }, | |
683 | ||
684 | { "transform", no_argument, NULL, option_transform }, | |
685 | { "no-transform", no_argument, NULL, option_no_transform }, | |
686 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
687 | { "no-text-section-literals", no_argument, NULL, | |
688 | option_no_text_section_literals }, | |
689 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
690 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
691 | /* This option was changed from -align-target to -target-align |
692 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 693 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
694 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
695 | { "warn-unaligned-targets", no_argument, NULL, | |
696 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
697 | { "longcalls", no_argument, NULL, option_longcalls }, |
698 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
699 | ||
700 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
701 | option_no_workaround_a0_b_retw }, | |
702 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 703 | |
43cd72b9 BW |
704 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
705 | option_no_workaround_b_j_loop_end }, | |
706 | { "workaround-b-j-loop-end", no_argument, NULL, | |
707 | option_workaround_b_j_loop_end }, | |
e0001a05 | 708 | |
43cd72b9 BW |
709 | { "no-workaround-short-loops", no_argument, NULL, |
710 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
711 | { "workaround-short-loops", no_argument, NULL, |
712 | option_workaround_short_loop }, | |
e0001a05 | 713 | |
43cd72b9 BW |
714 | { "no-workaround-all-short-loops", no_argument, NULL, |
715 | option_no_workaround_all_short_loops }, | |
716 | { "workaround-all-short-loop", no_argument, NULL, | |
717 | option_workaround_all_short_loops }, | |
718 | ||
719 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
720 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
721 | ||
722 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
723 | ||
724 | { "no-workaround-close-loop-end", no_argument, NULL, | |
725 | option_no_workaround_close_loop_end }, | |
726 | { "workaround-close-loop-end", no_argument, NULL, | |
727 | option_workaround_close_loop_end }, | |
e0001a05 | 728 | |
7fa3d080 | 729 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 730 | |
43cd72b9 BW |
731 | { "link-relax", no_argument, NULL, option_link_relax }, |
732 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
733 | ||
734 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
735 | ||
736 | { NULL, no_argument, NULL, 0 } | |
e0001a05 NC |
737 | }; |
738 | ||
739 | size_t md_longopts_size = sizeof md_longopts; | |
740 | ||
741 | ||
742 | int | |
7fa3d080 | 743 | md_parse_option (int c, char *arg) |
e0001a05 NC |
744 | { |
745 | switch (c) | |
746 | { | |
747 | case option_density: | |
43cd72b9 | 748 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
749 | return 1; |
750 | case option_no_density: | |
43cd72b9 | 751 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 752 | return 1; |
43cd72b9 BW |
753 | case option_link_relax: |
754 | linkrelax = 1; | |
e0001a05 | 755 | return 1; |
43cd72b9 BW |
756 | case option_no_link_relax: |
757 | linkrelax = 0; | |
e0001a05 | 758 | return 1; |
43cd72b9 BW |
759 | case option_generics: |
760 | as_warn (_("--generics is deprecated; use --transform instead")); | |
761 | return md_parse_option (option_transform, arg); | |
762 | case option_no_generics: | |
763 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
764 | return md_parse_option (option_no_transform, arg); | |
765 | case option_relax: | |
766 | as_warn (_("--relax is deprecated; use --transform instead")); | |
767 | return md_parse_option (option_transform, arg); | |
768 | case option_no_relax: | |
769 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
770 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
771 | case option_longcalls: |
772 | directive_state[directive_longcalls] = TRUE; | |
773 | return 1; | |
774 | case option_no_longcalls: | |
775 | directive_state[directive_longcalls] = FALSE; | |
776 | return 1; | |
777 | case option_text_section_literals: | |
778 | use_literal_section = FALSE; | |
779 | return 1; | |
780 | case option_no_text_section_literals: | |
781 | use_literal_section = TRUE; | |
782 | return 1; | |
43cd72b9 BW |
783 | case option_absolute_literals: |
784 | if (!absolute_literals_supported) | |
785 | { | |
786 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
787 | return 0; | |
788 | } | |
789 | directive_state[directive_absolute_literals] = TRUE; | |
790 | return 1; | |
791 | case option_no_absolute_literals: | |
792 | directive_state[directive_absolute_literals] = FALSE; | |
793 | return 1; | |
794 | ||
e0001a05 NC |
795 | case option_workaround_a0_b_retw: |
796 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
797 | return 1; |
798 | case option_no_workaround_a0_b_retw: | |
799 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
800 | return 1; |
801 | case option_workaround_b_j_loop_end: | |
802 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
803 | return 1; |
804 | case option_no_workaround_b_j_loop_end: | |
805 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
806 | return 1; |
807 | ||
808 | case option_workaround_short_loop: | |
809 | workaround_short_loop = TRUE; | |
e0001a05 NC |
810 | return 1; |
811 | case option_no_workaround_short_loop: | |
812 | workaround_short_loop = FALSE; | |
e0001a05 NC |
813 | return 1; |
814 | ||
815 | case option_workaround_all_short_loops: | |
816 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
817 | return 1; |
818 | case option_no_workaround_all_short_loops: | |
819 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
820 | return 1; |
821 | ||
822 | case option_workaround_close_loop_end: | |
823 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
824 | return 1; |
825 | case option_no_workaround_close_loop_end: | |
826 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
827 | return 1; |
828 | ||
829 | case option_no_workarounds: | |
830 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 831 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 832 | workaround_short_loop = FALSE; |
e0001a05 | 833 | workaround_all_short_loops = FALSE; |
e0001a05 | 834 | workaround_close_loop_end = FALSE; |
e0001a05 | 835 | return 1; |
43cd72b9 | 836 | |
e0001a05 NC |
837 | case option_align_targets: |
838 | align_targets = TRUE; | |
839 | return 1; | |
840 | case option_no_align_targets: | |
841 | align_targets = FALSE; | |
842 | return 1; | |
843 | ||
43cd72b9 BW |
844 | case option_warn_unaligned_targets: |
845 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
846 | return 1; |
847 | ||
e0001a05 NC |
848 | case option_rename_section_name: |
849 | build_section_rename (arg); | |
850 | return 1; | |
e0001a05 NC |
851 | |
852 | case 'Q': | |
853 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
854 | should be emitted or not. FIXME: Not implemented. */ | |
855 | return 1; | |
c138bc38 | 856 | |
43cd72b9 BW |
857 | case option_prefer_l32r: |
858 | if (prefer_const16) | |
859 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
860 | prefer_l32r = 1; | |
861 | return 1; | |
862 | ||
863 | case option_prefer_const16: | |
864 | if (prefer_l32r) | |
865 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
866 | prefer_const16 = 1; | |
867 | return 1; | |
868 | ||
c138bc38 | 869 | case option_target_hardware: |
43cd72b9 BW |
870 | { |
871 | int earliest, latest = 0; | |
872 | if (*arg == 0 || *arg == '-') | |
873 | as_fatal (_("invalid target hardware version")); | |
874 | ||
875 | earliest = strtol (arg, &arg, 0); | |
876 | ||
877 | if (*arg == 0) | |
878 | latest = earliest; | |
879 | else if (*arg == '-') | |
880 | { | |
881 | if (*++arg == 0) | |
882 | as_fatal (_("invalid target hardware version")); | |
883 | latest = strtol (arg, &arg, 0); | |
884 | } | |
885 | if (*arg != 0) | |
886 | as_fatal (_("invalid target hardware version")); | |
887 | ||
888 | xtensa_setup_hw_workarounds (earliest, latest); | |
889 | return 1; | |
890 | } | |
891 | ||
892 | case option_transform: | |
893 | /* This option has no affect other than to use the defaults, | |
894 | which are already set. */ | |
895 | return 1; | |
896 | ||
897 | case option_no_transform: | |
898 | /* This option turns off all transformations of any kind. | |
899 | However, because we want to preserve the state of other | |
900 | directives, we only change its own field. Thus, before | |
901 | you perform any transformation, always check if transform | |
902 | is available. If you use the functions we provide for this | |
903 | purpose, you will be ok. */ | |
904 | directive_state[directive_transform] = FALSE; | |
905 | return 1; | |
906 | ||
e0001a05 NC |
907 | default: |
908 | return 0; | |
909 | } | |
910 | } | |
911 | ||
912 | ||
913 | void | |
7fa3d080 | 914 | md_show_usage (FILE *stream) |
e0001a05 | 915 | { |
43cd72b9 BW |
916 | fputs ("\n\ |
917 | Xtensa options:\n\ | |
9456465c BW |
918 | --[no-]text-section-literals\n\ |
919 | [Do not] put literals in the text section\n\ | |
920 | --[no-]absolute-literals\n\ | |
921 | [Do not] default to use non-PC-relative literals\n\ | |
922 | --[no-]target-align [Do not] try to align branch targets\n\ | |
923 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
924 | --[no-]transform [Do not] transform instructions\n\ | |
925 | --rename-section old=new Rename section 'old' to 'new'\n", stream); | |
e0001a05 NC |
926 | } |
927 | ||
7fa3d080 BW |
928 | \f |
929 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
930 | |
931 | static void | |
7fa3d080 | 932 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 933 | { |
7fa3d080 | 934 | sym_list *l; |
43cd72b9 | 935 | |
7fa3d080 BW |
936 | if (!free_insn_labels) |
937 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
938 | else | |
43cd72b9 | 939 | { |
7fa3d080 BW |
940 | l = free_insn_labels; |
941 | free_insn_labels = l->next; | |
942 | } | |
943 | ||
944 | l->sym = sym; | |
945 | l->next = insn_labels; | |
946 | insn_labels = l; | |
947 | } | |
948 | ||
949 | ||
950 | static void | |
951 | xtensa_clear_insn_labels (void) | |
952 | { | |
953 | sym_list **pl; | |
954 | ||
955 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
956 | ; | |
957 | *pl = insn_labels; | |
958 | insn_labels = NULL; | |
959 | } | |
960 | ||
961 | ||
c138bc38 BW |
962 | /* The "loops_ok" argument is provided to allow ignoring labels that |
963 | define loop ends. This fixes a bug where the NOPs to align a | |
7fa3d080 BW |
964 | loop opcode were included in a previous zero-cost loop: |
965 | ||
966 | loop a0, loopend | |
967 | <loop1 body> | |
968 | loopend: | |
969 | ||
970 | loop a2, loopend2 | |
971 | <loop2 body> | |
972 | ||
973 | would become: | |
974 | ||
975 | loop a0, loopend | |
976 | <loop1 body> | |
977 | nop.n <===== bad! | |
978 | loopend: | |
979 | ||
980 | loop a2, loopend2 | |
981 | <loop2 body> | |
982 | ||
983 | This argument is used to prevent moving the NOP to before the | |
984 | loop-end label, which is what you want in this special case. */ | |
985 | ||
986 | static void | |
987 | xtensa_move_labels (fragS *new_frag, valueT new_offset, bfd_boolean loops_ok) | |
988 | { | |
989 | sym_list *lit; | |
990 | ||
991 | for (lit = insn_labels; lit; lit = lit->next) | |
992 | { | |
993 | symbolS *lit_sym = lit->sym; | |
994 | if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target) | |
995 | { | |
996 | S_SET_VALUE (lit_sym, new_offset); | |
997 | symbol_set_frag (lit_sym, new_frag); | |
998 | } | |
43cd72b9 BW |
999 | } |
1000 | } | |
1001 | ||
e0001a05 NC |
1002 | \f |
1003 | /* Directive data and functions. */ | |
1004 | ||
1005 | typedef struct state_stackS_struct | |
1006 | { | |
1007 | directiveE directive; | |
1008 | bfd_boolean negated; | |
1009 | bfd_boolean old_state; | |
1010 | const char *file; | |
1011 | unsigned int line; | |
1012 | const void *datum; | |
1013 | struct state_stackS_struct *prev; | |
1014 | } state_stackS; | |
1015 | ||
1016 | state_stackS *directive_state_stack; | |
1017 | ||
1018 | const pseudo_typeS md_pseudo_table[] = | |
1019 | { | |
43cd72b9 BW |
1020 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1021 | { "literal_position", xtensa_literal_position, 0 }, | |
1022 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1023 | { "long", xtensa_elf_cons, 4 }, | |
1024 | { "word", xtensa_elf_cons, 4 }, | |
1025 | { "short", xtensa_elf_cons, 2 }, | |
1026 | { "begin", xtensa_begin_directive, 0 }, | |
1027 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1028 | { "literal", xtensa_literal_pseudo, 0 }, |
1029 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1030 | { NULL, 0, 0 }, | |
e0001a05 NC |
1031 | }; |
1032 | ||
1033 | ||
7fa3d080 BW |
1034 | static bfd_boolean |
1035 | use_transform (void) | |
e0001a05 | 1036 | { |
43cd72b9 BW |
1037 | /* After md_end, you should be checking frag by frag, rather |
1038 | than state directives. */ | |
1039 | assert (!past_xtensa_end); | |
1040 | return directive_state[directive_transform]; | |
e0001a05 NC |
1041 | } |
1042 | ||
1043 | ||
7fa3d080 BW |
1044 | static bfd_boolean |
1045 | do_align_targets (void) | |
e0001a05 | 1046 | { |
7b1cc377 BW |
1047 | /* Do not use this function after md_end; just look at align_targets |
1048 | instead. There is no target-align directive, so alignment is either | |
1049 | enabled for all frags or not done at all. */ | |
43cd72b9 BW |
1050 | assert (!past_xtensa_end); |
1051 | return align_targets && use_transform (); | |
e0001a05 NC |
1052 | } |
1053 | ||
1054 | ||
1055 | static void | |
7fa3d080 | 1056 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 NC |
1057 | { |
1058 | char *file; | |
1059 | unsigned int line; | |
1060 | state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); | |
1061 | ||
1062 | as_where (&file, &line); | |
1063 | ||
1064 | stack->directive = directive; | |
1065 | stack->negated = negated; | |
1066 | stack->old_state = directive_state[directive]; | |
1067 | stack->file = file; | |
1068 | stack->line = line; | |
1069 | stack->datum = datum; | |
1070 | stack->prev = directive_state_stack; | |
1071 | directive_state_stack = stack; | |
1072 | ||
1073 | directive_state[directive] = !negated; | |
1074 | } | |
1075 | ||
7fa3d080 | 1076 | |
e0001a05 | 1077 | static void |
7fa3d080 BW |
1078 | directive_pop (directiveE *directive, |
1079 | bfd_boolean *negated, | |
1080 | const char **file, | |
1081 | unsigned int *line, | |
1082 | const void **datum) | |
e0001a05 NC |
1083 | { |
1084 | state_stackS *top = directive_state_stack; | |
1085 | ||
1086 | if (!directive_state_stack) | |
1087 | { | |
1088 | as_bad (_("unmatched end directive")); | |
1089 | *directive = directive_none; | |
1090 | return; | |
1091 | } | |
1092 | ||
1093 | directive_state[directive_state_stack->directive] = top->old_state; | |
1094 | *directive = top->directive; | |
1095 | *negated = top->negated; | |
1096 | *file = top->file; | |
1097 | *line = top->line; | |
1098 | *datum = top->datum; | |
1099 | directive_state_stack = top->prev; | |
1100 | free (top); | |
1101 | } | |
1102 | ||
1103 | ||
1104 | static void | |
7fa3d080 | 1105 | directive_balance (void) |
e0001a05 NC |
1106 | { |
1107 | while (directive_state_stack) | |
1108 | { | |
1109 | directiveE directive; | |
1110 | bfd_boolean negated; | |
1111 | const char *file; | |
1112 | unsigned int line; | |
1113 | const void *datum; | |
1114 | ||
1115 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1116 | as_warn_where ((char *) file, line, | |
1117 | _(".begin directive with no matching .end directive")); | |
1118 | } | |
1119 | } | |
1120 | ||
1121 | ||
1122 | static bfd_boolean | |
7fa3d080 | 1123 | inside_directive (directiveE dir) |
e0001a05 NC |
1124 | { |
1125 | state_stackS *top = directive_state_stack; | |
1126 | ||
1127 | while (top && top->directive != dir) | |
1128 | top = top->prev; | |
1129 | ||
1130 | return (top != NULL); | |
1131 | } | |
1132 | ||
1133 | ||
1134 | static void | |
7fa3d080 | 1135 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1136 | { |
1137 | int len; | |
1138 | unsigned i; | |
43cd72b9 | 1139 | char *directive_string; |
e0001a05 NC |
1140 | |
1141 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1142 | *negated = FALSE; | |
1143 | else | |
1144 | { | |
1145 | *negated = TRUE; | |
1146 | input_line_pointer += 3; | |
1147 | } | |
1148 | ||
1149 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1150 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1151 | ||
1152 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1153 | equivalent to .begin [no-]transform. We should remove it when | |
1154 | we stop accepting those options. */ | |
c138bc38 | 1155 | |
43cd72b9 BW |
1156 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1157 | { | |
1158 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1159 | directive_string = "transform"; | |
1160 | } | |
1161 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1162 | { | |
1163 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1164 | directive_string = "transform"; | |
c138bc38 | 1165 | } |
43cd72b9 BW |
1166 | else |
1167 | directive_string = input_line_pointer; | |
e0001a05 NC |
1168 | |
1169 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1170 | { | |
43cd72b9 | 1171 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1172 | { |
1173 | input_line_pointer += len; | |
1174 | *directive = (directiveE) i; | |
1175 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1176 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1177 | directive_info[i].name); |
1178 | return; | |
1179 | } | |
1180 | } | |
1181 | ||
1182 | as_bad (_("unknown directive")); | |
1183 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1184 | } | |
1185 | ||
1186 | ||
1187 | static void | |
7fa3d080 | 1188 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1189 | { |
1190 | directiveE directive; | |
1191 | bfd_boolean negated; | |
1192 | emit_state *state; | |
e0001a05 NC |
1193 | lit_state *ls; |
1194 | ||
1195 | get_directive (&directive, &negated); | |
1196 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1197 | { | |
1198 | discard_rest_of_line (); | |
1199 | return; | |
1200 | } | |
1201 | ||
43cd72b9 BW |
1202 | if (cur_vinsn.inside_bundle) |
1203 | as_bad (_("directives are not valid inside bundles")); | |
1204 | ||
e0001a05 NC |
1205 | switch (directive) |
1206 | { | |
1207 | case directive_literal: | |
82e7541d BW |
1208 | if (!inside_directive (directive_literal)) |
1209 | { | |
1210 | /* Previous labels go with whatever follows this directive, not with | |
1211 | the literal, so save them now. */ | |
1212 | saved_insn_labels = insn_labels; | |
1213 | insn_labels = NULL; | |
1214 | } | |
43cd72b9 | 1215 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
e0001a05 NC |
1216 | state = (emit_state *) xmalloc (sizeof (emit_state)); |
1217 | xtensa_switch_to_literal_fragment (state); | |
1218 | directive_push (directive_literal, negated, state); | |
1219 | break; | |
1220 | ||
1221 | case directive_literal_prefix: | |
c138bc38 | 1222 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1223 | might produce a literal. */ |
1224 | md_flush_pending_output (); | |
e0001a05 NC |
1225 | /* Check to see if the current fragment is a literal |
1226 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1227 | if (generating_literals) |
e0001a05 NC |
1228 | { |
1229 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1230 | return; | |
1231 | } | |
1232 | ||
1233 | /* Allocate the literal state for this section and push | |
1234 | onto the directive stack. */ | |
1235 | ls = xmalloc (sizeof (lit_state)); | |
1236 | assert (ls); | |
1237 | ||
1238 | *ls = default_lit_sections; | |
e0001a05 NC |
1239 | directive_push (directive_literal_prefix, negated, ls); |
1240 | ||
e0001a05 | 1241 | /* Process the new prefix. */ |
74869ac7 | 1242 | xtensa_literal_prefix (); |
e0001a05 NC |
1243 | break; |
1244 | ||
1245 | case directive_freeregs: | |
1246 | /* This information is currently unused, but we'll accept the statement | |
1247 | and just discard the rest of the line. This won't check the syntax, | |
1248 | but it will accept every correct freeregs directive. */ | |
1249 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1250 | directive_push (directive_freeregs, negated, 0); | |
1251 | break; | |
1252 | ||
43cd72b9 BW |
1253 | case directive_schedule: |
1254 | md_flush_pending_output (); | |
1255 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1256 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1257 | directive_push (directive_schedule, negated, 0); | |
1258 | xtensa_set_frag_assembly_state (frag_now); | |
1259 | break; | |
1260 | ||
e0001a05 | 1261 | case directive_density: |
43cd72b9 BW |
1262 | as_warn (_(".begin [no-]density is ignored")); |
1263 | break; | |
1264 | ||
1265 | case directive_absolute_literals: | |
1266 | md_flush_pending_output (); | |
1267 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1268 | { |
43cd72b9 | 1269 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1270 | break; |
1271 | } | |
43cd72b9 BW |
1272 | xtensa_set_frag_assembly_state (frag_now); |
1273 | directive_push (directive, negated, 0); | |
1274 | break; | |
e0001a05 NC |
1275 | |
1276 | default: | |
43cd72b9 BW |
1277 | md_flush_pending_output (); |
1278 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1279 | directive_push (directive, negated, 0); |
1280 | break; | |
1281 | } | |
1282 | ||
1283 | demand_empty_rest_of_line (); | |
1284 | } | |
1285 | ||
1286 | ||
1287 | static void | |
7fa3d080 | 1288 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1289 | { |
1290 | directiveE begin_directive, end_directive; | |
1291 | bfd_boolean begin_negated, end_negated; | |
1292 | const char *file; | |
1293 | unsigned int line; | |
1294 | emit_state *state; | |
43cd72b9 | 1295 | emit_state **state_ptr; |
e0001a05 NC |
1296 | lit_state *s; |
1297 | ||
43cd72b9 BW |
1298 | if (cur_vinsn.inside_bundle) |
1299 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1300 | |
e0001a05 | 1301 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1302 | |
1303 | md_flush_pending_output (); | |
1304 | ||
1305 | switch (end_directive) | |
e0001a05 | 1306 | { |
43cd72b9 | 1307 | case (directiveE) XTENSA_UNDEFINED: |
e0001a05 NC |
1308 | discard_rest_of_line (); |
1309 | return; | |
e0001a05 | 1310 | |
43cd72b9 BW |
1311 | case directive_density: |
1312 | as_warn (_(".end [no-]density is ignored")); | |
e0001a05 | 1313 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1314 | break; |
1315 | ||
1316 | case directive_absolute_literals: | |
1317 | if (!absolute_literals_supported && !end_negated) | |
1318 | { | |
1319 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1320 | demand_empty_rest_of_line (); | |
1321 | return; | |
1322 | } | |
1323 | break; | |
1324 | ||
1325 | default: | |
1326 | break; | |
e0001a05 NC |
1327 | } |
1328 | ||
43cd72b9 | 1329 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1330 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1331 | (const void **) state_ptr); |
e0001a05 NC |
1332 | |
1333 | if (begin_directive != directive_none) | |
1334 | { | |
1335 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1336 | { | |
1337 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1338 | begin_negated ? "no-" : "", | |
1339 | directive_info[begin_directive].name, file, line); | |
1340 | } | |
1341 | else | |
1342 | { | |
1343 | switch (end_directive) | |
1344 | { | |
1345 | case directive_literal: | |
1346 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1347 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1348 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1349 | free (state); |
82e7541d BW |
1350 | if (!inside_directive (directive_literal)) |
1351 | { | |
1352 | /* Restore the list of current labels. */ | |
1353 | xtensa_clear_insn_labels (); | |
1354 | insn_labels = saved_insn_labels; | |
1355 | } | |
e0001a05 NC |
1356 | break; |
1357 | ||
e0001a05 NC |
1358 | case directive_literal_prefix: |
1359 | /* Restore the default collection sections from saved state. */ | |
1360 | s = (lit_state *) state; | |
1361 | assert (s); | |
e8247da7 | 1362 | default_lit_sections = *s; |
e0001a05 | 1363 | |
74869ac7 BW |
1364 | /* Free the state storage. */ |
1365 | free (s->lit_prefix); | |
e0001a05 NC |
1366 | free (s); |
1367 | break; | |
1368 | ||
43cd72b9 BW |
1369 | case directive_schedule: |
1370 | case directive_freeregs: | |
1371 | break; | |
1372 | ||
e0001a05 | 1373 | default: |
43cd72b9 | 1374 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1375 | break; |
1376 | } | |
1377 | } | |
1378 | } | |
1379 | ||
1380 | demand_empty_rest_of_line (); | |
1381 | } | |
1382 | ||
1383 | ||
1384 | /* Place an aligned literal fragment at the current location. */ | |
1385 | ||
1386 | static void | |
7fa3d080 | 1387 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1388 | { |
43cd72b9 BW |
1389 | md_flush_pending_output (); |
1390 | ||
e0001a05 NC |
1391 | if (inside_directive (directive_literal)) |
1392 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1393 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1394 | |
1395 | demand_empty_rest_of_line (); | |
82e7541d | 1396 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1397 | } |
1398 | ||
1399 | ||
43cd72b9 | 1400 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1401 | |
1402 | static void | |
7fa3d080 | 1403 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1404 | { |
1405 | emit_state state; | |
1745fcba | 1406 | char *p, *base_name; |
e0001a05 | 1407 | char c; |
e0001a05 NC |
1408 | segT dest_seg; |
1409 | ||
82e7541d BW |
1410 | if (inside_directive (directive_literal)) |
1411 | { | |
1412 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1413 | ignore_rest_of_line (); | |
1414 | return; | |
1415 | } | |
1416 | ||
43cd72b9 BW |
1417 | md_flush_pending_output (); |
1418 | ||
82e7541d BW |
1419 | /* Previous labels go with whatever follows this directive, not with |
1420 | the literal, so save them now. */ | |
1421 | saved_insn_labels = insn_labels; | |
1422 | insn_labels = NULL; | |
1423 | ||
e0001a05 NC |
1424 | /* If we are using text-section literals, then this is the right value... */ |
1425 | dest_seg = now_seg; | |
1426 | ||
1427 | base_name = input_line_pointer; | |
1428 | ||
1429 | xtensa_switch_to_literal_fragment (&state); | |
1430 | ||
43cd72b9 | 1431 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1432 | need to put them in the section we just switched to. */ |
43cd72b9 | 1433 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1434 | dest_seg = now_seg; |
1435 | ||
43cd72b9 BW |
1436 | /* All literals are aligned to four-byte boundaries. */ |
1437 | frag_align (2, 0, 0); | |
1438 | record_alignment (now_seg, 2); | |
e0001a05 NC |
1439 | |
1440 | c = get_symbol_end (); | |
1441 | /* Just after name is now '\0'. */ | |
1442 | p = input_line_pointer; | |
1443 | *p = c; | |
1444 | SKIP_WHITESPACE (); | |
1445 | ||
1446 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1447 | { | |
1448 | as_bad (_("expected comma or colon after symbol name; " | |
1449 | "rest of line ignored")); | |
1450 | ignore_rest_of_line (); | |
1451 | xtensa_restore_emit_state (&state); | |
1452 | return; | |
1453 | } | |
1454 | *p = 0; | |
1455 | ||
e0001a05 | 1456 | colon (base_name); |
e0001a05 | 1457 | |
e0001a05 | 1458 | *p = c; |
43cd72b9 | 1459 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1460 | |
43cd72b9 | 1461 | xtensa_elf_cons (4); |
e0001a05 NC |
1462 | |
1463 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1464 | |
1465 | /* Restore the list of current labels. */ | |
1466 | xtensa_clear_insn_labels (); | |
1467 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1468 | } |
1469 | ||
1470 | ||
1471 | static void | |
74869ac7 | 1472 | xtensa_literal_prefix (void) |
e0001a05 | 1473 | { |
74869ac7 BW |
1474 | char *name; |
1475 | int len; | |
1476 | ||
1477 | /* Parse the new prefix from the input_line_pointer. */ | |
1478 | SKIP_WHITESPACE (); | |
1479 | len = strspn (input_line_pointer, | |
1480 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1481 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
e0001a05 NC |
1482 | |
1483 | /* Get a null-terminated copy of the name. */ | |
1484 | name = xmalloc (len + 1); | |
1485 | assert (name); | |
74869ac7 | 1486 | strncpy (name, input_line_pointer, len); |
e0001a05 NC |
1487 | name[len] = 0; |
1488 | ||
74869ac7 BW |
1489 | /* Skip the name in the input line. */ |
1490 | input_line_pointer += len; | |
43cd72b9 | 1491 | |
74869ac7 | 1492 | default_lit_sections.lit_prefix = name; |
43cd72b9 | 1493 | |
74869ac7 | 1494 | /* Clear cached literal sections, since the prefix has changed. */ |
43cd72b9 BW |
1495 | default_lit_sections.lit_seg = NULL; |
1496 | default_lit_sections.lit4_seg = NULL; | |
43cd72b9 BW |
1497 | } |
1498 | ||
1499 | ||
1500 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1501 | ||
1502 | static void | |
7fa3d080 | 1503 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1504 | { |
1505 | float fall_through_f, target_f; | |
43cd72b9 BW |
1506 | |
1507 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1508 | if (fall_through_f < 0) | |
1509 | { | |
1510 | as_bad (_("fall through frequency must be greater than 0")); | |
1511 | ignore_rest_of_line (); | |
1512 | return; | |
1513 | } | |
1514 | ||
1515 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1516 | if (target_f < 0) | |
1517 | { | |
1518 | as_bad (_("branch target frequency must be greater than 0")); | |
1519 | ignore_rest_of_line (); | |
1520 | return; | |
1521 | } | |
1522 | ||
b08b5071 | 1523 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1524 | |
1525 | demand_empty_rest_of_line (); | |
1526 | } | |
1527 | ||
1528 | ||
1529 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1530 | Clobbers input_line_pointer, checks end-of-line. */ | |
1531 | ||
1532 | static void | |
7fa3d080 | 1533 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1534 | { |
1535 | expressionS exp; | |
1536 | bfd_reloc_code_real_type reloc; | |
1537 | ||
1538 | md_flush_pending_output (); | |
1539 | ||
1540 | if (cur_vinsn.inside_bundle) | |
1541 | as_bad (_("directives are not valid inside bundles")); | |
1542 | ||
1543 | if (is_it_end_of_statement ()) | |
1544 | { | |
1545 | demand_empty_rest_of_line (); | |
1546 | return; | |
1547 | } | |
1548 | ||
1549 | do | |
1550 | { | |
1551 | expression (&exp); | |
1552 | if (exp.X_op == O_symbol | |
1553 | && *input_line_pointer == '@' | |
1554 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1555 | != BFD_RELOC_NONE)) | |
1556 | { | |
1557 | reloc_howto_type *reloc_howto = | |
1558 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1559 | ||
1560 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1561 | as_bad (_("unsupported relocation")); | |
1562 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1563 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1564 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1565 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1566 | as_bad (_("opcode-specific %s relocation used outside " | |
1567 | "an instruction"), reloc_howto->name); | |
1568 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
1569 | as_bad (_("%s relocations do not fit in %d bytes"), | |
1570 | reloc_howto->name, nbytes); | |
1571 | else | |
1572 | { | |
1573 | char *p = frag_more ((int) nbytes); | |
1574 | xtensa_set_frag_assembly_state (frag_now); | |
1575 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1576 | nbytes, &exp, 0, reloc); | |
1577 | } | |
1578 | } | |
1579 | else | |
1580 | emit_expr (&exp, (unsigned int) nbytes); | |
1581 | } | |
1582 | while (*input_line_pointer++ == ','); | |
1583 | ||
1584 | input_line_pointer--; /* Put terminator back into stream. */ | |
1585 | demand_empty_rest_of_line (); | |
1586 | } | |
1587 | ||
7fa3d080 BW |
1588 | \f |
1589 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1590 | |
1591 | /* Parse @plt, etc. and return the desired relocation. */ | |
1592 | static bfd_reloc_code_real_type | |
7fa3d080 | 1593 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 | 1594 | { |
43cd72b9 BW |
1595 | char ident[20]; |
1596 | char *str = *str_p; | |
1597 | char *str2; | |
1598 | int ch; | |
1599 | int len; | |
bbdd25a8 | 1600 | struct suffix_reloc_map *ptr; |
43cd72b9 BW |
1601 | |
1602 | if (*str++ != '@') | |
1603 | return BFD_RELOC_NONE; | |
1604 | ||
1605 | for (ch = *str, str2 = ident; | |
1606 | (str2 < ident + sizeof (ident) - 1 | |
1607 | && (ISALNUM (ch) || ch == '@')); | |
1608 | ch = *++str) | |
1609 | { | |
1610 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1611 | } | |
1612 | ||
1613 | *str2 = '\0'; | |
1614 | len = str2 - ident; | |
1615 | ||
1616 | ch = ident[0]; | |
bbdd25a8 BW |
1617 | for (ptr = &suffix_relocs[0]; ptr->length > 0; ptr++) |
1618 | if (ch == ptr->suffix[0] | |
43cd72b9 | 1619 | && len == ptr->length |
bbdd25a8 | 1620 | && memcmp (ident, ptr->suffix, ptr->length) == 0) |
43cd72b9 BW |
1621 | { |
1622 | /* Now check for "identifier@suffix+constant". */ | |
1623 | if (*str == '-' || *str == '+') | |
1624 | { | |
1625 | char *orig_line = input_line_pointer; | |
1626 | expressionS new_exp; | |
1627 | ||
1628 | input_line_pointer = str; | |
1629 | expression (&new_exp); | |
1630 | if (new_exp.X_op == O_constant) | |
1631 | { | |
1632 | exp_p->X_add_number += new_exp.X_add_number; | |
1633 | str = input_line_pointer; | |
1634 | } | |
1635 | ||
1636 | if (&input_line_pointer != str_p) | |
1637 | input_line_pointer = orig_line; | |
1638 | } | |
1639 | ||
1640 | *str_p = str; | |
1641 | return ptr->reloc; | |
1642 | } | |
1643 | ||
1644 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1645 | } |
1646 | ||
e0001a05 | 1647 | |
bbdd25a8 BW |
1648 | /* Find the matching operator type. */ |
1649 | static unsigned char | |
1650 | map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) | |
1651 | { | |
1652 | struct suffix_reloc_map *sfx; | |
1653 | unsigned char operator = (unsigned char) -1; | |
1654 | ||
1655 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1656 | { | |
1657 | if (sfx->reloc == reloc) | |
1658 | { | |
1659 | operator = sfx->operator; | |
1660 | break; | |
1661 | } | |
1662 | } | |
1663 | assert (operator != (unsigned char) -1); | |
1664 | return operator; | |
1665 | } | |
1666 | ||
1667 | ||
1668 | /* Find the matching reloc type. */ | |
1669 | static bfd_reloc_code_real_type | |
1670 | map_operator_to_reloc (unsigned char operator) | |
1671 | { | |
1672 | struct suffix_reloc_map *sfx; | |
1673 | bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; | |
1674 | ||
1675 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1676 | { | |
1677 | if (sfx->operator == operator) | |
1678 | { | |
1679 | reloc = sfx->reloc; | |
1680 | break; | |
1681 | } | |
1682 | } | |
1683 | ||
1684 | if (reloc == BFD_RELOC_UNUSED) | |
1685 | return BFD_RELOC_32; | |
1686 | ||
1687 | return reloc; | |
1688 | } | |
1689 | ||
1690 | ||
e0001a05 | 1691 | static const char * |
7fa3d080 | 1692 | expression_end (const char *name) |
e0001a05 NC |
1693 | { |
1694 | while (1) | |
1695 | { | |
1696 | switch (*name) | |
1697 | { | |
43cd72b9 | 1698 | case '}': |
e0001a05 NC |
1699 | case ';': |
1700 | case '\0': | |
1701 | case ',': | |
43cd72b9 | 1702 | case ':': |
e0001a05 NC |
1703 | return name; |
1704 | case ' ': | |
1705 | case '\t': | |
1706 | ++name; | |
1707 | continue; | |
1708 | default: | |
1709 | return 0; | |
1710 | } | |
1711 | } | |
1712 | } | |
1713 | ||
1714 | ||
1715 | #define ERROR_REG_NUM ((unsigned) -1) | |
1716 | ||
1717 | static unsigned | |
7fa3d080 | 1718 | tc_get_register (const char *prefix) |
e0001a05 NC |
1719 | { |
1720 | unsigned reg; | |
1721 | const char *next_expr; | |
1722 | const char *old_line_pointer; | |
1723 | ||
1724 | SKIP_WHITESPACE (); | |
1725 | old_line_pointer = input_line_pointer; | |
1726 | ||
1727 | if (*input_line_pointer == '$') | |
1728 | ++input_line_pointer; | |
1729 | ||
1730 | /* Accept "sp" as a synonym for "a1". */ | |
1731 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1732 | && expression_end (input_line_pointer + 2)) | |
1733 | { | |
1734 | input_line_pointer += 2; | |
1735 | return 1; /* AR[1] */ | |
1736 | } | |
1737 | ||
1738 | while (*input_line_pointer++ == *prefix++) | |
1739 | ; | |
1740 | --input_line_pointer; | |
1741 | --prefix; | |
1742 | ||
1743 | if (*prefix) | |
1744 | { | |
1745 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1746 | return ERROR_REG_NUM; | |
1747 | } | |
1748 | ||
1749 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1750 | { | |
1751 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1752 | return ERROR_REG_NUM; | |
1753 | } | |
1754 | ||
1755 | reg = 0; | |
1756 | ||
1757 | while (ISDIGIT ((int) *input_line_pointer)) | |
1758 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1759 | ||
1760 | if (!(next_expr = expression_end (input_line_pointer))) | |
1761 | { | |
1762 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1763 | return ERROR_REG_NUM; | |
1764 | } | |
1765 | ||
1766 | input_line_pointer = (char *) next_expr; | |
1767 | ||
1768 | return reg; | |
1769 | } | |
1770 | ||
1771 | ||
e0001a05 | 1772 | static void |
7fa3d080 | 1773 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1774 | { |
43cd72b9 | 1775 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1776 | |
43cd72b9 BW |
1777 | /* Check if this is an immediate operand. */ |
1778 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1779 | { |
43cd72b9 | 1780 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1781 | segT t = expression (tok); |
43cd72b9 BW |
1782 | if (t == absolute_section |
1783 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 NC |
1784 | { |
1785 | assert (tok->X_op == O_constant); | |
1786 | tok->X_op = O_symbol; | |
1787 | tok->X_add_symbol = &abs_symbol; | |
1788 | } | |
43cd72b9 BW |
1789 | |
1790 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
bbdd25a8 BW |
1791 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) |
1792 | != BFD_RELOC_NONE)) | |
e0001a05 | 1793 | { |
bbdd25a8 | 1794 | if (reloc == BFD_RELOC_UNUSED) |
43cd72b9 | 1795 | { |
bbdd25a8 BW |
1796 | as_bad (_("unsupported relocation")); |
1797 | return; | |
1798 | } | |
43cd72b9 | 1799 | |
bbdd25a8 BW |
1800 | if (tok->X_op == O_constant) |
1801 | { | |
1802 | switch (reloc) | |
1803 | { | |
1804 | case BFD_RELOC_LO16: | |
43cd72b9 | 1805 | tok->X_add_number &= 0xffff; |
bbdd25a8 | 1806 | return; |
43cd72b9 | 1807 | |
bbdd25a8 | 1808 | case BFD_RELOC_HI16: |
43cd72b9 | 1809 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; |
bbdd25a8 BW |
1810 | return; |
1811 | ||
1812 | default: | |
1813 | break; | |
1814 | } | |
43cd72b9 | 1815 | } |
bbdd25a8 | 1816 | tok->X_op = map_suffix_reloc_to_operator (reloc); |
e0001a05 | 1817 | } |
e0001a05 NC |
1818 | } |
1819 | else | |
1820 | { | |
43cd72b9 BW |
1821 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1822 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1823 | |
1824 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1825 | { | |
1826 | uint32 buf = reg; | |
43cd72b9 | 1827 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1828 | as_bad (_("register number out of range")); |
1829 | } | |
1830 | ||
1831 | tok->X_op = O_register; | |
1832 | tok->X_add_symbol = 0; | |
1833 | tok->X_add_number = reg; | |
1834 | } | |
1835 | } | |
1836 | ||
1837 | ||
1838 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1839 | ||
1840 | static int | |
7fa3d080 | 1841 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1842 | { |
1843 | char *old_input_line_pointer; | |
1844 | bfd_boolean saw_comma = FALSE; | |
1845 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1846 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1847 | int num_args = 0; |
1848 | char *arg_end, *arg; | |
1849 | int arg_len; | |
43cd72b9 BW |
1850 | |
1851 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1852 | old_input_line_pointer = input_line_pointer; |
1853 | input_line_pointer = str; | |
1854 | ||
1855 | while (*input_line_pointer) | |
1856 | { | |
1857 | SKIP_WHITESPACE (); | |
1858 | switch (*input_line_pointer) | |
1859 | { | |
1860 | case '\0': | |
43cd72b9 | 1861 | case '}': |
e0001a05 NC |
1862 | goto fini; |
1863 | ||
43cd72b9 BW |
1864 | case ':': |
1865 | input_line_pointer++; | |
1866 | if (saw_comma || saw_colon || !saw_arg) | |
1867 | goto err; | |
1868 | saw_colon = TRUE; | |
1869 | break; | |
1870 | ||
e0001a05 NC |
1871 | case ',': |
1872 | input_line_pointer++; | |
43cd72b9 | 1873 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
1874 | goto err; |
1875 | saw_comma = TRUE; | |
1876 | break; | |
1877 | ||
1878 | default: | |
43cd72b9 | 1879 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
1880 | goto err; |
1881 | ||
1882 | arg_end = input_line_pointer + 1; | |
1883 | while (!expression_end (arg_end)) | |
1884 | arg_end += 1; | |
43cd72b9 | 1885 | |
e0001a05 | 1886 | arg_len = arg_end - input_line_pointer; |
43cd72b9 | 1887 | arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
1888 | args[num_args] = arg; |
1889 | ||
43cd72b9 BW |
1890 | if (saw_colon) |
1891 | *arg++ = ':'; | |
e0001a05 NC |
1892 | strncpy (arg, input_line_pointer, arg_len); |
1893 | arg[arg_len] = '\0'; | |
43cd72b9 | 1894 | |
e0001a05 NC |
1895 | input_line_pointer = arg_end; |
1896 | num_args += 1; | |
c138bc38 | 1897 | saw_comma = FALSE; |
43cd72b9 | 1898 | saw_colon = FALSE; |
c138bc38 | 1899 | saw_arg = TRUE; |
e0001a05 NC |
1900 | break; |
1901 | } | |
1902 | } | |
1903 | ||
1904 | fini: | |
43cd72b9 | 1905 | if (saw_comma || saw_colon) |
e0001a05 NC |
1906 | goto err; |
1907 | input_line_pointer = old_input_line_pointer; | |
1908 | return num_args; | |
1909 | ||
1910 | err: | |
43cd72b9 BW |
1911 | if (saw_comma) |
1912 | as_bad (_("extra comma")); | |
1913 | else if (saw_colon) | |
1914 | as_bad (_("extra colon")); | |
1915 | else if (!saw_arg) | |
c138bc38 | 1916 | as_bad (_("missing argument")); |
43cd72b9 BW |
1917 | else |
1918 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
1919 | input_line_pointer = old_input_line_pointer; |
1920 | return -1; | |
1921 | } | |
1922 | ||
1923 | ||
43cd72b9 | 1924 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
1925 | |
1926 | static bfd_boolean | |
7fa3d080 | 1927 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 1928 | { |
43cd72b9 | 1929 | expressionS *tok, *last_tok; |
e0001a05 NC |
1930 | xtensa_opcode opcode = insn->opcode; |
1931 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
1932 | xtensa_isa isa = xtensa_default_isa; |
1933 | int n, num_regs = 0; | |
e0001a05 | 1934 | int opcode_operand_count; |
43cd72b9 BW |
1935 | int opnd_cnt, last_opnd_cnt; |
1936 | unsigned int next_reg = 0; | |
e0001a05 NC |
1937 | char *old_input_line_pointer; |
1938 | ||
1939 | if (insn->insn_type == ITYPE_LITERAL) | |
1940 | opcode_operand_count = 1; | |
1941 | else | |
43cd72b9 | 1942 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 1943 | |
43cd72b9 | 1944 | tok = insn->tok; |
e0001a05 NC |
1945 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
1946 | ||
1947 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
1948 | old_input_line_pointer = input_line_pointer; |
1949 | ||
1950 | last_tok = 0; | |
1951 | last_opnd_cnt = -1; | |
1952 | opnd_cnt = 0; | |
1953 | ||
1954 | /* Skip invisible operands. */ | |
1955 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
1956 | { | |
1957 | opnd_cnt += 1; | |
1958 | tok++; | |
1959 | } | |
e0001a05 NC |
1960 | |
1961 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 1962 | { |
e0001a05 | 1963 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
1964 | if (*input_line_pointer == ':') |
1965 | { | |
1966 | xtensa_regfile opnd_rf; | |
1967 | input_line_pointer++; | |
1968 | if (num_regs == 0) | |
1969 | goto err; | |
1970 | assert (opnd_cnt > 0); | |
1971 | num_regs--; | |
1972 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
1973 | if (next_reg | |
1974 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
1975 | as_warn (_("incorrect register number, ignoring")); | |
1976 | next_reg++; | |
1977 | } | |
1978 | else | |
1979 | { | |
1980 | if (opnd_cnt >= opcode_operand_count) | |
1981 | { | |
1982 | as_warn (_("too many arguments")); | |
1983 | goto err; | |
1984 | } | |
1985 | assert (opnd_cnt < MAX_INSN_ARGS); | |
1986 | ||
1987 | expression_maybe_register (opcode, opnd_cnt, tok); | |
1988 | next_reg = tok->X_add_number + 1; | |
1989 | ||
1990 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
1991 | goto err; | |
1992 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
1993 | { | |
1994 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
1995 | /* minus 1 because we are seeing one right now */ | |
1996 | } | |
1997 | else | |
1998 | num_regs = 0; | |
e0001a05 | 1999 | |
43cd72b9 BW |
2000 | last_tok = tok; |
2001 | last_opnd_cnt = opnd_cnt; | |
e0001a05 | 2002 | |
43cd72b9 BW |
2003 | do |
2004 | { | |
2005 | opnd_cnt += 1; | |
2006 | tok++; | |
2007 | } | |
2008 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
2009 | } | |
2010 | } | |
e0001a05 | 2011 | |
43cd72b9 BW |
2012 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
2013 | goto err; | |
e0001a05 NC |
2014 | |
2015 | insn->ntok = tok - insn->tok; | |
c138bc38 | 2016 | had_error = FALSE; |
e0001a05 NC |
2017 | |
2018 | err: | |
43cd72b9 | 2019 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2020 | return had_error; |
2021 | } | |
2022 | ||
2023 | ||
43cd72b9 | 2024 | static int |
7fa3d080 | 2025 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2026 | { |
2027 | xtensa_isa isa = xtensa_default_isa; | |
2028 | static xtensa_insnbuf slotbuf = NULL; | |
2029 | xtensa_format fmt; | |
2030 | xtensa_opcode opc = insn->opcode; | |
2031 | int slot, opnd, fmt_found; | |
2032 | unsigned val; | |
2033 | ||
2034 | if (!slotbuf) | |
2035 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2036 | ||
2037 | /* Find format/slot where this can be encoded. */ | |
2038 | fmt_found = 0; | |
2039 | slot = 0; | |
2040 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2041 | { | |
2042 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2043 | { | |
2044 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2045 | { | |
2046 | fmt_found = 1; | |
2047 | break; | |
2048 | } | |
2049 | } | |
2050 | if (fmt_found) break; | |
2051 | } | |
2052 | ||
2053 | if (!fmt_found) | |
2054 | { | |
2055 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2056 | return -1; | |
2057 | } | |
2058 | ||
2059 | /* First encode all the visible operands | |
2060 | (to deal with shared field operands). */ | |
2061 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2062 | { | |
2063 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2064 | && (insn->tok[opnd].X_op == O_register | |
2065 | || insn->tok[opnd].X_op == O_constant)) | |
2066 | { | |
2067 | val = insn->tok[opnd].X_add_number; | |
2068 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2069 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2070 | } | |
2071 | } | |
2072 | ||
2073 | /* Then pull out the values for the invisible ones. */ | |
2074 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2075 | { | |
2076 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2077 | { | |
2078 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2079 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2080 | insn->tok[opnd].X_add_number = val; | |
2081 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2082 | insn->tok[opnd].X_op = O_register; | |
2083 | else | |
2084 | insn->tok[opnd].X_op = O_constant; | |
2085 | } | |
2086 | } | |
2087 | ||
2088 | return 0; | |
2089 | } | |
2090 | ||
2091 | ||
e0001a05 | 2092 | static void |
7fa3d080 | 2093 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2094 | { |
2095 | char *cnt_arg, *new_arg; | |
2096 | cnt_arg = *cnt_argp; | |
2097 | ||
2098 | /* replace the argument with "31-(argument)" */ | |
2099 | new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); | |
2100 | sprintf (new_arg, "31-(%s)", cnt_arg); | |
2101 | ||
2102 | free (cnt_arg); | |
2103 | *cnt_argp = new_arg; | |
2104 | } | |
2105 | ||
2106 | ||
2107 | /* If "arg" is a constant expression, return non-zero with the value | |
2108 | in *valp. */ | |
2109 | ||
2110 | static int | |
7fa3d080 | 2111 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2112 | { |
2113 | expressionS exp; | |
2114 | char *save_ptr = input_line_pointer; | |
2115 | ||
2116 | input_line_pointer = arg; | |
2117 | expression (&exp); | |
2118 | input_line_pointer = save_ptr; | |
2119 | ||
2120 | if (exp.X_op == O_constant) | |
2121 | { | |
2122 | *valp = exp.X_add_number; | |
2123 | return 1; | |
2124 | } | |
2125 | ||
2126 | return 0; | |
2127 | } | |
2128 | ||
2129 | ||
2130 | static void | |
7fa3d080 | 2131 | xg_replace_opname (char **popname, char *newop) |
e0001a05 NC |
2132 | { |
2133 | free (*popname); | |
2134 | *popname = (char *) xmalloc (strlen (newop) + 1); | |
2135 | strcpy (*popname, newop); | |
2136 | } | |
2137 | ||
2138 | ||
2139 | static int | |
7fa3d080 BW |
2140 | xg_check_num_args (int *pnum_args, |
2141 | int expected_num, | |
2142 | char *opname, | |
2143 | char **arg_strings) | |
e0001a05 NC |
2144 | { |
2145 | int num_args = *pnum_args; | |
2146 | ||
43cd72b9 | 2147 | if (num_args < expected_num) |
e0001a05 NC |
2148 | { |
2149 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2150 | num_args, opname, expected_num); | |
2151 | return -1; | |
2152 | } | |
2153 | ||
2154 | if (num_args > expected_num) | |
2155 | { | |
2156 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2157 | num_args, opname, expected_num); | |
2158 | while (num_args-- > expected_num) | |
2159 | { | |
2160 | free (arg_strings[num_args]); | |
2161 | arg_strings[num_args] = 0; | |
2162 | } | |
2163 | *pnum_args = expected_num; | |
2164 | return -1; | |
2165 | } | |
2166 | ||
2167 | return 0; | |
2168 | } | |
2169 | ||
2170 | ||
43cd72b9 BW |
2171 | /* If the register is not specified as part of the opcode, |
2172 | then get it from the operand and move it to the opcode. */ | |
2173 | ||
e0001a05 | 2174 | static int |
7fa3d080 | 2175 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2176 | { |
43cd72b9 BW |
2177 | xtensa_isa isa = xtensa_default_isa; |
2178 | xtensa_sysreg sr; | |
e0001a05 | 2179 | char *opname, *new_opname; |
43cd72b9 BW |
2180 | const char *sr_name; |
2181 | int is_user, is_write; | |
e0001a05 NC |
2182 | |
2183 | opname = *popname; | |
2184 | if (*opname == '_') | |
80ca4e2c | 2185 | opname += 1; |
43cd72b9 BW |
2186 | is_user = (opname[1] == 'u'); |
2187 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2188 | |
43cd72b9 | 2189 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2190 | |
43cd72b9 BW |
2191 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2192 | return -1; | |
e0001a05 | 2193 | |
43cd72b9 BW |
2194 | /* Check if the argument is a symbolic register name. */ |
2195 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2196 | /* Handle WSR to "INTSET" as a special case. */ | |
2197 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2198 | && !strcasecmp (arg_strings[1], "intset")) | |
2199 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2200 | if (sr == XTENSA_UNDEFINED | |
2201 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2202 | { | |
2203 | /* Maybe it's a register number.... */ | |
2204 | offsetT val; | |
e0001a05 NC |
2205 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2206 | { | |
43cd72b9 BW |
2207 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2208 | arg_strings[1], opname); | |
e0001a05 NC |
2209 | return -1; |
2210 | } | |
43cd72b9 BW |
2211 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2212 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2213 | { |
43cd72b9 | 2214 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2215 | (long) val, opname); |
e0001a05 NC |
2216 | return -1; |
2217 | } | |
43cd72b9 | 2218 | } |
e0001a05 | 2219 | |
43cd72b9 BW |
2220 | /* Remove the last argument, which is now part of the opcode. */ |
2221 | free (arg_strings[1]); | |
2222 | arg_strings[1] = 0; | |
2223 | *pnum_args = 1; | |
2224 | ||
2225 | /* Translate the opcode. */ | |
2226 | sr_name = xtensa_sysreg_name (isa, sr); | |
2227 | /* Another special case for "WSR.INTSET".... */ | |
2228 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2229 | sr_name = "intset"; | |
2230 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
80ca4e2c | 2231 | sprintf (new_opname, "%s.%s", *popname, sr_name); |
43cd72b9 BW |
2232 | free (*popname); |
2233 | *popname = new_opname; | |
2234 | ||
2235 | return 0; | |
2236 | } | |
2237 | ||
2238 | ||
2239 | static int | |
7fa3d080 | 2240 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2241 | { |
2242 | xtensa_isa isa = xtensa_default_isa; | |
2243 | xtensa_sysreg sr; | |
2244 | char *opname, *new_opname; | |
2245 | const char *sr_name; | |
2246 | bfd_boolean has_underbar = FALSE; | |
2247 | ||
2248 | opname = *popname; | |
2249 | if (opname[0] == '_') | |
2250 | { | |
2251 | has_underbar = TRUE; | |
2252 | opname += 1; | |
2253 | } | |
2254 | ||
2255 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2256 | if (sr != XTENSA_UNDEFINED) | |
2257 | { | |
2258 | /* The new default name ("nnn") is different from the old default | |
2259 | name ("URnnn"). The old default is handled below, and we don't | |
2260 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2261 | default. */ | |
2262 | static char namebuf[10]; | |
2263 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2264 | if (strcmp (namebuf, opname + 1) == 0) | |
2265 | return 0; | |
2266 | } | |
2267 | else | |
2268 | { | |
2269 | offsetT val; | |
2270 | char *end; | |
2271 | ||
2272 | /* Only continue if the reg name is "URnnn". */ | |
2273 | if (opname[1] != 'u' || opname[2] != 'r') | |
2274 | return 0; | |
2275 | val = strtoul (opname + 3, &end, 10); | |
2276 | if (*end != '\0') | |
2277 | return 0; | |
2278 | ||
2279 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2280 | if (sr == XTENSA_UNDEFINED) | |
2281 | { | |
2282 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2283 | (long) val, opname); |
43cd72b9 BW |
2284 | return -1; |
2285 | } | |
2286 | } | |
2287 | ||
2288 | /* Translate the opcode. */ | |
2289 | sr_name = xtensa_sysreg_name (isa, sr); | |
2290 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
2291 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), | |
2292 | opname[0], sr_name); | |
2293 | free (*popname); | |
2294 | *popname = new_opname; | |
2295 | ||
2296 | return 0; | |
2297 | } | |
2298 | ||
2299 | ||
2300 | static int | |
7fa3d080 BW |
2301 | xtensa_translate_zero_immed (char *old_op, |
2302 | char *new_op, | |
2303 | char **popname, | |
2304 | int *pnum_args, | |
2305 | char **arg_strings) | |
43cd72b9 BW |
2306 | { |
2307 | char *opname; | |
2308 | offsetT val; | |
2309 | ||
2310 | opname = *popname; | |
2311 | assert (opname[0] != '_'); | |
2312 | ||
2313 | if (strcmp (opname, old_op) != 0) | |
2314 | return 0; | |
e0001a05 | 2315 | |
43cd72b9 BW |
2316 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2317 | return -1; | |
2318 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2319 | { | |
2320 | xg_replace_opname (popname, new_op); | |
2321 | free (arg_strings[1]); | |
2322 | arg_strings[1] = arg_strings[2]; | |
2323 | arg_strings[2] = 0; | |
2324 | *pnum_args = 2; | |
e0001a05 NC |
2325 | } |
2326 | ||
2327 | return 0; | |
2328 | } | |
2329 | ||
2330 | ||
2331 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2332 | Returns non-zero if an error was found. */ | |
2333 | ||
2334 | static int | |
7fa3d080 | 2335 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2336 | { |
2337 | char *opname = *popname; | |
2338 | bfd_boolean has_underbar = FALSE; | |
2339 | ||
43cd72b9 BW |
2340 | if (cur_vinsn.inside_bundle) |
2341 | return 0; | |
2342 | ||
e0001a05 NC |
2343 | if (*opname == '_') |
2344 | { | |
2345 | has_underbar = TRUE; | |
2346 | opname += 1; | |
2347 | } | |
2348 | ||
2349 | if (strcmp (opname, "mov") == 0) | |
2350 | { | |
43cd72b9 | 2351 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2352 | xg_replace_opname (popname, "mov.n"); |
2353 | else | |
2354 | { | |
2355 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2356 | return -1; | |
2357 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2358 | arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); | |
2359 | strcpy (arg_strings[2], arg_strings[1]); | |
2360 | *pnum_args = 3; | |
2361 | } | |
2362 | return 0; | |
2363 | } | |
2364 | ||
2365 | if (strcmp (opname, "bbsi.l") == 0) | |
2366 | { | |
2367 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2368 | return -1; | |
2369 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2370 | if (target_big_endian) | |
2371 | xg_reverse_shift_count (&arg_strings[1]); | |
2372 | return 0; | |
2373 | } | |
2374 | ||
2375 | if (strcmp (opname, "bbci.l") == 0) | |
2376 | { | |
2377 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2378 | return -1; | |
2379 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2380 | if (target_big_endian) | |
2381 | xg_reverse_shift_count (&arg_strings[1]); | |
2382 | return 0; | |
2383 | } | |
2384 | ||
43cd72b9 BW |
2385 | if (xtensa_nop_opcode == XTENSA_UNDEFINED |
2386 | && strcmp (opname, "nop") == 0) | |
e0001a05 | 2387 | { |
43cd72b9 | 2388 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2389 | xg_replace_opname (popname, "nop.n"); |
2390 | else | |
2391 | { | |
2392 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2393 | return -1; | |
2394 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2395 | arg_strings[0] = (char *) xmalloc (3); | |
2396 | arg_strings[1] = (char *) xmalloc (3); | |
2397 | arg_strings[2] = (char *) xmalloc (3); | |
2398 | strcpy (arg_strings[0], "a1"); | |
2399 | strcpy (arg_strings[1], "a1"); | |
2400 | strcpy (arg_strings[2], "a1"); | |
2401 | *pnum_args = 3; | |
2402 | } | |
2403 | return 0; | |
2404 | } | |
2405 | ||
43cd72b9 BW |
2406 | /* Recognize [RW]UR and [RWX]SR. */ |
2407 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2408 | && (opname[1] == 'u' || opname[1] == 's')) | |
2409 | || (opname[0] == 'x' && opname[1] == 's')) | |
2410 | && opname[2] == 'r' | |
2411 | && opname[3] == '\0') | |
e0001a05 NC |
2412 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2413 | ||
43cd72b9 BW |
2414 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2415 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2416 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2417 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2418 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2419 | |
43cd72b9 BW |
2420 | /* Relax branches that don't allow comparisons against an immediate value |
2421 | of zero to the corresponding branches with implicit zero immediates. */ | |
2422 | if (!has_underbar && use_transform ()) | |
2423 | { | |
2424 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2425 | pnum_args, arg_strings)) | |
2426 | return -1; | |
e0001a05 | 2427 | |
43cd72b9 BW |
2428 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2429 | pnum_args, arg_strings)) | |
2430 | return -1; | |
e0001a05 | 2431 | |
43cd72b9 BW |
2432 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2433 | pnum_args, arg_strings)) | |
2434 | return -1; | |
e0001a05 | 2435 | |
43cd72b9 BW |
2436 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2437 | pnum_args, arg_strings)) | |
2438 | return -1; | |
2439 | } | |
e0001a05 | 2440 | |
43cd72b9 BW |
2441 | return 0; |
2442 | } | |
e0001a05 | 2443 | |
43cd72b9 BW |
2444 | \f |
2445 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2446 | |
43cd72b9 BW |
2447 | /* Currently the assembler only allows us to use a single target per |
2448 | fragment. Because of this, only one operand for a given | |
2449 | instruction may be symbolic. If there is a PC-relative operand, | |
2450 | the last one is chosen. Otherwise, the result is the number of the | |
2451 | last immediate operand, and if there are none of those, we fail and | |
2452 | return -1. */ | |
e0001a05 | 2453 | |
7fa3d080 BW |
2454 | static int |
2455 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2456 | { |
2457 | int last_immed = -1; | |
2458 | int noperands, opi; | |
e0001a05 | 2459 | |
43cd72b9 BW |
2460 | if (opcode == XTENSA_UNDEFINED) |
2461 | return -1; | |
e0001a05 | 2462 | |
43cd72b9 BW |
2463 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2464 | for (opi = noperands - 1; opi >= 0; opi--) | |
2465 | { | |
2466 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2467 | continue; | |
2468 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2469 | return opi; | |
2470 | if (last_immed == -1 | |
2471 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2472 | last_immed = opi; | |
e0001a05 | 2473 | } |
43cd72b9 | 2474 | return last_immed; |
e0001a05 NC |
2475 | } |
2476 | ||
e0001a05 | 2477 | |
43cd72b9 | 2478 | static xtensa_opcode |
7fa3d080 | 2479 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2480 | { |
43cd72b9 BW |
2481 | static xtensa_insnbuf insnbuf = NULL; |
2482 | static xtensa_insnbuf slotbuf = NULL; | |
2483 | xtensa_isa isa = xtensa_default_isa; | |
2484 | xtensa_format fmt; | |
2485 | ||
2486 | if (!insnbuf) | |
e0001a05 | 2487 | { |
43cd72b9 BW |
2488 | insnbuf = xtensa_insnbuf_alloc (isa); |
2489 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2490 | } |
e0001a05 | 2491 | |
d77b99c9 | 2492 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2493 | fmt = xtensa_format_decode (isa, insnbuf); |
2494 | if (fmt == XTENSA_UNDEFINED) | |
2495 | return XTENSA_UNDEFINED; | |
e0001a05 | 2496 | |
43cd72b9 BW |
2497 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2498 | return XTENSA_UNDEFINED; | |
e0001a05 | 2499 | |
43cd72b9 BW |
2500 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2501 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2502 | } |
2503 | ||
2504 | ||
43cd72b9 | 2505 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2506 | |
43cd72b9 | 2507 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2508 | |
7fa3d080 BW |
2509 | static void |
2510 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2511 | { |
2512 | int num_opcodes, num_operands; | |
2513 | xtensa_opcode opcode; | |
2514 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2515 | |
43cd72b9 BW |
2516 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2517 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2518 | { |
43cd72b9 BW |
2519 | int opn; |
2520 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2521 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2522 | for (opn = 0; opn < num_operands; opn++) | |
2523 | { | |
2524 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2525 | continue; | |
2526 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2527 | { | |
2528 | xtensa_regfile opnd_rf = | |
2529 | xtensa_operand_regfile (isa, opcode, opn); | |
2530 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2531 | } | |
2532 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2533 | fputs ("[lLr] ", stderr); | |
2534 | else | |
2535 | fputs ("i ", stderr); | |
2536 | } | |
2537 | fprintf (stderr, "\n"); | |
e0001a05 | 2538 | } |
e0001a05 NC |
2539 | } |
2540 | ||
2541 | ||
43cd72b9 | 2542 | static void |
7fa3d080 | 2543 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2544 | { |
e0001a05 | 2545 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2546 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2547 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2548 | int op; | |
e0001a05 | 2549 | |
43cd72b9 | 2550 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2551 | |
43cd72b9 BW |
2552 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2553 | { | |
2554 | xtensa_opcode opcode; | |
2555 | const char *opname; | |
2556 | int operands; | |
2557 | ||
2558 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2559 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2560 | opname = xtensa_opcode_name (isa, opcode); | |
2561 | ||
2562 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2563 | fprintf (stderr, " operands = "); | |
2564 | for (operands = 0; | |
2565 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2566 | operands++) | |
2567 | { | |
2568 | unsigned int val; | |
2569 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2570 | continue; | |
2571 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2572 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2573 | fprintf (stderr, "%d ", val); | |
2574 | } | |
2575 | fprintf (stderr, "\n"); | |
2576 | } | |
2577 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2578 | } |
2579 | ||
43cd72b9 BW |
2580 | #endif /* TENSILICA_DEBUG */ |
2581 | ||
e0001a05 NC |
2582 | |
2583 | static bfd_boolean | |
7fa3d080 | 2584 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2585 | { |
43cd72b9 BW |
2586 | xtensa_isa isa = xtensa_default_isa; |
2587 | int n, num_operands; | |
e0001a05 | 2588 | |
64b607e6 | 2589 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
e0001a05 NC |
2590 | return FALSE; |
2591 | ||
43cd72b9 BW |
2592 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2593 | for (n = 0; n < num_operands; n++) | |
2594 | { | |
2595 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2596 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2597 | return TRUE; | |
2598 | } | |
2599 | return FALSE; | |
e0001a05 NC |
2600 | } |
2601 | ||
2602 | ||
43cd72b9 BW |
2603 | /* Convert from BFD relocation type code to slot and operand number. |
2604 | Returns non-zero on failure. */ | |
e0001a05 | 2605 | |
43cd72b9 | 2606 | static int |
7fa3d080 | 2607 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2608 | { |
43cd72b9 BW |
2609 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2610 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2611 | { |
43cd72b9 BW |
2612 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2613 | *is_alt = FALSE; | |
e0001a05 | 2614 | } |
43cd72b9 BW |
2615 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2616 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2617 | { |
43cd72b9 BW |
2618 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2619 | *is_alt = TRUE; | |
e0001a05 | 2620 | } |
43cd72b9 BW |
2621 | else |
2622 | return -1; | |
2623 | ||
2624 | return 0; | |
e0001a05 NC |
2625 | } |
2626 | ||
2627 | ||
43cd72b9 BW |
2628 | /* Convert from slot number to BFD relocation type code for the |
2629 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2630 | failure. */ | |
e0001a05 | 2631 | |
43cd72b9 | 2632 | static bfd_reloc_code_real_type |
7fa3d080 | 2633 | encode_reloc (int slot) |
e0001a05 | 2634 | { |
43cd72b9 BW |
2635 | if (slot < 0 || slot > 14) |
2636 | return BFD_RELOC_NONE; | |
2637 | ||
2638 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2639 | } |
2640 | ||
2641 | ||
43cd72b9 BW |
2642 | /* Convert from slot numbers to BFD relocation type code for the |
2643 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2644 | |
43cd72b9 | 2645 | static bfd_reloc_code_real_type |
7fa3d080 | 2646 | encode_alt_reloc (int slot) |
e0001a05 | 2647 | { |
43cd72b9 BW |
2648 | if (slot < 0 || slot > 14) |
2649 | return BFD_RELOC_NONE; | |
2650 | ||
2651 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2652 | } |
2653 | ||
2654 | ||
2655 | static void | |
7fa3d080 BW |
2656 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2657 | xtensa_format fmt, | |
2658 | int slot, | |
2659 | xtensa_opcode opcode, | |
2660 | int operand, | |
2661 | uint32 value, | |
2662 | const char *file, | |
2663 | unsigned int line) | |
e0001a05 | 2664 | { |
e0001a05 NC |
2665 | uint32 valbuf = value; |
2666 | ||
43cd72b9 | 2667 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2668 | { |
43cd72b9 BW |
2669 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2670 | == 1) | |
2671 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2672 | _("operand %d of '%s' has out of range value '%u'"), |
2673 | operand + 1, | |
2674 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2675 | value); | |
43cd72b9 BW |
2676 | else |
2677 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2678 | _("operand %d of '%s' has invalid value '%u'"), |
2679 | operand + 1, | |
2680 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2681 | value); | |
43cd72b9 | 2682 | return; |
e0001a05 NC |
2683 | } |
2684 | ||
43cd72b9 BW |
2685 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2686 | slotbuf, valbuf); | |
e0001a05 NC |
2687 | } |
2688 | ||
2689 | ||
2690 | static uint32 | |
7fa3d080 BW |
2691 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2692 | xtensa_format fmt, | |
2693 | int slot, | |
2694 | xtensa_opcode opcode, | |
2695 | int opnum) | |
e0001a05 | 2696 | { |
43cd72b9 BW |
2697 | uint32 val = 0; |
2698 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2699 | fmt, slot, slotbuf, &val); | |
2700 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2701 | return val; | |
e0001a05 NC |
2702 | } |
2703 | ||
e0001a05 | 2704 | \f |
7fa3d080 | 2705 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2706 | |
7fa3d080 BW |
2707 | /* The routine xg_instruction_matches_option_term must return TRUE |
2708 | when a given option term is true. The meaning of all of the option | |
2709 | terms is given interpretation by this function. This is needed when | |
2710 | an option depends on the state of a directive, but there are no such | |
2711 | options in use right now. */ | |
e0001a05 | 2712 | |
7fa3d080 BW |
2713 | static bfd_boolean |
2714 | xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED, | |
2715 | const ReqOrOption *option) | |
e0001a05 | 2716 | { |
7fa3d080 BW |
2717 | if (strcmp (option->option_name, "realnop") == 0 |
2718 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2719 | { | |
2720 | /* These conditions were evaluated statically when building the | |
2721 | relaxation table. There's no need to reevaluate them now. */ | |
2722 | return TRUE; | |
2723 | } | |
2724 | else | |
2725 | { | |
2726 | as_fatal (_("internal error: unknown option name '%s'"), | |
2727 | option->option_name); | |
2728 | } | |
e0001a05 NC |
2729 | } |
2730 | ||
2731 | ||
7fa3d080 BW |
2732 | static bfd_boolean |
2733 | xg_instruction_matches_or_options (TInsn *insn, | |
2734 | const ReqOrOptionList *or_option) | |
e0001a05 | 2735 | { |
7fa3d080 BW |
2736 | const ReqOrOption *option; |
2737 | /* Must match each of the AND terms. */ | |
2738 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2739 | { |
7fa3d080 BW |
2740 | if (xg_instruction_matches_option_term (insn, option)) |
2741 | return TRUE; | |
e0001a05 | 2742 | } |
7fa3d080 | 2743 | return FALSE; |
e0001a05 NC |
2744 | } |
2745 | ||
2746 | ||
7fa3d080 BW |
2747 | static bfd_boolean |
2748 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2749 | { |
7fa3d080 BW |
2750 | const ReqOption *req_options; |
2751 | /* Must match each of the AND terms. */ | |
2752 | for (req_options = options; | |
2753 | req_options != NULL; | |
2754 | req_options = req_options->next) | |
e0001a05 | 2755 | { |
7fa3d080 BW |
2756 | /* Must match one of the OR clauses. */ |
2757 | if (!xg_instruction_matches_or_options (insn, | |
2758 | req_options->or_option_terms)) | |
2759 | return FALSE; | |
e0001a05 | 2760 | } |
7fa3d080 | 2761 | return TRUE; |
e0001a05 NC |
2762 | } |
2763 | ||
2764 | ||
7fa3d080 | 2765 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2766 | |
7fa3d080 BW |
2767 | static bfd_boolean |
2768 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2769 | { |
7fa3d080 | 2770 | PreconditionList *condition_l; |
e0001a05 | 2771 | |
7fa3d080 BW |
2772 | if (rule->opcode != insn->opcode) |
2773 | return FALSE; | |
e0001a05 | 2774 | |
7fa3d080 BW |
2775 | for (condition_l = rule->conditions; |
2776 | condition_l != NULL; | |
2777 | condition_l = condition_l->next) | |
e0001a05 | 2778 | { |
7fa3d080 BW |
2779 | expressionS *exp1; |
2780 | expressionS *exp2; | |
2781 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2782 | |
7fa3d080 | 2783 | switch (cond->typ) |
e0001a05 | 2784 | { |
7fa3d080 BW |
2785 | case OP_CONSTANT: |
2786 | /* The expression must be the constant. */ | |
2787 | assert (cond->op_num < insn->ntok); | |
2788 | exp1 = &insn->tok[cond->op_num]; | |
2789 | if (expr_is_const (exp1)) | |
2790 | { | |
2791 | switch (cond->cmp) | |
2792 | { | |
2793 | case OP_EQUAL: | |
2794 | if (get_expr_const (exp1) != cond->op_data) | |
2795 | return FALSE; | |
2796 | break; | |
2797 | case OP_NOTEQUAL: | |
2798 | if (get_expr_const (exp1) == cond->op_data) | |
2799 | return FALSE; | |
2800 | break; | |
2801 | default: | |
2802 | return FALSE; | |
2803 | } | |
2804 | } | |
2805 | else if (expr_is_register (exp1)) | |
2806 | { | |
2807 | switch (cond->cmp) | |
2808 | { | |
2809 | case OP_EQUAL: | |
2810 | if (get_expr_register (exp1) != cond->op_data) | |
2811 | return FALSE; | |
2812 | break; | |
2813 | case OP_NOTEQUAL: | |
2814 | if (get_expr_register (exp1) == cond->op_data) | |
2815 | return FALSE; | |
2816 | break; | |
2817 | default: | |
2818 | return FALSE; | |
2819 | } | |
2820 | } | |
2821 | else | |
2822 | return FALSE; | |
2823 | break; | |
2824 | ||
2825 | case OP_OPERAND: | |
2826 | assert (cond->op_num < insn->ntok); | |
2827 | assert (cond->op_data < insn->ntok); | |
2828 | exp1 = &insn->tok[cond->op_num]; | |
2829 | exp2 = &insn->tok[cond->op_data]; | |
2830 | ||
2831 | switch (cond->cmp) | |
2832 | { | |
2833 | case OP_EQUAL: | |
2834 | if (!expr_is_equal (exp1, exp2)) | |
2835 | return FALSE; | |
2836 | break; | |
2837 | case OP_NOTEQUAL: | |
2838 | if (expr_is_equal (exp1, exp2)) | |
2839 | return FALSE; | |
2840 | break; | |
2841 | } | |
2842 | break; | |
2843 | ||
2844 | case OP_LITERAL: | |
2845 | case OP_LABEL: | |
2846 | default: | |
2847 | return FALSE; | |
2848 | } | |
2849 | } | |
2850 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2851 | return FALSE; | |
2852 | ||
2853 | return TRUE; | |
2854 | } | |
2855 | ||
2856 | ||
2857 | static int | |
2858 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2859 | { | |
2860 | bfd_boolean a_greater = FALSE; | |
2861 | bfd_boolean b_greater = FALSE; | |
2862 | ||
2863 | ReqOptionList *l_a = a->options; | |
2864 | ReqOptionList *l_b = b->options; | |
2865 | ||
2866 | /* We only care if they both are the same except for | |
2867 | a const16 vs. an l32r. */ | |
2868 | ||
2869 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2870 | { | |
2871 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2872 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2873 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2874 | { | |
2875 | if (l_or_a->is_true != l_or_b->is_true) | |
2876 | return 0; | |
2877 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2878 | { | |
2879 | /* This is the case we care about. */ | |
2880 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
2881 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
2882 | { | |
2883 | if (prefer_const16) | |
2884 | a_greater = TRUE; | |
2885 | else | |
2886 | b_greater = TRUE; | |
2887 | } | |
2888 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
2889 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
2890 | { | |
2891 | if (prefer_const16) | |
2892 | b_greater = TRUE; | |
2893 | else | |
2894 | a_greater = TRUE; | |
2895 | } | |
2896 | else | |
2897 | return 0; | |
2898 | } | |
2899 | l_or_a = l_or_a->next; | |
2900 | l_or_b = l_or_b->next; | |
2901 | } | |
2902 | if (l_or_a || l_or_b) | |
2903 | return 0; | |
2904 | ||
2905 | l_a = l_a->next; | |
2906 | l_b = l_b->next; | |
2907 | } | |
2908 | if (l_a || l_b) | |
2909 | return 0; | |
2910 | ||
2911 | /* Incomparable if the substitution was used differently in two cases. */ | |
2912 | if (a_greater && b_greater) | |
2913 | return 0; | |
2914 | ||
2915 | if (b_greater) | |
2916 | return 1; | |
2917 | if (a_greater) | |
2918 | return -1; | |
2919 | ||
2920 | return 0; | |
2921 | } | |
2922 | ||
2923 | ||
2924 | static TransitionRule * | |
2925 | xg_instruction_match (TInsn *insn) | |
2926 | { | |
2927 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
2928 | TransitionList *l; | |
2929 | assert (insn->opcode < table->num_opcodes); | |
2930 | ||
2931 | /* Walk through all of the possible transitions. */ | |
2932 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2933 | { | |
2934 | TransitionRule *rule = l->rule; | |
2935 | if (xg_instruction_matches_rule (insn, rule)) | |
2936 | return rule; | |
2937 | } | |
2938 | return NULL; | |
2939 | } | |
2940 | ||
2941 | \f | |
2942 | /* Various Other Internal Functions. */ | |
2943 | ||
2944 | static bfd_boolean | |
2945 | is_unique_insn_expansion (TransitionRule *r) | |
2946 | { | |
2947 | if (!r->to_instr || r->to_instr->next != NULL) | |
2948 | return FALSE; | |
2949 | if (r->to_instr->typ != INSTR_INSTR) | |
2950 | return FALSE; | |
2951 | return TRUE; | |
2952 | } | |
2953 | ||
2954 | ||
84b08ed9 BW |
2955 | /* Check if there is exactly one relaxation for INSN that converts it to |
2956 | another instruction of equal or larger size. If so, and if TARG is | |
2957 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
2958 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
2959 | instruction, i.e., ignore relaxations that convert to an instruction of | |
2960 | equal size. In some contexts where this function is used, only | |
c138bc38 | 2961 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
2962 | exclude cases like ADDI being "widened" to an ADDMI, which may |
2963 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 2964 | |
84b08ed9 BW |
2965 | bfd_boolean |
2966 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
2967 | { |
2968 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
2969 | TransitionList *l; | |
84b08ed9 | 2970 | TransitionRule *match = 0; |
7fa3d080 | 2971 | |
7fa3d080 BW |
2972 | assert (insn->insn_type == ITYPE_INSN); |
2973 | assert (insn->opcode < table->num_opcodes); | |
2974 | ||
2975 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2976 | { | |
2977 | TransitionRule *rule = l->rule; | |
2978 | ||
2979 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
2980 | && is_unique_insn_expansion (rule) |
2981 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
2982 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 2983 | { |
84b08ed9 BW |
2984 | if (match) |
2985 | return FALSE; | |
2986 | match = rule; | |
7fa3d080 BW |
2987 | } |
2988 | } | |
84b08ed9 BW |
2989 | if (!match) |
2990 | return FALSE; | |
2991 | ||
2992 | if (targ) | |
2993 | xg_build_to_insn (targ, insn, match->to_instr); | |
2994 | return TRUE; | |
7fa3d080 BW |
2995 | } |
2996 | ||
2997 | ||
2998 | /* Return the maximum number of bytes this opcode can expand to. */ | |
2999 | ||
3000 | static int | |
3001 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
3002 | { | |
3003 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3004 | TransitionList *l; | |
3005 | int max_size = xg_get_single_size (opcode); | |
3006 | ||
3007 | assert (opcode < table->num_opcodes); | |
3008 | ||
3009 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3010 | { | |
3011 | TransitionRule *rule = l->rule; | |
3012 | BuildInstr *build_list; | |
3013 | int this_size = 0; | |
3014 | ||
3015 | if (!rule) | |
3016 | continue; | |
3017 | build_list = rule->to_instr; | |
3018 | if (is_unique_insn_expansion (rule)) | |
3019 | { | |
3020 | assert (build_list->typ == INSTR_INSTR); | |
3021 | this_size = xg_get_max_insn_widen_size (build_list->opcode); | |
3022 | } | |
3023 | else | |
3024 | for (; build_list != NULL; build_list = build_list->next) | |
3025 | { | |
3026 | switch (build_list->typ) | |
3027 | { | |
3028 | case INSTR_INSTR: | |
3029 | this_size += xg_get_single_size (build_list->opcode); | |
3030 | break; | |
3031 | case INSTR_LITERAL_DEF: | |
3032 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3033 | default: |
3034 | break; | |
3035 | } | |
3036 | } | |
3037 | if (this_size > max_size) | |
3038 | max_size = this_size; | |
3039 | } | |
3040 | return max_size; | |
3041 | } | |
3042 | ||
3043 | ||
3044 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3045 | ||
7fa3d080 BW |
3046 | static int |
3047 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3048 | { |
43cd72b9 | 3049 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3050 | TransitionList *l; |
3051 | int max_size = 0; | |
3052 | ||
3053 | assert (opcode < table->num_opcodes); | |
3054 | ||
3055 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3056 | { | |
3057 | TransitionRule *rule = l->rule; | |
3058 | BuildInstr *build_list; | |
3059 | int this_size = 0; | |
3060 | ||
3061 | if (!rule) | |
3062 | continue; | |
3063 | build_list = rule->to_instr; | |
3064 | if (is_unique_insn_expansion (rule)) | |
3065 | { | |
3066 | assert (build_list->typ == INSTR_INSTR); | |
3067 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); | |
3068 | } | |
3069 | else | |
3070 | for (; build_list != NULL; build_list = build_list->next) | |
3071 | { | |
3072 | switch (build_list->typ) | |
3073 | { | |
3074 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3075 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3076 | this_size += 4; |
3077 | break; | |
3078 | case INSTR_INSTR: | |
3079 | case INSTR_LABEL_DEF: | |
3080 | default: | |
3081 | break; | |
3082 | } | |
3083 | } | |
3084 | if (this_size > max_size) | |
3085 | max_size = this_size; | |
3086 | } | |
3087 | return max_size; | |
3088 | } | |
3089 | ||
3090 | ||
7fa3d080 BW |
3091 | static bfd_boolean |
3092 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3093 | { | |
3094 | int steps_taken = 0; | |
3095 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3096 | TransitionList *l; | |
3097 | ||
3098 | assert (insn->insn_type == ITYPE_INSN); | |
3099 | assert (insn->opcode < table->num_opcodes); | |
3100 | ||
3101 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3102 | { | |
3103 | TransitionRule *rule = l->rule; | |
3104 | ||
3105 | if (xg_instruction_matches_rule (insn, rule)) | |
3106 | { | |
3107 | if (steps_taken == lateral_steps) | |
3108 | return TRUE; | |
3109 | steps_taken++; | |
3110 | } | |
3111 | } | |
3112 | return FALSE; | |
3113 | } | |
3114 | ||
3115 | ||
3116 | static symbolS * | |
3117 | get_special_literal_symbol (void) | |
3118 | { | |
3119 | static symbolS *sym = NULL; | |
3120 | ||
3121 | if (sym == NULL) | |
3122 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3123 | return sym; | |
3124 | } | |
3125 | ||
3126 | ||
3127 | static symbolS * | |
3128 | get_special_label_symbol (void) | |
3129 | { | |
3130 | static symbolS *sym = NULL; | |
3131 | ||
3132 | if (sym == NULL) | |
3133 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3134 | return sym; | |
3135 | } | |
3136 | ||
3137 | ||
3138 | static bfd_boolean | |
3139 | xg_valid_literal_expression (const expressionS *exp) | |
3140 | { | |
3141 | switch (exp->X_op) | |
3142 | { | |
3143 | case O_constant: | |
3144 | case O_symbol: | |
3145 | case O_big: | |
3146 | case O_uminus: | |
3147 | case O_subtract: | |
3148 | case O_pltrel: | |
3149 | return TRUE; | |
3150 | default: | |
3151 | return FALSE; | |
3152 | } | |
3153 | } | |
3154 | ||
3155 | ||
3156 | /* This will check to see if the value can be converted into the | |
3157 | operand type. It will return TRUE if it does not fit. */ | |
3158 | ||
3159 | static bfd_boolean | |
3160 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3161 | { | |
3162 | uint32 valbuf = value; | |
3163 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3164 | return TRUE; | |
3165 | return FALSE; | |
3166 | } | |
3167 | ||
3168 | ||
3169 | /* Assumes: All immeds are constants. Check that all constants fit | |
3170 | into their immeds; return FALSE if not. */ | |
3171 | ||
3172 | static bfd_boolean | |
3173 | xg_immeds_fit (const TInsn *insn) | |
3174 | { | |
3175 | xtensa_isa isa = xtensa_default_isa; | |
3176 | int i; | |
3177 | ||
3178 | int n = insn->ntok; | |
3179 | assert (insn->insn_type == ITYPE_INSN); | |
3180 | for (i = 0; i < n; ++i) | |
3181 | { | |
3182 | const expressionS *expr = &insn->tok[i]; | |
3183 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3184 | continue; | |
3185 | ||
3186 | switch (expr->X_op) | |
3187 | { | |
3188 | case O_register: | |
3189 | case O_constant: | |
3190 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3191 | return FALSE; | |
3192 | break; | |
3193 | ||
3194 | default: | |
3195 | /* The symbol should have a fixup associated with it. */ | |
3196 | assert (FALSE); | |
3197 | break; | |
3198 | } | |
3199 | } | |
3200 | return TRUE; | |
3201 | } | |
3202 | ||
3203 | ||
3204 | /* This should only be called after we have an initial | |
3205 | estimate of the addresses. */ | |
3206 | ||
3207 | static bfd_boolean | |
3208 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3209 | segT pc_seg, | |
3210 | fragS *pc_frag, | |
3211 | offsetT pc_offset, | |
3212 | long stretch) | |
e0001a05 | 3213 | { |
7fa3d080 BW |
3214 | xtensa_isa isa = xtensa_default_isa; |
3215 | symbolS *symbolP; | |
3216 | fragS *sym_frag; | |
3217 | offsetT target, pc; | |
3218 | uint32 new_offset; | |
3219 | int i; | |
3220 | int n = insn->ntok; | |
e0001a05 NC |
3221 | |
3222 | assert (insn->insn_type == ITYPE_INSN); | |
e0001a05 | 3223 | |
7fa3d080 | 3224 | for (i = 0; i < n; ++i) |
e0001a05 | 3225 | { |
7fa3d080 BW |
3226 | const expressionS *expr = &insn->tok[i]; |
3227 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3228 | continue; | |
e0001a05 | 3229 | |
7fa3d080 | 3230 | switch (expr->X_op) |
e0001a05 | 3231 | { |
7fa3d080 BW |
3232 | case O_register: |
3233 | case O_constant: | |
3234 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3235 | return FALSE; | |
3236 | break; | |
e0001a05 | 3237 | |
7fa3d080 BW |
3238 | case O_lo16: |
3239 | case O_hi16: | |
3240 | /* Check for the worst case. */ | |
3241 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3242 | return FALSE; | |
3243 | break; | |
e0001a05 | 3244 | |
7fa3d080 | 3245 | case O_symbol: |
7c834684 | 3246 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3247 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3248 | if (pc_frag == 0 |
3249 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3250 | return FALSE; |
e0001a05 | 3251 | |
7c834684 BW |
3252 | /* If it is a weak symbol, then assume it won't reach. */ |
3253 | if (S_IS_WEAK (expr->X_add_symbol)) | |
7fa3d080 | 3254 | return FALSE; |
e0001a05 | 3255 | |
7c834684 BW |
3256 | if (is_direct_call_opcode (insn->opcode) |
3257 | && ! pc_frag->tc_frag_data.use_longcalls) | |
3258 | { | |
3259 | /* If callee is undefined or in a different segment, be | |
3260 | optimistic and assume it will be in range. */ | |
3261 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
3262 | return TRUE; | |
3263 | } | |
3264 | ||
3265 | /* Only references within a segment can be known to fit in the | |
3266 | operands at assembly time. */ | |
3267 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
7fa3d080 | 3268 | return FALSE; |
e0001a05 | 3269 | |
7fa3d080 BW |
3270 | symbolP = expr->X_add_symbol; |
3271 | sym_frag = symbol_get_frag (symbolP); | |
3272 | target = S_GET_VALUE (symbolP) + expr->X_add_number; | |
3273 | pc = pc_frag->fr_address + pc_offset; | |
e0001a05 | 3274 | |
7fa3d080 BW |
3275 | /* If frag has yet to be reached on this pass, assume it |
3276 | will move by STRETCH just as we did. If this is not so, | |
3277 | it will be because some frag between grows, and that will | |
3278 | force another pass. Beware zero-length frags. There | |
3279 | should be a faster way to do this. */ | |
3280 | ||
3281 | if (stretch != 0 | |
3282 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3283 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3284 | { | |
3285 | target += stretch; | |
3286 | } | |
c138bc38 | 3287 | |
7fa3d080 BW |
3288 | new_offset = target; |
3289 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3290 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3291 | return FALSE; | |
3292 | break; | |
3293 | ||
3294 | default: | |
3295 | /* The symbol should have a fixup associated with it. */ | |
3296 | return FALSE; | |
3297 | } | |
3298 | } | |
3299 | ||
3300 | return TRUE; | |
e0001a05 NC |
3301 | } |
3302 | ||
3303 | ||
43cd72b9 | 3304 | /* Return TRUE on success. */ |
e0001a05 | 3305 | |
7fa3d080 BW |
3306 | static bfd_boolean |
3307 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3308 | { |
3309 | BuildOp *op; | |
3310 | symbolS *sym; | |
3311 | ||
60242db2 | 3312 | tinsn_init (targ); |
7c430684 | 3313 | targ->linenum = insn->linenum; |
e0001a05 NC |
3314 | switch (bi->typ) |
3315 | { | |
3316 | case INSTR_INSTR: | |
3317 | op = bi->ops; | |
3318 | targ->opcode = bi->opcode; | |
3319 | targ->insn_type = ITYPE_INSN; | |
3320 | targ->is_specific_opcode = FALSE; | |
3321 | ||
3322 | for (; op != NULL; op = op->next) | |
3323 | { | |
3324 | int op_num = op->op_num; | |
3325 | int op_data = op->op_data; | |
3326 | ||
3327 | assert (op->op_num < MAX_INSN_ARGS); | |
3328 | ||
3329 | if (targ->ntok <= op_num) | |
3330 | targ->ntok = op_num + 1; | |
3331 | ||
3332 | switch (op->typ) | |
3333 | { | |
3334 | case OP_CONSTANT: | |
3335 | set_expr_const (&targ->tok[op_num], op_data); | |
3336 | break; | |
3337 | case OP_OPERAND: | |
3338 | assert (op_data < insn->ntok); | |
3339 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3340 | break; | |
3341 | case OP_LITERAL: | |
3342 | sym = get_special_literal_symbol (); | |
3343 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3344 | break; | |
3345 | case OP_LABEL: | |
3346 | sym = get_special_label_symbol (); | |
3347 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3348 | break; | |
43cd72b9 BW |
3349 | case OP_OPERAND_HI16U: |
3350 | case OP_OPERAND_LOW16U: | |
3351 | assert (op_data < insn->ntok); | |
3352 | if (expr_is_const (&insn->tok[op_data])) | |
3353 | { | |
3354 | long val; | |
3355 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3356 | val = xg_apply_userdef_op_fn (op->typ, | |
3357 | targ->tok[op_num]. | |
3358 | X_add_number); | |
3359 | targ->tok[op_num].X_add_number = val; | |
3360 | } | |
3361 | else | |
3362 | { | |
3363 | /* For const16 we can create relocations for these. */ | |
3364 | if (targ->opcode == XTENSA_UNDEFINED | |
3365 | || (targ->opcode != xtensa_const16_opcode)) | |
3366 | return FALSE; | |
3367 | assert (op_data < insn->ntok); | |
3368 | /* Need to build a O_lo16 or O_hi16. */ | |
3369 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3370 | if (targ->tok[op_num].X_op == O_symbol) | |
3371 | { | |
3372 | if (op->typ == OP_OPERAND_HI16U) | |
3373 | targ->tok[op_num].X_op = O_hi16; | |
3374 | else if (op->typ == OP_OPERAND_LOW16U) | |
3375 | targ->tok[op_num].X_op = O_lo16; | |
3376 | else | |
3377 | return FALSE; | |
3378 | } | |
3379 | } | |
3380 | break; | |
e0001a05 NC |
3381 | default: |
3382 | /* currently handles: | |
3383 | OP_OPERAND_LOW8 | |
3384 | OP_OPERAND_HI24S | |
3385 | OP_OPERAND_F32MINUS */ | |
3386 | if (xg_has_userdef_op_fn (op->typ)) | |
3387 | { | |
3388 | assert (op_data < insn->ntok); | |
3389 | if (expr_is_const (&insn->tok[op_data])) | |
3390 | { | |
3391 | long val; | |
3392 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3393 | val = xg_apply_userdef_op_fn (op->typ, | |
3394 | targ->tok[op_num]. | |
3395 | X_add_number); | |
3396 | targ->tok[op_num].X_add_number = val; | |
3397 | } | |
3398 | else | |
3399 | return FALSE; /* We cannot use a relocation for this. */ | |
3400 | break; | |
3401 | } | |
3402 | assert (0); | |
3403 | break; | |
3404 | } | |
3405 | } | |
3406 | break; | |
3407 | ||
3408 | case INSTR_LITERAL_DEF: | |
3409 | op = bi->ops; | |
3410 | targ->opcode = XTENSA_UNDEFINED; | |
3411 | targ->insn_type = ITYPE_LITERAL; | |
3412 | targ->is_specific_opcode = FALSE; | |
3413 | for (; op != NULL; op = op->next) | |
3414 | { | |
3415 | int op_num = op->op_num; | |
3416 | int op_data = op->op_data; | |
3417 | assert (op->op_num < MAX_INSN_ARGS); | |
3418 | ||
3419 | if (targ->ntok <= op_num) | |
3420 | targ->ntok = op_num + 1; | |
3421 | ||
3422 | switch (op->typ) | |
3423 | { | |
3424 | case OP_OPERAND: | |
3425 | assert (op_data < insn->ntok); | |
43cd72b9 BW |
3426 | /* We can only pass resolvable literals through. */ |
3427 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3428 | return FALSE; | |
e0001a05 NC |
3429 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3430 | break; | |
3431 | case OP_LITERAL: | |
3432 | case OP_CONSTANT: | |
3433 | case OP_LABEL: | |
3434 | default: | |
3435 | assert (0); | |
3436 | break; | |
3437 | } | |
3438 | } | |
3439 | break; | |
3440 | ||
3441 | case INSTR_LABEL_DEF: | |
3442 | op = bi->ops; | |
3443 | targ->opcode = XTENSA_UNDEFINED; | |
3444 | targ->insn_type = ITYPE_LABEL; | |
3445 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3446 | /* Literal with no ops is a label? */ |
e0001a05 NC |
3447 | assert (op == NULL); |
3448 | break; | |
3449 | ||
3450 | default: | |
3451 | assert (0); | |
3452 | } | |
3453 | ||
3454 | return TRUE; | |
3455 | } | |
3456 | ||
3457 | ||
43cd72b9 | 3458 | /* Return TRUE on success. */ |
e0001a05 | 3459 | |
7fa3d080 BW |
3460 | static bfd_boolean |
3461 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3462 | { |
3463 | for (; bi != NULL; bi = bi->next) | |
3464 | { | |
3465 | TInsn *next_insn = istack_push_space (istack); | |
3466 | ||
3467 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3468 | return FALSE; | |
3469 | } | |
3470 | return TRUE; | |
3471 | } | |
3472 | ||
3473 | ||
43cd72b9 | 3474 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3475 | |
7fa3d080 BW |
3476 | static bfd_boolean |
3477 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3478 | { |
3479 | int stack_size = istack->ninsn; | |
3480 | int steps_taken = 0; | |
43cd72b9 | 3481 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3482 | TransitionList *l; |
3483 | ||
3484 | assert (insn->insn_type == ITYPE_INSN); | |
3485 | assert (insn->opcode < table->num_opcodes); | |
3486 | ||
3487 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3488 | { | |
3489 | TransitionRule *rule = l->rule; | |
3490 | ||
3491 | if (xg_instruction_matches_rule (insn, rule)) | |
3492 | { | |
3493 | if (lateral_steps == steps_taken) | |
3494 | { | |
3495 | int i; | |
3496 | ||
3497 | /* This is it. Expand the rule to the stack. */ | |
3498 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3499 | return FALSE; | |
3500 | ||
3501 | /* Check to see if it fits. */ | |
3502 | for (i = stack_size; i < istack->ninsn; i++) | |
3503 | { | |
3504 | TInsn *insn = &istack->insn[i]; | |
3505 | ||
3506 | if (insn->insn_type == ITYPE_INSN | |
3507 | && !tinsn_has_symbolic_operands (insn) | |
3508 | && !xg_immeds_fit (insn)) | |
3509 | { | |
3510 | istack->ninsn = stack_size; | |
3511 | return FALSE; | |
3512 | } | |
3513 | } | |
3514 | return TRUE; | |
3515 | } | |
3516 | steps_taken++; | |
3517 | } | |
3518 | } | |
3519 | return FALSE; | |
3520 | } | |
3521 | ||
43cd72b9 | 3522 | \f |
43cd72b9 BW |
3523 | /* Relax the assembly instruction at least "min_steps". |
3524 | Return the number of steps taken. */ | |
e0001a05 | 3525 | |
7fa3d080 BW |
3526 | static int |
3527 | xg_assembly_relax (IStack *istack, | |
3528 | TInsn *insn, | |
3529 | segT pc_seg, | |
3530 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3531 | offsetT pc_offset, /* offset in fragment */ | |
3532 | int min_steps, /* minimum conversion steps */ | |
3533 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3534 | { |
3535 | int steps_taken = 0; | |
3536 | ||
3537 | /* assert (has no symbolic operands) | |
3538 | Some of its immeds don't fit. | |
3539 | Try to build a relaxed version. | |
3540 | This may go through a couple of stages | |
3541 | of single instruction transformations before | |
3542 | we get there. */ | |
3543 | ||
3544 | TInsn single_target; | |
3545 | TInsn current_insn; | |
3546 | int lateral_steps = 0; | |
3547 | int istack_size = istack->ninsn; | |
3548 | ||
3549 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3550 | && steps_taken >= min_steps) | |
3551 | { | |
3552 | istack_push (istack, insn); | |
3553 | return steps_taken; | |
3554 | } | |
43cd72b9 | 3555 | current_insn = *insn; |
e0001a05 | 3556 | |
7c834684 | 3557 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3558 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3559 | { |
21af2bbd | 3560 | steps_taken++; |
e0001a05 NC |
3561 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3562 | stretch)) | |
3563 | { | |
e0001a05 NC |
3564 | if (steps_taken >= min_steps) |
3565 | { | |
3566 | istack_push (istack, &single_target); | |
3567 | return steps_taken; | |
3568 | } | |
3569 | } | |
43cd72b9 | 3570 | current_insn = single_target; |
e0001a05 NC |
3571 | } |
3572 | ||
3573 | /* Now check for a multi-instruction expansion. */ | |
3574 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3575 | { | |
3576 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3577 | stretch)) | |
3578 | { | |
3579 | if (steps_taken >= min_steps) | |
3580 | { | |
3581 | istack_push (istack, ¤t_insn); | |
3582 | return steps_taken; | |
3583 | } | |
3584 | } | |
3585 | steps_taken++; | |
3586 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3587 | { | |
3588 | if (steps_taken >= min_steps) | |
3589 | return steps_taken; | |
3590 | } | |
3591 | lateral_steps++; | |
3592 | istack->ninsn = istack_size; | |
3593 | } | |
3594 | ||
3595 | /* It's not going to work -- use the original. */ | |
3596 | istack_push (istack, insn); | |
3597 | return steps_taken; | |
3598 | } | |
3599 | ||
3600 | ||
3601 | static void | |
7fa3d080 | 3602 | xg_force_frag_space (int size) |
e0001a05 NC |
3603 | { |
3604 | /* This may have the side effect of creating a new fragment for the | |
3605 | space to go into. I just do not like the name of the "frag" | |
3606 | functions. */ | |
3607 | frag_grow (size); | |
3608 | } | |
3609 | ||
3610 | ||
7fa3d080 BW |
3611 | static void |
3612 | xg_finish_frag (char *last_insn, | |
3613 | enum xtensa_relax_statesE frag_state, | |
3614 | enum xtensa_relax_statesE slot0_state, | |
3615 | int max_growth, | |
3616 | bfd_boolean is_insn) | |
e0001a05 NC |
3617 | { |
3618 | /* Finish off this fragment so that it has at LEAST the desired | |
3619 | max_growth. If it doesn't fit in this fragment, close this one | |
3620 | and start a new one. In either case, return a pointer to the | |
3621 | beginning of the growth area. */ | |
3622 | ||
3623 | fragS *old_frag; | |
43cd72b9 | 3624 | |
e0001a05 NC |
3625 | xg_force_frag_space (max_growth); |
3626 | ||
3627 | old_frag = frag_now; | |
3628 | ||
3629 | frag_now->fr_opcode = last_insn; | |
3630 | if (is_insn) | |
3631 | frag_now->tc_frag_data.is_insn = TRUE; | |
3632 | ||
3633 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3634 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3635 | ||
3636 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3637 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3638 | |
3639 | /* Just to make sure that we did not split it up. */ | |
3640 | assert (old_frag->fr_next == frag_now); | |
3641 | } | |
3642 | ||
3643 | ||
7fa3d080 BW |
3644 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3645 | ||
3646 | static bfd_boolean | |
3647 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3648 | { | |
3649 | if (fragP == NULL) | |
3650 | return FALSE; | |
3651 | ||
3652 | for (; fragP; fragP = fragP->fr_next) | |
3653 | { | |
3654 | if (fragP == target) | |
3655 | return TRUE; | |
3656 | if (fragP->fr_fix != 0) | |
3657 | return FALSE; | |
3658 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3659 | return FALSE; | |
3660 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3661 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3662 | return FALSE; | |
3663 | if (fragP->fr_type == rs_space) | |
3664 | return FALSE; | |
3665 | } | |
3666 | return FALSE; | |
3667 | } | |
3668 | ||
3669 | ||
e0001a05 | 3670 | static bfd_boolean |
7fa3d080 | 3671 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3672 | { |
3673 | xtensa_isa isa = xtensa_default_isa; | |
3674 | int i; | |
43cd72b9 | 3675 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3676 | int target_op = -1; |
3677 | symbolS *sym; | |
3678 | fragS *target_frag; | |
3679 | ||
64b607e6 BW |
3680 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3681 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
e0001a05 NC |
3682 | return FALSE; |
3683 | ||
3684 | for (i = 0; i < num_ops; i++) | |
3685 | { | |
43cd72b9 | 3686 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3687 | { |
3688 | target_op = i; | |
3689 | break; | |
3690 | } | |
3691 | } | |
3692 | if (target_op == -1) | |
3693 | return FALSE; | |
3694 | ||
3695 | if (insn->ntok <= target_op) | |
3696 | return FALSE; | |
3697 | ||
3698 | if (insn->tok[target_op].X_op != O_symbol) | |
3699 | return FALSE; | |
3700 | ||
3701 | sym = insn->tok[target_op].X_add_symbol; | |
3702 | if (sym == NULL) | |
3703 | return FALSE; | |
3704 | ||
3705 | if (insn->tok[target_op].X_add_number != 0) | |
3706 | return FALSE; | |
3707 | ||
3708 | target_frag = symbol_get_frag (sym); | |
3709 | if (target_frag == NULL) | |
3710 | return FALSE; | |
3711 | ||
c138bc38 | 3712 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3713 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3714 | return TRUE; | |
3715 | ||
3716 | return FALSE; | |
3717 | } | |
3718 | ||
3719 | ||
3720 | static void | |
7fa3d080 | 3721 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3722 | { |
3723 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3724 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3725 | |
7fa3d080 BW |
3726 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3727 | { | |
3728 | int i = 1; | |
3729 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3730 | && insn->tok[i].X_op == O_symbol) | |
3731 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3732 | return; | |
3733 | } | |
e0001a05 | 3734 | |
7fa3d080 BW |
3735 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3736 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3737 | { |
7fa3d080 BW |
3738 | int i; |
3739 | ||
3740 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3741 | { | |
3742 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3743 | && insn->tok[i].X_op == O_symbol) | |
3744 | { | |
3745 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3746 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3747 | if (S_IS_DEFINED (sym)) | |
3748 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3749 | } | |
3750 | } | |
e0001a05 | 3751 | } |
e0001a05 NC |
3752 | } |
3753 | ||
3754 | ||
43cd72b9 | 3755 | /* Return FALSE if no error. */ |
e0001a05 | 3756 | |
7fa3d080 BW |
3757 | static bfd_boolean |
3758 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3759 | { |
3760 | int num_ops = 0; | |
3761 | BuildOp *b_op; | |
3762 | ||
3763 | switch (instr_spec->typ) | |
3764 | { | |
3765 | case INSTR_INSTR: | |
3766 | new_insn->insn_type = ITYPE_INSN; | |
3767 | new_insn->opcode = instr_spec->opcode; | |
3768 | new_insn->is_specific_opcode = FALSE; | |
7c430684 | 3769 | new_insn->linenum = old_insn->linenum; |
e0001a05 NC |
3770 | break; |
3771 | case INSTR_LITERAL_DEF: | |
3772 | new_insn->insn_type = ITYPE_LITERAL; | |
3773 | new_insn->opcode = XTENSA_UNDEFINED; | |
3774 | new_insn->is_specific_opcode = FALSE; | |
7c430684 | 3775 | new_insn->linenum = old_insn->linenum; |
e0001a05 NC |
3776 | break; |
3777 | case INSTR_LABEL_DEF: | |
3778 | as_bad (_("INSTR_LABEL_DEF not supported yet")); | |
3779 | break; | |
3780 | } | |
3781 | ||
3782 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3783 | { | |
3784 | expressionS *exp; | |
3785 | const expressionS *src_exp; | |
3786 | ||
3787 | num_ops++; | |
3788 | switch (b_op->typ) | |
3789 | { | |
3790 | case OP_CONSTANT: | |
3791 | /* The expression must be the constant. */ | |
3792 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3793 | exp = &new_insn->tok[b_op->op_num]; | |
3794 | set_expr_const (exp, b_op->op_data); | |
3795 | break; | |
3796 | ||
3797 | case OP_OPERAND: | |
3798 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3799 | assert (b_op->op_data < (unsigned) old_insn->ntok); | |
3800 | src_exp = &old_insn->tok[b_op->op_data]; | |
3801 | exp = &new_insn->tok[b_op->op_num]; | |
3802 | copy_expr (exp, src_exp); | |
3803 | break; | |
3804 | ||
3805 | case OP_LITERAL: | |
3806 | case OP_LABEL: | |
3807 | as_bad (_("can't handle generation of literal/labels yet")); | |
3808 | assert (0); | |
3809 | ||
3810 | default: | |
3811 | as_bad (_("can't handle undefined OP TYPE")); | |
3812 | assert (0); | |
3813 | } | |
3814 | } | |
3815 | ||
3816 | new_insn->ntok = num_ops; | |
3817 | return FALSE; | |
3818 | } | |
3819 | ||
3820 | ||
43cd72b9 | 3821 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3822 | |
7fa3d080 BW |
3823 | static bfd_boolean |
3824 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3825 | { |
43cd72b9 | 3826 | TransitionRule *rule; |
e0001a05 | 3827 | BuildInstr *insn_spec; |
43cd72b9 BW |
3828 | |
3829 | if (old_insn->is_specific_opcode || !density_supported) | |
3830 | return FALSE; | |
3831 | ||
3832 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3833 | if (rule == NULL) |
3834 | return FALSE; | |
3835 | ||
3836 | insn_spec = rule->to_instr; | |
3837 | /* There should only be one. */ | |
3838 | assert (insn_spec != NULL); | |
3839 | assert (insn_spec->next == NULL); | |
3840 | if (insn_spec->next != NULL) | |
3841 | return FALSE; | |
3842 | ||
3843 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3844 | ||
3845 | return TRUE; | |
3846 | } | |
3847 | ||
3848 | ||
3849 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3850 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
3851 | tokens into the stack or relax it and place multiple |
3852 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
3853 | |
3854 | static bfd_boolean | |
7fa3d080 | 3855 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
3856 | { |
3857 | int noperands; | |
3858 | TInsn new_insn; | |
7c834684 BW |
3859 | bfd_boolean do_expand; |
3860 | ||
60242db2 | 3861 | tinsn_init (&new_insn); |
e0001a05 | 3862 | |
43cd72b9 BW |
3863 | /* Narrow it if we can. xg_simplify_insn now does all the |
3864 | appropriate checking (e.g., for the density option). */ | |
3865 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
3866 | orig_insn = &new_insn; | |
e0001a05 | 3867 | |
43cd72b9 BW |
3868 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
3869 | orig_insn->opcode); | |
e0001a05 NC |
3870 | if (orig_insn->ntok < noperands) |
3871 | { | |
3872 | as_bad (_("found %d operands for '%s': Expected %d"), | |
3873 | orig_insn->ntok, | |
3874 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3875 | noperands); | |
3876 | return TRUE; | |
3877 | } | |
3878 | if (orig_insn->ntok > noperands) | |
3879 | as_warn (_("found too many (%d) operands for '%s': Expected %d"), | |
3880 | orig_insn->ntok, | |
3881 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3882 | noperands); | |
3883 | ||
43cd72b9 | 3884 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 3885 | are too many, just cut out the extras here. */ |
e0001a05 NC |
3886 | orig_insn->ntok = noperands; |
3887 | ||
e0001a05 NC |
3888 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
3889 | return TRUE; | |
3890 | ||
7c834684 BW |
3891 | /* If the instruction will definitely need to be relaxed, it is better |
3892 | to expand it now for better scheduling. Decide whether to expand | |
3893 | now.... */ | |
3894 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
3895 | ||
3896 | /* Calls should be expanded to longcalls only in the backend relaxation | |
3897 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
3898 | adjacent. */ | |
3899 | if (is_direct_call_opcode (orig_insn->opcode)) | |
3900 | do_expand = FALSE; | |
e0001a05 NC |
3901 | |
3902 | if (tinsn_has_symbolic_operands (orig_insn)) | |
3903 | { | |
7c834684 BW |
3904 | /* The values of symbolic operands are not known yet, so only expand |
3905 | now if an operand is "complex" (e.g., difference of symbols) and | |
3906 | will have to be stored as a literal regardless of the value. */ | |
3907 | if (!tinsn_has_complex_operands (orig_insn)) | |
3908 | do_expand = FALSE; | |
e0001a05 | 3909 | } |
7c834684 BW |
3910 | else if (xg_immeds_fit (orig_insn)) |
3911 | do_expand = FALSE; | |
3912 | ||
3913 | if (do_expand) | |
3914 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 3915 | else |
7c834684 | 3916 | istack_push (istack, orig_insn); |
e0001a05 | 3917 | |
e0001a05 NC |
3918 | return FALSE; |
3919 | } | |
3920 | ||
3921 | ||
7fa3d080 | 3922 | /* Return TRUE if the section flags are marked linkonce |
74869ac7 BW |
3923 | or the name is .gnu.linkonce.*. */ |
3924 | ||
3925 | static int linkonce_len = sizeof (".gnu.linkonce.") - 1; | |
7fa3d080 BW |
3926 | |
3927 | static bfd_boolean | |
3928 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
3929 | { | |
3930 | flagword flags, link_once_flags; | |
3931 | ||
3932 | flags = bfd_get_section_flags (abfd, sec); | |
3933 | link_once_flags = (flags & SEC_LINK_ONCE); | |
3934 | ||
3935 | /* Flags might not be set yet. */ | |
74869ac7 BW |
3936 | if (!link_once_flags |
3937 | && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) | |
3938 | link_once_flags = SEC_LINK_ONCE; | |
7fa3d080 | 3939 | |
7fa3d080 BW |
3940 | return (link_once_flags != 0); |
3941 | } | |
3942 | ||
3943 | ||
3944 | static void | |
3945 | xtensa_add_literal_sym (symbolS *sym) | |
3946 | { | |
3947 | sym_list *l; | |
3948 | ||
3949 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
3950 | l->sym = sym; | |
3951 | l->next = literal_syms; | |
3952 | literal_syms = l; | |
3953 | } | |
3954 | ||
3955 | ||
3956 | static symbolS * | |
3957 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
3958 | { | |
3959 | static int lit_num = 0; | |
3960 | static char name[256]; | |
3961 | symbolS *symbolP; | |
3962 | ||
3963 | sprintf (name, ".L_lit_sym%d", lit_num); | |
3964 | ||
3965 | /* Create a local symbol. If it is in a linkonce section, we have to | |
3966 | be careful to make sure that if it is used in a relocation that the | |
3967 | symbol will be in the output file. */ | |
3968 | if (get_is_linkonce_section (stdoutput, sec)) | |
3969 | { | |
3970 | symbolP = symbol_new (name, sec, 0, frag); | |
3971 | S_CLEAR_EXTERNAL (symbolP); | |
3972 | /* symbolP->local = 1; */ | |
3973 | } | |
3974 | else | |
3975 | symbolP = symbol_new (name, sec, 0, frag); | |
3976 | ||
3977 | xtensa_add_literal_sym (symbolP); | |
3978 | ||
7fa3d080 BW |
3979 | lit_num++; |
3980 | return symbolP; | |
3981 | } | |
3982 | ||
3983 | ||
e0001a05 NC |
3984 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
3985 | ||
7fa3d080 BW |
3986 | static symbolS * |
3987 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
3988 | { |
3989 | emit_state state; | |
3990 | symbolS *lit_sym = NULL; | |
bbdd25a8 BW |
3991 | bfd_reloc_code_real_type reloc; |
3992 | char *p; | |
e0001a05 NC |
3993 | |
3994 | /* size = 4 for L32R. It could easily be larger when we move to | |
3995 | larger constants. Add a parameter later. */ | |
3996 | offsetT litsize = 4; | |
3997 | offsetT litalign = 2; /* 2^2 = 4 */ | |
3998 | expressionS saved_loc; | |
43cd72b9 BW |
3999 | expressionS * emit_val; |
4000 | ||
e0001a05 NC |
4001 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4002 | ||
4003 | assert (insn->insn_type == ITYPE_LITERAL); | |
77cd6497 | 4004 | assert (insn->ntok == 1); /* must be only one token here */ |
e0001a05 NC |
4005 | |
4006 | xtensa_switch_to_literal_fragment (&state); | |
4007 | ||
43cd72b9 BW |
4008 | emit_val = &insn->tok[0]; |
4009 | if (emit_val->X_op == O_big) | |
4010 | { | |
4011 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4012 | if (size > litsize) | |
4013 | { | |
4014 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4015 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4016 | _("invalid immediate")); |
4017 | xtensa_restore_emit_state (&state); | |
4018 | return NULL; | |
4019 | } | |
4020 | } | |
4021 | ||
e0001a05 NC |
4022 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4023 | literals done with this function have a frag to themselves. That's | |
4024 | important for the way text section literals work. */ | |
4025 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4026 | record_alignment (now_seg, litalign); |
e0001a05 | 4027 | |
bbdd25a8 | 4028 | switch (emit_val->X_op) |
43cd72b9 | 4029 | { |
bbdd25a8 BW |
4030 | case O_pltrel: |
4031 | p = frag_more (litsize); | |
43cd72b9 | 4032 | xtensa_set_frag_assembly_state (frag_now); |
bbdd25a8 | 4033 | reloc = map_operator_to_reloc (emit_val->X_op); |
43cd72b9 BW |
4034 | if (emit_val->X_add_symbol) |
4035 | emit_val->X_op = O_symbol; | |
4036 | else | |
4037 | emit_val->X_op = O_constant; | |
4038 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
bbdd25a8 BW |
4039 | litsize, emit_val, 0, reloc); |
4040 | break; | |
4041 | ||
4042 | default: | |
4043 | emit_expr (emit_val, litsize); | |
4044 | break; | |
43cd72b9 | 4045 | } |
e0001a05 NC |
4046 | |
4047 | assert (frag_now->tc_frag_data.literal_frag == NULL); | |
4048 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
4049 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4050 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4051 | |
4052 | /* Go back. */ | |
4053 | xtensa_restore_emit_state (&state); | |
4054 | return lit_sym; | |
4055 | } | |
4056 | ||
4057 | ||
4058 | static void | |
7fa3d080 | 4059 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4060 | { |
4061 | emit_state state; | |
43cd72b9 | 4062 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4063 | takes effect if something is placed here. */ |
4064 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4065 | fragS *lit_saved_frag; | |
4066 | ||
e0001a05 | 4067 | assert (size % 4 == 0); |
e0001a05 NC |
4068 | |
4069 | xtensa_switch_to_literal_fragment (&state); | |
4070 | ||
4071 | /* Force a 4-byte align here. */ | |
4072 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4073 | record_alignment (now_seg, litalign); |
e0001a05 NC |
4074 | |
4075 | xg_force_frag_space (size); | |
4076 | ||
4077 | lit_saved_frag = frag_now; | |
4078 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4079 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
43cd72b9 | 4080 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4081 | |
4082 | /* Go back. */ | |
4083 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4084 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4085 | } |
4086 | ||
4087 | ||
e0001a05 | 4088 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4089 | Return TRUE on success. */ |
e0001a05 | 4090 | |
7fa3d080 BW |
4091 | static bfd_boolean |
4092 | xg_add_opcode_fix (TInsn *tinsn, | |
4093 | int opnum, | |
4094 | xtensa_format fmt, | |
4095 | int slot, | |
4096 | expressionS *expr, | |
4097 | fragS *fragP, | |
4098 | offsetT offset) | |
43cd72b9 BW |
4099 | { |
4100 | xtensa_opcode opcode = tinsn->opcode; | |
4101 | bfd_reloc_code_real_type reloc; | |
4102 | reloc_howto_type *howto; | |
4103 | int fmt_length; | |
e0001a05 NC |
4104 | fixS *the_fix; |
4105 | ||
43cd72b9 BW |
4106 | reloc = BFD_RELOC_NONE; |
4107 | ||
4108 | /* First try the special cases for "alternate" relocs. */ | |
4109 | if (opcode == xtensa_l32r_opcode) | |
4110 | { | |
4111 | if (fragP->tc_frag_data.use_absolute_literals) | |
4112 | reloc = encode_alt_reloc (slot); | |
4113 | } | |
4114 | else if (opcode == xtensa_const16_opcode) | |
4115 | { | |
4116 | if (expr->X_op == O_lo16) | |
4117 | { | |
4118 | reloc = encode_reloc (slot); | |
4119 | expr->X_op = O_symbol; | |
4120 | } | |
4121 | else if (expr->X_op == O_hi16) | |
4122 | { | |
4123 | reloc = encode_alt_reloc (slot); | |
4124 | expr->X_op = O_symbol; | |
4125 | } | |
4126 | } | |
4127 | ||
4128 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4129 | { |
43cd72b9 | 4130 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4131 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4132 | return FALSE; |
4133 | } | |
4134 | ||
43cd72b9 BW |
4135 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4136 | into the symbol table where the generic portions of the assembler | |
4137 | won't know what to do with them. */ | |
4138 | if (expr->X_op == O_lo16 || expr->X_op == O_hi16) | |
4139 | { | |
4140 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4141 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4142 | return FALSE; |
4143 | } | |
4144 | ||
4145 | /* Next try the generic relocs. */ | |
4146 | if (reloc == BFD_RELOC_NONE) | |
4147 | reloc = encode_reloc (slot); | |
4148 | if (reloc == BFD_RELOC_NONE) | |
4149 | { | |
4150 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4151 | return FALSE; | |
4152 | } | |
e0001a05 | 4153 | |
43cd72b9 | 4154 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4155 | if (!howto) |
4156 | { | |
43cd72b9 | 4157 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4158 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4159 | return FALSE; | |
4160 | } | |
4161 | ||
43cd72b9 BW |
4162 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
4163 | the_fix = fix_new_exp (fragP, offset, fmt_length, expr, | |
e0001a05 | 4164 | howto->pc_relative, reloc); |
d9740523 | 4165 | the_fix->fx_no_overflow = 1; |
7fa3d080 BW |
4166 | the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol; |
4167 | the_fix->tc_fix_data.X_add_number = expr->X_add_number; | |
4168 | the_fix->tc_fix_data.slot = slot; | |
c138bc38 | 4169 | |
7fa3d080 BW |
4170 | return TRUE; |
4171 | } | |
4172 | ||
4173 | ||
4174 | static bfd_boolean | |
4175 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4176 | char *buf, |
4177 | fragS *fragP, | |
4178 | offsetT offset, | |
4179 | bfd_boolean build_fix) | |
4180 | { | |
4181 | static xtensa_insnbuf insnbuf = NULL; | |
4182 | bfd_boolean has_symbolic_immed = FALSE; | |
4183 | bfd_boolean ok = TRUE; | |
b2d179be | 4184 | |
7fa3d080 BW |
4185 | if (!insnbuf) |
4186 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4187 | ||
4188 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4189 | if (has_symbolic_immed && build_fix) | |
4190 | { | |
4191 | /* Add a fixup. */ | |
b2d179be BW |
4192 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4193 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4194 | int opnum = get_relaxable_immed (tinsn->opcode); |
4195 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4196 | |
b2d179be | 4197 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4198 | ok = FALSE; |
4199 | } | |
4200 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4201 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4202 | (unsigned char *) buf, 0); | |
7fa3d080 | 4203 | return ok; |
e0001a05 NC |
4204 | } |
4205 | ||
4206 | ||
7fa3d080 BW |
4207 | static void |
4208 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4209 | { |
4210 | symbolS *sym = get_special_literal_symbol (); | |
4211 | int i; | |
4212 | if (lit_sym == 0) | |
4213 | return; | |
4214 | assert (insn->insn_type == ITYPE_INSN); | |
4215 | for (i = 0; i < insn->ntok; i++) | |
4216 | if (insn->tok[i].X_add_symbol == sym) | |
4217 | insn->tok[i].X_add_symbol = lit_sym; | |
4218 | ||
4219 | } | |
4220 | ||
4221 | ||
7fa3d080 BW |
4222 | static void |
4223 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4224 | { |
4225 | symbolS *sym = get_special_label_symbol (); | |
4226 | int i; | |
e0001a05 NC |
4227 | for (i = 0; i < insn->ntok; i++) |
4228 | if (insn->tok[i].X_add_symbol == sym) | |
4229 | insn->tok[i].X_add_symbol = label_sym; | |
4230 | ||
4231 | } | |
4232 | ||
4233 | ||
43cd72b9 | 4234 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4235 | integer register. */ |
4236 | ||
4237 | static bfd_boolean | |
7fa3d080 | 4238 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4239 | { |
4240 | int i; | |
4241 | int num_ops; | |
4242 | xtensa_isa isa = xtensa_default_isa; | |
4243 | ||
43cd72b9 | 4244 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4245 | |
4246 | for (i = 0; i < num_ops; i++) | |
4247 | { | |
43cd72b9 BW |
4248 | char inout; |
4249 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4250 | if ((inout == 'o' || inout == 'm') | |
4251 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4252 | { |
43cd72b9 BW |
4253 | xtensa_regfile opnd_rf = |
4254 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4255 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4256 | { |
4257 | if ((insn->tok[i].X_op == O_register) | |
4258 | && (insn->tok[i].X_add_number == regnum)) | |
4259 | return TRUE; | |
4260 | } | |
4261 | } | |
4262 | } | |
4263 | return FALSE; | |
4264 | } | |
4265 | ||
4266 | ||
4267 | static bfd_boolean | |
7fa3d080 | 4268 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4269 | { |
4270 | xtensa_opcode opcode = tinsn->opcode; | |
4271 | ||
4272 | if (opcode == XTENSA_UNDEFINED) | |
4273 | return FALSE; | |
4274 | ||
4275 | if (opcode == xtensa_call0_opcode | |
4276 | || opcode == xtensa_callx0_opcode | |
4277 | || opcode == xtensa_call4_opcode | |
4278 | || opcode == xtensa_callx4_opcode | |
4279 | || opcode == xtensa_call8_opcode | |
4280 | || opcode == xtensa_callx8_opcode | |
4281 | || opcode == xtensa_call12_opcode | |
4282 | || opcode == xtensa_callx12_opcode | |
4283 | || opcode == xtensa_isync_opcode | |
4284 | || opcode == xtensa_ret_opcode | |
4285 | || opcode == xtensa_ret_n_opcode | |
4286 | || opcode == xtensa_retw_opcode | |
4287 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4288 | || opcode == xtensa_waiti_opcode |
4289 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4290 | return TRUE; |
c138bc38 | 4291 | |
e0001a05 NC |
4292 | return FALSE; |
4293 | } | |
4294 | ||
4295 | ||
4296 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4297 | This allows the debugger to add unaligned labels. | |
4298 | Also, the assembler generates stabs labels that need | |
4299 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4300 | ||
7fa3d080 BW |
4301 | static bfd_boolean |
4302 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4303 | { |
4304 | const char *name = S_GET_NAME (sym); | |
4305 | static size_t fake_size = 0; | |
4306 | ||
4307 | if (name | |
4308 | && name[0] == '.' | |
4309 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4310 | return TRUE; | |
4311 | ||
4312 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4313 | if (fake_size == 0) | |
4314 | fake_size = strlen (FAKE_LABEL_NAME); | |
4315 | ||
43cd72b9 | 4316 | if (name |
e0001a05 NC |
4317 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4318 | && (name[fake_size] == 'F' | |
4319 | || name[fake_size] == 'L' | |
4320 | || (name[fake_size] == 'e' | |
4321 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4322 | return TRUE; | |
4323 | ||
4324 | return FALSE; | |
4325 | } | |
4326 | ||
4327 | ||
7fa3d080 BW |
4328 | static fragS * |
4329 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4330 | { |
4331 | fragS *next_fragP = fragP->fr_next; | |
4332 | ||
c138bc38 | 4333 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4334 | So we have to skip until we find something legit. */ |
4335 | while (next_fragP && next_fragP->fr_fix == 0) | |
4336 | next_fragP = next_fragP->fr_next; | |
4337 | ||
4338 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4339 | return NULL; | |
4340 | ||
4341 | return next_fragP; | |
4342 | } | |
4343 | ||
4344 | ||
43cd72b9 | 4345 | static bfd_boolean |
7fa3d080 | 4346 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4347 | { |
4348 | xtensa_opcode out_opcode; | |
4349 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4350 | ||
4351 | if (next_fragP == NULL) | |
4352 | return FALSE; | |
4353 | ||
4354 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4355 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4356 | { | |
4357 | *opcode = out_opcode; | |
4358 | return TRUE; | |
4359 | } | |
4360 | return FALSE; | |
4361 | } | |
4362 | ||
4363 | ||
4364 | static int | |
7fa3d080 | 4365 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4366 | { |
e0001a05 NC |
4367 | static xtensa_insnbuf insnbuf = NULL; |
4368 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4369 | xtensa_format fmt; |
c138bc38 | 4370 | int fmt_size; |
e0001a05 NC |
4371 | |
4372 | if (!insnbuf) | |
4373 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4374 | ||
43cd72b9 BW |
4375 | if (fragP == NULL) |
4376 | return XTENSA_UNDEFINED; | |
4377 | ||
d77b99c9 BW |
4378 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4379 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4380 | |
4381 | fmt = xtensa_format_decode (isa, insnbuf); | |
4382 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4383 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4384 | fmt_size = xtensa_format_length (isa, fmt); |
4385 | ||
4386 | /* If the next format won't be changing due to relaxation, just | |
4387 | return the length of the first format. */ | |
4388 | if (fragP->fr_opcode != fragP->fr_literal) | |
4389 | return fmt_size; | |
4390 | ||
c138bc38 | 4391 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4392 | multi-slot instruction, we will return the more conservative |
4393 | number. This works because alignment on bigger instructions | |
4394 | is more restrictive than alignment on smaller instructions. | |
4395 | This is more conservative than we would like, but it happens | |
4396 | infrequently. */ | |
4397 | ||
4398 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4399 | return fmt_size; | |
4400 | ||
4401 | /* If we aren't doing one of our own relaxations or it isn't | |
4402 | slot-based, then the insn size won't change. */ | |
4403 | if (fragP->fr_type != rs_machine_dependent) | |
4404 | return fmt_size; | |
4405 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4406 | return fmt_size; | |
4407 | ||
4408 | /* If an instruction is about to grow, return the longer size. */ | |
4409 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
4410 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2) | |
4411 | return 3; | |
c138bc38 | 4412 | |
43cd72b9 BW |
4413 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4414 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4415 | |
43cd72b9 | 4416 | return fmt_size; |
e0001a05 NC |
4417 | } |
4418 | ||
4419 | ||
7fa3d080 BW |
4420 | static int |
4421 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4422 | { |
7fa3d080 BW |
4423 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4424 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4425 | } |
4426 | ||
4427 | ||
03aaa593 BW |
4428 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4429 | required two-byte instructions to be treated as three-byte instructions | |
4430 | for loop instruction alignment. This restriction was removed beginning | |
4431 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4432 | is that the first instruction of the loop must appear at an address that | |
4433 | does not cross a fetch boundary. */ | |
4434 | ||
4435 | static int | |
4436 | get_loop_align_size (int insn_size) | |
4437 | { | |
4438 | if (insn_size == XTENSA_UNDEFINED) | |
4439 | return xtensa_fetch_width; | |
4440 | ||
4441 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4442 | return 3; | |
4443 | ||
4444 | return insn_size; | |
4445 | } | |
4446 | ||
4447 | ||
e0001a05 NC |
4448 | /* If the next legit fragment is an end-of-loop marker, |
4449 | switch its state so it will instantiate a NOP. */ | |
4450 | ||
4451 | static void | |
1d19a770 | 4452 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4453 | { |
4454 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4455 | fragS *new_target = NULL; |
e0001a05 | 4456 | |
7b1cc377 | 4457 | if (align_targets) |
43cd72b9 BW |
4458 | { |
4459 | /* We are guaranteed there will be one of these... */ | |
4460 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4461 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4462 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4463 | next_fragP = next_fragP->fr_next; | |
4464 | ||
4465 | assert (next_fragP->fr_type == rs_machine_dependent | |
4466 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4467 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4468 | ||
4469 | /* ...and one of these. */ | |
4470 | new_target = next_fragP->fr_next; | |
4471 | while (!(new_target->fr_type == rs_machine_dependent | |
4472 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4473 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4474 | new_target = new_target->fr_next; | |
4475 | ||
4476 | assert (new_target->fr_type == rs_machine_dependent | |
4477 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4478 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4479 | } | |
43cd72b9 | 4480 | |
1d19a770 | 4481 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4482 | { |
1d19a770 BW |
4483 | if (next_fragP->fr_type == rs_machine_dependent |
4484 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4485 | { |
1d19a770 BW |
4486 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4487 | return; | |
e0001a05 | 4488 | } |
1d19a770 BW |
4489 | |
4490 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4491 | } |
4492 | } | |
4493 | ||
4494 | ||
4495 | static bfd_boolean | |
7fa3d080 | 4496 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4497 | { |
43cd72b9 | 4498 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4499 | so we have to skip until we find something legit. */ |
4500 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4501 | { | |
4502 | if (fragP->tc_frag_data.is_branch_target) | |
4503 | return TRUE; | |
4504 | if (fragP->fr_fix != 0) | |
4505 | break; | |
4506 | } | |
4507 | return FALSE; | |
4508 | } | |
4509 | ||
4510 | ||
4511 | static bfd_boolean | |
7fa3d080 | 4512 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4513 | { |
c138bc38 | 4514 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4515 | So we have to skip until we find something legit. */ |
4516 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4517 | { | |
4518 | if (fragP->tc_frag_data.is_loop_target) | |
4519 | return TRUE; | |
4520 | if (fragP->fr_fix != 0) | |
4521 | break; | |
4522 | } | |
4523 | return FALSE; | |
4524 | } | |
4525 | ||
4526 | ||
4527 | static addressT | |
7fa3d080 | 4528 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4529 | { |
4530 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4531 | xtensa_opcode next_opcode; |
e0001a05 | 4532 | |
43cd72b9 | 4533 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4534 | return 0; |
4535 | ||
43cd72b9 BW |
4536 | /* Sometimes an empty will end up here due to storage allocation issues, |
4537 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4538 | while (next_fragp->fr_fix == 0) |
4539 | next_fragp = next_fragp->fr_next; | |
4540 | ||
4541 | if (next_fragp->fr_type != rs_machine_dependent) | |
4542 | return 0; | |
4543 | ||
4544 | /* There is some implicit knowledge encoded in here. | |
4545 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4546 | been relaxed. Note that we can assume that the LOOP |
4547 | instruction is in slot 0 because loops aren't bundleable. */ | |
4548 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
e0001a05 NC |
4549 | return get_expanded_loop_offset (next_opcode); |
4550 | ||
4551 | return 0; | |
4552 | } | |
4553 | ||
4554 | ||
4555 | /* Mark a location where we can later insert literal frags. Update | |
4556 | the section's literal_pool_loc, so subsequent literals can be | |
4557 | placed nearest to their use. */ | |
4558 | ||
4559 | static void | |
7fa3d080 | 4560 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4561 | { |
4562 | /* Any labels pointing to the current location need | |
4563 | to be adjusted to after the literal pool. */ | |
4564 | emit_state s; | |
e0001a05 | 4565 | fragS *pool_location; |
e0001a05 | 4566 | |
1f2a7e38 | 4567 | if (use_literal_section) |
43cd72b9 BW |
4568 | return; |
4569 | ||
dd49a749 BW |
4570 | /* We stash info in these frags so we can later move the literal's |
4571 | fixes into this frchain's fix list. */ | |
e0001a05 | 4572 | pool_location = frag_now; |
dd49a749 BW |
4573 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
4574 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4575 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4576 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4577 | frag_now->tc_frag_data.lit_seg = now_seg; |
4578 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4579 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4580 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4581 | |
4582 | /* Now put a frag into the literal pool that points to this location. */ | |
4583 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4584 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4585 | frag_align (2, 0, 0); | |
4586 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4587 | |
4588 | /* Close whatever frag is there. */ | |
4589 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4590 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4591 | frag_now->tc_frag_data.literal_frag = pool_location; |
4592 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4593 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4594 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4595 | } |
4596 | ||
4597 | ||
43cd72b9 BW |
4598 | /* Build a nop of the correct size into tinsn. */ |
4599 | ||
4600 | static void | |
7fa3d080 | 4601 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4602 | { |
4603 | tinsn_init (tinsn); | |
4604 | switch (size) | |
4605 | { | |
4606 | case 2: | |
4607 | tinsn->opcode = xtensa_nop_n_opcode; | |
4608 | tinsn->ntok = 0; | |
4609 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4610 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4611 | break; | |
4612 | ||
4613 | case 3: | |
4614 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4615 | { | |
4616 | tinsn->opcode = xtensa_or_opcode; | |
4617 | set_expr_const (&tinsn->tok[0], 1); | |
4618 | set_expr_const (&tinsn->tok[1], 1); | |
4619 | set_expr_const (&tinsn->tok[2], 1); | |
4620 | tinsn->ntok = 3; | |
4621 | } | |
4622 | else | |
4623 | tinsn->opcode = xtensa_nop_opcode; | |
4624 | ||
4625 | assert (tinsn->opcode != XTENSA_UNDEFINED); | |
4626 | } | |
4627 | } | |
4628 | ||
4629 | ||
e0001a05 NC |
4630 | /* Assemble a NOP of the requested size in the buffer. User must have |
4631 | allocated "buf" with at least "size" bytes. */ | |
4632 | ||
7fa3d080 | 4633 | static void |
d77b99c9 | 4634 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4635 | { |
4636 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4637 | TInsn tinsn; |
e0001a05 | 4638 | |
43cd72b9 | 4639 | build_nop (&tinsn, size); |
e0001a05 | 4640 | |
43cd72b9 BW |
4641 | if (!insnbuf) |
4642 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4643 | |
43cd72b9 | 4644 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4645 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4646 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4647 | } |
4648 | ||
4649 | ||
4650 | /* Return the number of bytes for the offset of the expanded loop | |
4651 | instruction. This should be incorporated into the relaxation | |
4652 | specification but is hard-coded here. This is used to auto-align | |
4653 | the loop instruction. It is invalid to call this function if the | |
4654 | configuration does not have loops or if the opcode is not a loop | |
4655 | opcode. */ | |
4656 | ||
4657 | static addressT | |
7fa3d080 | 4658 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4659 | { |
4660 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4661 | This MUST correspond directly to the specification of the loop | |
4662 | expansion. It will be validated on fragment conversion. */ | |
43cd72b9 | 4663 | assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4664 | if (opcode == xtensa_loop_opcode) |
4665 | return 0; | |
4666 | if (opcode == xtensa_loopnez_opcode) | |
4667 | return 3; | |
4668 | if (opcode == xtensa_loopgtz_opcode) | |
4669 | return 6; | |
4670 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4671 | return 0; | |
4672 | } | |
4673 | ||
4674 | ||
7fa3d080 BW |
4675 | static fragS * |
4676 | get_literal_pool_location (segT seg) | |
e0001a05 NC |
4677 | { |
4678 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; | |
4679 | } | |
4680 | ||
4681 | ||
4682 | static void | |
7fa3d080 | 4683 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4684 | { |
4685 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4686 | } | |
4687 | ||
43cd72b9 BW |
4688 | |
4689 | /* Set frag assembly state should be called when a new frag is | |
4690 | opened and after a frag has been closed. */ | |
4691 | ||
7fa3d080 BW |
4692 | static void |
4693 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4694 | { |
4695 | if (!density_supported) | |
4696 | fragP->tc_frag_data.is_no_density = TRUE; | |
4697 | ||
4698 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4699 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4700 | "use_schedule" here. */ |
4701 | if (!directive_state[directive_transform]) | |
4702 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4703 | if (directive_state[directive_longcalls]) |
4704 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4705 | fragP->tc_frag_data.use_absolute_literals = |
4706 | directive_state[directive_absolute_literals]; | |
4707 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4708 | } | |
4709 | ||
4710 | ||
7fa3d080 BW |
4711 | static bfd_boolean |
4712 | relaxable_section (asection *sec) | |
43cd72b9 BW |
4713 | { |
4714 | return (sec->flags & SEC_DEBUGGING) == 0; | |
4715 | } | |
4716 | ||
4717 | ||
4718 | static void | |
7fa3d080 | 4719 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
4720 | { |
4721 | segT *seclist; | |
4722 | ||
4723 | /* Walk over each fragment of all of the current segments. For each | |
4724 | unmarked fragment, mark it with the same info as the previous | |
4725 | fragment. */ | |
4726 | for (seclist = &stdoutput->sections; | |
4727 | seclist && *seclist; | |
4728 | seclist = &(*seclist)->next) | |
4729 | { | |
4730 | segT sec = *seclist; | |
4731 | segment_info_type *seginfo; | |
4732 | fragS *fragP; | |
4733 | flagword flags; | |
4734 | flags = bfd_get_section_flags (stdoutput, sec); | |
4735 | if (flags & SEC_DEBUGGING) | |
4736 | continue; | |
4737 | if (!(flags & SEC_ALLOC)) | |
4738 | continue; | |
4739 | ||
4740 | seginfo = seg_info (sec); | |
4741 | if (seginfo && seginfo->frchainP) | |
4742 | { | |
4743 | fragS *last_fragP = 0; | |
4744 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4745 | fragP = fragP->fr_next) | |
4746 | { | |
4747 | if (fragP->fr_fix != 0 | |
4748 | && !fragP->tc_frag_data.is_assembly_state_set) | |
4749 | { | |
4750 | if (last_fragP == 0) | |
4751 | { | |
4752 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
4753 | _("assembly state not set for first frag in section %s"), | |
4754 | sec->name); | |
4755 | } | |
4756 | else | |
4757 | { | |
4758 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4759 | fragP->tc_frag_data.is_no_density = | |
4760 | last_fragP->tc_frag_data.is_no_density; | |
4761 | fragP->tc_frag_data.is_no_transform = | |
4762 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
4763 | fragP->tc_frag_data.use_longcalls = |
4764 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
4765 | fragP->tc_frag_data.use_absolute_literals = |
4766 | last_fragP->tc_frag_data.use_absolute_literals; | |
4767 | } | |
4768 | } | |
4769 | if (fragP->tc_frag_data.is_assembly_state_set) | |
4770 | last_fragP = fragP; | |
4771 | } | |
4772 | } | |
4773 | } | |
4774 | } | |
4775 | ||
4776 | ||
4777 | static void | |
7fa3d080 BW |
4778 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
4779 | asection *sec, | |
4780 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4781 | { |
4782 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4783 | segment_info_type *seginfo = seg_info (sec); | |
4784 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 4785 | |
43cd72b9 | 4786 | if (flags & SEC_CODE) |
c138bc38 | 4787 | { |
43cd72b9 BW |
4788 | xtensa_isa isa = xtensa_default_isa; |
4789 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
4790 | while (frag != NULL) | |
4791 | { | |
4792 | if (frag->tc_frag_data.is_branch_target) | |
4793 | { | |
4794 | int op_size; | |
664df4e4 | 4795 | addressT branch_align, frag_addr; |
43cd72b9 BW |
4796 | xtensa_format fmt; |
4797 | ||
d77b99c9 BW |
4798 | xtensa_insnbuf_from_chars |
4799 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4800 | fmt = xtensa_format_decode (isa, insnbuf); |
4801 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
4802 | branch_align = 1 << branch_align_power (sec); |
4803 | frag_addr = frag->fr_address % branch_align; | |
4804 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
4805 | as_warn_where (frag->fr_file, frag->fr_line, |
4806 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 4807 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4808 | } |
4809 | frag = frag->fr_next; | |
4810 | } | |
4811 | xtensa_insnbuf_free (isa, insnbuf); | |
4812 | } | |
4813 | } | |
4814 | ||
4815 | ||
4816 | static void | |
7fa3d080 BW |
4817 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
4818 | asection *sec, | |
4819 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4820 | { |
4821 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4822 | segment_info_type *seginfo = seg_info (sec); | |
4823 | fragS *frag = seginfo->frchainP->frch_root; | |
4824 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 4825 | |
43cd72b9 | 4826 | if (flags & SEC_CODE) |
c138bc38 | 4827 | { |
43cd72b9 BW |
4828 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
4829 | while (frag != NULL) | |
4830 | { | |
4831 | if (frag->tc_frag_data.is_first_loop_insn) | |
4832 | { | |
4833 | int op_size; | |
d77b99c9 | 4834 | addressT frag_addr; |
43cd72b9 BW |
4835 | xtensa_format fmt; |
4836 | ||
d77b99c9 BW |
4837 | xtensa_insnbuf_from_chars |
4838 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4839 | fmt = xtensa_format_decode (isa, insnbuf); |
4840 | op_size = xtensa_format_length (isa, fmt); | |
4841 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
4842 | ||
d77b99c9 | 4843 | if (frag_addr + op_size > xtensa_fetch_width) |
43cd72b9 BW |
4844 | as_warn_where (frag->fr_file, frag->fr_line, |
4845 | _("unaligned loop: %d bytes at 0x%lx"), | |
dd49a749 | 4846 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4847 | } |
4848 | frag = frag->fr_next; | |
4849 | } | |
4850 | xtensa_insnbuf_free (isa, insnbuf); | |
4851 | } | |
4852 | } | |
4853 | ||
4854 | ||
30f725a1 BW |
4855 | static int |
4856 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
4857 | { |
4858 | xtensa_isa isa = xtensa_default_isa; | |
4859 | static xtensa_insnbuf insnbuf = NULL; | |
4860 | static xtensa_insnbuf slotbuf = NULL; | |
4861 | xtensa_format fmt; | |
4862 | int slot; | |
4863 | bfd_boolean alt_reloc; | |
4864 | xtensa_opcode opcode; | |
4865 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
4866 | ||
4867 | (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc); | |
4868 | if (alt_reloc) | |
4869 | as_fatal (_("unexpected fix")); | |
4870 | ||
4871 | if (!insnbuf) | |
4872 | { | |
4873 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4874 | slotbuf = xtensa_insnbuf_alloc (isa); | |
4875 | } | |
4876 | ||
d77b99c9 | 4877 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
4878 | fmt = xtensa_format_decode (isa, insnbuf); |
4879 | if (fmt == XTENSA_UNDEFINED) | |
4880 | as_fatal (_("undecodable fix")); | |
4881 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
4882 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
4883 | if (opcode == XTENSA_UNDEFINED) | |
4884 | as_fatal (_("undecodable fix")); | |
4885 | ||
4886 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
4887 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 4888 | of a CONST16 operand. */ |
43cd72b9 | 4889 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 4890 | return 0; |
43cd72b9 BW |
4891 | |
4892 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
4893 | get_relaxable_immed (opcode), val, | |
4894 | fixP->fx_file, fixP->fx_line); | |
4895 | ||
4896 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 4897 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
4898 | |
4899 | return 1; | |
43cd72b9 BW |
4900 | } |
4901 | ||
e0001a05 NC |
4902 | \f |
4903 | /* External Functions and Other GAS Hooks. */ | |
4904 | ||
4905 | const char * | |
7fa3d080 | 4906 | xtensa_target_format (void) |
e0001a05 NC |
4907 | { |
4908 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
4909 | } | |
4910 | ||
4911 | ||
4912 | void | |
7fa3d080 | 4913 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
4914 | { |
4915 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
4916 | } | |
4917 | ||
4918 | ||
4919 | void | |
7fa3d080 | 4920 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
4921 | { |
4922 | if (target_big_endian) | |
4923 | number_to_chars_bigendian (buf, val, n); | |
4924 | else | |
4925 | number_to_chars_littleendian (buf, val, n); | |
4926 | } | |
4927 | ||
4928 | ||
4929 | /* This function is called once, at assembler startup time. It should | |
4930 | set up all the tables, etc. that the MD part of the assembler will | |
4931 | need. */ | |
4932 | ||
4933 | void | |
7fa3d080 | 4934 | md_begin (void) |
e0001a05 NC |
4935 | { |
4936 | segT current_section = now_seg; | |
4937 | int current_subsec = now_subseg; | |
4938 | xtensa_isa isa; | |
4939 | ||
43cd72b9 | 4940 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 4941 | isa = xtensa_default_isa; |
e0001a05 | 4942 | |
43cd72b9 BW |
4943 | linkrelax = 1; |
4944 | ||
74869ac7 | 4945 | /* Set up the literal sections. */ |
e0001a05 | 4946 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
e0001a05 NC |
4947 | |
4948 | subseg_set (current_section, current_subsec); | |
4949 | ||
43cd72b9 BW |
4950 | xg_init_vinsn (&cur_vinsn); |
4951 | ||
e0001a05 NC |
4952 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); |
4953 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
4954 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
4955 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
4956 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
4957 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
4958 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
4959 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
4960 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
4961 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 4962 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 4963 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
43cd72b9 BW |
4964 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
4965 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 4966 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
e0001a05 | 4967 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 4968 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
4969 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
4970 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
4971 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 4972 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
4973 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
4974 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
4975 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
4976 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
4977 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
4978 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 4979 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 4980 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 BW |
4981 | |
4982 | init_op_placement_info_table (); | |
4983 | ||
4984 | /* Set up the assembly state. */ | |
4985 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
4986 | xtensa_set_frag_assembly_state (frag_now); | |
4987 | } | |
4988 | ||
4989 | ||
4990 | /* TC_INIT_FIX_DATA hook */ | |
4991 | ||
4992 | void | |
7fa3d080 | 4993 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
4994 | { |
4995 | x->tc_fix_data.slot = 0; | |
4996 | x->tc_fix_data.X_add_symbol = NULL; | |
4997 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
4998 | } |
4999 | ||
5000 | ||
5001 | /* tc_frob_label hook */ | |
5002 | ||
5003 | void | |
7fa3d080 | 5004 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5005 | { |
3ea38ac2 BW |
5006 | float freq; |
5007 | ||
5008 | if (cur_vinsn.inside_bundle) | |
5009 | { | |
5010 | as_bad (_("labels are not valid inside bundles")); | |
5011 | return; | |
5012 | } | |
5013 | ||
5014 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5015 | |
43cd72b9 BW |
5016 | /* Since the label was already attached to a frag associated with the |
5017 | previous basic block, it now needs to be reset to the current frag. */ | |
5018 | symbol_set_frag (sym, frag_now); | |
5019 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5020 | ||
82e7541d BW |
5021 | if (generating_literals) |
5022 | xtensa_add_literal_sym (sym); | |
5023 | else | |
5024 | xtensa_add_insn_label (sym); | |
5025 | ||
7b1cc377 BW |
5026 | if (symbol_get_tc (sym)->is_loop_target) |
5027 | { | |
5028 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5029 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5030 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5031 | ||
5032 | xtensa_set_frag_assembly_state (frag_now); | |
5033 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5034 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5035 | ||
5036 | xtensa_set_frag_assembly_state (frag_now); | |
5037 | xtensa_move_labels (frag_now, 0, TRUE); | |
07a53e5c | 5038 | } |
e0001a05 NC |
5039 | |
5040 | /* No target aligning in the absolute section. */ | |
61846f28 | 5041 | if (now_seg != absolute_section |
43cd72b9 | 5042 | && do_align_targets () |
61846f28 | 5043 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5044 | && !generating_literals) |
5045 | { | |
43cd72b9 BW |
5046 | xtensa_set_frag_assembly_state (frag_now); |
5047 | ||
43cd72b9 | 5048 | frag_var (rs_machine_dependent, |
7b1cc377 | 5049 | 0, (int) freq, |
e0001a05 NC |
5050 | RELAX_DESIRE_ALIGN_IF_TARGET, |
5051 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5052 | xtensa_set_frag_assembly_state (frag_now); |
82e7541d | 5053 | xtensa_move_labels (frag_now, 0, TRUE); |
43cd72b9 BW |
5054 | } |
5055 | ||
5056 | /* We need to mark the following properties even if we aren't aligning. */ | |
5057 | ||
5058 | /* If the label is already known to be a branch target, i.e., a | |
5059 | forward branch, mark the frag accordingly. Backward branches | |
5060 | are handled by xg_add_branch_and_loop_targets. */ | |
5061 | if (symbol_get_tc (sym)->is_branch_target) | |
5062 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5063 | ||
5064 | /* Loops only go forward, so they can be identified here. */ | |
5065 | if (symbol_get_tc (sym)->is_loop_target) | |
5066 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5067 | |
5068 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5069 | } |
5070 | ||
5071 | ||
5072 | /* tc_unrecognized_line hook */ | |
5073 | ||
5074 | int | |
7fa3d080 | 5075 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5076 | { |
5077 | switch (ch) | |
5078 | { | |
5079 | case '{' : | |
5080 | if (cur_vinsn.inside_bundle == 0) | |
5081 | { | |
5082 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5083 | when using --gstabs. Temporarily disable debug info. */ | |
5084 | generate_lineno_debug (); | |
5085 | if (debug_type == DEBUG_STABS) | |
5086 | { | |
5087 | xt_saved_debug_type = debug_type; | |
5088 | debug_type = DEBUG_NONE; | |
5089 | } | |
82e7541d | 5090 | |
43cd72b9 BW |
5091 | cur_vinsn.inside_bundle = 1; |
5092 | } | |
5093 | else | |
5094 | { | |
5095 | as_bad (_("extra opening brace")); | |
5096 | return 0; | |
5097 | } | |
5098 | break; | |
82e7541d | 5099 | |
43cd72b9 BW |
5100 | case '}' : |
5101 | if (cur_vinsn.inside_bundle) | |
5102 | finish_vinsn (&cur_vinsn); | |
5103 | else | |
5104 | { | |
5105 | as_bad (_("extra closing brace")); | |
5106 | return 0; | |
5107 | } | |
5108 | break; | |
5109 | default: | |
5110 | as_bad (_("syntax error")); | |
5111 | return 0; | |
e0001a05 | 5112 | } |
43cd72b9 | 5113 | return 1; |
e0001a05 NC |
5114 | } |
5115 | ||
5116 | ||
5117 | /* md_flush_pending_output hook */ | |
5118 | ||
5119 | void | |
7fa3d080 | 5120 | xtensa_flush_pending_output (void) |
e0001a05 | 5121 | { |
43cd72b9 BW |
5122 | if (cur_vinsn.inside_bundle) |
5123 | as_bad (_("missing closing brace")); | |
5124 | ||
e0001a05 NC |
5125 | /* If there is a non-zero instruction fragment, close it. */ |
5126 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5127 | { | |
5128 | frag_wane (frag_now); | |
5129 | frag_new (0); | |
43cd72b9 | 5130 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5131 | } |
5132 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5133 | |
5134 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5135 | } |
5136 | ||
5137 | ||
43cd72b9 BW |
5138 | /* We had an error while parsing an instruction. The string might look |
5139 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5140 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5141 | and the num_slots field will grow past the end of the array of slots, | |
5142 | and bad things happen. */ | |
5143 | ||
5144 | static void | |
7fa3d080 | 5145 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5146 | { |
5147 | if (cur_vinsn.inside_bundle) | |
5148 | { | |
5149 | if (*input_line_pointer == '}' | |
5150 | || *(input_line_pointer - 1) == '}' | |
5151 | || *(input_line_pointer - 2) == '}') | |
5152 | xg_clear_vinsn (&cur_vinsn); | |
5153 | } | |
5154 | } | |
5155 | ||
5156 | ||
e0001a05 | 5157 | void |
7fa3d080 | 5158 | md_assemble (char *str) |
e0001a05 NC |
5159 | { |
5160 | xtensa_isa isa = xtensa_default_isa; | |
7c430684 | 5161 | char *opname, *file_name; |
e0001a05 NC |
5162 | unsigned opnamelen; |
5163 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5164 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5165 | int num_args; |
e0001a05 | 5166 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5167 | |
e0001a05 NC |
5168 | tinsn_init (&orig_insn); |
5169 | ||
5170 | /* Split off the opcode. */ | |
5171 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
5172 | opname = xmalloc (opnamelen + 1); | |
5173 | memcpy (opname, str, opnamelen); | |
5174 | opname[opnamelen] = '\0'; | |
5175 | ||
5176 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5177 | if (num_args == -1) | |
5178 | { | |
5179 | as_bad (_("syntax error")); | |
5180 | return; | |
5181 | } | |
5182 | ||
5183 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5184 | return; | |
5185 | ||
5186 | /* Check for an underbar prefix. */ | |
5187 | if (*opname == '_') | |
5188 | { | |
5189 | has_underbar = TRUE; | |
5190 | opname += 1; | |
5191 | } | |
5192 | ||
5193 | orig_insn.insn_type = ITYPE_INSN; | |
5194 | orig_insn.ntok = 0; | |
43cd72b9 | 5195 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 NC |
5196 | |
5197 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); | |
5198 | if (orig_insn.opcode == XTENSA_UNDEFINED) | |
5199 | { | |
43cd72b9 BW |
5200 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5201 | if (fmt == XTENSA_UNDEFINED) | |
5202 | { | |
5203 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5204 | error_reset_cur_vinsn (); | |
5205 | return; | |
5206 | } | |
5207 | if (!cur_vinsn.inside_bundle) | |
5208 | { | |
5209 | as_bad (_("format names only valid inside bundles")); | |
5210 | error_reset_cur_vinsn (); | |
5211 | return; | |
5212 | } | |
5213 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5214 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5215 | opname); | |
5216 | cur_vinsn.format = fmt; | |
5217 | free (has_underbar ? opname - 1 : opname); | |
5218 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5219 | return; |
5220 | } | |
5221 | ||
e0001a05 NC |
5222 | /* Parse the arguments. */ |
5223 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5224 | { | |
5225 | as_bad (_("syntax error")); | |
43cd72b9 | 5226 | error_reset_cur_vinsn (); |
e0001a05 NC |
5227 | return; |
5228 | } | |
5229 | ||
5230 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5231 | free (has_underbar ? opname - 1 : opname); | |
5232 | opname = 0; | |
5233 | while (num_args-- > 0) | |
5234 | free (arg_strings[num_args]); | |
5235 | ||
43cd72b9 BW |
5236 | /* Get expressions for invisible operands. */ |
5237 | if (get_invisible_operands (&orig_insn)) | |
5238 | { | |
5239 | error_reset_cur_vinsn (); | |
5240 | return; | |
5241 | } | |
5242 | ||
e0001a05 NC |
5243 | /* Check for the right number and type of arguments. */ |
5244 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5245 | { |
43cd72b9 BW |
5246 | error_reset_cur_vinsn (); |
5247 | return; | |
e0001a05 NC |
5248 | } |
5249 | ||
7c430684 BW |
5250 | /* A FLIX bundle may be spread across multiple input lines. We want to |
5251 | report the first such line in the debug information. Record the line | |
5252 | number for each TInsn (assume the file name doesn't change), so the | |
5253 | first line can be found later. */ | |
5254 | as_where (&file_name, &orig_insn.linenum); | |
c138bc38 | 5255 | |
43cd72b9 BW |
5256 | xg_add_branch_and_loop_targets (&orig_insn); |
5257 | ||
431ad2d0 BW |
5258 | /* Check that immediate value for ENTRY is >= 16. */ |
5259 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5260 | { |
431ad2d0 BW |
5261 | expressionS *exp = &orig_insn.tok[2]; |
5262 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5263 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5264 | } |
5265 | ||
e0001a05 | 5266 | /* Finish it off: |
43cd72b9 BW |
5267 | assemble_tokens (opcode, tok, ntok); |
5268 | expand the tokens from the orig_insn into the | |
5269 | stack of instructions that will not expand | |
e0001a05 | 5270 | unless required at relaxation time. */ |
e0001a05 | 5271 | |
43cd72b9 BW |
5272 | if (!cur_vinsn.inside_bundle) |
5273 | emit_single_op (&orig_insn); | |
5274 | else /* We are inside a bundle. */ | |
e0001a05 | 5275 | { |
43cd72b9 BW |
5276 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5277 | cur_vinsn.num_slots++; | |
5278 | if (*input_line_pointer == '}' | |
5279 | || *(input_line_pointer - 1) == '}' | |
5280 | || *(input_line_pointer - 2) == '}') | |
5281 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5282 | } |
5283 | ||
43cd72b9 BW |
5284 | /* We've just emitted a new instruction so clear the list of labels. */ |
5285 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5286 | } |
5287 | ||
5288 | ||
43cd72b9 | 5289 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5290 | |
43cd72b9 BW |
5291 | /* For a .align directive, we mark the previous block with the alignment |
5292 | information. This will be placed in the object file in the | |
5293 | property section corresponding to this section. */ | |
e0001a05 | 5294 | |
43cd72b9 | 5295 | void |
7fa3d080 | 5296 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5297 | { |
5298 | if (linkrelax | |
b08b5071 | 5299 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5300 | && (fragP->fr_type == rs_align |
5301 | || fragP->fr_type == rs_align_code) | |
5302 | && fragP->fr_address + fragP->fr_fix > 0 | |
5303 | && fragP->fr_offset > 0 | |
5304 | && now_seg != bss_section) | |
e0001a05 | 5305 | { |
43cd72b9 BW |
5306 | fragP->tc_frag_data.is_align = TRUE; |
5307 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5308 | } |
5309 | ||
43cd72b9 | 5310 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5311 | { |
43cd72b9 BW |
5312 | int count; |
5313 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5314 | if (count != 0) | |
c138bc38 | 5315 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5316 | _("unaligned entry instruction")); |
e0001a05 | 5317 | } |
e0001a05 | 5318 | } |
43cd72b9 | 5319 | |
e0001a05 NC |
5320 | |
5321 | /* TC_FRAG_INIT hook */ | |
5322 | ||
5323 | void | |
7fa3d080 | 5324 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5325 | { |
43cd72b9 | 5326 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5327 | } |
5328 | ||
5329 | ||
5330 | symbolS * | |
7fa3d080 | 5331 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5332 | { |
5333 | return NULL; | |
5334 | } | |
5335 | ||
5336 | ||
5337 | /* Round up a section size to the appropriate boundary. */ | |
5338 | ||
5339 | valueT | |
7fa3d080 | 5340 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5341 | { |
5342 | return size; /* Byte alignment is fine. */ | |
5343 | } | |
5344 | ||
5345 | ||
5346 | long | |
7fa3d080 | 5347 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5348 | { |
5349 | char *insn_p; | |
5350 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5351 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5352 | int opnum; |
43cd72b9 | 5353 | uint32 opnd_value; |
e0001a05 | 5354 | xtensa_opcode opcode; |
43cd72b9 BW |
5355 | xtensa_format fmt; |
5356 | int slot; | |
e0001a05 NC |
5357 | xtensa_isa isa = xtensa_default_isa; |
5358 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5359 | bfd_boolean alt_reloc; |
e0001a05 | 5360 | |
e0001a05 | 5361 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5362 | return 0; |
e0001a05 NC |
5363 | |
5364 | if (!insnbuf) | |
43cd72b9 BW |
5365 | { |
5366 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5367 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5368 | } | |
e0001a05 NC |
5369 | |
5370 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5371 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5372 | fmt = xtensa_format_decode (isa, insnbuf); |
5373 | ||
5374 | if (fmt == XTENSA_UNDEFINED) | |
5375 | as_fatal (_("bad instruction format")); | |
5376 | ||
5377 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5378 | as_fatal (_("invalid relocation")); | |
5379 | ||
5380 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5381 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5382 | ||
30f725a1 BW |
5383 | /* Check for "alternate" relocations (operand not specified). None |
5384 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5385 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5386 | { | |
5387 | if (opcode != xtensa_l32r_opcode | |
5388 | && opcode != xtensa_const16_opcode) | |
5389 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5390 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5391 | return 0; |
e0001a05 NC |
5392 | } |
5393 | ||
43cd72b9 BW |
5394 | opnum = get_relaxable_immed (opcode); |
5395 | opnd_value = 0; | |
5396 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5397 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5398 | { |
5399 | as_bad_where (fixP->fx_file, | |
5400 | fixP->fx_line, | |
5401 | _("invalid relocation for operand %d of '%s'"), | |
5402 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5403 | return 0; |
e0001a05 | 5404 | } |
43cd72b9 BW |
5405 | return 0 - opnd_value; |
5406 | } | |
5407 | ||
5408 | ||
5409 | /* TC_FORCE_RELOCATION hook */ | |
5410 | ||
5411 | int | |
7fa3d080 | 5412 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5413 | { |
5414 | switch (fix->fx_r_type) | |
30f725a1 BW |
5415 | { |
5416 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5417 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5418 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5419 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5420 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5421 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5422 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5423 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5424 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5425 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5426 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5427 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5428 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5429 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5430 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5431 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5432 | return 1; |
5433 | default: | |
5434 | break; | |
e0001a05 NC |
5435 | } |
5436 | ||
43cd72b9 BW |
5437 | if (linkrelax && fix->fx_addsy |
5438 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5439 | return 1; | |
5440 | ||
5441 | return generic_force_reloc (fix); | |
5442 | } | |
5443 | ||
5444 | ||
30f725a1 BW |
5445 | /* TC_VALIDATE_FIX_SUB hook */ |
5446 | ||
5447 | int | |
5448 | xtensa_validate_fix_sub (fixS *fix) | |
5449 | { | |
5450 | segT add_symbol_segment, sub_symbol_segment; | |
5451 | ||
5452 | /* The difference of two symbols should be resolved by the assembler when | |
5453 | linkrelax is not set. If the linker may relax the section containing | |
5454 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5455 | the linker knows to adjust the difference value. */ | |
5456 | if (!linkrelax || fix->fx_addsy == NULL) | |
5457 | return 0; | |
5458 | ||
5459 | /* Make sure both symbols are in the same segment, and that segment is | |
5460 | "normal" and relaxable. If the segment is not "normal", then the | |
5461 | fix is not valid. If the segment is not "relaxable", then the fix | |
5462 | should have been handled earlier. */ | |
5463 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5464 | if (! SEG_NORMAL (add_symbol_segment) || | |
5465 | ! relaxable_section (add_symbol_segment)) | |
5466 | return 0; | |
5467 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5468 | return (sub_symbol_segment == add_symbol_segment); | |
5469 | } | |
5470 | ||
5471 | ||
43cd72b9 BW |
5472 | /* NO_PSEUDO_DOT hook */ |
5473 | ||
5474 | /* This function has nothing to do with pseudo dots, but this is the | |
5475 | nearest macro to where the check needs to take place. FIXME: This | |
5476 | seems wrong. */ | |
5477 | ||
5478 | bfd_boolean | |
7fa3d080 | 5479 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5480 | { |
5481 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5482 | as_bad (_("directives are not valid inside bundles")); | |
5483 | ||
5484 | /* This function must always return FALSE because it is called via a | |
5485 | macro that has nothing to do with bundling. */ | |
5486 | return FALSE; | |
e0001a05 NC |
5487 | } |
5488 | ||
5489 | ||
43cd72b9 | 5490 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5491 | |
5492 | void | |
7fa3d080 | 5493 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5494 | { |
43cd72b9 BW |
5495 | /* Set up the assembly state. */ |
5496 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5497 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5498 | } |
5499 | ||
5500 | ||
5501 | /* tc_fix_adjustable hook */ | |
5502 | ||
5503 | bfd_boolean | |
7fa3d080 | 5504 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 | 5505 | { |
43cd72b9 BW |
5506 | /* An offset is not allowed in combination with the difference of two |
5507 | symbols, but that cannot be easily detected after a local symbol | |
5508 | has been adjusted to a (section+offset) form. Return 0 so that such | |
5509 | an fix will not be adjusted. */ | |
5510 | if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset | |
5511 | && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy))) | |
5512 | return 0; | |
5513 | ||
e0001a05 NC |
5514 | /* We need the symbol name for the VTABLE entries. */ |
5515 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5516 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5517 | return 0; | |
5518 | ||
5519 | return 1; | |
5520 | } | |
5521 | ||
5522 | ||
5523 | void | |
55cf6793 | 5524 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5525 | { |
30f725a1 | 5526 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5527 | valueT val = 0; |
30f725a1 | 5528 | |
e7da6241 BW |
5529 | /* Subtracted symbols are only allowed for a few relocation types, and |
5530 | unless linkrelax is enabled, they should not make it to this point. */ | |
5531 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5532 | || fixP->fx_r_type == BFD_RELOC_16 | |
5533 | || fixP->fx_r_type == BFD_RELOC_8))) | |
5534 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
5535 | ||
30f725a1 | 5536 | switch (fixP->fx_r_type) |
e0001a05 | 5537 | { |
30f725a1 BW |
5538 | case BFD_RELOC_32: |
5539 | case BFD_RELOC_16: | |
5540 | case BFD_RELOC_8: | |
e7da6241 | 5541 | if (fixP->fx_subsy) |
30f725a1 BW |
5542 | { |
5543 | switch (fixP->fx_r_type) | |
5544 | { | |
5545 | case BFD_RELOC_8: | |
5546 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
5547 | break; | |
5548 | case BFD_RELOC_16: | |
5549 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
5550 | break; | |
5551 | case BFD_RELOC_32: | |
5552 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
5553 | break; | |
5554 | default: | |
5555 | break; | |
5556 | } | |
e0001a05 | 5557 | |
30f725a1 BW |
5558 | /* An offset is only allowed when it results from adjusting a |
5559 | local symbol into a section-relative offset. If the offset | |
5560 | came from the original expression, tc_fix_adjustable will have | |
5561 | prevented the fix from being converted to a section-relative | |
5562 | form so that we can flag the error here. */ | |
5563 | if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy)) | |
5564 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5565 | _("cannot represent subtraction with an offset")); | |
5566 | ||
5567 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5568 | - S_GET_VALUE (fixP->fx_subsy)); | |
5569 | ||
5570 | /* The difference value gets written out, and the DIFF reloc | |
5571 | identifies the address of the subtracted symbol (i.e., the one | |
5572 | with the lowest address). */ | |
5573 | *valP = val; | |
5574 | fixP->fx_offset -= val; | |
5575 | fixP->fx_subsy = NULL; | |
5576 | } | |
5577 | else if (! fixP->fx_addsy) | |
e0001a05 | 5578 | { |
30f725a1 | 5579 | val = *valP; |
e0001a05 | 5580 | fixP->fx_done = 1; |
30f725a1 | 5581 | } |
d47d412e BW |
5582 | /* fall through */ |
5583 | ||
5584 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
5585 | md_number_to_chars (fixpos, val, fixP->fx_size); |
5586 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5587 | break; | |
e0001a05 | 5588 | |
30f725a1 BW |
5589 | case BFD_RELOC_XTENSA_SLOT0_OP: |
5590 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
5591 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
5592 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
5593 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
5594 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
5595 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
5596 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
5597 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
5598 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
5599 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
5600 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
5601 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
5602 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
5603 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
5604 | if (linkrelax) | |
5605 | { | |
5606 | /* Write the tentative value of a PC-relative relocation to a | |
5607 | local symbol into the instruction. The value will be ignored | |
5608 | by the linker, and it makes the object file disassembly | |
5609 | readable when all branch targets are encoded in relocations. */ | |
5610 | ||
5611 | assert (fixP->fx_addsy); | |
20ee54e8 | 5612 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg |
30f725a1 BW |
5613 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) |
5614 | { | |
5615 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5616 | - md_pcrel_from (fixP)); | |
5617 | (void) xg_apply_fix_value (fixP, val); | |
5618 | } | |
5619 | } | |
5620 | else if (! fixP->fx_addsy) | |
5621 | { | |
5622 | val = *valP; | |
5623 | if (xg_apply_fix_value (fixP, val)) | |
5624 | fixP->fx_done = 1; | |
5625 | } | |
5626 | break; | |
e0001a05 | 5627 | |
30f725a1 BW |
5628 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
5629 | case BFD_RELOC_XTENSA_SLOT0_ALT: | |
5630 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5631 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5632 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5633 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5634 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5635 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5636 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5637 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5638 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5639 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5640 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5641 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5642 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5643 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
5644 | /* These all need to be resolved at link-time. Do nothing now. */ | |
5645 | break; | |
e0001a05 | 5646 | |
30f725a1 BW |
5647 | case BFD_RELOC_VTABLE_INHERIT: |
5648 | case BFD_RELOC_VTABLE_ENTRY: | |
5649 | fixP->fx_done = 0; | |
5650 | break; | |
e0001a05 | 5651 | |
30f725a1 BW |
5652 | default: |
5653 | as_bad (_("unhandled local relocation fix %s"), | |
5654 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
5655 | } |
5656 | } | |
5657 | ||
5658 | ||
5659 | char * | |
7fa3d080 | 5660 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 NC |
5661 | { |
5662 | int prec; | |
5663 | LITTLENUM_TYPE words[4]; | |
5664 | char *t; | |
5665 | int i; | |
5666 | ||
5667 | switch (type) | |
5668 | { | |
5669 | case 'f': | |
5670 | prec = 2; | |
5671 | break; | |
5672 | ||
5673 | case 'd': | |
5674 | prec = 4; | |
5675 | break; | |
5676 | ||
5677 | default: | |
5678 | *sizeP = 0; | |
5679 | return "bad call to md_atof"; | |
5680 | } | |
5681 | ||
5682 | t = atof_ieee (input_line_pointer, type, words); | |
5683 | if (t) | |
5684 | input_line_pointer = t; | |
5685 | ||
5686 | *sizeP = prec * 2; | |
5687 | ||
5688 | for (i = prec - 1; i >= 0; i--) | |
5689 | { | |
5690 | int idx = i; | |
5691 | if (target_big_endian) | |
5692 | idx = (prec - 1 - i); | |
5693 | ||
5694 | md_number_to_chars (litP, (valueT) words[idx], 2); | |
5695 | litP += 2; | |
5696 | } | |
5697 | ||
5698 | return NULL; | |
5699 | } | |
5700 | ||
5701 | ||
5702 | int | |
7fa3d080 | 5703 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 5704 | { |
34e41783 | 5705 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
5706 | } |
5707 | ||
5708 | ||
5709 | /* Translate internal representation of relocation info to BFD target | |
5710 | format. */ | |
5711 | ||
5712 | arelent * | |
30f725a1 | 5713 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
5714 | { |
5715 | arelent *reloc; | |
5716 | ||
5717 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
5718 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
5719 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
5720 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
5721 | ||
5722 | /* Make sure none of our internal relocations make it this far. | |
5723 | They'd better have been fully resolved by this point. */ | |
5724 | assert ((int) fixp->fx_r_type > 0); | |
5725 | ||
30f725a1 | 5726 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 5727 | |
e0001a05 NC |
5728 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
5729 | if (reloc->howto == NULL) | |
5730 | { | |
5731 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
5732 | _("cannot represent `%s' relocation in object file"), | |
5733 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
5734 | free (reloc->sym_ptr_ptr); |
5735 | free (reloc); | |
e0001a05 NC |
5736 | return NULL; |
5737 | } | |
5738 | ||
5739 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
43cd72b9 BW |
5740 | as_fatal (_("internal error? cannot generate `%s' relocation"), |
5741 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
e0001a05 | 5742 | |
e0001a05 NC |
5743 | return reloc; |
5744 | } | |
5745 | ||
7fa3d080 BW |
5746 | \f |
5747 | /* Checks for resource conflicts between instructions. */ | |
5748 | ||
c138bc38 BW |
5749 | /* The func unit stuff could be implemented as bit-vectors rather |
5750 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
5751 | slow, we will switch it. */ |
5752 | ||
c138bc38 | 5753 | resource_table * |
7fa3d080 BW |
5754 | new_resource_table (void *data, |
5755 | int cycles, | |
5756 | int nu, | |
5757 | unit_num_copies_func uncf, | |
5758 | opcode_num_units_func onuf, | |
5759 | opcode_funcUnit_use_unit_func ouuf, | |
5760 | opcode_funcUnit_use_stage_func ousf) | |
5761 | { | |
5762 | int i; | |
5763 | resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); | |
5764 | rt->data = data; | |
5765 | rt->cycles = cycles; | |
5766 | rt->allocated_cycles = cycles; | |
5767 | rt->num_units = nu; | |
5768 | rt->unit_num_copies = uncf; | |
5769 | rt->opcode_num_units = onuf; | |
5770 | rt->opcode_unit_use = ouuf; | |
5771 | rt->opcode_unit_stage = ousf; | |
5772 | ||
0bf60745 | 5773 | rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *)); |
7fa3d080 | 5774 | for (i = 0; i < cycles; i++) |
0bf60745 | 5775 | rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char)); |
7fa3d080 BW |
5776 | |
5777 | return rt; | |
5778 | } | |
5779 | ||
5780 | ||
c138bc38 | 5781 | void |
7fa3d080 BW |
5782 | clear_resource_table (resource_table *rt) |
5783 | { | |
5784 | int i, j; | |
5785 | for (i = 0; i < rt->allocated_cycles; i++) | |
5786 | for (j = 0; j < rt->num_units; j++) | |
5787 | rt->units[i][j] = 0; | |
5788 | } | |
5789 | ||
5790 | ||
5791 | /* We never shrink it, just fake it into thinking so. */ | |
5792 | ||
c138bc38 | 5793 | void |
7fa3d080 BW |
5794 | resize_resource_table (resource_table *rt, int cycles) |
5795 | { | |
5796 | int i, old_cycles; | |
5797 | ||
5798 | rt->cycles = cycles; | |
5799 | if (cycles <= rt->allocated_cycles) | |
5800 | return; | |
5801 | ||
5802 | old_cycles = rt->allocated_cycles; | |
5803 | rt->allocated_cycles = cycles; | |
5804 | ||
0bf60745 BW |
5805 | rt->units = xrealloc (rt->units, |
5806 | rt->allocated_cycles * sizeof (unsigned char *)); | |
7fa3d080 | 5807 | for (i = 0; i < old_cycles; i++) |
0bf60745 BW |
5808 | rt->units[i] = xrealloc (rt->units[i], |
5809 | rt->num_units * sizeof (unsigned char)); | |
7fa3d080 | 5810 | for (i = old_cycles; i < cycles; i++) |
0bf60745 | 5811 | rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char)); |
7fa3d080 BW |
5812 | } |
5813 | ||
5814 | ||
c138bc38 | 5815 | bfd_boolean |
7fa3d080 BW |
5816 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
5817 | { | |
5818 | int i; | |
5819 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5820 | ||
c138bc38 | 5821 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5822 | { |
5823 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5824 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
5825 | int copies_in_use = rt->units[stage + cycle][unit]; | |
5826 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
5827 | if (copies_in_use >= copies) | |
5828 | return FALSE; | |
5829 | } | |
5830 | return TRUE; | |
5831 | } | |
7fa3d080 | 5832 | |
c138bc38 BW |
5833 | |
5834 | void | |
7fa3d080 BW |
5835 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5836 | { | |
5837 | int i; | |
5838 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5839 | ||
c138bc38 | 5840 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5841 | { |
5842 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5843 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
5844 | /* Note that this allows resources to be oversubscribed. That's |
5845 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
5846 | resources_available reports when a resource is over-subscribed, |
5847 | so it's easy to tell. */ | |
5848 | rt->units[stage + cycle][unit]++; | |
5849 | } | |
5850 | } | |
5851 | ||
5852 | ||
c138bc38 | 5853 | void |
7fa3d080 BW |
5854 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5855 | { | |
5856 | int i; | |
5857 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5858 | ||
c138bc38 | 5859 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5860 | { |
5861 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5862 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
0bf60745 | 5863 | assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 5864 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
5865 | } |
5866 | } | |
c138bc38 | 5867 | |
7fa3d080 BW |
5868 | |
5869 | /* Wrapper functions make parameterized resource reservation | |
5870 | more convenient. */ | |
5871 | ||
c138bc38 | 5872 | int |
7fa3d080 BW |
5873 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
5874 | { | |
5875 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 5876 | return use->unit; |
7fa3d080 BW |
5877 | } |
5878 | ||
5879 | ||
c138bc38 | 5880 | int |
7fa3d080 BW |
5881 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
5882 | { | |
5883 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
5884 | return use->stage; | |
5885 | } | |
5886 | ||
5887 | ||
5888 | /* Note that this function does not check issue constraints, but | |
5889 | solely whether the hardware is available to execute the given | |
c138bc38 | 5890 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 5891 | write the same state, or access the same tieports. That is |
a1ace8d8 | 5892 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
5893 | |
5894 | static bfd_boolean | |
5895 | resources_conflict (vliw_insn *vinsn) | |
5896 | { | |
5897 | int i; | |
5898 | static resource_table *rt = NULL; | |
5899 | ||
5900 | /* This is the most common case by far. Optimize it. */ | |
5901 | if (vinsn->num_slots == 1) | |
5902 | return FALSE; | |
43cd72b9 | 5903 | |
c138bc38 | 5904 | if (rt == NULL) |
7fa3d080 BW |
5905 | { |
5906 | xtensa_isa isa = xtensa_default_isa; | |
5907 | rt = new_resource_table | |
5908 | (isa, xtensa_isa_num_pipe_stages (isa), | |
5909 | xtensa_isa_num_funcUnits (isa), | |
5910 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
5911 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
5912 | opcode_funcUnit_use_unit, | |
5913 | opcode_funcUnit_use_stage); | |
5914 | } | |
43cd72b9 | 5915 | |
7fa3d080 | 5916 | clear_resource_table (rt); |
43cd72b9 | 5917 | |
7fa3d080 BW |
5918 | for (i = 0; i < vinsn->num_slots; i++) |
5919 | { | |
5920 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
5921 | return TRUE; | |
5922 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
5923 | } | |
e0001a05 | 5924 | |
7fa3d080 BW |
5925 | return FALSE; |
5926 | } | |
e0001a05 | 5927 | |
7fa3d080 BW |
5928 | \f |
5929 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 5930 | |
7fa3d080 BW |
5931 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
5932 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 5933 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
5934 | |
5935 | ||
43cd72b9 BW |
5936 | /* We have reached the end of a bundle; emit into the frag. */ |
5937 | ||
e0001a05 | 5938 | static void |
7fa3d080 | 5939 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 5940 | { |
43cd72b9 BW |
5941 | IStack slotstack; |
5942 | int i; | |
5943 | char *file_name; | |
d77b99c9 | 5944 | unsigned line; |
e0001a05 | 5945 | |
43cd72b9 | 5946 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
5947 | { |
5948 | xg_clear_vinsn (vinsn); | |
5949 | return; | |
5950 | } | |
43cd72b9 BW |
5951 | |
5952 | /* First, find a format that works. */ | |
5953 | if (vinsn->format == XTENSA_UNDEFINED) | |
5954 | vinsn->format = xg_find_narrowest_format (vinsn); | |
5955 | ||
5956 | if (vinsn->format == XTENSA_UNDEFINED) | |
5957 | { | |
5958 | as_where (&file_name, &line); | |
5959 | as_bad_where (file_name, line, | |
5960 | _("couldn't find a valid instruction format")); | |
5961 | fprintf (stderr, _(" ops were: ")); | |
5962 | for (i = 0; i < vinsn->num_slots; i++) | |
5963 | fprintf (stderr, _(" %s;"), | |
5964 | xtensa_opcode_name (xtensa_default_isa, | |
5965 | vinsn->slots[i].opcode)); | |
5966 | fprintf (stderr, _("\n")); | |
5967 | xg_clear_vinsn (vinsn); | |
5968 | return; | |
5969 | } | |
5970 | ||
5971 | if (vinsn->num_slots | |
5972 | != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) | |
e0001a05 | 5973 | { |
43cd72b9 BW |
5974 | as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), |
5975 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
5976 | xtensa_format_num_slots (xtensa_default_isa, vinsn->format), | |
5977 | vinsn->num_slots); | |
5978 | xg_clear_vinsn (vinsn); | |
5979 | return; | |
5980 | } | |
e0001a05 | 5981 | |
c138bc38 | 5982 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
5983 | { |
5984 | as_where (&file_name, &line); | |
5985 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
5986 | fprintf (stderr, " ops were: "); | |
5987 | for (i = 0; i < vinsn->num_slots; i++) | |
5988 | fprintf (stderr, " %s;", | |
5989 | xtensa_opcode_name (xtensa_default_isa, | |
5990 | vinsn->slots[i].opcode)); | |
5991 | fprintf (stderr, "\n"); | |
5992 | xg_clear_vinsn (vinsn); | |
5993 | return; | |
5994 | } | |
5995 | ||
5996 | for (i = 0; i < vinsn->num_slots; i++) | |
5997 | { | |
5998 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 5999 | { |
43cd72b9 BW |
6000 | symbolS *lit_sym = NULL; |
6001 | int j; | |
6002 | bfd_boolean e = FALSE; | |
6003 | bfd_boolean saved_density = density_supported; | |
6004 | ||
6005 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6006 | if (vinsn->num_slots > 1) | |
6007 | density_supported = FALSE; | |
6008 | ||
6009 | istack_init (&slotstack); | |
6010 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6011 | { |
43cd72b9 BW |
6012 | vinsn->slots[i].opcode = |
6013 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6014 | vinsn->format, i); | |
6015 | vinsn->slots[i].ntok = 0; | |
6016 | } | |
e0001a05 | 6017 | |
43cd72b9 BW |
6018 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6019 | { | |
6020 | e = TRUE; | |
6021 | continue; | |
e0001a05 | 6022 | } |
e0001a05 | 6023 | |
43cd72b9 | 6024 | density_supported = saved_density; |
e0001a05 | 6025 | |
43cd72b9 BW |
6026 | if (e) |
6027 | { | |
6028 | xg_clear_vinsn (vinsn); | |
6029 | return; | |
6030 | } | |
e0001a05 | 6031 | |
0fa77c95 | 6032 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6033 | { |
6034 | TInsn *insn = &slotstack.insn[j]; | |
6035 | if (insn->insn_type == ITYPE_LITERAL) | |
6036 | { | |
6037 | assert (lit_sym == NULL); | |
6038 | lit_sym = xg_assemble_literal (insn); | |
6039 | } | |
6040 | else | |
6041 | { | |
0fa77c95 | 6042 | assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6043 | if (lit_sym) |
6044 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6045 | if (j != slotstack.ninsn - 1) |
6046 | emit_single_op (insn); | |
43cd72b9 BW |
6047 | } |
6048 | } | |
6049 | ||
6050 | if (vinsn->num_slots > 1) | |
6051 | { | |
6052 | if (opcode_fits_format_slot | |
6053 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6054 | vinsn->format, i)) | |
6055 | { | |
6056 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6057 | } | |
6058 | else | |
6059 | { | |
b2d179be | 6060 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6061 | if (vinsn->format == XTENSA_UNDEFINED) |
6062 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6063 | else | |
c138bc38 | 6064 | vinsn->slots[i].opcode |
43cd72b9 BW |
6065 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6066 | vinsn->format, i); | |
6067 | ||
6068 | vinsn->slots[i].ntok = 0; | |
6069 | } | |
6070 | } | |
6071 | else | |
6072 | { | |
6073 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6074 | vinsn->format = XTENSA_UNDEFINED; | |
6075 | } | |
6076 | } | |
6077 | } | |
6078 | ||
6079 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6080 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6081 | { |
6082 | as_where (&file_name, &line); | |
6083 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6084 | fprintf (stderr, " ops were: "); | |
6085 | for (i = 0; i < vinsn->num_slots; i++) | |
6086 | fprintf (stderr, " %s;", | |
6087 | xtensa_opcode_name (xtensa_default_isa, | |
6088 | vinsn->slots[i].opcode)); | |
6089 | fprintf (stderr, "\n"); | |
6090 | xg_clear_vinsn (vinsn); | |
6091 | return; | |
6092 | } | |
6093 | ||
6094 | /* First, find a format that works. */ | |
6095 | if (vinsn->format == XTENSA_UNDEFINED) | |
6096 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6097 | ||
6098 | xg_assemble_vliw_tokens (vinsn); | |
6099 | ||
6100 | xg_clear_vinsn (vinsn); | |
6101 | } | |
6102 | ||
6103 | ||
6104 | /* Given an vliw instruction, what conflicts are there in register | |
6105 | usage and in writes to states and queues? | |
6106 | ||
6107 | This function does two things: | |
6108 | 1. Reports an error when a vinsn contains illegal combinations | |
6109 | of writes to registers states or queues. | |
6110 | 2. Marks individual tinsns as not relaxable if the combination | |
6111 | contains antidependencies. | |
6112 | ||
6113 | Job 2 handles things like swap semantics in instructions that need | |
6114 | to be relaxed. For example, | |
6115 | ||
6116 | addi a0, a1, 100000 | |
6117 | ||
6118 | normally would be relaxed to | |
6119 | ||
6120 | l32r a0, some_label | |
6121 | add a0, a1, a0 | |
6122 | ||
6123 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6124 | ||
6125 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6126 | ||
6127 | then we can't relax it into | |
6128 | ||
6129 | l32r a0, some_label | |
6130 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6131 | ||
6132 | because the value of a0 is trashed before the second add can read it. */ | |
6133 | ||
7fa3d080 BW |
6134 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6135 | ||
43cd72b9 | 6136 | static bfd_boolean |
7fa3d080 | 6137 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6138 | { |
6139 | int i, j; | |
6140 | int branches = 0; | |
6141 | xtensa_isa isa = xtensa_default_isa; | |
6142 | ||
6143 | assert (!past_xtensa_end); | |
6144 | ||
6145 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6146 | { | |
6147 | TInsn *op1 = &vinsn->slots[i]; | |
6148 | if (op1->is_specific_opcode) | |
6149 | op1->keep_wide = TRUE; | |
6150 | else | |
6151 | op1->keep_wide = FALSE; | |
6152 | } | |
6153 | ||
6154 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6155 | { | |
6156 | TInsn *op1 = &vinsn->slots[i]; | |
6157 | ||
6158 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6159 | branches++; | |
6160 | ||
6161 | for (j = 0; j < vinsn->num_slots; j++) | |
6162 | { | |
6163 | if (i != j) | |
6164 | { | |
6165 | TInsn *op2 = &vinsn->slots[j]; | |
6166 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6167 | switch (conflict_type) | |
6168 | { | |
6169 | case 'c': | |
6170 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6171 | xtensa_opcode_name (isa, op1->opcode), i, | |
6172 | xtensa_opcode_name (isa, op2->opcode), j); | |
6173 | return TRUE; | |
6174 | case 'd': | |
6175 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6176 | xtensa_opcode_name (isa, op1->opcode), i, | |
6177 | xtensa_opcode_name (isa, op2->opcode), j); | |
6178 | return TRUE; | |
6179 | case 'e': | |
53dfbcc7 | 6180 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6181 | xtensa_opcode_name (isa, op1->opcode), i, |
6182 | xtensa_opcode_name (isa, op2->opcode), j); | |
6183 | return TRUE; | |
6184 | case 'f': | |
53dfbcc7 | 6185 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6186 | xtensa_opcode_name (isa, op1->opcode), i, |
6187 | xtensa_opcode_name (isa, op2->opcode), j); | |
6188 | return TRUE; | |
6189 | default: | |
6190 | /* Everything is OK. */ | |
6191 | break; | |
6192 | } | |
6193 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6194 | || conflict_type == 'a'); | |
6195 | } | |
6196 | } | |
6197 | } | |
6198 | ||
6199 | if (branches > 1) | |
6200 | { | |
6201 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6202 | return TRUE; | |
6203 | } | |
6204 | ||
6205 | return FALSE; | |
6206 | } | |
6207 | ||
6208 | ||
a1ace8d8 | 6209 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6210 | Cases found are: |
6211 | ||
6212 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6213 | case B: no relationship between what is read and written (both could | |
6214 | read the same reg though) | |
c138bc38 | 6215 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6216 | bundle) |
6217 | case D: t1 writes a state that t2 also writes | |
6218 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6219 | case F: two volatile queue accesses |
43cd72b9 BW |
6220 | */ |
6221 | ||
6222 | static char | |
7fa3d080 | 6223 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6224 | { |
6225 | xtensa_isa isa = xtensa_default_isa; | |
6226 | xtensa_regfile t1_regfile, t2_regfile; | |
6227 | int t1_reg, t2_reg; | |
6228 | int t1_base_reg, t1_last_reg; | |
6229 | int t2_base_reg, t2_last_reg; | |
6230 | char t1_inout, t2_inout; | |
6231 | int i, j; | |
6232 | char conflict = 'b'; | |
6233 | int t1_states; | |
6234 | int t2_states; | |
6235 | int t1_interfaces; | |
6236 | int t2_interfaces; | |
6237 | bfd_boolean t1_volatile = FALSE; | |
6238 | bfd_boolean t2_volatile = FALSE; | |
6239 | ||
6240 | /* Check registers. */ | |
6241 | for (j = 0; j < t2->ntok; j++) | |
6242 | { | |
6243 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6244 | continue; | |
6245 | ||
6246 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6247 | t2_base_reg = t2->tok[j].X_add_number; | |
6248 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6249 | ||
6250 | for (i = 0; i < t1->ntok; i++) | |
6251 | { | |
6252 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6253 | continue; | |
6254 | ||
6255 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6256 | ||
6257 | if (t1_regfile != t2_regfile) | |
6258 | continue; | |
6259 | ||
6260 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6261 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6262 | ||
6263 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6264 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6265 | { | |
6266 | if (t1_inout == 'm' || t1_inout == 'o' | |
6267 | || t2_inout == 'm' || t2_inout == 'o') | |
6268 | { | |
6269 | conflict = 'a'; | |
6270 | continue; | |
6271 | } | |
6272 | } | |
6273 | ||
6274 | t1_base_reg = t1->tok[i].X_add_number; | |
6275 | t1_last_reg = (t1_base_reg | |
6276 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6277 | ||
6278 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6279 | { | |
6280 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6281 | { | |
6282 | if (t1_reg != t2_reg) | |
6283 | continue; | |
6284 | ||
6285 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6286 | { |
6287 | conflict = 'a'; | |
6288 | continue; | |
6289 | } | |
43cd72b9 | 6290 | |
7fa3d080 BW |
6291 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6292 | { | |
6293 | conflict = 'a'; | |
6294 | continue; | |
6295 | } | |
43cd72b9 | 6296 | |
7fa3d080 BW |
6297 | if (t1_inout != 'i' && t2_inout != 'i') |
6298 | return 'c'; | |
6299 | } | |
6300 | } | |
6301 | } | |
6302 | } | |
43cd72b9 | 6303 | |
7fa3d080 BW |
6304 | /* Check states. */ |
6305 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6306 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6307 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6308 | { |
7fa3d080 BW |
6309 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6310 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6311 | for (i = 0; i < t1_states; i++) | |
6312 | { | |
6313 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6314 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
c138bc38 | 6315 | if (t1_so != t2_so) |
7fa3d080 | 6316 | continue; |
43cd72b9 | 6317 | |
7fa3d080 BW |
6318 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6319 | { | |
6320 | conflict = 'a'; | |
6321 | continue; | |
6322 | } | |
c138bc38 | 6323 | |
7fa3d080 BW |
6324 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6325 | { | |
6326 | conflict = 'a'; | |
6327 | continue; | |
6328 | } | |
c138bc38 | 6329 | |
7fa3d080 BW |
6330 | if (t1_inout != 'i' && t2_inout != 'i') |
6331 | return 'd'; | |
c138bc38 | 6332 | } |
7fa3d080 | 6333 | } |
43cd72b9 | 6334 | |
7fa3d080 BW |
6335 | /* Check tieports. */ |
6336 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6337 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6338 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6339 | { |
7fa3d080 BW |
6340 | xtensa_interface t2_int |
6341 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6342 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6343 | ||
53dfbcc7 | 6344 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6345 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6346 | t2_volatile = TRUE; |
a1ace8d8 | 6347 | |
7fa3d080 BW |
6348 | for (i = 0; i < t1_interfaces; i++) |
6349 | { | |
6350 | xtensa_interface t1_int | |
6351 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6352 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6353 | |
53dfbcc7 | 6354 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6355 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6356 | t1_volatile = TRUE; |
a1ace8d8 BW |
6357 | |
6358 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6359 | return 'f'; | |
c138bc38 | 6360 | |
7fa3d080 BW |
6361 | if (t1_int != t2_int) |
6362 | continue; | |
c138bc38 | 6363 | |
7fa3d080 BW |
6364 | if (t2_inout == 'i' && t1_inout == 'o') |
6365 | { | |
6366 | conflict = 'a'; | |
6367 | continue; | |
6368 | } | |
c138bc38 | 6369 | |
7fa3d080 BW |
6370 | if (t1_inout == 'i' && t2_inout == 'o') |
6371 | { | |
6372 | conflict = 'a'; | |
6373 | continue; | |
6374 | } | |
c138bc38 | 6375 | |
7fa3d080 BW |
6376 | if (t1_inout != 'i' && t2_inout != 'i') |
6377 | return 'e'; | |
6378 | } | |
43cd72b9 | 6379 | } |
c138bc38 | 6380 | |
7fa3d080 | 6381 | return conflict; |
43cd72b9 BW |
6382 | } |
6383 | ||
6384 | ||
6385 | static xtensa_format | |
7fa3d080 | 6386 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6387 | { |
6388 | /* Right now we assume that the ops within the vinsn are properly | |
6389 | ordered for the slots that the programmer wanted them in. In | |
6390 | other words, we don't rearrange the ops in hopes of finding a | |
6391 | better format. The scheduler handles that. */ | |
6392 | ||
6393 | xtensa_isa isa = xtensa_default_isa; | |
6394 | xtensa_format format; | |
6395 | vliw_insn v_copy = *vinsn; | |
6396 | xtensa_opcode nop_opcode = xtensa_nop_opcode; | |
6397 | ||
65738a7d BW |
6398 | if (vinsn->num_slots == 1) |
6399 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6400 | ||
43cd72b9 BW |
6401 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6402 | { | |
6403 | v_copy = *vinsn; | |
6404 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) | |
6405 | { | |
6406 | int slot; | |
6407 | int fit = 0; | |
6408 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6409 | { | |
6410 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6411 | { | |
6412 | v_copy.slots[slot].opcode = | |
6413 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6414 | v_copy.slots[slot].ntok = 0; | |
6415 | } | |
6416 | ||
6417 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6418 | format, slot)) | |
6419 | fit++; | |
7fa3d080 | 6420 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6421 | { |
7fa3d080 BW |
6422 | TInsn widened; |
6423 | /* Try the widened version. */ | |
6424 | if (!v_copy.slots[slot].keep_wide | |
6425 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6426 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6427 | &widened, TRUE) | |
7fa3d080 BW |
6428 | && opcode_fits_format_slot (widened.opcode, |
6429 | format, slot)) | |
43cd72b9 | 6430 | { |
7fa3d080 BW |
6431 | v_copy.slots[slot] = widened; |
6432 | fit++; | |
43cd72b9 BW |
6433 | } |
6434 | } | |
6435 | } | |
6436 | if (fit == v_copy.num_slots) | |
6437 | { | |
6438 | *vinsn = v_copy; | |
6439 | xtensa_format_encode (isa, format, vinsn->insnbuf); | |
6440 | vinsn->format = format; | |
6441 | break; | |
6442 | } | |
6443 | } | |
6444 | } | |
6445 | ||
6446 | if (format == xtensa_isa_num_formats (isa)) | |
6447 | return XTENSA_UNDEFINED; | |
6448 | ||
6449 | return format; | |
6450 | } | |
6451 | ||
6452 | ||
6453 | /* Return the additional space needed in a frag | |
6454 | for possible relaxations of any ops in a VLIW insn. | |
6455 | Also fill out the relaxations that might be required of | |
6456 | each tinsn in the vinsn. */ | |
6457 | ||
6458 | static int | |
e7da6241 | 6459 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6460 | { |
e7da6241 | 6461 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6462 | int extra_space = 0; |
6463 | int slot; | |
6464 | ||
6465 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6466 | { | |
6467 | TInsn *tinsn = &vinsn->slots[slot]; | |
6468 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6469 | { | |
6470 | /* A narrow instruction could be widened later to help | |
6471 | alignment issues. */ | |
84b08ed9 | 6472 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6473 | && !tinsn->is_specific_opcode |
6474 | && vinsn->num_slots == 1) | |
6475 | { | |
6476 | /* Difference in bytes between narrow and wide insns... */ | |
6477 | extra_space += 1; | |
6478 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6479 | } |
6480 | } | |
6481 | else | |
6482 | { | |
b08b5071 BW |
6483 | if (workaround_b_j_loop_end |
6484 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6485 | && use_transform ()) |
6486 | { | |
6487 | /* Add 2 of these. */ | |
6488 | extra_space += 3; /* for the nop size */ | |
6489 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6490 | } | |
c138bc38 | 6491 | |
43cd72b9 BW |
6492 | /* Need to assemble it with space for the relocation. */ |
6493 | if (xg_is_relaxable_insn (tinsn, 0) | |
6494 | && !tinsn->is_specific_opcode) | |
6495 | { | |
6496 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6497 | int max_literal_size = | |
6498 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6499 | |
43cd72b9 | 6500 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6501 | |
43cd72b9 | 6502 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6503 | extra_space += max_size; |
6504 | } | |
6505 | else | |
6506 | { | |
e7da6241 BW |
6507 | /* A fix record will be added for this instruction prior |
6508 | to relaxation, so make it end the frag. */ | |
6509 | finish_frag = TRUE; | |
43cd72b9 BW |
6510 | } |
6511 | } | |
6512 | } | |
e7da6241 | 6513 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6514 | return extra_space; |
6515 | } | |
6516 | ||
6517 | ||
6518 | static void | |
b2d179be | 6519 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6520 | { |
6521 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6522 | int slot, chosen_slot; |
43cd72b9 | 6523 | |
b2d179be BW |
6524 | vinsn->format = xg_get_single_format (tinsn->opcode); |
6525 | assert (vinsn->format != XTENSA_UNDEFINED); | |
6526 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); | |
43cd72b9 | 6527 | |
b2d179be BW |
6528 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6529 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6530 | { |
b2d179be BW |
6531 | if (slot == chosen_slot) |
6532 | vinsn->slots[slot] = *tinsn; | |
6533 | else | |
6534 | { | |
6535 | vinsn->slots[slot].opcode = | |
6536 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6537 | vinsn->slots[slot].ntok = 0; | |
6538 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6539 | } | |
43cd72b9 | 6540 | } |
43cd72b9 BW |
6541 | } |
6542 | ||
6543 | ||
6544 | static bfd_boolean | |
7fa3d080 | 6545 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6546 | { |
6547 | int i; | |
6548 | IStack istack; /* put instructions into here */ | |
6549 | symbolS *lit_sym = NULL; | |
6550 | symbolS *label_sym = NULL; | |
6551 | ||
6552 | istack_init (&istack); | |
6553 | ||
6554 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
6555 | Because the scheduling and bundling characteristics of movi and |
6556 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 6557 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 6558 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
6559 | || orig_insn->opcode == xtensa_movi_n_opcode) |
6560 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 6561 | && (orig_insn->tok[1].X_op == O_symbol |
482fd9f9 BW |
6562 | || orig_insn->tok[1].X_op == O_pltrel) |
6563 | && !orig_insn->is_specific_opcode && use_transform ()) | |
43cd72b9 BW |
6564 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
6565 | else | |
6566 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6567 | return TRUE; | |
6568 | ||
6569 | for (i = 0; i < istack.ninsn; i++) | |
6570 | { | |
6571 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 6572 | switch (insn->insn_type) |
43cd72b9 BW |
6573 | { |
6574 | case ITYPE_LITERAL: | |
6575 | assert (lit_sym == NULL); | |
6576 | lit_sym = xg_assemble_literal (insn); | |
6577 | break; | |
6578 | case ITYPE_LABEL: | |
6579 | { | |
6580 | static int relaxed_sym_idx = 0; | |
6581 | char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); | |
6582 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); | |
6583 | colon (label); | |
6584 | assert (label_sym == NULL); | |
6585 | label_sym = symbol_find_or_make (label); | |
6586 | assert (label_sym); | |
6587 | free (label); | |
6588 | } | |
6589 | break; | |
6590 | case ITYPE_INSN: | |
b2d179be BW |
6591 | { |
6592 | vliw_insn v; | |
6593 | if (lit_sym) | |
6594 | xg_resolve_literals (insn, lit_sym); | |
6595 | if (label_sym) | |
6596 | xg_resolve_labels (insn, label_sym); | |
6597 | xg_init_vinsn (&v); | |
6598 | bundle_tinsn (insn, &v); | |
6599 | finish_vinsn (&v); | |
6600 | xg_free_vinsn (&v); | |
6601 | } | |
43cd72b9 BW |
6602 | break; |
6603 | default: | |
6604 | assert (0); | |
6605 | break; | |
6606 | } | |
6607 | } | |
6608 | return FALSE; | |
6609 | } | |
6610 | ||
6611 | ||
34e41783 BW |
6612 | static int |
6613 | total_frag_text_expansion (fragS *fragP) | |
6614 | { | |
6615 | int slot; | |
6616 | int total_expansion = 0; | |
6617 | ||
6618 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
6619 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; | |
6620 | ||
6621 | return total_expansion; | |
6622 | } | |
6623 | ||
6624 | ||
43cd72b9 BW |
6625 | /* Emit a vliw instruction to the current fragment. */ |
6626 | ||
7fa3d080 BW |
6627 | static void |
6628 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 6629 | { |
e7da6241 | 6630 | bfd_boolean finish_frag; |
43cd72b9 BW |
6631 | bfd_boolean is_jump = FALSE; |
6632 | bfd_boolean is_branch = FALSE; | |
6633 | xtensa_isa isa = xtensa_default_isa; | |
6634 | int i; | |
6635 | int insn_size; | |
6636 | int extra_space; | |
6637 | char *f = NULL; | |
6638 | int slot; | |
7c430684 BW |
6639 | unsigned current_line, best_linenum; |
6640 | char *current_file; | |
43cd72b9 | 6641 | |
7c430684 | 6642 | best_linenum = UINT_MAX; |
43cd72b9 BW |
6643 | |
6644 | if (generating_literals) | |
6645 | { | |
6646 | static int reported = 0; | |
6647 | if (reported < 4) | |
6648 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
6649 | _("cannot assemble into a literal fragment")); | |
6650 | if (reported == 3) | |
6651 | as_bad (_("...")); | |
6652 | reported++; | |
6653 | return; | |
6654 | } | |
6655 | ||
6656 | if (frag_now_fix () != 0 | |
b08b5071 | 6657 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 6658 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
b08b5071 | 6659 | || !use_transform () != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
6660 | || (directive_state[directive_longcalls] |
6661 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
6662 | || (directive_state[directive_absolute_literals] |
6663 | != frag_now->tc_frag_data.use_absolute_literals))) | |
6664 | { | |
6665 | frag_wane (frag_now); | |
6666 | frag_new (0); | |
6667 | xtensa_set_frag_assembly_state (frag_now); | |
6668 | } | |
6669 | ||
6670 | if (workaround_a0_b_retw | |
6671 | && vinsn->num_slots == 1 | |
6672 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
6673 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
6674 | && use_transform ()) | |
6675 | { | |
6676 | has_a0_b_retw = TRUE; | |
6677 | ||
6678 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
6679 | After the first assembly pass we will check all of them and | |
6680 | add a nop if needed. */ | |
6681 | frag_now->tc_frag_data.is_insn = TRUE; | |
6682 | frag_var (rs_machine_dependent, 4, 4, | |
6683 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6684 | frag_now->fr_symbol, | |
6685 | frag_now->fr_offset, | |
6686 | NULL); | |
6687 | xtensa_set_frag_assembly_state (frag_now); | |
6688 | frag_now->tc_frag_data.is_insn = TRUE; | |
6689 | frag_var (rs_machine_dependent, 4, 4, | |
6690 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6691 | frag_now->fr_symbol, | |
6692 | frag_now->fr_offset, | |
6693 | NULL); | |
6694 | xtensa_set_frag_assembly_state (frag_now); | |
6695 | } | |
6696 | ||
6697 | for (i = 0; i < vinsn->num_slots; i++) | |
6698 | { | |
6699 | /* See if the instruction implies an aligned section. */ | |
6700 | if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1) | |
6701 | record_alignment (now_seg, 2); | |
c138bc38 | 6702 | |
43cd72b9 | 6703 | /* Also determine the best line number for debug info. */ |
7c430684 BW |
6704 | best_linenum = vinsn->slots[i].linenum < best_linenum |
6705 | ? vinsn->slots[i].linenum : best_linenum; | |
43cd72b9 BW |
6706 | } |
6707 | ||
6708 | /* Special cases for instructions that force an alignment... */ | |
6709 | /* None of these opcodes are bundle-able. */ | |
6710 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
6711 | { | |
d77b99c9 | 6712 | int max_fill; |
c138bc38 | 6713 | |
05d58145 BW |
6714 | /* Remember the symbol that marks the end of the loop in the frag |
6715 | that marks the start of the loop. This way we can easily find | |
6716 | the end of the loop at the beginning, without adding special code | |
6717 | to mark the loop instructions themselves. */ | |
6718 | symbolS *target_sym = NULL; | |
6719 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
6720 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
6721 | ||
43cd72b9 BW |
6722 | xtensa_set_frag_assembly_state (frag_now); |
6723 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 6724 | |
43cd72b9 BW |
6725 | max_fill = get_text_align_max_fill_size |
6726 | (get_text_align_power (xtensa_fetch_width), | |
6727 | TRUE, frag_now->tc_frag_data.is_no_density); | |
6728 | ||
6729 | if (use_transform ()) | |
6730 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 6731 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6732 | else |
c138bc38 | 6733 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 6734 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6735 | xtensa_set_frag_assembly_state (frag_now); |
c138bc38 | 6736 | |
43cd72b9 BW |
6737 | xtensa_move_labels (frag_now, 0, FALSE); |
6738 | } | |
6739 | ||
b08b5071 | 6740 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
6741 | && !vinsn->slots[0].is_specific_opcode) |
6742 | { | |
6743 | xtensa_mark_literal_pool_location (); | |
6744 | xtensa_move_labels (frag_now, 0, TRUE); | |
6745 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); | |
6746 | } | |
6747 | ||
6748 | if (vinsn->num_slots == 1) | |
6749 | { | |
6750 | if (workaround_a0_b_retw && use_transform ()) | |
6751 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
6752 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
6753 | ||
6754 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
6755 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
6756 | } | |
6757 | else | |
6758 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
6759 | ||
6760 | insn_size = xtensa_format_length (isa, vinsn->format); | |
6761 | ||
e7da6241 | 6762 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
6763 | |
6764 | /* vinsn_to_insnbuf will produce the error. */ | |
6765 | if (vinsn->format != XTENSA_UNDEFINED) | |
6766 | { | |
d77b99c9 | 6767 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
6768 | xtensa_set_frag_assembly_state (frag_now); |
6769 | frag_now->tc_frag_data.is_insn = TRUE; | |
6770 | } | |
6771 | ||
e7da6241 | 6772 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
6773 | if (vinsn->format == XTENSA_UNDEFINED) |
6774 | return; | |
6775 | ||
d77b99c9 | 6776 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 6777 | |
7c430684 BW |
6778 | /* Temporarily set the logical line number to the one we want to appear |
6779 | in the debug information. */ | |
6780 | as_where (¤t_file, ¤t_line); | |
6781 | new_logical_line (current_file, best_linenum); | |
6782 | dwarf2_emit_insn (insn_size + extra_space); | |
6783 | new_logical_line (current_file, current_line); | |
43cd72b9 BW |
6784 | |
6785 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6786 | { | |
6787 | TInsn *tinsn = &vinsn->slots[slot]; | |
6788 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; | |
7c834684 | 6789 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 6790 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 BW |
6791 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
6792 | if (tinsn->literal_space != 0) | |
6793 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
6794 | ||
6795 | if (tinsn->subtype == RELAX_NARROW) | |
6796 | assert (vinsn->num_slots == 1); | |
6797 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) | |
6798 | is_jump = TRUE; | |
6799 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
6800 | is_branch = TRUE; | |
6801 | ||
e7da6241 BW |
6802 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
6803 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
6804 | finish_frag = TRUE; |
6805 | } | |
6806 | ||
6807 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 6808 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
6809 | |
6810 | if (finish_frag) | |
6811 | { | |
6812 | frag_variant (rs_machine_dependent, | |
6813 | extra_space, extra_space, RELAX_SLOTS, | |
6814 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
6815 | xtensa_set_frag_assembly_state (frag_now); | |
6816 | } | |
6817 | ||
6818 | /* Special cases for loops: | |
6819 | close_loop_end should be inserted AFTER short_loop. | |
6820 | Make sure that CLOSE loops are processed BEFORE short_loops | |
6821 | when converting them. */ | |
6822 | ||
6823 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 6824 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
6825 | && !vinsn->slots[0].is_specific_opcode) |
6826 | { | |
6827 | if (workaround_short_loop && use_transform ()) | |
6828 | { | |
6829 | maybe_has_short_loop = TRUE; | |
6830 | frag_now->tc_frag_data.is_insn = TRUE; | |
6831 | frag_var (rs_machine_dependent, 4, 4, | |
6832 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6833 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6834 | frag_now->tc_frag_data.is_insn = TRUE; | |
6835 | frag_var (rs_machine_dependent, 4, 4, | |
6836 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6837 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6838 | } | |
6839 | ||
6840 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
6841 | loop at least 12 bytes away from another loop's end. */ | |
6842 | if (workaround_close_loop_end && use_transform ()) | |
6843 | { | |
6844 | maybe_has_close_loop_end = TRUE; | |
6845 | frag_now->tc_frag_data.is_insn = TRUE; | |
6846 | frag_var (rs_machine_dependent, 12, 12, | |
6847 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
6848 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6849 | } | |
6850 | } | |
6851 | ||
6852 | if (use_transform ()) | |
6853 | { | |
6854 | if (is_jump) | |
6855 | { | |
6856 | assert (finish_frag); | |
6857 | frag_var (rs_machine_dependent, | |
6858 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6859 | RELAX_UNREACHABLE, | |
6860 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6861 | xtensa_set_frag_assembly_state (frag_now); | |
6862 | } | |
7b1cc377 | 6863 | else if (is_branch && do_align_targets ()) |
43cd72b9 BW |
6864 | { |
6865 | assert (finish_frag); | |
6866 | frag_var (rs_machine_dependent, | |
6867 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6868 | RELAX_MAYBE_UNREACHABLE, | |
6869 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6870 | xtensa_set_frag_assembly_state (frag_now); | |
6871 | frag_var (rs_machine_dependent, | |
6872 | 0, 0, | |
6873 | RELAX_MAYBE_DESIRE_ALIGN, | |
6874 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6875 | xtensa_set_frag_assembly_state (frag_now); | |
6876 | } | |
6877 | } | |
6878 | ||
6879 | /* Now, if the original opcode was a call... */ | |
6880 | if (do_align_targets () | |
6881 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
6882 | { | |
b08b5071 | 6883 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
6884 | frag_now->tc_frag_data.is_insn = TRUE; |
6885 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
6886 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6887 | xtensa_set_frag_assembly_state (frag_now); | |
6888 | } | |
6889 | ||
6890 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
6891 | { | |
6892 | frag_wane (frag_now); | |
6893 | frag_new (0); | |
6894 | xtensa_set_frag_assembly_state (frag_now); | |
6895 | } | |
6896 | } | |
6897 | ||
6898 | \f | |
7fa3d080 BW |
6899 | /* xtensa_end and helper functions. */ |
6900 | ||
6901 | static void xtensa_cleanup_align_frags (void); | |
6902 | static void xtensa_fix_target_frags (void); | |
6903 | static void xtensa_mark_narrow_branches (void); | |
6904 | static void xtensa_mark_zcl_first_insns (void); | |
6905 | static void xtensa_fix_a0_b_retw_frags (void); | |
6906 | static void xtensa_fix_b_j_loop_end_frags (void); | |
6907 | static void xtensa_fix_close_loop_end_frags (void); | |
6908 | static void xtensa_fix_short_loop_frags (void); | |
6909 | static void xtensa_sanity_check (void); | |
2caa7ca0 | 6910 | static void xtensa_add_config_info (void); |
7fa3d080 | 6911 | |
43cd72b9 | 6912 | void |
7fa3d080 | 6913 | xtensa_end (void) |
43cd72b9 BW |
6914 | { |
6915 | directive_balance (); | |
6916 | xtensa_flush_pending_output (); | |
6917 | ||
6918 | past_xtensa_end = TRUE; | |
6919 | ||
6920 | xtensa_move_literals (); | |
6921 | ||
6922 | xtensa_reorder_segments (); | |
6923 | xtensa_cleanup_align_frags (); | |
6924 | xtensa_fix_target_frags (); | |
6925 | if (workaround_a0_b_retw && has_a0_b_retw) | |
6926 | xtensa_fix_a0_b_retw_frags (); | |
6927 | if (workaround_b_j_loop_end) | |
6928 | xtensa_fix_b_j_loop_end_frags (); | |
6929 | ||
6930 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
6931 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
6932 | xtensa_fix_close_loop_end_frags (); | |
6933 | ||
6934 | if (workaround_short_loop && maybe_has_short_loop) | |
6935 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
6936 | if (align_targets) |
6937 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
6938 | xtensa_mark_zcl_first_insns (); |
6939 | ||
6940 | xtensa_sanity_check (); | |
2caa7ca0 BW |
6941 | |
6942 | xtensa_add_config_info (); | |
43cd72b9 BW |
6943 | } |
6944 | ||
6945 | ||
6946 | static void | |
7fa3d080 | 6947 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
6948 | { |
6949 | frchainS *frchP; | |
c9049d30 | 6950 | asection *s; |
43cd72b9 | 6951 | |
c9049d30 AM |
6952 | for (s = stdoutput->sections; s; s = s->next) |
6953 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
6954 | { | |
6955 | fragS *fragP; | |
6956 | /* Walk over all of the fragments in a subsection. */ | |
6957 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
6958 | { | |
6959 | if ((fragP->fr_type == rs_align | |
6960 | || fragP->fr_type == rs_align_code | |
6961 | || (fragP->fr_type == rs_machine_dependent | |
6962 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
6963 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
6964 | && fragP->fr_fix == 0) | |
6965 | { | |
6966 | fragS *next = fragP->fr_next; | |
6967 | ||
6968 | while (next | |
6969 | && next->fr_fix == 0 | |
6970 | && next->fr_type == rs_machine_dependent | |
6971 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
6972 | { | |
6973 | frag_wane (next); | |
6974 | next = next->fr_next; | |
6975 | } | |
6976 | } | |
6977 | /* If we don't widen branch targets, then they | |
6978 | will be easier to align. */ | |
6979 | if (fragP->tc_frag_data.is_branch_target | |
6980 | && fragP->fr_opcode == fragP->fr_literal | |
6981 | && fragP->fr_type == rs_machine_dependent | |
6982 | && fragP->fr_subtype == RELAX_SLOTS | |
6983 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
6984 | frag_wane (fragP); | |
6985 | if (fragP->fr_type == rs_machine_dependent | |
6986 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
6987 | fragP->tc_frag_data.is_unreachable = TRUE; | |
6988 | } | |
6989 | } | |
43cd72b9 BW |
6990 | } |
6991 | ||
6992 | ||
6993 | /* Re-process all of the fragments looking to convert all of the | |
6994 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
6995 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 6996 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 6997 | |
43cd72b9 | 6998 | static void |
7fa3d080 | 6999 | xtensa_fix_target_frags (void) |
e0001a05 NC |
7000 | { |
7001 | frchainS *frchP; | |
c9049d30 | 7002 | asection *s; |
e0001a05 NC |
7003 | |
7004 | /* When this routine is called, all of the subsections are still intact | |
7005 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7006 | for (s = stdoutput->sections; s; s = s->next) |
7007 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7008 | { | |
7009 | fragS *fragP; | |
e0001a05 | 7010 | |
c9049d30 AM |
7011 | /* Walk over all of the fragments in a subsection. */ |
7012 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7013 | { | |
7014 | if (fragP->fr_type == rs_machine_dependent | |
7015 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7016 | { | |
7017 | if (next_frag_is_branch_target (fragP)) | |
7018 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
7019 | else | |
7020 | frag_wane (fragP); | |
7021 | } | |
7022 | } | |
7023 | } | |
e0001a05 NC |
7024 | } |
7025 | ||
7026 | ||
7fa3d080 BW |
7027 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7028 | ||
43cd72b9 | 7029 | static void |
7fa3d080 | 7030 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
7031 | { |
7032 | frchainS *frchP; | |
c9049d30 | 7033 | asection *s; |
43cd72b9 | 7034 | |
c9049d30 AM |
7035 | for (s = stdoutput->sections; s; s = s->next) |
7036 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7037 | { | |
7038 | fragS *fragP; | |
7039 | /* Walk over all of the fragments in a subsection. */ | |
7040 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7041 | { | |
7042 | if (fragP->fr_type == rs_machine_dependent | |
7043 | && fragP->fr_subtype == RELAX_SLOTS | |
7044 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
7045 | { | |
7046 | vliw_insn vinsn; | |
7047 | ||
7048 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
7049 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
7050 | ||
7051 | if (vinsn.num_slots == 1 | |
7052 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 7053 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
7054 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
7055 | && is_narrow_branch_guaranteed_in_range (fragP, | |
7056 | &vinsn.slots[0])) | |
7057 | { | |
7058 | fragP->fr_subtype = RELAX_SLOTS; | |
7059 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
7060 | fragP->tc_frag_data.is_aligning_branch = 1; | |
7061 | } | |
7062 | } | |
7063 | } | |
7064 | } | |
43cd72b9 BW |
7065 | } |
7066 | ||
7067 | ||
7068 | /* A branch is typically widened only when its target is out of | |
7069 | range. However, we would like to widen them to align a subsequent | |
7070 | branch target when possible. | |
7071 | ||
7072 | Because the branch relaxation code is so convoluted, the optimal solution | |
7073 | (combining the two cases) is difficult to get right in all circumstances. | |
7074 | We therefore go with an "almost as good" solution, where we only | |
7075 | use for alignment narrow branches that definitely will not expand to a | |
7076 | jump and a branch. These functions find and mark these cases. */ | |
7077 | ||
a67517f4 BW |
7078 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
7079 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
7080 | We start counting beginning with the frag after the 2-byte branch, so the | |
7081 | maximum offset is (4 - 2) + 63 = 65. */ | |
7082 | #define MAX_IMMED6 65 | |
43cd72b9 | 7083 | |
d77b99c9 | 7084 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 7085 | |
43cd72b9 | 7086 | static bfd_boolean |
7fa3d080 | 7087 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 BW |
7088 | { |
7089 | const expressionS *expr = &tinsn->tok[1]; | |
7090 | symbolS *symbolP = expr->X_add_symbol; | |
d77b99c9 | 7091 | offsetT max_distance = expr->X_add_number; |
e7da6241 BW |
7092 | fragS *target_frag; |
7093 | ||
7094 | if (expr->X_op != O_symbol) | |
7095 | return FALSE; | |
7096 | ||
7097 | target_frag = symbol_get_frag (symbolP); | |
7098 | ||
43cd72b9 BW |
7099 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
7100 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
7101 | return FALSE; | |
7102 | ||
7103 | /* The branch doesn't branch over it's own frag, | |
7104 | but over the subsequent ones. */ | |
7105 | fragP = fragP->fr_next; | |
7106 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
7107 | { | |
7108 | max_distance += unrelaxed_frag_max_size (fragP); | |
7109 | fragP = fragP->fr_next; | |
7110 | } | |
7111 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
7112 | return TRUE; | |
e0001a05 NC |
7113 | return FALSE; |
7114 | } | |
7115 | ||
7116 | ||
43cd72b9 | 7117 | static void |
7fa3d080 | 7118 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
7119 | { |
7120 | frchainS *frchP; | |
c9049d30 | 7121 | asection *s; |
43cd72b9 | 7122 | |
c9049d30 AM |
7123 | for (s = stdoutput->sections; s; s = s->next) |
7124 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7125 | { | |
7126 | fragS *fragP; | |
7127 | /* Walk over all of the fragments in a subsection. */ | |
7128 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7129 | { | |
7130 | if (fragP->fr_type == rs_machine_dependent | |
7131 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
7132 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
7133 | { | |
7134 | /* Find the loop frag. */ | |
7135 | fragS *targ_frag = next_non_empty_frag (fragP); | |
7136 | /* Find the first insn frag. */ | |
7137 | targ_frag = next_non_empty_frag (targ_frag); | |
7138 | ||
7139 | /* Of course, sometimes (mostly for toy test cases) a | |
7140 | zero-cost loop instruction is the last in a section. */ | |
7141 | if (targ_frag) | |
7142 | { | |
7143 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
7144 | /* Do not widen a frag that is the first instruction of a | |
7145 | zero-cost loop. It makes that loop harder to align. */ | |
7146 | if (targ_frag->fr_type == rs_machine_dependent | |
7147 | && targ_frag->fr_subtype == RELAX_SLOTS | |
7148 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
7149 | == RELAX_NARROW)) | |
7150 | { | |
7151 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
7152 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
7153 | else | |
7154 | { | |
7155 | frag_wane (targ_frag); | |
7156 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
7157 | } | |
7158 | } | |
7159 | } | |
7160 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
7161 | frag_wane (fragP); | |
7162 | } | |
7163 | } | |
7164 | } | |
43cd72b9 BW |
7165 | } |
7166 | ||
7167 | ||
e0001a05 NC |
7168 | /* Re-process all of the fragments looking to convert all of the |
7169 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
7170 | conditional branch or a retw/retw.n, convert this frag to one that | |
7171 | will generate a NOP. In any case close it off with a .fill 0. */ | |
7172 | ||
7fa3d080 BW |
7173 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
7174 | ||
e0001a05 | 7175 | static void |
7fa3d080 | 7176 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
7177 | { |
7178 | frchainS *frchP; | |
c9049d30 | 7179 | asection *s; |
e0001a05 NC |
7180 | |
7181 | /* When this routine is called, all of the subsections are still intact | |
7182 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7183 | for (s = stdoutput->sections; s; s = s->next) |
7184 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7185 | { | |
7186 | fragS *fragP; | |
e0001a05 | 7187 | |
c9049d30 AM |
7188 | /* Walk over all of the fragments in a subsection. */ |
7189 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7190 | { | |
7191 | if (fragP->fr_type == rs_machine_dependent | |
7192 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
7193 | { | |
7194 | if (next_instrs_are_b_retw (fragP)) | |
7195 | { | |
7196 | if (fragP->tc_frag_data.is_no_transform) | |
7197 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
7198 | else | |
7199 | relax_frag_add_nop (fragP); | |
7200 | } | |
7201 | frag_wane (fragP); | |
7202 | } | |
7203 | } | |
7204 | } | |
e0001a05 NC |
7205 | } |
7206 | ||
7207 | ||
7fa3d080 BW |
7208 | static bfd_boolean |
7209 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
7210 | { |
7211 | xtensa_opcode opcode; | |
43cd72b9 | 7212 | xtensa_format fmt; |
e0001a05 NC |
7213 | const fragS *next_fragP = next_non_empty_frag (fragP); |
7214 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 7215 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
7216 | xtensa_isa isa = xtensa_default_isa; |
7217 | int offset = 0; | |
43cd72b9 BW |
7218 | int slot; |
7219 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
7220 | |
7221 | if (!insnbuf) | |
43cd72b9 BW |
7222 | { |
7223 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7224 | slotbuf = xtensa_insnbuf_alloc (isa); | |
7225 | } | |
e0001a05 NC |
7226 | |
7227 | if (next_fragP == NULL) | |
7228 | return FALSE; | |
7229 | ||
7230 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
7231 | xtensa_insnbuf_from_chars |
7232 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7233 | fmt = xtensa_format_decode (isa, insnbuf); |
7234 | if (fmt == XTENSA_UNDEFINED) | |
7235 | return FALSE; | |
7236 | ||
7237 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
7238 | { | |
7239 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
7240 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
7241 | ||
7242 | branch_seen = (branch_seen | |
7243 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
7244 | } | |
e0001a05 | 7245 | |
43cd72b9 | 7246 | if (!branch_seen) |
e0001a05 NC |
7247 | return FALSE; |
7248 | ||
43cd72b9 | 7249 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7250 | if (offset == next_fragP->fr_fix) |
7251 | { | |
7252 | next_fragP = next_non_empty_frag (next_fragP); | |
7253 | offset = 0; | |
7254 | } | |
43cd72b9 | 7255 | |
e0001a05 NC |
7256 | if (next_fragP == NULL) |
7257 | return FALSE; | |
7258 | ||
7259 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
7260 | xtensa_insnbuf_from_chars |
7261 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7262 | fmt = xtensa_format_decode (isa, insnbuf); |
7263 | ||
7264 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
7265 | have no problems. */ | |
7266 | if (fmt == XTENSA_UNDEFINED | |
7267 | || xtensa_format_num_slots (isa, fmt) != 1) | |
7268 | return FALSE; | |
7269 | ||
7270 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
7271 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 7272 | |
b08b5071 | 7273 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 7274 | return TRUE; |
43cd72b9 | 7275 | |
e0001a05 NC |
7276 | return FALSE; |
7277 | } | |
7278 | ||
7279 | ||
7280 | /* Re-process all of the fragments looking to convert all of the | |
7281 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
7282 | loop end label, convert this frag to one that will generate a NOP. | |
7283 | In any case close it off with a .fill 0. */ | |
7284 | ||
7fa3d080 BW |
7285 | static bfd_boolean next_instr_is_loop_end (fragS *); |
7286 | ||
e0001a05 | 7287 | static void |
7fa3d080 | 7288 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
7289 | { |
7290 | frchainS *frchP; | |
c9049d30 | 7291 | asection *s; |
e0001a05 NC |
7292 | |
7293 | /* When this routine is called, all of the subsections are still intact | |
7294 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7295 | for (s = stdoutput->sections; s; s = s->next) |
7296 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7297 | { | |
7298 | fragS *fragP; | |
e0001a05 | 7299 | |
c9049d30 AM |
7300 | /* Walk over all of the fragments in a subsection. */ |
7301 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7302 | { | |
7303 | if (fragP->fr_type == rs_machine_dependent | |
7304 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
7305 | { | |
7306 | if (next_instr_is_loop_end (fragP)) | |
7307 | { | |
7308 | if (fragP->tc_frag_data.is_no_transform) | |
7309 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
7310 | else | |
7311 | relax_frag_add_nop (fragP); | |
7312 | } | |
7313 | frag_wane (fragP); | |
7314 | } | |
7315 | } | |
7316 | } | |
e0001a05 NC |
7317 | } |
7318 | ||
7319 | ||
7fa3d080 BW |
7320 | static bfd_boolean |
7321 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
7322 | { |
7323 | const fragS *next_fragP; | |
7324 | ||
7325 | if (next_frag_is_loop_target (fragP)) | |
7326 | return FALSE; | |
7327 | ||
7328 | next_fragP = next_non_empty_frag (fragP); | |
7329 | if (next_fragP == NULL) | |
7330 | return FALSE; | |
7331 | ||
7332 | if (!next_frag_is_loop_target (next_fragP)) | |
7333 | return FALSE; | |
7334 | ||
7335 | /* If the size is >= 3 then there is more than one instruction here. | |
7336 | The hardware bug will not fire. */ | |
7337 | if (next_fragP->fr_fix > 3) | |
7338 | return FALSE; | |
7339 | ||
7340 | return TRUE; | |
7341 | } | |
7342 | ||
7343 | ||
7344 | /* Re-process all of the fragments looking to convert all of the | |
7345 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
7346 | not MY loop's loop end within 12 bytes, add enough nops here to | |
7347 | make it at least 12 bytes away. In any case close it off with a | |
7348 | .fill 0. */ | |
7349 | ||
d77b99c9 | 7350 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 7351 | (fragS *, fragS *, offsetT); |
7fa3d080 | 7352 | |
e0001a05 | 7353 | static void |
7fa3d080 | 7354 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
7355 | { |
7356 | frchainS *frchP; | |
c9049d30 | 7357 | asection *s; |
e0001a05 NC |
7358 | |
7359 | /* When this routine is called, all of the subsections are still intact | |
7360 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7361 | for (s = stdoutput->sections; s; s = s->next) |
7362 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7363 | { | |
7364 | fragS *fragP; | |
e0001a05 | 7365 | |
c9049d30 | 7366 | fragS *current_target = NULL; |
e0001a05 | 7367 | |
c9049d30 AM |
7368 | /* Walk over all of the fragments in a subsection. */ |
7369 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7370 | { | |
7371 | if (fragP->fr_type == rs_machine_dependent | |
7372 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7373 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 7374 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 7375 | |
c9049d30 AM |
7376 | if (current_target |
7377 | && fragP->fr_type == rs_machine_dependent | |
7378 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
7379 | { | |
7380 | offsetT min_bytes; | |
7381 | int bytes_added = 0; | |
e0001a05 NC |
7382 | |
7383 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
7384 | /* Max out at 12. */ |
7385 | min_bytes = min_bytes_to_other_loop_end | |
7386 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
7387 | ||
7388 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
7389 | { | |
7390 | if (fragP->tc_frag_data.is_no_transform) | |
7391 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
7392 | else | |
7393 | { | |
7394 | while (min_bytes + bytes_added | |
7395 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
7396 | { | |
7397 | int length = 3; | |
7398 | ||
7399 | if (fragP->fr_var < length) | |
7400 | as_fatal (_("fr_var %lu < length %d"), | |
7401 | (long) fragP->fr_var, length); | |
7402 | else | |
7403 | { | |
7404 | assemble_nop (length, | |
7405 | fragP->fr_literal + fragP->fr_fix); | |
7406 | fragP->fr_fix += length; | |
7407 | fragP->fr_var -= length; | |
7408 | } | |
7409 | bytes_added += length; | |
7410 | } | |
7411 | } | |
7412 | } | |
7413 | frag_wane (fragP); | |
7414 | } | |
7415 | assert (fragP->fr_type != rs_machine_dependent | |
7416 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); | |
7417 | } | |
7418 | } | |
e0001a05 NC |
7419 | } |
7420 | ||
7421 | ||
d77b99c9 | 7422 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 7423 | |
d77b99c9 | 7424 | static offsetT |
7fa3d080 BW |
7425 | min_bytes_to_other_loop_end (fragS *fragP, |
7426 | fragS *current_target, | |
d77b99c9 | 7427 | offsetT max_size) |
e0001a05 | 7428 | { |
d77b99c9 | 7429 | offsetT offset = 0; |
e0001a05 NC |
7430 | fragS *current_fragP; |
7431 | ||
7432 | for (current_fragP = fragP; | |
7433 | current_fragP; | |
7434 | current_fragP = current_fragP->fr_next) | |
7435 | { | |
7436 | if (current_fragP->tc_frag_data.is_loop_target | |
7437 | && current_fragP != current_target) | |
05d58145 | 7438 | return offset; |
e0001a05 NC |
7439 | |
7440 | offset += unrelaxed_frag_min_size (current_fragP); | |
7441 | ||
05d58145 | 7442 | if (offset >= max_size) |
e0001a05 NC |
7443 | return max_size; |
7444 | } | |
7445 | return max_size; | |
7446 | } | |
7447 | ||
7448 | ||
d77b99c9 | 7449 | static offsetT |
7fa3d080 | 7450 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 7451 | { |
d77b99c9 | 7452 | offsetT size = fragP->fr_fix; |
e0001a05 | 7453 | |
d77b99c9 | 7454 | /* Add fill size. */ |
e0001a05 NC |
7455 | if (fragP->fr_type == rs_fill) |
7456 | size += fragP->fr_offset; | |
7457 | ||
7458 | return size; | |
7459 | } | |
7460 | ||
7461 | ||
d77b99c9 | 7462 | static offsetT |
7fa3d080 | 7463 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 7464 | { |
d77b99c9 | 7465 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
7466 | switch (fragP->fr_type) |
7467 | { | |
7468 | case 0: | |
c138bc38 | 7469 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
7470 | end up with type 0. */ |
7471 | break; | |
7472 | case rs_fill: | |
7473 | case rs_org: | |
7474 | case rs_space: | |
7475 | size += fragP->fr_offset; | |
7476 | break; | |
7477 | case rs_align: | |
7478 | case rs_align_code: | |
7479 | case rs_align_test: | |
7480 | case rs_leb128: | |
7481 | case rs_cfa: | |
7482 | case rs_dwarf2dbg: | |
7483 | /* No further adjustments needed. */ | |
7484 | break; | |
7485 | case rs_machine_dependent: | |
7486 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
7487 | size += fragP->fr_var; | |
7488 | break; | |
7489 | default: | |
7490 | /* We had darn well better know how big it is. */ | |
7491 | assert (0); | |
7492 | break; | |
7493 | } | |
7494 | ||
7495 | return size; | |
7496 | } | |
7497 | ||
7498 | ||
e0001a05 NC |
7499 | /* Re-process all of the fragments looking to convert all |
7500 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
7501 | ||
7502 | A) | |
7503 | 1) the instruction size count to the loop end label | |
7504 | is too short (<= 2 instructions), | |
7505 | 2) loop has a jump or branch in it | |
7506 | ||
7507 | or B) | |
43cd72b9 | 7508 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
7509 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
7510 | 3) the instruction size count to the loop end label is too short | |
7511 | (<= 2 instructions) | |
7512 | then convert this frag (and maybe the next one) to generate a NOP. | |
7513 | In any case close it off with a .fill 0. */ | |
7514 | ||
d77b99c9 | 7515 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
7516 | static bfd_boolean branch_before_loop_end (fragS *); |
7517 | ||
e0001a05 | 7518 | static void |
7fa3d080 | 7519 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
7520 | { |
7521 | frchainS *frchP; | |
c9049d30 | 7522 | asection *s; |
e0001a05 NC |
7523 | |
7524 | /* When this routine is called, all of the subsections are still intact | |
7525 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7526 | for (s = stdoutput->sections; s; s = s->next) |
7527 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7528 | { | |
7529 | fragS *fragP; | |
7530 | fragS *current_target = NULL; | |
7531 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; | |
e0001a05 | 7532 | |
c9049d30 AM |
7533 | /* Walk over all of the fragments in a subsection. */ |
7534 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7535 | { | |
7536 | if (fragP->fr_type == rs_machine_dependent | |
7537 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7538 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
7539 | { | |
7540 | TInsn t_insn; | |
7541 | fragS *loop_frag = next_non_empty_frag (fragP); | |
7542 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
7543 | current_target = symbol_get_frag (fragP->fr_symbol); | |
7544 | current_opcode = t_insn.opcode; | |
7545 | assert (xtensa_opcode_is_loop (xtensa_default_isa, | |
64b607e6 | 7546 | current_opcode) == 1); |
c9049d30 | 7547 | } |
e0001a05 | 7548 | |
c9049d30 AM |
7549 | if (fragP->fr_type == rs_machine_dependent |
7550 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7551 | { | |
7552 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 | |
7553 | && (branch_before_loop_end (fragP->fr_next) | |
7554 | || (workaround_all_short_loops | |
7555 | && current_opcode != XTENSA_UNDEFINED | |
7556 | && current_opcode != xtensa_loop_opcode))) | |
7557 | { | |
7558 | if (fragP->tc_frag_data.is_no_transform) | |
7559 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
7560 | else | |
7561 | relax_frag_add_nop (fragP); | |
7562 | } | |
7563 | frag_wane (fragP); | |
7564 | } | |
7565 | } | |
7566 | } | |
e0001a05 NC |
7567 | } |
7568 | ||
7569 | ||
d77b99c9 | 7570 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 7571 | |
d77b99c9 | 7572 | static int |
7fa3d080 BW |
7573 | count_insns_to_loop_end (fragS *base_fragP, |
7574 | bfd_boolean count_relax_add, | |
d77b99c9 | 7575 | int max_count) |
e0001a05 NC |
7576 | { |
7577 | fragS *fragP = NULL; | |
d77b99c9 | 7578 | int insn_count = 0; |
e0001a05 NC |
7579 | |
7580 | fragP = base_fragP; | |
7581 | ||
7582 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
7583 | { | |
7584 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
7585 | if (insn_count >= max_count) | |
7586 | return max_count; | |
7587 | ||
7588 | if (count_relax_add) | |
7589 | { | |
7590 | if (fragP->fr_type == rs_machine_dependent | |
7591 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7592 | { | |
7593 | /* In order to add the appropriate number of | |
7594 | NOPs, we count an instruction for downstream | |
7595 | occurrences. */ | |
7596 | insn_count++; | |
7597 | if (insn_count >= max_count) | |
7598 | return max_count; | |
7599 | } | |
7600 | } | |
7601 | } | |
7602 | return insn_count; | |
7603 | } | |
7604 | ||
7605 | ||
d77b99c9 | 7606 | static int |
7fa3d080 | 7607 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 7608 | { |
43cd72b9 BW |
7609 | xtensa_isa isa = xtensa_default_isa; |
7610 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 7611 | int insn_count = 0; |
e0001a05 NC |
7612 | int offset = 0; |
7613 | ||
7614 | if (!fragP->tc_frag_data.is_insn) | |
7615 | return insn_count; | |
7616 | ||
43cd72b9 BW |
7617 | if (!insnbuf) |
7618 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7619 | ||
e0001a05 NC |
7620 | /* Decode the fixed instructions. */ |
7621 | while (offset < fragP->fr_fix) | |
7622 | { | |
43cd72b9 BW |
7623 | xtensa_format fmt; |
7624 | ||
d77b99c9 BW |
7625 | xtensa_insnbuf_from_chars |
7626 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7627 | fmt = xtensa_format_decode (isa, insnbuf); |
7628 | ||
7629 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
7630 | { |
7631 | as_fatal (_("undecodable instruction in instruction frag")); | |
7632 | return insn_count; | |
7633 | } | |
43cd72b9 | 7634 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7635 | insn_count++; |
7636 | } | |
7637 | ||
7638 | return insn_count; | |
7639 | } | |
7640 | ||
7641 | ||
7fa3d080 BW |
7642 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
7643 | ||
43cd72b9 | 7644 | static bfd_boolean |
7fa3d080 | 7645 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
7646 | { |
7647 | fragS *fragP; | |
7648 | ||
7649 | for (fragP = base_fragP; | |
7650 | fragP && !fragP->tc_frag_data.is_loop_target; | |
7651 | fragP = fragP->fr_next) | |
7652 | { | |
7653 | if (unrelaxed_frag_has_b_j (fragP)) | |
7654 | return TRUE; | |
7655 | } | |
7656 | return FALSE; | |
7657 | } | |
7658 | ||
7659 | ||
43cd72b9 | 7660 | static bfd_boolean |
7fa3d080 | 7661 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 7662 | { |
43cd72b9 BW |
7663 | static xtensa_insnbuf insnbuf = NULL; |
7664 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
7665 | int offset = 0; |
7666 | ||
7667 | if (!fragP->tc_frag_data.is_insn) | |
7668 | return FALSE; | |
7669 | ||
43cd72b9 BW |
7670 | if (!insnbuf) |
7671 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7672 | ||
e0001a05 NC |
7673 | /* Decode the fixed instructions. */ |
7674 | while (offset < fragP->fr_fix) | |
7675 | { | |
43cd72b9 BW |
7676 | xtensa_format fmt; |
7677 | int slot; | |
7678 | ||
d77b99c9 BW |
7679 | xtensa_insnbuf_from_chars |
7680 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7681 | fmt = xtensa_format_decode (isa, insnbuf); |
7682 | if (fmt == XTENSA_UNDEFINED) | |
7683 | return FALSE; | |
7684 | ||
7685 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 7686 | { |
43cd72b9 BW |
7687 | xtensa_opcode opcode = |
7688 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
7689 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
7690 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
7691 | return TRUE; | |
e0001a05 | 7692 | } |
43cd72b9 | 7693 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7694 | } |
7695 | return FALSE; | |
7696 | } | |
7697 | ||
7698 | ||
7699 | /* Checks to be made after initial assembly but before relaxation. */ | |
7700 | ||
7fa3d080 BW |
7701 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
7702 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
7703 | ||
e0001a05 | 7704 | static void |
7fa3d080 | 7705 | xtensa_sanity_check (void) |
e0001a05 NC |
7706 | { |
7707 | char *file_name; | |
d77b99c9 | 7708 | unsigned line; |
e0001a05 | 7709 | frchainS *frchP; |
c9049d30 | 7710 | asection *s; |
e0001a05 NC |
7711 | |
7712 | as_where (&file_name, &line); | |
c9049d30 AM |
7713 | for (s = stdoutput->sections; s; s = s->next) |
7714 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7715 | { | |
7716 | fragS *fragP; | |
e0001a05 | 7717 | |
c9049d30 AM |
7718 | /* Walk over all of the fragments in a subsection. */ |
7719 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7720 | { | |
c9049d30 | 7721 | if (fragP->fr_type == rs_machine_dependent |
a7284bf1 BW |
7722 | && fragP->fr_subtype == RELAX_SLOTS |
7723 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
c9049d30 AM |
7724 | { |
7725 | static xtensa_insnbuf insnbuf = NULL; | |
7726 | TInsn t_insn; | |
7727 | ||
7728 | if (fragP->fr_opcode != NULL) | |
7729 | { | |
7730 | if (!insnbuf) | |
7731 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7732 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
7733 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
7734 | ||
7735 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
7736 | t_insn.opcode) == 1) | |
7737 | { | |
7738 | if (is_empty_loop (&t_insn, fragP)) | |
7739 | { | |
7740 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7741 | as_bad (_("invalid empty loop")); | |
7742 | } | |
7743 | if (!is_local_forward_loop (&t_insn, fragP)) | |
7744 | { | |
7745 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7746 | as_bad (_("loop target does not follow " | |
7747 | "loop instruction in section")); | |
7748 | } | |
7749 | } | |
7750 | } | |
7751 | } | |
7752 | } | |
7753 | } | |
e0001a05 NC |
7754 | new_logical_line (file_name, line); |
7755 | } | |
7756 | ||
7757 | ||
7758 | #define LOOP_IMMED_OPN 1 | |
7759 | ||
43cd72b9 | 7760 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 7761 | |
7fa3d080 BW |
7762 | static bfd_boolean |
7763 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7764 | { |
7765 | const expressionS *expr; | |
7766 | symbolS *symbolP; | |
7767 | fragS *next_fragP; | |
7768 | ||
7769 | if (insn->insn_type != ITYPE_INSN) | |
7770 | return FALSE; | |
7771 | ||
43cd72b9 | 7772 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7773 | return FALSE; |
7774 | ||
7775 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7776 | return FALSE; | |
7777 | ||
7778 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7779 | ||
7780 | if (expr->X_op != O_symbol) | |
7781 | return FALSE; | |
7782 | ||
7783 | symbolP = expr->X_add_symbol; | |
7784 | if (!symbolP) | |
7785 | return FALSE; | |
7786 | ||
7787 | if (symbol_get_frag (symbolP) == NULL) | |
7788 | return FALSE; | |
7789 | ||
7790 | if (S_GET_VALUE (symbolP) != 0) | |
7791 | return FALSE; | |
7792 | ||
7793 | /* Walk through the zero-size fragments from this one. If we find | |
7794 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 7795 | |
e0001a05 NC |
7796 | for (next_fragP = fragP->fr_next; |
7797 | next_fragP != NULL; | |
7798 | next_fragP = next_fragP->fr_next) | |
7799 | { | |
7800 | if (next_fragP == symbol_get_frag (symbolP)) | |
7801 | return TRUE; | |
7802 | if (next_fragP->fr_fix != 0) | |
7803 | return FALSE; | |
7804 | } | |
7805 | return FALSE; | |
7806 | } | |
7807 | ||
7808 | ||
7fa3d080 BW |
7809 | static bfd_boolean |
7810 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7811 | { |
7812 | const expressionS *expr; | |
7813 | symbolS *symbolP; | |
7814 | fragS *next_fragP; | |
7815 | ||
7816 | if (insn->insn_type != ITYPE_INSN) | |
7817 | return FALSE; | |
7818 | ||
64b607e6 | 7819 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7820 | return FALSE; |
7821 | ||
7822 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7823 | return FALSE; | |
7824 | ||
7825 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7826 | ||
7827 | if (expr->X_op != O_symbol) | |
7828 | return FALSE; | |
7829 | ||
7830 | symbolP = expr->X_add_symbol; | |
7831 | if (!symbolP) | |
7832 | return FALSE; | |
7833 | ||
7834 | if (symbol_get_frag (symbolP) == NULL) | |
7835 | return FALSE; | |
7836 | ||
7837 | /* Walk through fragments until we find the target. | |
7838 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 7839 | |
e0001a05 NC |
7840 | for (next_fragP = fragP->fr_next; |
7841 | next_fragP != NULL; | |
7842 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
7843 | { |
7844 | if (next_fragP == symbol_get_frag (symbolP)) | |
7845 | return TRUE; | |
7846 | } | |
e0001a05 NC |
7847 | |
7848 | return FALSE; | |
7849 | } | |
7850 | ||
2caa7ca0 BW |
7851 | |
7852 | #define XTINFO_NAME "Xtensa_Info" | |
7853 | #define XTINFO_NAMESZ 12 | |
7854 | #define XTINFO_TYPE 1 | |
7855 | ||
7856 | static void | |
7857 | xtensa_add_config_info (void) | |
7858 | { | |
7859 | asection *info_sec; | |
7860 | char *data, *p; | |
7861 | int sz; | |
7862 | ||
7863 | info_sec = subseg_new (".xtensa.info", 0); | |
7864 | bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY); | |
7865 | ||
7866 | data = xmalloc (100); | |
7867 | sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", | |
7868 | XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI); | |
7869 | sz = strlen (data) + 1; | |
7870 | ||
7871 | /* Add enough null terminators to pad to a word boundary. */ | |
7872 | do | |
7873 | data[sz++] = 0; | |
7874 | while ((sz & 3) != 0); | |
7875 | ||
7876 | /* Follow the standard note section layout: | |
7877 | First write the length of the name string. */ | |
7878 | p = frag_more (4); | |
7879 | md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); | |
7880 | ||
7881 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
7882 | p = frag_more (4); | |
7883 | md_number_to_chars (p, (valueT) sz, 4); | |
7884 | ||
7885 | /* Write the note type. */ | |
7886 | p = frag_more (4); | |
7887 | md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); | |
7888 | ||
7889 | /* Write the name field. */ | |
7890 | p = frag_more (XTINFO_NAMESZ); | |
7891 | memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); | |
7892 | ||
7893 | /* Finally, write the descriptor. */ | |
7894 | p = frag_more (sz); | |
7895 | memcpy (p, data, sz); | |
7896 | ||
7897 | free (data); | |
7898 | } | |
7899 | ||
e0001a05 NC |
7900 | \f |
7901 | /* Alignment Functions. */ | |
7902 | ||
d77b99c9 BW |
7903 | static int |
7904 | get_text_align_power (unsigned target_size) | |
e0001a05 | 7905 | { |
03aaa593 BW |
7906 | if (target_size <= 4) |
7907 | return 2; | |
7908 | assert (target_size == 8); | |
7909 | return 3; | |
e0001a05 NC |
7910 | } |
7911 | ||
7912 | ||
d77b99c9 | 7913 | static int |
7fa3d080 BW |
7914 | get_text_align_max_fill_size (int align_pow, |
7915 | bfd_boolean use_nops, | |
7916 | bfd_boolean use_no_density) | |
e0001a05 NC |
7917 | { |
7918 | if (!use_nops) | |
7919 | return (1 << align_pow); | |
7920 | if (use_no_density) | |
7921 | return 3 * (1 << align_pow); | |
7922 | ||
7923 | return 1 + (1 << align_pow); | |
7924 | } | |
7925 | ||
7926 | ||
d77b99c9 BW |
7927 | /* Calculate the minimum bytes of fill needed at "address" to align a |
7928 | target instruction of size "target_size" so that it does not cross a | |
7929 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
7930 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
7931 | be filled by NOP instructions. */ | |
e0001a05 | 7932 | |
d77b99c9 | 7933 | static int |
7fa3d080 BW |
7934 | get_text_align_fill_size (addressT address, |
7935 | int align_pow, | |
7936 | int target_size, | |
7937 | bfd_boolean use_nops, | |
7938 | bfd_boolean use_no_density) | |
e0001a05 | 7939 | { |
d77b99c9 BW |
7940 | addressT alignment, fill, fill_limit, fill_step; |
7941 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 7942 | |
d77b99c9 BW |
7943 | alignment = (1 << align_pow); |
7944 | assert (target_size > 0 && alignment >= (addressT) target_size); | |
c138bc38 | 7945 | |
e0001a05 NC |
7946 | if (!use_nops) |
7947 | { | |
d77b99c9 BW |
7948 | fill_limit = alignment; |
7949 | fill_step = 1; | |
e0001a05 | 7950 | } |
d77b99c9 | 7951 | else if (!use_no_density) |
e0001a05 | 7952 | { |
d77b99c9 BW |
7953 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
7954 | fill_limit = alignment * 2; | |
7955 | fill_step = 1; | |
7956 | skip_one = TRUE; | |
e0001a05 NC |
7957 | } |
7958 | else | |
7959 | { | |
d77b99c9 BW |
7960 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
7961 | fill_limit = alignment * 3; | |
7962 | fill_step = 3; | |
7963 | } | |
e0001a05 | 7964 | |
d77b99c9 BW |
7965 | /* Try all fill sizes until finding one that works. */ |
7966 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
7967 | { | |
7968 | if (skip_one && fill == 1) | |
7969 | continue; | |
7970 | if ((address + fill) >> align_pow | |
7971 | == (address + fill + target_size - 1) >> align_pow) | |
7972 | return fill; | |
e0001a05 NC |
7973 | } |
7974 | assert (0); | |
7975 | return 0; | |
7976 | } | |
7977 | ||
7978 | ||
664df4e4 BW |
7979 | static int |
7980 | branch_align_power (segT sec) | |
7981 | { | |
7982 | /* If the Xtensa processor has a fetch width of 8 bytes, and the section | |
7983 | is aligned to at least an 8-byte boundary, then a branch target need | |
7984 | only fit within an 8-byte aligned block of memory to avoid a stall. | |
7985 | Otherwise, try to fit branch targets within 4-byte aligned blocks | |
7986 | (which may be insufficient, e.g., if the section has no alignment, but | |
7987 | it's good enough). */ | |
7988 | if (xtensa_fetch_width == 8) | |
7989 | { | |
7990 | if (get_recorded_alignment (sec) >= 3) | |
7991 | return 3; | |
7992 | } | |
7993 | else | |
7994 | assert (xtensa_fetch_width == 4); | |
7995 | ||
7996 | return 2; | |
7997 | } | |
7998 | ||
7999 | ||
e0001a05 NC |
8000 | /* This will assert if it is not possible. */ |
8001 | ||
d77b99c9 BW |
8002 | static int |
8003 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 8004 | { |
d77b99c9 BW |
8005 | int count = 0; |
8006 | ||
e0001a05 NC |
8007 | if (use_no_density) |
8008 | { | |
8009 | assert (fill_size % 3 == 0); | |
8010 | return (fill_size / 3); | |
8011 | } | |
8012 | ||
8013 | assert (fill_size != 1); /* Bad argument. */ | |
8014 | ||
8015 | while (fill_size > 1) | |
8016 | { | |
d77b99c9 | 8017 | int insn_size = 3; |
e0001a05 NC |
8018 | if (fill_size == 2 || fill_size == 4) |
8019 | insn_size = 2; | |
8020 | fill_size -= insn_size; | |
8021 | count++; | |
8022 | } | |
8023 | assert (fill_size != 1); /* Bad algorithm. */ | |
8024 | return count; | |
8025 | } | |
8026 | ||
8027 | ||
d77b99c9 BW |
8028 | static int |
8029 | get_text_align_nth_nop_size (offsetT fill_size, | |
8030 | int n, | |
7fa3d080 | 8031 | bfd_boolean use_no_density) |
e0001a05 | 8032 | { |
d77b99c9 | 8033 | int count = 0; |
e0001a05 NC |
8034 | |
8035 | if (use_no_density) | |
8036 | return 3; | |
8037 | ||
d77b99c9 BW |
8038 | assert (fill_size != 1); /* Bad argument. */ |
8039 | ||
e0001a05 NC |
8040 | while (fill_size > 1) |
8041 | { | |
d77b99c9 | 8042 | int insn_size = 3; |
e0001a05 NC |
8043 | if (fill_size == 2 || fill_size == 4) |
8044 | insn_size = 2; | |
8045 | fill_size -= insn_size; | |
8046 | count++; | |
8047 | if (n + 1 == count) | |
8048 | return insn_size; | |
8049 | } | |
8050 | assert (0); | |
8051 | return 0; | |
8052 | } | |
8053 | ||
8054 | ||
8055 | /* For the given fragment, find the appropriate address | |
8056 | for it to begin at if we are using NOPs to align it. */ | |
8057 | ||
8058 | static addressT | |
7fa3d080 | 8059 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 8060 | { |
43cd72b9 BW |
8061 | /* The rule is: get next fragment's FIRST instruction. Find |
8062 | the smallest number of bytes that need to be added to | |
8063 | ensure that the next fragment's FIRST instruction will fit | |
8064 | in a single word. | |
c138bc38 | 8065 | |
43cd72b9 BW |
8066 | E.G., 2 bytes : 0, 1, 2 mod 4 |
8067 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 8068 | |
43cd72b9 BW |
8069 | If the FIRST instruction MIGHT be relaxed, |
8070 | assume that it will become a 3-byte instruction. | |
c138bc38 | 8071 | |
43cd72b9 BW |
8072 | Note again here that LOOP instructions are not bundleable, |
8073 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 8074 | |
d77b99c9 | 8075 | int fill_size = 0; |
43cd72b9 BW |
8076 | int first_insn_size; |
8077 | int loop_insn_size; | |
8078 | addressT pre_opcode_bytes; | |
d77b99c9 | 8079 | int align_power; |
43cd72b9 BW |
8080 | fragS *first_insn; |
8081 | xtensa_opcode opcode; | |
8082 | bfd_boolean is_loop; | |
e0001a05 | 8083 | |
43cd72b9 BW |
8084 | assert (fragP->fr_type == rs_machine_dependent); |
8085 | assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 8086 | |
43cd72b9 BW |
8087 | /* Find the loop frag. */ |
8088 | first_insn = next_non_empty_frag (fragP); | |
8089 | /* Now find the first insn frag. */ | |
8090 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 8091 | |
43cd72b9 BW |
8092 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
8093 | assert (is_loop); | |
8094 | loop_insn_size = xg_get_single_size (opcode); | |
e0001a05 | 8095 | |
43cd72b9 BW |
8096 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
8097 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 8098 | |
43cd72b9 BW |
8099 | /* For loops, the alignment depends on the size of the |
8100 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 8101 | |
43cd72b9 | 8102 | if (first_insn == NULL) |
03aaa593 BW |
8103 | first_insn_size = xtensa_fetch_width; |
8104 | else | |
8105 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 8106 | |
43cd72b9 | 8107 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
8108 | align_power = get_text_align_power (first_insn_size); |
8109 | record_alignment (now_seg, align_power); | |
c138bc38 | 8110 | |
43cd72b9 | 8111 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
8112 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
8113 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
8114 | |
8115 | return address + fill_size; | |
8116 | } | |
8117 | ||
8118 | ||
43cd72b9 BW |
8119 | /* 3 mechanisms for relaxing an alignment: |
8120 | ||
8121 | Align to a power of 2. | |
8122 | Align so the next fragment's instruction does not cross a word boundary. | |
8123 | Align the current instruction so that if the next instruction | |
8124 | were 3 bytes, it would not cross a word boundary. | |
8125 | ||
e0001a05 NC |
8126 | We can align with: |
8127 | ||
43cd72b9 BW |
8128 | zeros - This is easy; always insert zeros. |
8129 | nops - 3-byte and 2-byte instructions | |
8130 | 2 - 2-byte nop | |
8131 | 3 - 3-byte nop | |
8132 | 4 - 2 2-byte nops | |
8133 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
8134 | widening - widen previous instructions. */ |
8135 | ||
d77b99c9 BW |
8136 | static offsetT |
8137 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 8138 | { |
43cd72b9 BW |
8139 | addressT target_address, loop_insn_offset; |
8140 | int target_size; | |
8141 | xtensa_opcode loop_opcode; | |
8142 | bfd_boolean is_loop; | |
d77b99c9 BW |
8143 | int align_power; |
8144 | offsetT opt_diff; | |
5f9084e9 | 8145 | offsetT branch_align; |
e0001a05 | 8146 | |
43cd72b9 BW |
8147 | assert (fragP->fr_type == rs_machine_dependent); |
8148 | switch (fragP->fr_subtype) | |
e0001a05 | 8149 | { |
43cd72b9 BW |
8150 | case RELAX_DESIRE_ALIGN: |
8151 | target_size = next_frag_format_size (fragP); | |
8152 | if (target_size == XTENSA_UNDEFINED) | |
8153 | target_size = 3; | |
664df4e4 BW |
8154 | align_power = branch_align_power (now_seg); |
8155 | branch_align = 1 << align_power; | |
0e5cd789 BW |
8156 | /* Don't count on the section alignment being as large as the target. */ |
8157 | if (target_size > branch_align) | |
8158 | target_size = branch_align; | |
d77b99c9 | 8159 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
8160 | target_size, FALSE, FALSE); |
8161 | ||
664df4e4 BW |
8162 | *max_diff = (opt_diff + branch_align |
8163 | - (target_size + ((address + opt_diff) % branch_align))); | |
43cd72b9 BW |
8164 | assert (*max_diff >= opt_diff); |
8165 | return opt_diff; | |
e0001a05 | 8166 | |
43cd72b9 | 8167 | case RELAX_ALIGN_NEXT_OPCODE: |
03aaa593 | 8168 | target_size = get_loop_align_size (next_frag_format_size (fragP)); |
43cd72b9 BW |
8169 | loop_insn_offset = 0; |
8170 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
8171 | assert (is_loop); | |
8172 | ||
8173 | /* If the loop has been expanded then the LOOP instruction | |
8174 | could be at an offset from this fragment. */ | |
8175 | if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0] | |
8176 | != RELAX_IMMED) | |
8177 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); | |
8178 | ||
43cd72b9 BW |
8179 | /* In an ideal world, which is what we are shooting for here, |
8180 | we wouldn't need to use any NOPs immediately prior to the | |
8181 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
8182 | will call get_noop_aligned_address. */ | |
8183 | target_address = | |
8184 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
d77b99c9 BW |
8185 | align_power = get_text_align_power (target_size), |
8186 | opt_diff = get_text_align_fill_size (target_address, align_power, | |
43cd72b9 BW |
8187 | target_size, FALSE, FALSE); |
8188 | ||
8189 | *max_diff = xtensa_fetch_width | |
8190 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
8191 | - target_size + opt_diff; | |
8192 | assert (*max_diff >= opt_diff); | |
8193 | return opt_diff; | |
e0001a05 | 8194 | |
43cd72b9 BW |
8195 | default: |
8196 | break; | |
e0001a05 | 8197 | } |
43cd72b9 BW |
8198 | assert (0); |
8199 | return 0; | |
e0001a05 NC |
8200 | } |
8201 | ||
8202 | \f | |
8203 | /* md_relax_frag Hook and Helper Functions. */ | |
8204 | ||
7fa3d080 BW |
8205 | static long relax_frag_loop_align (fragS *, long); |
8206 | static long relax_frag_for_align (fragS *, long); | |
8207 | static long relax_frag_immed | |
8208 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
8209 | ||
8210 | ||
e0001a05 NC |
8211 | /* Return the number of bytes added to this fragment, given that the |
8212 | input has been stretched already by "stretch". */ | |
8213 | ||
8214 | long | |
7fa3d080 | 8215 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 8216 | { |
43cd72b9 | 8217 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
8218 | int unreported = fragP->tc_frag_data.unreported_expansion; |
8219 | long new_stretch = 0; | |
8220 | char *file_name; | |
d77b99c9 BW |
8221 | unsigned line; |
8222 | int lit_size; | |
43cd72b9 BW |
8223 | static xtensa_insnbuf vbuf = NULL; |
8224 | int slot, num_slots; | |
8225 | xtensa_format fmt; | |
e0001a05 NC |
8226 | |
8227 | as_where (&file_name, &line); | |
8228 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8229 | ||
8230 | fragP->tc_frag_data.unreported_expansion = 0; | |
8231 | ||
8232 | switch (fragP->fr_subtype) | |
8233 | { | |
8234 | case RELAX_ALIGN_NEXT_OPCODE: | |
8235 | /* Always convert. */ | |
43cd72b9 BW |
8236 | if (fragP->tc_frag_data.relax_seen) |
8237 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
8238 | break; |
8239 | ||
8240 | case RELAX_LOOP_END: | |
8241 | /* Do nothing. */ | |
8242 | break; | |
8243 | ||
8244 | case RELAX_LOOP_END_ADD_NOP: | |
8245 | /* Add a NOP and switch to .fill 0. */ | |
8246 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 8247 | frag_wane (fragP); |
e0001a05 NC |
8248 | break; |
8249 | ||
8250 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 8251 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
8252 | it or not. */ |
8253 | break; | |
8254 | ||
8255 | case RELAX_LITERAL: | |
8256 | case RELAX_LITERAL_FINAL: | |
8257 | return 0; | |
8258 | ||
8259 | case RELAX_LITERAL_NR: | |
8260 | lit_size = 4; | |
8261 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
8262 | assert (unreported == lit_size); | |
8263 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); | |
8264 | fragP->fr_var -= lit_size; | |
8265 | fragP->fr_fix += lit_size; | |
8266 | new_stretch = 4; | |
8267 | break; | |
8268 | ||
43cd72b9 BW |
8269 | case RELAX_SLOTS: |
8270 | if (vbuf == NULL) | |
8271 | vbuf = xtensa_insnbuf_alloc (isa); | |
8272 | ||
d77b99c9 BW |
8273 | xtensa_insnbuf_from_chars |
8274 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
8275 | fmt = xtensa_format_decode (isa, vbuf); |
8276 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 8277 | |
43cd72b9 BW |
8278 | for (slot = 0; slot < num_slots; slot++) |
8279 | { | |
8280 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
8281 | { | |
8282 | case RELAX_NARROW: | |
8283 | if (fragP->tc_frag_data.relax_seen) | |
8284 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8285 | break; | |
8286 | ||
8287 | case RELAX_IMMED: | |
8288 | case RELAX_IMMED_STEP1: | |
8289 | case RELAX_IMMED_STEP2: | |
8290 | /* Place the immediate. */ | |
8291 | new_stretch += relax_frag_immed | |
8292 | (now_seg, fragP, stretch, | |
8293 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8294 | fmt, slot, stretched_p, FALSE); | |
8295 | break; | |
8296 | ||
8297 | default: | |
8298 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
8299 | break; | |
8300 | } | |
8301 | } | |
e0001a05 NC |
8302 | break; |
8303 | ||
8304 | case RELAX_LITERAL_POOL_BEGIN: | |
8305 | case RELAX_LITERAL_POOL_END: | |
43cd72b9 BW |
8306 | case RELAX_MAYBE_UNREACHABLE: |
8307 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
8308 | /* No relaxation required. */ |
8309 | break; | |
8310 | ||
43cd72b9 BW |
8311 | case RELAX_FILL_NOP: |
8312 | case RELAX_UNREACHABLE: | |
8313 | if (fragP->tc_frag_data.relax_seen) | |
8314 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8315 | break; | |
8316 | ||
e0001a05 NC |
8317 | default: |
8318 | as_bad (_("bad relaxation state")); | |
8319 | } | |
8320 | ||
43cd72b9 | 8321 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 8322 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
8323 | { |
8324 | fragP->tc_frag_data.relax_seen = TRUE; | |
8325 | *stretched_p = 1; | |
8326 | } | |
8327 | ||
e0001a05 NC |
8328 | new_logical_line (file_name, line); |
8329 | return new_stretch; | |
8330 | } | |
8331 | ||
8332 | ||
8333 | static long | |
7fa3d080 | 8334 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
8335 | { |
8336 | addressT old_address, old_next_address, old_size; | |
8337 | addressT new_address, new_next_address, new_size; | |
8338 | addressT growth; | |
8339 | ||
43cd72b9 BW |
8340 | /* All the frags with relax_frag_for_alignment prior to this one in the |
8341 | section have been done, hopefully eliminating the need for a NOP here. | |
8342 | But, this will put it in if necessary. */ | |
e0001a05 NC |
8343 | |
8344 | /* Calculate the old address of this fragment and the next fragment. */ | |
8345 | old_address = fragP->fr_address - stretch; | |
8346 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 8347 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
8348 | old_size = old_next_address - old_address; |
8349 | ||
8350 | /* Calculate the new address of this fragment and the next fragment. */ | |
8351 | new_address = fragP->fr_address; | |
8352 | new_next_address = | |
8353 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
8354 | new_size = new_next_address - new_address; | |
8355 | ||
8356 | growth = new_size - old_size; | |
8357 | ||
8358 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 8359 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
8360 | return growth; |
8361 | } | |
8362 | ||
8363 | ||
43cd72b9 | 8364 | /* Add a NOP instruction. */ |
e0001a05 NC |
8365 | |
8366 | static long | |
7fa3d080 | 8367 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 8368 | { |
e0001a05 | 8369 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
8370 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
8371 | assemble_nop (length, nop_buf); | |
e0001a05 | 8372 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 8373 | |
e0001a05 NC |
8374 | if (fragP->fr_var < length) |
8375 | { | |
dd49a749 | 8376 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
8377 | return 0; |
8378 | } | |
8379 | ||
8380 | fragP->fr_fix += length; | |
8381 | fragP->fr_var -= length; | |
e0001a05 NC |
8382 | return length; |
8383 | } | |
8384 | ||
8385 | ||
7fa3d080 BW |
8386 | static long future_alignment_required (fragS *, long); |
8387 | ||
e0001a05 | 8388 | static long |
7fa3d080 | 8389 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 8390 | { |
43cd72b9 BW |
8391 | /* Overview of the relaxation procedure for alignment: |
8392 | We can widen with NOPs or by widening instructions or by filling | |
8393 | bytes after jump instructions. Find the opportune places and widen | |
8394 | them if necessary. */ | |
8395 | ||
8396 | long stretch_me; | |
8397 | long diff; | |
e0001a05 | 8398 | |
43cd72b9 BW |
8399 | assert (fragP->fr_subtype == RELAX_FILL_NOP |
8400 | || fragP->fr_subtype == RELAX_UNREACHABLE | |
8401 | || (fragP->fr_subtype == RELAX_SLOTS | |
8402 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
8403 | ||
8404 | stretch_me = future_alignment_required (fragP, stretch); | |
8405 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
8406 | if (diff == 0) | |
8407 | return 0; | |
e0001a05 | 8408 | |
43cd72b9 | 8409 | if (diff < 0) |
e0001a05 | 8410 | { |
43cd72b9 BW |
8411 | /* We expanded on a previous pass. Can we shrink now? */ |
8412 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
8413 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 8414 | { |
43cd72b9 BW |
8415 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
8416 | return -shrink; | |
e0001a05 NC |
8417 | } |
8418 | return 0; | |
8419 | } | |
8420 | ||
43cd72b9 BW |
8421 | /* Below here, diff > 0. */ |
8422 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 8423 | |
43cd72b9 | 8424 | return diff; |
e0001a05 NC |
8425 | } |
8426 | ||
8427 | ||
43cd72b9 BW |
8428 | /* Return the address of the next frag that should be aligned. |
8429 | ||
8430 | By "address" we mean the address it _would_ be at if there | |
8431 | is no action taken to align it between here and the target frag. | |
8432 | In other words, if no narrows and no fill nops are used between | |
8433 | here and the frag to align, _even_if_ some of the frags we use | |
8434 | to align targets have already expanded on a previous relaxation | |
8435 | pass. | |
8436 | ||
8437 | Also, count each frag that may be used to help align the target. | |
8438 | ||
8439 | Return 0 if there are no frags left in the chain that need to be | |
8440 | aligned. */ | |
8441 | ||
8442 | static addressT | |
7fa3d080 BW |
8443 | find_address_of_next_align_frag (fragS **fragPP, |
8444 | int *wide_nops, | |
8445 | int *narrow_nops, | |
8446 | int *widens, | |
8447 | bfd_boolean *paddable) | |
e0001a05 | 8448 | { |
43cd72b9 BW |
8449 | fragS *fragP = *fragPP; |
8450 | addressT address = fragP->fr_address; | |
8451 | ||
8452 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
8453 | |
8454 | while (fragP) | |
8455 | { | |
8456 | /* Limit this to a small search. */ | |
b5e4a23d | 8457 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
8458 | { |
8459 | *fragPP = fragP; | |
8460 | return 0; | |
8461 | } | |
e0001a05 NC |
8462 | address += fragP->fr_fix; |
8463 | ||
43cd72b9 BW |
8464 | if (fragP->fr_type == rs_fill) |
8465 | address += fragP->fr_offset * fragP->fr_var; | |
8466 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 8467 | { |
e0001a05 NC |
8468 | switch (fragP->fr_subtype) |
8469 | { | |
43cd72b9 BW |
8470 | case RELAX_UNREACHABLE: |
8471 | *paddable = TRUE; | |
8472 | break; | |
8473 | ||
8474 | case RELAX_FILL_NOP: | |
8475 | (*wide_nops)++; | |
8476 | if (!fragP->tc_frag_data.is_no_density) | |
8477 | (*narrow_nops)++; | |
8478 | break; | |
8479 | ||
8480 | case RELAX_SLOTS: | |
8481 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8482 | { | |
8483 | (*widens)++; | |
8484 | break; | |
8485 | } | |
34e41783 | 8486 | address += total_frag_text_expansion (fragP);; |
e0001a05 NC |
8487 | break; |
8488 | ||
8489 | case RELAX_IMMED: | |
43cd72b9 | 8490 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
8491 | break; |
8492 | ||
8493 | case RELAX_ALIGN_NEXT_OPCODE: | |
8494 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
8495 | *fragPP = fragP; |
8496 | return address; | |
8497 | ||
8498 | case RELAX_MAYBE_UNREACHABLE: | |
8499 | case RELAX_MAYBE_DESIRE_ALIGN: | |
8500 | /* Do nothing. */ | |
e0001a05 NC |
8501 | break; |
8502 | ||
8503 | default: | |
43cd72b9 BW |
8504 | /* Just punt if we don't know the type. */ |
8505 | *fragPP = fragP; | |
8506 | return 0; | |
e0001a05 | 8507 | } |
43cd72b9 | 8508 | } |
c138bc38 | 8509 | else |
43cd72b9 BW |
8510 | { |
8511 | /* Just punt if we don't know the type. */ | |
8512 | *fragPP = fragP; | |
8513 | return 0; | |
8514 | } | |
8515 | fragP = fragP->fr_next; | |
8516 | } | |
8517 | ||
8518 | *fragPP = fragP; | |
8519 | return 0; | |
8520 | } | |
8521 | ||
8522 | ||
7fa3d080 BW |
8523 | static long bytes_to_stretch (fragS *, int, int, int, int); |
8524 | ||
43cd72b9 | 8525 | static long |
7fa3d080 | 8526 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
8527 | { |
8528 | fragS *this_frag = fragP; | |
8529 | long address; | |
8530 | int num_widens = 0; | |
8531 | int wide_nops = 0; | |
8532 | int narrow_nops = 0; | |
8533 | bfd_boolean paddable = FALSE; | |
8534 | offsetT local_opt_diff; | |
8535 | offsetT opt_diff; | |
8536 | offsetT max_diff; | |
8537 | int stretch_amount = 0; | |
8538 | int local_stretch_amount; | |
8539 | int global_stretch_amount; | |
8540 | ||
7fa3d080 BW |
8541 | address = find_address_of_next_align_frag |
8542 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 8543 | |
b5e4a23d BW |
8544 | if (!address) |
8545 | { | |
8546 | if (this_frag->tc_frag_data.is_aligning_branch) | |
8547 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
8548 | else | |
8549 | frag_wane (this_frag); | |
8550 | } | |
8551 | else | |
43cd72b9 BW |
8552 | { |
8553 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
8554 | opt_diff = local_opt_diff; | |
8555 | assert (opt_diff >= 0); | |
8556 | assert (max_diff >= opt_diff); | |
c138bc38 | 8557 | if (max_diff == 0) |
43cd72b9 | 8558 | return 0; |
d2a033cd | 8559 | |
43cd72b9 BW |
8560 | if (fragP) |
8561 | fragP = fragP->fr_next; | |
8562 | ||
8563 | while (fragP && opt_diff < max_diff && address) | |
8564 | { | |
8565 | /* We only use these to determine if we can exit early | |
c138bc38 | 8566 | because there will be plenty of ways to align future |
43cd72b9 | 8567 | align frags. */ |
d77b99c9 | 8568 | int glob_widens = 0; |
43cd72b9 BW |
8569 | int dnn = 0; |
8570 | int dw = 0; | |
8571 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
8572 | address = find_address_of_next_align_frag |
8573 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 8574 | /* If there is a padable portion, then skip. */ |
664df4e4 | 8575 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 8576 | address = 0; |
43cd72b9 | 8577 | |
c138bc38 | 8578 | if (address) |
43cd72b9 BW |
8579 | { |
8580 | offsetT next_m_diff; | |
8581 | offsetT next_o_diff; | |
8582 | ||
8583 | /* Downrange frags haven't had stretch added to them yet. */ | |
8584 | address += stretch; | |
8585 | ||
8586 | /* The address also includes any text expansion from this | |
8587 | frag in a previous pass, but we don't want that. */ | |
8588 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
8589 | ||
8590 | /* Assume we are going to move at least opt_diff. In | |
8591 | reality, we might not be able to, but assuming that | |
8592 | we will helps catch cases where moving opt_diff pushes | |
8593 | the next target from aligned to unaligned. */ | |
8594 | address += opt_diff; | |
8595 | ||
8596 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
8597 | ||
8598 | /* Now cleanup for the adjustments to address. */ | |
8599 | next_o_diff += opt_diff; | |
8600 | next_m_diff += opt_diff; | |
8601 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
8602 | opt_diff = next_o_diff; | |
8603 | if (next_m_diff < max_diff) | |
8604 | max_diff = next_m_diff; | |
8605 | fragP = fragP->fr_next; | |
8606 | } | |
8607 | } | |
d2a033cd | 8608 | |
43cd72b9 BW |
8609 | /* If there are enough wideners in between, do it. */ |
8610 | if (paddable) | |
8611 | { | |
8612 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
8613 | { | |
8614 | assert (opt_diff <= UNREACHABLE_MAX_WIDTH); | |
8615 | return opt_diff; | |
8616 | } | |
8617 | return 0; | |
8618 | } | |
c138bc38 | 8619 | local_stretch_amount |
43cd72b9 BW |
8620 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
8621 | num_widens, local_opt_diff); | |
c138bc38 BW |
8622 | global_stretch_amount |
8623 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 8624 | num_widens, opt_diff); |
c138bc38 BW |
8625 | /* If the condition below is true, then the frag couldn't |
8626 | stretch the correct amount for the global case, so we just | |
8627 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
8628 | the correct alignment in the global case. */ |
8629 | if (global_stretch_amount < local_stretch_amount) | |
8630 | stretch_amount = local_stretch_amount; | |
8631 | else | |
8632 | stretch_amount = global_stretch_amount; | |
d2a033cd | 8633 | |
43cd72b9 BW |
8634 | if (this_frag->fr_subtype == RELAX_SLOTS |
8635 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8636 | assert (stretch_amount <= 1); | |
8637 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8638 | { | |
8639 | if (this_frag->tc_frag_data.is_no_density) | |
8640 | assert (stretch_amount == 3 || stretch_amount == 0); | |
8641 | else | |
8642 | assert (stretch_amount <= 3); | |
8643 | } | |
8644 | } | |
8645 | return stretch_amount; | |
8646 | } | |
8647 | ||
8648 | ||
8649 | /* The idea: widen everything you can to get a target or loop aligned, | |
8650 | then start using NOPs. | |
8651 | ||
8652 | When we must have a NOP, here is a table of how we decide | |
8653 | (so you don't have to fight through the control flow below): | |
8654 | ||
8655 | wide_nops = the number of wide NOPs available for aligning | |
8656 | narrow_nops = the number of narrow NOPs available for aligning | |
8657 | (a subset of wide_nops) | |
8658 | widens = the number of narrow instructions that should be widened | |
8659 | ||
8660 | Desired wide narrow | |
8661 | Diff nop nop widens | |
8662 | 1 0 0 1 | |
8663 | 2 0 1 0 | |
8664 | 3a 1 0 0 | |
8665 | b 0 1 1 (case 3a makes this case unnecessary) | |
8666 | 4a 1 0 1 | |
8667 | b 0 2 0 | |
8668 | c 0 1 2 (case 4a makes this case unnecessary) | |
8669 | 5a 1 0 2 | |
8670 | b 1 1 0 | |
8671 | c 0 2 1 (case 5b makes this case unnecessary) | |
8672 | 6a 2 0 0 | |
8673 | b 1 0 3 | |
708587a4 | 8674 | c 0 1 4 (case 6b makes this case unnecessary) |
43cd72b9 BW |
8675 | d 1 1 1 (case 6a makes this case unnecessary) |
8676 | e 0 2 2 (case 6a makes this case unnecessary) | |
8677 | f 0 3 0 (case 6a makes this case unnecessary) | |
8678 | 7a 1 0 4 | |
8679 | b 2 0 1 | |
8680 | c 1 1 2 (case 7b makes this case unnecessary) | |
8681 | d 0 1 5 (case 7a makes this case unnecessary) | |
8682 | e 0 2 3 (case 7b makes this case unnecessary) | |
8683 | f 0 3 1 (case 7b makes this case unnecessary) | |
8684 | g 1 2 1 (case 7b makes this case unnecessary) | |
8685 | */ | |
8686 | ||
8687 | static long | |
7fa3d080 BW |
8688 | bytes_to_stretch (fragS *this_frag, |
8689 | int wide_nops, | |
8690 | int narrow_nops, | |
8691 | int num_widens, | |
8692 | int desired_diff) | |
43cd72b9 BW |
8693 | { |
8694 | int bytes_short = desired_diff - num_widens; | |
8695 | ||
8696 | assert (desired_diff >= 0 && desired_diff < 8); | |
8697 | if (desired_diff == 0) | |
8698 | return 0; | |
c138bc38 | 8699 | |
43cd72b9 | 8700 | assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 8701 | |
43cd72b9 BW |
8702 | /* Always prefer widening to NOP-filling. */ |
8703 | if (bytes_short < 0) | |
8704 | { | |
8705 | /* There are enough RELAX_NARROW frags after this one | |
8706 | to align the target without widening this frag in any way. */ | |
8707 | return 0; | |
8708 | } | |
c138bc38 | 8709 | |
43cd72b9 BW |
8710 | if (bytes_short == 0) |
8711 | { | |
8712 | /* Widen every narrow between here and the align target | |
8713 | and the align target will be properly aligned. */ | |
8714 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8715 | return 0; | |
8716 | else | |
8717 | return 1; | |
8718 | } | |
c138bc38 | 8719 | |
43cd72b9 BW |
8720 | /* From here we will need at least one NOP to get an alignment. |
8721 | However, we may not be able to align at all, in which case, | |
8722 | don't widen. */ | |
8723 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8724 | { | |
8725 | switch (desired_diff) | |
8726 | { | |
8727 | case 1: | |
8728 | return 0; | |
8729 | case 2: | |
8730 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1) | |
8731 | return 2; /* case 2 */ | |
8732 | return 0; | |
c138bc38 | 8733 | case 3: |
43cd72b9 BW |
8734 | if (wide_nops > 1) |
8735 | return 0; | |
8736 | else | |
8737 | return 3; /* case 3a */ | |
8738 | case 4: | |
8739 | if (num_widens >= 1 && wide_nops == 1) | |
8740 | return 3; /* case 4a */ | |
8741 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2) | |
8742 | return 2; /* case 4b */ | |
8743 | return 0; | |
8744 | case 5: | |
8745 | if (num_widens >= 2 && wide_nops == 1) | |
8746 | return 3; /* case 5a */ | |
c138bc38 | 8747 | /* We will need two nops. Are there enough nops |
43cd72b9 BW |
8748 | between here and the align target? */ |
8749 | if (wide_nops < 2 || narrow_nops == 0) | |
8750 | return 0; | |
8751 | /* Are there other nops closer that can serve instead? */ | |
8752 | if (wide_nops > 2 && narrow_nops > 1) | |
8753 | return 0; | |
8754 | /* Take the density one first, because there might not be | |
8755 | another density one available. */ | |
8756 | if (!this_frag->tc_frag_data.is_no_density) | |
8757 | return 2; /* case 5b narrow */ | |
8758 | else | |
8759 | return 3; /* case 5b wide */ | |
8760 | return 0; | |
8761 | case 6: | |
8762 | if (wide_nops == 2) | |
8763 | return 3; /* case 6a */ | |
8764 | else if (num_widens >= 3 && wide_nops == 1) | |
8765 | return 3; /* case 6b */ | |
8766 | return 0; | |
8767 | case 7: | |
8768 | if (wide_nops == 1 && num_widens >= 4) | |
8769 | return 3; /* case 7a */ | |
8770 | else if (wide_nops == 2 && num_widens >= 1) | |
8771 | return 3; /* case 7b */ | |
8772 | return 0; | |
e0001a05 | 8773 | default: |
43cd72b9 | 8774 | assert (0); |
e0001a05 | 8775 | } |
e0001a05 | 8776 | } |
43cd72b9 BW |
8777 | else |
8778 | { | |
c138bc38 | 8779 | /* We will need a NOP no matter what, but should we widen |
43cd72b9 | 8780 | this instruction to help? |
e0001a05 | 8781 | |
03aaa593 | 8782 | This is a RELAX_NARROW frag. */ |
43cd72b9 BW |
8783 | switch (desired_diff) |
8784 | { | |
8785 | case 1: | |
8786 | assert (0); | |
8787 | return 0; | |
8788 | case 2: | |
8789 | case 3: | |
8790 | return 0; | |
8791 | case 4: | |
8792 | if (wide_nops >= 1 && num_widens == 1) | |
8793 | return 1; /* case 4a */ | |
8794 | return 0; | |
8795 | case 5: | |
8796 | if (wide_nops >= 1 && num_widens == 2) | |
8797 | return 1; /* case 5a */ | |
8798 | return 0; | |
8799 | case 6: | |
8800 | if (wide_nops >= 2) | |
8801 | return 0; /* case 6a */ | |
8802 | else if (wide_nops >= 1 && num_widens == 3) | |
8803 | return 1; /* case 6b */ | |
8804 | return 0; | |
8805 | case 7: | |
8806 | if (wide_nops >= 1 && num_widens == 4) | |
8807 | return 1; /* case 7a */ | |
8808 | else if (wide_nops >= 2 && num_widens == 1) | |
8809 | return 1; /* case 7b */ | |
8810 | return 0; | |
8811 | default: | |
8812 | assert (0); | |
8813 | return 0; | |
8814 | } | |
8815 | } | |
8816 | assert (0); | |
8817 | return 0; | |
e0001a05 NC |
8818 | } |
8819 | ||
8820 | ||
8821 | static long | |
7fa3d080 BW |
8822 | relax_frag_immed (segT segP, |
8823 | fragS *fragP, | |
8824 | long stretch, | |
8825 | int min_steps, | |
8826 | xtensa_format fmt, | |
8827 | int slot, | |
8828 | int *stretched_p, | |
8829 | bfd_boolean estimate_only) | |
e0001a05 | 8830 | { |
43cd72b9 | 8831 | TInsn tinsn; |
e0001a05 NC |
8832 | int old_size; |
8833 | bfd_boolean negatable_branch = FALSE; | |
8834 | bfd_boolean branch_jmp_to_next = FALSE; | |
43cd72b9 BW |
8835 | bfd_boolean wide_insn = FALSE; |
8836 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
8837 | IStack istack; |
8838 | offsetT frag_offset; | |
8839 | int num_steps; | |
8840 | fragS *lit_fragP; | |
8841 | int num_text_bytes, num_literal_bytes; | |
43cd72b9 | 8842 | int literal_diff, total_text_diff, this_text_diff, first; |
e0001a05 NC |
8843 | |
8844 | assert (fragP->fr_opcode != NULL); | |
8845 | ||
b5e4a23d BW |
8846 | xg_clear_vinsn (&cur_vinsn); |
8847 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 8848 | if (cur_vinsn.num_slots > 1) |
43cd72b9 BW |
8849 | wide_insn = TRUE; |
8850 | ||
b5e4a23d | 8851 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 8852 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 8853 | |
64b607e6 | 8854 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 8855 | return 0; |
e0001a05 | 8856 | |
b08b5071 | 8857 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 8858 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 8859 | |
43cd72b9 | 8860 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 8861 | |
43cd72b9 | 8862 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
8863 | |
8864 | /* Special case: replace a branch to the next instruction with a NOP. | |
8865 | This is required to work around a hardware bug in T1040.0 and also | |
8866 | serves as an optimization. */ | |
8867 | ||
8868 | if (branch_jmp_to_next | |
8869 | && ((old_size == 2) || (old_size == 3)) | |
8870 | && !next_frag_is_loop_target (fragP)) | |
8871 | return 0; | |
8872 | ||
8873 | /* Here is the fun stuff: Get the immediate field from this | |
8874 | instruction. If it fits, we are done. If not, find the next | |
8875 | instruction sequence that fits. */ | |
8876 | ||
8877 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
8878 | istack_init (&istack); | |
43cd72b9 | 8879 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 NC |
8880 | min_steps, stretch); |
8881 | if (num_steps < min_steps) | |
8882 | { | |
8883 | as_fatal (_("internal error: relaxation failed")); | |
8884 | return 0; | |
8885 | } | |
8886 | ||
8887 | if (num_steps > RELAX_IMMED_MAXSTEPS) | |
8888 | { | |
8889 | as_fatal (_("internal error: relaxation requires too many steps")); | |
8890 | return 0; | |
8891 | } | |
8892 | ||
43cd72b9 | 8893 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
8894 | |
8895 | /* Figure out the number of bytes needed. */ | |
8896 | lit_fragP = 0; | |
e0001a05 | 8897 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
43cd72b9 BW |
8898 | literal_diff = |
8899 | num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
8900 | first = 0; | |
8901 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
8902 | first++; | |
8903 | num_text_bytes = get_num_stack_text_bytes (&istack); | |
8904 | if (wide_insn) | |
8905 | { | |
8906 | num_text_bytes += old_size; | |
8907 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
8908 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
8909 | } | |
8910 | total_text_diff = num_text_bytes - old_size; | |
8911 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
8912 | |
8913 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
43cd72b9 BW |
8914 | assert (num_text_bytes >= 0); |
8915 | assert (literal_diff >= 0); | |
8916 | assert (total_text_diff >= 0); | |
e0001a05 | 8917 | |
43cd72b9 BW |
8918 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
8919 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
8920 | assert (fragP->tc_frag_data.text_expansion[slot] >= 0); | |
8921 | assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
8922 | |
8923 | /* Find the associated expandable literal for this. */ | |
8924 | if (literal_diff != 0) | |
8925 | { | |
43cd72b9 | 8926 | lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
8927 | if (lit_fragP) |
8928 | { | |
8929 | assert (literal_diff == 4); | |
8930 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; | |
8931 | ||
8932 | /* We expect that the literal section state has NOT been | |
8933 | modified yet. */ | |
8934 | assert (lit_fragP->fr_type == rs_machine_dependent | |
8935 | && lit_fragP->fr_subtype == RELAX_LITERAL); | |
8936 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
8937 | ||
8938 | /* We need to mark this section for another iteration | |
8939 | of relaxation. */ | |
8940 | (*stretched_p)++; | |
8941 | } | |
8942 | } | |
8943 | ||
43cd72b9 | 8944 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 8945 | update_next_frag_state (fragP); |
e0001a05 | 8946 | |
43cd72b9 | 8947 | return this_text_diff; |
e0001a05 NC |
8948 | } |
8949 | ||
8950 | \f | |
8951 | /* md_convert_frag Hook and Helper Functions. */ | |
8952 | ||
7fa3d080 BW |
8953 | static void convert_frag_align_next_opcode (fragS *); |
8954 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
8955 | static void convert_frag_fill_nop (fragS *); | |
8956 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
8957 | ||
e0001a05 | 8958 | void |
7fa3d080 | 8959 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 8960 | { |
43cd72b9 BW |
8961 | static xtensa_insnbuf vbuf = NULL; |
8962 | xtensa_isa isa = xtensa_default_isa; | |
8963 | int slot; | |
8964 | int num_slots; | |
8965 | xtensa_format fmt; | |
e0001a05 | 8966 | char *file_name; |
d77b99c9 | 8967 | unsigned line; |
e0001a05 NC |
8968 | |
8969 | as_where (&file_name, &line); | |
8970 | new_logical_line (fragp->fr_file, fragp->fr_line); | |
8971 | ||
8972 | switch (fragp->fr_subtype) | |
8973 | { | |
8974 | case RELAX_ALIGN_NEXT_OPCODE: | |
8975 | /* Always convert. */ | |
8976 | convert_frag_align_next_opcode (fragp); | |
8977 | break; | |
8978 | ||
8979 | case RELAX_DESIRE_ALIGN: | |
8980 | /* Do nothing. If not aligned already, too bad. */ | |
8981 | break; | |
8982 | ||
43cd72b9 BW |
8983 | case RELAX_LITERAL: |
8984 | case RELAX_LITERAL_FINAL: | |
8985 | break; | |
8986 | ||
8987 | case RELAX_SLOTS: | |
8988 | if (vbuf == NULL) | |
8989 | vbuf = xtensa_insnbuf_alloc (isa); | |
8990 | ||
d77b99c9 BW |
8991 | xtensa_insnbuf_from_chars |
8992 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
8993 | fmt = xtensa_format_decode (isa, vbuf); |
8994 | num_slots = xtensa_format_num_slots (isa, fmt); | |
8995 | ||
8996 | for (slot = 0; slot < num_slots; slot++) | |
8997 | { | |
8998 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
8999 | { | |
9000 | case RELAX_NARROW: | |
9001 | convert_frag_narrow (sec, fragp, fmt, slot); | |
9002 | break; | |
9003 | ||
9004 | case RELAX_IMMED: | |
9005 | case RELAX_IMMED_STEP1: | |
9006 | case RELAX_IMMED_STEP2: | |
9007 | /* Place the immediate. */ | |
9008 | convert_frag_immed | |
9009 | (sec, fragp, | |
9010 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
9011 | fmt, slot); | |
9012 | break; | |
9013 | ||
9014 | default: | |
9015 | /* This is OK because some slots could have | |
9016 | relaxations and others have none. */ | |
9017 | break; | |
9018 | } | |
9019 | } | |
9020 | break; | |
9021 | ||
9022 | case RELAX_UNREACHABLE: | |
9023 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
9024 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
9025 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
9026 | frag_wane (fragp); | |
e0001a05 NC |
9027 | break; |
9028 | ||
43cd72b9 BW |
9029 | case RELAX_MAYBE_UNREACHABLE: |
9030 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9031 | frag_wane (fragp); | |
e0001a05 NC |
9032 | break; |
9033 | ||
43cd72b9 BW |
9034 | case RELAX_FILL_NOP: |
9035 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
9036 | break; |
9037 | ||
9038 | case RELAX_LITERAL_NR: | |
9039 | if (use_literal_section) | |
9040 | { | |
9041 | /* This should have been handled during relaxation. When | |
9042 | relaxing a code segment, literals sometimes need to be | |
9043 | added to the corresponding literal segment. If that | |
9044 | literal segment has already been relaxed, then we end up | |
9045 | in this situation. Marking the literal segments as data | |
9046 | would make this happen less often (since GAS always relaxes | |
9047 | code before data), but we could still get into trouble if | |
9048 | there are instructions in a segment that is not marked as | |
9049 | containing code. Until we can implement a better solution, | |
9050 | cheat and adjust the addresses of all the following frags. | |
9051 | This could break subsequent alignments, but the linker's | |
9052 | literal coalescing will do that anyway. */ | |
9053 | ||
9054 | fragS *f; | |
9055 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9056 | assert (fragp->tc_frag_data.unreported_expansion == 4); | |
9057 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); | |
9058 | fragp->fr_var -= 4; | |
9059 | fragp->fr_fix += 4; | |
9060 | for (f = fragp->fr_next; f; f = f->fr_next) | |
9061 | f->fr_address += 4; | |
9062 | } | |
9063 | else | |
9064 | as_bad (_("invalid relaxation fragment result")); | |
9065 | break; | |
9066 | } | |
9067 | ||
9068 | fragp->fr_var = 0; | |
9069 | new_logical_line (file_name, line); | |
9070 | } | |
9071 | ||
9072 | ||
7fa3d080 BW |
9073 | static void |
9074 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
9075 | { |
9076 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
9077 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
9078 | addressT aligned_address; | |
d77b99c9 BW |
9079 | offsetT fill_size; |
9080 | int nop, nop_count; | |
e0001a05 NC |
9081 | |
9082 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
9083 | fragp->fr_fix); | |
9084 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
9085 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
9086 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
9087 | ||
d77b99c9 | 9088 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 9089 | { |
d77b99c9 BW |
9090 | int nop_size; |
9091 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
9092 | |
9093 | assemble_nop (nop_size, nop_buf); | |
9094 | nop_buf += nop_size; | |
9095 | } | |
9096 | ||
9097 | fragp->fr_fix += fill_size; | |
9098 | fragp->fr_var -= fill_size; | |
9099 | } | |
9100 | ||
9101 | ||
9102 | static void | |
7fa3d080 | 9103 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 9104 | { |
43cd72b9 | 9105 | TInsn tinsn, single_target; |
84b08ed9 | 9106 | int size, old_size, diff; |
e0001a05 NC |
9107 | offsetT frag_offset; |
9108 | ||
43cd72b9 BW |
9109 | assert (slot == 0); |
9110 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); | |
9111 | ||
b5e4a23d | 9112 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 BW |
9113 | { |
9114 | assert (fragP->tc_frag_data.text_expansion[0] == 1 | |
9115 | || fragP->tc_frag_data.text_expansion[0] == 0); | |
9116 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
9117 | fmt, slot); | |
9118 | return; | |
9119 | } | |
9120 | ||
9121 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
9122 | { |
9123 | /* No conversion. */ | |
9124 | fragP->fr_var = 0; | |
9125 | return; | |
9126 | } | |
9127 | ||
9128 | assert (fragP->fr_opcode != NULL); | |
9129 | ||
43cd72b9 BW |
9130 | /* Frags in this relaxation state should only contain |
9131 | single instruction bundles. */ | |
9132 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
9133 | |
9134 | /* Just convert it to a wide form.... */ | |
9135 | size = 0; | |
43cd72b9 | 9136 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
9137 | |
9138 | tinsn_init (&single_target); | |
9139 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9140 | ||
84b08ed9 | 9141 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
9142 | { |
9143 | as_bad (_("unable to widen instruction")); | |
9144 | return; | |
9145 | } | |
9146 | ||
9147 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
9148 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
9149 | frag_offset, TRUE); | |
e0001a05 NC |
9150 | |
9151 | diff = size - old_size; | |
9152 | assert (diff >= 0); | |
9153 | assert (diff <= fragP->fr_var); | |
9154 | fragP->fr_var -= diff; | |
9155 | fragP->fr_fix += diff; | |
9156 | ||
9157 | /* clean it up */ | |
9158 | fragP->fr_var = 0; | |
9159 | } | |
9160 | ||
9161 | ||
9162 | static void | |
7fa3d080 | 9163 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
9164 | { |
9165 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
9166 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9167 | assert ((unsigned) size == (fragP->fr_next->fr_address | |
9168 | - fragP->fr_address - fragP->fr_fix)); | |
9169 | if (size == 0) | |
9170 | { | |
9171 | /* No conversion. */ | |
9172 | fragP->fr_var = 0; | |
9173 | return; | |
9174 | } | |
9175 | assemble_nop (size, loc); | |
9176 | fragP->tc_frag_data.is_insn = TRUE; | |
9177 | fragP->fr_var -= size; | |
9178 | fragP->fr_fix += size; | |
9179 | frag_wane (fragP); | |
9180 | } | |
9181 | ||
9182 | ||
7fa3d080 BW |
9183 | static fixS *fix_new_exp_in_seg |
9184 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
9185 | bfd_reloc_code_real_type); | |
9186 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
9187 | ||
43cd72b9 | 9188 | static void |
7fa3d080 BW |
9189 | convert_frag_immed (segT segP, |
9190 | fragS *fragP, | |
9191 | int min_steps, | |
9192 | xtensa_format fmt, | |
9193 | int slot) | |
e0001a05 NC |
9194 | { |
9195 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 9196 | TInsn orig_tinsn; |
e0001a05 | 9197 | bfd_boolean expanded = FALSE; |
e0001a05 | 9198 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 9199 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 BW |
9200 | xtensa_isa isa = xtensa_default_isa; |
9201 | bfd_boolean wide_insn = FALSE; | |
9202 | int bytes; | |
9203 | bfd_boolean is_loop; | |
e0001a05 | 9204 | |
43cd72b9 | 9205 | assert (fr_opcode != NULL); |
e0001a05 | 9206 | |
b5e4a23d | 9207 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 9208 | |
b5e4a23d | 9209 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 9210 | if (cur_vinsn.num_slots > 1) |
43cd72b9 | 9211 | wide_insn = TRUE; |
e0001a05 | 9212 | |
b5e4a23d | 9213 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
9214 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
9215 | ||
9216 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 9217 | |
b08b5071 | 9218 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9219 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
9220 | |
9221 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
9222 | { | |
9223 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
9224 | bytes = xtensa_format_length (isa, fmt); |
9225 | if (bytes >= 4) | |
9226 | { | |
b5e4a23d BW |
9227 | cur_vinsn.slots[slot].opcode = |
9228 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
9229 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
9230 | } |
9231 | else | |
9232 | { | |
9233 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9234 | assert (bytes == 2 || bytes == 3); | |
b5e4a23d | 9235 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
9236 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
9237 | } | |
e7da6241 | 9238 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 9239 | xtensa_insnbuf_to_chars |
b5e4a23d | 9240 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
9241 | fragP->fr_var = 0; |
9242 | } | |
7c834684 | 9243 | else |
e0001a05 | 9244 | { |
43cd72b9 BW |
9245 | /* Here is the fun stuff: Get the immediate field from this |
9246 | instruction. If it fits, we're done. If not, find the next | |
9247 | instruction sequence that fits. */ | |
9248 | ||
e0001a05 NC |
9249 | IStack istack; |
9250 | int i; | |
9251 | symbolS *lit_sym = NULL; | |
9252 | int total_size = 0; | |
43cd72b9 | 9253 | int target_offset = 0; |
e0001a05 NC |
9254 | int old_size; |
9255 | int diff; | |
9256 | symbolS *gen_label = NULL; | |
9257 | offsetT frag_offset; | |
43cd72b9 BW |
9258 | bfd_boolean first = TRUE; |
9259 | bfd_boolean last_is_jump; | |
e0001a05 | 9260 | |
43cd72b9 | 9261 | /* It does not fit. Find something that does and |
e0001a05 | 9262 | convert immediately. */ |
43cd72b9 | 9263 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 9264 | istack_init (&istack); |
43cd72b9 | 9265 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
9266 | segP, fragP, frag_offset, min_steps, 0); |
9267 | ||
43cd72b9 | 9268 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9269 | |
9270 | /* Assemble this right inline. */ | |
9271 | ||
9272 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 9273 | target_offset = 0; |
e0001a05 NC |
9274 | for (i = 0; i < istack.ninsn; i++) |
9275 | { | |
43cd72b9 | 9276 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9277 | fragS *lit_frag; |
9278 | ||
43cd72b9 | 9279 | switch (tinsn->insn_type) |
e0001a05 NC |
9280 | { |
9281 | case ITYPE_LITERAL: | |
9282 | if (lit_sym != NULL) | |
9283 | as_bad (_("multiple literals in expansion")); | |
9284 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 9285 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9286 | if (lit_frag == NULL) |
9287 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 9288 | if (tinsn->ntok != 1) |
e0001a05 NC |
9289 | as_bad (_("number of literal tokens != 1")); |
9290 | ||
9291 | /* Set the literal symbol and add a fixup. */ | |
9292 | lit_sym = lit_frag->fr_symbol; | |
9293 | break; | |
9294 | ||
9295 | case ITYPE_LABEL: | |
43cd72b9 BW |
9296 | if (align_targets && !is_loop) |
9297 | { | |
9298 | fragS *unreach = fragP->fr_next; | |
9299 | while (!(unreach->fr_type == rs_machine_dependent | |
9300 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9301 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
9302 | { | |
9303 | unreach = unreach->fr_next; | |
9304 | } | |
9305 | ||
9306 | assert (unreach->fr_type == rs_machine_dependent | |
9307 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9308 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
9309 | ||
9310 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
9311 | } | |
e0001a05 NC |
9312 | assert (gen_label == NULL); |
9313 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, | |
43cd72b9 BW |
9314 | fr_opcode - fragP->fr_literal |
9315 | + target_offset, fragP); | |
e0001a05 NC |
9316 | break; |
9317 | ||
9318 | case ITYPE_INSN: | |
43cd72b9 BW |
9319 | if (first && wide_insn) |
9320 | { | |
9321 | target_offset += xtensa_format_length (isa, fmt); | |
9322 | first = FALSE; | |
9323 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9324 | target_offset += xg_get_single_size (tinsn->opcode); | |
9325 | } | |
9326 | else | |
9327 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
9328 | break; |
9329 | } | |
9330 | } | |
9331 | ||
9332 | total_size = 0; | |
43cd72b9 BW |
9333 | first = TRUE; |
9334 | last_is_jump = FALSE; | |
e0001a05 NC |
9335 | for (i = 0; i < istack.ninsn; i++) |
9336 | { | |
43cd72b9 | 9337 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9338 | fragS *lit_frag; |
9339 | int size; | |
9340 | segT target_seg; | |
43cd72b9 | 9341 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 9342 | |
43cd72b9 | 9343 | switch (tinsn->insn_type) |
e0001a05 NC |
9344 | { |
9345 | case ITYPE_LITERAL: | |
43cd72b9 BW |
9346 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
9347 | /* Already checked. */ | |
e0001a05 NC |
9348 | assert (lit_frag != NULL); |
9349 | assert (lit_sym != NULL); | |
43cd72b9 BW |
9350 | assert (tinsn->ntok == 1); |
9351 | /* Add a fixup. */ | |
e0001a05 NC |
9352 | target_seg = S_GET_SEGMENT (lit_sym); |
9353 | assert (target_seg); | |
bbdd25a8 | 9354 | reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op); |
e0001a05 | 9355 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 9356 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
9357 | break; |
9358 | ||
9359 | case ITYPE_LABEL: | |
9360 | break; | |
9361 | ||
9362 | case ITYPE_INSN: | |
43cd72b9 BW |
9363 | xg_resolve_labels (tinsn, gen_label); |
9364 | xg_resolve_literals (tinsn, lit_sym); | |
9365 | if (wide_insn && first) | |
9366 | { | |
9367 | first = FALSE; | |
9368 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9369 | { | |
b5e4a23d | 9370 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
9371 | } |
9372 | else | |
9373 | { | |
b5e4a23d | 9374 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 9375 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 9376 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 9377 | } |
b5e4a23d BW |
9378 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
9379 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 9380 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
9381 | fragP->tc_frag_data.is_insn = TRUE; |
9382 | size = xtensa_format_length (isa, fmt); | |
9383 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9384 | { | |
43cd72b9 | 9385 | xg_emit_insn_to_buf |
b2d179be | 9386 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
9387 | immed_instr - fragP->fr_literal + size, TRUE); |
9388 | size += xg_get_single_size (tinsn->opcode); | |
9389 | } | |
9390 | } | |
9391 | else | |
9392 | { | |
43cd72b9 | 9393 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 9394 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 9395 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 9396 | } |
e0001a05 | 9397 | immed_instr += size; |
43cd72b9 | 9398 | total_size += size; |
e0001a05 NC |
9399 | break; |
9400 | } | |
9401 | } | |
9402 | ||
9403 | diff = total_size - old_size; | |
9404 | assert (diff >= 0); | |
9405 | if (diff != 0) | |
9406 | expanded = TRUE; | |
9407 | assert (diff <= fragP->fr_var); | |
9408 | fragP->fr_var -= diff; | |
9409 | fragP->fr_fix += diff; | |
9410 | } | |
9411 | ||
e0001a05 | 9412 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 9413 | if (is_loop) |
e0001a05 NC |
9414 | { |
9415 | symbolS *sym; | |
43cd72b9 | 9416 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
9417 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9418 | { | |
9419 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9420 | return; | |
9421 | } | |
43cd72b9 | 9422 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
9423 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9424 | { | |
9425 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9426 | return; | |
9427 | } | |
9428 | } | |
9429 | ||
43cd72b9 BW |
9430 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
9431 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 9432 | |
43cd72b9 | 9433 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
9434 | { |
9435 | /* Add an expansion note on the expanded instruction. */ | |
9436 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 9437 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 9438 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
9439 | } |
9440 | } | |
9441 | ||
9442 | ||
9443 | /* Add a new fix expression into the desired segment. We have to | |
9444 | switch to that segment to do this. */ | |
9445 | ||
9446 | static fixS * | |
7fa3d080 BW |
9447 | fix_new_exp_in_seg (segT new_seg, |
9448 | subsegT new_subseg, | |
9449 | fragS *frag, | |
9450 | int where, | |
9451 | int size, | |
9452 | expressionS *exp, | |
9453 | int pcrel, | |
9454 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
9455 | { |
9456 | fixS *new_fix; | |
9457 | segT seg = now_seg; | |
9458 | subsegT subseg = now_subseg; | |
43cd72b9 | 9459 | |
e0001a05 NC |
9460 | assert (new_seg != 0); |
9461 | subseg_set (new_seg, new_subseg); | |
9462 | ||
e0001a05 NC |
9463 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
9464 | subseg_set (seg, subseg); | |
9465 | return new_fix; | |
9466 | } | |
9467 | ||
9468 | ||
43cd72b9 BW |
9469 | /* Relax a loop instruction so that it can span loop >256 bytes. |
9470 | ||
9471 | loop as, .L1 | |
9472 | .L0: | |
9473 | rsr as, LEND | |
9474 | wsr as, LBEG | |
9475 | addi as, as, lo8 (label-.L1) | |
9476 | addmi as, as, mid8 (label-.L1) | |
9477 | wsr as, LEND | |
9478 | isync | |
9479 | rsr as, LCOUNT | |
9480 | addi as, as, 1 | |
9481 | .L1: | |
9482 | <<body>> | |
9483 | label: | |
9484 | */ | |
e0001a05 NC |
9485 | |
9486 | static void | |
7fa3d080 | 9487 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
9488 | { |
9489 | TInsn loop_insn; | |
9490 | TInsn addi_insn; | |
9491 | TInsn addmi_insn; | |
9492 | unsigned long target; | |
9493 | static xtensa_insnbuf insnbuf = NULL; | |
9494 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
9495 | xtensa_isa isa = xtensa_default_isa; | |
9496 | addressT loop_offset; | |
9497 | addressT addi_offset = 9; | |
9498 | addressT addmi_offset = 12; | |
43cd72b9 | 9499 | fragS *next_fragP; |
d77b99c9 | 9500 | int target_count; |
e0001a05 NC |
9501 | |
9502 | if (!insnbuf) | |
9503 | insnbuf = xtensa_insnbuf_alloc (isa); | |
9504 | ||
9505 | /* Get the loop offset. */ | |
43cd72b9 | 9506 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 9507 | |
43cd72b9 BW |
9508 | /* Validate that there really is a LOOP at the loop_offset. Because |
9509 | loops are not bundleable, we can assume that the instruction will be | |
9510 | in slot 0. */ | |
9511 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
9512 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
9513 | ||
9514 | assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); | |
e0001a05 NC |
9515 | addi_offset += loop_offset; |
9516 | addmi_offset += loop_offset; | |
9517 | ||
43cd72b9 | 9518 | assert (tinsn->ntok == 2); |
b08b5071 BW |
9519 | if (tinsn->tok[1].X_op == O_constant) |
9520 | target = tinsn->tok[1].X_add_number; | |
9521 | else if (tinsn->tok[1].X_op == O_symbol) | |
9522 | { | |
9523 | /* Find the fragment. */ | |
9524 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9525 | assert (S_GET_SEGMENT (sym) == segP | |
9526 | || S_GET_SEGMENT (sym) == absolute_section); | |
9527 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
9528 | } | |
9529 | else | |
9530 | { | |
9531 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
9532 | target = 0; | |
9533 | } | |
e0001a05 NC |
9534 | |
9535 | know (symbolP); | |
9536 | know (symbolP->sy_frag); | |
9537 | know (!(S_GET_SEGMENT (symbolP) == absolute_section) | |
9538 | || symbol_get_frag (symbolP) == &zero_address_frag); | |
9539 | ||
9540 | loop_length = target - (fragP->fr_address + fragP->fr_fix); | |
9541 | loop_length_hi = loop_length & ~0x0ff; | |
9542 | loop_length_lo = loop_length & 0x0ff; | |
9543 | if (loop_length_lo >= 128) | |
9544 | { | |
9545 | loop_length_lo -= 256; | |
9546 | loop_length_hi += 256; | |
9547 | } | |
9548 | ||
43cd72b9 | 9549 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
9550 | 32512. If the loop is larger than that, then we just fail. */ |
9551 | if (loop_length_hi > 32512) | |
9552 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9553 | _("loop too long for LOOP instruction")); | |
9554 | ||
43cd72b9 | 9555 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
e0001a05 NC |
9556 | assert (addi_insn.opcode == xtensa_addi_opcode); |
9557 | ||
43cd72b9 | 9558 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
e0001a05 NC |
9559 | assert (addmi_insn.opcode == xtensa_addmi_opcode); |
9560 | ||
9561 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
9562 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 9563 | |
e0001a05 | 9564 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
9565 | xtensa_insnbuf_to_chars |
9566 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
9567 | |
9568 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
9569 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
9570 | xtensa_insnbuf_to_chars |
9571 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
9572 | |
9573 | /* Walk through all of the frags from here to the loop end | |
9574 | and mark them as no_transform to keep them from being modified | |
9575 | by the linker. If we ever have a relocation for the | |
9576 | addi/addmi of the difference of two symbols we can remove this. */ | |
9577 | ||
9578 | target_count = 0; | |
9579 | for (next_fragP = fragP; next_fragP != NULL; | |
9580 | next_fragP = next_fragP->fr_next) | |
9581 | { | |
b08b5071 | 9582 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
9583 | if (next_fragP->tc_frag_data.is_loop_target) |
9584 | target_count++; | |
9585 | if (target_count == 2) | |
9586 | break; | |
9587 | } | |
e0001a05 NC |
9588 | } |
9589 | ||
b08b5071 BW |
9590 | \f |
9591 | /* A map that keeps information on a per-subsegment basis. This is | |
9592 | maintained during initial assembly, but is invalid once the | |
9593 | subsegments are smashed together. I.E., it cannot be used during | |
9594 | the relaxation. */ | |
e0001a05 | 9595 | |
b08b5071 | 9596 | typedef struct subseg_map_struct |
e0001a05 | 9597 | { |
b08b5071 BW |
9598 | /* the key */ |
9599 | segT seg; | |
9600 | subsegT subseg; | |
e0001a05 | 9601 | |
b08b5071 BW |
9602 | /* the data */ |
9603 | unsigned flags; | |
9604 | float total_freq; /* fall-through + branch target frequency */ | |
9605 | float target_freq; /* branch target frequency alone */ | |
9606 | ||
9607 | struct subseg_map_struct *next; | |
9608 | } subseg_map; | |
e0001a05 | 9609 | |
e0001a05 | 9610 | |
e0001a05 NC |
9611 | static subseg_map *sseg_map = NULL; |
9612 | ||
43cd72b9 | 9613 | static subseg_map * |
7fa3d080 | 9614 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
9615 | { |
9616 | subseg_map *subseg_e; | |
9617 | ||
9618 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 9619 | { |
43cd72b9 | 9620 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 9621 | break; |
e0001a05 | 9622 | } |
b08b5071 BW |
9623 | return subseg_e; |
9624 | } | |
9625 | ||
9626 | ||
9627 | static subseg_map * | |
9628 | add_subseg_info (segT seg, subsegT subseg) | |
9629 | { | |
9630 | subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); | |
43cd72b9 BW |
9631 | memset (subseg_e, 0, sizeof (subseg_map)); |
9632 | subseg_e->seg = seg; | |
9633 | subseg_e->subseg = subseg; | |
9634 | subseg_e->flags = 0; | |
9635 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
9636 | subseg_e->target_freq = 1.0; |
9637 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
9638 | subseg_e->next = sseg_map; |
9639 | sseg_map = subseg_e; | |
43cd72b9 BW |
9640 | return subseg_e; |
9641 | } | |
e0001a05 | 9642 | |
7fa3d080 BW |
9643 | |
9644 | static unsigned | |
9645 | get_last_insn_flags (segT seg, subsegT subseg) | |
9646 | { | |
9647 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9648 | if (subseg_e) |
9649 | return subseg_e->flags; | |
9650 | return 0; | |
7fa3d080 BW |
9651 | } |
9652 | ||
9653 | ||
43cd72b9 | 9654 | static void |
7fa3d080 BW |
9655 | set_last_insn_flags (segT seg, |
9656 | subsegT subseg, | |
9657 | unsigned fl, | |
9658 | bfd_boolean val) | |
43cd72b9 BW |
9659 | { |
9660 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9661 | if (! subseg_e) |
9662 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
9663 | if (val) |
9664 | subseg_e->flags |= fl; | |
9665 | else | |
9666 | subseg_e->flags &= ~fl; | |
9667 | } | |
9668 | ||
b08b5071 BW |
9669 | |
9670 | static float | |
9671 | get_subseg_total_freq (segT seg, subsegT subseg) | |
9672 | { | |
9673 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9674 | if (subseg_e) | |
9675 | return subseg_e->total_freq; | |
9676 | return 1.0; | |
9677 | } | |
9678 | ||
9679 | ||
9680 | static float | |
9681 | get_subseg_target_freq (segT seg, subsegT subseg) | |
9682 | { | |
9683 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9684 | if (subseg_e) | |
9685 | return subseg_e->target_freq; | |
9686 | return 1.0; | |
9687 | } | |
9688 | ||
9689 | ||
9690 | static void | |
9691 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
9692 | { | |
9693 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9694 | if (! subseg_e) | |
9695 | subseg_e = add_subseg_info (seg, subseg); | |
9696 | subseg_e->total_freq = total_f; | |
9697 | subseg_e->target_freq = target_f; | |
9698 | } | |
9699 | ||
e0001a05 NC |
9700 | \f |
9701 | /* Segment Lists and emit_state Stuff. */ | |
9702 | ||
e0001a05 | 9703 | static void |
7fa3d080 | 9704 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
9705 | { |
9706 | head = head->next; | |
9707 | while (head) | |
9708 | { | |
9709 | segT literal_section = head->seg; | |
9710 | ||
9711 | /* Move the literal section to the front of the section list. */ | |
9712 | assert (literal_section); | |
69852798 AM |
9713 | if (literal_section != stdoutput->sections) |
9714 | { | |
9715 | bfd_section_list_remove (stdoutput, literal_section); | |
9716 | bfd_section_list_prepend (stdoutput, literal_section); | |
9717 | } | |
e0001a05 NC |
9718 | head = head->next; |
9719 | } | |
9720 | } | |
9721 | ||
9722 | ||
7fa3d080 BW |
9723 | static void mark_literal_frags (seg_list *); |
9724 | ||
9725 | static void | |
9726 | xtensa_move_literals (void) | |
e0001a05 NC |
9727 | { |
9728 | seg_list *segment; | |
9729 | frchainS *frchain_from, *frchain_to; | |
9730 | fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after; | |
9731 | fragS **frag_splice; | |
9732 | emit_state state; | |
9733 | segT dest_seg; | |
9734 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 9735 | sym_list *lit; |
e0001a05 | 9736 | |
a7877748 | 9737 | mark_literal_frags (literal_head->next); |
e0001a05 NC |
9738 | |
9739 | if (use_literal_section) | |
9740 | return; | |
9741 | ||
74869ac7 | 9742 | for (segment = literal_head->next; segment; segment = segment->next) |
e0001a05 | 9743 | { |
74869ac7 BW |
9744 | /* Keep the literals for .init and .fini in separate sections. */ |
9745 | if (!strcmp (segment_name (segment->seg), INIT_SECTION_NAME) | |
9746 | || !strcmp (segment_name (segment->seg), FINI_SECTION_NAME)) | |
9747 | continue; | |
9748 | ||
e0001a05 NC |
9749 | frchain_from = seg_info (segment->seg)->frchainP; |
9750 | search_frag = frchain_from->frch_root; | |
9751 | literal_pool = NULL; | |
9752 | frchain_to = NULL; | |
9753 | frag_splice = &(frchain_from->frch_root); | |
9754 | ||
9755 | while (!search_frag->tc_frag_data.literal_frag) | |
9756 | { | |
9757 | assert (search_frag->fr_fix == 0 | |
9758 | || search_frag->fr_type == rs_align); | |
9759 | search_frag = search_frag->fr_next; | |
9760 | } | |
9761 | ||
9762 | assert (search_frag->tc_frag_data.literal_frag->fr_subtype | |
9763 | == RELAX_LITERAL_POOL_BEGIN); | |
9764 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
9765 | ||
9766 | /* Make sure that all the frags in this series are closed, and | |
9767 | that there is at least one left over of zero-size. This | |
9768 | prevents us from making a segment with an frchain without any | |
9769 | frags in it. */ | |
9770 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9771 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
9772 | last_frag = frag_now; |
9773 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9774 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 9775 | |
43cd72b9 | 9776 | while (search_frag != frag_now) |
e0001a05 NC |
9777 | { |
9778 | next_frag = search_frag->fr_next; | |
9779 | ||
43cd72b9 | 9780 | /* First, move the frag out of the literal section and |
e0001a05 NC |
9781 | to the appropriate place. */ |
9782 | if (search_frag->tc_frag_data.literal_frag) | |
9783 | { | |
9784 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9785 | assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); | |
dd49a749 BW |
9786 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9787 | assert (frchain_to); | |
e0001a05 NC |
9788 | } |
9789 | insert_after = literal_pool; | |
43cd72b9 | 9790 | |
e0001a05 NC |
9791 | while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END) |
9792 | insert_after = insert_after->fr_next; | |
9793 | ||
dd49a749 | 9794 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
43cd72b9 | 9795 | |
e0001a05 NC |
9796 | *frag_splice = next_frag; |
9797 | search_frag->fr_next = insert_after->fr_next; | |
9798 | insert_after->fr_next = search_frag; | |
9799 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
9800 | ||
9801 | /* Now move any fixups associated with this frag to the | |
9802 | right section. */ | |
9803 | fix = frchain_from->fix_root; | |
9804 | fix_splice = &(frchain_from->fix_root); | |
9805 | while (fix) | |
9806 | { | |
9807 | next_fix = fix->fx_next; | |
9808 | if (fix->fx_frag == search_frag) | |
9809 | { | |
9810 | *fix_splice = next_fix; | |
9811 | fix->fx_next = frchain_to->fix_root; | |
9812 | frchain_to->fix_root = fix; | |
9813 | if (frchain_to->fix_tail == NULL) | |
9814 | frchain_to->fix_tail = fix; | |
9815 | } | |
9816 | else | |
9817 | fix_splice = &(fix->fx_next); | |
9818 | fix = next_fix; | |
9819 | } | |
9820 | search_frag = next_frag; | |
9821 | } | |
9822 | ||
9823 | if (frchain_from->fix_root != NULL) | |
9824 | { | |
9825 | frchain_from = seg_info (segment->seg)->frchainP; | |
9826 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
9827 | ||
9828 | assert (frchain_from->fix_root == NULL); | |
9829 | } | |
9830 | frchain_from->fix_tail = NULL; | |
9831 | xtensa_restore_emit_state (&state); | |
e0001a05 NC |
9832 | } |
9833 | ||
82e7541d BW |
9834 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
9835 | for (lit = literal_syms; lit; lit = lit->next) | |
9836 | { | |
9837 | symbolS *lit_sym = lit->sym; | |
9838 | segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; | |
43cd72b9 BW |
9839 | if (dest_seg) |
9840 | S_SET_SEGMENT (lit_sym, dest_seg); | |
82e7541d | 9841 | } |
e0001a05 NC |
9842 | } |
9843 | ||
9844 | ||
a7877748 BW |
9845 | /* Walk over all the frags for segments in a list and mark them as |
9846 | containing literals. As clunky as this is, we can't rely on frag_var | |
9847 | and frag_variant to get called in all situations. */ | |
9848 | ||
9849 | static void | |
7fa3d080 | 9850 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
9851 | { |
9852 | frchainS *frchain_from; | |
9853 | fragS *search_frag; | |
9854 | ||
9855 | while (segment) | |
9856 | { | |
9857 | frchain_from = seg_info (segment->seg)->frchainP; | |
9858 | search_frag = frchain_from->frch_root; | |
c138bc38 | 9859 | while (search_frag) |
a7877748 BW |
9860 | { |
9861 | search_frag->tc_frag_data.is_literal = TRUE; | |
9862 | search_frag = search_frag->fr_next; | |
9863 | } | |
9864 | segment = segment->next; | |
9865 | } | |
9866 | } | |
9867 | ||
9868 | ||
e0001a05 | 9869 | static void |
7fa3d080 | 9870 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
9871 | { |
9872 | /* Move all of the sections in the section list to come | |
9873 | after "after" in the gnu segment list. */ | |
9874 | ||
9875 | head = head->next; | |
9876 | while (head) | |
9877 | { | |
9878 | segT literal_section = head->seg; | |
9879 | ||
9880 | /* Move the literal section after "after". */ | |
9881 | assert (literal_section); | |
9882 | if (literal_section != after) | |
9883 | { | |
69852798 AM |
9884 | bfd_section_list_remove (stdoutput, literal_section); |
9885 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
9886 | } |
9887 | ||
9888 | head = head->next; | |
9889 | } | |
9890 | } | |
9891 | ||
9892 | ||
9893 | /* Push all the literal segments to the end of the gnu list. */ | |
9894 | ||
7fa3d080 BW |
9895 | static void |
9896 | xtensa_reorder_segments (void) | |
e0001a05 NC |
9897 | { |
9898 | segT sec; | |
b08b5071 | 9899 | segT last_sec = 0; |
e0001a05 NC |
9900 | int old_count = 0; |
9901 | int new_count = 0; | |
9902 | ||
9903 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
9904 | { |
9905 | last_sec = sec; | |
9906 | old_count++; | |
9907 | } | |
e0001a05 NC |
9908 | |
9909 | /* Now that we have the last section, push all the literal | |
9910 | sections to the end. */ | |
e0001a05 | 9911 | xtensa_reorder_seg_list (literal_head, last_sec); |
e0001a05 NC |
9912 | |
9913 | /* Now perform the final error check. */ | |
9914 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
9915 | new_count++; | |
9916 | assert (new_count == old_count); | |
9917 | } | |
9918 | ||
9919 | ||
e0001a05 NC |
9920 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
9921 | correct location. Return a emit_state which can be passed to | |
9922 | xtensa_restore_emit_state to return to current fragment. */ | |
9923 | ||
7fa3d080 BW |
9924 | static void |
9925 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
9926 | { |
9927 | if (directive_state[directive_absolute_literals]) | |
9928 | { | |
74869ac7 BW |
9929 | segT lit4_seg = cache_literal_section (TRUE); |
9930 | xtensa_switch_section_emit_state (result, lit4_seg, 0); | |
43cd72b9 BW |
9931 | } |
9932 | else | |
9933 | xtensa_switch_to_non_abs_literal_fragment (result); | |
9934 | ||
9935 | /* Do a 4-byte align here. */ | |
9936 | frag_align (2, 0, 0); | |
9937 | record_alignment (now_seg, 2); | |
9938 | } | |
9939 | ||
9940 | ||
7fa3d080 BW |
9941 | static void |
9942 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 | 9943 | { |
e0001a05 NC |
9944 | static bfd_boolean recursive = FALSE; |
9945 | fragS *pool_location = get_literal_pool_location (now_seg); | |
74869ac7 | 9946 | segT lit_seg; |
c138bc38 | 9947 | bfd_boolean is_init = |
e0001a05 | 9948 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); |
c138bc38 | 9949 | bfd_boolean is_fini = |
e0001a05 | 9950 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); |
e0001a05 | 9951 | |
43cd72b9 BW |
9952 | if (pool_location == NULL |
9953 | && !use_literal_section | |
e0001a05 NC |
9954 | && !recursive |
9955 | && !is_init && ! is_fini) | |
9956 | { | |
43cd72b9 | 9957 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); |
74869ac7 BW |
9958 | |
9959 | /* When we mark a literal pool location, we want to put a frag in | |
9960 | the literal pool that points to it. But to do that, we want to | |
9961 | switch_to_literal_fragment. But literal sections don't have | |
9962 | literal pools, so their location is always null, so we would | |
9963 | recurse forever. This is kind of hacky, but it works. */ | |
9964 | ||
e0001a05 | 9965 | recursive = TRUE; |
61846f28 | 9966 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
9967 | recursive = FALSE; |
9968 | } | |
9969 | ||
74869ac7 BW |
9970 | lit_seg = cache_literal_section (FALSE); |
9971 | xtensa_switch_section_emit_state (result, lit_seg, 0); | |
e0001a05 | 9972 | |
43cd72b9 BW |
9973 | if (!use_literal_section |
9974 | && !is_init && !is_fini | |
9975 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
9976 | { |
9977 | /* Close whatever frag is there. */ | |
9978 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9979 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
9980 | frag_now->tc_frag_data.literal_frag = pool_location; |
9981 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9982 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 9983 | } |
e0001a05 NC |
9984 | } |
9985 | ||
9986 | ||
9987 | /* Call this function before emitting data into the literal section. | |
9988 | This is a helper function for xtensa_switch_to_literal_fragment. | |
9989 | This is similar to a .section new_now_seg subseg. */ | |
9990 | ||
7fa3d080 BW |
9991 | static void |
9992 | xtensa_switch_section_emit_state (emit_state *state, | |
9993 | segT new_now_seg, | |
9994 | subsegT new_now_subseg) | |
e0001a05 NC |
9995 | { |
9996 | state->name = now_seg->name; | |
9997 | state->now_seg = now_seg; | |
9998 | state->now_subseg = now_subseg; | |
9999 | state->generating_literals = generating_literals; | |
10000 | generating_literals++; | |
2b0210eb | 10001 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
10002 | } |
10003 | ||
10004 | ||
10005 | /* Use to restore the emitting into the normal place. */ | |
10006 | ||
7fa3d080 BW |
10007 | static void |
10008 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
10009 | { |
10010 | generating_literals = state->generating_literals; | |
2b0210eb | 10011 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
10012 | } |
10013 | ||
10014 | ||
74869ac7 | 10015 | /* Predicate function used to look up a section in a particular group. */ |
e0001a05 | 10016 | |
74869ac7 BW |
10017 | static bfd_boolean |
10018 | match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) | |
e0001a05 | 10019 | { |
74869ac7 BW |
10020 | const char *gname = inf; |
10021 | const char *group_name = elf_group_name (sec); | |
10022 | ||
10023 | return (group_name == gname | |
10024 | || (group_name != NULL | |
10025 | && gname != NULL | |
10026 | && strcmp (group_name, gname) == 0)); | |
10027 | } | |
e0001a05 | 10028 | |
e0001a05 | 10029 | |
74869ac7 BW |
10030 | /* Get the literal section to be used for the current text section. |
10031 | The result may be cached in the default_lit_sections structure. */ | |
10032 | ||
10033 | static segT | |
10034 | cache_literal_section (bfd_boolean use_abs_literals) | |
10035 | { | |
10036 | const char *text_name, *group_name = 0; | |
10037 | char *base_name, *name, *suffix; | |
10038 | segT *pcached; | |
10039 | segT seg, current_section; | |
10040 | int current_subsec; | |
10041 | bfd_boolean linkonce = FALSE; | |
10042 | ||
10043 | /* Save the current section/subsection. */ | |
10044 | current_section = now_seg; | |
10045 | current_subsec = now_subseg; | |
10046 | ||
10047 | /* Clear the cached values if they are no longer valid. */ | |
10048 | if (now_seg != default_lit_sections.current_text_seg) | |
b08b5071 | 10049 | { |
74869ac7 BW |
10050 | default_lit_sections.current_text_seg = now_seg; |
10051 | default_lit_sections.lit_seg = NULL; | |
10052 | default_lit_sections.lit4_seg = NULL; | |
10053 | } | |
10054 | ||
10055 | /* Check if the literal section is already cached. */ | |
10056 | if (use_abs_literals) | |
10057 | pcached = &default_lit_sections.lit4_seg; | |
10058 | else | |
10059 | pcached = &default_lit_sections.lit_seg; | |
10060 | ||
10061 | if (*pcached) | |
10062 | return *pcached; | |
10063 | ||
10064 | text_name = default_lit_sections.lit_prefix; | |
10065 | if (! text_name || ! *text_name) | |
10066 | { | |
10067 | text_name = segment_name (current_section); | |
10068 | group_name = elf_group_name (current_section); | |
10069 | linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; | |
10070 | } | |
10071 | ||
10072 | base_name = use_abs_literals ? ".lit4" : ".literal"; | |
10073 | if (group_name) | |
10074 | { | |
10075 | name = xmalloc (strlen (base_name) + strlen (group_name) + 2); | |
10076 | sprintf (name, "%s.%s", base_name, group_name); | |
10077 | } | |
10078 | else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) | |
10079 | { | |
10080 | suffix = strchr (text_name + linkonce_len, '.'); | |
10081 | ||
10082 | name = xmalloc (linkonce_len + strlen (base_name) + 1 | |
10083 | + (suffix ? strlen (suffix) : 0)); | |
10084 | strcpy (name, ".gnu.linkonce"); | |
10085 | strcat (name, base_name); | |
10086 | if (suffix) | |
10087 | strcat (name, suffix); | |
10088 | linkonce = TRUE; | |
10089 | } | |
10090 | else | |
10091 | { | |
10092 | /* If the section name ends with ".text", then replace that suffix | |
10093 | instead of appending an additional suffix. */ | |
10094 | size_t len = strlen (text_name); | |
10095 | if (len >= 5 && strcmp (text_name + len - 5, ".text") == 0) | |
10096 | len -= 5; | |
10097 | ||
10098 | name = xmalloc (len + strlen (base_name) + 1); | |
10099 | strcpy (name, text_name); | |
10100 | strcpy (name + len, base_name); | |
b08b5071 | 10101 | } |
e0001a05 | 10102 | |
74869ac7 BW |
10103 | /* Canonicalize section names to allow renaming literal sections. |
10104 | The group name, if any, came from the current text section and | |
10105 | has already been canonicalized. */ | |
10106 | name = tc_canonicalize_symbol_name (name); | |
10107 | ||
10108 | seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, | |
10109 | (void *) group_name); | |
10110 | if (! seg) | |
e0001a05 | 10111 | { |
74869ac7 BW |
10112 | flagword flags; |
10113 | ||
10114 | seg = subseg_force_new (name, 0); | |
10115 | ||
10116 | if (! use_abs_literals) | |
b08b5071 | 10117 | { |
74869ac7 | 10118 | /* Add the newly created literal segment to the list. */ |
b08b5071 BW |
10119 | seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); |
10120 | n->seg = seg; | |
74869ac7 BW |
10121 | n->next = literal_head->next; |
10122 | literal_head->next = n; | |
b08b5071 | 10123 | } |
74869ac7 BW |
10124 | |
10125 | flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD | |
10126 | | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) | |
10127 | | (use_abs_literals ? SEC_DATA : SEC_CODE)); | |
10128 | ||
10129 | elf_group_name (seg) = group_name; | |
10130 | ||
10131 | bfd_set_section_flags (stdoutput, seg, flags); | |
b08b5071 | 10132 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
10133 | } |
10134 | ||
74869ac7 | 10135 | *pcached = seg; |
b08b5071 | 10136 | subseg_set (current_section, current_subsec); |
74869ac7 | 10137 | return seg; |
e0001a05 NC |
10138 | } |
10139 | ||
43cd72b9 BW |
10140 | \f |
10141 | /* Property Tables Stuff. */ | |
10142 | ||
7fa3d080 BW |
10143 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
10144 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
10145 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
10146 | ||
10147 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
10148 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
10149 | ||
b08b5071 | 10150 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
10151 | static void xtensa_create_property_segments |
10152 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
10153 | static void xtensa_create_xproperty_segments | |
10154 | (frag_flags_fn, const char *, xt_section_type); | |
10155 | static segment_info_type *retrieve_segment_info (segT); | |
7fa3d080 BW |
10156 | static bfd_boolean section_has_property (segT, frag_predicate); |
10157 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
10158 | static void add_xt_block_frags | |
10159 | (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate); | |
10160 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); | |
10161 | static void xtensa_frag_flags_init (frag_flags *); | |
10162 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
10163 | static bfd_vma frag_flags_to_number (const frag_flags *); | |
10164 | static void add_xt_prop_frags | |
10165 | (segT, segT, xtensa_block_info **, frag_flags_fn); | |
10166 | ||
10167 | /* Set up property tables after relaxation. */ | |
10168 | ||
10169 | void | |
10170 | xtensa_post_relax_hook (void) | |
10171 | { | |
10172 | xtensa_move_seg_list_to_beginning (literal_head); | |
7fa3d080 BW |
10173 | |
10174 | xtensa_find_unmarked_state_frags (); | |
10175 | ||
b29757dc BW |
10176 | xtensa_create_property_segments (get_frag_is_literal, |
10177 | NULL, | |
10178 | XTENSA_LIT_SEC_NAME, | |
10179 | xt_literal_sec); | |
7fa3d080 BW |
10180 | xtensa_create_xproperty_segments (get_frag_property_flags, |
10181 | XTENSA_PROP_SEC_NAME, | |
10182 | xt_prop_sec); | |
10183 | ||
10184 | if (warn_unaligned_branch_targets) | |
10185 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
10186 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
10187 | } | |
10188 | ||
10189 | ||
43cd72b9 BW |
10190 | /* This function is only meaningful after xtensa_move_literals. */ |
10191 | ||
10192 | static bfd_boolean | |
7fa3d080 | 10193 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 BW |
10194 | { |
10195 | assert (fragP != NULL); | |
10196 | return fragP->tc_frag_data.is_literal; | |
10197 | } | |
10198 | ||
10199 | ||
43cd72b9 | 10200 | static void |
7fa3d080 BW |
10201 | xtensa_create_property_segments (frag_predicate property_function, |
10202 | frag_predicate end_property_function, | |
10203 | const char *section_name_base, | |
10204 | xt_section_type sec_type) | |
43cd72b9 BW |
10205 | { |
10206 | segT *seclist; | |
10207 | ||
10208 | /* Walk over all of the current segments. | |
10209 | Walk over each fragment | |
10210 | For each non-empty fragment, | |
10211 | Build a property record (append where possible). */ | |
10212 | ||
10213 | for (seclist = &stdoutput->sections; | |
10214 | seclist && *seclist; | |
10215 | seclist = &(*seclist)->next) | |
10216 | { | |
10217 | segT sec = *seclist; | |
10218 | flagword flags; | |
10219 | ||
10220 | flags = bfd_get_section_flags (stdoutput, sec); | |
10221 | if (flags & SEC_DEBUGGING) | |
10222 | continue; | |
10223 | if (!(flags & SEC_ALLOC)) | |
10224 | continue; | |
10225 | ||
10226 | if (section_has_property (sec, property_function)) | |
10227 | { | |
74869ac7 BW |
10228 | segT insn_sec = |
10229 | xtensa_get_property_section (sec, section_name_base); | |
43cd72b9 BW |
10230 | segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); |
10231 | xtensa_block_info **xt_blocks = | |
10232 | &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10233 | /* Walk over all of the frchains here and add new sections. */ | |
10234 | add_xt_block_frags (sec, insn_sec, xt_blocks, property_function, | |
10235 | end_property_function); | |
10236 | } | |
10237 | } | |
10238 | ||
10239 | /* Now we fill them out.... */ | |
10240 | ||
10241 | for (seclist = &stdoutput->sections; | |
10242 | seclist && *seclist; | |
10243 | seclist = &(*seclist)->next) | |
10244 | { | |
10245 | segment_info_type *seginfo; | |
10246 | xtensa_block_info *block; | |
10247 | segT sec = *seclist; | |
10248 | ||
10249 | seginfo = seg_info (sec); | |
10250 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10251 | ||
10252 | if (block) | |
10253 | { | |
10254 | xtensa_block_info *cur_block; | |
10255 | /* This is a section with some data. */ | |
10256 | int num_recs = 0; | |
d77b99c9 | 10257 | bfd_size_type rec_size; |
43cd72b9 BW |
10258 | |
10259 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10260 | num_recs++; | |
10261 | ||
10262 | rec_size = num_recs * 8; | |
10263 | bfd_set_section_size (stdoutput, sec, rec_size); | |
10264 | ||
10265 | /* In order to make this work with the assembler, we have to | |
10266 | build some frags and then build the "fixups" for it. It | |
10267 | would be easier to just set the contents then set the | |
10268 | arlents. */ | |
10269 | ||
10270 | if (num_recs) | |
10271 | { | |
10272 | /* Allocate a fragment and leak it. */ | |
10273 | fragS *fragP; | |
d77b99c9 | 10274 | bfd_size_type frag_size; |
43cd72b9 BW |
10275 | fixS *fixes; |
10276 | frchainS *frchainP; | |
10277 | int i; | |
10278 | char *frag_data; | |
10279 | ||
10280 | frag_size = sizeof (fragS) + rec_size; | |
10281 | fragP = (fragS *) xmalloc (frag_size); | |
e0001a05 | 10282 | |
43cd72b9 BW |
10283 | memset (fragP, 0, frag_size); |
10284 | fragP->fr_address = 0; | |
10285 | fragP->fr_next = NULL; | |
10286 | fragP->fr_fix = rec_size; | |
10287 | fragP->fr_var = 0; | |
10288 | fragP->fr_type = rs_fill; | |
10289 | /* The rest are zeros. */ | |
e0001a05 | 10290 | |
43cd72b9 BW |
10291 | frchainP = seginfo->frchainP; |
10292 | frchainP->frch_root = fragP; | |
10293 | frchainP->frch_last = fragP; | |
e0001a05 | 10294 | |
43cd72b9 BW |
10295 | fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); |
10296 | memset (fixes, 0, sizeof (fixS) * num_recs); | |
e0001a05 | 10297 | |
43cd72b9 BW |
10298 | seginfo->fix_root = fixes; |
10299 | seginfo->fix_tail = &fixes[num_recs - 1]; | |
10300 | cur_block = block; | |
10301 | frag_data = &fragP->fr_literal[0]; | |
10302 | for (i = 0; i < num_recs; i++) | |
10303 | { | |
10304 | fixS *fix = &fixes[i]; | |
10305 | assert (cur_block); | |
e0001a05 | 10306 | |
43cd72b9 BW |
10307 | /* Write the fixup. */ |
10308 | if (i != num_recs - 1) | |
10309 | fix->fx_next = &fixes[i + 1]; | |
10310 | else | |
10311 | fix->fx_next = NULL; | |
10312 | fix->fx_size = 4; | |
10313 | fix->fx_done = 0; | |
10314 | fix->fx_frag = fragP; | |
10315 | fix->fx_where = i * 8; | |
10316 | fix->fx_addsy = section_symbol (cur_block->sec); | |
10317 | fix->fx_offset = cur_block->offset; | |
10318 | fix->fx_r_type = BFD_RELOC_32; | |
10319 | fix->fx_file = "Internal Assembly"; | |
10320 | fix->fx_line = 0; | |
e0001a05 | 10321 | |
43cd72b9 BW |
10322 | /* Write the length. */ |
10323 | md_number_to_chars (&frag_data[4 + 8 * i], | |
10324 | cur_block->size, 4); | |
10325 | cur_block = cur_block->next; | |
10326 | } | |
10327 | } | |
10328 | } | |
10329 | } | |
e0001a05 NC |
10330 | } |
10331 | ||
10332 | ||
7fa3d080 BW |
10333 | static void |
10334 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
10335 | const char *section_name_base, | |
10336 | xt_section_type sec_type) | |
e0001a05 NC |
10337 | { |
10338 | segT *seclist; | |
10339 | ||
10340 | /* Walk over all of the current segments. | |
43cd72b9 BW |
10341 | Walk over each fragment. |
10342 | For each fragment that has instructions, | |
10343 | build an instruction record (append where possible). */ | |
e0001a05 NC |
10344 | |
10345 | for (seclist = &stdoutput->sections; | |
10346 | seclist && *seclist; | |
10347 | seclist = &(*seclist)->next) | |
10348 | { | |
10349 | segT sec = *seclist; | |
43cd72b9 BW |
10350 | flagword flags; |
10351 | ||
10352 | flags = bfd_get_section_flags (stdoutput, sec); | |
6624cbde BW |
10353 | if ((flags & SEC_DEBUGGING) |
10354 | || !(flags & SEC_ALLOC) | |
10355 | || (flags & SEC_MERGE)) | |
43cd72b9 BW |
10356 | continue; |
10357 | ||
10358 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 10359 | { |
74869ac7 BW |
10360 | segT insn_sec = |
10361 | xtensa_get_property_section (sec, section_name_base); | |
e0001a05 | 10362 | segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); |
43cd72b9 | 10363 | xtensa_block_info **xt_blocks = |
e0001a05 NC |
10364 | &xt_seg_info->tc_segment_info_data.blocks[sec_type]; |
10365 | /* Walk over all of the frchains here and add new sections. */ | |
43cd72b9 | 10366 | add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn); |
e0001a05 NC |
10367 | } |
10368 | } | |
10369 | ||
10370 | /* Now we fill them out.... */ | |
10371 | ||
10372 | for (seclist = &stdoutput->sections; | |
10373 | seclist && *seclist; | |
10374 | seclist = &(*seclist)->next) | |
10375 | { | |
10376 | segment_info_type *seginfo; | |
10377 | xtensa_block_info *block; | |
10378 | segT sec = *seclist; | |
43cd72b9 | 10379 | |
e0001a05 NC |
10380 | seginfo = seg_info (sec); |
10381 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10382 | ||
10383 | if (block) | |
10384 | { | |
10385 | xtensa_block_info *cur_block; | |
10386 | /* This is a section with some data. */ | |
43cd72b9 | 10387 | int num_recs = 0; |
d77b99c9 | 10388 | bfd_size_type rec_size; |
e0001a05 NC |
10389 | |
10390 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10391 | num_recs++; | |
10392 | ||
43cd72b9 | 10393 | rec_size = num_recs * (8 + 4); |
e0001a05 NC |
10394 | bfd_set_section_size (stdoutput, sec, rec_size); |
10395 | ||
43cd72b9 BW |
10396 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
10397 | ||
10398 | /* In order to make this work with the assembler, we have to build | |
10399 | some frags then build the "fixups" for it. It would be easier to | |
10400 | just set the contents then set the arlents. */ | |
e0001a05 NC |
10401 | |
10402 | if (num_recs) | |
10403 | { | |
43cd72b9 | 10404 | /* Allocate a fragment and (unfortunately) leak it. */ |
e0001a05 | 10405 | fragS *fragP; |
d77b99c9 | 10406 | bfd_size_type frag_size; |
e0001a05 NC |
10407 | fixS *fixes; |
10408 | frchainS *frchainP; | |
43cd72b9 | 10409 | int i; |
e0001a05 NC |
10410 | char *frag_data; |
10411 | ||
10412 | frag_size = sizeof (fragS) + rec_size; | |
10413 | fragP = (fragS *) xmalloc (frag_size); | |
10414 | ||
10415 | memset (fragP, 0, frag_size); | |
10416 | fragP->fr_address = 0; | |
10417 | fragP->fr_next = NULL; | |
10418 | fragP->fr_fix = rec_size; | |
10419 | fragP->fr_var = 0; | |
10420 | fragP->fr_type = rs_fill; | |
43cd72b9 | 10421 | /* The rest are zeros. */ |
e0001a05 NC |
10422 | |
10423 | frchainP = seginfo->frchainP; | |
10424 | frchainP->frch_root = fragP; | |
10425 | frchainP->frch_last = fragP; | |
10426 | ||
10427 | fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); | |
10428 | memset (fixes, 0, sizeof (fixS) * num_recs); | |
10429 | ||
10430 | seginfo->fix_root = fixes; | |
10431 | seginfo->fix_tail = &fixes[num_recs - 1]; | |
10432 | cur_block = block; | |
10433 | frag_data = &fragP->fr_literal[0]; | |
10434 | for (i = 0; i < num_recs; i++) | |
10435 | { | |
10436 | fixS *fix = &fixes[i]; | |
10437 | assert (cur_block); | |
10438 | ||
10439 | /* Write the fixup. */ | |
10440 | if (i != num_recs - 1) | |
10441 | fix->fx_next = &fixes[i + 1]; | |
10442 | else | |
10443 | fix->fx_next = NULL; | |
10444 | fix->fx_size = 4; | |
10445 | fix->fx_done = 0; | |
10446 | fix->fx_frag = fragP; | |
43cd72b9 | 10447 | fix->fx_where = i * (8 + 4); |
e0001a05 NC |
10448 | fix->fx_addsy = section_symbol (cur_block->sec); |
10449 | fix->fx_offset = cur_block->offset; | |
10450 | fix->fx_r_type = BFD_RELOC_32; | |
10451 | fix->fx_file = "Internal Assembly"; | |
10452 | fix->fx_line = 0; | |
10453 | ||
10454 | /* Write the length. */ | |
43cd72b9 | 10455 | md_number_to_chars (&frag_data[4 + (8+4) * i], |
e0001a05 | 10456 | cur_block->size, 4); |
43cd72b9 BW |
10457 | md_number_to_chars (&frag_data[8 + (8+4) * i], |
10458 | frag_flags_to_number (&cur_block->flags), | |
10459 | 4); | |
e0001a05 NC |
10460 | cur_block = cur_block->next; |
10461 | } | |
10462 | } | |
10463 | } | |
10464 | } | |
10465 | } | |
10466 | ||
10467 | ||
7fa3d080 BW |
10468 | static segment_info_type * |
10469 | retrieve_segment_info (segT seg) | |
e0001a05 NC |
10470 | { |
10471 | segment_info_type *seginfo; | |
10472 | seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg); | |
10473 | if (!seginfo) | |
10474 | { | |
10475 | frchainS *frchainP; | |
10476 | ||
10477 | seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo)); | |
7fa3d080 | 10478 | memset ((void *) seginfo, 0, sizeof (*seginfo)); |
e0001a05 NC |
10479 | seginfo->fix_root = NULL; |
10480 | seginfo->fix_tail = NULL; | |
10481 | seginfo->bfd_section = seg; | |
10482 | seginfo->sym = 0; | |
10483 | /* We will not be dealing with these, only our special ones. */ | |
65ec77d2 | 10484 | bfd_set_section_userdata (stdoutput, seg, (void *) seginfo); |
e0001a05 NC |
10485 | |
10486 | frchainP = (frchainS *) xmalloc (sizeof (frchainS)); | |
10487 | frchainP->frch_root = NULL; | |
10488 | frchainP->frch_last = NULL; | |
10489 | frchainP->frch_next = NULL; | |
e0001a05 NC |
10490 | frchainP->frch_subseg = 0; |
10491 | frchainP->fix_root = NULL; | |
10492 | frchainP->fix_tail = NULL; | |
10493 | /* Do not init the objstack. */ | |
10494 | /* obstack_begin (&frchainP->frch_obstack, chunksize); */ | |
10495 | /* frchainP->frch_frag_now = fragP; */ | |
10496 | frchainP->frch_frag_now = NULL; | |
10497 | ||
10498 | seginfo->frchainP = frchainP; | |
10499 | } | |
10500 | ||
10501 | return seginfo; | |
10502 | } | |
10503 | ||
10504 | ||
7fa3d080 BW |
10505 | static bfd_boolean |
10506 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
10507 | { |
10508 | segment_info_type *seginfo = seg_info (sec); | |
10509 | fragS *fragP; | |
10510 | ||
10511 | if (seginfo && seginfo->frchainP) | |
10512 | { | |
10513 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10514 | { | |
10515 | if (property_function (fragP) | |
10516 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10517 | return TRUE; | |
10518 | } | |
10519 | } | |
10520 | return FALSE; | |
10521 | } | |
10522 | ||
10523 | ||
7fa3d080 BW |
10524 | static bfd_boolean |
10525 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
10526 | { |
10527 | segment_info_type *seginfo = seg_info (sec); | |
10528 | fragS *fragP; | |
10529 | ||
10530 | if (seginfo && seginfo->frchainP) | |
10531 | { | |
10532 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10533 | { | |
10534 | frag_flags prop_flags; | |
10535 | property_function (fragP, &prop_flags); | |
10536 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
10537 | return TRUE; | |
10538 | } | |
10539 | } | |
10540 | return FALSE; | |
10541 | } | |
10542 | ||
10543 | ||
e0001a05 NC |
10544 | /* Two types of block sections exist right now: literal and insns. */ |
10545 | ||
7fa3d080 BW |
10546 | static void |
10547 | add_xt_block_frags (segT sec, | |
10548 | segT xt_block_sec, | |
10549 | xtensa_block_info **xt_block, | |
10550 | frag_predicate property_function, | |
10551 | frag_predicate end_property_function) | |
e0001a05 NC |
10552 | { |
10553 | segment_info_type *seg_info; | |
10554 | segment_info_type *xt_seg_info; | |
10555 | bfd_vma seg_offset; | |
10556 | fragS *fragP; | |
10557 | ||
10558 | xt_seg_info = retrieve_segment_info (xt_block_sec); | |
10559 | seg_info = retrieve_segment_info (sec); | |
10560 | ||
10561 | /* Build it if needed. */ | |
10562 | while (*xt_block != NULL) | |
10563 | xt_block = &(*xt_block)->next; | |
10564 | /* We are either at NULL at the beginning or at the end. */ | |
10565 | ||
10566 | /* Walk through the frags. */ | |
10567 | seg_offset = 0; | |
10568 | ||
10569 | if (seg_info->frchainP) | |
10570 | { | |
10571 | for (fragP = seg_info->frchainP->frch_root; | |
10572 | fragP; | |
10573 | fragP = fragP->fr_next) | |
10574 | { | |
10575 | if (property_function (fragP) | |
10576 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10577 | { | |
10578 | if (*xt_block != NULL) | |
10579 | { | |
10580 | if ((*xt_block)->offset + (*xt_block)->size | |
10581 | == fragP->fr_address) | |
10582 | (*xt_block)->size += fragP->fr_fix; | |
10583 | else | |
10584 | xt_block = &((*xt_block)->next); | |
10585 | } | |
10586 | if (*xt_block == NULL) | |
10587 | { | |
43cd72b9 BW |
10588 | xtensa_block_info *new_block = (xtensa_block_info *) |
10589 | xmalloc (sizeof (xtensa_block_info)); | |
10590 | new_block->sec = sec; | |
10591 | new_block->offset = fragP->fr_address; | |
10592 | new_block->size = fragP->fr_fix; | |
10593 | new_block->next = NULL; | |
10594 | xtensa_frag_flags_init (&new_block->flags); | |
10595 | *xt_block = new_block; | |
10596 | } | |
10597 | if (end_property_function | |
10598 | && end_property_function (fragP)) | |
10599 | { | |
10600 | xt_block = &((*xt_block)->next); | |
10601 | } | |
10602 | } | |
10603 | } | |
10604 | } | |
10605 | } | |
10606 | ||
10607 | ||
10608 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
10609 | ||
7fa3d080 BW |
10610 | static bfd_boolean |
10611 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
10612 | { |
10613 | if (prop_flags->is_literal | |
10614 | || prop_flags->is_insn | |
10615 | || prop_flags->is_data | |
10616 | || prop_flags->is_unreachable) | |
10617 | return FALSE; | |
10618 | return TRUE; | |
10619 | } | |
10620 | ||
10621 | ||
7fa3d080 BW |
10622 | static void |
10623 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
10624 | { |
10625 | memset (prop_flags, 0, sizeof (frag_flags)); | |
10626 | } | |
10627 | ||
10628 | ||
7fa3d080 BW |
10629 | static void |
10630 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
10631 | { |
10632 | xtensa_frag_flags_init (prop_flags); | |
10633 | if (fragP->tc_frag_data.is_literal) | |
10634 | prop_flags->is_literal = TRUE; | |
10635 | if (fragP->tc_frag_data.is_unreachable) | |
7fa3d080 | 10636 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
10637 | else if (fragP->tc_frag_data.is_insn) |
10638 | { | |
10639 | prop_flags->is_insn = TRUE; | |
10640 | if (fragP->tc_frag_data.is_loop_target) | |
10641 | prop_flags->insn.is_loop_target = TRUE; | |
10642 | if (fragP->tc_frag_data.is_branch_target) | |
10643 | prop_flags->insn.is_branch_target = TRUE; | |
10644 | if (fragP->tc_frag_data.is_specific_opcode | |
10645 | || fragP->tc_frag_data.is_no_transform) | |
10646 | prop_flags->insn.is_no_transform = TRUE; | |
10647 | if (fragP->tc_frag_data.is_no_density) | |
10648 | prop_flags->insn.is_no_density = TRUE; | |
10649 | if (fragP->tc_frag_data.use_absolute_literals) | |
10650 | prop_flags->insn.is_abslit = TRUE; | |
10651 | } | |
10652 | if (fragP->tc_frag_data.is_align) | |
10653 | { | |
10654 | prop_flags->is_align = TRUE; | |
10655 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
10656 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10657 | prop_flags->is_data = TRUE; | |
10658 | } | |
10659 | } | |
10660 | ||
10661 | ||
7fa3d080 BW |
10662 | static bfd_vma |
10663 | frag_flags_to_number (const frag_flags *prop_flags) | |
43cd72b9 BW |
10664 | { |
10665 | bfd_vma num = 0; | |
10666 | if (prop_flags->is_literal) | |
10667 | num |= XTENSA_PROP_LITERAL; | |
10668 | if (prop_flags->is_insn) | |
10669 | num |= XTENSA_PROP_INSN; | |
10670 | if (prop_flags->is_data) | |
10671 | num |= XTENSA_PROP_DATA; | |
10672 | if (prop_flags->is_unreachable) | |
10673 | num |= XTENSA_PROP_UNREACHABLE; | |
10674 | if (prop_flags->insn.is_loop_target) | |
10675 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
10676 | if (prop_flags->insn.is_branch_target) | |
10677 | { | |
10678 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
10679 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
10680 | } | |
10681 | ||
10682 | if (prop_flags->insn.is_no_density) | |
10683 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
10684 | if (prop_flags->insn.is_no_transform) | |
10685 | num |= XTENSA_PROP_INSN_NO_TRANSFORM; | |
10686 | if (prop_flags->insn.is_no_reorder) | |
10687 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
10688 | if (prop_flags->insn.is_abslit) | |
10689 | num |= XTENSA_PROP_INSN_ABSLIT; | |
10690 | ||
10691 | if (prop_flags->is_align) | |
10692 | { | |
10693 | num |= XTENSA_PROP_ALIGN; | |
10694 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
10695 | } | |
10696 | ||
10697 | return num; | |
10698 | } | |
10699 | ||
10700 | ||
10701 | static bfd_boolean | |
7fa3d080 BW |
10702 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
10703 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
10704 | { |
10705 | /* Cannot combine with an end marker. */ | |
10706 | ||
10707 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
10708 | return FALSE; | |
10709 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
10710 | return FALSE; | |
10711 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
10712 | return FALSE; | |
10713 | ||
10714 | if (prop_flags_1->is_insn) | |
10715 | { | |
10716 | /* Properties of the beginning of the frag. */ | |
10717 | if (prop_flags_2->insn.is_loop_target) | |
10718 | return FALSE; | |
10719 | if (prop_flags_2->insn.is_branch_target) | |
10720 | return FALSE; | |
10721 | if (prop_flags_1->insn.is_no_density != | |
10722 | prop_flags_2->insn.is_no_density) | |
10723 | return FALSE; | |
10724 | if (prop_flags_1->insn.is_no_transform != | |
10725 | prop_flags_2->insn.is_no_transform) | |
10726 | return FALSE; | |
10727 | if (prop_flags_1->insn.is_no_reorder != | |
10728 | prop_flags_2->insn.is_no_reorder) | |
10729 | return FALSE; | |
10730 | if (prop_flags_1->insn.is_abslit != | |
10731 | prop_flags_2->insn.is_abslit) | |
10732 | return FALSE; | |
10733 | } | |
10734 | ||
10735 | if (prop_flags_1->is_align) | |
10736 | return FALSE; | |
10737 | ||
10738 | return TRUE; | |
10739 | } | |
10740 | ||
10741 | ||
7fa3d080 BW |
10742 | static bfd_vma |
10743 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
10744 | { |
10745 | bfd_vma end_addr; | |
d77b99c9 | 10746 | unsigned align_bits; |
43cd72b9 BW |
10747 | |
10748 | if (!xt_block->flags.is_align) | |
10749 | return xt_block->size; | |
10750 | ||
10751 | end_addr = xt_block->offset + xt_block->size; | |
10752 | align_bits = xt_block->flags.alignment; | |
10753 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
10754 | return end_addr - xt_block->offset; | |
10755 | } | |
10756 | ||
10757 | ||
10758 | static bfd_boolean | |
7fa3d080 BW |
10759 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
10760 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
10761 | { |
10762 | if (xt_block->sec != xt_block_2->sec) | |
10763 | return FALSE; | |
10764 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
10765 | != xt_block_2->offset) | |
10766 | return FALSE; | |
10767 | ||
10768 | if (xt_block_2->size == 0 | |
10769 | && (!xt_block_2->flags.is_unreachable | |
10770 | || xt_block->flags.is_unreachable)) | |
10771 | { | |
10772 | if (xt_block_2->flags.is_align | |
10773 | && xt_block->flags.is_align) | |
10774 | { | |
10775 | /* Nothing needed. */ | |
10776 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
10777 | return TRUE; | |
10778 | } | |
10779 | else | |
10780 | { | |
10781 | if (xt_block_2->flags.is_align) | |
10782 | { | |
10783 | /* Push alignment to previous entry. */ | |
10784 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
10785 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10786 | } | |
10787 | return TRUE; | |
10788 | } | |
10789 | } | |
10790 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
10791 | &xt_block_2->flags)) | |
10792 | return FALSE; | |
10793 | ||
10794 | xt_block->size += xt_block_2->size; | |
10795 | ||
10796 | if (xt_block_2->flags.is_align) | |
10797 | { | |
10798 | xt_block->flags.is_align = TRUE; | |
10799 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10800 | } | |
10801 | ||
10802 | return TRUE; | |
10803 | } | |
10804 | ||
10805 | ||
7fa3d080 BW |
10806 | static void |
10807 | add_xt_prop_frags (segT sec, | |
10808 | segT xt_block_sec, | |
10809 | xtensa_block_info **xt_block, | |
10810 | frag_flags_fn property_function) | |
43cd72b9 BW |
10811 | { |
10812 | segment_info_type *seg_info; | |
10813 | segment_info_type *xt_seg_info; | |
10814 | bfd_vma seg_offset; | |
10815 | fragS *fragP; | |
10816 | ||
10817 | xt_seg_info = retrieve_segment_info (xt_block_sec); | |
10818 | seg_info = retrieve_segment_info (sec); | |
10819 | /* Build it if needed. */ | |
10820 | while (*xt_block != NULL) | |
10821 | { | |
10822 | xt_block = &(*xt_block)->next; | |
10823 | } | |
10824 | /* We are either at NULL at the beginning or at the end. */ | |
10825 | ||
10826 | /* Walk through the frags. */ | |
10827 | seg_offset = 0; | |
10828 | ||
10829 | if (seg_info->frchainP) | |
10830 | { | |
10831 | for (fragP = seg_info->frchainP->frch_root; fragP; | |
10832 | fragP = fragP->fr_next) | |
10833 | { | |
10834 | xtensa_block_info tmp_block; | |
10835 | tmp_block.sec = sec; | |
10836 | tmp_block.offset = fragP->fr_address; | |
10837 | tmp_block.size = fragP->fr_fix; | |
10838 | tmp_block.next = NULL; | |
10839 | property_function (fragP, &tmp_block.flags); | |
10840 | ||
10841 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
10842 | /* && fragP->fr_fix != 0) */ | |
10843 | { | |
10844 | if ((*xt_block) == NULL | |
10845 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
10846 | { | |
10847 | xtensa_block_info *new_block; | |
10848 | if ((*xt_block) != NULL) | |
10849 | xt_block = &(*xt_block)->next; | |
10850 | new_block = (xtensa_block_info *) | |
10851 | xmalloc (sizeof (xtensa_block_info)); | |
10852 | *new_block = tmp_block; | |
10853 | *xt_block = new_block; | |
10854 | } | |
10855 | } | |
10856 | } | |
10857 | } | |
10858 | } | |
10859 | ||
10860 | \f | |
10861 | /* op_placement_info_table */ | |
10862 | ||
10863 | /* op_placement_info makes it easier to determine which | |
10864 | ops can go in which slots. */ | |
10865 | ||
10866 | static void | |
7fa3d080 | 10867 | init_op_placement_info_table (void) |
43cd72b9 BW |
10868 | { |
10869 | xtensa_isa isa = xtensa_default_isa; | |
10870 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
10871 | xtensa_opcode opcode; | |
10872 | xtensa_format fmt; | |
10873 | int slot; | |
10874 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
10875 | ||
10876 | op_placement_table = (op_placement_info_table) | |
10877 | xmalloc (sizeof (op_placement_info) * num_opcodes); | |
10878 | assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); | |
10879 | ||
10880 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
10881 | { | |
10882 | op_placement_info *opi = &op_placement_table[opcode]; | |
10883 | /* FIXME: Make tinsn allocation dynamic. */ | |
10884 | if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS) | |
10885 | as_fatal (_("too many operands in instruction")); | |
43cd72b9 BW |
10886 | opi->narrowest = XTENSA_UNDEFINED; |
10887 | opi->narrowest_size = 0x7F; | |
b2d179be | 10888 | opi->narrowest_slot = 0; |
43cd72b9 BW |
10889 | opi->formats = 0; |
10890 | opi->num_formats = 0; | |
10891 | opi->issuef = 0; | |
10892 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
10893 | { | |
10894 | opi->slots[fmt] = 0; | |
10895 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
10896 | { | |
10897 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
10898 | { | |
10899 | int fmt_length = xtensa_format_length (isa, fmt); | |
10900 | opi->issuef++; | |
10901 | set_bit (fmt, opi->formats); | |
10902 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
10903 | if (fmt_length < opi->narrowest_size |
10904 | || (fmt_length == opi->narrowest_size | |
10905 | && (xtensa_format_num_slots (isa, fmt) | |
10906 | < xtensa_format_num_slots (isa, | |
10907 | opi->narrowest)))) | |
43cd72b9 BW |
10908 | { |
10909 | opi->narrowest = fmt; | |
10910 | opi->narrowest_size = fmt_length; | |
b2d179be | 10911 | opi->narrowest_slot = slot; |
43cd72b9 | 10912 | } |
e0001a05 NC |
10913 | } |
10914 | } | |
43cd72b9 BW |
10915 | if (opi->formats) |
10916 | opi->num_formats++; | |
e0001a05 NC |
10917 | } |
10918 | } | |
43cd72b9 BW |
10919 | xtensa_insnbuf_free (isa, ibuf); |
10920 | } | |
10921 | ||
10922 | ||
10923 | bfd_boolean | |
7fa3d080 | 10924 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
10925 | { |
10926 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
10927 | } | |
10928 | ||
10929 | ||
10930 | /* If the opcode is available in a single slot format, return its size. */ | |
10931 | ||
7fa3d080 BW |
10932 | static int |
10933 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 10934 | { |
b2d179be | 10935 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
10936 | } |
10937 | ||
10938 | ||
7fa3d080 BW |
10939 | static xtensa_format |
10940 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 10941 | { |
b2d179be BW |
10942 | return op_placement_table[opcode].narrowest; |
10943 | } | |
10944 | ||
10945 | ||
10946 | static int | |
10947 | xg_get_single_slot (xtensa_opcode opcode) | |
10948 | { | |
10949 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
10950 | } |
10951 | ||
10952 | \f | |
10953 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
10954 | ||
10955 | void | |
7fa3d080 | 10956 | istack_init (IStack *stack) |
e0001a05 NC |
10957 | { |
10958 | memset (stack, 0, sizeof (IStack)); | |
10959 | stack->ninsn = 0; | |
10960 | } | |
10961 | ||
10962 | ||
10963 | bfd_boolean | |
7fa3d080 | 10964 | istack_empty (IStack *stack) |
e0001a05 NC |
10965 | { |
10966 | return (stack->ninsn == 0); | |
10967 | } | |
10968 | ||
10969 | ||
10970 | bfd_boolean | |
7fa3d080 | 10971 | istack_full (IStack *stack) |
e0001a05 NC |
10972 | { |
10973 | return (stack->ninsn == MAX_ISTACK); | |
10974 | } | |
10975 | ||
10976 | ||
10977 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 10978 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
10979 | |
10980 | TInsn * | |
7fa3d080 | 10981 | istack_top (IStack *stack) |
e0001a05 NC |
10982 | { |
10983 | int rec = stack->ninsn - 1; | |
10984 | assert (!istack_empty (stack)); | |
10985 | return &stack->insn[rec]; | |
10986 | } | |
10987 | ||
10988 | ||
10989 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 10990 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
10991 | |
10992 | void | |
7fa3d080 | 10993 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
10994 | { |
10995 | int rec = stack->ninsn; | |
10996 | assert (!istack_full (stack)); | |
43cd72b9 | 10997 | stack->insn[rec] = *insn; |
e0001a05 NC |
10998 | stack->ninsn++; |
10999 | } | |
11000 | ||
11001 | ||
11002 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 11003 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11004 | |
11005 | TInsn * | |
7fa3d080 | 11006 | istack_push_space (IStack *stack) |
e0001a05 NC |
11007 | { |
11008 | int rec = stack->ninsn; | |
11009 | TInsn *insn; | |
11010 | assert (!istack_full (stack)); | |
11011 | insn = &stack->insn[rec]; | |
60242db2 | 11012 | tinsn_init (insn); |
e0001a05 NC |
11013 | stack->ninsn++; |
11014 | return insn; | |
11015 | } | |
11016 | ||
11017 | ||
11018 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 11019 | istack_empty () returns TRUE. */ |
e0001a05 NC |
11020 | |
11021 | void | |
7fa3d080 | 11022 | istack_pop (IStack *stack) |
e0001a05 NC |
11023 | { |
11024 | int rec = stack->ninsn - 1; | |
11025 | assert (!istack_empty (stack)); | |
11026 | stack->ninsn--; | |
60242db2 | 11027 | tinsn_init (&stack->insn[rec]); |
e0001a05 NC |
11028 | } |
11029 | ||
11030 | \f | |
11031 | /* TInsn functions. */ | |
11032 | ||
11033 | void | |
7fa3d080 | 11034 | tinsn_init (TInsn *dst) |
e0001a05 NC |
11035 | { |
11036 | memset (dst, 0, sizeof (TInsn)); | |
11037 | } | |
11038 | ||
11039 | ||
43cd72b9 | 11040 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
11041 | |
11042 | static bfd_boolean | |
7fa3d080 | 11043 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
11044 | { |
11045 | int i; | |
11046 | int n = insn->ntok; | |
11047 | ||
11048 | assert (insn->insn_type == ITYPE_INSN); | |
11049 | ||
11050 | for (i = 0; i < n; ++i) | |
11051 | { | |
11052 | switch (insn->tok[i].X_op) | |
11053 | { | |
11054 | case O_register: | |
11055 | case O_constant: | |
11056 | break; | |
11057 | default: | |
11058 | return TRUE; | |
11059 | } | |
11060 | } | |
11061 | return FALSE; | |
11062 | } | |
11063 | ||
11064 | ||
11065 | bfd_boolean | |
7fa3d080 | 11066 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 11067 | { |
43cd72b9 | 11068 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
11069 | int i; |
11070 | int n = insn->ntok; | |
11071 | ||
11072 | assert (insn->insn_type == ITYPE_INSN); | |
11073 | ||
11074 | for (i = 0; i < n; ++i) | |
11075 | { | |
11076 | switch (insn->tok[i].X_op) | |
11077 | { | |
11078 | case O_register: | |
11079 | case O_constant: | |
11080 | break; | |
43cd72b9 BW |
11081 | case O_big: |
11082 | case O_illegal: | |
11083 | case O_absent: | |
11084 | /* Errors for these types are caught later. */ | |
11085 | break; | |
11086 | case O_hi16: | |
11087 | case O_lo16: | |
e0001a05 | 11088 | default: |
43cd72b9 BW |
11089 | /* Symbolic immediates are only allowed on the last immediate |
11090 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 11091 | support non-PC-relative relocations. */ |
43cd72b9 BW |
11092 | if (i != get_relaxable_immed (insn->opcode) |
11093 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
11094 | && insn->opcode != xtensa_const16_opcode)) | |
11095 | { | |
431ad2d0 | 11096 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
11097 | return TRUE; |
11098 | } | |
e0001a05 NC |
11099 | } |
11100 | } | |
11101 | return FALSE; | |
11102 | } | |
11103 | ||
11104 | ||
11105 | /* For assembly code with complex expressions (e.g. subtraction), | |
11106 | we have to build them in the literal pool so that | |
11107 | their results are calculated correctly after relaxation. | |
11108 | The relaxation only handles expressions that | |
11109 | boil down to SYMBOL + OFFSET. */ | |
11110 | ||
11111 | static bfd_boolean | |
7fa3d080 | 11112 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
11113 | { |
11114 | int i; | |
11115 | int n = insn->ntok; | |
11116 | assert (insn->insn_type == ITYPE_INSN); | |
11117 | for (i = 0; i < n; ++i) | |
11118 | { | |
11119 | switch (insn->tok[i].X_op) | |
11120 | { | |
11121 | case O_register: | |
11122 | case O_constant: | |
11123 | case O_symbol: | |
43cd72b9 BW |
11124 | case O_lo16: |
11125 | case O_hi16: | |
e0001a05 NC |
11126 | break; |
11127 | default: | |
11128 | return TRUE; | |
11129 | } | |
11130 | } | |
11131 | return FALSE; | |
11132 | } | |
11133 | ||
11134 | ||
b2d179be BW |
11135 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
11136 | Return TRUE if there is a symbol in the immediate field. This | |
11137 | function assumes that: | |
11138 | 1) The number of operands are correct. | |
11139 | 2) The insn_type is ITYPE_INSN. | |
11140 | 3) The opcode can be encoded in the specified format and slot. | |
11141 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
11142 | |
11143 | static bfd_boolean | |
7fa3d080 BW |
11144 | tinsn_to_slotbuf (xtensa_format fmt, |
11145 | int slot, | |
11146 | TInsn *tinsn, | |
11147 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
11148 | { |
11149 | xtensa_isa isa = xtensa_default_isa; | |
11150 | xtensa_opcode opcode = tinsn->opcode; | |
11151 | bfd_boolean has_fixup = FALSE; | |
11152 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11153 | int i; | |
11154 | ||
43cd72b9 BW |
11155 | assert (tinsn->insn_type == ITYPE_INSN); |
11156 | if (noperands != tinsn->ntok) | |
11157 | as_fatal (_("operand number mismatch")); | |
11158 | ||
11159 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
11160 | { | |
11161 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
11162 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
11163 | return FALSE; | |
11164 | } | |
11165 | ||
11166 | for (i = 0; i < noperands; i++) | |
11167 | { | |
11168 | expressionS *expr = &tinsn->tok[i]; | |
d77b99c9 BW |
11169 | int rc; |
11170 | unsigned line; | |
43cd72b9 BW |
11171 | char *file_name; |
11172 | uint32 opnd_value; | |
11173 | ||
11174 | switch (expr->X_op) | |
11175 | { | |
11176 | case O_register: | |
11177 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11178 | break; | |
11179 | /* The register number has already been checked in | |
11180 | expression_maybe_register, so we don't need to check here. */ | |
11181 | opnd_value = expr->X_add_number; | |
11182 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); | |
11183 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
11184 | opnd_value); | |
11185 | if (rc != 0) | |
11186 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
11187 | break; | |
11188 | ||
11189 | case O_constant: | |
11190 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11191 | break; | |
11192 | as_where (&file_name, &line); | |
11193 | /* It is a constant and we called this function | |
11194 | then we have to try to fit it. */ | |
11195 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
e0001a05 NC |
11196 | expr->X_add_number, file_name, line); |
11197 | break; | |
11198 | ||
e0001a05 NC |
11199 | default: |
11200 | has_fixup = TRUE; | |
11201 | break; | |
11202 | } | |
11203 | } | |
43cd72b9 | 11204 | |
e0001a05 NC |
11205 | return has_fixup; |
11206 | } | |
11207 | ||
11208 | ||
b2d179be BW |
11209 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
11210 | into a multi-slot instruction, fill the other slots with NOPs. | |
11211 | Return TRUE if there is a symbol in the immediate field. See also the | |
11212 | assumptions listed for tinsn_to_slotbuf. */ | |
11213 | ||
11214 | static bfd_boolean | |
11215 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
11216 | { | |
11217 | static xtensa_insnbuf slotbuf = 0; | |
11218 | static vliw_insn vinsn; | |
11219 | xtensa_isa isa = xtensa_default_isa; | |
11220 | bfd_boolean has_fixup = FALSE; | |
11221 | int i; | |
11222 | ||
11223 | if (!slotbuf) | |
11224 | { | |
11225 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11226 | xg_init_vinsn (&vinsn); | |
11227 | } | |
11228 | ||
11229 | xg_clear_vinsn (&vinsn); | |
11230 | ||
11231 | bundle_tinsn (tinsn, &vinsn); | |
11232 | ||
11233 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
11234 | ||
11235 | for (i = 0; i < vinsn.num_slots; i++) | |
11236 | { | |
11237 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
11238 | has_fixup |= | |
11239 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
11240 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
11241 | } | |
11242 | ||
11243 | return has_fixup; | |
11244 | } | |
11245 | ||
11246 | ||
43cd72b9 | 11247 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 11248 | |
7fa3d080 BW |
11249 | static bfd_boolean |
11250 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
11251 | { |
11252 | xtensa_isa isa = xtensa_default_isa; | |
11253 | xtensa_opcode opcode = insn->opcode; | |
11254 | ||
11255 | if (opcode == XTENSA_UNDEFINED) | |
11256 | { | |
11257 | as_bad (_("invalid opcode")); | |
11258 | return TRUE; | |
11259 | } | |
11260 | ||
43cd72b9 | 11261 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
11262 | { |
11263 | as_bad (_("too few operands")); | |
11264 | return TRUE; | |
11265 | } | |
11266 | ||
43cd72b9 | 11267 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
11268 | { |
11269 | as_bad (_("too many operands")); | |
11270 | return TRUE; | |
11271 | } | |
11272 | return FALSE; | |
11273 | } | |
11274 | ||
11275 | ||
11276 | /* Load an instruction from its encoded form. */ | |
11277 | ||
11278 | static void | |
7fa3d080 | 11279 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 11280 | { |
43cd72b9 | 11281 | vliw_insn vinsn; |
e0001a05 | 11282 | |
43cd72b9 BW |
11283 | xg_init_vinsn (&vinsn); |
11284 | vinsn_from_chars (&vinsn, f); | |
11285 | ||
11286 | *tinsn = vinsn.slots[slot]; | |
11287 | xg_free_vinsn (&vinsn); | |
11288 | } | |
e0001a05 | 11289 | |
43cd72b9 BW |
11290 | |
11291 | static void | |
7fa3d080 BW |
11292 | tinsn_from_insnbuf (TInsn *tinsn, |
11293 | xtensa_insnbuf slotbuf, | |
11294 | xtensa_format fmt, | |
11295 | int slot) | |
43cd72b9 BW |
11296 | { |
11297 | int i; | |
11298 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
11299 | |
11300 | /* Find the immed. */ | |
43cd72b9 BW |
11301 | tinsn_init (tinsn); |
11302 | tinsn->insn_type = ITYPE_INSN; | |
11303 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
11304 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
11305 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
11306 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 11307 | { |
43cd72b9 BW |
11308 | set_expr_const (&tinsn->tok[i], |
11309 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
11310 | tinsn->opcode, i)); | |
e0001a05 NC |
11311 | } |
11312 | } | |
11313 | ||
11314 | ||
11315 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
11316 | ||
11317 | static void | |
7fa3d080 | 11318 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 11319 | { |
43cd72b9 | 11320 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
11321 | int opnum; |
11322 | ||
43cd72b9 | 11323 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
11324 | { |
11325 | opnum = get_relaxable_immed (opcode); | |
43cd72b9 | 11326 | assert (opnum >= 0); |
e7da6241 BW |
11327 | set_expr_symbol_offset (&tinsn->tok[opnum], |
11328 | fragP->tc_frag_data.slot_symbols[slot], | |
11329 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 NC |
11330 | } |
11331 | } | |
11332 | ||
11333 | ||
11334 | static int | |
7fa3d080 | 11335 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
11336 | { |
11337 | int i; | |
11338 | int text_bytes = 0; | |
11339 | ||
11340 | for (i = 0; i < istack->ninsn; i++) | |
11341 | { | |
43cd72b9 BW |
11342 | TInsn *tinsn = &istack->insn[i]; |
11343 | if (tinsn->insn_type == ITYPE_INSN) | |
11344 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
11345 | } |
11346 | return text_bytes; | |
11347 | } | |
11348 | ||
11349 | ||
11350 | static int | |
7fa3d080 | 11351 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
11352 | { |
11353 | int i; | |
11354 | int lit_bytes = 0; | |
11355 | ||
11356 | for (i = 0; i < istack->ninsn; i++) | |
11357 | { | |
43cd72b9 BW |
11358 | TInsn *tinsn = &istack->insn[i]; |
11359 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
11360 | lit_bytes += 4; |
11361 | } | |
11362 | return lit_bytes; | |
11363 | } | |
11364 | ||
43cd72b9 BW |
11365 | \f |
11366 | /* vliw_insn functions. */ | |
11367 | ||
7fa3d080 BW |
11368 | static void |
11369 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11370 | { |
11371 | int i; | |
11372 | xtensa_isa isa = xtensa_default_isa; | |
11373 | ||
11374 | xg_clear_vinsn (v); | |
11375 | ||
11376 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
11377 | if (v->insnbuf == NULL) | |
11378 | as_fatal (_("out of memory")); | |
11379 | ||
11380 | for (i = 0; i < MAX_SLOTS; i++) | |
11381 | { | |
43cd72b9 BW |
11382 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
11383 | if (v->slotbuf[i] == NULL) | |
11384 | as_fatal (_("out of memory")); | |
11385 | } | |
11386 | } | |
11387 | ||
11388 | ||
7fa3d080 BW |
11389 | static void |
11390 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11391 | { |
11392 | int i; | |
65738a7d BW |
11393 | |
11394 | memset (v, 0, offsetof (vliw_insn, insnbuf)); | |
11395 | ||
43cd72b9 BW |
11396 | v->format = XTENSA_UNDEFINED; |
11397 | v->num_slots = 0; | |
11398 | v->inside_bundle = FALSE; | |
11399 | ||
11400 | if (xt_saved_debug_type != DEBUG_NONE) | |
11401 | debug_type = xt_saved_debug_type; | |
11402 | ||
11403 | for (i = 0; i < MAX_SLOTS; i++) | |
65738a7d | 11404 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
11405 | } |
11406 | ||
11407 | ||
7fa3d080 BW |
11408 | static bfd_boolean |
11409 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
11410 | { |
11411 | int i; | |
c138bc38 | 11412 | |
43cd72b9 BW |
11413 | for (i = 0; i < v->num_slots; i++) |
11414 | { | |
11415 | if (v->slots[i].is_specific_opcode) | |
11416 | return TRUE; | |
11417 | } | |
11418 | return FALSE; | |
11419 | } | |
11420 | ||
11421 | ||
7fa3d080 BW |
11422 | static void |
11423 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11424 | { |
11425 | int i; | |
11426 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
11427 | for (i = 0; i < MAX_SLOTS; i++) | |
11428 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); | |
11429 | } | |
11430 | ||
11431 | ||
e7da6241 BW |
11432 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
11433 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
11434 | |
11435 | static bfd_boolean | |
7fa3d080 BW |
11436 | vinsn_to_insnbuf (vliw_insn *vinsn, |
11437 | char *frag_offset, | |
11438 | fragS *fragP, | |
11439 | bfd_boolean record_fixup) | |
43cd72b9 BW |
11440 | { |
11441 | xtensa_isa isa = xtensa_default_isa; | |
11442 | xtensa_format fmt = vinsn->format; | |
11443 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
11444 | int slot; | |
11445 | bfd_boolean has_fixup = FALSE; | |
11446 | ||
11447 | xtensa_format_encode (isa, fmt, insnbuf); | |
11448 | ||
11449 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
11450 | { | |
11451 | TInsn *tinsn = &vinsn->slots[slot]; | |
11452 | bfd_boolean tinsn_has_fixup = | |
11453 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
11454 | vinsn->slotbuf[slot]); | |
11455 | ||
11456 | xtensa_format_set_slot (isa, fmt, slot, | |
11457 | insnbuf, vinsn->slotbuf[slot]); | |
e7da6241 | 11458 | if (tinsn_has_fixup) |
43cd72b9 BW |
11459 | { |
11460 | int i; | |
11461 | xtensa_opcode opcode = tinsn->opcode; | |
11462 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11463 | has_fixup = TRUE; | |
11464 | ||
11465 | for (i = 0; i < noperands; i++) | |
11466 | { | |
11467 | expressionS* expr = &tinsn->tok[i]; | |
11468 | switch (expr->X_op) | |
11469 | { | |
11470 | case O_symbol: | |
11471 | case O_lo16: | |
11472 | case O_hi16: | |
11473 | if (get_relaxable_immed (opcode) == i) | |
11474 | { | |
e7da6241 BW |
11475 | /* Add a fix record for the instruction, except if this |
11476 | function is being called prior to relaxation, i.e., | |
11477 | if record_fixup is false, and the instruction might | |
11478 | be relaxed later. */ | |
11479 | if (record_fixup | |
11480 | || tinsn->is_specific_opcode | |
11481 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 11482 | { |
e7da6241 BW |
11483 | xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP, |
11484 | frag_offset - fragP->fr_literal); | |
43cd72b9 BW |
11485 | } |
11486 | else | |
11487 | { | |
e7da6241 BW |
11488 | if (expr->X_op != O_symbol) |
11489 | as_bad (_("invalid operand")); | |
43cd72b9 BW |
11490 | tinsn->symbol = expr->X_add_symbol; |
11491 | tinsn->offset = expr->X_add_number; | |
11492 | } | |
11493 | } | |
11494 | else | |
e7da6241 | 11495 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
11496 | break; |
11497 | ||
11498 | case O_constant: | |
11499 | case O_register: | |
11500 | break; | |
11501 | ||
43cd72b9 | 11502 | default: |
e7da6241 | 11503 | as_bad (_("expression too complex")); |
43cd72b9 BW |
11504 | break; |
11505 | } | |
11506 | } | |
11507 | } | |
11508 | } | |
11509 | ||
11510 | return has_fixup; | |
11511 | } | |
11512 | ||
11513 | ||
11514 | static void | |
7fa3d080 | 11515 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
11516 | { |
11517 | static xtensa_insnbuf insnbuf = NULL; | |
11518 | static xtensa_insnbuf slotbuf = NULL; | |
11519 | int i; | |
11520 | xtensa_format fmt; | |
11521 | xtensa_isa isa = xtensa_default_isa; | |
11522 | ||
11523 | if (!insnbuf) | |
11524 | { | |
11525 | insnbuf = xtensa_insnbuf_alloc (isa); | |
11526 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11527 | } | |
11528 | ||
d77b99c9 | 11529 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
11530 | fmt = xtensa_format_decode (isa, insnbuf); |
11531 | if (fmt == XTENSA_UNDEFINED) | |
11532 | as_fatal (_("cannot decode instruction format")); | |
11533 | vinsn->format = fmt; | |
11534 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
11535 | ||
11536 | for (i = 0; i < vinsn->num_slots; i++) | |
11537 | { | |
11538 | TInsn *tinsn = &vinsn->slots[i]; | |
11539 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
11540 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
11541 | } | |
11542 | } | |
11543 | ||
e0001a05 NC |
11544 | \f |
11545 | /* Expression utilities. */ | |
11546 | ||
43cd72b9 | 11547 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
11548 | |
11549 | bfd_boolean | |
7fa3d080 | 11550 | expr_is_const (const expressionS *s) |
e0001a05 NC |
11551 | { |
11552 | return (s->X_op == O_constant); | |
11553 | } | |
11554 | ||
11555 | ||
11556 | /* Get the expression constant. | |
43cd72b9 | 11557 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
11558 | |
11559 | offsetT | |
7fa3d080 | 11560 | get_expr_const (const expressionS *s) |
e0001a05 NC |
11561 | { |
11562 | assert (expr_is_const (s)); | |
11563 | return s->X_add_number; | |
11564 | } | |
11565 | ||
11566 | ||
11567 | /* Set the expression to a constant value. */ | |
11568 | ||
11569 | void | |
7fa3d080 | 11570 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
11571 | { |
11572 | s->X_op = O_constant; | |
11573 | s->X_add_number = val; | |
11574 | s->X_add_symbol = NULL; | |
11575 | s->X_op_symbol = NULL; | |
11576 | } | |
11577 | ||
11578 | ||
43cd72b9 | 11579 | bfd_boolean |
7fa3d080 | 11580 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
11581 | { |
11582 | return (s->X_op == O_register); | |
11583 | } | |
11584 | ||
11585 | ||
11586 | /* Get the expression constant. | |
11587 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
11588 | ||
11589 | offsetT | |
7fa3d080 | 11590 | get_expr_register (const expressionS *s) |
43cd72b9 BW |
11591 | { |
11592 | assert (expr_is_register (s)); | |
11593 | return s->X_add_number; | |
11594 | } | |
11595 | ||
11596 | ||
e0001a05 NC |
11597 | /* Set the expression to a symbol + constant offset. */ |
11598 | ||
11599 | void | |
7fa3d080 | 11600 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
11601 | { |
11602 | s->X_op = O_symbol; | |
11603 | s->X_add_symbol = sym; | |
11604 | s->X_op_symbol = NULL; /* unused */ | |
11605 | s->X_add_number = offset; | |
11606 | } | |
11607 | ||
11608 | ||
43cd72b9 BW |
11609 | /* Return TRUE if the two expressions are equal. */ |
11610 | ||
e0001a05 | 11611 | bfd_boolean |
7fa3d080 | 11612 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
11613 | { |
11614 | if (s1->X_op != s2->X_op) | |
11615 | return FALSE; | |
11616 | if (s1->X_add_symbol != s2->X_add_symbol) | |
11617 | return FALSE; | |
11618 | if (s1->X_op_symbol != s2->X_op_symbol) | |
11619 | return FALSE; | |
11620 | if (s1->X_add_number != s2->X_add_number) | |
11621 | return FALSE; | |
11622 | return TRUE; | |
11623 | } | |
11624 | ||
11625 | ||
11626 | static void | |
7fa3d080 | 11627 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
11628 | { |
11629 | memcpy (dst, src, sizeof (expressionS)); | |
11630 | } | |
11631 | ||
11632 | \f | |
9456465c | 11633 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
11634 | |
11635 | struct rename_section_struct | |
11636 | { | |
11637 | char *old_name; | |
11638 | char *new_name; | |
11639 | struct rename_section_struct *next; | |
11640 | }; | |
11641 | ||
11642 | static struct rename_section_struct *section_rename; | |
11643 | ||
11644 | ||
9456465c BW |
11645 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
11646 | entries to the section_rename list. Note: Specifying multiple | |
11647 | renamings separated by colons is not documented and is retained only | |
11648 | for backward compatibility. */ | |
e0001a05 | 11649 | |
7fa3d080 BW |
11650 | static void |
11651 | build_section_rename (const char *arg) | |
e0001a05 | 11652 | { |
9456465c | 11653 | struct rename_section_struct *r; |
e0001a05 NC |
11654 | char *this_arg = NULL; |
11655 | char *next_arg = NULL; | |
11656 | ||
9456465c | 11657 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 11658 | { |
9456465c BW |
11659 | char *old_name, *new_name; |
11660 | ||
e0001a05 NC |
11661 | if (this_arg) |
11662 | { | |
11663 | next_arg = strchr (this_arg, ':'); | |
11664 | if (next_arg) | |
11665 | { | |
11666 | *next_arg = '\0'; | |
11667 | next_arg++; | |
11668 | } | |
11669 | } | |
e0001a05 | 11670 | |
9456465c BW |
11671 | old_name = this_arg; |
11672 | new_name = strchr (this_arg, '='); | |
e0001a05 | 11673 | |
9456465c BW |
11674 | if (*old_name == '\0') |
11675 | { | |
11676 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
11677 | continue; | |
11678 | } | |
11679 | if (!new_name || new_name[1] == '\0') | |
11680 | { | |
11681 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
11682 | old_name); | |
11683 | continue; | |
11684 | } | |
11685 | *new_name = '\0'; | |
11686 | new_name++; | |
e0001a05 | 11687 | |
9456465c BW |
11688 | /* Check for invalid section renaming. */ |
11689 | for (r = section_rename; r != NULL; r = r->next) | |
11690 | { | |
11691 | if (strcmp (r->old_name, old_name) == 0) | |
11692 | as_bad (_("section %s renamed multiple times"), old_name); | |
11693 | if (strcmp (r->new_name, new_name) == 0) | |
11694 | as_bad (_("multiple sections remapped to output section %s"), | |
11695 | new_name); | |
11696 | } | |
e0001a05 | 11697 | |
9456465c BW |
11698 | /* Now add it. */ |
11699 | r = (struct rename_section_struct *) | |
11700 | xmalloc (sizeof (struct rename_section_struct)); | |
11701 | r->old_name = xstrdup (old_name); | |
11702 | r->new_name = xstrdup (new_name); | |
11703 | r->next = section_rename; | |
11704 | section_rename = r; | |
e0001a05 | 11705 | } |
e0001a05 NC |
11706 | } |
11707 | ||
11708 | ||
9456465c BW |
11709 | char * |
11710 | xtensa_section_rename (char *name) | |
e0001a05 NC |
11711 | { |
11712 | struct rename_section_struct *r = section_rename; | |
11713 | ||
11714 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
11715 | { |
11716 | if (strcmp (r->old_name, name) == 0) | |
11717 | return r->new_name; | |
11718 | } | |
e0001a05 NC |
11719 | |
11720 | return name; | |
11721 | } |