projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gas/
[deliverable/binutils-gdb.git] / gas / config / tc-xtensa.c
CommitLineData
e0001a05 1/* tc-xtensa.c -- Assemble Xtensa instructions.
43cd72b9 2 Copyright 2003, 2004 Free Software Foundation, Inc.
e0001a05
NC		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
43cd72b9 18 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
e0001a05
NC		 19 MA 02111-1307, USA. */
20
21#include <string.h>
43cd72b9 22#include <limits.h>
e0001a05
NC		 23#include "as.h"
24#include "sb.h"
25#include "safe-ctype.h"
26#include "tc-xtensa.h"
27#include "frags.h"
28#include "subsegs.h"
29#include "xtensa-relax.h"
30#include "xtensa-istack.h"
cda2eb9e 31#include "dwarf2dbg.h"
e0001a05
NC		 32#include "struc-symbol.h"
33#include "xtensa-config.h"
34
35#ifndef uint32
36#define uint32 unsigned int
37#endif
38#ifndef int32
39#define int32 signed int
40#endif
41
42/* Notes:
43
e0001a05
NC		 44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
47
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
58
59
60/* Define characters with special meanings to GAS. */
61const char comment_chars[] = "#";
62const char line_comment_chars[] = "#";
63const char line_separator_chars[] = ";";
64const char EXP_CHARS[] = "eE";
65const char FLT_CHARS[] = "rRsSfFdDxXpP";
66
67
43cd72b9
BW		 68/* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
e0001a05 70
e0001a05 71bfd_boolean density_supported = XCHAL_HAVE_DENSITY;
43cd72b9
BW		 72bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
73
74/* Maximum width we would pad an unreachable frag to get alignment. */
75#define UNREACHABLE_MAX_WIDTH 8
e0001a05 76
43cd72b9
BW		 77static vliw_insn cur_vinsn;
78
79size_t xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
80
81static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
82
83/* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
85 back end. */
86static bfd_boolean past_xtensa_end = FALSE;
e0001a05
NC		 87
88/* Flags for properties of the last instruction in a segment. */
89#define FLAG_IS_A0_WRITER 0x1
90#define FLAG_IS_BAD_LOOPEND 0x2
91
92
93/* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
97
98#define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
43cd72b9 99#define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
e0001a05
NC		 100#define FINI_SECTION_NAME xtensa_section_rename (".fini")
101#define INIT_SECTION_NAME xtensa_section_rename (".init")
102#define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103#define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
104
105
43cd72b9 106/* This type is used for the directive_stack to keep track of the
e0001a05
NC		 107 state of the literal collection pools. */
108
109typedef struct lit_state_struct
110{
111 const char *lit_seg_name;
43cd72b9 112 const char *lit4_seg_name;
e0001a05
NC		 113 const char *init_lit_seg_name;
114 const char *fini_lit_seg_name;
115 segT lit_seg;
43cd72b9 116 segT lit4_seg;
e0001a05
NC		 117 segT init_lit_seg;
118 segT fini_lit_seg;
119} lit_state;
120
121static lit_state default_lit_sections;
122
123
124/* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
127
128typedef struct seg_list_struct
129{
130 struct seg_list_struct *next;
131 segT seg;
132} seg_list;
133
134static seg_list literal_head_h;
135static seg_list *literal_head = &literal_head_h;
136static seg_list init_literal_head_h;
137static seg_list *init_literal_head = &init_literal_head_h;
138static seg_list fini_literal_head_h;
139static seg_list *fini_literal_head = &fini_literal_head_h;
140
141
82e7541d
BW		 142/* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
147
148typedef struct sym_list_struct
149{
150 struct sym_list_struct *next;
151 symbolS *sym;
152} sym_list;
153
154static sym_list *insn_labels = NULL;
155static sym_list *free_insn_labels = NULL;
156static sym_list *saved_insn_labels = NULL;
157
158static sym_list *literal_syms;
159
160
43cd72b9
BW		 161/* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163int prefer_const16 = 0;
164int prefer_l32r = 0;
165
e0001a05
NC		 166/* Global flag to indicate when we are emitting literals. */
167int generating_literals = 0;
168
43cd72b9
BW		 169/* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
171
172/* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
181
182#define XTENSA_PROP_LITERAL 0x00000001
183#define XTENSA_PROP_INSN 0x00000002
184#define XTENSA_PROP_DATA 0x00000004
185#define XTENSA_PROP_UNREACHABLE 0x00000008
186/* Instruction only properties at beginning of code. */
187#define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188#define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189/* Instruction only properties about code. */
190#define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191#define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192#define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
193
194/* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 Common usage is
200
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
206*/
207#define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
208
209/* No branch target alignment. */
210#define XTENSA_PROP_BT_ALIGN_NONE 0x0
211/* Low priority branch target alignment. */
212#define XTENSA_PROP_BT_ALIGN_LOW 0x1
213/* High priority branch target alignment. */
214#define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215/* Required branch target alignment. */
216#define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
217
218#define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220#define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223
224
225/* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
235
236#define XTENSA_PROP_ALIGN 0x00000800
237
238#define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
239
240#define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242#define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
245
246#define XTENSA_PROP_INSN_ABSLIT 0x00020000
247
248
249/* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
254
255typedef struct frag_flags_struct frag_flags;
256
257struct frag_flags_struct
258{
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
262
263 unsigned is_literal : 1;
264 unsigned is_insn : 1;
265 unsigned is_data : 1;
266 unsigned is_unreachable : 1;
267
268 struct
269 {
270 unsigned is_loop_target : 1;
271 unsigned is_branch_target : 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority : 2;
273
274 unsigned is_no_density : 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform : 1;
278
279 unsigned is_no_reorder : 1;
280
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit : 1;
283 } insn;
284 unsigned is_align : 1;
285 unsigned alignment : 5;
286};
287
288
289/* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291struct xtensa_block_info_struct
292{
293 segT sec;
294 bfd_vma offset;
295 size_t size;
296 frag_flags flags;
297 struct xtensa_block_info_struct *next;
298};
299
e0001a05
NC		 300
301/* Structure for saving the current state before emitting literals. */
302typedef struct emit_state_struct
303{
304 const char *name;
305 segT now_seg;
306 subsegT now_subseg;
307 int generating_literals;
308} emit_state;
309
310
43cd72b9
BW		 311/* Opcode placement information */
312
313typedef unsigned long long bitfield;
314#define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315#define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316#define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
317
318#define MAX_FORMATS 32
319
320typedef struct op_placement_info_struct
321{
322 int num_formats;
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
328 format. */
329 int issuef;
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
332 and their sizes: */
333 xtensa_format single;
334 xtensa_format narrowest;
335 xtensa_format widest;
336 char narrowest_size;
337 char widest_size;
338 char single_size;
339
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
342 bitfield formats;
343
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots[MAX_FORMATS];
347
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format[MAX_FORMATS];
351
352} op_placement_info, *op_placement_info_table;
353
354op_placement_info_table op_placement_table;
355
356
357/* Extra expression types. */
358
359#define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360#define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361#define O_lo16 O_md3 /* use low 16 bits of symbolic value */
362
363
e0001a05
NC		 364/* Directives. */
365
366typedef enum
367{
368 directive_none = 0,
369 directive_literal,
370 directive_density,
43cd72b9 371 directive_transform,
e0001a05
NC		 372 directive_freeregs,
373 directive_longcalls,
43cd72b9
BW		 374 directive_literal_prefix,
375 directive_schedule,
376 directive_absolute_literals,
377 directive_last_directive
e0001a05
NC		 378} directiveE;
379
380typedef struct
381{
382 const char *name;
383 bfd_boolean can_be_negated;
384} directive_infoS;
385
386const directive_infoS directive_info[] =
387{
43cd72b9
BW		 388 { "none", FALSE },
389 { "literal", FALSE },
390 { "density", TRUE },
391 { "transform", TRUE },
392 { "freeregs", FALSE },
393 { "longcalls", TRUE },
394 { "literal_prefix", FALSE },
395 { "schedule", TRUE },
396 { "absolute-literals", TRUE }
e0001a05
NC		 397};
398
399bfd_boolean directive_state[] =
400{
401 FALSE, /* none */
402 FALSE, /* literal */
43cd72b9 403#if !XCHAL_HAVE_DENSITY
e0001a05
NC		 404 FALSE, /* density */
405#else
406 TRUE, /* density */
407#endif
43cd72b9 408 TRUE, /* transform */
e0001a05
NC		 409 FALSE, /* freeregs */
410 FALSE, /* longcalls */
43cd72b9
BW		 411 FALSE, /* literal_prefix */
412 TRUE, /* schedule */
413#if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE /* absolute_literals */
415#else
416 FALSE /* absolute_literals */
417#endif
e0001a05
NC		 418};
419
e0001a05
NC		 420
421/* Directive functions. */
422
7fa3d080
BW		 423static void xtensa_begin_directive (int);
424static void xtensa_end_directive (int);
425static void xtensa_dwarf2_directive_loc (int);
426static void xtensa_literal_prefix (char const *, int);
427static void xtensa_literal_position (int);
428static void xtensa_literal_pseudo (int);
429static void xtensa_frequency_pseudo (int);
430static void xtensa_elf_cons (int);
e0001a05 431
7fa3d080 432/* Parsing and Idiom Translation. */
e0001a05 433
7fa3d080 434static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *);
e0001a05 435
e0001a05
NC		 436/* Various Other Internal Functions. */
437
7fa3d080
BW		 438static void xtensa_mark_literal_pool_location (void);
439static addressT get_expanded_loop_offset (xtensa_opcode);
440static fragS *get_literal_pool_location (segT);
441static void set_literal_pool_location (segT, fragS *);
442static void xtensa_set_frag_assembly_state (fragS *);
443static void finish_vinsn (vliw_insn *);
444static bfd_boolean emit_single_op (TInsn *);
e0001a05
NC		 445
446/* Alignment Functions. */
447
7fa3d080
BW		 448static size_t get_text_align_power (int);
449static addressT get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean);
e0001a05
NC		 450
451/* Helpers for xtensa_relax_frag(). */
452
7fa3d080 453static long relax_frag_add_nop (fragS *);
e0001a05 454
b08b5071 455/* Accessors for additional per-subsegment information. */
e0001a05 456
7fa3d080
BW		 457static unsigned get_last_insn_flags (segT, subsegT);
458static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean);
b08b5071
BW		 459static float get_subseg_total_freq (segT, subsegT);
460static float get_subseg_target_freq (segT, subsegT);
461static void set_subseg_freq (segT, subsegT, float, float);
e0001a05
NC		 462
463/* Segment list functions. */
464
7fa3d080
BW		 465static void xtensa_move_literals (void);
466static void xtensa_reorder_segments (void);
467static void xtensa_switch_to_literal_fragment (emit_state *);
468static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
469static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
470static void xtensa_restore_emit_state (emit_state *);
e0001a05 471static void cache_literal_section
7fa3d080 472 (seg_list *, const char *, segT *, bfd_boolean);
e0001a05 473
e0001a05 474/* Import from elf32-xtensa.c in BFD library. */
43cd72b9 475
7fa3d080 476extern char *xtensa_get_property_section_name (asection *, const char *);
e0001a05 477
43cd72b9
BW		 478/* op_placement_info functions. */
479
7fa3d080
BW		 480static void init_op_placement_info_table (void);
481extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
482static int xg_get_single_size (xtensa_opcode);
483static xtensa_format xg_get_single_format (xtensa_opcode);
43cd72b9 484
e0001a05 485/* TInsn and IStack functions. */
43cd72b9 486
7fa3d080
BW		 487static bfd_boolean tinsn_has_symbolic_operands (const TInsn *);
488static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *);
489static bfd_boolean tinsn_has_complex_operands (const TInsn *);
490static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
491static bfd_boolean tinsn_check_arguments (const TInsn *);
492static void tinsn_from_chars (TInsn *, char *, int);
493static void tinsn_immed_from_frag (TInsn *, fragS *, int);
494static int get_num_stack_text_bytes (IStack *);
495static int get_num_stack_literal_bytes (IStack *);
e0001a05 496
43cd72b9
BW		 497/* vliw_insn functions. */
498
7fa3d080
BW		 499static void xg_init_vinsn (vliw_insn *);
500static void xg_clear_vinsn (vliw_insn *);
501static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *);
502static void xg_free_vinsn (vliw_insn *);
43cd72b9 503static bfd_boolean vinsn_to_insnbuf
7fa3d080
BW		 504 (vliw_insn *, char *, fragS *, bfd_boolean);
505static void vinsn_from_chars (vliw_insn *, char *);
43cd72b9 506
e0001a05 507/* Expression Utilities. */
43cd72b9 508
7fa3d080
BW		 509bfd_boolean expr_is_const (const expressionS *);
510offsetT get_expr_const (const expressionS *);
511void set_expr_const (expressionS *, offsetT);
512bfd_boolean expr_is_register (const expressionS *);
513offsetT get_expr_register (const expressionS *);
514void set_expr_symbol_offset (expressionS *, symbolS *, offsetT);
43cd72b9 515static void set_expr_symbol_offset_diff
7fa3d080
BW		 516 (expressionS *, symbolS *, symbolS *, offsetT);
517bfd_boolean expr_is_equal (expressionS *, expressionS *);
518static void copy_expr (expressionS *, const expressionS *);
e0001a05
NC		 519
520#ifdef XTENSA_SECTION_RENAME
7fa3d080
BW		 521static void build_section_rename (const char *);
522static void add_section_rename (char *, char *);
e0001a05
NC		 523#endif
524
e0001a05
NC		 525
526/* ISA imported from bfd. */
527extern xtensa_isa xtensa_default_isa;
528
529extern int target_big_endian;
530
531static xtensa_opcode xtensa_addi_opcode;
532static xtensa_opcode xtensa_addmi_opcode;
533static xtensa_opcode xtensa_call0_opcode;
534static xtensa_opcode xtensa_call4_opcode;
535static xtensa_opcode xtensa_call8_opcode;
536static xtensa_opcode xtensa_call12_opcode;
537static xtensa_opcode xtensa_callx0_opcode;
538static xtensa_opcode xtensa_callx4_opcode;
539static xtensa_opcode xtensa_callx8_opcode;
540static xtensa_opcode xtensa_callx12_opcode;
43cd72b9 541static xtensa_opcode xtensa_const16_opcode;
e0001a05 542static xtensa_opcode xtensa_entry_opcode;
43cd72b9
BW		 543static xtensa_opcode xtensa_movi_opcode;
544static xtensa_opcode xtensa_movi_n_opcode;
e0001a05 545static xtensa_opcode xtensa_isync_opcode;
e0001a05 546static xtensa_opcode xtensa_jx_opcode;
43cd72b9 547static xtensa_opcode xtensa_l32r_opcode;
e0001a05
NC		 548static xtensa_opcode xtensa_loop_opcode;
549static xtensa_opcode xtensa_loopnez_opcode;
550static xtensa_opcode xtensa_loopgtz_opcode;
43cd72b9 551static xtensa_opcode xtensa_nop_opcode;
e0001a05
NC		 552static xtensa_opcode xtensa_nop_n_opcode;
553static xtensa_opcode xtensa_or_opcode;
554static xtensa_opcode xtensa_ret_opcode;
555static xtensa_opcode xtensa_ret_n_opcode;
556static xtensa_opcode xtensa_retw_opcode;
557static xtensa_opcode xtensa_retw_n_opcode;
43cd72b9 558static xtensa_opcode xtensa_rsr_lcount_opcode;
e0001a05
NC		 559static xtensa_opcode xtensa_waiti_opcode;
560
561\f
562/* Command-line Options. */
563
564bfd_boolean use_literal_section = TRUE;
565static bfd_boolean align_targets = TRUE;
43cd72b9 566static bfd_boolean warn_unaligned_branch_targets = FALSE;
e0001a05 567static bfd_boolean has_a0_b_retw = FALSE;
43cd72b9
BW		 568static bfd_boolean workaround_a0_b_retw = FALSE;
569static bfd_boolean workaround_b_j_loop_end = FALSE;
570static bfd_boolean workaround_short_loop = FALSE;
e0001a05 571static bfd_boolean maybe_has_short_loop = FALSE;
43cd72b9 572static bfd_boolean workaround_close_loop_end = FALSE;
e0001a05
NC		 573static bfd_boolean maybe_has_close_loop_end = FALSE;
574
43cd72b9
BW		 575/* When workaround_short_loops is TRUE, all loops with early exits must
576 have at least 3 instructions. workaround_all_short_loops is a modifier
577 to the workaround_short_loop flag. In addition to the
578 workaround_short_loop actions, all straightline loopgtz and loopnez
579 must have at least 3 instructions. */
e0001a05 580
43cd72b9 581static bfd_boolean workaround_all_short_loops = FALSE;
e0001a05 582
7fa3d080
BW		 583
584static void
585xtensa_setup_hw_workarounds (int earliest, int latest)
586{
587 if (earliest > latest)
588 as_fatal (_("illegal range of target hardware versions"));
589
590 /* Enable all workarounds for pre-T1050.0 hardware. */
591 if (earliest < 105000 || latest < 105000)
592 {
593 workaround_a0_b_retw |= TRUE;
594 workaround_b_j_loop_end |= TRUE;
595 workaround_short_loop |= TRUE;
596 workaround_close_loop_end |= TRUE;
597 workaround_all_short_loops |= TRUE;
598 }
599}
600
601
e0001a05
NC		 602enum
603{
604 option_density = OPTION_MD_BASE,
605 option_no_density,
606
607 option_relax,
608 option_no_relax,
609
43cd72b9
BW		 610 option_link_relax,
611 option_no_link_relax,
612
e0001a05
NC		 613 option_generics,
614 option_no_generics,
615
43cd72b9
BW		 616 option_transform,
617 option_no_transform,
618
e0001a05
NC		 619 option_text_section_literals,
620 option_no_text_section_literals,
621
43cd72b9
BW		 622 option_absolute_literals,
623 option_no_absolute_literals,
624
e0001a05
NC		 625 option_align_targets,
626 option_no_align_targets,
627
43cd72b9 628 option_warn_unaligned_targets,
e0001a05
NC		 629
630 option_longcalls,
631 option_no_longcalls,
632
633 option_workaround_a0_b_retw,
634 option_no_workaround_a0_b_retw,
635
636 option_workaround_b_j_loop_end,
637 option_no_workaround_b_j_loop_end,
638
639 option_workaround_short_loop,
640 option_no_workaround_short_loop,
641
642 option_workaround_all_short_loops,
643 option_no_workaround_all_short_loops,
644
645 option_workaround_close_loop_end,
646 option_no_workaround_close_loop_end,
647
648 option_no_workarounds,
649
650#ifdef XTENSA_SECTION_RENAME
e0001a05
NC		 651 option_rename_section_name,
652#endif
653
43cd72b9
BW		 654 option_prefer_l32r,
655 option_prefer_const16,
656
657 option_target_hardware
e0001a05
NC		 658};
659
660const char *md_shortopts = "";
661
662struct option md_longopts[] =
663{
43cd72b9
BW		 664 { "density", no_argument, NULL, option_density },
665 { "no-density", no_argument, NULL, option_no_density },
666
667 /* Both "relax" and "generics" are deprecated and treated as equivalent
668 to the "transform" option. */
669 { "relax", no_argument, NULL, option_relax },
670 { "no-relax", no_argument, NULL, option_no_relax },
671 { "generics", no_argument, NULL, option_generics },
672 { "no-generics", no_argument, NULL, option_no_generics },
673
674 { "transform", no_argument, NULL, option_transform },
675 { "no-transform", no_argument, NULL, option_no_transform },
676 { "text-section-literals", no_argument, NULL, option_text_section_literals },
677 { "no-text-section-literals", no_argument, NULL,
678 option_no_text_section_literals },
679 { "absolute-literals", no_argument, NULL, option_absolute_literals },
680 { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals },
e0001a05
NC		 681 /* This option was changed from -align-target to -target-align
682 because it conflicted with the "-al" option. */
43cd72b9 683 { "target-align", no_argument, NULL, option_align_targets },
7fa3d080
BW		 684 { "no-target-align", no_argument, NULL, option_no_align_targets },
685 { "warn-unaligned-targets", no_argument, NULL,
686 option_warn_unaligned_targets },
43cd72b9
BW		 687 { "longcalls", no_argument, NULL, option_longcalls },
688 { "no-longcalls", no_argument, NULL, option_no_longcalls },
689
690 { "no-workaround-a0-b-retw", no_argument, NULL,
691 option_no_workaround_a0_b_retw },
692 { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw },
e0001a05 693
43cd72b9
BW		 694 { "no-workaround-b-j-loop-end", no_argument, NULL,
695 option_no_workaround_b_j_loop_end },
696 { "workaround-b-j-loop-end", no_argument, NULL,
697 option_workaround_b_j_loop_end },
e0001a05 698
43cd72b9
BW		 699 { "no-workaround-short-loops", no_argument, NULL,
700 option_no_workaround_short_loop },
7fa3d080
BW		 701 { "workaround-short-loops", no_argument, NULL,
702 option_workaround_short_loop },
e0001a05 703
43cd72b9
BW		 704 { "no-workaround-all-short-loops", no_argument, NULL,
705 option_no_workaround_all_short_loops },
706 { "workaround-all-short-loop", no_argument, NULL,
707 option_workaround_all_short_loops },
708
709 { "prefer-l32r", no_argument, NULL, option_prefer_l32r },
710 { "prefer-const16", no_argument, NULL, option_prefer_const16 },
711
712 { "no-workarounds", no_argument, NULL, option_no_workarounds },
713
714 { "no-workaround-close-loop-end", no_argument, NULL,
715 option_no_workaround_close_loop_end },
716 { "workaround-close-loop-end", no_argument, NULL,
717 option_workaround_close_loop_end },
e0001a05
NC		 718
719#ifdef XTENSA_SECTION_RENAME
7fa3d080 720 { "rename-section", required_argument, NULL, option_rename_section_name },
e0001a05
NC		 721#endif /* XTENSA_SECTION_RENAME */
722
43cd72b9
BW		 723 { "link-relax", no_argument, NULL, option_link_relax },
724 { "no-link-relax", no_argument, NULL, option_no_link_relax },
725
726 { "target-hardware", required_argument, NULL, option_target_hardware },
727
728 { NULL, no_argument, NULL, 0 }
e0001a05
NC		 729};
730
731size_t md_longopts_size = sizeof md_longopts;
732
733
734int
7fa3d080 735md_parse_option (int c, char *arg)
e0001a05
NC		 736{
737 switch (c)
738 {
739 case option_density:
43cd72b9 740 as_warn (_("--density option is ignored"));
e0001a05
NC		 741 return 1;
742 case option_no_density:
43cd72b9 743 as_warn (_("--no-density option is ignored"));
e0001a05 744 return 1;
43cd72b9
BW		 745 case option_link_relax:
746 linkrelax = 1;
e0001a05 747 return 1;
43cd72b9
BW		 748 case option_no_link_relax:
749 linkrelax = 0;
e0001a05 750 return 1;
43cd72b9
BW		 751 case option_generics:
752 as_warn (_("--generics is deprecated; use --transform instead"));
753 return md_parse_option (option_transform, arg);
754 case option_no_generics:
755 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
756 return md_parse_option (option_no_transform, arg);
757 case option_relax:
758 as_warn (_("--relax is deprecated; use --transform instead"));
759 return md_parse_option (option_transform, arg);
760 case option_no_relax:
761 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
762 return md_parse_option (option_no_transform, arg);
e0001a05
NC		 763 case option_longcalls:
764 directive_state[directive_longcalls] = TRUE;
765 return 1;
766 case option_no_longcalls:
767 directive_state[directive_longcalls] = FALSE;
768 return 1;
769 case option_text_section_literals:
770 use_literal_section = FALSE;
771 return 1;
772 case option_no_text_section_literals:
773 use_literal_section = TRUE;
774 return 1;
43cd72b9
BW		 775 case option_absolute_literals:
776 if (!absolute_literals_supported)
777 {
778 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
779 return 0;
780 }
781 directive_state[directive_absolute_literals] = TRUE;
782 return 1;
783 case option_no_absolute_literals:
784 directive_state[directive_absolute_literals] = FALSE;
785 return 1;
786
e0001a05
NC		 787 case option_workaround_a0_b_retw:
788 workaround_a0_b_retw = TRUE;
e0001a05
NC		 789 return 1;
790 case option_no_workaround_a0_b_retw:
791 workaround_a0_b_retw = FALSE;
e0001a05
NC		 792 return 1;
793 case option_workaround_b_j_loop_end:
794 workaround_b_j_loop_end = TRUE;
e0001a05
NC		 795 return 1;
796 case option_no_workaround_b_j_loop_end:
797 workaround_b_j_loop_end = FALSE;
e0001a05
NC		 798 return 1;
799
800 case option_workaround_short_loop:
801 workaround_short_loop = TRUE;
e0001a05
NC		 802 return 1;
803 case option_no_workaround_short_loop:
804 workaround_short_loop = FALSE;
e0001a05
NC		 805 return 1;
806
807 case option_workaround_all_short_loops:
808 workaround_all_short_loops = TRUE;
e0001a05
NC		 809 return 1;
810 case option_no_workaround_all_short_loops:
811 workaround_all_short_loops = FALSE;
e0001a05
NC		 812 return 1;
813
814 case option_workaround_close_loop_end:
815 workaround_close_loop_end = TRUE;
e0001a05
NC		 816 return 1;
817 case option_no_workaround_close_loop_end:
818 workaround_close_loop_end = FALSE;
e0001a05
NC		 819 return 1;
820
821 case option_no_workarounds:
822 workaround_a0_b_retw = FALSE;
e0001a05 823 workaround_b_j_loop_end = FALSE;
e0001a05 824 workaround_short_loop = FALSE;
e0001a05 825 workaround_all_short_loops = FALSE;
e0001a05 826 workaround_close_loop_end = FALSE;
e0001a05 827 return 1;
43cd72b9 828
e0001a05
NC		 829 case option_align_targets:
830 align_targets = TRUE;
831 return 1;
832 case option_no_align_targets:
833 align_targets = FALSE;
834 return 1;
835
43cd72b9
BW		 836 case option_warn_unaligned_targets:
837 warn_unaligned_branch_targets = TRUE;
e0001a05
NC		 838 return 1;
839
840#ifdef XTENSA_SECTION_RENAME
e0001a05
NC		 841 case option_rename_section_name:
842 build_section_rename (arg);
843 return 1;
844#endif /* XTENSA_SECTION_RENAME */
845
846 case 'Q':
847 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
848 should be emitted or not. FIXME: Not implemented. */
849 return 1;
850
43cd72b9
BW		 851 case option_prefer_l32r:
852 if (prefer_const16)
853 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
854 prefer_l32r = 1;
855 return 1;
856
857 case option_prefer_const16:
858 if (prefer_l32r)
859 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
860 prefer_const16 = 1;
861 return 1;
862
863 case option_target_hardware:
864 {
865 int earliest, latest = 0;
866 if (*arg == 0 || *arg == '-')
867 as_fatal (_("invalid target hardware version"));
868
869 earliest = strtol (arg, &arg, 0);
870
871 if (*arg == 0)
872 latest = earliest;
873 else if (*arg == '-')
874 {
875 if (*++arg == 0)
876 as_fatal (_("invalid target hardware version"));
877 latest = strtol (arg, &arg, 0);
878 }
879 if (*arg != 0)
880 as_fatal (_("invalid target hardware version"));
881
882 xtensa_setup_hw_workarounds (earliest, latest);
883 return 1;
884 }
885
886 case option_transform:
887 /* This option has no affect other than to use the defaults,
888 which are already set. */
889 return 1;
890
891 case option_no_transform:
892 /* This option turns off all transformations of any kind.
893 However, because we want to preserve the state of other
894 directives, we only change its own field. Thus, before
895 you perform any transformation, always check if transform
896 is available. If you use the functions we provide for this
897 purpose, you will be ok. */
898 directive_state[directive_transform] = FALSE;
899 return 1;
900
e0001a05
NC		 901 default:
902 return 0;
903 }
904}
905
906
907void
7fa3d080 908md_show_usage (FILE *stream)
e0001a05 909{
43cd72b9
BW		 910 fputs ("\n\
911Xtensa options:\n\
912--[no-]text-section-literals\n\
913 [Do not] put literals in the text section\n\
914--[no-]absolute-literals\n\
915 [Do not] default to use non-PC-relative literals\n\
916--[no-]target-align [Do not] try to align branch targets\n\
917--[no-]longcalls [Do not] emit 32-bit call sequences\n\
918--[no-]transform [Do not] transform instructions\n"
e0001a05 919#ifdef XTENSA_SECTION_RENAME
43cd72b9
BW		 920"--rename-section old=new(:old1=new1)*\n\
921 Rename section 'old' to 'new'\n"
922#endif /* XTENSA_SECTION_RENAME */
e0001a05
NC		 923 , stream);
924}
925
7fa3d080
BW		 926\f
927/* Functions related to the list of current label symbols. */
43cd72b9
BW		 928
929static void
7fa3d080 930xtensa_add_insn_label (symbolS *sym)
43cd72b9 931{
7fa3d080 932 sym_list *l;
43cd72b9 933
7fa3d080
BW		 934 if (!free_insn_labels)
935 l = (sym_list *) xmalloc (sizeof (sym_list));
936 else
43cd72b9 937 {
7fa3d080
BW		 938 l = free_insn_labels;
939 free_insn_labels = l->next;
940 }
941
942 l->sym = sym;
943 l->next = insn_labels;
944 insn_labels = l;
945}
946
947
948static void
949xtensa_clear_insn_labels (void)
950{
951 sym_list **pl;
952
953 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
954 ;
955 *pl = insn_labels;
956 insn_labels = NULL;
957}
958
959
960/* The "loops_ok" argument is provided to allow ignoring labels that
961 define loop ends. This fixes a bug where the NOPs to align a
962 loop opcode were included in a previous zero-cost loop:
963
964 loop a0, loopend
965 <loop1 body>
966 loopend:
967
968 loop a2, loopend2
969 <loop2 body>
970
971 would become:
972
973 loop a0, loopend
974 <loop1 body>
975 nop.n <===== bad!
976 loopend:
977
978 loop a2, loopend2
979 <loop2 body>
980
981 This argument is used to prevent moving the NOP to before the
982 loop-end label, which is what you want in this special case. */
983
984static void
985xtensa_move_labels (fragS *new_frag, valueT new_offset, bfd_boolean loops_ok)
986{
987 sym_list *lit;
988
989 for (lit = insn_labels; lit; lit = lit->next)
990 {
991 symbolS *lit_sym = lit->sym;
992 if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target)
993 {
994 S_SET_VALUE (lit_sym, new_offset);
995 symbol_set_frag (lit_sym, new_frag);
996 }
43cd72b9
BW		 997 }
998}
999
e0001a05
NC		 1000\f
1001/* Directive data and functions. */
1002
1003typedef struct state_stackS_struct
1004{
1005 directiveE directive;
1006 bfd_boolean negated;
1007 bfd_boolean old_state;
1008 const char *file;
1009 unsigned int line;
1010 const void *datum;
1011 struct state_stackS_struct *prev;
1012} state_stackS;
1013
1014state_stackS *directive_state_stack;
1015
1016const pseudo_typeS md_pseudo_table[] =
1017{
43cd72b9
BW		 1018 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
1019 { "literal_position", xtensa_literal_position, 0 },
1020 { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */
1021 { "long", xtensa_elf_cons, 4 },
1022 { "word", xtensa_elf_cons, 4 },
1023 { "short", xtensa_elf_cons, 2 },
1024 { "begin", xtensa_begin_directive, 0 },
1025 { "end", xtensa_end_directive, 0 },
1026 { "loc", xtensa_dwarf2_directive_loc, 0 },
1027 { "literal", xtensa_literal_pseudo, 0 },
1028 { "frequency", xtensa_frequency_pseudo, 0 },
1029 { NULL, 0, 0 },
e0001a05
NC		 1030};
1031
1032
7fa3d080
BW		 1033static bfd_boolean
1034use_transform (void)
e0001a05 1035{
43cd72b9
BW		 1036 /* After md_end, you should be checking frag by frag, rather
1037 than state directives. */
1038 assert (!past_xtensa_end);
1039 return directive_state[directive_transform];
e0001a05
NC		 1040}
1041
1042
7fa3d080
BW		 1043static bfd_boolean
1044use_longcalls (void)
e0001a05 1045{
43cd72b9
BW		 1046 /* After md_end, you should be checking frag by frag, rather
1047 than state directives. */
1048 assert (!past_xtensa_end);
1049 return directive_state[directive_longcalls] && use_transform ();
e0001a05
NC		 1050}
1051
1052
7fa3d080
BW		 1053static bfd_boolean
1054do_align_targets (void)
e0001a05 1055{
43cd72b9
BW		 1056 /* After md_end, you should be checking frag by frag, rather
1057 than state directives. */
1058 assert (!past_xtensa_end);
1059 return align_targets && use_transform ();
e0001a05
NC		 1060}
1061
1062
1063static void
7fa3d080 1064directive_push (directiveE directive, bfd_boolean negated, const void *datum)
e0001a05
NC		 1065{
1066 char *file;
1067 unsigned int line;
1068 state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS));
1069
1070 as_where (&file, &line);
1071
1072 stack->directive = directive;
1073 stack->negated = negated;
1074 stack->old_state = directive_state[directive];
1075 stack->file = file;
1076 stack->line = line;
1077 stack->datum = datum;
1078 stack->prev = directive_state_stack;
1079 directive_state_stack = stack;
1080
1081 directive_state[directive] = !negated;
1082}
1083
7fa3d080 1084
e0001a05 1085static void
7fa3d080
BW		 1086directive_pop (directiveE *directive,
1087 bfd_boolean *negated,
1088 const char **file,
1089 unsigned int *line,
1090 const void **datum)
e0001a05
NC		 1091{
1092 state_stackS *top = directive_state_stack;
1093
1094 if (!directive_state_stack)
1095 {
1096 as_bad (_("unmatched end directive"));
1097 *directive = directive_none;
1098 return;
1099 }
1100
1101 directive_state[directive_state_stack->directive] = top->old_state;
1102 *directive = top->directive;
1103 *negated = top->negated;
1104 *file = top->file;
1105 *line = top->line;
1106 *datum = top->datum;
1107 directive_state_stack = top->prev;
1108 free (top);
1109}
1110
1111
1112static void
7fa3d080 1113directive_balance (void)
e0001a05
NC		 1114{
1115 while (directive_state_stack)
1116 {
1117 directiveE directive;
1118 bfd_boolean negated;
1119 const char *file;
1120 unsigned int line;
1121 const void *datum;
1122
1123 directive_pop (&directive, &negated, &file, &line, &datum);
1124 as_warn_where ((char *) file, line,
1125 _(".begin directive with no matching .end directive"));
1126 }
1127}
1128
1129
1130static bfd_boolean
7fa3d080 1131inside_directive (directiveE dir)
e0001a05
NC		 1132{
1133 state_stackS *top = directive_state_stack;
1134
1135 while (top && top->directive != dir)
1136 top = top->prev;
1137
1138 return (top != NULL);
1139}
1140
1141
1142static void
7fa3d080 1143get_directive (directiveE *directive, bfd_boolean *negated)
e0001a05
NC		 1144{
1145 int len;
1146 unsigned i;
43cd72b9 1147 char *directive_string;
e0001a05
NC		 1148
1149 if (strncmp (input_line_pointer, "no-", 3) != 0)
1150 *negated = FALSE;
1151 else
1152 {
1153 *negated = TRUE;
1154 input_line_pointer += 3;
1155 }
1156
1157 len = strspn (input_line_pointer,
43cd72b9
BW		 1158 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1159
1160 /* This code is a hack to make .begin [no-][generics|relax] exactly
1161 equivalent to .begin [no-]transform. We should remove it when
1162 we stop accepting those options. */
1163
1164 if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0)
1165 {
1166 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1167 directive_string = "transform";
1168 }
1169 else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0)
1170 {
1171 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1172 directive_string = "transform";
1173 }
1174 else
1175 directive_string = input_line_pointer;
e0001a05
NC		 1176
1177 for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i)
1178 {
43cd72b9 1179 if (strncmp (directive_string, directive_info[i].name, len) == 0)
e0001a05
NC		 1180 {
1181 input_line_pointer += len;
1182 *directive = (directiveE) i;
1183 if (*negated && !directive_info[i].can_be_negated)
43cd72b9 1184 as_bad (_("directive %s cannot be negated"),
e0001a05
NC		 1185 directive_info[i].name);
1186 return;
1187 }
1188 }
1189
1190 as_bad (_("unknown directive"));
1191 *directive = (directiveE) XTENSA_UNDEFINED;
1192}
1193
1194
1195static void
7fa3d080 1196xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
e0001a05
NC		 1197{
1198 directiveE directive;
1199 bfd_boolean negated;
1200 emit_state *state;
1201 int len;
1202 lit_state *ls;
1203
1204 get_directive (&directive, &negated);
1205 if (directive == (directiveE) XTENSA_UNDEFINED)
1206 {
1207 discard_rest_of_line ();
1208 return;
1209 }
1210
43cd72b9
BW		 1211 if (cur_vinsn.inside_bundle)
1212 as_bad (_("directives are not valid inside bundles"));
1213
e0001a05
NC		 1214 switch (directive)
1215 {
1216 case directive_literal:
82e7541d
BW		 1217 if (!inside_directive (directive_literal))
1218 {
1219 /* Previous labels go with whatever follows this directive, not with
1220 the literal, so save them now. */
1221 saved_insn_labels = insn_labels;
1222 insn_labels = NULL;
1223 }
43cd72b9 1224 as_warn (_(".begin literal is deprecated; use .literal instead"));
e0001a05
NC		 1225 state = (emit_state *) xmalloc (sizeof (emit_state));
1226 xtensa_switch_to_literal_fragment (state);
1227 directive_push (directive_literal, negated, state);
1228 break;
1229
1230 case directive_literal_prefix:
43cd72b9
BW		 1231 /* Have to flush pending output because a movi relaxed to an l32r
1232 might produce a literal. */
1233 md_flush_pending_output ();
e0001a05
NC		 1234 /* Check to see if the current fragment is a literal
1235 fragment. If it is, then this operation is not allowed. */
43cd72b9 1236 if (generating_literals)
e0001a05
NC		 1237 {
1238 as_bad (_("cannot set literal_prefix inside literal fragment"));
1239 return;
1240 }
1241
1242 /* Allocate the literal state for this section and push
1243 onto the directive stack. */
1244 ls = xmalloc (sizeof (lit_state));
1245 assert (ls);
1246
1247 *ls = default_lit_sections;
1248
1249 directive_push (directive_literal_prefix, negated, ls);
1250
1251 /* Parse the new prefix from the input_line_pointer. */
1252 SKIP_WHITESPACE ();
1253 len = strspn (input_line_pointer,
1254 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1255 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1256
1257 /* Process the new prefix. */
1258 xtensa_literal_prefix (input_line_pointer, len);
1259
1260 /* Skip the name in the input line. */
1261 input_line_pointer += len;
1262 break;
1263
1264 case directive_freeregs:
1265 /* This information is currently unused, but we'll accept the statement
1266 and just discard the rest of the line. This won't check the syntax,
1267 but it will accept every correct freeregs directive. */
1268 input_line_pointer += strcspn (input_line_pointer, "\n");
1269 directive_push (directive_freeregs, negated, 0);
1270 break;
1271
43cd72b9
BW		 1272 case directive_schedule:
1273 md_flush_pending_output ();
1274 frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
1275 frag_now->fr_symbol, frag_now->fr_offset, NULL);
1276 directive_push (directive_schedule, negated, 0);
1277 xtensa_set_frag_assembly_state (frag_now);
1278 break;
1279
e0001a05 1280 case directive_density:
43cd72b9
BW		 1281 as_warn (_(".begin [no-]density is ignored"));
1282 break;
1283
1284 case directive_absolute_literals:
1285 md_flush_pending_output ();
1286 if (!absolute_literals_supported && !negated)
e0001a05 1287 {
43cd72b9 1288 as_warn (_("Xtensa absolute literals option not supported; ignored"));
e0001a05
NC		 1289 break;
1290 }
43cd72b9
BW		 1291 xtensa_set_frag_assembly_state (frag_now);
1292 directive_push (directive, negated, 0);
1293 break;
e0001a05
NC		 1294
1295 default:
43cd72b9
BW		 1296 md_flush_pending_output ();
1297 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 1298 directive_push (directive, negated, 0);
1299 break;
1300 }
1301
1302 demand_empty_rest_of_line ();
1303}
1304
1305
1306static void
7fa3d080 1307xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
e0001a05
NC		 1308{
1309 directiveE begin_directive, end_directive;
1310 bfd_boolean begin_negated, end_negated;
1311 const char *file;
1312 unsigned int line;
1313 emit_state *state;
43cd72b9 1314 emit_state **state_ptr;
e0001a05
NC		 1315 lit_state *s;
1316
43cd72b9
BW		 1317 if (cur_vinsn.inside_bundle)
1318 as_bad (_("directives are not valid inside bundles"));
82e7541d 1319
e0001a05 1320 get_directive (&end_directive, &end_negated);
43cd72b9
BW		 1321
1322 md_flush_pending_output ();
1323
1324 switch (end_directive)
e0001a05 1325 {
43cd72b9 1326 case (directiveE) XTENSA_UNDEFINED:
e0001a05
NC		 1327 discard_rest_of_line ();
1328 return;
e0001a05 1329
43cd72b9
BW		 1330 case directive_density:
1331 as_warn (_(".end [no-]density is ignored"));
e0001a05 1332 demand_empty_rest_of_line ();
43cd72b9
BW		 1333 break;
1334
1335 case directive_absolute_literals:
1336 if (!absolute_literals_supported && !end_negated)
1337 {
1338 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1339 demand_empty_rest_of_line ();
1340 return;
1341 }
1342 break;
1343
1344 default:
1345 break;
e0001a05
NC		 1346 }
1347
43cd72b9 1348 state_ptr = &state; /* use state_ptr to avoid type-punning warning */
e0001a05 1349 directive_pop (&begin_directive, &begin_negated, &file, &line,
43cd72b9 1350 (const void **) state_ptr);
e0001a05
NC		 1351
1352 if (begin_directive != directive_none)
1353 {
1354 if (begin_directive != end_directive || begin_negated != end_negated)
1355 {
1356 as_bad (_("does not match begin %s%s at %s:%d"),
1357 begin_negated ? "no-" : "",
1358 directive_info[begin_directive].name, file, line);
1359 }
1360 else
1361 {
1362 switch (end_directive)
1363 {
1364 case directive_literal:
1365 frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL);
1366 xtensa_restore_emit_state (state);
43cd72b9 1367 xtensa_set_frag_assembly_state (frag_now);
e0001a05 1368 free (state);
82e7541d
BW		 1369 if (!inside_directive (directive_literal))
1370 {
1371 /* Restore the list of current labels. */
1372 xtensa_clear_insn_labels ();
1373 insn_labels = saved_insn_labels;
1374 }
e0001a05
NC		 1375 break;
1376
e0001a05
NC		 1377 case directive_literal_prefix:
1378 /* Restore the default collection sections from saved state. */
1379 s = (lit_state *) state;
1380 assert (s);
1381
1382 if (use_literal_section)
1383 default_lit_sections = *s;
1384
1385 /* free the state storage */
1386 free (s);
1387 break;
1388
43cd72b9
BW		 1389 case directive_schedule:
1390 case directive_freeregs:
1391 break;
1392
e0001a05 1393 default:
43cd72b9 1394 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 1395 break;
1396 }
1397 }
1398 }
1399
1400 demand_empty_rest_of_line ();
1401}
1402
1403
43cd72b9
BW		 1404/* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1405
1406static bfd_boolean xtensa_loc_directive_seen = FALSE;
1407
1408static void
7fa3d080 1409xtensa_dwarf2_directive_loc (int x)
43cd72b9
BW		 1410{
1411 xtensa_loc_directive_seen = TRUE;
1412 dwarf2_directive_loc (x);
1413}
1414
1415
1416static void
7fa3d080 1417xtensa_dwarf2_emit_insn (int size, struct dwarf2_line_info *loc)
43cd72b9
BW		 1418{
1419 if (debug_type != DEBUG_DWARF2 && ! xtensa_loc_directive_seen)
1420 return;
1421 xtensa_loc_directive_seen = FALSE;
1422 dwarf2_gen_line_info (frag_now_fix () - size, loc);
1423}
1424
1425
e0001a05
NC		 1426/* Place an aligned literal fragment at the current location. */
1427
1428static void
7fa3d080 1429xtensa_literal_position (int ignore ATTRIBUTE_UNUSED)
e0001a05 1430{
43cd72b9
BW		 1431 md_flush_pending_output ();
1432
e0001a05
NC		 1433 if (inside_directive (directive_literal))
1434 as_warn (_(".literal_position inside literal directive; ignoring"));
43cd72b9 1435 xtensa_mark_literal_pool_location ();
e0001a05
NC		 1436
1437 demand_empty_rest_of_line ();
82e7541d 1438 xtensa_clear_insn_labels ();
e0001a05
NC		 1439}
1440
1441
43cd72b9 1442/* Support .literal label, expr, ... */
e0001a05
NC		 1443
1444static void
7fa3d080 1445xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED)
e0001a05
NC		 1446{
1447 emit_state state;
1745fcba 1448 char *p, *base_name;
e0001a05 1449 char c;
e0001a05
NC		 1450 segT dest_seg;
1451
82e7541d
BW		 1452 if (inside_directive (directive_literal))
1453 {
1454 as_bad (_(".literal not allowed inside .begin literal region"));
1455 ignore_rest_of_line ();
1456 return;
1457 }
1458
43cd72b9
BW		 1459 md_flush_pending_output ();
1460
82e7541d
BW		 1461 /* Previous labels go with whatever follows this directive, not with
1462 the literal, so save them now. */
1463 saved_insn_labels = insn_labels;
1464 insn_labels = NULL;
1465
e0001a05
NC		 1466 /* If we are using text-section literals, then this is the right value... */
1467 dest_seg = now_seg;
1468
1469 base_name = input_line_pointer;
1470
1471 xtensa_switch_to_literal_fragment (&state);
1472
43cd72b9 1473 /* ...but if we aren't using text-section-literals, then we
e0001a05 1474 need to put them in the section we just switched to. */
43cd72b9 1475 if (use_literal_section || directive_state[directive_absolute_literals])
e0001a05
NC		 1476 dest_seg = now_seg;
1477
43cd72b9
BW		 1478 /* All literals are aligned to four-byte boundaries. */
1479 frag_align (2, 0, 0);
1480 record_alignment (now_seg, 2);
e0001a05
NC		 1481
1482 c = get_symbol_end ();
1483 /* Just after name is now '\0'. */
1484 p = input_line_pointer;
1485 *p = c;
1486 SKIP_WHITESPACE ();
1487
1488 if (*input_line_pointer != ',' && *input_line_pointer != ':')
1489 {
1490 as_bad (_("expected comma or colon after symbol name; "
1491 "rest of line ignored"));
1492 ignore_rest_of_line ();
1493 xtensa_restore_emit_state (&state);
1494 return;
1495 }
1496 *p = 0;
1497
e0001a05 1498 colon (base_name);
e0001a05 1499
e0001a05 1500 *p = c;
43cd72b9 1501 input_line_pointer++; /* skip ',' or ':' */
e0001a05 1502
43cd72b9 1503 xtensa_elf_cons (4);
e0001a05
NC		 1504
1505 xtensa_restore_emit_state (&state);
82e7541d
BW		 1506
1507 /* Restore the list of current labels. */
1508 xtensa_clear_insn_labels ();
1509 insn_labels = saved_insn_labels;
e0001a05
NC		 1510}
1511
1512
1513static void
7fa3d080 1514xtensa_literal_prefix (char const *start, int len)
e0001a05 1515{
43cd72b9
BW		 1516 char *name, *linkonce_suffix;
1517 char *newname, *newname4;
1518 size_t linkonce_len;
e0001a05
NC		 1519
1520 /* Get a null-terminated copy of the name. */
1521 name = xmalloc (len + 1);
1522 assert (name);
1523
1524 strncpy (name, start, len);
1525 name[len] = 0;
1526
1527 /* Allocate the sections (interesting note: the memory pointing to
1528 the name is actually used for the name by the new section). */
43cd72b9 1529
e0001a05 1530 newname = xmalloc (len + strlen (".literal") + 1);
43cd72b9 1531 newname4 = xmalloc (len + strlen (".lit4") + 1);
e0001a05 1532
43cd72b9
BW		 1533 linkonce_len = sizeof (".gnu.linkonce.") - 1;
1534 if (strncmp (name, ".gnu.linkonce.", linkonce_len) == 0
1535 && (linkonce_suffix = strchr (name + linkonce_len, '.')) != 0)
1536 {
1537 strcpy (newname, ".gnu.linkonce.literal");
1538 strcpy (newname4, ".gnu.linkonce.lit4");
e0001a05 1539
43cd72b9
BW		 1540 strcat (newname, linkonce_suffix);
1541 strcat (newname4, linkonce_suffix);
1542 }
1543 else
1544 {
1545 int suffix_pos = len;
1546
1547 /* If the section name ends with ".text", then replace that suffix
1548 instead of appending an additional suffix. */
1549 if (len >= 5 && strcmp (name + len - 5, ".text") == 0)
1550 suffix_pos -= 5;
1551
1552 strcpy (newname, name);
1553 strcpy (newname4, name);
1554
1555 strcpy (newname + suffix_pos, ".literal");
1556 strcpy (newname4 + suffix_pos, ".lit4");
1557 }
1558
b08b5071 1559 /* Note that cache_literal_section does not create a segment if
43cd72b9
BW		 1560 it already exists. */
1561 default_lit_sections.lit_seg = NULL;
1562 default_lit_sections.lit4_seg = NULL;
1563
1564 /* Canonicalizing section names allows renaming literal
e0001a05 1565 sections to occur correctly. */
43cd72b9
BW		 1566 default_lit_sections.lit_seg_name = tc_canonicalize_symbol_name (newname);
1567 default_lit_sections.lit4_seg_name = tc_canonicalize_symbol_name (newname4);
e0001a05
NC		 1568
1569 free (name);
43cd72b9
BW		 1570}
1571
1572
1573/* Support ".frequency branch_target_frequency fall_through_frequency". */
1574
1575static void
7fa3d080 1576xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED)
43cd72b9
BW		 1577{
1578 float fall_through_f, target_f;
43cd72b9
BW		 1579
1580 fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer);
1581 if (fall_through_f < 0)
1582 {
1583 as_bad (_("fall through frequency must be greater than 0"));
1584 ignore_rest_of_line ();
1585 return;
1586 }
1587
1588 target_f = (float) strtod (input_line_pointer, &input_line_pointer);
1589 if (target_f < 0)
1590 {
1591 as_bad (_("branch target frequency must be greater than 0"));
1592 ignore_rest_of_line ();
1593 return;
1594 }
1595
b08b5071 1596 set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f);
43cd72b9
BW		 1597
1598 demand_empty_rest_of_line ();
1599}
1600
1601
1602/* Like normal .long/.short/.word, except support @plt, etc.
1603 Clobbers input_line_pointer, checks end-of-line. */
1604
1605static void
7fa3d080 1606xtensa_elf_cons (int nbytes)
43cd72b9
BW		 1607{
1608 expressionS exp;
1609 bfd_reloc_code_real_type reloc;
1610
1611 md_flush_pending_output ();
1612
1613 if (cur_vinsn.inside_bundle)
1614 as_bad (_("directives are not valid inside bundles"));
1615
1616 if (is_it_end_of_statement ())
1617 {
1618 demand_empty_rest_of_line ();
1619 return;
1620 }
1621
1622 do
1623 {
1624 expression (&exp);
1625 if (exp.X_op == O_symbol
1626 && *input_line_pointer == '@'
1627 && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp))
1628 != BFD_RELOC_NONE))
1629 {
1630 reloc_howto_type *reloc_howto =
1631 bfd_reloc_type_lookup (stdoutput, reloc);
1632
1633 if (reloc == BFD_RELOC_UNUSED || !reloc_howto)
1634 as_bad (_("unsupported relocation"));
1635 else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP
1636 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
1637 || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
1638 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT))
1639 as_bad (_("opcode-specific %s relocation used outside "
1640 "an instruction"), reloc_howto->name);
1641 else if (nbytes != (int) bfd_get_reloc_size (reloc_howto))
1642 as_bad (_("%s relocations do not fit in %d bytes"),
1643 reloc_howto->name, nbytes);
1644 else
1645 {
1646 char *p = frag_more ((int) nbytes);
1647 xtensa_set_frag_assembly_state (frag_now);
1648 fix_new_exp (frag_now, p - frag_now->fr_literal,
1649 nbytes, &exp, 0, reloc);
1650 }
1651 }
1652 else
1653 emit_expr (&exp, (unsigned int) nbytes);
1654 }
1655 while (*input_line_pointer++ == ',');
1656
1657 input_line_pointer--; /* Put terminator back into stream. */
1658 demand_empty_rest_of_line ();
1659}
1660
7fa3d080
BW		 1661\f
1662/* Parsing and Idiom Translation. */
43cd72b9
BW		 1663
1664/* Parse @plt, etc. and return the desired relocation. */
1665static bfd_reloc_code_real_type
7fa3d080 1666xtensa_elf_suffix (char **str_p, expressionS *exp_p)
43cd72b9
BW		 1667{
1668 struct map_bfd
1669 {
1670 char *string;
1671 int length;
1672 bfd_reloc_code_real_type reloc;
1673 };
1674
1675 char ident[20];
1676 char *str = *str_p;
1677 char *str2;
1678 int ch;
1679 int len;
1680 struct map_bfd *ptr;
1681
1682#define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
e0001a05 1683
43cd72b9
BW		 1684 static struct map_bfd mapping[] =
1685 {
1686 MAP ("l", BFD_RELOC_LO16),
1687 MAP ("h", BFD_RELOC_HI16),
1688 MAP ("plt", BFD_RELOC_XTENSA_PLT),
1689 { (char *) 0, 0, BFD_RELOC_UNUSED }
1690 };
1691
1692 if (*str++ != '@')
1693 return BFD_RELOC_NONE;
1694
1695 for (ch = *str, str2 = ident;
1696 (str2 < ident + sizeof (ident) - 1
1697 && (ISALNUM (ch) || ch == '@'));
1698 ch = *++str)
1699 {
1700 *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch);
1701 }
1702
1703 *str2 = '\0';
1704 len = str2 - ident;
1705
1706 ch = ident[0];
1707 for (ptr = &mapping[0]; ptr->length > 0; ptr++)
1708 if (ch == ptr->string[0]
1709 && len == ptr->length
1710 && memcmp (ident, ptr->string, ptr->length) == 0)
1711 {
1712 /* Now check for "identifier@suffix+constant". */
1713 if (*str == '-' || *str == '+')
1714 {
1715 char *orig_line = input_line_pointer;
1716 expressionS new_exp;
1717
1718 input_line_pointer = str;
1719 expression (&new_exp);
1720 if (new_exp.X_op == O_constant)
1721 {
1722 exp_p->X_add_number += new_exp.X_add_number;
1723 str = input_line_pointer;
1724 }
1725
1726 if (&input_line_pointer != str_p)
1727 input_line_pointer = orig_line;
1728 }
1729
1730 *str_p = str;
1731 return ptr->reloc;
1732 }
1733
1734 return BFD_RELOC_UNUSED;
e0001a05
NC		 1735}
1736
e0001a05
NC		 1737
1738static const char *
7fa3d080 1739expression_end (const char *name)
e0001a05
NC		 1740{
1741 while (1)
1742 {
1743 switch (*name)
1744 {
43cd72b9 1745 case '}':
e0001a05
NC		 1746 case ';':
1747 case '\0':
1748 case ',':
43cd72b9 1749 case ':':
e0001a05
NC		 1750 return name;
1751 case ' ':
1752 case '\t':
1753 ++name;
1754 continue;
1755 default:
1756 return 0;
1757 }
1758 }
1759}
1760
1761
1762#define ERROR_REG_NUM ((unsigned) -1)
1763
1764static unsigned
7fa3d080 1765tc_get_register (const char *prefix)
e0001a05
NC		 1766{
1767 unsigned reg;
1768 const char *next_expr;
1769 const char *old_line_pointer;
1770
1771 SKIP_WHITESPACE ();
1772 old_line_pointer = input_line_pointer;
1773
1774 if (*input_line_pointer == '$')
1775 ++input_line_pointer;
1776
1777 /* Accept "sp" as a synonym for "a1". */
1778 if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p'
1779 && expression_end (input_line_pointer + 2))
1780 {
1781 input_line_pointer += 2;
1782 return 1; /* AR[1] */
1783 }
1784
1785 while (*input_line_pointer++ == *prefix++)
1786 ;
1787 --input_line_pointer;
1788 --prefix;
1789
1790 if (*prefix)
1791 {
1792 as_bad (_("bad register name: %s"), old_line_pointer);
1793 return ERROR_REG_NUM;
1794 }
1795
1796 if (!ISDIGIT ((unsigned char) *input_line_pointer))
1797 {
1798 as_bad (_("bad register number: %s"), input_line_pointer);
1799 return ERROR_REG_NUM;
1800 }
1801
1802 reg = 0;
1803
1804 while (ISDIGIT ((int) *input_line_pointer))
1805 reg = reg * 10 + *input_line_pointer++ - '0';
1806
1807 if (!(next_expr = expression_end (input_line_pointer)))
1808 {
1809 as_bad (_("bad register name: %s"), old_line_pointer);
1810 return ERROR_REG_NUM;
1811 }
1812
1813 input_line_pointer = (char *) next_expr;
1814
1815 return reg;
1816}
1817
1818
e0001a05 1819static void
7fa3d080 1820expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok)
e0001a05 1821{
43cd72b9 1822 xtensa_isa isa = xtensa_default_isa;
e0001a05 1823
43cd72b9
BW		 1824 /* Check if this is an immediate operand. */
1825 if (xtensa_operand_is_register (isa, opc, opnd) == 0)
e0001a05 1826 {
43cd72b9 1827 bfd_reloc_code_real_type reloc;
e0001a05 1828 segT t = expression (tok);
43cd72b9
BW		 1829 if (t == absolute_section
1830 && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
e0001a05
NC		 1831 {
1832 assert (tok->X_op == O_constant);
1833 tok->X_op = O_symbol;
1834 tok->X_add_symbol = &abs_symbol;
1835 }
43cd72b9
BW		 1836
1837 if ((tok->X_op == O_constant || tok->X_op == O_symbol)
1838 && (reloc = xtensa_elf_suffix (&input_line_pointer, tok))
1839 && (reloc != BFD_RELOC_NONE))
e0001a05 1840 {
43cd72b9
BW		 1841 switch (reloc)
1842 {
1843 default:
1844 case BFD_RELOC_UNUSED:
1845 as_bad (_("unsupported relocation"));
1846 break;
1847
1848 case BFD_RELOC_XTENSA_PLT:
1849 tok->X_op = O_pltrel;
1850 break;
1851
1852 case BFD_RELOC_LO16:
1853 if (tok->X_op == O_constant)
1854 tok->X_add_number &= 0xffff;
1855 else
1856 tok->X_op = O_lo16;
1857 break;
1858
1859 case BFD_RELOC_HI16:
1860 if (tok->X_op == O_constant)
1861 tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
1862 else
1863 tok->X_op = O_hi16;
1864 break;
1865 }
e0001a05 1866 }
e0001a05
NC		 1867 }
1868 else
1869 {
43cd72b9
BW		 1870 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
1871 unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf));
e0001a05
NC		 1872
1873 if (reg != ERROR_REG_NUM) /* Already errored */
1874 {
1875 uint32 buf = reg;
43cd72b9 1876 if (xtensa_operand_encode (isa, opc, opnd, &buf))
e0001a05
NC		 1877 as_bad (_("register number out of range"));
1878 }
1879
1880 tok->X_op = O_register;
1881 tok->X_add_symbol = 0;
1882 tok->X_add_number = reg;
1883 }
1884}
1885
1886
1887/* Split up the arguments for an opcode or pseudo-op. */
1888
1889static int
7fa3d080 1890tokenize_arguments (char **args, char *str)
e0001a05
NC		 1891{
1892 char *old_input_line_pointer;
1893 bfd_boolean saw_comma = FALSE;
1894 bfd_boolean saw_arg = FALSE;
43cd72b9 1895 bfd_boolean saw_colon = FALSE;
e0001a05
NC		 1896 int num_args = 0;
1897 char *arg_end, *arg;
1898 int arg_len;
43cd72b9
BW		 1899
1900 /* Save and restore input_line_pointer around this function. */
e0001a05
NC		 1901 old_input_line_pointer = input_line_pointer;
1902 input_line_pointer = str;
1903
1904 while (*input_line_pointer)
1905 {
1906 SKIP_WHITESPACE ();
1907 switch (*input_line_pointer)
1908 {
1909 case '\0':
43cd72b9 1910 case '}':
e0001a05
NC		 1911 goto fini;
1912
43cd72b9
BW		 1913 case ':':
1914 input_line_pointer++;
1915 if (saw_comma || saw_colon || !saw_arg)
1916 goto err;
1917 saw_colon = TRUE;
1918 break;
1919
e0001a05
NC		 1920 case ',':
1921 input_line_pointer++;
43cd72b9 1922 if (saw_comma || saw_colon || !saw_arg)
e0001a05
NC		 1923 goto err;
1924 saw_comma = TRUE;
1925 break;
1926
1927 default:
43cd72b9 1928 if (!saw_comma && !saw_colon && saw_arg)
e0001a05
NC		 1929 goto err;
1930
1931 arg_end = input_line_pointer + 1;
1932 while (!expression_end (arg_end))
1933 arg_end += 1;
43cd72b9 1934
e0001a05 1935 arg_len = arg_end - input_line_pointer;
43cd72b9 1936 arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1);
e0001a05
NC		 1937 args[num_args] = arg;
1938
43cd72b9
BW		 1939 if (saw_colon)
1940 *arg++ = ':';
e0001a05
NC		 1941 strncpy (arg, input_line_pointer, arg_len);
1942 arg[arg_len] = '\0';
43cd72b9 1943
e0001a05
NC		 1944 input_line_pointer = arg_end;
1945 num_args += 1;
1946 saw_comma = FALSE;
43cd72b9 1947 saw_colon = FALSE;
e0001a05
NC		 1948 saw_arg = TRUE;
1949 break;
1950 }
1951 }
1952
1953fini:
43cd72b9 1954 if (saw_comma || saw_colon)
e0001a05
NC		 1955 goto err;
1956 input_line_pointer = old_input_line_pointer;
1957 return num_args;
1958
1959err:
43cd72b9
BW		 1960 if (saw_comma)
1961 as_bad (_("extra comma"));
1962 else if (saw_colon)
1963 as_bad (_("extra colon"));
1964 else if (!saw_arg)
1965 as_bad (_("missing argument"));
1966 else
1967 as_bad (_("missing comma or colon"));
e0001a05
NC		 1968 input_line_pointer = old_input_line_pointer;
1969 return -1;
1970}
1971
1972
43cd72b9 1973/* Parse the arguments to an opcode. Return TRUE on error. */
e0001a05
NC		 1974
1975static bfd_boolean
7fa3d080 1976parse_arguments (TInsn *insn, int num_args, char **arg_strings)
e0001a05 1977{
43cd72b9 1978 expressionS *tok, *last_tok;
e0001a05
NC		 1979 xtensa_opcode opcode = insn->opcode;
1980 bfd_boolean had_error = TRUE;
43cd72b9
BW		 1981 xtensa_isa isa = xtensa_default_isa;
1982 int n, num_regs = 0;
e0001a05 1983 int opcode_operand_count;
43cd72b9
BW		 1984 int opnd_cnt, last_opnd_cnt;
1985 unsigned int next_reg = 0;
e0001a05
NC		 1986 char *old_input_line_pointer;
1987
1988 if (insn->insn_type == ITYPE_LITERAL)
1989 opcode_operand_count = 1;
1990 else
43cd72b9 1991 opcode_operand_count = xtensa_opcode_num_operands (isa, opcode);
e0001a05 1992
43cd72b9 1993 tok = insn->tok;
e0001a05
NC		 1994 memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS);
1995
1996 /* Save and restore input_line_pointer around this function. */
43cd72b9
BW		 1997 old_input_line_pointer = input_line_pointer;
1998
1999 last_tok = 0;
2000 last_opnd_cnt = -1;
2001 opnd_cnt = 0;
2002
2003 /* Skip invisible operands. */
2004 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0)
2005 {
2006 opnd_cnt += 1;
2007 tok++;
2008 }
e0001a05
NC		 2009
2010 for (n = 0; n < num_args; n++)
43cd72b9 2011 {
e0001a05 2012 input_line_pointer = arg_strings[n];
43cd72b9
BW		 2013 if (*input_line_pointer == ':')
2014 {
2015 xtensa_regfile opnd_rf;
2016 input_line_pointer++;
2017 if (num_regs == 0)
2018 goto err;
2019 assert (opnd_cnt > 0);
2020 num_regs--;
2021 opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt);
2022 if (next_reg
2023 != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)))
2024 as_warn (_("incorrect register number, ignoring"));
2025 next_reg++;
2026 }
2027 else
2028 {
2029 if (opnd_cnt >= opcode_operand_count)
2030 {
2031 as_warn (_("too many arguments"));
2032 goto err;
2033 }
2034 assert (opnd_cnt < MAX_INSN_ARGS);
2035
2036 expression_maybe_register (opcode, opnd_cnt, tok);
2037 next_reg = tok->X_add_number + 1;
2038
2039 if (tok->X_op == O_illegal || tok->X_op == O_absent)
2040 goto err;
2041 if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1)
2042 {
2043 num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1;
2044 /* minus 1 because we are seeing one right now */
2045 }
2046 else
2047 num_regs = 0;
e0001a05 2048
43cd72b9
BW		 2049 last_tok = tok;
2050 last_opnd_cnt = opnd_cnt;
e0001a05 2051
43cd72b9
BW		 2052 do
2053 {
2054 opnd_cnt += 1;
2055 tok++;
2056 }
2057 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0);
2058 }
2059 }
e0001a05 2060
43cd72b9
BW		 2061 if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1))
2062 goto err;
e0001a05
NC		 2063
2064 insn->ntok = tok - insn->tok;
2065 had_error = FALSE;
2066
2067 err:
43cd72b9 2068 input_line_pointer = old_input_line_pointer;
e0001a05
NC		 2069 return had_error;
2070}
2071
2072
43cd72b9 2073static int
7fa3d080 2074get_invisible_operands (TInsn *insn)
43cd72b9
BW		 2075{
2076 xtensa_isa isa = xtensa_default_isa;
2077 static xtensa_insnbuf slotbuf = NULL;
2078 xtensa_format fmt;
2079 xtensa_opcode opc = insn->opcode;
2080 int slot, opnd, fmt_found;
2081 unsigned val;
2082
2083 if (!slotbuf)
2084 slotbuf = xtensa_insnbuf_alloc (isa);
2085
2086 /* Find format/slot where this can be encoded. */
2087 fmt_found = 0;
2088 slot = 0;
2089 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
2090 {
2091 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
2092 {
2093 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0)
2094 {
2095 fmt_found = 1;
2096 break;
2097 }
2098 }
2099 if (fmt_found) break;
2100 }
2101
2102 if (!fmt_found)
2103 {
2104 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc));
2105 return -1;
2106 }
2107
2108 /* First encode all the visible operands
2109 (to deal with shared field operands). */
2110 for (opnd = 0; opnd < insn->ntok; opnd++)
2111 {
2112 if (xtensa_operand_is_visible (isa, opc, opnd) == 1
2113 && (insn->tok[opnd].X_op == O_register
2114 || insn->tok[opnd].X_op == O_constant))
2115 {
2116 val = insn->tok[opnd].X_add_number;
2117 xtensa_operand_encode (isa, opc, opnd, &val);
2118 xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val);
2119 }
2120 }
2121
2122 /* Then pull out the values for the invisible ones. */
2123 for (opnd = 0; opnd < insn->ntok; opnd++)
2124 {
2125 if (xtensa_operand_is_visible (isa, opc, opnd) == 0)
2126 {
2127 xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val);
2128 xtensa_operand_decode (isa, opc, opnd, &val);
2129 insn->tok[opnd].X_add_number = val;
2130 if (xtensa_operand_is_register (isa, opc, opnd) == 1)
2131 insn->tok[opnd].X_op = O_register;
2132 else
2133 insn->tok[opnd].X_op = O_constant;
2134 }
2135 }
2136
2137 return 0;
2138}
2139
2140
e0001a05 2141static void
7fa3d080 2142xg_reverse_shift_count (char **cnt_argp)
e0001a05
NC		 2143{
2144 char *cnt_arg, *new_arg;
2145 cnt_arg = *cnt_argp;
2146
2147 /* replace the argument with "31-(argument)" */
2148 new_arg = (char *) xmalloc (strlen (cnt_arg) + 6);
2149 sprintf (new_arg, "31-(%s)", cnt_arg);
2150
2151 free (cnt_arg);
2152 *cnt_argp = new_arg;
2153}
2154
2155
2156/* If "arg" is a constant expression, return non-zero with the value
2157 in *valp. */
2158
2159static int
7fa3d080 2160xg_arg_is_constant (char *arg, offsetT *valp)
e0001a05
NC		 2161{
2162 expressionS exp;
2163 char *save_ptr = input_line_pointer;
2164
2165 input_line_pointer = arg;
2166 expression (&exp);
2167 input_line_pointer = save_ptr;
2168
2169 if (exp.X_op == O_constant)
2170 {
2171 *valp = exp.X_add_number;
2172 return 1;
2173 }
2174
2175 return 0;
2176}
2177
2178
2179static void
7fa3d080 2180xg_replace_opname (char **popname, char *newop)
e0001a05
NC		 2181{
2182 free (*popname);
2183 *popname = (char *) xmalloc (strlen (newop) + 1);
2184 strcpy (*popname, newop);
2185}
2186
2187
2188static int
7fa3d080
BW		 2189xg_check_num_args (int *pnum_args,
2190 int expected_num,
2191 char *opname,
2192 char **arg_strings)
e0001a05
NC		 2193{
2194 int num_args = *pnum_args;
2195
43cd72b9 2196 if (num_args < expected_num)
e0001a05
NC		 2197 {
2198 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2199 num_args, opname, expected_num);
2200 return -1;
2201 }
2202
2203 if (num_args > expected_num)
2204 {
2205 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2206 num_args, opname, expected_num);
2207 while (num_args-- > expected_num)
2208 {
2209 free (arg_strings[num_args]);
2210 arg_strings[num_args] = 0;
2211 }
2212 *pnum_args = expected_num;
2213 return -1;
2214 }
2215
2216 return 0;
2217}
2218
2219
43cd72b9
BW		 2220/* If the register is not specified as part of the opcode,
2221 then get it from the operand and move it to the opcode. */
2222
e0001a05 2223static int
7fa3d080 2224xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings)
e0001a05 2225{
43cd72b9
BW		 2226 xtensa_isa isa = xtensa_default_isa;
2227 xtensa_sysreg sr;
e0001a05 2228 char *opname, *new_opname;
43cd72b9
BW		 2229 const char *sr_name;
2230 int is_user, is_write;
e0001a05
NC		 2231 bfd_boolean has_underbar = FALSE;
2232
2233 opname = *popname;
2234 if (*opname == '_')
2235 {
2236 has_underbar = TRUE;
2237 opname += 1;
2238 }
43cd72b9
BW		 2239 is_user = (opname[1] == 'u');
2240 is_write = (opname[0] == 'w');
e0001a05 2241
43cd72b9 2242 /* Opname == [rw]ur or [rwx]sr... */
e0001a05 2243
43cd72b9
BW		 2244 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2245 return -1;
e0001a05 2246
43cd72b9
BW		 2247 /* Check if the argument is a symbolic register name. */
2248 sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]);
2249 /* Handle WSR to "INTSET" as a special case. */
2250 if (sr == XTENSA_UNDEFINED && is_write && !is_user
2251 && !strcasecmp (arg_strings[1], "intset"))
2252 sr = xtensa_sysreg_lookup_name (isa, "interrupt");
2253 if (sr == XTENSA_UNDEFINED
2254 || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user)
2255 {
2256 /* Maybe it's a register number.... */
2257 offsetT val;
e0001a05
NC		 2258 if (!xg_arg_is_constant (arg_strings[1], &val))
2259 {
43cd72b9
BW		 2260 as_bad (_("invalid register '%s' for '%s' instruction"),
2261 arg_strings[1], opname);
e0001a05
NC		 2262 return -1;
2263 }
43cd72b9
BW		 2264 sr = xtensa_sysreg_lookup (isa, val, is_user);
2265 if (sr == XTENSA_UNDEFINED)
e0001a05 2266 {
43cd72b9 2267 as_bad (_("invalid register number (%ld) for '%s' instruction"),
e0001a05
NC		 2268 val, opname);
2269 return -1;
2270 }
43cd72b9 2271 }
e0001a05 2272
43cd72b9
BW		 2273 /* Remove the last argument, which is now part of the opcode. */
2274 free (arg_strings[1]);
2275 arg_strings[1] = 0;
2276 *pnum_args = 1;
2277
2278 /* Translate the opcode. */
2279 sr_name = xtensa_sysreg_name (isa, sr);
2280 /* Another special case for "WSR.INTSET".... */
2281 if (is_write && !is_user && !strcasecmp ("interrupt", sr_name))
2282 sr_name = "intset";
2283 new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2284 sprintf (new_opname, "%s%s.%s", (has_underbar ? "_" : ""),
2285 *popname, sr_name);
2286 free (*popname);
2287 *popname = new_opname;
2288
2289 return 0;
2290}
2291
2292
2293static int
7fa3d080 2294xtensa_translate_old_userreg_ops (char **popname)
43cd72b9
BW		 2295{
2296 xtensa_isa isa = xtensa_default_isa;
2297 xtensa_sysreg sr;
2298 char *opname, *new_opname;
2299 const char *sr_name;
2300 bfd_boolean has_underbar = FALSE;
2301
2302 opname = *popname;
2303 if (opname[0] == '_')
2304 {
2305 has_underbar = TRUE;
2306 opname += 1;
2307 }
2308
2309 sr = xtensa_sysreg_lookup_name (isa, opname + 1);
2310 if (sr != XTENSA_UNDEFINED)
2311 {
2312 /* The new default name ("nnn") is different from the old default
2313 name ("URnnn"). The old default is handled below, and we don't
2314 want to recognize [RW]nnn, so do nothing if the name is the (new)
2315 default. */
2316 static char namebuf[10];
2317 sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr));
2318 if (strcmp (namebuf, opname + 1) == 0)
2319 return 0;
2320 }
2321 else
2322 {
2323 offsetT val;
2324 char *end;
2325
2326 /* Only continue if the reg name is "URnnn". */
2327 if (opname[1] != 'u' || opname[2] != 'r')
2328 return 0;
2329 val = strtoul (opname + 3, &end, 10);
2330 if (*end != '\0')
2331 return 0;
2332
2333 sr = xtensa_sysreg_lookup (isa, val, 1);
2334 if (sr == XTENSA_UNDEFINED)
2335 {
2336 as_bad (_("invalid register number (%ld) for '%s'"),
2337 val, opname);
2338 return -1;
2339 }
2340 }
2341
2342 /* Translate the opcode. */
2343 sr_name = xtensa_sysreg_name (isa, sr);
2344 new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2345 sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""),
2346 opname[0], sr_name);
2347 free (*popname);
2348 *popname = new_opname;
2349
2350 return 0;
2351}
2352
2353
2354static int
7fa3d080
BW		 2355xtensa_translate_zero_immed (char *old_op,
2356 char *new_op,
2357 char **popname,
2358 int *pnum_args,
2359 char **arg_strings)
43cd72b9
BW		 2360{
2361 char *opname;
2362 offsetT val;
2363
2364 opname = *popname;
2365 assert (opname[0] != '_');
2366
2367 if (strcmp (opname, old_op) != 0)
2368 return 0;
e0001a05 2369
43cd72b9
BW		 2370 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2371 return -1;
2372 if (xg_arg_is_constant (arg_strings[1], &val) && val == 0)
2373 {
2374 xg_replace_opname (popname, new_op);
2375 free (arg_strings[1]);
2376 arg_strings[1] = arg_strings[2];
2377 arg_strings[2] = 0;
2378 *pnum_args = 2;
e0001a05
NC		 2379 }
2380
2381 return 0;
2382}
2383
2384
2385/* If the instruction is an idiom (i.e., a built-in macro), translate it.
2386 Returns non-zero if an error was found. */
2387
2388static int
7fa3d080 2389xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
e0001a05
NC		 2390{
2391 char *opname = *popname;
2392 bfd_boolean has_underbar = FALSE;
2393
43cd72b9
BW		 2394 if (cur_vinsn.inside_bundle)
2395 return 0;
2396
e0001a05
NC		 2397 if (*opname == '_')
2398 {
2399 has_underbar = TRUE;
2400 opname += 1;
2401 }
2402
2403 if (strcmp (opname, "mov") == 0)
2404 {
43cd72b9 2405 if (use_transform () && !has_underbar && density_supported)
e0001a05
NC		 2406 xg_replace_opname (popname, "mov.n");
2407 else
2408 {
2409 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2410 return -1;
2411 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2412 arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1);
2413 strcpy (arg_strings[2], arg_strings[1]);
2414 *pnum_args = 3;
2415 }
2416 return 0;
2417 }
2418
2419 if (strcmp (opname, "bbsi.l") == 0)
2420 {
2421 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2422 return -1;
2423 xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi"));
2424 if (target_big_endian)
2425 xg_reverse_shift_count (&arg_strings[1]);
2426 return 0;
2427 }
2428
2429 if (strcmp (opname, "bbci.l") == 0)
2430 {
2431 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2432 return -1;
2433 xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci"));
2434 if (target_big_endian)
2435 xg_reverse_shift_count (&arg_strings[1]);
2436 return 0;
2437 }
2438
43cd72b9
BW		 2439 if (xtensa_nop_opcode == XTENSA_UNDEFINED
2440 && strcmp (opname, "nop") == 0)
e0001a05 2441 {
43cd72b9 2442 if (use_transform () && !has_underbar && density_supported)
e0001a05
NC		 2443 xg_replace_opname (popname, "nop.n");
2444 else
2445 {
2446 if (xg_check_num_args (pnum_args, 0, opname, arg_strings))
2447 return -1;
2448 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2449 arg_strings[0] = (char *) xmalloc (3);
2450 arg_strings[1] = (char *) xmalloc (3);
2451 arg_strings[2] = (char *) xmalloc (3);
2452 strcpy (arg_strings[0], "a1");
2453 strcpy (arg_strings[1], "a1");
2454 strcpy (arg_strings[2], "a1");
2455 *pnum_args = 3;
2456 }
2457 return 0;
2458 }
2459
43cd72b9
BW		 2460 /* Recognize [RW]UR and [RWX]SR. */
2461 if ((((opname[0] == 'r' || opname[0] == 'w')
2462 && (opname[1] == 'u' || opname[1] == 's'))
2463 || (opname[0] == 'x' && opname[1] == 's'))
2464 && opname[2] == 'r'
2465 && opname[3] == '\0')
e0001a05
NC		 2466 return xg_translate_sysreg_op (popname, pnum_args, arg_strings);
2467
43cd72b9
BW		 2468 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2469 [RW]<name> if <name> is the non-default name of a user register. */
2470 if ((opname[0] == 'r' || opname[0] == 'w')
2471 && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED)
2472 return xtensa_translate_old_userreg_ops (popname);
e0001a05 2473
43cd72b9
BW		 2474 /* Relax branches that don't allow comparisons against an immediate value
2475 of zero to the corresponding branches with implicit zero immediates. */
2476 if (!has_underbar && use_transform ())
2477 {
2478 if (xtensa_translate_zero_immed ("bnei", "bnez", popname,
2479 pnum_args, arg_strings))
2480 return -1;
e0001a05 2481
43cd72b9
BW		 2482 if (xtensa_translate_zero_immed ("beqi", "beqz", popname,
2483 pnum_args, arg_strings))
2484 return -1;
e0001a05 2485
43cd72b9
BW		 2486 if (xtensa_translate_zero_immed ("bgei", "bgez", popname,
2487 pnum_args, arg_strings))
2488 return -1;
e0001a05 2489
43cd72b9
BW		 2490 if (xtensa_translate_zero_immed ("blti", "bltz", popname,
2491 pnum_args, arg_strings))
2492 return -1;
2493 }
e0001a05 2494
43cd72b9
BW		 2495 return 0;
2496}
e0001a05 2497
43cd72b9
BW		 2498\f
2499/* Functions for dealing with the Xtensa ISA. */
e0001a05 2500
43cd72b9
BW		 2501/* Currently the assembler only allows us to use a single target per
2502 fragment. Because of this, only one operand for a given
2503 instruction may be symbolic. If there is a PC-relative operand,
2504 the last one is chosen. Otherwise, the result is the number of the
2505 last immediate operand, and if there are none of those, we fail and
2506 return -1. */
e0001a05 2507
7fa3d080
BW		 2508static int
2509get_relaxable_immed (xtensa_opcode opcode)
43cd72b9
BW		 2510{
2511 int last_immed = -1;
2512 int noperands, opi;
e0001a05 2513
43cd72b9
BW		 2514 if (opcode == XTENSA_UNDEFINED)
2515 return -1;
e0001a05 2516
43cd72b9
BW		 2517 noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode);
2518 for (opi = noperands - 1; opi >= 0; opi--)
2519 {
2520 if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0)
2521 continue;
2522 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1)
2523 return opi;
2524 if (last_immed == -1
2525 && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0)
2526 last_immed = opi;
e0001a05 2527 }
43cd72b9 2528 return last_immed;
e0001a05
NC		 2529}
2530
e0001a05 2531
43cd72b9 2532static xtensa_opcode
7fa3d080 2533get_opcode_from_buf (const char *buf, int slot)
e0001a05 2534{
43cd72b9
BW		 2535 static xtensa_insnbuf insnbuf = NULL;
2536 static xtensa_insnbuf slotbuf = NULL;
2537 xtensa_isa isa = xtensa_default_isa;
2538 xtensa_format fmt;
2539
2540 if (!insnbuf)
e0001a05 2541 {
43cd72b9
BW		 2542 insnbuf = xtensa_insnbuf_alloc (isa);
2543 slotbuf = xtensa_insnbuf_alloc (isa);
e0001a05 2544 }
e0001a05 2545
43cd72b9
BW		 2546 xtensa_insnbuf_from_chars (isa, insnbuf, buf, 0);
2547 fmt = xtensa_format_decode (isa, insnbuf);
2548 if (fmt == XTENSA_UNDEFINED)
2549 return XTENSA_UNDEFINED;
e0001a05 2550
43cd72b9
BW		 2551 if (slot >= xtensa_format_num_slots (isa, fmt))
2552 return XTENSA_UNDEFINED;
e0001a05 2553
43cd72b9
BW		 2554 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
2555 return xtensa_opcode_decode (isa, fmt, slot, slotbuf);
e0001a05
NC		 2556}
2557
2558
43cd72b9 2559#ifdef TENSILICA_DEBUG
e0001a05 2560
43cd72b9 2561/* For debugging, print out the mapping of opcode numbers to opcodes. */
e0001a05 2562
7fa3d080
BW		 2563static void
2564xtensa_print_insn_table (void)
43cd72b9
BW		 2565{
2566 int num_opcodes, num_operands;
2567 xtensa_opcode opcode;
2568 xtensa_isa isa = xtensa_default_isa;
e0001a05 2569
43cd72b9
BW		 2570 num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
2571 for (opcode = 0; opcode < num_opcodes; opcode++)
e0001a05 2572 {
43cd72b9
BW		 2573 int opn;
2574 fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode));
2575 num_operands = xtensa_opcode_num_operands (isa, opcode);
2576 for (opn = 0; opn < num_operands; opn++)
2577 {
2578 if (xtensa_operand_is_visible (isa, opcode, opn) == 0)
2579 continue;
2580 if (xtensa_operand_is_register (isa, opcode, opn) == 1)
2581 {
2582 xtensa_regfile opnd_rf =
2583 xtensa_operand_regfile (isa, opcode, opn);
2584 fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf));
2585 }
2586 else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1)
2587 fputs ("[lLr] ", stderr);
2588 else
2589 fputs ("i ", stderr);
2590 }
2591 fprintf (stderr, "\n");
e0001a05 2592 }
e0001a05
NC		 2593}
2594
2595
43cd72b9 2596static void
7fa3d080 2597print_vliw_insn (xtensa_insnbuf vbuf)
e0001a05 2598{
e0001a05 2599 xtensa_isa isa = xtensa_default_isa;
43cd72b9
BW		 2600 xtensa_format f = xtensa_format_decode (isa, vbuf);
2601 xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa);
2602 int op;
e0001a05 2603
43cd72b9 2604 fprintf (stderr, "format = %d\n", f);
e0001a05 2605
43cd72b9
BW		 2606 for (op = 0; op < xtensa_format_num_slots (isa, f); op++)
2607 {
2608 xtensa_opcode opcode;
2609 const char *opname;
2610 int operands;
2611
2612 xtensa_format_get_slot (isa, f, op, vbuf, sbuf);
2613 opcode = xtensa_opcode_decode (isa, f, op, sbuf);
2614 opname = xtensa_opcode_name (isa, opcode);
2615
2616 fprintf (stderr, "op in slot %i is %s;\n", op, opname);
2617 fprintf (stderr, " operands = ");
2618 for (operands = 0;
2619 operands < xtensa_opcode_num_operands (isa, opcode);
2620 operands++)
2621 {
2622 unsigned int val;
2623 if (xtensa_operand_is_visible (isa, opcode, operands) == 0)
2624 continue;
2625 xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val);
2626 xtensa_operand_decode (isa, opcode, operands, &val);
2627 fprintf (stderr, "%d ", val);
2628 }
2629 fprintf (stderr, "\n");
2630 }
2631 xtensa_insnbuf_free (isa, sbuf);
e0001a05
NC		 2632}
2633
43cd72b9
BW		 2634#endif /* TENSILICA_DEBUG */
2635
e0001a05
NC		 2636
2637static bfd_boolean
7fa3d080 2638is_direct_call_opcode (xtensa_opcode opcode)
e0001a05 2639{
43cd72b9
BW		 2640 xtensa_isa isa = xtensa_default_isa;
2641 int n, num_operands;
e0001a05 2642
43cd72b9 2643 if (xtensa_opcode_is_call (isa, opcode) == 0)
e0001a05
NC		 2644 return FALSE;
2645
43cd72b9
BW		 2646 num_operands = xtensa_opcode_num_operands (isa, opcode);
2647 for (n = 0; n < num_operands; n++)
2648 {
2649 if (xtensa_operand_is_register (isa, opcode, n) == 0
2650 && xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
2651 return TRUE;
2652 }
2653 return FALSE;
e0001a05
NC		 2654}
2655
2656
43cd72b9
BW		 2657/* Convert from BFD relocation type code to slot and operand number.
2658 Returns non-zero on failure. */
e0001a05 2659
43cd72b9 2660static int
7fa3d080 2661decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt)
e0001a05 2662{
43cd72b9
BW		 2663 if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
2664 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
e0001a05 2665 {
43cd72b9
BW		 2666 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
2667 *is_alt = FALSE;
e0001a05 2668 }
43cd72b9
BW		 2669 else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
2670 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
e0001a05 2671 {
43cd72b9
BW		 2672 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
2673 *is_alt = TRUE;
e0001a05 2674 }
43cd72b9
BW		 2675 else
2676 return -1;
2677
2678 return 0;
e0001a05
NC		 2679}
2680
2681
43cd72b9
BW		 2682/* Convert from slot number to BFD relocation type code for the
2683 standard PC-relative relocations. Return BFD_RELOC_NONE on
2684 failure. */
e0001a05 2685
43cd72b9 2686static bfd_reloc_code_real_type
7fa3d080 2687encode_reloc (int slot)
e0001a05 2688{
43cd72b9
BW		 2689 if (slot < 0 || slot > 14)
2690 return BFD_RELOC_NONE;
2691
2692 return BFD_RELOC_XTENSA_SLOT0_OP + slot;
e0001a05
NC		 2693}
2694
2695
43cd72b9
BW		 2696/* Convert from slot numbers to BFD relocation type code for the
2697 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
e0001a05 2698
43cd72b9 2699static bfd_reloc_code_real_type
7fa3d080 2700encode_alt_reloc (int slot)
e0001a05 2701{
43cd72b9
BW		 2702 if (slot < 0 || slot > 14)
2703 return BFD_RELOC_NONE;
2704
2705 return BFD_RELOC_XTENSA_SLOT0_ALT + slot;
e0001a05
NC		 2706}
2707
2708
2709static void
7fa3d080
BW		 2710xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf,
2711 xtensa_format fmt,
2712 int slot,
2713 xtensa_opcode opcode,
2714 int operand,
2715 uint32 value,
2716 const char *file,
2717 unsigned int line)
e0001a05 2718{
e0001a05
NC		 2719 uint32 valbuf = value;
2720
43cd72b9 2721 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
e0001a05 2722 {
43cd72b9
BW		 2723 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
2724 == 1)
2725 as_bad_where ((char *) file, line,
2726 _("operand %u is out of range for '%s'"), value,
2727 xtensa_opcode_name (xtensa_default_isa, opcode));
2728 else
2729 as_bad_where ((char *) file, line,
2730 _("operand %u is invalid for '%s'"), value,
2731 xtensa_opcode_name (xtensa_default_isa, opcode));
2732 return;
e0001a05
NC		 2733 }
2734
43cd72b9
BW		 2735 xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot,
2736 slotbuf, valbuf);
e0001a05
NC		 2737}
2738
2739
2740static uint32
7fa3d080
BW		 2741xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf,
2742 xtensa_format fmt,
2743 int slot,
2744 xtensa_opcode opcode,
2745 int opnum)
e0001a05 2746{
43cd72b9
BW		 2747 uint32 val = 0;
2748 (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum,
2749 fmt, slot, slotbuf, &val);
2750 (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val);
2751 return val;
e0001a05
NC		 2752}
2753
e0001a05 2754\f
7fa3d080 2755/* Checks for rules from xtensa-relax tables. */
e0001a05 2756
7fa3d080
BW		 2757/* The routine xg_instruction_matches_option_term must return TRUE
2758 when a given option term is true. The meaning of all of the option
2759 terms is given interpretation by this function. This is needed when
2760 an option depends on the state of a directive, but there are no such
2761 options in use right now. */
e0001a05 2762
7fa3d080
BW		 2763static bfd_boolean
2764xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED,
2765 const ReqOrOption *option)
e0001a05 2766{
7fa3d080
BW		 2767 if (strcmp (option->option_name, "realnop") == 0
2768 || strncmp (option->option_name, "IsaUse", 6) == 0)
2769 {
2770 /* These conditions were evaluated statically when building the
2771 relaxation table. There's no need to reevaluate them now. */
2772 return TRUE;
2773 }
2774 else
2775 {
2776 as_fatal (_("internal error: unknown option name '%s'"),
2777 option->option_name);
2778 }
e0001a05
NC		 2779}
2780
2781
7fa3d080
BW		 2782static bfd_boolean
2783xg_instruction_matches_or_options (TInsn *insn,
2784 const ReqOrOptionList *or_option)
e0001a05 2785{
7fa3d080
BW		 2786 const ReqOrOption *option;
2787 /* Must match each of the AND terms. */
2788 for (option = or_option; option != NULL; option = option->next)
e0001a05 2789 {
7fa3d080
BW		 2790 if (xg_instruction_matches_option_term (insn, option))
2791 return TRUE;
e0001a05 2792 }
7fa3d080 2793 return FALSE;
e0001a05
NC		 2794}
2795
2796
7fa3d080
BW		 2797static bfd_boolean
2798xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options)
e0001a05 2799{
7fa3d080
BW		 2800 const ReqOption *req_options;
2801 /* Must match each of the AND terms. */
2802 for (req_options = options;
2803 req_options != NULL;
2804 req_options = req_options->next)
e0001a05 2805 {
7fa3d080
BW		 2806 /* Must match one of the OR clauses. */
2807 if (!xg_instruction_matches_or_options (insn,
2808 req_options->or_option_terms))
2809 return FALSE;
e0001a05 2810 }
7fa3d080 2811 return TRUE;
e0001a05
NC		 2812}
2813
2814
7fa3d080 2815/* Return the transition rule that matches or NULL if none matches. */
e0001a05 2816
7fa3d080
BW		 2817static bfd_boolean
2818xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule)
e0001a05 2819{
7fa3d080 2820 PreconditionList *condition_l;
e0001a05 2821
7fa3d080
BW		 2822 if (rule->opcode != insn->opcode)
2823 return FALSE;
e0001a05 2824
7fa3d080
BW		 2825 for (condition_l = rule->conditions;
2826 condition_l != NULL;
2827 condition_l = condition_l->next)
e0001a05 2828 {
7fa3d080
BW		 2829 expressionS *exp1;
2830 expressionS *exp2;
2831 Precondition *cond = condition_l->precond;
e0001a05 2832
7fa3d080 2833 switch (cond->typ)
e0001a05 2834 {
7fa3d080
BW		 2835 case OP_CONSTANT:
2836 /* The expression must be the constant. */
2837 assert (cond->op_num < insn->ntok);
2838 exp1 = &insn->tok[cond->op_num];
2839 if (expr_is_const (exp1))
2840 {
2841 switch (cond->cmp)
2842 {
2843 case OP_EQUAL:
2844 if (get_expr_const (exp1) != cond->op_data)
2845 return FALSE;
2846 break;
2847 case OP_NOTEQUAL:
2848 if (get_expr_const (exp1) == cond->op_data)
2849 return FALSE;
2850 break;
2851 default:
2852 return FALSE;
2853 }
2854 }
2855 else if (expr_is_register (exp1))
2856 {
2857 switch (cond->cmp)
2858 {
2859 case OP_EQUAL:
2860 if (get_expr_register (exp1) != cond->op_data)
2861 return FALSE;
2862 break;
2863 case OP_NOTEQUAL:
2864 if (get_expr_register (exp1) == cond->op_data)
2865 return FALSE;
2866 break;
2867 default:
2868 return FALSE;
2869 }
2870 }
2871 else
2872 return FALSE;
2873 break;
2874
2875 case OP_OPERAND:
2876 assert (cond->op_num < insn->ntok);
2877 assert (cond->op_data < insn->ntok);
2878 exp1 = &insn->tok[cond->op_num];
2879 exp2 = &insn->tok[cond->op_data];
2880
2881 switch (cond->cmp)
2882 {
2883 case OP_EQUAL:
2884 if (!expr_is_equal (exp1, exp2))
2885 return FALSE;
2886 break;
2887 case OP_NOTEQUAL:
2888 if (expr_is_equal (exp1, exp2))
2889 return FALSE;
2890 break;
2891 }
2892 break;
2893
2894 case OP_LITERAL:
2895 case OP_LABEL:
2896 default:
2897 return FALSE;
2898 }
2899 }
2900 if (!xg_instruction_matches_options (insn, rule->options))
2901 return FALSE;
2902
2903 return TRUE;
2904}
2905
2906
2907static int
2908transition_rule_cmp (const TransitionRule *a, const TransitionRule *b)
2909{
2910 bfd_boolean a_greater = FALSE;
2911 bfd_boolean b_greater = FALSE;
2912
2913 ReqOptionList *l_a = a->options;
2914 ReqOptionList *l_b = b->options;
2915
2916 /* We only care if they both are the same except for
2917 a const16 vs. an l32r. */
2918
2919 while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2920 {
2921 ReqOrOptionList *l_or_a = l_a->or_option_terms;
2922 ReqOrOptionList *l_or_b = l_b->or_option_terms;
2923 while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2924 {
2925 if (l_or_a->is_true != l_or_b->is_true)
2926 return 0;
2927 if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0)
2928 {
2929 /* This is the case we care about. */
2930 if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0
2931 && strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
2932 {
2933 if (prefer_const16)
2934 a_greater = TRUE;
2935 else
2936 b_greater = TRUE;
2937 }
2938 else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
2939 && strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
2940 {
2941 if (prefer_const16)
2942 b_greater = TRUE;
2943 else
2944 a_greater = TRUE;
2945 }
2946 else
2947 return 0;
2948 }
2949 l_or_a = l_or_a->next;
2950 l_or_b = l_or_b->next;
2951 }
2952 if (l_or_a || l_or_b)
2953 return 0;
2954
2955 l_a = l_a->next;
2956 l_b = l_b->next;
2957 }
2958 if (l_a || l_b)
2959 return 0;
2960
2961 /* Incomparable if the substitution was used differently in two cases. */
2962 if (a_greater && b_greater)
2963 return 0;
2964
2965 if (b_greater)
2966 return 1;
2967 if (a_greater)
2968 return -1;
2969
2970 return 0;
2971}
2972
2973
2974static TransitionRule *
2975xg_instruction_match (TInsn *insn)
2976{
2977 TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp);
2978 TransitionList *l;
2979 assert (insn->opcode < table->num_opcodes);
2980
2981 /* Walk through all of the possible transitions. */
2982 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
2983 {
2984 TransitionRule *rule = l->rule;
2985 if (xg_instruction_matches_rule (insn, rule))
2986 return rule;
2987 }
2988 return NULL;
2989}
2990
2991\f
2992/* Various Other Internal Functions. */
2993
2994static bfd_boolean
2995is_unique_insn_expansion (TransitionRule *r)
2996{
2997 if (!r->to_instr || r->to_instr->next != NULL)
2998 return FALSE;
2999 if (r->to_instr->typ != INSTR_INSTR)
3000 return FALSE;
3001 return TRUE;
3002}
3003
3004
3005static int
3006xg_get_build_instr_size (BuildInstr *insn)
3007{
3008 assert (insn->typ == INSTR_INSTR);
3009 return xg_get_single_size (insn->opcode);
3010}
3011
3012
3013static bfd_boolean
3014xg_is_narrow_insn (TInsn *insn)
3015{
3016 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3017 TransitionList *l;
3018 int num_match = 0;
3019 assert (insn->insn_type == ITYPE_INSN);
3020 assert (insn->opcode < table->num_opcodes);
3021
3022 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3023 {
3024 TransitionRule *rule = l->rule;
3025
3026 if (xg_instruction_matches_rule (insn, rule)
3027 && is_unique_insn_expansion (rule))
3028 {
3029 /* It only generates one instruction... */
3030 assert (insn->insn_type == ITYPE_INSN);
3031 /* ...and it is a larger instruction. */
3032 if (xg_get_single_size (insn->opcode)
3033 < xg_get_build_instr_size (rule->to_instr))
3034 {
3035 num_match++;
3036 if (num_match > 1)
3037 return FALSE;
3038 }
3039 }
3040 }
3041 return (num_match == 1);
3042}
3043
3044
3045static bfd_boolean
3046xg_is_single_relaxable_insn (TInsn *insn)
3047{
3048 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3049 TransitionList *l;
3050 int num_match = 0;
3051 assert (insn->insn_type == ITYPE_INSN);
3052 assert (insn->opcode < table->num_opcodes);
3053
3054 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3055 {
3056 TransitionRule *rule = l->rule;
3057
3058 if (xg_instruction_matches_rule (insn, rule)
3059 && is_unique_insn_expansion (rule))
3060 {
3061 /* It only generates one instruction... */
3062 assert (insn->insn_type == ITYPE_INSN);
3063 /* ... and it is a larger instruction. */
3064 if (xg_get_single_size (insn->opcode)
3065 <= xg_get_build_instr_size (rule->to_instr))
3066 {
3067 num_match++;
3068 if (num_match > 1)
3069 return FALSE;
3070 }
3071 }
3072 }
3073 return (num_match == 1);
3074}
3075
3076
3077/* Return the maximum number of bytes this opcode can expand to. */
3078
3079static int
3080xg_get_max_insn_widen_size (xtensa_opcode opcode)
3081{
3082 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3083 TransitionList *l;
3084 int max_size = xg_get_single_size (opcode);
3085
3086 assert (opcode < table->num_opcodes);
3087
3088 for (l = table->table[opcode]; l != NULL; l = l->next)
3089 {
3090 TransitionRule *rule = l->rule;
3091 BuildInstr *build_list;
3092 int this_size = 0;
3093
3094 if (!rule)
3095 continue;
3096 build_list = rule->to_instr;
3097 if (is_unique_insn_expansion (rule))
3098 {
3099 assert (build_list->typ == INSTR_INSTR);
3100 this_size = xg_get_max_insn_widen_size (build_list->opcode);
3101 }
3102 else
3103 for (; build_list != NULL; build_list = build_list->next)
3104 {
3105 switch (build_list->typ)
3106 {
3107 case INSTR_INSTR:
3108 this_size += xg_get_single_size (build_list->opcode);
3109 break;
3110 case INSTR_LITERAL_DEF:
3111 case INSTR_LABEL_DEF:
e0001a05
NC		 3112 default:
3113 break;
3114 }
3115 }
3116 if (this_size > max_size)
3117 max_size = this_size;
3118 }
3119 return max_size;
3120}
3121
3122
3123/* Return the maximum number of literal bytes this opcode can generate. */
3124
7fa3d080
BW		 3125static int
3126xg_get_max_insn_widen_literal_size (xtensa_opcode opcode)
e0001a05 3127{
43cd72b9 3128 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3129 TransitionList *l;
3130 int max_size = 0;
3131
3132 assert (opcode < table->num_opcodes);
3133
3134 for (l = table->table[opcode]; l != NULL; l = l->next)
3135 {
3136 TransitionRule *rule = l->rule;
3137 BuildInstr *build_list;
3138 int this_size = 0;
3139
3140 if (!rule)
3141 continue;
3142 build_list = rule->to_instr;
3143 if (is_unique_insn_expansion (rule))
3144 {
3145 assert (build_list->typ == INSTR_INSTR);
3146 this_size = xg_get_max_insn_widen_literal_size (build_list->opcode);
3147 }
3148 else
3149 for (; build_list != NULL; build_list = build_list->next)
3150 {
3151 switch (build_list->typ)
3152 {
3153 case INSTR_LITERAL_DEF:
43cd72b9 3154 /* Hard-coded 4-byte literal. */
e0001a05
NC		 3155 this_size += 4;
3156 break;
3157 case INSTR_INSTR:
3158 case INSTR_LABEL_DEF:
3159 default:
3160 break;
3161 }
3162 }
3163 if (this_size > max_size)
3164 max_size = this_size;
3165 }
3166 return max_size;
3167}
3168
3169
7fa3d080
BW		 3170static bfd_boolean
3171xg_is_relaxable_insn (TInsn *insn, int lateral_steps)
3172{
3173 int steps_taken = 0;
3174 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3175 TransitionList *l;
3176
3177 assert (insn->insn_type == ITYPE_INSN);
3178 assert (insn->opcode < table->num_opcodes);
3179
3180 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3181 {
3182 TransitionRule *rule = l->rule;
3183
3184 if (xg_instruction_matches_rule (insn, rule))
3185 {
3186 if (steps_taken == lateral_steps)
3187 return TRUE;
3188 steps_taken++;
3189 }
3190 }
3191 return FALSE;
3192}
3193
3194
3195static symbolS *
3196get_special_literal_symbol (void)
3197{
3198 static symbolS *sym = NULL;
3199
3200 if (sym == NULL)
3201 sym = symbol_find_or_make ("SPECIAL_LITERAL0\001");
3202 return sym;
3203}
3204
3205
3206static symbolS *
3207get_special_label_symbol (void)
3208{
3209 static symbolS *sym = NULL;
3210
3211 if (sym == NULL)
3212 sym = symbol_find_or_make ("SPECIAL_LABEL0\001");
3213 return sym;
3214}
3215
3216
3217static bfd_boolean
3218xg_valid_literal_expression (const expressionS *exp)
3219{
3220 switch (exp->X_op)
3221 {
3222 case O_constant:
3223 case O_symbol:
3224 case O_big:
3225 case O_uminus:
3226 case O_subtract:
3227 case O_pltrel:
3228 return TRUE;
3229 default:
3230 return FALSE;
3231 }
3232}
3233
3234
3235/* This will check to see if the value can be converted into the
3236 operand type. It will return TRUE if it does not fit. */
3237
3238static bfd_boolean
3239xg_check_operand (int32 value, xtensa_opcode opcode, int operand)
3240{
3241 uint32 valbuf = value;
3242 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
3243 return TRUE;
3244 return FALSE;
3245}
3246
3247
3248/* Assumes: All immeds are constants. Check that all constants fit
3249 into their immeds; return FALSE if not. */
3250
3251static bfd_boolean
3252xg_immeds_fit (const TInsn *insn)
3253{
3254 xtensa_isa isa = xtensa_default_isa;
3255 int i;
3256
3257 int n = insn->ntok;
3258 assert (insn->insn_type == ITYPE_INSN);
3259 for (i = 0; i < n; ++i)
3260 {
3261 const expressionS *expr = &insn->tok[i];
3262 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3263 continue;
3264
3265 switch (expr->X_op)
3266 {
3267 case O_register:
3268 case O_constant:
3269 if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3270 return FALSE;
3271 break;
3272
3273 default:
3274 /* The symbol should have a fixup associated with it. */
3275 assert (FALSE);
3276 break;
3277 }
3278 }
3279 return TRUE;
3280}
3281
3282
3283/* This should only be called after we have an initial
3284 estimate of the addresses. */
3285
3286static bfd_boolean
3287xg_symbolic_immeds_fit (const TInsn *insn,
3288 segT pc_seg,
3289 fragS *pc_frag,
3290 offsetT pc_offset,
3291 long stretch)
e0001a05 3292{
7fa3d080
BW		 3293 xtensa_isa isa = xtensa_default_isa;
3294 symbolS *symbolP;
3295 fragS *sym_frag;
3296 offsetT target, pc;
3297 uint32 new_offset;
3298 int i;
3299 int n = insn->ntok;
e0001a05
NC		 3300
3301 assert (insn->insn_type == ITYPE_INSN);
e0001a05 3302
7fa3d080 3303 for (i = 0; i < n; ++i)
e0001a05 3304 {
7fa3d080
BW		 3305 const expressionS *expr = &insn->tok[i];
3306 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3307 continue;
e0001a05 3308
7fa3d080 3309 switch (expr->X_op)
e0001a05 3310 {
7fa3d080
BW		 3311 case O_register:
3312 case O_constant:
3313 if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3314 return FALSE;
3315 break;
e0001a05 3316
7fa3d080
BW		 3317 case O_lo16:
3318 case O_hi16:
3319 /* Check for the worst case. */
3320 if (xg_check_operand (0xffff, insn->opcode, i))
3321 return FALSE;
3322 break;
e0001a05 3323
7fa3d080
BW		 3324 case O_symbol:
3325 /* We only allow symbols for pc-relative stuff.
3326 If pc_frag == 0, then we don't have frag locations yet. */
3327 if (pc_frag == 0)
3328 return FALSE;
e0001a05 3329
7fa3d080
BW		 3330 /* If it is PC-relative and the symbol is not in the same
3331 segment as the PC.... */
3332 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0
3333 || S_GET_SEGMENT (expr->X_add_symbol) != pc_seg)
3334 return FALSE;
e0001a05 3335
7fa3d080
BW		 3336 /* If it is a weak symbol, then assume it won't reach. This will
3337 only affect calls when longcalls are enabled, because if
3338 longcalls are disabled, then the call is marked as a specific
3339 opcode. */
3340 if (S_IS_WEAK (expr->X_add_symbol))
3341 return FALSE;
e0001a05 3342
7fa3d080
BW		 3343 symbolP = expr->X_add_symbol;
3344 sym_frag = symbol_get_frag (symbolP);
3345 target = S_GET_VALUE (symbolP) + expr->X_add_number;
3346 pc = pc_frag->fr_address + pc_offset;
e0001a05 3347
7fa3d080
BW		 3348 /* If frag has yet to be reached on this pass, assume it
3349 will move by STRETCH just as we did. If this is not so,
3350 it will be because some frag between grows, and that will
3351 force another pass. Beware zero-length frags. There
3352 should be a faster way to do this. */
3353
3354 if (stretch != 0
3355 && sym_frag->relax_marker != pc_frag->relax_marker
3356 && S_GET_SEGMENT (symbolP) == pc_seg)
3357 {
3358 target += stretch;
3359 }
3360
3361 new_offset = target;
3362 xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
3363 if (xg_check_operand (new_offset, insn->opcode, i))
3364 return FALSE;
3365 break;
3366
3367 default:
3368 /* The symbol should have a fixup associated with it. */
3369 return FALSE;
3370 }
3371 }
3372
3373 return TRUE;
e0001a05
NC		 3374}
3375
3376
43cd72b9 3377/* Return TRUE on success. */
e0001a05 3378
7fa3d080
BW		 3379static bfd_boolean
3380xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
e0001a05
NC		 3381{
3382 BuildOp *op;
3383 symbolS *sym;
3384
3385 memset (targ, 0, sizeof (TInsn));
43cd72b9 3386 targ->loc = insn->loc;
e0001a05
NC		 3387 switch (bi->typ)
3388 {
3389 case INSTR_INSTR:
3390 op = bi->ops;
3391 targ->opcode = bi->opcode;
3392 targ->insn_type = ITYPE_INSN;
3393 targ->is_specific_opcode = FALSE;
3394
3395 for (; op != NULL; op = op->next)
3396 {
3397 int op_num = op->op_num;
3398 int op_data = op->op_data;
3399
3400 assert (op->op_num < MAX_INSN_ARGS);
3401
3402 if (targ->ntok <= op_num)
3403 targ->ntok = op_num + 1;
3404
3405 switch (op->typ)
3406 {
3407 case OP_CONSTANT:
3408 set_expr_const (&targ->tok[op_num], op_data);
3409 break;
3410 case OP_OPERAND:
3411 assert (op_data < insn->ntok);
3412 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3413 break;
3414 case OP_LITERAL:
3415 sym = get_special_literal_symbol ();
3416 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3417 break;
3418 case OP_LABEL:
3419 sym = get_special_label_symbol ();
3420 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3421 break;
43cd72b9
BW		 3422 case OP_OPERAND_HI16U:
3423 case OP_OPERAND_LOW16U:
3424 assert (op_data < insn->ntok);
3425 if (expr_is_const (&insn->tok[op_data]))
3426 {
3427 long val;
3428 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3429 val = xg_apply_userdef_op_fn (op->typ,
3430 targ->tok[op_num].
3431 X_add_number);
3432 targ->tok[op_num].X_add_number = val;
3433 }
3434 else
3435 {
3436 /* For const16 we can create relocations for these. */
3437 if (targ->opcode == XTENSA_UNDEFINED
3438 || (targ->opcode != xtensa_const16_opcode))
3439 return FALSE;
3440 assert (op_data < insn->ntok);
3441 /* Need to build a O_lo16 or O_hi16. */
3442 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3443 if (targ->tok[op_num].X_op == O_symbol)
3444 {
3445 if (op->typ == OP_OPERAND_HI16U)
3446 targ->tok[op_num].X_op = O_hi16;
3447 else if (op->typ == OP_OPERAND_LOW16U)
3448 targ->tok[op_num].X_op = O_lo16;
3449 else
3450 return FALSE;
3451 }
3452 }
3453 break;
e0001a05
NC		 3454 default:
3455 /* currently handles:
3456 OP_OPERAND_LOW8
3457 OP_OPERAND_HI24S
3458 OP_OPERAND_F32MINUS */
3459 if (xg_has_userdef_op_fn (op->typ))
3460 {
3461 assert (op_data < insn->ntok);
3462 if (expr_is_const (&insn->tok[op_data]))
3463 {
3464 long val;
3465 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3466 val = xg_apply_userdef_op_fn (op->typ,
3467 targ->tok[op_num].
3468 X_add_number);
3469 targ->tok[op_num].X_add_number = val;
3470 }
3471 else
3472 return FALSE; /* We cannot use a relocation for this. */
3473 break;
3474 }
3475 assert (0);
3476 break;
3477 }
3478 }
3479 break;
3480
3481 case INSTR_LITERAL_DEF:
3482 op = bi->ops;
3483 targ->opcode = XTENSA_UNDEFINED;
3484 targ->insn_type = ITYPE_LITERAL;
3485 targ->is_specific_opcode = FALSE;
3486 for (; op != NULL; op = op->next)
3487 {
3488 int op_num = op->op_num;
3489 int op_data = op->op_data;
3490 assert (op->op_num < MAX_INSN_ARGS);
3491
3492 if (targ->ntok <= op_num)
3493 targ->ntok = op_num + 1;
3494
3495 switch (op->typ)
3496 {
3497 case OP_OPERAND:
3498 assert (op_data < insn->ntok);
43cd72b9
BW		 3499 /* We can only pass resolvable literals through. */
3500 if (!xg_valid_literal_expression (&insn->tok[op_data]))
3501 return FALSE;
e0001a05
NC		 3502 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3503 break;
3504 case OP_LITERAL:
3505 case OP_CONSTANT:
3506 case OP_LABEL:
3507 default:
3508 assert (0);
3509 break;
3510 }
3511 }
3512 break;
3513
3514 case INSTR_LABEL_DEF:
3515 op = bi->ops;
3516 targ->opcode = XTENSA_UNDEFINED;
3517 targ->insn_type = ITYPE_LABEL;
3518 targ->is_specific_opcode = FALSE;
43cd72b9 3519 /* Literal with no ops is a label? */
e0001a05
NC		 3520 assert (op == NULL);
3521 break;
3522
3523 default:
3524 assert (0);
3525 }
3526
3527 return TRUE;
3528}
3529
3530
43cd72b9 3531/* Return TRUE on success. */
e0001a05 3532
7fa3d080
BW		 3533static bfd_boolean
3534xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi)
e0001a05
NC		 3535{
3536 for (; bi != NULL; bi = bi->next)
3537 {
3538 TInsn *next_insn = istack_push_space (istack);
3539
3540 if (!xg_build_to_insn (next_insn, insn, bi))
3541 return FALSE;
3542 }
3543 return TRUE;
3544}
3545
3546
43cd72b9 3547/* Return TRUE on valid expansion. */
e0001a05 3548
7fa3d080
BW		 3549static bfd_boolean
3550xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
e0001a05
NC		 3551{
3552 int stack_size = istack->ninsn;
3553 int steps_taken = 0;
43cd72b9 3554 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3555 TransitionList *l;
3556
3557 assert (insn->insn_type == ITYPE_INSN);
3558 assert (insn->opcode < table->num_opcodes);
3559
3560 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3561 {
3562 TransitionRule *rule = l->rule;
3563
3564 if (xg_instruction_matches_rule (insn, rule))
3565 {
3566 if (lateral_steps == steps_taken)
3567 {
3568 int i;
3569
3570 /* This is it. Expand the rule to the stack. */
3571 if (!xg_build_to_stack (istack, insn, rule->to_instr))
3572 return FALSE;
3573
3574 /* Check to see if it fits. */
3575 for (i = stack_size; i < istack->ninsn; i++)
3576 {
3577 TInsn *insn = &istack->insn[i];
3578
3579 if (insn->insn_type == ITYPE_INSN
3580 && !tinsn_has_symbolic_operands (insn)
3581 && !xg_immeds_fit (insn))
3582 {
3583 istack->ninsn = stack_size;
3584 return FALSE;
3585 }
3586 }
3587 return TRUE;
3588 }
3589 steps_taken++;
3590 }
3591 }
3592 return FALSE;
3593}
3594
3595
7fa3d080
BW		 3596static bfd_boolean
3597xg_expand_narrow (TInsn *targ, TInsn *insn)
e0001a05 3598{
43cd72b9 3599 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3600 TransitionList *l;
3601
3602 assert (insn->insn_type == ITYPE_INSN);
3603 assert (insn->opcode < table->num_opcodes);
3604
3605 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3606 {
3607 TransitionRule *rule = l->rule;
3608 if (xg_instruction_matches_rule (insn, rule)
3609 && is_unique_insn_expansion (rule))
3610 {
3611 /* Is it a larger instruction? */
43cd72b9 3612 if (xg_get_single_size (insn->opcode)
e0001a05
NC		 3613 <= xg_get_build_instr_size (rule->to_instr))
3614 {
3615 xg_build_to_insn (targ, insn, rule->to_instr);
3616 return FALSE;
3617 }
3618 }
3619 }
3620 return TRUE;
3621}
3622
43cd72b9 3623\f
43cd72b9
BW		 3624/* Relax the assembly instruction at least "min_steps".
3625 Return the number of steps taken. */
e0001a05 3626
7fa3d080
BW		 3627static int
3628xg_assembly_relax (IStack *istack,
3629 TInsn *insn,
3630 segT pc_seg,
3631 fragS *pc_frag, /* if pc_frag == 0, not pc-relative */
3632 offsetT pc_offset, /* offset in fragment */
3633 int min_steps, /* minimum conversion steps */
3634 long stretch) /* number of bytes stretched so far */
e0001a05
NC		 3635{
3636 int steps_taken = 0;
3637
3638 /* assert (has no symbolic operands)
3639 Some of its immeds don't fit.
3640 Try to build a relaxed version.
3641 This may go through a couple of stages
3642 of single instruction transformations before
3643 we get there. */
3644
3645 TInsn single_target;
3646 TInsn current_insn;
3647 int lateral_steps = 0;
3648 int istack_size = istack->ninsn;
3649
3650 if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
3651 && steps_taken >= min_steps)
3652 {
3653 istack_push (istack, insn);
3654 return steps_taken;
3655 }
43cd72b9 3656 current_insn = *insn;
e0001a05
NC		 3657
3658 /* Walk through all of the single instruction expansions. */
3659 while (xg_is_single_relaxable_insn (&current_insn))
3660 {
3661 int error_val = xg_expand_narrow (&single_target, &current_insn);
3662
3663 assert (!error_val);
3664
3665 if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
3666 stretch))
3667 {
3668 steps_taken++;
3669 if (steps_taken >= min_steps)
3670 {
3671 istack_push (istack, &single_target);
3672 return steps_taken;
3673 }
3674 }
43cd72b9 3675 current_insn = single_target;
e0001a05
NC		 3676 }
3677
3678 /* Now check for a multi-instruction expansion. */
3679 while (xg_is_relaxable_insn (&current_insn, lateral_steps))
3680 {
3681 if (xg_symbolic_immeds_fit (&current_insn, pc_seg, pc_frag, pc_offset,
3682 stretch))
3683 {
3684 if (steps_taken >= min_steps)
3685 {
3686 istack_push (istack, &current_insn);
3687 return steps_taken;
3688 }
3689 }
3690 steps_taken++;
3691 if (xg_expand_to_stack (istack, &current_insn, lateral_steps))
3692 {
3693 if (steps_taken >= min_steps)
3694 return steps_taken;
3695 }
3696 lateral_steps++;
3697 istack->ninsn = istack_size;
3698 }
3699
3700 /* It's not going to work -- use the original. */
3701 istack_push (istack, insn);
3702 return steps_taken;
3703}
3704
3705
3706static void
7fa3d080 3707xg_force_frag_space (int size)
e0001a05
NC		 3708{
3709 /* This may have the side effect of creating a new fragment for the
3710 space to go into. I just do not like the name of the "frag"
3711 functions. */
3712 frag_grow (size);
3713}
3714
3715
7fa3d080
BW		 3716static void
3717xg_finish_frag (char *last_insn,
3718 enum xtensa_relax_statesE frag_state,
3719 enum xtensa_relax_statesE slot0_state,
3720 int max_growth,
3721 bfd_boolean is_insn)
e0001a05
NC		 3722{
3723 /* Finish off this fragment so that it has at LEAST the desired
3724 max_growth. If it doesn't fit in this fragment, close this one
3725 and start a new one. In either case, return a pointer to the
3726 beginning of the growth area. */
3727
3728 fragS *old_frag;
43cd72b9 3729
e0001a05
NC		 3730 xg_force_frag_space (max_growth);
3731
3732 old_frag = frag_now;
3733
3734 frag_now->fr_opcode = last_insn;
3735 if (is_insn)
3736 frag_now->tc_frag_data.is_insn = TRUE;
3737
3738 frag_var (rs_machine_dependent, max_growth, max_growth,
43cd72b9
BW		 3739 frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
3740
3741 old_frag->tc_frag_data.slot_subtypes[0] = slot0_state;
3742 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 3743
3744 /* Just to make sure that we did not split it up. */
3745 assert (old_frag->fr_next == frag_now);
3746}
3747
3748
7fa3d080
BW		 3749/* Return TRUE if the target frag is one of the next non-empty frags. */
3750
3751static bfd_boolean
3752is_next_frag_target (const fragS *fragP, const fragS *target)
3753{
3754 if (fragP == NULL)
3755 return FALSE;
3756
3757 for (; fragP; fragP = fragP->fr_next)
3758 {
3759 if (fragP == target)
3760 return TRUE;
3761 if (fragP->fr_fix != 0)
3762 return FALSE;
3763 if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
3764 return FALSE;
3765 if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
3766 && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
3767 return FALSE;
3768 if (fragP->fr_type == rs_space)
3769 return FALSE;
3770 }
3771 return FALSE;
3772}
3773
3774
e0001a05 3775static bfd_boolean
7fa3d080 3776is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
e0001a05
NC		 3777{
3778 xtensa_isa isa = xtensa_default_isa;
3779 int i;
43cd72b9 3780 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
e0001a05
NC		 3781 int target_op = -1;
3782 symbolS *sym;
3783 fragS *target_frag;
3784
43cd72b9
BW		 3785 if (xtensa_opcode_is_branch (isa, insn->opcode) == 0
3786 && xtensa_opcode_is_jump (isa, insn->opcode) == 0)
e0001a05
NC		 3787 return FALSE;
3788
3789 for (i = 0; i < num_ops; i++)
3790 {
43cd72b9 3791 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1)
e0001a05
NC		 3792 {
3793 target_op = i;
3794 break;
3795 }
3796 }
3797 if (target_op == -1)
3798 return FALSE;
3799
3800 if (insn->ntok <= target_op)
3801 return FALSE;
3802
3803 if (insn->tok[target_op].X_op != O_symbol)
3804 return FALSE;
3805
3806 sym = insn->tok[target_op].X_add_symbol;
3807 if (sym == NULL)
3808 return FALSE;
3809
3810 if (insn->tok[target_op].X_add_number != 0)
3811 return FALSE;
3812
3813 target_frag = symbol_get_frag (sym);
3814 if (target_frag == NULL)
3815 return FALSE;
3816
3817 if (is_next_frag_target (fragP->fr_next, target_frag)
3818 && S_GET_VALUE (sym) == target_frag->fr_address)
3819 return TRUE;
3820
3821 return FALSE;
3822}
3823
3824
3825static void
7fa3d080 3826xg_add_branch_and_loop_targets (TInsn *insn)
e0001a05
NC		 3827{
3828 xtensa_isa isa = xtensa_default_isa;
7fa3d080 3829 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
43cd72b9 3830
7fa3d080
BW		 3831 if (xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3832 {
3833 int i = 1;
3834 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3835 && insn->tok[i].X_op == O_symbol)
3836 symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
3837 return;
3838 }
e0001a05 3839
7fa3d080
BW		 3840 if (xtensa_opcode_is_branch (isa, insn->opcode) == 1
3841 || xtensa_opcode_is_loop (isa, insn->opcode) == 1)
e0001a05 3842 {
7fa3d080
BW		 3843 int i;
3844
3845 for (i = 0; i < insn->ntok && i < num_ops; i++)
3846 {
3847 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3848 && insn->tok[i].X_op == O_symbol)
3849 {
3850 symbolS *sym = insn->tok[i].X_add_symbol;
3851 symbol_get_tc (sym)->is_branch_target = TRUE;
3852 if (S_IS_DEFINED (sym))
3853 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
3854 }
3855 }
e0001a05 3856 }
e0001a05
NC		 3857}
3858
3859
43cd72b9 3860/* Return FALSE if no error. */
e0001a05 3861
7fa3d080
BW		 3862static bfd_boolean
3863xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn)
e0001a05
NC		 3864{
3865 int num_ops = 0;
3866 BuildOp *b_op;
3867
3868 switch (instr_spec->typ)
3869 {
3870 case INSTR_INSTR:
3871 new_insn->insn_type = ITYPE_INSN;
3872 new_insn->opcode = instr_spec->opcode;
3873 new_insn->is_specific_opcode = FALSE;
43cd72b9 3874 new_insn->loc = old_insn->loc;
e0001a05
NC		 3875 break;
3876 case INSTR_LITERAL_DEF:
3877 new_insn->insn_type = ITYPE_LITERAL;
3878 new_insn->opcode = XTENSA_UNDEFINED;
3879 new_insn->is_specific_opcode = FALSE;
43cd72b9 3880 new_insn->loc = old_insn->loc;
e0001a05
NC		 3881 break;
3882 case INSTR_LABEL_DEF:
3883 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3884 break;
3885 }
3886
3887 for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next)
3888 {
3889 expressionS *exp;
3890 const expressionS *src_exp;
3891
3892 num_ops++;
3893 switch (b_op->typ)
3894 {
3895 case OP_CONSTANT:
3896 /* The expression must be the constant. */
3897 assert (b_op->op_num < MAX_INSN_ARGS);
3898 exp = &new_insn->tok[b_op->op_num];
3899 set_expr_const (exp, b_op->op_data);
3900 break;
3901
3902 case OP_OPERAND:
3903 assert (b_op->op_num < MAX_INSN_ARGS);
3904 assert (b_op->op_data < (unsigned) old_insn->ntok);
3905 src_exp = &old_insn->tok[b_op->op_data];
3906 exp = &new_insn->tok[b_op->op_num];
3907 copy_expr (exp, src_exp);
3908 break;
3909
3910 case OP_LITERAL:
3911 case OP_LABEL:
3912 as_bad (_("can't handle generation of literal/labels yet"));
3913 assert (0);
3914
3915 default:
3916 as_bad (_("can't handle undefined OP TYPE"));
3917 assert (0);
3918 }
3919 }
3920
3921 new_insn->ntok = num_ops;
3922 return FALSE;
3923}
3924
3925
43cd72b9 3926/* Return TRUE if it was simplified. */
e0001a05 3927
7fa3d080
BW		 3928static bfd_boolean
3929xg_simplify_insn (TInsn *old_insn, TInsn *new_insn)
e0001a05 3930{
43cd72b9 3931 TransitionRule *rule;
e0001a05 3932 BuildInstr *insn_spec;
43cd72b9
BW		 3933
3934 if (old_insn->is_specific_opcode || !density_supported)
3935 return FALSE;
3936
3937 rule = xg_instruction_match (old_insn);
e0001a05
NC		 3938 if (rule == NULL)
3939 return FALSE;
3940
3941 insn_spec = rule->to_instr;
3942 /* There should only be one. */
3943 assert (insn_spec != NULL);
3944 assert (insn_spec->next == NULL);
3945 if (insn_spec->next != NULL)
3946 return FALSE;
3947
3948 xg_build_token_insn (insn_spec, old_insn, new_insn);
3949
3950 return TRUE;
3951}
3952
3953
3954/* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3955 l32i.n. (2) Check the number of operands. (3) Place the instruction
3956 tokens into the stack or if we can relax it at assembly time, place
43cd72b9 3957 multiple instructions/literals onto the stack. Return FALSE if no
e0001a05
NC		 3958 error. */
3959
3960static bfd_boolean
7fa3d080 3961xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
e0001a05
NC		 3962{
3963 int noperands;
3964 TInsn new_insn;
3965 memset (&new_insn, 0, sizeof (TInsn));
3966
43cd72b9
BW		 3967 /* Narrow it if we can. xg_simplify_insn now does all the
3968 appropriate checking (e.g., for the density option). */
3969 if (xg_simplify_insn (orig_insn, &new_insn))
3970 orig_insn = &new_insn;
e0001a05 3971
43cd72b9
BW		 3972 noperands = xtensa_opcode_num_operands (xtensa_default_isa,
3973 orig_insn->opcode);
e0001a05
NC		 3974 if (orig_insn->ntok < noperands)
3975 {
3976 as_bad (_("found %d operands for '%s': Expected %d"),
3977 orig_insn->ntok,
3978 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
3979 noperands);
3980 return TRUE;
3981 }
3982 if (orig_insn->ntok > noperands)
3983 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3984 orig_insn->ntok,
3985 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
3986 noperands);
3987
43cd72b9 3988 /* If there are not enough operands, we will assert above. If there
e0001a05
NC		 3989 are too many, just cut out the extras here. */
3990
3991 orig_insn->ntok = noperands;
3992
43cd72b9 3993 /* Cases:
e0001a05
NC		 3994
3995 Instructions with all constant immeds:
3996 Assemble them and relax the instruction if possible.
3997 Give error if not possible; no fixup needed.
3998
3999 Instructions with symbolic immeds:
4000 Assemble them with a Fix up (that may cause instruction expansion).
43cd72b9
BW		 4001 Also close out the fragment if the fixup may cause instruction expansion.
4002
e0001a05
NC		 4003 There are some other special cases where we need alignment.
4004 1) before certain instructions with required alignment (OPCODE_ALIGN)
4005 2) before labels that have jumps (LABEL_ALIGN)
4006 3) after call instructions (RETURN_ALIGN)
43cd72b9
BW		 4007 Multiple of these may be possible on the same fragment.
4008 If so, make sure to satisfy the required alignment.
e0001a05
NC		 4009 Then try to get the desired alignment. */
4010
4011 if (tinsn_has_invalid_symbolic_operands (orig_insn))
4012 return TRUE;
4013
43cd72b9 4014 if (orig_insn->is_specific_opcode || !use_transform ())
e0001a05
NC		 4015 {
4016 istack_push (istack, orig_insn);
4017 return FALSE;
4018 }
4019
4020 if (tinsn_has_symbolic_operands (orig_insn))
4021 {
4022 if (tinsn_has_complex_operands (orig_insn))
4023 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4024 else
4025 istack_push (istack, orig_insn);
4026 }
4027 else
4028 {
4029 if (xg_immeds_fit (orig_insn))
4030 istack_push (istack, orig_insn);
4031 else
4032 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4033 }
4034
e0001a05
NC		 4035 return FALSE;
4036}
4037
4038
7fa3d080
BW		 4039/* Return TRUE if the section flags are marked linkonce
4040 or the name is .gnu.linkonce*. */
4041
4042static bfd_boolean
4043get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
4044{
4045 flagword flags, link_once_flags;
4046
4047 flags = bfd_get_section_flags (abfd, sec);
4048 link_once_flags = (flags & SEC_LINK_ONCE);
4049
4050 /* Flags might not be set yet. */
4051 if (!link_once_flags)
4052 {
4053 static size_t len = sizeof ".gnu.linkonce.t.";
4054
4055 if (strncmp (segment_name (sec), ".gnu.linkonce.t.", len - 1) == 0)
4056 link_once_flags = SEC_LINK_ONCE;
4057 }
4058 return (link_once_flags != 0);
4059}
4060
4061
4062static void
4063xtensa_add_literal_sym (symbolS *sym)
4064{
4065 sym_list *l;
4066
4067 l = (sym_list *) xmalloc (sizeof (sym_list));
4068 l->sym = sym;
4069 l->next = literal_syms;
4070 literal_syms = l;
4071}
4072
4073
4074static symbolS *
4075xtensa_create_literal_symbol (segT sec, fragS *frag)
4076{
4077 static int lit_num = 0;
4078 static char name[256];
4079 symbolS *symbolP;
4080
4081 sprintf (name, ".L_lit_sym%d", lit_num);
4082
4083 /* Create a local symbol. If it is in a linkonce section, we have to
4084 be careful to make sure that if it is used in a relocation that the
4085 symbol will be in the output file. */
4086 if (get_is_linkonce_section (stdoutput, sec))
4087 {
4088 symbolP = symbol_new (name, sec, 0, frag);
4089 S_CLEAR_EXTERNAL (symbolP);
4090 /* symbolP->local = 1; */
4091 }
4092 else
4093 symbolP = symbol_new (name, sec, 0, frag);
4094
4095 xtensa_add_literal_sym (symbolP);
4096
4097 frag->tc_frag_data.is_literal = TRUE;
4098 lit_num++;
4099 return symbolP;
4100}
4101
4102
e0001a05
NC		 4103/* Currently all literals that are generated here are 32-bit L32R targets. */
4104
7fa3d080
BW		 4105static symbolS *
4106xg_assemble_literal (/* const */ TInsn *insn)
e0001a05
NC		 4107{
4108 emit_state state;
4109 symbolS *lit_sym = NULL;
4110
4111 /* size = 4 for L32R. It could easily be larger when we move to
4112 larger constants. Add a parameter later. */
4113 offsetT litsize = 4;
4114 offsetT litalign = 2; /* 2^2 = 4 */
4115 expressionS saved_loc;
43cd72b9
BW		 4116 expressionS * emit_val;
4117
e0001a05
NC		 4118 set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
4119
4120 assert (insn->insn_type == ITYPE_LITERAL);
77cd6497 4121 assert (insn->ntok == 1); /* must be only one token here */
e0001a05
NC		 4122
4123 xtensa_switch_to_literal_fragment (&state);
4124
43cd72b9
BW		 4125 emit_val = &insn->tok[0];
4126 if (emit_val->X_op == O_big)
4127 {
4128 int size = emit_val->X_add_number * CHARS_PER_LITTLENUM;
4129 if (size > litsize)
4130 {
4131 /* This happens when someone writes a "movi a2, big_number". */
4132 as_bad_where (frag_now->fr_file, frag_now->fr_line,
4133 _("invalid immediate"));
4134 xtensa_restore_emit_state (&state);
4135 return NULL;
4136 }
4137 }
4138
e0001a05
NC		 4139 /* Force a 4-byte align here. Note that this opens a new frag, so all
4140 literals done with this function have a frag to themselves. That's
4141 important for the way text section literals work. */
4142 frag_align (litalign, 0, 0);
43cd72b9 4143 record_alignment (now_seg, litalign);
e0001a05 4144
43cd72b9
BW		 4145 if (emit_val->X_op == O_pltrel)
4146 {
4147 char *p = frag_more (litsize);
4148 xtensa_set_frag_assembly_state (frag_now);
4149 if (emit_val->X_add_symbol)
4150 emit_val->X_op = O_symbol;
4151 else
4152 emit_val->X_op = O_constant;
4153 fix_new_exp (frag_now, p - frag_now->fr_literal,
4154 litsize, emit_val, 0, BFD_RELOC_XTENSA_PLT);
4155 }
4156 else
4157 emit_expr (emit_val, litsize);
e0001a05
NC		 4158
4159 assert (frag_now->tc_frag_data.literal_frag == NULL);
4160 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4161 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4162 lit_sym = frag_now->fr_symbol;
4163 frag_now->tc_frag_data.is_literal = TRUE;
4164
4165 /* Go back. */
4166 xtensa_restore_emit_state (&state);
4167 return lit_sym;
4168}
4169
4170
4171static void
7fa3d080 4172xg_assemble_literal_space (/* const */ int size, int slot)
e0001a05
NC		 4173{
4174 emit_state state;
43cd72b9 4175 /* We might have to do something about this alignment. It only
e0001a05
NC		 4176 takes effect if something is placed here. */
4177 offsetT litalign = 2; /* 2^2 = 4 */
4178 fragS *lit_saved_frag;
4179
e0001a05 4180 assert (size % 4 == 0);
e0001a05
NC		 4181
4182 xtensa_switch_to_literal_fragment (&state);
4183
4184 /* Force a 4-byte align here. */
4185 frag_align (litalign, 0, 0);
43cd72b9 4186 record_alignment (now_seg, litalign);
e0001a05
NC		 4187
4188 xg_force_frag_space (size);
4189
4190 lit_saved_frag = frag_now;
4191 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4192 frag_now->tc_frag_data.is_literal = TRUE;
4193 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
43cd72b9 4194 xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE);
e0001a05
NC		 4195
4196 /* Go back. */
4197 xtensa_restore_emit_state (&state);
43cd72b9 4198 frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag;
e0001a05
NC		 4199}
4200
4201
e0001a05 4202/* Put in a fixup record based on the opcode.
43cd72b9 4203 Return TRUE on success. */
e0001a05 4204
7fa3d080
BW		 4205static bfd_boolean
4206xg_add_opcode_fix (TInsn *tinsn,
4207 int opnum,
4208 xtensa_format fmt,
4209 int slot,
4210 expressionS *expr,
4211 fragS *fragP,
4212 offsetT offset)
43cd72b9
BW		 4213{
4214 xtensa_opcode opcode = tinsn->opcode;
4215 bfd_reloc_code_real_type reloc;
4216 reloc_howto_type *howto;
4217 int fmt_length;
e0001a05
NC		 4218 fixS *the_fix;
4219
43cd72b9
BW		 4220 reloc = BFD_RELOC_NONE;
4221
4222 /* First try the special cases for "alternate" relocs. */
4223 if (opcode == xtensa_l32r_opcode)
4224 {
4225 if (fragP->tc_frag_data.use_absolute_literals)
4226 reloc = encode_alt_reloc (slot);
4227 }
4228 else if (opcode == xtensa_const16_opcode)
4229 {
4230 if (expr->X_op == O_lo16)
4231 {
4232 reloc = encode_reloc (slot);
4233 expr->X_op = O_symbol;
4234 }
4235 else if (expr->X_op == O_hi16)
4236 {
4237 reloc = encode_alt_reloc (slot);
4238 expr->X_op = O_symbol;
4239 }
4240 }
4241
4242 if (opnum != get_relaxable_immed (opcode))
e0001a05 4243 {
43cd72b9 4244 as_bad (_("invalid relocation for operand %i of '%s'"),
e0001a05
NC		 4245 opnum, xtensa_opcode_name (xtensa_default_isa, opcode));
4246 return FALSE;
4247 }
4248
43cd72b9
BW		 4249 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4250 into the symbol table where the generic portions of the assembler
4251 won't know what to do with them. */
4252 if (expr->X_op == O_lo16 || expr->X_op == O_hi16)
4253 {
4254 as_bad (_("invalid expression for operand %i of '%s'"),
4255 opnum, xtensa_opcode_name (xtensa_default_isa, opcode));
4256 return FALSE;
4257 }
4258
4259 /* Next try the generic relocs. */
4260 if (reloc == BFD_RELOC_NONE)
4261 reloc = encode_reloc (slot);
4262 if (reloc == BFD_RELOC_NONE)
4263 {
4264 as_bad (_("invalid relocation in instruction slot %i"), slot);
4265 return FALSE;
4266 }
e0001a05 4267
43cd72b9 4268 howto = bfd_reloc_type_lookup (stdoutput, reloc);
e0001a05
NC		 4269 if (!howto)
4270 {
43cd72b9 4271 as_bad (_("undefined symbol for opcode \"%s\""),
e0001a05
NC		 4272 xtensa_opcode_name (xtensa_default_isa, opcode));
4273 return FALSE;
4274 }
4275
43cd72b9
BW		 4276 fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
4277 the_fix = fix_new_exp (fragP, offset, fmt_length, expr,
e0001a05
NC		 4278 howto->pc_relative, reloc);
4279
7fa3d080
BW		 4280 if (expr->X_add_symbol
4281 && (S_IS_EXTERNAL (expr->X_add_symbol)
4282 || S_IS_WEAK (expr->X_add_symbol)))
4283 the_fix->fx_plt = TRUE;
4284
4285 the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol;
4286 the_fix->tc_fix_data.X_add_number = expr->X_add_number;
4287 the_fix->tc_fix_data.slot = slot;
4288
4289 return TRUE;
4290}
4291
4292
4293static bfd_boolean
4294xg_emit_insn_to_buf (TInsn *tinsn,
4295 xtensa_format fmt,
4296 char *buf,
4297 fragS *fragP,
4298 offsetT offset,
4299 bfd_boolean build_fix)
4300{
4301 static xtensa_insnbuf insnbuf = NULL;
4302 bfd_boolean has_symbolic_immed = FALSE;
4303 bfd_boolean ok = TRUE;
4304 if (!insnbuf)
4305 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4306
4307 has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf);
4308 if (has_symbolic_immed && build_fix)
4309 {
4310 /* Add a fixup. */
4311 int opnum = get_relaxable_immed (tinsn->opcode);
4312 expressionS *exp = &tinsn->tok[opnum];
43cd72b9 4313
7fa3d080
BW		 4314 if (!xg_add_opcode_fix (tinsn, opnum, fmt, 0, exp, fragP, offset))
4315 ok = FALSE;
4316 }
4317 fragP->tc_frag_data.is_insn = TRUE;
4318 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, buf, 0);
4319 return ok;
e0001a05
NC		 4320}
4321
4322
7fa3d080
BW		 4323static void
4324xg_resolve_literals (TInsn *insn, symbolS *lit_sym)
e0001a05
NC		 4325{
4326 symbolS *sym = get_special_literal_symbol ();
4327 int i;
4328 if (lit_sym == 0)
4329 return;
4330 assert (insn->insn_type == ITYPE_INSN);
4331 for (i = 0; i < insn->ntok; i++)
4332 if (insn->tok[i].X_add_symbol == sym)
4333 insn->tok[i].X_add_symbol = lit_sym;
4334
4335}
4336
4337
7fa3d080
BW		 4338static void
4339xg_resolve_labels (TInsn *insn, symbolS *label_sym)
e0001a05
NC		 4340{
4341 symbolS *sym = get_special_label_symbol ();
4342 int i;
43cd72b9 4343 /* assert (!insn->is_literal); */
e0001a05
NC		 4344 for (i = 0; i < insn->ntok; i++)
4345 if (insn->tok[i].X_add_symbol == sym)
4346 insn->tok[i].X_add_symbol = label_sym;
4347
4348}
4349
4350
43cd72b9 4351/* Return TRUE if the instruction can write to the specified
e0001a05
NC		 4352 integer register. */
4353
4354static bfd_boolean
7fa3d080 4355is_register_writer (const TInsn *insn, const char *regset, int regnum)
e0001a05
NC		 4356{
4357 int i;
4358 int num_ops;
4359 xtensa_isa isa = xtensa_default_isa;
4360
43cd72b9 4361 num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
e0001a05
NC		 4362
4363 for (i = 0; i < num_ops; i++)
4364 {
43cd72b9
BW		 4365 char inout;
4366 inout = xtensa_operand_inout (isa, insn->opcode, i);
4367 if ((inout == 'o' || inout == 'm')
4368 && xtensa_operand_is_register (isa, insn->opcode, i) == 1)
e0001a05 4369 {
43cd72b9
BW		 4370 xtensa_regfile opnd_rf =
4371 xtensa_operand_regfile (isa, insn->opcode, i);
4372 if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset))
e0001a05
NC		 4373 {
4374 if ((insn->tok[i].X_op == O_register)
4375 && (insn->tok[i].X_add_number == regnum))
4376 return TRUE;
4377 }
4378 }
4379 }
4380 return FALSE;
4381}
4382
4383
4384static bfd_boolean
7fa3d080 4385is_bad_loopend_opcode (const TInsn *tinsn)
e0001a05
NC		 4386{
4387 xtensa_opcode opcode = tinsn->opcode;
4388
4389 if (opcode == XTENSA_UNDEFINED)
4390 return FALSE;
4391
4392 if (opcode == xtensa_call0_opcode
4393 || opcode == xtensa_callx0_opcode
4394 || opcode == xtensa_call4_opcode
4395 || opcode == xtensa_callx4_opcode
4396 || opcode == xtensa_call8_opcode
4397 || opcode == xtensa_callx8_opcode
4398 || opcode == xtensa_call12_opcode
4399 || opcode == xtensa_callx12_opcode
4400 || opcode == xtensa_isync_opcode
4401 || opcode == xtensa_ret_opcode
4402 || opcode == xtensa_ret_n_opcode
4403 || opcode == xtensa_retw_opcode
4404 || opcode == xtensa_retw_n_opcode
43cd72b9
BW		 4405 || opcode == xtensa_waiti_opcode
4406 || opcode == xtensa_rsr_lcount_opcode)
e0001a05
NC		 4407 return TRUE;
4408
e0001a05
NC		 4409 return FALSE;
4410}
4411
4412
4413/* Labels that begin with ".Ln" or ".LM" are unaligned.
4414 This allows the debugger to add unaligned labels.
4415 Also, the assembler generates stabs labels that need
4416 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4417
7fa3d080
BW		 4418static bfd_boolean
4419is_unaligned_label (symbolS *sym)
e0001a05
NC		 4420{
4421 const char *name = S_GET_NAME (sym);
4422 static size_t fake_size = 0;
4423
4424 if (name
4425 && name[0] == '.'
4426 && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M'))
4427 return TRUE;
4428
4429 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4430 if (fake_size == 0)
4431 fake_size = strlen (FAKE_LABEL_NAME);
4432
43cd72b9 4433 if (name
e0001a05
NC		 4434 && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0
4435 && (name[fake_size] == 'F'
4436 || name[fake_size] == 'L'
4437 || (name[fake_size] == 'e'
4438 && strncmp ("endfunc", name+fake_size, 7) == 0)))
4439 return TRUE;
4440
4441 return FALSE;
4442}
4443
4444
7fa3d080
BW		 4445static fragS *
4446next_non_empty_frag (const fragS *fragP)
e0001a05
NC		 4447{
4448 fragS *next_fragP = fragP->fr_next;
4449
4450 /* Sometimes an empty will end up here due storage allocation issues.
4451 So we have to skip until we find something legit. */
4452 while (next_fragP && next_fragP->fr_fix == 0)
4453 next_fragP = next_fragP->fr_next;
4454
4455 if (next_fragP == NULL || next_fragP->fr_fix == 0)
4456 return NULL;
4457
4458 return next_fragP;
4459}
4460
4461
43cd72b9 4462static bfd_boolean
7fa3d080 4463next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode)
43cd72b9
BW		 4464{
4465 xtensa_opcode out_opcode;
4466 const fragS *next_fragP = next_non_empty_frag (fragP);
4467
4468 if (next_fragP == NULL)
4469 return FALSE;
4470
4471 out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
4472 if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
4473 {
4474 *opcode = out_opcode;
4475 return TRUE;
4476 }
4477 return FALSE;
4478}
4479
4480
4481static int
7fa3d080 4482frag_format_size (const fragS *fragP)
43cd72b9 4483{
e0001a05
NC		 4484 static xtensa_insnbuf insnbuf = NULL;
4485 xtensa_isa isa = xtensa_default_isa;
43cd72b9
BW		 4486 xtensa_format fmt;
4487 int fmt_size;
e0001a05
NC		 4488
4489 if (!insnbuf)
4490 insnbuf = xtensa_insnbuf_alloc (isa);
4491
43cd72b9
BW		 4492 if (fragP == NULL)
4493 return XTENSA_UNDEFINED;
4494
4495 xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal, 0);
4496
4497 fmt = xtensa_format_decode (isa, insnbuf);
4498 if (fmt == XTENSA_UNDEFINED)
e0001a05 4499 return XTENSA_UNDEFINED;
43cd72b9
BW		 4500 fmt_size = xtensa_format_length (isa, fmt);
4501
4502 /* If the next format won't be changing due to relaxation, just
4503 return the length of the first format. */
4504 if (fragP->fr_opcode != fragP->fr_literal)
4505 return fmt_size;
4506
4507 /* If during relaxation we have to pull an instruction out of a
4508 multi-slot instruction, we will return the more conservative
4509 number. This works because alignment on bigger instructions
4510 is more restrictive than alignment on smaller instructions.
4511 This is more conservative than we would like, but it happens
4512 infrequently. */
4513
4514 if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1)
4515 return fmt_size;
4516
4517 /* If we aren't doing one of our own relaxations or it isn't
4518 slot-based, then the insn size won't change. */
4519 if (fragP->fr_type != rs_machine_dependent)
4520 return fmt_size;
4521 if (fragP->fr_subtype != RELAX_SLOTS)
4522 return fmt_size;
4523
4524 /* If an instruction is about to grow, return the longer size. */
4525 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
4526 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2)
4527 return 3;
4528
4529 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
4530 return 2 + fragP->tc_frag_data.text_expansion[0];
e0001a05 4531
43cd72b9 4532 return fmt_size;
e0001a05
NC		 4533}
4534
4535
7fa3d080
BW		 4536static int
4537next_frag_format_size (const fragS *fragP)
e0001a05 4538{
7fa3d080
BW		 4539 const fragS *next_fragP = next_non_empty_frag (fragP);
4540 return frag_format_size (next_fragP);
e0001a05
NC		 4541}
4542
4543
4544/* If the next legit fragment is an end-of-loop marker,
4545 switch its state so it will instantiate a NOP. */
4546
4547static void
7fa3d080 4548update_next_frag_state (fragS *fragP, bfd_boolean unreachable)
e0001a05
NC		 4549{
4550 fragS *next_fragP = fragP->fr_next;
43cd72b9 4551 fragS *new_target = NULL;
e0001a05 4552
43cd72b9
BW		 4553 if (align_targets)
4554 {
4555 /* We are guaranteed there will be one of these... */
4556 while (!(next_fragP->fr_type == rs_machine_dependent
4557 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4558 || next_fragP->fr_subtype == RELAX_UNREACHABLE)))
4559 next_fragP = next_fragP->fr_next;
4560
4561 assert (next_fragP->fr_type == rs_machine_dependent
4562 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4563 || next_fragP->fr_subtype == RELAX_UNREACHABLE));
4564
4565 /* ...and one of these. */
4566 new_target = next_fragP->fr_next;
4567 while (!(new_target->fr_type == rs_machine_dependent
4568 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4569 || new_target->fr_subtype == RELAX_DESIRE_ALIGN)))
4570 new_target = new_target->fr_next;
4571
4572 assert (new_target->fr_type == rs_machine_dependent
4573 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4574 || new_target->fr_subtype == RELAX_DESIRE_ALIGN));
4575 }
4576 if (unreachable)
e0001a05 4577 {
43cd72b9 4578 if (align_targets)
e0001a05 4579 {
43cd72b9
BW		 4580 next_fragP->fr_subtype = RELAX_UNREACHABLE;
4581 next_fragP->tc_frag_data.is_unreachable = TRUE;
4582 new_target->fr_subtype = RELAX_DESIRE_ALIGN;
4583 new_target->tc_frag_data.is_branch_target = TRUE;
4584 }
4585 while (next_fragP && next_fragP->fr_fix == 0)
4586 {
4587 if (next_fragP->fr_type == rs_machine_dependent
4588 && next_fragP->fr_subtype == RELAX_LOOP_END)
4589 {
4590 next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP;
4591 return;
4592 }
4593
4594 next_fragP = next_fragP->fr_next;
4595 }
4596 }
4597 else
4598 {
4599 if (align_targets)
4600 {
4601 next_fragP->fr_subtype = RELAX_MAYBE_UNREACHABLE;
4602 next_fragP->tc_frag_data.is_unreachable = FALSE;
4603 new_target->fr_subtype = RELAX_MAYBE_DESIRE_ALIGN;
4604 new_target->tc_frag_data.is_branch_target = FALSE;
e0001a05 4605 }
e0001a05
NC		 4606 }
4607}
4608
4609
4610static bfd_boolean
7fa3d080 4611next_frag_is_branch_target (const fragS *fragP)
e0001a05 4612{
43cd72b9 4613 /* Sometimes an empty will end up here due to storage allocation issues,
e0001a05
NC		 4614 so we have to skip until we find something legit. */
4615 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4616 {
4617 if (fragP->tc_frag_data.is_branch_target)
4618 return TRUE;
4619 if (fragP->fr_fix != 0)
4620 break;
4621 }
4622 return FALSE;
4623}
4624
4625
4626static bfd_boolean
7fa3d080 4627next_frag_is_loop_target (const fragS *fragP)
e0001a05
NC		 4628{
4629 /* Sometimes an empty will end up here due storage allocation issues.
4630 So we have to skip until we find something legit. */
4631 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4632 {
4633 if (fragP->tc_frag_data.is_loop_target)
4634 return TRUE;
4635 if (fragP->fr_fix != 0)
4636 break;
4637 }
4638 return FALSE;
4639}
4640
4641
4642static addressT
7fa3d080 4643next_frag_pre_opcode_bytes (const fragS *fragp)
e0001a05
NC		 4644{
4645 const fragS *next_fragp = fragp->fr_next;
43cd72b9 4646 xtensa_opcode next_opcode;
e0001a05 4647
43cd72b9 4648 if (!next_frag_opcode_is_loop (fragp, &next_opcode))
e0001a05
NC		 4649 return 0;
4650
43cd72b9
BW		 4651 /* Sometimes an empty will end up here due to storage allocation issues,
4652 so we have to skip until we find something legit. */
e0001a05
NC		 4653 while (next_fragp->fr_fix == 0)
4654 next_fragp = next_fragp->fr_next;
4655
4656 if (next_fragp->fr_type != rs_machine_dependent)
4657 return 0;
4658
4659 /* There is some implicit knowledge encoded in here.
4660 The LOOP instructions that are NOT RELAX_IMMED have
43cd72b9
BW		 4661 been relaxed. Note that we can assume that the LOOP
4662 instruction is in slot 0 because loops aren't bundleable. */
4663 if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED)
e0001a05
NC		 4664 return get_expanded_loop_offset (next_opcode);
4665
4666 return 0;
4667}
4668
4669
4670/* Mark a location where we can later insert literal frags. Update
4671 the section's literal_pool_loc, so subsequent literals can be
4672 placed nearest to their use. */
4673
4674static void
7fa3d080 4675xtensa_mark_literal_pool_location (void)
e0001a05
NC		 4676{
4677 /* Any labels pointing to the current location need
4678 to be adjusted to after the literal pool. */
4679 emit_state s;
e0001a05 4680 fragS *pool_location;
e0001a05 4681
43cd72b9
BW		 4682 if (use_literal_section && !directive_state[directive_absolute_literals])
4683 return;
4684
e0001a05 4685 frag_align (2, 0, 0);
43cd72b9 4686 record_alignment (now_seg, 2);
e0001a05
NC		 4687
4688 /* We stash info in the fr_var of these frags
43cd72b9 4689 so we can later move the literal's fixes into this
e0001a05
NC		 4690 frchain's fix list. We can use fr_var because fr_var's
4691 interpretation depends solely on the fr_type and subtype. */
4692 pool_location = frag_now;
43cd72b9 4693 frag_variant (rs_machine_dependent, 0, (int) frchain_now,
e0001a05 4694 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
43cd72b9
BW		 4695 xtensa_set_frag_assembly_state (frag_now);
4696 frag_variant (rs_machine_dependent, 0, (int) now_seg,
e0001a05 4697 RELAX_LITERAL_POOL_END, NULL, 0, NULL);
43cd72b9 4698 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 4699
4700 /* Now put a frag into the literal pool that points to this location. */
4701 set_literal_pool_location (now_seg, pool_location);
43cd72b9
BW		 4702 xtensa_switch_to_non_abs_literal_fragment (&s);
4703 frag_align (2, 0, 0);
4704 record_alignment (now_seg, 2);
e0001a05
NC		 4705
4706 /* Close whatever frag is there. */
4707 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 4708 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 4709 frag_now->tc_frag_data.literal_frag = pool_location;
4710 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4711 xtensa_restore_emit_state (&s);
43cd72b9 4712 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 4713}
4714
4715
43cd72b9
BW		 4716/* Build a nop of the correct size into tinsn. */
4717
4718static void
7fa3d080 4719build_nop (TInsn *tinsn, int size)
43cd72b9
BW		 4720{
4721 tinsn_init (tinsn);
4722 switch (size)
4723 {
4724 case 2:
4725 tinsn->opcode = xtensa_nop_n_opcode;
4726 tinsn->ntok = 0;
4727 if (tinsn->opcode == XTENSA_UNDEFINED)
4728 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4729 break;
4730
4731 case 3:
4732 if (xtensa_nop_opcode == XTENSA_UNDEFINED)
4733 {
4734 tinsn->opcode = xtensa_or_opcode;
4735 set_expr_const (&tinsn->tok[0], 1);
4736 set_expr_const (&tinsn->tok[1], 1);
4737 set_expr_const (&tinsn->tok[2], 1);
4738 tinsn->ntok = 3;
4739 }
4740 else
4741 tinsn->opcode = xtensa_nop_opcode;
4742
4743 assert (tinsn->opcode != XTENSA_UNDEFINED);
4744 }
4745}
4746
4747
e0001a05
NC		 4748/* Assemble a NOP of the requested size in the buffer. User must have
4749 allocated "buf" with at least "size" bytes. */
4750
7fa3d080
BW		 4751static void
4752assemble_nop (size_t size, char *buf)
e0001a05
NC		 4753{
4754 static xtensa_insnbuf insnbuf = NULL;
43cd72b9 4755 TInsn tinsn;
e0001a05 4756
43cd72b9 4757 build_nop (&tinsn, size);
e0001a05 4758
43cd72b9
BW		 4759 if (!insnbuf)
4760 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
e0001a05 4761
43cd72b9
BW		 4762 tinsn_to_insnbuf (&tinsn, insnbuf);
4763 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, buf, 0);
e0001a05
NC		 4764}
4765
4766
4767/* Return the number of bytes for the offset of the expanded loop
4768 instruction. This should be incorporated into the relaxation
4769 specification but is hard-coded here. This is used to auto-align
4770 the loop instruction. It is invalid to call this function if the
4771 configuration does not have loops or if the opcode is not a loop
4772 opcode. */
4773
4774static addressT
7fa3d080 4775get_expanded_loop_offset (xtensa_opcode opcode)
e0001a05
NC		 4776{
4777 /* This is the OFFSET of the loop instruction in the expanded loop.
4778 This MUST correspond directly to the specification of the loop
4779 expansion. It will be validated on fragment conversion. */
43cd72b9 4780 assert (opcode != XTENSA_UNDEFINED);
e0001a05
NC		 4781 if (opcode == xtensa_loop_opcode)
4782 return 0;
4783 if (opcode == xtensa_loopnez_opcode)
4784 return 3;
4785 if (opcode == xtensa_loopgtz_opcode)
4786 return 6;
4787 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4788 return 0;
4789}
4790
4791
7fa3d080
BW		 4792static fragS *
4793get_literal_pool_location (segT seg)
e0001a05
NC		 4794{
4795 return seg_info (seg)->tc_segment_info_data.literal_pool_loc;
4796}
4797
4798
4799static void
7fa3d080 4800set_literal_pool_location (segT seg, fragS *literal_pool_loc)
e0001a05
NC		 4801{
4802 seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc;
4803}
4804
43cd72b9
BW		 4805
4806/* Set frag assembly state should be called when a new frag is
4807 opened and after a frag has been closed. */
4808
7fa3d080
BW		 4809static void
4810xtensa_set_frag_assembly_state (fragS *fragP)
43cd72b9
BW		 4811{
4812 if (!density_supported)
4813 fragP->tc_frag_data.is_no_density = TRUE;
4814
4815 /* This function is called from subsegs_finish, which is called
4816 after xtensa_end, so we can't use "use_transform" or
4817 "use_schedule" here. */
4818 if (!directive_state[directive_transform])
4819 fragP->tc_frag_data.is_no_transform = TRUE;
4820 fragP->tc_frag_data.use_absolute_literals =
4821 directive_state[directive_absolute_literals];
4822 fragP->tc_frag_data.is_assembly_state_set = TRUE;
4823}
4824
4825
7fa3d080
BW		 4826static bfd_boolean
4827relaxable_section (asection *sec)
43cd72b9
BW		 4828{
4829 return (sec->flags & SEC_DEBUGGING) == 0;
4830}
4831
4832
4833static void
7fa3d080 4834xtensa_find_unmarked_state_frags (void)
43cd72b9
BW		 4835{
4836 segT *seclist;
4837
4838 /* Walk over each fragment of all of the current segments. For each
4839 unmarked fragment, mark it with the same info as the previous
4840 fragment. */
4841 for (seclist = &stdoutput->sections;
4842 seclist && *seclist;
4843 seclist = &(*seclist)->next)
4844 {
4845 segT sec = *seclist;
4846 segment_info_type *seginfo;
4847 fragS *fragP;
4848 flagword flags;
4849 flags = bfd_get_section_flags (stdoutput, sec);
4850 if (flags & SEC_DEBUGGING)
4851 continue;
4852 if (!(flags & SEC_ALLOC))
4853 continue;
4854
4855 seginfo = seg_info (sec);
4856 if (seginfo && seginfo->frchainP)
4857 {
4858 fragS *last_fragP = 0;
4859 for (fragP = seginfo->frchainP->frch_root; fragP;
4860 fragP = fragP->fr_next)
4861 {
4862 if (fragP->fr_fix != 0
4863 && !fragP->tc_frag_data.is_assembly_state_set)
4864 {
4865 if (last_fragP == 0)
4866 {
4867 as_warn_where (fragP->fr_file, fragP->fr_line,
4868 _("assembly state not set for first frag in section %s"),
4869 sec->name);
4870 }
4871 else
4872 {
4873 fragP->tc_frag_data.is_assembly_state_set = TRUE;
4874 fragP->tc_frag_data.is_no_density =
4875 last_fragP->tc_frag_data.is_no_density;
4876 fragP->tc_frag_data.is_no_transform =
4877 last_fragP->tc_frag_data.is_no_transform;
4878 fragP->tc_frag_data.use_absolute_literals =
4879 last_fragP->tc_frag_data.use_absolute_literals;
4880 }
4881 }
4882 if (fragP->tc_frag_data.is_assembly_state_set)
4883 last_fragP = fragP;
4884 }
4885 }
4886 }
4887}
4888
4889
4890static void
7fa3d080
BW		 4891xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED,
4892 asection *sec,
4893 void *unused ATTRIBUTE_UNUSED)
43cd72b9
BW		 4894{
4895 flagword flags = bfd_get_section_flags (abfd, sec);
4896 segment_info_type *seginfo = seg_info (sec);
4897 fragS *frag = seginfo->frchainP->frch_root;
4898
4899 if (flags & SEC_CODE)
4900 {
4901 xtensa_isa isa = xtensa_default_isa;
4902 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
4903 while (frag != NULL)
4904 {
4905 if (frag->tc_frag_data.is_branch_target)
4906 {
4907 int op_size;
4908 int frag_addr;
4909 xtensa_format fmt;
4910
4911 xtensa_insnbuf_from_chars (isa, insnbuf, frag->fr_literal, 0);
4912 fmt = xtensa_format_decode (isa, insnbuf);
4913 op_size = xtensa_format_length (isa, fmt);
4914 frag_addr = frag->fr_address % xtensa_fetch_width;
4915 if (frag_addr + op_size > (int) xtensa_fetch_width)
4916 as_warn_where (frag->fr_file, frag->fr_line,
4917 _("unaligned branch target: %d bytes at 0x%lx"),
4918 op_size, frag->fr_address);
4919 }
4920 frag = frag->fr_next;
4921 }
4922 xtensa_insnbuf_free (isa, insnbuf);
4923 }
4924}
4925
4926
4927static void
7fa3d080
BW		 4928xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED,
4929 asection *sec,
4930 void *unused ATTRIBUTE_UNUSED)
43cd72b9
BW		 4931{
4932 flagword flags = bfd_get_section_flags (abfd, sec);
4933 segment_info_type *seginfo = seg_info (sec);
4934 fragS *frag = seginfo->frchainP->frch_root;
4935 xtensa_isa isa = xtensa_default_isa;
4936
4937 if (flags & SEC_CODE)
4938 {
4939 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
4940 while (frag != NULL)
4941 {
4942 if (frag->tc_frag_data.is_first_loop_insn)
4943 {
4944 int op_size;
4945 int frag_addr;
4946 xtensa_format fmt;
4947
4948 xtensa_insnbuf_from_chars (isa, insnbuf, frag->fr_literal, 0);
4949 fmt = xtensa_format_decode (isa, insnbuf);
4950 op_size = xtensa_format_length (isa, fmt);
4951 frag_addr = frag->fr_address % xtensa_fetch_width;
4952
4953 if (frag_addr + op_size > (signed) xtensa_fetch_width)
4954 as_warn_where (frag->fr_file, frag->fr_line,
4955 _("unaligned loop: %d bytes at 0x%lx"),
4956 op_size, frag->fr_address);
4957 }
4958 frag = frag->fr_next;
4959 }
4960 xtensa_insnbuf_free (isa, insnbuf);
4961 }
4962}
4963
4964
7fa3d080
BW		 4965static void
4966xg_apply_tentative_value (fixS *fixP, valueT val)
43cd72b9
BW		 4967{
4968 xtensa_isa isa = xtensa_default_isa;
4969 static xtensa_insnbuf insnbuf = NULL;
4970 static xtensa_insnbuf slotbuf = NULL;
4971 xtensa_format fmt;
4972 int slot;
4973 bfd_boolean alt_reloc;
4974 xtensa_opcode opcode;
4975 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
4976
4977 (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc);
4978 if (alt_reloc)
4979 as_fatal (_("unexpected fix"));
4980
4981 if (!insnbuf)
4982 {
4983 insnbuf = xtensa_insnbuf_alloc (isa);
4984 slotbuf = xtensa_insnbuf_alloc (isa);
4985 }
4986
4987 xtensa_insnbuf_from_chars (isa, insnbuf, fixpos, 0);
4988 fmt = xtensa_format_decode (isa, insnbuf);
4989 if (fmt == XTENSA_UNDEFINED)
4990 as_fatal (_("undecodable fix"));
4991 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
4992 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
4993 if (opcode == XTENSA_UNDEFINED)
4994 as_fatal (_("undecodable fix"));
4995
4996 /* CONST16 immediates are not PC-relative, despite the fact that we
4997 reuse the normal PC-relative operand relocations for the low part
4998 of a CONST16 operand. The code in tc_gen_reloc does not decode
4999 the opcodes so it is more convenient to detect this special case
5000 here. */
5001 if (opcode == xtensa_const16_opcode)
5002 return;
5003
5004 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode,
5005 get_relaxable_immed (opcode), val,
5006 fixP->fx_file, fixP->fx_line);
5007
5008 xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf);
5009 xtensa_insnbuf_to_chars (isa, insnbuf, fixpos, 0);
5010}
5011
e0001a05
NC		 5012\f
5013/* External Functions and Other GAS Hooks. */
5014
5015const char *
7fa3d080 5016xtensa_target_format (void)
e0001a05
NC		 5017{
5018 return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le");
5019}
5020
5021
5022void
7fa3d080 5023xtensa_file_arch_init (bfd *abfd)
e0001a05
NC		 5024{
5025 bfd_set_private_flags (abfd, 0x100 | 0x200);
5026}
5027
5028
5029void
7fa3d080 5030md_number_to_chars (char *buf, valueT val, int n)
e0001a05
NC		 5031{
5032 if (target_big_endian)
5033 number_to_chars_bigendian (buf, val, n);
5034 else
5035 number_to_chars_littleendian (buf, val, n);
5036}
5037
5038
5039/* This function is called once, at assembler startup time. It should
5040 set up all the tables, etc. that the MD part of the assembler will
5041 need. */
5042
5043void
7fa3d080 5044md_begin (void)
e0001a05
NC		 5045{
5046 segT current_section = now_seg;
5047 int current_subsec = now_subseg;
5048 xtensa_isa isa;
5049
43cd72b9 5050 xtensa_default_isa = xtensa_isa_init (0, 0);
e0001a05 5051 isa = xtensa_default_isa;
e0001a05 5052
43cd72b9
BW		 5053 linkrelax = 1;
5054
5055 /* Set up the .literal, .fini.literal and .init.literal sections. */
e0001a05
NC		 5056 memset (&default_lit_sections, 0, sizeof (default_lit_sections));
5057 default_lit_sections.init_lit_seg_name = INIT_LITERAL_SECTION_NAME;
5058 default_lit_sections.fini_lit_seg_name = FINI_LITERAL_SECTION_NAME;
5059 default_lit_sections.lit_seg_name = LITERAL_SECTION_NAME;
43cd72b9 5060 default_lit_sections.lit4_seg_name = LIT4_SECTION_NAME;
e0001a05
NC		 5061
5062 subseg_set (current_section, current_subsec);
5063
43cd72b9
BW		 5064 xg_init_vinsn (&cur_vinsn);
5065
e0001a05
NC		 5066 xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi");
5067 xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi");
5068 xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0");
5069 xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4");
5070 xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8");
5071 xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12");
5072 xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0");
5073 xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4");
5074 xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8");
5075 xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12");
43cd72b9 5076 xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16");
e0001a05 5077 xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry");
43cd72b9
BW		 5078 xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
5079 xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
e0001a05 5080 xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
e0001a05 5081 xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
43cd72b9 5082 xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
e0001a05
NC		 5083 xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
5084 xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez");
5085 xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz");
43cd72b9 5086 xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop");
e0001a05
NC		 5087 xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n");
5088 xtensa_or_opcode = xtensa_opcode_lookup (isa, "or");
5089 xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret");
5090 xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n");
5091 xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw");
5092 xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n");
43cd72b9 5093 xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
e0001a05 5094 xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
43cd72b9
BW		 5095
5096 init_op_placement_info_table ();
5097
5098 /* Set up the assembly state. */
5099 if (!frag_now->tc_frag_data.is_assembly_state_set)
5100 xtensa_set_frag_assembly_state (frag_now);
5101}
5102
5103
5104/* TC_INIT_FIX_DATA hook */
5105
5106void
7fa3d080 5107xtensa_init_fix_data (fixS *x)
43cd72b9
BW		 5108{
5109 x->tc_fix_data.slot = 0;
5110 x->tc_fix_data.X_add_symbol = NULL;
5111 x->tc_fix_data.X_add_number = 0;
e0001a05
NC		 5112}
5113
5114
5115/* tc_frob_label hook */
5116
5117void
7fa3d080 5118xtensa_frob_label (symbolS *sym)
e0001a05 5119{
43cd72b9
BW		 5120 /* Since the label was already attached to a frag associated with the
5121 previous basic block, it now needs to be reset to the current frag. */
5122 symbol_set_frag (sym, frag_now);
5123 S_SET_VALUE (sym, (valueT) frag_now_fix ());
5124
82e7541d
BW		 5125 if (generating_literals)
5126 xtensa_add_literal_sym (sym);
5127 else
5128 xtensa_add_insn_label (sym);
5129
5130 if (symbol_get_tc (sym)->is_loop_target
e0001a05
NC		 5131 && (get_last_insn_flags (now_seg, now_subseg)
5132 & FLAG_IS_BAD_LOOPEND) != 0)
5133 as_bad (_("invalid last instruction for a zero-overhead loop"));
5134
5135 /* No target aligning in the absolute section. */
61846f28 5136 if (now_seg != absolute_section
43cd72b9 5137 && do_align_targets ()
61846f28 5138 && !is_unaligned_label (sym)
43cd72b9
BW		 5139 && !generating_literals)
5140 {
b08b5071 5141 float freq = get_subseg_target_freq (now_seg, now_subseg);
43cd72b9
BW		 5142 xtensa_set_frag_assembly_state (frag_now);
5143
5144 /* The only time this type of frag grows is when there is a
5145 negatable branch that needs to be relaxed as the last
5146 instruction in a zero-overhead loop. Because alignment frags
5147 are so common, marking them all as possibly growing four
5148 bytes makes any worst-case analysis appear much worse than it
5149 is. So, we make fr_var not actually reflect the amount of
5150 memory allocated at the end of this frag, but rather the
5151 amount of memory this frag might grow. The "4, 0" below
5152 allocates four bytes at the end of the frag for room to grow
5153 if we need to relax a loop end with a NOP. Frags prior to
5154 this one might grow to align this one, but the frag itself
5155 won't grow unless it meets the condition above. */
5156
5157#define RELAX_LOOP_END_BYTES 4
5158
5159 frag_var (rs_machine_dependent,
5160 RELAX_LOOP_END_BYTES, (int) freq,
e0001a05
NC		 5161 RELAX_DESIRE_ALIGN_IF_TARGET,
5162 frag_now->fr_symbol, frag_now->fr_offset, NULL);
43cd72b9 5163 xtensa_set_frag_assembly_state (frag_now);
82e7541d 5164 xtensa_move_labels (frag_now, 0, TRUE);
43cd72b9
BW		 5165 }
5166
5167 /* We need to mark the following properties even if we aren't aligning. */
5168
5169 /* If the label is already known to be a branch target, i.e., a
5170 forward branch, mark the frag accordingly. Backward branches
5171 are handled by xg_add_branch_and_loop_targets. */
5172 if (symbol_get_tc (sym)->is_branch_target)
5173 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
5174
5175 /* Loops only go forward, so they can be identified here. */
5176 if (symbol_get_tc (sym)->is_loop_target)
5177 symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
5178}
5179
5180
5181/* tc_unrecognized_line hook */
5182
5183int
7fa3d080 5184xtensa_unrecognized_line (int ch)
43cd72b9
BW		 5185{
5186 switch (ch)
5187 {
5188 case '{' :
5189 if (cur_vinsn.inside_bundle == 0)
5190 {
5191 /* PR8110: Cannot emit line number info inside a FLIX bundle
5192 when using --gstabs. Temporarily disable debug info. */
5193 generate_lineno_debug ();
5194 if (debug_type == DEBUG_STABS)
5195 {
5196 xt_saved_debug_type = debug_type;
5197 debug_type = DEBUG_NONE;
5198 }
82e7541d 5199
43cd72b9
BW		 5200 cur_vinsn.inside_bundle = 1;
5201 }
5202 else
5203 {
5204 as_bad (_("extra opening brace"));
5205 return 0;
5206 }
5207 break;
82e7541d 5208
43cd72b9
BW		 5209 case '}' :
5210 if (cur_vinsn.inside_bundle)
5211 finish_vinsn (&cur_vinsn);
5212 else
5213 {
5214 as_bad (_("extra closing brace"));
5215 return 0;
5216 }
5217 break;
5218 default:
5219 as_bad (_("syntax error"));
5220 return 0;
e0001a05 5221 }
43cd72b9 5222 return 1;
e0001a05
NC		 5223}
5224
5225
5226/* md_flush_pending_output hook */
5227
5228void
7fa3d080 5229xtensa_flush_pending_output (void)
e0001a05 5230{
43cd72b9
BW		 5231 if (cur_vinsn.inside_bundle)
5232 as_bad (_("missing closing brace"));
5233
e0001a05
NC		 5234 /* If there is a non-zero instruction fragment, close it. */
5235 if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn)
5236 {
5237 frag_wane (frag_now);
5238 frag_new (0);
43cd72b9 5239 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 5240 }
5241 frag_now->tc_frag_data.is_insn = FALSE;
82e7541d
BW		 5242
5243 xtensa_clear_insn_labels ();
e0001a05
NC		 5244}
5245
5246
43cd72b9
BW		 5247/* We had an error while parsing an instruction. The string might look
5248 like this: "insn arg1, arg2 }". If so, we need to see the closing
5249 brace and reset some fields. Otherwise, the vinsn never gets closed
5250 and the num_slots field will grow past the end of the array of slots,
5251 and bad things happen. */
5252
5253static void
7fa3d080 5254error_reset_cur_vinsn (void)
43cd72b9
BW		 5255{
5256 if (cur_vinsn.inside_bundle)
5257 {
5258 if (*input_line_pointer == '}'
5259 || *(input_line_pointer - 1) == '}'
5260 || *(input_line_pointer - 2) == '}')
5261 xg_clear_vinsn (&cur_vinsn);
5262 }
5263}
5264
5265
e0001a05 5266void
7fa3d080 5267md_assemble (char *str)
e0001a05
NC		 5268{
5269 xtensa_isa isa = xtensa_default_isa;
5270 char *opname;
5271 unsigned opnamelen;
5272 bfd_boolean has_underbar = FALSE;
43cd72b9 5273 char *arg_strings[MAX_INSN_ARGS];
e0001a05 5274 int num_args;
e0001a05 5275 TInsn orig_insn; /* Original instruction from the input. */
e0001a05 5276
e0001a05
NC		 5277 tinsn_init (&orig_insn);
5278
5279 /* Split off the opcode. */
5280 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5281 opname = xmalloc (opnamelen + 1);
5282 memcpy (opname, str, opnamelen);
5283 opname[opnamelen] = '\0';
5284
5285 num_args = tokenize_arguments (arg_strings, str + opnamelen);
5286 if (num_args == -1)
5287 {
5288 as_bad (_("syntax error"));
5289 return;
5290 }
5291
5292 if (xg_translate_idioms (&opname, &num_args, arg_strings))
5293 return;
5294
5295 /* Check for an underbar prefix. */
5296 if (*opname == '_')
5297 {
5298 has_underbar = TRUE;
5299 opname += 1;
5300 }
5301
5302 orig_insn.insn_type = ITYPE_INSN;
5303 orig_insn.ntok = 0;
43cd72b9 5304 orig_insn.is_specific_opcode = (has_underbar || !use_transform ());
e0001a05
NC		 5305
5306 orig_insn.opcode = xtensa_opcode_lookup (isa, opname);
5307 if (orig_insn.opcode == XTENSA_UNDEFINED)
5308 {
43cd72b9
BW		 5309 xtensa_format fmt = xtensa_format_lookup (isa, opname);
5310 if (fmt == XTENSA_UNDEFINED)
5311 {
5312 as_bad (_("unknown opcode or format name '%s'"), opname);
5313 error_reset_cur_vinsn ();
5314 return;
5315 }
5316 if (!cur_vinsn.inside_bundle)
5317 {
5318 as_bad (_("format names only valid inside bundles"));
5319 error_reset_cur_vinsn ();
5320 return;
5321 }
5322 if (cur_vinsn.format != XTENSA_UNDEFINED)
5323 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5324 opname);
5325 cur_vinsn.format = fmt;
5326 free (has_underbar ? opname - 1 : opname);
5327 error_reset_cur_vinsn ();
e0001a05
NC		 5328 return;
5329 }
5330
e0001a05
NC		 5331 /* Special case: The call instructions should be marked "specific opcode"
5332 to keep them from expanding. */
5333 if (!use_longcalls () && is_direct_call_opcode (orig_insn.opcode))
5334 orig_insn.is_specific_opcode = TRUE;
5335
5336 /* Parse the arguments. */
5337 if (parse_arguments (&orig_insn, num_args, arg_strings))
5338 {
5339 as_bad (_("syntax error"));
43cd72b9 5340 error_reset_cur_vinsn ();
e0001a05
NC		 5341 return;
5342 }
5343
5344 /* Free the opcode and argument strings, now that they've been parsed. */
5345 free (has_underbar ? opname - 1 : opname);
5346 opname = 0;
5347 while (num_args-- > 0)
5348 free (arg_strings[num_args]);
5349
43cd72b9
BW		 5350 /* Get expressions for invisible operands. */
5351 if (get_invisible_operands (&orig_insn))
5352 {
5353 error_reset_cur_vinsn ();
5354 return;
5355 }
5356
e0001a05
NC		 5357 /* Check for the right number and type of arguments. */
5358 if (tinsn_check_arguments (&orig_insn))
e0001a05 5359 {
43cd72b9
BW		 5360 error_reset_cur_vinsn ();
5361 return;
e0001a05
NC		 5362 }
5363
43cd72b9
BW		 5364 dwarf2_where (&orig_insn.loc);
5365
5366 xg_add_branch_and_loop_targets (&orig_insn);
5367
61846f28 5368 /* Special-case for "entry" instruction. */
b08b5071 5369 if (orig_insn.opcode == xtensa_entry_opcode)
e0001a05 5370 {
43cd72b9
BW		 5371 /* Check that the third opcode (#2) is >= 16. */
5372 if (orig_insn.ntok >= 3)
e0001a05 5373 {
43cd72b9 5374 expressionS *exp = &orig_insn.tok[2];
e0001a05
NC		 5375 switch (exp->X_op)
5376 {
5377 case O_constant:
5378 if (exp->X_add_number < 16)
5379 as_warn (_("entry instruction with stack decrement < 16"));
5380 break;
5381
5382 default:
5383 as_warn (_("entry instruction with non-constant decrement"));
5384 }
5385 }
e0001a05
NC		 5386 }
5387
e0001a05 5388 /* Finish it off:
43cd72b9
BW		 5389 assemble_tokens (opcode, tok, ntok);
5390 expand the tokens from the orig_insn into the
5391 stack of instructions that will not expand
e0001a05 5392 unless required at relaxation time. */
e0001a05 5393
43cd72b9
BW		 5394 if (!cur_vinsn.inside_bundle)
5395 emit_single_op (&orig_insn);
5396 else /* We are inside a bundle. */
e0001a05 5397 {
43cd72b9
BW		 5398 cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn;
5399 cur_vinsn.num_slots++;
5400 if (*input_line_pointer == '}'
5401 || *(input_line_pointer - 1) == '}'
5402 || *(input_line_pointer - 2) == '}')
5403 finish_vinsn (&cur_vinsn);
e0001a05
NC		 5404 }
5405
43cd72b9
BW		 5406 /* We've just emitted a new instruction so clear the list of labels. */
5407 xtensa_clear_insn_labels ();
e0001a05
NC		 5408}
5409
5410
43cd72b9 5411/* HANDLE_ALIGN hook */
e0001a05 5412
43cd72b9
BW		 5413/* For a .align directive, we mark the previous block with the alignment
5414 information. This will be placed in the object file in the
5415 property section corresponding to this section. */
e0001a05 5416
43cd72b9 5417void
7fa3d080 5418xtensa_handle_align (fragS *fragP)
43cd72b9
BW		 5419{
5420 if (linkrelax
b08b5071 5421 && ! fragP->tc_frag_data.is_literal
43cd72b9
BW		 5422 && (fragP->fr_type == rs_align
5423 || fragP->fr_type == rs_align_code)
5424 && fragP->fr_address + fragP->fr_fix > 0
5425 && fragP->fr_offset > 0
5426 && now_seg != bss_section)
e0001a05 5427 {
43cd72b9
BW		 5428 fragP->tc_frag_data.is_align = TRUE;
5429 fragP->tc_frag_data.alignment = fragP->fr_offset;
e0001a05
NC		 5430 }
5431
43cd72b9 5432 if (fragP->fr_type == rs_align_test)
e0001a05 5433 {
43cd72b9
BW		 5434 int count;
5435 count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5436 if (count != 0)
5437 as_bad_where (fragP->fr_file, fragP->fr_line,
5438 _("unaligned entry instruction"));
e0001a05 5439 }
e0001a05 5440}
43cd72b9 5441
e0001a05
NC		 5442
5443/* TC_FRAG_INIT hook */
5444
5445void
7fa3d080 5446xtensa_frag_init (fragS *frag)
e0001a05 5447{
43cd72b9 5448 xtensa_set_frag_assembly_state (frag);
e0001a05
NC		 5449}
5450
5451
5452symbolS *
7fa3d080 5453md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
e0001a05
NC		 5454{
5455 return NULL;
5456}
5457
5458
5459/* Round up a section size to the appropriate boundary. */
5460
5461valueT
7fa3d080 5462md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
e0001a05
NC		 5463{
5464 return size; /* Byte alignment is fine. */
5465}
5466
5467
5468long
7fa3d080 5469md_pcrel_from (fixS *fixP)
e0001a05
NC		 5470{
5471 char *insn_p;
5472 static xtensa_insnbuf insnbuf = NULL;
43cd72b9 5473 static xtensa_insnbuf slotbuf = NULL;
e0001a05 5474 int opnum;
43cd72b9 5475 uint32 opnd_value;
e0001a05 5476 xtensa_opcode opcode;
43cd72b9
BW		 5477 xtensa_format fmt;
5478 int slot;
e0001a05
NC		 5479 xtensa_isa isa = xtensa_default_isa;
5480 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
43cd72b9 5481 bfd_boolean alt_reloc;
e0001a05
NC		 5482
5483 if (fixP->fx_done)
5484 return addr;
5485
5486 if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
5487 return addr;
5488
5489 if (!insnbuf)
43cd72b9
BW		 5490 {
5491 insnbuf = xtensa_insnbuf_alloc (isa);
5492 slotbuf = xtensa_insnbuf_alloc (isa);
5493 }
e0001a05
NC		 5494
5495 insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where];
43cd72b9
BW		 5496 xtensa_insnbuf_from_chars (isa, insnbuf, insn_p, 0);
5497 fmt = xtensa_format_decode (isa, insnbuf);
5498
5499 if (fmt == XTENSA_UNDEFINED)
5500 as_fatal (_("bad instruction format"));
5501
5502 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0)
5503 as_fatal (_("invalid relocation"));
5504
5505 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5506 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5507
5508 /* Check for "alternate" relocation (operand not specified). */
5509 if (alt_reloc || opcode == xtensa_const16_opcode)
5510 {
5511 if (opcode != xtensa_l32r_opcode
5512 && opcode != xtensa_const16_opcode)
5513 as_fatal (_("invalid relocation for '%s' instruction"),
5514 xtensa_opcode_name (isa, opcode));
e0001a05
NC		 5515 return addr;
5516 }
5517
43cd72b9
BW		 5518 opnum = get_relaxable_immed (opcode);
5519 opnd_value = 0;
5520 if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1
5521 || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr))
e0001a05
NC		 5522 {
5523 as_bad_where (fixP->fx_file,
5524 fixP->fx_line,
5525 _("invalid relocation for operand %d of '%s'"),
5526 opnum, xtensa_opcode_name (isa, opcode));
5527 return addr;
5528 }
43cd72b9
BW		 5529 return 0 - opnd_value;
5530}
5531
5532
5533/* TC_FORCE_RELOCATION hook */
5534
5535int
7fa3d080 5536xtensa_force_relocation (fixS *fix)
43cd72b9
BW		 5537{
5538 switch (fix->fx_r_type)
5539 {
5540 case BFD_RELOC_XTENSA_SLOT0_ALT:
5541 case BFD_RELOC_XTENSA_SLOT1_ALT:
5542 case BFD_RELOC_XTENSA_SLOT2_ALT:
5543 case BFD_RELOC_XTENSA_SLOT3_ALT:
5544 case BFD_RELOC_XTENSA_SLOT4_ALT:
5545 case BFD_RELOC_XTENSA_SLOT5_ALT:
5546 case BFD_RELOC_XTENSA_SLOT6_ALT:
5547 case BFD_RELOC_XTENSA_SLOT7_ALT:
5548 case BFD_RELOC_XTENSA_SLOT8_ALT:
5549 case BFD_RELOC_XTENSA_SLOT9_ALT:
5550 case BFD_RELOC_XTENSA_SLOT10_ALT:
5551 case BFD_RELOC_XTENSA_SLOT11_ALT:
5552 case BFD_RELOC_XTENSA_SLOT12_ALT:
5553 case BFD_RELOC_XTENSA_SLOT13_ALT:
5554 case BFD_RELOC_XTENSA_SLOT14_ALT:
5555 case BFD_RELOC_VTABLE_INHERIT:
5556 case BFD_RELOC_VTABLE_ENTRY:
5557 return 1;
5558 default:
5559 break;
e0001a05
NC		 5560 }
5561
43cd72b9
BW		 5562 if (linkrelax && fix->fx_addsy
5563 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
5564 return 1;
5565
5566 return generic_force_reloc (fix);
5567}
5568
5569
5570/* NO_PSEUDO_DOT hook */
5571
5572/* This function has nothing to do with pseudo dots, but this is the
5573 nearest macro to where the check needs to take place. FIXME: This
5574 seems wrong. */
5575
5576bfd_boolean
7fa3d080 5577xtensa_check_inside_bundle (void)
43cd72b9
BW		 5578{
5579 if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
5580 as_bad (_("directives are not valid inside bundles"));
5581
5582 /* This function must always return FALSE because it is called via a
5583 macro that has nothing to do with bundling. */
5584 return FALSE;
e0001a05
NC		 5585}
5586
5587
43cd72b9 5588/* md_elf_section_change_hook */
e0001a05
NC		 5589
5590void
7fa3d080 5591xtensa_elf_section_change_hook (void)
e0001a05 5592{
43cd72b9
BW		 5593 /* Set up the assembly state. */
5594 if (!frag_now->tc_frag_data.is_assembly_state_set)
5595 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 5596}
5597
5598
5599/* tc_fix_adjustable hook */
5600
5601bfd_boolean
7fa3d080 5602xtensa_fix_adjustable (fixS *fixP)
e0001a05 5603{
43cd72b9
BW		 5604 /* An offset is not allowed in combination with the difference of two
5605 symbols, but that cannot be easily detected after a local symbol
5606 has been adjusted to a (section+offset) form. Return 0 so that such
5607 an fix will not be adjusted. */
5608 if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset
5609 && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy)))
5610 return 0;
5611
e0001a05
NC		 5612 /* We need the symbol name for the VTABLE entries. */
5613 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5614 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5615 return 0;
5616
43cd72b9
BW		 5617 if (fixP->fx_addsy
5618 && (S_IS_EXTERNAL (fixP->fx_addsy) || S_IS_WEAK (fixP->fx_addsy)))
5619 return 0;
5620
5621#if 0
5622 /* We may someday want to enable this code to preserve relocations for
5623 non-PC-relative fixes, possibly under control of a PIC flag. */
5624 return (fixP->fx_pcrel
5625 || (fixP->fx_subsy != NULL
5626 && (S_GET_SEGMENT (fixP->fx_subsy)
5627 == S_GET_SEGMENT (fixP->fx_addsy)))
5628 || S_IS_LOCAL (fixP->fx_addsy));
5629#else
e0001a05 5630 return 1;
43cd72b9 5631#endif
e0001a05
NC		 5632}
5633
5634
5635void
7fa3d080 5636md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
e0001a05
NC		 5637{
5638 if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
5639 {
e0001a05 5640 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
e0001a05
NC		 5641
5642 switch (fixP->fx_r_type)
5643 {
5644 case BFD_RELOC_XTENSA_ASM_EXPAND:
5645 fixP->fx_done = 1;
5646 break;
5647
5648 case BFD_RELOC_XTENSA_ASM_SIMPLIFY:
5649 as_bad (_("unhandled local relocation fix %s"),
5650 bfd_get_reloc_code_name (fixP->fx_r_type));
5651 break;
5652
5653 case BFD_RELOC_32:
5654 case BFD_RELOC_16:
5655 case BFD_RELOC_8:
5656 /* The only one we support that isn't an instruction field. */
5657 md_number_to_chars (fixpos, *valP, fixP->fx_size);
5658 fixP->fx_done = 1;
5659 break;
5660
e0001a05
NC		 5661 case BFD_RELOC_VTABLE_INHERIT:
5662 case BFD_RELOC_VTABLE_ENTRY:
5663 fixP->fx_done = 0;
5664 break;
5665
5666 default:
5667 as_bad (_("unhandled local relocation fix %s"),
5668 bfd_get_reloc_code_name (fixP->fx_r_type));
5669 }
5670 }
5671}
5672
5673
5674char *
7fa3d080 5675md_atof (int type, char *litP, int *sizeP)
e0001a05
NC		 5676{
5677 int prec;
5678 LITTLENUM_TYPE words[4];
5679 char *t;
5680 int i;
5681
5682 switch (type)
5683 {
5684 case 'f':
5685 prec = 2;
5686 break;
5687
5688 case 'd':
5689 prec = 4;
5690 break;
5691
5692 default:
5693 *sizeP = 0;
5694 return "bad call to md_atof";
5695 }
5696
5697 t = atof_ieee (input_line_pointer, type, words);
5698 if (t)
5699 input_line_pointer = t;
5700
5701 *sizeP = prec * 2;
5702
5703 for (i = prec - 1; i >= 0; i--)
5704 {
5705 int idx = i;
5706 if (target_big_endian)
5707 idx = (prec - 1 - i);
5708
5709 md_number_to_chars (litP, (valueT) words[idx], 2);
5710 litP += 2;
5711 }
5712
5713 return NULL;
5714}
5715
5716
5717int
7fa3d080 5718md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED)
e0001a05 5719{
43cd72b9 5720 return fragP->tc_frag_data.text_expansion[0];
e0001a05
NC		 5721}
5722
5723
5724/* Translate internal representation of relocation info to BFD target
5725 format. */
5726
5727arelent *
7fa3d080 5728tc_gen_reloc (asection *section, fixS *fixp)
e0001a05
NC		 5729{
5730 arelent *reloc;
43cd72b9 5731 bfd_boolean apply_tentative_value = FALSE;
e0001a05
NC		 5732
5733 reloc = (arelent *) xmalloc (sizeof (arelent));
5734 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5735 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5736 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5737
5738 /* Make sure none of our internal relocations make it this far.
5739 They'd better have been fully resolved by this point. */
5740 assert ((int) fixp->fx_r_type > 0);
5741
43cd72b9
BW		 5742 if (linkrelax && fixp->fx_subsy
5743 && (fixp->fx_r_type == BFD_RELOC_8
5744 || fixp->fx_r_type == BFD_RELOC_16
5745 || fixp->fx_r_type == BFD_RELOC_32))
5746 {
5747 int diff_size = 0;
5748 bfd_vma diff_value, diff_mask = 0;
5749
5750 switch (fixp->fx_r_type)
5751 {
5752 case BFD_RELOC_8:
5753 fixp->fx_r_type = BFD_RELOC_XTENSA_DIFF8;
5754 diff_size = 1;
5755 diff_mask = 0xff;
5756 break;
5757 case BFD_RELOC_16:
5758 fixp->fx_r_type = BFD_RELOC_XTENSA_DIFF16;
5759 diff_size = 2;
5760 diff_mask = 0xffff;
5761 break;
5762 case BFD_RELOC_32:
5763 fixp->fx_r_type = BFD_RELOC_XTENSA_DIFF32;
5764 diff_size = 4;
5765 diff_mask = 0xffffffff;
5766 break;
5767 default:
5768 break;
5769 }
5770
5771 /* An offset is only allowed when it results from adjusting a local
5772 symbol into a section-relative offset. If the offset came from the
5773 original expression, tc_fix_adjustable will have prevented the fix
5774 from being converted to a section-relative form so that we can flag
5775 the error here. */
5776 if (fixp->fx_offset != 0 && !symbol_section_p (fixp->fx_addsy))
5777 {
5778 as_bad_where (fixp->fx_file, fixp->fx_line,
5779 _("cannot represent subtraction with an offset"));
5780 free (reloc->sym_ptr_ptr);
5781 free (reloc);
5782 return NULL;
5783 }
5784
5785 assert (S_GET_SEGMENT (fixp->fx_addsy)
5786 == S_GET_SEGMENT (fixp->fx_subsy));
5787
5788 diff_value = (S_GET_VALUE (fixp->fx_addsy) + fixp->fx_offset
5789 - S_GET_VALUE (fixp->fx_subsy));
5790
5791 /* Check for overflow. */
5792 if ((diff_value & ~diff_mask) != 0)
5793 {
5794 as_bad_where (fixp->fx_file, fixp->fx_line,
5795 _("value of %ld too large"), diff_value);
5796 free (reloc->sym_ptr_ptr);
5797 free (reloc);
5798 return NULL;
5799 }
5800
5801 md_number_to_chars (fixp->fx_frag->fr_literal + fixp->fx_where,
5802 diff_value, diff_size);
5803 reloc->addend = fixp->fx_offset - diff_value;
5804 }
5805 else
5806 {
5807 reloc->addend = fixp->fx_offset;
5808
5809 switch (fixp->fx_r_type)
5810 {
5811 case BFD_RELOC_XTENSA_SLOT0_OP:
5812 case BFD_RELOC_XTENSA_SLOT1_OP:
5813 case BFD_RELOC_XTENSA_SLOT2_OP:
5814 case BFD_RELOC_XTENSA_SLOT3_OP:
5815 case BFD_RELOC_XTENSA_SLOT4_OP:
5816 case BFD_RELOC_XTENSA_SLOT5_OP:
5817 case BFD_RELOC_XTENSA_SLOT6_OP:
5818 case BFD_RELOC_XTENSA_SLOT7_OP:
5819 case BFD_RELOC_XTENSA_SLOT8_OP:
5820 case BFD_RELOC_XTENSA_SLOT9_OP:
5821 case BFD_RELOC_XTENSA_SLOT10_OP:
5822 case BFD_RELOC_XTENSA_SLOT11_OP:
5823 case BFD_RELOC_XTENSA_SLOT12_OP:
5824 case BFD_RELOC_XTENSA_SLOT13_OP:
5825 case BFD_RELOC_XTENSA_SLOT14_OP:
5826 /* As a special case, the immediate value for a CONST16 opcode
5827 should not be applied, since this kind of relocation is
5828 handled specially for CONST16 and is not really PC-relative.
5829 Rather than decode the opcode here, just wait and handle it
5830 in xg_apply_tentative_value. */
5831 apply_tentative_value = TRUE;
5832 break;
5833
5834 case BFD_RELOC_XTENSA_SLOT0_ALT:
5835 case BFD_RELOC_XTENSA_SLOT1_ALT:
5836 case BFD_RELOC_XTENSA_SLOT2_ALT:
5837 case BFD_RELOC_XTENSA_SLOT3_ALT:
5838 case BFD_RELOC_XTENSA_SLOT4_ALT:
5839 case BFD_RELOC_XTENSA_SLOT5_ALT:
5840 case BFD_RELOC_XTENSA_SLOT6_ALT:
5841 case BFD_RELOC_XTENSA_SLOT7_ALT:
5842 case BFD_RELOC_XTENSA_SLOT8_ALT:
5843 case BFD_RELOC_XTENSA_SLOT9_ALT:
5844 case BFD_RELOC_XTENSA_SLOT10_ALT:
5845 case BFD_RELOC_XTENSA_SLOT11_ALT:
5846 case BFD_RELOC_XTENSA_SLOT12_ALT:
5847 case BFD_RELOC_XTENSA_SLOT13_ALT:
5848 case BFD_RELOC_XTENSA_SLOT14_ALT:
5849 case BFD_RELOC_XTENSA_ASM_EXPAND:
5850 case BFD_RELOC_32:
5851 case BFD_RELOC_XTENSA_PLT:
5852 case BFD_RELOC_VTABLE_INHERIT:
5853 case BFD_RELOC_VTABLE_ENTRY:
5854 break;
5855
5856 case BFD_RELOC_XTENSA_ASM_SIMPLIFY:
5857 as_warn (_("emitting simplification relocation"));
5858 break;
5859
5860 default:
5861 as_warn (_("emitting unknown relocation"));
5862 }
5863 }
5864
e0001a05
NC		 5865 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
5866 if (reloc->howto == NULL)
5867 {
5868 as_bad_where (fixp->fx_file, fixp->fx_line,
5869 _("cannot represent `%s' relocation in object file"),
5870 bfd_get_reloc_code_name (fixp->fx_r_type));
43cd72b9
BW		 5871 free (reloc->sym_ptr_ptr);
5872 free (reloc);
e0001a05
NC		 5873 return NULL;
5874 }
5875
5876 if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
43cd72b9
BW		 5877 as_fatal (_("internal error? cannot generate `%s' relocation"),
5878 bfd_get_reloc_code_name (fixp->fx_r_type));
e0001a05 5879
43cd72b9
BW		 5880 /* Write the tentative value of a PC-relative relocation to a local symbol
5881 into the instruction. The value will be ignored by the linker, and it
5882 makes the object file disassembly readable when the linkrelax flag is
5883 set and all branch targets are encoded in relocations. */
e0001a05 5884
43cd72b9 5885 if (linkrelax && apply_tentative_value && fixp->fx_pcrel)
e0001a05 5886 {
43cd72b9
BW		 5887 valueT val;
5888 assert (fixp->fx_addsy);
5889 if (S_GET_SEGMENT (fixp->fx_addsy) == section && !fixp->fx_plt
5890 && !S_FORCE_RELOC (fixp->fx_addsy, 1))
5891 {
5892 val = (S_GET_VALUE (fixp->fx_addsy) + fixp->fx_offset
5893 - md_pcrel_from (fixp));
5894 xg_apply_tentative_value (fixp, val);
5895 }
e0001a05
NC		 5896 }
5897
5898 return reloc;
5899}
5900
7fa3d080
BW		 5901\f
5902/* Checks for resource conflicts between instructions. */
5903
5904/* The func unit stuff could be implemented as bit-vectors rather
5905 than the iterative approach here. If it ends up being too
5906 slow, we will switch it. */
5907
5908resource_table *
5909new_resource_table (void *data,
5910 int cycles,
5911 int nu,
5912 unit_num_copies_func uncf,
5913 opcode_num_units_func onuf,
5914 opcode_funcUnit_use_unit_func ouuf,
5915 opcode_funcUnit_use_stage_func ousf)
5916{
5917 int i;
5918 resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table));
5919 rt->data = data;
5920 rt->cycles = cycles;
5921 rt->allocated_cycles = cycles;
5922 rt->num_units = nu;
5923 rt->unit_num_copies = uncf;
5924 rt->opcode_num_units = onuf;
5925 rt->opcode_unit_use = ouuf;
5926 rt->opcode_unit_stage = ousf;
5927
5928 rt->units = (char **) xcalloc (cycles, sizeof (char *));
5929 for (i = 0; i < cycles; i++)
5930 rt->units[i] = (char *) xcalloc (nu, sizeof (char));
5931
5932 return rt;
5933}
5934
5935
5936void
5937clear_resource_table (resource_table *rt)
5938{
5939 int i, j;
5940 for (i = 0; i < rt->allocated_cycles; i++)
5941 for (j = 0; j < rt->num_units; j++)
5942 rt->units[i][j] = 0;
5943}
5944
5945
5946/* We never shrink it, just fake it into thinking so. */
5947
5948void
5949resize_resource_table (resource_table *rt, int cycles)
5950{
5951 int i, old_cycles;
5952
5953 rt->cycles = cycles;
5954 if (cycles <= rt->allocated_cycles)
5955 return;
5956
5957 old_cycles = rt->allocated_cycles;
5958 rt->allocated_cycles = cycles;
5959
5960 rt->units = xrealloc (rt->units, sizeof (char *) * rt->allocated_cycles);
5961 for (i = 0; i < old_cycles; i++)
5962 rt->units[i] = xrealloc (rt->units[i], sizeof (char) * rt->num_units);
5963 for (i = old_cycles; i < cycles; i++)
5964 rt->units[i] = xcalloc (rt->num_units, sizeof (char));
5965}
5966
5967
5968bfd_boolean
5969resources_available (resource_table *rt, xtensa_opcode opcode, int cycle)
5970{
5971 int i;
5972 int uses = (rt->opcode_num_units) (rt->data, opcode);
5973
5974 for (i = 0; i < uses; i++)
5975 {
5976 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5977 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
5978 int copies_in_use = rt->units[stage + cycle][unit];
5979 int copies = (rt->unit_num_copies) (rt->data, unit);
5980 if (copies_in_use >= copies)
5981 return FALSE;
5982 }
5983 return TRUE;
5984}
5985
5986
5987void
5988reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
5989{
5990 int i;
5991 int uses = (rt->opcode_num_units) (rt->data, opcode);
5992
5993 for (i = 0; i < uses; i++)
5994 {
5995 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5996 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
5997 /* Note that this allows resources to be oversubscribed. That's
5998 essential to the way the optional scheduler works.
5999 resources_available reports when a resource is over-subscribed,
6000 so it's easy to tell. */
6001 rt->units[stage + cycle][unit]++;
6002 }
6003}
6004
6005
6006void
6007release_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
6008{
6009 int i;
6010 int uses = (rt->opcode_num_units) (rt->data, opcode);
6011
6012 for (i = 0; i < uses; i++)
6013 {
6014 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6015 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6016 rt->units[stage + cycle][unit]--;
6017 assert (rt->units[stage + cycle][unit] >= 0);
6018 }
6019}
6020
6021
6022/* Wrapper functions make parameterized resource reservation
6023 more convenient. */
6024
6025int
6026opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx)
6027{
6028 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6029 return use->unit;
6030}
6031
6032
6033int
6034opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx)
6035{
6036 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6037 return use->stage;
6038}
6039
6040
6041/* Note that this function does not check issue constraints, but
6042 solely whether the hardware is available to execute the given
6043 instructions together. It also doesn't check if the tinsns
6044 write the same state, or access the same tieports. That is
6045 checked by check_t1_t2_read_write. */
6046
6047static bfd_boolean
6048resources_conflict (vliw_insn *vinsn)
6049{
6050 int i;
6051 static resource_table *rt = NULL;
6052
6053 /* This is the most common case by far. Optimize it. */
6054 if (vinsn->num_slots == 1)
6055 return FALSE;
43cd72b9 6056
7fa3d080
BW		 6057 if (rt == NULL)
6058 {
6059 xtensa_isa isa = xtensa_default_isa;
6060 rt = new_resource_table
6061 (isa, xtensa_isa_num_pipe_stages (isa),
6062 xtensa_isa_num_funcUnits (isa),
6063 (unit_num_copies_func) xtensa_funcUnit_num_copies,
6064 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses,
6065 opcode_funcUnit_use_unit,
6066 opcode_funcUnit_use_stage);
6067 }
43cd72b9 6068
7fa3d080 6069 clear_resource_table (rt);
43cd72b9 6070
7fa3d080
BW		 6071 for (i = 0; i < vinsn->num_slots; i++)
6072 {
6073 if (!resources_available (rt, vinsn->slots[i].opcode, 0))
6074 return TRUE;
6075 reserve_resources (rt, vinsn->slots[i].opcode, 0);
6076 }
e0001a05 6077
7fa3d080
BW		 6078 return FALSE;
6079}
e0001a05 6080
7fa3d080
BW		 6081\f
6082/* finish_vinsn, emit_single_op and helper functions. */
e0001a05 6083
7fa3d080
BW		 6084static bfd_boolean find_vinsn_conflicts (vliw_insn *);
6085static xtensa_format xg_find_narrowest_format (vliw_insn *);
6086static void bundle_single_op (TInsn *);
6087static void xg_assemble_vliw_tokens (vliw_insn *);
e0001a05
NC		 6088
6089
43cd72b9
BW		 6090/* We have reached the end of a bundle; emit into the frag. */
6091
e0001a05 6092static void
7fa3d080 6093finish_vinsn (vliw_insn *vinsn)
e0001a05 6094{
43cd72b9
BW		 6095 IStack slotstack;
6096 int i;
6097 char *file_name;
6098 int line;
e0001a05 6099
43cd72b9
BW		 6100 if (find_vinsn_conflicts (vinsn))
6101 return;
6102
6103 /* First, find a format that works. */
6104 if (vinsn->format == XTENSA_UNDEFINED)
6105 vinsn->format = xg_find_narrowest_format (vinsn);
6106
6107 if (vinsn->format == XTENSA_UNDEFINED)
6108 {
6109 as_where (&file_name, &line);
6110 as_bad_where (file_name, line,
6111 _("couldn't find a valid instruction format"));
6112 fprintf (stderr, _(" ops were: "));
6113 for (i = 0; i < vinsn->num_slots; i++)
6114 fprintf (stderr, _(" %s;"),
6115 xtensa_opcode_name (xtensa_default_isa,
6116 vinsn->slots[i].opcode));
6117 fprintf (stderr, _("\n"));
6118 xg_clear_vinsn (vinsn);
6119 return;
6120 }
6121
6122 if (vinsn->num_slots
6123 != xtensa_format_num_slots (xtensa_default_isa, vinsn->format))
e0001a05 6124 {
43cd72b9
BW		 6125 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6126 xtensa_format_name (xtensa_default_isa, vinsn->format),
6127 xtensa_format_num_slots (xtensa_default_isa, vinsn->format),
6128 vinsn->num_slots);
6129 xg_clear_vinsn (vinsn);
6130 return;
6131 }
e0001a05 6132
43cd72b9
BW		 6133 if (resources_conflict (vinsn))
6134 {
6135 as_where (&file_name, &line);
6136 as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6137 fprintf (stderr, " ops were: ");
6138 for (i = 0; i < vinsn->num_slots; i++)
6139 fprintf (stderr, " %s;",
6140 xtensa_opcode_name (xtensa_default_isa,
6141 vinsn->slots[i].opcode));
6142 fprintf (stderr, "\n");
6143 xg_clear_vinsn (vinsn);
6144 return;
6145 }
6146
6147 for (i = 0; i < vinsn->num_slots; i++)
6148 {
6149 if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
e0001a05 6150 {
43cd72b9
BW		 6151 symbolS *lit_sym = NULL;
6152 int j;
6153 bfd_boolean e = FALSE;
6154 bfd_boolean saved_density = density_supported;
6155
6156 /* We don't want to narrow ops inside multi-slot bundles. */
6157 if (vinsn->num_slots > 1)
6158 density_supported = FALSE;
6159
6160 istack_init (&slotstack);
6161 if (vinsn->slots[i].opcode == xtensa_nop_opcode)
e0001a05 6162 {
43cd72b9
BW		 6163 vinsn->slots[i].opcode =
6164 xtensa_format_slot_nop_opcode (xtensa_default_isa,
6165 vinsn->format, i);
6166 vinsn->slots[i].ntok = 0;
6167 }
e0001a05 6168
43cd72b9
BW		 6169 if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
6170 {
6171 e = TRUE;
6172 continue;
e0001a05 6173 }
e0001a05 6174
43cd72b9 6175 density_supported = saved_density;
e0001a05 6176
43cd72b9
BW		 6177 if (e)
6178 {
6179 xg_clear_vinsn (vinsn);
6180 return;
6181 }
e0001a05 6182
43cd72b9
BW		 6183 for (j = 0; j < slotstack.ninsn - 1; j++)
6184 {
6185 TInsn *insn = &slotstack.insn[j];
6186 if (insn->insn_type == ITYPE_LITERAL)
6187 {
6188 assert (lit_sym == NULL);
6189 lit_sym = xg_assemble_literal (insn);
6190 }
6191 else
6192 {
6193 if (lit_sym)
6194 xg_resolve_literals (insn, lit_sym);
6195 emit_single_op (insn);
6196 }
6197 }
6198
6199 if (vinsn->num_slots > 1)
6200 {
6201 if (opcode_fits_format_slot
6202 (slotstack.insn[slotstack.ninsn - 1].opcode,
6203 vinsn->format, i))
6204 {
6205 vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
6206 }
6207 else
6208 {
6209 bundle_single_op (&slotstack.insn[slotstack.ninsn - 1]);
6210 if (vinsn->format == XTENSA_UNDEFINED)
6211 vinsn->slots[i].opcode = xtensa_nop_opcode;
6212 else
6213 vinsn->slots[i].opcode
6214 = xtensa_format_slot_nop_opcode (xtensa_default_isa,
6215 vinsn->format, i);
6216
6217 vinsn->slots[i].ntok = 0;
6218 }
6219 }
6220 else
6221 {
6222 vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
6223 vinsn->format = XTENSA_UNDEFINED;
6224 }
6225 }
6226 }
6227
6228 /* Now check resource conflicts on the modified bundle. */
6229 if (resources_conflict (vinsn))
6230 {
6231 as_where (&file_name, &line);
6232 as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6233 fprintf (stderr, " ops were: ");
6234 for (i = 0; i < vinsn->num_slots; i++)
6235 fprintf (stderr, " %s;",
6236 xtensa_opcode_name (xtensa_default_isa,
6237 vinsn->slots[i].opcode));
6238 fprintf (stderr, "\n");
6239 xg_clear_vinsn (vinsn);
6240 return;
6241 }
6242
6243 /* First, find a format that works. */
6244 if (vinsn->format == XTENSA_UNDEFINED)
6245 vinsn->format = xg_find_narrowest_format (vinsn);
6246
6247 xg_assemble_vliw_tokens (vinsn);
6248
6249 xg_clear_vinsn (vinsn);
6250}
6251
6252
6253/* Given an vliw instruction, what conflicts are there in register
6254 usage and in writes to states and queues?
6255
6256 This function does two things:
6257 1. Reports an error when a vinsn contains illegal combinations
6258 of writes to registers states or queues.
6259 2. Marks individual tinsns as not relaxable if the combination
6260 contains antidependencies.
6261
6262 Job 2 handles things like swap semantics in instructions that need
6263 to be relaxed. For example,
6264
6265 addi a0, a1, 100000
6266
6267 normally would be relaxed to
6268
6269 l32r a0, some_label
6270 add a0, a1, a0
6271
6272 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6273
6274 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6275
6276 then we can't relax it into
6277
6278 l32r a0, some_label
6279 { add a0, a1, a0 ; add a2, a0, a4 ; }
6280
6281 because the value of a0 is trashed before the second add can read it. */
6282
7fa3d080
BW		 6283static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
6284
43cd72b9 6285static bfd_boolean
7fa3d080 6286find_vinsn_conflicts (vliw_insn *vinsn)
43cd72b9
BW		 6287{
6288 int i, j;
6289 int branches = 0;
6290 xtensa_isa isa = xtensa_default_isa;
6291
6292 assert (!past_xtensa_end);
6293
6294 for (i = 0 ; i < vinsn->num_slots; i++)
6295 {
6296 TInsn *op1 = &vinsn->slots[i];
6297 if (op1->is_specific_opcode)
6298 op1->keep_wide = TRUE;
6299 else
6300 op1->keep_wide = FALSE;
6301 }
6302
6303 for (i = 0 ; i < vinsn->num_slots; i++)
6304 {
6305 TInsn *op1 = &vinsn->slots[i];
6306
6307 if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
6308 branches++;
6309
6310 for (j = 0; j < vinsn->num_slots; j++)
6311 {
6312 if (i != j)
6313 {
6314 TInsn *op2 = &vinsn->slots[j];
6315 char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
6316 switch (conflict_type)
6317 {
6318 case 'c':
6319 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6320 xtensa_opcode_name (isa, op1->opcode), i,
6321 xtensa_opcode_name (isa, op2->opcode), j);
6322 return TRUE;
6323 case 'd':
6324 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6325 xtensa_opcode_name (isa, op1->opcode), i,
6326 xtensa_opcode_name (isa, op2->opcode), j);
6327 return TRUE;
6328 case 'e':
6329 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6330 xtensa_opcode_name (isa, op1->opcode), i,
6331 xtensa_opcode_name (isa, op2->opcode), j);
6332 return TRUE;
6333 case 'f':
6334 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6335 xtensa_opcode_name (isa, op1->opcode), i,
6336 xtensa_opcode_name (isa, op2->opcode), j);
6337 return TRUE;
6338 default:
6339 /* Everything is OK. */
6340 break;
6341 }
6342 op2->is_specific_opcode = (op2->is_specific_opcode
6343 || conflict_type == 'a');
6344 }
6345 }
6346 }
6347
6348 if (branches > 1)
6349 {
6350 as_bad (_("multiple branches or jumps in the same bundle"));
6351 return TRUE;
6352 }
6353
6354 return FALSE;
6355}
6356
6357
6358/* Check how the result registers of t1 and t2 relate.
6359 Cases found are:
6360
6361 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6362 case B: no relationship between what is read and written (both could
6363 read the same reg though)
6364 case C: t1 writes a register t2 writes (a register conflict within a
6365 bundle)
6366 case D: t1 writes a state that t2 also writes
6367 case E: t1 writes a tie queue that t2 also writes
6368 case F: two volatile queue writes
6369*/
6370
6371static char
7fa3d080 6372check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2)
43cd72b9
BW		 6373{
6374 xtensa_isa isa = xtensa_default_isa;
6375 xtensa_regfile t1_regfile, t2_regfile;
6376 int t1_reg, t2_reg;
6377 int t1_base_reg, t1_last_reg;
6378 int t2_base_reg, t2_last_reg;
6379 char t1_inout, t2_inout;
6380 int i, j;
6381 char conflict = 'b';
6382 int t1_states;
6383 int t2_states;
6384 int t1_interfaces;
6385 int t2_interfaces;
6386 bfd_boolean t1_volatile = FALSE;
6387 bfd_boolean t2_volatile = FALSE;
6388
6389 /* Check registers. */
6390 for (j = 0; j < t2->ntok; j++)
6391 {
6392 if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
6393 continue;
6394
6395 t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
6396 t2_base_reg = t2->tok[j].X_add_number;
6397 t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
6398
6399 for (i = 0; i < t1->ntok; i++)
6400 {
6401 if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
6402 continue;
6403
6404 t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
6405
6406 if (t1_regfile != t2_regfile)
6407 continue;
6408
6409 t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
6410 t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
6411
6412 if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
6413 || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
6414 {
6415 if (t1_inout == 'm' || t1_inout == 'o'
6416 || t2_inout == 'm' || t2_inout == 'o')
6417 {
6418 conflict = 'a';
6419 continue;
6420 }
6421 }
6422
6423 t1_base_reg = t1->tok[i].X_add_number;
6424 t1_last_reg = (t1_base_reg
6425 + xtensa_operand_num_regs (isa, t1->opcode, i));
6426
6427 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
6428 {
6429 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
6430 {
6431 if (t1_reg != t2_reg)
6432 continue;
6433
6434 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
7fa3d080
BW		 6435 {
6436 conflict = 'a';
6437 continue;
6438 }
43cd72b9 6439
7fa3d080
BW		 6440 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6441 {
6442 conflict = 'a';
6443 continue;
6444 }
43cd72b9 6445
7fa3d080
BW		 6446 if (t1_inout != 'i' && t2_inout != 'i')
6447 return 'c';
6448 }
6449 }
6450 }
6451 }
43cd72b9 6452
7fa3d080
BW		 6453 /* Check states. */
6454 t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
6455 t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
6456 for (j = 0; j < t2_states; j++)
43cd72b9 6457 {
7fa3d080
BW		 6458 xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
6459 t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
6460 for (i = 0; i < t1_states; i++)
6461 {
6462 xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
6463 t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
6464 if (t1_so != t2_so)
6465 continue;
43cd72b9 6466
7fa3d080
BW		 6467 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6468 {
6469 conflict = 'a';
6470 continue;
6471 }
6472
6473 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6474 {
6475 conflict = 'a';
6476 continue;
6477 }
6478
6479 if (t1_inout != 'i' && t2_inout != 'i')
6480 return 'd';
6481 }
6482 }
43cd72b9 6483
7fa3d080
BW		 6484 /* Check tieports. */
6485 t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
6486 t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
6487 for (j = 0; j < t2_interfaces; j++)
43cd72b9 6488 {
7fa3d080
BW		 6489 xtensa_interface t2_int
6490 = xtensa_interfaceOperand_interface (isa, t2->opcode, j);
6491 t2_inout = xtensa_interface_inout (isa, j);
6492 if (xtensa_interface_has_side_effect (isa, t2_int) == 1
6493 && t2_inout != 'i')
6494 t2_volatile = TRUE;
6495 for (i = 0; i < t1_interfaces; i++)
6496 {
6497 xtensa_interface t1_int
6498 = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
6499 t1_inout = xtensa_interface_inout (isa, i);
6500 if (xtensa_interface_has_side_effect (isa, t1_int) == 1
6501 && t1_inout != 'i')
6502 t1_volatile = TRUE;
6503
6504 if (t1_int != t2_int)
6505 continue;
6506
6507 if (t2_inout == 'i' && t1_inout == 'o')
6508 {
6509 conflict = 'a';
6510 continue;
6511 }
6512
6513 if (t1_inout == 'i' && t2_inout == 'o')
6514 {
6515 conflict = 'a';
6516 continue;
6517 }
6518
6519 if (t1_inout != 'i' && t2_inout != 'i')
6520 return 'e';
6521 }
43cd72b9
BW		 6522 }
6523
7fa3d080
BW		 6524 if (t1_volatile && t2_volatile)
6525 return 'f';
6526
6527 return conflict;
43cd72b9
BW		 6528}
6529
6530
6531static xtensa_format
7fa3d080 6532xg_find_narrowest_format (vliw_insn *vinsn)
43cd72b9
BW		 6533{
6534 /* Right now we assume that the ops within the vinsn are properly
6535 ordered for the slots that the programmer wanted them in. In
6536 other words, we don't rearrange the ops in hopes of finding a
6537 better format. The scheduler handles that. */
6538
6539 xtensa_isa isa = xtensa_default_isa;
6540 xtensa_format format;
6541 vliw_insn v_copy = *vinsn;
6542 xtensa_opcode nop_opcode = xtensa_nop_opcode;
6543
6544 for (format = 0; format < xtensa_isa_num_formats (isa); format++)
6545 {
6546 v_copy = *vinsn;
6547 if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
6548 {
6549 int slot;
6550 int fit = 0;
6551 for (slot = 0; slot < v_copy.num_slots; slot++)
6552 {
6553 if (v_copy.slots[slot].opcode == nop_opcode)
6554 {
6555 v_copy.slots[slot].opcode =
6556 xtensa_format_slot_nop_opcode (isa, format, slot);
6557 v_copy.slots[slot].ntok = 0;
6558 }
6559
6560 if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
6561 format, slot))
6562 fit++;
7fa3d080 6563 else if (v_copy.num_slots > 1)
43cd72b9 6564 {
7fa3d080
BW		 6565 TInsn widened;
6566 /* Try the widened version. */
6567 if (!v_copy.slots[slot].keep_wide
6568 && !v_copy.slots[slot].is_specific_opcode
6569 && xg_is_narrow_insn (&v_copy.slots[slot])
6570 && !xg_expand_narrow (&widened, &v_copy.slots[slot])
6571 && opcode_fits_format_slot (widened.opcode,
6572 format, slot))
43cd72b9 6573 {
7fa3d080 6574 /* The xg_is_narrow clause requires some explanation:
43cd72b9 6575
7fa3d080
BW		 6576 addi can be "widened" to an addmi, which is then
6577 expanded to an addmi/addi pair if the immediate
6578 requires it, but here we must have a single widen
6579 only.
43cd72b9 6580
7fa3d080
BW		 6581 xg_is_narrow tells us that addi isn't really
6582 narrow. The widen_spec_list says that there are
6583 other cases. */
43cd72b9 6584
7fa3d080
BW		 6585 v_copy.slots[slot] = widened;
6586 fit++;
43cd72b9
BW		 6587 }
6588 }
6589 }
6590 if (fit == v_copy.num_slots)
6591 {
6592 *vinsn = v_copy;
6593 xtensa_format_encode (isa, format, vinsn->insnbuf);
6594 vinsn->format = format;
6595 break;
6596 }
6597 }
6598 }
6599
6600 if (format == xtensa_isa_num_formats (isa))
6601 return XTENSA_UNDEFINED;
6602
6603 return format;
6604}
6605
6606
6607/* Return the additional space needed in a frag
6608 for possible relaxations of any ops in a VLIW insn.
6609 Also fill out the relaxations that might be required of
6610 each tinsn in the vinsn. */
6611
6612static int
7fa3d080 6613relaxation_requirements (vliw_insn *vinsn)
43cd72b9
BW		 6614{
6615 int extra_space = 0;
6616 int slot;
6617
6618 for (slot = 0; slot < vinsn->num_slots; slot++)
6619 {
6620 TInsn *tinsn = &vinsn->slots[slot];
6621 if (!tinsn_has_symbolic_operands (tinsn))
6622 {
6623 /* A narrow instruction could be widened later to help
6624 alignment issues. */
6625 if (xg_is_narrow_insn (tinsn)
6626 && !tinsn->is_specific_opcode
6627 && vinsn->num_slots == 1)
6628 {
6629 /* Difference in bytes between narrow and wide insns... */
6630 extra_space += 1;
6631 tinsn->subtype = RELAX_NARROW;
6632 tinsn->record_fix = TRUE;
6633 break;
6634 }
6635 else
6636 {
6637 tinsn->record_fix = FALSE;
6638 /* No extra_space needed. */
6639 }
6640 }
6641 else
6642 {
b08b5071
BW		 6643 if (workaround_b_j_loop_end
6644 && tinsn->opcode == xtensa_jx_opcode
43cd72b9
BW		 6645 && use_transform ())
6646 {
6647 /* Add 2 of these. */
6648 extra_space += 3; /* for the nop size */
6649 tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
6650 }
6651
6652 /* Need to assemble it with space for the relocation. */
6653 if (xg_is_relaxable_insn (tinsn, 0)
6654 && !tinsn->is_specific_opcode)
6655 {
6656 int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
6657 int max_literal_size =
6658 xg_get_max_insn_widen_literal_size (tinsn->opcode);
6659
6660 tinsn->literal_space = max_literal_size;
6661
6662 tinsn->subtype = RELAX_IMMED;
6663 tinsn->record_fix = FALSE;
6664 extra_space += max_size;
6665 }
6666 else
6667 {
6668 tinsn->record_fix = TRUE;
6669 /* No extra space needed. */
6670 }
6671 }
6672 }
6673 return extra_space;
6674}
6675
6676
6677static void
7fa3d080 6678bundle_single_op (TInsn *orig_insn)
43cd72b9
BW		 6679{
6680 xtensa_isa isa = xtensa_default_isa;
6681 vliw_insn v;
6682 int slot;
6683
6684 xg_init_vinsn (&v);
6685 v.format = op_placement_table[orig_insn->opcode].narrowest;
6686 assert (v.format != XTENSA_UNDEFINED);
6687 v.num_slots = xtensa_format_num_slots (isa, v.format);
6688
6689 for (slot = 0;
6690 !opcode_fits_format_slot (orig_insn->opcode, v.format, slot);
6691 slot++)
6692 {
6693 v.slots[slot].opcode =
6694 xtensa_format_slot_nop_opcode (isa, v.format, slot);
6695 v.slots[slot].ntok = 0;
6696 v.slots[slot].insn_type = ITYPE_INSN;
6697 }
6698
6699 v.slots[slot] = *orig_insn;
6700 slot++;
6701
6702 for ( ; slot < v.num_slots; slot++)
6703 {
6704 v.slots[slot].opcode =
6705 xtensa_format_slot_nop_opcode (isa, v.format, slot);
6706 v.slots[slot].ntok = 0;
6707 v.slots[slot].insn_type = ITYPE_INSN;
6708 }
6709
6710 finish_vinsn (&v);
6711 xg_free_vinsn (&v);
6712}
6713
6714
6715static bfd_boolean
7fa3d080 6716emit_single_op (TInsn *orig_insn)
43cd72b9
BW		 6717{
6718 int i;
6719 IStack istack; /* put instructions into here */
6720 symbolS *lit_sym = NULL;
6721 symbolS *label_sym = NULL;
6722
6723 istack_init (&istack);
6724
6725 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6726 Because the scheduling and bundling characteristics of movi and
6727 l32r or const16 are so different, we can do much better if we relax
6728 it prior to scheduling and bundling, rather than after. */
b08b5071
BW		 6729 if ((orig_insn->opcode == xtensa_movi_opcode
6730 || orig_insn->opcode == xtensa_movi_n_opcode)
6731 && !cur_vinsn.inside_bundle
43cd72b9
BW		 6732 && (orig_insn->tok[1].X_op == O_symbol
6733 || orig_insn->tok[1].X_op == O_pltrel))
6734 xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
6735 else
6736 if (xg_expand_assembly_insn (&istack, orig_insn))
6737 return TRUE;
6738
6739 for (i = 0; i < istack.ninsn; i++)
6740 {
6741 TInsn *insn = &istack.insn[i];
6742 switch (insn->insn_type)
6743 {
6744 case ITYPE_LITERAL:
6745 assert (lit_sym == NULL);
6746 lit_sym = xg_assemble_literal (insn);
6747 break;
6748 case ITYPE_LABEL:
6749 {
6750 static int relaxed_sym_idx = 0;
6751 char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12);
6752 sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
6753 colon (label);
6754 assert (label_sym == NULL);
6755 label_sym = symbol_find_or_make (label);
6756 assert (label_sym);
6757 free (label);
6758 }
6759 break;
6760 case ITYPE_INSN:
6761 if (lit_sym)
6762 xg_resolve_literals (insn, lit_sym);
6763 if (label_sym)
6764 xg_resolve_labels (insn, label_sym);
6765 bundle_single_op (insn);
6766 break;
6767 default:
6768 assert (0);
6769 break;
6770 }
6771 }
6772 return FALSE;
6773}
6774
6775
6776/* Emit a vliw instruction to the current fragment. */
6777
7fa3d080
BW		 6778static void
6779xg_assemble_vliw_tokens (vliw_insn *vinsn)
43cd72b9
BW		 6780{
6781 bfd_boolean finish_frag = FALSE;
6782 bfd_boolean is_jump = FALSE;
6783 bfd_boolean is_branch = FALSE;
6784 xtensa_isa isa = xtensa_default_isa;
6785 int i;
6786 int insn_size;
6787 int extra_space;
6788 char *f = NULL;
6789 int slot;
6790 struct dwarf2_line_info best_loc;
6791
6792 best_loc.line = INT_MAX;
6793
6794 if (generating_literals)
6795 {
6796 static int reported = 0;
6797 if (reported < 4)
6798 as_bad_where (frag_now->fr_file, frag_now->fr_line,
6799 _("cannot assemble into a literal fragment"));
6800 if (reported == 3)
6801 as_bad (_("..."));
6802 reported++;
6803 return;
6804 }
6805
6806 if (frag_now_fix () != 0
b08b5071 6807 && (! frag_now->tc_frag_data.is_insn
43cd72b9 6808 || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
b08b5071 6809 || !use_transform () != frag_now->tc_frag_data.is_no_transform
43cd72b9
BW		 6810 || (directive_state[directive_absolute_literals]
6811 != frag_now->tc_frag_data.use_absolute_literals)))
6812 {
6813 frag_wane (frag_now);
6814 frag_new (0);
6815 xtensa_set_frag_assembly_state (frag_now);
6816 }
6817
6818 if (workaround_a0_b_retw
6819 && vinsn->num_slots == 1
6820 && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
6821 && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
6822 && use_transform ())
6823 {
6824 has_a0_b_retw = TRUE;
6825
6826 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6827 After the first assembly pass we will check all of them and
6828 add a nop if needed. */
6829 frag_now->tc_frag_data.is_insn = TRUE;
6830 frag_var (rs_machine_dependent, 4, 4,
6831 RELAX_ADD_NOP_IF_A0_B_RETW,
6832 frag_now->fr_symbol,
6833 frag_now->fr_offset,
6834 NULL);
6835 xtensa_set_frag_assembly_state (frag_now);
6836 frag_now->tc_frag_data.is_insn = TRUE;
6837 frag_var (rs_machine_dependent, 4, 4,
6838 RELAX_ADD_NOP_IF_A0_B_RETW,
6839 frag_now->fr_symbol,
6840 frag_now->fr_offset,
6841 NULL);
6842 xtensa_set_frag_assembly_state (frag_now);
6843 }
6844
6845 for (i = 0; i < vinsn->num_slots; i++)
6846 {
6847 /* See if the instruction implies an aligned section. */
6848 if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1)
6849 record_alignment (now_seg, 2);
6850
6851 /* Also determine the best line number for debug info. */
6852 best_loc = vinsn->slots[i].loc.line < best_loc.line
6853 ? vinsn->slots[i].loc : best_loc;
6854 }
6855
6856 /* Special cases for instructions that force an alignment... */
6857 /* None of these opcodes are bundle-able. */
6858 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
6859 {
6860 size_t max_fill;
6861
6862 xtensa_set_frag_assembly_state (frag_now);
6863 frag_now->tc_frag_data.is_insn = TRUE;
6864
6865 max_fill = get_text_align_max_fill_size
6866 (get_text_align_power (xtensa_fetch_width),
6867 TRUE, frag_now->tc_frag_data.is_no_density);
6868
6869 if (use_transform ())
6870 frag_var (rs_machine_dependent, max_fill, max_fill,
6871 RELAX_ALIGN_NEXT_OPCODE,
6872 frag_now->fr_symbol,
6873 frag_now->fr_offset,
6874 NULL);
6875 else
6876 frag_var (rs_machine_dependent, 0, 0,
6877 RELAX_CHECK_ALIGN_NEXT_OPCODE, 0, 0, NULL);
6878 xtensa_set_frag_assembly_state (frag_now);
6879
6880 xtensa_move_labels (frag_now, 0, FALSE);
6881 }
6882
b08b5071 6883 if (vinsn->slots[0].opcode == xtensa_entry_opcode
43cd72b9
BW		 6884 && !vinsn->slots[0].is_specific_opcode)
6885 {
6886 xtensa_mark_literal_pool_location ();
6887 xtensa_move_labels (frag_now, 0, TRUE);
6888 frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
6889 }
6890
6891 if (vinsn->num_slots == 1)
6892 {
6893 if (workaround_a0_b_retw && use_transform ())
6894 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
6895 is_register_writer (&vinsn->slots[0], "a", 0));
6896
6897 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
6898 is_bad_loopend_opcode (&vinsn->slots[0]));
6899 }
6900 else
6901 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
6902
6903 insn_size = xtensa_format_length (isa, vinsn->format);
6904
6905 extra_space = relaxation_requirements (vinsn);
6906
6907 /* vinsn_to_insnbuf will produce the error. */
6908 if (vinsn->format != XTENSA_UNDEFINED)
6909 {
6910 f = (char *) frag_more (insn_size + extra_space);
6911 xtensa_set_frag_assembly_state (frag_now);
6912 frag_now->tc_frag_data.is_insn = TRUE;
6913 }
6914
6915 vinsn_to_insnbuf (vinsn, f, frag_now, TRUE);
6916 if (vinsn->format == XTENSA_UNDEFINED)
6917 return;
6918
6919 xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, f, 0);
6920
6921 xtensa_dwarf2_emit_insn (insn_size - extra_space, &best_loc);
6922
6923 for (slot = 0; slot < vinsn->num_slots; slot++)
6924 {
6925 TInsn *tinsn = &vinsn->slots[slot];
6926 frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
6927 frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol;
6928 frag_now->tc_frag_data.slot_sub_symbols[slot] = tinsn->sub_symbol;
6929 frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset;
6930 frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
6931 if (tinsn->literal_space != 0)
6932 xg_assemble_literal_space (tinsn->literal_space, slot);
6933
6934 if (tinsn->subtype == RELAX_NARROW)
6935 assert (vinsn->num_slots == 1);
6936 if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
6937 is_jump = TRUE;
6938 if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
6939 is_branch = TRUE;
6940
6941 if (tinsn->subtype || tinsn->symbol || tinsn->record_fix
6942 || tinsn->offset || tinsn->literal_frag || is_jump || is_branch)
6943 finish_frag = TRUE;
6944 }
6945
6946 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
b08b5071 6947 frag_now->tc_frag_data.is_specific_opcode = TRUE;
43cd72b9
BW		 6948
6949 if (finish_frag)
6950 {
6951 frag_variant (rs_machine_dependent,
6952 extra_space, extra_space, RELAX_SLOTS,
6953 frag_now->fr_symbol, frag_now->fr_offset, f);
6954 xtensa_set_frag_assembly_state (frag_now);
6955 }
6956
6957 /* Special cases for loops:
6958 close_loop_end should be inserted AFTER short_loop.
6959 Make sure that CLOSE loops are processed BEFORE short_loops
6960 when converting them. */
6961
6962 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6963 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode)
6964 && !vinsn->slots[0].is_specific_opcode)
6965 {
6966 if (workaround_short_loop && use_transform ())
6967 {
6968 maybe_has_short_loop = TRUE;
6969 frag_now->tc_frag_data.is_insn = TRUE;
6970 frag_var (rs_machine_dependent, 4, 4,
6971 RELAX_ADD_NOP_IF_SHORT_LOOP,
6972 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6973 frag_now->tc_frag_data.is_insn = TRUE;
6974 frag_var (rs_machine_dependent, 4, 4,
6975 RELAX_ADD_NOP_IF_SHORT_LOOP,
6976 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6977 }
6978
6979 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6980 loop at least 12 bytes away from another loop's end. */
6981 if (workaround_close_loop_end && use_transform ())
6982 {
6983 maybe_has_close_loop_end = TRUE;
6984 frag_now->tc_frag_data.is_insn = TRUE;
6985 frag_var (rs_machine_dependent, 12, 12,
6986 RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
6987 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6988 }
6989 }
6990
6991 if (use_transform ())
6992 {
6993 if (is_jump)
6994 {
6995 assert (finish_frag);
6996 frag_var (rs_machine_dependent,
6997 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
6998 RELAX_UNREACHABLE,
6999 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7000 xtensa_set_frag_assembly_state (frag_now);
7001 }
7002 else if (is_branch && align_targets)
7003 {
7004 assert (finish_frag);
7005 frag_var (rs_machine_dependent,
7006 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
7007 RELAX_MAYBE_UNREACHABLE,
7008 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7009 xtensa_set_frag_assembly_state (frag_now);
7010 frag_var (rs_machine_dependent,
7011 0, 0,
7012 RELAX_MAYBE_DESIRE_ALIGN,
7013 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7014 xtensa_set_frag_assembly_state (frag_now);
7015 }
7016 }
7017
7018 /* Now, if the original opcode was a call... */
7019 if (do_align_targets ()
7020 && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
7021 {
b08b5071 7022 float freq = get_subseg_total_freq (now_seg, now_subseg);
43cd72b9
BW		 7023 frag_now->tc_frag_data.is_insn = TRUE;
7024 frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
7025 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7026 xtensa_set_frag_assembly_state (frag_now);
7027 }
7028
7029 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7030 {
7031 frag_wane (frag_now);
7032 frag_new (0);
7033 xtensa_set_frag_assembly_state (frag_now);
7034 }
7035}
7036
7037\f
7fa3d080
BW		 7038/* xtensa_end and helper functions. */
7039
7040static void xtensa_cleanup_align_frags (void);
7041static void xtensa_fix_target_frags (void);
7042static void xtensa_mark_narrow_branches (void);
7043static void xtensa_mark_zcl_first_insns (void);
7044static void xtensa_fix_a0_b_retw_frags (void);
7045static void xtensa_fix_b_j_loop_end_frags (void);
7046static void xtensa_fix_close_loop_end_frags (void);
7047static void xtensa_fix_short_loop_frags (void);
7048static void xtensa_sanity_check (void);
7049
43cd72b9 7050void
7fa3d080 7051xtensa_end (void)
43cd72b9
BW		 7052{
7053 directive_balance ();
7054 xtensa_flush_pending_output ();
7055
7056 past_xtensa_end = TRUE;
7057
7058 xtensa_move_literals ();
7059
7060 xtensa_reorder_segments ();
7061 xtensa_cleanup_align_frags ();
7062 xtensa_fix_target_frags ();
7063 if (workaround_a0_b_retw && has_a0_b_retw)
7064 xtensa_fix_a0_b_retw_frags ();
7065 if (workaround_b_j_loop_end)
7066 xtensa_fix_b_j_loop_end_frags ();
7067
7068 /* "close_loop_end" should be processed BEFORE "short_loop". */
7069 if (workaround_close_loop_end && maybe_has_close_loop_end)
7070 xtensa_fix_close_loop_end_frags ();
7071
7072 if (workaround_short_loop && maybe_has_short_loop)
7073 xtensa_fix_short_loop_frags ();
7074 xtensa_mark_narrow_branches ();
7075 xtensa_mark_zcl_first_insns ();
7076
7077 xtensa_sanity_check ();
7078}
7079
7080
7081static void
7fa3d080 7082xtensa_cleanup_align_frags (void)
43cd72b9
BW		 7083{
7084 frchainS *frchP;
7085
7086 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7087 {
7088 fragS *fragP;
7089 /* Walk over all of the fragments in a subsection. */
7090 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7091 {
7092 if ((fragP->fr_type == rs_align
7093 || fragP->fr_type == rs_align_code
7094 || (fragP->fr_type == rs_machine_dependent
7095 && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
7096 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
7097 && fragP->fr_fix == 0)
7098 {
7099 fragS *next = fragP->fr_next;
7100
7101 while (next
7102 && next->fr_fix == 0
7103 && next->fr_type == rs_machine_dependent
7104 && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7105 {
7106 frag_wane (next);
7107 next = next->fr_next;
7108 }
7109 }
7110 /* If we don't widen branch targets, then they
7111 will be easier to align. */
7112 if (fragP->tc_frag_data.is_branch_target
7113 && fragP->fr_opcode == fragP->fr_literal
7114 && fragP->fr_type == rs_machine_dependent
7115 && fragP->fr_subtype == RELAX_SLOTS
7116 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
7117 frag_wane (fragP);
7118 if (fragP->fr_type == rs_machine_dependent
7119 && fragP->fr_subtype == RELAX_UNREACHABLE)
7120 fragP->tc_frag_data.is_unreachable = TRUE;
7121 }
7122 }
7123}
7124
7125
7126/* Re-process all of the fragments looking to convert all of the
7127 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7128 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7129 If the next fragment starts with a loop target, AND the previous
7130 fragment can be expanded to negate the branch, convert this to a
7131 RELAX_LOOP_END. Otherwise, convert to a .fill 0. */
7132
7fa3d080
BW		 7133static bfd_boolean frag_can_negate_branch (fragS *);
7134
43cd72b9 7135static void
7fa3d080 7136xtensa_fix_target_frags (void)
e0001a05
NC		 7137{
7138 frchainS *frchP;
7139
7140 /* When this routine is called, all of the subsections are still intact
7141 so we walk over subsections instead of sections. */
7142 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7143 {
7144 bfd_boolean prev_frag_can_negate_branch = FALSE;
7145 fragS *fragP;
7146
7147 /* Walk over all of the fragments in a subsection. */
7148 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7149 {
7150 if (fragP->fr_type == rs_machine_dependent
7151 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7152 {
7153 if (next_frag_is_loop_target (fragP))
7154 {
7155 if (prev_frag_can_negate_branch)
43cd72b9
BW		 7156 {
7157 fragP->fr_subtype = RELAX_LOOP_END;
7158 /* See the comment near the frag_var with a
7159 RELAX_DESIRE_ALIGN to see why we do this. */
7160 fragP->fr_var = RELAX_LOOP_END_BYTES;
7161 }
e0001a05
NC		 7162 else
7163 {
43cd72b9 7164 if (next_frag_is_branch_target (fragP))
e0001a05
NC		 7165 fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7166 else
7167 frag_wane (fragP);
7168 }
7169 }
43cd72b9 7170 else if (next_frag_is_branch_target (fragP))
e0001a05
NC		 7171 fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7172 else
7173 frag_wane (fragP);
7174 }
7175 if (fragP->fr_fix != 0)
7176 prev_frag_can_negate_branch = FALSE;
7177 if (frag_can_negate_branch (fragP))
7178 prev_frag_can_negate_branch = TRUE;
7179 }
7180 }
7181}
7182
7183
7184static bfd_boolean
7fa3d080 7185frag_can_negate_branch (fragS *fragP)
e0001a05 7186{
43cd72b9
BW		 7187 xtensa_isa isa = xtensa_default_isa;
7188 vliw_insn vinsn;
7189 int slot;
7190
7191 if (fragP->fr_type != rs_machine_dependent
7192 || fragP->fr_subtype != RELAX_SLOTS)
7193 return FALSE;
7194
7195 vinsn_from_chars (&vinsn, fragP->fr_opcode);
7196
7197 for (slot = 0; slot < xtensa_format_num_slots (isa, vinsn.format); slot++)
e0001a05 7198 {
43cd72b9
BW		 7199 if ((fragP->tc_frag_data.slot_subtypes[slot] == RELAX_IMMED)
7200 && xtensa_opcode_is_branch (isa, vinsn.slots[slot].opcode) == 1)
e0001a05
NC		 7201 return TRUE;
7202 }
43cd72b9
BW		 7203
7204 return FALSE;
7205}
7206
7207
7fa3d080
BW		 7208static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
7209
43cd72b9 7210static void
7fa3d080 7211xtensa_mark_narrow_branches (void)
43cd72b9
BW		 7212{
7213 frchainS *frchP;
7214
7215 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7216 {
7217 fragS *fragP;
7218 /* Walk over all of the fragments in a subsection. */
7219 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7220 {
7221 if (fragP->fr_type == rs_machine_dependent
7222 && fragP->fr_subtype == RELAX_SLOTS
7223 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
7224 {
7225 vliw_insn vinsn;
7226 const expressionS *expr;
7227 symbolS *symbolP;
7228
7229 vinsn_from_chars (&vinsn, fragP->fr_opcode);
7230 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
7231
7232 expr = &vinsn.slots[0].tok[1];
7233 symbolP = expr->X_add_symbol;
7234
7235 if (vinsn.num_slots == 1
7236 && xtensa_opcode_is_branch (xtensa_default_isa,
7237 vinsn.slots[0].opcode)
7238 && xg_get_single_size (vinsn.slots[0].opcode) == 2
7239 && is_narrow_branch_guaranteed_in_range (fragP,
7240 &vinsn.slots[0]))
7241 {
7242 fragP->fr_subtype = RELAX_SLOTS;
7243 fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
7244 }
7245 }
7246 }
7247 }
7248}
7249
7250
7251/* A branch is typically widened only when its target is out of
7252 range. However, we would like to widen them to align a subsequent
7253 branch target when possible.
7254
7255 Because the branch relaxation code is so convoluted, the optimal solution
7256 (combining the two cases) is difficult to get right in all circumstances.
7257 We therefore go with an "almost as good" solution, where we only
7258 use for alignment narrow branches that definitely will not expand to a
7259 jump and a branch. These functions find and mark these cases. */
7260
7261/* the range in bytes of a bnez.n and beqz.n */
7262#define MAX_IMMED6 68
7263
7fa3d080
BW		 7264static size_t unrelaxed_frag_max_size (fragS *);
7265
43cd72b9 7266static bfd_boolean
7fa3d080 7267is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn)
43cd72b9
BW		 7268{
7269 const expressionS *expr = &tinsn->tok[1];
7270 symbolS *symbolP = expr->X_add_symbol;
7271 fragS *target_frag = symbol_get_frag (symbolP);
7272 size_t max_distance = expr->X_add_number;
7273 max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
7274 if (is_branch_jmp_to_next (tinsn, fragP))
7275 return FALSE;
7276
7277 /* The branch doesn't branch over it's own frag,
7278 but over the subsequent ones. */
7279 fragP = fragP->fr_next;
7280 while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6)
7281 {
7282 max_distance += unrelaxed_frag_max_size (fragP);
7283 fragP = fragP->fr_next;
7284 }
7285 if (max_distance <= MAX_IMMED6 && fragP == target_frag)
7286 return TRUE;
e0001a05
NC		 7287 return FALSE;
7288}
7289
7290
43cd72b9 7291static void
7fa3d080 7292xtensa_mark_zcl_first_insns (void)
43cd72b9
BW		 7293{
7294 frchainS *frchP;
7295
7296 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7297 {
7298 fragS *fragP;
7299 /* Walk over all of the fragments in a subsection. */
7300 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7301 {
7302 if (fragP->fr_type == rs_machine_dependent
7303 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
7304 || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
7305 {
7306 /* Find the loop frag. */
7307 fragS *targ_frag = next_non_empty_frag (fragP);
7308 /* Find the first insn frag. */
7309 targ_frag = next_non_empty_frag (targ_frag);
7310
7311 /* Of course, sometimes (mostly for toy test cases) a
7312 zero-cost loop instruction is the last in a section. */
7313 if (targ_frag)
7314 {
7315 targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
7316 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
7317 frag_wane (fragP);
7318 }
7319 }
7320 }
7321 }
7322}
7323
7324
e0001a05
NC		 7325/* Re-process all of the fragments looking to convert all of the
7326 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7327 conditional branch or a retw/retw.n, convert this frag to one that
7328 will generate a NOP. In any case close it off with a .fill 0. */
7329
7fa3d080
BW		 7330static bfd_boolean next_instrs_are_b_retw (fragS *);
7331
e0001a05 7332static void
7fa3d080 7333xtensa_fix_a0_b_retw_frags (void)
e0001a05
NC		 7334{
7335 frchainS *frchP;
7336
7337 /* When this routine is called, all of the subsections are still intact
7338 so we walk over subsections instead of sections. */
7339 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7340 {
7341 fragS *fragP;
7342
7343 /* Walk over all of the fragments in a subsection. */
7344 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7345 {
7346 if (fragP->fr_type == rs_machine_dependent
7347 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
7348 {
7349 if (next_instrs_are_b_retw (fragP))
43cd72b9 7350 {
b08b5071 7351 if (fragP->tc_frag_data.is_no_transform)
43cd72b9
BW		 7352 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7353 else
7354 relax_frag_add_nop (fragP);
7355 }
7356 frag_wane (fragP);
e0001a05
NC		 7357 }
7358 }
7359 }
7360}
7361
7362
7fa3d080
BW		 7363static bfd_boolean
7364next_instrs_are_b_retw (fragS *fragP)
e0001a05
NC		 7365{
7366 xtensa_opcode opcode;
43cd72b9 7367 xtensa_format fmt;
e0001a05
NC		 7368 const fragS *next_fragP = next_non_empty_frag (fragP);
7369 static xtensa_insnbuf insnbuf = NULL;
43cd72b9 7370 static xtensa_insnbuf slotbuf = NULL;
e0001a05
NC		 7371 xtensa_isa isa = xtensa_default_isa;
7372 int offset = 0;
43cd72b9
BW		 7373 int slot;
7374 bfd_boolean branch_seen = FALSE;
e0001a05
NC		 7375
7376 if (!insnbuf)
43cd72b9
BW		 7377 {
7378 insnbuf = xtensa_insnbuf_alloc (isa);
7379 slotbuf = xtensa_insnbuf_alloc (isa);
7380 }
e0001a05
NC		 7381
7382 if (next_fragP == NULL)
7383 return FALSE;
7384
7385 /* Check for the conditional branch. */
43cd72b9
BW		 7386 xtensa_insnbuf_from_chars (isa, insnbuf, &next_fragP->fr_literal[offset], 0);
7387 fmt = xtensa_format_decode (isa, insnbuf);
7388 if (fmt == XTENSA_UNDEFINED)
7389 return FALSE;
7390
7391 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
7392 {
7393 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
7394 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
7395
7396 branch_seen = (branch_seen
7397 || xtensa_opcode_is_branch (isa, opcode) == 1);
7398 }
e0001a05 7399
43cd72b9 7400 if (!branch_seen)
e0001a05
NC		 7401 return FALSE;
7402
43cd72b9 7403 offset += xtensa_format_length (isa, fmt);
e0001a05
NC		 7404 if (offset == next_fragP->fr_fix)
7405 {
7406 next_fragP = next_non_empty_frag (next_fragP);
7407 offset = 0;
7408 }
43cd72b9 7409
e0001a05
NC		 7410 if (next_fragP == NULL)
7411 return FALSE;
7412
7413 /* Check for the retw/retw.n. */
43cd72b9
BW		 7414 xtensa_insnbuf_from_chars (isa, insnbuf, &next_fragP->fr_literal[offset], 0);
7415 fmt = xtensa_format_decode (isa, insnbuf);
7416
7417 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7418 have no problems. */
7419 if (fmt == XTENSA_UNDEFINED
7420 || xtensa_format_num_slots (isa, fmt) != 1)
7421 return FALSE;
7422
7423 xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
7424 opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
e0001a05 7425
b08b5071 7426 if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode)
e0001a05 7427 return TRUE;
43cd72b9 7428
e0001a05
NC		 7429 return FALSE;
7430}
7431
7432
7433/* Re-process all of the fragments looking to convert all of the
7434 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7435 loop end label, convert this frag to one that will generate a NOP.
7436 In any case close it off with a .fill 0. */
7437
7fa3d080
BW		 7438static bfd_boolean next_instr_is_loop_end (fragS *);
7439
e0001a05 7440static void
7fa3d080 7441xtensa_fix_b_j_loop_end_frags (void)
e0001a05
NC		 7442{
7443 frchainS *frchP;
7444
7445 /* When this routine is called, all of the subsections are still intact
7446 so we walk over subsections instead of sections. */
7447 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7448 {
7449 fragS *fragP;
7450
7451 /* Walk over all of the fragments in a subsection. */
7452 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7453 {
7454 if (fragP->fr_type == rs_machine_dependent
7455 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
7456 {
7457 if (next_instr_is_loop_end (fragP))
43cd72b9 7458 {
b08b5071 7459 if (fragP->tc_frag_data.is_no_transform)
43cd72b9
BW		 7460 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7461 else
7462 relax_frag_add_nop (fragP);
7463 }
7464 frag_wane (fragP);
e0001a05
NC		 7465 }
7466 }
7467 }
7468}
7469
7470
7fa3d080
BW		 7471static bfd_boolean
7472next_instr_is_loop_end (fragS *fragP)
e0001a05
NC		 7473{
7474 const fragS *next_fragP;
7475
7476 if (next_frag_is_loop_target (fragP))
7477 return FALSE;
7478
7479 next_fragP = next_non_empty_frag (fragP);
7480 if (next_fragP == NULL)
7481 return FALSE;
7482
7483 if (!next_frag_is_loop_target (next_fragP))
7484 return FALSE;
7485
7486 /* If the size is >= 3 then there is more than one instruction here.
7487 The hardware bug will not fire. */
7488 if (next_fragP->fr_fix > 3)
7489 return FALSE;
7490
7491 return TRUE;
7492}
7493
7494
7495/* Re-process all of the fragments looking to convert all of the
7496 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7497 not MY loop's loop end within 12 bytes, add enough nops here to
7498 make it at least 12 bytes away. In any case close it off with a
7499 .fill 0. */
7500
7fa3d080
BW		 7501static size_t min_bytes_to_other_loop_end (fragS *, fragS *, offsetT, size_t);
7502
e0001a05 7503static void
7fa3d080 7504xtensa_fix_close_loop_end_frags (void)
e0001a05
NC		 7505{
7506 frchainS *frchP;
7507
7508 /* When this routine is called, all of the subsections are still intact
7509 so we walk over subsections instead of sections. */
7510 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7511 {
7512 fragS *fragP;
7513
7514 fragS *current_target = NULL;
7515 offsetT current_offset = 0;
7516
7517 /* Walk over all of the fragments in a subsection. */
7518 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7519 {
7520 if (fragP->fr_type == rs_machine_dependent
43cd72b9
BW		 7521 && ((fragP->fr_subtype == RELAX_IMMED)
7522 || ((fragP->fr_subtype == RELAX_SLOTS)
7523 && (fragP->tc_frag_data.slot_subtypes[0]
7524 == RELAX_IMMED))))
e0001a05
NC		 7525 {
7526 /* Read it. If the instruction is a loop, get the target. */
43cd72b9
BW		 7527 TInsn t_insn;
7528 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7529 if (xtensa_opcode_is_loop (xtensa_default_isa,
7530 t_insn.opcode) == 1)
e0001a05 7531 {
e0001a05 7532 /* Get the current fragment target. */
43cd72b9 7533 if (fragP->tc_frag_data.slot_symbols[0])
e0001a05 7534 {
43cd72b9
BW		 7535 symbolS *sym = fragP->tc_frag_data.slot_symbols[0];
7536 current_target = symbol_get_frag (sym);
e0001a05
NC		 7537 current_offset = fragP->fr_offset;
7538 }
7539 }
7540 }
7541
7542 if (current_target
7543 && fragP->fr_type == rs_machine_dependent
7544 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
7545 {
7546 size_t min_bytes;
7547 size_t bytes_added = 0;
7548
7549#define REQUIRED_LOOP_DIVIDING_BYTES 12
7550 /* Max out at 12. */
7551 min_bytes = min_bytes_to_other_loop_end
7552 (fragP->fr_next, current_target, current_offset,
7553 REQUIRED_LOOP_DIVIDING_BYTES);
7554
7555 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
7556 {
b08b5071 7557 if (fragP->tc_frag_data.is_no_transform)
43cd72b9
BW		 7558 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7559 else
e0001a05 7560 {
43cd72b9
BW		 7561 while (min_bytes + bytes_added
7562 < REQUIRED_LOOP_DIVIDING_BYTES)
e0001a05 7563 {
43cd72b9
BW		 7564 int length = 3;
7565
7566 if (fragP->fr_var < length)
7567 as_fatal (_("fr_var %lu < length %d"),
7568 fragP->fr_var, length);
7569 else
7570 {
7571 assemble_nop (length,
7572 fragP->fr_literal + fragP->fr_fix);
7573 fragP->fr_fix += length;
7574 fragP->fr_var -= length;
7575 }
7576 bytes_added += length;
e0001a05 7577 }
e0001a05
NC		 7578 }
7579 }
7580 frag_wane (fragP);
7581 }
43cd72b9
BW		 7582 assert (fragP->fr_type != rs_machine_dependent
7583 || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
e0001a05
NC		 7584 }
7585 }
7586}
7587
7588
7fa3d080
BW		 7589static size_t unrelaxed_frag_min_size (fragS *);
7590
43cd72b9 7591static size_t
7fa3d080
BW		 7592min_bytes_to_other_loop_end (fragS *fragP,
7593 fragS *current_target,
7594 offsetT current_offset,
7595 size_t max_size)
e0001a05
NC		 7596{
7597 size_t offset = 0;
7598 fragS *current_fragP;
7599
7600 for (current_fragP = fragP;
7601 current_fragP;
7602 current_fragP = current_fragP->fr_next)
7603 {
7604 if (current_fragP->tc_frag_data.is_loop_target
7605 && current_fragP != current_target)
7606 return offset + current_offset;
7607
7608 offset += unrelaxed_frag_min_size (current_fragP);
7609
7610 if (offset + current_offset >= max_size)
7611 return max_size;
7612 }
7613 return max_size;
7614}
7615
7616
43cd72b9 7617static size_t
7fa3d080 7618unrelaxed_frag_min_size (fragS *fragP)
e0001a05
NC		 7619{
7620 size_t size = fragP->fr_fix;
7621
7622 /* add fill size */
7623 if (fragP->fr_type == rs_fill)
7624 size += fragP->fr_offset;
7625
7626 return size;
7627}
7628
7629
43cd72b9 7630static size_t
7fa3d080 7631unrelaxed_frag_max_size (fragS *fragP)
43cd72b9
BW		 7632{
7633 size_t size = fragP->fr_fix;
7634 switch (fragP->fr_type)
7635 {
7636 case 0:
7637 /* Empty frags created by the obstack allocation scheme
7638 end up with type 0. */
7639 break;
7640 case rs_fill:
7641 case rs_org:
7642 case rs_space:
7643 size += fragP->fr_offset;
7644 break;
7645 case rs_align:
7646 case rs_align_code:
7647 case rs_align_test:
7648 case rs_leb128:
7649 case rs_cfa:
7650 case rs_dwarf2dbg:
7651 /* No further adjustments needed. */
7652 break;
7653 case rs_machine_dependent:
7654 if (fragP->fr_subtype != RELAX_DESIRE_ALIGN)
7655 size += fragP->fr_var;
7656 break;
7657 default:
7658 /* We had darn well better know how big it is. */
7659 assert (0);
7660 break;
7661 }
7662
7663 return size;
7664}
7665
7666
e0001a05
NC		 7667/* Re-process all of the fragments looking to convert all
7668 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7669
7670 A)
7671 1) the instruction size count to the loop end label
7672 is too short (<= 2 instructions),
7673 2) loop has a jump or branch in it
7674
7675 or B)
43cd72b9 7676 1) workaround_all_short_loops is TRUE
e0001a05
NC		 7677 2) The generating loop was a 'loopgtz' or 'loopnez'
7678 3) the instruction size count to the loop end label is too short
7679 (<= 2 instructions)
7680 then convert this frag (and maybe the next one) to generate a NOP.
7681 In any case close it off with a .fill 0. */
7682
7fa3d080
BW		 7683static size_t count_insns_to_loop_end (fragS *, bfd_boolean, size_t);
7684static bfd_boolean branch_before_loop_end (fragS *);
7685
e0001a05 7686static void
7fa3d080 7687xtensa_fix_short_loop_frags (void)
e0001a05
NC		 7688{
7689 frchainS *frchP;
7690
7691 /* When this routine is called, all of the subsections are still intact
7692 so we walk over subsections instead of sections. */
7693 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7694 {
7695 fragS *fragP;
7696 fragS *current_target = NULL;
7697 offsetT current_offset = 0;
7698 xtensa_opcode current_opcode = XTENSA_UNDEFINED;
7699
7700 /* Walk over all of the fragments in a subsection. */
7701 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7702 {
43cd72b9 7703 /* Check on the current loop. */
e0001a05 7704 if (fragP->fr_type == rs_machine_dependent
43cd72b9
BW		 7705 && ((fragP->fr_subtype == RELAX_IMMED)
7706 || ((fragP->fr_subtype == RELAX_SLOTS)
7707 && (fragP->tc_frag_data.slot_subtypes[0]
7708 == RELAX_IMMED))))
e0001a05 7709 {
43cd72b9
BW		 7710 TInsn t_insn;
7711
e0001a05 7712 /* Read it. If the instruction is a loop, get the target. */
43cd72b9
BW		 7713 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7714 if (xtensa_opcode_is_loop (xtensa_default_isa,
7715 t_insn.opcode) == 1)
e0001a05 7716 {
e0001a05 7717 /* Get the current fragment target. */
43cd72b9 7718 if (fragP->tc_frag_data.slot_symbols[0])
e0001a05 7719 {
43cd72b9
BW		 7720 symbolS *sym = fragP->tc_frag_data.slot_symbols[0];
7721 current_target = symbol_get_frag (sym);
e0001a05 7722 current_offset = fragP->fr_offset;
43cd72b9 7723 current_opcode = t_insn.opcode;
e0001a05
NC		 7724 }
7725 }
7726 }
7727
7728 if (fragP->fr_type == rs_machine_dependent
7729 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7730 {
7731 size_t insn_count =
7732 count_insns_to_loop_end (fragP->fr_next, TRUE, 3);
7733 if (insn_count < 3
7734 && (branch_before_loop_end (fragP->fr_next)
43cd72b9 7735 || (workaround_all_short_loops
e0001a05 7736 && current_opcode != XTENSA_UNDEFINED
b08b5071 7737 && current_opcode != xtensa_loop_opcode)))
43cd72b9 7738 {
b08b5071 7739 if (fragP->tc_frag_data.is_no_transform)
43cd72b9
BW		 7740 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7741 else
7742 relax_frag_add_nop (fragP);
7743 }
7744 frag_wane (fragP);
e0001a05
NC		 7745 }
7746 }
7747 }
7748}
7749
7750
7fa3d080
BW		 7751static size_t unrelaxed_frag_min_insn_count (fragS *);
7752
43cd72b9 7753static size_t
7fa3d080
BW		 7754count_insns_to_loop_end (fragS *base_fragP,
7755 bfd_boolean count_relax_add,
7756 size_t max_count)
e0001a05
NC		 7757{
7758 fragS *fragP = NULL;
7759 size_t insn_count = 0;
7760
7761 fragP = base_fragP;
7762
7763 for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next)
7764 {
7765 insn_count += unrelaxed_frag_min_insn_count (fragP);
7766 if (insn_count >= max_count)
7767 return max_count;
7768
7769 if (count_relax_add)
7770 {
7771 if (fragP->fr_type == rs_machine_dependent
7772 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7773 {
7774 /* In order to add the appropriate number of
7775 NOPs, we count an instruction for downstream
7776 occurrences. */
7777 insn_count++;
7778 if (insn_count >= max_count)
7779 return max_count;
7780 }
7781 }
7782 }
7783 return insn_count;
7784}
7785
7786
43cd72b9 7787static size_t
7fa3d080 7788unrelaxed_frag_min_insn_count (fragS *fragP)
e0001a05 7789{
43cd72b9
BW		 7790 xtensa_isa isa = xtensa_default_isa;
7791 static xtensa_insnbuf insnbuf = NULL;
e0001a05
NC		 7792 size_t insn_count = 0;
7793 int offset = 0;
7794
7795 if (!fragP->tc_frag_data.is_insn)
7796 return insn_count;
7797
43cd72b9
BW		 7798 if (!insnbuf)
7799 insnbuf = xtensa_insnbuf_alloc (isa);
7800
e0001a05
NC		 7801 /* Decode the fixed instructions. */
7802 while (offset < fragP->fr_fix)
7803 {
43cd72b9
BW		 7804 xtensa_format fmt;
7805
7806 xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal + offset, 0);
7807 fmt = xtensa_format_decode (isa, insnbuf);
7808
7809 if (fmt == XTENSA_UNDEFINED)
e0001a05
NC		 7810 {
7811 as_fatal (_("undecodable instruction in instruction frag"));
7812 return insn_count;
7813 }
43cd72b9 7814 offset += xtensa_format_length (isa, fmt);
e0001a05
NC		 7815 insn_count++;
7816 }
7817
7818 return insn_count;
7819}
7820
7821
7fa3d080
BW		 7822static bfd_boolean unrelaxed_frag_has_b_j (fragS *);
7823
43cd72b9 7824static bfd_boolean
7fa3d080 7825branch_before_loop_end (fragS *base_fragP)
e0001a05
NC		 7826{
7827 fragS *fragP;
7828
7829 for (fragP = base_fragP;
7830 fragP && !fragP->tc_frag_data.is_loop_target;
7831 fragP = fragP->fr_next)
7832 {
7833 if (unrelaxed_frag_has_b_j (fragP))
7834 return TRUE;
7835 }
7836 return FALSE;
7837}
7838
7839
43cd72b9 7840static bfd_boolean
7fa3d080 7841unrelaxed_frag_has_b_j (fragS *fragP)
e0001a05 7842{
43cd72b9
BW		 7843 static xtensa_insnbuf insnbuf = NULL;
7844 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 7845 int offset = 0;
7846
7847 if (!fragP->tc_frag_data.is_insn)
7848 return FALSE;
7849
43cd72b9
BW		 7850 if (!insnbuf)
7851 insnbuf = xtensa_insnbuf_alloc (isa);
7852
e0001a05
NC		 7853 /* Decode the fixed instructions. */
7854 while (offset < fragP->fr_fix)
7855 {
43cd72b9
BW		 7856 xtensa_format fmt;
7857 int slot;
7858
7859 xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal + offset, 0);
7860 fmt = xtensa_format_decode (isa, insnbuf);
7861 if (fmt == XTENSA_UNDEFINED)
7862 return FALSE;
7863
7864 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
e0001a05 7865 {
43cd72b9
BW		 7866 xtensa_opcode opcode =
7867 get_opcode_from_buf (fragP->fr_literal + offset, slot);
7868 if (xtensa_opcode_is_branch (isa, opcode) == 1
7869 || xtensa_opcode_is_jump (isa, opcode) == 1)
7870 return TRUE;
e0001a05 7871 }
43cd72b9 7872 offset += xtensa_format_length (isa, fmt);
e0001a05
NC		 7873 }
7874 return FALSE;
7875}
7876
7877
7878/* Checks to be made after initial assembly but before relaxation. */
7879
7fa3d080
BW		 7880static bfd_boolean is_empty_loop (const TInsn *, fragS *);
7881static bfd_boolean is_local_forward_loop (const TInsn *, fragS *);
7882
e0001a05 7883static void
7fa3d080 7884xtensa_sanity_check (void)
e0001a05
NC		 7885{
7886 char *file_name;
7887 int line;
7888
7889 frchainS *frchP;
7890
7891 as_where (&file_name, &line);
7892 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7893 {
7894 fragS *fragP;
7895
7896 /* Walk over all of the fragments in a subsection. */
7897 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7898 {
7899 /* Currently we only check for empty loops here. */
7900 if (fragP->fr_type == rs_machine_dependent
7901 && fragP->fr_subtype == RELAX_IMMED)
7902 {
7903 static xtensa_insnbuf insnbuf = NULL;
7904 TInsn t_insn;
7905
7906 if (fragP->fr_opcode != NULL)
7907 {
7908 if (!insnbuf)
7909 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
43cd72b9
BW		 7910 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7911 tinsn_immed_from_frag (&t_insn, fragP, 0);
e0001a05 7912
43cd72b9
BW		 7913 if (xtensa_opcode_is_loop (xtensa_default_isa,
7914 t_insn.opcode) == 1)
e0001a05
NC		 7915 {
7916 if (is_empty_loop (&t_insn, fragP))
7917 {
7918 new_logical_line (fragP->fr_file, fragP->fr_line);
7919 as_bad (_("invalid empty loop"));
7920 }
7921 if (!is_local_forward_loop (&t_insn, fragP))
7922 {
7923 new_logical_line (fragP->fr_file, fragP->fr_line);
7924 as_bad (_("loop target does not follow "
7925 "loop instruction in section"));
7926 }
7927 }
7928 }
7929 }
7930 }
7931 }
7932 new_logical_line (file_name, line);
7933}
7934
7935
7936#define LOOP_IMMED_OPN 1
7937
43cd72b9 7938/* Return TRUE if the loop target is the next non-zero fragment. */
e0001a05 7939
7fa3d080
BW		 7940static bfd_boolean
7941is_empty_loop (const TInsn *insn, fragS *fragP)
e0001a05
NC		 7942{
7943 const expressionS *expr;
7944 symbolS *symbolP;
7945 fragS *next_fragP;
7946
7947 if (insn->insn_type != ITYPE_INSN)
7948 return FALSE;
7949
43cd72b9 7950 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
e0001a05
NC		 7951 return FALSE;
7952
7953 if (insn->ntok <= LOOP_IMMED_OPN)
7954 return FALSE;
7955
7956 expr = &insn->tok[LOOP_IMMED_OPN];
7957
7958 if (expr->X_op != O_symbol)
7959 return FALSE;
7960
7961 symbolP = expr->X_add_symbol;
7962 if (!symbolP)
7963 return FALSE;
7964
7965 if (symbol_get_frag (symbolP) == NULL)
7966 return FALSE;
7967
7968 if (S_GET_VALUE (symbolP) != 0)
7969 return FALSE;
7970
7971 /* Walk through the zero-size fragments from this one. If we find
7972 the target fragment, then this is a zero-size loop. */
43cd72b9 7973
e0001a05
NC		 7974 for (next_fragP = fragP->fr_next;
7975 next_fragP != NULL;
7976 next_fragP = next_fragP->fr_next)
7977 {
7978 if (next_fragP == symbol_get_frag (symbolP))
7979 return TRUE;
7980 if (next_fragP->fr_fix != 0)
7981 return FALSE;
7982 }
7983 return FALSE;
7984}
7985
7986
7fa3d080
BW		 7987static bfd_boolean
7988is_local_forward_loop (const TInsn *insn, fragS *fragP)
e0001a05
NC		 7989{
7990 const expressionS *expr;
7991 symbolS *symbolP;
7992 fragS *next_fragP;
7993
7994 if (insn->insn_type != ITYPE_INSN)
7995 return FALSE;
7996
43cd72b9 7997 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) == 0)
e0001a05
NC		 7998 return FALSE;
7999
8000 if (insn->ntok <= LOOP_IMMED_OPN)
8001 return FALSE;
8002
8003 expr = &insn->tok[LOOP_IMMED_OPN];
8004
8005 if (expr->X_op != O_symbol)
8006 return FALSE;
8007
8008 symbolP = expr->X_add_symbol;
8009 if (!symbolP)
8010 return FALSE;
8011
8012 if (symbol_get_frag (symbolP) == NULL)
8013 return FALSE;
8014
8015 /* Walk through fragments until we find the target.
8016 If we do not find the target, then this is an invalid loop. */
43cd72b9 8017
e0001a05
NC		 8018 for (next_fragP = fragP->fr_next;
8019 next_fragP != NULL;
8020 next_fragP = next_fragP->fr_next)
43cd72b9
BW		 8021 {
8022 if (next_fragP == symbol_get_frag (symbolP))
8023 return TRUE;
8024 }
e0001a05
NC		 8025
8026 return FALSE;
8027}
8028
8029\f
8030/* Alignment Functions. */
8031
43cd72b9 8032static size_t
7fa3d080 8033get_text_align_power (int target_size)
e0001a05
NC		 8034{
8035 size_t i = 0;
8036 for (i = 0; i < sizeof (size_t); i++)
8037 {
8038 if (target_size <= (1 << i))
8039 return i;
8040 }
43cd72b9 8041 assert (0);
e0001a05
NC		 8042 return 0;
8043}
8044
8045
43cd72b9 8046static addressT
7fa3d080
BW		 8047get_text_align_max_fill_size (int align_pow,
8048 bfd_boolean use_nops,
8049 bfd_boolean use_no_density)
e0001a05
NC		 8050{
8051 if (!use_nops)
8052 return (1 << align_pow);
8053 if (use_no_density)
8054 return 3 * (1 << align_pow);
8055
8056 return 1 + (1 << align_pow);
8057}
8058
8059
8060/* get_text_align_fill_size ()
43cd72b9 8061
e0001a05
NC		 8062 Desired alignments:
8063 give the address
8064 target_size = size of next instruction
8065 align_pow = get_text_align_power (target_size).
8066 use_nops = 0
8067 use_no_density = 0;
8068 Loop alignments:
8069 address = current address + loop instruction size;
8070 target_size = 3 (for 2 or 3 byte target)
43cd72b9 8071 = 4 (for 4 byte target)
e0001a05
NC		 8072 = 8 (for 8 byte target)
8073 align_pow = get_text_align_power (target_size);
8074 use_nops = 1
8075 use_no_density = set appropriately
8076 Text alignments:
8077 address = current address + loop instruction size;
8078 target_size = 0
8079 align_pow = get_text_align_power (target_size);
8080 use_nops = 0
8081 use_no_density = 0. */
8082
43cd72b9 8083static addressT
7fa3d080
BW		 8084get_text_align_fill_size (addressT address,
8085 int align_pow,
8086 int target_size,
8087 bfd_boolean use_nops,
8088 bfd_boolean use_no_density)
e0001a05
NC		 8089{
8090 /* Input arguments:
8091
8092 align_pow: log2 (required alignment).
8093
8094 target_size: alignment must allow the new_address and
8095 new_address+target_size-1.
8096
43cd72b9 8097 use_nops: if TRUE, then we can only use 2- or 3-byte nops.
e0001a05
NC		 8098
8099 use_no_density: if use_nops and use_no_density, we can only use
8100 3-byte nops.
8101
43cd72b9
BW		 8102 Usually the align_pow is the power of 2 that is greater than
8103 or equal to the target_size. This handles the 2-byte, 3-byte
8104 and 8-byte instructions.
8105
8106 Two cases:
8107
8108 (1) aligning an instruction properly, but without using NOPs.
8109 E.G.: a 3-byte instruction can go on any address where address mod 4
8110 is zero or one. The aligner uses this case to find the optimal
8111 number of fill bytes for relax_frag_for_align.
8112
8113 (2) aligning an instruction properly, but where we might need to use
8114 extra NOPs. E.G.: when the aligner couldn't find enough widenings
8115 or similar to get the optimal location. */
e0001a05
NC		 8116
8117 size_t alignment = (1 << align_pow);
43cd72b9
BW		 8118
8119 assert (target_size != 0);
8120
e0001a05
NC		 8121 if (!use_nops)
8122 {
43cd72b9
BW		 8123 unsigned fill_bytes;
8124 for (fill_bytes = 0; fill_bytes < alignment; fill_bytes++)
8125 {
8126 addressT end_address = address + target_size - 1 + fill_bytes;
8127 addressT start_address = address + fill_bytes;
8128 if ((end_address >> align_pow) == (start_address >> align_pow))
8129 return fill_bytes;
8130 }
8131 assert (0);
e0001a05
NC		 8132 }
8133
8134 /* This is the slightly harder case. */
8135 assert ((int) alignment >= target_size);
8136 assert (target_size > 0);
8137 if (!use_no_density)
8138 {
8139 size_t i;
8140 for (i = 0; i < alignment * 2; i++)
8141 {
8142 if (i == 1)
8143 continue;
43cd72b9
BW		 8144 if ((address + i) >> align_pow
8145 == (address + i + target_size - 1) >> align_pow)
e0001a05
NC		 8146 return i;
8147 }
8148 }
8149 else
8150 {
8151 size_t i;
8152
8153 /* Can only fill multiples of 3. */
8154 for (i = 0; i <= alignment * 3; i += 3)
8155 {
43cd72b9
BW		 8156 if ((address + i) >> align_pow
8157 == (address + i + target_size - 1) >> align_pow)
e0001a05
NC		 8158 return i;
8159 }
8160 }
8161 assert (0);
8162 return 0;
8163}
8164
8165
8166/* This will assert if it is not possible. */
8167
7fa3d080
BW		 8168static size_t
8169get_text_align_nop_count (size_t fill_size, bfd_boolean use_no_density)
e0001a05
NC		 8170{
8171 size_t count = 0;
8172 if (use_no_density)
8173 {
8174 assert (fill_size % 3 == 0);
8175 return (fill_size / 3);
8176 }
8177
8178 assert (fill_size != 1); /* Bad argument. */
8179
8180 while (fill_size > 1)
8181 {
8182 size_t insn_size = 3;
8183 if (fill_size == 2 || fill_size == 4)
8184 insn_size = 2;
8185 fill_size -= insn_size;
8186 count++;
8187 }
8188 assert (fill_size != 1); /* Bad algorithm. */
8189 return count;
8190}
8191
8192
7fa3d080
BW		 8193static size_t
8194get_text_align_nth_nop_size (size_t fill_size,
8195 size_t n,
8196 bfd_boolean use_no_density)
e0001a05
NC		 8197{
8198 size_t count = 0;
8199
8200 assert (get_text_align_nop_count (fill_size, use_no_density) > n);
8201
8202 if (use_no_density)
8203 return 3;
8204
8205 while (fill_size > 1)
8206 {
8207 size_t insn_size = 3;
8208 if (fill_size == 2 || fill_size == 4)
8209 insn_size = 2;
8210 fill_size -= insn_size;
8211 count++;
8212 if (n + 1 == count)
8213 return insn_size;
8214 }
8215 assert (0);
8216 return 0;
8217}
8218
8219
8220/* For the given fragment, find the appropriate address
8221 for it to begin at if we are using NOPs to align it. */
8222
8223static addressT
7fa3d080 8224get_noop_aligned_address (fragS *fragP, addressT address)
e0001a05 8225{
43cd72b9
BW		 8226 /* The rule is: get next fragment's FIRST instruction. Find
8227 the smallest number of bytes that need to be added to
8228 ensure that the next fragment's FIRST instruction will fit
8229 in a single word.
8230
8231 E.G., 2 bytes : 0, 1, 2 mod 4
8232 3 bytes: 0, 1 mod 4
8233
8234 If the FIRST instruction MIGHT be relaxed,
8235 assume that it will become a 3-byte instruction.
8236
8237 Note again here that LOOP instructions are not bundleable,
8238 and this relaxation only applies to LOOP opcodes. */
8239
e0001a05 8240 size_t fill_size = 0;
43cd72b9
BW		 8241 int first_insn_size;
8242 int loop_insn_size;
8243 addressT pre_opcode_bytes;
8244 size_t alignment;
8245 fragS *first_insn;
8246 xtensa_opcode opcode;
8247 bfd_boolean is_loop;
e0001a05 8248
43cd72b9
BW		 8249 assert (fragP->fr_type == rs_machine_dependent);
8250 assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
e0001a05 8251
43cd72b9
BW		 8252 /* Find the loop frag. */
8253 first_insn = next_non_empty_frag (fragP);
8254 /* Now find the first insn frag. */
8255 first_insn = next_non_empty_frag (first_insn);
e0001a05 8256
43cd72b9
BW		 8257 is_loop = next_frag_opcode_is_loop (fragP, &opcode);
8258 assert (is_loop);
8259 loop_insn_size = xg_get_single_size (opcode);
e0001a05 8260
43cd72b9
BW		 8261 pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
8262 pre_opcode_bytes += loop_insn_size;
e0001a05 8263
43cd72b9
BW		 8264 /* For loops, the alignment depends on the size of the
8265 instruction following the loop, not the LOOP instruction. */
e0001a05 8266
43cd72b9
BW		 8267 if (first_insn == NULL)
8268 return address;
e0001a05 8269
43cd72b9 8270 assert (first_insn->tc_frag_data.is_first_loop_insn);
e0001a05 8271
43cd72b9 8272 first_insn_size = frag_format_size (first_insn);
e0001a05 8273
43cd72b9
BW		 8274 if (first_insn_size == 2 || first_insn_size == XTENSA_UNDEFINED)
8275 first_insn_size = 3; /* ISA specifies this */
e0001a05 8276
43cd72b9
BW		 8277 /* If it was 8, then we'll need a larger alignment for the section. */
8278 alignment = get_text_align_power (first_insn_size);
e0001a05 8279
43cd72b9
BW		 8280 /* Is now_seg valid? */
8281 record_alignment (now_seg, alignment);
8282
8283 fill_size = get_text_align_fill_size
8284 (address + pre_opcode_bytes,
8285 get_text_align_power (first_insn_size),
8286 first_insn_size, TRUE, fragP->tc_frag_data.is_no_density);
e0001a05
NC		 8287
8288 return address + fill_size;
8289}
8290
8291
43cd72b9
BW		 8292/* 3 mechanisms for relaxing an alignment:
8293
8294 Align to a power of 2.
8295 Align so the next fragment's instruction does not cross a word boundary.
8296 Align the current instruction so that if the next instruction
8297 were 3 bytes, it would not cross a word boundary.
8298
e0001a05
NC		 8299 We can align with:
8300
43cd72b9
BW		 8301 zeros - This is easy; always insert zeros.
8302 nops - 3-byte and 2-byte instructions
8303 2 - 2-byte nop
8304 3 - 3-byte nop
8305 4 - 2 2-byte nops
8306 >=5 : 3-byte instruction + fn (n-3)
e0001a05
NC		 8307 widening - widen previous instructions. */
8308
8309static addressT
7fa3d080 8310get_aligned_diff (fragS *fragP, addressT address, addressT *max_diff)
e0001a05 8311{
43cd72b9
BW		 8312 addressT target_address, loop_insn_offset;
8313 int target_size;
8314 xtensa_opcode loop_opcode;
8315 bfd_boolean is_loop;
8316 int text_align_power;
8317 addressT opt_diff;
e0001a05 8318
43cd72b9
BW		 8319 assert (fragP->fr_type == rs_machine_dependent);
8320 switch (fragP->fr_subtype)
e0001a05 8321 {
43cd72b9
BW		 8322 case RELAX_DESIRE_ALIGN:
8323 target_size = next_frag_format_size (fragP);
8324 if (target_size == XTENSA_UNDEFINED)
8325 target_size = 3;
8326 text_align_power = get_text_align_power (xtensa_fetch_width);
8327 opt_diff = get_text_align_fill_size (address, text_align_power,
8328 target_size, FALSE, FALSE);
8329
8330 *max_diff = opt_diff + xtensa_fetch_width
8331 - (target_size + ((address + opt_diff) % xtensa_fetch_width));
8332 assert (*max_diff >= opt_diff);
8333 return opt_diff;
e0001a05 8334
43cd72b9
BW		 8335 case RELAX_ALIGN_NEXT_OPCODE:
8336 target_size = next_frag_format_size (fragP);
8337 loop_insn_offset = 0;
8338 is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode);
8339 assert (is_loop);
8340
8341 /* If the loop has been expanded then the LOOP instruction
8342 could be at an offset from this fragment. */
8343 if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0]
8344 != RELAX_IMMED)
8345 loop_insn_offset = get_expanded_loop_offset (loop_opcode);
8346
8347 if (target_size == 2)
8348 target_size = 3; /* ISA specifies this */
8349
8350 /* In an ideal world, which is what we are shooting for here,
8351 we wouldn't need to use any NOPs immediately prior to the
8352 LOOP instruction. If this approach fails, relax_frag_loop_align
8353 will call get_noop_aligned_address. */
8354 target_address =
8355 address + loop_insn_offset + xg_get_single_size (loop_opcode);
8356 text_align_power = get_text_align_power (target_size),
8357 opt_diff = get_text_align_fill_size (target_address, text_align_power,
8358 target_size, FALSE, FALSE);
8359
8360 *max_diff = xtensa_fetch_width
8361 - ((target_address + opt_diff) % xtensa_fetch_width)
8362 - target_size + opt_diff;
8363 assert (*max_diff >= opt_diff);
8364 return opt_diff;
e0001a05 8365
43cd72b9
BW		 8366 default:
8367 break;
e0001a05 8368 }
43cd72b9
BW		 8369 assert (0);
8370 return 0;
e0001a05
NC		 8371}
8372
8373\f
8374/* md_relax_frag Hook and Helper Functions. */
8375
7fa3d080
BW		 8376static long relax_frag_loop_align (fragS *, long);
8377static long relax_frag_for_align (fragS *, long);
8378static long relax_frag_immed
8379 (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean);
8380
8381
e0001a05
NC		 8382/* Return the number of bytes added to this fragment, given that the
8383 input has been stretched already by "stretch". */
8384
8385long
7fa3d080 8386xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
e0001a05 8387{
43cd72b9 8388 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 8389 int unreported = fragP->tc_frag_data.unreported_expansion;
8390 long new_stretch = 0;
8391 char *file_name;
8392 int line, lit_size;
43cd72b9
BW		 8393 static xtensa_insnbuf vbuf = NULL;
8394 int slot, num_slots;
8395 xtensa_format fmt;
e0001a05
NC		 8396
8397 as_where (&file_name, &line);
8398 new_logical_line (fragP->fr_file, fragP->fr_line);
8399
8400 fragP->tc_frag_data.unreported_expansion = 0;
8401
8402 switch (fragP->fr_subtype)
8403 {
8404 case RELAX_ALIGN_NEXT_OPCODE:
8405 /* Always convert. */
43cd72b9
BW		 8406 if (fragP->tc_frag_data.relax_seen)
8407 new_stretch = relax_frag_loop_align (fragP, stretch);
e0001a05
NC		 8408 break;
8409
8410 case RELAX_LOOP_END:
8411 /* Do nothing. */
8412 break;
8413
8414 case RELAX_LOOP_END_ADD_NOP:
8415 /* Add a NOP and switch to .fill 0. */
8416 new_stretch = relax_frag_add_nop (fragP);
43cd72b9 8417 frag_wane (fragP);
e0001a05
NC		 8418 break;
8419
8420 case RELAX_DESIRE_ALIGN:
43cd72b9 8421 /* Do nothing. The narrowing before this frag will either align
e0001a05
NC		 8422 it or not. */
8423 break;
8424
8425 case RELAX_LITERAL:
8426 case RELAX_LITERAL_FINAL:
8427 return 0;
8428
8429 case RELAX_LITERAL_NR:
8430 lit_size = 4;
8431 fragP->fr_subtype = RELAX_LITERAL_FINAL;
8432 assert (unreported == lit_size);
8433 memset (&fragP->fr_literal[fragP->fr_fix], 0, 4);
8434 fragP->fr_var -= lit_size;
8435 fragP->fr_fix += lit_size;
8436 new_stretch = 4;
8437 break;
8438
43cd72b9
BW		 8439 case RELAX_SLOTS:
8440 if (vbuf == NULL)
8441 vbuf = xtensa_insnbuf_alloc (isa);
8442
8443 xtensa_insnbuf_from_chars (isa, vbuf, fragP->fr_opcode, 0);
8444 fmt = xtensa_format_decode (isa, vbuf);
8445 num_slots = xtensa_format_num_slots (isa, fmt);
e0001a05 8446
43cd72b9
BW		 8447 for (slot = 0; slot < num_slots; slot++)
8448 {
8449 switch (fragP->tc_frag_data.slot_subtypes[slot])
8450 {
8451 case RELAX_NARROW:
8452 if (fragP->tc_frag_data.relax_seen)
8453 new_stretch += relax_frag_for_align (fragP, stretch);
8454 break;
8455
8456 case RELAX_IMMED:
8457 case RELAX_IMMED_STEP1:
8458 case RELAX_IMMED_STEP2:
8459 /* Place the immediate. */
8460 new_stretch += relax_frag_immed
8461 (now_seg, fragP, stretch,
8462 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
8463 fmt, slot, stretched_p, FALSE);
8464 break;
8465
8466 default:
8467 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8468 break;
8469 }
8470 }
e0001a05
NC		 8471 break;
8472
8473 case RELAX_LITERAL_POOL_BEGIN:
8474 case RELAX_LITERAL_POOL_END:
43cd72b9
BW		 8475 case RELAX_MAYBE_UNREACHABLE:
8476 case RELAX_MAYBE_DESIRE_ALIGN:
e0001a05
NC		 8477 /* No relaxation required. */
8478 break;
8479
43cd72b9
BW		 8480 case RELAX_FILL_NOP:
8481 case RELAX_UNREACHABLE:
8482 if (fragP->tc_frag_data.relax_seen)
8483 new_stretch += relax_frag_for_align (fragP, stretch);
8484 break;
8485
e0001a05
NC		 8486 default:
8487 as_bad (_("bad relaxation state"));
8488 }
8489
43cd72b9
BW		 8490 /* Tell gas we need another relaxation pass. */
8491 if (! fragP->tc_frag_data.relax_seen)
8492 {
8493 fragP->tc_frag_data.relax_seen = TRUE;
8494 *stretched_p = 1;
8495 }
8496
e0001a05
NC		 8497 new_logical_line (file_name, line);
8498 return new_stretch;
8499}
8500
8501
8502static long
7fa3d080 8503relax_frag_loop_align (fragS *fragP, long stretch)
e0001a05
NC		 8504{
8505 addressT old_address, old_next_address, old_size;
8506 addressT new_address, new_next_address, new_size;
8507 addressT growth;
8508
43cd72b9
BW		 8509 /* All the frags with relax_frag_for_alignment prior to this one in the
8510 section have been done, hopefully eliminating the need for a NOP here.
8511 But, this will put it in if necessary. */
e0001a05
NC		 8512
8513 /* Calculate the old address of this fragment and the next fragment. */
8514 old_address = fragP->fr_address - stretch;
8515 old_next_address = (fragP->fr_address - stretch + fragP->fr_fix +
43cd72b9 8516 fragP->tc_frag_data.text_expansion[0]);
e0001a05
NC		 8517 old_size = old_next_address - old_address;
8518
8519 /* Calculate the new address of this fragment and the next fragment. */
8520 new_address = fragP->fr_address;
8521 new_next_address =
8522 get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix);
8523 new_size = new_next_address - new_address;
8524
8525 growth = new_size - old_size;
8526
8527 /* Fix up the text_expansion field and return the new growth. */
43cd72b9 8528 fragP->tc_frag_data.text_expansion[0] += growth;
e0001a05
NC		 8529 return growth;
8530}
8531
8532
43cd72b9 8533/* Add a NOP instruction. */
e0001a05
NC		 8534
8535static long
7fa3d080 8536relax_frag_add_nop (fragS *fragP)
e0001a05 8537{
e0001a05 8538 char *nop_buf = fragP->fr_literal + fragP->fr_fix;
43cd72b9
BW		 8539 int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
8540 assemble_nop (length, nop_buf);
e0001a05 8541 fragP->tc_frag_data.is_insn = TRUE;
e0001a05 8542
e0001a05
NC		 8543 if (fragP->fr_var < length)
8544 {
43cd72b9 8545 as_fatal (_("fr_var (%ld) < length (%d)"), fragP->fr_var, length);
e0001a05
NC		 8546 return 0;
8547 }
8548
8549 fragP->fr_fix += length;
8550 fragP->fr_var -= length;
e0001a05
NC		 8551 return length;
8552}
8553
8554
7fa3d080
BW		 8555static long future_alignment_required (fragS *, long);
8556
e0001a05 8557static long
7fa3d080 8558relax_frag_for_align (fragS *fragP, long stretch)
e0001a05 8559{
43cd72b9
BW		 8560 /* Overview of the relaxation procedure for alignment:
8561 We can widen with NOPs or by widening instructions or by filling
8562 bytes after jump instructions. Find the opportune places and widen
8563 them if necessary. */
8564
8565 long stretch_me;
8566 long diff;
e0001a05 8567
43cd72b9
BW		 8568 assert (fragP->fr_subtype == RELAX_FILL_NOP
8569 || fragP->fr_subtype == RELAX_UNREACHABLE
8570 || (fragP->fr_subtype == RELAX_SLOTS
8571 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW));
8572
8573 stretch_me = future_alignment_required (fragP, stretch);
8574 diff = stretch_me - fragP->tc_frag_data.text_expansion[0];
8575 if (diff == 0)
8576 return 0;
e0001a05 8577
43cd72b9 8578 if (diff < 0)
e0001a05 8579 {
43cd72b9
BW		 8580 /* We expanded on a previous pass. Can we shrink now? */
8581 long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me;
8582 if (shrink <= stretch && stretch > 0)
e0001a05 8583 {
43cd72b9
BW		 8584 fragP->tc_frag_data.text_expansion[0] = stretch_me;
8585 return -shrink;
e0001a05
NC		 8586 }
8587 return 0;
8588 }
8589
43cd72b9
BW		 8590 /* Below here, diff > 0. */
8591 fragP->tc_frag_data.text_expansion[0] = stretch_me;
e0001a05 8592
43cd72b9 8593 return diff;
e0001a05
NC		 8594}
8595
8596
43cd72b9
BW		 8597/* Return the address of the next frag that should be aligned.
8598
8599 By "address" we mean the address it _would_ be at if there
8600 is no action taken to align it between here and the target frag.
8601 In other words, if no narrows and no fill nops are used between
8602 here and the frag to align, _even_if_ some of the frags we use
8603 to align targets have already expanded on a previous relaxation
8604 pass.
8605
8606 Also, count each frag that may be used to help align the target.
8607
8608 Return 0 if there are no frags left in the chain that need to be
8609 aligned. */
8610
8611static addressT
7fa3d080
BW		 8612find_address_of_next_align_frag (fragS **fragPP,
8613 int *wide_nops,
8614 int *narrow_nops,
8615 int *widens,
8616 bfd_boolean *paddable)
e0001a05 8617{
43cd72b9
BW		 8618 fragS *fragP = *fragPP;
8619 addressT address = fragP->fr_address;
8620
8621 /* Do not reset the counts to 0. */
e0001a05
NC		 8622
8623 while (fragP)
8624 {
8625 /* Limit this to a small search. */
43cd72b9
BW		 8626 if (*widens > 8)
8627 {
8628 *fragPP = fragP;
8629 return 0;
8630 }
e0001a05
NC		 8631 address += fragP->fr_fix;
8632
43cd72b9
BW		 8633 if (fragP->fr_type == rs_fill)
8634 address += fragP->fr_offset * fragP->fr_var;
8635 else if (fragP->fr_type == rs_machine_dependent)
e0001a05 8636 {
e0001a05
NC		 8637 switch (fragP->fr_subtype)
8638 {
43cd72b9
BW		 8639 case RELAX_UNREACHABLE:
8640 *paddable = TRUE;
8641 break;
8642
8643 case RELAX_FILL_NOP:
8644 (*wide_nops)++;
8645 if (!fragP->tc_frag_data.is_no_density)
8646 (*narrow_nops)++;
8647 break;
8648
8649 case RELAX_SLOTS:
8650 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8651 {
8652 (*widens)++;
8653 break;
8654 }
8655 /* FIXME: shouldn't this add the expansion of all slots? */
8656 address += fragP->tc_frag_data.text_expansion[0];
e0001a05
NC		 8657 break;
8658
8659 case RELAX_IMMED:
43cd72b9 8660 address += fragP->tc_frag_data.text_expansion[0];
e0001a05
NC		 8661 break;
8662
8663 case RELAX_ALIGN_NEXT_OPCODE:
8664 case RELAX_DESIRE_ALIGN:
43cd72b9
BW		 8665 *fragPP = fragP;
8666 return address;
8667
8668 case RELAX_MAYBE_UNREACHABLE:
8669 case RELAX_MAYBE_DESIRE_ALIGN:
8670 /* Do nothing. */
e0001a05
NC		 8671 break;
8672
8673 default:
43cd72b9
BW		 8674 /* Just punt if we don't know the type. */
8675 *fragPP = fragP;
8676 return 0;
e0001a05 8677 }
43cd72b9
BW		 8678 }
8679 else
8680 {
8681 /* Just punt if we don't know the type. */
8682 *fragPP = fragP;
8683 return 0;
8684 }
8685 fragP = fragP->fr_next;
8686 }
8687
8688 *fragPP = fragP;
8689 return 0;
8690}
8691
8692
7fa3d080
BW		 8693static long bytes_to_stretch (fragS *, int, int, int, int);
8694
43cd72b9
BW		 8695/* Undefine LOOKAHEAD_ALIGNER to get the older behavior.
8696 I'll leave this in until I am more confident this works. */
8697
8698#define LOOKAHEAD_ALIGNER 1
8699
8700static long
7fa3d080 8701future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED)
43cd72b9
BW		 8702{
8703 fragS *this_frag = fragP;
8704 long address;
8705 int num_widens = 0;
8706 int wide_nops = 0;
8707 int narrow_nops = 0;
8708 bfd_boolean paddable = FALSE;
8709 offsetT local_opt_diff;
8710 offsetT opt_diff;
8711 offsetT max_diff;
8712 int stretch_amount = 0;
8713 int local_stretch_amount;
8714 int global_stretch_amount;
8715
7fa3d080
BW		 8716 address = find_address_of_next_align_frag
8717 (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable);
43cd72b9
BW		 8718
8719 if (address)
8720 {
8721 local_opt_diff = get_aligned_diff (fragP, address, &max_diff);
8722 opt_diff = local_opt_diff;
8723 assert (opt_diff >= 0);
8724 assert (max_diff >= opt_diff);
8725 if (max_diff == 0)
8726 return 0;
8727#ifdef LOOKAHEAD_ALIGNER
8728 if (fragP)
8729 fragP = fragP->fr_next;
8730
8731 while (fragP && opt_diff < max_diff && address)
8732 {
8733 /* We only use these to determine if we can exit early
8734 because there will be plenty of ways to align future
8735 align frags. */
8736 unsigned int glob_widens = 0;
8737 int dnn = 0;
8738 int dw = 0;
8739 bfd_boolean glob_pad = 0;
7fa3d080
BW		 8740 address = find_address_of_next_align_frag
8741 (&fragP, &glob_widens, &dnn, &dw, &glob_pad);
43cd72b9
BW		 8742 /* If there is a padable portion, then skip. */
8743 if (glob_pad || (glob_widens >= xtensa_fetch_width))
8744 break;
8745
8746 if (address)
8747 {
8748 offsetT next_m_diff;
8749 offsetT next_o_diff;
8750
8751 /* Downrange frags haven't had stretch added to them yet. */
8752 address += stretch;
8753
8754 /* The address also includes any text expansion from this
8755 frag in a previous pass, but we don't want that. */
8756 address -= this_frag->tc_frag_data.text_expansion[0];
8757
8758 /* Assume we are going to move at least opt_diff. In
8759 reality, we might not be able to, but assuming that
8760 we will helps catch cases where moving opt_diff pushes
8761 the next target from aligned to unaligned. */
8762 address += opt_diff;
8763
8764 next_o_diff = get_aligned_diff (fragP, address, &next_m_diff);
8765
8766 /* Now cleanup for the adjustments to address. */
8767 next_o_diff += opt_diff;
8768 next_m_diff += opt_diff;
8769 if (next_o_diff <= max_diff && next_o_diff > opt_diff)
8770 opt_diff = next_o_diff;
8771 if (next_m_diff < max_diff)
8772 max_diff = next_m_diff;
8773 fragP = fragP->fr_next;
8774 }
8775 }
8776#endif /* LOOKAHEAD_ALIGNER */
8777 /* If there are enough wideners in between, do it. */
8778 if (paddable)
8779 {
8780 if (this_frag->fr_subtype == RELAX_UNREACHABLE)
8781 {
8782 assert (opt_diff <= UNREACHABLE_MAX_WIDTH);
8783 return opt_diff;
8784 }
8785 return 0;
8786 }
8787 local_stretch_amount
8788 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
8789 num_widens, local_opt_diff);
8790#ifdef LOOKAHEAD_ALIGNER
8791 global_stretch_amount
8792 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
8793 num_widens, opt_diff);
8794 /* If the condition below is true, then the frag couldn't
8795 stretch the correct amount for the global case, so we just
8796 optimize locally. We'll rely on the subsequent frags to get
8797 the correct alignment in the global case. */
8798 if (global_stretch_amount < local_stretch_amount)
8799 stretch_amount = local_stretch_amount;
8800 else
8801 stretch_amount = global_stretch_amount;
8802#else /* ! LOOKAHEAD_ALIGNER */
8803 stretch_amount = local_stretch_amount;
8804#endif /* ! LOOKAHEAD_ALIGNER */
8805 if (this_frag->fr_subtype == RELAX_SLOTS
8806 && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8807 assert (stretch_amount <= 1);
8808 else if (this_frag->fr_subtype == RELAX_FILL_NOP)
8809 {
8810 if (this_frag->tc_frag_data.is_no_density)
8811 assert (stretch_amount == 3 || stretch_amount == 0);
8812 else
8813 assert (stretch_amount <= 3);
8814 }
8815 }
8816 return stretch_amount;
8817}
8818
8819
8820/* The idea: widen everything you can to get a target or loop aligned,
8821 then start using NOPs.
8822
8823 When we must have a NOP, here is a table of how we decide
8824 (so you don't have to fight through the control flow below):
8825
8826 wide_nops = the number of wide NOPs available for aligning
8827 narrow_nops = the number of narrow NOPs available for aligning
8828 (a subset of wide_nops)
8829 widens = the number of narrow instructions that should be widened
8830
8831 Desired wide narrow
8832 Diff nop nop widens
8833 1 0 0 1
8834 2 0 1 0
8835 3a 1 0 0
8836 b 0 1 1 (case 3a makes this case unnecessary)
8837 4a 1 0 1
8838 b 0 2 0
8839 c 0 1 2 (case 4a makes this case unnecessary)
8840 5a 1 0 2
8841 b 1 1 0
8842 c 0 2 1 (case 5b makes this case unnecessary)
8843 6a 2 0 0
8844 b 1 0 3
8845 c 0 1 4 (case 6b makes this case unneccesary)
8846 d 1 1 1 (case 6a makes this case unnecessary)
8847 e 0 2 2 (case 6a makes this case unnecessary)
8848 f 0 3 0 (case 6a makes this case unnecessary)
8849 7a 1 0 4
8850 b 2 0 1
8851 c 1 1 2 (case 7b makes this case unnecessary)
8852 d 0 1 5 (case 7a makes this case unnecessary)
8853 e 0 2 3 (case 7b makes this case unnecessary)
8854 f 0 3 1 (case 7b makes this case unnecessary)
8855 g 1 2 1 (case 7b makes this case unnecessary)
8856*/
8857
8858static long
7fa3d080
BW		 8859bytes_to_stretch (fragS *this_frag,
8860 int wide_nops,
8861 int narrow_nops,
8862 int num_widens,
8863 int desired_diff)
43cd72b9
BW		 8864{
8865 int bytes_short = desired_diff - num_widens;
8866
8867 assert (desired_diff >= 0 && desired_diff < 8);
8868 if (desired_diff == 0)
8869 return 0;
8870
8871 assert (wide_nops > 0 || num_widens > 0);
e0001a05 8872
43cd72b9
BW		 8873 /* Always prefer widening to NOP-filling. */
8874 if (bytes_short < 0)
8875 {
8876 /* There are enough RELAX_NARROW frags after this one
8877 to align the target without widening this frag in any way. */
8878 return 0;
8879 }
8880
8881 if (bytes_short == 0)
8882 {
8883 /* Widen every narrow between here and the align target
8884 and the align target will be properly aligned. */
8885 if (this_frag->fr_subtype == RELAX_FILL_NOP)
8886 return 0;
8887 else
8888 return 1;
8889 }
8890
8891 /* From here we will need at least one NOP to get an alignment.
8892 However, we may not be able to align at all, in which case,
8893 don't widen. */
8894 if (this_frag->fr_subtype == RELAX_FILL_NOP)
8895 {
8896 switch (desired_diff)
8897 {
8898 case 1:
8899 return 0;
8900 case 2:
8901 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1)
8902 return 2; /* case 2 */
8903 return 0;
8904 case 3:
8905 if (wide_nops > 1)
8906 return 0;
8907 else
8908 return 3; /* case 3a */
8909 case 4:
8910 if (num_widens >= 1 && wide_nops == 1)
8911 return 3; /* case 4a */
8912 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2)
8913 return 2; /* case 4b */
8914 return 0;
8915 case 5:
8916 if (num_widens >= 2 && wide_nops == 1)
8917 return 3; /* case 5a */
8918 /* We will need two nops. Are there enough nops
8919 between here and the align target? */
8920 if (wide_nops < 2 || narrow_nops == 0)
8921 return 0;
8922 /* Are there other nops closer that can serve instead? */
8923 if (wide_nops > 2 && narrow_nops > 1)
8924 return 0;
8925 /* Take the density one first, because there might not be
8926 another density one available. */
8927 if (!this_frag->tc_frag_data.is_no_density)
8928 return 2; /* case 5b narrow */
8929 else
8930 return 3; /* case 5b wide */
8931 return 0;
8932 case 6:
8933 if (wide_nops == 2)
8934 return 3; /* case 6a */
8935 else if (num_widens >= 3 && wide_nops == 1)
8936 return 3; /* case 6b */
8937 return 0;
8938 case 7:
8939 if (wide_nops == 1 && num_widens >= 4)
8940 return 3; /* case 7a */
8941 else if (wide_nops == 2 && num_widens >= 1)
8942 return 3; /* case 7b */
8943 return 0;
e0001a05 8944 default:
43cd72b9 8945 assert (0);
e0001a05 8946 }
e0001a05 8947 }
43cd72b9
BW		 8948 else
8949 {
8950 /* We will need a NOP no matter what, but should we widen
8951 this instruction to help?
e0001a05 8952
43cd72b9
BW		 8953 This is a RELAX_FRAG_NARROW frag. */
8954 switch (desired_diff)
8955 {
8956 case 1:
8957 assert (0);
8958 return 0;
8959 case 2:
8960 case 3:
8961 return 0;
8962 case 4:
8963 if (wide_nops >= 1 && num_widens == 1)
8964 return 1; /* case 4a */
8965 return 0;
8966 case 5:
8967 if (wide_nops >= 1 && num_widens == 2)
8968 return 1; /* case 5a */
8969 return 0;
8970 case 6:
8971 if (wide_nops >= 2)
8972 return 0; /* case 6a */
8973 else if (wide_nops >= 1 && num_widens == 3)
8974 return 1; /* case 6b */
8975 return 0;
8976 case 7:
8977 if (wide_nops >= 1 && num_widens == 4)
8978 return 1; /* case 7a */
8979 else if (wide_nops >= 2 && num_widens == 1)
8980 return 1; /* case 7b */
8981 return 0;
8982 default:
8983 assert (0);
8984 return 0;
8985 }
8986 }
8987 assert (0);
8988 return 0;
e0001a05
NC		 8989}
8990
8991
8992static long
7fa3d080
BW		 8993relax_frag_immed (segT segP,
8994 fragS *fragP,
8995 long stretch,
8996 int min_steps,
8997 xtensa_format fmt,
8998 int slot,
8999 int *stretched_p,
9000 bfd_boolean estimate_only)
e0001a05 9001{
43cd72b9
BW		 9002 TInsn tinsn;
9003 vliw_insn orig_vinsn;
e0001a05
NC		 9004 int old_size;
9005 bfd_boolean negatable_branch = FALSE;
9006 bfd_boolean branch_jmp_to_next = FALSE;
43cd72b9
BW		 9007 bfd_boolean wide_insn = FALSE;
9008 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 9009 IStack istack;
9010 offsetT frag_offset;
9011 int num_steps;
9012 fragS *lit_fragP;
9013 int num_text_bytes, num_literal_bytes;
43cd72b9 9014 int literal_diff, total_text_diff, this_text_diff, first;
e0001a05
NC		 9015
9016 assert (fragP->fr_opcode != NULL);
9017
43cd72b9
BW		 9018 xg_init_vinsn (&orig_vinsn);
9019 vinsn_from_chars (&orig_vinsn, fragP->fr_opcode);
9020 if (xtensa_format_num_slots (isa, fmt) > 1)
9021 wide_insn = TRUE;
9022
9023 tinsn = orig_vinsn.slots[slot];
9024 tinsn_immed_from_frag (&tinsn, fragP, slot);
e0001a05 9025
43cd72b9
BW		 9026 if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode))
9027 return 0;
e0001a05 9028
b08b5071 9029 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
43cd72b9 9030 branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP);
e0001a05 9031
43cd72b9 9032 negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1);
e0001a05 9033
43cd72b9 9034 old_size = xtensa_format_length (isa, fmt);
e0001a05
NC		 9035
9036 /* Special case: replace a branch to the next instruction with a NOP.
9037 This is required to work around a hardware bug in T1040.0 and also
9038 serves as an optimization. */
9039
9040 if (branch_jmp_to_next
9041 && ((old_size == 2) || (old_size == 3))
9042 && !next_frag_is_loop_target (fragP))
9043 return 0;
9044
9045 /* Here is the fun stuff: Get the immediate field from this
9046 instruction. If it fits, we are done. If not, find the next
9047 instruction sequence that fits. */
9048
9049 frag_offset = fragP->fr_opcode - fragP->fr_literal;
9050 istack_init (&istack);
43cd72b9 9051 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset,
e0001a05
NC		 9052 min_steps, stretch);
9053 if (num_steps < min_steps)
9054 {
9055 as_fatal (_("internal error: relaxation failed"));
9056 return 0;
9057 }
9058
9059 if (num_steps > RELAX_IMMED_MAXSTEPS)
9060 {
9061 as_fatal (_("internal error: relaxation requires too many steps"));
9062 return 0;
9063 }
9064
43cd72b9 9065 fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps;
e0001a05
NC		 9066
9067 /* Figure out the number of bytes needed. */
9068 lit_fragP = 0;
e0001a05 9069 num_literal_bytes = get_num_stack_literal_bytes (&istack);
43cd72b9
BW		 9070 literal_diff =
9071 num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
9072 first = 0;
9073 while (istack.insn[first].opcode == XTENSA_UNDEFINED)
9074 first++;
9075 num_text_bytes = get_num_stack_text_bytes (&istack);
9076 if (wide_insn)
9077 {
9078 num_text_bytes += old_size;
9079 if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot))
9080 num_text_bytes -= xg_get_single_size (istack.insn[first].opcode);
9081 }
9082 total_text_diff = num_text_bytes - old_size;
9083 this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot];
e0001a05
NC		 9084
9085 /* It MUST get larger. If not, we could get an infinite loop. */
43cd72b9
BW		 9086 assert (num_text_bytes >= 0);
9087 assert (literal_diff >= 0);
9088 assert (total_text_diff >= 0);
e0001a05 9089
43cd72b9
BW		 9090 fragP->tc_frag_data.text_expansion[slot] = total_text_diff;
9091 fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes;
9092 assert (fragP->tc_frag_data.text_expansion[slot] >= 0);
9093 assert (fragP->tc_frag_data.literal_expansion[slot] >= 0);
e0001a05
NC		 9094
9095 /* Find the associated expandable literal for this. */
9096 if (literal_diff != 0)
9097 {
43cd72b9 9098 lit_fragP = fragP->tc_frag_data.literal_frags[slot];
e0001a05
NC		 9099 if (lit_fragP)
9100 {
9101 assert (literal_diff == 4);
9102 lit_fragP->tc_frag_data.unreported_expansion += literal_diff;
9103
9104 /* We expect that the literal section state has NOT been
9105 modified yet. */
9106 assert (lit_fragP->fr_type == rs_machine_dependent
9107 && lit_fragP->fr_subtype == RELAX_LITERAL);
9108 lit_fragP->fr_subtype = RELAX_LITERAL_NR;
9109
9110 /* We need to mark this section for another iteration
9111 of relaxation. */
9112 (*stretched_p)++;
9113 }
9114 }
9115
43cd72b9
BW		 9116 /* FIXME: When a negatable branch expands and then contracts in a
9117 subsequent pass, update_next_frag_state correctly updates the
9118 type of the frag to RELAX_MAYBE_UNREACHABLE, but it doesn't undo
9119 any expansion relax_frag_for_align may have expected it to. For
9120 now, change back to only call it when the branch expands. */
9121 if (negatable_branch && istack.ninsn > 1)
9122 update_next_frag_state (fragP, FALSE /* istack.ninsn > 1 */);
e0001a05 9123
43cd72b9 9124 return this_text_diff;
e0001a05
NC		 9125}
9126
9127\f
9128/* md_convert_frag Hook and Helper Functions. */
9129
7fa3d080
BW		 9130static void convert_frag_align_next_opcode (fragS *);
9131static void convert_frag_narrow (segT, fragS *, xtensa_format, int);
9132static void convert_frag_fill_nop (fragS *);
9133static void convert_frag_immed (segT, fragS *, int, xtensa_format, int);
9134
e0001a05 9135void
7fa3d080 9136md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
e0001a05 9137{
43cd72b9
BW		 9138 static xtensa_insnbuf vbuf = NULL;
9139 xtensa_isa isa = xtensa_default_isa;
9140 int slot;
9141 int num_slots;
9142 xtensa_format fmt;
e0001a05
NC		 9143 char *file_name;
9144 int line;
9145
9146 as_where (&file_name, &line);
9147 new_logical_line (fragp->fr_file, fragp->fr_line);
9148
9149 switch (fragp->fr_subtype)
9150 {
9151 case RELAX_ALIGN_NEXT_OPCODE:
9152 /* Always convert. */
9153 convert_frag_align_next_opcode (fragp);
9154 break;
9155
9156 case RELAX_DESIRE_ALIGN:
9157 /* Do nothing. If not aligned already, too bad. */
9158 break;
9159
43cd72b9
BW		 9160 case RELAX_LITERAL:
9161 case RELAX_LITERAL_FINAL:
9162 break;
9163
9164 case RELAX_SLOTS:
9165 if (vbuf == NULL)
9166 vbuf = xtensa_insnbuf_alloc (isa);
9167
9168 xtensa_insnbuf_from_chars (isa, vbuf, fragp->fr_opcode, 0);
9169 fmt = xtensa_format_decode (isa, vbuf);
9170 num_slots = xtensa_format_num_slots (isa, fmt);
9171
9172 for (slot = 0; slot < num_slots; slot++)
9173 {
9174 switch (fragp->tc_frag_data.slot_subtypes[slot])
9175 {
9176 case RELAX_NARROW:
9177 convert_frag_narrow (sec, fragp, fmt, slot);
9178 break;
9179
9180 case RELAX_IMMED:
9181 case RELAX_IMMED_STEP1:
9182 case RELAX_IMMED_STEP2:
9183 /* Place the immediate. */
9184 convert_frag_immed
9185 (sec, fragp,
9186 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
9187 fmt, slot);
9188 break;
9189
9190 default:
9191 /* This is OK because some slots could have
9192 relaxations and others have none. */
9193 break;
9194 }
9195 }
9196 break;
9197
9198 case RELAX_UNREACHABLE:
9199 memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var);
9200 fragp->fr_fix += fragp->tc_frag_data.text_expansion[0];
9201 fragp->fr_var -= fragp->tc_frag_data.text_expansion[0];
9202 frag_wane (fragp);
e0001a05
NC		 9203 break;
9204
43cd72b9
BW		 9205 case RELAX_MAYBE_UNREACHABLE:
9206 case RELAX_MAYBE_DESIRE_ALIGN:
9207 frag_wane (fragp);
e0001a05
NC		 9208 break;
9209
43cd72b9
BW		 9210 case RELAX_FILL_NOP:
9211 convert_frag_fill_nop (fragp);
e0001a05
NC		 9212 break;
9213
9214 case RELAX_LITERAL_NR:
9215 if (use_literal_section)
9216 {
9217 /* This should have been handled during relaxation. When
9218 relaxing a code segment, literals sometimes need to be
9219 added to the corresponding literal segment. If that
9220 literal segment has already been relaxed, then we end up
9221 in this situation. Marking the literal segments as data
9222 would make this happen less often (since GAS always relaxes
9223 code before data), but we could still get into trouble if
9224 there are instructions in a segment that is not marked as
9225 containing code. Until we can implement a better solution,
9226 cheat and adjust the addresses of all the following frags.
9227 This could break subsequent alignments, but the linker's
9228 literal coalescing will do that anyway. */
9229
9230 fragS *f;
9231 fragp->fr_subtype = RELAX_LITERAL_FINAL;
9232 assert (fragp->tc_frag_data.unreported_expansion == 4);
9233 memset (&fragp->fr_literal[fragp->fr_fix], 0, 4);
9234 fragp->fr_var -= 4;
9235 fragp->fr_fix += 4;
9236 for (f = fragp->fr_next; f; f = f->fr_next)
9237 f->fr_address += 4;
9238 }
9239 else
9240 as_bad (_("invalid relaxation fragment result"));
9241 break;
9242 }
9243
9244 fragp->fr_var = 0;
9245 new_logical_line (file_name, line);
9246}
9247
9248
7fa3d080
BW		 9249static void
9250convert_frag_align_next_opcode (fragS *fragp)
e0001a05
NC		 9251{
9252 char *nop_buf; /* Location for Writing. */
9253 size_t i;
9254
9255 bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density;
9256 addressT aligned_address;
9257 size_t fill_size, nop_count;
9258
9259 aligned_address = get_noop_aligned_address (fragp, fragp->fr_address +
9260 fragp->fr_fix);
9261 fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix);
9262 nop_count = get_text_align_nop_count (fill_size, use_no_density);
9263 nop_buf = fragp->fr_literal + fragp->fr_fix;
9264
9265 for (i = 0; i < nop_count; i++)
9266 {
9267 size_t nop_size;
9268 nop_size = get_text_align_nth_nop_size (fill_size, i, use_no_density);
9269
9270 assemble_nop (nop_size, nop_buf);
9271 nop_buf += nop_size;
9272 }
9273
9274 fragp->fr_fix += fill_size;
9275 fragp->fr_var -= fill_size;
9276}
9277
9278
9279static void
7fa3d080 9280convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
e0001a05 9281{
43cd72b9
BW		 9282 TInsn tinsn, single_target;
9283 xtensa_format single_fmt;
e0001a05
NC		 9284 int size, old_size, diff, error_val;
9285 offsetT frag_offset;
9286
43cd72b9
BW		 9287 assert (slot == 0);
9288 tinsn_from_chars (&tinsn, fragP->fr_opcode, 0);
9289
9290 if (xtensa_opcode_is_branch (xtensa_default_isa, tinsn.opcode) == 1)
9291 {
9292 assert (fragP->tc_frag_data.text_expansion[0] == 1
9293 || fragP->tc_frag_data.text_expansion[0] == 0);
9294 convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0],
9295 fmt, slot);
9296 return;
9297 }
9298
9299 if (fragP->tc_frag_data.text_expansion[0] == 0)
e0001a05
NC		 9300 {
9301 /* No conversion. */
9302 fragP->fr_var = 0;
9303 return;
9304 }
9305
9306 assert (fragP->fr_opcode != NULL);
9307
43cd72b9
BW		 9308 /* Frags in this relaxation state should only contain
9309 single instruction bundles. */
9310 tinsn_immed_from_frag (&tinsn, fragP, 0);
e0001a05
NC		 9311
9312 /* Just convert it to a wide form.... */
9313 size = 0;
43cd72b9 9314 old_size = xg_get_single_size (tinsn.opcode);
e0001a05
NC		 9315
9316 tinsn_init (&single_target);
9317 frag_offset = fragP->fr_opcode - fragP->fr_literal;
9318
43cd72b9 9319 error_val = xg_expand_narrow (&single_target, &tinsn);
e0001a05 9320 if (error_val)
43cd72b9
BW		 9321 {
9322 as_bad (_("unable to widen instruction"));
9323 return;
9324 }
9325
9326 size = xg_get_single_size (single_target.opcode);
9327 single_fmt = xg_get_single_format (single_target.opcode);
e0001a05 9328
43cd72b9 9329 xg_emit_insn_to_buf (&single_target, single_fmt, fragP->fr_opcode,
e0001a05
NC		 9330 fragP, frag_offset, TRUE);
9331
9332 diff = size - old_size;
9333 assert (diff >= 0);
9334 assert (diff <= fragP->fr_var);
9335 fragP->fr_var -= diff;
9336 fragP->fr_fix += diff;
9337
9338 /* clean it up */
9339 fragP->fr_var = 0;
9340}
9341
9342
9343static void
7fa3d080 9344convert_frag_fill_nop (fragS *fragP)
43cd72b9
BW		 9345{
9346 char *loc = &fragP->fr_literal[fragP->fr_fix];
9347 int size = fragP->tc_frag_data.text_expansion[0];
9348 assert ((unsigned) size == (fragP->fr_next->fr_address
9349 - fragP->fr_address - fragP->fr_fix));
9350 if (size == 0)
9351 {
9352 /* No conversion. */
9353 fragP->fr_var = 0;
9354 return;
9355 }
9356 assemble_nop (size, loc);
9357 fragP->tc_frag_data.is_insn = TRUE;
9358 fragP->fr_var -= size;
9359 fragP->fr_fix += size;
9360 frag_wane (fragP);
9361}
9362
9363
7fa3d080
BW		 9364static fixS *fix_new_exp_in_seg
9365 (segT, subsegT, fragS *, int, int, expressionS *, int,
9366 bfd_reloc_code_real_type);
9367static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *);
9368
43cd72b9 9369static void
7fa3d080
BW		 9370convert_frag_immed (segT segP,
9371 fragS *fragP,
9372 int min_steps,
9373 xtensa_format fmt,
9374 int slot)
e0001a05
NC		 9375{
9376 char *immed_instr = fragP->fr_opcode;
43cd72b9 9377 TInsn orig_tinsn;
e0001a05 9378 bfd_boolean expanded = FALSE;
e0001a05 9379 bfd_boolean branch_jmp_to_next = FALSE;
43cd72b9
BW		 9380 char *fr_opcode = fragP->fr_opcode;
9381 vliw_insn orig_vinsn;
9382 xtensa_isa isa = xtensa_default_isa;
9383 bfd_boolean wide_insn = FALSE;
9384 int bytes;
9385 bfd_boolean is_loop;
e0001a05 9386
43cd72b9 9387 assert (fr_opcode != NULL);
e0001a05 9388
43cd72b9 9389 xg_init_vinsn (&orig_vinsn);
e0001a05 9390
43cd72b9
BW		 9391 vinsn_from_chars (&orig_vinsn, fr_opcode);
9392 if (xtensa_format_num_slots (isa, fmt) > 1)
9393 wide_insn = TRUE;
e0001a05 9394
43cd72b9
BW		 9395 orig_tinsn = orig_vinsn.slots[slot];
9396 tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
9397
9398 is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1;
e0001a05 9399
b08b5071 9400 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
43cd72b9 9401 branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP);
e0001a05
NC		 9402
9403 if (branch_jmp_to_next && !next_frag_is_loop_target (fragP))
9404 {
9405 /* Conversion just inserts a NOP and marks the fix as completed. */
43cd72b9
BW		 9406 bytes = xtensa_format_length (isa, fmt);
9407 if (bytes >= 4)
9408 {
9409 orig_vinsn.slots[slot].opcode =
9410 xtensa_format_slot_nop_opcode (isa, orig_vinsn.format, slot);
9411 orig_vinsn.slots[slot].ntok = 0;
9412 }
9413 else
9414 {
9415 bytes += fragP->tc_frag_data.text_expansion[0];
9416 assert (bytes == 2 || bytes == 3);
9417 build_nop (&orig_vinsn.slots[0], bytes);
9418 fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
9419 }
9420 vinsn_to_insnbuf (&orig_vinsn, fr_opcode, frag_now, FALSE);
9421 xtensa_insnbuf_to_chars (isa, orig_vinsn.insnbuf, fr_opcode, 0);
e0001a05
NC		 9422 fragP->fr_var = 0;
9423 }
43cd72b9 9424 else if (!orig_tinsn.is_specific_opcode)
e0001a05 9425 {
43cd72b9
BW		 9426 /* Here is the fun stuff: Get the immediate field from this
9427 instruction. If it fits, we're done. If not, find the next
9428 instruction sequence that fits. */
9429
e0001a05
NC		 9430 IStack istack;
9431 int i;
9432 symbolS *lit_sym = NULL;
9433 int total_size = 0;
43cd72b9 9434 int target_offset = 0;
e0001a05
NC		 9435 int old_size;
9436 int diff;
9437 symbolS *gen_label = NULL;
9438 offsetT frag_offset;
43cd72b9
BW		 9439 bfd_boolean first = TRUE;
9440 bfd_boolean last_is_jump;
e0001a05 9441
43cd72b9 9442 /* It does not fit. Find something that does and
e0001a05 9443 convert immediately. */
43cd72b9 9444 frag_offset = fr_opcode - fragP->fr_literal;
e0001a05 9445 istack_init (&istack);
43cd72b9 9446 xg_assembly_relax (&istack, &orig_tinsn,
e0001a05
NC		 9447 segP, fragP, frag_offset, min_steps, 0);
9448
43cd72b9 9449 old_size = xtensa_format_length (isa, fmt);
e0001a05
NC		 9450
9451 /* Assemble this right inline. */
9452
9453 /* First, create the mapping from a label name to the REAL label. */
43cd72b9 9454 target_offset = 0;
e0001a05
NC		 9455 for (i = 0; i < istack.ninsn; i++)
9456 {
43cd72b9 9457 TInsn *tinsn = &istack.insn[i];
e0001a05
NC		 9458 fragS *lit_frag;
9459
43cd72b9 9460 switch (tinsn->insn_type)
e0001a05
NC		 9461 {
9462 case ITYPE_LITERAL:
9463 if (lit_sym != NULL)
9464 as_bad (_("multiple literals in expansion"));
9465 /* First find the appropriate space in the literal pool. */
43cd72b9 9466 lit_frag = fragP->tc_frag_data.literal_frags[slot];
e0001a05
NC		 9467 if (lit_frag == NULL)
9468 as_bad (_("no registered fragment for literal"));
43cd72b9 9469 if (tinsn->ntok != 1)
e0001a05
NC		 9470 as_bad (_("number of literal tokens != 1"));
9471
9472 /* Set the literal symbol and add a fixup. */
9473 lit_sym = lit_frag->fr_symbol;
9474 break;
9475
9476 case ITYPE_LABEL:
43cd72b9
BW		 9477 if (align_targets && !is_loop)
9478 {
9479 fragS *unreach = fragP->fr_next;
9480 while (!(unreach->fr_type == rs_machine_dependent
9481 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9482 || unreach->fr_subtype == RELAX_UNREACHABLE)))
9483 {
9484 unreach = unreach->fr_next;
9485 }
9486
9487 assert (unreach->fr_type == rs_machine_dependent
9488 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9489 || unreach->fr_subtype == RELAX_UNREACHABLE));
9490
9491 target_offset += unreach->tc_frag_data.text_expansion[0];
9492 }
e0001a05
NC		 9493 assert (gen_label == NULL);
9494 gen_label = symbol_new (FAKE_LABEL_NAME, now_seg,
43cd72b9
BW		 9495 fr_opcode - fragP->fr_literal
9496 + target_offset, fragP);
e0001a05
NC		 9497 break;
9498
9499 case ITYPE_INSN:
43cd72b9
BW		 9500 if (first && wide_insn)
9501 {
9502 target_offset += xtensa_format_length (isa, fmt);
9503 first = FALSE;
9504 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9505 target_offset += xg_get_single_size (tinsn->opcode);
9506 }
9507 else
9508 target_offset += xg_get_single_size (tinsn->opcode);
e0001a05
NC		 9509 break;
9510 }
9511 }
9512
9513 total_size = 0;
43cd72b9
BW		 9514 first = TRUE;
9515 last_is_jump = FALSE;
e0001a05
NC		 9516 for (i = 0; i < istack.ninsn; i++)
9517 {
43cd72b9 9518 TInsn *tinsn = &istack.insn[i];
e0001a05
NC		 9519 fragS *lit_frag;
9520 int size;
9521 segT target_seg;
43cd72b9 9522 bfd_reloc_code_real_type reloc_type;
e0001a05 9523
43cd72b9 9524 switch (tinsn->insn_type)
e0001a05
NC		 9525 {
9526 case ITYPE_LITERAL:
43cd72b9
BW		 9527 lit_frag = fragP->tc_frag_data.literal_frags[slot];
9528 /* Already checked. */
e0001a05
NC		 9529 assert (lit_frag != NULL);
9530 assert (lit_sym != NULL);
43cd72b9
BW		 9531 assert (tinsn->ntok == 1);
9532 /* Add a fixup. */
e0001a05
NC		 9533 target_seg = S_GET_SEGMENT (lit_sym);
9534 assert (target_seg);
43cd72b9
BW		 9535 if (tinsn->tok[0].X_op == O_pltrel)
9536 reloc_type = BFD_RELOC_XTENSA_PLT;
9537 else
9538 reloc_type = BFD_RELOC_32;
e0001a05 9539 fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
43cd72b9 9540 &tinsn->tok[0], FALSE, reloc_type);
e0001a05
NC		 9541 break;
9542
9543 case ITYPE_LABEL:
9544 break;
9545
9546 case ITYPE_INSN:
43cd72b9
BW		 9547 xg_resolve_labels (tinsn, gen_label);
9548 xg_resolve_literals (tinsn, lit_sym);
9549 if (wide_insn && first)
9550 {
9551 first = FALSE;
9552 if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9553 {
9554 tinsn->record_fix = TRUE;
9555 orig_vinsn.slots[slot] = *tinsn;
9556 }
9557 else
9558 {
9559 orig_vinsn.slots[slot].opcode =
9560 xtensa_format_slot_nop_opcode (isa, fmt, slot);
9561 orig_vinsn.slots[slot].ntok = 0;
9562 orig_vinsn.slots[slot].record_fix = FALSE;
9563 }
9564 vinsn_to_insnbuf (&orig_vinsn, immed_instr, fragP, TRUE);
9565 xtensa_insnbuf_to_chars (isa, orig_vinsn.insnbuf,
9566 immed_instr, 0);
9567 fragP->tc_frag_data.is_insn = TRUE;
9568 size = xtensa_format_length (isa, fmt);
9569 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9570 {
9571 xtensa_format single_fmt =
9572 xg_get_single_format (tinsn->opcode);
9573
9574 xg_emit_insn_to_buf
9575 (tinsn, single_fmt, immed_instr + size, fragP,
9576 immed_instr - fragP->fr_literal + size, TRUE);
9577 size += xg_get_single_size (tinsn->opcode);
9578 }
9579 }
9580 else
9581 {
9582 xtensa_format single_format;
9583 size = xg_get_single_size (tinsn->opcode);
9584 single_format = xg_get_single_format (tinsn->opcode);
9585 xg_emit_insn_to_buf (tinsn, single_format, immed_instr,
9586 fragP,
9587 immed_instr - fragP->fr_literal, TRUE);
9588#if 0
9589 /* Code to recognize branch-around expansion
9590 so the fragment is properly marked as ending in a
9591 jump. */
9592 if ((((i == istack.ninsn - 2)
9593 && (istack.insn[istack.ninsn-1].insn_type
9594 == ITYPE_LABEL))
9595 || i == istack.ninsn -1)
9596 && xtensa_opcode_is_jump (xtensa_default_isa,
9597 tinsn->opcode) == 1
9598 && fragP->fr_next != NULL
9599 && ! fragP->fr_next->tc_frag_data.is_unreachable)
9600 {
9601 /* Create a new unreachable frag of zero size. */
9602 size_t frag_size = sizeof (fragS);
9603 fragS *new_fragP = (fragS *) xmalloc (frag_size);
9604 memset (new_fragP, 0, frag_size);
9605 new_fragP->fr_address = fragP->fr_next->fr_address;
9606 new_fragP->fr_next = fragP->fr_next;
9607 new_fragP->fr_fix = 0;
9608 new_fragP->fr_var = 0;
9609 new_fragP->fr_type = rs_fill;
9610 new_fragP->tc_frag_data.is_unreachable = TRUE;
9611 /* The rest are zeros.... */
9612 /* Link it in to the chain. */
9613 fragP->fr_next = new_fragP;
9614 }
9615#endif
9616 }
e0001a05 9617 immed_instr += size;
43cd72b9 9618 total_size += size;
e0001a05
NC		 9619 break;
9620 }
9621 }
9622
9623 diff = total_size - old_size;
9624 assert (diff >= 0);
9625 if (diff != 0)
9626 expanded = TRUE;
9627 assert (diff <= fragP->fr_var);
9628 fragP->fr_var -= diff;
9629 fragP->fr_fix += diff;
9630 }
9631
9632 /* Clean it up. */
43cd72b9 9633 xg_free_vinsn (&orig_vinsn);
e0001a05
NC		 9634
9635 /* Check for undefined immediates in LOOP instructions. */
43cd72b9 9636 if (is_loop)
e0001a05
NC		 9637 {
9638 symbolS *sym;
43cd72b9 9639 sym = orig_tinsn.tok[1].X_add_symbol;
e0001a05
NC		 9640 if (sym != NULL && !S_IS_DEFINED (sym))
9641 {
9642 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9643 return;
9644 }
43cd72b9 9645 sym = orig_tinsn.tok[1].X_op_symbol;
e0001a05
NC		 9646 if (sym != NULL && !S_IS_DEFINED (sym))
9647 {
9648 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9649 return;
9650 }
9651 }
9652
43cd72b9
BW		 9653 if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1)
9654 convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn);
e0001a05 9655
43cd72b9 9656 if (expanded && is_direct_call_opcode (orig_tinsn.opcode))
e0001a05
NC		 9657 {
9658 /* Add an expansion note on the expanded instruction. */
9659 fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
43cd72b9 9660 &orig_tinsn.tok[0], TRUE,
e0001a05 9661 BFD_RELOC_XTENSA_ASM_EXPAND);
e0001a05
NC		 9662 }
9663}
9664
9665
9666/* Add a new fix expression into the desired segment. We have to
9667 switch to that segment to do this. */
9668
9669static fixS *
7fa3d080
BW		 9670fix_new_exp_in_seg (segT new_seg,
9671 subsegT new_subseg,
9672 fragS *frag,
9673 int where,
9674 int size,
9675 expressionS *exp,
9676 int pcrel,
9677 bfd_reloc_code_real_type r_type)
e0001a05
NC		 9678{
9679 fixS *new_fix;
9680 segT seg = now_seg;
9681 subsegT subseg = now_subseg;
43cd72b9 9682
e0001a05
NC		 9683 assert (new_seg != 0);
9684 subseg_set (new_seg, new_subseg);
9685
e0001a05
NC		 9686 new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
9687 subseg_set (seg, subseg);
9688 return new_fix;
9689}
9690
9691
43cd72b9
BW		 9692/* Relax a loop instruction so that it can span loop >256 bytes.
9693
9694 loop as, .L1
9695 .L0:
9696 rsr as, LEND
9697 wsr as, LBEG
9698 addi as, as, lo8 (label-.L1)
9699 addmi as, as, mid8 (label-.L1)
9700 wsr as, LEND
9701 isync
9702 rsr as, LCOUNT
9703 addi as, as, 1
9704 .L1:
9705 <<body>>
9706 label:
9707*/
e0001a05
NC		 9708
9709static void
7fa3d080 9710convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn)
e0001a05
NC		 9711{
9712 TInsn loop_insn;
9713 TInsn addi_insn;
9714 TInsn addmi_insn;
9715 unsigned long target;
9716 static xtensa_insnbuf insnbuf = NULL;
9717 unsigned int loop_length, loop_length_hi, loop_length_lo;
9718 xtensa_isa isa = xtensa_default_isa;
9719 addressT loop_offset;
9720 addressT addi_offset = 9;
9721 addressT addmi_offset = 12;
43cd72b9
BW		 9722 fragS *next_fragP;
9723 size_t target_count;
e0001a05
NC		 9724
9725 if (!insnbuf)
9726 insnbuf = xtensa_insnbuf_alloc (isa);
9727
9728 /* Get the loop offset. */
43cd72b9 9729 loop_offset = get_expanded_loop_offset (tinsn->opcode);
e0001a05 9730
43cd72b9
BW		 9731 /* Validate that there really is a LOOP at the loop_offset. Because
9732 loops are not bundleable, we can assume that the instruction will be
9733 in slot 0. */
9734 tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0);
9735 tinsn_immed_from_frag (&loop_insn, fragP, 0);
9736
9737 assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1);
e0001a05
NC		 9738 addi_offset += loop_offset;
9739 addmi_offset += loop_offset;
9740
43cd72b9 9741 assert (tinsn->ntok == 2);
b08b5071
BW		 9742 if (tinsn->tok[1].X_op == O_constant)
9743 target = tinsn->tok[1].X_add_number;
9744 else if (tinsn->tok[1].X_op == O_symbol)
9745 {
9746 /* Find the fragment. */
9747 symbolS *sym = tinsn->tok[1].X_add_symbol;
9748 assert (S_GET_SEGMENT (sym) == segP
9749 || S_GET_SEGMENT (sym) == absolute_section);
9750 target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number);
9751 }
9752 else
9753 {
9754 as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op);
9755 target = 0;
9756 }
e0001a05
NC		 9757
9758 know (symbolP);
9759 know (symbolP->sy_frag);
9760 know (!(S_GET_SEGMENT (symbolP) == absolute_section)
9761 || symbol_get_frag (symbolP) == &zero_address_frag);
9762
9763 loop_length = target - (fragP->fr_address + fragP->fr_fix);
9764 loop_length_hi = loop_length & ~0x0ff;
9765 loop_length_lo = loop_length & 0x0ff;
9766 if (loop_length_lo >= 128)
9767 {
9768 loop_length_lo -= 256;
9769 loop_length_hi += 256;
9770 }
9771
43cd72b9 9772 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
e0001a05
NC		 9773 32512. If the loop is larger than that, then we just fail. */
9774 if (loop_length_hi > 32512)
9775 as_bad_where (fragP->fr_file, fragP->fr_line,
9776 _("loop too long for LOOP instruction"));
9777
43cd72b9 9778 tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0);
e0001a05
NC		 9779 assert (addi_insn.opcode == xtensa_addi_opcode);
9780
43cd72b9 9781 tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0);
e0001a05
NC		 9782 assert (addmi_insn.opcode == xtensa_addmi_opcode);
9783
9784 set_expr_const (&addi_insn.tok[2], loop_length_lo);
9785 tinsn_to_insnbuf (&addi_insn, insnbuf);
43cd72b9 9786
e0001a05 9787 fragP->tc_frag_data.is_insn = TRUE;
43cd72b9 9788 xtensa_insnbuf_to_chars (isa, insnbuf, fragP->fr_opcode + addi_offset, 0);
e0001a05
NC		 9789
9790 set_expr_const (&addmi_insn.tok[2], loop_length_hi);
9791 tinsn_to_insnbuf (&addmi_insn, insnbuf);
43cd72b9
BW		 9792 xtensa_insnbuf_to_chars (isa, insnbuf, fragP->fr_opcode + addmi_offset, 0);
9793
9794 /* Walk through all of the frags from here to the loop end
9795 and mark them as no_transform to keep them from being modified
9796 by the linker. If we ever have a relocation for the
9797 addi/addmi of the difference of two symbols we can remove this. */
9798
9799 target_count = 0;
9800 for (next_fragP = fragP; next_fragP != NULL;
9801 next_fragP = next_fragP->fr_next)
9802 {
b08b5071 9803 next_fragP->tc_frag_data.is_no_transform = TRUE;
43cd72b9
BW		 9804 if (next_fragP->tc_frag_data.is_loop_target)
9805 target_count++;
9806 if (target_count == 2)
9807 break;
9808 }
e0001a05
NC		 9809}
9810
b08b5071
BW		 9811\f
9812/* A map that keeps information on a per-subsegment basis. This is
9813 maintained during initial assembly, but is invalid once the
9814 subsegments are smashed together. I.E., it cannot be used during
9815 the relaxation. */
e0001a05 9816
b08b5071 9817typedef struct subseg_map_struct
e0001a05 9818{
b08b5071
BW		 9819 /* the key */
9820 segT seg;
9821 subsegT subseg;
e0001a05 9822
b08b5071
BW		 9823 /* the data */
9824 unsigned flags;
9825 float total_freq; /* fall-through + branch target frequency */
9826 float target_freq; /* branch target frequency alone */
9827
9828 struct subseg_map_struct *next;
9829} subseg_map;
e0001a05 9830
e0001a05 9831
e0001a05
NC		 9832static subseg_map *sseg_map = NULL;
9833
43cd72b9 9834static subseg_map *
7fa3d080 9835get_subseg_info (segT seg, subsegT subseg)
e0001a05
NC		 9836{
9837 subseg_map *subseg_e;
9838
9839 for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
e0001a05 9840 {
43cd72b9 9841 if (seg == subseg_e->seg && subseg == subseg_e->subseg)
b08b5071 9842 break;
e0001a05 9843 }
b08b5071
BW		 9844 return subseg_e;
9845}
9846
9847
9848static subseg_map *
9849add_subseg_info (segT seg, subsegT subseg)
9850{
9851 subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map));
43cd72b9
BW		 9852 memset (subseg_e, 0, sizeof (subseg_map));
9853 subseg_e->seg = seg;
9854 subseg_e->subseg = subseg;
9855 subseg_e->flags = 0;
9856 /* Start off considering every branch target very important. */
b08b5071
BW		 9857 subseg_e->target_freq = 1.0;
9858 subseg_e->total_freq = 1.0;
43cd72b9
BW		 9859 subseg_e->next = sseg_map;
9860 sseg_map = subseg_e;
43cd72b9
BW		 9861 return subseg_e;
9862}
e0001a05 9863
7fa3d080
BW		 9864
9865static unsigned
9866get_last_insn_flags (segT seg, subsegT subseg)
9867{
9868 subseg_map *subseg_e = get_subseg_info (seg, subseg);
b08b5071
BW		 9869 if (subseg_e)
9870 return subseg_e->flags;
9871 return 0;
7fa3d080
BW		 9872}
9873
9874
43cd72b9 9875static void
7fa3d080
BW		 9876set_last_insn_flags (segT seg,
9877 subsegT subseg,
9878 unsigned fl,
9879 bfd_boolean val)
43cd72b9
BW		 9880{
9881 subseg_map *subseg_e = get_subseg_info (seg, subseg);
b08b5071
BW		 9882 if (! subseg_e)
9883 subseg_e = add_subseg_info (seg, subseg);
e0001a05
NC		 9884 if (val)
9885 subseg_e->flags |= fl;
9886 else
9887 subseg_e->flags &= ~fl;
9888}
9889
b08b5071
BW		 9890
9891static float
9892get_subseg_total_freq (segT seg, subsegT subseg)
9893{
9894 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9895 if (subseg_e)
9896 return subseg_e->total_freq;
9897 return 1.0;
9898}
9899
9900
9901static float
9902get_subseg_target_freq (segT seg, subsegT subseg)
9903{
9904 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9905 if (subseg_e)
9906 return subseg_e->target_freq;
9907 return 1.0;
9908}
9909
9910
9911static void
9912set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f)
9913{
9914 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9915 if (! subseg_e)
9916 subseg_e = add_subseg_info (seg, subseg);
9917 subseg_e->total_freq = total_f;
9918 subseg_e->target_freq = target_f;
9919}
9920
e0001a05
NC		 9921\f
9922/* Segment Lists and emit_state Stuff. */
9923
9924/* Remove the segment from the global sections list. */
9925
9926static void
7fa3d080 9927xtensa_remove_section (segT sec)
e0001a05
NC		 9928{
9929 /* Handle brain-dead bfd_section_list_remove macro, which
9930 expect the address of the prior section's "next" field, not
9931 just the address of the section to remove. */
9932
9933 segT *ps_next_ptr = &stdoutput->sections;
9934 while (*ps_next_ptr != sec && *ps_next_ptr != NULL)
9935 ps_next_ptr = &(*ps_next_ptr)->next;
9936
9937 assert (*ps_next_ptr != NULL);
9938
9939 bfd_section_list_remove (stdoutput, ps_next_ptr);
9940}
9941
9942
9943static void
7fa3d080 9944xtensa_insert_section (segT after_sec, segT sec)
e0001a05
NC		 9945{
9946 segT *after_sec_next;
9947 if (after_sec == NULL)
9948 after_sec_next = &stdoutput->sections;
9949 else
9950 after_sec_next = &after_sec->next;
9951
9952 bfd_section_list_insert (stdoutput, after_sec_next, sec);
9953}
9954
9955
9956static void
7fa3d080 9957xtensa_move_seg_list_to_beginning (seg_list *head)
e0001a05
NC		 9958{
9959 head = head->next;
9960 while (head)
9961 {
9962 segT literal_section = head->seg;
9963
9964 /* Move the literal section to the front of the section list. */
9965 assert (literal_section);
9966 xtensa_remove_section (literal_section);
9967 xtensa_insert_section (NULL, literal_section);
9968
9969 head = head->next;
9970 }
9971}
9972
9973
7fa3d080
BW		 9974static void mark_literal_frags (seg_list *);
9975
9976static void
9977xtensa_move_literals (void)
e0001a05
NC		 9978{
9979 seg_list *segment;
9980 frchainS *frchain_from, *frchain_to;
9981 fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after;
9982 fragS **frag_splice;
9983 emit_state state;
9984 segT dest_seg;
9985 fixS *fix, *next_fix, **fix_splice;
82e7541d 9986 sym_list *lit;
e0001a05 9987
a7877748
BW		 9988 mark_literal_frags (literal_head->next);
9989 mark_literal_frags (init_literal_head->next);
9990 mark_literal_frags (fini_literal_head->next);
e0001a05
NC		 9991
9992 if (use_literal_section)
9993 return;
9994
9995 segment = literal_head->next;
9996 while (segment)
9997 {
9998 frchain_from = seg_info (segment->seg)->frchainP;
9999 search_frag = frchain_from->frch_root;
10000 literal_pool = NULL;
10001 frchain_to = NULL;
10002 frag_splice = &(frchain_from->frch_root);
10003
10004 while (!search_frag->tc_frag_data.literal_frag)
10005 {
10006 assert (search_frag->fr_fix == 0
10007 || search_frag->fr_type == rs_align);
10008 search_frag = search_frag->fr_next;
10009 }
10010
10011 assert (search_frag->tc_frag_data.literal_frag->fr_subtype
10012 == RELAX_LITERAL_POOL_BEGIN);
10013 xtensa_switch_section_emit_state (&state, segment->seg, 0);
10014
10015 /* Make sure that all the frags in this series are closed, and
10016 that there is at least one left over of zero-size. This
10017 prevents us from making a segment with an frchain without any
10018 frags in it. */
10019 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 10020 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 10021 last_frag = frag_now;
10022 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 10023 xtensa_set_frag_assembly_state (frag_now);
e0001a05 10024
43cd72b9 10025 while (search_frag != frag_now)
e0001a05
NC		 10026 {
10027 next_frag = search_frag->fr_next;
10028
43cd72b9 10029 /* First, move the frag out of the literal section and
e0001a05
NC		 10030 to the appropriate place. */
10031 if (search_frag->tc_frag_data.literal_frag)
10032 {
10033 literal_pool = search_frag->tc_frag_data.literal_frag;
10034 assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN);
43cd72b9 10035 /* Note that we set this fr_var to be a fix
e0001a05
NC		 10036 chain when we created the literal pool location
10037 as RELAX_LITERAL_POOL_BEGIN. */
10038 frchain_to = (frchainS *) literal_pool->fr_var;
10039 }
10040 insert_after = literal_pool;
43cd72b9 10041
e0001a05
NC		 10042 while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END)
10043 insert_after = insert_after->fr_next;
10044
10045 dest_seg = (segT) insert_after->fr_next->fr_var;
43cd72b9 10046
e0001a05
NC		 10047 *frag_splice = next_frag;
10048 search_frag->fr_next = insert_after->fr_next;
10049 insert_after->fr_next = search_frag;
10050 search_frag->tc_frag_data.lit_seg = dest_seg;
10051
10052 /* Now move any fixups associated with this frag to the
10053 right section. */
10054 fix = frchain_from->fix_root;
10055 fix_splice = &(frchain_from->fix_root);
10056 while (fix)
10057 {
10058 next_fix = fix->fx_next;
10059 if (fix->fx_frag == search_frag)
10060 {
10061 *fix_splice = next_fix;
10062 fix->fx_next = frchain_to->fix_root;
10063 frchain_to->fix_root = fix;
10064 if (frchain_to->fix_tail == NULL)
10065 frchain_to->fix_tail = fix;
10066 }
10067 else
10068 fix_splice = &(fix->fx_next);
10069 fix = next_fix;
10070 }
10071 search_frag = next_frag;
10072 }
10073
10074 if (frchain_from->fix_root != NULL)
10075 {
10076 frchain_from = seg_info (segment->seg)->frchainP;
10077 as_warn (_("fixes not all moved from %s"), segment->seg->name);
10078
10079 assert (frchain_from->fix_root == NULL);
10080 }
10081 frchain_from->fix_tail = NULL;
10082 xtensa_restore_emit_state (&state);
10083 segment = segment->next;
10084 }
10085
82e7541d
BW		 10086 /* Now fix up the SEGMENT value for all the literal symbols. */
10087 for (lit = literal_syms; lit; lit = lit->next)
10088 {
10089 symbolS *lit_sym = lit->sym;
10090 segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg;
43cd72b9
BW		 10091 if (dest_seg)
10092 S_SET_SEGMENT (lit_sym, dest_seg);
82e7541d 10093 }
e0001a05
NC		 10094}
10095
10096
a7877748
BW		 10097/* Walk over all the frags for segments in a list and mark them as
10098 containing literals. As clunky as this is, we can't rely on frag_var
10099 and frag_variant to get called in all situations. */
10100
10101static void
7fa3d080 10102mark_literal_frags (seg_list *segment)
a7877748
BW		 10103{
10104 frchainS *frchain_from;
10105 fragS *search_frag;
10106
10107 while (segment)
10108 {
10109 frchain_from = seg_info (segment->seg)->frchainP;
10110 search_frag = frchain_from->frch_root;
10111 while (search_frag)
10112 {
10113 search_frag->tc_frag_data.is_literal = TRUE;
10114 search_frag = search_frag->fr_next;
10115 }
10116 segment = segment->next;
10117 }
10118}
10119
10120
e0001a05 10121static void
7fa3d080 10122xtensa_reorder_seg_list (seg_list *head, segT after)
e0001a05
NC		 10123{
10124 /* Move all of the sections in the section list to come
10125 after "after" in the gnu segment list. */
10126
10127 head = head->next;
10128 while (head)
10129 {
10130 segT literal_section = head->seg;
10131
10132 /* Move the literal section after "after". */
10133 assert (literal_section);
10134 if (literal_section != after)
10135 {
10136 xtensa_remove_section (literal_section);
10137 xtensa_insert_section (after, literal_section);
10138 }
10139
10140 head = head->next;
10141 }
10142}
10143
10144
10145/* Push all the literal segments to the end of the gnu list. */
10146
7fa3d080
BW		 10147static void
10148xtensa_reorder_segments (void)
e0001a05
NC		 10149{
10150 segT sec;
b08b5071 10151 segT last_sec = 0;
e0001a05
NC		 10152 int old_count = 0;
10153 int new_count = 0;
10154
10155 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
b08b5071
BW		 10156 {
10157 last_sec = sec;
10158 old_count++;
10159 }
e0001a05
NC		 10160
10161 /* Now that we have the last section, push all the literal
10162 sections to the end. */
e0001a05
NC		 10163 xtensa_reorder_seg_list (literal_head, last_sec);
10164 xtensa_reorder_seg_list (init_literal_head, last_sec);
10165 xtensa_reorder_seg_list (fini_literal_head, last_sec);
10166
10167 /* Now perform the final error check. */
10168 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
10169 new_count++;
10170 assert (new_count == old_count);
10171}
10172
10173
e0001a05
NC		 10174/* Change the emit state (seg, subseg, and frag related stuff) to the
10175 correct location. Return a emit_state which can be passed to
10176 xtensa_restore_emit_state to return to current fragment. */
10177
7fa3d080
BW		 10178static void
10179xtensa_switch_to_literal_fragment (emit_state *result)
43cd72b9
BW		 10180{
10181 if (directive_state[directive_absolute_literals])
10182 {
10183 cache_literal_section (0, default_lit_sections.lit4_seg_name,
10184 &default_lit_sections.lit4_seg, FALSE);
10185 xtensa_switch_section_emit_state (result,
10186 default_lit_sections.lit4_seg, 0);
10187 }
10188 else
10189 xtensa_switch_to_non_abs_literal_fragment (result);
10190
10191 /* Do a 4-byte align here. */
10192 frag_align (2, 0, 0);
10193 record_alignment (now_seg, 2);
10194}
10195
10196
7fa3d080
BW		 10197static void
10198xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
e0001a05
NC		 10199{
10200 /* When we mark a literal pool location, we want to put a frag in
10201 the literal pool that points to it. But to do that, we want to
10202 switch_to_literal_fragment. But literal sections don't have
10203 literal pools, so their location is always null, so we would
10204 recurse forever. This is kind of hacky, but it works. */
10205
10206 static bfd_boolean recursive = FALSE;
10207 fragS *pool_location = get_literal_pool_location (now_seg);
10208 bfd_boolean is_init =
10209 (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME));
10210
10211 bfd_boolean is_fini =
10212 (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME));
e0001a05 10213
43cd72b9
BW		 10214 if (pool_location == NULL
10215 && !use_literal_section
e0001a05
NC		 10216 && !recursive
10217 && !is_init && ! is_fini)
10218 {
43cd72b9 10219 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
e0001a05 10220 recursive = TRUE;
61846f28 10221 xtensa_mark_literal_pool_location ();
e0001a05
NC		 10222 recursive = FALSE;
10223 }
10224
10225 /* Special case: If we are in the ".fini" or ".init" section, then
10226 we will ALWAYS be generating to the ".fini.literal" and
10227 ".init.literal" sections. */
10228
10229 if (is_init)
10230 {
10231 cache_literal_section (init_literal_head,
10232 default_lit_sections.init_lit_seg_name,
43cd72b9 10233 &default_lit_sections.init_lit_seg, TRUE);
e0001a05
NC		 10234 xtensa_switch_section_emit_state (result,
10235 default_lit_sections.init_lit_seg, 0);
10236 }
10237 else if (is_fini)
10238 {
10239 cache_literal_section (fini_literal_head,
10240 default_lit_sections.fini_lit_seg_name,
43cd72b9 10241 &default_lit_sections.fini_lit_seg, TRUE);
e0001a05
NC		 10242 xtensa_switch_section_emit_state (result,
10243 default_lit_sections.fini_lit_seg, 0);
10244 }
43cd72b9 10245 else
e0001a05
NC		 10246 {
10247 cache_literal_section (literal_head,
10248 default_lit_sections.lit_seg_name,
43cd72b9 10249 &default_lit_sections.lit_seg, TRUE);
e0001a05
NC		 10250 xtensa_switch_section_emit_state (result,
10251 default_lit_sections.lit_seg, 0);
10252 }
10253
43cd72b9
BW		 10254 if (!use_literal_section
10255 && !is_init && !is_fini
10256 && get_literal_pool_location (now_seg) != pool_location)
e0001a05
NC		 10257 {
10258 /* Close whatever frag is there. */
10259 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 10260 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 10261 frag_now->tc_frag_data.literal_frag = pool_location;
10262 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 10263 xtensa_set_frag_assembly_state (frag_now);
e0001a05 10264 }
e0001a05
NC		 10265}
10266
10267
10268/* Call this function before emitting data into the literal section.
10269 This is a helper function for xtensa_switch_to_literal_fragment.
10270 This is similar to a .section new_now_seg subseg. */
10271
7fa3d080
BW		 10272static void
10273xtensa_switch_section_emit_state (emit_state *state,
10274 segT new_now_seg,
10275 subsegT new_now_subseg)
e0001a05
NC		 10276{
10277 state->name = now_seg->name;
10278 state->now_seg = now_seg;
10279 state->now_subseg = now_subseg;
10280 state->generating_literals = generating_literals;
10281 generating_literals++;
10282 subseg_new (segment_name (new_now_seg), new_now_subseg);
10283}
10284
10285
10286/* Use to restore the emitting into the normal place. */
10287
7fa3d080
BW		 10288static void
10289xtensa_restore_emit_state (emit_state *state)
e0001a05
NC		 10290{
10291 generating_literals = state->generating_literals;
10292 subseg_new (state->name, state->now_subseg);
10293}
10294
10295
10296/* Get a segment of a given name. If the segment is already
10297 present, return it; otherwise, create a new one. */
10298
10299static void
7fa3d080
BW		 10300cache_literal_section (seg_list *head,
10301 const char *name,
b08b5071 10302 segT *pseg,
7fa3d080 10303 bfd_boolean is_code)
e0001a05
NC		 10304{
10305 segT current_section = now_seg;
10306 int current_subsec = now_subseg;
b08b5071 10307 segT seg;
e0001a05 10308
b08b5071 10309 if (*pseg != 0)
e0001a05 10310 return;
e0001a05 10311
b08b5071
BW		 10312 /* Check if the named section exists. */
10313 for (seg = stdoutput->sections; seg; seg = seg->next)
10314 {
10315 if (!strcmp (segment_name (seg), name))
10316 break;
10317 }
e0001a05 10318
b08b5071 10319 if (!seg)
e0001a05 10320 {
b08b5071
BW		 10321 /* Create a new literal section. */
10322 seg = subseg_new (name, (subsegT) 0);
43cd72b9 10323 if (head)
b08b5071
BW		 10324 {
10325 /* Add the newly created literal segment to the specified list. */
10326 seg_list *n = (seg_list *) xmalloc (sizeof (seg_list));
10327 n->seg = seg;
10328 n->next = head->next;
10329 head->next = n;
10330 }
10331 bfd_set_section_flags (stdoutput, seg, SEC_HAS_CONTENTS |
43cd72b9
BW		 10332 SEC_READONLY | SEC_ALLOC | SEC_LOAD
10333 | (is_code ? SEC_CODE : SEC_DATA));
b08b5071 10334 bfd_set_section_alignment (stdoutput, seg, 2);
e0001a05
NC		 10335 }
10336
b08b5071
BW		 10337 *pseg = seg;
10338 subseg_set (current_section, current_subsec);
e0001a05
NC		 10339}
10340
43cd72b9
BW		 10341\f
10342/* Property Tables Stuff. */
10343
7fa3d080
BW		 10344#define XTENSA_INSN_SEC_NAME ".xt.insn"
10345#define XTENSA_LIT_SEC_NAME ".xt.lit"
10346#define XTENSA_PROP_SEC_NAME ".xt.prop"
10347
10348typedef bfd_boolean (*frag_predicate) (const fragS *);
10349typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
10350
b08b5071 10351static bfd_boolean get_frag_is_literal (const fragS *);
7fa3d080
BW		 10352static void xtensa_create_property_segments
10353 (frag_predicate, frag_predicate, const char *, xt_section_type);
10354static void xtensa_create_xproperty_segments
10355 (frag_flags_fn, const char *, xt_section_type);
10356static segment_info_type *retrieve_segment_info (segT);
10357static segT retrieve_xtensa_section (char *);
10358static bfd_boolean section_has_property (segT, frag_predicate);
10359static bfd_boolean section_has_xproperty (segT, frag_flags_fn);
10360static void add_xt_block_frags
10361 (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate);
10362static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *);
10363static void xtensa_frag_flags_init (frag_flags *);
10364static void get_frag_property_flags (const fragS *, frag_flags *);
10365static bfd_vma frag_flags_to_number (const frag_flags *);
10366static void add_xt_prop_frags
10367 (segT, segT, xtensa_block_info **, frag_flags_fn);
10368
10369/* Set up property tables after relaxation. */
10370
10371void
10372xtensa_post_relax_hook (void)
10373{
10374 xtensa_move_seg_list_to_beginning (literal_head);
10375 xtensa_move_seg_list_to_beginning (init_literal_head);
10376 xtensa_move_seg_list_to_beginning (fini_literal_head);
10377
10378 xtensa_find_unmarked_state_frags ();
10379
10380 if (use_literal_section)
10381 xtensa_create_property_segments (get_frag_is_literal,
10382 NULL,
10383 XTENSA_LIT_SEC_NAME,
10384 xt_literal_sec);
10385 xtensa_create_xproperty_segments (get_frag_property_flags,
10386 XTENSA_PROP_SEC_NAME,
10387 xt_prop_sec);
10388
10389 if (warn_unaligned_branch_targets)
10390 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0);
10391 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0);
10392}
10393
10394
43cd72b9
BW		 10395/* This function is only meaningful after xtensa_move_literals. */
10396
10397static bfd_boolean
7fa3d080 10398get_frag_is_literal (const fragS *fragP)
43cd72b9
BW		 10399{
10400 assert (fragP != NULL);
10401 return fragP->tc_frag_data.is_literal;
10402}
10403
10404
43cd72b9 10405static void
7fa3d080
BW		 10406xtensa_create_property_segments (frag_predicate property_function,
10407 frag_predicate end_property_function,
10408 const char *section_name_base,
10409 xt_section_type sec_type)
43cd72b9
BW		 10410{
10411 segT *seclist;
10412
10413 /* Walk over all of the current segments.
10414 Walk over each fragment
10415 For each non-empty fragment,
10416 Build a property record (append where possible). */
10417
10418 for (seclist = &stdoutput->sections;
10419 seclist && *seclist;
10420 seclist = &(*seclist)->next)
10421 {
10422 segT sec = *seclist;
10423 flagword flags;
10424
10425 flags = bfd_get_section_flags (stdoutput, sec);
10426 if (flags & SEC_DEBUGGING)
10427 continue;
10428 if (!(flags & SEC_ALLOC))
10429 continue;
10430
10431 if (section_has_property (sec, property_function))
10432 {
10433 char *property_section_name =
10434 xtensa_get_property_section_name (sec, section_name_base);
10435 segT insn_sec = retrieve_xtensa_section (property_section_name);
10436 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
10437 xtensa_block_info **xt_blocks =
10438 &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10439 /* Walk over all of the frchains here and add new sections. */
10440 add_xt_block_frags (sec, insn_sec, xt_blocks, property_function,
10441 end_property_function);
10442 }
10443 }
10444
10445 /* Now we fill them out.... */
10446
10447 for (seclist = &stdoutput->sections;
10448 seclist && *seclist;
10449 seclist = &(*seclist)->next)
10450 {
10451 segment_info_type *seginfo;
10452 xtensa_block_info *block;
10453 segT sec = *seclist;
10454
10455 seginfo = seg_info (sec);
10456 block = seginfo->tc_segment_info_data.blocks[sec_type];
10457
10458 if (block)
10459 {
10460 xtensa_block_info *cur_block;
10461 /* This is a section with some data. */
10462 int num_recs = 0;
10463 size_t rec_size;
10464
10465 for (cur_block = block; cur_block; cur_block = cur_block->next)
10466 num_recs++;
10467
10468 rec_size = num_recs * 8;
10469 bfd_set_section_size (stdoutput, sec, rec_size);
10470
10471 /* In order to make this work with the assembler, we have to
10472 build some frags and then build the "fixups" for it. It
10473 would be easier to just set the contents then set the
10474 arlents. */
10475
10476 if (num_recs)
10477 {
10478 /* Allocate a fragment and leak it. */
10479 fragS *fragP;
10480 size_t frag_size;
10481 fixS *fixes;
10482 frchainS *frchainP;
10483 int i;
10484 char *frag_data;
10485
10486 frag_size = sizeof (fragS) + rec_size;
10487 fragP = (fragS *) xmalloc (frag_size);
e0001a05 10488
43cd72b9
BW		 10489 memset (fragP, 0, frag_size);
10490 fragP->fr_address = 0;
10491 fragP->fr_next = NULL;
10492 fragP->fr_fix = rec_size;
10493 fragP->fr_var = 0;
10494 fragP->fr_type = rs_fill;
10495 /* The rest are zeros. */
e0001a05 10496
43cd72b9
BW		 10497 frchainP = seginfo->frchainP;
10498 frchainP->frch_root = fragP;
10499 frchainP->frch_last = fragP;
e0001a05 10500
43cd72b9
BW		 10501 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
10502 memset (fixes, 0, sizeof (fixS) * num_recs);
e0001a05 10503
43cd72b9
BW		 10504 seginfo->fix_root = fixes;
10505 seginfo->fix_tail = &fixes[num_recs - 1];
10506 cur_block = block;
10507 frag_data = &fragP->fr_literal[0];
10508 for (i = 0; i < num_recs; i++)
10509 {
10510 fixS *fix = &fixes[i];
10511 assert (cur_block);
e0001a05 10512
43cd72b9
BW		 10513 /* Write the fixup. */
10514 if (i != num_recs - 1)
10515 fix->fx_next = &fixes[i + 1];
10516 else
10517 fix->fx_next = NULL;
10518 fix->fx_size = 4;
10519 fix->fx_done = 0;
10520 fix->fx_frag = fragP;
10521 fix->fx_where = i * 8;
10522 fix->fx_addsy = section_symbol (cur_block->sec);
10523 fix->fx_offset = cur_block->offset;
10524 fix->fx_r_type = BFD_RELOC_32;
10525 fix->fx_file = "Internal Assembly";
10526 fix->fx_line = 0;
e0001a05 10527
43cd72b9
BW		 10528 /* Write the length. */
10529 md_number_to_chars (&frag_data[4 + 8 * i],
10530 cur_block->size, 4);
10531 cur_block = cur_block->next;
10532 }
10533 }
10534 }
10535 }
e0001a05
NC		 10536}
10537
10538
7fa3d080
BW		 10539static void
10540xtensa_create_xproperty_segments (frag_flags_fn flag_fn,
10541 const char *section_name_base,
10542 xt_section_type sec_type)
e0001a05
NC		 10543{
10544 segT *seclist;
10545
10546 /* Walk over all of the current segments.
43cd72b9
BW		 10547 Walk over each fragment.
10548 For each fragment that has instructions,
10549 build an instruction record (append where possible). */
e0001a05
NC		 10550
10551 for (seclist = &stdoutput->sections;
10552 seclist && *seclist;
10553 seclist = &(*seclist)->next)
10554 {
10555 segT sec = *seclist;
43cd72b9
BW		 10556 flagword flags;
10557
10558 flags = bfd_get_section_flags (stdoutput, sec);
10559 if (flags & SEC_DEBUGGING)
10560 continue;
10561 if (!(flags & SEC_ALLOC))
10562 continue;
10563
10564 if (section_has_xproperty (sec, flag_fn))
e0001a05 10565 {
b614a702
BW		 10566 char *property_section_name =
10567 xtensa_get_property_section_name (sec, section_name_base);
e0001a05
NC		 10568 segT insn_sec = retrieve_xtensa_section (property_section_name);
10569 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
43cd72b9 10570 xtensa_block_info **xt_blocks =
e0001a05
NC		 10571 &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10572 /* Walk over all of the frchains here and add new sections. */
43cd72b9 10573 add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn);
e0001a05
NC		 10574 }
10575 }
10576
10577 /* Now we fill them out.... */
10578
10579 for (seclist = &stdoutput->sections;
10580 seclist && *seclist;
10581 seclist = &(*seclist)->next)
10582 {
10583 segment_info_type *seginfo;
10584 xtensa_block_info *block;
10585 segT sec = *seclist;
43cd72b9 10586
e0001a05
NC		 10587 seginfo = seg_info (sec);
10588 block = seginfo->tc_segment_info_data.blocks[sec_type];
10589
10590 if (block)
10591 {
10592 xtensa_block_info *cur_block;
10593 /* This is a section with some data. */
43cd72b9 10594 int num_recs = 0;
e0001a05
NC		 10595 size_t rec_size;
10596
10597 for (cur_block = block; cur_block; cur_block = cur_block->next)
10598 num_recs++;
10599
43cd72b9 10600 rec_size = num_recs * (8 + 4);
e0001a05
NC		 10601 bfd_set_section_size (stdoutput, sec, rec_size);
10602
43cd72b9
BW		 10603 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10604
10605 /* In order to make this work with the assembler, we have to build
10606 some frags then build the "fixups" for it. It would be easier to
10607 just set the contents then set the arlents. */
e0001a05
NC		 10608
10609 if (num_recs)
10610 {
43cd72b9 10611 /* Allocate a fragment and (unfortunately) leak it. */
e0001a05
NC		 10612 fragS *fragP;
10613 size_t frag_size;
10614 fixS *fixes;
10615 frchainS *frchainP;
43cd72b9 10616 int i;
e0001a05
NC		 10617 char *frag_data;
10618
10619 frag_size = sizeof (fragS) + rec_size;
10620 fragP = (fragS *) xmalloc (frag_size);
10621
10622 memset (fragP, 0, frag_size);
10623 fragP->fr_address = 0;
10624 fragP->fr_next = NULL;
10625 fragP->fr_fix = rec_size;
10626 fragP->fr_var = 0;
10627 fragP->fr_type = rs_fill;
43cd72b9 10628 /* The rest are zeros. */
e0001a05
NC		 10629
10630 frchainP = seginfo->frchainP;
10631 frchainP->frch_root = fragP;
10632 frchainP->frch_last = fragP;
10633
10634 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
10635 memset (fixes, 0, sizeof (fixS) * num_recs);
10636
10637 seginfo->fix_root = fixes;
10638 seginfo->fix_tail = &fixes[num_recs - 1];
10639 cur_block = block;
10640 frag_data = &fragP->fr_literal[0];
10641 for (i = 0; i < num_recs; i++)
10642 {
10643 fixS *fix = &fixes[i];
10644 assert (cur_block);
10645
10646 /* Write the fixup. */
10647 if (i != num_recs - 1)
10648 fix->fx_next = &fixes[i + 1];
10649 else
10650 fix->fx_next = NULL;
10651 fix->fx_size = 4;
10652 fix->fx_done = 0;
10653 fix->fx_frag = fragP;
43cd72b9 10654 fix->fx_where = i * (8 + 4);
e0001a05
NC		 10655 fix->fx_addsy = section_symbol (cur_block->sec);
10656 fix->fx_offset = cur_block->offset;
10657 fix->fx_r_type = BFD_RELOC_32;
10658 fix->fx_file = "Internal Assembly";
10659 fix->fx_line = 0;
10660
10661 /* Write the length. */
43cd72b9 10662 md_number_to_chars (&frag_data[4 + (8+4) * i],
e0001a05 10663 cur_block->size, 4);
43cd72b9
BW		 10664 md_number_to_chars (&frag_data[8 + (8+4) * i],
10665 frag_flags_to_number (&cur_block->flags),
10666 4);
e0001a05
NC		 10667 cur_block = cur_block->next;
10668 }
10669 }
10670 }
10671 }
10672}
10673
10674
7fa3d080
BW		 10675static segment_info_type *
10676retrieve_segment_info (segT seg)
e0001a05
NC		 10677{
10678 segment_info_type *seginfo;
10679 seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg);
10680 if (!seginfo)
10681 {
10682 frchainS *frchainP;
10683
10684 seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
7fa3d080 10685 memset ((void *) seginfo, 0, sizeof (*seginfo));
e0001a05
NC		 10686 seginfo->fix_root = NULL;
10687 seginfo->fix_tail = NULL;
10688 seginfo->bfd_section = seg;
10689 seginfo->sym = 0;
10690 /* We will not be dealing with these, only our special ones. */
10691#if 0
10692 if (seg == bfd_abs_section_ptr)
10693 abs_seg_info = seginfo;
10694 else if (seg == bfd_und_section_ptr)
10695 und_seg_info = seginfo;
10696 else
10697#endif
7fa3d080 10698 bfd_set_section_userdata (stdoutput, seg, (void *) seginfo);
e0001a05
NC		 10699#if 0
10700 seg_fix_rootP = &segment_info[seg].fix_root;
10701 seg_fix_tailP = &segment_info[seg].fix_tail;
10702#endif
10703
10704 frchainP = (frchainS *) xmalloc (sizeof (frchainS));
10705 frchainP->frch_root = NULL;
10706 frchainP->frch_last = NULL;
10707 frchainP->frch_next = NULL;
10708 frchainP->frch_seg = seg;
10709 frchainP->frch_subseg = 0;
10710 frchainP->fix_root = NULL;
10711 frchainP->fix_tail = NULL;
10712 /* Do not init the objstack. */
10713 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10714 /* frchainP->frch_frag_now = fragP; */
10715 frchainP->frch_frag_now = NULL;
10716
10717 seginfo->frchainP = frchainP;
10718 }
10719
10720 return seginfo;
10721}
10722
10723
7fa3d080
BW		 10724static segT
10725retrieve_xtensa_section (char *sec_name)
e0001a05
NC		 10726{
10727 bfd *abfd = stdoutput;
10728 flagword flags, out_flags, link_once_flags;
10729 segT s;
10730
10731 flags = bfd_get_section_flags (abfd, now_seg);
10732 link_once_flags = (flags & SEC_LINK_ONCE);
10733 if (link_once_flags)
10734 link_once_flags |= (flags & SEC_LINK_DUPLICATES);
10735 out_flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY | link_once_flags);
10736
10737 s = bfd_make_section_old_way (abfd, sec_name);
10738 if (s == NULL)
10739 as_bad (_("could not create section %s"), sec_name);
10740 if (!bfd_set_section_flags (abfd, s, out_flags))
10741 as_bad (_("invalid flag combination on section %s"), sec_name);
10742
10743 return s;
10744}
10745
10746
7fa3d080
BW		 10747static bfd_boolean
10748section_has_property (segT sec, frag_predicate property_function)
e0001a05
NC		 10749{
10750 segment_info_type *seginfo = seg_info (sec);
10751 fragS *fragP;
10752
10753 if (seginfo && seginfo->frchainP)
10754 {
10755 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10756 {
10757 if (property_function (fragP)
10758 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10759 return TRUE;
10760 }
10761 }
10762 return FALSE;
10763}
10764
10765
7fa3d080
BW		 10766static bfd_boolean
10767section_has_xproperty (segT sec, frag_flags_fn property_function)
43cd72b9
BW		 10768{
10769 segment_info_type *seginfo = seg_info (sec);
10770 fragS *fragP;
10771
10772 if (seginfo && seginfo->frchainP)
10773 {
10774 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10775 {
10776 frag_flags prop_flags;
10777 property_function (fragP, &prop_flags);
10778 if (!xtensa_frag_flags_is_empty (&prop_flags))
10779 return TRUE;
10780 }
10781 }
10782 return FALSE;
10783}
10784
10785
e0001a05
NC		 10786/* Two types of block sections exist right now: literal and insns. */
10787
7fa3d080
BW		 10788static void
10789add_xt_block_frags (segT sec,
10790 segT xt_block_sec,
10791 xtensa_block_info **xt_block,
10792 frag_predicate property_function,
10793 frag_predicate end_property_function)
e0001a05
NC		 10794{
10795 segment_info_type *seg_info;
10796 segment_info_type *xt_seg_info;
10797 bfd_vma seg_offset;
10798 fragS *fragP;
10799
10800 xt_seg_info = retrieve_segment_info (xt_block_sec);
10801 seg_info = retrieve_segment_info (sec);
10802
10803 /* Build it if needed. */
10804 while (*xt_block != NULL)
10805 xt_block = &(*xt_block)->next;
10806 /* We are either at NULL at the beginning or at the end. */
10807
10808 /* Walk through the frags. */
10809 seg_offset = 0;
10810
10811 if (seg_info->frchainP)
10812 {
10813 for (fragP = seg_info->frchainP->frch_root;
10814 fragP;
10815 fragP = fragP->fr_next)
10816 {
10817 if (property_function (fragP)
10818 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10819 {
10820 if (*xt_block != NULL)
10821 {
10822 if ((*xt_block)->offset + (*xt_block)->size
10823 == fragP->fr_address)
10824 (*xt_block)->size += fragP->fr_fix;
10825 else
10826 xt_block = &((*xt_block)->next);
10827 }
10828 if (*xt_block == NULL)
10829 {
43cd72b9
BW		 10830 xtensa_block_info *new_block = (xtensa_block_info *)
10831 xmalloc (sizeof (xtensa_block_info));
10832 new_block->sec = sec;
10833 new_block->offset = fragP->fr_address;
10834 new_block->size = fragP->fr_fix;
10835 new_block->next = NULL;
10836 xtensa_frag_flags_init (&new_block->flags);
10837 *xt_block = new_block;
10838 }
10839 if (end_property_function
10840 && end_property_function (fragP))
10841 {
10842 xt_block = &((*xt_block)->next);
10843 }
10844 }
10845 }
10846 }
10847}
10848
10849
10850/* Break the encapsulation of add_xt_prop_frags here. */
10851
7fa3d080
BW		 10852static bfd_boolean
10853xtensa_frag_flags_is_empty (const frag_flags *prop_flags)
43cd72b9
BW		 10854{
10855 if (prop_flags->is_literal
10856 || prop_flags->is_insn
10857 || prop_flags->is_data
10858 || prop_flags->is_unreachable)
10859 return FALSE;
10860 return TRUE;
10861}
10862
10863
7fa3d080
BW		 10864static void
10865xtensa_frag_flags_init (frag_flags *prop_flags)
43cd72b9
BW		 10866{
10867 memset (prop_flags, 0, sizeof (frag_flags));
10868}
10869
10870
7fa3d080
BW		 10871static void
10872get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
43cd72b9
BW		 10873{
10874 xtensa_frag_flags_init (prop_flags);
10875 if (fragP->tc_frag_data.is_literal)
10876 prop_flags->is_literal = TRUE;
10877 if (fragP->tc_frag_data.is_unreachable)
7fa3d080 10878 prop_flags->is_unreachable = TRUE;
43cd72b9
BW		 10879 else if (fragP->tc_frag_data.is_insn)
10880 {
10881 prop_flags->is_insn = TRUE;
10882 if (fragP->tc_frag_data.is_loop_target)
10883 prop_flags->insn.is_loop_target = TRUE;
10884 if (fragP->tc_frag_data.is_branch_target)
10885 prop_flags->insn.is_branch_target = TRUE;
10886 if (fragP->tc_frag_data.is_specific_opcode
10887 || fragP->tc_frag_data.is_no_transform)
10888 prop_flags->insn.is_no_transform = TRUE;
10889 if (fragP->tc_frag_data.is_no_density)
10890 prop_flags->insn.is_no_density = TRUE;
10891 if (fragP->tc_frag_data.use_absolute_literals)
10892 prop_flags->insn.is_abslit = TRUE;
10893 }
10894 if (fragP->tc_frag_data.is_align)
10895 {
10896 prop_flags->is_align = TRUE;
10897 prop_flags->alignment = fragP->tc_frag_data.alignment;
10898 if (xtensa_frag_flags_is_empty (prop_flags))
10899 prop_flags->is_data = TRUE;
10900 }
10901}
10902
10903
7fa3d080
BW		 10904static bfd_vma
10905frag_flags_to_number (const frag_flags *prop_flags)
43cd72b9
BW		 10906{
10907 bfd_vma num = 0;
10908 if (prop_flags->is_literal)
10909 num |= XTENSA_PROP_LITERAL;
10910 if (prop_flags->is_insn)
10911 num |= XTENSA_PROP_INSN;
10912 if (prop_flags->is_data)
10913 num |= XTENSA_PROP_DATA;
10914 if (prop_flags->is_unreachable)
10915 num |= XTENSA_PROP_UNREACHABLE;
10916 if (prop_flags->insn.is_loop_target)
10917 num |= XTENSA_PROP_INSN_LOOP_TARGET;
10918 if (prop_flags->insn.is_branch_target)
10919 {
10920 num |= XTENSA_PROP_INSN_BRANCH_TARGET;
10921 num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority);
10922 }
10923
10924 if (prop_flags->insn.is_no_density)
10925 num |= XTENSA_PROP_INSN_NO_DENSITY;
10926 if (prop_flags->insn.is_no_transform)
10927 num |= XTENSA_PROP_INSN_NO_TRANSFORM;
10928 if (prop_flags->insn.is_no_reorder)
10929 num |= XTENSA_PROP_INSN_NO_REORDER;
10930 if (prop_flags->insn.is_abslit)
10931 num |= XTENSA_PROP_INSN_ABSLIT;
10932
10933 if (prop_flags->is_align)
10934 {
10935 num |= XTENSA_PROP_ALIGN;
10936 num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment);
10937 }
10938
10939 return num;
10940}
10941
10942
10943static bfd_boolean
7fa3d080
BW		 10944xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
10945 const frag_flags *prop_flags_2)
43cd72b9
BW		 10946{
10947 /* Cannot combine with an end marker. */
10948
10949 if (prop_flags_1->is_literal != prop_flags_2->is_literal)
10950 return FALSE;
10951 if (prop_flags_1->is_insn != prop_flags_2->is_insn)
10952 return FALSE;
10953 if (prop_flags_1->is_data != prop_flags_2->is_data)
10954 return FALSE;
10955
10956 if (prop_flags_1->is_insn)
10957 {
10958 /* Properties of the beginning of the frag. */
10959 if (prop_flags_2->insn.is_loop_target)
10960 return FALSE;
10961 if (prop_flags_2->insn.is_branch_target)
10962 return FALSE;
10963 if (prop_flags_1->insn.is_no_density !=
10964 prop_flags_2->insn.is_no_density)
10965 return FALSE;
10966 if (prop_flags_1->insn.is_no_transform !=
10967 prop_flags_2->insn.is_no_transform)
10968 return FALSE;
10969 if (prop_flags_1->insn.is_no_reorder !=
10970 prop_flags_2->insn.is_no_reorder)
10971 return FALSE;
10972 if (prop_flags_1->insn.is_abslit !=
10973 prop_flags_2->insn.is_abslit)
10974 return FALSE;
10975 }
10976
10977 if (prop_flags_1->is_align)
10978 return FALSE;
10979
10980 return TRUE;
10981}
10982
10983
7fa3d080
BW		 10984static bfd_vma
10985xt_block_aligned_size (const xtensa_block_info *xt_block)
43cd72b9
BW		 10986{
10987 bfd_vma end_addr;
10988 size_t align_bits;
10989
10990 if (!xt_block->flags.is_align)
10991 return xt_block->size;
10992
10993 end_addr = xt_block->offset + xt_block->size;
10994 align_bits = xt_block->flags.alignment;
10995 end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits;
10996 return end_addr - xt_block->offset;
10997}
10998
10999
11000static bfd_boolean
7fa3d080
BW		 11001xtensa_xt_block_combine (xtensa_block_info *xt_block,
11002 const xtensa_block_info *xt_block_2)
43cd72b9
BW		 11003{
11004 if (xt_block->sec != xt_block_2->sec)
11005 return FALSE;
11006 if (xt_block->offset + xt_block_aligned_size (xt_block)
11007 != xt_block_2->offset)
11008 return FALSE;
11009
11010 if (xt_block_2->size == 0
11011 && (!xt_block_2->flags.is_unreachable
11012 || xt_block->flags.is_unreachable))
11013 {
11014 if (xt_block_2->flags.is_align
11015 && xt_block->flags.is_align)
11016 {
11017 /* Nothing needed. */
11018 if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
11019 return TRUE;
11020 }
11021 else
11022 {
11023 if (xt_block_2->flags.is_align)
11024 {
11025 /* Push alignment to previous entry. */
11026 xt_block->flags.is_align = xt_block_2->flags.is_align;
11027 xt_block->flags.alignment = xt_block_2->flags.alignment;
11028 }
11029 return TRUE;
11030 }
11031 }
11032 if (!xtensa_frag_flags_combinable (&xt_block->flags,
11033 &xt_block_2->flags))
11034 return FALSE;
11035
11036 xt_block->size += xt_block_2->size;
11037
11038 if (xt_block_2->flags.is_align)
11039 {
11040 xt_block->flags.is_align = TRUE;
11041 xt_block->flags.alignment = xt_block_2->flags.alignment;
11042 }
11043
11044 return TRUE;
11045}
11046
11047
7fa3d080
BW		 11048static void
11049add_xt_prop_frags (segT sec,
11050 segT xt_block_sec,
11051 xtensa_block_info **xt_block,
11052 frag_flags_fn property_function)
43cd72b9
BW		 11053{
11054 segment_info_type *seg_info;
11055 segment_info_type *xt_seg_info;
11056 bfd_vma seg_offset;
11057 fragS *fragP;
11058
11059 xt_seg_info = retrieve_segment_info (xt_block_sec);
11060 seg_info = retrieve_segment_info (sec);
11061 /* Build it if needed. */
11062 while (*xt_block != NULL)
11063 {
11064 xt_block = &(*xt_block)->next;
11065 }
11066 /* We are either at NULL at the beginning or at the end. */
11067
11068 /* Walk through the frags. */
11069 seg_offset = 0;
11070
11071 if (seg_info->frchainP)
11072 {
11073 for (fragP = seg_info->frchainP->frch_root; fragP;
11074 fragP = fragP->fr_next)
11075 {
11076 xtensa_block_info tmp_block;
11077 tmp_block.sec = sec;
11078 tmp_block.offset = fragP->fr_address;
11079 tmp_block.size = fragP->fr_fix;
11080 tmp_block.next = NULL;
11081 property_function (fragP, &tmp_block.flags);
11082
11083 if (!xtensa_frag_flags_is_empty (&tmp_block.flags))
11084 /* && fragP->fr_fix != 0) */
11085 {
11086 if ((*xt_block) == NULL
11087 || !xtensa_xt_block_combine (*xt_block, &tmp_block))
11088 {
11089 xtensa_block_info *new_block;
11090 if ((*xt_block) != NULL)
11091 xt_block = &(*xt_block)->next;
11092 new_block = (xtensa_block_info *)
11093 xmalloc (sizeof (xtensa_block_info));
11094 *new_block = tmp_block;
11095 *xt_block = new_block;
11096 }
11097 }
11098 }
11099 }
11100}
11101
11102\f
11103/* op_placement_info_table */
11104
11105/* op_placement_info makes it easier to determine which
11106 ops can go in which slots. */
11107
11108static void
7fa3d080 11109init_op_placement_info_table (void)
43cd72b9
BW		 11110{
11111 xtensa_isa isa = xtensa_default_isa;
11112 xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa);
11113 xtensa_opcode opcode;
11114 xtensa_format fmt;
11115 int slot;
11116 int num_opcodes = xtensa_isa_num_opcodes (isa);
11117
11118 op_placement_table = (op_placement_info_table)
11119 xmalloc (sizeof (op_placement_info) * num_opcodes);
11120 assert (xtensa_isa_num_formats (isa) < MAX_FORMATS);
11121
11122 for (opcode = 0; opcode < num_opcodes; opcode++)
11123 {
11124 op_placement_info *opi = &op_placement_table[opcode];
11125 /* FIXME: Make tinsn allocation dynamic. */
11126 if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS)
11127 as_fatal (_("too many operands in instruction"));
11128 opi->single = XTENSA_UNDEFINED;
11129 opi->single_size = 0;
11130 opi->widest = XTENSA_UNDEFINED;
11131 opi->widest_size = 0;
11132 opi->narrowest = XTENSA_UNDEFINED;
11133 opi->narrowest_size = 0x7F;
11134 opi->formats = 0;
11135 opi->num_formats = 0;
11136 opi->issuef = 0;
11137 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
11138 {
11139 opi->slots[fmt] = 0;
11140 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
11141 {
11142 if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0)
11143 {
11144 int fmt_length = xtensa_format_length (isa, fmt);
11145 opi->issuef++;
11146 set_bit (fmt, opi->formats);
11147 set_bit (slot, opi->slots[fmt]);
11148 /* opi->slot_count[fmt]++; */
11149 if (fmt_length < opi->narrowest_size)
11150 {
11151 opi->narrowest = fmt;
11152 opi->narrowest_size = fmt_length;
11153 }
11154 if (fmt_length > opi->widest_size)
11155 {
11156 opi->widest = fmt;
11157 opi->widest_size = fmt_length;
11158 }
11159 if (xtensa_format_num_slots (isa, fmt) == 1)
11160 {
11161 if (opi->single_size == 0
11162 || fmt_length < opi->single_size)
11163 {
11164 opi->single = fmt;
11165 opi->single_size = fmt_length;
11166 }
11167 }
e0001a05
NC		 11168 }
11169 }
43cd72b9
BW		 11170 if (opi->formats)
11171 opi->num_formats++;
e0001a05
NC		 11172 }
11173 }
43cd72b9
BW		 11174 xtensa_insnbuf_free (isa, ibuf);
11175}
11176
11177
11178bfd_boolean
7fa3d080 11179opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot)
43cd72b9
BW		 11180{
11181 return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
11182}
11183
11184
11185/* If the opcode is available in a single slot format, return its size. */
11186
7fa3d080
BW		 11187static int
11188xg_get_single_size (xtensa_opcode opcode)
43cd72b9
BW		 11189{
11190 assert (op_placement_table[opcode].single != XTENSA_UNDEFINED);
11191 return op_placement_table[opcode].single_size;
11192}
11193
11194
7fa3d080
BW		 11195static xtensa_format
11196xg_get_single_format (xtensa_opcode opcode)
43cd72b9
BW		 11197{
11198 return op_placement_table[opcode].single;
e0001a05
NC		 11199}
11200
11201\f
11202/* Instruction Stack Functions (from "xtensa-istack.h"). */
11203
11204void
7fa3d080 11205istack_init (IStack *stack)
e0001a05
NC		 11206{
11207 memset (stack, 0, sizeof (IStack));
11208 stack->ninsn = 0;
11209}
11210
11211
11212bfd_boolean
7fa3d080 11213istack_empty (IStack *stack)
e0001a05
NC		 11214{
11215 return (stack->ninsn == 0);
11216}
11217
11218
11219bfd_boolean
7fa3d080 11220istack_full (IStack *stack)
e0001a05
NC		 11221{
11222 return (stack->ninsn == MAX_ISTACK);
11223}
11224
11225
11226/* Return a pointer to the top IStack entry.
43cd72b9 11227 It is an error to call this if istack_empty () is TRUE. */
e0001a05
NC		 11228
11229TInsn *
7fa3d080 11230istack_top (IStack *stack)
e0001a05
NC		 11231{
11232 int rec = stack->ninsn - 1;
11233 assert (!istack_empty (stack));
11234 return &stack->insn[rec];
11235}
11236
11237
11238/* Add a new TInsn to an IStack.
43cd72b9 11239 It is an error to call this if istack_full () is TRUE. */
e0001a05
NC		 11240
11241void
7fa3d080 11242istack_push (IStack *stack, TInsn *insn)
e0001a05
NC		 11243{
11244 int rec = stack->ninsn;
11245 assert (!istack_full (stack));
43cd72b9 11246 stack->insn[rec] = *insn;
e0001a05
NC		 11247 stack->ninsn++;
11248}
11249
11250
11251/* Clear space for the next TInsn on the IStack and return a pointer
43cd72b9 11252 to it. It is an error to call this if istack_full () is TRUE. */
e0001a05
NC		 11253
11254TInsn *
7fa3d080 11255istack_push_space (IStack *stack)
e0001a05
NC		 11256{
11257 int rec = stack->ninsn;
11258 TInsn *insn;
11259 assert (!istack_full (stack));
11260 insn = &stack->insn[rec];
11261 memset (insn, 0, sizeof (TInsn));
11262 stack->ninsn++;
11263 return insn;
11264}
11265
11266
11267/* Remove the last pushed instruction. It is an error to call this if
43cd72b9 11268 istack_empty () returns TRUE. */
e0001a05
NC		 11269
11270void
7fa3d080 11271istack_pop (IStack *stack)
e0001a05
NC		 11272{
11273 int rec = stack->ninsn - 1;
11274 assert (!istack_empty (stack));
11275 stack->ninsn--;
11276 memset (&stack->insn[rec], 0, sizeof (TInsn));
11277}
11278
11279\f
11280/* TInsn functions. */
11281
11282void
7fa3d080 11283tinsn_init (TInsn *dst)
e0001a05
NC		 11284{
11285 memset (dst, 0, sizeof (TInsn));
11286}
11287
11288
e0001a05
NC		 11289/* Get the ``num''th token of the TInsn.
11290 It is illegal to call this if num > insn->ntoks. */
11291
11292expressionS *
7fa3d080 11293tinsn_get_tok (TInsn *insn, int num)
e0001a05
NC		 11294{
11295 assert (num < insn->ntok);
11296 return &insn->tok[num];
11297}
11298
11299
43cd72b9 11300/* Return TRUE if ANY of the operands in the insn are symbolic. */
e0001a05
NC		 11301
11302static bfd_boolean
7fa3d080 11303tinsn_has_symbolic_operands (const TInsn *insn)
e0001a05
NC		 11304{
11305 int i;
11306 int n = insn->ntok;
11307
11308 assert (insn->insn_type == ITYPE_INSN);
11309
11310 for (i = 0; i < n; ++i)
11311 {
11312 switch (insn->tok[i].X_op)
11313 {
11314 case O_register:
11315 case O_constant:
11316 break;
11317 default:
11318 return TRUE;
11319 }
11320 }
11321 return FALSE;
11322}
11323
11324
11325bfd_boolean
7fa3d080 11326tinsn_has_invalid_symbolic_operands (const TInsn *insn)
e0001a05 11327{
43cd72b9 11328 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 11329 int i;
11330 int n = insn->ntok;
11331
11332 assert (insn->insn_type == ITYPE_INSN);
11333
11334 for (i = 0; i < n; ++i)
11335 {
11336 switch (insn->tok[i].X_op)
11337 {
11338 case O_register:
11339 case O_constant:
11340 break;
43cd72b9
BW		 11341 case O_big:
11342 case O_illegal:
11343 case O_absent:
11344 /* Errors for these types are caught later. */
11345 break;
11346 case O_hi16:
11347 case O_lo16:
e0001a05 11348 default:
43cd72b9
BW		 11349 /* Symbolic immediates are only allowed on the last immediate
11350 operand. At this time, CONST16 is the only opcode where we
11351 support non-PC-relative relocations. (It isn't necessary
11352 to complain about non-PC-relative relocations here, but
11353 otherwise, no error is reported until the relocations are
11354 generated, and the assembler won't get that far if there
11355 are any other errors. It's nice to see all the problems
11356 at once.) */
11357 if (i != get_relaxable_immed (insn->opcode)
11358 || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1
11359 && insn->opcode != xtensa_const16_opcode))
11360 {
11361 as_bad (_("invalid symbolic operand %d on '%s'"),
11362 i, xtensa_opcode_name (isa, insn->opcode));
11363 return TRUE;
11364 }
e0001a05
NC		 11365 }
11366 }
11367 return FALSE;
11368}
11369
11370
11371/* For assembly code with complex expressions (e.g. subtraction),
11372 we have to build them in the literal pool so that
11373 their results are calculated correctly after relaxation.
11374 The relaxation only handles expressions that
11375 boil down to SYMBOL + OFFSET. */
11376
11377static bfd_boolean
7fa3d080 11378tinsn_has_complex_operands (const TInsn *insn)
e0001a05
NC		 11379{
11380 int i;
11381 int n = insn->ntok;
11382 assert (insn->insn_type == ITYPE_INSN);
11383 for (i = 0; i < n; ++i)
11384 {
11385 switch (insn->tok[i].X_op)
11386 {
11387 case O_register:
11388 case O_constant:
11389 case O_symbol:
43cd72b9
BW		 11390 case O_lo16:
11391 case O_hi16:
e0001a05
NC		 11392 break;
11393 default:
11394 return TRUE;
11395 }
11396 }
11397 return FALSE;
11398}
11399
11400
43cd72b9
BW		 11401/* Convert the constant operands in the tinsn to insnbuf.
11402 Return TRUE if there is a symbol in the immediate field.
e0001a05 11403
43cd72b9 11404 Before this is called,
e0001a05 11405 1) the number of operands are correct
43cd72b9 11406 2) the tinsn is a ITYPE_INSN
e0001a05
NC		 11407 3) ONLY the relaxable_ is built
11408 4) All operands are O_constant, O_symbol. All constants fit
11409 The return value tells whether there are any remaining O_symbols. */
11410
11411static bfd_boolean
7fa3d080 11412tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf)
e0001a05 11413{
43cd72b9 11414 static xtensa_insnbuf slotbuf = 0;
e0001a05 11415 xtensa_isa isa = xtensa_default_isa;
43cd72b9
BW		 11416 xtensa_opcode opcode = tinsn->opcode;
11417 xtensa_format fmt = xg_get_single_format (opcode);
e0001a05 11418 bfd_boolean has_fixup = FALSE;
43cd72b9 11419 int noperands = xtensa_opcode_num_operands (isa, opcode);
e0001a05
NC		 11420 int i;
11421 uint32 opnd_value;
11422 char *file_name;
11423 int line;
11424
43cd72b9
BW		 11425 if (!slotbuf)
11426 slotbuf = xtensa_insnbuf_alloc (isa);
11427
11428 assert (tinsn->insn_type == ITYPE_INSN);
11429 if (noperands != tinsn->ntok)
e0001a05
NC		 11430 as_fatal (_("operand number mismatch"));
11431
43cd72b9
BW		 11432 if (xtensa_opcode_encode (isa, fmt, 0, slotbuf, opcode))
11433 as_fatal (_("cannot encode opcode"));
e0001a05
NC		 11434
11435 for (i = 0; i < noperands; ++i)
11436 {
43cd72b9 11437 expressionS *expr = &tinsn->tok[i];
e0001a05
NC		 11438 switch (expr->X_op)
11439 {
11440 case O_register:
43cd72b9
BW		 11441 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11442 break;
11443 /* The register number has already been checked in
e0001a05
NC		 11444 expression_maybe_register, so we don't need to check here. */
11445 opnd_value = expr->X_add_number;
43cd72b9
BW		 11446 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
11447 xtensa_operand_set_field (isa, opcode, i, fmt, 0,
11448 slotbuf, opnd_value);
e0001a05
NC		 11449 break;
11450
11451 case O_constant:
43cd72b9
BW		 11452 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11453 break;
e0001a05
NC		 11454 as_where (&file_name, &line);
11455 /* It is a constant and we called this function,
11456 then we have to try to fit it. */
43cd72b9
BW		 11457 xtensa_insnbuf_set_operand (slotbuf, fmt, 0, opcode, i,
11458 expr->X_add_number, file_name, line);
11459 break;
11460
11461 default:
11462 has_fixup = TRUE;
11463 break;
11464 }
11465 }
11466
11467 xtensa_format_encode (isa, fmt, insnbuf);
11468 xtensa_format_set_slot (isa, fmt, 0, insnbuf, slotbuf);
11469
11470 return has_fixup;
11471}
11472
11473
11474/* Convert the constant operands in the tinsn to slotbuf.
11475 Return TRUE if there is a symbol in the immediate field.
11476 (Eventually this should replace tinsn_to_insnbuf.) */
11477
11478/* Before this is called,
11479 1) the number of operands are correct
11480 2) the tinsn is a ITYPE_INSN
11481 3) ONLY the relaxable_ is built
11482 4) All operands are
11483 O_constant, O_symbol
11484 All constants fit
11485
11486 The return value tells whether there are any remaining O_symbols. */
11487
11488static bfd_boolean
7fa3d080
BW		 11489tinsn_to_slotbuf (xtensa_format fmt,
11490 int slot,
11491 TInsn *tinsn,
11492 xtensa_insnbuf slotbuf)
43cd72b9
BW		 11493{
11494 xtensa_isa isa = xtensa_default_isa;
11495 xtensa_opcode opcode = tinsn->opcode;
11496 bfd_boolean has_fixup = FALSE;
11497 int noperands = xtensa_opcode_num_operands (isa, opcode);
11498 int i;
11499
11500 *((int *) &slotbuf[0]) = 0;
11501 *((int *) &slotbuf[1]) = 0;
11502 assert (tinsn->insn_type == ITYPE_INSN);
11503 if (noperands != tinsn->ntok)
11504 as_fatal (_("operand number mismatch"));
11505
11506 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode))
11507 {
11508 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11509 xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
11510 return FALSE;
11511 }
11512
11513 for (i = 0; i < noperands; i++)
11514 {
11515 expressionS *expr = &tinsn->tok[i];
11516 int rc, line;
11517 char *file_name;
11518 uint32 opnd_value;
11519
11520 switch (expr->X_op)
11521 {
11522 case O_register:
11523 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11524 break;
11525 /* The register number has already been checked in
11526 expression_maybe_register, so we don't need to check here. */
11527 opnd_value = expr->X_add_number;
11528 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
11529 rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf,
11530 opnd_value);
11531 if (rc != 0)
11532 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa));
11533 break;
11534
11535 case O_constant:
11536 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11537 break;
11538 as_where (&file_name, &line);
11539 /* It is a constant and we called this function
11540 then we have to try to fit it. */
11541 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i,
e0001a05
NC		 11542 expr->X_add_number, file_name, line);
11543 break;
11544
e0001a05
NC		 11545 default:
11546 has_fixup = TRUE;
11547 break;
11548 }
11549 }
43cd72b9 11550
e0001a05
NC		 11551 return has_fixup;
11552}
11553
11554
43cd72b9 11555/* Check the instruction arguments. Return TRUE on failure. */
e0001a05 11556
7fa3d080
BW		 11557static bfd_boolean
11558tinsn_check_arguments (const TInsn *insn)
e0001a05
NC		 11559{
11560 xtensa_isa isa = xtensa_default_isa;
11561 xtensa_opcode opcode = insn->opcode;
11562
11563 if (opcode == XTENSA_UNDEFINED)
11564 {
11565 as_bad (_("invalid opcode"));
11566 return TRUE;
11567 }
11568
43cd72b9 11569 if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
e0001a05
NC		 11570 {
11571 as_bad (_("too few operands"));
11572 return TRUE;
11573 }
11574
43cd72b9 11575 if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
e0001a05
NC		 11576 {
11577 as_bad (_("too many operands"));
11578 return TRUE;
11579 }
11580 return FALSE;
11581}
11582
11583
11584/* Load an instruction from its encoded form. */
11585
11586static void
7fa3d080 11587tinsn_from_chars (TInsn *tinsn, char *f, int slot)
e0001a05 11588{
43cd72b9 11589 vliw_insn vinsn;
e0001a05 11590
43cd72b9
BW		 11591 xg_init_vinsn (&vinsn);
11592 vinsn_from_chars (&vinsn, f);
11593
11594 *tinsn = vinsn.slots[slot];
11595 xg_free_vinsn (&vinsn);
11596}
e0001a05 11597
43cd72b9
BW		 11598
11599static void
7fa3d080
BW		 11600tinsn_from_insnbuf (TInsn *tinsn,
11601 xtensa_insnbuf slotbuf,
11602 xtensa_format fmt,
11603 int slot)
43cd72b9
BW		 11604{
11605 int i;
11606 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 11607
11608 /* Find the immed. */
43cd72b9
BW		 11609 tinsn_init (tinsn);
11610 tinsn->insn_type = ITYPE_INSN;
11611 tinsn->is_specific_opcode = FALSE; /* must not be specific */
11612 tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
11613 tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
11614 for (i = 0; i < tinsn->ntok; i++)
e0001a05 11615 {
43cd72b9
BW		 11616 set_expr_const (&tinsn->tok[i],
11617 xtensa_insnbuf_get_operand (slotbuf, fmt, slot,
11618 tinsn->opcode, i));
e0001a05
NC		 11619 }
11620}
11621
11622
11623/* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11624
11625static void
7fa3d080 11626tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot)
e0001a05 11627{
43cd72b9 11628 xtensa_opcode opcode = tinsn->opcode;
e0001a05
NC		 11629 int opnum;
11630
43cd72b9 11631 if (fragP->tc_frag_data.slot_symbols[slot])
e0001a05
NC		 11632 {
11633 opnum = get_relaxable_immed (opcode);
43cd72b9
BW		 11634 assert (opnum >= 0);
11635 if (fragP->tc_frag_data.slot_sub_symbols[slot])
11636 {
11637 set_expr_symbol_offset_diff
11638 (&tinsn->tok[opnum],
11639 fragP->tc_frag_data.slot_symbols[slot],
11640 fragP->tc_frag_data.slot_sub_symbols[slot],
11641 fragP->tc_frag_data.slot_offsets[slot]);
11642 }
11643 else
11644 {
11645 set_expr_symbol_offset
11646 (&tinsn->tok[opnum],
11647 fragP->tc_frag_data.slot_symbols[slot],
11648 fragP->tc_frag_data.slot_offsets[slot]);
11649 }
e0001a05
NC		 11650 }
11651}
11652
11653
11654static int
7fa3d080 11655get_num_stack_text_bytes (IStack *istack)
e0001a05
NC		 11656{
11657 int i;
11658 int text_bytes = 0;
11659
11660 for (i = 0; i < istack->ninsn; i++)
11661 {
43cd72b9
BW		 11662 TInsn *tinsn = &istack->insn[i];
11663 if (tinsn->insn_type == ITYPE_INSN)
11664 text_bytes += xg_get_single_size (tinsn->opcode);
e0001a05
NC		 11665 }
11666 return text_bytes;
11667}
11668
11669
11670static int
7fa3d080 11671get_num_stack_literal_bytes (IStack *istack)
e0001a05
NC		 11672{
11673 int i;
11674 int lit_bytes = 0;
11675
11676 for (i = 0; i < istack->ninsn; i++)
11677 {
43cd72b9
BW		 11678 TInsn *tinsn = &istack->insn[i];
11679 if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1)
e0001a05
NC		 11680 lit_bytes += 4;
11681 }
11682 return lit_bytes;
11683}
11684
43cd72b9
BW		 11685\f
11686/* vliw_insn functions. */
11687
7fa3d080
BW		 11688static void
11689xg_init_vinsn (vliw_insn *v)
43cd72b9
BW		 11690{
11691 int i;
11692 xtensa_isa isa = xtensa_default_isa;
11693
11694 xg_clear_vinsn (v);
11695
11696 v->insnbuf = xtensa_insnbuf_alloc (isa);
11697 if (v->insnbuf == NULL)
11698 as_fatal (_("out of memory"));
11699
11700 for (i = 0; i < MAX_SLOTS; i++)
11701 {
11702 tinsn_init (&v->slots[i]);
11703 v->slots[i].opcode = XTENSA_UNDEFINED;
11704 v->slotbuf[i] = xtensa_insnbuf_alloc (isa);
11705 if (v->slotbuf[i] == NULL)
11706 as_fatal (_("out of memory"));
11707 }
11708}
11709
11710
7fa3d080
BW		 11711static void
11712xg_clear_vinsn (vliw_insn *v)
43cd72b9
BW		 11713{
11714 int i;
11715 v->format = XTENSA_UNDEFINED;
11716 v->num_slots = 0;
11717 v->inside_bundle = FALSE;
11718
11719 if (xt_saved_debug_type != DEBUG_NONE)
11720 debug_type = xt_saved_debug_type;
11721
11722 for (i = 0; i < MAX_SLOTS; i++)
11723 {
11724 memset (&v->slots[i], 0, sizeof (TInsn));
11725 v->slots[i].opcode = XTENSA_UNDEFINED;
11726 }
11727}
11728
11729
7fa3d080
BW		 11730static bfd_boolean
11731vinsn_has_specific_opcodes (vliw_insn *v)
43cd72b9
BW		 11732{
11733 int i;
11734
11735 for (i = 0; i < v->num_slots; i++)
11736 {
11737 if (v->slots[i].is_specific_opcode)
11738 return TRUE;
11739 }
11740 return FALSE;
11741}
11742
11743
7fa3d080
BW		 11744static void
11745xg_free_vinsn (vliw_insn *v)
43cd72b9
BW		 11746{
11747 int i;
11748 xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf);
11749 for (i = 0; i < MAX_SLOTS; i++)
11750 xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]);
11751}
11752
11753
11754/* Before this is called, we should have
11755 filled out the following fields:
11756
11757 1) the number of operands for each opcode are correct
11758 2) the tinsn in the slots are ITYPE_INSN
11759 3) ONLY the relaxable_ is built
11760 4) All operands are
11761 O_constant, O_symbol
11762 All constants fit
11763
11764 The return value tells whether there are any remaining O_symbols. */
11765
11766static bfd_boolean
7fa3d080
BW		 11767vinsn_to_insnbuf (vliw_insn *vinsn,
11768 char *frag_offset,
11769 fragS *fragP,
11770 bfd_boolean record_fixup)
43cd72b9
BW		 11771{
11772 xtensa_isa isa = xtensa_default_isa;
11773 xtensa_format fmt = vinsn->format;
11774 xtensa_insnbuf insnbuf = vinsn->insnbuf;
11775 int slot;
11776 bfd_boolean has_fixup = FALSE;
11777
11778 xtensa_format_encode (isa, fmt, insnbuf);
11779
11780 for (slot = 0; slot < vinsn->num_slots; slot++)
11781 {
11782 TInsn *tinsn = &vinsn->slots[slot];
11783 bfd_boolean tinsn_has_fixup =
11784 tinsn_to_slotbuf (vinsn->format, slot, tinsn,
11785 vinsn->slotbuf[slot]);
11786
11787 xtensa_format_set_slot (isa, fmt, slot,
11788 insnbuf, vinsn->slotbuf[slot]);
11789 /* tinsn_has_fixup tracks if there is a fixup at all.
11790 record_fixup controls globally. I.E., we use this
11791 function from several places, some of which are after
11792 fixups have already been recorded. Finally,
11793 tinsn->record_fixup controls based on the individual ops,
11794 which may or may not need it based on the relaxation
11795 requirements. */
11796 if (tinsn_has_fixup && record_fixup)
11797 {
11798 int i;
11799 xtensa_opcode opcode = tinsn->opcode;
11800 int noperands = xtensa_opcode_num_operands (isa, opcode);
11801 has_fixup = TRUE;
11802
11803 for (i = 0; i < noperands; i++)
11804 {
11805 expressionS* expr = &tinsn->tok[i];
11806 switch (expr->X_op)
11807 {
11808 case O_symbol:
11809 case O_lo16:
11810 case O_hi16:
11811 if (get_relaxable_immed (opcode) == i)
11812 {
11813 if (tinsn->record_fix || expr->X_op != O_symbol)
11814 {
11815 if (!xg_add_opcode_fix
11816 (tinsn, i, fmt, slot, expr, fragP,
11817 frag_offset - fragP->fr_literal))
11818 as_bad (_("instruction with constant operands does not fit"));
11819 }
11820 else
11821 {
11822 tinsn->symbol = expr->X_add_symbol;
11823 tinsn->offset = expr->X_add_number;
11824 }
11825 }
11826 else
11827 as_bad (_("invalid operand %d on '%s'"),
11828 i, xtensa_opcode_name (isa, opcode));
11829 break;
11830
11831 case O_constant:
11832 case O_register:
11833 break;
11834
11835 case O_subtract:
11836 if (get_relaxable_immed (opcode) == i)
11837 {
11838 if (tinsn->record_fix)
11839 as_bad (_("invalid subtract operand"));
11840 else
11841 {
11842 tinsn->symbol = expr->X_add_symbol;
11843 tinsn->sub_symbol = expr->X_op_symbol;
11844 tinsn->offset = expr->X_add_number;
11845 }
11846 }
11847 else
11848 as_bad (_("invalid operand %d on '%s'"),
11849 i, xtensa_opcode_name (isa, opcode));
11850 break;
11851
11852 default:
11853 as_bad (_("invalid expression for operand %d on '%s'"),
11854 i, xtensa_opcode_name (isa, opcode));
11855 break;
11856 }
11857 }
11858 }
11859 }
11860
11861 return has_fixup;
11862}
11863
11864
11865static void
7fa3d080 11866vinsn_from_chars (vliw_insn *vinsn, char *f)
43cd72b9
BW		 11867{
11868 static xtensa_insnbuf insnbuf = NULL;
11869 static xtensa_insnbuf slotbuf = NULL;
11870 int i;
11871 xtensa_format fmt;
11872 xtensa_isa isa = xtensa_default_isa;
11873
11874 if (!insnbuf)
11875 {
11876 insnbuf = xtensa_insnbuf_alloc (isa);
11877 slotbuf = xtensa_insnbuf_alloc (isa);
11878 }
11879
11880 xtensa_insnbuf_from_chars (isa, insnbuf, f, 0);
11881 fmt = xtensa_format_decode (isa, insnbuf);
11882 if (fmt == XTENSA_UNDEFINED)
11883 as_fatal (_("cannot decode instruction format"));
11884 vinsn->format = fmt;
11885 vinsn->num_slots = xtensa_format_num_slots (isa, fmt);
11886
11887 for (i = 0; i < vinsn->num_slots; i++)
11888 {
11889 TInsn *tinsn = &vinsn->slots[i];
11890 xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf);
11891 tinsn_from_insnbuf (tinsn, slotbuf, fmt, i);
11892 }
11893}
11894
e0001a05
NC		 11895\f
11896/* Expression utilities. */
11897
43cd72b9 11898/* Return TRUE if the expression is an integer constant. */
e0001a05
NC		 11899
11900bfd_boolean
7fa3d080 11901expr_is_const (const expressionS *s)
e0001a05
NC		 11902{
11903 return (s->X_op == O_constant);
11904}
11905
11906
11907/* Get the expression constant.
43cd72b9 11908 Calling this is illegal if expr_is_const () returns TRUE. */
e0001a05
NC		 11909
11910offsetT
7fa3d080 11911get_expr_const (const expressionS *s)
e0001a05
NC		 11912{
11913 assert (expr_is_const (s));
11914 return s->X_add_number;
11915}
11916
11917
11918/* Set the expression to a constant value. */
11919
11920void
7fa3d080 11921set_expr_const (expressionS *s, offsetT val)
e0001a05
NC		 11922{
11923 s->X_op = O_constant;
11924 s->X_add_number = val;
11925 s->X_add_symbol = NULL;
11926 s->X_op_symbol = NULL;
11927}
11928
11929
43cd72b9 11930bfd_boolean
7fa3d080 11931expr_is_register (const expressionS *s)
43cd72b9
BW		 11932{
11933 return (s->X_op == O_register);
11934}
11935
11936
11937/* Get the expression constant.
11938 Calling this is illegal if expr_is_const () returns TRUE. */
11939
11940offsetT
7fa3d080 11941get_expr_register (const expressionS *s)
43cd72b9
BW		 11942{
11943 assert (expr_is_register (s));
11944 return s->X_add_number;
11945}
11946
11947
e0001a05
NC		 11948/* Set the expression to a symbol + constant offset. */
11949
11950void
7fa3d080 11951set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset)
e0001a05
NC		 11952{
11953 s->X_op = O_symbol;
11954 s->X_add_symbol = sym;
11955 s->X_op_symbol = NULL; /* unused */
11956 s->X_add_number = offset;
11957}
11958
11959
43cd72b9
BW		 11960/* Set the expression to symbol - minus_sym + offset. */
11961
7fa3d080
BW		 11962static void
11963set_expr_symbol_offset_diff (expressionS *s,
11964 symbolS *sym,
11965 symbolS *minus_sym,
11966 offsetT offset)
43cd72b9
BW		 11967{
11968 s->X_op = O_subtract;
11969 s->X_add_symbol = sym;
11970 s->X_op_symbol = minus_sym; /* unused */
11971 s->X_add_number = offset;
11972}
11973
11974
11975/* Return TRUE if the two expressions are equal. */
11976
e0001a05 11977bfd_boolean
7fa3d080 11978expr_is_equal (expressionS *s1, expressionS *s2)
e0001a05
NC		 11979{
11980 if (s1->X_op != s2->X_op)
11981 return FALSE;
11982 if (s1->X_add_symbol != s2->X_add_symbol)
11983 return FALSE;
11984 if (s1->X_op_symbol != s2->X_op_symbol)
11985 return FALSE;
11986 if (s1->X_add_number != s2->X_add_number)
11987 return FALSE;
11988 return TRUE;
11989}
11990
11991
11992static void
7fa3d080 11993copy_expr (expressionS *dst, const expressionS *src)
e0001a05
NC		 11994{
11995 memcpy (dst, src, sizeof (expressionS));
11996}
11997
11998\f
11999/* Support for Tensilica's "--rename-section" option. */
12000
12001#ifdef XTENSA_SECTION_RENAME
12002
12003struct rename_section_struct
12004{
12005 char *old_name;
12006 char *new_name;
12007 struct rename_section_struct *next;
12008};
12009
12010static struct rename_section_struct *section_rename;
12011
12012
43cd72b9 12013/* Parse the string oldname=new_name:oldname2=new_name2
e0001a05
NC		 12014 and call add_section_rename. */
12015
7fa3d080
BW		 12016static void
12017build_section_rename (const char *arg)
e0001a05
NC		 12018{
12019 char *this_arg = NULL;
12020 char *next_arg = NULL;
12021
12022 for (this_arg = strdup (arg); this_arg != NULL; this_arg = next_arg)
12023 {
12024 if (this_arg)
12025 {
12026 next_arg = strchr (this_arg, ':');
12027 if (next_arg)
12028 {
12029 *next_arg = '\0';
12030 next_arg++;
12031 }
12032 }
12033 {
12034 char *old_name = this_arg;
12035 char *new_name = strchr (this_arg, '=');
12036
12037 if (*old_name == '\0')
12038 {
12039 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
12040 continue;
12041 }
12042 if (!new_name || new_name[1] == '\0')
12043 {
12044 as_warn (_("ignoring invalid '-rename-section' "
12045 "specification: '%s'"), old_name);
12046 continue;
12047 }
12048 *new_name = '\0';
12049 new_name++;
12050 add_section_rename (old_name, new_name);
12051 }
12052 }
12053}
12054
12055
12056static void
7fa3d080 12057add_section_rename (char *old_name, char *new_name)
e0001a05
NC		 12058{
12059 struct rename_section_struct *r = section_rename;
12060
12061 /* Check for invalid section renaming. */
12062 for (r = section_rename; r != NULL; r = r->next)
12063 {
12064 if (strcmp (r->old_name, old_name) == 0)
12065 as_bad (_("section %s renamed multiple times"), old_name);
12066 if (strcmp (r->new_name, new_name) == 0)
12067 as_bad (_("multiple sections remapped to output section %s"),
12068 new_name);
12069 }
12070
12071 /* Now add it. */
12072 r = (struct rename_section_struct *)
12073 xmalloc (sizeof (struct rename_section_struct));
12074 r->old_name = strdup (old_name);
12075 r->new_name = strdup (new_name);
12076 r->next = section_rename;
12077 section_rename = r;
12078}
12079
12080
12081const char *
7fa3d080 12082xtensa_section_rename (const char *name)
e0001a05
NC		 12083{
12084 struct rename_section_struct *r = section_rename;
12085
12086 for (r = section_rename; r != NULL; r = r->next)
43cd72b9
BW		 12087 {
12088 if (strcmp (r->old_name, name) == 0)
12089 return r->new_name;
12090 }
e0001a05
NC		 12091
12092 return name;
12093}
12094
12095#endif /* XTENSA_SECTION_RENAME */
GDB Binutils - Deliverables
This page took 0.692881 seconds and 4 git commands to generate.