Commit | Line | Data |
---|---|---|
e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
2571583a | 2 | Copyright (C) 2003-2017 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
e0001a05 NC |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 | 20 | |
e0001a05 | 21 | #include "as.h" |
df7b86aa | 22 | #include <limits.h> |
e0001a05 NC |
23 | #include "sb.h" |
24 | #include "safe-ctype.h" | |
25 | #include "tc-xtensa.h" | |
e0001a05 NC |
26 | #include "subsegs.h" |
27 | #include "xtensa-relax.h" | |
cda2eb9e | 28 | #include "dwarf2dbg.h" |
b224e962 | 29 | #include "xtensa-istack.h" |
e0001a05 NC |
30 | #include "struc-symbol.h" |
31 | #include "xtensa-config.h" | |
b0b79343 | 32 | #include "elf/xtensa.h" |
e0001a05 | 33 | |
2caa7ca0 BW |
34 | /* Provide default values for new configuration settings. */ |
35 | #ifndef XSHAL_ABI | |
36 | #define XSHAL_ABI 0 | |
37 | #endif | |
38 | ||
e0001a05 NC |
39 | #ifndef uint32 |
40 | #define uint32 unsigned int | |
41 | #endif | |
42 | #ifndef int32 | |
43 | #define int32 signed int | |
44 | #endif | |
45 | ||
46 | /* Notes: | |
47 | ||
e0001a05 NC |
48 | Naming conventions (used somewhat inconsistently): |
49 | The xtensa_ functions are exported | |
50 | The xg_ functions are internal | |
51 | ||
52 | We also have a couple of different extensibility mechanisms. | |
53 | 1) The idiom replacement: | |
54 | This is used when a line is first parsed to | |
55 | replace an instruction pattern with another instruction | |
56 | It is currently limited to replacements of instructions | |
57 | with constant operands. | |
58 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
59 | replacement patterns. When an instruction's immediate field | |
60 | does not fit the next instruction sequence is attempted. | |
61 | In addition, "narrow" opcodes are supported this way. */ | |
62 | ||
63 | ||
64 | /* Define characters with special meanings to GAS. */ | |
65 | const char comment_chars[] = "#"; | |
66 | const char line_comment_chars[] = "#"; | |
67 | const char line_separator_chars[] = ";"; | |
68 | const char EXP_CHARS[] = "eE"; | |
69 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
70 | ||
71 | ||
43cd72b9 BW |
72 | /* Flags to indicate whether the hardware supports the density and |
73 | absolute literals options. */ | |
e0001a05 | 74 | |
f7e16c2a MF |
75 | bfd_boolean density_supported; |
76 | bfd_boolean absolute_literals_supported; | |
43cd72b9 | 77 | |
43cd72b9 BW |
78 | static vliw_insn cur_vinsn; |
79 | ||
77cba8a3 | 80 | unsigned xtensa_num_pipe_stages; |
f7e16c2a | 81 | unsigned xtensa_fetch_width; |
43cd72b9 BW |
82 | |
83 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
84 | ||
85 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 86 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
87 | back end. */ |
88 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
89 | |
90 | /* Flags for properties of the last instruction in a segment. */ | |
91 | #define FLAG_IS_A0_WRITER 0x1 | |
92 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
93 | ||
94 | ||
95 | /* We define a special segment names ".literal" to place literals | |
96 | into. The .fini and .init sections are special because they | |
97 | contain code that is moved together by the linker. We give them | |
98 | their own special .fini.literal and .init.literal sections. */ | |
99 | ||
100 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 101 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 | 102 | #define INIT_SECTION_NAME xtensa_section_rename (".init") |
74869ac7 | 103 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
e0001a05 NC |
104 | |
105 | ||
43cd72b9 | 106 | /* This type is used for the directive_stack to keep track of the |
74869ac7 BW |
107 | state of the literal collection pools. If lit_prefix is set, it is |
108 | used to determine the literal section names; otherwise, the literal | |
109 | sections are determined based on the current text section. The | |
110 | lit_seg and lit4_seg fields cache these literal sections, with the | |
111 | current_text_seg field used a tag to indicate whether the cached | |
112 | values are valid. */ | |
e0001a05 NC |
113 | |
114 | typedef struct lit_state_struct | |
115 | { | |
74869ac7 BW |
116 | char *lit_prefix; |
117 | segT current_text_seg; | |
e0001a05 | 118 | segT lit_seg; |
43cd72b9 | 119 | segT lit4_seg; |
e0001a05 NC |
120 | } lit_state; |
121 | ||
122 | static lit_state default_lit_sections; | |
123 | ||
124 | ||
74869ac7 BW |
125 | /* We keep a list of literal segments. The seg_list type is the node |
126 | for this list. The literal_head pointer is the head of the list, | |
127 | with the literal_head_h dummy node at the start. */ | |
e0001a05 NC |
128 | |
129 | typedef struct seg_list_struct | |
130 | { | |
131 | struct seg_list_struct *next; | |
132 | segT seg; | |
133 | } seg_list; | |
134 | ||
135 | static seg_list literal_head_h; | |
136 | static seg_list *literal_head = &literal_head_h; | |
e0001a05 NC |
137 | |
138 | ||
82e7541d BW |
139 | /* Lists of symbols. We keep a list of symbols that label the current |
140 | instruction, so that we can adjust the symbols when inserting alignment | |
141 | for various instructions. We also keep a list of all the symbols on | |
142 | literals, so that we can fix up those symbols when the literals are | |
143 | later moved into the text sections. */ | |
144 | ||
145 | typedef struct sym_list_struct | |
146 | { | |
147 | struct sym_list_struct *next; | |
148 | symbolS *sym; | |
149 | } sym_list; | |
150 | ||
151 | static sym_list *insn_labels = NULL; | |
152 | static sym_list *free_insn_labels = NULL; | |
153 | static sym_list *saved_insn_labels = NULL; | |
154 | ||
155 | static sym_list *literal_syms; | |
156 | ||
157 | ||
43cd72b9 BW |
158 | /* Flags to determine whether to prefer const16 or l32r |
159 | if both options are available. */ | |
160 | int prefer_const16 = 0; | |
161 | int prefer_l32r = 0; | |
162 | ||
e0001a05 NC |
163 | /* Global flag to indicate when we are emitting literals. */ |
164 | int generating_literals = 0; | |
165 | ||
43cd72b9 BW |
166 | /* The following PROPERTY table definitions are copied from |
167 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
168 | ||
169 | /* Flags in the property tables to specify whether blocks of memory | |
170 | are literals, instructions, data, or unreachable. For | |
171 | instructions, blocks that begin loop targets and branch targets are | |
172 | designated. Blocks that do not allow density, instruction | |
173 | reordering or transformation are also specified. Finally, for | |
174 | branch targets, branch target alignment priority is included. | |
175 | Alignment of the next block is specified in the current block | |
176 | and the size of the current block does not include any fill required | |
177 | to align to the next block. */ | |
178 | ||
179 | #define XTENSA_PROP_LITERAL 0x00000001 | |
180 | #define XTENSA_PROP_INSN 0x00000002 | |
181 | #define XTENSA_PROP_DATA 0x00000004 | |
182 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
183 | /* Instruction only properties at beginning of code. */ | |
184 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
185 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
186 | /* Instruction only properties about code. */ | |
187 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
188 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
99ded152 BW |
189 | /* Historically, NO_TRANSFORM was a property of instructions, |
190 | but it should apply to literals under certain circumstances. */ | |
191 | #define XTENSA_PROP_NO_TRANSFORM 0x00000100 | |
43cd72b9 BW |
192 | |
193 | /* Branch target alignment information. This transmits information | |
194 | to the linker optimization about the priority of aligning a | |
195 | particular block for branch target alignment: None, low priority, | |
196 | high priority, or required. These only need to be checked in | |
197 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
198 | Common usage is | |
199 | ||
200 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
201 | case XTENSA_PROP_BT_ALIGN_NONE: | |
202 | case XTENSA_PROP_BT_ALIGN_LOW: | |
203 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
204 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
205 | */ | |
206 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
207 | ||
208 | /* No branch target alignment. */ | |
209 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
210 | /* Low priority branch target alignment. */ | |
211 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
212 | /* High priority branch target alignment. */ | |
213 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
214 | /* Required branch target alignment. */ | |
215 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
216 | ||
43cd72b9 BW |
217 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ |
218 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
219 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
220 | ||
221 | ||
222 | /* Alignment is specified in the block BEFORE the one that needs | |
223 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
224 | get the required alignment specified as a power of 2. Use | |
225 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
226 | alignment. Be careful of side effects since the SET will evaluate | |
227 | flags twice. Also, note that the SIZE of a block in the property | |
228 | table does not include the alignment size, so the alignment fill | |
229 | must be calculated to determine if two blocks are contiguous. | |
230 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
231 | possible future implementation. */ | |
232 | ||
233 | #define XTENSA_PROP_ALIGN 0x00000800 | |
234 | ||
235 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
236 | ||
43cd72b9 BW |
237 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ |
238 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
239 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
240 | ||
241 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
242 | ||
243 | ||
244 | /* Structure for saving instruction and alignment per-fragment data | |
245 | that will be written to the object file. This structure is | |
246 | equivalent to the actual data that will be written out to the file | |
247 | but is easier to use. We provide a conversion to file flags | |
248 | in frag_flags_to_number. */ | |
249 | ||
250 | typedef struct frag_flags_struct frag_flags; | |
251 | ||
252 | struct frag_flags_struct | |
253 | { | |
254 | /* is_literal should only be used after xtensa_move_literals. | |
255 | If you need to check if you are generating a literal fragment, | |
256 | then use the generating_literals global. */ | |
257 | ||
258 | unsigned is_literal : 1; | |
259 | unsigned is_insn : 1; | |
260 | unsigned is_data : 1; | |
261 | unsigned is_unreachable : 1; | |
262 | ||
99ded152 BW |
263 | /* is_specific_opcode implies no_transform. */ |
264 | unsigned is_no_transform : 1; | |
265 | ||
43cd72b9 BW |
266 | struct |
267 | { | |
268 | unsigned is_loop_target : 1; | |
269 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
270 | unsigned bt_align_priority : 2; | |
271 | ||
272 | unsigned is_no_density : 1; | |
273 | /* no_longcalls flag does not need to be placed in the object file. */ | |
43cd72b9 BW |
274 | |
275 | unsigned is_no_reorder : 1; | |
276 | ||
277 | /* Uses absolute literal addressing for l32r. */ | |
278 | unsigned is_abslit : 1; | |
279 | } insn; | |
280 | unsigned is_align : 1; | |
281 | unsigned alignment : 5; | |
282 | }; | |
283 | ||
284 | ||
285 | /* Structure for saving information about a block of property data | |
286 | for frags that have the same flags. */ | |
287 | struct xtensa_block_info_struct | |
288 | { | |
289 | segT sec; | |
290 | bfd_vma offset; | |
291 | size_t size; | |
292 | frag_flags flags; | |
293 | struct xtensa_block_info_struct *next; | |
294 | }; | |
295 | ||
e0001a05 NC |
296 | |
297 | /* Structure for saving the current state before emitting literals. */ | |
298 | typedef struct emit_state_struct | |
299 | { | |
300 | const char *name; | |
301 | segT now_seg; | |
302 | subsegT now_subseg; | |
303 | int generating_literals; | |
304 | } emit_state; | |
305 | ||
306 | ||
43cd72b9 BW |
307 | /* Opcode placement information */ |
308 | ||
309 | typedef unsigned long long bitfield; | |
310 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
311 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
312 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
313 | ||
314 | #define MAX_FORMATS 32 | |
315 | ||
316 | typedef struct op_placement_info_struct | |
317 | { | |
318 | int num_formats; | |
319 | /* A number describing how restrictive the issue is for this | |
320 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 321 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 322 | only one format but many slots in that format. The most |
c138bc38 | 323 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
324 | format. */ |
325 | int issuef; | |
43cd72b9 | 326 | xtensa_format narrowest; |
43cd72b9 | 327 | char narrowest_size; |
b2d179be | 328 | char narrowest_slot; |
43cd72b9 BW |
329 | |
330 | /* formats is a bitfield with the Nth bit set | |
331 | if the opcode fits in the Nth xtensa_format. */ | |
332 | bitfield formats; | |
333 | ||
334 | /* slots[N]'s Mth bit is set if the op fits in the | |
335 | Mth slot of the Nth xtensa_format. */ | |
336 | bitfield slots[MAX_FORMATS]; | |
337 | ||
338 | /* A count of the number of slots in a given format | |
339 | an op can fit (i.e., the bitcount of the slot field above). */ | |
340 | char slots_in_format[MAX_FORMATS]; | |
341 | ||
342 | } op_placement_info, *op_placement_info_table; | |
343 | ||
344 | op_placement_info_table op_placement_table; | |
345 | ||
346 | ||
347 | /* Extra expression types. */ | |
348 | ||
349 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
350 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
351 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
1bbb5f21 | 352 | #define O_pcrel O_md4 /* value is a PC-relative offset */ |
28dbbc02 BW |
353 | #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */ |
354 | #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */ | |
355 | #define O_tlscall O_md7 /* TLS_CALL relocation */ | |
356 | #define O_tpoff O_md8 /* TPOFF relocation */ | |
357 | #define O_dtpoff O_md9 /* DTPOFF relocation */ | |
43cd72b9 | 358 | |
bbdd25a8 BW |
359 | struct suffix_reloc_map |
360 | { | |
b9bb4a93 | 361 | const char *suffix; |
bbdd25a8 BW |
362 | int length; |
363 | bfd_reloc_code_real_type reloc; | |
cc34adb2 | 364 | operatorT operator; |
bbdd25a8 BW |
365 | }; |
366 | ||
367 | #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } | |
368 | ||
369 | static struct suffix_reloc_map suffix_relocs[] = | |
370 | { | |
371 | SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), | |
372 | SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), | |
373 | SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), | |
1bbb5f21 | 374 | SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel), |
28dbbc02 BW |
375 | SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC, O_tlsfunc), |
376 | SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG, O_tlsarg), | |
377 | SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL, O_tlscall), | |
378 | SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF, O_tpoff), | |
379 | SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF, O_dtpoff), | |
bbdd25a8 BW |
380 | }; |
381 | ||
43cd72b9 | 382 | |
e0001a05 NC |
383 | /* Directives. */ |
384 | ||
385 | typedef enum | |
386 | { | |
387 | directive_none = 0, | |
388 | directive_literal, | |
389 | directive_density, | |
43cd72b9 | 390 | directive_transform, |
e0001a05 NC |
391 | directive_freeregs, |
392 | directive_longcalls, | |
43cd72b9 BW |
393 | directive_literal_prefix, |
394 | directive_schedule, | |
395 | directive_absolute_literals, | |
396 | directive_last_directive | |
e0001a05 NC |
397 | } directiveE; |
398 | ||
399 | typedef struct | |
400 | { | |
401 | const char *name; | |
402 | bfd_boolean can_be_negated; | |
403 | } directive_infoS; | |
404 | ||
405 | const directive_infoS directive_info[] = | |
406 | { | |
43cd72b9 BW |
407 | { "none", FALSE }, |
408 | { "literal", FALSE }, | |
409 | { "density", TRUE }, | |
410 | { "transform", TRUE }, | |
411 | { "freeregs", FALSE }, | |
412 | { "longcalls", TRUE }, | |
413 | { "literal_prefix", FALSE }, | |
414 | { "schedule", TRUE }, | |
415 | { "absolute-literals", TRUE } | |
e0001a05 NC |
416 | }; |
417 | ||
418 | bfd_boolean directive_state[] = | |
419 | { | |
420 | FALSE, /* none */ | |
421 | FALSE, /* literal */ | |
e0001a05 | 422 | FALSE, /* density */ |
43cd72b9 | 423 | TRUE, /* transform */ |
e0001a05 NC |
424 | FALSE, /* freeregs */ |
425 | FALSE, /* longcalls */ | |
43cd72b9 | 426 | FALSE, /* literal_prefix */ |
2caa7ca0 | 427 | FALSE, /* schedule */ |
43cd72b9 | 428 | FALSE /* absolute_literals */ |
e0001a05 NC |
429 | }; |
430 | ||
b46824bd MF |
431 | /* A circular list of all potential and actual literal pool locations |
432 | in a segment. */ | |
433 | struct litpool_frag | |
434 | { | |
435 | struct litpool_frag *next; | |
436 | struct litpool_frag *prev; | |
437 | fragS *fragP; | |
438 | addressT addr; | |
439 | short priority; /* 1, 2, or 3 -- 1 is highest */ | |
440 | short original_priority; | |
441 | }; | |
442 | ||
443 | /* Map a segment to its litpool_frag list. */ | |
444 | struct litpool_seg | |
445 | { | |
446 | struct litpool_seg *next; | |
447 | asection *seg; | |
448 | struct litpool_frag frag_list; | |
449 | int frag_count; /* since last litpool location */ | |
450 | }; | |
451 | ||
452 | static struct litpool_seg litpool_seg_list; | |
453 | ||
e0001a05 NC |
454 | |
455 | /* Directive functions. */ | |
456 | ||
7fa3d080 BW |
457 | static void xtensa_begin_directive (int); |
458 | static void xtensa_end_directive (int); | |
74869ac7 | 459 | static void xtensa_literal_prefix (void); |
7fa3d080 BW |
460 | static void xtensa_literal_position (int); |
461 | static void xtensa_literal_pseudo (int); | |
462 | static void xtensa_frequency_pseudo (int); | |
463 | static void xtensa_elf_cons (int); | |
fb227da0 | 464 | static void xtensa_leb128 (int); |
e0001a05 | 465 | |
7fa3d080 | 466 | /* Parsing and Idiom Translation. */ |
e0001a05 | 467 | |
7fa3d080 | 468 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 469 | |
e0001a05 NC |
470 | /* Various Other Internal Functions. */ |
471 | ||
84b08ed9 BW |
472 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
473 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
474 | static void xtensa_mark_literal_pool_location (void); |
475 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
476 | static fragS *get_literal_pool_location (segT); | |
477 | static void set_literal_pool_location (segT, fragS *); | |
478 | static void xtensa_set_frag_assembly_state (fragS *); | |
479 | static void finish_vinsn (vliw_insn *); | |
480 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 481 | static int total_frag_text_expansion (fragS *); |
a82c7d90 DW |
482 | static bfd_boolean use_trampolines = TRUE; |
483 | static void xtensa_check_frag_count (void); | |
484 | static void xtensa_create_trampoline_frag (bfd_boolean); | |
485 | static void xtensa_maybe_create_trampoline_frag (void); | |
486 | struct trampoline_frag; | |
46888d71 MF |
487 | static int init_trampoline_frag (fragS *); |
488 | static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset); | |
b46824bd MF |
489 | static void xtensa_maybe_create_literal_pool_frag (bfd_boolean, bfd_boolean); |
490 | static bfd_boolean auto_litpools = FALSE; | |
491 | static int auto_litpool_limit = 10000; | |
e0001a05 NC |
492 | |
493 | /* Alignment Functions. */ | |
494 | ||
d77b99c9 BW |
495 | static int get_text_align_power (unsigned); |
496 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 497 | static int branch_align_power (segT); |
e0001a05 NC |
498 | |
499 | /* Helpers for xtensa_relax_frag(). */ | |
500 | ||
7fa3d080 | 501 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 502 | |
b08b5071 | 503 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 504 | |
7fa3d080 BW |
505 | static unsigned get_last_insn_flags (segT, subsegT); |
506 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
507 | static float get_subseg_total_freq (segT, subsegT); |
508 | static float get_subseg_target_freq (segT, subsegT); | |
509 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
510 | |
511 | /* Segment list functions. */ | |
512 | ||
7fa3d080 BW |
513 | static void xtensa_move_literals (void); |
514 | static void xtensa_reorder_segments (void); | |
515 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
516 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
517 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
518 | static void xtensa_restore_emit_state (emit_state *); | |
74869ac7 | 519 | static segT cache_literal_section (bfd_boolean); |
e0001a05 | 520 | |
43cd72b9 BW |
521 | /* op_placement_info functions. */ |
522 | ||
7fa3d080 BW |
523 | static void init_op_placement_info_table (void); |
524 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
525 | static int xg_get_single_size (xtensa_opcode); | |
526 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 527 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 528 | |
e0001a05 | 529 | /* TInsn and IStack functions. */ |
43cd72b9 | 530 | |
7fa3d080 BW |
531 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
532 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
533 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
534 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
535 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
536 | static void tinsn_from_chars (TInsn *, char *, int); | |
537 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
538 | static int get_num_stack_text_bytes (IStack *); | |
539 | static int get_num_stack_literal_bytes (IStack *); | |
a82c7d90 | 540 | static bfd_boolean tinsn_to_slotbuf (xtensa_format, int, TInsn *, xtensa_insnbuf); |
e0001a05 | 541 | |
43cd72b9 BW |
542 | /* vliw_insn functions. */ |
543 | ||
7fa3d080 | 544 | static void xg_init_vinsn (vliw_insn *); |
d8392fd9 | 545 | static void xg_copy_vinsn (vliw_insn *, vliw_insn *); |
7fa3d080 BW |
546 | static void xg_clear_vinsn (vliw_insn *); |
547 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
548 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 549 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
550 | (vliw_insn *, char *, fragS *, bfd_boolean); |
551 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 552 | |
e0001a05 | 553 | /* Expression Utilities. */ |
43cd72b9 | 554 | |
7fa3d080 BW |
555 | bfd_boolean expr_is_const (const expressionS *); |
556 | offsetT get_expr_const (const expressionS *); | |
557 | void set_expr_const (expressionS *, offsetT); | |
558 | bfd_boolean expr_is_register (const expressionS *); | |
559 | offsetT get_expr_register (const expressionS *); | |
560 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
561 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
562 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 563 | |
9456465c BW |
564 | /* Section renaming. */ |
565 | ||
7fa3d080 | 566 | static void build_section_rename (const char *); |
e0001a05 | 567 | |
e0001a05 NC |
568 | |
569 | /* ISA imported from bfd. */ | |
570 | extern xtensa_isa xtensa_default_isa; | |
571 | ||
572 | extern int target_big_endian; | |
573 | ||
574 | static xtensa_opcode xtensa_addi_opcode; | |
575 | static xtensa_opcode xtensa_addmi_opcode; | |
576 | static xtensa_opcode xtensa_call0_opcode; | |
577 | static xtensa_opcode xtensa_call4_opcode; | |
578 | static xtensa_opcode xtensa_call8_opcode; | |
579 | static xtensa_opcode xtensa_call12_opcode; | |
580 | static xtensa_opcode xtensa_callx0_opcode; | |
581 | static xtensa_opcode xtensa_callx4_opcode; | |
582 | static xtensa_opcode xtensa_callx8_opcode; | |
583 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 584 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 585 | static xtensa_opcode xtensa_entry_opcode; |
d12f9798 | 586 | static xtensa_opcode xtensa_extui_opcode; |
43cd72b9 BW |
587 | static xtensa_opcode xtensa_movi_opcode; |
588 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 589 | static xtensa_opcode xtensa_isync_opcode; |
19e8f41a | 590 | static xtensa_opcode xtensa_j_opcode; |
e0001a05 | 591 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 592 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
593 | static xtensa_opcode xtensa_loop_opcode; |
594 | static xtensa_opcode xtensa_loopnez_opcode; | |
595 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 596 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
597 | static xtensa_opcode xtensa_nop_n_opcode; |
598 | static xtensa_opcode xtensa_or_opcode; | |
599 | static xtensa_opcode xtensa_ret_opcode; | |
600 | static xtensa_opcode xtensa_ret_n_opcode; | |
601 | static xtensa_opcode xtensa_retw_opcode; | |
602 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 603 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 | 604 | static xtensa_opcode xtensa_waiti_opcode; |
62af60e2 | 605 | static int config_max_slots = 0; |
e0001a05 NC |
606 | |
607 | \f | |
608 | /* Command-line Options. */ | |
609 | ||
610 | bfd_boolean use_literal_section = TRUE; | |
19fc3723 | 611 | enum flix_level produce_flix = FLIX_ALL; |
e0001a05 | 612 | static bfd_boolean align_targets = TRUE; |
43cd72b9 | 613 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 614 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
615 | static bfd_boolean workaround_a0_b_retw = FALSE; |
616 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
617 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 618 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 619 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 620 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 621 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
e0001a05 | 622 | |
43cd72b9 BW |
623 | /* When workaround_short_loops is TRUE, all loops with early exits must |
624 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
625 | to the workaround_short_loop flag. In addition to the | |
626 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
627 | must have at least 3 instructions. */ | |
e0001a05 | 628 | |
43cd72b9 | 629 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 630 | |
7fa3d080 BW |
631 | |
632 | static void | |
633 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
634 | { | |
635 | if (earliest > latest) | |
636 | as_fatal (_("illegal range of target hardware versions")); | |
637 | ||
638 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
639 | if (earliest < 105000 || latest < 105000) | |
640 | { | |
641 | workaround_a0_b_retw |= TRUE; | |
642 | workaround_b_j_loop_end |= TRUE; | |
643 | workaround_short_loop |= TRUE; | |
644 | workaround_close_loop_end |= TRUE; | |
645 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 646 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
647 | } |
648 | } | |
649 | ||
650 | ||
e0001a05 NC |
651 | enum |
652 | { | |
653 | option_density = OPTION_MD_BASE, | |
654 | option_no_density, | |
655 | ||
19fc3723 SA |
656 | option_flix, |
657 | option_no_generate_flix, | |
658 | option_no_flix, | |
659 | ||
e0001a05 NC |
660 | option_relax, |
661 | option_no_relax, | |
662 | ||
43cd72b9 BW |
663 | option_link_relax, |
664 | option_no_link_relax, | |
665 | ||
e0001a05 NC |
666 | option_generics, |
667 | option_no_generics, | |
668 | ||
43cd72b9 BW |
669 | option_transform, |
670 | option_no_transform, | |
671 | ||
e0001a05 NC |
672 | option_text_section_literals, |
673 | option_no_text_section_literals, | |
674 | ||
43cd72b9 BW |
675 | option_absolute_literals, |
676 | option_no_absolute_literals, | |
677 | ||
e0001a05 NC |
678 | option_align_targets, |
679 | option_no_align_targets, | |
680 | ||
43cd72b9 | 681 | option_warn_unaligned_targets, |
e0001a05 NC |
682 | |
683 | option_longcalls, | |
684 | option_no_longcalls, | |
685 | ||
686 | option_workaround_a0_b_retw, | |
687 | option_no_workaround_a0_b_retw, | |
688 | ||
689 | option_workaround_b_j_loop_end, | |
690 | option_no_workaround_b_j_loop_end, | |
691 | ||
692 | option_workaround_short_loop, | |
693 | option_no_workaround_short_loop, | |
694 | ||
695 | option_workaround_all_short_loops, | |
696 | option_no_workaround_all_short_loops, | |
697 | ||
698 | option_workaround_close_loop_end, | |
699 | option_no_workaround_close_loop_end, | |
700 | ||
701 | option_no_workarounds, | |
702 | ||
e0001a05 | 703 | option_rename_section_name, |
e0001a05 | 704 | |
43cd72b9 BW |
705 | option_prefer_l32r, |
706 | option_prefer_const16, | |
707 | ||
a82c7d90 DW |
708 | option_target_hardware, |
709 | ||
710 | option_trampolines, | |
711 | option_no_trampolines, | |
b46824bd MF |
712 | |
713 | option_auto_litpools, | |
714 | option_no_auto_litpools, | |
715 | option_auto_litpool_limit, | |
e0001a05 NC |
716 | }; |
717 | ||
718 | const char *md_shortopts = ""; | |
719 | ||
720 | struct option md_longopts[] = | |
721 | { | |
43cd72b9 BW |
722 | { "density", no_argument, NULL, option_density }, |
723 | { "no-density", no_argument, NULL, option_no_density }, | |
724 | ||
19fc3723 SA |
725 | { "flix", no_argument, NULL, option_flix }, |
726 | { "no-generate-flix", no_argument, NULL, option_no_generate_flix }, | |
727 | { "no-allow-flix", no_argument, NULL, option_no_flix }, | |
728 | ||
43cd72b9 BW |
729 | /* Both "relax" and "generics" are deprecated and treated as equivalent |
730 | to the "transform" option. */ | |
731 | { "relax", no_argument, NULL, option_relax }, | |
732 | { "no-relax", no_argument, NULL, option_no_relax }, | |
733 | { "generics", no_argument, NULL, option_generics }, | |
734 | { "no-generics", no_argument, NULL, option_no_generics }, | |
735 | ||
736 | { "transform", no_argument, NULL, option_transform }, | |
737 | { "no-transform", no_argument, NULL, option_no_transform }, | |
738 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
739 | { "no-text-section-literals", no_argument, NULL, | |
740 | option_no_text_section_literals }, | |
741 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
742 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
743 | /* This option was changed from -align-target to -target-align |
744 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 745 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
746 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
747 | { "warn-unaligned-targets", no_argument, NULL, | |
748 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
749 | { "longcalls", no_argument, NULL, option_longcalls }, |
750 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
751 | ||
752 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
753 | option_no_workaround_a0_b_retw }, | |
754 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 755 | |
43cd72b9 BW |
756 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
757 | option_no_workaround_b_j_loop_end }, | |
758 | { "workaround-b-j-loop-end", no_argument, NULL, | |
759 | option_workaround_b_j_loop_end }, | |
e0001a05 | 760 | |
43cd72b9 BW |
761 | { "no-workaround-short-loops", no_argument, NULL, |
762 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
763 | { "workaround-short-loops", no_argument, NULL, |
764 | option_workaround_short_loop }, | |
e0001a05 | 765 | |
43cd72b9 BW |
766 | { "no-workaround-all-short-loops", no_argument, NULL, |
767 | option_no_workaround_all_short_loops }, | |
768 | { "workaround-all-short-loop", no_argument, NULL, | |
769 | option_workaround_all_short_loops }, | |
770 | ||
771 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
772 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
773 | ||
774 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
775 | ||
776 | { "no-workaround-close-loop-end", no_argument, NULL, | |
777 | option_no_workaround_close_loop_end }, | |
778 | { "workaround-close-loop-end", no_argument, NULL, | |
779 | option_workaround_close_loop_end }, | |
e0001a05 | 780 | |
7fa3d080 | 781 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 782 | |
43cd72b9 BW |
783 | { "link-relax", no_argument, NULL, option_link_relax }, |
784 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
785 | ||
786 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
787 | ||
a82c7d90 DW |
788 | { "trampolines", no_argument, NULL, option_trampolines }, |
789 | { "no-trampolines", no_argument, NULL, option_no_trampolines }, | |
790 | ||
b46824bd MF |
791 | { "auto-litpools", no_argument, NULL, option_auto_litpools }, |
792 | { "no-auto-litpools", no_argument, NULL, option_no_auto_litpools }, | |
793 | { "auto-litpool-limit", required_argument, NULL, option_auto_litpool_limit }, | |
794 | ||
43cd72b9 | 795 | { NULL, no_argument, NULL, 0 } |
e0001a05 NC |
796 | }; |
797 | ||
798 | size_t md_longopts_size = sizeof md_longopts; | |
799 | ||
800 | ||
801 | int | |
17b9d67d | 802 | md_parse_option (int c, const char *arg) |
e0001a05 NC |
803 | { |
804 | switch (c) | |
805 | { | |
806 | case option_density: | |
43cd72b9 | 807 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
808 | return 1; |
809 | case option_no_density: | |
43cd72b9 | 810 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 811 | return 1; |
43cd72b9 BW |
812 | case option_link_relax: |
813 | linkrelax = 1; | |
e0001a05 | 814 | return 1; |
43cd72b9 BW |
815 | case option_no_link_relax: |
816 | linkrelax = 0; | |
e0001a05 | 817 | return 1; |
19fc3723 SA |
818 | case option_flix: |
819 | produce_flix = FLIX_ALL; | |
820 | return 1; | |
821 | case option_no_generate_flix: | |
822 | produce_flix = FLIX_NO_GENERATE; | |
823 | return 1; | |
824 | case option_no_flix: | |
825 | produce_flix = FLIX_NONE; | |
826 | return 1; | |
43cd72b9 BW |
827 | case option_generics: |
828 | as_warn (_("--generics is deprecated; use --transform instead")); | |
829 | return md_parse_option (option_transform, arg); | |
830 | case option_no_generics: | |
831 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
832 | return md_parse_option (option_no_transform, arg); | |
833 | case option_relax: | |
834 | as_warn (_("--relax is deprecated; use --transform instead")); | |
835 | return md_parse_option (option_transform, arg); | |
836 | case option_no_relax: | |
837 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
838 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
839 | case option_longcalls: |
840 | directive_state[directive_longcalls] = TRUE; | |
841 | return 1; | |
842 | case option_no_longcalls: | |
843 | directive_state[directive_longcalls] = FALSE; | |
844 | return 1; | |
845 | case option_text_section_literals: | |
846 | use_literal_section = FALSE; | |
847 | return 1; | |
848 | case option_no_text_section_literals: | |
849 | use_literal_section = TRUE; | |
850 | return 1; | |
43cd72b9 BW |
851 | case option_absolute_literals: |
852 | if (!absolute_literals_supported) | |
853 | { | |
854 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
855 | return 0; | |
856 | } | |
857 | directive_state[directive_absolute_literals] = TRUE; | |
858 | return 1; | |
859 | case option_no_absolute_literals: | |
860 | directive_state[directive_absolute_literals] = FALSE; | |
861 | return 1; | |
862 | ||
e0001a05 NC |
863 | case option_workaround_a0_b_retw: |
864 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
865 | return 1; |
866 | case option_no_workaround_a0_b_retw: | |
867 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
868 | return 1; |
869 | case option_workaround_b_j_loop_end: | |
870 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
871 | return 1; |
872 | case option_no_workaround_b_j_loop_end: | |
873 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
874 | return 1; |
875 | ||
876 | case option_workaround_short_loop: | |
877 | workaround_short_loop = TRUE; | |
e0001a05 NC |
878 | return 1; |
879 | case option_no_workaround_short_loop: | |
880 | workaround_short_loop = FALSE; | |
e0001a05 NC |
881 | return 1; |
882 | ||
883 | case option_workaround_all_short_loops: | |
884 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
885 | return 1; |
886 | case option_no_workaround_all_short_loops: | |
887 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
888 | return 1; |
889 | ||
890 | case option_workaround_close_loop_end: | |
891 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
892 | return 1; |
893 | case option_no_workaround_close_loop_end: | |
894 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
895 | return 1; |
896 | ||
897 | case option_no_workarounds: | |
898 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 899 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 900 | workaround_short_loop = FALSE; |
e0001a05 | 901 | workaround_all_short_loops = FALSE; |
e0001a05 | 902 | workaround_close_loop_end = FALSE; |
e0001a05 | 903 | return 1; |
43cd72b9 | 904 | |
e0001a05 NC |
905 | case option_align_targets: |
906 | align_targets = TRUE; | |
907 | return 1; | |
908 | case option_no_align_targets: | |
909 | align_targets = FALSE; | |
910 | return 1; | |
911 | ||
43cd72b9 BW |
912 | case option_warn_unaligned_targets: |
913 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
914 | return 1; |
915 | ||
e0001a05 NC |
916 | case option_rename_section_name: |
917 | build_section_rename (arg); | |
918 | return 1; | |
e0001a05 NC |
919 | |
920 | case 'Q': | |
921 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
922 | should be emitted or not. FIXME: Not implemented. */ | |
923 | return 1; | |
c138bc38 | 924 | |
43cd72b9 BW |
925 | case option_prefer_l32r: |
926 | if (prefer_const16) | |
927 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
928 | prefer_l32r = 1; | |
929 | return 1; | |
930 | ||
931 | case option_prefer_const16: | |
932 | if (prefer_l32r) | |
933 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
934 | prefer_const16 = 1; | |
935 | return 1; | |
936 | ||
c138bc38 | 937 | case option_target_hardware: |
43cd72b9 BW |
938 | { |
939 | int earliest, latest = 0; | |
17b9d67d | 940 | char *end; |
43cd72b9 BW |
941 | if (*arg == 0 || *arg == '-') |
942 | as_fatal (_("invalid target hardware version")); | |
943 | ||
17b9d67d | 944 | earliest = strtol (arg, &end, 0); |
43cd72b9 | 945 | |
17b9d67d | 946 | if (*end == 0) |
43cd72b9 | 947 | latest = earliest; |
17b9d67d | 948 | else if (*end == '-') |
43cd72b9 | 949 | { |
17b9d67d | 950 | if (*++end == 0) |
43cd72b9 | 951 | as_fatal (_("invalid target hardware version")); |
17b9d67d | 952 | latest = strtol (end, &end, 0); |
43cd72b9 | 953 | } |
17b9d67d | 954 | if (*end != 0) |
43cd72b9 BW |
955 | as_fatal (_("invalid target hardware version")); |
956 | ||
957 | xtensa_setup_hw_workarounds (earliest, latest); | |
958 | return 1; | |
959 | } | |
960 | ||
961 | case option_transform: | |
962 | /* This option has no affect other than to use the defaults, | |
963 | which are already set. */ | |
964 | return 1; | |
965 | ||
966 | case option_no_transform: | |
967 | /* This option turns off all transformations of any kind. | |
968 | However, because we want to preserve the state of other | |
969 | directives, we only change its own field. Thus, before | |
970 | you perform any transformation, always check if transform | |
971 | is available. If you use the functions we provide for this | |
972 | purpose, you will be ok. */ | |
973 | directive_state[directive_transform] = FALSE; | |
974 | return 1; | |
975 | ||
a82c7d90 DW |
976 | case option_trampolines: |
977 | use_trampolines = TRUE; | |
978 | return 1; | |
979 | ||
980 | case option_no_trampolines: | |
981 | use_trampolines = FALSE; | |
982 | return 1; | |
983 | ||
b46824bd MF |
984 | case option_auto_litpools: |
985 | auto_litpools = TRUE; | |
986 | use_literal_section = FALSE; | |
987 | return 1; | |
988 | ||
989 | case option_no_auto_litpools: | |
990 | auto_litpools = FALSE; | |
991 | auto_litpool_limit = -1; | |
992 | return 1; | |
993 | ||
994 | case option_auto_litpool_limit: | |
995 | { | |
996 | int value = 0; | |
17b9d67d | 997 | char *end; |
b46824bd MF |
998 | if (auto_litpool_limit < 0) |
999 | as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit")); | |
1000 | if (*arg == 0 || *arg == '-') | |
1001 | as_fatal (_("invalid auto-litpool-limit argument")); | |
17b9d67d TS |
1002 | value = strtol (arg, &end, 10); |
1003 | if (*end != 0) | |
b46824bd MF |
1004 | as_fatal (_("invalid auto-litpool-limit argument")); |
1005 | if (value < 100 || value > 10000) | |
1006 | as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)")); | |
1007 | auto_litpool_limit = value; | |
1008 | auto_litpools = TRUE; | |
1009 | use_literal_section = FALSE; | |
1010 | return 1; | |
1011 | } | |
1012 | ||
e0001a05 NC |
1013 | default: |
1014 | return 0; | |
1015 | } | |
1016 | } | |
1017 | ||
1018 | ||
1019 | void | |
7fa3d080 | 1020 | md_show_usage (FILE *stream) |
e0001a05 | 1021 | { |
43cd72b9 BW |
1022 | fputs ("\n\ |
1023 | Xtensa options:\n\ | |
9456465c BW |
1024 | --[no-]text-section-literals\n\ |
1025 | [Do not] put literals in the text section\n\ | |
1026 | --[no-]absolute-literals\n\ | |
1027 | [Do not] default to use non-PC-relative literals\n\ | |
1028 | --[no-]target-align [Do not] try to align branch targets\n\ | |
1029 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
1030 | --[no-]transform [Do not] transform instructions\n\ | |
19fc3723 SA |
1031 | --flix both allow hand-written and generate flix bundles\n\ |
1032 | --no-generate-flix allow hand-written but do not generate\n\ | |
1033 | flix bundles\n\ | |
1034 | --no-allow-flix neither allow hand-written nor generate\n\ | |
1035 | flix bundles\n\ | |
a82c7d90 DW |
1036 | --rename-section old=new Rename section 'old' to 'new'\n\ |
1037 | --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\ | |
b46824bd MF |
1038 | when jumps do not reach their targets\n\ |
1039 | --[no-]auto-litpools [Do not] automatically create literal pools\n\ | |
1040 | --auto-litpool-limit=<value>\n\ | |
1041 | (range 100-10000) Maximum number of blocks of\n\ | |
1042 | instructions to emit between literal pool\n\ | |
1043 | locations; implies --auto-litpools flag\n", stream); | |
e0001a05 NC |
1044 | } |
1045 | ||
7fa3d080 BW |
1046 | \f |
1047 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
1048 | |
1049 | static void | |
7fa3d080 | 1050 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 1051 | { |
7fa3d080 | 1052 | sym_list *l; |
43cd72b9 | 1053 | |
7fa3d080 | 1054 | if (!free_insn_labels) |
325801bd | 1055 | l = XNEW (sym_list); |
7fa3d080 | 1056 | else |
43cd72b9 | 1057 | { |
7fa3d080 BW |
1058 | l = free_insn_labels; |
1059 | free_insn_labels = l->next; | |
1060 | } | |
1061 | ||
1062 | l->sym = sym; | |
1063 | l->next = insn_labels; | |
1064 | insn_labels = l; | |
1065 | } | |
1066 | ||
1067 | ||
1068 | static void | |
1069 | xtensa_clear_insn_labels (void) | |
1070 | { | |
1071 | sym_list **pl; | |
1072 | ||
1073 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1074 | ; | |
1075 | *pl = insn_labels; | |
1076 | insn_labels = NULL; | |
1077 | } | |
1078 | ||
1079 | ||
7fa3d080 | 1080 | static void |
c3ea6048 | 1081 | xtensa_move_labels (fragS *new_frag, valueT new_offset) |
7fa3d080 BW |
1082 | { |
1083 | sym_list *lit; | |
1084 | ||
1085 | for (lit = insn_labels; lit; lit = lit->next) | |
1086 | { | |
1087 | symbolS *lit_sym = lit->sym; | |
c3ea6048 BW |
1088 | S_SET_VALUE (lit_sym, new_offset); |
1089 | symbol_set_frag (lit_sym, new_frag); | |
43cd72b9 BW |
1090 | } |
1091 | } | |
1092 | ||
e0001a05 NC |
1093 | \f |
1094 | /* Directive data and functions. */ | |
1095 | ||
1096 | typedef struct state_stackS_struct | |
1097 | { | |
1098 | directiveE directive; | |
1099 | bfd_boolean negated; | |
1100 | bfd_boolean old_state; | |
1101 | const char *file; | |
1102 | unsigned int line; | |
1103 | const void *datum; | |
1104 | struct state_stackS_struct *prev; | |
1105 | } state_stackS; | |
1106 | ||
1107 | state_stackS *directive_state_stack; | |
1108 | ||
1109 | const pseudo_typeS md_pseudo_table[] = | |
1110 | { | |
43cd72b9 BW |
1111 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1112 | { "literal_position", xtensa_literal_position, 0 }, | |
1113 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1114 | { "long", xtensa_elf_cons, 4 }, | |
1115 | { "word", xtensa_elf_cons, 4 }, | |
1bbb5f21 | 1116 | { "4byte", xtensa_elf_cons, 4 }, |
43cd72b9 | 1117 | { "short", xtensa_elf_cons, 2 }, |
1bbb5f21 | 1118 | { "2byte", xtensa_elf_cons, 2 }, |
fb227da0 BW |
1119 | { "sleb128", xtensa_leb128, 1}, |
1120 | { "uleb128", xtensa_leb128, 0}, | |
43cd72b9 BW |
1121 | { "begin", xtensa_begin_directive, 0 }, |
1122 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1123 | { "literal", xtensa_literal_pseudo, 0 }, |
1124 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1125 | { NULL, 0, 0 }, | |
e0001a05 NC |
1126 | }; |
1127 | ||
1128 | ||
7fa3d080 BW |
1129 | static bfd_boolean |
1130 | use_transform (void) | |
e0001a05 | 1131 | { |
43cd72b9 BW |
1132 | /* After md_end, you should be checking frag by frag, rather |
1133 | than state directives. */ | |
9c2799c2 | 1134 | gas_assert (!past_xtensa_end); |
43cd72b9 | 1135 | return directive_state[directive_transform]; |
e0001a05 NC |
1136 | } |
1137 | ||
1138 | ||
7fa3d080 BW |
1139 | static bfd_boolean |
1140 | do_align_targets (void) | |
e0001a05 | 1141 | { |
7b1cc377 BW |
1142 | /* Do not use this function after md_end; just look at align_targets |
1143 | instead. There is no target-align directive, so alignment is either | |
1144 | enabled for all frags or not done at all. */ | |
9c2799c2 | 1145 | gas_assert (!past_xtensa_end); |
43cd72b9 | 1146 | return align_targets && use_transform (); |
e0001a05 NC |
1147 | } |
1148 | ||
1149 | ||
1150 | static void | |
7fa3d080 | 1151 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 | 1152 | { |
3b4dbbbf | 1153 | const char *file; |
e0001a05 | 1154 | unsigned int line; |
325801bd | 1155 | state_stackS *stack = XNEW (state_stackS); |
e0001a05 | 1156 | |
3b4dbbbf | 1157 | file = as_where (&line); |
e0001a05 NC |
1158 | |
1159 | stack->directive = directive; | |
1160 | stack->negated = negated; | |
1161 | stack->old_state = directive_state[directive]; | |
1162 | stack->file = file; | |
1163 | stack->line = line; | |
1164 | stack->datum = datum; | |
1165 | stack->prev = directive_state_stack; | |
1166 | directive_state_stack = stack; | |
1167 | ||
1168 | directive_state[directive] = !negated; | |
1169 | } | |
1170 | ||
7fa3d080 | 1171 | |
e0001a05 | 1172 | static void |
7fa3d080 BW |
1173 | directive_pop (directiveE *directive, |
1174 | bfd_boolean *negated, | |
1175 | const char **file, | |
1176 | unsigned int *line, | |
1177 | const void **datum) | |
e0001a05 NC |
1178 | { |
1179 | state_stackS *top = directive_state_stack; | |
1180 | ||
1181 | if (!directive_state_stack) | |
1182 | { | |
33eaf5de | 1183 | as_bad (_("unmatched .end directive")); |
e0001a05 NC |
1184 | *directive = directive_none; |
1185 | return; | |
1186 | } | |
1187 | ||
1188 | directive_state[directive_state_stack->directive] = top->old_state; | |
1189 | *directive = top->directive; | |
1190 | *negated = top->negated; | |
1191 | *file = top->file; | |
1192 | *line = top->line; | |
1193 | *datum = top->datum; | |
1194 | directive_state_stack = top->prev; | |
1195 | free (top); | |
1196 | } | |
1197 | ||
1198 | ||
1199 | static void | |
7fa3d080 | 1200 | directive_balance (void) |
e0001a05 NC |
1201 | { |
1202 | while (directive_state_stack) | |
1203 | { | |
1204 | directiveE directive; | |
1205 | bfd_boolean negated; | |
1206 | const char *file; | |
1207 | unsigned int line; | |
1208 | const void *datum; | |
1209 | ||
1210 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1211 | as_warn_where ((char *) file, line, | |
1212 | _(".begin directive with no matching .end directive")); | |
1213 | } | |
1214 | } | |
1215 | ||
1216 | ||
1217 | static bfd_boolean | |
7fa3d080 | 1218 | inside_directive (directiveE dir) |
e0001a05 NC |
1219 | { |
1220 | state_stackS *top = directive_state_stack; | |
1221 | ||
1222 | while (top && top->directive != dir) | |
1223 | top = top->prev; | |
1224 | ||
1225 | return (top != NULL); | |
1226 | } | |
1227 | ||
1228 | ||
1229 | static void | |
7fa3d080 | 1230 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1231 | { |
1232 | int len; | |
1233 | unsigned i; | |
b9bb4a93 | 1234 | const char *directive_string; |
e0001a05 NC |
1235 | |
1236 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1237 | *negated = FALSE; | |
1238 | else | |
1239 | { | |
1240 | *negated = TRUE; | |
1241 | input_line_pointer += 3; | |
1242 | } | |
1243 | ||
1244 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1245 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1246 | ||
1247 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1248 | equivalent to .begin [no-]transform. We should remove it when | |
1249 | we stop accepting those options. */ | |
c138bc38 | 1250 | |
43cd72b9 BW |
1251 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1252 | { | |
1253 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1254 | directive_string = "transform"; | |
1255 | } | |
1256 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1257 | { | |
1258 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1259 | directive_string = "transform"; | |
c138bc38 | 1260 | } |
43cd72b9 BW |
1261 | else |
1262 | directive_string = input_line_pointer; | |
e0001a05 NC |
1263 | |
1264 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1265 | { | |
43cd72b9 | 1266 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1267 | { |
1268 | input_line_pointer += len; | |
1269 | *directive = (directiveE) i; | |
1270 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1271 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1272 | directive_info[i].name); |
1273 | return; | |
1274 | } | |
1275 | } | |
1276 | ||
1277 | as_bad (_("unknown directive")); | |
1278 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1279 | } | |
1280 | ||
1281 | ||
1282 | static void | |
7fa3d080 | 1283 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1284 | { |
1285 | directiveE directive; | |
1286 | bfd_boolean negated; | |
1287 | emit_state *state; | |
e0001a05 NC |
1288 | lit_state *ls; |
1289 | ||
1290 | get_directive (&directive, &negated); | |
1291 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1292 | { | |
1293 | discard_rest_of_line (); | |
1294 | return; | |
1295 | } | |
1296 | ||
43cd72b9 BW |
1297 | if (cur_vinsn.inside_bundle) |
1298 | as_bad (_("directives are not valid inside bundles")); | |
1299 | ||
e0001a05 NC |
1300 | switch (directive) |
1301 | { | |
1302 | case directive_literal: | |
82e7541d BW |
1303 | if (!inside_directive (directive_literal)) |
1304 | { | |
1305 | /* Previous labels go with whatever follows this directive, not with | |
1306 | the literal, so save them now. */ | |
1307 | saved_insn_labels = insn_labels; | |
1308 | insn_labels = NULL; | |
1309 | } | |
43cd72b9 | 1310 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
325801bd | 1311 | state = XNEW (emit_state); |
e0001a05 NC |
1312 | xtensa_switch_to_literal_fragment (state); |
1313 | directive_push (directive_literal, negated, state); | |
1314 | break; | |
1315 | ||
1316 | case directive_literal_prefix: | |
c138bc38 | 1317 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1318 | might produce a literal. */ |
1319 | md_flush_pending_output (); | |
e0001a05 NC |
1320 | /* Check to see if the current fragment is a literal |
1321 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1322 | if (generating_literals) |
e0001a05 NC |
1323 | { |
1324 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1325 | return; | |
1326 | } | |
1327 | ||
1328 | /* Allocate the literal state for this section and push | |
1329 | onto the directive stack. */ | |
325801bd | 1330 | ls = XNEW (lit_state); |
9c2799c2 | 1331 | gas_assert (ls); |
e0001a05 NC |
1332 | |
1333 | *ls = default_lit_sections; | |
e0001a05 NC |
1334 | directive_push (directive_literal_prefix, negated, ls); |
1335 | ||
e0001a05 | 1336 | /* Process the new prefix. */ |
74869ac7 | 1337 | xtensa_literal_prefix (); |
e0001a05 NC |
1338 | break; |
1339 | ||
1340 | case directive_freeregs: | |
1341 | /* This information is currently unused, but we'll accept the statement | |
1342 | and just discard the rest of the line. This won't check the syntax, | |
1343 | but it will accept every correct freeregs directive. */ | |
1344 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1345 | directive_push (directive_freeregs, negated, 0); | |
1346 | break; | |
1347 | ||
43cd72b9 BW |
1348 | case directive_schedule: |
1349 | md_flush_pending_output (); | |
1350 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1351 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1352 | directive_push (directive_schedule, negated, 0); | |
1353 | xtensa_set_frag_assembly_state (frag_now); | |
1354 | break; | |
1355 | ||
e0001a05 | 1356 | case directive_density: |
43cd72b9 BW |
1357 | as_warn (_(".begin [no-]density is ignored")); |
1358 | break; | |
1359 | ||
1360 | case directive_absolute_literals: | |
1361 | md_flush_pending_output (); | |
1362 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1363 | { |
43cd72b9 | 1364 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1365 | break; |
1366 | } | |
43cd72b9 BW |
1367 | xtensa_set_frag_assembly_state (frag_now); |
1368 | directive_push (directive, negated, 0); | |
1369 | break; | |
e0001a05 NC |
1370 | |
1371 | default: | |
43cd72b9 BW |
1372 | md_flush_pending_output (); |
1373 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1374 | directive_push (directive, negated, 0); |
1375 | break; | |
1376 | } | |
1377 | ||
1378 | demand_empty_rest_of_line (); | |
1379 | } | |
1380 | ||
1381 | ||
1382 | static void | |
7fa3d080 | 1383 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1384 | { |
1385 | directiveE begin_directive, end_directive; | |
1386 | bfd_boolean begin_negated, end_negated; | |
1387 | const char *file; | |
1388 | unsigned int line; | |
1389 | emit_state *state; | |
43cd72b9 | 1390 | emit_state **state_ptr; |
e0001a05 NC |
1391 | lit_state *s; |
1392 | ||
43cd72b9 BW |
1393 | if (cur_vinsn.inside_bundle) |
1394 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1395 | |
e0001a05 | 1396 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1397 | |
1398 | md_flush_pending_output (); | |
1399 | ||
87975d2a | 1400 | switch ((int) end_directive) |
e0001a05 | 1401 | { |
87975d2a | 1402 | case XTENSA_UNDEFINED: |
e0001a05 NC |
1403 | discard_rest_of_line (); |
1404 | return; | |
e0001a05 | 1405 | |
87975d2a | 1406 | case (int) directive_density: |
43cd72b9 | 1407 | as_warn (_(".end [no-]density is ignored")); |
e0001a05 | 1408 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1409 | break; |
1410 | ||
87975d2a | 1411 | case (int) directive_absolute_literals: |
43cd72b9 BW |
1412 | if (!absolute_literals_supported && !end_negated) |
1413 | { | |
1414 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1415 | demand_empty_rest_of_line (); | |
1416 | return; | |
1417 | } | |
1418 | break; | |
1419 | ||
1420 | default: | |
1421 | break; | |
e0001a05 NC |
1422 | } |
1423 | ||
43cd72b9 | 1424 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1425 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1426 | (const void **) state_ptr); |
e0001a05 NC |
1427 | |
1428 | if (begin_directive != directive_none) | |
1429 | { | |
1430 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1431 | { | |
1432 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1433 | begin_negated ? "no-" : "", | |
1434 | directive_info[begin_directive].name, file, line); | |
1435 | } | |
1436 | else | |
1437 | { | |
1438 | switch (end_directive) | |
1439 | { | |
1440 | case directive_literal: | |
1441 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1442 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1443 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1444 | free (state); |
82e7541d BW |
1445 | if (!inside_directive (directive_literal)) |
1446 | { | |
1447 | /* Restore the list of current labels. */ | |
1448 | xtensa_clear_insn_labels (); | |
1449 | insn_labels = saved_insn_labels; | |
1450 | } | |
e0001a05 NC |
1451 | break; |
1452 | ||
e0001a05 NC |
1453 | case directive_literal_prefix: |
1454 | /* Restore the default collection sections from saved state. */ | |
1455 | s = (lit_state *) state; | |
9c2799c2 | 1456 | gas_assert (s); |
e8247da7 | 1457 | default_lit_sections = *s; |
e0001a05 | 1458 | |
74869ac7 BW |
1459 | /* Free the state storage. */ |
1460 | free (s->lit_prefix); | |
e0001a05 NC |
1461 | free (s); |
1462 | break; | |
1463 | ||
43cd72b9 BW |
1464 | case directive_schedule: |
1465 | case directive_freeregs: | |
1466 | break; | |
1467 | ||
e0001a05 | 1468 | default: |
43cd72b9 | 1469 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1470 | break; |
1471 | } | |
1472 | } | |
1473 | } | |
1474 | ||
1475 | demand_empty_rest_of_line (); | |
1476 | } | |
1477 | ||
1478 | ||
1479 | /* Place an aligned literal fragment at the current location. */ | |
1480 | ||
1481 | static void | |
7fa3d080 | 1482 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1483 | { |
43cd72b9 BW |
1484 | md_flush_pending_output (); |
1485 | ||
e0001a05 NC |
1486 | if (inside_directive (directive_literal)) |
1487 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1488 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1489 | |
1490 | demand_empty_rest_of_line (); | |
82e7541d | 1491 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1492 | } |
1493 | ||
1494 | ||
43cd72b9 | 1495 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1496 | |
1497 | static void | |
7fa3d080 | 1498 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1499 | { |
1500 | emit_state state; | |
1745fcba | 1501 | char *p, *base_name; |
e0001a05 | 1502 | char c; |
e0001a05 NC |
1503 | segT dest_seg; |
1504 | ||
82e7541d BW |
1505 | if (inside_directive (directive_literal)) |
1506 | { | |
1507 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1508 | ignore_rest_of_line (); | |
1509 | return; | |
1510 | } | |
1511 | ||
43cd72b9 BW |
1512 | md_flush_pending_output (); |
1513 | ||
82e7541d BW |
1514 | /* Previous labels go with whatever follows this directive, not with |
1515 | the literal, so save them now. */ | |
1516 | saved_insn_labels = insn_labels; | |
1517 | insn_labels = NULL; | |
1518 | ||
e0001a05 NC |
1519 | /* If we are using text-section literals, then this is the right value... */ |
1520 | dest_seg = now_seg; | |
1521 | ||
1522 | base_name = input_line_pointer; | |
1523 | ||
1524 | xtensa_switch_to_literal_fragment (&state); | |
1525 | ||
43cd72b9 | 1526 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1527 | need to put them in the section we just switched to. */ |
43cd72b9 | 1528 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1529 | dest_seg = now_seg; |
1530 | ||
87975d2a AM |
1531 | /* FIXME, despite the previous comments, dest_seg is unused... */ |
1532 | (void) dest_seg; | |
1533 | ||
43cd72b9 BW |
1534 | /* All literals are aligned to four-byte boundaries. */ |
1535 | frag_align (2, 0, 0); | |
1536 | record_alignment (now_seg, 2); | |
e0001a05 | 1537 | |
d02603dc | 1538 | c = get_symbol_name (&base_name); |
e0001a05 NC |
1539 | /* Just after name is now '\0'. */ |
1540 | p = input_line_pointer; | |
1541 | *p = c; | |
d02603dc | 1542 | SKIP_WHITESPACE_AFTER_NAME (); |
e0001a05 NC |
1543 | |
1544 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1545 | { | |
1546 | as_bad (_("expected comma or colon after symbol name; " | |
1547 | "rest of line ignored")); | |
1548 | ignore_rest_of_line (); | |
1549 | xtensa_restore_emit_state (&state); | |
1550 | return; | |
1551 | } | |
e0001a05 | 1552 | |
d02603dc | 1553 | *p = 0; |
e0001a05 | 1554 | colon (base_name); |
e0001a05 | 1555 | *p = c; |
d02603dc | 1556 | |
43cd72b9 | 1557 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1558 | |
43cd72b9 | 1559 | xtensa_elf_cons (4); |
e0001a05 NC |
1560 | |
1561 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1562 | |
1563 | /* Restore the list of current labels. */ | |
1564 | xtensa_clear_insn_labels (); | |
1565 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1566 | } |
1567 | ||
1568 | ||
1569 | static void | |
74869ac7 | 1570 | xtensa_literal_prefix (void) |
e0001a05 | 1571 | { |
74869ac7 BW |
1572 | char *name; |
1573 | int len; | |
1574 | ||
1575 | /* Parse the new prefix from the input_line_pointer. */ | |
1576 | SKIP_WHITESPACE (); | |
1577 | len = strspn (input_line_pointer, | |
1578 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1579 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
e0001a05 NC |
1580 | |
1581 | /* Get a null-terminated copy of the name. */ | |
29a2809e | 1582 | name = xmemdup0 (input_line_pointer, len); |
e0001a05 | 1583 | |
74869ac7 BW |
1584 | /* Skip the name in the input line. */ |
1585 | input_line_pointer += len; | |
43cd72b9 | 1586 | |
74869ac7 | 1587 | default_lit_sections.lit_prefix = name; |
43cd72b9 | 1588 | |
74869ac7 | 1589 | /* Clear cached literal sections, since the prefix has changed. */ |
43cd72b9 BW |
1590 | default_lit_sections.lit_seg = NULL; |
1591 | default_lit_sections.lit4_seg = NULL; | |
43cd72b9 BW |
1592 | } |
1593 | ||
1594 | ||
1595 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1596 | ||
1597 | static void | |
7fa3d080 | 1598 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1599 | { |
1600 | float fall_through_f, target_f; | |
43cd72b9 BW |
1601 | |
1602 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1603 | if (fall_through_f < 0) | |
1604 | { | |
1605 | as_bad (_("fall through frequency must be greater than 0")); | |
1606 | ignore_rest_of_line (); | |
1607 | return; | |
1608 | } | |
1609 | ||
1610 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1611 | if (target_f < 0) | |
1612 | { | |
1613 | as_bad (_("branch target frequency must be greater than 0")); | |
1614 | ignore_rest_of_line (); | |
1615 | return; | |
1616 | } | |
1617 | ||
b08b5071 | 1618 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1619 | |
1620 | demand_empty_rest_of_line (); | |
1621 | } | |
1622 | ||
1623 | ||
1624 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1625 | Clobbers input_line_pointer, checks end-of-line. */ | |
1626 | ||
1627 | static void | |
7fa3d080 | 1628 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1629 | { |
1630 | expressionS exp; | |
1631 | bfd_reloc_code_real_type reloc; | |
1632 | ||
1633 | md_flush_pending_output (); | |
1634 | ||
1635 | if (cur_vinsn.inside_bundle) | |
1636 | as_bad (_("directives are not valid inside bundles")); | |
1637 | ||
1638 | if (is_it_end_of_statement ()) | |
1639 | { | |
1640 | demand_empty_rest_of_line (); | |
1641 | return; | |
1642 | } | |
1643 | ||
1644 | do | |
1645 | { | |
1646 | expression (&exp); | |
1647 | if (exp.X_op == O_symbol | |
1648 | && *input_line_pointer == '@' | |
1649 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1650 | != BFD_RELOC_NONE)) | |
1651 | { | |
1652 | reloc_howto_type *reloc_howto = | |
1653 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1654 | ||
1655 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1656 | as_bad (_("unsupported relocation")); | |
1657 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1658 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1659 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1660 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1661 | as_bad (_("opcode-specific %s relocation used outside " | |
1662 | "an instruction"), reloc_howto->name); | |
1663 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
992a06ee AM |
1664 | as_bad (ngettext ("%s relocations do not fit in %d byte", |
1665 | "%s relocations do not fit in %d bytes", | |
1666 | nbytes), | |
43cd72b9 | 1667 | reloc_howto->name, nbytes); |
28dbbc02 BW |
1668 | else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC |
1669 | || reloc == BFD_RELOC_XTENSA_TLS_ARG | |
1670 | || reloc == BFD_RELOC_XTENSA_TLS_CALL) | |
1671 | as_bad (_("invalid use of %s relocation"), reloc_howto->name); | |
43cd72b9 BW |
1672 | else |
1673 | { | |
1674 | char *p = frag_more ((int) nbytes); | |
1675 | xtensa_set_frag_assembly_state (frag_now); | |
1676 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 1677 | nbytes, &exp, reloc_howto->pc_relative, reloc); |
43cd72b9 BW |
1678 | } |
1679 | } | |
1680 | else | |
1f7efbae BW |
1681 | { |
1682 | xtensa_set_frag_assembly_state (frag_now); | |
1683 | emit_expr (&exp, (unsigned int) nbytes); | |
1684 | } | |
43cd72b9 BW |
1685 | } |
1686 | while (*input_line_pointer++ == ','); | |
1687 | ||
1688 | input_line_pointer--; /* Put terminator back into stream. */ | |
1689 | demand_empty_rest_of_line (); | |
1690 | } | |
1691 | ||
fb227da0 BW |
1692 | static bfd_boolean is_leb128_expr; |
1693 | ||
1694 | static void | |
1695 | xtensa_leb128 (int sign) | |
1696 | { | |
1697 | is_leb128_expr = TRUE; | |
1698 | s_leb128 (sign); | |
1699 | is_leb128_expr = FALSE; | |
1700 | } | |
1701 | ||
7fa3d080 BW |
1702 | \f |
1703 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1704 | |
1705 | /* Parse @plt, etc. and return the desired relocation. */ | |
1706 | static bfd_reloc_code_real_type | |
7fa3d080 | 1707 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 | 1708 | { |
43cd72b9 BW |
1709 | char ident[20]; |
1710 | char *str = *str_p; | |
1711 | char *str2; | |
1712 | int ch; | |
1713 | int len; | |
e066bf5f | 1714 | unsigned int i; |
43cd72b9 BW |
1715 | |
1716 | if (*str++ != '@') | |
1717 | return BFD_RELOC_NONE; | |
1718 | ||
1719 | for (ch = *str, str2 = ident; | |
1720 | (str2 < ident + sizeof (ident) - 1 | |
1721 | && (ISALNUM (ch) || ch == '@')); | |
1722 | ch = *++str) | |
1723 | { | |
1724 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1725 | } | |
1726 | ||
1727 | *str2 = '\0'; | |
1728 | len = str2 - ident; | |
1729 | ||
1730 | ch = ident[0]; | |
e066bf5f TS |
1731 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
1732 | if (ch == suffix_relocs[i].suffix[0] | |
1733 | && len == suffix_relocs[i].length | |
1734 | && memcmp (ident, suffix_relocs[i].suffix, suffix_relocs[i].length) == 0) | |
43cd72b9 BW |
1735 | { |
1736 | /* Now check for "identifier@suffix+constant". */ | |
1737 | if (*str == '-' || *str == '+') | |
1738 | { | |
1739 | char *orig_line = input_line_pointer; | |
1740 | expressionS new_exp; | |
1741 | ||
1742 | input_line_pointer = str; | |
1743 | expression (&new_exp); | |
1744 | if (new_exp.X_op == O_constant) | |
1745 | { | |
1746 | exp_p->X_add_number += new_exp.X_add_number; | |
1747 | str = input_line_pointer; | |
1748 | } | |
1749 | ||
1750 | if (&input_line_pointer != str_p) | |
1751 | input_line_pointer = orig_line; | |
1752 | } | |
1753 | ||
1754 | *str_p = str; | |
e066bf5f | 1755 | return suffix_relocs[i].reloc; |
43cd72b9 BW |
1756 | } |
1757 | ||
1758 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1759 | } |
1760 | ||
e0001a05 | 1761 | |
bbdd25a8 | 1762 | /* Find the matching operator type. */ |
cc34adb2 | 1763 | static operatorT |
bbdd25a8 BW |
1764 | map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) |
1765 | { | |
cc34adb2 | 1766 | operatorT operator = O_illegal; |
e066bf5f | 1767 | unsigned int i; |
3739860c | 1768 | |
e066bf5f | 1769 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
bbdd25a8 | 1770 | { |
e066bf5f | 1771 | if (suffix_relocs[i].reloc == reloc) |
bbdd25a8 | 1772 | { |
e066bf5f | 1773 | operator = suffix_relocs[i].operator; |
bbdd25a8 BW |
1774 | break; |
1775 | } | |
1776 | } | |
cc34adb2 | 1777 | gas_assert (operator != O_illegal); |
bbdd25a8 BW |
1778 | return operator; |
1779 | } | |
1780 | ||
1781 | ||
1782 | /* Find the matching reloc type. */ | |
1783 | static bfd_reloc_code_real_type | |
28dbbc02 | 1784 | map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal) |
bbdd25a8 | 1785 | { |
e066bf5f | 1786 | unsigned int i; |
bbdd25a8 BW |
1787 | bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; |
1788 | ||
e066bf5f | 1789 | for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) |
bbdd25a8 | 1790 | { |
e066bf5f | 1791 | if (suffix_relocs[i].operator == operator) |
bbdd25a8 | 1792 | { |
e066bf5f | 1793 | reloc = suffix_relocs[i].reloc; |
bbdd25a8 BW |
1794 | break; |
1795 | } | |
1796 | } | |
1797 | ||
28dbbc02 BW |
1798 | if (is_literal) |
1799 | { | |
1800 | if (reloc == BFD_RELOC_XTENSA_TLS_FUNC) | |
1801 | return BFD_RELOC_XTENSA_TLSDESC_FN; | |
1802 | else if (reloc == BFD_RELOC_XTENSA_TLS_ARG) | |
1803 | return BFD_RELOC_XTENSA_TLSDESC_ARG; | |
1804 | } | |
1805 | ||
bbdd25a8 BW |
1806 | if (reloc == BFD_RELOC_UNUSED) |
1807 | return BFD_RELOC_32; | |
1808 | ||
1809 | return reloc; | |
1810 | } | |
1811 | ||
1812 | ||
e0001a05 | 1813 | static const char * |
7fa3d080 | 1814 | expression_end (const char *name) |
e0001a05 NC |
1815 | { |
1816 | while (1) | |
1817 | { | |
1818 | switch (*name) | |
1819 | { | |
43cd72b9 | 1820 | case '}': |
e0001a05 NC |
1821 | case ';': |
1822 | case '\0': | |
1823 | case ',': | |
43cd72b9 | 1824 | case ':': |
e0001a05 NC |
1825 | return name; |
1826 | case ' ': | |
1827 | case '\t': | |
1828 | ++name; | |
1829 | continue; | |
1830 | default: | |
1831 | return 0; | |
1832 | } | |
1833 | } | |
1834 | } | |
1835 | ||
1836 | ||
1837 | #define ERROR_REG_NUM ((unsigned) -1) | |
1838 | ||
1839 | static unsigned | |
7fa3d080 | 1840 | tc_get_register (const char *prefix) |
e0001a05 NC |
1841 | { |
1842 | unsigned reg; | |
1843 | const char *next_expr; | |
1844 | const char *old_line_pointer; | |
1845 | ||
1846 | SKIP_WHITESPACE (); | |
1847 | old_line_pointer = input_line_pointer; | |
1848 | ||
1849 | if (*input_line_pointer == '$') | |
1850 | ++input_line_pointer; | |
1851 | ||
1852 | /* Accept "sp" as a synonym for "a1". */ | |
1853 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1854 | && expression_end (input_line_pointer + 2)) | |
1855 | { | |
1856 | input_line_pointer += 2; | |
1857 | return 1; /* AR[1] */ | |
1858 | } | |
1859 | ||
1860 | while (*input_line_pointer++ == *prefix++) | |
1861 | ; | |
1862 | --input_line_pointer; | |
1863 | --prefix; | |
1864 | ||
1865 | if (*prefix) | |
1866 | { | |
1867 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1868 | return ERROR_REG_NUM; | |
1869 | } | |
1870 | ||
1871 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1872 | { | |
1873 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1874 | return ERROR_REG_NUM; | |
1875 | } | |
1876 | ||
1877 | reg = 0; | |
1878 | ||
1879 | while (ISDIGIT ((int) *input_line_pointer)) | |
1880 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1881 | ||
1882 | if (!(next_expr = expression_end (input_line_pointer))) | |
1883 | { | |
1884 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1885 | return ERROR_REG_NUM; | |
1886 | } | |
1887 | ||
1888 | input_line_pointer = (char *) next_expr; | |
1889 | ||
1890 | return reg; | |
1891 | } | |
1892 | ||
1893 | ||
e0001a05 | 1894 | static void |
7fa3d080 | 1895 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1896 | { |
43cd72b9 | 1897 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1898 | |
43cd72b9 BW |
1899 | /* Check if this is an immediate operand. */ |
1900 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1901 | { |
43cd72b9 | 1902 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1903 | segT t = expression (tok); |
91d6fa6a | 1904 | |
43cd72b9 BW |
1905 | if (t == absolute_section |
1906 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 | 1907 | { |
9c2799c2 | 1908 | gas_assert (tok->X_op == O_constant); |
e0001a05 NC |
1909 | tok->X_op = O_symbol; |
1910 | tok->X_add_symbol = &abs_symbol; | |
1911 | } | |
43cd72b9 BW |
1912 | |
1913 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
bbdd25a8 BW |
1914 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) |
1915 | != BFD_RELOC_NONE)) | |
e0001a05 | 1916 | { |
1bbb5f21 | 1917 | switch (reloc) |
43cd72b9 | 1918 | { |
1bbb5f21 BW |
1919 | case BFD_RELOC_LO16: |
1920 | if (tok->X_op == O_constant) | |
bbdd25a8 | 1921 | { |
43cd72b9 | 1922 | tok->X_add_number &= 0xffff; |
bbdd25a8 | 1923 | return; |
1bbb5f21 BW |
1924 | } |
1925 | break; | |
1926 | case BFD_RELOC_HI16: | |
1927 | if (tok->X_op == O_constant) | |
1928 | { | |
43cd72b9 | 1929 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; |
bbdd25a8 | 1930 | return; |
bbdd25a8 | 1931 | } |
1bbb5f21 BW |
1932 | break; |
1933 | case BFD_RELOC_UNUSED: | |
1934 | as_bad (_("unsupported relocation")); | |
1935 | return; | |
1936 | case BFD_RELOC_32_PCREL: | |
1937 | as_bad (_("pcrel relocation not allowed in an instruction")); | |
1938 | return; | |
1939 | default: | |
1940 | break; | |
43cd72b9 | 1941 | } |
bbdd25a8 | 1942 | tok->X_op = map_suffix_reloc_to_operator (reloc); |
e0001a05 | 1943 | } |
e0001a05 NC |
1944 | } |
1945 | else | |
1946 | { | |
43cd72b9 BW |
1947 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1948 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1949 | |
1950 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1951 | { | |
1952 | uint32 buf = reg; | |
43cd72b9 | 1953 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1954 | as_bad (_("register number out of range")); |
1955 | } | |
1956 | ||
1957 | tok->X_op = O_register; | |
1958 | tok->X_add_symbol = 0; | |
1959 | tok->X_add_number = reg; | |
1960 | } | |
1961 | } | |
1962 | ||
1963 | ||
1964 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1965 | ||
1966 | static int | |
7fa3d080 | 1967 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1968 | { |
1969 | char *old_input_line_pointer; | |
1970 | bfd_boolean saw_comma = FALSE; | |
1971 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1972 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1973 | int num_args = 0; |
1974 | char *arg_end, *arg; | |
1975 | int arg_len; | |
43cd72b9 BW |
1976 | |
1977 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1978 | old_input_line_pointer = input_line_pointer; |
1979 | input_line_pointer = str; | |
1980 | ||
1981 | while (*input_line_pointer) | |
1982 | { | |
1983 | SKIP_WHITESPACE (); | |
1984 | switch (*input_line_pointer) | |
1985 | { | |
1986 | case '\0': | |
43cd72b9 | 1987 | case '}': |
e0001a05 NC |
1988 | goto fini; |
1989 | ||
43cd72b9 BW |
1990 | case ':': |
1991 | input_line_pointer++; | |
1992 | if (saw_comma || saw_colon || !saw_arg) | |
1993 | goto err; | |
1994 | saw_colon = TRUE; | |
1995 | break; | |
1996 | ||
e0001a05 NC |
1997 | case ',': |
1998 | input_line_pointer++; | |
43cd72b9 | 1999 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
2000 | goto err; |
2001 | saw_comma = TRUE; | |
2002 | break; | |
2003 | ||
2004 | default: | |
43cd72b9 | 2005 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
2006 | goto err; |
2007 | ||
2008 | arg_end = input_line_pointer + 1; | |
2009 | while (!expression_end (arg_end)) | |
2010 | arg_end += 1; | |
43cd72b9 | 2011 | |
e0001a05 | 2012 | arg_len = arg_end - input_line_pointer; |
325801bd | 2013 | arg = XNEWVEC (char, (saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
2014 | args[num_args] = arg; |
2015 | ||
43cd72b9 BW |
2016 | if (saw_colon) |
2017 | *arg++ = ':'; | |
e0001a05 NC |
2018 | strncpy (arg, input_line_pointer, arg_len); |
2019 | arg[arg_len] = '\0'; | |
43cd72b9 | 2020 | |
e0001a05 NC |
2021 | input_line_pointer = arg_end; |
2022 | num_args += 1; | |
c138bc38 | 2023 | saw_comma = FALSE; |
43cd72b9 | 2024 | saw_colon = FALSE; |
c138bc38 | 2025 | saw_arg = TRUE; |
e0001a05 NC |
2026 | break; |
2027 | } | |
2028 | } | |
2029 | ||
2030 | fini: | |
43cd72b9 | 2031 | if (saw_comma || saw_colon) |
e0001a05 NC |
2032 | goto err; |
2033 | input_line_pointer = old_input_line_pointer; | |
2034 | return num_args; | |
2035 | ||
2036 | err: | |
43cd72b9 BW |
2037 | if (saw_comma) |
2038 | as_bad (_("extra comma")); | |
2039 | else if (saw_colon) | |
2040 | as_bad (_("extra colon")); | |
2041 | else if (!saw_arg) | |
c138bc38 | 2042 | as_bad (_("missing argument")); |
43cd72b9 BW |
2043 | else |
2044 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
2045 | input_line_pointer = old_input_line_pointer; |
2046 | return -1; | |
2047 | } | |
2048 | ||
2049 | ||
43cd72b9 | 2050 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
2051 | |
2052 | static bfd_boolean | |
7fa3d080 | 2053 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 2054 | { |
43cd72b9 | 2055 | expressionS *tok, *last_tok; |
e0001a05 NC |
2056 | xtensa_opcode opcode = insn->opcode; |
2057 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
2058 | xtensa_isa isa = xtensa_default_isa; |
2059 | int n, num_regs = 0; | |
e0001a05 | 2060 | int opcode_operand_count; |
43cd72b9 BW |
2061 | int opnd_cnt, last_opnd_cnt; |
2062 | unsigned int next_reg = 0; | |
e0001a05 NC |
2063 | char *old_input_line_pointer; |
2064 | ||
2065 | if (insn->insn_type == ITYPE_LITERAL) | |
2066 | opcode_operand_count = 1; | |
2067 | else | |
43cd72b9 | 2068 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 2069 | |
43cd72b9 | 2070 | tok = insn->tok; |
e0001a05 NC |
2071 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
2072 | ||
2073 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
2074 | old_input_line_pointer = input_line_pointer; |
2075 | ||
2076 | last_tok = 0; | |
2077 | last_opnd_cnt = -1; | |
2078 | opnd_cnt = 0; | |
2079 | ||
2080 | /* Skip invisible operands. */ | |
2081 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
2082 | { | |
2083 | opnd_cnt += 1; | |
2084 | tok++; | |
2085 | } | |
e0001a05 NC |
2086 | |
2087 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 2088 | { |
e0001a05 | 2089 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
2090 | if (*input_line_pointer == ':') |
2091 | { | |
2092 | xtensa_regfile opnd_rf; | |
2093 | input_line_pointer++; | |
2094 | if (num_regs == 0) | |
2095 | goto err; | |
9c2799c2 | 2096 | gas_assert (opnd_cnt > 0); |
43cd72b9 BW |
2097 | num_regs--; |
2098 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
2099 | if (next_reg | |
2100 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
2101 | as_warn (_("incorrect register number, ignoring")); | |
2102 | next_reg++; | |
2103 | } | |
2104 | else | |
2105 | { | |
2106 | if (opnd_cnt >= opcode_operand_count) | |
2107 | { | |
2108 | as_warn (_("too many arguments")); | |
2109 | goto err; | |
2110 | } | |
9c2799c2 | 2111 | gas_assert (opnd_cnt < MAX_INSN_ARGS); |
43cd72b9 BW |
2112 | |
2113 | expression_maybe_register (opcode, opnd_cnt, tok); | |
2114 | next_reg = tok->X_add_number + 1; | |
2115 | ||
2116 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
2117 | goto err; | |
2118 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
2119 | { | |
2120 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
2121 | /* minus 1 because we are seeing one right now */ | |
2122 | } | |
2123 | else | |
2124 | num_regs = 0; | |
e0001a05 | 2125 | |
43cd72b9 BW |
2126 | last_tok = tok; |
2127 | last_opnd_cnt = opnd_cnt; | |
1ec520b7 | 2128 | demand_empty_rest_of_line (); |
e0001a05 | 2129 | |
43cd72b9 BW |
2130 | do |
2131 | { | |
2132 | opnd_cnt += 1; | |
2133 | tok++; | |
2134 | } | |
2135 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
2136 | } | |
2137 | } | |
e0001a05 | 2138 | |
43cd72b9 BW |
2139 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
2140 | goto err; | |
e0001a05 NC |
2141 | |
2142 | insn->ntok = tok - insn->tok; | |
c138bc38 | 2143 | had_error = FALSE; |
e0001a05 NC |
2144 | |
2145 | err: | |
43cd72b9 | 2146 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2147 | return had_error; |
2148 | } | |
2149 | ||
2150 | ||
43cd72b9 | 2151 | static int |
7fa3d080 | 2152 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2153 | { |
2154 | xtensa_isa isa = xtensa_default_isa; | |
2155 | static xtensa_insnbuf slotbuf = NULL; | |
2156 | xtensa_format fmt; | |
2157 | xtensa_opcode opc = insn->opcode; | |
2158 | int slot, opnd, fmt_found; | |
2159 | unsigned val; | |
2160 | ||
2161 | if (!slotbuf) | |
2162 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2163 | ||
2164 | /* Find format/slot where this can be encoded. */ | |
2165 | fmt_found = 0; | |
2166 | slot = 0; | |
2167 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2168 | { | |
2169 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2170 | { | |
2171 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2172 | { | |
2173 | fmt_found = 1; | |
2174 | break; | |
2175 | } | |
2176 | } | |
2177 | if (fmt_found) break; | |
2178 | } | |
2179 | ||
2180 | if (!fmt_found) | |
2181 | { | |
2182 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2183 | return -1; | |
2184 | } | |
2185 | ||
2186 | /* First encode all the visible operands | |
2187 | (to deal with shared field operands). */ | |
2188 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2189 | { | |
2190 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2191 | && (insn->tok[opnd].X_op == O_register | |
2192 | || insn->tok[opnd].X_op == O_constant)) | |
2193 | { | |
2194 | val = insn->tok[opnd].X_add_number; | |
2195 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2196 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2197 | } | |
2198 | } | |
2199 | ||
2200 | /* Then pull out the values for the invisible ones. */ | |
2201 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2202 | { | |
2203 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2204 | { | |
2205 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2206 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2207 | insn->tok[opnd].X_add_number = val; | |
2208 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2209 | insn->tok[opnd].X_op = O_register; | |
2210 | else | |
2211 | insn->tok[opnd].X_op = O_constant; | |
2212 | } | |
2213 | } | |
2214 | ||
2215 | return 0; | |
2216 | } | |
2217 | ||
2218 | ||
e0001a05 | 2219 | static void |
7fa3d080 | 2220 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2221 | { |
2222 | char *cnt_arg, *new_arg; | |
2223 | cnt_arg = *cnt_argp; | |
2224 | ||
2225 | /* replace the argument with "31-(argument)" */ | |
78fb7e37 | 2226 | new_arg = concat ("31-(", cnt_arg, ")", (char *) NULL); |
e0001a05 NC |
2227 | |
2228 | free (cnt_arg); | |
2229 | *cnt_argp = new_arg; | |
2230 | } | |
2231 | ||
2232 | ||
2233 | /* If "arg" is a constant expression, return non-zero with the value | |
2234 | in *valp. */ | |
2235 | ||
2236 | static int | |
7fa3d080 | 2237 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2238 | { |
2239 | expressionS exp; | |
2240 | char *save_ptr = input_line_pointer; | |
2241 | ||
2242 | input_line_pointer = arg; | |
2243 | expression (&exp); | |
2244 | input_line_pointer = save_ptr; | |
2245 | ||
2246 | if (exp.X_op == O_constant) | |
2247 | { | |
2248 | *valp = exp.X_add_number; | |
2249 | return 1; | |
2250 | } | |
2251 | ||
2252 | return 0; | |
2253 | } | |
2254 | ||
2255 | ||
2256 | static void | |
b9bb4a93 | 2257 | xg_replace_opname (char **popname, const char *newop) |
e0001a05 NC |
2258 | { |
2259 | free (*popname); | |
4ec9d7d5 | 2260 | *popname = xstrdup (newop); |
e0001a05 NC |
2261 | } |
2262 | ||
2263 | ||
2264 | static int | |
7fa3d080 BW |
2265 | xg_check_num_args (int *pnum_args, |
2266 | int expected_num, | |
2267 | char *opname, | |
2268 | char **arg_strings) | |
e0001a05 NC |
2269 | { |
2270 | int num_args = *pnum_args; | |
2271 | ||
43cd72b9 | 2272 | if (num_args < expected_num) |
e0001a05 NC |
2273 | { |
2274 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2275 | num_args, opname, expected_num); | |
2276 | return -1; | |
2277 | } | |
2278 | ||
2279 | if (num_args > expected_num) | |
2280 | { | |
2281 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2282 | num_args, opname, expected_num); | |
2283 | while (num_args-- > expected_num) | |
2284 | { | |
2285 | free (arg_strings[num_args]); | |
2286 | arg_strings[num_args] = 0; | |
2287 | } | |
2288 | *pnum_args = expected_num; | |
2289 | return -1; | |
2290 | } | |
2291 | ||
2292 | return 0; | |
2293 | } | |
2294 | ||
2295 | ||
43cd72b9 BW |
2296 | /* If the register is not specified as part of the opcode, |
2297 | then get it from the operand and move it to the opcode. */ | |
2298 | ||
e0001a05 | 2299 | static int |
7fa3d080 | 2300 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2301 | { |
43cd72b9 BW |
2302 | xtensa_isa isa = xtensa_default_isa; |
2303 | xtensa_sysreg sr; | |
e0001a05 | 2304 | char *opname, *new_opname; |
43cd72b9 BW |
2305 | const char *sr_name; |
2306 | int is_user, is_write; | |
e0001a05 NC |
2307 | |
2308 | opname = *popname; | |
2309 | if (*opname == '_') | |
80ca4e2c | 2310 | opname += 1; |
43cd72b9 BW |
2311 | is_user = (opname[1] == 'u'); |
2312 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2313 | |
43cd72b9 | 2314 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2315 | |
43cd72b9 BW |
2316 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2317 | return -1; | |
e0001a05 | 2318 | |
43cd72b9 BW |
2319 | /* Check if the argument is a symbolic register name. */ |
2320 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2321 | /* Handle WSR to "INTSET" as a special case. */ | |
2322 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2323 | && !strcasecmp (arg_strings[1], "intset")) | |
2324 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2325 | if (sr == XTENSA_UNDEFINED | |
2326 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2327 | { | |
2328 | /* Maybe it's a register number.... */ | |
2329 | offsetT val; | |
e0001a05 NC |
2330 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2331 | { | |
43cd72b9 BW |
2332 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2333 | arg_strings[1], opname); | |
e0001a05 NC |
2334 | return -1; |
2335 | } | |
43cd72b9 BW |
2336 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2337 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2338 | { |
43cd72b9 | 2339 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2340 | (long) val, opname); |
e0001a05 NC |
2341 | return -1; |
2342 | } | |
43cd72b9 | 2343 | } |
e0001a05 | 2344 | |
43cd72b9 BW |
2345 | /* Remove the last argument, which is now part of the opcode. */ |
2346 | free (arg_strings[1]); | |
2347 | arg_strings[1] = 0; | |
2348 | *pnum_args = 1; | |
2349 | ||
2350 | /* Translate the opcode. */ | |
2351 | sr_name = xtensa_sysreg_name (isa, sr); | |
2352 | /* Another special case for "WSR.INTSET".... */ | |
2353 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2354 | sr_name = "intset"; | |
4ec9d7d5 | 2355 | new_opname = concat (*popname, ".", sr_name, (char *) NULL); |
43cd72b9 BW |
2356 | free (*popname); |
2357 | *popname = new_opname; | |
2358 | ||
2359 | return 0; | |
2360 | } | |
2361 | ||
2362 | ||
2363 | static int | |
7fa3d080 | 2364 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2365 | { |
2366 | xtensa_isa isa = xtensa_default_isa; | |
2367 | xtensa_sysreg sr; | |
2368 | char *opname, *new_opname; | |
2369 | const char *sr_name; | |
2370 | bfd_boolean has_underbar = FALSE; | |
2371 | ||
2372 | opname = *popname; | |
2373 | if (opname[0] == '_') | |
2374 | { | |
2375 | has_underbar = TRUE; | |
2376 | opname += 1; | |
2377 | } | |
2378 | ||
2379 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2380 | if (sr != XTENSA_UNDEFINED) | |
2381 | { | |
2382 | /* The new default name ("nnn") is different from the old default | |
2383 | name ("URnnn"). The old default is handled below, and we don't | |
2384 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2385 | default. */ | |
2386 | static char namebuf[10]; | |
2387 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2388 | if (strcmp (namebuf, opname + 1) == 0) | |
2389 | return 0; | |
2390 | } | |
2391 | else | |
2392 | { | |
2393 | offsetT val; | |
2394 | char *end; | |
2395 | ||
2396 | /* Only continue if the reg name is "URnnn". */ | |
2397 | if (opname[1] != 'u' || opname[2] != 'r') | |
2398 | return 0; | |
2399 | val = strtoul (opname + 3, &end, 10); | |
2400 | if (*end != '\0') | |
2401 | return 0; | |
2402 | ||
2403 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2404 | if (sr == XTENSA_UNDEFINED) | |
2405 | { | |
2406 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2407 | (long) val, opname); |
43cd72b9 BW |
2408 | return -1; |
2409 | } | |
2410 | } | |
2411 | ||
2412 | /* Translate the opcode. */ | |
2413 | sr_name = xtensa_sysreg_name (isa, sr); | |
add39d23 | 2414 | new_opname = XNEWVEC (char, strlen (sr_name) + 6); |
43cd72b9 BW |
2415 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), |
2416 | opname[0], sr_name); | |
2417 | free (*popname); | |
2418 | *popname = new_opname; | |
2419 | ||
2420 | return 0; | |
2421 | } | |
2422 | ||
2423 | ||
2424 | static int | |
b9bb4a93 TS |
2425 | xtensa_translate_zero_immed (const char *old_op, |
2426 | const char *new_op, | |
7fa3d080 BW |
2427 | char **popname, |
2428 | int *pnum_args, | |
2429 | char **arg_strings) | |
43cd72b9 BW |
2430 | { |
2431 | char *opname; | |
2432 | offsetT val; | |
2433 | ||
2434 | opname = *popname; | |
9c2799c2 | 2435 | gas_assert (opname[0] != '_'); |
43cd72b9 BW |
2436 | |
2437 | if (strcmp (opname, old_op) != 0) | |
2438 | return 0; | |
e0001a05 | 2439 | |
43cd72b9 BW |
2440 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2441 | return -1; | |
2442 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2443 | { | |
2444 | xg_replace_opname (popname, new_op); | |
2445 | free (arg_strings[1]); | |
2446 | arg_strings[1] = arg_strings[2]; | |
2447 | arg_strings[2] = 0; | |
2448 | *pnum_args = 2; | |
e0001a05 NC |
2449 | } |
2450 | ||
2451 | return 0; | |
2452 | } | |
2453 | ||
2454 | ||
2455 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2456 | Returns non-zero if an error was found. */ | |
2457 | ||
2458 | static int | |
7fa3d080 | 2459 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2460 | { |
2461 | char *opname = *popname; | |
2462 | bfd_boolean has_underbar = FALSE; | |
2463 | ||
2464 | if (*opname == '_') | |
2465 | { | |
2466 | has_underbar = TRUE; | |
2467 | opname += 1; | |
2468 | } | |
2469 | ||
2470 | if (strcmp (opname, "mov") == 0) | |
2471 | { | |
43cd72b9 | 2472 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2473 | xg_replace_opname (popname, "mov.n"); |
2474 | else | |
2475 | { | |
2476 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2477 | return -1; | |
2478 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
4ec9d7d5 | 2479 | arg_strings[2] = xstrdup (arg_strings[1]); |
e0001a05 NC |
2480 | *pnum_args = 3; |
2481 | } | |
2482 | return 0; | |
2483 | } | |
2484 | ||
2485 | if (strcmp (opname, "bbsi.l") == 0) | |
2486 | { | |
2487 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2488 | return -1; | |
2489 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2490 | if (target_big_endian) | |
2491 | xg_reverse_shift_count (&arg_strings[1]); | |
2492 | return 0; | |
2493 | } | |
2494 | ||
2495 | if (strcmp (opname, "bbci.l") == 0) | |
2496 | { | |
2497 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2498 | return -1; | |
2499 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2500 | if (target_big_endian) | |
2501 | xg_reverse_shift_count (&arg_strings[1]); | |
2502 | return 0; | |
2503 | } | |
2504 | ||
eb6d9dce | 2505 | /* Don't do anything special with NOPs inside FLIX instructions. They |
3739860c | 2506 | are handled elsewhere. Real NOP instructions are always available |
eb6d9dce BW |
2507 | in configurations with FLIX, so this should never be an issue but |
2508 | check for it anyway. */ | |
2509 | if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED | |
43cd72b9 | 2510 | && strcmp (opname, "nop") == 0) |
e0001a05 | 2511 | { |
43cd72b9 | 2512 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2513 | xg_replace_opname (popname, "nop.n"); |
2514 | else | |
2515 | { | |
2516 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2517 | return -1; | |
2518 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
4ec9d7d5 TS |
2519 | arg_strings[0] = xstrdup ("a1"); |
2520 | arg_strings[1] = xstrdup ("a1"); | |
2521 | arg_strings[2] = xstrdup ("a1"); | |
e0001a05 NC |
2522 | *pnum_args = 3; |
2523 | } | |
2524 | return 0; | |
2525 | } | |
2526 | ||
43cd72b9 BW |
2527 | /* Recognize [RW]UR and [RWX]SR. */ |
2528 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2529 | && (opname[1] == 'u' || opname[1] == 's')) | |
2530 | || (opname[0] == 'x' && opname[1] == 's')) | |
2531 | && opname[2] == 'r' | |
2532 | && opname[3] == '\0') | |
e0001a05 NC |
2533 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2534 | ||
43cd72b9 BW |
2535 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2536 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2537 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2538 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2539 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2540 | |
43cd72b9 BW |
2541 | /* Relax branches that don't allow comparisons against an immediate value |
2542 | of zero to the corresponding branches with implicit zero immediates. */ | |
2543 | if (!has_underbar && use_transform ()) | |
2544 | { | |
2545 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2546 | pnum_args, arg_strings)) | |
2547 | return -1; | |
e0001a05 | 2548 | |
43cd72b9 BW |
2549 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2550 | pnum_args, arg_strings)) | |
2551 | return -1; | |
e0001a05 | 2552 | |
43cd72b9 BW |
2553 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2554 | pnum_args, arg_strings)) | |
2555 | return -1; | |
e0001a05 | 2556 | |
43cd72b9 BW |
2557 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2558 | pnum_args, arg_strings)) | |
2559 | return -1; | |
2560 | } | |
e0001a05 | 2561 | |
43cd72b9 BW |
2562 | return 0; |
2563 | } | |
e0001a05 | 2564 | |
43cd72b9 BW |
2565 | \f |
2566 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2567 | |
43cd72b9 BW |
2568 | /* Currently the assembler only allows us to use a single target per |
2569 | fragment. Because of this, only one operand for a given | |
2570 | instruction may be symbolic. If there is a PC-relative operand, | |
2571 | the last one is chosen. Otherwise, the result is the number of the | |
2572 | last immediate operand, and if there are none of those, we fail and | |
2573 | return -1. */ | |
e0001a05 | 2574 | |
7fa3d080 BW |
2575 | static int |
2576 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2577 | { |
2578 | int last_immed = -1; | |
2579 | int noperands, opi; | |
e0001a05 | 2580 | |
43cd72b9 BW |
2581 | if (opcode == XTENSA_UNDEFINED) |
2582 | return -1; | |
e0001a05 | 2583 | |
43cd72b9 BW |
2584 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2585 | for (opi = noperands - 1; opi >= 0; opi--) | |
2586 | { | |
2587 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2588 | continue; | |
2589 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2590 | return opi; | |
2591 | if (last_immed == -1 | |
2592 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2593 | last_immed = opi; | |
e0001a05 | 2594 | } |
43cd72b9 | 2595 | return last_immed; |
e0001a05 NC |
2596 | } |
2597 | ||
e0001a05 | 2598 | |
43cd72b9 | 2599 | static xtensa_opcode |
7fa3d080 | 2600 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2601 | { |
43cd72b9 BW |
2602 | static xtensa_insnbuf insnbuf = NULL; |
2603 | static xtensa_insnbuf slotbuf = NULL; | |
2604 | xtensa_isa isa = xtensa_default_isa; | |
2605 | xtensa_format fmt; | |
2606 | ||
2607 | if (!insnbuf) | |
e0001a05 | 2608 | { |
43cd72b9 BW |
2609 | insnbuf = xtensa_insnbuf_alloc (isa); |
2610 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2611 | } |
e0001a05 | 2612 | |
d77b99c9 | 2613 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2614 | fmt = xtensa_format_decode (isa, insnbuf); |
2615 | if (fmt == XTENSA_UNDEFINED) | |
2616 | return XTENSA_UNDEFINED; | |
e0001a05 | 2617 | |
43cd72b9 BW |
2618 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2619 | return XTENSA_UNDEFINED; | |
e0001a05 | 2620 | |
43cd72b9 BW |
2621 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2622 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2623 | } |
2624 | ||
2625 | ||
43cd72b9 | 2626 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2627 | |
43cd72b9 | 2628 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2629 | |
7fa3d080 BW |
2630 | static void |
2631 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2632 | { |
2633 | int num_opcodes, num_operands; | |
2634 | xtensa_opcode opcode; | |
2635 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2636 | |
43cd72b9 BW |
2637 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2638 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2639 | { |
43cd72b9 BW |
2640 | int opn; |
2641 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2642 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2643 | for (opn = 0; opn < num_operands; opn++) | |
2644 | { | |
2645 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2646 | continue; | |
2647 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2648 | { | |
2649 | xtensa_regfile opnd_rf = | |
2650 | xtensa_operand_regfile (isa, opcode, opn); | |
2651 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2652 | } | |
2653 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2654 | fputs ("[lLr] ", stderr); | |
2655 | else | |
2656 | fputs ("i ", stderr); | |
2657 | } | |
2658 | fprintf (stderr, "\n"); | |
e0001a05 | 2659 | } |
e0001a05 NC |
2660 | } |
2661 | ||
2662 | ||
43cd72b9 | 2663 | static void |
7fa3d080 | 2664 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2665 | { |
e0001a05 | 2666 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2667 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2668 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2669 | int op; | |
e0001a05 | 2670 | |
43cd72b9 | 2671 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2672 | |
43cd72b9 BW |
2673 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2674 | { | |
2675 | xtensa_opcode opcode; | |
2676 | const char *opname; | |
2677 | int operands; | |
2678 | ||
2679 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2680 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2681 | opname = xtensa_opcode_name (isa, opcode); | |
2682 | ||
2683 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2684 | fprintf (stderr, " operands = "); | |
2685 | for (operands = 0; | |
2686 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2687 | operands++) | |
2688 | { | |
2689 | unsigned int val; | |
2690 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2691 | continue; | |
2692 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2693 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2694 | fprintf (stderr, "%d ", val); | |
2695 | } | |
2696 | fprintf (stderr, "\n"); | |
2697 | } | |
2698 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2699 | } |
2700 | ||
43cd72b9 BW |
2701 | #endif /* TENSILICA_DEBUG */ |
2702 | ||
e0001a05 NC |
2703 | |
2704 | static bfd_boolean | |
7fa3d080 | 2705 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2706 | { |
43cd72b9 BW |
2707 | xtensa_isa isa = xtensa_default_isa; |
2708 | int n, num_operands; | |
e0001a05 | 2709 | |
64b607e6 | 2710 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
e0001a05 NC |
2711 | return FALSE; |
2712 | ||
43cd72b9 BW |
2713 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2714 | for (n = 0; n < num_operands; n++) | |
2715 | { | |
2716 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2717 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2718 | return TRUE; | |
2719 | } | |
2720 | return FALSE; | |
e0001a05 NC |
2721 | } |
2722 | ||
2723 | ||
43cd72b9 BW |
2724 | /* Convert from BFD relocation type code to slot and operand number. |
2725 | Returns non-zero on failure. */ | |
e0001a05 | 2726 | |
43cd72b9 | 2727 | static int |
7fa3d080 | 2728 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2729 | { |
43cd72b9 BW |
2730 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2731 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2732 | { |
43cd72b9 BW |
2733 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2734 | *is_alt = FALSE; | |
e0001a05 | 2735 | } |
43cd72b9 BW |
2736 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2737 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2738 | { |
43cd72b9 BW |
2739 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2740 | *is_alt = TRUE; | |
e0001a05 | 2741 | } |
43cd72b9 BW |
2742 | else |
2743 | return -1; | |
2744 | ||
2745 | return 0; | |
e0001a05 NC |
2746 | } |
2747 | ||
2748 | ||
43cd72b9 BW |
2749 | /* Convert from slot number to BFD relocation type code for the |
2750 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2751 | failure. */ | |
e0001a05 | 2752 | |
43cd72b9 | 2753 | static bfd_reloc_code_real_type |
7fa3d080 | 2754 | encode_reloc (int slot) |
e0001a05 | 2755 | { |
43cd72b9 BW |
2756 | if (slot < 0 || slot > 14) |
2757 | return BFD_RELOC_NONE; | |
2758 | ||
2759 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2760 | } |
2761 | ||
2762 | ||
43cd72b9 BW |
2763 | /* Convert from slot numbers to BFD relocation type code for the |
2764 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2765 | |
43cd72b9 | 2766 | static bfd_reloc_code_real_type |
7fa3d080 | 2767 | encode_alt_reloc (int slot) |
e0001a05 | 2768 | { |
43cd72b9 BW |
2769 | if (slot < 0 || slot > 14) |
2770 | return BFD_RELOC_NONE; | |
2771 | ||
2772 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2773 | } |
2774 | ||
2775 | ||
2776 | static void | |
7fa3d080 BW |
2777 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2778 | xtensa_format fmt, | |
2779 | int slot, | |
2780 | xtensa_opcode opcode, | |
2781 | int operand, | |
2782 | uint32 value, | |
2783 | const char *file, | |
2784 | unsigned int line) | |
e0001a05 | 2785 | { |
e0001a05 NC |
2786 | uint32 valbuf = value; |
2787 | ||
43cd72b9 | 2788 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2789 | { |
43cd72b9 BW |
2790 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2791 | == 1) | |
2792 | as_bad_where ((char *) file, line, | |
3739860c | 2793 | _("operand %d of '%s' has out of range value '%u'"), |
d7c531cd BW |
2794 | operand + 1, |
2795 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2796 | value); | |
43cd72b9 BW |
2797 | else |
2798 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2799 | _("operand %d of '%s' has invalid value '%u'"), |
2800 | operand + 1, | |
2801 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2802 | value); | |
43cd72b9 | 2803 | return; |
e0001a05 NC |
2804 | } |
2805 | ||
43cd72b9 BW |
2806 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2807 | slotbuf, valbuf); | |
e0001a05 NC |
2808 | } |
2809 | ||
2810 | ||
2811 | static uint32 | |
7fa3d080 BW |
2812 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2813 | xtensa_format fmt, | |
2814 | int slot, | |
2815 | xtensa_opcode opcode, | |
2816 | int opnum) | |
e0001a05 | 2817 | { |
43cd72b9 BW |
2818 | uint32 val = 0; |
2819 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2820 | fmt, slot, slotbuf, &val); | |
2821 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2822 | return val; | |
e0001a05 NC |
2823 | } |
2824 | ||
e0001a05 | 2825 | \f |
7fa3d080 | 2826 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2827 | |
7fa3d080 BW |
2828 | /* The routine xg_instruction_matches_option_term must return TRUE |
2829 | when a given option term is true. The meaning of all of the option | |
19e8f41a | 2830 | terms is given interpretation by this function. */ |
e0001a05 | 2831 | |
7fa3d080 | 2832 | static bfd_boolean |
19e8f41a | 2833 | xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option) |
e0001a05 | 2834 | { |
7fa3d080 BW |
2835 | if (strcmp (option->option_name, "realnop") == 0 |
2836 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2837 | { | |
2838 | /* These conditions were evaluated statically when building the | |
2839 | relaxation table. There's no need to reevaluate them now. */ | |
2840 | return TRUE; | |
2841 | } | |
19e8f41a BW |
2842 | else if (strcmp (option->option_name, "FREEREG") == 0) |
2843 | return insn->extra_arg.X_op == O_register; | |
7fa3d080 BW |
2844 | else |
2845 | { | |
2846 | as_fatal (_("internal error: unknown option name '%s'"), | |
2847 | option->option_name); | |
2848 | } | |
e0001a05 NC |
2849 | } |
2850 | ||
2851 | ||
7fa3d080 BW |
2852 | static bfd_boolean |
2853 | xg_instruction_matches_or_options (TInsn *insn, | |
2854 | const ReqOrOptionList *or_option) | |
e0001a05 | 2855 | { |
7fa3d080 BW |
2856 | const ReqOrOption *option; |
2857 | /* Must match each of the AND terms. */ | |
2858 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2859 | { |
7fa3d080 BW |
2860 | if (xg_instruction_matches_option_term (insn, option)) |
2861 | return TRUE; | |
e0001a05 | 2862 | } |
7fa3d080 | 2863 | return FALSE; |
e0001a05 NC |
2864 | } |
2865 | ||
2866 | ||
7fa3d080 BW |
2867 | static bfd_boolean |
2868 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2869 | { |
7fa3d080 BW |
2870 | const ReqOption *req_options; |
2871 | /* Must match each of the AND terms. */ | |
2872 | for (req_options = options; | |
2873 | req_options != NULL; | |
2874 | req_options = req_options->next) | |
e0001a05 | 2875 | { |
7fa3d080 BW |
2876 | /* Must match one of the OR clauses. */ |
2877 | if (!xg_instruction_matches_or_options (insn, | |
2878 | req_options->or_option_terms)) | |
2879 | return FALSE; | |
e0001a05 | 2880 | } |
7fa3d080 | 2881 | return TRUE; |
e0001a05 NC |
2882 | } |
2883 | ||
2884 | ||
7fa3d080 | 2885 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2886 | |
7fa3d080 BW |
2887 | static bfd_boolean |
2888 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2889 | { |
7fa3d080 | 2890 | PreconditionList *condition_l; |
e0001a05 | 2891 | |
7fa3d080 BW |
2892 | if (rule->opcode != insn->opcode) |
2893 | return FALSE; | |
e0001a05 | 2894 | |
7fa3d080 BW |
2895 | for (condition_l = rule->conditions; |
2896 | condition_l != NULL; | |
2897 | condition_l = condition_l->next) | |
e0001a05 | 2898 | { |
7fa3d080 BW |
2899 | expressionS *exp1; |
2900 | expressionS *exp2; | |
2901 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2902 | |
7fa3d080 | 2903 | switch (cond->typ) |
e0001a05 | 2904 | { |
7fa3d080 BW |
2905 | case OP_CONSTANT: |
2906 | /* The expression must be the constant. */ | |
9c2799c2 | 2907 | gas_assert (cond->op_num < insn->ntok); |
7fa3d080 BW |
2908 | exp1 = &insn->tok[cond->op_num]; |
2909 | if (expr_is_const (exp1)) | |
2910 | { | |
2911 | switch (cond->cmp) | |
2912 | { | |
2913 | case OP_EQUAL: | |
2914 | if (get_expr_const (exp1) != cond->op_data) | |
2915 | return FALSE; | |
2916 | break; | |
2917 | case OP_NOTEQUAL: | |
2918 | if (get_expr_const (exp1) == cond->op_data) | |
2919 | return FALSE; | |
2920 | break; | |
2921 | default: | |
2922 | return FALSE; | |
2923 | } | |
2924 | } | |
2925 | else if (expr_is_register (exp1)) | |
2926 | { | |
2927 | switch (cond->cmp) | |
2928 | { | |
2929 | case OP_EQUAL: | |
2930 | if (get_expr_register (exp1) != cond->op_data) | |
2931 | return FALSE; | |
2932 | break; | |
2933 | case OP_NOTEQUAL: | |
2934 | if (get_expr_register (exp1) == cond->op_data) | |
2935 | return FALSE; | |
2936 | break; | |
2937 | default: | |
2938 | return FALSE; | |
2939 | } | |
2940 | } | |
2941 | else | |
2942 | return FALSE; | |
2943 | break; | |
2944 | ||
2945 | case OP_OPERAND: | |
9c2799c2 NC |
2946 | gas_assert (cond->op_num < insn->ntok); |
2947 | gas_assert (cond->op_data < insn->ntok); | |
7fa3d080 BW |
2948 | exp1 = &insn->tok[cond->op_num]; |
2949 | exp2 = &insn->tok[cond->op_data]; | |
2950 | ||
2951 | switch (cond->cmp) | |
2952 | { | |
2953 | case OP_EQUAL: | |
2954 | if (!expr_is_equal (exp1, exp2)) | |
2955 | return FALSE; | |
2956 | break; | |
2957 | case OP_NOTEQUAL: | |
2958 | if (expr_is_equal (exp1, exp2)) | |
2959 | return FALSE; | |
2960 | break; | |
2961 | } | |
2962 | break; | |
2963 | ||
2964 | case OP_LITERAL: | |
2965 | case OP_LABEL: | |
2966 | default: | |
2967 | return FALSE; | |
2968 | } | |
2969 | } | |
2970 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2971 | return FALSE; | |
2972 | ||
2973 | return TRUE; | |
2974 | } | |
2975 | ||
2976 | ||
2977 | static int | |
2978 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2979 | { | |
2980 | bfd_boolean a_greater = FALSE; | |
2981 | bfd_boolean b_greater = FALSE; | |
2982 | ||
2983 | ReqOptionList *l_a = a->options; | |
2984 | ReqOptionList *l_b = b->options; | |
2985 | ||
2986 | /* We only care if they both are the same except for | |
2987 | a const16 vs. an l32r. */ | |
2988 | ||
2989 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2990 | { | |
2991 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2992 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2993 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2994 | { | |
2995 | if (l_or_a->is_true != l_or_b->is_true) | |
2996 | return 0; | |
2997 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2998 | { | |
2999 | /* This is the case we care about. */ | |
3000 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
3001 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
3002 | { | |
3003 | if (prefer_const16) | |
3004 | a_greater = TRUE; | |
3005 | else | |
3006 | b_greater = TRUE; | |
3007 | } | |
3008 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
3009 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
3010 | { | |
3011 | if (prefer_const16) | |
3012 | b_greater = TRUE; | |
3013 | else | |
3014 | a_greater = TRUE; | |
3015 | } | |
3016 | else | |
3017 | return 0; | |
3018 | } | |
3019 | l_or_a = l_or_a->next; | |
3020 | l_or_b = l_or_b->next; | |
3021 | } | |
3022 | if (l_or_a || l_or_b) | |
3023 | return 0; | |
3024 | ||
3025 | l_a = l_a->next; | |
3026 | l_b = l_b->next; | |
3027 | } | |
3028 | if (l_a || l_b) | |
3029 | return 0; | |
3030 | ||
3031 | /* Incomparable if the substitution was used differently in two cases. */ | |
3032 | if (a_greater && b_greater) | |
3033 | return 0; | |
3034 | ||
3035 | if (b_greater) | |
3036 | return 1; | |
3037 | if (a_greater) | |
3038 | return -1; | |
3039 | ||
3040 | return 0; | |
3041 | } | |
3042 | ||
3043 | ||
3044 | static TransitionRule * | |
3045 | xg_instruction_match (TInsn *insn) | |
3046 | { | |
3047 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
3048 | TransitionList *l; | |
9c2799c2 | 3049 | gas_assert (insn->opcode < table->num_opcodes); |
7fa3d080 BW |
3050 | |
3051 | /* Walk through all of the possible transitions. */ | |
3052 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3053 | { | |
3054 | TransitionRule *rule = l->rule; | |
3055 | if (xg_instruction_matches_rule (insn, rule)) | |
3056 | return rule; | |
3057 | } | |
3058 | return NULL; | |
3059 | } | |
3060 | ||
3061 | \f | |
3062 | /* Various Other Internal Functions. */ | |
3063 | ||
3064 | static bfd_boolean | |
3065 | is_unique_insn_expansion (TransitionRule *r) | |
3066 | { | |
3067 | if (!r->to_instr || r->to_instr->next != NULL) | |
3068 | return FALSE; | |
3069 | if (r->to_instr->typ != INSTR_INSTR) | |
3070 | return FALSE; | |
3071 | return TRUE; | |
3072 | } | |
3073 | ||
3074 | ||
84b08ed9 BW |
3075 | /* Check if there is exactly one relaxation for INSN that converts it to |
3076 | another instruction of equal or larger size. If so, and if TARG is | |
3077 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
3078 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
3079 | instruction, i.e., ignore relaxations that convert to an instruction of | |
3080 | equal size. In some contexts where this function is used, only | |
c138bc38 | 3081 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
3082 | exclude cases like ADDI being "widened" to an ADDMI, which may |
3083 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 3084 | |
84b08ed9 BW |
3085 | bfd_boolean |
3086 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
3087 | { |
3088 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3089 | TransitionList *l; | |
84b08ed9 | 3090 | TransitionRule *match = 0; |
7fa3d080 | 3091 | |
9c2799c2 NC |
3092 | gas_assert (insn->insn_type == ITYPE_INSN); |
3093 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3094 | |
3095 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3096 | { | |
3097 | TransitionRule *rule = l->rule; | |
3098 | ||
3099 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
3100 | && is_unique_insn_expansion (rule) |
3101 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
3102 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 3103 | { |
84b08ed9 BW |
3104 | if (match) |
3105 | return FALSE; | |
3106 | match = rule; | |
7fa3d080 BW |
3107 | } |
3108 | } | |
84b08ed9 BW |
3109 | if (!match) |
3110 | return FALSE; | |
3111 | ||
3112 | if (targ) | |
3113 | xg_build_to_insn (targ, insn, match->to_instr); | |
3114 | return TRUE; | |
7fa3d080 BW |
3115 | } |
3116 | ||
3117 | ||
3118 | /* Return the maximum number of bytes this opcode can expand to. */ | |
3119 | ||
3120 | static int | |
3121 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
3122 | { | |
3123 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3124 | TransitionList *l; | |
3125 | int max_size = xg_get_single_size (opcode); | |
3126 | ||
9c2799c2 | 3127 | gas_assert (opcode < table->num_opcodes); |
7fa3d080 BW |
3128 | |
3129 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3130 | { | |
3131 | TransitionRule *rule = l->rule; | |
3132 | BuildInstr *build_list; | |
3133 | int this_size = 0; | |
3134 | ||
3135 | if (!rule) | |
3136 | continue; | |
3137 | build_list = rule->to_instr; | |
3138 | if (is_unique_insn_expansion (rule)) | |
3139 | { | |
9c2799c2 | 3140 | gas_assert (build_list->typ == INSTR_INSTR); |
7fa3d080 BW |
3141 | this_size = xg_get_max_insn_widen_size (build_list->opcode); |
3142 | } | |
3143 | else | |
3144 | for (; build_list != NULL; build_list = build_list->next) | |
3145 | { | |
3146 | switch (build_list->typ) | |
3147 | { | |
3148 | case INSTR_INSTR: | |
3149 | this_size += xg_get_single_size (build_list->opcode); | |
3150 | break; | |
3151 | case INSTR_LITERAL_DEF: | |
3152 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3153 | default: |
3154 | break; | |
3155 | } | |
3156 | } | |
3157 | if (this_size > max_size) | |
3158 | max_size = this_size; | |
3159 | } | |
3160 | return max_size; | |
3161 | } | |
3162 | ||
3163 | ||
3164 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3165 | ||
7fa3d080 BW |
3166 | static int |
3167 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3168 | { |
43cd72b9 | 3169 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3170 | TransitionList *l; |
3171 | int max_size = 0; | |
3172 | ||
9c2799c2 | 3173 | gas_assert (opcode < table->num_opcodes); |
e0001a05 NC |
3174 | |
3175 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3176 | { | |
3177 | TransitionRule *rule = l->rule; | |
3178 | BuildInstr *build_list; | |
3179 | int this_size = 0; | |
3180 | ||
3181 | if (!rule) | |
3182 | continue; | |
3183 | build_list = rule->to_instr; | |
3184 | if (is_unique_insn_expansion (rule)) | |
3185 | { | |
9c2799c2 | 3186 | gas_assert (build_list->typ == INSTR_INSTR); |
e0001a05 NC |
3187 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); |
3188 | } | |
3189 | else | |
3190 | for (; build_list != NULL; build_list = build_list->next) | |
3191 | { | |
3192 | switch (build_list->typ) | |
3193 | { | |
3194 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3195 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3196 | this_size += 4; |
3197 | break; | |
3198 | case INSTR_INSTR: | |
3199 | case INSTR_LABEL_DEF: | |
3200 | default: | |
3201 | break; | |
3202 | } | |
3203 | } | |
3204 | if (this_size > max_size) | |
3205 | max_size = this_size; | |
3206 | } | |
3207 | return max_size; | |
3208 | } | |
3209 | ||
3210 | ||
7fa3d080 BW |
3211 | static bfd_boolean |
3212 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3213 | { | |
3214 | int steps_taken = 0; | |
3215 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3216 | TransitionList *l; | |
3217 | ||
9c2799c2 NC |
3218 | gas_assert (insn->insn_type == ITYPE_INSN); |
3219 | gas_assert (insn->opcode < table->num_opcodes); | |
7fa3d080 BW |
3220 | |
3221 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3222 | { | |
3223 | TransitionRule *rule = l->rule; | |
3224 | ||
3225 | if (xg_instruction_matches_rule (insn, rule)) | |
3226 | { | |
3227 | if (steps_taken == lateral_steps) | |
3228 | return TRUE; | |
3229 | steps_taken++; | |
3230 | } | |
3231 | } | |
3232 | return FALSE; | |
3233 | } | |
3234 | ||
3235 | ||
3236 | static symbolS * | |
3237 | get_special_literal_symbol (void) | |
3238 | { | |
3239 | static symbolS *sym = NULL; | |
3240 | ||
3241 | if (sym == NULL) | |
3242 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3243 | return sym; | |
3244 | } | |
3245 | ||
3246 | ||
3247 | static symbolS * | |
3248 | get_special_label_symbol (void) | |
3249 | { | |
3250 | static symbolS *sym = NULL; | |
3251 | ||
3252 | if (sym == NULL) | |
3253 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3254 | return sym; | |
3255 | } | |
3256 | ||
3257 | ||
3258 | static bfd_boolean | |
3259 | xg_valid_literal_expression (const expressionS *exp) | |
3260 | { | |
3261 | switch (exp->X_op) | |
3262 | { | |
3263 | case O_constant: | |
3264 | case O_symbol: | |
3265 | case O_big: | |
3266 | case O_uminus: | |
3267 | case O_subtract: | |
3268 | case O_pltrel: | |
1bbb5f21 | 3269 | case O_pcrel: |
28dbbc02 BW |
3270 | case O_tlsfunc: |
3271 | case O_tlsarg: | |
3272 | case O_tpoff: | |
3273 | case O_dtpoff: | |
7fa3d080 BW |
3274 | return TRUE; |
3275 | default: | |
3276 | return FALSE; | |
3277 | } | |
3278 | } | |
3279 | ||
3280 | ||
3281 | /* This will check to see if the value can be converted into the | |
3282 | operand type. It will return TRUE if it does not fit. */ | |
3283 | ||
3284 | static bfd_boolean | |
3285 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3286 | { | |
3287 | uint32 valbuf = value; | |
3288 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3289 | return TRUE; | |
3290 | return FALSE; | |
3291 | } | |
3292 | ||
3293 | ||
3294 | /* Assumes: All immeds are constants. Check that all constants fit | |
3295 | into their immeds; return FALSE if not. */ | |
3296 | ||
3297 | static bfd_boolean | |
3298 | xg_immeds_fit (const TInsn *insn) | |
3299 | { | |
3300 | xtensa_isa isa = xtensa_default_isa; | |
3301 | int i; | |
3302 | ||
3303 | int n = insn->ntok; | |
9c2799c2 | 3304 | gas_assert (insn->insn_type == ITYPE_INSN); |
7fa3d080 BW |
3305 | for (i = 0; i < n; ++i) |
3306 | { | |
91d6fa6a NC |
3307 | const expressionS *exp = &insn->tok[i]; |
3308 | ||
7fa3d080 BW |
3309 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) |
3310 | continue; | |
3311 | ||
91d6fa6a | 3312 | switch (exp->X_op) |
7fa3d080 BW |
3313 | { |
3314 | case O_register: | |
3315 | case O_constant: | |
91d6fa6a | 3316 | if (xg_check_operand (exp->X_add_number, insn->opcode, i)) |
7fa3d080 BW |
3317 | return FALSE; |
3318 | break; | |
3319 | ||
3320 | default: | |
3321 | /* The symbol should have a fixup associated with it. */ | |
9c2799c2 | 3322 | gas_assert (FALSE); |
7fa3d080 BW |
3323 | break; |
3324 | } | |
3325 | } | |
3326 | return TRUE; | |
3327 | } | |
3328 | ||
3329 | ||
3330 | /* This should only be called after we have an initial | |
3331 | estimate of the addresses. */ | |
3332 | ||
3333 | static bfd_boolean | |
3334 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3335 | segT pc_seg, | |
3336 | fragS *pc_frag, | |
3337 | offsetT pc_offset, | |
3338 | long stretch) | |
e0001a05 | 3339 | { |
7fa3d080 BW |
3340 | xtensa_isa isa = xtensa_default_isa; |
3341 | symbolS *symbolP; | |
3342 | fragS *sym_frag; | |
3343 | offsetT target, pc; | |
3344 | uint32 new_offset; | |
3345 | int i; | |
3346 | int n = insn->ntok; | |
e0001a05 | 3347 | |
9c2799c2 | 3348 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 | 3349 | |
7fa3d080 | 3350 | for (i = 0; i < n; ++i) |
e0001a05 | 3351 | { |
91d6fa6a NC |
3352 | const expressionS *exp = &insn->tok[i]; |
3353 | ||
7fa3d080 BW |
3354 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) |
3355 | continue; | |
e0001a05 | 3356 | |
91d6fa6a | 3357 | switch (exp->X_op) |
e0001a05 | 3358 | { |
7fa3d080 BW |
3359 | case O_register: |
3360 | case O_constant: | |
91d6fa6a | 3361 | if (xg_check_operand (exp->X_add_number, insn->opcode, i)) |
7fa3d080 BW |
3362 | return FALSE; |
3363 | break; | |
e0001a05 | 3364 | |
7fa3d080 BW |
3365 | case O_lo16: |
3366 | case O_hi16: | |
3367 | /* Check for the worst case. */ | |
3368 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3369 | return FALSE; | |
3370 | break; | |
e0001a05 | 3371 | |
7fa3d080 | 3372 | case O_symbol: |
7c834684 | 3373 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3374 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3375 | if (pc_frag == 0 |
3376 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3377 | return FALSE; |
e0001a05 | 3378 | |
8e6bc631 BW |
3379 | /* If it is a weak symbol or a symbol in a different section, |
3380 | it cannot be known to fit at assembly time. */ | |
91d6fa6a NC |
3381 | if (S_IS_WEAK (exp->X_add_symbol) |
3382 | || S_GET_SEGMENT (exp->X_add_symbol) != pc_seg) | |
7c834684 | 3383 | { |
8e6bc631 | 3384 | /* For a direct call with --no-longcalls, be optimistic and |
38f9cb7f BW |
3385 | assume it will be in range. If the symbol is weak and |
3386 | undefined, it may remain undefined at link-time, in which | |
3387 | case it will have a zero value and almost certainly be out | |
3388 | of range for a direct call; thus, relax for undefined weak | |
3389 | symbols even if longcalls is not enabled. */ | |
8e6bc631 | 3390 | if (is_direct_call_opcode (insn->opcode) |
38f9cb7f | 3391 | && ! pc_frag->tc_frag_data.use_longcalls |
91d6fa6a NC |
3392 | && (! S_IS_WEAK (exp->X_add_symbol) |
3393 | || S_IS_DEFINED (exp->X_add_symbol))) | |
7c834684 | 3394 | return TRUE; |
7c834684 | 3395 | |
8e6bc631 BW |
3396 | return FALSE; |
3397 | } | |
e0001a05 | 3398 | |
91d6fa6a | 3399 | symbolP = exp->X_add_symbol; |
7fa3d080 | 3400 | sym_frag = symbol_get_frag (symbolP); |
91d6fa6a | 3401 | target = S_GET_VALUE (symbolP) + exp->X_add_number; |
7fa3d080 | 3402 | pc = pc_frag->fr_address + pc_offset; |
e0001a05 | 3403 | |
7fa3d080 BW |
3404 | /* If frag has yet to be reached on this pass, assume it |
3405 | will move by STRETCH just as we did. If this is not so, | |
3406 | it will be because some frag between grows, and that will | |
3407 | force another pass. Beware zero-length frags. There | |
3408 | should be a faster way to do this. */ | |
3409 | ||
3410 | if (stretch != 0 | |
3411 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3412 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3413 | { | |
3414 | target += stretch; | |
3415 | } | |
c138bc38 | 3416 | |
7fa3d080 BW |
3417 | new_offset = target; |
3418 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3419 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3420 | return FALSE; | |
3421 | break; | |
3422 | ||
3423 | default: | |
3424 | /* The symbol should have a fixup associated with it. */ | |
3425 | return FALSE; | |
3426 | } | |
3427 | } | |
3428 | ||
3429 | return TRUE; | |
e0001a05 NC |
3430 | } |
3431 | ||
3432 | ||
43cd72b9 | 3433 | /* Return TRUE on success. */ |
e0001a05 | 3434 | |
7fa3d080 BW |
3435 | static bfd_boolean |
3436 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3437 | { |
3438 | BuildOp *op; | |
3439 | symbolS *sym; | |
3440 | ||
60242db2 | 3441 | tinsn_init (targ); |
b224e962 BW |
3442 | targ->debug_line = insn->debug_line; |
3443 | targ->loc_directive_seen = insn->loc_directive_seen; | |
e0001a05 NC |
3444 | switch (bi->typ) |
3445 | { | |
3446 | case INSTR_INSTR: | |
3447 | op = bi->ops; | |
3448 | targ->opcode = bi->opcode; | |
3449 | targ->insn_type = ITYPE_INSN; | |
3450 | targ->is_specific_opcode = FALSE; | |
3451 | ||
3452 | for (; op != NULL; op = op->next) | |
3453 | { | |
3454 | int op_num = op->op_num; | |
3455 | int op_data = op->op_data; | |
3456 | ||
9c2799c2 | 3457 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3458 | |
3459 | if (targ->ntok <= op_num) | |
3460 | targ->ntok = op_num + 1; | |
3461 | ||
3462 | switch (op->typ) | |
3463 | { | |
3464 | case OP_CONSTANT: | |
3465 | set_expr_const (&targ->tok[op_num], op_data); | |
3466 | break; | |
3467 | case OP_OPERAND: | |
9c2799c2 | 3468 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3469 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3470 | break; | |
19e8f41a BW |
3471 | case OP_FREEREG: |
3472 | if (insn->extra_arg.X_op != O_register) | |
3473 | return FALSE; | |
3474 | copy_expr (&targ->tok[op_num], &insn->extra_arg); | |
3475 | break; | |
e0001a05 NC |
3476 | case OP_LITERAL: |
3477 | sym = get_special_literal_symbol (); | |
3478 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
28dbbc02 BW |
3479 | if (insn->tok[op_data].X_op == O_tlsfunc |
3480 | || insn->tok[op_data].X_op == O_tlsarg) | |
19e8f41a | 3481 | copy_expr (&targ->extra_arg, &insn->tok[op_data]); |
e0001a05 NC |
3482 | break; |
3483 | case OP_LABEL: | |
3484 | sym = get_special_label_symbol (); | |
3485 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3486 | break; | |
43cd72b9 BW |
3487 | case OP_OPERAND_HI16U: |
3488 | case OP_OPERAND_LOW16U: | |
9c2799c2 | 3489 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3490 | if (expr_is_const (&insn->tok[op_data])) |
3491 | { | |
3492 | long val; | |
3493 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3494 | val = xg_apply_userdef_op_fn (op->typ, | |
3495 | targ->tok[op_num]. | |
3496 | X_add_number); | |
3497 | targ->tok[op_num].X_add_number = val; | |
3498 | } | |
3499 | else | |
3500 | { | |
3501 | /* For const16 we can create relocations for these. */ | |
3502 | if (targ->opcode == XTENSA_UNDEFINED | |
3503 | || (targ->opcode != xtensa_const16_opcode)) | |
3504 | return FALSE; | |
9c2799c2 | 3505 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3506 | /* Need to build a O_lo16 or O_hi16. */ |
3507 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3508 | if (targ->tok[op_num].X_op == O_symbol) | |
3509 | { | |
3510 | if (op->typ == OP_OPERAND_HI16U) | |
3511 | targ->tok[op_num].X_op = O_hi16; | |
3512 | else if (op->typ == OP_OPERAND_LOW16U) | |
3513 | targ->tok[op_num].X_op = O_lo16; | |
3514 | else | |
3515 | return FALSE; | |
3516 | } | |
3517 | } | |
3518 | break; | |
e0001a05 NC |
3519 | default: |
3520 | /* currently handles: | |
3521 | OP_OPERAND_LOW8 | |
3522 | OP_OPERAND_HI24S | |
3523 | OP_OPERAND_F32MINUS */ | |
3524 | if (xg_has_userdef_op_fn (op->typ)) | |
3525 | { | |
9c2799c2 | 3526 | gas_assert (op_data < insn->ntok); |
e0001a05 NC |
3527 | if (expr_is_const (&insn->tok[op_data])) |
3528 | { | |
3529 | long val; | |
3530 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3531 | val = xg_apply_userdef_op_fn (op->typ, | |
3532 | targ->tok[op_num]. | |
3533 | X_add_number); | |
3534 | targ->tok[op_num].X_add_number = val; | |
3535 | } | |
3536 | else | |
3537 | return FALSE; /* We cannot use a relocation for this. */ | |
3538 | break; | |
3539 | } | |
9c2799c2 | 3540 | gas_assert (0); |
e0001a05 NC |
3541 | break; |
3542 | } | |
3543 | } | |
3544 | break; | |
3545 | ||
3546 | case INSTR_LITERAL_DEF: | |
3547 | op = bi->ops; | |
3548 | targ->opcode = XTENSA_UNDEFINED; | |
3549 | targ->insn_type = ITYPE_LITERAL; | |
3550 | targ->is_specific_opcode = FALSE; | |
3551 | for (; op != NULL; op = op->next) | |
3552 | { | |
3553 | int op_num = op->op_num; | |
3554 | int op_data = op->op_data; | |
9c2799c2 | 3555 | gas_assert (op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3556 | |
3557 | if (targ->ntok <= op_num) | |
3558 | targ->ntok = op_num + 1; | |
3559 | ||
3560 | switch (op->typ) | |
3561 | { | |
3562 | case OP_OPERAND: | |
9c2799c2 | 3563 | gas_assert (op_data < insn->ntok); |
43cd72b9 BW |
3564 | /* We can only pass resolvable literals through. */ |
3565 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3566 | return FALSE; | |
e0001a05 NC |
3567 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3568 | break; | |
3569 | case OP_LITERAL: | |
3570 | case OP_CONSTANT: | |
3571 | case OP_LABEL: | |
3572 | default: | |
9c2799c2 | 3573 | gas_assert (0); |
e0001a05 NC |
3574 | break; |
3575 | } | |
3576 | } | |
3577 | break; | |
3578 | ||
3579 | case INSTR_LABEL_DEF: | |
3580 | op = bi->ops; | |
3581 | targ->opcode = XTENSA_UNDEFINED; | |
3582 | targ->insn_type = ITYPE_LABEL; | |
3583 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3584 | /* Literal with no ops is a label? */ |
9c2799c2 | 3585 | gas_assert (op == NULL); |
e0001a05 NC |
3586 | break; |
3587 | ||
3588 | default: | |
9c2799c2 | 3589 | gas_assert (0); |
e0001a05 NC |
3590 | } |
3591 | ||
3592 | return TRUE; | |
3593 | } | |
3594 | ||
3595 | ||
43cd72b9 | 3596 | /* Return TRUE on success. */ |
e0001a05 | 3597 | |
7fa3d080 BW |
3598 | static bfd_boolean |
3599 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3600 | { |
3601 | for (; bi != NULL; bi = bi->next) | |
3602 | { | |
3603 | TInsn *next_insn = istack_push_space (istack); | |
3604 | ||
3605 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3606 | return FALSE; | |
3607 | } | |
3608 | return TRUE; | |
3609 | } | |
3610 | ||
3611 | ||
43cd72b9 | 3612 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3613 | |
7fa3d080 BW |
3614 | static bfd_boolean |
3615 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3616 | { |
3617 | int stack_size = istack->ninsn; | |
3618 | int steps_taken = 0; | |
43cd72b9 | 3619 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3620 | TransitionList *l; |
3621 | ||
9c2799c2 NC |
3622 | gas_assert (insn->insn_type == ITYPE_INSN); |
3623 | gas_assert (insn->opcode < table->num_opcodes); | |
e0001a05 NC |
3624 | |
3625 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3626 | { | |
3627 | TransitionRule *rule = l->rule; | |
3628 | ||
3629 | if (xg_instruction_matches_rule (insn, rule)) | |
3630 | { | |
3631 | if (lateral_steps == steps_taken) | |
3632 | { | |
3633 | int i; | |
3634 | ||
3635 | /* This is it. Expand the rule to the stack. */ | |
3636 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3637 | return FALSE; | |
3638 | ||
3639 | /* Check to see if it fits. */ | |
3640 | for (i = stack_size; i < istack->ninsn; i++) | |
3641 | { | |
91d6fa6a | 3642 | TInsn *tinsn = &istack->insn[i]; |
e0001a05 | 3643 | |
91d6fa6a NC |
3644 | if (tinsn->insn_type == ITYPE_INSN |
3645 | && !tinsn_has_symbolic_operands (tinsn) | |
3646 | && !xg_immeds_fit (tinsn)) | |
e0001a05 NC |
3647 | { |
3648 | istack->ninsn = stack_size; | |
3649 | return FALSE; | |
3650 | } | |
3651 | } | |
3652 | return TRUE; | |
3653 | } | |
3654 | steps_taken++; | |
3655 | } | |
3656 | } | |
3657 | return FALSE; | |
3658 | } | |
3659 | ||
43cd72b9 | 3660 | \f |
43cd72b9 | 3661 | /* Relax the assembly instruction at least "min_steps". |
b81bf389 BW |
3662 | Return the number of steps taken. |
3663 | ||
3664 | For relaxation to correctly terminate, every relaxation chain must | |
3665 | terminate in one of two ways: | |
3666 | ||
3667 | 1. If the chain from one instruction to the next consists entirely of | |
3668 | single instructions, then the chain *must* handle all possible | |
3669 | immediates without failing. It must not ever fail because an | |
3670 | immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation | |
3671 | chain is one example. L32R loads 32 bits, and there cannot be an | |
3672 | immediate larger than 32 bits, so it satisfies this condition. | |
3673 | Single instruction relaxation chains are as defined by | |
3674 | xg_is_single_relaxable_instruction. | |
3675 | ||
3676 | 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., | |
3677 | BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J | |
3678 | ||
3679 | Strictly speaking, in most cases you can violate condition 1 and be OK | |
3680 | -- in particular when the last two instructions have the same single | |
3681 | size. But nevertheless, you should guarantee the above two conditions. | |
3682 | ||
3683 | We could fix this so that single-instruction expansions correctly | |
3684 | terminate when they can't handle the range, but the error messages are | |
3685 | worse, and it actually turns out that in every case but one (18-bit wide | |
3686 | branches), you need a multi-instruction expansion to get the full range | |
3687 | anyway. And because 18-bit branches are handled identically to 15-bit | |
3688 | branches, there isn't any point in changing it. */ | |
e0001a05 | 3689 | |
7fa3d080 BW |
3690 | static int |
3691 | xg_assembly_relax (IStack *istack, | |
3692 | TInsn *insn, | |
3693 | segT pc_seg, | |
3694 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3695 | offsetT pc_offset, /* offset in fragment */ | |
3696 | int min_steps, /* minimum conversion steps */ | |
3697 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3698 | { |
3699 | int steps_taken = 0; | |
3700 | ||
b81bf389 BW |
3701 | /* Some of its immeds don't fit. Try to build a relaxed version. |
3702 | This may go through a couple of stages of single instruction | |
3703 | transformations before we get there. */ | |
e0001a05 NC |
3704 | |
3705 | TInsn single_target; | |
3706 | TInsn current_insn; | |
3707 | int lateral_steps = 0; | |
3708 | int istack_size = istack->ninsn; | |
3709 | ||
3710 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3711 | && steps_taken >= min_steps) | |
3712 | { | |
3713 | istack_push (istack, insn); | |
3714 | return steps_taken; | |
3715 | } | |
43cd72b9 | 3716 | current_insn = *insn; |
e0001a05 | 3717 | |
7c834684 | 3718 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3719 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3720 | { |
21af2bbd | 3721 | steps_taken++; |
e0001a05 NC |
3722 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3723 | stretch)) | |
3724 | { | |
e0001a05 NC |
3725 | if (steps_taken >= min_steps) |
3726 | { | |
3727 | istack_push (istack, &single_target); | |
3728 | return steps_taken; | |
3729 | } | |
3730 | } | |
43cd72b9 | 3731 | current_insn = single_target; |
e0001a05 NC |
3732 | } |
3733 | ||
3734 | /* Now check for a multi-instruction expansion. */ | |
3735 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3736 | { | |
3737 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3738 | stretch)) | |
3739 | { | |
3740 | if (steps_taken >= min_steps) | |
3741 | { | |
3742 | istack_push (istack, ¤t_insn); | |
3743 | return steps_taken; | |
3744 | } | |
3745 | } | |
3746 | steps_taken++; | |
3747 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3748 | { | |
3749 | if (steps_taken >= min_steps) | |
3750 | return steps_taken; | |
3751 | } | |
3752 | lateral_steps++; | |
3753 | istack->ninsn = istack_size; | |
3754 | } | |
3755 | ||
3756 | /* It's not going to work -- use the original. */ | |
3757 | istack_push (istack, insn); | |
3758 | return steps_taken; | |
3759 | } | |
3760 | ||
3761 | ||
7fa3d080 BW |
3762 | static void |
3763 | xg_finish_frag (char *last_insn, | |
3764 | enum xtensa_relax_statesE frag_state, | |
3765 | enum xtensa_relax_statesE slot0_state, | |
3766 | int max_growth, | |
3767 | bfd_boolean is_insn) | |
e0001a05 NC |
3768 | { |
3769 | /* Finish off this fragment so that it has at LEAST the desired | |
3770 | max_growth. If it doesn't fit in this fragment, close this one | |
3771 | and start a new one. In either case, return a pointer to the | |
3772 | beginning of the growth area. */ | |
3773 | ||
3774 | fragS *old_frag; | |
43cd72b9 | 3775 | |
542f8b94 | 3776 | frag_grow (max_growth); |
e0001a05 NC |
3777 | old_frag = frag_now; |
3778 | ||
3779 | frag_now->fr_opcode = last_insn; | |
3780 | if (is_insn) | |
3781 | frag_now->tc_frag_data.is_insn = TRUE; | |
3782 | ||
3783 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3784 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3785 | ||
3786 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3787 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3788 | |
3789 | /* Just to make sure that we did not split it up. */ | |
9c2799c2 | 3790 | gas_assert (old_frag->fr_next == frag_now); |
e0001a05 NC |
3791 | } |
3792 | ||
3793 | ||
7fa3d080 BW |
3794 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3795 | ||
3796 | static bfd_boolean | |
3797 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3798 | { | |
3799 | if (fragP == NULL) | |
3800 | return FALSE; | |
3801 | ||
3802 | for (; fragP; fragP = fragP->fr_next) | |
3803 | { | |
3804 | if (fragP == target) | |
3805 | return TRUE; | |
3806 | if (fragP->fr_fix != 0) | |
3807 | return FALSE; | |
3808 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3809 | return FALSE; | |
3810 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3811 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3812 | return FALSE; | |
3813 | if (fragP->fr_type == rs_space) | |
3814 | return FALSE; | |
3815 | } | |
3816 | return FALSE; | |
3817 | } | |
3818 | ||
3819 | ||
e0001a05 | 3820 | static bfd_boolean |
7fa3d080 | 3821 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3822 | { |
3823 | xtensa_isa isa = xtensa_default_isa; | |
3824 | int i; | |
43cd72b9 | 3825 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3826 | int target_op = -1; |
3827 | symbolS *sym; | |
3828 | fragS *target_frag; | |
3829 | ||
64b607e6 BW |
3830 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3831 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
e0001a05 NC |
3832 | return FALSE; |
3833 | ||
3834 | for (i = 0; i < num_ops; i++) | |
3835 | { | |
43cd72b9 | 3836 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3837 | { |
3838 | target_op = i; | |
3839 | break; | |
3840 | } | |
3841 | } | |
3842 | if (target_op == -1) | |
3843 | return FALSE; | |
3844 | ||
3845 | if (insn->ntok <= target_op) | |
3846 | return FALSE; | |
3847 | ||
3848 | if (insn->tok[target_op].X_op != O_symbol) | |
3849 | return FALSE; | |
3850 | ||
3851 | sym = insn->tok[target_op].X_add_symbol; | |
3852 | if (sym == NULL) | |
3853 | return FALSE; | |
3854 | ||
3855 | if (insn->tok[target_op].X_add_number != 0) | |
3856 | return FALSE; | |
3857 | ||
3858 | target_frag = symbol_get_frag (sym); | |
3859 | if (target_frag == NULL) | |
3860 | return FALSE; | |
3861 | ||
c138bc38 | 3862 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3863 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3864 | return TRUE; | |
3865 | ||
3866 | return FALSE; | |
3867 | } | |
3868 | ||
3869 | ||
3870 | static void | |
7fa3d080 | 3871 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3872 | { |
3873 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3874 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3875 | |
7fa3d080 BW |
3876 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3877 | { | |
3878 | int i = 1; | |
3879 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3880 | && insn->tok[i].X_op == O_symbol) | |
3881 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3882 | return; | |
3883 | } | |
e0001a05 | 3884 | |
7fa3d080 BW |
3885 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3886 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3887 | { |
7fa3d080 BW |
3888 | int i; |
3889 | ||
3890 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3891 | { | |
3892 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3893 | && insn->tok[i].X_op == O_symbol) | |
3894 | { | |
3895 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3896 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3897 | if (S_IS_DEFINED (sym)) | |
3898 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3899 | } | |
3900 | } | |
e0001a05 | 3901 | } |
e0001a05 NC |
3902 | } |
3903 | ||
3904 | ||
43cd72b9 | 3905 | /* Return FALSE if no error. */ |
e0001a05 | 3906 | |
7fa3d080 BW |
3907 | static bfd_boolean |
3908 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3909 | { |
3910 | int num_ops = 0; | |
3911 | BuildOp *b_op; | |
3912 | ||
3913 | switch (instr_spec->typ) | |
3914 | { | |
3915 | case INSTR_INSTR: | |
3916 | new_insn->insn_type = ITYPE_INSN; | |
3917 | new_insn->opcode = instr_spec->opcode; | |
e0001a05 NC |
3918 | break; |
3919 | case INSTR_LITERAL_DEF: | |
3920 | new_insn->insn_type = ITYPE_LITERAL; | |
3921 | new_insn->opcode = XTENSA_UNDEFINED; | |
e0001a05 NC |
3922 | break; |
3923 | case INSTR_LABEL_DEF: | |
b224e962 | 3924 | abort (); |
e0001a05 | 3925 | } |
b224e962 BW |
3926 | new_insn->is_specific_opcode = FALSE; |
3927 | new_insn->debug_line = old_insn->debug_line; | |
3928 | new_insn->loc_directive_seen = old_insn->loc_directive_seen; | |
e0001a05 NC |
3929 | |
3930 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3931 | { | |
3932 | expressionS *exp; | |
3933 | const expressionS *src_exp; | |
3934 | ||
3935 | num_ops++; | |
3936 | switch (b_op->typ) | |
3937 | { | |
3938 | case OP_CONSTANT: | |
3939 | /* The expression must be the constant. */ | |
9c2799c2 | 3940 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
e0001a05 NC |
3941 | exp = &new_insn->tok[b_op->op_num]; |
3942 | set_expr_const (exp, b_op->op_data); | |
3943 | break; | |
3944 | ||
3945 | case OP_OPERAND: | |
9c2799c2 NC |
3946 | gas_assert (b_op->op_num < MAX_INSN_ARGS); |
3947 | gas_assert (b_op->op_data < (unsigned) old_insn->ntok); | |
e0001a05 NC |
3948 | src_exp = &old_insn->tok[b_op->op_data]; |
3949 | exp = &new_insn->tok[b_op->op_num]; | |
3950 | copy_expr (exp, src_exp); | |
3951 | break; | |
3952 | ||
3953 | case OP_LITERAL: | |
3954 | case OP_LABEL: | |
3955 | as_bad (_("can't handle generation of literal/labels yet")); | |
9c2799c2 | 3956 | gas_assert (0); |
e0001a05 NC |
3957 | |
3958 | default: | |
3959 | as_bad (_("can't handle undefined OP TYPE")); | |
9c2799c2 | 3960 | gas_assert (0); |
e0001a05 NC |
3961 | } |
3962 | } | |
3963 | ||
3964 | new_insn->ntok = num_ops; | |
3965 | return FALSE; | |
3966 | } | |
3967 | ||
3968 | ||
43cd72b9 | 3969 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3970 | |
7fa3d080 BW |
3971 | static bfd_boolean |
3972 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3973 | { |
43cd72b9 | 3974 | TransitionRule *rule; |
e0001a05 | 3975 | BuildInstr *insn_spec; |
43cd72b9 BW |
3976 | |
3977 | if (old_insn->is_specific_opcode || !density_supported) | |
3978 | return FALSE; | |
3979 | ||
3980 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3981 | if (rule == NULL) |
3982 | return FALSE; | |
3983 | ||
3984 | insn_spec = rule->to_instr; | |
3985 | /* There should only be one. */ | |
9c2799c2 NC |
3986 | gas_assert (insn_spec != NULL); |
3987 | gas_assert (insn_spec->next == NULL); | |
e0001a05 NC |
3988 | if (insn_spec->next != NULL) |
3989 | return FALSE; | |
3990 | ||
3991 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3992 | ||
3993 | return TRUE; | |
3994 | } | |
3995 | ||
3996 | ||
3997 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3998 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
3999 | tokens into the stack or relax it and place multiple |
4000 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
4001 | |
4002 | static bfd_boolean | |
7fa3d080 | 4003 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
4004 | { |
4005 | int noperands; | |
4006 | TInsn new_insn; | |
7c834684 BW |
4007 | bfd_boolean do_expand; |
4008 | ||
60242db2 | 4009 | tinsn_init (&new_insn); |
e0001a05 | 4010 | |
43cd72b9 BW |
4011 | /* Narrow it if we can. xg_simplify_insn now does all the |
4012 | appropriate checking (e.g., for the density option). */ | |
4013 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
4014 | orig_insn = &new_insn; | |
e0001a05 | 4015 | |
43cd72b9 BW |
4016 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
4017 | orig_insn->opcode); | |
e0001a05 NC |
4018 | if (orig_insn->ntok < noperands) |
4019 | { | |
992a06ee AM |
4020 | as_bad (ngettext ("found %d operand for '%s': Expected %d", |
4021 | "found %d operands for '%s': Expected %d", | |
4022 | orig_insn->ntok), | |
e0001a05 NC |
4023 | orig_insn->ntok, |
4024 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
4025 | noperands); | |
4026 | return TRUE; | |
4027 | } | |
4028 | if (orig_insn->ntok > noperands) | |
992a06ee AM |
4029 | as_warn (ngettext ("found %d operand for '%s': Expected %d", |
4030 | "found %d operands for '%s': Expected %d", | |
4031 | orig_insn->ntok), | |
e0001a05 NC |
4032 | orig_insn->ntok, |
4033 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
4034 | noperands); | |
4035 | ||
43cd72b9 | 4036 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 4037 | are too many, just cut out the extras here. */ |
e0001a05 NC |
4038 | orig_insn->ntok = noperands; |
4039 | ||
e0001a05 NC |
4040 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
4041 | return TRUE; | |
4042 | ||
d12f9798 BW |
4043 | /* Special case for extui opcode which has constraints not handled |
4044 | by the ordinary operand encoding checks. The number of operands | |
4045 | and related syntax issues have already been checked. */ | |
4046 | if (orig_insn->opcode == xtensa_extui_opcode) | |
4047 | { | |
4048 | int shiftimm = orig_insn->tok[2].X_add_number; | |
4049 | int maskimm = orig_insn->tok[3].X_add_number; | |
4050 | if (shiftimm + maskimm > 32) | |
4051 | { | |
4052 | as_bad (_("immediate operands sum to greater than 32")); | |
4053 | return TRUE; | |
4054 | } | |
4055 | } | |
4056 | ||
7c834684 BW |
4057 | /* If the instruction will definitely need to be relaxed, it is better |
4058 | to expand it now for better scheduling. Decide whether to expand | |
4059 | now.... */ | |
4060 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
4061 | ||
4062 | /* Calls should be expanded to longcalls only in the backend relaxation | |
4063 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
4064 | adjacent. */ | |
4065 | if (is_direct_call_opcode (orig_insn->opcode)) | |
4066 | do_expand = FALSE; | |
e0001a05 NC |
4067 | |
4068 | if (tinsn_has_symbolic_operands (orig_insn)) | |
4069 | { | |
7c834684 BW |
4070 | /* The values of symbolic operands are not known yet, so only expand |
4071 | now if an operand is "complex" (e.g., difference of symbols) and | |
4072 | will have to be stored as a literal regardless of the value. */ | |
4073 | if (!tinsn_has_complex_operands (orig_insn)) | |
4074 | do_expand = FALSE; | |
e0001a05 | 4075 | } |
7c834684 BW |
4076 | else if (xg_immeds_fit (orig_insn)) |
4077 | do_expand = FALSE; | |
4078 | ||
4079 | if (do_expand) | |
4080 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 4081 | else |
7c834684 | 4082 | istack_push (istack, orig_insn); |
e0001a05 | 4083 | |
e0001a05 NC |
4084 | return FALSE; |
4085 | } | |
4086 | ||
4087 | ||
7fa3d080 | 4088 | /* Return TRUE if the section flags are marked linkonce |
74869ac7 BW |
4089 | or the name is .gnu.linkonce.*. */ |
4090 | ||
4091 | static int linkonce_len = sizeof (".gnu.linkonce.") - 1; | |
7fa3d080 BW |
4092 | |
4093 | static bfd_boolean | |
4094 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
4095 | { | |
4096 | flagword flags, link_once_flags; | |
4097 | ||
4098 | flags = bfd_get_section_flags (abfd, sec); | |
4099 | link_once_flags = (flags & SEC_LINK_ONCE); | |
4100 | ||
4101 | /* Flags might not be set yet. */ | |
74869ac7 BW |
4102 | if (!link_once_flags |
4103 | && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) | |
4104 | link_once_flags = SEC_LINK_ONCE; | |
7fa3d080 | 4105 | |
7fa3d080 BW |
4106 | return (link_once_flags != 0); |
4107 | } | |
4108 | ||
4109 | ||
4110 | static void | |
4111 | xtensa_add_literal_sym (symbolS *sym) | |
4112 | { | |
4113 | sym_list *l; | |
4114 | ||
325801bd | 4115 | l = XNEW (sym_list); |
7fa3d080 BW |
4116 | l->sym = sym; |
4117 | l->next = literal_syms; | |
4118 | literal_syms = l; | |
4119 | } | |
4120 | ||
4121 | ||
4122 | static symbolS * | |
4123 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
4124 | { | |
4125 | static int lit_num = 0; | |
4126 | static char name[256]; | |
4127 | symbolS *symbolP; | |
4128 | ||
4129 | sprintf (name, ".L_lit_sym%d", lit_num); | |
4130 | ||
4131 | /* Create a local symbol. If it is in a linkonce section, we have to | |
4132 | be careful to make sure that if it is used in a relocation that the | |
4133 | symbol will be in the output file. */ | |
4134 | if (get_is_linkonce_section (stdoutput, sec)) | |
4135 | { | |
4136 | symbolP = symbol_new (name, sec, 0, frag); | |
4137 | S_CLEAR_EXTERNAL (symbolP); | |
4138 | /* symbolP->local = 1; */ | |
4139 | } | |
4140 | else | |
4141 | symbolP = symbol_new (name, sec, 0, frag); | |
4142 | ||
4143 | xtensa_add_literal_sym (symbolP); | |
4144 | ||
7fa3d080 BW |
4145 | lit_num++; |
4146 | return symbolP; | |
4147 | } | |
4148 | ||
4149 | ||
e0001a05 NC |
4150 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
4151 | ||
7fa3d080 BW |
4152 | static symbolS * |
4153 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
4154 | { |
4155 | emit_state state; | |
4156 | symbolS *lit_sym = NULL; | |
bbdd25a8 | 4157 | bfd_reloc_code_real_type reloc; |
1bbb5f21 | 4158 | bfd_boolean pcrel = FALSE; |
bbdd25a8 | 4159 | char *p; |
e0001a05 NC |
4160 | |
4161 | /* size = 4 for L32R. It could easily be larger when we move to | |
4162 | larger constants. Add a parameter later. */ | |
4163 | offsetT litsize = 4; | |
4164 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4165 | expressionS saved_loc; | |
43cd72b9 BW |
4166 | expressionS * emit_val; |
4167 | ||
e0001a05 NC |
4168 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4169 | ||
9c2799c2 NC |
4170 | gas_assert (insn->insn_type == ITYPE_LITERAL); |
4171 | gas_assert (insn->ntok == 1); /* must be only one token here */ | |
e0001a05 NC |
4172 | |
4173 | xtensa_switch_to_literal_fragment (&state); | |
4174 | ||
43cd72b9 BW |
4175 | emit_val = &insn->tok[0]; |
4176 | if (emit_val->X_op == O_big) | |
4177 | { | |
4178 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4179 | if (size > litsize) | |
4180 | { | |
4181 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4182 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4183 | _("invalid immediate")); |
4184 | xtensa_restore_emit_state (&state); | |
4185 | return NULL; | |
4186 | } | |
4187 | } | |
4188 | ||
e0001a05 NC |
4189 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4190 | literals done with this function have a frag to themselves. That's | |
4191 | important for the way text section literals work. */ | |
4192 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4193 | record_alignment (now_seg, litalign); |
e0001a05 | 4194 | |
bbdd25a8 | 4195 | switch (emit_val->X_op) |
43cd72b9 | 4196 | { |
1bbb5f21 BW |
4197 | case O_pcrel: |
4198 | pcrel = TRUE; | |
4199 | /* fall through */ | |
bbdd25a8 | 4200 | case O_pltrel: |
28dbbc02 BW |
4201 | case O_tlsfunc: |
4202 | case O_tlsarg: | |
4203 | case O_tpoff: | |
4204 | case O_dtpoff: | |
bbdd25a8 | 4205 | p = frag_more (litsize); |
43cd72b9 | 4206 | xtensa_set_frag_assembly_state (frag_now); |
28dbbc02 | 4207 | reloc = map_operator_to_reloc (emit_val->X_op, TRUE); |
43cd72b9 BW |
4208 | if (emit_val->X_add_symbol) |
4209 | emit_val->X_op = O_symbol; | |
4210 | else | |
4211 | emit_val->X_op = O_constant; | |
4212 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1bbb5f21 | 4213 | litsize, emit_val, pcrel, reloc); |
bbdd25a8 BW |
4214 | break; |
4215 | ||
4216 | default: | |
4217 | emit_expr (emit_val, litsize); | |
4218 | break; | |
43cd72b9 | 4219 | } |
e0001a05 | 4220 | |
9c2799c2 | 4221 | gas_assert (frag_now->tc_frag_data.literal_frag == NULL); |
e0001a05 NC |
4222 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); |
4223 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4224 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4225 | |
4226 | /* Go back. */ | |
4227 | xtensa_restore_emit_state (&state); | |
4228 | return lit_sym; | |
4229 | } | |
4230 | ||
4231 | ||
4232 | static void | |
7fa3d080 | 4233 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4234 | { |
4235 | emit_state state; | |
43cd72b9 | 4236 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4237 | takes effect if something is placed here. */ |
4238 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4239 | fragS *lit_saved_frag; | |
4240 | ||
9c2799c2 | 4241 | gas_assert (size % 4 == 0); |
e0001a05 NC |
4242 | |
4243 | xtensa_switch_to_literal_fragment (&state); | |
4244 | ||
4245 | /* Force a 4-byte align here. */ | |
4246 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4247 | record_alignment (now_seg, litalign); |
e0001a05 | 4248 | |
542f8b94 | 4249 | frag_grow (size); |
e0001a05 NC |
4250 | |
4251 | lit_saved_frag = frag_now; | |
4252 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4253 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
43cd72b9 | 4254 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4255 | |
4256 | /* Go back. */ | |
4257 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4258 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4259 | } |
4260 | ||
4261 | ||
e0001a05 | 4262 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4263 | Return TRUE on success. */ |
e0001a05 | 4264 | |
7fa3d080 BW |
4265 | static bfd_boolean |
4266 | xg_add_opcode_fix (TInsn *tinsn, | |
4267 | int opnum, | |
4268 | xtensa_format fmt, | |
4269 | int slot, | |
91d6fa6a | 4270 | expressionS *exp, |
7fa3d080 BW |
4271 | fragS *fragP, |
4272 | offsetT offset) | |
43cd72b9 BW |
4273 | { |
4274 | xtensa_opcode opcode = tinsn->opcode; | |
4275 | bfd_reloc_code_real_type reloc; | |
4276 | reloc_howto_type *howto; | |
4277 | int fmt_length; | |
e0001a05 NC |
4278 | fixS *the_fix; |
4279 | ||
43cd72b9 BW |
4280 | reloc = BFD_RELOC_NONE; |
4281 | ||
4282 | /* First try the special cases for "alternate" relocs. */ | |
4283 | if (opcode == xtensa_l32r_opcode) | |
4284 | { | |
4285 | if (fragP->tc_frag_data.use_absolute_literals) | |
4286 | reloc = encode_alt_reloc (slot); | |
4287 | } | |
4288 | else if (opcode == xtensa_const16_opcode) | |
4289 | { | |
91d6fa6a | 4290 | if (exp->X_op == O_lo16) |
43cd72b9 BW |
4291 | { |
4292 | reloc = encode_reloc (slot); | |
91d6fa6a | 4293 | exp->X_op = O_symbol; |
43cd72b9 | 4294 | } |
91d6fa6a | 4295 | else if (exp->X_op == O_hi16) |
43cd72b9 BW |
4296 | { |
4297 | reloc = encode_alt_reloc (slot); | |
91d6fa6a | 4298 | exp->X_op = O_symbol; |
43cd72b9 BW |
4299 | } |
4300 | } | |
4301 | ||
4302 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4303 | { |
43cd72b9 | 4304 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4305 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4306 | return FALSE; |
4307 | } | |
4308 | ||
43cd72b9 BW |
4309 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4310 | into the symbol table where the generic portions of the assembler | |
4311 | won't know what to do with them. */ | |
91d6fa6a | 4312 | if (exp->X_op == O_lo16 || exp->X_op == O_hi16) |
43cd72b9 BW |
4313 | { |
4314 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4315 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4316 | return FALSE; |
4317 | } | |
4318 | ||
4319 | /* Next try the generic relocs. */ | |
4320 | if (reloc == BFD_RELOC_NONE) | |
4321 | reloc = encode_reloc (slot); | |
4322 | if (reloc == BFD_RELOC_NONE) | |
4323 | { | |
4324 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4325 | return FALSE; | |
4326 | } | |
e0001a05 | 4327 | |
43cd72b9 | 4328 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4329 | if (!howto) |
4330 | { | |
43cd72b9 | 4331 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4332 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4333 | return FALSE; | |
4334 | } | |
4335 | ||
43cd72b9 | 4336 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
91d6fa6a | 4337 | the_fix = fix_new_exp (fragP, offset, fmt_length, exp, |
e0001a05 | 4338 | howto->pc_relative, reloc); |
d9740523 | 4339 | the_fix->fx_no_overflow = 1; |
91d6fa6a NC |
4340 | the_fix->tc_fix_data.X_add_symbol = exp->X_add_symbol; |
4341 | the_fix->tc_fix_data.X_add_number = exp->X_add_number; | |
7fa3d080 | 4342 | the_fix->tc_fix_data.slot = slot; |
c138bc38 | 4343 | |
7fa3d080 BW |
4344 | return TRUE; |
4345 | } | |
4346 | ||
4347 | ||
4348 | static bfd_boolean | |
4349 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4350 | char *buf, |
4351 | fragS *fragP, | |
4352 | offsetT offset, | |
4353 | bfd_boolean build_fix) | |
4354 | { | |
4355 | static xtensa_insnbuf insnbuf = NULL; | |
4356 | bfd_boolean has_symbolic_immed = FALSE; | |
4357 | bfd_boolean ok = TRUE; | |
b2d179be | 4358 | |
7fa3d080 BW |
4359 | if (!insnbuf) |
4360 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4361 | ||
4362 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4363 | if (has_symbolic_immed && build_fix) | |
4364 | { | |
4365 | /* Add a fixup. */ | |
b2d179be BW |
4366 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4367 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4368 | int opnum = get_relaxable_immed (tinsn->opcode); |
4369 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4370 | |
b2d179be | 4371 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4372 | ok = FALSE; |
4373 | } | |
4374 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4375 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4376 | (unsigned char *) buf, 0); | |
7fa3d080 | 4377 | return ok; |
e0001a05 NC |
4378 | } |
4379 | ||
4380 | ||
7fa3d080 BW |
4381 | static void |
4382 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4383 | { |
4384 | symbolS *sym = get_special_literal_symbol (); | |
4385 | int i; | |
4386 | if (lit_sym == 0) | |
4387 | return; | |
9c2799c2 | 4388 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
4389 | for (i = 0; i < insn->ntok; i++) |
4390 | if (insn->tok[i].X_add_symbol == sym) | |
4391 | insn->tok[i].X_add_symbol = lit_sym; | |
4392 | ||
4393 | } | |
4394 | ||
4395 | ||
7fa3d080 BW |
4396 | static void |
4397 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4398 | { |
4399 | symbolS *sym = get_special_label_symbol (); | |
4400 | int i; | |
e0001a05 NC |
4401 | for (i = 0; i < insn->ntok; i++) |
4402 | if (insn->tok[i].X_add_symbol == sym) | |
4403 | insn->tok[i].X_add_symbol = label_sym; | |
4404 | ||
4405 | } | |
4406 | ||
4407 | ||
43cd72b9 | 4408 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4409 | integer register. */ |
4410 | ||
4411 | static bfd_boolean | |
7fa3d080 | 4412 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4413 | { |
4414 | int i; | |
4415 | int num_ops; | |
4416 | xtensa_isa isa = xtensa_default_isa; | |
4417 | ||
43cd72b9 | 4418 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4419 | |
4420 | for (i = 0; i < num_ops; i++) | |
4421 | { | |
43cd72b9 BW |
4422 | char inout; |
4423 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4424 | if ((inout == 'o' || inout == 'm') | |
4425 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4426 | { |
43cd72b9 BW |
4427 | xtensa_regfile opnd_rf = |
4428 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4429 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4430 | { |
4431 | if ((insn->tok[i].X_op == O_register) | |
4432 | && (insn->tok[i].X_add_number == regnum)) | |
4433 | return TRUE; | |
4434 | } | |
4435 | } | |
4436 | } | |
4437 | return FALSE; | |
4438 | } | |
4439 | ||
4440 | ||
4441 | static bfd_boolean | |
7fa3d080 | 4442 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4443 | { |
4444 | xtensa_opcode opcode = tinsn->opcode; | |
4445 | ||
4446 | if (opcode == XTENSA_UNDEFINED) | |
4447 | return FALSE; | |
4448 | ||
4449 | if (opcode == xtensa_call0_opcode | |
4450 | || opcode == xtensa_callx0_opcode | |
4451 | || opcode == xtensa_call4_opcode | |
4452 | || opcode == xtensa_callx4_opcode | |
4453 | || opcode == xtensa_call8_opcode | |
4454 | || opcode == xtensa_callx8_opcode | |
4455 | || opcode == xtensa_call12_opcode | |
4456 | || opcode == xtensa_callx12_opcode | |
4457 | || opcode == xtensa_isync_opcode | |
4458 | || opcode == xtensa_ret_opcode | |
4459 | || opcode == xtensa_ret_n_opcode | |
4460 | || opcode == xtensa_retw_opcode | |
4461 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4462 | || opcode == xtensa_waiti_opcode |
4463 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4464 | return TRUE; |
c138bc38 | 4465 | |
e0001a05 NC |
4466 | return FALSE; |
4467 | } | |
4468 | ||
4469 | ||
4470 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4471 | This allows the debugger to add unaligned labels. | |
4472 | Also, the assembler generates stabs labels that need | |
4473 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4474 | ||
7fa3d080 BW |
4475 | static bfd_boolean |
4476 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4477 | { |
4478 | const char *name = S_GET_NAME (sym); | |
4479 | static size_t fake_size = 0; | |
4480 | ||
4481 | if (name | |
4482 | && name[0] == '.' | |
4483 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4484 | return TRUE; | |
4485 | ||
4486 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4487 | if (fake_size == 0) | |
4488 | fake_size = strlen (FAKE_LABEL_NAME); | |
4489 | ||
43cd72b9 | 4490 | if (name |
e0001a05 NC |
4491 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4492 | && (name[fake_size] == 'F' | |
4493 | || name[fake_size] == 'L' | |
4494 | || (name[fake_size] == 'e' | |
4495 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4496 | return TRUE; | |
4497 | ||
4498 | return FALSE; | |
4499 | } | |
4500 | ||
4501 | ||
7fa3d080 BW |
4502 | static fragS * |
4503 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4504 | { |
4505 | fragS *next_fragP = fragP->fr_next; | |
4506 | ||
c138bc38 | 4507 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4508 | So we have to skip until we find something legit. */ |
4509 | while (next_fragP && next_fragP->fr_fix == 0) | |
4510 | next_fragP = next_fragP->fr_next; | |
4511 | ||
4512 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4513 | return NULL; | |
4514 | ||
4515 | return next_fragP; | |
4516 | } | |
4517 | ||
4518 | ||
43cd72b9 | 4519 | static bfd_boolean |
7fa3d080 | 4520 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4521 | { |
4522 | xtensa_opcode out_opcode; | |
4523 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4524 | ||
4525 | if (next_fragP == NULL) | |
4526 | return FALSE; | |
4527 | ||
4528 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4529 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4530 | { | |
4531 | *opcode = out_opcode; | |
4532 | return TRUE; | |
4533 | } | |
4534 | return FALSE; | |
4535 | } | |
4536 | ||
4537 | ||
4538 | static int | |
7fa3d080 | 4539 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4540 | { |
e0001a05 NC |
4541 | static xtensa_insnbuf insnbuf = NULL; |
4542 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4543 | xtensa_format fmt; |
c138bc38 | 4544 | int fmt_size; |
e0001a05 NC |
4545 | |
4546 | if (!insnbuf) | |
4547 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4548 | ||
43cd72b9 BW |
4549 | if (fragP == NULL) |
4550 | return XTENSA_UNDEFINED; | |
4551 | ||
d77b99c9 BW |
4552 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4553 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4554 | |
4555 | fmt = xtensa_format_decode (isa, insnbuf); | |
4556 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4557 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4558 | fmt_size = xtensa_format_length (isa, fmt); |
4559 | ||
4560 | /* If the next format won't be changing due to relaxation, just | |
4561 | return the length of the first format. */ | |
4562 | if (fragP->fr_opcode != fragP->fr_literal) | |
4563 | return fmt_size; | |
4564 | ||
c138bc38 | 4565 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4566 | multi-slot instruction, we will return the more conservative |
4567 | number. This works because alignment on bigger instructions | |
4568 | is more restrictive than alignment on smaller instructions. | |
4569 | This is more conservative than we would like, but it happens | |
4570 | infrequently. */ | |
4571 | ||
4572 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4573 | return fmt_size; | |
4574 | ||
4575 | /* If we aren't doing one of our own relaxations or it isn't | |
4576 | slot-based, then the insn size won't change. */ | |
4577 | if (fragP->fr_type != rs_machine_dependent) | |
4578 | return fmt_size; | |
4579 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4580 | return fmt_size; | |
4581 | ||
4582 | /* If an instruction is about to grow, return the longer size. */ | |
4583 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
b81bf389 BW |
4584 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 |
4585 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) | |
def13efb BW |
4586 | { |
4587 | /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first | |
4588 | instruction in the relaxed version is of length 3. (The case | |
4589 | where we have to pull the instruction out of a FLIX bundle | |
4590 | is handled conservatively above.) However, frags with opcodes | |
4591 | that are expanding to wide branches end up having formats that | |
4592 | are not determinable by the RELAX_IMMED_STEPX enumeration, and | |
4593 | we can't tell directly what format the relaxer picked. This | |
4594 | is a wart in the design of the relaxer that should someday be | |
4595 | fixed, but would require major changes, or at least should | |
4596 | be accompanied by major changes to make use of that data. | |
4597 | ||
4598 | In any event, we can tell that we are expanding from a single-slot | |
19ef5f3d | 4599 | format to a wider one with the logic below. */ |
def13efb | 4600 | |
19ef5f3d SA |
4601 | int i; |
4602 | int relaxed_size = fmt_size + fragP->tc_frag_data.text_expansion[0]; | |
4603 | ||
4604 | for (i = 0; i < xtensa_isa_num_formats (isa); i++) | |
4605 | { | |
4606 | if (relaxed_size == xtensa_format_length (isa, i)) | |
4607 | return relaxed_size; | |
4608 | } | |
4609 | ||
4610 | return 3; | |
def13efb | 4611 | } |
c138bc38 | 4612 | |
43cd72b9 BW |
4613 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4614 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4615 | |
43cd72b9 | 4616 | return fmt_size; |
e0001a05 NC |
4617 | } |
4618 | ||
4619 | ||
7fa3d080 BW |
4620 | static int |
4621 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4622 | { |
7fa3d080 BW |
4623 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4624 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4625 | } |
4626 | ||
4627 | ||
03aaa593 BW |
4628 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4629 | required two-byte instructions to be treated as three-byte instructions | |
4630 | for loop instruction alignment. This restriction was removed beginning | |
4631 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4632 | is that the first instruction of the loop must appear at an address that | |
4633 | does not cross a fetch boundary. */ | |
4634 | ||
4635 | static int | |
4636 | get_loop_align_size (int insn_size) | |
4637 | { | |
4638 | if (insn_size == XTENSA_UNDEFINED) | |
4639 | return xtensa_fetch_width; | |
4640 | ||
4641 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4642 | return 3; | |
4643 | ||
4644 | return insn_size; | |
4645 | } | |
4646 | ||
4647 | ||
e0001a05 NC |
4648 | /* If the next legit fragment is an end-of-loop marker, |
4649 | switch its state so it will instantiate a NOP. */ | |
4650 | ||
4651 | static void | |
1d19a770 | 4652 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4653 | { |
4654 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4655 | fragS *new_target = NULL; |
e0001a05 | 4656 | |
7b1cc377 | 4657 | if (align_targets) |
43cd72b9 BW |
4658 | { |
4659 | /* We are guaranteed there will be one of these... */ | |
4660 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4661 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4662 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4663 | next_fragP = next_fragP->fr_next; | |
4664 | ||
9c2799c2 | 4665 | gas_assert (next_fragP->fr_type == rs_machine_dependent |
43cd72b9 BW |
4666 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE |
4667 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4668 | ||
4669 | /* ...and one of these. */ | |
4670 | new_target = next_fragP->fr_next; | |
4671 | while (!(new_target->fr_type == rs_machine_dependent | |
4672 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4673 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4674 | new_target = new_target->fr_next; | |
4675 | ||
9c2799c2 | 4676 | gas_assert (new_target->fr_type == rs_machine_dependent |
43cd72b9 BW |
4677 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN |
4678 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4679 | } | |
43cd72b9 | 4680 | |
1d19a770 | 4681 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4682 | { |
1d19a770 BW |
4683 | if (next_fragP->fr_type == rs_machine_dependent |
4684 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4685 | { |
1d19a770 BW |
4686 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4687 | return; | |
e0001a05 | 4688 | } |
1d19a770 BW |
4689 | |
4690 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4691 | } |
4692 | } | |
4693 | ||
4694 | ||
4695 | static bfd_boolean | |
7fa3d080 | 4696 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4697 | { |
43cd72b9 | 4698 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4699 | so we have to skip until we find something legit. */ |
4700 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4701 | { | |
4702 | if (fragP->tc_frag_data.is_branch_target) | |
4703 | return TRUE; | |
4704 | if (fragP->fr_fix != 0) | |
4705 | break; | |
4706 | } | |
4707 | return FALSE; | |
4708 | } | |
4709 | ||
4710 | ||
4711 | static bfd_boolean | |
7fa3d080 | 4712 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4713 | { |
c138bc38 | 4714 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4715 | So we have to skip until we find something legit. */ |
4716 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4717 | { | |
4718 | if (fragP->tc_frag_data.is_loop_target) | |
4719 | return TRUE; | |
4720 | if (fragP->fr_fix != 0) | |
4721 | break; | |
4722 | } | |
4723 | return FALSE; | |
4724 | } | |
4725 | ||
4726 | ||
3a1e9c4a SA |
4727 | /* As specified in the relaxation table, when a loop instruction is |
4728 | relaxed, there are 24 bytes between the loop instruction itself and | |
4729 | the first instruction in the loop. */ | |
4730 | ||
4731 | #define RELAXED_LOOP_INSN_BYTES 24 | |
4732 | ||
e0001a05 | 4733 | static addressT |
7fa3d080 | 4734 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4735 | { |
4736 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4737 | xtensa_opcode next_opcode; |
e0001a05 | 4738 | |
43cd72b9 | 4739 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4740 | return 0; |
4741 | ||
43cd72b9 BW |
4742 | /* Sometimes an empty will end up here due to storage allocation issues, |
4743 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4744 | while (next_fragp->fr_fix == 0) |
4745 | next_fragp = next_fragp->fr_next; | |
4746 | ||
4747 | if (next_fragp->fr_type != rs_machine_dependent) | |
4748 | return 0; | |
4749 | ||
4750 | /* There is some implicit knowledge encoded in here. | |
4751 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4752 | been relaxed. Note that we can assume that the LOOP |
4753 | instruction is in slot 0 because loops aren't bundleable. */ | |
4754 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
3a1e9c4a | 4755 | return get_expanded_loop_offset (next_opcode) + RELAXED_LOOP_INSN_BYTES; |
e0001a05 NC |
4756 | |
4757 | return 0; | |
4758 | } | |
4759 | ||
4760 | ||
4761 | /* Mark a location where we can later insert literal frags. Update | |
4762 | the section's literal_pool_loc, so subsequent literals can be | |
4763 | placed nearest to their use. */ | |
4764 | ||
4765 | static void | |
7fa3d080 | 4766 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4767 | { |
4768 | /* Any labels pointing to the current location need | |
4769 | to be adjusted to after the literal pool. */ | |
4770 | emit_state s; | |
e0001a05 | 4771 | fragS *pool_location; |
e0001a05 | 4772 | |
1f2a7e38 | 4773 | if (use_literal_section) |
43cd72b9 BW |
4774 | return; |
4775 | ||
dd49a749 BW |
4776 | /* We stash info in these frags so we can later move the literal's |
4777 | fixes into this frchain's fix list. */ | |
e0001a05 | 4778 | pool_location = frag_now; |
dd49a749 | 4779 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
c48aaca0 | 4780 | frag_now->tc_frag_data.literal_frag = frag_now; |
b46824bd MF |
4781 | /* Just record this frag. */ |
4782 | xtensa_maybe_create_literal_pool_frag (FALSE, FALSE); | |
dd49a749 | 4783 | frag_variant (rs_machine_dependent, 0, 0, |
e0001a05 | 4784 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4785 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4786 | frag_now->tc_frag_data.lit_seg = now_seg; |
4787 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4788 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4789 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4790 | |
4791 | /* Now put a frag into the literal pool that points to this location. */ | |
4792 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4793 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4794 | frag_align (2, 0, 0); | |
4795 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4796 | |
4797 | /* Close whatever frag is there. */ | |
4798 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4799 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4800 | frag_now->tc_frag_data.literal_frag = pool_location; |
4801 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4802 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4803 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4804 | } |
4805 | ||
4806 | ||
43cd72b9 BW |
4807 | /* Build a nop of the correct size into tinsn. */ |
4808 | ||
4809 | static void | |
7fa3d080 | 4810 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4811 | { |
4812 | tinsn_init (tinsn); | |
4813 | switch (size) | |
4814 | { | |
4815 | case 2: | |
4816 | tinsn->opcode = xtensa_nop_n_opcode; | |
4817 | tinsn->ntok = 0; | |
4818 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4819 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4820 | break; | |
4821 | ||
4822 | case 3: | |
4823 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4824 | { | |
4825 | tinsn->opcode = xtensa_or_opcode; | |
4826 | set_expr_const (&tinsn->tok[0], 1); | |
4827 | set_expr_const (&tinsn->tok[1], 1); | |
4828 | set_expr_const (&tinsn->tok[2], 1); | |
4829 | tinsn->ntok = 3; | |
4830 | } | |
4831 | else | |
4832 | tinsn->opcode = xtensa_nop_opcode; | |
4833 | ||
9c2799c2 | 4834 | gas_assert (tinsn->opcode != XTENSA_UNDEFINED); |
43cd72b9 BW |
4835 | } |
4836 | } | |
4837 | ||
4838 | ||
e0001a05 NC |
4839 | /* Assemble a NOP of the requested size in the buffer. User must have |
4840 | allocated "buf" with at least "size" bytes. */ | |
4841 | ||
7fa3d080 | 4842 | static void |
d77b99c9 | 4843 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4844 | { |
4845 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4846 | TInsn tinsn; |
e0001a05 | 4847 | |
43cd72b9 | 4848 | build_nop (&tinsn, size); |
e0001a05 | 4849 | |
43cd72b9 BW |
4850 | if (!insnbuf) |
4851 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4852 | |
43cd72b9 | 4853 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4854 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4855 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4856 | } |
4857 | ||
4858 | ||
4859 | /* Return the number of bytes for the offset of the expanded loop | |
4860 | instruction. This should be incorporated into the relaxation | |
4861 | specification but is hard-coded here. This is used to auto-align | |
4862 | the loop instruction. It is invalid to call this function if the | |
4863 | configuration does not have loops or if the opcode is not a loop | |
4864 | opcode. */ | |
4865 | ||
4866 | static addressT | |
7fa3d080 | 4867 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4868 | { |
4869 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4870 | This MUST correspond directly to the specification of the loop | |
4871 | expansion. It will be validated on fragment conversion. */ | |
9c2799c2 | 4872 | gas_assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4873 | if (opcode == xtensa_loop_opcode) |
4874 | return 0; | |
4875 | if (opcode == xtensa_loopnez_opcode) | |
4876 | return 3; | |
4877 | if (opcode == xtensa_loopgtz_opcode) | |
4878 | return 6; | |
4879 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4880 | return 0; | |
4881 | } | |
4882 | ||
4883 | ||
7fa3d080 BW |
4884 | static fragS * |
4885 | get_literal_pool_location (segT seg) | |
e0001a05 | 4886 | { |
b46824bd MF |
4887 | struct litpool_seg *lps = litpool_seg_list.next; |
4888 | struct litpool_frag *lpf; | |
4889 | for ( ; lps && lps->seg->id != seg->id; lps = lps->next) | |
4890 | ; | |
4891 | if (lps) | |
4892 | { | |
4893 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) | |
4894 | { /* Skip "candidates" for now. */ | |
4895 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN && | |
4896 | lpf->priority == 1) | |
4897 | return lpf->fragP; | |
4898 | } | |
4899 | /* Must convert a lower-priority pool. */ | |
4900 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) | |
4901 | { | |
4902 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN) | |
4903 | return lpf->fragP; | |
4904 | } | |
4905 | /* Still no match -- try for a low priority pool. */ | |
4906 | for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) | |
4907 | { | |
4908 | if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
4909 | return lpf->fragP; | |
4910 | } | |
4911 | } | |
e0001a05 NC |
4912 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; |
4913 | } | |
4914 | ||
4915 | ||
4916 | static void | |
7fa3d080 | 4917 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4918 | { |
4919 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4920 | } | |
4921 | ||
43cd72b9 BW |
4922 | |
4923 | /* Set frag assembly state should be called when a new frag is | |
4924 | opened and after a frag has been closed. */ | |
4925 | ||
7fa3d080 BW |
4926 | static void |
4927 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4928 | { |
4929 | if (!density_supported) | |
4930 | fragP->tc_frag_data.is_no_density = TRUE; | |
4931 | ||
4932 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4933 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4934 | "use_schedule" here. */ |
4935 | if (!directive_state[directive_transform]) | |
4936 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4937 | if (directive_state[directive_longcalls]) |
4938 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4939 | fragP->tc_frag_data.use_absolute_literals = |
4940 | directive_state[directive_absolute_literals]; | |
4941 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4942 | } | |
4943 | ||
4944 | ||
7fa3d080 BW |
4945 | static bfd_boolean |
4946 | relaxable_section (asection *sec) | |
43cd72b9 | 4947 | { |
11ac2671 BW |
4948 | return ((sec->flags & SEC_DEBUGGING) == 0 |
4949 | && strcmp (sec->name, ".eh_frame") != 0); | |
43cd72b9 BW |
4950 | } |
4951 | ||
4952 | ||
99ded152 BW |
4953 | static void |
4954 | xtensa_mark_frags_for_org (void) | |
4955 | { | |
4956 | segT *seclist; | |
4957 | ||
4958 | /* Walk over each fragment of all of the current segments. If we find | |
4959 | a .org frag in any of the segments, mark all frags prior to it as | |
4960 | "no transform", which will prevent linker optimizations from messing | |
4961 | up the .org distance. This should be done after | |
4962 | xtensa_find_unmarked_state_frags, because we don't want to worry here | |
4963 | about that function trashing the data we save here. */ | |
4964 | ||
4965 | for (seclist = &stdoutput->sections; | |
4966 | seclist && *seclist; | |
4967 | seclist = &(*seclist)->next) | |
4968 | { | |
4969 | segT sec = *seclist; | |
4970 | segment_info_type *seginfo; | |
4971 | fragS *fragP; | |
4972 | flagword flags; | |
4973 | flags = bfd_get_section_flags (stdoutput, sec); | |
4974 | if (flags & SEC_DEBUGGING) | |
4975 | continue; | |
4976 | if (!(flags & SEC_ALLOC)) | |
4977 | continue; | |
4978 | ||
4979 | seginfo = seg_info (sec); | |
4980 | if (seginfo && seginfo->frchainP) | |
4981 | { | |
4982 | fragS *last_fragP = seginfo->frchainP->frch_root; | |
4983 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4984 | fragP = fragP->fr_next) | |
4985 | { | |
4986 | /* cvt_frag_to_fill has changed the fr_type of org frags to | |
4987 | rs_fill, so use the value as cached in rs_subtype here. */ | |
4988 | if (fragP->fr_subtype == RELAX_ORG) | |
4989 | { | |
4990 | while (last_fragP != fragP->fr_next) | |
4991 | { | |
4992 | last_fragP->tc_frag_data.is_no_transform = TRUE; | |
4993 | last_fragP = last_fragP->fr_next; | |
4994 | } | |
4995 | } | |
4996 | } | |
4997 | } | |
4998 | } | |
4999 | } | |
5000 | ||
5001 | ||
43cd72b9 | 5002 | static void |
7fa3d080 | 5003 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
5004 | { |
5005 | segT *seclist; | |
5006 | ||
5007 | /* Walk over each fragment of all of the current segments. For each | |
5008 | unmarked fragment, mark it with the same info as the previous | |
5009 | fragment. */ | |
5010 | for (seclist = &stdoutput->sections; | |
5011 | seclist && *seclist; | |
5012 | seclist = &(*seclist)->next) | |
5013 | { | |
5014 | segT sec = *seclist; | |
5015 | segment_info_type *seginfo; | |
5016 | fragS *fragP; | |
5017 | flagword flags; | |
5018 | flags = bfd_get_section_flags (stdoutput, sec); | |
5019 | if (flags & SEC_DEBUGGING) | |
5020 | continue; | |
5021 | if (!(flags & SEC_ALLOC)) | |
5022 | continue; | |
5023 | ||
5024 | seginfo = seg_info (sec); | |
5025 | if (seginfo && seginfo->frchainP) | |
5026 | { | |
5027 | fragS *last_fragP = 0; | |
5028 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
5029 | fragP = fragP->fr_next) | |
5030 | { | |
5031 | if (fragP->fr_fix != 0 | |
5032 | && !fragP->tc_frag_data.is_assembly_state_set) | |
5033 | { | |
5034 | if (last_fragP == 0) | |
5035 | { | |
5036 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
5037 | _("assembly state not set for first frag in section %s"), | |
5038 | sec->name); | |
5039 | } | |
5040 | else | |
5041 | { | |
5042 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
5043 | fragP->tc_frag_data.is_no_density = | |
5044 | last_fragP->tc_frag_data.is_no_density; | |
5045 | fragP->tc_frag_data.is_no_transform = | |
5046 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
5047 | fragP->tc_frag_data.use_longcalls = |
5048 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
5049 | fragP->tc_frag_data.use_absolute_literals = |
5050 | last_fragP->tc_frag_data.use_absolute_literals; | |
5051 | } | |
5052 | } | |
5053 | if (fragP->tc_frag_data.is_assembly_state_set) | |
5054 | last_fragP = fragP; | |
5055 | } | |
5056 | } | |
5057 | } | |
5058 | } | |
5059 | ||
5060 | ||
5061 | static void | |
7fa3d080 BW |
5062 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
5063 | asection *sec, | |
5064 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
5065 | { |
5066 | flagword flags = bfd_get_section_flags (abfd, sec); | |
5067 | segment_info_type *seginfo = seg_info (sec); | |
5068 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 5069 | |
43cd72b9 | 5070 | if (flags & SEC_CODE) |
c138bc38 | 5071 | { |
43cd72b9 BW |
5072 | xtensa_isa isa = xtensa_default_isa; |
5073 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
5074 | while (frag != NULL) | |
5075 | { | |
5076 | if (frag->tc_frag_data.is_branch_target) | |
5077 | { | |
5078 | int op_size; | |
664df4e4 | 5079 | addressT branch_align, frag_addr; |
43cd72b9 BW |
5080 | xtensa_format fmt; |
5081 | ||
d77b99c9 BW |
5082 | xtensa_insnbuf_from_chars |
5083 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
5084 | fmt = xtensa_format_decode (isa, insnbuf); |
5085 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
5086 | branch_align = 1 << branch_align_power (sec); |
5087 | frag_addr = frag->fr_address % branch_align; | |
5088 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
5089 | as_warn_where (frag->fr_file, frag->fr_line, |
5090 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 5091 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
5092 | } |
5093 | frag = frag->fr_next; | |
5094 | } | |
5095 | xtensa_insnbuf_free (isa, insnbuf); | |
5096 | } | |
5097 | } | |
5098 | ||
5099 | ||
5100 | static void | |
7fa3d080 BW |
5101 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
5102 | asection *sec, | |
5103 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
5104 | { |
5105 | flagword flags = bfd_get_section_flags (abfd, sec); | |
5106 | segment_info_type *seginfo = seg_info (sec); | |
5107 | fragS *frag = seginfo->frchainP->frch_root; | |
5108 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 5109 | |
43cd72b9 | 5110 | if (flags & SEC_CODE) |
c138bc38 | 5111 | { |
43cd72b9 BW |
5112 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
5113 | while (frag != NULL) | |
5114 | { | |
5115 | if (frag->tc_frag_data.is_first_loop_insn) | |
5116 | { | |
5117 | int op_size; | |
d77b99c9 | 5118 | addressT frag_addr; |
43cd72b9 BW |
5119 | xtensa_format fmt; |
5120 | ||
3c83b96e SA |
5121 | if (frag->fr_fix == 0) |
5122 | frag = next_non_empty_frag (frag); | |
3739860c | 5123 | |
3c83b96e SA |
5124 | if (frag) |
5125 | { | |
5126 | xtensa_insnbuf_from_chars | |
5127 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
5128 | fmt = xtensa_format_decode (isa, insnbuf); | |
5129 | op_size = xtensa_format_length (isa, fmt); | |
5130 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
3739860c | 5131 | |
3c83b96e SA |
5132 | if (frag_addr + op_size > xtensa_fetch_width) |
5133 | as_warn_where (frag->fr_file, frag->fr_line, | |
5134 | _("unaligned loop: %d bytes at 0x%lx"), | |
5135 | op_size, (long) frag->fr_address); | |
5136 | } | |
43cd72b9 BW |
5137 | } |
5138 | frag = frag->fr_next; | |
5139 | } | |
5140 | xtensa_insnbuf_free (isa, insnbuf); | |
5141 | } | |
5142 | } | |
5143 | ||
5144 | ||
30f725a1 BW |
5145 | static int |
5146 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
5147 | { |
5148 | xtensa_isa isa = xtensa_default_isa; | |
5149 | static xtensa_insnbuf insnbuf = NULL; | |
5150 | static xtensa_insnbuf slotbuf = NULL; | |
5151 | xtensa_format fmt; | |
5152 | int slot; | |
5153 | bfd_boolean alt_reloc; | |
5154 | xtensa_opcode opcode; | |
5155 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
5156 | ||
1b6e95c2 BW |
5157 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) |
5158 | || alt_reloc) | |
43cd72b9 BW |
5159 | as_fatal (_("unexpected fix")); |
5160 | ||
5161 | if (!insnbuf) | |
5162 | { | |
5163 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5164 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5165 | } | |
5166 | ||
d77b99c9 | 5167 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
5168 | fmt = xtensa_format_decode (isa, insnbuf); |
5169 | if (fmt == XTENSA_UNDEFINED) | |
5170 | as_fatal (_("undecodable fix")); | |
5171 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5172 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5173 | if (opcode == XTENSA_UNDEFINED) | |
5174 | as_fatal (_("undecodable fix")); | |
5175 | ||
5176 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
5177 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 5178 | of a CONST16 operand. */ |
43cd72b9 | 5179 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 5180 | return 0; |
43cd72b9 BW |
5181 | |
5182 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
5183 | get_relaxable_immed (opcode), val, | |
5184 | fixP->fx_file, fixP->fx_line); | |
5185 | ||
5186 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 5187 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
5188 | |
5189 | return 1; | |
43cd72b9 BW |
5190 | } |
5191 | ||
e0001a05 NC |
5192 | \f |
5193 | /* External Functions and Other GAS Hooks. */ | |
5194 | ||
5195 | const char * | |
7fa3d080 | 5196 | xtensa_target_format (void) |
e0001a05 NC |
5197 | { |
5198 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
5199 | } | |
5200 | ||
5201 | ||
5202 | void | |
7fa3d080 | 5203 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
5204 | { |
5205 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
5206 | } | |
5207 | ||
5208 | ||
5209 | void | |
7fa3d080 | 5210 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
5211 | { |
5212 | if (target_big_endian) | |
5213 | number_to_chars_bigendian (buf, val, n); | |
5214 | else | |
5215 | number_to_chars_littleendian (buf, val, n); | |
5216 | } | |
5217 | ||
f7e16c2a MF |
5218 | static void |
5219 | xg_init_global_config (void) | |
5220 | { | |
5221 | target_big_endian = XCHAL_HAVE_BE; | |
5222 | ||
5223 | density_supported = XCHAL_HAVE_DENSITY; | |
5224 | absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; | |
5225 | xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; | |
5226 | ||
5227 | directive_state[directive_density] = XCHAL_HAVE_DENSITY; | |
5228 | directive_state[directive_absolute_literals] = XSHAL_USE_ABSOLUTE_LITERALS; | |
5229 | } | |
5230 | ||
5231 | void | |
5232 | xtensa_init (int argc ATTRIBUTE_UNUSED, char **argv ATTRIBUTE_UNUSED) | |
5233 | { | |
5234 | xg_init_global_config (); | |
5235 | } | |
e0001a05 NC |
5236 | |
5237 | /* This function is called once, at assembler startup time. It should | |
5238 | set up all the tables, etc. that the MD part of the assembler will | |
5239 | need. */ | |
5240 | ||
5241 | void | |
7fa3d080 | 5242 | md_begin (void) |
e0001a05 NC |
5243 | { |
5244 | segT current_section = now_seg; | |
5245 | int current_subsec = now_subseg; | |
5246 | xtensa_isa isa; | |
62af60e2 | 5247 | int i; |
e0001a05 | 5248 | |
43cd72b9 | 5249 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 5250 | isa = xtensa_default_isa; |
e0001a05 | 5251 | |
43cd72b9 BW |
5252 | linkrelax = 1; |
5253 | ||
74869ac7 | 5254 | /* Set up the literal sections. */ |
e0001a05 | 5255 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
e0001a05 NC |
5256 | |
5257 | subseg_set (current_section, current_subsec); | |
5258 | ||
5259 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); | |
5260 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
5261 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
5262 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
5263 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
5264 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
5265 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
5266 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
5267 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
5268 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 5269 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 5270 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
d12f9798 | 5271 | xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); |
43cd72b9 BW |
5272 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
5273 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 5274 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
19e8f41a | 5275 | xtensa_j_opcode = xtensa_opcode_lookup (isa, "j"); |
e0001a05 | 5276 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 5277 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
5278 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
5279 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
5280 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 5281 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
5282 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
5283 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
5284 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
5285 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
5286 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
5287 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 5288 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 5289 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 | 5290 | |
3739860c | 5291 | for (i = 0; i < xtensa_isa_num_formats (isa); i++) |
62af60e2 SA |
5292 | { |
5293 | int format_slots = xtensa_format_num_slots (isa, i); | |
5294 | if (format_slots > config_max_slots) | |
5295 | config_max_slots = format_slots; | |
5296 | } | |
5297 | ||
5298 | xg_init_vinsn (&cur_vinsn); | |
5299 | ||
77cba8a3 BW |
5300 | xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa); |
5301 | ||
43cd72b9 BW |
5302 | init_op_placement_info_table (); |
5303 | ||
5304 | /* Set up the assembly state. */ | |
5305 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5306 | xtensa_set_frag_assembly_state (frag_now); | |
5307 | } | |
5308 | ||
5309 | ||
5310 | /* TC_INIT_FIX_DATA hook */ | |
5311 | ||
5312 | void | |
7fa3d080 | 5313 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5314 | { |
5315 | x->tc_fix_data.slot = 0; | |
5316 | x->tc_fix_data.X_add_symbol = NULL; | |
5317 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5318 | } |
5319 | ||
5320 | ||
5321 | /* tc_frob_label hook */ | |
5322 | ||
5323 | void | |
7fa3d080 | 5324 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5325 | { |
3ea38ac2 BW |
5326 | float freq; |
5327 | ||
5328 | if (cur_vinsn.inside_bundle) | |
5329 | { | |
5330 | as_bad (_("labels are not valid inside bundles")); | |
5331 | return; | |
5332 | } | |
5333 | ||
5334 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5335 | |
43cd72b9 BW |
5336 | /* Since the label was already attached to a frag associated with the |
5337 | previous basic block, it now needs to be reset to the current frag. */ | |
5338 | symbol_set_frag (sym, frag_now); | |
5339 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5340 | ||
82e7541d BW |
5341 | if (generating_literals) |
5342 | xtensa_add_literal_sym (sym); | |
5343 | else | |
5344 | xtensa_add_insn_label (sym); | |
5345 | ||
7b1cc377 BW |
5346 | if (symbol_get_tc (sym)->is_loop_target) |
5347 | { | |
5348 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5349 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5350 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5351 | ||
5352 | xtensa_set_frag_assembly_state (frag_now); | |
5353 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5354 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5355 | ||
5356 | xtensa_set_frag_assembly_state (frag_now); | |
c3ea6048 | 5357 | xtensa_move_labels (frag_now, 0); |
07a53e5c | 5358 | } |
e0001a05 NC |
5359 | |
5360 | /* No target aligning in the absolute section. */ | |
61846f28 | 5361 | if (now_seg != absolute_section |
61846f28 | 5362 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5363 | && !generating_literals) |
5364 | { | |
43cd72b9 BW |
5365 | xtensa_set_frag_assembly_state (frag_now); |
5366 | ||
b7afdeef SA |
5367 | if (do_align_targets ()) |
5368 | frag_var (rs_machine_dependent, 0, (int) freq, | |
5369 | RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol, | |
5370 | frag_now->fr_offset, NULL); | |
5371 | else | |
5372 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
5373 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5374 | xtensa_set_frag_assembly_state (frag_now); |
c3ea6048 | 5375 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
5376 | } |
5377 | ||
5378 | /* We need to mark the following properties even if we aren't aligning. */ | |
5379 | ||
5380 | /* If the label is already known to be a branch target, i.e., a | |
5381 | forward branch, mark the frag accordingly. Backward branches | |
5382 | are handled by xg_add_branch_and_loop_targets. */ | |
5383 | if (symbol_get_tc (sym)->is_branch_target) | |
5384 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5385 | ||
5386 | /* Loops only go forward, so they can be identified here. */ | |
5387 | if (symbol_get_tc (sym)->is_loop_target) | |
5388 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5389 | |
5390 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5391 | } |
5392 | ||
5393 | ||
5394 | /* tc_unrecognized_line hook */ | |
5395 | ||
5396 | int | |
7fa3d080 | 5397 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5398 | { |
5399 | switch (ch) | |
5400 | { | |
5401 | case '{' : | |
5402 | if (cur_vinsn.inside_bundle == 0) | |
5403 | { | |
5404 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5405 | when using --gstabs. Temporarily disable debug info. */ | |
5406 | generate_lineno_debug (); | |
5407 | if (debug_type == DEBUG_STABS) | |
5408 | { | |
5409 | xt_saved_debug_type = debug_type; | |
5410 | debug_type = DEBUG_NONE; | |
5411 | } | |
82e7541d | 5412 | |
43cd72b9 BW |
5413 | cur_vinsn.inside_bundle = 1; |
5414 | } | |
5415 | else | |
5416 | { | |
5417 | as_bad (_("extra opening brace")); | |
5418 | return 0; | |
5419 | } | |
5420 | break; | |
82e7541d | 5421 | |
43cd72b9 BW |
5422 | case '}' : |
5423 | if (cur_vinsn.inside_bundle) | |
5424 | finish_vinsn (&cur_vinsn); | |
5425 | else | |
5426 | { | |
5427 | as_bad (_("extra closing brace")); | |
5428 | return 0; | |
5429 | } | |
5430 | break; | |
5431 | default: | |
5432 | as_bad (_("syntax error")); | |
5433 | return 0; | |
e0001a05 | 5434 | } |
43cd72b9 | 5435 | return 1; |
e0001a05 NC |
5436 | } |
5437 | ||
5438 | ||
5439 | /* md_flush_pending_output hook */ | |
5440 | ||
5441 | void | |
7fa3d080 | 5442 | xtensa_flush_pending_output (void) |
e0001a05 | 5443 | { |
a3582eee BW |
5444 | /* This line fixes a bug where automatically generated gstabs info |
5445 | separates a function label from its entry instruction, ending up | |
5446 | with the literal position between the function label and the entry | |
5447 | instruction and crashing code. It only happens with --gstabs and | |
5448 | --text-section-literals, and when several other obscure relaxation | |
5449 | conditions are met. */ | |
5450 | if (outputting_stabs_line_debug) | |
5451 | return; | |
5452 | ||
43cd72b9 BW |
5453 | if (cur_vinsn.inside_bundle) |
5454 | as_bad (_("missing closing brace")); | |
5455 | ||
e0001a05 NC |
5456 | /* If there is a non-zero instruction fragment, close it. */ |
5457 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5458 | { | |
5459 | frag_wane (frag_now); | |
5460 | frag_new (0); | |
43cd72b9 | 5461 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5462 | } |
5463 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5464 | |
5465 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5466 | } |
5467 | ||
5468 | ||
43cd72b9 BW |
5469 | /* We had an error while parsing an instruction. The string might look |
5470 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5471 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5472 | and the num_slots field will grow past the end of the array of slots, | |
5473 | and bad things happen. */ | |
5474 | ||
5475 | static void | |
7fa3d080 | 5476 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5477 | { |
5478 | if (cur_vinsn.inside_bundle) | |
5479 | { | |
5480 | if (*input_line_pointer == '}' | |
5481 | || *(input_line_pointer - 1) == '}' | |
5482 | || *(input_line_pointer - 2) == '}') | |
5483 | xg_clear_vinsn (&cur_vinsn); | |
5484 | } | |
5485 | } | |
5486 | ||
5487 | ||
e0001a05 | 5488 | void |
7fa3d080 | 5489 | md_assemble (char *str) |
e0001a05 NC |
5490 | { |
5491 | xtensa_isa isa = xtensa_default_isa; | |
b224e962 | 5492 | char *opname; |
e0001a05 NC |
5493 | unsigned opnamelen; |
5494 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5495 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5496 | int num_args; |
e0001a05 | 5497 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5498 | |
e0001a05 NC |
5499 | tinsn_init (&orig_insn); |
5500 | ||
5501 | /* Split off the opcode. */ | |
5502 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
4ec9d7d5 | 5503 | opname = xstrndup (str, opnamelen); |
e0001a05 NC |
5504 | |
5505 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5506 | if (num_args == -1) | |
5507 | { | |
5508 | as_bad (_("syntax error")); | |
5509 | return; | |
5510 | } | |
5511 | ||
5512 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5513 | return; | |
5514 | ||
5515 | /* Check for an underbar prefix. */ | |
5516 | if (*opname == '_') | |
5517 | { | |
5518 | has_underbar = TRUE; | |
5519 | opname += 1; | |
5520 | } | |
5521 | ||
5522 | orig_insn.insn_type = ITYPE_INSN; | |
5523 | orig_insn.ntok = 0; | |
43cd72b9 | 5524 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 | 5525 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); |
28dbbc02 | 5526 | |
2b0f3761 | 5527 | /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its |
28dbbc02 BW |
5528 | extra argument and set the opcode to "CALLXn". */ |
5529 | if (orig_insn.opcode == XTENSA_UNDEFINED | |
5530 | && strncasecmp (opname, "callx", 5) == 0) | |
5531 | { | |
5532 | unsigned long window_size; | |
5533 | char *suffix; | |
5534 | ||
5535 | window_size = strtoul (opname + 5, &suffix, 10); | |
5536 | if (suffix != opname + 5 | |
5537 | && (window_size == 0 | |
5538 | || window_size == 4 | |
5539 | || window_size == 8 | |
5540 | || window_size == 12) | |
5541 | && strcasecmp (suffix, ".tls") == 0) | |
5542 | { | |
5543 | switch (window_size) | |
5544 | { | |
5545 | case 0: orig_insn.opcode = xtensa_callx0_opcode; break; | |
5546 | case 4: orig_insn.opcode = xtensa_callx4_opcode; break; | |
5547 | case 8: orig_insn.opcode = xtensa_callx8_opcode; break; | |
5548 | case 12: orig_insn.opcode = xtensa_callx12_opcode; break; | |
5549 | } | |
5550 | ||
5551 | if (num_args != 2) | |
5552 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5553 | else | |
5554 | { | |
5555 | bfd_reloc_code_real_type reloc; | |
5556 | char *old_input_line_pointer; | |
19e8f41a | 5557 | expressionS *tok = &orig_insn.extra_arg; |
28dbbc02 BW |
5558 | |
5559 | old_input_line_pointer = input_line_pointer; | |
5560 | input_line_pointer = arg_strings[num_args - 1]; | |
5561 | ||
87975d2a | 5562 | expression (tok); |
28dbbc02 BW |
5563 | if (tok->X_op == O_symbol |
5564 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) | |
5565 | == BFD_RELOC_XTENSA_TLS_CALL)) | |
5566 | tok->X_op = map_suffix_reloc_to_operator (reloc); | |
5567 | else | |
5568 | as_bad (_("bad relocation expression for '%s'"), opname); | |
5569 | ||
5570 | input_line_pointer = old_input_line_pointer; | |
5571 | num_args -= 1; | |
5572 | } | |
5573 | } | |
5574 | } | |
5575 | ||
2b0f3761 | 5576 | /* Special case: Check for "j.l" pseudo op. */ |
19e8f41a BW |
5577 | if (orig_insn.opcode == XTENSA_UNDEFINED |
5578 | && strncasecmp (opname, "j.l", 3) == 0) | |
5579 | { | |
5580 | if (num_args != 2) | |
5581 | as_bad (_("wrong number of operands for '%s'"), opname); | |
5582 | else | |
5583 | { | |
5584 | char *old_input_line_pointer; | |
5585 | expressionS *tok = &orig_insn.extra_arg; | |
5586 | ||
5587 | old_input_line_pointer = input_line_pointer; | |
5588 | input_line_pointer = arg_strings[num_args - 1]; | |
5589 | ||
5590 | expression_maybe_register (xtensa_jx_opcode, 0, tok); | |
5591 | input_line_pointer = old_input_line_pointer; | |
5592 | ||
5593 | num_args -= 1; | |
5594 | orig_insn.opcode = xtensa_j_opcode; | |
5595 | } | |
5596 | } | |
5597 | ||
e0001a05 NC |
5598 | if (orig_insn.opcode == XTENSA_UNDEFINED) |
5599 | { | |
43cd72b9 BW |
5600 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5601 | if (fmt == XTENSA_UNDEFINED) | |
5602 | { | |
5603 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5604 | error_reset_cur_vinsn (); | |
5605 | return; | |
5606 | } | |
5607 | if (!cur_vinsn.inside_bundle) | |
5608 | { | |
5609 | as_bad (_("format names only valid inside bundles")); | |
5610 | error_reset_cur_vinsn (); | |
5611 | return; | |
5612 | } | |
5613 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5614 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5615 | opname); | |
5616 | cur_vinsn.format = fmt; | |
5617 | free (has_underbar ? opname - 1 : opname); | |
5618 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5619 | return; |
5620 | } | |
5621 | ||
e0001a05 NC |
5622 | /* Parse the arguments. */ |
5623 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5624 | { | |
5625 | as_bad (_("syntax error")); | |
43cd72b9 | 5626 | error_reset_cur_vinsn (); |
e0001a05 NC |
5627 | return; |
5628 | } | |
5629 | ||
5630 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5631 | free (has_underbar ? opname - 1 : opname); | |
5632 | opname = 0; | |
5633 | while (num_args-- > 0) | |
5634 | free (arg_strings[num_args]); | |
5635 | ||
43cd72b9 BW |
5636 | /* Get expressions for invisible operands. */ |
5637 | if (get_invisible_operands (&orig_insn)) | |
5638 | { | |
5639 | error_reset_cur_vinsn (); | |
5640 | return; | |
5641 | } | |
5642 | ||
e0001a05 NC |
5643 | /* Check for the right number and type of arguments. */ |
5644 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5645 | { |
43cd72b9 BW |
5646 | error_reset_cur_vinsn (); |
5647 | return; | |
e0001a05 NC |
5648 | } |
5649 | ||
b224e962 BW |
5650 | /* Record the line number for each TInsn, because a FLIX bundle may be |
5651 | spread across multiple input lines and individual instructions may be | |
5652 | moved around in some cases. */ | |
5653 | orig_insn.loc_directive_seen = dwarf2_loc_directive_seen; | |
5654 | dwarf2_where (&orig_insn.debug_line); | |
5655 | dwarf2_consume_line_info (); | |
c138bc38 | 5656 | |
43cd72b9 BW |
5657 | xg_add_branch_and_loop_targets (&orig_insn); |
5658 | ||
431ad2d0 BW |
5659 | /* Check that immediate value for ENTRY is >= 16. */ |
5660 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5661 | { |
431ad2d0 BW |
5662 | expressionS *exp = &orig_insn.tok[2]; |
5663 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5664 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5665 | } |
5666 | ||
e0001a05 | 5667 | /* Finish it off: |
43cd72b9 BW |
5668 | assemble_tokens (opcode, tok, ntok); |
5669 | expand the tokens from the orig_insn into the | |
5670 | stack of instructions that will not expand | |
e0001a05 | 5671 | unless required at relaxation time. */ |
e0001a05 | 5672 | |
43cd72b9 BW |
5673 | if (!cur_vinsn.inside_bundle) |
5674 | emit_single_op (&orig_insn); | |
5675 | else /* We are inside a bundle. */ | |
e0001a05 | 5676 | { |
43cd72b9 BW |
5677 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5678 | cur_vinsn.num_slots++; | |
5679 | if (*input_line_pointer == '}' | |
5680 | || *(input_line_pointer - 1) == '}' | |
5681 | || *(input_line_pointer - 2) == '}') | |
5682 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5683 | } |
5684 | ||
43cd72b9 BW |
5685 | /* We've just emitted a new instruction so clear the list of labels. */ |
5686 | xtensa_clear_insn_labels (); | |
a82c7d90 DW |
5687 | |
5688 | xtensa_check_frag_count (); | |
e0001a05 NC |
5689 | } |
5690 | ||
5691 | ||
43cd72b9 | 5692 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5693 | |
43cd72b9 BW |
5694 | /* For a .align directive, we mark the previous block with the alignment |
5695 | information. This will be placed in the object file in the | |
5696 | property section corresponding to this section. */ | |
e0001a05 | 5697 | |
43cd72b9 | 5698 | void |
7fa3d080 | 5699 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5700 | { |
5701 | if (linkrelax | |
b08b5071 | 5702 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5703 | && (fragP->fr_type == rs_align |
5704 | || fragP->fr_type == rs_align_code) | |
43cd72b9 BW |
5705 | && fragP->fr_offset > 0 |
5706 | && now_seg != bss_section) | |
e0001a05 | 5707 | { |
43cd72b9 BW |
5708 | fragP->tc_frag_data.is_align = TRUE; |
5709 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5710 | } |
5711 | ||
43cd72b9 | 5712 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5713 | { |
43cd72b9 BW |
5714 | int count; |
5715 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5716 | if (count != 0) | |
c138bc38 | 5717 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5718 | _("unaligned entry instruction")); |
e0001a05 | 5719 | } |
99ded152 BW |
5720 | |
5721 | if (linkrelax && fragP->fr_type == rs_org) | |
5722 | fragP->fr_subtype = RELAX_ORG; | |
e0001a05 | 5723 | } |
43cd72b9 | 5724 | |
e0001a05 NC |
5725 | |
5726 | /* TC_FRAG_INIT hook */ | |
5727 | ||
5728 | void | |
7fa3d080 | 5729 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5730 | { |
43cd72b9 | 5731 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5732 | } |
5733 | ||
5734 | ||
5735 | symbolS * | |
7fa3d080 | 5736 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5737 | { |
5738 | return NULL; | |
5739 | } | |
5740 | ||
5741 | ||
5742 | /* Round up a section size to the appropriate boundary. */ | |
5743 | ||
5744 | valueT | |
7fa3d080 | 5745 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5746 | { |
5747 | return size; /* Byte alignment is fine. */ | |
5748 | } | |
5749 | ||
5750 | ||
5751 | long | |
7fa3d080 | 5752 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5753 | { |
5754 | char *insn_p; | |
5755 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5756 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5757 | int opnum; |
43cd72b9 | 5758 | uint32 opnd_value; |
e0001a05 | 5759 | xtensa_opcode opcode; |
43cd72b9 BW |
5760 | xtensa_format fmt; |
5761 | int slot; | |
e0001a05 NC |
5762 | xtensa_isa isa = xtensa_default_isa; |
5763 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5764 | bfd_boolean alt_reloc; |
e0001a05 | 5765 | |
e0001a05 | 5766 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5767 | return 0; |
e0001a05 | 5768 | |
1bbb5f21 BW |
5769 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL) |
5770 | return addr; | |
5771 | ||
e0001a05 | 5772 | if (!insnbuf) |
43cd72b9 BW |
5773 | { |
5774 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5775 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5776 | } | |
e0001a05 NC |
5777 | |
5778 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5779 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5780 | fmt = xtensa_format_decode (isa, insnbuf); |
5781 | ||
5782 | if (fmt == XTENSA_UNDEFINED) | |
5783 | as_fatal (_("bad instruction format")); | |
5784 | ||
5785 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5786 | as_fatal (_("invalid relocation")); | |
5787 | ||
5788 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5789 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5790 | ||
30f725a1 BW |
5791 | /* Check for "alternate" relocations (operand not specified). None |
5792 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5793 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5794 | { | |
5795 | if (opcode != xtensa_l32r_opcode | |
5796 | && opcode != xtensa_const16_opcode) | |
5797 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5798 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5799 | return 0; |
e0001a05 NC |
5800 | } |
5801 | ||
43cd72b9 BW |
5802 | opnum = get_relaxable_immed (opcode); |
5803 | opnd_value = 0; | |
5804 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5805 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5806 | { |
5807 | as_bad_where (fixP->fx_file, | |
5808 | fixP->fx_line, | |
5809 | _("invalid relocation for operand %d of '%s'"), | |
5810 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5811 | return 0; |
e0001a05 | 5812 | } |
43cd72b9 BW |
5813 | return 0 - opnd_value; |
5814 | } | |
5815 | ||
5816 | ||
5817 | /* TC_FORCE_RELOCATION hook */ | |
5818 | ||
5819 | int | |
7fa3d080 | 5820 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5821 | { |
5822 | switch (fix->fx_r_type) | |
30f725a1 BW |
5823 | { |
5824 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5825 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5826 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5827 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5828 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5829 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5830 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5831 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5832 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5833 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5834 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5835 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5836 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5837 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5838 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5839 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5840 | return 1; |
5841 | default: | |
5842 | break; | |
e0001a05 NC |
5843 | } |
5844 | ||
43cd72b9 BW |
5845 | if (linkrelax && fix->fx_addsy |
5846 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5847 | return 1; | |
5848 | ||
5849 | return generic_force_reloc (fix); | |
5850 | } | |
5851 | ||
5852 | ||
30f725a1 BW |
5853 | /* TC_VALIDATE_FIX_SUB hook */ |
5854 | ||
5855 | int | |
5856 | xtensa_validate_fix_sub (fixS *fix) | |
5857 | { | |
5858 | segT add_symbol_segment, sub_symbol_segment; | |
5859 | ||
5860 | /* The difference of two symbols should be resolved by the assembler when | |
5861 | linkrelax is not set. If the linker may relax the section containing | |
5862 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5863 | the linker knows to adjust the difference value. */ | |
5864 | if (!linkrelax || fix->fx_addsy == NULL) | |
5865 | return 0; | |
5866 | ||
5867 | /* Make sure both symbols are in the same segment, and that segment is | |
5868 | "normal" and relaxable. If the segment is not "normal", then the | |
5869 | fix is not valid. If the segment is not "relaxable", then the fix | |
5870 | should have been handled earlier. */ | |
5871 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5872 | if (! SEG_NORMAL (add_symbol_segment) || | |
5873 | ! relaxable_section (add_symbol_segment)) | |
5874 | return 0; | |
5875 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5876 | return (sub_symbol_segment == add_symbol_segment); | |
5877 | } | |
5878 | ||
5879 | ||
43cd72b9 BW |
5880 | /* NO_PSEUDO_DOT hook */ |
5881 | ||
5882 | /* This function has nothing to do with pseudo dots, but this is the | |
5883 | nearest macro to where the check needs to take place. FIXME: This | |
5884 | seems wrong. */ | |
5885 | ||
5886 | bfd_boolean | |
7fa3d080 | 5887 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5888 | { |
5889 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5890 | as_bad (_("directives are not valid inside bundles")); | |
5891 | ||
5892 | /* This function must always return FALSE because it is called via a | |
5893 | macro that has nothing to do with bundling. */ | |
5894 | return FALSE; | |
e0001a05 NC |
5895 | } |
5896 | ||
5897 | ||
43cd72b9 | 5898 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5899 | |
5900 | void | |
7fa3d080 | 5901 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5902 | { |
43cd72b9 BW |
5903 | /* Set up the assembly state. */ |
5904 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5905 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5906 | } |
5907 | ||
5908 | ||
5909 | /* tc_fix_adjustable hook */ | |
5910 | ||
5911 | bfd_boolean | |
7fa3d080 | 5912 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 NC |
5913 | { |
5914 | /* We need the symbol name for the VTABLE entries. */ | |
5915 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5916 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5917 | return 0; | |
5918 | ||
5919 | return 1; | |
5920 | } | |
5921 | ||
5922 | ||
6a7eedfe BW |
5923 | /* tc_symbol_new_hook */ |
5924 | ||
5925 | symbolS *expr_symbols = NULL; | |
5926 | ||
3739860c | 5927 | void |
6a7eedfe BW |
5928 | xtensa_symbol_new_hook (symbolS *sym) |
5929 | { | |
fb227da0 | 5930 | if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section) |
6a7eedfe BW |
5931 | { |
5932 | symbol_get_tc (sym)->next_expr_symbol = expr_symbols; | |
5933 | expr_symbols = sym; | |
5934 | } | |
5935 | } | |
5936 | ||
5937 | ||
e0001a05 | 5938 | void |
55cf6793 | 5939 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5940 | { |
30f725a1 | 5941 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5942 | valueT val = 0; |
30f725a1 | 5943 | |
e7da6241 BW |
5944 | /* Subtracted symbols are only allowed for a few relocation types, and |
5945 | unless linkrelax is enabled, they should not make it to this point. */ | |
5946 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5947 | || fixP->fx_r_type == BFD_RELOC_16 | |
5948 | || fixP->fx_r_type == BFD_RELOC_8))) | |
5949 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
5950 | ||
30f725a1 | 5951 | switch (fixP->fx_r_type) |
e0001a05 | 5952 | { |
1bbb5f21 | 5953 | case BFD_RELOC_32_PCREL: |
30f725a1 BW |
5954 | case BFD_RELOC_32: |
5955 | case BFD_RELOC_16: | |
5956 | case BFD_RELOC_8: | |
e7da6241 | 5957 | if (fixP->fx_subsy) |
30f725a1 BW |
5958 | { |
5959 | switch (fixP->fx_r_type) | |
5960 | { | |
5961 | case BFD_RELOC_8: | |
5962 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
ea173078 | 5963 | fixP->fx_signed = 0; |
30f725a1 BW |
5964 | break; |
5965 | case BFD_RELOC_16: | |
5966 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
ea173078 | 5967 | fixP->fx_signed = 0; |
30f725a1 BW |
5968 | break; |
5969 | case BFD_RELOC_32: | |
5970 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
ea173078 | 5971 | fixP->fx_signed = 0; |
30f725a1 BW |
5972 | break; |
5973 | default: | |
5974 | break; | |
5975 | } | |
e0001a05 | 5976 | |
30f725a1 BW |
5977 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset |
5978 | - S_GET_VALUE (fixP->fx_subsy)); | |
5979 | ||
5980 | /* The difference value gets written out, and the DIFF reloc | |
5981 | identifies the address of the subtracted symbol (i.e., the one | |
5982 | with the lowest address). */ | |
5983 | *valP = val; | |
5984 | fixP->fx_offset -= val; | |
5985 | fixP->fx_subsy = NULL; | |
5986 | } | |
5987 | else if (! fixP->fx_addsy) | |
e0001a05 | 5988 | { |
30f725a1 | 5989 | val = *valP; |
e0001a05 | 5990 | fixP->fx_done = 1; |
30f725a1 | 5991 | } |
d47d412e BW |
5992 | /* fall through */ |
5993 | ||
5994 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
5995 | md_number_to_chars (fixpos, val, fixP->fx_size); |
5996 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5997 | break; | |
e0001a05 | 5998 | |
28dbbc02 BW |
5999 | case BFD_RELOC_XTENSA_TLSDESC_FN: |
6000 | case BFD_RELOC_XTENSA_TLSDESC_ARG: | |
6001 | case BFD_RELOC_XTENSA_TLS_TPOFF: | |
6002 | case BFD_RELOC_XTENSA_TLS_DTPOFF: | |
6003 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
6004 | md_number_to_chars (fixpos, 0, fixP->fx_size); | |
6005 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
6006 | break; | |
6007 | ||
30f725a1 BW |
6008 | case BFD_RELOC_XTENSA_SLOT0_OP: |
6009 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
6010 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
6011 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
6012 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
6013 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
6014 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
6015 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
6016 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
6017 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
6018 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
6019 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
6020 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
6021 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
6022 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
6023 | if (linkrelax) | |
6024 | { | |
6025 | /* Write the tentative value of a PC-relative relocation to a | |
6026 | local symbol into the instruction. The value will be ignored | |
6027 | by the linker, and it makes the object file disassembly | |
6028 | readable when all branch targets are encoded in relocations. */ | |
6029 | ||
9c2799c2 | 6030 | gas_assert (fixP->fx_addsy); |
20ee54e8 | 6031 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg |
30f725a1 BW |
6032 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) |
6033 | { | |
6034 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
6035 | - md_pcrel_from (fixP)); | |
6036 | (void) xg_apply_fix_value (fixP, val); | |
6037 | } | |
6038 | } | |
6039 | else if (! fixP->fx_addsy) | |
6040 | { | |
6041 | val = *valP; | |
6042 | if (xg_apply_fix_value (fixP, val)) | |
6043 | fixP->fx_done = 1; | |
6044 | } | |
6045 | break; | |
e0001a05 | 6046 | |
30f725a1 | 6047 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
28dbbc02 BW |
6048 | case BFD_RELOC_XTENSA_TLS_FUNC: |
6049 | case BFD_RELOC_XTENSA_TLS_ARG: | |
6050 | case BFD_RELOC_XTENSA_TLS_CALL: | |
30f725a1 BW |
6051 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
6052 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
6053 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
6054 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
6055 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
6056 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
6057 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
6058 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
6059 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
6060 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
6061 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
6062 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
6063 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
6064 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
6065 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
6066 | /* These all need to be resolved at link-time. Do nothing now. */ | |
6067 | break; | |
e0001a05 | 6068 | |
30f725a1 BW |
6069 | case BFD_RELOC_VTABLE_INHERIT: |
6070 | case BFD_RELOC_VTABLE_ENTRY: | |
6071 | fixP->fx_done = 0; | |
6072 | break; | |
e0001a05 | 6073 | |
30f725a1 BW |
6074 | default: |
6075 | as_bad (_("unhandled local relocation fix %s"), | |
6076 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
6077 | } |
6078 | } | |
6079 | ||
6080 | ||
6d4af3c2 | 6081 | const char * |
7fa3d080 | 6082 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 | 6083 | { |
499ac353 | 6084 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
e0001a05 NC |
6085 | } |
6086 | ||
6087 | ||
6088 | int | |
7fa3d080 | 6089 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 6090 | { |
34e41783 | 6091 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
6092 | } |
6093 | ||
6094 | ||
6095 | /* Translate internal representation of relocation info to BFD target | |
6096 | format. */ | |
6097 | ||
6098 | arelent * | |
30f725a1 | 6099 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
6100 | { |
6101 | arelent *reloc; | |
6102 | ||
325801bd TS |
6103 | reloc = XNEW (arelent); |
6104 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
e0001a05 NC |
6105 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
6106 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
6107 | ||
6108 | /* Make sure none of our internal relocations make it this far. | |
6109 | They'd better have been fully resolved by this point. */ | |
9c2799c2 | 6110 | gas_assert ((int) fixp->fx_r_type > 0); |
e0001a05 | 6111 | |
30f725a1 | 6112 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 6113 | |
e0001a05 NC |
6114 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
6115 | if (reloc->howto == NULL) | |
6116 | { | |
6117 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
6118 | _("cannot represent `%s' relocation in object file"), | |
6119 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
6120 | free (reloc->sym_ptr_ptr); |
6121 | free (reloc); | |
e0001a05 NC |
6122 | return NULL; |
6123 | } | |
6124 | ||
6125 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
1bbb5f21 | 6126 | as_fatal (_("internal error; cannot generate `%s' relocation"), |
43cd72b9 | 6127 | bfd_get_reloc_code_name (fixp->fx_r_type)); |
e0001a05 | 6128 | |
e0001a05 NC |
6129 | return reloc; |
6130 | } | |
6131 | ||
7fa3d080 BW |
6132 | \f |
6133 | /* Checks for resource conflicts between instructions. */ | |
6134 | ||
c138bc38 BW |
6135 | /* The func unit stuff could be implemented as bit-vectors rather |
6136 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
6137 | slow, we will switch it. */ |
6138 | ||
c138bc38 | 6139 | resource_table * |
7fa3d080 BW |
6140 | new_resource_table (void *data, |
6141 | int cycles, | |
6142 | int nu, | |
6143 | unit_num_copies_func uncf, | |
6144 | opcode_num_units_func onuf, | |
6145 | opcode_funcUnit_use_unit_func ouuf, | |
6146 | opcode_funcUnit_use_stage_func ousf) | |
6147 | { | |
6148 | int i; | |
325801bd | 6149 | resource_table *rt = XNEW (resource_table); |
7fa3d080 BW |
6150 | rt->data = data; |
6151 | rt->cycles = cycles; | |
6152 | rt->allocated_cycles = cycles; | |
6153 | rt->num_units = nu; | |
6154 | rt->unit_num_copies = uncf; | |
6155 | rt->opcode_num_units = onuf; | |
6156 | rt->opcode_unit_use = ouuf; | |
6157 | rt->opcode_unit_stage = ousf; | |
6158 | ||
add39d23 | 6159 | rt->units = XCNEWVEC (unsigned char *, cycles); |
7fa3d080 | 6160 | for (i = 0; i < cycles; i++) |
add39d23 | 6161 | rt->units[i] = XCNEWVEC (unsigned char, nu); |
7fa3d080 BW |
6162 | |
6163 | return rt; | |
6164 | } | |
6165 | ||
6166 | ||
c138bc38 | 6167 | void |
7fa3d080 BW |
6168 | clear_resource_table (resource_table *rt) |
6169 | { | |
6170 | int i, j; | |
6171 | for (i = 0; i < rt->allocated_cycles; i++) | |
6172 | for (j = 0; j < rt->num_units; j++) | |
6173 | rt->units[i][j] = 0; | |
6174 | } | |
6175 | ||
6176 | ||
6177 | /* We never shrink it, just fake it into thinking so. */ | |
6178 | ||
c138bc38 | 6179 | void |
7fa3d080 BW |
6180 | resize_resource_table (resource_table *rt, int cycles) |
6181 | { | |
6182 | int i, old_cycles; | |
6183 | ||
6184 | rt->cycles = cycles; | |
6185 | if (cycles <= rt->allocated_cycles) | |
6186 | return; | |
6187 | ||
6188 | old_cycles = rt->allocated_cycles; | |
6189 | rt->allocated_cycles = cycles; | |
6190 | ||
325801bd | 6191 | rt->units = XRESIZEVEC (unsigned char *, rt->units, rt->allocated_cycles); |
7fa3d080 | 6192 | for (i = 0; i < old_cycles; i++) |
325801bd | 6193 | rt->units[i] = XRESIZEVEC (unsigned char, rt->units[i], rt->num_units); |
7fa3d080 | 6194 | for (i = old_cycles; i < cycles; i++) |
add39d23 | 6195 | rt->units[i] = XCNEWVEC (unsigned char, rt->num_units); |
7fa3d080 BW |
6196 | } |
6197 | ||
6198 | ||
c138bc38 | 6199 | bfd_boolean |
7fa3d080 BW |
6200 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
6201 | { | |
6202 | int i; | |
6203 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6204 | ||
c138bc38 | 6205 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6206 | { |
6207 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6208 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
6209 | int copies_in_use = rt->units[stage + cycle][unit]; | |
6210 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
6211 | if (copies_in_use >= copies) | |
6212 | return FALSE; | |
6213 | } | |
6214 | return TRUE; | |
6215 | } | |
7fa3d080 | 6216 | |
c138bc38 BW |
6217 | |
6218 | void | |
7fa3d080 BW |
6219 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6220 | { | |
6221 | int i; | |
6222 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6223 | ||
c138bc38 | 6224 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6225 | { |
6226 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6227 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
6228 | /* Note that this allows resources to be oversubscribed. That's |
6229 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
6230 | resources_available reports when a resource is over-subscribed, |
6231 | so it's easy to tell. */ | |
6232 | rt->units[stage + cycle][unit]++; | |
6233 | } | |
6234 | } | |
6235 | ||
6236 | ||
c138bc38 | 6237 | void |
7fa3d080 BW |
6238 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
6239 | { | |
6240 | int i; | |
6241 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
6242 | ||
c138bc38 | 6243 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
6244 | { |
6245 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
6246 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
9c2799c2 | 6247 | gas_assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 6248 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
6249 | } |
6250 | } | |
c138bc38 | 6251 | |
7fa3d080 BW |
6252 | |
6253 | /* Wrapper functions make parameterized resource reservation | |
6254 | more convenient. */ | |
6255 | ||
c138bc38 | 6256 | int |
7fa3d080 BW |
6257 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
6258 | { | |
6259 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 6260 | return use->unit; |
7fa3d080 BW |
6261 | } |
6262 | ||
6263 | ||
c138bc38 | 6264 | int |
7fa3d080 BW |
6265 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
6266 | { | |
6267 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
6268 | return use->stage; | |
6269 | } | |
6270 | ||
6271 | ||
6272 | /* Note that this function does not check issue constraints, but | |
6273 | solely whether the hardware is available to execute the given | |
c138bc38 | 6274 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 6275 | write the same state, or access the same tieports. That is |
a1ace8d8 | 6276 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
6277 | |
6278 | static bfd_boolean | |
6279 | resources_conflict (vliw_insn *vinsn) | |
6280 | { | |
6281 | int i; | |
6282 | static resource_table *rt = NULL; | |
6283 | ||
6284 | /* This is the most common case by far. Optimize it. */ | |
6285 | if (vinsn->num_slots == 1) | |
6286 | return FALSE; | |
43cd72b9 | 6287 | |
c138bc38 | 6288 | if (rt == NULL) |
7fa3d080 BW |
6289 | { |
6290 | xtensa_isa isa = xtensa_default_isa; | |
6291 | rt = new_resource_table | |
77cba8a3 | 6292 | (isa, xtensa_num_pipe_stages, |
7fa3d080 BW |
6293 | xtensa_isa_num_funcUnits (isa), |
6294 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
6295 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
6296 | opcode_funcUnit_use_unit, | |
6297 | opcode_funcUnit_use_stage); | |
6298 | } | |
43cd72b9 | 6299 | |
7fa3d080 | 6300 | clear_resource_table (rt); |
43cd72b9 | 6301 | |
7fa3d080 BW |
6302 | for (i = 0; i < vinsn->num_slots; i++) |
6303 | { | |
6304 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
6305 | return TRUE; | |
6306 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
6307 | } | |
e0001a05 | 6308 | |
7fa3d080 BW |
6309 | return FALSE; |
6310 | } | |
e0001a05 | 6311 | |
7fa3d080 BW |
6312 | \f |
6313 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 6314 | |
7fa3d080 BW |
6315 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
6316 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 6317 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
6318 | |
6319 | ||
43cd72b9 BW |
6320 | /* We have reached the end of a bundle; emit into the frag. */ |
6321 | ||
e0001a05 | 6322 | static void |
7fa3d080 | 6323 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 6324 | { |
43cd72b9 BW |
6325 | IStack slotstack; |
6326 | int i; | |
bf3d1399 | 6327 | int slots; |
e0001a05 | 6328 | |
43cd72b9 | 6329 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
6330 | { |
6331 | xg_clear_vinsn (vinsn); | |
6332 | return; | |
6333 | } | |
43cd72b9 BW |
6334 | |
6335 | /* First, find a format that works. */ | |
6336 | if (vinsn->format == XTENSA_UNDEFINED) | |
6337 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6338 | ||
bf3d1399 AM |
6339 | slots = xtensa_format_num_slots (xtensa_default_isa, vinsn->format); |
6340 | if (slots > 1 | |
19fc3723 SA |
6341 | && produce_flix == FLIX_NONE) |
6342 | { | |
6343 | as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix.")); | |
6344 | xg_clear_vinsn (vinsn); | |
6345 | return; | |
6346 | } | |
6347 | ||
43cd72b9 BW |
6348 | if (vinsn->format == XTENSA_UNDEFINED) |
6349 | { | |
3b4dbbbf | 6350 | as_bad (_("couldn't find a valid instruction format")); |
43cd72b9 BW |
6351 | fprintf (stderr, _(" ops were: ")); |
6352 | for (i = 0; i < vinsn->num_slots; i++) | |
6353 | fprintf (stderr, _(" %s;"), | |
6354 | xtensa_opcode_name (xtensa_default_isa, | |
6355 | vinsn->slots[i].opcode)); | |
6356 | fprintf (stderr, _("\n")); | |
6357 | xg_clear_vinsn (vinsn); | |
6358 | return; | |
6359 | } | |
6360 | ||
bf3d1399 | 6361 | if (vinsn->num_slots != slots) |
e0001a05 | 6362 | { |
bf3d1399 AM |
6363 | as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"), |
6364 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
6e98b342 | 6365 | slots, vinsn->num_slots); |
43cd72b9 BW |
6366 | xg_clear_vinsn (vinsn); |
6367 | return; | |
6368 | } | |
e0001a05 | 6369 | |
c138bc38 | 6370 | if (resources_conflict (vinsn)) |
43cd72b9 | 6371 | { |
3b4dbbbf | 6372 | as_bad (_("illegal resource usage in bundle")); |
43cd72b9 BW |
6373 | fprintf (stderr, " ops were: "); |
6374 | for (i = 0; i < vinsn->num_slots; i++) | |
6375 | fprintf (stderr, " %s;", | |
6376 | xtensa_opcode_name (xtensa_default_isa, | |
6377 | vinsn->slots[i].opcode)); | |
6378 | fprintf (stderr, "\n"); | |
6379 | xg_clear_vinsn (vinsn); | |
6380 | return; | |
6381 | } | |
6382 | ||
6383 | for (i = 0; i < vinsn->num_slots; i++) | |
6384 | { | |
6385 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6386 | { |
43cd72b9 BW |
6387 | symbolS *lit_sym = NULL; |
6388 | int j; | |
6389 | bfd_boolean e = FALSE; | |
6390 | bfd_boolean saved_density = density_supported; | |
6391 | ||
6392 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6393 | if (vinsn->num_slots > 1) | |
6394 | density_supported = FALSE; | |
6395 | ||
6396 | istack_init (&slotstack); | |
6397 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6398 | { |
43cd72b9 BW |
6399 | vinsn->slots[i].opcode = |
6400 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6401 | vinsn->format, i); | |
6402 | vinsn->slots[i].ntok = 0; | |
6403 | } | |
e0001a05 | 6404 | |
43cd72b9 BW |
6405 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6406 | { | |
6407 | e = TRUE; | |
6408 | continue; | |
e0001a05 | 6409 | } |
e0001a05 | 6410 | |
43cd72b9 | 6411 | density_supported = saved_density; |
e0001a05 | 6412 | |
43cd72b9 BW |
6413 | if (e) |
6414 | { | |
6415 | xg_clear_vinsn (vinsn); | |
6416 | return; | |
6417 | } | |
e0001a05 | 6418 | |
0fa77c95 | 6419 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6420 | { |
6421 | TInsn *insn = &slotstack.insn[j]; | |
6422 | if (insn->insn_type == ITYPE_LITERAL) | |
6423 | { | |
9c2799c2 | 6424 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
6425 | lit_sym = xg_assemble_literal (insn); |
6426 | } | |
6427 | else | |
6428 | { | |
9c2799c2 | 6429 | gas_assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6430 | if (lit_sym) |
6431 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6432 | if (j != slotstack.ninsn - 1) |
6433 | emit_single_op (insn); | |
43cd72b9 BW |
6434 | } |
6435 | } | |
6436 | ||
6437 | if (vinsn->num_slots > 1) | |
6438 | { | |
6439 | if (opcode_fits_format_slot | |
6440 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6441 | vinsn->format, i)) | |
6442 | { | |
6443 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6444 | } | |
6445 | else | |
6446 | { | |
b2d179be | 6447 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6448 | if (vinsn->format == XTENSA_UNDEFINED) |
6449 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6450 | else | |
c138bc38 | 6451 | vinsn->slots[i].opcode |
43cd72b9 BW |
6452 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6453 | vinsn->format, i); | |
6454 | ||
6455 | vinsn->slots[i].ntok = 0; | |
6456 | } | |
6457 | } | |
6458 | else | |
6459 | { | |
6460 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6461 | vinsn->format = XTENSA_UNDEFINED; | |
6462 | } | |
6463 | } | |
6464 | } | |
6465 | ||
6466 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6467 | if (resources_conflict (vinsn)) |
43cd72b9 | 6468 | { |
3b4dbbbf | 6469 | as_bad (_("illegal resource usage in bundle")); |
43cd72b9 BW |
6470 | fprintf (stderr, " ops were: "); |
6471 | for (i = 0; i < vinsn->num_slots; i++) | |
6472 | fprintf (stderr, " %s;", | |
6473 | xtensa_opcode_name (xtensa_default_isa, | |
6474 | vinsn->slots[i].opcode)); | |
6475 | fprintf (stderr, "\n"); | |
6476 | xg_clear_vinsn (vinsn); | |
6477 | return; | |
6478 | } | |
6479 | ||
6480 | /* First, find a format that works. */ | |
6481 | if (vinsn->format == XTENSA_UNDEFINED) | |
6482 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6483 | ||
6484 | xg_assemble_vliw_tokens (vinsn); | |
6485 | ||
6486 | xg_clear_vinsn (vinsn); | |
a82c7d90 DW |
6487 | |
6488 | xtensa_check_frag_count (); | |
43cd72b9 BW |
6489 | } |
6490 | ||
6491 | ||
6492 | /* Given an vliw instruction, what conflicts are there in register | |
6493 | usage and in writes to states and queues? | |
6494 | ||
6495 | This function does two things: | |
6496 | 1. Reports an error when a vinsn contains illegal combinations | |
6497 | of writes to registers states or queues. | |
6498 | 2. Marks individual tinsns as not relaxable if the combination | |
6499 | contains antidependencies. | |
6500 | ||
6501 | Job 2 handles things like swap semantics in instructions that need | |
6502 | to be relaxed. For example, | |
6503 | ||
6504 | addi a0, a1, 100000 | |
6505 | ||
6506 | normally would be relaxed to | |
6507 | ||
6508 | l32r a0, some_label | |
6509 | add a0, a1, a0 | |
6510 | ||
6511 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6512 | ||
6513 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6514 | ||
6515 | then we can't relax it into | |
6516 | ||
6517 | l32r a0, some_label | |
6518 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6519 | ||
6520 | because the value of a0 is trashed before the second add can read it. */ | |
6521 | ||
7fa3d080 BW |
6522 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6523 | ||
43cd72b9 | 6524 | static bfd_boolean |
7fa3d080 | 6525 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6526 | { |
6527 | int i, j; | |
6528 | int branches = 0; | |
6529 | xtensa_isa isa = xtensa_default_isa; | |
6530 | ||
9c2799c2 | 6531 | gas_assert (!past_xtensa_end); |
43cd72b9 BW |
6532 | |
6533 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6534 | { | |
6535 | TInsn *op1 = &vinsn->slots[i]; | |
6536 | if (op1->is_specific_opcode) | |
6537 | op1->keep_wide = TRUE; | |
6538 | else | |
6539 | op1->keep_wide = FALSE; | |
6540 | } | |
6541 | ||
6542 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6543 | { | |
6544 | TInsn *op1 = &vinsn->slots[i]; | |
6545 | ||
6546 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6547 | branches++; | |
6548 | ||
6549 | for (j = 0; j < vinsn->num_slots; j++) | |
6550 | { | |
6551 | if (i != j) | |
6552 | { | |
6553 | TInsn *op2 = &vinsn->slots[j]; | |
6554 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6555 | switch (conflict_type) | |
6556 | { | |
6557 | case 'c': | |
6558 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6559 | xtensa_opcode_name (isa, op1->opcode), i, | |
6560 | xtensa_opcode_name (isa, op2->opcode), j); | |
6561 | return TRUE; | |
6562 | case 'd': | |
6563 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6564 | xtensa_opcode_name (isa, op1->opcode), i, | |
6565 | xtensa_opcode_name (isa, op2->opcode), j); | |
6566 | return TRUE; | |
6567 | case 'e': | |
53dfbcc7 | 6568 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6569 | xtensa_opcode_name (isa, op1->opcode), i, |
6570 | xtensa_opcode_name (isa, op2->opcode), j); | |
6571 | return TRUE; | |
6572 | case 'f': | |
53dfbcc7 | 6573 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6574 | xtensa_opcode_name (isa, op1->opcode), i, |
6575 | xtensa_opcode_name (isa, op2->opcode), j); | |
6576 | return TRUE; | |
6577 | default: | |
6578 | /* Everything is OK. */ | |
6579 | break; | |
6580 | } | |
6581 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6582 | || conflict_type == 'a'); | |
6583 | } | |
6584 | } | |
6585 | } | |
6586 | ||
6587 | if (branches > 1) | |
6588 | { | |
6589 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6590 | return TRUE; | |
6591 | } | |
6592 | ||
6593 | return FALSE; | |
6594 | } | |
6595 | ||
6596 | ||
a1ace8d8 | 6597 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6598 | Cases found are: |
6599 | ||
6600 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6601 | case B: no relationship between what is read and written (both could | |
6602 | read the same reg though) | |
c138bc38 | 6603 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6604 | bundle) |
6605 | case D: t1 writes a state that t2 also writes | |
6606 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6607 | case F: two volatile queue accesses |
43cd72b9 BW |
6608 | */ |
6609 | ||
6610 | static char | |
7fa3d080 | 6611 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6612 | { |
6613 | xtensa_isa isa = xtensa_default_isa; | |
6614 | xtensa_regfile t1_regfile, t2_regfile; | |
6615 | int t1_reg, t2_reg; | |
6616 | int t1_base_reg, t1_last_reg; | |
6617 | int t2_base_reg, t2_last_reg; | |
6618 | char t1_inout, t2_inout; | |
6619 | int i, j; | |
6620 | char conflict = 'b'; | |
6621 | int t1_states; | |
6622 | int t2_states; | |
6623 | int t1_interfaces; | |
6624 | int t2_interfaces; | |
6625 | bfd_boolean t1_volatile = FALSE; | |
6626 | bfd_boolean t2_volatile = FALSE; | |
6627 | ||
6628 | /* Check registers. */ | |
6629 | for (j = 0; j < t2->ntok; j++) | |
6630 | { | |
6631 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6632 | continue; | |
6633 | ||
6634 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6635 | t2_base_reg = t2->tok[j].X_add_number; | |
6636 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6637 | ||
6638 | for (i = 0; i < t1->ntok; i++) | |
6639 | { | |
6640 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6641 | continue; | |
6642 | ||
6643 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6644 | ||
6645 | if (t1_regfile != t2_regfile) | |
6646 | continue; | |
6647 | ||
6648 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6649 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6650 | ||
6651 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6652 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6653 | { | |
6654 | if (t1_inout == 'm' || t1_inout == 'o' | |
6655 | || t2_inout == 'm' || t2_inout == 'o') | |
6656 | { | |
6657 | conflict = 'a'; | |
6658 | continue; | |
6659 | } | |
6660 | } | |
6661 | ||
6662 | t1_base_reg = t1->tok[i].X_add_number; | |
6663 | t1_last_reg = (t1_base_reg | |
6664 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6665 | ||
6666 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6667 | { | |
6668 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6669 | { | |
6670 | if (t1_reg != t2_reg) | |
6671 | continue; | |
6672 | ||
6673 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6674 | { |
6675 | conflict = 'a'; | |
6676 | continue; | |
6677 | } | |
43cd72b9 | 6678 | |
7fa3d080 BW |
6679 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6680 | { | |
6681 | conflict = 'a'; | |
6682 | continue; | |
6683 | } | |
43cd72b9 | 6684 | |
7fa3d080 BW |
6685 | if (t1_inout != 'i' && t2_inout != 'i') |
6686 | return 'c'; | |
6687 | } | |
6688 | } | |
6689 | } | |
6690 | } | |
43cd72b9 | 6691 | |
7fa3d080 BW |
6692 | /* Check states. */ |
6693 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6694 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6695 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6696 | { |
7fa3d080 BW |
6697 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6698 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6699 | for (i = 0; i < t1_states; i++) | |
6700 | { | |
6701 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6702 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
1fa3cd83 | 6703 | if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1) |
7fa3d080 | 6704 | continue; |
43cd72b9 | 6705 | |
7fa3d080 BW |
6706 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6707 | { | |
6708 | conflict = 'a'; | |
6709 | continue; | |
6710 | } | |
c138bc38 | 6711 | |
7fa3d080 BW |
6712 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6713 | { | |
6714 | conflict = 'a'; | |
6715 | continue; | |
6716 | } | |
c138bc38 | 6717 | |
7fa3d080 BW |
6718 | if (t1_inout != 'i' && t2_inout != 'i') |
6719 | return 'd'; | |
c138bc38 | 6720 | } |
7fa3d080 | 6721 | } |
43cd72b9 | 6722 | |
7fa3d080 BW |
6723 | /* Check tieports. */ |
6724 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6725 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6726 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6727 | { |
7fa3d080 BW |
6728 | xtensa_interface t2_int |
6729 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6730 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6731 | ||
53dfbcc7 | 6732 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6733 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6734 | t2_volatile = TRUE; |
a1ace8d8 | 6735 | |
7fa3d080 BW |
6736 | for (i = 0; i < t1_interfaces; i++) |
6737 | { | |
6738 | xtensa_interface t1_int | |
6739 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6740 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6741 | |
53dfbcc7 | 6742 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6743 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6744 | t1_volatile = TRUE; |
a1ace8d8 BW |
6745 | |
6746 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6747 | return 'f'; | |
c138bc38 | 6748 | |
7fa3d080 BW |
6749 | if (t1_int != t2_int) |
6750 | continue; | |
c138bc38 | 6751 | |
7fa3d080 BW |
6752 | if (t2_inout == 'i' && t1_inout == 'o') |
6753 | { | |
6754 | conflict = 'a'; | |
6755 | continue; | |
6756 | } | |
c138bc38 | 6757 | |
7fa3d080 BW |
6758 | if (t1_inout == 'i' && t2_inout == 'o') |
6759 | { | |
6760 | conflict = 'a'; | |
6761 | continue; | |
6762 | } | |
c138bc38 | 6763 | |
7fa3d080 BW |
6764 | if (t1_inout != 'i' && t2_inout != 'i') |
6765 | return 'e'; | |
6766 | } | |
43cd72b9 | 6767 | } |
c138bc38 | 6768 | |
7fa3d080 | 6769 | return conflict; |
43cd72b9 BW |
6770 | } |
6771 | ||
6772 | ||
6773 | static xtensa_format | |
7fa3d080 | 6774 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6775 | { |
6776 | /* Right now we assume that the ops within the vinsn are properly | |
6777 | ordered for the slots that the programmer wanted them in. In | |
6778 | other words, we don't rearrange the ops in hopes of finding a | |
6779 | better format. The scheduler handles that. */ | |
6780 | ||
6781 | xtensa_isa isa = xtensa_default_isa; | |
6782 | xtensa_format format; | |
43cd72b9 BW |
6783 | xtensa_opcode nop_opcode = xtensa_nop_opcode; |
6784 | ||
65738a7d BW |
6785 | if (vinsn->num_slots == 1) |
6786 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6787 | ||
43cd72b9 BW |
6788 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6789 | { | |
d8392fd9 SA |
6790 | vliw_insn v_copy; |
6791 | xg_copy_vinsn (&v_copy, vinsn); | |
43cd72b9 BW |
6792 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) |
6793 | { | |
6794 | int slot; | |
6795 | int fit = 0; | |
6796 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6797 | { | |
6798 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6799 | { | |
6800 | v_copy.slots[slot].opcode = | |
6801 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6802 | v_copy.slots[slot].ntok = 0; | |
6803 | } | |
6804 | ||
6805 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6806 | format, slot)) | |
6807 | fit++; | |
7fa3d080 | 6808 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6809 | { |
7fa3d080 BW |
6810 | TInsn widened; |
6811 | /* Try the widened version. */ | |
6812 | if (!v_copy.slots[slot].keep_wide | |
6813 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6814 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6815 | &widened, TRUE) | |
7fa3d080 BW |
6816 | && opcode_fits_format_slot (widened.opcode, |
6817 | format, slot)) | |
43cd72b9 | 6818 | { |
7fa3d080 BW |
6819 | v_copy.slots[slot] = widened; |
6820 | fit++; | |
43cd72b9 BW |
6821 | } |
6822 | } | |
6823 | } | |
6824 | if (fit == v_copy.num_slots) | |
6825 | { | |
d8392fd9 | 6826 | xg_copy_vinsn (vinsn, &v_copy); |
43cd72b9 BW |
6827 | xtensa_format_encode (isa, format, vinsn->insnbuf); |
6828 | vinsn->format = format; | |
6829 | break; | |
6830 | } | |
6831 | } | |
6832 | } | |
6833 | ||
6834 | if (format == xtensa_isa_num_formats (isa)) | |
6835 | return XTENSA_UNDEFINED; | |
6836 | ||
6837 | return format; | |
6838 | } | |
6839 | ||
6840 | ||
6841 | /* Return the additional space needed in a frag | |
6842 | for possible relaxations of any ops in a VLIW insn. | |
6843 | Also fill out the relaxations that might be required of | |
6844 | each tinsn in the vinsn. */ | |
6845 | ||
6846 | static int | |
e7da6241 | 6847 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6848 | { |
e7da6241 | 6849 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6850 | int extra_space = 0; |
6851 | int slot; | |
6852 | ||
6853 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6854 | { | |
6855 | TInsn *tinsn = &vinsn->slots[slot]; | |
6856 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6857 | { | |
6858 | /* A narrow instruction could be widened later to help | |
6859 | alignment issues. */ | |
84b08ed9 | 6860 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6861 | && !tinsn->is_specific_opcode |
6862 | && vinsn->num_slots == 1) | |
6863 | { | |
6864 | /* Difference in bytes between narrow and wide insns... */ | |
6865 | extra_space += 1; | |
6866 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6867 | } |
6868 | } | |
6869 | else | |
6870 | { | |
b08b5071 BW |
6871 | if (workaround_b_j_loop_end |
6872 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6873 | && use_transform ()) |
6874 | { | |
6875 | /* Add 2 of these. */ | |
6876 | extra_space += 3; /* for the nop size */ | |
6877 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6878 | } | |
c138bc38 | 6879 | |
43cd72b9 BW |
6880 | /* Need to assemble it with space for the relocation. */ |
6881 | if (xg_is_relaxable_insn (tinsn, 0) | |
6882 | && !tinsn->is_specific_opcode) | |
6883 | { | |
6884 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6885 | int max_literal_size = | |
6886 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6887 | |
43cd72b9 | 6888 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6889 | |
43cd72b9 | 6890 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6891 | extra_space += max_size; |
6892 | } | |
6893 | else | |
6894 | { | |
e7da6241 BW |
6895 | /* A fix record will be added for this instruction prior |
6896 | to relaxation, so make it end the frag. */ | |
6897 | finish_frag = TRUE; | |
43cd72b9 BW |
6898 | } |
6899 | } | |
6900 | } | |
e7da6241 | 6901 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6902 | return extra_space; |
6903 | } | |
6904 | ||
6905 | ||
6906 | static void | |
b2d179be | 6907 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6908 | { |
6909 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6910 | int slot, chosen_slot; |
43cd72b9 | 6911 | |
b2d179be | 6912 | vinsn->format = xg_get_single_format (tinsn->opcode); |
9c2799c2 | 6913 | gas_assert (vinsn->format != XTENSA_UNDEFINED); |
b2d179be | 6914 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); |
43cd72b9 | 6915 | |
b2d179be BW |
6916 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6917 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6918 | { |
b2d179be BW |
6919 | if (slot == chosen_slot) |
6920 | vinsn->slots[slot] = *tinsn; | |
6921 | else | |
6922 | { | |
6923 | vinsn->slots[slot].opcode = | |
6924 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6925 | vinsn->slots[slot].ntok = 0; | |
6926 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6927 | } | |
43cd72b9 | 6928 | } |
43cd72b9 BW |
6929 | } |
6930 | ||
6931 | ||
6932 | static bfd_boolean | |
7fa3d080 | 6933 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6934 | { |
6935 | int i; | |
6936 | IStack istack; /* put instructions into here */ | |
6937 | symbolS *lit_sym = NULL; | |
6938 | symbolS *label_sym = NULL; | |
6939 | ||
6940 | istack_init (&istack); | |
6941 | ||
6942 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
6943 | Because the scheduling and bundling characteristics of movi and |
6944 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 6945 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 6946 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
6947 | || orig_insn->opcode == xtensa_movi_n_opcode) |
6948 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 6949 | && (orig_insn->tok[1].X_op == O_symbol |
28dbbc02 BW |
6950 | || orig_insn->tok[1].X_op == O_pltrel |
6951 | || orig_insn->tok[1].X_op == O_tlsfunc | |
6952 | || orig_insn->tok[1].X_op == O_tlsarg | |
6953 | || orig_insn->tok[1].X_op == O_tpoff | |
6954 | || orig_insn->tok[1].X_op == O_dtpoff) | |
482fd9f9 | 6955 | && !orig_insn->is_specific_opcode && use_transform ()) |
43cd72b9 BW |
6956 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
6957 | else | |
6958 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6959 | return TRUE; | |
6960 | ||
6961 | for (i = 0; i < istack.ninsn; i++) | |
6962 | { | |
6963 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 6964 | switch (insn->insn_type) |
43cd72b9 BW |
6965 | { |
6966 | case ITYPE_LITERAL: | |
9c2799c2 | 6967 | gas_assert (lit_sym == NULL); |
43cd72b9 BW |
6968 | lit_sym = xg_assemble_literal (insn); |
6969 | break; | |
6970 | case ITYPE_LABEL: | |
6971 | { | |
6972 | static int relaxed_sym_idx = 0; | |
325801bd | 6973 | char *label = XNEWVEC (char, strlen (FAKE_LABEL_NAME) + 12); |
43cd72b9 BW |
6974 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); |
6975 | colon (label); | |
9c2799c2 | 6976 | gas_assert (label_sym == NULL); |
43cd72b9 | 6977 | label_sym = symbol_find_or_make (label); |
9c2799c2 | 6978 | gas_assert (label_sym); |
43cd72b9 BW |
6979 | free (label); |
6980 | } | |
6981 | break; | |
6982 | case ITYPE_INSN: | |
b2d179be BW |
6983 | { |
6984 | vliw_insn v; | |
6985 | if (lit_sym) | |
6986 | xg_resolve_literals (insn, lit_sym); | |
6987 | if (label_sym) | |
6988 | xg_resolve_labels (insn, label_sym); | |
6989 | xg_init_vinsn (&v); | |
6990 | bundle_tinsn (insn, &v); | |
6991 | finish_vinsn (&v); | |
6992 | xg_free_vinsn (&v); | |
6993 | } | |
43cd72b9 BW |
6994 | break; |
6995 | default: | |
9c2799c2 | 6996 | gas_assert (0); |
43cd72b9 BW |
6997 | break; |
6998 | } | |
6999 | } | |
7000 | return FALSE; | |
7001 | } | |
7002 | ||
7003 | ||
34e41783 BW |
7004 | static int |
7005 | total_frag_text_expansion (fragS *fragP) | |
7006 | { | |
7007 | int slot; | |
7008 | int total_expansion = 0; | |
7009 | ||
62af60e2 | 7010 | for (slot = 0; slot < config_max_slots; slot++) |
34e41783 BW |
7011 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; |
7012 | ||
7013 | return total_expansion; | |
7014 | } | |
7015 | ||
7016 | ||
43cd72b9 BW |
7017 | /* Emit a vliw instruction to the current fragment. */ |
7018 | ||
7fa3d080 BW |
7019 | static void |
7020 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 7021 | { |
e7da6241 | 7022 | bfd_boolean finish_frag; |
43cd72b9 BW |
7023 | bfd_boolean is_jump = FALSE; |
7024 | bfd_boolean is_branch = FALSE; | |
7025 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 BW |
7026 | int insn_size; |
7027 | int extra_space; | |
7028 | char *f = NULL; | |
7029 | int slot; | |
b224e962 BW |
7030 | struct dwarf2_line_info debug_line; |
7031 | bfd_boolean loc_directive_seen = FALSE; | |
7032 | TInsn *tinsn; | |
43cd72b9 | 7033 | |
b224e962 | 7034 | memset (&debug_line, 0, sizeof (struct dwarf2_line_info)); |
43cd72b9 BW |
7035 | |
7036 | if (generating_literals) | |
7037 | { | |
7038 | static int reported = 0; | |
7039 | if (reported < 4) | |
7040 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
7041 | _("cannot assemble into a literal fragment")); | |
7042 | if (reported == 3) | |
7043 | as_bad (_("...")); | |
7044 | reported++; | |
7045 | return; | |
7046 | } | |
7047 | ||
7048 | if (frag_now_fix () != 0 | |
b08b5071 | 7049 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 7050 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
28a0da39 | 7051 | || (!use_transform ()) != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
7052 | || (directive_state[directive_longcalls] |
7053 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
7054 | || (directive_state[directive_absolute_literals] |
7055 | != frag_now->tc_frag_data.use_absolute_literals))) | |
7056 | { | |
7057 | frag_wane (frag_now); | |
7058 | frag_new (0); | |
7059 | xtensa_set_frag_assembly_state (frag_now); | |
7060 | } | |
7061 | ||
7062 | if (workaround_a0_b_retw | |
7063 | && vinsn->num_slots == 1 | |
7064 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
7065 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
7066 | && use_transform ()) | |
7067 | { | |
7068 | has_a0_b_retw = TRUE; | |
7069 | ||
7070 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
7071 | After the first assembly pass we will check all of them and | |
7072 | add a nop if needed. */ | |
7073 | frag_now->tc_frag_data.is_insn = TRUE; | |
7074 | frag_var (rs_machine_dependent, 4, 4, | |
7075 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
7076 | frag_now->fr_symbol, | |
7077 | frag_now->fr_offset, | |
7078 | NULL); | |
7079 | xtensa_set_frag_assembly_state (frag_now); | |
7080 | frag_now->tc_frag_data.is_insn = TRUE; | |
7081 | frag_var (rs_machine_dependent, 4, 4, | |
7082 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
7083 | frag_now->fr_symbol, | |
7084 | frag_now->fr_offset, | |
7085 | NULL); | |
7086 | xtensa_set_frag_assembly_state (frag_now); | |
7087 | } | |
7088 | ||
b224e962 | 7089 | for (slot = 0; slot < vinsn->num_slots; slot++) |
43cd72b9 | 7090 | { |
b224e962 BW |
7091 | tinsn = &vinsn->slots[slot]; |
7092 | ||
43cd72b9 | 7093 | /* See if the instruction implies an aligned section. */ |
b224e962 | 7094 | if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1) |
43cd72b9 | 7095 | record_alignment (now_seg, 2); |
c138bc38 | 7096 | |
b224e962 BW |
7097 | /* Determine the best line number for debug info. */ |
7098 | if ((tinsn->loc_directive_seen || !loc_directive_seen) | |
7099 | && (tinsn->debug_line.filenum != debug_line.filenum | |
7100 | || tinsn->debug_line.line < debug_line.line | |
7101 | || tinsn->debug_line.column < debug_line.column)) | |
7102 | debug_line = tinsn->debug_line; | |
7103 | if (tinsn->loc_directive_seen) | |
7104 | loc_directive_seen = TRUE; | |
43cd72b9 BW |
7105 | } |
7106 | ||
7107 | /* Special cases for instructions that force an alignment... */ | |
7108 | /* None of these opcodes are bundle-able. */ | |
7109 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
7110 | { | |
d77b99c9 | 7111 | int max_fill; |
c138bc38 | 7112 | |
05d58145 BW |
7113 | /* Remember the symbol that marks the end of the loop in the frag |
7114 | that marks the start of the loop. This way we can easily find | |
7115 | the end of the loop at the beginning, without adding special code | |
7116 | to mark the loop instructions themselves. */ | |
7117 | symbolS *target_sym = NULL; | |
7118 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
7119 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
7120 | ||
43cd72b9 BW |
7121 | xtensa_set_frag_assembly_state (frag_now); |
7122 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 7123 | |
43cd72b9 BW |
7124 | max_fill = get_text_align_max_fill_size |
7125 | (get_text_align_power (xtensa_fetch_width), | |
7126 | TRUE, frag_now->tc_frag_data.is_no_density); | |
7127 | ||
7128 | if (use_transform ()) | |
7129 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 7130 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7131 | else |
c138bc38 | 7132 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 7133 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 7134 | xtensa_set_frag_assembly_state (frag_now); |
43cd72b9 BW |
7135 | } |
7136 | ||
b08b5071 | 7137 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
7138 | && !vinsn->slots[0].is_specific_opcode) |
7139 | { | |
7140 | xtensa_mark_literal_pool_location (); | |
c3ea6048 | 7141 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
7142 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); |
7143 | } | |
7144 | ||
7145 | if (vinsn->num_slots == 1) | |
7146 | { | |
7147 | if (workaround_a0_b_retw && use_transform ()) | |
7148 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
7149 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
7150 | ||
7151 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
7152 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
7153 | } | |
7154 | else | |
7155 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
7156 | ||
7157 | insn_size = xtensa_format_length (isa, vinsn->format); | |
7158 | ||
e7da6241 | 7159 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
7160 | |
7161 | /* vinsn_to_insnbuf will produce the error. */ | |
7162 | if (vinsn->format != XTENSA_UNDEFINED) | |
7163 | { | |
d77b99c9 | 7164 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
7165 | xtensa_set_frag_assembly_state (frag_now); |
7166 | frag_now->tc_frag_data.is_insn = TRUE; | |
7167 | } | |
7168 | ||
e7da6241 | 7169 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
7170 | if (vinsn->format == XTENSA_UNDEFINED) |
7171 | return; | |
7172 | ||
d77b99c9 | 7173 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 7174 | |
b224e962 BW |
7175 | if (debug_type == DEBUG_DWARF2 || loc_directive_seen) |
7176 | dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space), | |
7177 | &debug_line); | |
43cd72b9 BW |
7178 | |
7179 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
7180 | { | |
b224e962 | 7181 | tinsn = &vinsn->slots[slot]; |
43cd72b9 | 7182 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; |
7c834684 | 7183 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 7184 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 | 7185 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
b46824bd MF |
7186 | if (tinsn->opcode == xtensa_l32r_opcode) |
7187 | { | |
7188 | frag_now->tc_frag_data.literal_frags[slot] = | |
7189 | tinsn->tok[1].X_add_symbol->sy_frag; | |
7190 | } | |
43cd72b9 BW |
7191 | if (tinsn->literal_space != 0) |
7192 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
19e8f41a | 7193 | frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg; |
43cd72b9 BW |
7194 | |
7195 | if (tinsn->subtype == RELAX_NARROW) | |
9c2799c2 | 7196 | gas_assert (vinsn->num_slots == 1); |
43cd72b9 BW |
7197 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) |
7198 | is_jump = TRUE; | |
7199 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
7200 | is_branch = TRUE; | |
7201 | ||
e7da6241 BW |
7202 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
7203 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
7204 | finish_frag = TRUE; |
7205 | } | |
7206 | ||
7207 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 7208 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
7209 | |
7210 | if (finish_frag) | |
7211 | { | |
7212 | frag_variant (rs_machine_dependent, | |
7213 | extra_space, extra_space, RELAX_SLOTS, | |
7214 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
7215 | xtensa_set_frag_assembly_state (frag_now); | |
7216 | } | |
7217 | ||
7218 | /* Special cases for loops: | |
7219 | close_loop_end should be inserted AFTER short_loop. | |
7220 | Make sure that CLOSE loops are processed BEFORE short_loops | |
7221 | when converting them. */ | |
7222 | ||
7223 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 7224 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
7225 | && !vinsn->slots[0].is_specific_opcode) |
7226 | { | |
7227 | if (workaround_short_loop && use_transform ()) | |
7228 | { | |
7229 | maybe_has_short_loop = TRUE; | |
7230 | frag_now->tc_frag_data.is_insn = TRUE; | |
7231 | frag_var (rs_machine_dependent, 4, 4, | |
7232 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7233 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7234 | frag_now->tc_frag_data.is_insn = TRUE; | |
7235 | frag_var (rs_machine_dependent, 4, 4, | |
7236 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
7237 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7238 | } | |
7239 | ||
7240 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
7241 | loop at least 12 bytes away from another loop's end. */ | |
7242 | if (workaround_close_loop_end && use_transform ()) | |
7243 | { | |
7244 | maybe_has_close_loop_end = TRUE; | |
7245 | frag_now->tc_frag_data.is_insn = TRUE; | |
7246 | frag_var (rs_machine_dependent, 12, 12, | |
7247 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
7248 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7249 | } | |
7250 | } | |
7251 | ||
7252 | if (use_transform ()) | |
7253 | { | |
7254 | if (is_jump) | |
7255 | { | |
9c2799c2 | 7256 | gas_assert (finish_frag); |
43cd72b9 | 7257 | frag_var (rs_machine_dependent, |
1beeb686 | 7258 | xtensa_fetch_width, xtensa_fetch_width, |
43cd72b9 BW |
7259 | RELAX_UNREACHABLE, |
7260 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7261 | xtensa_set_frag_assembly_state (frag_now); | |
a82c7d90 | 7262 | xtensa_maybe_create_trampoline_frag (); |
b46824bd MF |
7263 | /* Always create one here. */ |
7264 | xtensa_maybe_create_literal_pool_frag (TRUE, FALSE); | |
43cd72b9 | 7265 | } |
7b1cc377 | 7266 | else if (is_branch && do_align_targets ()) |
43cd72b9 | 7267 | { |
9c2799c2 | 7268 | gas_assert (finish_frag); |
43cd72b9 | 7269 | frag_var (rs_machine_dependent, |
1beeb686 | 7270 | xtensa_fetch_width, xtensa_fetch_width, |
43cd72b9 BW |
7271 | RELAX_MAYBE_UNREACHABLE, |
7272 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7273 | xtensa_set_frag_assembly_state (frag_now); | |
7274 | frag_var (rs_machine_dependent, | |
7275 | 0, 0, | |
7276 | RELAX_MAYBE_DESIRE_ALIGN, | |
7277 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7278 | xtensa_set_frag_assembly_state (frag_now); | |
7279 | } | |
7280 | } | |
7281 | ||
7282 | /* Now, if the original opcode was a call... */ | |
7283 | if (do_align_targets () | |
7284 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
7285 | { | |
b08b5071 | 7286 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
7287 | frag_now->tc_frag_data.is_insn = TRUE; |
7288 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
7289 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
7290 | xtensa_set_frag_assembly_state (frag_now); | |
7291 | } | |
7292 | ||
7293 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
7294 | { | |
7295 | frag_wane (frag_now); | |
7296 | frag_new (0); | |
7297 | xtensa_set_frag_assembly_state (frag_now); | |
7298 | } | |
7299 | } | |
7300 | ||
7301 | \f | |
7fa3d080 BW |
7302 | /* xtensa_end and helper functions. */ |
7303 | ||
7304 | static void xtensa_cleanup_align_frags (void); | |
7305 | static void xtensa_fix_target_frags (void); | |
7306 | static void xtensa_mark_narrow_branches (void); | |
7307 | static void xtensa_mark_zcl_first_insns (void); | |
6a7eedfe | 7308 | static void xtensa_mark_difference_of_two_symbols (void); |
7fa3d080 BW |
7309 | static void xtensa_fix_a0_b_retw_frags (void); |
7310 | static void xtensa_fix_b_j_loop_end_frags (void); | |
7311 | static void xtensa_fix_close_loop_end_frags (void); | |
7312 | static void xtensa_fix_short_loop_frags (void); | |
7313 | static void xtensa_sanity_check (void); | |
2caa7ca0 | 7314 | static void xtensa_add_config_info (void); |
7fa3d080 | 7315 | |
43cd72b9 | 7316 | void |
7fa3d080 | 7317 | xtensa_end (void) |
43cd72b9 BW |
7318 | { |
7319 | directive_balance (); | |
7320 | xtensa_flush_pending_output (); | |
7321 | ||
7322 | past_xtensa_end = TRUE; | |
7323 | ||
7324 | xtensa_move_literals (); | |
7325 | ||
7326 | xtensa_reorder_segments (); | |
7327 | xtensa_cleanup_align_frags (); | |
7328 | xtensa_fix_target_frags (); | |
7329 | if (workaround_a0_b_retw && has_a0_b_retw) | |
7330 | xtensa_fix_a0_b_retw_frags (); | |
7331 | if (workaround_b_j_loop_end) | |
7332 | xtensa_fix_b_j_loop_end_frags (); | |
7333 | ||
7334 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
7335 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
7336 | xtensa_fix_close_loop_end_frags (); | |
7337 | ||
7338 | if (workaround_short_loop && maybe_has_short_loop) | |
7339 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
7340 | if (align_targets) |
7341 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
7342 | xtensa_mark_zcl_first_insns (); |
7343 | ||
7344 | xtensa_sanity_check (); | |
2caa7ca0 BW |
7345 | |
7346 | xtensa_add_config_info (); | |
a82c7d90 DW |
7347 | |
7348 | xtensa_check_frag_count (); | |
43cd72b9 BW |
7349 | } |
7350 | ||
148d6384 MF |
7351 | struct trampoline_chain_entry |
7352 | { | |
7353 | symbolS *sym; | |
7354 | addressT offset; | |
7355 | }; | |
7356 | ||
7357 | /* Trampoline chain for a given (sym, offset) pair is a sorted array | |
7358 | of locations of trampoline jumps leading there. Jumps are represented | |
7359 | as pairs (sym, offset): trampoline frag symbol and offset of the jump | |
7360 | inside the frag. */ | |
7361 | struct trampoline_chain | |
7362 | { | |
7363 | struct trampoline_chain_entry target; | |
7364 | struct trampoline_chain_entry *entry; | |
7365 | size_t n_entries; | |
7366 | size_t n_max; | |
7367 | bfd_boolean needs_sorting; | |
7368 | }; | |
7369 | ||
7370 | struct trampoline_chain_index | |
7371 | { | |
7372 | struct trampoline_chain *entry; | |
7373 | size_t n_entries; | |
7374 | size_t n_max; | |
7375 | bfd_boolean needs_sorting; | |
7376 | }; | |
7377 | ||
fe6c2f1b MF |
7378 | struct trampoline_index |
7379 | { | |
7380 | fragS **entry; | |
7381 | size_t n_entries; | |
7382 | size_t n_max; | |
7383 | }; | |
43cd72b9 | 7384 | |
a82c7d90 DW |
7385 | struct trampoline_seg |
7386 | { | |
7387 | struct trampoline_seg *next; | |
7388 | asection *seg; | |
148d6384 | 7389 | /* Trampolines ordered by their frag fr_address */ |
fe6c2f1b | 7390 | struct trampoline_index index; |
148d6384 MF |
7391 | /* Known trampoline chains ordered by (sym, offset) pair */ |
7392 | struct trampoline_chain_index chain_index; | |
a82c7d90 DW |
7393 | }; |
7394 | ||
7395 | static struct trampoline_seg trampoline_seg_list; | |
7396 | #define J_RANGE (128 * 1024) | |
fe6c2f1b | 7397 | #define J_MARGIN 4096 |
a82c7d90 DW |
7398 | |
7399 | static int unreachable_count = 0; | |
7400 | ||
7401 | ||
7402 | static void | |
7403 | xtensa_maybe_create_trampoline_frag (void) | |
7404 | { | |
7405 | if (!use_trampolines) | |
7406 | return; | |
7407 | ||
7408 | /* We create an area for possible trampolines every 10 unreachable frags. | |
7409 | These are preferred over the ones not preceded by an unreachable frag, | |
7410 | because we don't have to jump around them. This function is called after | |
7411 | each RELAX_UNREACHABLE frag is created. */ | |
7412 | ||
7413 | if (++unreachable_count > 10) | |
7414 | { | |
7415 | xtensa_create_trampoline_frag (FALSE); | |
7416 | clear_frag_count (); | |
7417 | unreachable_count = 0; | |
7418 | } | |
7419 | } | |
7420 | ||
7421 | static void | |
7422 | xtensa_check_frag_count (void) | |
7423 | { | |
7424 | if (!use_trampolines || frag_now->tc_frag_data.is_no_transform) | |
7425 | return; | |
7426 | ||
7427 | /* We create an area for possible trampolines every 8000 frags or so. This | |
7428 | is an estimate based on the max range of a "j" insn (+/-128K) divided | |
7429 | by a typical frag byte count (16), minus a few for safety. This function | |
7430 | is called after each source line is processed. */ | |
7431 | ||
7432 | if (get_frag_count () > 8000) | |
7433 | { | |
7434 | xtensa_create_trampoline_frag (TRUE); | |
7435 | clear_frag_count (); | |
7436 | unreachable_count = 0; | |
7437 | } | |
b46824bd MF |
7438 | |
7439 | /* We create an area for a possible literal pool every N (default 5000) | |
7440 | frags or so. */ | |
7441 | xtensa_maybe_create_literal_pool_frag (TRUE, TRUE); | |
a82c7d90 DW |
7442 | } |
7443 | ||
7444 | static xtensa_insnbuf trampoline_buf = NULL; | |
7445 | static xtensa_insnbuf trampoline_slotbuf = NULL; | |
7446 | ||
b46824bd MF |
7447 | static xtensa_insnbuf litpool_buf = NULL; |
7448 | static xtensa_insnbuf litpool_slotbuf = NULL; | |
7449 | ||
a82c7d90 DW |
7450 | #define TRAMPOLINE_FRAG_SIZE 3000 |
7451 | ||
1c2649f5 MF |
7452 | static struct trampoline_seg * |
7453 | find_trampoline_seg (asection *seg) | |
7454 | { | |
7455 | struct trampoline_seg *ts = trampoline_seg_list.next; | |
407e1140 MF |
7456 | static struct trampoline_seg *mr; |
7457 | ||
7458 | if (mr && mr->seg == seg) | |
7459 | return mr; | |
1c2649f5 MF |
7460 | |
7461 | for ( ; ts; ts = ts->next) | |
7462 | { | |
7463 | if (ts->seg == seg) | |
407e1140 MF |
7464 | { |
7465 | mr = ts; | |
7466 | return ts; | |
7467 | } | |
1c2649f5 MF |
7468 | } |
7469 | ||
7470 | return NULL; | |
7471 | } | |
7472 | ||
fe6c2f1b MF |
7473 | static size_t xg_find_trampoline (const struct trampoline_index *idx, |
7474 | addressT addr) | |
7475 | { | |
7476 | size_t a = 0; | |
7477 | size_t b = idx->n_entries; | |
7478 | ||
7479 | while (b - a > 1) | |
7480 | { | |
7481 | size_t c = (a + b) / 2; | |
7482 | ||
7483 | if (idx->entry[c]->fr_address <= addr) | |
7484 | a = c; | |
7485 | else | |
7486 | b = c; | |
7487 | } | |
7488 | return a; | |
7489 | } | |
7490 | ||
7491 | static void xg_add_trampoline_to_index (struct trampoline_index *idx, | |
7492 | fragS *fragP) | |
7493 | { | |
7494 | if (idx->n_entries == idx->n_max) | |
7495 | { | |
7496 | idx->n_max = (idx->n_entries + 1) * 2; | |
7497 | idx->entry = xrealloc (idx->entry, | |
7498 | sizeof (*idx->entry) * idx->n_max); | |
7499 | } | |
7500 | idx->entry[idx->n_entries] = fragP; | |
7501 | ++idx->n_entries; | |
7502 | } | |
7503 | ||
7504 | static void xg_remove_trampoline_from_index (struct trampoline_index *idx, | |
7505 | size_t i) | |
7506 | { | |
7507 | gas_assert (i < idx->n_entries); | |
7508 | memmove (idx->entry + i, idx->entry + i + 1, | |
7509 | (idx->n_entries - i - 1) * sizeof (*idx->entry)); | |
7510 | --idx->n_entries; | |
7511 | } | |
7512 | ||
7513 | static void xg_add_trampoline_to_seg (struct trampoline_seg *ts, | |
7514 | fragS *fragP) | |
7515 | { | |
7516 | xg_add_trampoline_to_index (&ts->index, fragP); | |
7517 | } | |
1c2649f5 | 7518 | |
a82c7d90 DW |
7519 | static void |
7520 | xtensa_create_trampoline_frag (bfd_boolean needs_jump_around) | |
7521 | { | |
7522 | /* Emit a frag where we can place intermediate jump instructions, | |
7523 | in case we need to jump farther than 128K bytes. | |
7524 | Each jump instruction takes three bytes. | |
7525 | We allocate enough for 1000 trampolines in each frag. | |
7526 | If that's not enough, oh well. */ | |
7527 | ||
1c2649f5 | 7528 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); |
a82c7d90 DW |
7529 | char *varP; |
7530 | fragS *fragP; | |
7531 | int size = TRAMPOLINE_FRAG_SIZE; | |
7532 | ||
a82c7d90 DW |
7533 | if (ts == NULL) |
7534 | { | |
add39d23 | 7535 | ts = XCNEW(struct trampoline_seg); |
a82c7d90 DW |
7536 | ts->next = trampoline_seg_list.next; |
7537 | trampoline_seg_list.next = ts; | |
7538 | ts->seg = now_seg; | |
7539 | } | |
7540 | ||
7541 | frag_wane (frag_now); | |
7542 | frag_new (0); | |
7543 | xtensa_set_frag_assembly_state (frag_now); | |
7544 | varP = frag_var (rs_machine_dependent, size, size, RELAX_TRAMPOLINE, NULL, 0, NULL); | |
7545 | fragP = (fragS *)(varP - SIZEOF_STRUCT_FRAG); | |
7546 | if (trampoline_buf == NULL) | |
7547 | { | |
7548 | trampoline_buf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7549 | trampoline_slotbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7550 | } | |
46888d71 | 7551 | fragP->tc_frag_data.needs_jump_around = needs_jump_around; |
fe6c2f1b | 7552 | xg_add_trampoline_to_seg (ts, fragP); |
a82c7d90 DW |
7553 | } |
7554 | ||
fe6c2f1b MF |
7555 | static bfd_boolean xg_is_trampoline_frag_full (const fragS *fragP) |
7556 | { | |
7557 | return fragP->fr_var < 3; | |
7558 | } | |
a82c7d90 | 7559 | |
148d6384 MF |
7560 | static int xg_order_trampoline_chain_entry (const void *a, const void *b) |
7561 | { | |
7562 | const struct trampoline_chain_entry *pa = a; | |
7563 | const struct trampoline_chain_entry *pb = b; | |
7564 | ||
7565 | if (pa->sym == pb->sym || | |
7566 | S_GET_VALUE (pa->sym) == S_GET_VALUE (pb->sym)) | |
7567 | if (pa->offset == pb->offset) | |
7568 | return 0; | |
7569 | else | |
7570 | return pa->offset < pb->offset ? -1 : 1; | |
7571 | else | |
7572 | return S_GET_VALUE (pa->sym) < S_GET_VALUE (pb->sym) ? -1 : 1; | |
7573 | } | |
7574 | ||
7575 | static void xg_sort_trampoline_chain (struct trampoline_chain *tc) | |
7576 | { | |
7577 | qsort (tc->entry, tc->n_entries, sizeof (*tc->entry), | |
7578 | xg_order_trampoline_chain_entry); | |
7579 | tc->needs_sorting = FALSE; | |
7580 | } | |
7581 | ||
7582 | /* Find entry index in the given chain with maximal address <= source. */ | |
7583 | static size_t xg_find_chain_entry (struct trampoline_chain *tc, | |
7584 | addressT source) | |
7585 | { | |
7586 | size_t a = 0; | |
7587 | size_t b = tc->n_entries; | |
7588 | ||
7589 | if (tc->needs_sorting) | |
7590 | xg_sort_trampoline_chain (tc); | |
7591 | ||
7592 | while (b - a > 1) | |
7593 | { | |
7594 | size_t c = (a + b) / 2; | |
7595 | struct trampoline_chain_entry *e = tc->entry + c; | |
7596 | ||
7597 | if (S_GET_VALUE(e->sym) + e->offset <= source) | |
7598 | a = c; | |
7599 | else | |
7600 | b = c; | |
7601 | } | |
7602 | return a; | |
7603 | } | |
7604 | ||
7605 | /* Find the best jump target for the source in the given trampoline chain. | |
7606 | The best jump target is the one that results in the shortest path to the | |
7607 | final target, it's the location of the jump closest to the final target, | |
7608 | but within the J_RANGE - J_MARGIN from the source. */ | |
7609 | static struct trampoline_chain_entry * | |
7610 | xg_get_best_chain_entry (struct trampoline_chain *tc, addressT source) | |
7611 | { | |
7612 | addressT target = S_GET_VALUE(tc->target.sym) + tc->target.offset; | |
7613 | size_t i = xg_find_chain_entry (tc, source); | |
7614 | struct trampoline_chain_entry *e = tc->entry + i; | |
7615 | int step = target < source ? -1 : 1; | |
7616 | addressT chained_target; | |
7617 | offsetT off; | |
7618 | ||
7619 | if (target > source && | |
7620 | S_GET_VALUE(e->sym) + e->offset <= source && | |
7621 | i + 1 < tc->n_entries) | |
7622 | ++i; | |
7623 | ||
7624 | while (i + step < tc->n_entries) | |
7625 | { | |
7626 | struct trampoline_chain_entry *next = tc->entry + i + step; | |
7627 | ||
7628 | chained_target = S_GET_VALUE(next->sym) + next->offset; | |
7629 | off = source - chained_target; | |
7630 | ||
7631 | if (labs (off) >= J_RANGE - J_MARGIN) | |
7632 | break; | |
7633 | ||
7634 | i += step; | |
7635 | } | |
7636 | ||
7637 | e = tc->entry + i; | |
7638 | chained_target = S_GET_VALUE(e->sym) + e->offset; | |
7639 | off = source - chained_target; | |
7640 | ||
7641 | if (labs (off) < J_MARGIN || | |
7642 | labs (off) >= J_RANGE - J_MARGIN) | |
7643 | return &tc->target; | |
7644 | return tc->entry + i; | |
7645 | } | |
7646 | ||
7647 | static int xg_order_trampoline_chain (const void *a, const void *b) | |
7648 | { | |
7649 | const struct trampoline_chain *pa = a; | |
7650 | const struct trampoline_chain *pb = b; | |
7651 | ||
7652 | return xg_order_trampoline_chain_entry (&pa->target, &pb->target); | |
7653 | } | |
7654 | ||
7655 | static struct trampoline_chain * | |
7656 | xg_get_trampoline_chain (struct trampoline_seg *ts, | |
7657 | symbolS *sym, | |
7658 | addressT offset) | |
7659 | { | |
7660 | struct trampoline_chain_index *idx = &ts->chain_index; | |
7661 | struct trampoline_chain c; | |
7662 | ||
7663 | if (idx->needs_sorting) | |
7664 | { | |
7665 | qsort (idx->entry, idx->n_entries, sizeof (*idx->entry), | |
7666 | xg_order_trampoline_chain); | |
7667 | idx->needs_sorting = FALSE; | |
7668 | } | |
7669 | c.target.sym = sym; | |
7670 | c.target.offset = offset; | |
7671 | return bsearch (&c, idx->entry, idx->n_entries, | |
7672 | sizeof (struct trampoline_chain), | |
7673 | xg_order_trampoline_chain); | |
7674 | } | |
7675 | ||
7676 | /* Find trampoline chain in the given trampoline segment that is going | |
7677 | to the *sym + *offset. If found, replace *sym and *offset with the | |
7678 | best jump target in that chain. */ | |
7679 | static struct trampoline_chain * | |
7680 | xg_find_best_eq_target (struct trampoline_seg *ts, | |
7681 | addressT source, symbolS **sym, | |
7682 | addressT *offset) | |
7683 | { | |
7684 | struct trampoline_chain *tc = xg_get_trampoline_chain (ts, *sym, *offset); | |
7685 | ||
7686 | if (tc) | |
7687 | { | |
7688 | struct trampoline_chain_entry *e = xg_get_best_chain_entry (tc, source); | |
7689 | ||
7690 | *sym = e->sym; | |
7691 | *offset = e->offset; | |
7692 | } | |
7693 | return tc; | |
7694 | } | |
7695 | ||
7696 | static void xg_add_location_to_chain (struct trampoline_chain *tc, | |
7697 | symbolS *sym, addressT offset) | |
7698 | { | |
7699 | struct trampoline_chain_entry *e; | |
7700 | ||
7701 | if (tc->n_entries == tc->n_max) | |
7702 | { | |
7703 | tc->n_max = (tc->n_max + 1) * 2; | |
7704 | tc->entry = xrealloc (tc->entry, sizeof (*tc->entry) * tc->n_max); | |
7705 | } | |
7706 | e = tc->entry + tc->n_entries; | |
7707 | e->sym = sym; | |
7708 | e->offset = offset; | |
7709 | ++tc->n_entries; | |
7710 | tc->needs_sorting = TRUE; | |
7711 | } | |
7712 | ||
7713 | static struct trampoline_chain * | |
7714 | xg_create_trampoline_chain (struct trampoline_seg *ts, | |
7715 | symbolS *sym, addressT offset) | |
7716 | { | |
7717 | struct trampoline_chain_index *idx = &ts->chain_index; | |
7718 | struct trampoline_chain *tc; | |
7719 | ||
7720 | if (idx->n_entries == idx->n_max) | |
7721 | { | |
7722 | idx->n_max = (idx->n_max + 1) * 2; | |
7723 | idx->entry = xrealloc (idx->entry, | |
7724 | sizeof (*idx->entry) * idx->n_max); | |
7725 | } | |
7726 | ||
7727 | tc = idx->entry + idx->n_entries; | |
7728 | tc->target.sym = sym; | |
7729 | tc->target.offset = offset; | |
7730 | tc->entry = NULL; | |
7731 | tc->n_entries = 0; | |
7732 | tc->n_max = 0; | |
7733 | xg_add_location_to_chain (tc, sym, offset); | |
7734 | ||
7735 | ++idx->n_entries; | |
7736 | idx->needs_sorting = TRUE; | |
7737 | ||
7738 | return tc; | |
7739 | } | |
7740 | ||
a82c7d90 DW |
7741 | void dump_trampolines (void); |
7742 | ||
7743 | void | |
7744 | dump_trampolines (void) | |
7745 | { | |
7746 | struct trampoline_seg *ts = trampoline_seg_list.next; | |
7747 | ||
7748 | for ( ; ts; ts = ts->next) | |
7749 | { | |
fe6c2f1b | 7750 | size_t i; |
a82c7d90 DW |
7751 | asection *seg = ts->seg; |
7752 | ||
7753 | if (seg == NULL) | |
7754 | continue; | |
7755 | fprintf(stderr, "SECTION %s\n", seg->name); | |
fe6c2f1b MF |
7756 | |
7757 | for (i = 0; i < ts->index.n_entries; ++i) | |
a82c7d90 | 7758 | { |
fe6c2f1b MF |
7759 | fragS *tf = ts->index.entry[i]; |
7760 | ||
a82c7d90 | 7761 | fprintf(stderr, " 0x%08x: fix=%d, jump_around=%s\n", |
46888d71 MF |
7762 | (int)tf->fr_address, (int)tf->fr_fix, |
7763 | tf->tc_frag_data.needs_jump_around ? "T" : "F"); | |
a82c7d90 DW |
7764 | } |
7765 | } | |
7766 | } | |
7767 | ||
b46824bd MF |
7768 | static void dump_litpools (void) __attribute__ ((unused)); |
7769 | ||
7770 | static void | |
7771 | dump_litpools (void) | |
7772 | { | |
7773 | struct litpool_seg *lps = litpool_seg_list.next; | |
7774 | struct litpool_frag *lpf; | |
7775 | ||
7776 | for ( ; lps ; lps = lps->next ) | |
7777 | { | |
7778 | printf("litpool seg %s\n", lps->seg->name); | |
7779 | for ( lpf = lps->frag_list.next; lpf->fragP; lpf = lpf->next ) | |
7780 | { | |
7781 | fragS *litfrag = lpf->fragP->fr_next; | |
7782 | int count = 0; | |
7783 | while (litfrag && litfrag->fr_subtype != RELAX_LITERAL_POOL_END) | |
7784 | { | |
7785 | if (litfrag->fr_fix == 4) | |
7786 | count++; | |
7787 | litfrag = litfrag->fr_next; | |
7788 | } | |
7789 | printf(" %ld <%d:%d> (%d) [%d]: ", | |
7790 | lpf->addr, lpf->priority, lpf->original_priority, | |
7791 | lpf->fragP->fr_line, count); | |
7792 | //dump_frag(lpf->fragP); | |
7793 | } | |
7794 | } | |
7795 | } | |
7796 | ||
7797 | static void | |
7798 | xtensa_maybe_create_literal_pool_frag (bfd_boolean create, | |
7799 | bfd_boolean only_if_needed) | |
7800 | { | |
7801 | struct litpool_seg *lps = litpool_seg_list.next; | |
7802 | fragS *fragP; | |
7803 | struct litpool_frag *lpf; | |
7804 | bfd_boolean needed = FALSE; | |
7805 | ||
7806 | if (use_literal_section || !auto_litpools) | |
7807 | return; | |
7808 | ||
7809 | for ( ; lps ; lps = lps->next ) | |
7810 | { | |
7811 | if (lps->seg == now_seg) | |
7812 | break; | |
7813 | } | |
7814 | ||
7815 | if (lps == NULL) | |
7816 | { | |
add39d23 | 7817 | lps = XCNEW (struct litpool_seg); |
b46824bd MF |
7818 | lps->next = litpool_seg_list.next; |
7819 | litpool_seg_list.next = lps; | |
7820 | lps->seg = now_seg; | |
7821 | lps->frag_list.next = &lps->frag_list; | |
7822 | lps->frag_list.prev = &lps->frag_list; | |
947fa914 MF |
7823 | /* Put candidate literal pool at the beginning of every section, |
7824 | so that even when section starts with literal load there's a | |
7825 | literal pool available. */ | |
7826 | lps->frag_count = auto_litpool_limit; | |
b46824bd MF |
7827 | } |
7828 | ||
7829 | lps->frag_count++; | |
7830 | ||
7831 | if (create) | |
7832 | { | |
7833 | if (only_if_needed) | |
7834 | { | |
7835 | if (past_xtensa_end || !use_transform() || | |
7836 | frag_now->tc_frag_data.is_no_transform) | |
7837 | { | |
7838 | return; | |
7839 | } | |
7840 | if (auto_litpool_limit <= 0) | |
7841 | { | |
7842 | /* Don't create a litpool based only on frag count. */ | |
7843 | return; | |
7844 | } | |
7845 | else if (lps->frag_count > auto_litpool_limit) | |
7846 | { | |
7847 | needed = TRUE; | |
7848 | } | |
7849 | else | |
7850 | { | |
7851 | return; | |
7852 | } | |
7853 | } | |
7854 | else | |
7855 | { | |
7856 | needed = TRUE; | |
7857 | } | |
7858 | } | |
7859 | ||
7860 | if (needed) | |
7861 | { | |
7862 | int size = (only_if_needed) ? 3 : 0; /* Space for a "j" insn. */ | |
7863 | /* Create a potential site for a literal pool. */ | |
7864 | frag_wane (frag_now); | |
7865 | frag_new (0); | |
7866 | xtensa_set_frag_assembly_state (frag_now); | |
7867 | fragP = frag_now; | |
7868 | fragP->tc_frag_data.lit_frchain = frchain_now; | |
7869 | fragP->tc_frag_data.literal_frag = fragP; | |
7870 | frag_var (rs_machine_dependent, size, size, | |
7871 | (only_if_needed) ? | |
7872 | RELAX_LITERAL_POOL_CANDIDATE_BEGIN : | |
7873 | RELAX_LITERAL_POOL_BEGIN, | |
7874 | NULL, 0, NULL); | |
7875 | frag_now->tc_frag_data.lit_seg = now_seg; | |
7876 | frag_variant (rs_machine_dependent, 0, 0, | |
7877 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); | |
7878 | xtensa_set_frag_assembly_state (frag_now); | |
7879 | } | |
7880 | else | |
7881 | { | |
7882 | /* RELAX_LITERAL_POOL_BEGIN frag is being created; | |
7883 | just record it here. */ | |
7884 | fragP = frag_now; | |
7885 | } | |
7886 | ||
325801bd | 7887 | lpf = XNEW (struct litpool_frag); |
b46824bd MF |
7888 | /* Insert at tail of circular list. */ |
7889 | lpf->addr = 0; | |
7890 | lps->frag_list.prev->next = lpf; | |
7891 | lpf->next = &lps->frag_list; | |
7892 | lpf->prev = lps->frag_list.prev; | |
7893 | lps->frag_list.prev = lpf; | |
7894 | lpf->fragP = fragP; | |
7895 | lpf->priority = (needed) ? (only_if_needed) ? 3 : 2 : 1; | |
7896 | lpf->original_priority = lpf->priority; | |
7897 | ||
7898 | lps->frag_count = 0; | |
7899 | } | |
7900 | ||
43cd72b9 | 7901 | static void |
7fa3d080 | 7902 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
7903 | { |
7904 | frchainS *frchP; | |
c9049d30 | 7905 | asection *s; |
43cd72b9 | 7906 | |
c9049d30 AM |
7907 | for (s = stdoutput->sections; s; s = s->next) |
7908 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7909 | { | |
7910 | fragS *fragP; | |
7911 | /* Walk over all of the fragments in a subsection. */ | |
7912 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7913 | { | |
7914 | if ((fragP->fr_type == rs_align | |
7915 | || fragP->fr_type == rs_align_code | |
7916 | || (fragP->fr_type == rs_machine_dependent | |
7917 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
7918 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
7919 | && fragP->fr_fix == 0) | |
7920 | { | |
7921 | fragS *next = fragP->fr_next; | |
7922 | ||
7923 | while (next | |
7924 | && next->fr_fix == 0 | |
7925 | && next->fr_type == rs_machine_dependent | |
7926 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7927 | { | |
7928 | frag_wane (next); | |
7929 | next = next->fr_next; | |
7930 | } | |
7931 | } | |
7932 | /* If we don't widen branch targets, then they | |
7933 | will be easier to align. */ | |
7934 | if (fragP->tc_frag_data.is_branch_target | |
7935 | && fragP->fr_opcode == fragP->fr_literal | |
7936 | && fragP->fr_type == rs_machine_dependent | |
7937 | && fragP->fr_subtype == RELAX_SLOTS | |
7938 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
7939 | frag_wane (fragP); | |
7940 | if (fragP->fr_type == rs_machine_dependent | |
7941 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
7942 | fragP->tc_frag_data.is_unreachable = TRUE; | |
7943 | } | |
7944 | } | |
43cd72b9 BW |
7945 | } |
7946 | ||
7947 | ||
7948 | /* Re-process all of the fragments looking to convert all of the | |
7949 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
7950 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 7951 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 7952 | |
43cd72b9 | 7953 | static void |
7fa3d080 | 7954 | xtensa_fix_target_frags (void) |
e0001a05 NC |
7955 | { |
7956 | frchainS *frchP; | |
c9049d30 | 7957 | asection *s; |
e0001a05 NC |
7958 | |
7959 | /* When this routine is called, all of the subsections are still intact | |
7960 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7961 | for (s = stdoutput->sections; s; s = s->next) |
7962 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7963 | { | |
7964 | fragS *fragP; | |
e0001a05 | 7965 | |
c9049d30 AM |
7966 | /* Walk over all of the fragments in a subsection. */ |
7967 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7968 | { | |
7969 | if (fragP->fr_type == rs_machine_dependent | |
7970 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7971 | { | |
7972 | if (next_frag_is_branch_target (fragP)) | |
7973 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
7974 | else | |
7975 | frag_wane (fragP); | |
7976 | } | |
7977 | } | |
7978 | } | |
e0001a05 NC |
7979 | } |
7980 | ||
7981 | ||
7fa3d080 BW |
7982 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7983 | ||
43cd72b9 | 7984 | static void |
7fa3d080 | 7985 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
7986 | { |
7987 | frchainS *frchP; | |
c9049d30 | 7988 | asection *s; |
43cd72b9 | 7989 | |
c9049d30 AM |
7990 | for (s = stdoutput->sections; s; s = s->next) |
7991 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7992 | { | |
7993 | fragS *fragP; | |
7994 | /* Walk over all of the fragments in a subsection. */ | |
7995 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7996 | { | |
7997 | if (fragP->fr_type == rs_machine_dependent | |
7998 | && fragP->fr_subtype == RELAX_SLOTS | |
7999 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
8000 | { | |
8001 | vliw_insn vinsn; | |
8002 | ||
8003 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
8004 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
8005 | ||
8006 | if (vinsn.num_slots == 1 | |
8007 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 8008 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
8009 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
8010 | && is_narrow_branch_guaranteed_in_range (fragP, | |
8011 | &vinsn.slots[0])) | |
8012 | { | |
8013 | fragP->fr_subtype = RELAX_SLOTS; | |
8014 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
8015 | fragP->tc_frag_data.is_aligning_branch = 1; | |
8016 | } | |
8017 | } | |
8018 | } | |
8019 | } | |
43cd72b9 BW |
8020 | } |
8021 | ||
8022 | ||
8023 | /* A branch is typically widened only when its target is out of | |
8024 | range. However, we would like to widen them to align a subsequent | |
8025 | branch target when possible. | |
8026 | ||
8027 | Because the branch relaxation code is so convoluted, the optimal solution | |
8028 | (combining the two cases) is difficult to get right in all circumstances. | |
8029 | We therefore go with an "almost as good" solution, where we only | |
8030 | use for alignment narrow branches that definitely will not expand to a | |
8031 | jump and a branch. These functions find and mark these cases. */ | |
8032 | ||
a67517f4 BW |
8033 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
8034 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
8035 | We start counting beginning with the frag after the 2-byte branch, so the | |
8036 | maximum offset is (4 - 2) + 63 = 65. */ | |
8037 | #define MAX_IMMED6 65 | |
43cd72b9 | 8038 | |
d77b99c9 | 8039 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 8040 | |
43cd72b9 | 8041 | static bfd_boolean |
7fa3d080 | 8042 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 | 8043 | { |
91d6fa6a NC |
8044 | const expressionS *exp = &tinsn->tok[1]; |
8045 | symbolS *symbolP = exp->X_add_symbol; | |
8046 | offsetT max_distance = exp->X_add_number; | |
e7da6241 BW |
8047 | fragS *target_frag; |
8048 | ||
91d6fa6a | 8049 | if (exp->X_op != O_symbol) |
e7da6241 BW |
8050 | return FALSE; |
8051 | ||
8052 | target_frag = symbol_get_frag (symbolP); | |
8053 | ||
43cd72b9 BW |
8054 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
8055 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
8056 | return FALSE; | |
8057 | ||
8058 | /* The branch doesn't branch over it's own frag, | |
8059 | but over the subsequent ones. */ | |
8060 | fragP = fragP->fr_next; | |
8061 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
8062 | { | |
8063 | max_distance += unrelaxed_frag_max_size (fragP); | |
8064 | fragP = fragP->fr_next; | |
8065 | } | |
8066 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
8067 | return TRUE; | |
e0001a05 NC |
8068 | return FALSE; |
8069 | } | |
8070 | ||
8071 | ||
43cd72b9 | 8072 | static void |
7fa3d080 | 8073 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
8074 | { |
8075 | frchainS *frchP; | |
c9049d30 | 8076 | asection *s; |
43cd72b9 | 8077 | |
c9049d30 AM |
8078 | for (s = stdoutput->sections; s; s = s->next) |
8079 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8080 | { | |
8081 | fragS *fragP; | |
8082 | /* Walk over all of the fragments in a subsection. */ | |
8083 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8084 | { | |
8085 | if (fragP->fr_type == rs_machine_dependent | |
8086 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
8087 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
8088 | { | |
8089 | /* Find the loop frag. */ | |
3a1e9c4a | 8090 | fragS *loop_frag = next_non_empty_frag (fragP); |
c9049d30 | 8091 | /* Find the first insn frag. */ |
3a1e9c4a SA |
8092 | fragS *targ_frag = next_non_empty_frag (loop_frag); |
8093 | ||
8094 | /* Handle a corner case that comes up in hardware | |
8095 | diagnostics. The original assembly looks like this: | |
3739860c | 8096 | |
3a1e9c4a SA |
8097 | loop aX, LabelA |
8098 | <empty_frag>--not found by next_non_empty_frag | |
8099 | loop aY, LabelB | |
8100 | ||
8101 | Depending on the start address, the assembler may or | |
8102 | may not change it to look something like this: | |
8103 | ||
8104 | loop aX, LabelA | |
8105 | nop--frag isn't empty anymore | |
8106 | loop aY, LabelB | |
8107 | ||
8108 | So set up to check the alignment of the nop if it | |
8109 | exists */ | |
8110 | while (loop_frag != targ_frag) | |
8111 | { | |
8112 | if (loop_frag->fr_type == rs_machine_dependent | |
8113 | && (loop_frag->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
3739860c | 8114 | || loop_frag->fr_subtype |
3a1e9c4a SA |
8115 | == RELAX_CHECK_ALIGN_NEXT_OPCODE)) |
8116 | targ_frag = loop_frag; | |
8117 | else | |
8118 | loop_frag = loop_frag->fr_next; | |
8119 | } | |
c9049d30 AM |
8120 | |
8121 | /* Of course, sometimes (mostly for toy test cases) a | |
8122 | zero-cost loop instruction is the last in a section. */ | |
8123 | if (targ_frag) | |
8124 | { | |
8125 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
8126 | /* Do not widen a frag that is the first instruction of a | |
8127 | zero-cost loop. It makes that loop harder to align. */ | |
8128 | if (targ_frag->fr_type == rs_machine_dependent | |
8129 | && targ_frag->fr_subtype == RELAX_SLOTS | |
8130 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
8131 | == RELAX_NARROW)) | |
8132 | { | |
8133 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
8134 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
8135 | else | |
8136 | { | |
8137 | frag_wane (targ_frag); | |
8138 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
8139 | } | |
8140 | } | |
8141 | } | |
8142 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
8143 | frag_wane (fragP); | |
8144 | } | |
8145 | } | |
8146 | } | |
43cd72b9 BW |
8147 | } |
8148 | ||
8149 | ||
fb227da0 BW |
8150 | /* When a difference-of-symbols expression is encoded as a uleb128 or |
8151 | sleb128 value, the linker is unable to adjust that value to account for | |
8152 | link-time relaxation. Mark all the code between such symbols so that | |
8153 | its size cannot be changed by linker relaxation. */ | |
3739860c | 8154 | |
6a7eedfe BW |
8155 | static void |
8156 | xtensa_mark_difference_of_two_symbols (void) | |
8157 | { | |
8158 | symbolS *expr_sym; | |
8159 | ||
3739860c | 8160 | for (expr_sym = expr_symbols; expr_sym; |
6a7eedfe BW |
8161 | expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) |
8162 | { | |
91d6fa6a | 8163 | expressionS *exp = symbol_get_value_expression (expr_sym); |
6a7eedfe | 8164 | |
91d6fa6a | 8165 | if (exp->X_op == O_subtract) |
6a7eedfe | 8166 | { |
91d6fa6a NC |
8167 | symbolS *left = exp->X_add_symbol; |
8168 | symbolS *right = exp->X_op_symbol; | |
3739860c | 8169 | |
6a7eedfe BW |
8170 | /* Difference of two symbols not in the same section |
8171 | are handled with relocations in the linker. */ | |
8172 | if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) | |
8173 | { | |
8174 | fragS *start; | |
8175 | fragS *end; | |
983f90e3 | 8176 | fragS *walk; |
6a7eedfe | 8177 | |
3739860c | 8178 | if (symbol_get_frag (left)->fr_address |
6a7eedfe BW |
8179 | <= symbol_get_frag (right)->fr_address) |
8180 | { | |
8181 | start = symbol_get_frag (left); | |
8182 | end = symbol_get_frag (right); | |
8183 | } | |
8184 | else | |
8185 | { | |
8186 | start = symbol_get_frag (right); | |
8187 | end = symbol_get_frag (left); | |
8188 | } | |
983f90e3 SA |
8189 | |
8190 | if (start->tc_frag_data.no_transform_end != NULL) | |
8191 | walk = start->tc_frag_data.no_transform_end; | |
8192 | else | |
8193 | walk = start; | |
3739860c | 8194 | do |
6a7eedfe | 8195 | { |
983f90e3 SA |
8196 | walk->tc_frag_data.is_no_transform = 1; |
8197 | walk = walk->fr_next; | |
6a7eedfe | 8198 | } |
983f90e3 SA |
8199 | while (walk && walk->fr_address < end->fr_address); |
8200 | ||
8201 | start->tc_frag_data.no_transform_end = walk; | |
6a7eedfe BW |
8202 | } |
8203 | } | |
8204 | } | |
8205 | } | |
8206 | ||
8207 | ||
e0001a05 NC |
8208 | /* Re-process all of the fragments looking to convert all of the |
8209 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
8210 | conditional branch or a retw/retw.n, convert this frag to one that | |
8211 | will generate a NOP. In any case close it off with a .fill 0. */ | |
8212 | ||
7fa3d080 BW |
8213 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
8214 | ||
e0001a05 | 8215 | static void |
7fa3d080 | 8216 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
8217 | { |
8218 | frchainS *frchP; | |
c9049d30 | 8219 | asection *s; |
e0001a05 NC |
8220 | |
8221 | /* When this routine is called, all of the subsections are still intact | |
8222 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8223 | for (s = stdoutput->sections; s; s = s->next) |
8224 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8225 | { | |
8226 | fragS *fragP; | |
e0001a05 | 8227 | |
c9049d30 AM |
8228 | /* Walk over all of the fragments in a subsection. */ |
8229 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8230 | { | |
8231 | if (fragP->fr_type == rs_machine_dependent | |
8232 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
8233 | { | |
8234 | if (next_instrs_are_b_retw (fragP)) | |
8235 | { | |
8236 | if (fragP->tc_frag_data.is_no_transform) | |
8237 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
8238 | else | |
8239 | relax_frag_add_nop (fragP); | |
8240 | } | |
8241 | frag_wane (fragP); | |
8242 | } | |
8243 | } | |
8244 | } | |
e0001a05 NC |
8245 | } |
8246 | ||
8247 | ||
7fa3d080 BW |
8248 | static bfd_boolean |
8249 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
8250 | { |
8251 | xtensa_opcode opcode; | |
43cd72b9 | 8252 | xtensa_format fmt; |
e0001a05 NC |
8253 | const fragS *next_fragP = next_non_empty_frag (fragP); |
8254 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 8255 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
8256 | xtensa_isa isa = xtensa_default_isa; |
8257 | int offset = 0; | |
43cd72b9 BW |
8258 | int slot; |
8259 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
8260 | |
8261 | if (!insnbuf) | |
43cd72b9 BW |
8262 | { |
8263 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8264 | slotbuf = xtensa_insnbuf_alloc (isa); | |
8265 | } | |
e0001a05 NC |
8266 | |
8267 | if (next_fragP == NULL) | |
8268 | return FALSE; | |
8269 | ||
8270 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
8271 | xtensa_insnbuf_from_chars |
8272 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
8273 | fmt = xtensa_format_decode (isa, insnbuf); |
8274 | if (fmt == XTENSA_UNDEFINED) | |
8275 | return FALSE; | |
8276 | ||
8277 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
8278 | { | |
8279 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
8280 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
8281 | ||
8282 | branch_seen = (branch_seen | |
8283 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
8284 | } | |
e0001a05 | 8285 | |
43cd72b9 | 8286 | if (!branch_seen) |
e0001a05 NC |
8287 | return FALSE; |
8288 | ||
43cd72b9 | 8289 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8290 | if (offset == next_fragP->fr_fix) |
8291 | { | |
8292 | next_fragP = next_non_empty_frag (next_fragP); | |
8293 | offset = 0; | |
8294 | } | |
43cd72b9 | 8295 | |
e0001a05 NC |
8296 | if (next_fragP == NULL) |
8297 | return FALSE; | |
8298 | ||
8299 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
8300 | xtensa_insnbuf_from_chars |
8301 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
8302 | fmt = xtensa_format_decode (isa, insnbuf); |
8303 | ||
8304 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
8305 | have no problems. */ | |
8306 | if (fmt == XTENSA_UNDEFINED | |
8307 | || xtensa_format_num_slots (isa, fmt) != 1) | |
8308 | return FALSE; | |
8309 | ||
8310 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
8311 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 8312 | |
b08b5071 | 8313 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 8314 | return TRUE; |
43cd72b9 | 8315 | |
e0001a05 NC |
8316 | return FALSE; |
8317 | } | |
8318 | ||
8319 | ||
8320 | /* Re-process all of the fragments looking to convert all of the | |
8321 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
8322 | loop end label, convert this frag to one that will generate a NOP. | |
8323 | In any case close it off with a .fill 0. */ | |
8324 | ||
7fa3d080 BW |
8325 | static bfd_boolean next_instr_is_loop_end (fragS *); |
8326 | ||
e0001a05 | 8327 | static void |
7fa3d080 | 8328 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
8329 | { |
8330 | frchainS *frchP; | |
c9049d30 | 8331 | asection *s; |
e0001a05 NC |
8332 | |
8333 | /* When this routine is called, all of the subsections are still intact | |
8334 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8335 | for (s = stdoutput->sections; s; s = s->next) |
8336 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8337 | { | |
8338 | fragS *fragP; | |
e0001a05 | 8339 | |
c9049d30 AM |
8340 | /* Walk over all of the fragments in a subsection. */ |
8341 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8342 | { | |
8343 | if (fragP->fr_type == rs_machine_dependent | |
8344 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
8345 | { | |
8346 | if (next_instr_is_loop_end (fragP)) | |
8347 | { | |
8348 | if (fragP->tc_frag_data.is_no_transform) | |
8349 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
8350 | else | |
8351 | relax_frag_add_nop (fragP); | |
8352 | } | |
8353 | frag_wane (fragP); | |
8354 | } | |
8355 | } | |
8356 | } | |
e0001a05 NC |
8357 | } |
8358 | ||
8359 | ||
7fa3d080 BW |
8360 | static bfd_boolean |
8361 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
8362 | { |
8363 | const fragS *next_fragP; | |
8364 | ||
8365 | if (next_frag_is_loop_target (fragP)) | |
8366 | return FALSE; | |
8367 | ||
8368 | next_fragP = next_non_empty_frag (fragP); | |
8369 | if (next_fragP == NULL) | |
8370 | return FALSE; | |
8371 | ||
8372 | if (!next_frag_is_loop_target (next_fragP)) | |
8373 | return FALSE; | |
8374 | ||
8375 | /* If the size is >= 3 then there is more than one instruction here. | |
8376 | The hardware bug will not fire. */ | |
8377 | if (next_fragP->fr_fix > 3) | |
8378 | return FALSE; | |
8379 | ||
8380 | return TRUE; | |
8381 | } | |
8382 | ||
8383 | ||
8384 | /* Re-process all of the fragments looking to convert all of the | |
8385 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
8386 | not MY loop's loop end within 12 bytes, add enough nops here to | |
8387 | make it at least 12 bytes away. In any case close it off with a | |
8388 | .fill 0. */ | |
8389 | ||
d77b99c9 | 8390 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 8391 | (fragS *, fragS *, offsetT); |
7fa3d080 | 8392 | |
e0001a05 | 8393 | static void |
7fa3d080 | 8394 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
8395 | { |
8396 | frchainS *frchP; | |
c9049d30 | 8397 | asection *s; |
e0001a05 NC |
8398 | |
8399 | /* When this routine is called, all of the subsections are still intact | |
8400 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8401 | for (s = stdoutput->sections; s; s = s->next) |
8402 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8403 | { | |
8404 | fragS *fragP; | |
e0001a05 | 8405 | |
c9049d30 | 8406 | fragS *current_target = NULL; |
e0001a05 | 8407 | |
c9049d30 AM |
8408 | /* Walk over all of the fragments in a subsection. */ |
8409 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8410 | { | |
8411 | if (fragP->fr_type == rs_machine_dependent | |
8412 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
8413 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 8414 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 8415 | |
c9049d30 AM |
8416 | if (current_target |
8417 | && fragP->fr_type == rs_machine_dependent | |
8418 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
8419 | { | |
8420 | offsetT min_bytes; | |
8421 | int bytes_added = 0; | |
e0001a05 NC |
8422 | |
8423 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
8424 | /* Max out at 12. */ |
8425 | min_bytes = min_bytes_to_other_loop_end | |
8426 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
8427 | ||
8428 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
8429 | { | |
8430 | if (fragP->tc_frag_data.is_no_transform) | |
8431 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
8432 | else | |
8433 | { | |
8434 | while (min_bytes + bytes_added | |
8435 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
8436 | { | |
8437 | int length = 3; | |
8438 | ||
8439 | if (fragP->fr_var < length) | |
8440 | as_fatal (_("fr_var %lu < length %d"), | |
8441 | (long) fragP->fr_var, length); | |
8442 | else | |
8443 | { | |
8444 | assemble_nop (length, | |
8445 | fragP->fr_literal + fragP->fr_fix); | |
8446 | fragP->fr_fix += length; | |
8447 | fragP->fr_var -= length; | |
8448 | } | |
8449 | bytes_added += length; | |
8450 | } | |
8451 | } | |
8452 | } | |
8453 | frag_wane (fragP); | |
8454 | } | |
9c2799c2 | 8455 | gas_assert (fragP->fr_type != rs_machine_dependent |
c9049d30 AM |
8456 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); |
8457 | } | |
8458 | } | |
e0001a05 NC |
8459 | } |
8460 | ||
8461 | ||
d77b99c9 | 8462 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 8463 | |
d77b99c9 | 8464 | static offsetT |
7fa3d080 BW |
8465 | min_bytes_to_other_loop_end (fragS *fragP, |
8466 | fragS *current_target, | |
d77b99c9 | 8467 | offsetT max_size) |
e0001a05 | 8468 | { |
d77b99c9 | 8469 | offsetT offset = 0; |
e0001a05 NC |
8470 | fragS *current_fragP; |
8471 | ||
8472 | for (current_fragP = fragP; | |
8473 | current_fragP; | |
8474 | current_fragP = current_fragP->fr_next) | |
8475 | { | |
8476 | if (current_fragP->tc_frag_data.is_loop_target | |
8477 | && current_fragP != current_target) | |
05d58145 | 8478 | return offset; |
e0001a05 NC |
8479 | |
8480 | offset += unrelaxed_frag_min_size (current_fragP); | |
8481 | ||
05d58145 | 8482 | if (offset >= max_size) |
e0001a05 NC |
8483 | return max_size; |
8484 | } | |
8485 | return max_size; | |
8486 | } | |
8487 | ||
8488 | ||
d77b99c9 | 8489 | static offsetT |
7fa3d080 | 8490 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 8491 | { |
d77b99c9 | 8492 | offsetT size = fragP->fr_fix; |
e0001a05 | 8493 | |
d77b99c9 | 8494 | /* Add fill size. */ |
e0001a05 NC |
8495 | if (fragP->fr_type == rs_fill) |
8496 | size += fragP->fr_offset; | |
8497 | ||
8498 | return size; | |
8499 | } | |
8500 | ||
8501 | ||
d77b99c9 | 8502 | static offsetT |
7fa3d080 | 8503 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 8504 | { |
d77b99c9 | 8505 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
8506 | switch (fragP->fr_type) |
8507 | { | |
8508 | case 0: | |
c138bc38 | 8509 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
8510 | end up with type 0. */ |
8511 | break; | |
8512 | case rs_fill: | |
8513 | case rs_org: | |
8514 | case rs_space: | |
8515 | size += fragP->fr_offset; | |
8516 | break; | |
8517 | case rs_align: | |
8518 | case rs_align_code: | |
8519 | case rs_align_test: | |
8520 | case rs_leb128: | |
8521 | case rs_cfa: | |
8522 | case rs_dwarf2dbg: | |
8523 | /* No further adjustments needed. */ | |
8524 | break; | |
8525 | case rs_machine_dependent: | |
8526 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
8527 | size += fragP->fr_var; | |
8528 | break; | |
8529 | default: | |
8530 | /* We had darn well better know how big it is. */ | |
9c2799c2 | 8531 | gas_assert (0); |
43cd72b9 BW |
8532 | break; |
8533 | } | |
8534 | ||
8535 | return size; | |
8536 | } | |
8537 | ||
8538 | ||
e0001a05 NC |
8539 | /* Re-process all of the fragments looking to convert all |
8540 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
8541 | ||
8542 | A) | |
8543 | 1) the instruction size count to the loop end label | |
8544 | is too short (<= 2 instructions), | |
8545 | 2) loop has a jump or branch in it | |
8546 | ||
8547 | or B) | |
43cd72b9 | 8548 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
8549 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
8550 | 3) the instruction size count to the loop end label is too short | |
8551 | (<= 2 instructions) | |
8552 | then convert this frag (and maybe the next one) to generate a NOP. | |
8553 | In any case close it off with a .fill 0. */ | |
8554 | ||
d77b99c9 | 8555 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
8556 | static bfd_boolean branch_before_loop_end (fragS *); |
8557 | ||
e0001a05 | 8558 | static void |
7fa3d080 | 8559 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
8560 | { |
8561 | frchainS *frchP; | |
c9049d30 | 8562 | asection *s; |
e0001a05 NC |
8563 | |
8564 | /* When this routine is called, all of the subsections are still intact | |
8565 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
8566 | for (s = stdoutput->sections; s; s = s->next) |
8567 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8568 | { | |
8569 | fragS *fragP; | |
c9049d30 | 8570 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; |
e0001a05 | 8571 | |
c9049d30 AM |
8572 | /* Walk over all of the fragments in a subsection. */ |
8573 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8574 | { | |
8575 | if (fragP->fr_type == rs_machine_dependent | |
8576 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
8577 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
8578 | { | |
8579 | TInsn t_insn; | |
8580 | fragS *loop_frag = next_non_empty_frag (fragP); | |
8581 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
c9049d30 | 8582 | current_opcode = t_insn.opcode; |
9c2799c2 | 8583 | gas_assert (xtensa_opcode_is_loop (xtensa_default_isa, |
64b607e6 | 8584 | current_opcode) == 1); |
c9049d30 | 8585 | } |
e0001a05 | 8586 | |
c9049d30 AM |
8587 | if (fragP->fr_type == rs_machine_dependent |
8588 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
8589 | { | |
8590 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 | |
8591 | && (branch_before_loop_end (fragP->fr_next) | |
8592 | || (workaround_all_short_loops | |
8593 | && current_opcode != XTENSA_UNDEFINED | |
8594 | && current_opcode != xtensa_loop_opcode))) | |
8595 | { | |
8596 | if (fragP->tc_frag_data.is_no_transform) | |
8597 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
8598 | else | |
8599 | relax_frag_add_nop (fragP); | |
8600 | } | |
8601 | frag_wane (fragP); | |
8602 | } | |
8603 | } | |
8604 | } | |
e0001a05 NC |
8605 | } |
8606 | ||
8607 | ||
d77b99c9 | 8608 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 8609 | |
d77b99c9 | 8610 | static int |
7fa3d080 BW |
8611 | count_insns_to_loop_end (fragS *base_fragP, |
8612 | bfd_boolean count_relax_add, | |
d77b99c9 | 8613 | int max_count) |
e0001a05 NC |
8614 | { |
8615 | fragS *fragP = NULL; | |
d77b99c9 | 8616 | int insn_count = 0; |
e0001a05 NC |
8617 | |
8618 | fragP = base_fragP; | |
8619 | ||
8620 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
8621 | { | |
8622 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
8623 | if (insn_count >= max_count) | |
8624 | return max_count; | |
8625 | ||
8626 | if (count_relax_add) | |
8627 | { | |
8628 | if (fragP->fr_type == rs_machine_dependent | |
8629 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
8630 | { | |
8631 | /* In order to add the appropriate number of | |
8632 | NOPs, we count an instruction for downstream | |
8633 | occurrences. */ | |
8634 | insn_count++; | |
8635 | if (insn_count >= max_count) | |
8636 | return max_count; | |
8637 | } | |
8638 | } | |
8639 | } | |
8640 | return insn_count; | |
8641 | } | |
8642 | ||
8643 | ||
d77b99c9 | 8644 | static int |
7fa3d080 | 8645 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 8646 | { |
43cd72b9 BW |
8647 | xtensa_isa isa = xtensa_default_isa; |
8648 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 8649 | int insn_count = 0; |
e0001a05 NC |
8650 | int offset = 0; |
8651 | ||
8652 | if (!fragP->tc_frag_data.is_insn) | |
8653 | return insn_count; | |
8654 | ||
43cd72b9 BW |
8655 | if (!insnbuf) |
8656 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8657 | ||
e0001a05 NC |
8658 | /* Decode the fixed instructions. */ |
8659 | while (offset < fragP->fr_fix) | |
8660 | { | |
43cd72b9 BW |
8661 | xtensa_format fmt; |
8662 | ||
d77b99c9 BW |
8663 | xtensa_insnbuf_from_chars |
8664 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
8665 | fmt = xtensa_format_decode (isa, insnbuf); |
8666 | ||
8667 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
8668 | { |
8669 | as_fatal (_("undecodable instruction in instruction frag")); | |
8670 | return insn_count; | |
8671 | } | |
43cd72b9 | 8672 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8673 | insn_count++; |
8674 | } | |
8675 | ||
8676 | return insn_count; | |
8677 | } | |
8678 | ||
8679 | ||
7fa3d080 BW |
8680 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
8681 | ||
43cd72b9 | 8682 | static bfd_boolean |
7fa3d080 | 8683 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
8684 | { |
8685 | fragS *fragP; | |
8686 | ||
8687 | for (fragP = base_fragP; | |
8688 | fragP && !fragP->tc_frag_data.is_loop_target; | |
8689 | fragP = fragP->fr_next) | |
8690 | { | |
8691 | if (unrelaxed_frag_has_b_j (fragP)) | |
8692 | return TRUE; | |
8693 | } | |
8694 | return FALSE; | |
8695 | } | |
8696 | ||
8697 | ||
43cd72b9 | 8698 | static bfd_boolean |
7fa3d080 | 8699 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 8700 | { |
43cd72b9 BW |
8701 | static xtensa_insnbuf insnbuf = NULL; |
8702 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
8703 | int offset = 0; |
8704 | ||
8705 | if (!fragP->tc_frag_data.is_insn) | |
8706 | return FALSE; | |
8707 | ||
43cd72b9 BW |
8708 | if (!insnbuf) |
8709 | insnbuf = xtensa_insnbuf_alloc (isa); | |
8710 | ||
e0001a05 NC |
8711 | /* Decode the fixed instructions. */ |
8712 | while (offset < fragP->fr_fix) | |
8713 | { | |
43cd72b9 BW |
8714 | xtensa_format fmt; |
8715 | int slot; | |
8716 | ||
d77b99c9 BW |
8717 | xtensa_insnbuf_from_chars |
8718 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
8719 | fmt = xtensa_format_decode (isa, insnbuf); |
8720 | if (fmt == XTENSA_UNDEFINED) | |
8721 | return FALSE; | |
8722 | ||
8723 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 8724 | { |
43cd72b9 BW |
8725 | xtensa_opcode opcode = |
8726 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
8727 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
8728 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
8729 | return TRUE; | |
e0001a05 | 8730 | } |
43cd72b9 | 8731 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
8732 | } |
8733 | return FALSE; | |
8734 | } | |
8735 | ||
8736 | ||
8737 | /* Checks to be made after initial assembly but before relaxation. */ | |
8738 | ||
7fa3d080 BW |
8739 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
8740 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
8741 | ||
e0001a05 | 8742 | static void |
7fa3d080 | 8743 | xtensa_sanity_check (void) |
e0001a05 | 8744 | { |
3b4dbbbf | 8745 | const char *file_name; |
d77b99c9 | 8746 | unsigned line; |
e0001a05 | 8747 | frchainS *frchP; |
c9049d30 | 8748 | asection *s; |
e0001a05 | 8749 | |
3b4dbbbf | 8750 | file_name = as_where (&line); |
c9049d30 AM |
8751 | for (s = stdoutput->sections; s; s = s->next) |
8752 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
8753 | { | |
8754 | fragS *fragP; | |
e0001a05 | 8755 | |
c9049d30 AM |
8756 | /* Walk over all of the fragments in a subsection. */ |
8757 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
8758 | { | |
c9049d30 | 8759 | if (fragP->fr_type == rs_machine_dependent |
3739860c | 8760 | && fragP->fr_subtype == RELAX_SLOTS |
a7284bf1 | 8761 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) |
c9049d30 AM |
8762 | { |
8763 | static xtensa_insnbuf insnbuf = NULL; | |
8764 | TInsn t_insn; | |
8765 | ||
8766 | if (fragP->fr_opcode != NULL) | |
8767 | { | |
8768 | if (!insnbuf) | |
8769 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
8770 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
8771 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
8772 | ||
8773 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
8774 | t_insn.opcode) == 1) | |
8775 | { | |
8776 | if (is_empty_loop (&t_insn, fragP)) | |
8777 | { | |
8778 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8779 | as_bad (_("invalid empty loop")); | |
8780 | } | |
8781 | if (!is_local_forward_loop (&t_insn, fragP)) | |
8782 | { | |
8783 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8784 | as_bad (_("loop target does not follow " | |
8785 | "loop instruction in section")); | |
8786 | } | |
8787 | } | |
8788 | } | |
8789 | } | |
8790 | } | |
8791 | } | |
e0001a05 NC |
8792 | new_logical_line (file_name, line); |
8793 | } | |
8794 | ||
8795 | ||
8796 | #define LOOP_IMMED_OPN 1 | |
8797 | ||
43cd72b9 | 8798 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 8799 | |
7fa3d080 BW |
8800 | static bfd_boolean |
8801 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 | 8802 | { |
91d6fa6a | 8803 | const expressionS *exp; |
e0001a05 NC |
8804 | symbolS *symbolP; |
8805 | fragS *next_fragP; | |
8806 | ||
8807 | if (insn->insn_type != ITYPE_INSN) | |
8808 | return FALSE; | |
8809 | ||
43cd72b9 | 8810 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8811 | return FALSE; |
8812 | ||
8813 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8814 | return FALSE; | |
8815 | ||
91d6fa6a | 8816 | exp = &insn->tok[LOOP_IMMED_OPN]; |
e0001a05 | 8817 | |
91d6fa6a | 8818 | if (exp->X_op != O_symbol) |
e0001a05 NC |
8819 | return FALSE; |
8820 | ||
91d6fa6a | 8821 | symbolP = exp->X_add_symbol; |
e0001a05 NC |
8822 | if (!symbolP) |
8823 | return FALSE; | |
8824 | ||
8825 | if (symbol_get_frag (symbolP) == NULL) | |
8826 | return FALSE; | |
8827 | ||
8828 | if (S_GET_VALUE (symbolP) != 0) | |
8829 | return FALSE; | |
8830 | ||
8831 | /* Walk through the zero-size fragments from this one. If we find | |
8832 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 8833 | |
e0001a05 NC |
8834 | for (next_fragP = fragP->fr_next; |
8835 | next_fragP != NULL; | |
8836 | next_fragP = next_fragP->fr_next) | |
8837 | { | |
8838 | if (next_fragP == symbol_get_frag (symbolP)) | |
8839 | return TRUE; | |
8840 | if (next_fragP->fr_fix != 0) | |
8841 | return FALSE; | |
8842 | } | |
8843 | return FALSE; | |
8844 | } | |
8845 | ||
8846 | ||
7fa3d080 BW |
8847 | static bfd_boolean |
8848 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 | 8849 | { |
91d6fa6a | 8850 | const expressionS *exp; |
e0001a05 NC |
8851 | symbolS *symbolP; |
8852 | fragS *next_fragP; | |
8853 | ||
8854 | if (insn->insn_type != ITYPE_INSN) | |
8855 | return FALSE; | |
8856 | ||
64b607e6 | 8857 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
8858 | return FALSE; |
8859 | ||
8860 | if (insn->ntok <= LOOP_IMMED_OPN) | |
8861 | return FALSE; | |
8862 | ||
91d6fa6a | 8863 | exp = &insn->tok[LOOP_IMMED_OPN]; |
e0001a05 | 8864 | |
91d6fa6a | 8865 | if (exp->X_op != O_symbol) |
e0001a05 NC |
8866 | return FALSE; |
8867 | ||
91d6fa6a | 8868 | symbolP = exp->X_add_symbol; |
e0001a05 NC |
8869 | if (!symbolP) |
8870 | return FALSE; | |
8871 | ||
8872 | if (symbol_get_frag (symbolP) == NULL) | |
8873 | return FALSE; | |
8874 | ||
8875 | /* Walk through fragments until we find the target. | |
8876 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 8877 | |
e0001a05 NC |
8878 | for (next_fragP = fragP->fr_next; |
8879 | next_fragP != NULL; | |
8880 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
8881 | { |
8882 | if (next_fragP == symbol_get_frag (symbolP)) | |
8883 | return TRUE; | |
8884 | } | |
e0001a05 NC |
8885 | |
8886 | return FALSE; | |
8887 | } | |
8888 | ||
2caa7ca0 BW |
8889 | |
8890 | #define XTINFO_NAME "Xtensa_Info" | |
8891 | #define XTINFO_NAMESZ 12 | |
8892 | #define XTINFO_TYPE 1 | |
8893 | ||
8894 | static void | |
8895 | xtensa_add_config_info (void) | |
8896 | { | |
8897 | asection *info_sec; | |
8898 | char *data, *p; | |
8899 | int sz; | |
8900 | ||
8901 | info_sec = subseg_new (".xtensa.info", 0); | |
8902 | bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY); | |
8903 | ||
325801bd | 8904 | data = XNEWVEC (char, 100); |
2caa7ca0 BW |
8905 | sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", |
8906 | XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI); | |
8907 | sz = strlen (data) + 1; | |
8908 | ||
8909 | /* Add enough null terminators to pad to a word boundary. */ | |
8910 | do | |
8911 | data[sz++] = 0; | |
8912 | while ((sz & 3) != 0); | |
8913 | ||
8914 | /* Follow the standard note section layout: | |
8915 | First write the length of the name string. */ | |
8916 | p = frag_more (4); | |
8917 | md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); | |
8918 | ||
8919 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
8920 | p = frag_more (4); | |
8921 | md_number_to_chars (p, (valueT) sz, 4); | |
8922 | ||
8923 | /* Write the note type. */ | |
8924 | p = frag_more (4); | |
8925 | md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); | |
8926 | ||
8927 | /* Write the name field. */ | |
8928 | p = frag_more (XTINFO_NAMESZ); | |
8929 | memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); | |
8930 | ||
8931 | /* Finally, write the descriptor. */ | |
8932 | p = frag_more (sz); | |
8933 | memcpy (p, data, sz); | |
8934 | ||
8935 | free (data); | |
8936 | } | |
8937 | ||
e0001a05 NC |
8938 | \f |
8939 | /* Alignment Functions. */ | |
8940 | ||
d77b99c9 BW |
8941 | static int |
8942 | get_text_align_power (unsigned target_size) | |
e0001a05 | 8943 | { |
03aaa593 BW |
8944 | if (target_size <= 4) |
8945 | return 2; | |
19ef5f3d SA |
8946 | |
8947 | if (target_size <= 8) | |
8948 | return 3; | |
8949 | ||
8950 | if (target_size <= 16) | |
8951 | return 4; | |
8952 | ||
8953 | if (target_size <= 32) | |
8954 | return 5; | |
8955 | ||
8956 | if (target_size <= 64) | |
8957 | return 6; | |
8958 | ||
8959 | if (target_size <= 128) | |
8960 | return 7; | |
8961 | ||
8962 | if (target_size <= 256) | |
8963 | return 8; | |
8964 | ||
8965 | if (target_size <= 512) | |
8966 | return 9; | |
8967 | ||
8968 | if (target_size <= 1024) | |
8969 | return 10; | |
8970 | ||
8971 | gas_assert (0); | |
8972 | return 0; | |
e0001a05 NC |
8973 | } |
8974 | ||
8975 | ||
d77b99c9 | 8976 | static int |
7fa3d080 BW |
8977 | get_text_align_max_fill_size (int align_pow, |
8978 | bfd_boolean use_nops, | |
8979 | bfd_boolean use_no_density) | |
e0001a05 NC |
8980 | { |
8981 | if (!use_nops) | |
8982 | return (1 << align_pow); | |
8983 | if (use_no_density) | |
8984 | return 3 * (1 << align_pow); | |
8985 | ||
8986 | return 1 + (1 << align_pow); | |
8987 | } | |
8988 | ||
8989 | ||
d77b99c9 BW |
8990 | /* Calculate the minimum bytes of fill needed at "address" to align a |
8991 | target instruction of size "target_size" so that it does not cross a | |
8992 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
8993 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
8994 | be filled by NOP instructions. */ | |
e0001a05 | 8995 | |
d77b99c9 | 8996 | static int |
7fa3d080 BW |
8997 | get_text_align_fill_size (addressT address, |
8998 | int align_pow, | |
8999 | int target_size, | |
9000 | bfd_boolean use_nops, | |
9001 | bfd_boolean use_no_density) | |
e0001a05 | 9002 | { |
d77b99c9 BW |
9003 | addressT alignment, fill, fill_limit, fill_step; |
9004 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 9005 | |
d77b99c9 | 9006 | alignment = (1 << align_pow); |
9c2799c2 | 9007 | gas_assert (target_size > 0 && alignment >= (addressT) target_size); |
c138bc38 | 9008 | |
e0001a05 NC |
9009 | if (!use_nops) |
9010 | { | |
d77b99c9 BW |
9011 | fill_limit = alignment; |
9012 | fill_step = 1; | |
e0001a05 | 9013 | } |
d77b99c9 | 9014 | else if (!use_no_density) |
e0001a05 | 9015 | { |
d77b99c9 BW |
9016 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
9017 | fill_limit = alignment * 2; | |
9018 | fill_step = 1; | |
9019 | skip_one = TRUE; | |
e0001a05 NC |
9020 | } |
9021 | else | |
9022 | { | |
d77b99c9 BW |
9023 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
9024 | fill_limit = alignment * 3; | |
9025 | fill_step = 3; | |
9026 | } | |
e0001a05 | 9027 | |
d77b99c9 BW |
9028 | /* Try all fill sizes until finding one that works. */ |
9029 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
9030 | { | |
9031 | if (skip_one && fill == 1) | |
9032 | continue; | |
9033 | if ((address + fill) >> align_pow | |
9034 | == (address + fill + target_size - 1) >> align_pow) | |
9035 | return fill; | |
e0001a05 | 9036 | } |
9c2799c2 | 9037 | gas_assert (0); |
e0001a05 NC |
9038 | return 0; |
9039 | } | |
9040 | ||
9041 | ||
664df4e4 BW |
9042 | static int |
9043 | branch_align_power (segT sec) | |
9044 | { | |
19ef5f3d SA |
9045 | /* If the Xtensa processor has a fetch width of X, and |
9046 | the section is aligned to at least that boundary, then a branch | |
9047 | target need only fit within that aligned block of memory to avoid | |
9048 | a stall. Otherwise, try to fit branch targets within 4-byte | |
9049 | aligned blocks (which may be insufficient, e.g., if the section | |
9050 | has no alignment, but it's good enough). */ | |
9051 | int fetch_align = get_text_align_power(xtensa_fetch_width); | |
9052 | int sec_align = get_recorded_alignment (sec); | |
9053 | ||
9054 | if (sec_align >= fetch_align) | |
9055 | return fetch_align; | |
664df4e4 BW |
9056 | |
9057 | return 2; | |
9058 | } | |
9059 | ||
9060 | ||
e0001a05 NC |
9061 | /* This will assert if it is not possible. */ |
9062 | ||
d77b99c9 BW |
9063 | static int |
9064 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 9065 | { |
d77b99c9 BW |
9066 | int count = 0; |
9067 | ||
e0001a05 NC |
9068 | if (use_no_density) |
9069 | { | |
9c2799c2 | 9070 | gas_assert (fill_size % 3 == 0); |
e0001a05 NC |
9071 | return (fill_size / 3); |
9072 | } | |
9073 | ||
9c2799c2 | 9074 | gas_assert (fill_size != 1); /* Bad argument. */ |
e0001a05 NC |
9075 | |
9076 | while (fill_size > 1) | |
9077 | { | |
d77b99c9 | 9078 | int insn_size = 3; |
e0001a05 NC |
9079 | if (fill_size == 2 || fill_size == 4) |
9080 | insn_size = 2; | |
9081 | fill_size -= insn_size; | |
9082 | count++; | |
9083 | } | |
9c2799c2 | 9084 | gas_assert (fill_size != 1); /* Bad algorithm. */ |
e0001a05 NC |
9085 | return count; |
9086 | } | |
9087 | ||
9088 | ||
d77b99c9 BW |
9089 | static int |
9090 | get_text_align_nth_nop_size (offsetT fill_size, | |
9091 | int n, | |
7fa3d080 | 9092 | bfd_boolean use_no_density) |
e0001a05 | 9093 | { |
d77b99c9 | 9094 | int count = 0; |
e0001a05 NC |
9095 | |
9096 | if (use_no_density) | |
9097 | return 3; | |
9098 | ||
9c2799c2 | 9099 | gas_assert (fill_size != 1); /* Bad argument. */ |
d77b99c9 | 9100 | |
e0001a05 NC |
9101 | while (fill_size > 1) |
9102 | { | |
d77b99c9 | 9103 | int insn_size = 3; |
e0001a05 NC |
9104 | if (fill_size == 2 || fill_size == 4) |
9105 | insn_size = 2; | |
9106 | fill_size -= insn_size; | |
9107 | count++; | |
9108 | if (n + 1 == count) | |
9109 | return insn_size; | |
9110 | } | |
9c2799c2 | 9111 | gas_assert (0); |
e0001a05 NC |
9112 | return 0; |
9113 | } | |
9114 | ||
9115 | ||
9116 | /* For the given fragment, find the appropriate address | |
9117 | for it to begin at if we are using NOPs to align it. */ | |
9118 | ||
9119 | static addressT | |
7fa3d080 | 9120 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 9121 | { |
43cd72b9 BW |
9122 | /* The rule is: get next fragment's FIRST instruction. Find |
9123 | the smallest number of bytes that need to be added to | |
9124 | ensure that the next fragment's FIRST instruction will fit | |
9125 | in a single word. | |
c138bc38 | 9126 | |
43cd72b9 BW |
9127 | E.G., 2 bytes : 0, 1, 2 mod 4 |
9128 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 9129 | |
43cd72b9 BW |
9130 | If the FIRST instruction MIGHT be relaxed, |
9131 | assume that it will become a 3-byte instruction. | |
c138bc38 | 9132 | |
43cd72b9 BW |
9133 | Note again here that LOOP instructions are not bundleable, |
9134 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 9135 | |
d77b99c9 | 9136 | int fill_size = 0; |
43cd72b9 BW |
9137 | int first_insn_size; |
9138 | int loop_insn_size; | |
9139 | addressT pre_opcode_bytes; | |
d77b99c9 | 9140 | int align_power; |
43cd72b9 BW |
9141 | fragS *first_insn; |
9142 | xtensa_opcode opcode; | |
9143 | bfd_boolean is_loop; | |
e0001a05 | 9144 | |
9c2799c2 NC |
9145 | gas_assert (fragP->fr_type == rs_machine_dependent); |
9146 | gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 9147 | |
43cd72b9 BW |
9148 | /* Find the loop frag. */ |
9149 | first_insn = next_non_empty_frag (fragP); | |
9150 | /* Now find the first insn frag. */ | |
9151 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 9152 | |
43cd72b9 | 9153 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
9c2799c2 | 9154 | gas_assert (is_loop); |
43cd72b9 | 9155 | loop_insn_size = xg_get_single_size (opcode); |
e0001a05 | 9156 | |
43cd72b9 BW |
9157 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
9158 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 9159 | |
43cd72b9 BW |
9160 | /* For loops, the alignment depends on the size of the |
9161 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 9162 | |
43cd72b9 | 9163 | if (first_insn == NULL) |
03aaa593 BW |
9164 | first_insn_size = xtensa_fetch_width; |
9165 | else | |
9166 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 9167 | |
43cd72b9 | 9168 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
9169 | align_power = get_text_align_power (first_insn_size); |
9170 | record_alignment (now_seg, align_power); | |
c138bc38 | 9171 | |
43cd72b9 | 9172 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
9173 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
9174 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
9175 | |
9176 | return address + fill_size; | |
9177 | } | |
9178 | ||
9179 | ||
43cd72b9 BW |
9180 | /* 3 mechanisms for relaxing an alignment: |
9181 | ||
9182 | Align to a power of 2. | |
9183 | Align so the next fragment's instruction does not cross a word boundary. | |
9184 | Align the current instruction so that if the next instruction | |
9185 | were 3 bytes, it would not cross a word boundary. | |
9186 | ||
e0001a05 NC |
9187 | We can align with: |
9188 | ||
43cd72b9 BW |
9189 | zeros - This is easy; always insert zeros. |
9190 | nops - 3-byte and 2-byte instructions | |
9191 | 2 - 2-byte nop | |
9192 | 3 - 3-byte nop | |
9193 | 4 - 2 2-byte nops | |
9194 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
9195 | widening - widen previous instructions. */ |
9196 | ||
d77b99c9 BW |
9197 | static offsetT |
9198 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 9199 | { |
43cd72b9 BW |
9200 | addressT target_address, loop_insn_offset; |
9201 | int target_size; | |
9202 | xtensa_opcode loop_opcode; | |
9203 | bfd_boolean is_loop; | |
d77b99c9 BW |
9204 | int align_power; |
9205 | offsetT opt_diff; | |
5f9084e9 | 9206 | offsetT branch_align; |
def13efb | 9207 | fragS *loop_frag; |
e0001a05 | 9208 | |
9c2799c2 | 9209 | gas_assert (fragP->fr_type == rs_machine_dependent); |
43cd72b9 | 9210 | switch (fragP->fr_subtype) |
e0001a05 | 9211 | { |
43cd72b9 BW |
9212 | case RELAX_DESIRE_ALIGN: |
9213 | target_size = next_frag_format_size (fragP); | |
9214 | if (target_size == XTENSA_UNDEFINED) | |
9215 | target_size = 3; | |
664df4e4 BW |
9216 | align_power = branch_align_power (now_seg); |
9217 | branch_align = 1 << align_power; | |
0e5cd789 BW |
9218 | /* Don't count on the section alignment being as large as the target. */ |
9219 | if (target_size > branch_align) | |
9220 | target_size = branch_align; | |
d77b99c9 | 9221 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
9222 | target_size, FALSE, FALSE); |
9223 | ||
664df4e4 BW |
9224 | *max_diff = (opt_diff + branch_align |
9225 | - (target_size + ((address + opt_diff) % branch_align))); | |
9c2799c2 | 9226 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 9227 | return opt_diff; |
e0001a05 | 9228 | |
43cd72b9 | 9229 | case RELAX_ALIGN_NEXT_OPCODE: |
def13efb BW |
9230 | /* The next non-empty frag after this one holds the LOOP instruction |
9231 | that needs to be aligned. The required alignment depends on the | |
9232 | size of the next non-empty frag after the loop frag, i.e., the | |
9233 | first instruction in the loop. */ | |
9234 | loop_frag = next_non_empty_frag (fragP); | |
9235 | target_size = get_loop_align_size (next_frag_format_size (loop_frag)); | |
43cd72b9 BW |
9236 | loop_insn_offset = 0; |
9237 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
9c2799c2 | 9238 | gas_assert (is_loop); |
43cd72b9 BW |
9239 | |
9240 | /* If the loop has been expanded then the LOOP instruction | |
9241 | could be at an offset from this fragment. */ | |
def13efb | 9242 | if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED) |
43cd72b9 BW |
9243 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); |
9244 | ||
43cd72b9 BW |
9245 | /* In an ideal world, which is what we are shooting for here, |
9246 | we wouldn't need to use any NOPs immediately prior to the | |
9247 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
9248 | will call get_noop_aligned_address. */ | |
9249 | target_address = | |
9250 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
def13efb | 9251 | align_power = get_text_align_power (target_size); |
d77b99c9 | 9252 | opt_diff = get_text_align_fill_size (target_address, align_power, |
43cd72b9 BW |
9253 | target_size, FALSE, FALSE); |
9254 | ||
9255 | *max_diff = xtensa_fetch_width | |
9256 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
9257 | - target_size + opt_diff; | |
9c2799c2 | 9258 | gas_assert (*max_diff >= opt_diff); |
43cd72b9 | 9259 | return opt_diff; |
e0001a05 | 9260 | |
43cd72b9 BW |
9261 | default: |
9262 | break; | |
e0001a05 | 9263 | } |
9c2799c2 | 9264 | gas_assert (0); |
43cd72b9 | 9265 | return 0; |
e0001a05 NC |
9266 | } |
9267 | ||
9268 | \f | |
9269 | /* md_relax_frag Hook and Helper Functions. */ | |
9270 | ||
7fa3d080 BW |
9271 | static long relax_frag_loop_align (fragS *, long); |
9272 | static long relax_frag_for_align (fragS *, long); | |
9273 | static long relax_frag_immed | |
9274 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
9275 | ||
fe6c2f1b MF |
9276 | /* Get projected address for the first fulcrum on a path from source to |
9277 | target. */ | |
9278 | static addressT xg_get_fulcrum (addressT source, addressT target) | |
b76f99d7 | 9279 | { |
fe6c2f1b MF |
9280 | offsetT delta = target - source; |
9281 | int n; | |
b76f99d7 | 9282 | |
fe6c2f1b MF |
9283 | n = (labs (delta) + J_RANGE - J_MARGIN - 1) / (J_RANGE - J_MARGIN); |
9284 | return source + delta / n; | |
9285 | } | |
b76f99d7 | 9286 | |
fe6c2f1b MF |
9287 | /* Given trampoline index, source and target of a jump find the best |
9288 | candidate trampoline for the first fulcrum. The best trampoline is | |
9289 | the one in the reach of "j' instruction from the source, closest to | |
9290 | the projected fulcrum address, and preferrably w/o a jump around or | |
9291 | with already initialized jump around. */ | |
9292 | static size_t xg_find_best_trampoline (struct trampoline_index *idx, | |
9293 | addressT source, addressT target) | |
b76f99d7 | 9294 | { |
fe6c2f1b MF |
9295 | addressT fulcrum = xg_get_fulcrum (source, target); |
9296 | size_t dist = 0; | |
9297 | size_t best = -1; | |
9298 | size_t base_tr = xg_find_trampoline (idx, fulcrum); | |
9299 | int checked = 1; | |
b76f99d7 | 9300 | |
fe6c2f1b MF |
9301 | /* Check trampoline frags around the base_tr to find the best. */ |
9302 | for (dist = 0; checked; ++dist) | |
b76f99d7 | 9303 | { |
fe6c2f1b MF |
9304 | int i; |
9305 | size_t tr = base_tr - dist; | |
9306 | ||
9307 | checked = 0; | |
9308 | ||
9309 | /* Trampolines are checked in the following order: | |
9310 | base_tr, base_tr + 1, base_tr - 1, base_tr + 2, base_tr - 2 */ | |
9311 | for (i = 0; i < 2; ++i, tr = base_tr + dist + 1) | |
9312 | if (tr < idx->n_entries) | |
9313 | { | |
9314 | fragS *trampoline_frag = idx->entry[tr]; | |
9315 | offsetT off; | |
9316 | ||
9317 | /* Don't check trampolines outside source - target interval. */ | |
9318 | if ((trampoline_frag->fr_address < source && | |
9319 | trampoline_frag->fr_address < target) || | |
9320 | (trampoline_frag->fr_address > source && | |
9321 | trampoline_frag->fr_address > target)) | |
9322 | continue; | |
9323 | ||
9324 | off = trampoline_frag->fr_address - fulcrum; | |
9325 | /* Stop if some trampoline is found and the search is more than | |
9326 | J_RANGE / 4 from the projected fulcrum. A trampoline w/o jump | |
9327 | around is nice, but it shouldn't have much overhead. */ | |
9328 | if (best < idx->n_entries && labs (off) > J_RANGE / 4) | |
9329 | return best; | |
9330 | ||
9331 | off = trampoline_frag->fr_address - source; | |
9332 | if (labs (off) < J_RANGE - J_MARGIN) | |
9333 | { | |
9334 | ++checked; | |
9335 | /* Stop if a trampoline w/o jump around is found or initialized | |
9336 | trampoline with jump around is found. */ | |
9337 | if (!trampoline_frag->tc_frag_data.needs_jump_around || | |
9338 | trampoline_frag->fr_fix) | |
9339 | return tr; | |
9340 | else if (best >= idx->n_entries) | |
9341 | best = tr; | |
9342 | } | |
9343 | } | |
b76f99d7 | 9344 | } |
fe6c2f1b MF |
9345 | |
9346 | if (best < idx->n_entries) | |
9347 | return best; | |
9348 | else | |
9349 | as_fatal (_("cannot find suitable trampoline")); | |
b76f99d7 MF |
9350 | } |
9351 | ||
fe6c2f1b MF |
9352 | static fixS *xg_relax_fixup (struct trampoline_index *idx, fixS *fixP) |
9353 | { | |
9354 | symbolS *s = fixP->fx_addsy; | |
9355 | addressT source = fixP->fx_frag->fr_address; | |
9356 | addressT target = S_GET_VALUE (s) + fixP->fx_offset; | |
9357 | size_t tr = xg_find_best_trampoline (idx, source, target); | |
9358 | fragS *trampoline_frag = idx->entry[tr]; | |
9359 | fixS *newfixP; | |
9360 | ||
9361 | init_trampoline_frag (trampoline_frag); | |
9362 | newfixP = xg_append_jump (trampoline_frag, | |
9363 | fixP->fx_addsy, fixP->fx_offset); | |
9364 | ||
9365 | /* Adjust the fixup for the original "j" instruction to | |
9366 | point to the newly added jump. */ | |
9367 | fixP->fx_addsy = trampoline_frag->fr_symbol; | |
9368 | fixP->fx_offset = trampoline_frag->fr_fix - 3; | |
9369 | fixP->tc_fix_data.X_add_symbol = trampoline_frag->fr_symbol; | |
9370 | fixP->tc_fix_data.X_add_number = trampoline_frag->fr_fix - 3; | |
9371 | ||
9372 | trampoline_frag->tc_frag_data.relax_seen = FALSE; | |
9373 | ||
9374 | if (xg_is_trampoline_frag_full (trampoline_frag)) | |
9375 | xg_remove_trampoline_from_index (idx, tr); | |
9376 | ||
9377 | return newfixP; | |
9378 | } | |
9379 | ||
9380 | static bfd_boolean xg_is_relaxable_fixup (fixS *fixP) | |
b76f99d7 MF |
9381 | { |
9382 | xtensa_isa isa = xtensa_default_isa; | |
fe6c2f1b MF |
9383 | addressT addr = fixP->fx_frag->fr_address; |
9384 | addressT target; | |
9385 | offsetT delta; | |
b76f99d7 MF |
9386 | symbolS *s = fixP->fx_addsy; |
9387 | int slot; | |
9388 | xtensa_format fmt; | |
9389 | xtensa_opcode opcode; | |
9390 | ||
9391 | if (fixP->fx_r_type < BFD_RELOC_XTENSA_SLOT0_OP || | |
9392 | fixP->fx_r_type > BFD_RELOC_XTENSA_SLOT14_OP) | |
9393 | return FALSE; | |
fe6c2f1b MF |
9394 | |
9395 | target = S_GET_VALUE (s) + fixP->fx_offset; | |
b76f99d7 MF |
9396 | delta = target - addr; |
9397 | ||
fe6c2f1b | 9398 | if (labs (delta) < J_RANGE - J_MARGIN) |
b76f99d7 MF |
9399 | return FALSE; |
9400 | ||
9401 | xtensa_insnbuf_from_chars (isa, trampoline_buf, | |
9402 | (unsigned char *) fixP->fx_frag->fr_literal + | |
9403 | fixP->fx_where, 0); | |
9404 | fmt = xtensa_format_decode (isa, trampoline_buf); | |
9405 | gas_assert (fmt != XTENSA_UNDEFINED); | |
9406 | slot = fixP->tc_fix_data.slot; | |
9407 | xtensa_format_get_slot (isa, fmt, slot, trampoline_buf, trampoline_slotbuf); | |
9408 | opcode = xtensa_opcode_decode (isa, fmt, slot, trampoline_slotbuf); | |
fe6c2f1b | 9409 | return opcode == xtensa_j_opcode; |
b76f99d7 MF |
9410 | } |
9411 | ||
fe6c2f1b | 9412 | static void xg_relax_fixups (struct trampoline_seg *ts) |
b76f99d7 | 9413 | { |
fe6c2f1b MF |
9414 | struct trampoline_index *idx = &ts->index; |
9415 | segment_info_type *seginfo = seg_info (now_seg); | |
9416 | fixS *fx; | |
b76f99d7 | 9417 | |
fe6c2f1b | 9418 | for (fx = seginfo->fix_root; fx; fx = fx->fx_next) |
b76f99d7 | 9419 | { |
fe6c2f1b | 9420 | fixS *fixP = fx; |
148d6384 MF |
9421 | struct trampoline_chain *tc = NULL; |
9422 | ||
9423 | if (xg_is_relaxable_fixup (fixP)) | |
9424 | { | |
9425 | tc = xg_find_best_eq_target (ts, fixP->fx_frag->fr_address, | |
9426 | &fixP->fx_addsy, &fixP->fx_offset); | |
9427 | if (!tc) | |
9428 | tc = xg_create_trampoline_chain (ts, fixP->fx_addsy, | |
9429 | fixP->fx_offset); | |
9430 | gas_assert (tc); | |
9431 | } | |
b76f99d7 | 9432 | |
fe6c2f1b | 9433 | while (xg_is_relaxable_fixup (fixP)) |
148d6384 MF |
9434 | { |
9435 | fixP = xg_relax_fixup (idx, fixP); | |
9436 | xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol, | |
9437 | fixP->fx_where); | |
9438 | } | |
b76f99d7 | 9439 | } |
b76f99d7 | 9440 | } |
7fa3d080 | 9441 | |
fe6c2f1b MF |
9442 | /* Given a trampoline frag relax all jumps that might want to use this |
9443 | trampoline. Only do real work once per relaxation cycle, when | |
9444 | xg_relax_trampoline is called for the first trampoline in the now_seg. | |
9445 | Don't use stretch, don't update new_stretch: place fulcrums with a | |
9446 | slack to tolerate code movement. In the worst case if a jump between | |
9447 | two trampolines wouldn't reach the next relaxation pass will fix it. */ | |
9448 | static void xg_relax_trampoline (fragS *fragP, long stretch ATTRIBUTE_UNUSED, | |
9449 | long *new_stretch ATTRIBUTE_UNUSED) | |
120bc8b8 | 9450 | { |
fe6c2f1b | 9451 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); |
120bc8b8 | 9452 | |
fe6c2f1b MF |
9453 | if (ts->index.n_entries && ts->index.entry[0] == fragP) |
9454 | xg_relax_fixups (ts); | |
120bc8b8 MF |
9455 | } |
9456 | ||
e0001a05 NC |
9457 | /* Return the number of bytes added to this fragment, given that the |
9458 | input has been stretched already by "stretch". */ | |
9459 | ||
9460 | long | |
7fa3d080 | 9461 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 9462 | { |
43cd72b9 | 9463 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
9464 | int unreported = fragP->tc_frag_data.unreported_expansion; |
9465 | long new_stretch = 0; | |
3b4dbbbf | 9466 | const char *file_name; |
d77b99c9 BW |
9467 | unsigned line; |
9468 | int lit_size; | |
43cd72b9 BW |
9469 | static xtensa_insnbuf vbuf = NULL; |
9470 | int slot, num_slots; | |
9471 | xtensa_format fmt; | |
e0001a05 | 9472 | |
3b4dbbbf | 9473 | file_name = as_where (&line); |
e0001a05 NC |
9474 | new_logical_line (fragP->fr_file, fragP->fr_line); |
9475 | ||
9476 | fragP->tc_frag_data.unreported_expansion = 0; | |
9477 | ||
9478 | switch (fragP->fr_subtype) | |
9479 | { | |
9480 | case RELAX_ALIGN_NEXT_OPCODE: | |
9481 | /* Always convert. */ | |
43cd72b9 BW |
9482 | if (fragP->tc_frag_data.relax_seen) |
9483 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
9484 | break; |
9485 | ||
9486 | case RELAX_LOOP_END: | |
9487 | /* Do nothing. */ | |
9488 | break; | |
9489 | ||
9490 | case RELAX_LOOP_END_ADD_NOP: | |
9491 | /* Add a NOP and switch to .fill 0. */ | |
9492 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 9493 | frag_wane (fragP); |
e0001a05 NC |
9494 | break; |
9495 | ||
9496 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 9497 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
9498 | it or not. */ |
9499 | break; | |
9500 | ||
9501 | case RELAX_LITERAL: | |
9502 | case RELAX_LITERAL_FINAL: | |
9503 | return 0; | |
9504 | ||
9505 | case RELAX_LITERAL_NR: | |
9506 | lit_size = 4; | |
9507 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 9508 | gas_assert (unreported == lit_size); |
e0001a05 NC |
9509 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); |
9510 | fragP->fr_var -= lit_size; | |
9511 | fragP->fr_fix += lit_size; | |
9512 | new_stretch = 4; | |
9513 | break; | |
9514 | ||
43cd72b9 BW |
9515 | case RELAX_SLOTS: |
9516 | if (vbuf == NULL) | |
9517 | vbuf = xtensa_insnbuf_alloc (isa); | |
9518 | ||
d77b99c9 BW |
9519 | xtensa_insnbuf_from_chars |
9520 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
9521 | fmt = xtensa_format_decode (isa, vbuf); |
9522 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 9523 | |
43cd72b9 BW |
9524 | for (slot = 0; slot < num_slots; slot++) |
9525 | { | |
9526 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
9527 | { | |
9528 | case RELAX_NARROW: | |
9529 | if (fragP->tc_frag_data.relax_seen) | |
9530 | new_stretch += relax_frag_for_align (fragP, stretch); | |
9531 | break; | |
9532 | ||
9533 | case RELAX_IMMED: | |
9534 | case RELAX_IMMED_STEP1: | |
9535 | case RELAX_IMMED_STEP2: | |
b81bf389 | 9536 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
9537 | /* Place the immediate. */ |
9538 | new_stretch += relax_frag_immed | |
9539 | (now_seg, fragP, stretch, | |
9540 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
9541 | fmt, slot, stretched_p, FALSE); | |
9542 | break; | |
9543 | ||
9544 | default: | |
9545 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
9546 | break; | |
9547 | } | |
9548 | } | |
e0001a05 NC |
9549 | break; |
9550 | ||
9551 | case RELAX_LITERAL_POOL_BEGIN: | |
b46824bd MF |
9552 | if (fragP->fr_var != 0) |
9553 | { | |
9554 | /* We have a converted "candidate" literal pool; | |
9555 | assemble a jump around it. */ | |
9556 | TInsn insn; | |
9557 | if (!litpool_slotbuf) | |
9558 | { | |
9559 | litpool_buf = xtensa_insnbuf_alloc (isa); | |
9560 | litpool_slotbuf = xtensa_insnbuf_alloc (isa); | |
9561 | } | |
9562 | new_stretch += 3; | |
9563 | fragP->tc_frag_data.relax_seen = FALSE; /* Need another pass. */ | |
9564 | fragP->tc_frag_data.is_insn = TRUE; | |
9565 | tinsn_init (&insn); | |
9566 | insn.insn_type = ITYPE_INSN; | |
9567 | insn.opcode = xtensa_j_opcode; | |
9568 | insn.ntok = 1; | |
9569 | set_expr_symbol_offset (&insn.tok[0], fragP->fr_symbol, | |
9570 | fragP->fr_fix); | |
9571 | fmt = xg_get_single_format (xtensa_j_opcode); | |
9572 | tinsn_to_slotbuf (fmt, 0, &insn, litpool_slotbuf); | |
9573 | xtensa_format_set_slot (isa, fmt, 0, litpool_buf, litpool_slotbuf); | |
9574 | xtensa_insnbuf_to_chars (isa, litpool_buf, | |
9575 | (unsigned char *)fragP->fr_literal + | |
9576 | fragP->fr_fix, 3); | |
9577 | fragP->fr_fix += 3; | |
9578 | fragP->fr_var -= 3; | |
9579 | /* Add a fix-up. */ | |
9580 | fix_new (fragP, 0, 3, fragP->fr_symbol, 0, TRUE, | |
9581 | BFD_RELOC_XTENSA_SLOT0_OP); | |
9582 | } | |
9583 | break; | |
9584 | ||
e0001a05 | 9585 | case RELAX_LITERAL_POOL_END: |
b46824bd | 9586 | case RELAX_LITERAL_POOL_CANDIDATE_BEGIN: |
43cd72b9 BW |
9587 | case RELAX_MAYBE_UNREACHABLE: |
9588 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
9589 | /* No relaxation required. */ |
9590 | break; | |
9591 | ||
43cd72b9 BW |
9592 | case RELAX_FILL_NOP: |
9593 | case RELAX_UNREACHABLE: | |
9594 | if (fragP->tc_frag_data.relax_seen) | |
9595 | new_stretch += relax_frag_for_align (fragP, stretch); | |
9596 | break; | |
9597 | ||
a82c7d90 DW |
9598 | case RELAX_TRAMPOLINE: |
9599 | if (fragP->tc_frag_data.relax_seen) | |
120bc8b8 | 9600 | xg_relax_trampoline (fragP, stretch, &new_stretch); |
a82c7d90 DW |
9601 | break; |
9602 | ||
e0001a05 NC |
9603 | default: |
9604 | as_bad (_("bad relaxation state")); | |
9605 | } | |
9606 | ||
43cd72b9 | 9607 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 9608 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
9609 | { |
9610 | fragP->tc_frag_data.relax_seen = TRUE; | |
9611 | *stretched_p = 1; | |
9612 | } | |
9613 | ||
e0001a05 NC |
9614 | new_logical_line (file_name, line); |
9615 | return new_stretch; | |
9616 | } | |
9617 | ||
9618 | ||
9619 | static long | |
7fa3d080 | 9620 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
9621 | { |
9622 | addressT old_address, old_next_address, old_size; | |
9623 | addressT new_address, new_next_address, new_size; | |
9624 | addressT growth; | |
9625 | ||
43cd72b9 BW |
9626 | /* All the frags with relax_frag_for_alignment prior to this one in the |
9627 | section have been done, hopefully eliminating the need for a NOP here. | |
9628 | But, this will put it in if necessary. */ | |
e0001a05 NC |
9629 | |
9630 | /* Calculate the old address of this fragment and the next fragment. */ | |
9631 | old_address = fragP->fr_address - stretch; | |
9632 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 9633 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
9634 | old_size = old_next_address - old_address; |
9635 | ||
9636 | /* Calculate the new address of this fragment and the next fragment. */ | |
9637 | new_address = fragP->fr_address; | |
9638 | new_next_address = | |
9639 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
9640 | new_size = new_next_address - new_address; | |
9641 | ||
9642 | growth = new_size - old_size; | |
9643 | ||
9644 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 9645 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
9646 | return growth; |
9647 | } | |
9648 | ||
9649 | ||
43cd72b9 | 9650 | /* Add a NOP instruction. */ |
e0001a05 NC |
9651 | |
9652 | static long | |
7fa3d080 | 9653 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 9654 | { |
e0001a05 | 9655 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
9656 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
9657 | assemble_nop (length, nop_buf); | |
e0001a05 | 9658 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 9659 | |
e0001a05 NC |
9660 | if (fragP->fr_var < length) |
9661 | { | |
dd49a749 | 9662 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
9663 | return 0; |
9664 | } | |
9665 | ||
9666 | fragP->fr_fix += length; | |
9667 | fragP->fr_var -= length; | |
e0001a05 NC |
9668 | return length; |
9669 | } | |
9670 | ||
9671 | ||
7fa3d080 BW |
9672 | static long future_alignment_required (fragS *, long); |
9673 | ||
e0001a05 | 9674 | static long |
7fa3d080 | 9675 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 9676 | { |
43cd72b9 BW |
9677 | /* Overview of the relaxation procedure for alignment: |
9678 | We can widen with NOPs or by widening instructions or by filling | |
9679 | bytes after jump instructions. Find the opportune places and widen | |
9680 | them if necessary. */ | |
9681 | ||
9682 | long stretch_me; | |
9683 | long diff; | |
e0001a05 | 9684 | |
9c2799c2 | 9685 | gas_assert (fragP->fr_subtype == RELAX_FILL_NOP |
43cd72b9 BW |
9686 | || fragP->fr_subtype == RELAX_UNREACHABLE |
9687 | || (fragP->fr_subtype == RELAX_SLOTS | |
9688 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
9689 | ||
9690 | stretch_me = future_alignment_required (fragP, stretch); | |
9691 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
9692 | if (diff == 0) | |
9693 | return 0; | |
e0001a05 | 9694 | |
43cd72b9 | 9695 | if (diff < 0) |
e0001a05 | 9696 | { |
43cd72b9 BW |
9697 | /* We expanded on a previous pass. Can we shrink now? */ |
9698 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
9699 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 9700 | { |
43cd72b9 BW |
9701 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
9702 | return -shrink; | |
e0001a05 NC |
9703 | } |
9704 | return 0; | |
9705 | } | |
9706 | ||
43cd72b9 BW |
9707 | /* Below here, diff > 0. */ |
9708 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 9709 | |
43cd72b9 | 9710 | return diff; |
e0001a05 NC |
9711 | } |
9712 | ||
9713 | ||
43cd72b9 BW |
9714 | /* Return the address of the next frag that should be aligned. |
9715 | ||
9716 | By "address" we mean the address it _would_ be at if there | |
9717 | is no action taken to align it between here and the target frag. | |
9718 | In other words, if no narrows and no fill nops are used between | |
9719 | here and the frag to align, _even_if_ some of the frags we use | |
9720 | to align targets have already expanded on a previous relaxation | |
9721 | pass. | |
9722 | ||
9723 | Also, count each frag that may be used to help align the target. | |
9724 | ||
9725 | Return 0 if there are no frags left in the chain that need to be | |
9726 | aligned. */ | |
9727 | ||
9728 | static addressT | |
7fa3d080 BW |
9729 | find_address_of_next_align_frag (fragS **fragPP, |
9730 | int *wide_nops, | |
9731 | int *narrow_nops, | |
9732 | int *widens, | |
9733 | bfd_boolean *paddable) | |
e0001a05 | 9734 | { |
43cd72b9 BW |
9735 | fragS *fragP = *fragPP; |
9736 | addressT address = fragP->fr_address; | |
9737 | ||
9738 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
9739 | |
9740 | while (fragP) | |
9741 | { | |
9742 | /* Limit this to a small search. */ | |
b5e4a23d | 9743 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
9744 | { |
9745 | *fragPP = fragP; | |
9746 | return 0; | |
9747 | } | |
e0001a05 NC |
9748 | address += fragP->fr_fix; |
9749 | ||
43cd72b9 BW |
9750 | if (fragP->fr_type == rs_fill) |
9751 | address += fragP->fr_offset * fragP->fr_var; | |
9752 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 9753 | { |
e0001a05 NC |
9754 | switch (fragP->fr_subtype) |
9755 | { | |
43cd72b9 BW |
9756 | case RELAX_UNREACHABLE: |
9757 | *paddable = TRUE; | |
9758 | break; | |
9759 | ||
9760 | case RELAX_FILL_NOP: | |
9761 | (*wide_nops)++; | |
9762 | if (!fragP->tc_frag_data.is_no_density) | |
9763 | (*narrow_nops)++; | |
9764 | break; | |
9765 | ||
9766 | case RELAX_SLOTS: | |
9767 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
9768 | { | |
9769 | (*widens)++; | |
9770 | break; | |
9771 | } | |
5bb3703f | 9772 | address += total_frag_text_expansion (fragP); |
e0001a05 NC |
9773 | break; |
9774 | ||
9775 | case RELAX_IMMED: | |
43cd72b9 | 9776 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
9777 | break; |
9778 | ||
9779 | case RELAX_ALIGN_NEXT_OPCODE: | |
9780 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
9781 | *fragPP = fragP; |
9782 | return address; | |
9783 | ||
9784 | case RELAX_MAYBE_UNREACHABLE: | |
9785 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9786 | /* Do nothing. */ | |
e0001a05 NC |
9787 | break; |
9788 | ||
9789 | default: | |
43cd72b9 BW |
9790 | /* Just punt if we don't know the type. */ |
9791 | *fragPP = fragP; | |
9792 | return 0; | |
e0001a05 | 9793 | } |
43cd72b9 | 9794 | } |
c138bc38 | 9795 | else |
43cd72b9 BW |
9796 | { |
9797 | /* Just punt if we don't know the type. */ | |
9798 | *fragPP = fragP; | |
9799 | return 0; | |
9800 | } | |
9801 | fragP = fragP->fr_next; | |
9802 | } | |
9803 | ||
9804 | *fragPP = fragP; | |
9805 | return 0; | |
9806 | } | |
9807 | ||
9808 | ||
7fa3d080 BW |
9809 | static long bytes_to_stretch (fragS *, int, int, int, int); |
9810 | ||
43cd72b9 | 9811 | static long |
7fa3d080 | 9812 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
9813 | { |
9814 | fragS *this_frag = fragP; | |
9815 | long address; | |
9816 | int num_widens = 0; | |
9817 | int wide_nops = 0; | |
9818 | int narrow_nops = 0; | |
9819 | bfd_boolean paddable = FALSE; | |
9820 | offsetT local_opt_diff; | |
9821 | offsetT opt_diff; | |
9822 | offsetT max_diff; | |
9823 | int stretch_amount = 0; | |
9824 | int local_stretch_amount; | |
9825 | int global_stretch_amount; | |
9826 | ||
7fa3d080 BW |
9827 | address = find_address_of_next_align_frag |
9828 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 9829 | |
b5e4a23d BW |
9830 | if (!address) |
9831 | { | |
9832 | if (this_frag->tc_frag_data.is_aligning_branch) | |
9833 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
9834 | else | |
9835 | frag_wane (this_frag); | |
9836 | } | |
9837 | else | |
43cd72b9 BW |
9838 | { |
9839 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
9840 | opt_diff = local_opt_diff; | |
9c2799c2 NC |
9841 | gas_assert (opt_diff >= 0); |
9842 | gas_assert (max_diff >= opt_diff); | |
c138bc38 | 9843 | if (max_diff == 0) |
43cd72b9 | 9844 | return 0; |
d2a033cd | 9845 | |
43cd72b9 BW |
9846 | if (fragP) |
9847 | fragP = fragP->fr_next; | |
9848 | ||
9849 | while (fragP && opt_diff < max_diff && address) | |
9850 | { | |
9851 | /* We only use these to determine if we can exit early | |
c138bc38 | 9852 | because there will be plenty of ways to align future |
43cd72b9 | 9853 | align frags. */ |
d77b99c9 | 9854 | int glob_widens = 0; |
43cd72b9 BW |
9855 | int dnn = 0; |
9856 | int dw = 0; | |
9857 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
9858 | address = find_address_of_next_align_frag |
9859 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 9860 | /* If there is a padable portion, then skip. */ |
664df4e4 | 9861 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 9862 | address = 0; |
43cd72b9 | 9863 | |
c138bc38 | 9864 | if (address) |
43cd72b9 BW |
9865 | { |
9866 | offsetT next_m_diff; | |
9867 | offsetT next_o_diff; | |
9868 | ||
9869 | /* Downrange frags haven't had stretch added to them yet. */ | |
9870 | address += stretch; | |
9871 | ||
9872 | /* The address also includes any text expansion from this | |
9873 | frag in a previous pass, but we don't want that. */ | |
9874 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
9875 | ||
9876 | /* Assume we are going to move at least opt_diff. In | |
9877 | reality, we might not be able to, but assuming that | |
9878 | we will helps catch cases where moving opt_diff pushes | |
9879 | the next target from aligned to unaligned. */ | |
9880 | address += opt_diff; | |
9881 | ||
9882 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
9883 | ||
9884 | /* Now cleanup for the adjustments to address. */ | |
9885 | next_o_diff += opt_diff; | |
9886 | next_m_diff += opt_diff; | |
9887 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
9888 | opt_diff = next_o_diff; | |
9889 | if (next_m_diff < max_diff) | |
9890 | max_diff = next_m_diff; | |
9891 | fragP = fragP->fr_next; | |
9892 | } | |
9893 | } | |
d2a033cd | 9894 | |
43cd72b9 BW |
9895 | /* If there are enough wideners in between, do it. */ |
9896 | if (paddable) | |
9897 | { | |
9898 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
9899 | { | |
1beeb686 | 9900 | gas_assert (opt_diff <= (signed) xtensa_fetch_width); |
43cd72b9 BW |
9901 | return opt_diff; |
9902 | } | |
9903 | return 0; | |
9904 | } | |
c138bc38 | 9905 | local_stretch_amount |
43cd72b9 BW |
9906 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
9907 | num_widens, local_opt_diff); | |
c138bc38 BW |
9908 | global_stretch_amount |
9909 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 9910 | num_widens, opt_diff); |
c138bc38 BW |
9911 | /* If the condition below is true, then the frag couldn't |
9912 | stretch the correct amount for the global case, so we just | |
9913 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
9914 | the correct alignment in the global case. */ |
9915 | if (global_stretch_amount < local_stretch_amount) | |
9916 | stretch_amount = local_stretch_amount; | |
9917 | else | |
9918 | stretch_amount = global_stretch_amount; | |
d2a033cd | 9919 | |
43cd72b9 BW |
9920 | if (this_frag->fr_subtype == RELAX_SLOTS |
9921 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
9c2799c2 | 9922 | gas_assert (stretch_amount <= 1); |
43cd72b9 BW |
9923 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) |
9924 | { | |
9925 | if (this_frag->tc_frag_data.is_no_density) | |
9c2799c2 | 9926 | gas_assert (stretch_amount == 3 || stretch_amount == 0); |
43cd72b9 | 9927 | else |
9c2799c2 | 9928 | gas_assert (stretch_amount <= 3); |
43cd72b9 BW |
9929 | } |
9930 | } | |
9931 | return stretch_amount; | |
9932 | } | |
9933 | ||
9934 | ||
9935 | /* The idea: widen everything you can to get a target or loop aligned, | |
9936 | then start using NOPs. | |
9937 | ||
43cd72b9 BW |
9938 | wide_nops = the number of wide NOPs available for aligning |
9939 | narrow_nops = the number of narrow NOPs available for aligning | |
9940 | (a subset of wide_nops) | |
9941 | widens = the number of narrow instructions that should be widened | |
9942 | ||
43cd72b9 BW |
9943 | */ |
9944 | ||
9945 | static long | |
7fa3d080 BW |
9946 | bytes_to_stretch (fragS *this_frag, |
9947 | int wide_nops, | |
9948 | int narrow_nops, | |
9949 | int num_widens, | |
9950 | int desired_diff) | |
43cd72b9 | 9951 | { |
19ef5f3d SA |
9952 | int nops_needed; |
9953 | int nop_bytes; | |
9954 | int extra_bytes; | |
43cd72b9 BW |
9955 | int bytes_short = desired_diff - num_widens; |
9956 | ||
3739860c | 9957 | gas_assert (desired_diff >= 0 |
1beeb686 | 9958 | && desired_diff < (signed) xtensa_fetch_width); |
43cd72b9 BW |
9959 | if (desired_diff == 0) |
9960 | return 0; | |
c138bc38 | 9961 | |
9c2799c2 | 9962 | gas_assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 9963 | |
43cd72b9 BW |
9964 | /* Always prefer widening to NOP-filling. */ |
9965 | if (bytes_short < 0) | |
9966 | { | |
9967 | /* There are enough RELAX_NARROW frags after this one | |
9968 | to align the target without widening this frag in any way. */ | |
9969 | return 0; | |
9970 | } | |
c138bc38 | 9971 | |
43cd72b9 BW |
9972 | if (bytes_short == 0) |
9973 | { | |
9974 | /* Widen every narrow between here and the align target | |
9975 | and the align target will be properly aligned. */ | |
9976 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
9977 | return 0; | |
9978 | else | |
9979 | return 1; | |
9980 | } | |
c138bc38 | 9981 | |
43cd72b9 BW |
9982 | /* From here we will need at least one NOP to get an alignment. |
9983 | However, we may not be able to align at all, in which case, | |
9984 | don't widen. */ | |
19ef5f3d SA |
9985 | nops_needed = desired_diff / 3; |
9986 | ||
9987 | /* If there aren't enough nops, don't widen. */ | |
9988 | if (nops_needed > wide_nops) | |
9989 | return 0; | |
9990 | ||
9991 | /* First try it with all wide nops. */ | |
9992 | nop_bytes = nops_needed * 3; | |
9993 | extra_bytes = desired_diff - nop_bytes; | |
9994 | ||
9995 | if (nop_bytes + num_widens >= desired_diff) | |
43cd72b9 | 9996 | { |
19ef5f3d SA |
9997 | if (this_frag->fr_subtype == RELAX_FILL_NOP) |
9998 | return 3; | |
9999 | else if (num_widens == extra_bytes) | |
10000 | return 1; | |
10001 | return 0; | |
e0001a05 | 10002 | } |
19ef5f3d SA |
10003 | |
10004 | /* Add a narrow nop. */ | |
10005 | nops_needed++; | |
10006 | nop_bytes += 2; | |
10007 | extra_bytes -= 2; | |
10008 | if (narrow_nops == 0 || nops_needed > wide_nops) | |
10009 | return 0; | |
10010 | ||
10011 | if (nop_bytes + num_widens >= desired_diff && extra_bytes >= 0) | |
43cd72b9 | 10012 | { |
19ef5f3d SA |
10013 | if (this_frag->fr_subtype == RELAX_FILL_NOP) |
10014 | return !this_frag->tc_frag_data.is_no_density ? 2 : 3; | |
10015 | else if (num_widens == extra_bytes) | |
10016 | return 1; | |
10017 | return 0; | |
10018 | } | |
e0001a05 | 10019 | |
19ef5f3d SA |
10020 | /* Replace a wide nop with a narrow nop--we can get here if |
10021 | extra_bytes was negative in the previous conditional. */ | |
10022 | if (narrow_nops == 1) | |
10023 | return 0; | |
10024 | nop_bytes--; | |
10025 | extra_bytes++; | |
10026 | if (nop_bytes + num_widens >= desired_diff) | |
10027 | { | |
10028 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
10029 | return !this_frag->tc_frag_data.is_no_density ? 2 : 3; | |
10030 | else if (num_widens == extra_bytes) | |
10031 | return 1; | |
10032 | return 0; | |
43cd72b9 | 10033 | } |
19ef5f3d SA |
10034 | |
10035 | /* If we can't satisfy any of the above cases, then we can't align | |
10036 | using padding or fill nops. */ | |
43cd72b9 | 10037 | return 0; |
e0001a05 NC |
10038 | } |
10039 | ||
10040 | ||
46888d71 | 10041 | static fragS * |
76a493ab | 10042 | xg_find_best_trampoline_for_tinsn (TInsn *tinsn, fragS *fragP) |
a82c7d90 | 10043 | { |
76a493ab MF |
10044 | symbolS *sym = tinsn->tok[0].X_add_symbol; |
10045 | addressT source = fragP->fr_address; | |
10046 | addressT target = S_GET_VALUE (sym) + tinsn->tok[0].X_add_number; | |
a82c7d90 | 10047 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); |
fe6c2f1b | 10048 | size_t i; |
a82c7d90 | 10049 | |
76a493ab MF |
10050 | if (!ts || !ts->index.n_entries) |
10051 | return NULL; | |
a82c7d90 | 10052 | |
76a493ab | 10053 | i = xg_find_best_trampoline (&ts->index, source, target); |
a82c7d90 | 10054 | |
76a493ab | 10055 | return ts->index.entry[i]; |
a82c7d90 DW |
10056 | } |
10057 | ||
10058 | ||
fe6c2f1b MF |
10059 | /* Append jump to sym + offset to the end of the trampoline frag fragP. |
10060 | Adjust fragP's jump around if it's present. Adjust fragP's fr_fix/fr_var | |
10061 | and finish the frag if it's full (but don't remove it from the trampoline | |
10062 | frag index). Return fixup for the newly created jump. */ | |
46888d71 | 10063 | static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset) |
fec68fb1 MF |
10064 | { |
10065 | fixS *fixP; | |
10066 | TInsn insn; | |
10067 | xtensa_format fmt; | |
10068 | xtensa_isa isa = xtensa_default_isa; | |
10069 | ||
10070 | gas_assert (fragP->fr_var >= 3); | |
10071 | tinsn_init (&insn); | |
10072 | insn.insn_type = ITYPE_INSN; | |
10073 | insn.opcode = xtensa_j_opcode; | |
10074 | insn.ntok = 1; | |
10075 | set_expr_symbol_offset (&insn.tok[0], sym, offset); | |
10076 | fmt = xg_get_single_format (xtensa_j_opcode); | |
10077 | tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf); | |
10078 | xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf); | |
10079 | xtensa_insnbuf_to_chars (isa, trampoline_buf, | |
10080 | (unsigned char *)fragP->fr_literal + fragP->fr_fix, 3); | |
10081 | fixP = fix_new (fragP, fragP->fr_fix, 3, sym, offset, TRUE, | |
10082 | BFD_RELOC_XTENSA_SLOT0_OP); | |
10083 | fixP->tc_fix_data.slot = 0; | |
10084 | ||
10085 | fragP->fr_fix += 3; | |
10086 | fragP->fr_var -= 3; | |
10087 | ||
10088 | /* Adjust the jump around this trampoline (if present). */ | |
46888d71 MF |
10089 | if (fragP->tc_frag_data.jump_around_fix) |
10090 | fragP->tc_frag_data.jump_around_fix->fx_offset += 3; | |
fec68fb1 | 10091 | |
fe6c2f1b MF |
10092 | /* Do we have room for more? */ |
10093 | if (xg_is_trampoline_frag_full (fragP)) | |
10094 | { | |
10095 | frag_wane (fragP); | |
10096 | fragP->fr_subtype = 0; | |
10097 | } | |
10098 | ||
fec68fb1 MF |
10099 | return fixP; |
10100 | } | |
10101 | ||
a82c7d90 DW |
10102 | |
10103 | static int | |
46888d71 | 10104 | init_trampoline_frag (fragS *fp) |
a82c7d90 | 10105 | { |
a82c7d90 DW |
10106 | int growth = 0; |
10107 | ||
10108 | if (fp->fr_fix == 0) | |
10109 | { | |
10110 | symbolS *lsym; | |
10111 | char label[10 + 2 * sizeof(fp)]; | |
a82c7d90 | 10112 | |
fec68fb1 | 10113 | sprintf (label, ".L0_TR_%p", fp); |
a82c7d90 DW |
10114 | lsym = (symbolS *)local_symbol_make (label, now_seg, 0, fp); |
10115 | fp->fr_symbol = lsym; | |
46888d71 | 10116 | if (fp->tc_frag_data.needs_jump_around) |
a82c7d90 | 10117 | { |
46888d71 | 10118 | fp->tc_frag_data.jump_around_fix = xg_append_jump (fp, lsym, 3); |
a82c7d90 | 10119 | growth = 3; |
a82c7d90 DW |
10120 | } |
10121 | } | |
10122 | return growth; | |
10123 | } | |
10124 | ||
a82c7d90 | 10125 | static int |
148d6384 | 10126 | xg_get_single_symbol_slot (fragS *fragP) |
a82c7d90 | 10127 | { |
148d6384 MF |
10128 | int i; |
10129 | int slot = -1; | |
24e5b4e6 MF |
10130 | |
10131 | for (i = 0; i < MAX_SLOTS; ++i) | |
148d6384 | 10132 | if (fragP->tc_frag_data.slot_symbols[i]) |
24e5b4e6 MF |
10133 | { |
10134 | gas_assert (slot == -1); | |
10135 | slot = i; | |
10136 | } | |
10137 | ||
10138 | gas_assert (slot >= 0 && slot < MAX_SLOTS); | |
a82c7d90 | 10139 | |
148d6384 MF |
10140 | return slot; |
10141 | } | |
10142 | ||
10143 | static fixS * | |
10144 | add_jump_to_trampoline (fragS *tramp, fragS *origfrag) | |
10145 | { | |
10146 | int slot = xg_get_single_symbol_slot (origfrag); | |
10147 | fixS *fixP; | |
10148 | ||
a82c7d90 | 10149 | /* Assemble a jump to the target label in the trampoline frag. */ |
148d6384 MF |
10150 | fixP = xg_append_jump (tramp, |
10151 | origfrag->tc_frag_data.slot_symbols[slot], | |
10152 | origfrag->tc_frag_data.slot_offsets[slot]); | |
fec68fb1 | 10153 | |
a82c7d90 | 10154 | /* Modify the original j to point here. */ |
fec68fb1 | 10155 | origfrag->tc_frag_data.slot_symbols[slot] = tramp->fr_symbol; |
24e5b4e6 | 10156 | origfrag->tc_frag_data.slot_offsets[slot] = tramp->fr_fix - 3; |
fec68fb1 | 10157 | |
a82c7d90 | 10158 | /* If trampoline is full, remove it from the list. */ |
fe6c2f1b MF |
10159 | if (xg_is_trampoline_frag_full (tramp)) |
10160 | { | |
10161 | struct trampoline_seg *ts = find_trampoline_seg (now_seg); | |
10162 | size_t tr = xg_find_trampoline (&ts->index, tramp->fr_address); | |
10163 | ||
10164 | gas_assert (ts->index.entry[tr] == tramp); | |
10165 | xg_remove_trampoline_from_index (&ts->index, tr); | |
10166 | } | |
a82c7d90 | 10167 | |
148d6384 | 10168 | return fixP; |
a82c7d90 DW |
10169 | } |
10170 | ||
10171 | ||
e0001a05 | 10172 | static long |
7fa3d080 BW |
10173 | relax_frag_immed (segT segP, |
10174 | fragS *fragP, | |
10175 | long stretch, | |
10176 | int min_steps, | |
10177 | xtensa_format fmt, | |
10178 | int slot, | |
10179 | int *stretched_p, | |
10180 | bfd_boolean estimate_only) | |
e0001a05 | 10181 | { |
43cd72b9 | 10182 | TInsn tinsn; |
e0001a05 NC |
10183 | int old_size; |
10184 | bfd_boolean negatable_branch = FALSE; | |
10185 | bfd_boolean branch_jmp_to_next = FALSE; | |
def13efb | 10186 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 | 10187 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
10188 | IStack istack; |
10189 | offsetT frag_offset; | |
10190 | int num_steps; | |
e0001a05 | 10191 | int num_text_bytes, num_literal_bytes; |
2276bc20 | 10192 | int literal_diff, total_text_diff, this_text_diff; |
e0001a05 | 10193 | |
9c2799c2 | 10194 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 10195 | |
b5e4a23d BW |
10196 | xg_clear_vinsn (&cur_vinsn); |
10197 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 10198 | if (cur_vinsn.num_slots > 1) |
def13efb | 10199 | from_wide_insn = TRUE; |
43cd72b9 | 10200 | |
b5e4a23d | 10201 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 10202 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 10203 | |
64b607e6 | 10204 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 10205 | return 0; |
e0001a05 | 10206 | |
b08b5071 | 10207 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 10208 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 10209 | |
43cd72b9 | 10210 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 10211 | |
43cd72b9 | 10212 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
10213 | |
10214 | /* Special case: replace a branch to the next instruction with a NOP. | |
10215 | This is required to work around a hardware bug in T1040.0 and also | |
10216 | serves as an optimization. */ | |
10217 | ||
10218 | if (branch_jmp_to_next | |
10219 | && ((old_size == 2) || (old_size == 3)) | |
10220 | && !next_frag_is_loop_target (fragP)) | |
10221 | return 0; | |
10222 | ||
10223 | /* Here is the fun stuff: Get the immediate field from this | |
10224 | instruction. If it fits, we are done. If not, find the next | |
10225 | instruction sequence that fits. */ | |
10226 | ||
10227 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
10228 | istack_init (&istack); | |
43cd72b9 | 10229 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 | 10230 | min_steps, stretch); |
9c2799c2 | 10231 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
e0001a05 | 10232 | |
43cd72b9 | 10233 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
10234 | |
10235 | /* Figure out the number of bytes needed. */ | |
e0001a05 | 10236 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
2276bc20 BW |
10237 | literal_diff |
10238 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
43cd72b9 | 10239 | num_text_bytes = get_num_stack_text_bytes (&istack); |
def13efb BW |
10240 | |
10241 | if (from_wide_insn) | |
43cd72b9 | 10242 | { |
2276bc20 BW |
10243 | int first = 0; |
10244 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
10245 | first++; | |
10246 | ||
43cd72b9 BW |
10247 | num_text_bytes += old_size; |
10248 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
10249 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
2276bc20 BW |
10250 | else |
10251 | { | |
10252 | /* The first instruction in the relaxed sequence will go after | |
10253 | the current wide instruction, and thus its symbolic immediates | |
10254 | might not fit. */ | |
3739860c | 10255 | |
2276bc20 | 10256 | istack_init (&istack); |
3739860c | 10257 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, |
2276bc20 BW |
10258 | frag_offset + old_size, |
10259 | min_steps, stretch + old_size); | |
9c2799c2 | 10260 | gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); |
2276bc20 | 10261 | |
3739860c | 10262 | fragP->tc_frag_data.slot_subtypes[slot] |
2276bc20 BW |
10263 | = (int) RELAX_IMMED + num_steps; |
10264 | ||
10265 | num_literal_bytes = get_num_stack_literal_bytes (&istack); | |
3739860c | 10266 | literal_diff |
2276bc20 | 10267 | = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; |
3739860c | 10268 | |
2276bc20 BW |
10269 | num_text_bytes = get_num_stack_text_bytes (&istack) + old_size; |
10270 | } | |
43cd72b9 | 10271 | } |
def13efb | 10272 | |
43cd72b9 BW |
10273 | total_text_diff = num_text_bytes - old_size; |
10274 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
10275 | |
10276 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
9c2799c2 NC |
10277 | gas_assert (num_text_bytes >= 0); |
10278 | gas_assert (literal_diff >= 0); | |
10279 | gas_assert (total_text_diff >= 0); | |
e0001a05 | 10280 | |
43cd72b9 BW |
10281 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
10282 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
9c2799c2 NC |
10283 | gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0); |
10284 | gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
10285 | |
10286 | /* Find the associated expandable literal for this. */ | |
10287 | if (literal_diff != 0) | |
10288 | { | |
2276bc20 | 10289 | fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
10290 | if (lit_fragP) |
10291 | { | |
9c2799c2 | 10292 | gas_assert (literal_diff == 4); |
e0001a05 NC |
10293 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; |
10294 | ||
10295 | /* We expect that the literal section state has NOT been | |
10296 | modified yet. */ | |
9c2799c2 | 10297 | gas_assert (lit_fragP->fr_type == rs_machine_dependent |
e0001a05 NC |
10298 | && lit_fragP->fr_subtype == RELAX_LITERAL); |
10299 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
10300 | ||
10301 | /* We need to mark this section for another iteration | |
10302 | of relaxation. */ | |
10303 | (*stretched_p)++; | |
10304 | } | |
10305 | } | |
10306 | ||
43cd72b9 | 10307 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 10308 | update_next_frag_state (fragP); |
e0001a05 | 10309 | |
a82c7d90 DW |
10310 | /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */ |
10311 | if (istack.ninsn > 2 && | |
10312 | istack.insn[istack.ninsn - 1].insn_type == ITYPE_LABEL && | |
10313 | istack.insn[istack.ninsn - 2].insn_type == ITYPE_INSN && | |
10314 | istack.insn[istack.ninsn - 2].opcode == xtensa_j_opcode) | |
10315 | { | |
10316 | TInsn *jinsn = &istack.insn[istack.ninsn - 2]; | |
148d6384 MF |
10317 | struct trampoline_seg *ts = find_trampoline_seg (segP); |
10318 | struct trampoline_chain *tc = NULL; | |
10319 | ||
10320 | if (ts && | |
10321 | !xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset, | |
10322 | total_text_diff)) | |
10323 | { | |
10324 | int s = xg_get_single_symbol_slot (fragP); | |
10325 | addressT offset = fragP->tc_frag_data.slot_offsets[s]; | |
10326 | ||
10327 | tc = xg_find_best_eq_target (ts, fragP->fr_address, | |
10328 | &fragP->tc_frag_data.slot_symbols[s], | |
10329 | &offset); | |
10330 | ||
10331 | if (!tc) | |
10332 | tc = xg_create_trampoline_chain (ts, | |
10333 | fragP->tc_frag_data.slot_symbols[s], | |
10334 | offset); | |
10335 | fragP->tc_frag_data.slot_offsets[s] = offset; | |
10336 | tinsn_immed_from_frag (jinsn, fragP, s); | |
10337 | } | |
a82c7d90 | 10338 | |
148d6384 MF |
10339 | if (!xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset, |
10340 | total_text_diff)) | |
a82c7d90 | 10341 | { |
76a493ab | 10342 | fragS *tf = xg_find_best_trampoline_for_tinsn (jinsn, fragP); |
a82c7d90 DW |
10343 | |
10344 | if (tf) | |
10345 | { | |
148d6384 MF |
10346 | fixS *fixP; |
10347 | ||
10348 | this_text_diff += init_trampoline_frag (tf) + 3; | |
10349 | fixP = add_jump_to_trampoline (tf, fragP); | |
10350 | xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol, | |
10351 | fixP->fx_where); | |
10352 | fragP->tc_frag_data.relax_seen = FALSE; | |
a82c7d90 DW |
10353 | } |
10354 | else | |
10355 | { | |
10356 | /* If target symbol is undefined, assume it will reach once linked. */ | |
10357 | expressionS *exp = &istack.insn[istack.ninsn - 2].tok[0]; | |
10358 | ||
10359 | if (exp->X_op == O_symbol && S_IS_DEFINED (exp->X_add_symbol)) | |
10360 | { | |
10361 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10362 | _("jump target out of range; no usable trampoline found")); | |
10363 | } | |
10364 | } | |
10365 | } | |
10366 | } | |
10367 | ||
43cd72b9 | 10368 | return this_text_diff; |
e0001a05 NC |
10369 | } |
10370 | ||
10371 | \f | |
10372 | /* md_convert_frag Hook and Helper Functions. */ | |
10373 | ||
7fa3d080 BW |
10374 | static void convert_frag_align_next_opcode (fragS *); |
10375 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
10376 | static void convert_frag_fill_nop (fragS *); | |
10377 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
10378 | ||
e0001a05 | 10379 | void |
7fa3d080 | 10380 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 10381 | { |
43cd72b9 BW |
10382 | static xtensa_insnbuf vbuf = NULL; |
10383 | xtensa_isa isa = xtensa_default_isa; | |
10384 | int slot; | |
10385 | int num_slots; | |
10386 | xtensa_format fmt; | |
3b4dbbbf | 10387 | const char *file_name; |
d77b99c9 | 10388 | unsigned line; |
e0001a05 | 10389 | |
3b4dbbbf | 10390 | file_name = as_where (&line); |
e0001a05 NC |
10391 | new_logical_line (fragp->fr_file, fragp->fr_line); |
10392 | ||
10393 | switch (fragp->fr_subtype) | |
10394 | { | |
10395 | case RELAX_ALIGN_NEXT_OPCODE: | |
10396 | /* Always convert. */ | |
10397 | convert_frag_align_next_opcode (fragp); | |
10398 | break; | |
10399 | ||
10400 | case RELAX_DESIRE_ALIGN: | |
10401 | /* Do nothing. If not aligned already, too bad. */ | |
10402 | break; | |
10403 | ||
43cd72b9 BW |
10404 | case RELAX_LITERAL: |
10405 | case RELAX_LITERAL_FINAL: | |
10406 | break; | |
10407 | ||
10408 | case RELAX_SLOTS: | |
10409 | if (vbuf == NULL) | |
10410 | vbuf = xtensa_insnbuf_alloc (isa); | |
10411 | ||
d77b99c9 BW |
10412 | xtensa_insnbuf_from_chars |
10413 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
10414 | fmt = xtensa_format_decode (isa, vbuf); |
10415 | num_slots = xtensa_format_num_slots (isa, fmt); | |
10416 | ||
10417 | for (slot = 0; slot < num_slots; slot++) | |
10418 | { | |
10419 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
10420 | { | |
10421 | case RELAX_NARROW: | |
10422 | convert_frag_narrow (sec, fragp, fmt, slot); | |
10423 | break; | |
10424 | ||
10425 | case RELAX_IMMED: | |
10426 | case RELAX_IMMED_STEP1: | |
10427 | case RELAX_IMMED_STEP2: | |
b81bf389 | 10428 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
10429 | /* Place the immediate. */ |
10430 | convert_frag_immed | |
10431 | (sec, fragp, | |
10432 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
10433 | fmt, slot); | |
10434 | break; | |
10435 | ||
10436 | default: | |
10437 | /* This is OK because some slots could have | |
10438 | relaxations and others have none. */ | |
10439 | break; | |
10440 | } | |
10441 | } | |
10442 | break; | |
10443 | ||
10444 | case RELAX_UNREACHABLE: | |
10445 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
10446 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
10447 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
10448 | frag_wane (fragp); | |
e0001a05 NC |
10449 | break; |
10450 | ||
43cd72b9 BW |
10451 | case RELAX_MAYBE_UNREACHABLE: |
10452 | case RELAX_MAYBE_DESIRE_ALIGN: | |
10453 | frag_wane (fragp); | |
e0001a05 NC |
10454 | break; |
10455 | ||
43cd72b9 BW |
10456 | case RELAX_FILL_NOP: |
10457 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
10458 | break; |
10459 | ||
10460 | case RELAX_LITERAL_NR: | |
10461 | if (use_literal_section) | |
10462 | { | |
10463 | /* This should have been handled during relaxation. When | |
10464 | relaxing a code segment, literals sometimes need to be | |
10465 | added to the corresponding literal segment. If that | |
10466 | literal segment has already been relaxed, then we end up | |
10467 | in this situation. Marking the literal segments as data | |
10468 | would make this happen less often (since GAS always relaxes | |
10469 | code before data), but we could still get into trouble if | |
10470 | there are instructions in a segment that is not marked as | |
10471 | containing code. Until we can implement a better solution, | |
10472 | cheat and adjust the addresses of all the following frags. | |
10473 | This could break subsequent alignments, but the linker's | |
10474 | literal coalescing will do that anyway. */ | |
10475 | ||
10476 | fragS *f; | |
10477 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9c2799c2 | 10478 | gas_assert (fragp->tc_frag_data.unreported_expansion == 4); |
e0001a05 NC |
10479 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); |
10480 | fragp->fr_var -= 4; | |
10481 | fragp->fr_fix += 4; | |
10482 | for (f = fragp->fr_next; f; f = f->fr_next) | |
10483 | f->fr_address += 4; | |
10484 | } | |
10485 | else | |
10486 | as_bad (_("invalid relaxation fragment result")); | |
10487 | break; | |
a82c7d90 DW |
10488 | |
10489 | case RELAX_TRAMPOLINE: | |
10490 | break; | |
e0001a05 NC |
10491 | } |
10492 | ||
10493 | fragp->fr_var = 0; | |
10494 | new_logical_line (file_name, line); | |
10495 | } | |
10496 | ||
10497 | ||
7fa3d080 BW |
10498 | static void |
10499 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
10500 | { |
10501 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
10502 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
10503 | addressT aligned_address; | |
d77b99c9 BW |
10504 | offsetT fill_size; |
10505 | int nop, nop_count; | |
e0001a05 NC |
10506 | |
10507 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
10508 | fragp->fr_fix); | |
10509 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
10510 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
10511 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
10512 | ||
d77b99c9 | 10513 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 10514 | { |
d77b99c9 BW |
10515 | int nop_size; |
10516 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
10517 | |
10518 | assemble_nop (nop_size, nop_buf); | |
10519 | nop_buf += nop_size; | |
10520 | } | |
10521 | ||
10522 | fragp->fr_fix += fill_size; | |
10523 | fragp->fr_var -= fill_size; | |
10524 | } | |
10525 | ||
10526 | ||
10527 | static void | |
7fa3d080 | 10528 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 10529 | { |
43cd72b9 | 10530 | TInsn tinsn, single_target; |
84b08ed9 | 10531 | int size, old_size, diff; |
e0001a05 NC |
10532 | offsetT frag_offset; |
10533 | ||
9c2799c2 | 10534 | gas_assert (slot == 0); |
43cd72b9 BW |
10535 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); |
10536 | ||
b5e4a23d | 10537 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 | 10538 | { |
9c2799c2 | 10539 | gas_assert (fragP->tc_frag_data.text_expansion[0] == 1 |
43cd72b9 BW |
10540 | || fragP->tc_frag_data.text_expansion[0] == 0); |
10541 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
10542 | fmt, slot); | |
10543 | return; | |
10544 | } | |
10545 | ||
10546 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
10547 | { |
10548 | /* No conversion. */ | |
10549 | fragP->fr_var = 0; | |
10550 | return; | |
10551 | } | |
10552 | ||
9c2799c2 | 10553 | gas_assert (fragP->fr_opcode != NULL); |
e0001a05 | 10554 | |
43cd72b9 BW |
10555 | /* Frags in this relaxation state should only contain |
10556 | single instruction bundles. */ | |
10557 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
10558 | |
10559 | /* Just convert it to a wide form.... */ | |
10560 | size = 0; | |
43cd72b9 | 10561 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
10562 | |
10563 | tinsn_init (&single_target); | |
10564 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
10565 | ||
84b08ed9 | 10566 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
10567 | { |
10568 | as_bad (_("unable to widen instruction")); | |
10569 | return; | |
10570 | } | |
10571 | ||
10572 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
10573 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
10574 | frag_offset, TRUE); | |
e0001a05 NC |
10575 | |
10576 | diff = size - old_size; | |
9c2799c2 NC |
10577 | gas_assert (diff >= 0); |
10578 | gas_assert (diff <= fragP->fr_var); | |
e0001a05 NC |
10579 | fragP->fr_var -= diff; |
10580 | fragP->fr_fix += diff; | |
10581 | ||
10582 | /* clean it up */ | |
10583 | fragP->fr_var = 0; | |
10584 | } | |
10585 | ||
10586 | ||
10587 | static void | |
7fa3d080 | 10588 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
10589 | { |
10590 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
10591 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 10592 | gas_assert ((unsigned) size == (fragP->fr_next->fr_address |
43cd72b9 BW |
10593 | - fragP->fr_address - fragP->fr_fix)); |
10594 | if (size == 0) | |
10595 | { | |
10596 | /* No conversion. */ | |
10597 | fragP->fr_var = 0; | |
10598 | return; | |
10599 | } | |
10600 | assemble_nop (size, loc); | |
10601 | fragP->tc_frag_data.is_insn = TRUE; | |
10602 | fragP->fr_var -= size; | |
10603 | fragP->fr_fix += size; | |
10604 | frag_wane (fragP); | |
10605 | } | |
10606 | ||
10607 | ||
7fa3d080 BW |
10608 | static fixS *fix_new_exp_in_seg |
10609 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
10610 | bfd_reloc_code_real_type); | |
10611 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
10612 | ||
43cd72b9 | 10613 | static void |
7fa3d080 BW |
10614 | convert_frag_immed (segT segP, |
10615 | fragS *fragP, | |
10616 | int min_steps, | |
10617 | xtensa_format fmt, | |
10618 | int slot) | |
e0001a05 NC |
10619 | { |
10620 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 10621 | TInsn orig_tinsn; |
e0001a05 | 10622 | bfd_boolean expanded = FALSE; |
e0001a05 | 10623 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 10624 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 | 10625 | xtensa_isa isa = xtensa_default_isa; |
def13efb | 10626 | bfd_boolean from_wide_insn = FALSE; |
43cd72b9 BW |
10627 | int bytes; |
10628 | bfd_boolean is_loop; | |
e0001a05 | 10629 | |
9c2799c2 | 10630 | gas_assert (fr_opcode != NULL); |
e0001a05 | 10631 | |
b5e4a23d | 10632 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 10633 | |
b5e4a23d | 10634 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 10635 | if (cur_vinsn.num_slots > 1) |
def13efb | 10636 | from_wide_insn = TRUE; |
e0001a05 | 10637 | |
b5e4a23d | 10638 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
10639 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
10640 | ||
10641 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 10642 | |
b08b5071 | 10643 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 10644 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
10645 | |
10646 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
10647 | { | |
10648 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
10649 | bytes = xtensa_format_length (isa, fmt); |
10650 | if (bytes >= 4) | |
10651 | { | |
b5e4a23d BW |
10652 | cur_vinsn.slots[slot].opcode = |
10653 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
10654 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
10655 | } |
10656 | else | |
10657 | { | |
10658 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9c2799c2 | 10659 | gas_assert (bytes == 2 || bytes == 3); |
b5e4a23d | 10660 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
10661 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
10662 | } | |
e7da6241 | 10663 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 10664 | xtensa_insnbuf_to_chars |
b5e4a23d | 10665 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
10666 | fragP->fr_var = 0; |
10667 | } | |
7c834684 | 10668 | else |
e0001a05 | 10669 | { |
43cd72b9 BW |
10670 | /* Here is the fun stuff: Get the immediate field from this |
10671 | instruction. If it fits, we're done. If not, find the next | |
10672 | instruction sequence that fits. */ | |
10673 | ||
e0001a05 NC |
10674 | IStack istack; |
10675 | int i; | |
10676 | symbolS *lit_sym = NULL; | |
10677 | int total_size = 0; | |
43cd72b9 | 10678 | int target_offset = 0; |
e0001a05 NC |
10679 | int old_size; |
10680 | int diff; | |
10681 | symbolS *gen_label = NULL; | |
10682 | offsetT frag_offset; | |
43cd72b9 | 10683 | bfd_boolean first = TRUE; |
e0001a05 | 10684 | |
43cd72b9 | 10685 | /* It does not fit. Find something that does and |
e0001a05 | 10686 | convert immediately. */ |
43cd72b9 | 10687 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 10688 | istack_init (&istack); |
43cd72b9 | 10689 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
10690 | segP, fragP, frag_offset, min_steps, 0); |
10691 | ||
43cd72b9 | 10692 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
10693 | |
10694 | /* Assemble this right inline. */ | |
10695 | ||
10696 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 10697 | target_offset = 0; |
e0001a05 NC |
10698 | for (i = 0; i < istack.ninsn; i++) |
10699 | { | |
43cd72b9 | 10700 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
10701 | fragS *lit_frag; |
10702 | ||
43cd72b9 | 10703 | switch (tinsn->insn_type) |
e0001a05 NC |
10704 | { |
10705 | case ITYPE_LITERAL: | |
10706 | if (lit_sym != NULL) | |
10707 | as_bad (_("multiple literals in expansion")); | |
10708 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 10709 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
10710 | if (lit_frag == NULL) |
10711 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 10712 | if (tinsn->ntok != 1) |
e0001a05 NC |
10713 | as_bad (_("number of literal tokens != 1")); |
10714 | ||
10715 | /* Set the literal symbol and add a fixup. */ | |
10716 | lit_sym = lit_frag->fr_symbol; | |
10717 | break; | |
10718 | ||
10719 | case ITYPE_LABEL: | |
43cd72b9 BW |
10720 | if (align_targets && !is_loop) |
10721 | { | |
10722 | fragS *unreach = fragP->fr_next; | |
10723 | while (!(unreach->fr_type == rs_machine_dependent | |
10724 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
10725 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
10726 | { | |
10727 | unreach = unreach->fr_next; | |
10728 | } | |
10729 | ||
9c2799c2 | 10730 | gas_assert (unreach->fr_type == rs_machine_dependent |
43cd72b9 BW |
10731 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE |
10732 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
10733 | ||
10734 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
10735 | } | |
9c2799c2 | 10736 | gas_assert (gen_label == NULL); |
e0001a05 | 10737 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, |
43cd72b9 BW |
10738 | fr_opcode - fragP->fr_literal |
10739 | + target_offset, fragP); | |
e0001a05 NC |
10740 | break; |
10741 | ||
10742 | case ITYPE_INSN: | |
def13efb | 10743 | if (first && from_wide_insn) |
43cd72b9 BW |
10744 | { |
10745 | target_offset += xtensa_format_length (isa, fmt); | |
10746 | first = FALSE; | |
10747 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
10748 | target_offset += xg_get_single_size (tinsn->opcode); | |
10749 | } | |
10750 | else | |
10751 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
10752 | break; |
10753 | } | |
10754 | } | |
10755 | ||
10756 | total_size = 0; | |
43cd72b9 | 10757 | first = TRUE; |
e0001a05 NC |
10758 | for (i = 0; i < istack.ninsn; i++) |
10759 | { | |
43cd72b9 | 10760 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
10761 | fragS *lit_frag; |
10762 | int size; | |
10763 | segT target_seg; | |
43cd72b9 | 10764 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 10765 | |
43cd72b9 | 10766 | switch (tinsn->insn_type) |
e0001a05 NC |
10767 | { |
10768 | case ITYPE_LITERAL: | |
43cd72b9 BW |
10769 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
10770 | /* Already checked. */ | |
9c2799c2 NC |
10771 | gas_assert (lit_frag != NULL); |
10772 | gas_assert (lit_sym != NULL); | |
10773 | gas_assert (tinsn->ntok == 1); | |
43cd72b9 | 10774 | /* Add a fixup. */ |
e0001a05 | 10775 | target_seg = S_GET_SEGMENT (lit_sym); |
9c2799c2 | 10776 | gas_assert (target_seg); |
28dbbc02 | 10777 | reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE); |
e0001a05 | 10778 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 10779 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
10780 | break; |
10781 | ||
10782 | case ITYPE_LABEL: | |
10783 | break; | |
10784 | ||
10785 | case ITYPE_INSN: | |
43cd72b9 BW |
10786 | xg_resolve_labels (tinsn, gen_label); |
10787 | xg_resolve_literals (tinsn, lit_sym); | |
def13efb | 10788 | if (from_wide_insn && first) |
43cd72b9 BW |
10789 | { |
10790 | first = FALSE; | |
10791 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
10792 | { | |
b5e4a23d | 10793 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
10794 | } |
10795 | else | |
10796 | { | |
b5e4a23d | 10797 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 10798 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 10799 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 10800 | } |
b5e4a23d BW |
10801 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
10802 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 10803 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
10804 | fragP->tc_frag_data.is_insn = TRUE; |
10805 | size = xtensa_format_length (isa, fmt); | |
10806 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
10807 | { | |
43cd72b9 | 10808 | xg_emit_insn_to_buf |
b2d179be | 10809 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
10810 | immed_instr - fragP->fr_literal + size, TRUE); |
10811 | size += xg_get_single_size (tinsn->opcode); | |
10812 | } | |
10813 | } | |
10814 | else | |
10815 | { | |
43cd72b9 | 10816 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 10817 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 10818 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 10819 | } |
e0001a05 | 10820 | immed_instr += size; |
43cd72b9 | 10821 | total_size += size; |
e0001a05 NC |
10822 | break; |
10823 | } | |
10824 | } | |
10825 | ||
10826 | diff = total_size - old_size; | |
9c2799c2 | 10827 | gas_assert (diff >= 0); |
e0001a05 NC |
10828 | if (diff != 0) |
10829 | expanded = TRUE; | |
9c2799c2 | 10830 | gas_assert (diff <= fragP->fr_var); |
e0001a05 NC |
10831 | fragP->fr_var -= diff; |
10832 | fragP->fr_fix += diff; | |
10833 | } | |
10834 | ||
e0001a05 | 10835 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 10836 | if (is_loop) |
e0001a05 NC |
10837 | { |
10838 | symbolS *sym; | |
43cd72b9 | 10839 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
10840 | if (sym != NULL && !S_IS_DEFINED (sym)) |
10841 | { | |
10842 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
10843 | return; | |
10844 | } | |
43cd72b9 | 10845 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
10846 | if (sym != NULL && !S_IS_DEFINED (sym)) |
10847 | { | |
10848 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
10849 | return; | |
10850 | } | |
10851 | } | |
10852 | ||
43cd72b9 BW |
10853 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
10854 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 10855 | |
43cd72b9 | 10856 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
10857 | { |
10858 | /* Add an expansion note on the expanded instruction. */ | |
10859 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 10860 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 10861 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
10862 | } |
10863 | } | |
10864 | ||
10865 | ||
10866 | /* Add a new fix expression into the desired segment. We have to | |
10867 | switch to that segment to do this. */ | |
10868 | ||
10869 | static fixS * | |
7fa3d080 BW |
10870 | fix_new_exp_in_seg (segT new_seg, |
10871 | subsegT new_subseg, | |
10872 | fragS *frag, | |
10873 | int where, | |
10874 | int size, | |
10875 | expressionS *exp, | |
10876 | int pcrel, | |
10877 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
10878 | { |
10879 | fixS *new_fix; | |
10880 | segT seg = now_seg; | |
10881 | subsegT subseg = now_subseg; | |
43cd72b9 | 10882 | |
9c2799c2 | 10883 | gas_assert (new_seg != 0); |
e0001a05 NC |
10884 | subseg_set (new_seg, new_subseg); |
10885 | ||
e0001a05 NC |
10886 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
10887 | subseg_set (seg, subseg); | |
10888 | return new_fix; | |
10889 | } | |
10890 | ||
10891 | ||
43cd72b9 BW |
10892 | /* Relax a loop instruction so that it can span loop >256 bytes. |
10893 | ||
10894 | loop as, .L1 | |
10895 | .L0: | |
10896 | rsr as, LEND | |
10897 | wsr as, LBEG | |
10898 | addi as, as, lo8 (label-.L1) | |
10899 | addmi as, as, mid8 (label-.L1) | |
10900 | wsr as, LEND | |
10901 | isync | |
10902 | rsr as, LCOUNT | |
10903 | addi as, as, 1 | |
10904 | .L1: | |
10905 | <<body>> | |
10906 | label: | |
10907 | */ | |
e0001a05 NC |
10908 | |
10909 | static void | |
7fa3d080 | 10910 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
10911 | { |
10912 | TInsn loop_insn; | |
10913 | TInsn addi_insn; | |
10914 | TInsn addmi_insn; | |
10915 | unsigned long target; | |
10916 | static xtensa_insnbuf insnbuf = NULL; | |
10917 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
10918 | xtensa_isa isa = xtensa_default_isa; | |
10919 | addressT loop_offset; | |
10920 | addressT addi_offset = 9; | |
10921 | addressT addmi_offset = 12; | |
43cd72b9 | 10922 | fragS *next_fragP; |
d77b99c9 | 10923 | int target_count; |
e0001a05 NC |
10924 | |
10925 | if (!insnbuf) | |
10926 | insnbuf = xtensa_insnbuf_alloc (isa); | |
10927 | ||
10928 | /* Get the loop offset. */ | |
43cd72b9 | 10929 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 10930 | |
43cd72b9 BW |
10931 | /* Validate that there really is a LOOP at the loop_offset. Because |
10932 | loops are not bundleable, we can assume that the instruction will be | |
10933 | in slot 0. */ | |
10934 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
10935 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
10936 | ||
9c2799c2 | 10937 | gas_assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); |
e0001a05 NC |
10938 | addi_offset += loop_offset; |
10939 | addmi_offset += loop_offset; | |
10940 | ||
9c2799c2 | 10941 | gas_assert (tinsn->ntok == 2); |
b08b5071 BW |
10942 | if (tinsn->tok[1].X_op == O_constant) |
10943 | target = tinsn->tok[1].X_add_number; | |
10944 | else if (tinsn->tok[1].X_op == O_symbol) | |
10945 | { | |
10946 | /* Find the fragment. */ | |
10947 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9c2799c2 | 10948 | gas_assert (S_GET_SEGMENT (sym) == segP |
b08b5071 BW |
10949 | || S_GET_SEGMENT (sym) == absolute_section); |
10950 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
10951 | } | |
10952 | else | |
10953 | { | |
10954 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
10955 | target = 0; | |
10956 | } | |
e0001a05 | 10957 | |
e0001a05 NC |
10958 | loop_length = target - (fragP->fr_address + fragP->fr_fix); |
10959 | loop_length_hi = loop_length & ~0x0ff; | |
10960 | loop_length_lo = loop_length & 0x0ff; | |
10961 | if (loop_length_lo >= 128) | |
10962 | { | |
10963 | loop_length_lo -= 256; | |
10964 | loop_length_hi += 256; | |
10965 | } | |
10966 | ||
43cd72b9 | 10967 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
10968 | 32512. If the loop is larger than that, then we just fail. */ |
10969 | if (loop_length_hi > 32512) | |
10970 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10971 | _("loop too long for LOOP instruction")); | |
10972 | ||
43cd72b9 | 10973 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
9c2799c2 | 10974 | gas_assert (addi_insn.opcode == xtensa_addi_opcode); |
e0001a05 | 10975 | |
43cd72b9 | 10976 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
9c2799c2 | 10977 | gas_assert (addmi_insn.opcode == xtensa_addmi_opcode); |
e0001a05 NC |
10978 | |
10979 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
10980 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 10981 | |
e0001a05 | 10982 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
10983 | xtensa_insnbuf_to_chars |
10984 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
10985 | |
10986 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
10987 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
10988 | xtensa_insnbuf_to_chars |
10989 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
10990 | |
10991 | /* Walk through all of the frags from here to the loop end | |
10992 | and mark them as no_transform to keep them from being modified | |
10993 | by the linker. If we ever have a relocation for the | |
10994 | addi/addmi of the difference of two symbols we can remove this. */ | |
10995 | ||
10996 | target_count = 0; | |
10997 | for (next_fragP = fragP; next_fragP != NULL; | |
10998 | next_fragP = next_fragP->fr_next) | |
10999 | { | |
b08b5071 | 11000 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
11001 | if (next_fragP->tc_frag_data.is_loop_target) |
11002 | target_count++; | |
11003 | if (target_count == 2) | |
11004 | break; | |
11005 | } | |
e0001a05 NC |
11006 | } |
11007 | ||
b08b5071 BW |
11008 | \f |
11009 | /* A map that keeps information on a per-subsegment basis. This is | |
11010 | maintained during initial assembly, but is invalid once the | |
11011 | subsegments are smashed together. I.E., it cannot be used during | |
11012 | the relaxation. */ | |
e0001a05 | 11013 | |
b08b5071 | 11014 | typedef struct subseg_map_struct |
e0001a05 | 11015 | { |
b08b5071 BW |
11016 | /* the key */ |
11017 | segT seg; | |
11018 | subsegT subseg; | |
e0001a05 | 11019 | |
b08b5071 BW |
11020 | /* the data */ |
11021 | unsigned flags; | |
11022 | float total_freq; /* fall-through + branch target frequency */ | |
11023 | float target_freq; /* branch target frequency alone */ | |
11024 | ||
11025 | struct subseg_map_struct *next; | |
11026 | } subseg_map; | |
e0001a05 | 11027 | |
e0001a05 | 11028 | |
e0001a05 NC |
11029 | static subseg_map *sseg_map = NULL; |
11030 | ||
43cd72b9 | 11031 | static subseg_map * |
7fa3d080 | 11032 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
11033 | { |
11034 | subseg_map *subseg_e; | |
11035 | ||
11036 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 11037 | { |
43cd72b9 | 11038 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 11039 | break; |
e0001a05 | 11040 | } |
b08b5071 BW |
11041 | return subseg_e; |
11042 | } | |
11043 | ||
11044 | ||
11045 | static subseg_map * | |
11046 | add_subseg_info (segT seg, subsegT subseg) | |
11047 | { | |
325801bd | 11048 | subseg_map *subseg_e = XNEW (subseg_map); |
43cd72b9 BW |
11049 | memset (subseg_e, 0, sizeof (subseg_map)); |
11050 | subseg_e->seg = seg; | |
11051 | subseg_e->subseg = subseg; | |
11052 | subseg_e->flags = 0; | |
11053 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
11054 | subseg_e->target_freq = 1.0; |
11055 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
11056 | subseg_e->next = sseg_map; |
11057 | sseg_map = subseg_e; | |
43cd72b9 BW |
11058 | return subseg_e; |
11059 | } | |
e0001a05 | 11060 | |
7fa3d080 BW |
11061 | |
11062 | static unsigned | |
11063 | get_last_insn_flags (segT seg, subsegT subseg) | |
11064 | { | |
11065 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
11066 | if (subseg_e) |
11067 | return subseg_e->flags; | |
11068 | return 0; | |
7fa3d080 BW |
11069 | } |
11070 | ||
11071 | ||
43cd72b9 | 11072 | static void |
7fa3d080 BW |
11073 | set_last_insn_flags (segT seg, |
11074 | subsegT subseg, | |
11075 | unsigned fl, | |
11076 | bfd_boolean val) | |
43cd72b9 BW |
11077 | { |
11078 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
11079 | if (! subseg_e) |
11080 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
11081 | if (val) |
11082 | subseg_e->flags |= fl; | |
11083 | else | |
11084 | subseg_e->flags &= ~fl; | |
11085 | } | |
11086 | ||
b08b5071 BW |
11087 | |
11088 | static float | |
11089 | get_subseg_total_freq (segT seg, subsegT subseg) | |
11090 | { | |
11091 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
11092 | if (subseg_e) | |
11093 | return subseg_e->total_freq; | |
11094 | return 1.0; | |
11095 | } | |
11096 | ||
11097 | ||
11098 | static float | |
11099 | get_subseg_target_freq (segT seg, subsegT subseg) | |
11100 | { | |
11101 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
11102 | if (subseg_e) | |
11103 | return subseg_e->target_freq; | |
11104 | return 1.0; | |
11105 | } | |
11106 | ||
11107 | ||
11108 | static void | |
11109 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
11110 | { | |
11111 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
11112 | if (! subseg_e) | |
11113 | subseg_e = add_subseg_info (seg, subseg); | |
11114 | subseg_e->total_freq = total_f; | |
11115 | subseg_e->target_freq = target_f; | |
11116 | } | |
11117 | ||
e0001a05 NC |
11118 | \f |
11119 | /* Segment Lists and emit_state Stuff. */ | |
11120 | ||
e0001a05 | 11121 | static void |
7fa3d080 | 11122 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
11123 | { |
11124 | head = head->next; | |
11125 | while (head) | |
11126 | { | |
11127 | segT literal_section = head->seg; | |
11128 | ||
11129 | /* Move the literal section to the front of the section list. */ | |
9c2799c2 | 11130 | gas_assert (literal_section); |
69852798 AM |
11131 | if (literal_section != stdoutput->sections) |
11132 | { | |
11133 | bfd_section_list_remove (stdoutput, literal_section); | |
11134 | bfd_section_list_prepend (stdoutput, literal_section); | |
11135 | } | |
e0001a05 NC |
11136 | head = head->next; |
11137 | } | |
11138 | } | |
11139 | ||
11140 | ||
7fa3d080 BW |
11141 | static void mark_literal_frags (seg_list *); |
11142 | ||
947fa914 MF |
11143 | static void |
11144 | xg_promote_candidate_litpool (struct litpool_seg *lps, | |
11145 | struct litpool_frag *lp) | |
11146 | { | |
11147 | fragS *poolbeg; | |
11148 | fragS *poolend; | |
11149 | symbolS *lsym; | |
11150 | char label[10 + 2 * sizeof (fragS *)]; | |
11151 | ||
11152 | poolbeg = lp->fragP; | |
11153 | lp->priority = 1; | |
11154 | poolbeg->fr_subtype = RELAX_LITERAL_POOL_BEGIN; | |
11155 | poolend = poolbeg->fr_next; | |
11156 | gas_assert (poolend->fr_type == rs_machine_dependent && | |
11157 | poolend->fr_subtype == RELAX_LITERAL_POOL_END); | |
11158 | /* Create a local symbol pointing to the | |
11159 | end of the pool. */ | |
11160 | sprintf (label, ".L0_LT_%p", poolbeg); | |
11161 | lsym = (symbolS *)local_symbol_make (label, lps->seg, | |
11162 | 0, poolend); | |
11163 | poolbeg->fr_symbol = lsym; | |
11164 | /* Rest is done in xtensa_relax_frag. */ | |
11165 | } | |
11166 | ||
7fa3d080 BW |
11167 | static void |
11168 | xtensa_move_literals (void) | |
e0001a05 NC |
11169 | { |
11170 | seg_list *segment; | |
11171 | frchainS *frchain_from, *frchain_to; | |
87975d2a | 11172 | fragS *search_frag, *next_frag, *literal_pool, *insert_after; |
e0001a05 NC |
11173 | fragS **frag_splice; |
11174 | emit_state state; | |
11175 | segT dest_seg; | |
11176 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 11177 | sym_list *lit; |
b46824bd | 11178 | struct litpool_seg *lps; |
4111950f MF |
11179 | const char *init_name = INIT_SECTION_NAME; |
11180 | const char *fini_name = FINI_SECTION_NAME; | |
11181 | int init_name_len = strlen(init_name); | |
11182 | int fini_name_len = strlen(fini_name); | |
e0001a05 | 11183 | |
a7877748 | 11184 | mark_literal_frags (literal_head->next); |
e0001a05 NC |
11185 | |
11186 | if (use_literal_section) | |
11187 | return; | |
11188 | ||
b46824bd MF |
11189 | /* Assign addresses (rough estimates) to the potential literal pool locations |
11190 | and create new ones if the gaps are too large. */ | |
11191 | ||
11192 | for (lps = litpool_seg_list.next; lps; lps = lps->next) | |
11193 | { | |
11194 | frchainS *frchP = seg_info (lps->seg)->frchainP; | |
11195 | struct litpool_frag *lpf = lps->frag_list.next; | |
11196 | addressT addr = 0; | |
11197 | ||
11198 | for ( ; frchP; frchP = frchP->frch_next) | |
11199 | { | |
11200 | fragS *fragP; | |
11201 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
11202 | { | |
11203 | if (lpf && fragP == lpf->fragP) | |
11204 | { | |
11205 | gas_assert(fragP->fr_type == rs_machine_dependent && | |
11206 | (fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN || | |
11207 | fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)); | |
11208 | /* Found a litpool location. */ | |
11209 | lpf->addr = addr; | |
11210 | lpf = lpf->next; | |
11211 | } | |
11212 | if (fragP->fr_type == rs_machine_dependent && | |
11213 | fragP->fr_subtype == RELAX_SLOTS) | |
11214 | { | |
11215 | int slot; | |
11216 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
11217 | { | |
11218 | if (fragP->tc_frag_data.literal_frags[slot]) | |
11219 | { | |
11220 | /* L32R; point its literal to the nearest litpool | |
11221 | preferring non-"candidate" positions to avoid | |
11222 | the jump-around. */ | |
11223 | fragS *litfrag = fragP->tc_frag_data.literal_frags[slot]; | |
11224 | struct litpool_frag *lp = lpf->prev; | |
11225 | if (!lp->fragP) | |
11226 | { | |
11227 | break; | |
11228 | } | |
11229 | while (lp->fragP->fr_subtype == | |
11230 | RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
11231 | { | |
11232 | lp = lp->prev; | |
11233 | if (lp->fragP == NULL) | |
11234 | { | |
11235 | /* End of list; have to bite the bullet. | |
11236 | Take the nearest. */ | |
11237 | lp = lpf->prev; | |
11238 | break; | |
11239 | } | |
11240 | /* Does it (conservatively) reach? */ | |
11241 | if (addr - lp->addr <= 128 * 1024) | |
11242 | { | |
11243 | if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN) | |
11244 | { | |
11245 | /* Found a good one. */ | |
11246 | break; | |
11247 | } | |
11248 | else if (lp->prev->fragP && | |
11249 | addr - lp->prev->addr > 128 * 1024) | |
11250 | { | |
11251 | /* This is still a "candidate" but the next one | |
11252 | will be too far away, so revert to the nearest | |
11253 | one, convert it and add the jump around. */ | |
b46824bd | 11254 | lp = lpf->prev; |
947fa914 | 11255 | break; |
b46824bd MF |
11256 | } |
11257 | } | |
11258 | } | |
947fa914 MF |
11259 | |
11260 | /* Convert candidate and add the jump around. */ | |
11261 | if (lp->fragP->fr_subtype == | |
11262 | RELAX_LITERAL_POOL_CANDIDATE_BEGIN) | |
11263 | xg_promote_candidate_litpool (lps, lp); | |
11264 | ||
b46824bd MF |
11265 | if (! litfrag->tc_frag_data.literal_frag) |
11266 | { | |
11267 | /* Take earliest use of this literal to avoid | |
11268 | forward refs. */ | |
11269 | litfrag->tc_frag_data.literal_frag = lp->fragP; | |
11270 | } | |
11271 | } | |
11272 | } | |
11273 | } | |
11274 | addr += fragP->fr_fix; | |
11275 | if (fragP->fr_type == rs_fill) | |
11276 | addr += fragP->fr_offset; | |
11277 | } | |
11278 | } | |
11279 | } | |
11280 | ||
74869ac7 | 11281 | for (segment = literal_head->next; segment; segment = segment->next) |
e0001a05 | 11282 | { |
4111950f MF |
11283 | const char *seg_name = segment_name (segment->seg); |
11284 | ||
74869ac7 | 11285 | /* Keep the literals for .init and .fini in separate sections. */ |
4111950f MF |
11286 | if ((!memcmp (seg_name, init_name, init_name_len) && |
11287 | !strcmp (seg_name + init_name_len, ".literal")) || | |
11288 | (!memcmp (seg_name, fini_name, fini_name_len) && | |
11289 | !strcmp (seg_name + fini_name_len, ".literal"))) | |
74869ac7 BW |
11290 | continue; |
11291 | ||
e0001a05 NC |
11292 | frchain_from = seg_info (segment->seg)->frchainP; |
11293 | search_frag = frchain_from->frch_root; | |
11294 | literal_pool = NULL; | |
11295 | frchain_to = NULL; | |
11296 | frag_splice = &(frchain_from->frch_root); | |
11297 | ||
4de0562a | 11298 | while (search_frag && !search_frag->tc_frag_data.literal_frag) |
e0001a05 | 11299 | { |
9c2799c2 | 11300 | gas_assert (search_frag->fr_fix == 0 |
e0001a05 NC |
11301 | || search_frag->fr_type == rs_align); |
11302 | search_frag = search_frag->fr_next; | |
11303 | } | |
11304 | ||
4de0562a MF |
11305 | if (!search_frag) |
11306 | { | |
11307 | search_frag = frchain_from->frch_root; | |
11308 | as_bad_where (search_frag->fr_file, search_frag->fr_line, | |
11309 | _("literal pool location required for text-section-literals; specify with .literal_position")); | |
11310 | continue; | |
11311 | } | |
11312 | ||
9c2799c2 | 11313 | gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype |
e0001a05 NC |
11314 | == RELAX_LITERAL_POOL_BEGIN); |
11315 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
11316 | ||
11317 | /* Make sure that all the frags in this series are closed, and | |
11318 | that there is at least one left over of zero-size. This | |
11319 | prevents us from making a segment with an frchain without any | |
11320 | frags in it. */ | |
11321 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11322 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11323 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); |
43cd72b9 | 11324 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11325 | |
43cd72b9 | 11326 | while (search_frag != frag_now) |
e0001a05 NC |
11327 | { |
11328 | next_frag = search_frag->fr_next; | |
e0001a05 NC |
11329 | if (search_frag->tc_frag_data.literal_frag) |
11330 | { | |
11331 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9c2799c2 | 11332 | gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); |
dd49a749 | 11333 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9c2799c2 | 11334 | gas_assert (frchain_to); |
e0001a05 | 11335 | } |
b46824bd MF |
11336 | |
11337 | if (search_frag->fr_type == rs_fill && search_frag->fr_fix == 0) | |
11338 | { | |
11339 | /* Skip empty fill frags. */ | |
11340 | *frag_splice = next_frag; | |
11341 | search_frag = next_frag; | |
11342 | continue; | |
11343 | } | |
11344 | ||
11345 | if (search_frag->fr_type == rs_align) | |
11346 | { | |
11347 | /* Skip alignment frags, because the pool as a whole will be | |
11348 | aligned if used, and we don't want to force alignment if the | |
11349 | pool is unused. */ | |
11350 | *frag_splice = next_frag; | |
11351 | search_frag = next_frag; | |
11352 | continue; | |
11353 | } | |
11354 | ||
11355 | /* First, move the frag out of the literal section and | |
11356 | to the appropriate place. */ | |
11357 | ||
33eaf5de | 11358 | /* Insert an alignment frag at start of pool. */ |
b46824bd MF |
11359 | if (literal_pool->fr_next->fr_type == rs_machine_dependent && |
11360 | literal_pool->fr_next->fr_subtype == RELAX_LITERAL_POOL_END) | |
11361 | { | |
11362 | segT pool_seg = literal_pool->fr_next->tc_frag_data.lit_seg; | |
11363 | emit_state prev_state; | |
11364 | fragS *prev_frag; | |
11365 | fragS *align_frag; | |
11366 | xtensa_switch_section_emit_state (&prev_state, pool_seg, 0); | |
11367 | prev_frag = frag_now; | |
11368 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
11369 | align_frag = frag_now; | |
11370 | frag_align (2, 0, 0); | |
11371 | /* Splice it into the right place. */ | |
11372 | prev_frag->fr_next = align_frag->fr_next; | |
11373 | align_frag->fr_next = literal_pool->fr_next; | |
11374 | literal_pool->fr_next = align_frag; | |
11375 | /* Insert after this one. */ | |
11376 | literal_pool->tc_frag_data.literal_frag = align_frag; | |
11377 | xtensa_restore_emit_state (&prev_state); | |
11378 | } | |
c48aaca0 | 11379 | insert_after = literal_pool->tc_frag_data.literal_frag; |
dd49a749 | 11380 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
b46824bd MF |
11381 | /* Skip align frag. */ |
11382 | if (insert_after->fr_next->fr_type == rs_align) | |
11383 | { | |
11384 | insert_after = insert_after->fr_next; | |
11385 | } | |
43cd72b9 | 11386 | |
e0001a05 NC |
11387 | *frag_splice = next_frag; |
11388 | search_frag->fr_next = insert_after->fr_next; | |
11389 | insert_after->fr_next = search_frag; | |
11390 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
c48aaca0 | 11391 | literal_pool->tc_frag_data.literal_frag = search_frag; |
e0001a05 NC |
11392 | |
11393 | /* Now move any fixups associated with this frag to the | |
11394 | right section. */ | |
11395 | fix = frchain_from->fix_root; | |
11396 | fix_splice = &(frchain_from->fix_root); | |
11397 | while (fix) | |
11398 | { | |
11399 | next_fix = fix->fx_next; | |
11400 | if (fix->fx_frag == search_frag) | |
11401 | { | |
11402 | *fix_splice = next_fix; | |
11403 | fix->fx_next = frchain_to->fix_root; | |
11404 | frchain_to->fix_root = fix; | |
11405 | if (frchain_to->fix_tail == NULL) | |
11406 | frchain_to->fix_tail = fix; | |
11407 | } | |
11408 | else | |
11409 | fix_splice = &(fix->fx_next); | |
11410 | fix = next_fix; | |
11411 | } | |
11412 | search_frag = next_frag; | |
11413 | } | |
11414 | ||
11415 | if (frchain_from->fix_root != NULL) | |
11416 | { | |
11417 | frchain_from = seg_info (segment->seg)->frchainP; | |
11418 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
11419 | ||
9c2799c2 | 11420 | gas_assert (frchain_from->fix_root == NULL); |
e0001a05 NC |
11421 | } |
11422 | frchain_from->fix_tail = NULL; | |
11423 | xtensa_restore_emit_state (&state); | |
e0001a05 NC |
11424 | } |
11425 | ||
82e7541d BW |
11426 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
11427 | for (lit = literal_syms; lit; lit = lit->next) | |
11428 | { | |
11429 | symbolS *lit_sym = lit->sym; | |
91d6fa6a NC |
11430 | segT dseg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; |
11431 | if (dseg) | |
11432 | S_SET_SEGMENT (lit_sym, dseg); | |
82e7541d | 11433 | } |
e0001a05 NC |
11434 | } |
11435 | ||
11436 | ||
a7877748 BW |
11437 | /* Walk over all the frags for segments in a list and mark them as |
11438 | containing literals. As clunky as this is, we can't rely on frag_var | |
11439 | and frag_variant to get called in all situations. */ | |
11440 | ||
11441 | static void | |
7fa3d080 | 11442 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
11443 | { |
11444 | frchainS *frchain_from; | |
11445 | fragS *search_frag; | |
11446 | ||
11447 | while (segment) | |
11448 | { | |
11449 | frchain_from = seg_info (segment->seg)->frchainP; | |
11450 | search_frag = frchain_from->frch_root; | |
c138bc38 | 11451 | while (search_frag) |
a7877748 BW |
11452 | { |
11453 | search_frag->tc_frag_data.is_literal = TRUE; | |
11454 | search_frag = search_frag->fr_next; | |
11455 | } | |
11456 | segment = segment->next; | |
11457 | } | |
11458 | } | |
11459 | ||
11460 | ||
e0001a05 | 11461 | static void |
7fa3d080 | 11462 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
11463 | { |
11464 | /* Move all of the sections in the section list to come | |
11465 | after "after" in the gnu segment list. */ | |
11466 | ||
11467 | head = head->next; | |
11468 | while (head) | |
11469 | { | |
11470 | segT literal_section = head->seg; | |
11471 | ||
11472 | /* Move the literal section after "after". */ | |
9c2799c2 | 11473 | gas_assert (literal_section); |
e0001a05 NC |
11474 | if (literal_section != after) |
11475 | { | |
69852798 AM |
11476 | bfd_section_list_remove (stdoutput, literal_section); |
11477 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
11478 | } |
11479 | ||
11480 | head = head->next; | |
11481 | } | |
11482 | } | |
11483 | ||
11484 | ||
11485 | /* Push all the literal segments to the end of the gnu list. */ | |
11486 | ||
7fa3d080 BW |
11487 | static void |
11488 | xtensa_reorder_segments (void) | |
e0001a05 NC |
11489 | { |
11490 | segT sec; | |
b08b5071 | 11491 | segT last_sec = 0; |
e0001a05 NC |
11492 | int old_count = 0; |
11493 | int new_count = 0; | |
11494 | ||
11495 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
11496 | { |
11497 | last_sec = sec; | |
11498 | old_count++; | |
11499 | } | |
e0001a05 NC |
11500 | |
11501 | /* Now that we have the last section, push all the literal | |
11502 | sections to the end. */ | |
e0001a05 | 11503 | xtensa_reorder_seg_list (literal_head, last_sec); |
e0001a05 NC |
11504 | |
11505 | /* Now perform the final error check. */ | |
11506 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
11507 | new_count++; | |
9c2799c2 | 11508 | gas_assert (new_count == old_count); |
e0001a05 NC |
11509 | } |
11510 | ||
11511 | ||
e0001a05 NC |
11512 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
11513 | correct location. Return a emit_state which can be passed to | |
11514 | xtensa_restore_emit_state to return to current fragment. */ | |
11515 | ||
7fa3d080 BW |
11516 | static void |
11517 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
11518 | { |
11519 | if (directive_state[directive_absolute_literals]) | |
11520 | { | |
74869ac7 BW |
11521 | segT lit4_seg = cache_literal_section (TRUE); |
11522 | xtensa_switch_section_emit_state (result, lit4_seg, 0); | |
43cd72b9 BW |
11523 | } |
11524 | else | |
11525 | xtensa_switch_to_non_abs_literal_fragment (result); | |
11526 | ||
11527 | /* Do a 4-byte align here. */ | |
11528 | frag_align (2, 0, 0); | |
11529 | record_alignment (now_seg, 2); | |
11530 | } | |
11531 | ||
11532 | ||
7fa3d080 BW |
11533 | static void |
11534 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 | 11535 | { |
e0001a05 | 11536 | fragS *pool_location = get_literal_pool_location (now_seg); |
74869ac7 | 11537 | segT lit_seg; |
c138bc38 | 11538 | bfd_boolean is_init = |
e0001a05 | 11539 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); |
c138bc38 | 11540 | bfd_boolean is_fini = |
e0001a05 | 11541 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); |
e0001a05 | 11542 | |
43cd72b9 BW |
11543 | if (pool_location == NULL |
11544 | && !use_literal_section | |
e0001a05 NC |
11545 | && !is_init && ! is_fini) |
11546 | { | |
b46824bd MF |
11547 | if (!auto_litpools) |
11548 | { | |
11549 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); | |
11550 | } | |
947fa914 MF |
11551 | xtensa_maybe_create_literal_pool_frag (TRUE, TRUE); |
11552 | pool_location = get_literal_pool_location (now_seg); | |
e0001a05 NC |
11553 | } |
11554 | ||
74869ac7 BW |
11555 | lit_seg = cache_literal_section (FALSE); |
11556 | xtensa_switch_section_emit_state (result, lit_seg, 0); | |
e0001a05 | 11557 | |
43cd72b9 BW |
11558 | if (!use_literal_section |
11559 | && !is_init && !is_fini | |
11560 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
11561 | { |
11562 | /* Close whatever frag is there. */ | |
11563 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11564 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
11565 | frag_now->tc_frag_data.literal_frag = pool_location; |
11566 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 11567 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 11568 | } |
e0001a05 NC |
11569 | } |
11570 | ||
11571 | ||
11572 | /* Call this function before emitting data into the literal section. | |
11573 | This is a helper function for xtensa_switch_to_literal_fragment. | |
11574 | This is similar to a .section new_now_seg subseg. */ | |
11575 | ||
7fa3d080 BW |
11576 | static void |
11577 | xtensa_switch_section_emit_state (emit_state *state, | |
11578 | segT new_now_seg, | |
11579 | subsegT new_now_subseg) | |
e0001a05 NC |
11580 | { |
11581 | state->name = now_seg->name; | |
11582 | state->now_seg = now_seg; | |
11583 | state->now_subseg = now_subseg; | |
11584 | state->generating_literals = generating_literals; | |
11585 | generating_literals++; | |
2b0210eb | 11586 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
11587 | } |
11588 | ||
11589 | ||
11590 | /* Use to restore the emitting into the normal place. */ | |
11591 | ||
7fa3d080 BW |
11592 | static void |
11593 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
11594 | { |
11595 | generating_literals = state->generating_literals; | |
2b0210eb | 11596 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
11597 | } |
11598 | ||
11599 | ||
74869ac7 | 11600 | /* Predicate function used to look up a section in a particular group. */ |
e0001a05 | 11601 | |
74869ac7 BW |
11602 | static bfd_boolean |
11603 | match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) | |
e0001a05 | 11604 | { |
74869ac7 BW |
11605 | const char *gname = inf; |
11606 | const char *group_name = elf_group_name (sec); | |
3739860c | 11607 | |
74869ac7 BW |
11608 | return (group_name == gname |
11609 | || (group_name != NULL | |
11610 | && gname != NULL | |
11611 | && strcmp (group_name, gname) == 0)); | |
11612 | } | |
e0001a05 | 11613 | |
e0001a05 | 11614 | |
74869ac7 BW |
11615 | /* Get the literal section to be used for the current text section. |
11616 | The result may be cached in the default_lit_sections structure. */ | |
11617 | ||
11618 | static segT | |
11619 | cache_literal_section (bfd_boolean use_abs_literals) | |
11620 | { | |
11621 | const char *text_name, *group_name = 0; | |
b9bb4a93 TS |
11622 | const char *base_name, *suffix; |
11623 | char *name; | |
74869ac7 BW |
11624 | segT *pcached; |
11625 | segT seg, current_section; | |
11626 | int current_subsec; | |
11627 | bfd_boolean linkonce = FALSE; | |
11628 | ||
11629 | /* Save the current section/subsection. */ | |
11630 | current_section = now_seg; | |
11631 | current_subsec = now_subseg; | |
11632 | ||
11633 | /* Clear the cached values if they are no longer valid. */ | |
11634 | if (now_seg != default_lit_sections.current_text_seg) | |
b08b5071 | 11635 | { |
74869ac7 BW |
11636 | default_lit_sections.current_text_seg = now_seg; |
11637 | default_lit_sections.lit_seg = NULL; | |
11638 | default_lit_sections.lit4_seg = NULL; | |
11639 | } | |
11640 | ||
11641 | /* Check if the literal section is already cached. */ | |
11642 | if (use_abs_literals) | |
11643 | pcached = &default_lit_sections.lit4_seg; | |
11644 | else | |
11645 | pcached = &default_lit_sections.lit_seg; | |
11646 | ||
11647 | if (*pcached) | |
11648 | return *pcached; | |
3739860c | 11649 | |
74869ac7 BW |
11650 | text_name = default_lit_sections.lit_prefix; |
11651 | if (! text_name || ! *text_name) | |
11652 | { | |
11653 | text_name = segment_name (current_section); | |
11654 | group_name = elf_group_name (current_section); | |
11655 | linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; | |
11656 | } | |
11657 | ||
11658 | base_name = use_abs_literals ? ".lit4" : ".literal"; | |
11659 | if (group_name) | |
11660 | { | |
4ec9d7d5 | 11661 | name = concat (base_name, ".", group_name, (char *) NULL); |
74869ac7 BW |
11662 | } |
11663 | else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) | |
11664 | { | |
11665 | suffix = strchr (text_name + linkonce_len, '.'); | |
11666 | ||
4ec9d7d5 TS |
11667 | name = concat (".gnu.linkonce", base_name, suffix ? suffix : "", |
11668 | (char *) NULL); | |
74869ac7 BW |
11669 | linkonce = TRUE; |
11670 | } | |
11671 | else | |
11672 | { | |
a89c407e SA |
11673 | /* If the section name begins or ends with ".text", then replace |
11674 | that portion instead of appending an additional suffix. */ | |
74869ac7 | 11675 | size_t len = strlen (text_name); |
a89c407e SA |
11676 | if (len >= 5 |
11677 | && (strcmp (text_name + len - 5, ".text") == 0 | |
11678 | || strncmp (text_name, ".text", 5) == 0)) | |
74869ac7 BW |
11679 | len -= 5; |
11680 | ||
add39d23 | 11681 | name = XNEWVEC (char, len + strlen (base_name) + 1); |
a89c407e SA |
11682 | if (strncmp (text_name, ".text", 5) == 0) |
11683 | { | |
11684 | strcpy (name, base_name); | |
11685 | strcat (name, text_name + 5); | |
11686 | } | |
11687 | else | |
11688 | { | |
11689 | strcpy (name, text_name); | |
11690 | strcpy (name + len, base_name); | |
11691 | } | |
b08b5071 | 11692 | } |
e0001a05 | 11693 | |
74869ac7 BW |
11694 | /* Canonicalize section names to allow renaming literal sections. |
11695 | The group name, if any, came from the current text section and | |
11696 | has already been canonicalized. */ | |
11697 | name = tc_canonicalize_symbol_name (name); | |
11698 | ||
11699 | seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, | |
11700 | (void *) group_name); | |
11701 | if (! seg) | |
e0001a05 | 11702 | { |
74869ac7 BW |
11703 | flagword flags; |
11704 | ||
11705 | seg = subseg_force_new (name, 0); | |
11706 | ||
11707 | if (! use_abs_literals) | |
b08b5071 | 11708 | { |
74869ac7 | 11709 | /* Add the newly created literal segment to the list. */ |
325801bd | 11710 | seg_list *n = XNEW (seg_list); |
b08b5071 | 11711 | n->seg = seg; |
74869ac7 BW |
11712 | n->next = literal_head->next; |
11713 | literal_head->next = n; | |
b08b5071 | 11714 | } |
74869ac7 BW |
11715 | |
11716 | flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD | |
11717 | | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) | |
11718 | | (use_abs_literals ? SEC_DATA : SEC_CODE)); | |
11719 | ||
11720 | elf_group_name (seg) = group_name; | |
11721 | ||
11722 | bfd_set_section_flags (stdoutput, seg, flags); | |
b08b5071 | 11723 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
11724 | } |
11725 | ||
74869ac7 | 11726 | *pcached = seg; |
b08b5071 | 11727 | subseg_set (current_section, current_subsec); |
74869ac7 | 11728 | return seg; |
e0001a05 NC |
11729 | } |
11730 | ||
43cd72b9 BW |
11731 | \f |
11732 | /* Property Tables Stuff. */ | |
11733 | ||
7fa3d080 BW |
11734 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
11735 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
11736 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
11737 | ||
11738 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
11739 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
11740 | ||
b08b5071 | 11741 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
11742 | static void xtensa_create_property_segments |
11743 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
11744 | static void xtensa_create_xproperty_segments | |
11745 | (frag_flags_fn, const char *, xt_section_type); | |
532f93bd | 11746 | static bfd_boolean exclude_section_from_property_tables (segT); |
7fa3d080 BW |
11747 | static bfd_boolean section_has_property (segT, frag_predicate); |
11748 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
11749 | static void add_xt_block_frags | |
542f8b94 | 11750 | (segT, xtensa_block_info **, frag_predicate, frag_predicate); |
7fa3d080 BW |
11751 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); |
11752 | static void xtensa_frag_flags_init (frag_flags *); | |
11753 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
2f1bf5c1 | 11754 | static flagword frag_flags_to_number (const frag_flags *); |
542f8b94 | 11755 | static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn); |
7fa3d080 BW |
11756 | |
11757 | /* Set up property tables after relaxation. */ | |
11758 | ||
11759 | void | |
11760 | xtensa_post_relax_hook (void) | |
11761 | { | |
11762 | xtensa_move_seg_list_to_beginning (literal_head); | |
7fa3d080 BW |
11763 | |
11764 | xtensa_find_unmarked_state_frags (); | |
99ded152 | 11765 | xtensa_mark_frags_for_org (); |
6a7eedfe | 11766 | xtensa_mark_difference_of_two_symbols (); |
7fa3d080 | 11767 | |
b29757dc BW |
11768 | xtensa_create_property_segments (get_frag_is_literal, |
11769 | NULL, | |
11770 | XTENSA_LIT_SEC_NAME, | |
11771 | xt_literal_sec); | |
7fa3d080 BW |
11772 | xtensa_create_xproperty_segments (get_frag_property_flags, |
11773 | XTENSA_PROP_SEC_NAME, | |
11774 | xt_prop_sec); | |
11775 | ||
11776 | if (warn_unaligned_branch_targets) | |
11777 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
11778 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
11779 | } | |
11780 | ||
11781 | ||
43cd72b9 BW |
11782 | /* This function is only meaningful after xtensa_move_literals. */ |
11783 | ||
11784 | static bfd_boolean | |
7fa3d080 | 11785 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 | 11786 | { |
9c2799c2 | 11787 | gas_assert (fragP != NULL); |
43cd72b9 BW |
11788 | return fragP->tc_frag_data.is_literal; |
11789 | } | |
11790 | ||
11791 | ||
43cd72b9 | 11792 | static void |
7fa3d080 BW |
11793 | xtensa_create_property_segments (frag_predicate property_function, |
11794 | frag_predicate end_property_function, | |
11795 | const char *section_name_base, | |
11796 | xt_section_type sec_type) | |
43cd72b9 BW |
11797 | { |
11798 | segT *seclist; | |
11799 | ||
11800 | /* Walk over all of the current segments. | |
11801 | Walk over each fragment | |
11802 | For each non-empty fragment, | |
11803 | Build a property record (append where possible). */ | |
11804 | ||
11805 | for (seclist = &stdoutput->sections; | |
11806 | seclist && *seclist; | |
11807 | seclist = &(*seclist)->next) | |
11808 | { | |
11809 | segT sec = *seclist; | |
43cd72b9 | 11810 | |
532f93bd | 11811 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
11812 | continue; |
11813 | ||
11814 | if (section_has_property (sec, property_function)) | |
11815 | { | |
542f8b94 BW |
11816 | segment_info_type *xt_seg_info; |
11817 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 11818 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
11819 | |
11820 | prop_sec->output_section = prop_sec; | |
11821 | subseg_set (prop_sec, 0); | |
11822 | xt_seg_info = seg_info (prop_sec); | |
11823 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
11824 | ||
43cd72b9 | 11825 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 11826 | add_xt_block_frags (sec, xt_blocks, property_function, |
43cd72b9 BW |
11827 | end_property_function); |
11828 | } | |
11829 | } | |
11830 | ||
11831 | /* Now we fill them out.... */ | |
11832 | ||
11833 | for (seclist = &stdoutput->sections; | |
11834 | seclist && *seclist; | |
11835 | seclist = &(*seclist)->next) | |
11836 | { | |
11837 | segment_info_type *seginfo; | |
11838 | xtensa_block_info *block; | |
11839 | segT sec = *seclist; | |
11840 | ||
11841 | seginfo = seg_info (sec); | |
11842 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
11843 | ||
11844 | if (block) | |
11845 | { | |
11846 | xtensa_block_info *cur_block; | |
43cd72b9 | 11847 | int num_recs = 0; |
d77b99c9 | 11848 | bfd_size_type rec_size; |
43cd72b9 BW |
11849 | |
11850 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
11851 | num_recs++; | |
11852 | ||
11853 | rec_size = num_recs * 8; | |
11854 | bfd_set_section_size (stdoutput, sec, rec_size); | |
11855 | ||
43cd72b9 BW |
11856 | if (num_recs) |
11857 | { | |
43cd72b9 | 11858 | char *frag_data; |
542f8b94 | 11859 | int i; |
43cd72b9 | 11860 | |
542f8b94 BW |
11861 | subseg_set (sec, 0); |
11862 | frag_data = frag_more (rec_size); | |
43cd72b9 | 11863 | cur_block = block; |
43cd72b9 BW |
11864 | for (i = 0; i < num_recs; i++) |
11865 | { | |
542f8b94 | 11866 | fixS *fix; |
e0001a05 | 11867 | |
43cd72b9 | 11868 | /* Write the fixup. */ |
9c2799c2 | 11869 | gas_assert (cur_block); |
542f8b94 BW |
11870 | fix = fix_new (frag_now, i * 8, 4, |
11871 | section_symbol (cur_block->sec), | |
11872 | cur_block->offset, | |
11873 | FALSE, BFD_RELOC_32); | |
11874 | fix->fx_file = "<internal>"; | |
43cd72b9 | 11875 | fix->fx_line = 0; |
e0001a05 | 11876 | |
43cd72b9 | 11877 | /* Write the length. */ |
542f8b94 | 11878 | md_number_to_chars (&frag_data[4 + i * 8], |
43cd72b9 BW |
11879 | cur_block->size, 4); |
11880 | cur_block = cur_block->next; | |
11881 | } | |
542f8b94 BW |
11882 | frag_wane (frag_now); |
11883 | frag_new (0); | |
11884 | frag_wane (frag_now); | |
43cd72b9 BW |
11885 | } |
11886 | } | |
11887 | } | |
e0001a05 NC |
11888 | } |
11889 | ||
11890 | ||
7fa3d080 BW |
11891 | static void |
11892 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
11893 | const char *section_name_base, | |
11894 | xt_section_type sec_type) | |
e0001a05 NC |
11895 | { |
11896 | segT *seclist; | |
11897 | ||
11898 | /* Walk over all of the current segments. | |
43cd72b9 BW |
11899 | Walk over each fragment. |
11900 | For each fragment that has instructions, | |
11901 | build an instruction record (append where possible). */ | |
e0001a05 NC |
11902 | |
11903 | for (seclist = &stdoutput->sections; | |
11904 | seclist && *seclist; | |
11905 | seclist = &(*seclist)->next) | |
11906 | { | |
11907 | segT sec = *seclist; | |
43cd72b9 | 11908 | |
532f93bd | 11909 | if (exclude_section_from_property_tables (sec)) |
43cd72b9 BW |
11910 | continue; |
11911 | ||
11912 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 11913 | { |
542f8b94 BW |
11914 | segment_info_type *xt_seg_info; |
11915 | xtensa_block_info **xt_blocks; | |
51c8ebc1 | 11916 | segT prop_sec = xtensa_make_property_section (sec, section_name_base); |
542f8b94 BW |
11917 | |
11918 | prop_sec->output_section = prop_sec; | |
11919 | subseg_set (prop_sec, 0); | |
11920 | xt_seg_info = seg_info (prop_sec); | |
11921 | xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
11922 | ||
e0001a05 | 11923 | /* Walk over all of the frchains here and add new sections. */ |
542f8b94 | 11924 | add_xt_prop_frags (sec, xt_blocks, flag_fn); |
e0001a05 NC |
11925 | } |
11926 | } | |
11927 | ||
11928 | /* Now we fill them out.... */ | |
11929 | ||
11930 | for (seclist = &stdoutput->sections; | |
11931 | seclist && *seclist; | |
11932 | seclist = &(*seclist)->next) | |
11933 | { | |
11934 | segment_info_type *seginfo; | |
11935 | xtensa_block_info *block; | |
11936 | segT sec = *seclist; | |
43cd72b9 | 11937 | |
e0001a05 NC |
11938 | seginfo = seg_info (sec); |
11939 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
11940 | ||
11941 | if (block) | |
11942 | { | |
11943 | xtensa_block_info *cur_block; | |
43cd72b9 | 11944 | int num_recs = 0; |
d77b99c9 | 11945 | bfd_size_type rec_size; |
e0001a05 NC |
11946 | |
11947 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
11948 | num_recs++; | |
11949 | ||
43cd72b9 | 11950 | rec_size = num_recs * (8 + 4); |
e0001a05 | 11951 | bfd_set_section_size (stdoutput, sec, rec_size); |
43cd72b9 BW |
11952 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
11953 | ||
e0001a05 NC |
11954 | if (num_recs) |
11955 | { | |
e0001a05 | 11956 | char *frag_data; |
542f8b94 | 11957 | int i; |
e0001a05 | 11958 | |
542f8b94 BW |
11959 | subseg_set (sec, 0); |
11960 | frag_data = frag_more (rec_size); | |
e0001a05 | 11961 | cur_block = block; |
e0001a05 NC |
11962 | for (i = 0; i < num_recs; i++) |
11963 | { | |
542f8b94 | 11964 | fixS *fix; |
e0001a05 NC |
11965 | |
11966 | /* Write the fixup. */ | |
9c2799c2 | 11967 | gas_assert (cur_block); |
542f8b94 BW |
11968 | fix = fix_new (frag_now, i * 12, 4, |
11969 | section_symbol (cur_block->sec), | |
11970 | cur_block->offset, | |
11971 | FALSE, BFD_RELOC_32); | |
11972 | fix->fx_file = "<internal>"; | |
e0001a05 NC |
11973 | fix->fx_line = 0; |
11974 | ||
11975 | /* Write the length. */ | |
542f8b94 | 11976 | md_number_to_chars (&frag_data[4 + i * 12], |
e0001a05 | 11977 | cur_block->size, 4); |
542f8b94 | 11978 | md_number_to_chars (&frag_data[8 + i * 12], |
43cd72b9 | 11979 | frag_flags_to_number (&cur_block->flags), |
2f1bf5c1 | 11980 | sizeof (flagword)); |
e0001a05 NC |
11981 | cur_block = cur_block->next; |
11982 | } | |
542f8b94 BW |
11983 | frag_wane (frag_now); |
11984 | frag_new (0); | |
11985 | frag_wane (frag_now); | |
e0001a05 NC |
11986 | } |
11987 | } | |
11988 | } | |
11989 | } | |
11990 | ||
11991 | ||
532f93bd BW |
11992 | static bfd_boolean |
11993 | exclude_section_from_property_tables (segT sec) | |
11994 | { | |
11995 | flagword flags = bfd_get_section_flags (stdoutput, sec); | |
11996 | ||
11997 | /* Sections that don't contribute to the memory footprint are excluded. */ | |
11998 | if ((flags & SEC_DEBUGGING) | |
11999 | || !(flags & SEC_ALLOC) | |
12000 | || (flags & SEC_MERGE)) | |
12001 | return TRUE; | |
12002 | ||
12003 | /* Linker cie and fde optimizations mess up property entries for | |
12004 | eh_frame sections, but there is nothing inside them relevant to | |
12005 | property tables anyway. */ | |
12006 | if (strcmp (sec->name, ".eh_frame") == 0) | |
12007 | return TRUE; | |
12008 | ||
12009 | return FALSE; | |
12010 | } | |
12011 | ||
12012 | ||
7fa3d080 BW |
12013 | static bfd_boolean |
12014 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
12015 | { |
12016 | segment_info_type *seginfo = seg_info (sec); | |
12017 | fragS *fragP; | |
12018 | ||
12019 | if (seginfo && seginfo->frchainP) | |
12020 | { | |
12021 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
12022 | { | |
12023 | if (property_function (fragP) | |
12024 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
12025 | return TRUE; | |
12026 | } | |
12027 | } | |
12028 | return FALSE; | |
12029 | } | |
12030 | ||
12031 | ||
7fa3d080 BW |
12032 | static bfd_boolean |
12033 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
12034 | { |
12035 | segment_info_type *seginfo = seg_info (sec); | |
12036 | fragS *fragP; | |
12037 | ||
12038 | if (seginfo && seginfo->frchainP) | |
12039 | { | |
12040 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
12041 | { | |
12042 | frag_flags prop_flags; | |
12043 | property_function (fragP, &prop_flags); | |
12044 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
12045 | return TRUE; | |
12046 | } | |
12047 | } | |
12048 | return FALSE; | |
12049 | } | |
12050 | ||
12051 | ||
e0001a05 NC |
12052 | /* Two types of block sections exist right now: literal and insns. */ |
12053 | ||
7fa3d080 BW |
12054 | static void |
12055 | add_xt_block_frags (segT sec, | |
7fa3d080 BW |
12056 | xtensa_block_info **xt_block, |
12057 | frag_predicate property_function, | |
12058 | frag_predicate end_property_function) | |
e0001a05 | 12059 | { |
e0001a05 NC |
12060 | fragS *fragP; |
12061 | ||
e0001a05 NC |
12062 | /* Build it if needed. */ |
12063 | while (*xt_block != NULL) | |
12064 | xt_block = &(*xt_block)->next; | |
12065 | /* We are either at NULL at the beginning or at the end. */ | |
12066 | ||
12067 | /* Walk through the frags. */ | |
542f8b94 | 12068 | if (seg_info (sec)->frchainP) |
e0001a05 | 12069 | { |
542f8b94 | 12070 | for (fragP = seg_info (sec)->frchainP->frch_root; |
e0001a05 NC |
12071 | fragP; |
12072 | fragP = fragP->fr_next) | |
12073 | { | |
12074 | if (property_function (fragP) | |
12075 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
12076 | { | |
12077 | if (*xt_block != NULL) | |
12078 | { | |
12079 | if ((*xt_block)->offset + (*xt_block)->size | |
12080 | == fragP->fr_address) | |
12081 | (*xt_block)->size += fragP->fr_fix; | |
12082 | else | |
12083 | xt_block = &((*xt_block)->next); | |
12084 | } | |
12085 | if (*xt_block == NULL) | |
12086 | { | |
325801bd | 12087 | xtensa_block_info *new_block = XNEW (xtensa_block_info); |
43cd72b9 BW |
12088 | new_block->sec = sec; |
12089 | new_block->offset = fragP->fr_address; | |
12090 | new_block->size = fragP->fr_fix; | |
12091 | new_block->next = NULL; | |
12092 | xtensa_frag_flags_init (&new_block->flags); | |
12093 | *xt_block = new_block; | |
12094 | } | |
12095 | if (end_property_function | |
12096 | && end_property_function (fragP)) | |
12097 | { | |
12098 | xt_block = &((*xt_block)->next); | |
12099 | } | |
12100 | } | |
12101 | } | |
12102 | } | |
12103 | } | |
12104 | ||
12105 | ||
12106 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
12107 | ||
7fa3d080 BW |
12108 | static bfd_boolean |
12109 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
12110 | { |
12111 | if (prop_flags->is_literal | |
12112 | || prop_flags->is_insn | |
12113 | || prop_flags->is_data | |
12114 | || prop_flags->is_unreachable) | |
12115 | return FALSE; | |
12116 | return TRUE; | |
12117 | } | |
12118 | ||
12119 | ||
7fa3d080 BW |
12120 | static void |
12121 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
12122 | { |
12123 | memset (prop_flags, 0, sizeof (frag_flags)); | |
12124 | } | |
12125 | ||
12126 | ||
7fa3d080 BW |
12127 | static void |
12128 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
12129 | { |
12130 | xtensa_frag_flags_init (prop_flags); | |
12131 | if (fragP->tc_frag_data.is_literal) | |
12132 | prop_flags->is_literal = TRUE; | |
99ded152 BW |
12133 | if (fragP->tc_frag_data.is_specific_opcode |
12134 | || fragP->tc_frag_data.is_no_transform) | |
1f7efbae BW |
12135 | { |
12136 | prop_flags->is_no_transform = TRUE; | |
12137 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
12138 | prop_flags->is_data = TRUE; | |
12139 | } | |
43cd72b9 | 12140 | if (fragP->tc_frag_data.is_unreachable) |
7fa3d080 | 12141 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
12142 | else if (fragP->tc_frag_data.is_insn) |
12143 | { | |
12144 | prop_flags->is_insn = TRUE; | |
12145 | if (fragP->tc_frag_data.is_loop_target) | |
12146 | prop_flags->insn.is_loop_target = TRUE; | |
12147 | if (fragP->tc_frag_data.is_branch_target) | |
12148 | prop_flags->insn.is_branch_target = TRUE; | |
43cd72b9 BW |
12149 | if (fragP->tc_frag_data.is_no_density) |
12150 | prop_flags->insn.is_no_density = TRUE; | |
12151 | if (fragP->tc_frag_data.use_absolute_literals) | |
12152 | prop_flags->insn.is_abslit = TRUE; | |
12153 | } | |
12154 | if (fragP->tc_frag_data.is_align) | |
12155 | { | |
12156 | prop_flags->is_align = TRUE; | |
12157 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
12158 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
12159 | prop_flags->is_data = TRUE; | |
12160 | } | |
12161 | } | |
12162 | ||
12163 | ||
2f1bf5c1 | 12164 | static flagword |
7fa3d080 | 12165 | frag_flags_to_number (const frag_flags *prop_flags) |
43cd72b9 | 12166 | { |
2f1bf5c1 | 12167 | flagword num = 0; |
43cd72b9 BW |
12168 | if (prop_flags->is_literal) |
12169 | num |= XTENSA_PROP_LITERAL; | |
12170 | if (prop_flags->is_insn) | |
12171 | num |= XTENSA_PROP_INSN; | |
12172 | if (prop_flags->is_data) | |
12173 | num |= XTENSA_PROP_DATA; | |
12174 | if (prop_flags->is_unreachable) | |
12175 | num |= XTENSA_PROP_UNREACHABLE; | |
12176 | if (prop_flags->insn.is_loop_target) | |
12177 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
12178 | if (prop_flags->insn.is_branch_target) | |
12179 | { | |
12180 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
12181 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
12182 | } | |
12183 | ||
12184 | if (prop_flags->insn.is_no_density) | |
12185 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
99ded152 BW |
12186 | if (prop_flags->is_no_transform) |
12187 | num |= XTENSA_PROP_NO_TRANSFORM; | |
43cd72b9 BW |
12188 | if (prop_flags->insn.is_no_reorder) |
12189 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
12190 | if (prop_flags->insn.is_abslit) | |
12191 | num |= XTENSA_PROP_INSN_ABSLIT; | |
12192 | ||
12193 | if (prop_flags->is_align) | |
12194 | { | |
12195 | num |= XTENSA_PROP_ALIGN; | |
12196 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
12197 | } | |
12198 | ||
12199 | return num; | |
12200 | } | |
12201 | ||
12202 | ||
12203 | static bfd_boolean | |
7fa3d080 BW |
12204 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
12205 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
12206 | { |
12207 | /* Cannot combine with an end marker. */ | |
12208 | ||
12209 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
12210 | return FALSE; | |
12211 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
12212 | return FALSE; | |
12213 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
12214 | return FALSE; | |
12215 | ||
12216 | if (prop_flags_1->is_insn) | |
12217 | { | |
12218 | /* Properties of the beginning of the frag. */ | |
12219 | if (prop_flags_2->insn.is_loop_target) | |
12220 | return FALSE; | |
12221 | if (prop_flags_2->insn.is_branch_target) | |
12222 | return FALSE; | |
12223 | if (prop_flags_1->insn.is_no_density != | |
12224 | prop_flags_2->insn.is_no_density) | |
12225 | return FALSE; | |
99ded152 BW |
12226 | if (prop_flags_1->is_no_transform != |
12227 | prop_flags_2->is_no_transform) | |
43cd72b9 BW |
12228 | return FALSE; |
12229 | if (prop_flags_1->insn.is_no_reorder != | |
12230 | prop_flags_2->insn.is_no_reorder) | |
12231 | return FALSE; | |
12232 | if (prop_flags_1->insn.is_abslit != | |
12233 | prop_flags_2->insn.is_abslit) | |
12234 | return FALSE; | |
12235 | } | |
12236 | ||
12237 | if (prop_flags_1->is_align) | |
12238 | return FALSE; | |
12239 | ||
12240 | return TRUE; | |
12241 | } | |
12242 | ||
12243 | ||
7fa3d080 BW |
12244 | static bfd_vma |
12245 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
12246 | { |
12247 | bfd_vma end_addr; | |
d77b99c9 | 12248 | unsigned align_bits; |
43cd72b9 BW |
12249 | |
12250 | if (!xt_block->flags.is_align) | |
12251 | return xt_block->size; | |
12252 | ||
12253 | end_addr = xt_block->offset + xt_block->size; | |
12254 | align_bits = xt_block->flags.alignment; | |
12255 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
12256 | return end_addr - xt_block->offset; | |
12257 | } | |
12258 | ||
12259 | ||
12260 | static bfd_boolean | |
7fa3d080 BW |
12261 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
12262 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
12263 | { |
12264 | if (xt_block->sec != xt_block_2->sec) | |
12265 | return FALSE; | |
12266 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
12267 | != xt_block_2->offset) | |
12268 | return FALSE; | |
12269 | ||
12270 | if (xt_block_2->size == 0 | |
12271 | && (!xt_block_2->flags.is_unreachable | |
12272 | || xt_block->flags.is_unreachable)) | |
12273 | { | |
12274 | if (xt_block_2->flags.is_align | |
12275 | && xt_block->flags.is_align) | |
12276 | { | |
12277 | /* Nothing needed. */ | |
12278 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
12279 | return TRUE; | |
12280 | } | |
12281 | else | |
12282 | { | |
12283 | if (xt_block_2->flags.is_align) | |
12284 | { | |
12285 | /* Push alignment to previous entry. */ | |
12286 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
12287 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
12288 | } | |
12289 | return TRUE; | |
12290 | } | |
12291 | } | |
12292 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
12293 | &xt_block_2->flags)) | |
12294 | return FALSE; | |
12295 | ||
12296 | xt_block->size += xt_block_2->size; | |
12297 | ||
12298 | if (xt_block_2->flags.is_align) | |
12299 | { | |
12300 | xt_block->flags.is_align = TRUE; | |
12301 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
12302 | } | |
12303 | ||
12304 | return TRUE; | |
12305 | } | |
12306 | ||
12307 | ||
7fa3d080 BW |
12308 | static void |
12309 | add_xt_prop_frags (segT sec, | |
7fa3d080 BW |
12310 | xtensa_block_info **xt_block, |
12311 | frag_flags_fn property_function) | |
43cd72b9 | 12312 | { |
43cd72b9 BW |
12313 | fragS *fragP; |
12314 | ||
43cd72b9 BW |
12315 | /* Build it if needed. */ |
12316 | while (*xt_block != NULL) | |
12317 | { | |
12318 | xt_block = &(*xt_block)->next; | |
12319 | } | |
12320 | /* We are either at NULL at the beginning or at the end. */ | |
12321 | ||
12322 | /* Walk through the frags. */ | |
542f8b94 | 12323 | if (seg_info (sec)->frchainP) |
43cd72b9 | 12324 | { |
542f8b94 | 12325 | for (fragP = seg_info (sec)->frchainP->frch_root; fragP; |
43cd72b9 BW |
12326 | fragP = fragP->fr_next) |
12327 | { | |
12328 | xtensa_block_info tmp_block; | |
12329 | tmp_block.sec = sec; | |
12330 | tmp_block.offset = fragP->fr_address; | |
12331 | tmp_block.size = fragP->fr_fix; | |
12332 | tmp_block.next = NULL; | |
12333 | property_function (fragP, &tmp_block.flags); | |
12334 | ||
12335 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
12336 | /* && fragP->fr_fix != 0) */ | |
12337 | { | |
12338 | if ((*xt_block) == NULL | |
12339 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
12340 | { | |
12341 | xtensa_block_info *new_block; | |
12342 | if ((*xt_block) != NULL) | |
12343 | xt_block = &(*xt_block)->next; | |
325801bd | 12344 | new_block = XNEW (xtensa_block_info); |
43cd72b9 BW |
12345 | *new_block = tmp_block; |
12346 | *xt_block = new_block; | |
12347 | } | |
12348 | } | |
12349 | } | |
12350 | } | |
12351 | } | |
12352 | ||
12353 | \f | |
12354 | /* op_placement_info_table */ | |
12355 | ||
12356 | /* op_placement_info makes it easier to determine which | |
12357 | ops can go in which slots. */ | |
12358 | ||
12359 | static void | |
7fa3d080 | 12360 | init_op_placement_info_table (void) |
43cd72b9 BW |
12361 | { |
12362 | xtensa_isa isa = xtensa_default_isa; | |
12363 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
12364 | xtensa_opcode opcode; | |
12365 | xtensa_format fmt; | |
12366 | int slot; | |
12367 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
12368 | ||
325801bd | 12369 | op_placement_table = XNEWVEC (op_placement_info, num_opcodes); |
9c2799c2 | 12370 | gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); |
43cd72b9 BW |
12371 | |
12372 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
12373 | { | |
12374 | op_placement_info *opi = &op_placement_table[opcode]; | |
12375 | /* FIXME: Make tinsn allocation dynamic. */ | |
51add5c3 | 12376 | if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS) |
43cd72b9 | 12377 | as_fatal (_("too many operands in instruction")); |
43cd72b9 BW |
12378 | opi->narrowest = XTENSA_UNDEFINED; |
12379 | opi->narrowest_size = 0x7F; | |
b2d179be | 12380 | opi->narrowest_slot = 0; |
43cd72b9 BW |
12381 | opi->formats = 0; |
12382 | opi->num_formats = 0; | |
12383 | opi->issuef = 0; | |
12384 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
12385 | { | |
12386 | opi->slots[fmt] = 0; | |
12387 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
12388 | { | |
12389 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
12390 | { | |
12391 | int fmt_length = xtensa_format_length (isa, fmt); | |
12392 | opi->issuef++; | |
12393 | set_bit (fmt, opi->formats); | |
12394 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
12395 | if (fmt_length < opi->narrowest_size |
12396 | || (fmt_length == opi->narrowest_size | |
12397 | && (xtensa_format_num_slots (isa, fmt) | |
12398 | < xtensa_format_num_slots (isa, | |
12399 | opi->narrowest)))) | |
43cd72b9 BW |
12400 | { |
12401 | opi->narrowest = fmt; | |
12402 | opi->narrowest_size = fmt_length; | |
b2d179be | 12403 | opi->narrowest_slot = slot; |
43cd72b9 | 12404 | } |
e0001a05 NC |
12405 | } |
12406 | } | |
43cd72b9 BW |
12407 | if (opi->formats) |
12408 | opi->num_formats++; | |
e0001a05 NC |
12409 | } |
12410 | } | |
43cd72b9 BW |
12411 | xtensa_insnbuf_free (isa, ibuf); |
12412 | } | |
12413 | ||
12414 | ||
12415 | bfd_boolean | |
7fa3d080 | 12416 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
12417 | { |
12418 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
12419 | } | |
12420 | ||
12421 | ||
12422 | /* If the opcode is available in a single slot format, return its size. */ | |
12423 | ||
7fa3d080 BW |
12424 | static int |
12425 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 12426 | { |
b2d179be | 12427 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
12428 | } |
12429 | ||
12430 | ||
7fa3d080 BW |
12431 | static xtensa_format |
12432 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 12433 | { |
b2d179be BW |
12434 | return op_placement_table[opcode].narrowest; |
12435 | } | |
12436 | ||
12437 | ||
12438 | static int | |
12439 | xg_get_single_slot (xtensa_opcode opcode) | |
12440 | { | |
12441 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
12442 | } |
12443 | ||
12444 | \f | |
12445 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
12446 | ||
12447 | void | |
7fa3d080 | 12448 | istack_init (IStack *stack) |
e0001a05 | 12449 | { |
e0001a05 NC |
12450 | stack->ninsn = 0; |
12451 | } | |
12452 | ||
12453 | ||
12454 | bfd_boolean | |
7fa3d080 | 12455 | istack_empty (IStack *stack) |
e0001a05 NC |
12456 | { |
12457 | return (stack->ninsn == 0); | |
12458 | } | |
12459 | ||
12460 | ||
12461 | bfd_boolean | |
7fa3d080 | 12462 | istack_full (IStack *stack) |
e0001a05 NC |
12463 | { |
12464 | return (stack->ninsn == MAX_ISTACK); | |
12465 | } | |
12466 | ||
12467 | ||
12468 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 12469 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
12470 | |
12471 | TInsn * | |
7fa3d080 | 12472 | istack_top (IStack *stack) |
e0001a05 NC |
12473 | { |
12474 | int rec = stack->ninsn - 1; | |
9c2799c2 | 12475 | gas_assert (!istack_empty (stack)); |
e0001a05 NC |
12476 | return &stack->insn[rec]; |
12477 | } | |
12478 | ||
12479 | ||
12480 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 12481 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
12482 | |
12483 | void | |
7fa3d080 | 12484 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
12485 | { |
12486 | int rec = stack->ninsn; | |
9c2799c2 | 12487 | gas_assert (!istack_full (stack)); |
43cd72b9 | 12488 | stack->insn[rec] = *insn; |
e0001a05 NC |
12489 | stack->ninsn++; |
12490 | } | |
12491 | ||
12492 | ||
12493 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 12494 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
12495 | |
12496 | TInsn * | |
7fa3d080 | 12497 | istack_push_space (IStack *stack) |
e0001a05 NC |
12498 | { |
12499 | int rec = stack->ninsn; | |
12500 | TInsn *insn; | |
9c2799c2 | 12501 | gas_assert (!istack_full (stack)); |
e0001a05 | 12502 | insn = &stack->insn[rec]; |
60242db2 | 12503 | tinsn_init (insn); |
e0001a05 NC |
12504 | stack->ninsn++; |
12505 | return insn; | |
12506 | } | |
12507 | ||
12508 | ||
12509 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 12510 | istack_empty () returns TRUE. */ |
e0001a05 NC |
12511 | |
12512 | void | |
7fa3d080 | 12513 | istack_pop (IStack *stack) |
e0001a05 NC |
12514 | { |
12515 | int rec = stack->ninsn - 1; | |
9c2799c2 | 12516 | gas_assert (!istack_empty (stack)); |
e0001a05 | 12517 | stack->ninsn--; |
60242db2 | 12518 | tinsn_init (&stack->insn[rec]); |
e0001a05 NC |
12519 | } |
12520 | ||
12521 | \f | |
12522 | /* TInsn functions. */ | |
12523 | ||
12524 | void | |
7fa3d080 | 12525 | tinsn_init (TInsn *dst) |
e0001a05 NC |
12526 | { |
12527 | memset (dst, 0, sizeof (TInsn)); | |
12528 | } | |
12529 | ||
12530 | ||
43cd72b9 | 12531 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
12532 | |
12533 | static bfd_boolean | |
7fa3d080 | 12534 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
12535 | { |
12536 | int i; | |
12537 | int n = insn->ntok; | |
12538 | ||
9c2799c2 | 12539 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12540 | |
12541 | for (i = 0; i < n; ++i) | |
12542 | { | |
12543 | switch (insn->tok[i].X_op) | |
12544 | { | |
12545 | case O_register: | |
12546 | case O_constant: | |
12547 | break; | |
12548 | default: | |
12549 | return TRUE; | |
12550 | } | |
12551 | } | |
12552 | return FALSE; | |
12553 | } | |
12554 | ||
12555 | ||
12556 | bfd_boolean | |
7fa3d080 | 12557 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 12558 | { |
43cd72b9 | 12559 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
12560 | int i; |
12561 | int n = insn->ntok; | |
12562 | ||
9c2799c2 | 12563 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12564 | |
12565 | for (i = 0; i < n; ++i) | |
12566 | { | |
12567 | switch (insn->tok[i].X_op) | |
12568 | { | |
12569 | case O_register: | |
12570 | case O_constant: | |
12571 | break; | |
43cd72b9 BW |
12572 | case O_big: |
12573 | case O_illegal: | |
12574 | case O_absent: | |
12575 | /* Errors for these types are caught later. */ | |
12576 | break; | |
12577 | case O_hi16: | |
12578 | case O_lo16: | |
e0001a05 | 12579 | default: |
43cd72b9 BW |
12580 | /* Symbolic immediates are only allowed on the last immediate |
12581 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 12582 | support non-PC-relative relocations. */ |
43cd72b9 BW |
12583 | if (i != get_relaxable_immed (insn->opcode) |
12584 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
12585 | && insn->opcode != xtensa_const16_opcode)) | |
12586 | { | |
431ad2d0 | 12587 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
12588 | return TRUE; |
12589 | } | |
e0001a05 NC |
12590 | } |
12591 | } | |
12592 | return FALSE; | |
12593 | } | |
12594 | ||
12595 | ||
12596 | /* For assembly code with complex expressions (e.g. subtraction), | |
12597 | we have to build them in the literal pool so that | |
12598 | their results are calculated correctly after relaxation. | |
12599 | The relaxation only handles expressions that | |
12600 | boil down to SYMBOL + OFFSET. */ | |
12601 | ||
12602 | static bfd_boolean | |
7fa3d080 | 12603 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
12604 | { |
12605 | int i; | |
12606 | int n = insn->ntok; | |
9c2799c2 | 12607 | gas_assert (insn->insn_type == ITYPE_INSN); |
e0001a05 NC |
12608 | for (i = 0; i < n; ++i) |
12609 | { | |
12610 | switch (insn->tok[i].X_op) | |
12611 | { | |
12612 | case O_register: | |
12613 | case O_constant: | |
12614 | case O_symbol: | |
43cd72b9 BW |
12615 | case O_lo16: |
12616 | case O_hi16: | |
e0001a05 NC |
12617 | break; |
12618 | default: | |
12619 | return TRUE; | |
12620 | } | |
12621 | } | |
12622 | return FALSE; | |
12623 | } | |
12624 | ||
12625 | ||
b2d179be BW |
12626 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
12627 | Return TRUE if there is a symbol in the immediate field. This | |
12628 | function assumes that: | |
12629 | 1) The number of operands are correct. | |
12630 | 2) The insn_type is ITYPE_INSN. | |
12631 | 3) The opcode can be encoded in the specified format and slot. | |
12632 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
12633 | |
12634 | static bfd_boolean | |
7fa3d080 BW |
12635 | tinsn_to_slotbuf (xtensa_format fmt, |
12636 | int slot, | |
12637 | TInsn *tinsn, | |
12638 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
12639 | { |
12640 | xtensa_isa isa = xtensa_default_isa; | |
12641 | xtensa_opcode opcode = tinsn->opcode; | |
12642 | bfd_boolean has_fixup = FALSE; | |
12643 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
12644 | int i; | |
12645 | ||
9c2799c2 | 12646 | gas_assert (tinsn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
12647 | if (noperands != tinsn->ntok) |
12648 | as_fatal (_("operand number mismatch")); | |
12649 | ||
12650 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
12651 | { | |
12652 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
12653 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
12654 | return FALSE; | |
12655 | } | |
12656 | ||
12657 | for (i = 0; i < noperands; i++) | |
12658 | { | |
91d6fa6a | 12659 | expressionS *exp = &tinsn->tok[i]; |
d77b99c9 BW |
12660 | int rc; |
12661 | unsigned line; | |
3b4dbbbf | 12662 | const char *file_name; |
43cd72b9 BW |
12663 | uint32 opnd_value; |
12664 | ||
91d6fa6a | 12665 | switch (exp->X_op) |
43cd72b9 BW |
12666 | { |
12667 | case O_register: | |
12668 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
12669 | break; | |
12670 | /* The register number has already been checked in | |
12671 | expression_maybe_register, so we don't need to check here. */ | |
91d6fa6a | 12672 | opnd_value = exp->X_add_number; |
43cd72b9 BW |
12673 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); |
12674 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
12675 | opnd_value); | |
12676 | if (rc != 0) | |
12677 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
12678 | break; | |
12679 | ||
12680 | case O_constant: | |
12681 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
12682 | break; | |
3b4dbbbf | 12683 | file_name = as_where (&line); |
43cd72b9 BW |
12684 | /* It is a constant and we called this function |
12685 | then we have to try to fit it. */ | |
12686 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
91d6fa6a | 12687 | exp->X_add_number, file_name, line); |
e0001a05 NC |
12688 | break; |
12689 | ||
e0001a05 NC |
12690 | default: |
12691 | has_fixup = TRUE; | |
12692 | break; | |
12693 | } | |
12694 | } | |
43cd72b9 | 12695 | |
e0001a05 NC |
12696 | return has_fixup; |
12697 | } | |
12698 | ||
12699 | ||
b2d179be BW |
12700 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
12701 | into a multi-slot instruction, fill the other slots with NOPs. | |
12702 | Return TRUE if there is a symbol in the immediate field. See also the | |
12703 | assumptions listed for tinsn_to_slotbuf. */ | |
12704 | ||
12705 | static bfd_boolean | |
12706 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
12707 | { | |
12708 | static xtensa_insnbuf slotbuf = 0; | |
12709 | static vliw_insn vinsn; | |
12710 | xtensa_isa isa = xtensa_default_isa; | |
12711 | bfd_boolean has_fixup = FALSE; | |
12712 | int i; | |
12713 | ||
12714 | if (!slotbuf) | |
12715 | { | |
12716 | slotbuf = xtensa_insnbuf_alloc (isa); | |
12717 | xg_init_vinsn (&vinsn); | |
12718 | } | |
12719 | ||
12720 | xg_clear_vinsn (&vinsn); | |
12721 | ||
12722 | bundle_tinsn (tinsn, &vinsn); | |
12723 | ||
12724 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
12725 | ||
12726 | for (i = 0; i < vinsn.num_slots; i++) | |
12727 | { | |
12728 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
12729 | has_fixup |= | |
12730 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
12731 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
12732 | } | |
12733 | ||
12734 | return has_fixup; | |
12735 | } | |
12736 | ||
12737 | ||
43cd72b9 | 12738 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 12739 | |
7fa3d080 BW |
12740 | static bfd_boolean |
12741 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
12742 | { |
12743 | xtensa_isa isa = xtensa_default_isa; | |
12744 | xtensa_opcode opcode = insn->opcode; | |
6dc6b655 BW |
12745 | xtensa_regfile t1_regfile, t2_regfile; |
12746 | int t1_reg, t2_reg; | |
12747 | int t1_base_reg, t1_last_reg; | |
12748 | int t2_base_reg, t2_last_reg; | |
12749 | char t1_inout, t2_inout; | |
12750 | int i, j; | |
e0001a05 NC |
12751 | |
12752 | if (opcode == XTENSA_UNDEFINED) | |
12753 | { | |
12754 | as_bad (_("invalid opcode")); | |
12755 | return TRUE; | |
12756 | } | |
12757 | ||
43cd72b9 | 12758 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
12759 | { |
12760 | as_bad (_("too few operands")); | |
12761 | return TRUE; | |
12762 | } | |
12763 | ||
43cd72b9 | 12764 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
12765 | { |
12766 | as_bad (_("too many operands")); | |
12767 | return TRUE; | |
12768 | } | |
6dc6b655 BW |
12769 | |
12770 | /* Check registers. */ | |
12771 | for (j = 0; j < insn->ntok; j++) | |
12772 | { | |
12773 | if (xtensa_operand_is_register (isa, insn->opcode, j) != 1) | |
12774 | continue; | |
12775 | ||
12776 | t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j); | |
12777 | t2_base_reg = insn->tok[j].X_add_number; | |
12778 | t2_last_reg | |
12779 | = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j); | |
12780 | ||
12781 | for (i = 0; i < insn->ntok; i++) | |
12782 | { | |
12783 | if (i == j) | |
12784 | continue; | |
12785 | ||
12786 | if (xtensa_operand_is_register (isa, insn->opcode, i) != 1) | |
12787 | continue; | |
12788 | ||
12789 | t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i); | |
12790 | ||
12791 | if (t1_regfile != t2_regfile) | |
12792 | continue; | |
12793 | ||
12794 | t1_inout = xtensa_operand_inout (isa, insn->opcode, i); | |
12795 | t2_inout = xtensa_operand_inout (isa, insn->opcode, j); | |
12796 | ||
12797 | t1_base_reg = insn->tok[i].X_add_number; | |
12798 | t1_last_reg = (t1_base_reg | |
12799 | + xtensa_operand_num_regs (isa, insn->opcode, i)); | |
12800 | ||
12801 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
12802 | { | |
12803 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
12804 | { | |
12805 | if (t1_reg != t2_reg) | |
12806 | continue; | |
12807 | ||
12808 | if (t1_inout != 'i' && t2_inout != 'i') | |
12809 | { | |
12810 | as_bad (_("multiple writes to the same register")); | |
12811 | return TRUE; | |
12812 | } | |
12813 | } | |
12814 | } | |
12815 | } | |
12816 | } | |
e0001a05 NC |
12817 | return FALSE; |
12818 | } | |
12819 | ||
12820 | ||
12821 | /* Load an instruction from its encoded form. */ | |
12822 | ||
12823 | static void | |
7fa3d080 | 12824 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 12825 | { |
43cd72b9 | 12826 | vliw_insn vinsn; |
e0001a05 | 12827 | |
43cd72b9 BW |
12828 | xg_init_vinsn (&vinsn); |
12829 | vinsn_from_chars (&vinsn, f); | |
12830 | ||
12831 | *tinsn = vinsn.slots[slot]; | |
12832 | xg_free_vinsn (&vinsn); | |
12833 | } | |
e0001a05 | 12834 | |
43cd72b9 BW |
12835 | |
12836 | static void | |
7fa3d080 BW |
12837 | tinsn_from_insnbuf (TInsn *tinsn, |
12838 | xtensa_insnbuf slotbuf, | |
12839 | xtensa_format fmt, | |
12840 | int slot) | |
43cd72b9 BW |
12841 | { |
12842 | int i; | |
12843 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
12844 | |
12845 | /* Find the immed. */ | |
43cd72b9 BW |
12846 | tinsn_init (tinsn); |
12847 | tinsn->insn_type = ITYPE_INSN; | |
12848 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
12849 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
12850 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
12851 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 12852 | { |
43cd72b9 BW |
12853 | set_expr_const (&tinsn->tok[i], |
12854 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
12855 | tinsn->opcode, i)); | |
e0001a05 NC |
12856 | } |
12857 | } | |
12858 | ||
12859 | ||
12860 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
12861 | ||
12862 | static void | |
7fa3d080 | 12863 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 12864 | { |
43cd72b9 | 12865 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
12866 | int opnum; |
12867 | ||
43cd72b9 | 12868 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
12869 | { |
12870 | opnum = get_relaxable_immed (opcode); | |
9c2799c2 | 12871 | gas_assert (opnum >= 0); |
e7da6241 BW |
12872 | set_expr_symbol_offset (&tinsn->tok[opnum], |
12873 | fragP->tc_frag_data.slot_symbols[slot], | |
12874 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 | 12875 | } |
19e8f41a | 12876 | tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot]; |
e0001a05 NC |
12877 | } |
12878 | ||
12879 | ||
12880 | static int | |
7fa3d080 | 12881 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
12882 | { |
12883 | int i; | |
12884 | int text_bytes = 0; | |
12885 | ||
12886 | for (i = 0; i < istack->ninsn; i++) | |
12887 | { | |
43cd72b9 BW |
12888 | TInsn *tinsn = &istack->insn[i]; |
12889 | if (tinsn->insn_type == ITYPE_INSN) | |
12890 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
12891 | } |
12892 | return text_bytes; | |
12893 | } | |
12894 | ||
12895 | ||
12896 | static int | |
7fa3d080 | 12897 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
12898 | { |
12899 | int i; | |
12900 | int lit_bytes = 0; | |
12901 | ||
12902 | for (i = 0; i < istack->ninsn; i++) | |
12903 | { | |
43cd72b9 BW |
12904 | TInsn *tinsn = &istack->insn[i]; |
12905 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
12906 | lit_bytes += 4; |
12907 | } | |
12908 | return lit_bytes; | |
12909 | } | |
12910 | ||
43cd72b9 BW |
12911 | \f |
12912 | /* vliw_insn functions. */ | |
12913 | ||
7fa3d080 BW |
12914 | static void |
12915 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12916 | { |
12917 | int i; | |
12918 | xtensa_isa isa = xtensa_default_isa; | |
12919 | ||
12920 | xg_clear_vinsn (v); | |
12921 | ||
12922 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
12923 | if (v->insnbuf == NULL) | |
12924 | as_fatal (_("out of memory")); | |
12925 | ||
62af60e2 | 12926 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 | 12927 | { |
43cd72b9 BW |
12928 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
12929 | if (v->slotbuf[i] == NULL) | |
12930 | as_fatal (_("out of memory")); | |
12931 | } | |
12932 | } | |
12933 | ||
12934 | ||
7fa3d080 BW |
12935 | static void |
12936 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12937 | { |
12938 | int i; | |
65738a7d | 12939 | |
3739860c | 12940 | memset (v, 0, offsetof (vliw_insn, slots) |
62af60e2 | 12941 | + sizeof(TInsn) * config_max_slots); |
65738a7d | 12942 | |
43cd72b9 BW |
12943 | v->format = XTENSA_UNDEFINED; |
12944 | v->num_slots = 0; | |
12945 | v->inside_bundle = FALSE; | |
12946 | ||
12947 | if (xt_saved_debug_type != DEBUG_NONE) | |
12948 | debug_type = xt_saved_debug_type; | |
12949 | ||
62af60e2 | 12950 | for (i = 0; i < config_max_slots; i++) |
65738a7d | 12951 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
12952 | } |
12953 | ||
12954 | ||
d8392fd9 SA |
12955 | static void |
12956 | xg_copy_vinsn (vliw_insn *dst, vliw_insn *src) | |
12957 | { | |
3739860c | 12958 | memcpy (dst, src, |
d8392fd9 SA |
12959 | offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn)); |
12960 | dst->insnbuf = src->insnbuf; | |
12961 | memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf)); | |
12962 | } | |
12963 | ||
12964 | ||
7fa3d080 BW |
12965 | static bfd_boolean |
12966 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
12967 | { |
12968 | int i; | |
c138bc38 | 12969 | |
43cd72b9 BW |
12970 | for (i = 0; i < v->num_slots; i++) |
12971 | { | |
12972 | if (v->slots[i].is_specific_opcode) | |
12973 | return TRUE; | |
12974 | } | |
12975 | return FALSE; | |
12976 | } | |
12977 | ||
12978 | ||
7fa3d080 BW |
12979 | static void |
12980 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
12981 | { |
12982 | int i; | |
12983 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
62af60e2 | 12984 | for (i = 0; i < config_max_slots; i++) |
43cd72b9 BW |
12985 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); |
12986 | } | |
12987 | ||
12988 | ||
e7da6241 BW |
12989 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
12990 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
12991 | |
12992 | static bfd_boolean | |
7fa3d080 BW |
12993 | vinsn_to_insnbuf (vliw_insn *vinsn, |
12994 | char *frag_offset, | |
12995 | fragS *fragP, | |
12996 | bfd_boolean record_fixup) | |
43cd72b9 BW |
12997 | { |
12998 | xtensa_isa isa = xtensa_default_isa; | |
12999 | xtensa_format fmt = vinsn->format; | |
13000 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
13001 | int slot; | |
13002 | bfd_boolean has_fixup = FALSE; | |
13003 | ||
13004 | xtensa_format_encode (isa, fmt, insnbuf); | |
13005 | ||
13006 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
13007 | { | |
13008 | TInsn *tinsn = &vinsn->slots[slot]; | |
19e8f41a | 13009 | expressionS *extra_arg = &tinsn->extra_arg; |
43cd72b9 BW |
13010 | bfd_boolean tinsn_has_fixup = |
13011 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
13012 | vinsn->slotbuf[slot]); | |
13013 | ||
13014 | xtensa_format_set_slot (isa, fmt, slot, | |
13015 | insnbuf, vinsn->slotbuf[slot]); | |
19e8f41a | 13016 | if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register) |
28dbbc02 BW |
13017 | { |
13018 | if (vinsn->num_slots != 1) | |
13019 | as_bad (_("TLS relocation not allowed in FLIX bundle")); | |
13020 | else if (record_fixup) | |
13021 | /* Instructions that generate TLS relocations should always be | |
13022 | relaxed in the front-end. If "record_fixup" is set, then this | |
13023 | function is being called during back-end relaxation, so flag | |
13024 | the unexpected behavior as an error. */ | |
13025 | as_bad (_("unexpected TLS relocation")); | |
13026 | else | |
13027 | fix_new (fragP, frag_offset - fragP->fr_literal, | |
13028 | xtensa_format_length (isa, fmt), | |
19e8f41a BW |
13029 | extra_arg->X_add_symbol, extra_arg->X_add_number, |
13030 | FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE)); | |
28dbbc02 | 13031 | } |
e7da6241 | 13032 | if (tinsn_has_fixup) |
43cd72b9 BW |
13033 | { |
13034 | int i; | |
13035 | xtensa_opcode opcode = tinsn->opcode; | |
13036 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
13037 | has_fixup = TRUE; | |
13038 | ||
13039 | for (i = 0; i < noperands; i++) | |
13040 | { | |
91d6fa6a NC |
13041 | expressionS* exp = &tinsn->tok[i]; |
13042 | switch (exp->X_op) | |
43cd72b9 BW |
13043 | { |
13044 | case O_symbol: | |
13045 | case O_lo16: | |
13046 | case O_hi16: | |
13047 | if (get_relaxable_immed (opcode) == i) | |
13048 | { | |
e7da6241 BW |
13049 | /* Add a fix record for the instruction, except if this |
13050 | function is being called prior to relaxation, i.e., | |
13051 | if record_fixup is false, and the instruction might | |
13052 | be relaxed later. */ | |
13053 | if (record_fixup | |
13054 | || tinsn->is_specific_opcode | |
13055 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 13056 | { |
91d6fa6a | 13057 | xg_add_opcode_fix (tinsn, i, fmt, slot, exp, fragP, |
e7da6241 | 13058 | frag_offset - fragP->fr_literal); |
43cd72b9 BW |
13059 | } |
13060 | else | |
13061 | { | |
91d6fa6a | 13062 | if (exp->X_op != O_symbol) |
e7da6241 | 13063 | as_bad (_("invalid operand")); |
91d6fa6a NC |
13064 | tinsn->symbol = exp->X_add_symbol; |
13065 | tinsn->offset = exp->X_add_number; | |
43cd72b9 BW |
13066 | } |
13067 | } | |
13068 | else | |
e7da6241 | 13069 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
13070 | break; |
13071 | ||
13072 | case O_constant: | |
13073 | case O_register: | |
13074 | break; | |
13075 | ||
43cd72b9 | 13076 | default: |
e7da6241 | 13077 | as_bad (_("expression too complex")); |
43cd72b9 BW |
13078 | break; |
13079 | } | |
13080 | } | |
13081 | } | |
13082 | } | |
13083 | ||
13084 | return has_fixup; | |
13085 | } | |
13086 | ||
13087 | ||
13088 | static void | |
7fa3d080 | 13089 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
13090 | { |
13091 | static xtensa_insnbuf insnbuf = NULL; | |
13092 | static xtensa_insnbuf slotbuf = NULL; | |
13093 | int i; | |
13094 | xtensa_format fmt; | |
13095 | xtensa_isa isa = xtensa_default_isa; | |
13096 | ||
13097 | if (!insnbuf) | |
13098 | { | |
13099 | insnbuf = xtensa_insnbuf_alloc (isa); | |
13100 | slotbuf = xtensa_insnbuf_alloc (isa); | |
13101 | } | |
13102 | ||
d77b99c9 | 13103 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
13104 | fmt = xtensa_format_decode (isa, insnbuf); |
13105 | if (fmt == XTENSA_UNDEFINED) | |
13106 | as_fatal (_("cannot decode instruction format")); | |
13107 | vinsn->format = fmt; | |
13108 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
13109 | ||
13110 | for (i = 0; i < vinsn->num_slots; i++) | |
13111 | { | |
13112 | TInsn *tinsn = &vinsn->slots[i]; | |
13113 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
13114 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
13115 | } | |
13116 | } | |
13117 | ||
e0001a05 NC |
13118 | \f |
13119 | /* Expression utilities. */ | |
13120 | ||
43cd72b9 | 13121 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
13122 | |
13123 | bfd_boolean | |
7fa3d080 | 13124 | expr_is_const (const expressionS *s) |
e0001a05 NC |
13125 | { |
13126 | return (s->X_op == O_constant); | |
13127 | } | |
13128 | ||
13129 | ||
13130 | /* Get the expression constant. | |
43cd72b9 | 13131 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
13132 | |
13133 | offsetT | |
7fa3d080 | 13134 | get_expr_const (const expressionS *s) |
e0001a05 | 13135 | { |
9c2799c2 | 13136 | gas_assert (expr_is_const (s)); |
e0001a05 NC |
13137 | return s->X_add_number; |
13138 | } | |
13139 | ||
13140 | ||
13141 | /* Set the expression to a constant value. */ | |
13142 | ||
13143 | void | |
7fa3d080 | 13144 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
13145 | { |
13146 | s->X_op = O_constant; | |
13147 | s->X_add_number = val; | |
13148 | s->X_add_symbol = NULL; | |
13149 | s->X_op_symbol = NULL; | |
13150 | } | |
13151 | ||
13152 | ||
43cd72b9 | 13153 | bfd_boolean |
7fa3d080 | 13154 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
13155 | { |
13156 | return (s->X_op == O_register); | |
13157 | } | |
13158 | ||
13159 | ||
13160 | /* Get the expression constant. | |
13161 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
13162 | ||
13163 | offsetT | |
7fa3d080 | 13164 | get_expr_register (const expressionS *s) |
43cd72b9 | 13165 | { |
9c2799c2 | 13166 | gas_assert (expr_is_register (s)); |
43cd72b9 BW |
13167 | return s->X_add_number; |
13168 | } | |
13169 | ||
13170 | ||
e0001a05 NC |
13171 | /* Set the expression to a symbol + constant offset. */ |
13172 | ||
13173 | void | |
7fa3d080 | 13174 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
13175 | { |
13176 | s->X_op = O_symbol; | |
13177 | s->X_add_symbol = sym; | |
13178 | s->X_op_symbol = NULL; /* unused */ | |
13179 | s->X_add_number = offset; | |
13180 | } | |
13181 | ||
13182 | ||
43cd72b9 BW |
13183 | /* Return TRUE if the two expressions are equal. */ |
13184 | ||
e0001a05 | 13185 | bfd_boolean |
7fa3d080 | 13186 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
13187 | { |
13188 | if (s1->X_op != s2->X_op) | |
13189 | return FALSE; | |
13190 | if (s1->X_add_symbol != s2->X_add_symbol) | |
13191 | return FALSE; | |
13192 | if (s1->X_op_symbol != s2->X_op_symbol) | |
13193 | return FALSE; | |
13194 | if (s1->X_add_number != s2->X_add_number) | |
13195 | return FALSE; | |
13196 | return TRUE; | |
13197 | } | |
13198 | ||
13199 | ||
13200 | static void | |
7fa3d080 | 13201 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
13202 | { |
13203 | memcpy (dst, src, sizeof (expressionS)); | |
13204 | } | |
13205 | ||
13206 | \f | |
9456465c | 13207 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
13208 | |
13209 | struct rename_section_struct | |
13210 | { | |
e4a0c708 | 13211 | const char *old_name; |
e0001a05 NC |
13212 | char *new_name; |
13213 | struct rename_section_struct *next; | |
13214 | }; | |
13215 | ||
13216 | static struct rename_section_struct *section_rename; | |
13217 | ||
13218 | ||
9456465c BW |
13219 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
13220 | entries to the section_rename list. Note: Specifying multiple | |
13221 | renamings separated by colons is not documented and is retained only | |
13222 | for backward compatibility. */ | |
e0001a05 | 13223 | |
7fa3d080 BW |
13224 | static void |
13225 | build_section_rename (const char *arg) | |
e0001a05 | 13226 | { |
9456465c | 13227 | struct rename_section_struct *r; |
e0001a05 NC |
13228 | char *this_arg = NULL; |
13229 | char *next_arg = NULL; | |
13230 | ||
9456465c | 13231 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 13232 | { |
9456465c BW |
13233 | char *old_name, *new_name; |
13234 | ||
e0001a05 NC |
13235 | if (this_arg) |
13236 | { | |
13237 | next_arg = strchr (this_arg, ':'); | |
13238 | if (next_arg) | |
13239 | { | |
13240 | *next_arg = '\0'; | |
13241 | next_arg++; | |
13242 | } | |
13243 | } | |
e0001a05 | 13244 | |
9456465c BW |
13245 | old_name = this_arg; |
13246 | new_name = strchr (this_arg, '='); | |
e0001a05 | 13247 | |
9456465c BW |
13248 | if (*old_name == '\0') |
13249 | { | |
13250 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
13251 | continue; | |
13252 | } | |
13253 | if (!new_name || new_name[1] == '\0') | |
13254 | { | |
13255 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
13256 | old_name); | |
13257 | continue; | |
13258 | } | |
13259 | *new_name = '\0'; | |
13260 | new_name++; | |
e0001a05 | 13261 | |
9456465c BW |
13262 | /* Check for invalid section renaming. */ |
13263 | for (r = section_rename; r != NULL; r = r->next) | |
13264 | { | |
13265 | if (strcmp (r->old_name, old_name) == 0) | |
13266 | as_bad (_("section %s renamed multiple times"), old_name); | |
13267 | if (strcmp (r->new_name, new_name) == 0) | |
13268 | as_bad (_("multiple sections remapped to output section %s"), | |
13269 | new_name); | |
13270 | } | |
e0001a05 | 13271 | |
9456465c | 13272 | /* Now add it. */ |
325801bd | 13273 | r = XNEW (struct rename_section_struct); |
9456465c BW |
13274 | r->old_name = xstrdup (old_name); |
13275 | r->new_name = xstrdup (new_name); | |
13276 | r->next = section_rename; | |
13277 | section_rename = r; | |
e0001a05 | 13278 | } |
e0001a05 NC |
13279 | } |
13280 | ||
13281 | ||
9456465c | 13282 | char * |
e4a0c708 | 13283 | xtensa_section_rename (const char *name) |
e0001a05 NC |
13284 | { |
13285 | struct rename_section_struct *r = section_rename; | |
13286 | ||
13287 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
13288 | { |
13289 | if (strcmp (r->old_name, name) == 0) | |
13290 | return r->new_name; | |
13291 | } | |
e0001a05 | 13292 | |
e4a0c708 | 13293 | return (char *) name; |
e0001a05 | 13294 | } |