Commit | Line | Data |
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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
d47d412e | 2 | Copyright 2003, 2004, 2005, 2006 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 NC |
20 | |
21 | #include <string.h> | |
43cd72b9 | 22 | #include <limits.h> |
e0001a05 NC |
23 | #include "as.h" |
24 | #include "sb.h" | |
25 | #include "safe-ctype.h" | |
26 | #include "tc-xtensa.h" | |
27 | #include "frags.h" | |
28 | #include "subsegs.h" | |
29 | #include "xtensa-relax.h" | |
30 | #include "xtensa-istack.h" | |
cda2eb9e | 31 | #include "dwarf2dbg.h" |
e0001a05 NC |
32 | #include "struc-symbol.h" |
33 | #include "xtensa-config.h" | |
34 | ||
35 | #ifndef uint32 | |
36 | #define uint32 unsigned int | |
37 | #endif | |
38 | #ifndef int32 | |
39 | #define int32 signed int | |
40 | #endif | |
41 | ||
42 | /* Notes: | |
43 | ||
e0001a05 NC |
44 | Naming conventions (used somewhat inconsistently): |
45 | The xtensa_ functions are exported | |
46 | The xg_ functions are internal | |
47 | ||
48 | We also have a couple of different extensibility mechanisms. | |
49 | 1) The idiom replacement: | |
50 | This is used when a line is first parsed to | |
51 | replace an instruction pattern with another instruction | |
52 | It is currently limited to replacements of instructions | |
53 | with constant operands. | |
54 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
55 | replacement patterns. When an instruction's immediate field | |
56 | does not fit the next instruction sequence is attempted. | |
57 | In addition, "narrow" opcodes are supported this way. */ | |
58 | ||
59 | ||
60 | /* Define characters with special meanings to GAS. */ | |
61 | const char comment_chars[] = "#"; | |
62 | const char line_comment_chars[] = "#"; | |
63 | const char line_separator_chars[] = ";"; | |
64 | const char EXP_CHARS[] = "eE"; | |
65 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
66 | ||
67 | ||
43cd72b9 BW |
68 | /* Flags to indicate whether the hardware supports the density and |
69 | absolute literals options. */ | |
e0001a05 | 70 | |
e0001a05 | 71 | bfd_boolean density_supported = XCHAL_HAVE_DENSITY; |
43cd72b9 BW |
72 | bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; |
73 | ||
74 | /* Maximum width we would pad an unreachable frag to get alignment. */ | |
75 | #define UNREACHABLE_MAX_WIDTH 8 | |
e0001a05 | 76 | |
43cd72b9 BW |
77 | static vliw_insn cur_vinsn; |
78 | ||
d77b99c9 | 79 | unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; |
43cd72b9 BW |
80 | |
81 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
82 | ||
83 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 84 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
85 | back end. */ |
86 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
87 | |
88 | /* Flags for properties of the last instruction in a segment. */ | |
89 | #define FLAG_IS_A0_WRITER 0x1 | |
90 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
91 | ||
92 | ||
93 | /* We define a special segment names ".literal" to place literals | |
94 | into. The .fini and .init sections are special because they | |
95 | contain code that is moved together by the linker. We give them | |
96 | their own special .fini.literal and .init.literal sections. */ | |
97 | ||
98 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 99 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 NC |
100 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
101 | #define INIT_SECTION_NAME xtensa_section_rename (".init") | |
102 | #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal") | |
103 | #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal") | |
104 | ||
105 | ||
43cd72b9 | 106 | /* This type is used for the directive_stack to keep track of the |
e0001a05 NC |
107 | state of the literal collection pools. */ |
108 | ||
109 | typedef struct lit_state_struct | |
110 | { | |
111 | const char *lit_seg_name; | |
43cd72b9 | 112 | const char *lit4_seg_name; |
e0001a05 NC |
113 | const char *init_lit_seg_name; |
114 | const char *fini_lit_seg_name; | |
115 | segT lit_seg; | |
43cd72b9 | 116 | segT lit4_seg; |
e0001a05 NC |
117 | segT init_lit_seg; |
118 | segT fini_lit_seg; | |
119 | } lit_state; | |
120 | ||
121 | static lit_state default_lit_sections; | |
122 | ||
123 | ||
124 | /* We keep lists of literal segments. The seg_list type is the node | |
125 | for such a list. The *_literal_head locals are the heads of the | |
126 | various lists. All of these lists have a dummy node at the start. */ | |
127 | ||
128 | typedef struct seg_list_struct | |
129 | { | |
130 | struct seg_list_struct *next; | |
131 | segT seg; | |
132 | } seg_list; | |
133 | ||
134 | static seg_list literal_head_h; | |
135 | static seg_list *literal_head = &literal_head_h; | |
136 | static seg_list init_literal_head_h; | |
137 | static seg_list *init_literal_head = &init_literal_head_h; | |
138 | static seg_list fini_literal_head_h; | |
139 | static seg_list *fini_literal_head = &fini_literal_head_h; | |
140 | ||
141 | ||
82e7541d BW |
142 | /* Lists of symbols. We keep a list of symbols that label the current |
143 | instruction, so that we can adjust the symbols when inserting alignment | |
144 | for various instructions. We also keep a list of all the symbols on | |
145 | literals, so that we can fix up those symbols when the literals are | |
146 | later moved into the text sections. */ | |
147 | ||
148 | typedef struct sym_list_struct | |
149 | { | |
150 | struct sym_list_struct *next; | |
151 | symbolS *sym; | |
152 | } sym_list; | |
153 | ||
154 | static sym_list *insn_labels = NULL; | |
155 | static sym_list *free_insn_labels = NULL; | |
156 | static sym_list *saved_insn_labels = NULL; | |
157 | ||
158 | static sym_list *literal_syms; | |
159 | ||
160 | ||
43cd72b9 BW |
161 | /* Flags to determine whether to prefer const16 or l32r |
162 | if both options are available. */ | |
163 | int prefer_const16 = 0; | |
164 | int prefer_l32r = 0; | |
165 | ||
e0001a05 NC |
166 | /* Global flag to indicate when we are emitting literals. */ |
167 | int generating_literals = 0; | |
168 | ||
43cd72b9 BW |
169 | /* The following PROPERTY table definitions are copied from |
170 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
171 | ||
172 | /* Flags in the property tables to specify whether blocks of memory | |
173 | are literals, instructions, data, or unreachable. For | |
174 | instructions, blocks that begin loop targets and branch targets are | |
175 | designated. Blocks that do not allow density, instruction | |
176 | reordering or transformation are also specified. Finally, for | |
177 | branch targets, branch target alignment priority is included. | |
178 | Alignment of the next block is specified in the current block | |
179 | and the size of the current block does not include any fill required | |
180 | to align to the next block. */ | |
181 | ||
182 | #define XTENSA_PROP_LITERAL 0x00000001 | |
183 | #define XTENSA_PROP_INSN 0x00000002 | |
184 | #define XTENSA_PROP_DATA 0x00000004 | |
185 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
186 | /* Instruction only properties at beginning of code. */ | |
187 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
188 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
189 | /* Instruction only properties about code. */ | |
190 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
191 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
192 | #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100 | |
193 | ||
194 | /* Branch target alignment information. This transmits information | |
195 | to the linker optimization about the priority of aligning a | |
196 | particular block for branch target alignment: None, low priority, | |
197 | high priority, or required. These only need to be checked in | |
198 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
199 | Common usage is | |
200 | ||
201 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
202 | case XTENSA_PROP_BT_ALIGN_NONE: | |
203 | case XTENSA_PROP_BT_ALIGN_LOW: | |
204 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
205 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
206 | */ | |
207 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
208 | ||
209 | /* No branch target alignment. */ | |
210 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
211 | /* Low priority branch target alignment. */ | |
212 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
213 | /* High priority branch target alignment. */ | |
214 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
215 | /* Required branch target alignment. */ | |
216 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
217 | ||
218 | #define GET_XTENSA_PROP_BT_ALIGN(flag) \ | |
219 | (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) | |
220 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ | |
221 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
222 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
223 | ||
224 | ||
225 | /* Alignment is specified in the block BEFORE the one that needs | |
226 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
227 | get the required alignment specified as a power of 2. Use | |
228 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
229 | alignment. Be careful of side effects since the SET will evaluate | |
230 | flags twice. Also, note that the SIZE of a block in the property | |
231 | table does not include the alignment size, so the alignment fill | |
232 | must be calculated to determine if two blocks are contiguous. | |
233 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
234 | possible future implementation. */ | |
235 | ||
236 | #define XTENSA_PROP_ALIGN 0x00000800 | |
237 | ||
238 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
239 | ||
240 | #define GET_XTENSA_PROP_ALIGNMENT(flag) \ | |
241 | (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) | |
242 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ | |
243 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
244 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
245 | ||
246 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
247 | ||
248 | ||
249 | /* Structure for saving instruction and alignment per-fragment data | |
250 | that will be written to the object file. This structure is | |
251 | equivalent to the actual data that will be written out to the file | |
252 | but is easier to use. We provide a conversion to file flags | |
253 | in frag_flags_to_number. */ | |
254 | ||
255 | typedef struct frag_flags_struct frag_flags; | |
256 | ||
257 | struct frag_flags_struct | |
258 | { | |
259 | /* is_literal should only be used after xtensa_move_literals. | |
260 | If you need to check if you are generating a literal fragment, | |
261 | then use the generating_literals global. */ | |
262 | ||
263 | unsigned is_literal : 1; | |
264 | unsigned is_insn : 1; | |
265 | unsigned is_data : 1; | |
266 | unsigned is_unreachable : 1; | |
267 | ||
268 | struct | |
269 | { | |
270 | unsigned is_loop_target : 1; | |
271 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
272 | unsigned bt_align_priority : 2; | |
273 | ||
274 | unsigned is_no_density : 1; | |
275 | /* no_longcalls flag does not need to be placed in the object file. */ | |
276 | /* is_specific_opcode implies no_transform. */ | |
277 | unsigned is_no_transform : 1; | |
278 | ||
279 | unsigned is_no_reorder : 1; | |
280 | ||
281 | /* Uses absolute literal addressing for l32r. */ | |
282 | unsigned is_abslit : 1; | |
283 | } insn; | |
284 | unsigned is_align : 1; | |
285 | unsigned alignment : 5; | |
286 | }; | |
287 | ||
288 | ||
289 | /* Structure for saving information about a block of property data | |
290 | for frags that have the same flags. */ | |
291 | struct xtensa_block_info_struct | |
292 | { | |
293 | segT sec; | |
294 | bfd_vma offset; | |
295 | size_t size; | |
296 | frag_flags flags; | |
297 | struct xtensa_block_info_struct *next; | |
298 | }; | |
299 | ||
e0001a05 NC |
300 | |
301 | /* Structure for saving the current state before emitting literals. */ | |
302 | typedef struct emit_state_struct | |
303 | { | |
304 | const char *name; | |
305 | segT now_seg; | |
306 | subsegT now_subseg; | |
307 | int generating_literals; | |
308 | } emit_state; | |
309 | ||
310 | ||
43cd72b9 BW |
311 | /* Opcode placement information */ |
312 | ||
313 | typedef unsigned long long bitfield; | |
314 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
315 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
316 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
317 | ||
318 | #define MAX_FORMATS 32 | |
319 | ||
320 | typedef struct op_placement_info_struct | |
321 | { | |
322 | int num_formats; | |
323 | /* A number describing how restrictive the issue is for this | |
324 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 325 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 326 | only one format but many slots in that format. The most |
c138bc38 | 327 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
328 | format. */ |
329 | int issuef; | |
43cd72b9 | 330 | xtensa_format narrowest; |
43cd72b9 | 331 | char narrowest_size; |
b2d179be | 332 | char narrowest_slot; |
43cd72b9 BW |
333 | |
334 | /* formats is a bitfield with the Nth bit set | |
335 | if the opcode fits in the Nth xtensa_format. */ | |
336 | bitfield formats; | |
337 | ||
338 | /* slots[N]'s Mth bit is set if the op fits in the | |
339 | Mth slot of the Nth xtensa_format. */ | |
340 | bitfield slots[MAX_FORMATS]; | |
341 | ||
342 | /* A count of the number of slots in a given format | |
343 | an op can fit (i.e., the bitcount of the slot field above). */ | |
344 | char slots_in_format[MAX_FORMATS]; | |
345 | ||
346 | } op_placement_info, *op_placement_info_table; | |
347 | ||
348 | op_placement_info_table op_placement_table; | |
349 | ||
350 | ||
351 | /* Extra expression types. */ | |
352 | ||
353 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
354 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
355 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
356 | ||
357 | ||
e0001a05 NC |
358 | /* Directives. */ |
359 | ||
360 | typedef enum | |
361 | { | |
362 | directive_none = 0, | |
363 | directive_literal, | |
364 | directive_density, | |
43cd72b9 | 365 | directive_transform, |
e0001a05 NC |
366 | directive_freeregs, |
367 | directive_longcalls, | |
43cd72b9 BW |
368 | directive_literal_prefix, |
369 | directive_schedule, | |
370 | directive_absolute_literals, | |
371 | directive_last_directive | |
e0001a05 NC |
372 | } directiveE; |
373 | ||
374 | typedef struct | |
375 | { | |
376 | const char *name; | |
377 | bfd_boolean can_be_negated; | |
378 | } directive_infoS; | |
379 | ||
380 | const directive_infoS directive_info[] = | |
381 | { | |
43cd72b9 BW |
382 | { "none", FALSE }, |
383 | { "literal", FALSE }, | |
384 | { "density", TRUE }, | |
385 | { "transform", TRUE }, | |
386 | { "freeregs", FALSE }, | |
387 | { "longcalls", TRUE }, | |
388 | { "literal_prefix", FALSE }, | |
389 | { "schedule", TRUE }, | |
390 | { "absolute-literals", TRUE } | |
e0001a05 NC |
391 | }; |
392 | ||
393 | bfd_boolean directive_state[] = | |
394 | { | |
395 | FALSE, /* none */ | |
396 | FALSE, /* literal */ | |
43cd72b9 | 397 | #if !XCHAL_HAVE_DENSITY |
e0001a05 NC |
398 | FALSE, /* density */ |
399 | #else | |
400 | TRUE, /* density */ | |
401 | #endif | |
43cd72b9 | 402 | TRUE, /* transform */ |
e0001a05 NC |
403 | FALSE, /* freeregs */ |
404 | FALSE, /* longcalls */ | |
43cd72b9 BW |
405 | FALSE, /* literal_prefix */ |
406 | TRUE, /* schedule */ | |
407 | #if XSHAL_USE_ABSOLUTE_LITERALS | |
408 | TRUE /* absolute_literals */ | |
409 | #else | |
410 | FALSE /* absolute_literals */ | |
411 | #endif | |
e0001a05 NC |
412 | }; |
413 | ||
e0001a05 NC |
414 | |
415 | /* Directive functions. */ | |
416 | ||
7fa3d080 BW |
417 | static void xtensa_begin_directive (int); |
418 | static void xtensa_end_directive (int); | |
7fa3d080 BW |
419 | static void xtensa_literal_prefix (char const *, int); |
420 | static void xtensa_literal_position (int); | |
421 | static void xtensa_literal_pseudo (int); | |
422 | static void xtensa_frequency_pseudo (int); | |
423 | static void xtensa_elf_cons (int); | |
e0001a05 | 424 | |
7fa3d080 | 425 | /* Parsing and Idiom Translation. */ |
e0001a05 | 426 | |
7fa3d080 | 427 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 428 | |
e0001a05 NC |
429 | /* Various Other Internal Functions. */ |
430 | ||
84b08ed9 BW |
431 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
432 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
433 | static void xtensa_mark_literal_pool_location (void); |
434 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
435 | static fragS *get_literal_pool_location (segT); | |
436 | static void set_literal_pool_location (segT, fragS *); | |
437 | static void xtensa_set_frag_assembly_state (fragS *); | |
438 | static void finish_vinsn (vliw_insn *); | |
439 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 440 | static int total_frag_text_expansion (fragS *); |
e0001a05 NC |
441 | |
442 | /* Alignment Functions. */ | |
443 | ||
d77b99c9 BW |
444 | static int get_text_align_power (unsigned); |
445 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 446 | static int branch_align_power (segT); |
e0001a05 NC |
447 | |
448 | /* Helpers for xtensa_relax_frag(). */ | |
449 | ||
7fa3d080 | 450 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 451 | |
b08b5071 | 452 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 453 | |
7fa3d080 BW |
454 | static unsigned get_last_insn_flags (segT, subsegT); |
455 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
456 | static float get_subseg_total_freq (segT, subsegT); |
457 | static float get_subseg_target_freq (segT, subsegT); | |
458 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
459 | |
460 | /* Segment list functions. */ | |
461 | ||
7fa3d080 BW |
462 | static void xtensa_move_literals (void); |
463 | static void xtensa_reorder_segments (void); | |
464 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
465 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
466 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
467 | static void xtensa_restore_emit_state (emit_state *); | |
e0001a05 | 468 | static void cache_literal_section |
7fa3d080 | 469 | (seg_list *, const char *, segT *, bfd_boolean); |
e0001a05 | 470 | |
e0001a05 | 471 | /* Import from elf32-xtensa.c in BFD library. */ |
43cd72b9 | 472 | |
7fa3d080 | 473 | extern char *xtensa_get_property_section_name (asection *, const char *); |
e0001a05 | 474 | |
43cd72b9 BW |
475 | /* op_placement_info functions. */ |
476 | ||
7fa3d080 BW |
477 | static void init_op_placement_info_table (void); |
478 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
479 | static int xg_get_single_size (xtensa_opcode); | |
480 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 481 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 482 | |
e0001a05 | 483 | /* TInsn and IStack functions. */ |
43cd72b9 | 484 | |
7fa3d080 BW |
485 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
486 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
487 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
488 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
489 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
490 | static void tinsn_from_chars (TInsn *, char *, int); | |
491 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
492 | static int get_num_stack_text_bytes (IStack *); | |
493 | static int get_num_stack_literal_bytes (IStack *); | |
e0001a05 | 494 | |
43cd72b9 BW |
495 | /* vliw_insn functions. */ |
496 | ||
7fa3d080 BW |
497 | static void xg_init_vinsn (vliw_insn *); |
498 | static void xg_clear_vinsn (vliw_insn *); | |
499 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
500 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 501 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
502 | (vliw_insn *, char *, fragS *, bfd_boolean); |
503 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 504 | |
e0001a05 | 505 | /* Expression Utilities. */ |
43cd72b9 | 506 | |
7fa3d080 BW |
507 | bfd_boolean expr_is_const (const expressionS *); |
508 | offsetT get_expr_const (const expressionS *); | |
509 | void set_expr_const (expressionS *, offsetT); | |
510 | bfd_boolean expr_is_register (const expressionS *); | |
511 | offsetT get_expr_register (const expressionS *); | |
512 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
513 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
514 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 515 | |
9456465c BW |
516 | /* Section renaming. */ |
517 | ||
7fa3d080 | 518 | static void build_section_rename (const char *); |
e0001a05 | 519 | |
e0001a05 NC |
520 | |
521 | /* ISA imported from bfd. */ | |
522 | extern xtensa_isa xtensa_default_isa; | |
523 | ||
524 | extern int target_big_endian; | |
525 | ||
526 | static xtensa_opcode xtensa_addi_opcode; | |
527 | static xtensa_opcode xtensa_addmi_opcode; | |
528 | static xtensa_opcode xtensa_call0_opcode; | |
529 | static xtensa_opcode xtensa_call4_opcode; | |
530 | static xtensa_opcode xtensa_call8_opcode; | |
531 | static xtensa_opcode xtensa_call12_opcode; | |
532 | static xtensa_opcode xtensa_callx0_opcode; | |
533 | static xtensa_opcode xtensa_callx4_opcode; | |
534 | static xtensa_opcode xtensa_callx8_opcode; | |
535 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 536 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 537 | static xtensa_opcode xtensa_entry_opcode; |
43cd72b9 BW |
538 | static xtensa_opcode xtensa_movi_opcode; |
539 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 540 | static xtensa_opcode xtensa_isync_opcode; |
e0001a05 | 541 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 542 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
543 | static xtensa_opcode xtensa_loop_opcode; |
544 | static xtensa_opcode xtensa_loopnez_opcode; | |
545 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 546 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
547 | static xtensa_opcode xtensa_nop_n_opcode; |
548 | static xtensa_opcode xtensa_or_opcode; | |
549 | static xtensa_opcode xtensa_ret_opcode; | |
550 | static xtensa_opcode xtensa_ret_n_opcode; | |
551 | static xtensa_opcode xtensa_retw_opcode; | |
552 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 553 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 NC |
554 | static xtensa_opcode xtensa_waiti_opcode; |
555 | ||
556 | \f | |
557 | /* Command-line Options. */ | |
558 | ||
559 | bfd_boolean use_literal_section = TRUE; | |
560 | static bfd_boolean align_targets = TRUE; | |
43cd72b9 | 561 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 562 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
563 | static bfd_boolean workaround_a0_b_retw = FALSE; |
564 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
565 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 566 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 567 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 568 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 569 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
e0001a05 | 570 | |
43cd72b9 BW |
571 | /* When workaround_short_loops is TRUE, all loops with early exits must |
572 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
573 | to the workaround_short_loop flag. In addition to the | |
574 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
575 | must have at least 3 instructions. */ | |
e0001a05 | 576 | |
43cd72b9 | 577 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 578 | |
7fa3d080 BW |
579 | |
580 | static void | |
581 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
582 | { | |
583 | if (earliest > latest) | |
584 | as_fatal (_("illegal range of target hardware versions")); | |
585 | ||
586 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
587 | if (earliest < 105000 || latest < 105000) | |
588 | { | |
589 | workaround_a0_b_retw |= TRUE; | |
590 | workaround_b_j_loop_end |= TRUE; | |
591 | workaround_short_loop |= TRUE; | |
592 | workaround_close_loop_end |= TRUE; | |
593 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 594 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
595 | } |
596 | } | |
597 | ||
598 | ||
e0001a05 NC |
599 | enum |
600 | { | |
601 | option_density = OPTION_MD_BASE, | |
602 | option_no_density, | |
603 | ||
604 | option_relax, | |
605 | option_no_relax, | |
606 | ||
43cd72b9 BW |
607 | option_link_relax, |
608 | option_no_link_relax, | |
609 | ||
e0001a05 NC |
610 | option_generics, |
611 | option_no_generics, | |
612 | ||
43cd72b9 BW |
613 | option_transform, |
614 | option_no_transform, | |
615 | ||
e0001a05 NC |
616 | option_text_section_literals, |
617 | option_no_text_section_literals, | |
618 | ||
43cd72b9 BW |
619 | option_absolute_literals, |
620 | option_no_absolute_literals, | |
621 | ||
e0001a05 NC |
622 | option_align_targets, |
623 | option_no_align_targets, | |
624 | ||
43cd72b9 | 625 | option_warn_unaligned_targets, |
e0001a05 NC |
626 | |
627 | option_longcalls, | |
628 | option_no_longcalls, | |
629 | ||
630 | option_workaround_a0_b_retw, | |
631 | option_no_workaround_a0_b_retw, | |
632 | ||
633 | option_workaround_b_j_loop_end, | |
634 | option_no_workaround_b_j_loop_end, | |
635 | ||
636 | option_workaround_short_loop, | |
637 | option_no_workaround_short_loop, | |
638 | ||
639 | option_workaround_all_short_loops, | |
640 | option_no_workaround_all_short_loops, | |
641 | ||
642 | option_workaround_close_loop_end, | |
643 | option_no_workaround_close_loop_end, | |
644 | ||
645 | option_no_workarounds, | |
646 | ||
e0001a05 | 647 | option_rename_section_name, |
e0001a05 | 648 | |
43cd72b9 BW |
649 | option_prefer_l32r, |
650 | option_prefer_const16, | |
651 | ||
652 | option_target_hardware | |
e0001a05 NC |
653 | }; |
654 | ||
655 | const char *md_shortopts = ""; | |
656 | ||
657 | struct option md_longopts[] = | |
658 | { | |
43cd72b9 BW |
659 | { "density", no_argument, NULL, option_density }, |
660 | { "no-density", no_argument, NULL, option_no_density }, | |
661 | ||
662 | /* Both "relax" and "generics" are deprecated and treated as equivalent | |
663 | to the "transform" option. */ | |
664 | { "relax", no_argument, NULL, option_relax }, | |
665 | { "no-relax", no_argument, NULL, option_no_relax }, | |
666 | { "generics", no_argument, NULL, option_generics }, | |
667 | { "no-generics", no_argument, NULL, option_no_generics }, | |
668 | ||
669 | { "transform", no_argument, NULL, option_transform }, | |
670 | { "no-transform", no_argument, NULL, option_no_transform }, | |
671 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
672 | { "no-text-section-literals", no_argument, NULL, | |
673 | option_no_text_section_literals }, | |
674 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
675 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
676 | /* This option was changed from -align-target to -target-align |
677 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 678 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
679 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
680 | { "warn-unaligned-targets", no_argument, NULL, | |
681 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
682 | { "longcalls", no_argument, NULL, option_longcalls }, |
683 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
684 | ||
685 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
686 | option_no_workaround_a0_b_retw }, | |
687 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 688 | |
43cd72b9 BW |
689 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
690 | option_no_workaround_b_j_loop_end }, | |
691 | { "workaround-b-j-loop-end", no_argument, NULL, | |
692 | option_workaround_b_j_loop_end }, | |
e0001a05 | 693 | |
43cd72b9 BW |
694 | { "no-workaround-short-loops", no_argument, NULL, |
695 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
696 | { "workaround-short-loops", no_argument, NULL, |
697 | option_workaround_short_loop }, | |
e0001a05 | 698 | |
43cd72b9 BW |
699 | { "no-workaround-all-short-loops", no_argument, NULL, |
700 | option_no_workaround_all_short_loops }, | |
701 | { "workaround-all-short-loop", no_argument, NULL, | |
702 | option_workaround_all_short_loops }, | |
703 | ||
704 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
705 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
706 | ||
707 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
708 | ||
709 | { "no-workaround-close-loop-end", no_argument, NULL, | |
710 | option_no_workaround_close_loop_end }, | |
711 | { "workaround-close-loop-end", no_argument, NULL, | |
712 | option_workaround_close_loop_end }, | |
e0001a05 | 713 | |
7fa3d080 | 714 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 715 | |
43cd72b9 BW |
716 | { "link-relax", no_argument, NULL, option_link_relax }, |
717 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
718 | ||
719 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
720 | ||
721 | { NULL, no_argument, NULL, 0 } | |
e0001a05 NC |
722 | }; |
723 | ||
724 | size_t md_longopts_size = sizeof md_longopts; | |
725 | ||
726 | ||
727 | int | |
7fa3d080 | 728 | md_parse_option (int c, char *arg) |
e0001a05 NC |
729 | { |
730 | switch (c) | |
731 | { | |
732 | case option_density: | |
43cd72b9 | 733 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
734 | return 1; |
735 | case option_no_density: | |
43cd72b9 | 736 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 737 | return 1; |
43cd72b9 BW |
738 | case option_link_relax: |
739 | linkrelax = 1; | |
e0001a05 | 740 | return 1; |
43cd72b9 BW |
741 | case option_no_link_relax: |
742 | linkrelax = 0; | |
e0001a05 | 743 | return 1; |
43cd72b9 BW |
744 | case option_generics: |
745 | as_warn (_("--generics is deprecated; use --transform instead")); | |
746 | return md_parse_option (option_transform, arg); | |
747 | case option_no_generics: | |
748 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
749 | return md_parse_option (option_no_transform, arg); | |
750 | case option_relax: | |
751 | as_warn (_("--relax is deprecated; use --transform instead")); | |
752 | return md_parse_option (option_transform, arg); | |
753 | case option_no_relax: | |
754 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
755 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
756 | case option_longcalls: |
757 | directive_state[directive_longcalls] = TRUE; | |
758 | return 1; | |
759 | case option_no_longcalls: | |
760 | directive_state[directive_longcalls] = FALSE; | |
761 | return 1; | |
762 | case option_text_section_literals: | |
763 | use_literal_section = FALSE; | |
764 | return 1; | |
765 | case option_no_text_section_literals: | |
766 | use_literal_section = TRUE; | |
767 | return 1; | |
43cd72b9 BW |
768 | case option_absolute_literals: |
769 | if (!absolute_literals_supported) | |
770 | { | |
771 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
772 | return 0; | |
773 | } | |
774 | directive_state[directive_absolute_literals] = TRUE; | |
775 | return 1; | |
776 | case option_no_absolute_literals: | |
777 | directive_state[directive_absolute_literals] = FALSE; | |
778 | return 1; | |
779 | ||
e0001a05 NC |
780 | case option_workaround_a0_b_retw: |
781 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
782 | return 1; |
783 | case option_no_workaround_a0_b_retw: | |
784 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
785 | return 1; |
786 | case option_workaround_b_j_loop_end: | |
787 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
788 | return 1; |
789 | case option_no_workaround_b_j_loop_end: | |
790 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
791 | return 1; |
792 | ||
793 | case option_workaround_short_loop: | |
794 | workaround_short_loop = TRUE; | |
e0001a05 NC |
795 | return 1; |
796 | case option_no_workaround_short_loop: | |
797 | workaround_short_loop = FALSE; | |
e0001a05 NC |
798 | return 1; |
799 | ||
800 | case option_workaround_all_short_loops: | |
801 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
802 | return 1; |
803 | case option_no_workaround_all_short_loops: | |
804 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
805 | return 1; |
806 | ||
807 | case option_workaround_close_loop_end: | |
808 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
809 | return 1; |
810 | case option_no_workaround_close_loop_end: | |
811 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
812 | return 1; |
813 | ||
814 | case option_no_workarounds: | |
815 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 816 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 817 | workaround_short_loop = FALSE; |
e0001a05 | 818 | workaround_all_short_loops = FALSE; |
e0001a05 | 819 | workaround_close_loop_end = FALSE; |
e0001a05 | 820 | return 1; |
43cd72b9 | 821 | |
e0001a05 NC |
822 | case option_align_targets: |
823 | align_targets = TRUE; | |
824 | return 1; | |
825 | case option_no_align_targets: | |
826 | align_targets = FALSE; | |
827 | return 1; | |
828 | ||
43cd72b9 BW |
829 | case option_warn_unaligned_targets: |
830 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
831 | return 1; |
832 | ||
e0001a05 NC |
833 | case option_rename_section_name: |
834 | build_section_rename (arg); | |
835 | return 1; | |
e0001a05 NC |
836 | |
837 | case 'Q': | |
838 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
839 | should be emitted or not. FIXME: Not implemented. */ | |
840 | return 1; | |
c138bc38 | 841 | |
43cd72b9 BW |
842 | case option_prefer_l32r: |
843 | if (prefer_const16) | |
844 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
845 | prefer_l32r = 1; | |
846 | return 1; | |
847 | ||
848 | case option_prefer_const16: | |
849 | if (prefer_l32r) | |
850 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
851 | prefer_const16 = 1; | |
852 | return 1; | |
853 | ||
c138bc38 | 854 | case option_target_hardware: |
43cd72b9 BW |
855 | { |
856 | int earliest, latest = 0; | |
857 | if (*arg == 0 || *arg == '-') | |
858 | as_fatal (_("invalid target hardware version")); | |
859 | ||
860 | earliest = strtol (arg, &arg, 0); | |
861 | ||
862 | if (*arg == 0) | |
863 | latest = earliest; | |
864 | else if (*arg == '-') | |
865 | { | |
866 | if (*++arg == 0) | |
867 | as_fatal (_("invalid target hardware version")); | |
868 | latest = strtol (arg, &arg, 0); | |
869 | } | |
870 | if (*arg != 0) | |
871 | as_fatal (_("invalid target hardware version")); | |
872 | ||
873 | xtensa_setup_hw_workarounds (earliest, latest); | |
874 | return 1; | |
875 | } | |
876 | ||
877 | case option_transform: | |
878 | /* This option has no affect other than to use the defaults, | |
879 | which are already set. */ | |
880 | return 1; | |
881 | ||
882 | case option_no_transform: | |
883 | /* This option turns off all transformations of any kind. | |
884 | However, because we want to preserve the state of other | |
885 | directives, we only change its own field. Thus, before | |
886 | you perform any transformation, always check if transform | |
887 | is available. If you use the functions we provide for this | |
888 | purpose, you will be ok. */ | |
889 | directive_state[directive_transform] = FALSE; | |
890 | return 1; | |
891 | ||
e0001a05 NC |
892 | default: |
893 | return 0; | |
894 | } | |
895 | } | |
896 | ||
897 | ||
898 | void | |
7fa3d080 | 899 | md_show_usage (FILE *stream) |
e0001a05 | 900 | { |
43cd72b9 BW |
901 | fputs ("\n\ |
902 | Xtensa options:\n\ | |
9456465c BW |
903 | --[no-]text-section-literals\n\ |
904 | [Do not] put literals in the text section\n\ | |
905 | --[no-]absolute-literals\n\ | |
906 | [Do not] default to use non-PC-relative literals\n\ | |
907 | --[no-]target-align [Do not] try to align branch targets\n\ | |
908 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
909 | --[no-]transform [Do not] transform instructions\n\ | |
910 | --rename-section old=new Rename section 'old' to 'new'\n", stream); | |
e0001a05 NC |
911 | } |
912 | ||
7fa3d080 BW |
913 | \f |
914 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
915 | |
916 | static void | |
7fa3d080 | 917 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 918 | { |
7fa3d080 | 919 | sym_list *l; |
43cd72b9 | 920 | |
7fa3d080 BW |
921 | if (!free_insn_labels) |
922 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
923 | else | |
43cd72b9 | 924 | { |
7fa3d080 BW |
925 | l = free_insn_labels; |
926 | free_insn_labels = l->next; | |
927 | } | |
928 | ||
929 | l->sym = sym; | |
930 | l->next = insn_labels; | |
931 | insn_labels = l; | |
932 | } | |
933 | ||
934 | ||
935 | static void | |
936 | xtensa_clear_insn_labels (void) | |
937 | { | |
938 | sym_list **pl; | |
939 | ||
940 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
941 | ; | |
942 | *pl = insn_labels; | |
943 | insn_labels = NULL; | |
944 | } | |
945 | ||
946 | ||
c138bc38 BW |
947 | /* The "loops_ok" argument is provided to allow ignoring labels that |
948 | define loop ends. This fixes a bug where the NOPs to align a | |
7fa3d080 BW |
949 | loop opcode were included in a previous zero-cost loop: |
950 | ||
951 | loop a0, loopend | |
952 | <loop1 body> | |
953 | loopend: | |
954 | ||
955 | loop a2, loopend2 | |
956 | <loop2 body> | |
957 | ||
958 | would become: | |
959 | ||
960 | loop a0, loopend | |
961 | <loop1 body> | |
962 | nop.n <===== bad! | |
963 | loopend: | |
964 | ||
965 | loop a2, loopend2 | |
966 | <loop2 body> | |
967 | ||
968 | This argument is used to prevent moving the NOP to before the | |
969 | loop-end label, which is what you want in this special case. */ | |
970 | ||
971 | static void | |
972 | xtensa_move_labels (fragS *new_frag, valueT new_offset, bfd_boolean loops_ok) | |
973 | { | |
974 | sym_list *lit; | |
975 | ||
976 | for (lit = insn_labels; lit; lit = lit->next) | |
977 | { | |
978 | symbolS *lit_sym = lit->sym; | |
979 | if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target) | |
980 | { | |
981 | S_SET_VALUE (lit_sym, new_offset); | |
982 | symbol_set_frag (lit_sym, new_frag); | |
983 | } | |
43cd72b9 BW |
984 | } |
985 | } | |
986 | ||
e0001a05 NC |
987 | \f |
988 | /* Directive data and functions. */ | |
989 | ||
990 | typedef struct state_stackS_struct | |
991 | { | |
992 | directiveE directive; | |
993 | bfd_boolean negated; | |
994 | bfd_boolean old_state; | |
995 | const char *file; | |
996 | unsigned int line; | |
997 | const void *datum; | |
998 | struct state_stackS_struct *prev; | |
999 | } state_stackS; | |
1000 | ||
1001 | state_stackS *directive_state_stack; | |
1002 | ||
1003 | const pseudo_typeS md_pseudo_table[] = | |
1004 | { | |
43cd72b9 BW |
1005 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1006 | { "literal_position", xtensa_literal_position, 0 }, | |
1007 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1008 | { "long", xtensa_elf_cons, 4 }, | |
1009 | { "word", xtensa_elf_cons, 4 }, | |
1010 | { "short", xtensa_elf_cons, 2 }, | |
1011 | { "begin", xtensa_begin_directive, 0 }, | |
1012 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1013 | { "literal", xtensa_literal_pseudo, 0 }, |
1014 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1015 | { NULL, 0, 0 }, | |
e0001a05 NC |
1016 | }; |
1017 | ||
1018 | ||
7fa3d080 BW |
1019 | static bfd_boolean |
1020 | use_transform (void) | |
e0001a05 | 1021 | { |
43cd72b9 BW |
1022 | /* After md_end, you should be checking frag by frag, rather |
1023 | than state directives. */ | |
1024 | assert (!past_xtensa_end); | |
1025 | return directive_state[directive_transform]; | |
e0001a05 NC |
1026 | } |
1027 | ||
1028 | ||
7fa3d080 BW |
1029 | static bfd_boolean |
1030 | do_align_targets (void) | |
e0001a05 | 1031 | { |
7b1cc377 BW |
1032 | /* Do not use this function after md_end; just look at align_targets |
1033 | instead. There is no target-align directive, so alignment is either | |
1034 | enabled for all frags or not done at all. */ | |
43cd72b9 BW |
1035 | assert (!past_xtensa_end); |
1036 | return align_targets && use_transform (); | |
e0001a05 NC |
1037 | } |
1038 | ||
1039 | ||
1040 | static void | |
7fa3d080 | 1041 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 NC |
1042 | { |
1043 | char *file; | |
1044 | unsigned int line; | |
1045 | state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); | |
1046 | ||
1047 | as_where (&file, &line); | |
1048 | ||
1049 | stack->directive = directive; | |
1050 | stack->negated = negated; | |
1051 | stack->old_state = directive_state[directive]; | |
1052 | stack->file = file; | |
1053 | stack->line = line; | |
1054 | stack->datum = datum; | |
1055 | stack->prev = directive_state_stack; | |
1056 | directive_state_stack = stack; | |
1057 | ||
1058 | directive_state[directive] = !negated; | |
1059 | } | |
1060 | ||
7fa3d080 | 1061 | |
e0001a05 | 1062 | static void |
7fa3d080 BW |
1063 | directive_pop (directiveE *directive, |
1064 | bfd_boolean *negated, | |
1065 | const char **file, | |
1066 | unsigned int *line, | |
1067 | const void **datum) | |
e0001a05 NC |
1068 | { |
1069 | state_stackS *top = directive_state_stack; | |
1070 | ||
1071 | if (!directive_state_stack) | |
1072 | { | |
1073 | as_bad (_("unmatched end directive")); | |
1074 | *directive = directive_none; | |
1075 | return; | |
1076 | } | |
1077 | ||
1078 | directive_state[directive_state_stack->directive] = top->old_state; | |
1079 | *directive = top->directive; | |
1080 | *negated = top->negated; | |
1081 | *file = top->file; | |
1082 | *line = top->line; | |
1083 | *datum = top->datum; | |
1084 | directive_state_stack = top->prev; | |
1085 | free (top); | |
1086 | } | |
1087 | ||
1088 | ||
1089 | static void | |
7fa3d080 | 1090 | directive_balance (void) |
e0001a05 NC |
1091 | { |
1092 | while (directive_state_stack) | |
1093 | { | |
1094 | directiveE directive; | |
1095 | bfd_boolean negated; | |
1096 | const char *file; | |
1097 | unsigned int line; | |
1098 | const void *datum; | |
1099 | ||
1100 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1101 | as_warn_where ((char *) file, line, | |
1102 | _(".begin directive with no matching .end directive")); | |
1103 | } | |
1104 | } | |
1105 | ||
1106 | ||
1107 | static bfd_boolean | |
7fa3d080 | 1108 | inside_directive (directiveE dir) |
e0001a05 NC |
1109 | { |
1110 | state_stackS *top = directive_state_stack; | |
1111 | ||
1112 | while (top && top->directive != dir) | |
1113 | top = top->prev; | |
1114 | ||
1115 | return (top != NULL); | |
1116 | } | |
1117 | ||
1118 | ||
1119 | static void | |
7fa3d080 | 1120 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1121 | { |
1122 | int len; | |
1123 | unsigned i; | |
43cd72b9 | 1124 | char *directive_string; |
e0001a05 NC |
1125 | |
1126 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1127 | *negated = FALSE; | |
1128 | else | |
1129 | { | |
1130 | *negated = TRUE; | |
1131 | input_line_pointer += 3; | |
1132 | } | |
1133 | ||
1134 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1135 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1136 | ||
1137 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1138 | equivalent to .begin [no-]transform. We should remove it when | |
1139 | we stop accepting those options. */ | |
c138bc38 | 1140 | |
43cd72b9 BW |
1141 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1142 | { | |
1143 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1144 | directive_string = "transform"; | |
1145 | } | |
1146 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1147 | { | |
1148 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1149 | directive_string = "transform"; | |
c138bc38 | 1150 | } |
43cd72b9 BW |
1151 | else |
1152 | directive_string = input_line_pointer; | |
e0001a05 NC |
1153 | |
1154 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1155 | { | |
43cd72b9 | 1156 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1157 | { |
1158 | input_line_pointer += len; | |
1159 | *directive = (directiveE) i; | |
1160 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1161 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1162 | directive_info[i].name); |
1163 | return; | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | as_bad (_("unknown directive")); | |
1168 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1169 | } | |
1170 | ||
1171 | ||
1172 | static void | |
7fa3d080 | 1173 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1174 | { |
1175 | directiveE directive; | |
1176 | bfd_boolean negated; | |
1177 | emit_state *state; | |
1178 | int len; | |
1179 | lit_state *ls; | |
1180 | ||
1181 | get_directive (&directive, &negated); | |
1182 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1183 | { | |
1184 | discard_rest_of_line (); | |
1185 | return; | |
1186 | } | |
1187 | ||
43cd72b9 BW |
1188 | if (cur_vinsn.inside_bundle) |
1189 | as_bad (_("directives are not valid inside bundles")); | |
1190 | ||
e0001a05 NC |
1191 | switch (directive) |
1192 | { | |
1193 | case directive_literal: | |
82e7541d BW |
1194 | if (!inside_directive (directive_literal)) |
1195 | { | |
1196 | /* Previous labels go with whatever follows this directive, not with | |
1197 | the literal, so save them now. */ | |
1198 | saved_insn_labels = insn_labels; | |
1199 | insn_labels = NULL; | |
1200 | } | |
43cd72b9 | 1201 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
e0001a05 NC |
1202 | state = (emit_state *) xmalloc (sizeof (emit_state)); |
1203 | xtensa_switch_to_literal_fragment (state); | |
1204 | directive_push (directive_literal, negated, state); | |
1205 | break; | |
1206 | ||
1207 | case directive_literal_prefix: | |
c138bc38 | 1208 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1209 | might produce a literal. */ |
1210 | md_flush_pending_output (); | |
e0001a05 NC |
1211 | /* Check to see if the current fragment is a literal |
1212 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1213 | if (generating_literals) |
e0001a05 NC |
1214 | { |
1215 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1216 | return; | |
1217 | } | |
1218 | ||
1219 | /* Allocate the literal state for this section and push | |
1220 | onto the directive stack. */ | |
1221 | ls = xmalloc (sizeof (lit_state)); | |
1222 | assert (ls); | |
1223 | ||
1224 | *ls = default_lit_sections; | |
1225 | ||
1226 | directive_push (directive_literal_prefix, negated, ls); | |
1227 | ||
1228 | /* Parse the new prefix from the input_line_pointer. */ | |
1229 | SKIP_WHITESPACE (); | |
1230 | len = strspn (input_line_pointer, | |
1231 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1232 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
1233 | ||
1234 | /* Process the new prefix. */ | |
1235 | xtensa_literal_prefix (input_line_pointer, len); | |
1236 | ||
1237 | /* Skip the name in the input line. */ | |
1238 | input_line_pointer += len; | |
1239 | break; | |
1240 | ||
1241 | case directive_freeregs: | |
1242 | /* This information is currently unused, but we'll accept the statement | |
1243 | and just discard the rest of the line. This won't check the syntax, | |
1244 | but it will accept every correct freeregs directive. */ | |
1245 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1246 | directive_push (directive_freeregs, negated, 0); | |
1247 | break; | |
1248 | ||
43cd72b9 BW |
1249 | case directive_schedule: |
1250 | md_flush_pending_output (); | |
1251 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1252 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1253 | directive_push (directive_schedule, negated, 0); | |
1254 | xtensa_set_frag_assembly_state (frag_now); | |
1255 | break; | |
1256 | ||
e0001a05 | 1257 | case directive_density: |
43cd72b9 BW |
1258 | as_warn (_(".begin [no-]density is ignored")); |
1259 | break; | |
1260 | ||
1261 | case directive_absolute_literals: | |
1262 | md_flush_pending_output (); | |
1263 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1264 | { |
43cd72b9 | 1265 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1266 | break; |
1267 | } | |
43cd72b9 BW |
1268 | xtensa_set_frag_assembly_state (frag_now); |
1269 | directive_push (directive, negated, 0); | |
1270 | break; | |
e0001a05 NC |
1271 | |
1272 | default: | |
43cd72b9 BW |
1273 | md_flush_pending_output (); |
1274 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1275 | directive_push (directive, negated, 0); |
1276 | break; | |
1277 | } | |
1278 | ||
1279 | demand_empty_rest_of_line (); | |
1280 | } | |
1281 | ||
1282 | ||
1283 | static void | |
7fa3d080 | 1284 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1285 | { |
1286 | directiveE begin_directive, end_directive; | |
1287 | bfd_boolean begin_negated, end_negated; | |
1288 | const char *file; | |
1289 | unsigned int line; | |
1290 | emit_state *state; | |
43cd72b9 | 1291 | emit_state **state_ptr; |
e0001a05 NC |
1292 | lit_state *s; |
1293 | ||
43cd72b9 BW |
1294 | if (cur_vinsn.inside_bundle) |
1295 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1296 | |
e0001a05 | 1297 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1298 | |
1299 | md_flush_pending_output (); | |
1300 | ||
1301 | switch (end_directive) | |
e0001a05 | 1302 | { |
43cd72b9 | 1303 | case (directiveE) XTENSA_UNDEFINED: |
e0001a05 NC |
1304 | discard_rest_of_line (); |
1305 | return; | |
e0001a05 | 1306 | |
43cd72b9 BW |
1307 | case directive_density: |
1308 | as_warn (_(".end [no-]density is ignored")); | |
e0001a05 | 1309 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1310 | break; |
1311 | ||
1312 | case directive_absolute_literals: | |
1313 | if (!absolute_literals_supported && !end_negated) | |
1314 | { | |
1315 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1316 | demand_empty_rest_of_line (); | |
1317 | return; | |
1318 | } | |
1319 | break; | |
1320 | ||
1321 | default: | |
1322 | break; | |
e0001a05 NC |
1323 | } |
1324 | ||
43cd72b9 | 1325 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1326 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1327 | (const void **) state_ptr); |
e0001a05 NC |
1328 | |
1329 | if (begin_directive != directive_none) | |
1330 | { | |
1331 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1332 | { | |
1333 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1334 | begin_negated ? "no-" : "", | |
1335 | directive_info[begin_directive].name, file, line); | |
1336 | } | |
1337 | else | |
1338 | { | |
1339 | switch (end_directive) | |
1340 | { | |
1341 | case directive_literal: | |
1342 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1343 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1344 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1345 | free (state); |
82e7541d BW |
1346 | if (!inside_directive (directive_literal)) |
1347 | { | |
1348 | /* Restore the list of current labels. */ | |
1349 | xtensa_clear_insn_labels (); | |
1350 | insn_labels = saved_insn_labels; | |
1351 | } | |
e0001a05 NC |
1352 | break; |
1353 | ||
e0001a05 NC |
1354 | case directive_literal_prefix: |
1355 | /* Restore the default collection sections from saved state. */ | |
1356 | s = (lit_state *) state; | |
1357 | assert (s); | |
1358 | ||
e8247da7 | 1359 | default_lit_sections = *s; |
e0001a05 NC |
1360 | |
1361 | /* free the state storage */ | |
1362 | free (s); | |
1363 | break; | |
1364 | ||
43cd72b9 BW |
1365 | case directive_schedule: |
1366 | case directive_freeregs: | |
1367 | break; | |
1368 | ||
e0001a05 | 1369 | default: |
43cd72b9 | 1370 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1371 | break; |
1372 | } | |
1373 | } | |
1374 | } | |
1375 | ||
1376 | demand_empty_rest_of_line (); | |
1377 | } | |
1378 | ||
1379 | ||
1380 | /* Place an aligned literal fragment at the current location. */ | |
1381 | ||
1382 | static void | |
7fa3d080 | 1383 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1384 | { |
43cd72b9 BW |
1385 | md_flush_pending_output (); |
1386 | ||
e0001a05 NC |
1387 | if (inside_directive (directive_literal)) |
1388 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1389 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1390 | |
1391 | demand_empty_rest_of_line (); | |
82e7541d | 1392 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1393 | } |
1394 | ||
1395 | ||
43cd72b9 | 1396 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1397 | |
1398 | static void | |
7fa3d080 | 1399 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1400 | { |
1401 | emit_state state; | |
1745fcba | 1402 | char *p, *base_name; |
e0001a05 | 1403 | char c; |
e0001a05 NC |
1404 | segT dest_seg; |
1405 | ||
82e7541d BW |
1406 | if (inside_directive (directive_literal)) |
1407 | { | |
1408 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1409 | ignore_rest_of_line (); | |
1410 | return; | |
1411 | } | |
1412 | ||
43cd72b9 BW |
1413 | md_flush_pending_output (); |
1414 | ||
82e7541d BW |
1415 | /* Previous labels go with whatever follows this directive, not with |
1416 | the literal, so save them now. */ | |
1417 | saved_insn_labels = insn_labels; | |
1418 | insn_labels = NULL; | |
1419 | ||
e0001a05 NC |
1420 | /* If we are using text-section literals, then this is the right value... */ |
1421 | dest_seg = now_seg; | |
1422 | ||
1423 | base_name = input_line_pointer; | |
1424 | ||
1425 | xtensa_switch_to_literal_fragment (&state); | |
1426 | ||
43cd72b9 | 1427 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1428 | need to put them in the section we just switched to. */ |
43cd72b9 | 1429 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1430 | dest_seg = now_seg; |
1431 | ||
43cd72b9 BW |
1432 | /* All literals are aligned to four-byte boundaries. */ |
1433 | frag_align (2, 0, 0); | |
1434 | record_alignment (now_seg, 2); | |
e0001a05 NC |
1435 | |
1436 | c = get_symbol_end (); | |
1437 | /* Just after name is now '\0'. */ | |
1438 | p = input_line_pointer; | |
1439 | *p = c; | |
1440 | SKIP_WHITESPACE (); | |
1441 | ||
1442 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1443 | { | |
1444 | as_bad (_("expected comma or colon after symbol name; " | |
1445 | "rest of line ignored")); | |
1446 | ignore_rest_of_line (); | |
1447 | xtensa_restore_emit_state (&state); | |
1448 | return; | |
1449 | } | |
1450 | *p = 0; | |
1451 | ||
e0001a05 | 1452 | colon (base_name); |
e0001a05 | 1453 | |
e0001a05 | 1454 | *p = c; |
43cd72b9 | 1455 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1456 | |
43cd72b9 | 1457 | xtensa_elf_cons (4); |
e0001a05 NC |
1458 | |
1459 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1460 | |
1461 | /* Restore the list of current labels. */ | |
1462 | xtensa_clear_insn_labels (); | |
1463 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1464 | } |
1465 | ||
1466 | ||
1467 | static void | |
7fa3d080 | 1468 | xtensa_literal_prefix (char const *start, int len) |
e0001a05 | 1469 | { |
43cd72b9 BW |
1470 | char *name, *linkonce_suffix; |
1471 | char *newname, *newname4; | |
1472 | size_t linkonce_len; | |
e0001a05 NC |
1473 | |
1474 | /* Get a null-terminated copy of the name. */ | |
1475 | name = xmalloc (len + 1); | |
1476 | assert (name); | |
1477 | ||
1478 | strncpy (name, start, len); | |
1479 | name[len] = 0; | |
1480 | ||
1481 | /* Allocate the sections (interesting note: the memory pointing to | |
1482 | the name is actually used for the name by the new section). */ | |
43cd72b9 | 1483 | |
e0001a05 | 1484 | newname = xmalloc (len + strlen (".literal") + 1); |
43cd72b9 | 1485 | newname4 = xmalloc (len + strlen (".lit4") + 1); |
e0001a05 | 1486 | |
43cd72b9 BW |
1487 | linkonce_len = sizeof (".gnu.linkonce.") - 1; |
1488 | if (strncmp (name, ".gnu.linkonce.", linkonce_len) == 0 | |
1489 | && (linkonce_suffix = strchr (name + linkonce_len, '.')) != 0) | |
1490 | { | |
1491 | strcpy (newname, ".gnu.linkonce.literal"); | |
1492 | strcpy (newname4, ".gnu.linkonce.lit4"); | |
e0001a05 | 1493 | |
43cd72b9 BW |
1494 | strcat (newname, linkonce_suffix); |
1495 | strcat (newname4, linkonce_suffix); | |
1496 | } | |
1497 | else | |
1498 | { | |
1499 | int suffix_pos = len; | |
1500 | ||
1501 | /* If the section name ends with ".text", then replace that suffix | |
1502 | instead of appending an additional suffix. */ | |
1503 | if (len >= 5 && strcmp (name + len - 5, ".text") == 0) | |
1504 | suffix_pos -= 5; | |
1505 | ||
1506 | strcpy (newname, name); | |
1507 | strcpy (newname4, name); | |
1508 | ||
1509 | strcpy (newname + suffix_pos, ".literal"); | |
1510 | strcpy (newname4 + suffix_pos, ".lit4"); | |
1511 | } | |
1512 | ||
b08b5071 | 1513 | /* Note that cache_literal_section does not create a segment if |
43cd72b9 BW |
1514 | it already exists. */ |
1515 | default_lit_sections.lit_seg = NULL; | |
1516 | default_lit_sections.lit4_seg = NULL; | |
1517 | ||
1518 | /* Canonicalizing section names allows renaming literal | |
e0001a05 | 1519 | sections to occur correctly. */ |
43cd72b9 BW |
1520 | default_lit_sections.lit_seg_name = tc_canonicalize_symbol_name (newname); |
1521 | default_lit_sections.lit4_seg_name = tc_canonicalize_symbol_name (newname4); | |
e0001a05 NC |
1522 | |
1523 | free (name); | |
43cd72b9 BW |
1524 | } |
1525 | ||
1526 | ||
1527 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1528 | ||
1529 | static void | |
7fa3d080 | 1530 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1531 | { |
1532 | float fall_through_f, target_f; | |
43cd72b9 BW |
1533 | |
1534 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1535 | if (fall_through_f < 0) | |
1536 | { | |
1537 | as_bad (_("fall through frequency must be greater than 0")); | |
1538 | ignore_rest_of_line (); | |
1539 | return; | |
1540 | } | |
1541 | ||
1542 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1543 | if (target_f < 0) | |
1544 | { | |
1545 | as_bad (_("branch target frequency must be greater than 0")); | |
1546 | ignore_rest_of_line (); | |
1547 | return; | |
1548 | } | |
1549 | ||
b08b5071 | 1550 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1551 | |
1552 | demand_empty_rest_of_line (); | |
1553 | } | |
1554 | ||
1555 | ||
1556 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1557 | Clobbers input_line_pointer, checks end-of-line. */ | |
1558 | ||
1559 | static void | |
7fa3d080 | 1560 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1561 | { |
1562 | expressionS exp; | |
1563 | bfd_reloc_code_real_type reloc; | |
1564 | ||
1565 | md_flush_pending_output (); | |
1566 | ||
1567 | if (cur_vinsn.inside_bundle) | |
1568 | as_bad (_("directives are not valid inside bundles")); | |
1569 | ||
1570 | if (is_it_end_of_statement ()) | |
1571 | { | |
1572 | demand_empty_rest_of_line (); | |
1573 | return; | |
1574 | } | |
1575 | ||
1576 | do | |
1577 | { | |
1578 | expression (&exp); | |
1579 | if (exp.X_op == O_symbol | |
1580 | && *input_line_pointer == '@' | |
1581 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1582 | != BFD_RELOC_NONE)) | |
1583 | { | |
1584 | reloc_howto_type *reloc_howto = | |
1585 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1586 | ||
1587 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1588 | as_bad (_("unsupported relocation")); | |
1589 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1590 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1591 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1592 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1593 | as_bad (_("opcode-specific %s relocation used outside " | |
1594 | "an instruction"), reloc_howto->name); | |
1595 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
1596 | as_bad (_("%s relocations do not fit in %d bytes"), | |
1597 | reloc_howto->name, nbytes); | |
1598 | else | |
1599 | { | |
1600 | char *p = frag_more ((int) nbytes); | |
1601 | xtensa_set_frag_assembly_state (frag_now); | |
1602 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1603 | nbytes, &exp, 0, reloc); | |
1604 | } | |
1605 | } | |
1606 | else | |
1607 | emit_expr (&exp, (unsigned int) nbytes); | |
1608 | } | |
1609 | while (*input_line_pointer++ == ','); | |
1610 | ||
1611 | input_line_pointer--; /* Put terminator back into stream. */ | |
1612 | demand_empty_rest_of_line (); | |
1613 | } | |
1614 | ||
7fa3d080 BW |
1615 | \f |
1616 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1617 | |
1618 | /* Parse @plt, etc. and return the desired relocation. */ | |
1619 | static bfd_reloc_code_real_type | |
7fa3d080 | 1620 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 BW |
1621 | { |
1622 | struct map_bfd | |
1623 | { | |
1624 | char *string; | |
1625 | int length; | |
1626 | bfd_reloc_code_real_type reloc; | |
1627 | }; | |
1628 | ||
1629 | char ident[20]; | |
1630 | char *str = *str_p; | |
1631 | char *str2; | |
1632 | int ch; | |
1633 | int len; | |
1634 | struct map_bfd *ptr; | |
1635 | ||
1636 | #define MAP(str,reloc) { str, sizeof (str) - 1, reloc } | |
e0001a05 | 1637 | |
43cd72b9 BW |
1638 | static struct map_bfd mapping[] = |
1639 | { | |
1640 | MAP ("l", BFD_RELOC_LO16), | |
1641 | MAP ("h", BFD_RELOC_HI16), | |
1642 | MAP ("plt", BFD_RELOC_XTENSA_PLT), | |
1643 | { (char *) 0, 0, BFD_RELOC_UNUSED } | |
1644 | }; | |
1645 | ||
1646 | if (*str++ != '@') | |
1647 | return BFD_RELOC_NONE; | |
1648 | ||
1649 | for (ch = *str, str2 = ident; | |
1650 | (str2 < ident + sizeof (ident) - 1 | |
1651 | && (ISALNUM (ch) || ch == '@')); | |
1652 | ch = *++str) | |
1653 | { | |
1654 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1655 | } | |
1656 | ||
1657 | *str2 = '\0'; | |
1658 | len = str2 - ident; | |
1659 | ||
1660 | ch = ident[0]; | |
1661 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
1662 | if (ch == ptr->string[0] | |
1663 | && len == ptr->length | |
1664 | && memcmp (ident, ptr->string, ptr->length) == 0) | |
1665 | { | |
1666 | /* Now check for "identifier@suffix+constant". */ | |
1667 | if (*str == '-' || *str == '+') | |
1668 | { | |
1669 | char *orig_line = input_line_pointer; | |
1670 | expressionS new_exp; | |
1671 | ||
1672 | input_line_pointer = str; | |
1673 | expression (&new_exp); | |
1674 | if (new_exp.X_op == O_constant) | |
1675 | { | |
1676 | exp_p->X_add_number += new_exp.X_add_number; | |
1677 | str = input_line_pointer; | |
1678 | } | |
1679 | ||
1680 | if (&input_line_pointer != str_p) | |
1681 | input_line_pointer = orig_line; | |
1682 | } | |
1683 | ||
1684 | *str_p = str; | |
1685 | return ptr->reloc; | |
1686 | } | |
1687 | ||
1688 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1689 | } |
1690 | ||
e0001a05 NC |
1691 | |
1692 | static const char * | |
7fa3d080 | 1693 | expression_end (const char *name) |
e0001a05 NC |
1694 | { |
1695 | while (1) | |
1696 | { | |
1697 | switch (*name) | |
1698 | { | |
43cd72b9 | 1699 | case '}': |
e0001a05 NC |
1700 | case ';': |
1701 | case '\0': | |
1702 | case ',': | |
43cd72b9 | 1703 | case ':': |
e0001a05 NC |
1704 | return name; |
1705 | case ' ': | |
1706 | case '\t': | |
1707 | ++name; | |
1708 | continue; | |
1709 | default: | |
1710 | return 0; | |
1711 | } | |
1712 | } | |
1713 | } | |
1714 | ||
1715 | ||
1716 | #define ERROR_REG_NUM ((unsigned) -1) | |
1717 | ||
1718 | static unsigned | |
7fa3d080 | 1719 | tc_get_register (const char *prefix) |
e0001a05 NC |
1720 | { |
1721 | unsigned reg; | |
1722 | const char *next_expr; | |
1723 | const char *old_line_pointer; | |
1724 | ||
1725 | SKIP_WHITESPACE (); | |
1726 | old_line_pointer = input_line_pointer; | |
1727 | ||
1728 | if (*input_line_pointer == '$') | |
1729 | ++input_line_pointer; | |
1730 | ||
1731 | /* Accept "sp" as a synonym for "a1". */ | |
1732 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1733 | && expression_end (input_line_pointer + 2)) | |
1734 | { | |
1735 | input_line_pointer += 2; | |
1736 | return 1; /* AR[1] */ | |
1737 | } | |
1738 | ||
1739 | while (*input_line_pointer++ == *prefix++) | |
1740 | ; | |
1741 | --input_line_pointer; | |
1742 | --prefix; | |
1743 | ||
1744 | if (*prefix) | |
1745 | { | |
1746 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1747 | return ERROR_REG_NUM; | |
1748 | } | |
1749 | ||
1750 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1751 | { | |
1752 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1753 | return ERROR_REG_NUM; | |
1754 | } | |
1755 | ||
1756 | reg = 0; | |
1757 | ||
1758 | while (ISDIGIT ((int) *input_line_pointer)) | |
1759 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1760 | ||
1761 | if (!(next_expr = expression_end (input_line_pointer))) | |
1762 | { | |
1763 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1764 | return ERROR_REG_NUM; | |
1765 | } | |
1766 | ||
1767 | input_line_pointer = (char *) next_expr; | |
1768 | ||
1769 | return reg; | |
1770 | } | |
1771 | ||
1772 | ||
e0001a05 | 1773 | static void |
7fa3d080 | 1774 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1775 | { |
43cd72b9 | 1776 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1777 | |
43cd72b9 BW |
1778 | /* Check if this is an immediate operand. */ |
1779 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1780 | { |
43cd72b9 | 1781 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1782 | segT t = expression (tok); |
43cd72b9 BW |
1783 | if (t == absolute_section |
1784 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 NC |
1785 | { |
1786 | assert (tok->X_op == O_constant); | |
1787 | tok->X_op = O_symbol; | |
1788 | tok->X_add_symbol = &abs_symbol; | |
1789 | } | |
43cd72b9 BW |
1790 | |
1791 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
1792 | && (reloc = xtensa_elf_suffix (&input_line_pointer, tok)) | |
1793 | && (reloc != BFD_RELOC_NONE)) | |
e0001a05 | 1794 | { |
43cd72b9 BW |
1795 | switch (reloc) |
1796 | { | |
1797 | default: | |
1798 | case BFD_RELOC_UNUSED: | |
1799 | as_bad (_("unsupported relocation")); | |
1800 | break; | |
1801 | ||
1802 | case BFD_RELOC_XTENSA_PLT: | |
1803 | tok->X_op = O_pltrel; | |
1804 | break; | |
1805 | ||
1806 | case BFD_RELOC_LO16: | |
1807 | if (tok->X_op == O_constant) | |
1808 | tok->X_add_number &= 0xffff; | |
1809 | else | |
1810 | tok->X_op = O_lo16; | |
1811 | break; | |
1812 | ||
1813 | case BFD_RELOC_HI16: | |
1814 | if (tok->X_op == O_constant) | |
1815 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; | |
1816 | else | |
1817 | tok->X_op = O_hi16; | |
1818 | break; | |
1819 | } | |
e0001a05 | 1820 | } |
e0001a05 NC |
1821 | } |
1822 | else | |
1823 | { | |
43cd72b9 BW |
1824 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1825 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1826 | |
1827 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1828 | { | |
1829 | uint32 buf = reg; | |
43cd72b9 | 1830 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1831 | as_bad (_("register number out of range")); |
1832 | } | |
1833 | ||
1834 | tok->X_op = O_register; | |
1835 | tok->X_add_symbol = 0; | |
1836 | tok->X_add_number = reg; | |
1837 | } | |
1838 | } | |
1839 | ||
1840 | ||
1841 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1842 | ||
1843 | static int | |
7fa3d080 | 1844 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1845 | { |
1846 | char *old_input_line_pointer; | |
1847 | bfd_boolean saw_comma = FALSE; | |
1848 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1849 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1850 | int num_args = 0; |
1851 | char *arg_end, *arg; | |
1852 | int arg_len; | |
43cd72b9 BW |
1853 | |
1854 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1855 | old_input_line_pointer = input_line_pointer; |
1856 | input_line_pointer = str; | |
1857 | ||
1858 | while (*input_line_pointer) | |
1859 | { | |
1860 | SKIP_WHITESPACE (); | |
1861 | switch (*input_line_pointer) | |
1862 | { | |
1863 | case '\0': | |
43cd72b9 | 1864 | case '}': |
e0001a05 NC |
1865 | goto fini; |
1866 | ||
43cd72b9 BW |
1867 | case ':': |
1868 | input_line_pointer++; | |
1869 | if (saw_comma || saw_colon || !saw_arg) | |
1870 | goto err; | |
1871 | saw_colon = TRUE; | |
1872 | break; | |
1873 | ||
e0001a05 NC |
1874 | case ',': |
1875 | input_line_pointer++; | |
43cd72b9 | 1876 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
1877 | goto err; |
1878 | saw_comma = TRUE; | |
1879 | break; | |
1880 | ||
1881 | default: | |
43cd72b9 | 1882 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
1883 | goto err; |
1884 | ||
1885 | arg_end = input_line_pointer + 1; | |
1886 | while (!expression_end (arg_end)) | |
1887 | arg_end += 1; | |
43cd72b9 | 1888 | |
e0001a05 | 1889 | arg_len = arg_end - input_line_pointer; |
43cd72b9 | 1890 | arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
1891 | args[num_args] = arg; |
1892 | ||
43cd72b9 BW |
1893 | if (saw_colon) |
1894 | *arg++ = ':'; | |
e0001a05 NC |
1895 | strncpy (arg, input_line_pointer, arg_len); |
1896 | arg[arg_len] = '\0'; | |
43cd72b9 | 1897 | |
e0001a05 NC |
1898 | input_line_pointer = arg_end; |
1899 | num_args += 1; | |
c138bc38 | 1900 | saw_comma = FALSE; |
43cd72b9 | 1901 | saw_colon = FALSE; |
c138bc38 | 1902 | saw_arg = TRUE; |
e0001a05 NC |
1903 | break; |
1904 | } | |
1905 | } | |
1906 | ||
1907 | fini: | |
43cd72b9 | 1908 | if (saw_comma || saw_colon) |
e0001a05 NC |
1909 | goto err; |
1910 | input_line_pointer = old_input_line_pointer; | |
1911 | return num_args; | |
1912 | ||
1913 | err: | |
43cd72b9 BW |
1914 | if (saw_comma) |
1915 | as_bad (_("extra comma")); | |
1916 | else if (saw_colon) | |
1917 | as_bad (_("extra colon")); | |
1918 | else if (!saw_arg) | |
c138bc38 | 1919 | as_bad (_("missing argument")); |
43cd72b9 BW |
1920 | else |
1921 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
1922 | input_line_pointer = old_input_line_pointer; |
1923 | return -1; | |
1924 | } | |
1925 | ||
1926 | ||
43cd72b9 | 1927 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
1928 | |
1929 | static bfd_boolean | |
7fa3d080 | 1930 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 1931 | { |
43cd72b9 | 1932 | expressionS *tok, *last_tok; |
e0001a05 NC |
1933 | xtensa_opcode opcode = insn->opcode; |
1934 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
1935 | xtensa_isa isa = xtensa_default_isa; |
1936 | int n, num_regs = 0; | |
e0001a05 | 1937 | int opcode_operand_count; |
43cd72b9 BW |
1938 | int opnd_cnt, last_opnd_cnt; |
1939 | unsigned int next_reg = 0; | |
e0001a05 NC |
1940 | char *old_input_line_pointer; |
1941 | ||
1942 | if (insn->insn_type == ITYPE_LITERAL) | |
1943 | opcode_operand_count = 1; | |
1944 | else | |
43cd72b9 | 1945 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 1946 | |
43cd72b9 | 1947 | tok = insn->tok; |
e0001a05 NC |
1948 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
1949 | ||
1950 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
1951 | old_input_line_pointer = input_line_pointer; |
1952 | ||
1953 | last_tok = 0; | |
1954 | last_opnd_cnt = -1; | |
1955 | opnd_cnt = 0; | |
1956 | ||
1957 | /* Skip invisible operands. */ | |
1958 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
1959 | { | |
1960 | opnd_cnt += 1; | |
1961 | tok++; | |
1962 | } | |
e0001a05 NC |
1963 | |
1964 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 1965 | { |
e0001a05 | 1966 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
1967 | if (*input_line_pointer == ':') |
1968 | { | |
1969 | xtensa_regfile opnd_rf; | |
1970 | input_line_pointer++; | |
1971 | if (num_regs == 0) | |
1972 | goto err; | |
1973 | assert (opnd_cnt > 0); | |
1974 | num_regs--; | |
1975 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
1976 | if (next_reg | |
1977 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
1978 | as_warn (_("incorrect register number, ignoring")); | |
1979 | next_reg++; | |
1980 | } | |
1981 | else | |
1982 | { | |
1983 | if (opnd_cnt >= opcode_operand_count) | |
1984 | { | |
1985 | as_warn (_("too many arguments")); | |
1986 | goto err; | |
1987 | } | |
1988 | assert (opnd_cnt < MAX_INSN_ARGS); | |
1989 | ||
1990 | expression_maybe_register (opcode, opnd_cnt, tok); | |
1991 | next_reg = tok->X_add_number + 1; | |
1992 | ||
1993 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
1994 | goto err; | |
1995 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
1996 | { | |
1997 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
1998 | /* minus 1 because we are seeing one right now */ | |
1999 | } | |
2000 | else | |
2001 | num_regs = 0; | |
e0001a05 | 2002 | |
43cd72b9 BW |
2003 | last_tok = tok; |
2004 | last_opnd_cnt = opnd_cnt; | |
e0001a05 | 2005 | |
43cd72b9 BW |
2006 | do |
2007 | { | |
2008 | opnd_cnt += 1; | |
2009 | tok++; | |
2010 | } | |
2011 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
2012 | } | |
2013 | } | |
e0001a05 | 2014 | |
43cd72b9 BW |
2015 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
2016 | goto err; | |
e0001a05 NC |
2017 | |
2018 | insn->ntok = tok - insn->tok; | |
c138bc38 | 2019 | had_error = FALSE; |
e0001a05 NC |
2020 | |
2021 | err: | |
43cd72b9 | 2022 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2023 | return had_error; |
2024 | } | |
2025 | ||
2026 | ||
43cd72b9 | 2027 | static int |
7fa3d080 | 2028 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2029 | { |
2030 | xtensa_isa isa = xtensa_default_isa; | |
2031 | static xtensa_insnbuf slotbuf = NULL; | |
2032 | xtensa_format fmt; | |
2033 | xtensa_opcode opc = insn->opcode; | |
2034 | int slot, opnd, fmt_found; | |
2035 | unsigned val; | |
2036 | ||
2037 | if (!slotbuf) | |
2038 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2039 | ||
2040 | /* Find format/slot where this can be encoded. */ | |
2041 | fmt_found = 0; | |
2042 | slot = 0; | |
2043 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2044 | { | |
2045 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2046 | { | |
2047 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2048 | { | |
2049 | fmt_found = 1; | |
2050 | break; | |
2051 | } | |
2052 | } | |
2053 | if (fmt_found) break; | |
2054 | } | |
2055 | ||
2056 | if (!fmt_found) | |
2057 | { | |
2058 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2059 | return -1; | |
2060 | } | |
2061 | ||
2062 | /* First encode all the visible operands | |
2063 | (to deal with shared field operands). */ | |
2064 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2065 | { | |
2066 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2067 | && (insn->tok[opnd].X_op == O_register | |
2068 | || insn->tok[opnd].X_op == O_constant)) | |
2069 | { | |
2070 | val = insn->tok[opnd].X_add_number; | |
2071 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2072 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2073 | } | |
2074 | } | |
2075 | ||
2076 | /* Then pull out the values for the invisible ones. */ | |
2077 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2078 | { | |
2079 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2080 | { | |
2081 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2082 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2083 | insn->tok[opnd].X_add_number = val; | |
2084 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2085 | insn->tok[opnd].X_op = O_register; | |
2086 | else | |
2087 | insn->tok[opnd].X_op = O_constant; | |
2088 | } | |
2089 | } | |
2090 | ||
2091 | return 0; | |
2092 | } | |
2093 | ||
2094 | ||
e0001a05 | 2095 | static void |
7fa3d080 | 2096 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2097 | { |
2098 | char *cnt_arg, *new_arg; | |
2099 | cnt_arg = *cnt_argp; | |
2100 | ||
2101 | /* replace the argument with "31-(argument)" */ | |
2102 | new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); | |
2103 | sprintf (new_arg, "31-(%s)", cnt_arg); | |
2104 | ||
2105 | free (cnt_arg); | |
2106 | *cnt_argp = new_arg; | |
2107 | } | |
2108 | ||
2109 | ||
2110 | /* If "arg" is a constant expression, return non-zero with the value | |
2111 | in *valp. */ | |
2112 | ||
2113 | static int | |
7fa3d080 | 2114 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2115 | { |
2116 | expressionS exp; | |
2117 | char *save_ptr = input_line_pointer; | |
2118 | ||
2119 | input_line_pointer = arg; | |
2120 | expression (&exp); | |
2121 | input_line_pointer = save_ptr; | |
2122 | ||
2123 | if (exp.X_op == O_constant) | |
2124 | { | |
2125 | *valp = exp.X_add_number; | |
2126 | return 1; | |
2127 | } | |
2128 | ||
2129 | return 0; | |
2130 | } | |
2131 | ||
2132 | ||
2133 | static void | |
7fa3d080 | 2134 | xg_replace_opname (char **popname, char *newop) |
e0001a05 NC |
2135 | { |
2136 | free (*popname); | |
2137 | *popname = (char *) xmalloc (strlen (newop) + 1); | |
2138 | strcpy (*popname, newop); | |
2139 | } | |
2140 | ||
2141 | ||
2142 | static int | |
7fa3d080 BW |
2143 | xg_check_num_args (int *pnum_args, |
2144 | int expected_num, | |
2145 | char *opname, | |
2146 | char **arg_strings) | |
e0001a05 NC |
2147 | { |
2148 | int num_args = *pnum_args; | |
2149 | ||
43cd72b9 | 2150 | if (num_args < expected_num) |
e0001a05 NC |
2151 | { |
2152 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2153 | num_args, opname, expected_num); | |
2154 | return -1; | |
2155 | } | |
2156 | ||
2157 | if (num_args > expected_num) | |
2158 | { | |
2159 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2160 | num_args, opname, expected_num); | |
2161 | while (num_args-- > expected_num) | |
2162 | { | |
2163 | free (arg_strings[num_args]); | |
2164 | arg_strings[num_args] = 0; | |
2165 | } | |
2166 | *pnum_args = expected_num; | |
2167 | return -1; | |
2168 | } | |
2169 | ||
2170 | return 0; | |
2171 | } | |
2172 | ||
2173 | ||
43cd72b9 BW |
2174 | /* If the register is not specified as part of the opcode, |
2175 | then get it from the operand and move it to the opcode. */ | |
2176 | ||
e0001a05 | 2177 | static int |
7fa3d080 | 2178 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2179 | { |
43cd72b9 BW |
2180 | xtensa_isa isa = xtensa_default_isa; |
2181 | xtensa_sysreg sr; | |
e0001a05 | 2182 | char *opname, *new_opname; |
43cd72b9 BW |
2183 | const char *sr_name; |
2184 | int is_user, is_write; | |
e0001a05 NC |
2185 | |
2186 | opname = *popname; | |
2187 | if (*opname == '_') | |
80ca4e2c | 2188 | opname += 1; |
43cd72b9 BW |
2189 | is_user = (opname[1] == 'u'); |
2190 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2191 | |
43cd72b9 | 2192 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2193 | |
43cd72b9 BW |
2194 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2195 | return -1; | |
e0001a05 | 2196 | |
43cd72b9 BW |
2197 | /* Check if the argument is a symbolic register name. */ |
2198 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2199 | /* Handle WSR to "INTSET" as a special case. */ | |
2200 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2201 | && !strcasecmp (arg_strings[1], "intset")) | |
2202 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2203 | if (sr == XTENSA_UNDEFINED | |
2204 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2205 | { | |
2206 | /* Maybe it's a register number.... */ | |
2207 | offsetT val; | |
e0001a05 NC |
2208 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2209 | { | |
43cd72b9 BW |
2210 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2211 | arg_strings[1], opname); | |
e0001a05 NC |
2212 | return -1; |
2213 | } | |
43cd72b9 BW |
2214 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2215 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2216 | { |
43cd72b9 | 2217 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2218 | (long) val, opname); |
e0001a05 NC |
2219 | return -1; |
2220 | } | |
43cd72b9 | 2221 | } |
e0001a05 | 2222 | |
43cd72b9 BW |
2223 | /* Remove the last argument, which is now part of the opcode. */ |
2224 | free (arg_strings[1]); | |
2225 | arg_strings[1] = 0; | |
2226 | *pnum_args = 1; | |
2227 | ||
2228 | /* Translate the opcode. */ | |
2229 | sr_name = xtensa_sysreg_name (isa, sr); | |
2230 | /* Another special case for "WSR.INTSET".... */ | |
2231 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2232 | sr_name = "intset"; | |
2233 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
80ca4e2c | 2234 | sprintf (new_opname, "%s.%s", *popname, sr_name); |
43cd72b9 BW |
2235 | free (*popname); |
2236 | *popname = new_opname; | |
2237 | ||
2238 | return 0; | |
2239 | } | |
2240 | ||
2241 | ||
2242 | static int | |
7fa3d080 | 2243 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2244 | { |
2245 | xtensa_isa isa = xtensa_default_isa; | |
2246 | xtensa_sysreg sr; | |
2247 | char *opname, *new_opname; | |
2248 | const char *sr_name; | |
2249 | bfd_boolean has_underbar = FALSE; | |
2250 | ||
2251 | opname = *popname; | |
2252 | if (opname[0] == '_') | |
2253 | { | |
2254 | has_underbar = TRUE; | |
2255 | opname += 1; | |
2256 | } | |
2257 | ||
2258 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2259 | if (sr != XTENSA_UNDEFINED) | |
2260 | { | |
2261 | /* The new default name ("nnn") is different from the old default | |
2262 | name ("URnnn"). The old default is handled below, and we don't | |
2263 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2264 | default. */ | |
2265 | static char namebuf[10]; | |
2266 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2267 | if (strcmp (namebuf, opname + 1) == 0) | |
2268 | return 0; | |
2269 | } | |
2270 | else | |
2271 | { | |
2272 | offsetT val; | |
2273 | char *end; | |
2274 | ||
2275 | /* Only continue if the reg name is "URnnn". */ | |
2276 | if (opname[1] != 'u' || opname[2] != 'r') | |
2277 | return 0; | |
2278 | val = strtoul (opname + 3, &end, 10); | |
2279 | if (*end != '\0') | |
2280 | return 0; | |
2281 | ||
2282 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2283 | if (sr == XTENSA_UNDEFINED) | |
2284 | { | |
2285 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2286 | (long) val, opname); |
43cd72b9 BW |
2287 | return -1; |
2288 | } | |
2289 | } | |
2290 | ||
2291 | /* Translate the opcode. */ | |
2292 | sr_name = xtensa_sysreg_name (isa, sr); | |
2293 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
2294 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), | |
2295 | opname[0], sr_name); | |
2296 | free (*popname); | |
2297 | *popname = new_opname; | |
2298 | ||
2299 | return 0; | |
2300 | } | |
2301 | ||
2302 | ||
2303 | static int | |
7fa3d080 BW |
2304 | xtensa_translate_zero_immed (char *old_op, |
2305 | char *new_op, | |
2306 | char **popname, | |
2307 | int *pnum_args, | |
2308 | char **arg_strings) | |
43cd72b9 BW |
2309 | { |
2310 | char *opname; | |
2311 | offsetT val; | |
2312 | ||
2313 | opname = *popname; | |
2314 | assert (opname[0] != '_'); | |
2315 | ||
2316 | if (strcmp (opname, old_op) != 0) | |
2317 | return 0; | |
e0001a05 | 2318 | |
43cd72b9 BW |
2319 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2320 | return -1; | |
2321 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2322 | { | |
2323 | xg_replace_opname (popname, new_op); | |
2324 | free (arg_strings[1]); | |
2325 | arg_strings[1] = arg_strings[2]; | |
2326 | arg_strings[2] = 0; | |
2327 | *pnum_args = 2; | |
e0001a05 NC |
2328 | } |
2329 | ||
2330 | return 0; | |
2331 | } | |
2332 | ||
2333 | ||
2334 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2335 | Returns non-zero if an error was found. */ | |
2336 | ||
2337 | static int | |
7fa3d080 | 2338 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2339 | { |
2340 | char *opname = *popname; | |
2341 | bfd_boolean has_underbar = FALSE; | |
2342 | ||
43cd72b9 BW |
2343 | if (cur_vinsn.inside_bundle) |
2344 | return 0; | |
2345 | ||
e0001a05 NC |
2346 | if (*opname == '_') |
2347 | { | |
2348 | has_underbar = TRUE; | |
2349 | opname += 1; | |
2350 | } | |
2351 | ||
2352 | if (strcmp (opname, "mov") == 0) | |
2353 | { | |
43cd72b9 | 2354 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2355 | xg_replace_opname (popname, "mov.n"); |
2356 | else | |
2357 | { | |
2358 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2359 | return -1; | |
2360 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2361 | arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); | |
2362 | strcpy (arg_strings[2], arg_strings[1]); | |
2363 | *pnum_args = 3; | |
2364 | } | |
2365 | return 0; | |
2366 | } | |
2367 | ||
2368 | if (strcmp (opname, "bbsi.l") == 0) | |
2369 | { | |
2370 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2371 | return -1; | |
2372 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2373 | if (target_big_endian) | |
2374 | xg_reverse_shift_count (&arg_strings[1]); | |
2375 | return 0; | |
2376 | } | |
2377 | ||
2378 | if (strcmp (opname, "bbci.l") == 0) | |
2379 | { | |
2380 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2381 | return -1; | |
2382 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2383 | if (target_big_endian) | |
2384 | xg_reverse_shift_count (&arg_strings[1]); | |
2385 | return 0; | |
2386 | } | |
2387 | ||
43cd72b9 BW |
2388 | if (xtensa_nop_opcode == XTENSA_UNDEFINED |
2389 | && strcmp (opname, "nop") == 0) | |
e0001a05 | 2390 | { |
43cd72b9 | 2391 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2392 | xg_replace_opname (popname, "nop.n"); |
2393 | else | |
2394 | { | |
2395 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2396 | return -1; | |
2397 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2398 | arg_strings[0] = (char *) xmalloc (3); | |
2399 | arg_strings[1] = (char *) xmalloc (3); | |
2400 | arg_strings[2] = (char *) xmalloc (3); | |
2401 | strcpy (arg_strings[0], "a1"); | |
2402 | strcpy (arg_strings[1], "a1"); | |
2403 | strcpy (arg_strings[2], "a1"); | |
2404 | *pnum_args = 3; | |
2405 | } | |
2406 | return 0; | |
2407 | } | |
2408 | ||
43cd72b9 BW |
2409 | /* Recognize [RW]UR and [RWX]SR. */ |
2410 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2411 | && (opname[1] == 'u' || opname[1] == 's')) | |
2412 | || (opname[0] == 'x' && opname[1] == 's')) | |
2413 | && opname[2] == 'r' | |
2414 | && opname[3] == '\0') | |
e0001a05 NC |
2415 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2416 | ||
43cd72b9 BW |
2417 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2418 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2419 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2420 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2421 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2422 | |
43cd72b9 BW |
2423 | /* Relax branches that don't allow comparisons against an immediate value |
2424 | of zero to the corresponding branches with implicit zero immediates. */ | |
2425 | if (!has_underbar && use_transform ()) | |
2426 | { | |
2427 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2428 | pnum_args, arg_strings)) | |
2429 | return -1; | |
e0001a05 | 2430 | |
43cd72b9 BW |
2431 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2432 | pnum_args, arg_strings)) | |
2433 | return -1; | |
e0001a05 | 2434 | |
43cd72b9 BW |
2435 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2436 | pnum_args, arg_strings)) | |
2437 | return -1; | |
e0001a05 | 2438 | |
43cd72b9 BW |
2439 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2440 | pnum_args, arg_strings)) | |
2441 | return -1; | |
2442 | } | |
e0001a05 | 2443 | |
43cd72b9 BW |
2444 | return 0; |
2445 | } | |
e0001a05 | 2446 | |
43cd72b9 BW |
2447 | \f |
2448 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2449 | |
43cd72b9 BW |
2450 | /* Currently the assembler only allows us to use a single target per |
2451 | fragment. Because of this, only one operand for a given | |
2452 | instruction may be symbolic. If there is a PC-relative operand, | |
2453 | the last one is chosen. Otherwise, the result is the number of the | |
2454 | last immediate operand, and if there are none of those, we fail and | |
2455 | return -1. */ | |
e0001a05 | 2456 | |
7fa3d080 BW |
2457 | static int |
2458 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2459 | { |
2460 | int last_immed = -1; | |
2461 | int noperands, opi; | |
e0001a05 | 2462 | |
43cd72b9 BW |
2463 | if (opcode == XTENSA_UNDEFINED) |
2464 | return -1; | |
e0001a05 | 2465 | |
43cd72b9 BW |
2466 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2467 | for (opi = noperands - 1; opi >= 0; opi--) | |
2468 | { | |
2469 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2470 | continue; | |
2471 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2472 | return opi; | |
2473 | if (last_immed == -1 | |
2474 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2475 | last_immed = opi; | |
e0001a05 | 2476 | } |
43cd72b9 | 2477 | return last_immed; |
e0001a05 NC |
2478 | } |
2479 | ||
e0001a05 | 2480 | |
43cd72b9 | 2481 | static xtensa_opcode |
7fa3d080 | 2482 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2483 | { |
43cd72b9 BW |
2484 | static xtensa_insnbuf insnbuf = NULL; |
2485 | static xtensa_insnbuf slotbuf = NULL; | |
2486 | xtensa_isa isa = xtensa_default_isa; | |
2487 | xtensa_format fmt; | |
2488 | ||
2489 | if (!insnbuf) | |
e0001a05 | 2490 | { |
43cd72b9 BW |
2491 | insnbuf = xtensa_insnbuf_alloc (isa); |
2492 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2493 | } |
e0001a05 | 2494 | |
d77b99c9 | 2495 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2496 | fmt = xtensa_format_decode (isa, insnbuf); |
2497 | if (fmt == XTENSA_UNDEFINED) | |
2498 | return XTENSA_UNDEFINED; | |
e0001a05 | 2499 | |
43cd72b9 BW |
2500 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2501 | return XTENSA_UNDEFINED; | |
e0001a05 | 2502 | |
43cd72b9 BW |
2503 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2504 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2505 | } |
2506 | ||
2507 | ||
43cd72b9 | 2508 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2509 | |
43cd72b9 | 2510 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2511 | |
7fa3d080 BW |
2512 | static void |
2513 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2514 | { |
2515 | int num_opcodes, num_operands; | |
2516 | xtensa_opcode opcode; | |
2517 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2518 | |
43cd72b9 BW |
2519 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2520 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2521 | { |
43cd72b9 BW |
2522 | int opn; |
2523 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2524 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2525 | for (opn = 0; opn < num_operands; opn++) | |
2526 | { | |
2527 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2528 | continue; | |
2529 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2530 | { | |
2531 | xtensa_regfile opnd_rf = | |
2532 | xtensa_operand_regfile (isa, opcode, opn); | |
2533 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2534 | } | |
2535 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2536 | fputs ("[lLr] ", stderr); | |
2537 | else | |
2538 | fputs ("i ", stderr); | |
2539 | } | |
2540 | fprintf (stderr, "\n"); | |
e0001a05 | 2541 | } |
e0001a05 NC |
2542 | } |
2543 | ||
2544 | ||
43cd72b9 | 2545 | static void |
7fa3d080 | 2546 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2547 | { |
e0001a05 | 2548 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2549 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2550 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2551 | int op; | |
e0001a05 | 2552 | |
43cd72b9 | 2553 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2554 | |
43cd72b9 BW |
2555 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2556 | { | |
2557 | xtensa_opcode opcode; | |
2558 | const char *opname; | |
2559 | int operands; | |
2560 | ||
2561 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2562 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2563 | opname = xtensa_opcode_name (isa, opcode); | |
2564 | ||
2565 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2566 | fprintf (stderr, " operands = "); | |
2567 | for (operands = 0; | |
2568 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2569 | operands++) | |
2570 | { | |
2571 | unsigned int val; | |
2572 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2573 | continue; | |
2574 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2575 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2576 | fprintf (stderr, "%d ", val); | |
2577 | } | |
2578 | fprintf (stderr, "\n"); | |
2579 | } | |
2580 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2581 | } |
2582 | ||
43cd72b9 BW |
2583 | #endif /* TENSILICA_DEBUG */ |
2584 | ||
e0001a05 NC |
2585 | |
2586 | static bfd_boolean | |
7fa3d080 | 2587 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2588 | { |
43cd72b9 BW |
2589 | xtensa_isa isa = xtensa_default_isa; |
2590 | int n, num_operands; | |
e0001a05 | 2591 | |
43cd72b9 | 2592 | if (xtensa_opcode_is_call (isa, opcode) == 0) |
e0001a05 NC |
2593 | return FALSE; |
2594 | ||
43cd72b9 BW |
2595 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2596 | for (n = 0; n < num_operands; n++) | |
2597 | { | |
2598 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2599 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2600 | return TRUE; | |
2601 | } | |
2602 | return FALSE; | |
e0001a05 NC |
2603 | } |
2604 | ||
2605 | ||
43cd72b9 BW |
2606 | /* Convert from BFD relocation type code to slot and operand number. |
2607 | Returns non-zero on failure. */ | |
e0001a05 | 2608 | |
43cd72b9 | 2609 | static int |
7fa3d080 | 2610 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2611 | { |
43cd72b9 BW |
2612 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2613 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2614 | { |
43cd72b9 BW |
2615 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2616 | *is_alt = FALSE; | |
e0001a05 | 2617 | } |
43cd72b9 BW |
2618 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2619 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2620 | { |
43cd72b9 BW |
2621 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2622 | *is_alt = TRUE; | |
e0001a05 | 2623 | } |
43cd72b9 BW |
2624 | else |
2625 | return -1; | |
2626 | ||
2627 | return 0; | |
e0001a05 NC |
2628 | } |
2629 | ||
2630 | ||
43cd72b9 BW |
2631 | /* Convert from slot number to BFD relocation type code for the |
2632 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2633 | failure. */ | |
e0001a05 | 2634 | |
43cd72b9 | 2635 | static bfd_reloc_code_real_type |
7fa3d080 | 2636 | encode_reloc (int slot) |
e0001a05 | 2637 | { |
43cd72b9 BW |
2638 | if (slot < 0 || slot > 14) |
2639 | return BFD_RELOC_NONE; | |
2640 | ||
2641 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2642 | } |
2643 | ||
2644 | ||
43cd72b9 BW |
2645 | /* Convert from slot numbers to BFD relocation type code for the |
2646 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2647 | |
43cd72b9 | 2648 | static bfd_reloc_code_real_type |
7fa3d080 | 2649 | encode_alt_reloc (int slot) |
e0001a05 | 2650 | { |
43cd72b9 BW |
2651 | if (slot < 0 || slot > 14) |
2652 | return BFD_RELOC_NONE; | |
2653 | ||
2654 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2655 | } |
2656 | ||
2657 | ||
2658 | static void | |
7fa3d080 BW |
2659 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2660 | xtensa_format fmt, | |
2661 | int slot, | |
2662 | xtensa_opcode opcode, | |
2663 | int operand, | |
2664 | uint32 value, | |
2665 | const char *file, | |
2666 | unsigned int line) | |
e0001a05 | 2667 | { |
e0001a05 NC |
2668 | uint32 valbuf = value; |
2669 | ||
43cd72b9 | 2670 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2671 | { |
43cd72b9 BW |
2672 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2673 | == 1) | |
2674 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2675 | _("operand %d of '%s' has out of range value '%u'"), |
2676 | operand + 1, | |
2677 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2678 | value); | |
43cd72b9 BW |
2679 | else |
2680 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2681 | _("operand %d of '%s' has invalid value '%u'"), |
2682 | operand + 1, | |
2683 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2684 | value); | |
43cd72b9 | 2685 | return; |
e0001a05 NC |
2686 | } |
2687 | ||
43cd72b9 BW |
2688 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2689 | slotbuf, valbuf); | |
e0001a05 NC |
2690 | } |
2691 | ||
2692 | ||
2693 | static uint32 | |
7fa3d080 BW |
2694 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2695 | xtensa_format fmt, | |
2696 | int slot, | |
2697 | xtensa_opcode opcode, | |
2698 | int opnum) | |
e0001a05 | 2699 | { |
43cd72b9 BW |
2700 | uint32 val = 0; |
2701 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2702 | fmt, slot, slotbuf, &val); | |
2703 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2704 | return val; | |
e0001a05 NC |
2705 | } |
2706 | ||
e0001a05 | 2707 | \f |
7fa3d080 | 2708 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2709 | |
7fa3d080 BW |
2710 | /* The routine xg_instruction_matches_option_term must return TRUE |
2711 | when a given option term is true. The meaning of all of the option | |
2712 | terms is given interpretation by this function. This is needed when | |
2713 | an option depends on the state of a directive, but there are no such | |
2714 | options in use right now. */ | |
e0001a05 | 2715 | |
7fa3d080 BW |
2716 | static bfd_boolean |
2717 | xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED, | |
2718 | const ReqOrOption *option) | |
e0001a05 | 2719 | { |
7fa3d080 BW |
2720 | if (strcmp (option->option_name, "realnop") == 0 |
2721 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2722 | { | |
2723 | /* These conditions were evaluated statically when building the | |
2724 | relaxation table. There's no need to reevaluate them now. */ | |
2725 | return TRUE; | |
2726 | } | |
2727 | else | |
2728 | { | |
2729 | as_fatal (_("internal error: unknown option name '%s'"), | |
2730 | option->option_name); | |
2731 | } | |
e0001a05 NC |
2732 | } |
2733 | ||
2734 | ||
7fa3d080 BW |
2735 | static bfd_boolean |
2736 | xg_instruction_matches_or_options (TInsn *insn, | |
2737 | const ReqOrOptionList *or_option) | |
e0001a05 | 2738 | { |
7fa3d080 BW |
2739 | const ReqOrOption *option; |
2740 | /* Must match each of the AND terms. */ | |
2741 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2742 | { |
7fa3d080 BW |
2743 | if (xg_instruction_matches_option_term (insn, option)) |
2744 | return TRUE; | |
e0001a05 | 2745 | } |
7fa3d080 | 2746 | return FALSE; |
e0001a05 NC |
2747 | } |
2748 | ||
2749 | ||
7fa3d080 BW |
2750 | static bfd_boolean |
2751 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2752 | { |
7fa3d080 BW |
2753 | const ReqOption *req_options; |
2754 | /* Must match each of the AND terms. */ | |
2755 | for (req_options = options; | |
2756 | req_options != NULL; | |
2757 | req_options = req_options->next) | |
e0001a05 | 2758 | { |
7fa3d080 BW |
2759 | /* Must match one of the OR clauses. */ |
2760 | if (!xg_instruction_matches_or_options (insn, | |
2761 | req_options->or_option_terms)) | |
2762 | return FALSE; | |
e0001a05 | 2763 | } |
7fa3d080 | 2764 | return TRUE; |
e0001a05 NC |
2765 | } |
2766 | ||
2767 | ||
7fa3d080 | 2768 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2769 | |
7fa3d080 BW |
2770 | static bfd_boolean |
2771 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2772 | { |
7fa3d080 | 2773 | PreconditionList *condition_l; |
e0001a05 | 2774 | |
7fa3d080 BW |
2775 | if (rule->opcode != insn->opcode) |
2776 | return FALSE; | |
e0001a05 | 2777 | |
7fa3d080 BW |
2778 | for (condition_l = rule->conditions; |
2779 | condition_l != NULL; | |
2780 | condition_l = condition_l->next) | |
e0001a05 | 2781 | { |
7fa3d080 BW |
2782 | expressionS *exp1; |
2783 | expressionS *exp2; | |
2784 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2785 | |
7fa3d080 | 2786 | switch (cond->typ) |
e0001a05 | 2787 | { |
7fa3d080 BW |
2788 | case OP_CONSTANT: |
2789 | /* The expression must be the constant. */ | |
2790 | assert (cond->op_num < insn->ntok); | |
2791 | exp1 = &insn->tok[cond->op_num]; | |
2792 | if (expr_is_const (exp1)) | |
2793 | { | |
2794 | switch (cond->cmp) | |
2795 | { | |
2796 | case OP_EQUAL: | |
2797 | if (get_expr_const (exp1) != cond->op_data) | |
2798 | return FALSE; | |
2799 | break; | |
2800 | case OP_NOTEQUAL: | |
2801 | if (get_expr_const (exp1) == cond->op_data) | |
2802 | return FALSE; | |
2803 | break; | |
2804 | default: | |
2805 | return FALSE; | |
2806 | } | |
2807 | } | |
2808 | else if (expr_is_register (exp1)) | |
2809 | { | |
2810 | switch (cond->cmp) | |
2811 | { | |
2812 | case OP_EQUAL: | |
2813 | if (get_expr_register (exp1) != cond->op_data) | |
2814 | return FALSE; | |
2815 | break; | |
2816 | case OP_NOTEQUAL: | |
2817 | if (get_expr_register (exp1) == cond->op_data) | |
2818 | return FALSE; | |
2819 | break; | |
2820 | default: | |
2821 | return FALSE; | |
2822 | } | |
2823 | } | |
2824 | else | |
2825 | return FALSE; | |
2826 | break; | |
2827 | ||
2828 | case OP_OPERAND: | |
2829 | assert (cond->op_num < insn->ntok); | |
2830 | assert (cond->op_data < insn->ntok); | |
2831 | exp1 = &insn->tok[cond->op_num]; | |
2832 | exp2 = &insn->tok[cond->op_data]; | |
2833 | ||
2834 | switch (cond->cmp) | |
2835 | { | |
2836 | case OP_EQUAL: | |
2837 | if (!expr_is_equal (exp1, exp2)) | |
2838 | return FALSE; | |
2839 | break; | |
2840 | case OP_NOTEQUAL: | |
2841 | if (expr_is_equal (exp1, exp2)) | |
2842 | return FALSE; | |
2843 | break; | |
2844 | } | |
2845 | break; | |
2846 | ||
2847 | case OP_LITERAL: | |
2848 | case OP_LABEL: | |
2849 | default: | |
2850 | return FALSE; | |
2851 | } | |
2852 | } | |
2853 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2854 | return FALSE; | |
2855 | ||
2856 | return TRUE; | |
2857 | } | |
2858 | ||
2859 | ||
2860 | static int | |
2861 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2862 | { | |
2863 | bfd_boolean a_greater = FALSE; | |
2864 | bfd_boolean b_greater = FALSE; | |
2865 | ||
2866 | ReqOptionList *l_a = a->options; | |
2867 | ReqOptionList *l_b = b->options; | |
2868 | ||
2869 | /* We only care if they both are the same except for | |
2870 | a const16 vs. an l32r. */ | |
2871 | ||
2872 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2873 | { | |
2874 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2875 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2876 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2877 | { | |
2878 | if (l_or_a->is_true != l_or_b->is_true) | |
2879 | return 0; | |
2880 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2881 | { | |
2882 | /* This is the case we care about. */ | |
2883 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
2884 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
2885 | { | |
2886 | if (prefer_const16) | |
2887 | a_greater = TRUE; | |
2888 | else | |
2889 | b_greater = TRUE; | |
2890 | } | |
2891 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
2892 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
2893 | { | |
2894 | if (prefer_const16) | |
2895 | b_greater = TRUE; | |
2896 | else | |
2897 | a_greater = TRUE; | |
2898 | } | |
2899 | else | |
2900 | return 0; | |
2901 | } | |
2902 | l_or_a = l_or_a->next; | |
2903 | l_or_b = l_or_b->next; | |
2904 | } | |
2905 | if (l_or_a || l_or_b) | |
2906 | return 0; | |
2907 | ||
2908 | l_a = l_a->next; | |
2909 | l_b = l_b->next; | |
2910 | } | |
2911 | if (l_a || l_b) | |
2912 | return 0; | |
2913 | ||
2914 | /* Incomparable if the substitution was used differently in two cases. */ | |
2915 | if (a_greater && b_greater) | |
2916 | return 0; | |
2917 | ||
2918 | if (b_greater) | |
2919 | return 1; | |
2920 | if (a_greater) | |
2921 | return -1; | |
2922 | ||
2923 | return 0; | |
2924 | } | |
2925 | ||
2926 | ||
2927 | static TransitionRule * | |
2928 | xg_instruction_match (TInsn *insn) | |
2929 | { | |
2930 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
2931 | TransitionList *l; | |
2932 | assert (insn->opcode < table->num_opcodes); | |
2933 | ||
2934 | /* Walk through all of the possible transitions. */ | |
2935 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2936 | { | |
2937 | TransitionRule *rule = l->rule; | |
2938 | if (xg_instruction_matches_rule (insn, rule)) | |
2939 | return rule; | |
2940 | } | |
2941 | return NULL; | |
2942 | } | |
2943 | ||
2944 | \f | |
2945 | /* Various Other Internal Functions. */ | |
2946 | ||
2947 | static bfd_boolean | |
2948 | is_unique_insn_expansion (TransitionRule *r) | |
2949 | { | |
2950 | if (!r->to_instr || r->to_instr->next != NULL) | |
2951 | return FALSE; | |
2952 | if (r->to_instr->typ != INSTR_INSTR) | |
2953 | return FALSE; | |
2954 | return TRUE; | |
2955 | } | |
2956 | ||
2957 | ||
84b08ed9 BW |
2958 | /* Check if there is exactly one relaxation for INSN that converts it to |
2959 | another instruction of equal or larger size. If so, and if TARG is | |
2960 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
2961 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
2962 | instruction, i.e., ignore relaxations that convert to an instruction of | |
2963 | equal size. In some contexts where this function is used, only | |
c138bc38 | 2964 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
2965 | exclude cases like ADDI being "widened" to an ADDMI, which may |
2966 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 2967 | |
84b08ed9 BW |
2968 | bfd_boolean |
2969 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
2970 | { |
2971 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
2972 | TransitionList *l; | |
84b08ed9 | 2973 | TransitionRule *match = 0; |
7fa3d080 | 2974 | |
7fa3d080 BW |
2975 | assert (insn->insn_type == ITYPE_INSN); |
2976 | assert (insn->opcode < table->num_opcodes); | |
2977 | ||
2978 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2979 | { | |
2980 | TransitionRule *rule = l->rule; | |
2981 | ||
2982 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
2983 | && is_unique_insn_expansion (rule) |
2984 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
2985 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 2986 | { |
84b08ed9 BW |
2987 | if (match) |
2988 | return FALSE; | |
2989 | match = rule; | |
7fa3d080 BW |
2990 | } |
2991 | } | |
84b08ed9 BW |
2992 | if (!match) |
2993 | return FALSE; | |
2994 | ||
2995 | if (targ) | |
2996 | xg_build_to_insn (targ, insn, match->to_instr); | |
2997 | return TRUE; | |
7fa3d080 BW |
2998 | } |
2999 | ||
3000 | ||
3001 | /* Return the maximum number of bytes this opcode can expand to. */ | |
3002 | ||
3003 | static int | |
3004 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
3005 | { | |
3006 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3007 | TransitionList *l; | |
3008 | int max_size = xg_get_single_size (opcode); | |
3009 | ||
3010 | assert (opcode < table->num_opcodes); | |
3011 | ||
3012 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3013 | { | |
3014 | TransitionRule *rule = l->rule; | |
3015 | BuildInstr *build_list; | |
3016 | int this_size = 0; | |
3017 | ||
3018 | if (!rule) | |
3019 | continue; | |
3020 | build_list = rule->to_instr; | |
3021 | if (is_unique_insn_expansion (rule)) | |
3022 | { | |
3023 | assert (build_list->typ == INSTR_INSTR); | |
3024 | this_size = xg_get_max_insn_widen_size (build_list->opcode); | |
3025 | } | |
3026 | else | |
3027 | for (; build_list != NULL; build_list = build_list->next) | |
3028 | { | |
3029 | switch (build_list->typ) | |
3030 | { | |
3031 | case INSTR_INSTR: | |
3032 | this_size += xg_get_single_size (build_list->opcode); | |
3033 | break; | |
3034 | case INSTR_LITERAL_DEF: | |
3035 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3036 | default: |
3037 | break; | |
3038 | } | |
3039 | } | |
3040 | if (this_size > max_size) | |
3041 | max_size = this_size; | |
3042 | } | |
3043 | return max_size; | |
3044 | } | |
3045 | ||
3046 | ||
3047 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3048 | ||
7fa3d080 BW |
3049 | static int |
3050 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3051 | { |
43cd72b9 | 3052 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3053 | TransitionList *l; |
3054 | int max_size = 0; | |
3055 | ||
3056 | assert (opcode < table->num_opcodes); | |
3057 | ||
3058 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3059 | { | |
3060 | TransitionRule *rule = l->rule; | |
3061 | BuildInstr *build_list; | |
3062 | int this_size = 0; | |
3063 | ||
3064 | if (!rule) | |
3065 | continue; | |
3066 | build_list = rule->to_instr; | |
3067 | if (is_unique_insn_expansion (rule)) | |
3068 | { | |
3069 | assert (build_list->typ == INSTR_INSTR); | |
3070 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); | |
3071 | } | |
3072 | else | |
3073 | for (; build_list != NULL; build_list = build_list->next) | |
3074 | { | |
3075 | switch (build_list->typ) | |
3076 | { | |
3077 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3078 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3079 | this_size += 4; |
3080 | break; | |
3081 | case INSTR_INSTR: | |
3082 | case INSTR_LABEL_DEF: | |
3083 | default: | |
3084 | break; | |
3085 | } | |
3086 | } | |
3087 | if (this_size > max_size) | |
3088 | max_size = this_size; | |
3089 | } | |
3090 | return max_size; | |
3091 | } | |
3092 | ||
3093 | ||
7fa3d080 BW |
3094 | static bfd_boolean |
3095 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3096 | { | |
3097 | int steps_taken = 0; | |
3098 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3099 | TransitionList *l; | |
3100 | ||
3101 | assert (insn->insn_type == ITYPE_INSN); | |
3102 | assert (insn->opcode < table->num_opcodes); | |
3103 | ||
3104 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3105 | { | |
3106 | TransitionRule *rule = l->rule; | |
3107 | ||
3108 | if (xg_instruction_matches_rule (insn, rule)) | |
3109 | { | |
3110 | if (steps_taken == lateral_steps) | |
3111 | return TRUE; | |
3112 | steps_taken++; | |
3113 | } | |
3114 | } | |
3115 | return FALSE; | |
3116 | } | |
3117 | ||
3118 | ||
3119 | static symbolS * | |
3120 | get_special_literal_symbol (void) | |
3121 | { | |
3122 | static symbolS *sym = NULL; | |
3123 | ||
3124 | if (sym == NULL) | |
3125 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3126 | return sym; | |
3127 | } | |
3128 | ||
3129 | ||
3130 | static symbolS * | |
3131 | get_special_label_symbol (void) | |
3132 | { | |
3133 | static symbolS *sym = NULL; | |
3134 | ||
3135 | if (sym == NULL) | |
3136 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3137 | return sym; | |
3138 | } | |
3139 | ||
3140 | ||
3141 | static bfd_boolean | |
3142 | xg_valid_literal_expression (const expressionS *exp) | |
3143 | { | |
3144 | switch (exp->X_op) | |
3145 | { | |
3146 | case O_constant: | |
3147 | case O_symbol: | |
3148 | case O_big: | |
3149 | case O_uminus: | |
3150 | case O_subtract: | |
3151 | case O_pltrel: | |
3152 | return TRUE; | |
3153 | default: | |
3154 | return FALSE; | |
3155 | } | |
3156 | } | |
3157 | ||
3158 | ||
3159 | /* This will check to see if the value can be converted into the | |
3160 | operand type. It will return TRUE if it does not fit. */ | |
3161 | ||
3162 | static bfd_boolean | |
3163 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3164 | { | |
3165 | uint32 valbuf = value; | |
3166 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3167 | return TRUE; | |
3168 | return FALSE; | |
3169 | } | |
3170 | ||
3171 | ||
3172 | /* Assumes: All immeds are constants. Check that all constants fit | |
3173 | into their immeds; return FALSE if not. */ | |
3174 | ||
3175 | static bfd_boolean | |
3176 | xg_immeds_fit (const TInsn *insn) | |
3177 | { | |
3178 | xtensa_isa isa = xtensa_default_isa; | |
3179 | int i; | |
3180 | ||
3181 | int n = insn->ntok; | |
3182 | assert (insn->insn_type == ITYPE_INSN); | |
3183 | for (i = 0; i < n; ++i) | |
3184 | { | |
3185 | const expressionS *expr = &insn->tok[i]; | |
3186 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3187 | continue; | |
3188 | ||
3189 | switch (expr->X_op) | |
3190 | { | |
3191 | case O_register: | |
3192 | case O_constant: | |
3193 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3194 | return FALSE; | |
3195 | break; | |
3196 | ||
3197 | default: | |
3198 | /* The symbol should have a fixup associated with it. */ | |
3199 | assert (FALSE); | |
3200 | break; | |
3201 | } | |
3202 | } | |
3203 | return TRUE; | |
3204 | } | |
3205 | ||
3206 | ||
3207 | /* This should only be called after we have an initial | |
3208 | estimate of the addresses. */ | |
3209 | ||
3210 | static bfd_boolean | |
3211 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3212 | segT pc_seg, | |
3213 | fragS *pc_frag, | |
3214 | offsetT pc_offset, | |
3215 | long stretch) | |
e0001a05 | 3216 | { |
7fa3d080 BW |
3217 | xtensa_isa isa = xtensa_default_isa; |
3218 | symbolS *symbolP; | |
3219 | fragS *sym_frag; | |
3220 | offsetT target, pc; | |
3221 | uint32 new_offset; | |
3222 | int i; | |
3223 | int n = insn->ntok; | |
e0001a05 NC |
3224 | |
3225 | assert (insn->insn_type == ITYPE_INSN); | |
e0001a05 | 3226 | |
7fa3d080 | 3227 | for (i = 0; i < n; ++i) |
e0001a05 | 3228 | { |
7fa3d080 BW |
3229 | const expressionS *expr = &insn->tok[i]; |
3230 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3231 | continue; | |
e0001a05 | 3232 | |
7fa3d080 | 3233 | switch (expr->X_op) |
e0001a05 | 3234 | { |
7fa3d080 BW |
3235 | case O_register: |
3236 | case O_constant: | |
3237 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3238 | return FALSE; | |
3239 | break; | |
e0001a05 | 3240 | |
7fa3d080 BW |
3241 | case O_lo16: |
3242 | case O_hi16: | |
3243 | /* Check for the worst case. */ | |
3244 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3245 | return FALSE; | |
3246 | break; | |
e0001a05 | 3247 | |
7fa3d080 | 3248 | case O_symbol: |
7c834684 | 3249 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3250 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3251 | if (pc_frag == 0 |
3252 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3253 | return FALSE; |
e0001a05 | 3254 | |
7c834684 BW |
3255 | /* If it is a weak symbol, then assume it won't reach. */ |
3256 | if (S_IS_WEAK (expr->X_add_symbol)) | |
7fa3d080 | 3257 | return FALSE; |
e0001a05 | 3258 | |
7c834684 BW |
3259 | if (is_direct_call_opcode (insn->opcode) |
3260 | && ! pc_frag->tc_frag_data.use_longcalls) | |
3261 | { | |
3262 | /* If callee is undefined or in a different segment, be | |
3263 | optimistic and assume it will be in range. */ | |
3264 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
3265 | return TRUE; | |
3266 | } | |
3267 | ||
3268 | /* Only references within a segment can be known to fit in the | |
3269 | operands at assembly time. */ | |
3270 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
7fa3d080 | 3271 | return FALSE; |
e0001a05 | 3272 | |
7fa3d080 BW |
3273 | symbolP = expr->X_add_symbol; |
3274 | sym_frag = symbol_get_frag (symbolP); | |
3275 | target = S_GET_VALUE (symbolP) + expr->X_add_number; | |
3276 | pc = pc_frag->fr_address + pc_offset; | |
e0001a05 | 3277 | |
7fa3d080 BW |
3278 | /* If frag has yet to be reached on this pass, assume it |
3279 | will move by STRETCH just as we did. If this is not so, | |
3280 | it will be because some frag between grows, and that will | |
3281 | force another pass. Beware zero-length frags. There | |
3282 | should be a faster way to do this. */ | |
3283 | ||
3284 | if (stretch != 0 | |
3285 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3286 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3287 | { | |
3288 | target += stretch; | |
3289 | } | |
c138bc38 | 3290 | |
7fa3d080 BW |
3291 | new_offset = target; |
3292 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3293 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3294 | return FALSE; | |
3295 | break; | |
3296 | ||
3297 | default: | |
3298 | /* The symbol should have a fixup associated with it. */ | |
3299 | return FALSE; | |
3300 | } | |
3301 | } | |
3302 | ||
3303 | return TRUE; | |
e0001a05 NC |
3304 | } |
3305 | ||
3306 | ||
43cd72b9 | 3307 | /* Return TRUE on success. */ |
e0001a05 | 3308 | |
7fa3d080 BW |
3309 | static bfd_boolean |
3310 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3311 | { |
3312 | BuildOp *op; | |
3313 | symbolS *sym; | |
3314 | ||
3315 | memset (targ, 0, sizeof (TInsn)); | |
7c430684 | 3316 | targ->linenum = insn->linenum; |
e0001a05 NC |
3317 | switch (bi->typ) |
3318 | { | |
3319 | case INSTR_INSTR: | |
3320 | op = bi->ops; | |
3321 | targ->opcode = bi->opcode; | |
3322 | targ->insn_type = ITYPE_INSN; | |
3323 | targ->is_specific_opcode = FALSE; | |
3324 | ||
3325 | for (; op != NULL; op = op->next) | |
3326 | { | |
3327 | int op_num = op->op_num; | |
3328 | int op_data = op->op_data; | |
3329 | ||
3330 | assert (op->op_num < MAX_INSN_ARGS); | |
3331 | ||
3332 | if (targ->ntok <= op_num) | |
3333 | targ->ntok = op_num + 1; | |
3334 | ||
3335 | switch (op->typ) | |
3336 | { | |
3337 | case OP_CONSTANT: | |
3338 | set_expr_const (&targ->tok[op_num], op_data); | |
3339 | break; | |
3340 | case OP_OPERAND: | |
3341 | assert (op_data < insn->ntok); | |
3342 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3343 | break; | |
3344 | case OP_LITERAL: | |
3345 | sym = get_special_literal_symbol (); | |
3346 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3347 | break; | |
3348 | case OP_LABEL: | |
3349 | sym = get_special_label_symbol (); | |
3350 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3351 | break; | |
43cd72b9 BW |
3352 | case OP_OPERAND_HI16U: |
3353 | case OP_OPERAND_LOW16U: | |
3354 | assert (op_data < insn->ntok); | |
3355 | if (expr_is_const (&insn->tok[op_data])) | |
3356 | { | |
3357 | long val; | |
3358 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3359 | val = xg_apply_userdef_op_fn (op->typ, | |
3360 | targ->tok[op_num]. | |
3361 | X_add_number); | |
3362 | targ->tok[op_num].X_add_number = val; | |
3363 | } | |
3364 | else | |
3365 | { | |
3366 | /* For const16 we can create relocations for these. */ | |
3367 | if (targ->opcode == XTENSA_UNDEFINED | |
3368 | || (targ->opcode != xtensa_const16_opcode)) | |
3369 | return FALSE; | |
3370 | assert (op_data < insn->ntok); | |
3371 | /* Need to build a O_lo16 or O_hi16. */ | |
3372 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3373 | if (targ->tok[op_num].X_op == O_symbol) | |
3374 | { | |
3375 | if (op->typ == OP_OPERAND_HI16U) | |
3376 | targ->tok[op_num].X_op = O_hi16; | |
3377 | else if (op->typ == OP_OPERAND_LOW16U) | |
3378 | targ->tok[op_num].X_op = O_lo16; | |
3379 | else | |
3380 | return FALSE; | |
3381 | } | |
3382 | } | |
3383 | break; | |
e0001a05 NC |
3384 | default: |
3385 | /* currently handles: | |
3386 | OP_OPERAND_LOW8 | |
3387 | OP_OPERAND_HI24S | |
3388 | OP_OPERAND_F32MINUS */ | |
3389 | if (xg_has_userdef_op_fn (op->typ)) | |
3390 | { | |
3391 | assert (op_data < insn->ntok); | |
3392 | if (expr_is_const (&insn->tok[op_data])) | |
3393 | { | |
3394 | long val; | |
3395 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3396 | val = xg_apply_userdef_op_fn (op->typ, | |
3397 | targ->tok[op_num]. | |
3398 | X_add_number); | |
3399 | targ->tok[op_num].X_add_number = val; | |
3400 | } | |
3401 | else | |
3402 | return FALSE; /* We cannot use a relocation for this. */ | |
3403 | break; | |
3404 | } | |
3405 | assert (0); | |
3406 | break; | |
3407 | } | |
3408 | } | |
3409 | break; | |
3410 | ||
3411 | case INSTR_LITERAL_DEF: | |
3412 | op = bi->ops; | |
3413 | targ->opcode = XTENSA_UNDEFINED; | |
3414 | targ->insn_type = ITYPE_LITERAL; | |
3415 | targ->is_specific_opcode = FALSE; | |
3416 | for (; op != NULL; op = op->next) | |
3417 | { | |
3418 | int op_num = op->op_num; | |
3419 | int op_data = op->op_data; | |
3420 | assert (op->op_num < MAX_INSN_ARGS); | |
3421 | ||
3422 | if (targ->ntok <= op_num) | |
3423 | targ->ntok = op_num + 1; | |
3424 | ||
3425 | switch (op->typ) | |
3426 | { | |
3427 | case OP_OPERAND: | |
3428 | assert (op_data < insn->ntok); | |
43cd72b9 BW |
3429 | /* We can only pass resolvable literals through. */ |
3430 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3431 | return FALSE; | |
e0001a05 NC |
3432 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3433 | break; | |
3434 | case OP_LITERAL: | |
3435 | case OP_CONSTANT: | |
3436 | case OP_LABEL: | |
3437 | default: | |
3438 | assert (0); | |
3439 | break; | |
3440 | } | |
3441 | } | |
3442 | break; | |
3443 | ||
3444 | case INSTR_LABEL_DEF: | |
3445 | op = bi->ops; | |
3446 | targ->opcode = XTENSA_UNDEFINED; | |
3447 | targ->insn_type = ITYPE_LABEL; | |
3448 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3449 | /* Literal with no ops is a label? */ |
e0001a05 NC |
3450 | assert (op == NULL); |
3451 | break; | |
3452 | ||
3453 | default: | |
3454 | assert (0); | |
3455 | } | |
3456 | ||
3457 | return TRUE; | |
3458 | } | |
3459 | ||
3460 | ||
43cd72b9 | 3461 | /* Return TRUE on success. */ |
e0001a05 | 3462 | |
7fa3d080 BW |
3463 | static bfd_boolean |
3464 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3465 | { |
3466 | for (; bi != NULL; bi = bi->next) | |
3467 | { | |
3468 | TInsn *next_insn = istack_push_space (istack); | |
3469 | ||
3470 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3471 | return FALSE; | |
3472 | } | |
3473 | return TRUE; | |
3474 | } | |
3475 | ||
3476 | ||
43cd72b9 | 3477 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3478 | |
7fa3d080 BW |
3479 | static bfd_boolean |
3480 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3481 | { |
3482 | int stack_size = istack->ninsn; | |
3483 | int steps_taken = 0; | |
43cd72b9 | 3484 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3485 | TransitionList *l; |
3486 | ||
3487 | assert (insn->insn_type == ITYPE_INSN); | |
3488 | assert (insn->opcode < table->num_opcodes); | |
3489 | ||
3490 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3491 | { | |
3492 | TransitionRule *rule = l->rule; | |
3493 | ||
3494 | if (xg_instruction_matches_rule (insn, rule)) | |
3495 | { | |
3496 | if (lateral_steps == steps_taken) | |
3497 | { | |
3498 | int i; | |
3499 | ||
3500 | /* This is it. Expand the rule to the stack. */ | |
3501 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3502 | return FALSE; | |
3503 | ||
3504 | /* Check to see if it fits. */ | |
3505 | for (i = stack_size; i < istack->ninsn; i++) | |
3506 | { | |
3507 | TInsn *insn = &istack->insn[i]; | |
3508 | ||
3509 | if (insn->insn_type == ITYPE_INSN | |
3510 | && !tinsn_has_symbolic_operands (insn) | |
3511 | && !xg_immeds_fit (insn)) | |
3512 | { | |
3513 | istack->ninsn = stack_size; | |
3514 | return FALSE; | |
3515 | } | |
3516 | } | |
3517 | return TRUE; | |
3518 | } | |
3519 | steps_taken++; | |
3520 | } | |
3521 | } | |
3522 | return FALSE; | |
3523 | } | |
3524 | ||
43cd72b9 | 3525 | \f |
43cd72b9 BW |
3526 | /* Relax the assembly instruction at least "min_steps". |
3527 | Return the number of steps taken. */ | |
e0001a05 | 3528 | |
7fa3d080 BW |
3529 | static int |
3530 | xg_assembly_relax (IStack *istack, | |
3531 | TInsn *insn, | |
3532 | segT pc_seg, | |
3533 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3534 | offsetT pc_offset, /* offset in fragment */ | |
3535 | int min_steps, /* minimum conversion steps */ | |
3536 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3537 | { |
3538 | int steps_taken = 0; | |
3539 | ||
3540 | /* assert (has no symbolic operands) | |
3541 | Some of its immeds don't fit. | |
3542 | Try to build a relaxed version. | |
3543 | This may go through a couple of stages | |
3544 | of single instruction transformations before | |
3545 | we get there. */ | |
3546 | ||
3547 | TInsn single_target; | |
3548 | TInsn current_insn; | |
3549 | int lateral_steps = 0; | |
3550 | int istack_size = istack->ninsn; | |
3551 | ||
3552 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3553 | && steps_taken >= min_steps) | |
3554 | { | |
3555 | istack_push (istack, insn); | |
3556 | return steps_taken; | |
3557 | } | |
43cd72b9 | 3558 | current_insn = *insn; |
e0001a05 | 3559 | |
7c834684 | 3560 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3561 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3562 | { |
21af2bbd | 3563 | steps_taken++; |
e0001a05 NC |
3564 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3565 | stretch)) | |
3566 | { | |
e0001a05 NC |
3567 | if (steps_taken >= min_steps) |
3568 | { | |
3569 | istack_push (istack, &single_target); | |
3570 | return steps_taken; | |
3571 | } | |
3572 | } | |
43cd72b9 | 3573 | current_insn = single_target; |
e0001a05 NC |
3574 | } |
3575 | ||
3576 | /* Now check for a multi-instruction expansion. */ | |
3577 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3578 | { | |
3579 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3580 | stretch)) | |
3581 | { | |
3582 | if (steps_taken >= min_steps) | |
3583 | { | |
3584 | istack_push (istack, ¤t_insn); | |
3585 | return steps_taken; | |
3586 | } | |
3587 | } | |
3588 | steps_taken++; | |
3589 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3590 | { | |
3591 | if (steps_taken >= min_steps) | |
3592 | return steps_taken; | |
3593 | } | |
3594 | lateral_steps++; | |
3595 | istack->ninsn = istack_size; | |
3596 | } | |
3597 | ||
3598 | /* It's not going to work -- use the original. */ | |
3599 | istack_push (istack, insn); | |
3600 | return steps_taken; | |
3601 | } | |
3602 | ||
3603 | ||
3604 | static void | |
7fa3d080 | 3605 | xg_force_frag_space (int size) |
e0001a05 NC |
3606 | { |
3607 | /* This may have the side effect of creating a new fragment for the | |
3608 | space to go into. I just do not like the name of the "frag" | |
3609 | functions. */ | |
3610 | frag_grow (size); | |
3611 | } | |
3612 | ||
3613 | ||
7fa3d080 BW |
3614 | static void |
3615 | xg_finish_frag (char *last_insn, | |
3616 | enum xtensa_relax_statesE frag_state, | |
3617 | enum xtensa_relax_statesE slot0_state, | |
3618 | int max_growth, | |
3619 | bfd_boolean is_insn) | |
e0001a05 NC |
3620 | { |
3621 | /* Finish off this fragment so that it has at LEAST the desired | |
3622 | max_growth. If it doesn't fit in this fragment, close this one | |
3623 | and start a new one. In either case, return a pointer to the | |
3624 | beginning of the growth area. */ | |
3625 | ||
3626 | fragS *old_frag; | |
43cd72b9 | 3627 | |
e0001a05 NC |
3628 | xg_force_frag_space (max_growth); |
3629 | ||
3630 | old_frag = frag_now; | |
3631 | ||
3632 | frag_now->fr_opcode = last_insn; | |
3633 | if (is_insn) | |
3634 | frag_now->tc_frag_data.is_insn = TRUE; | |
3635 | ||
3636 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3637 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3638 | ||
3639 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3640 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3641 | |
3642 | /* Just to make sure that we did not split it up. */ | |
3643 | assert (old_frag->fr_next == frag_now); | |
3644 | } | |
3645 | ||
3646 | ||
7fa3d080 BW |
3647 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3648 | ||
3649 | static bfd_boolean | |
3650 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3651 | { | |
3652 | if (fragP == NULL) | |
3653 | return FALSE; | |
3654 | ||
3655 | for (; fragP; fragP = fragP->fr_next) | |
3656 | { | |
3657 | if (fragP == target) | |
3658 | return TRUE; | |
3659 | if (fragP->fr_fix != 0) | |
3660 | return FALSE; | |
3661 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3662 | return FALSE; | |
3663 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3664 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3665 | return FALSE; | |
3666 | if (fragP->fr_type == rs_space) | |
3667 | return FALSE; | |
3668 | } | |
3669 | return FALSE; | |
3670 | } | |
3671 | ||
3672 | ||
e0001a05 | 3673 | static bfd_boolean |
7fa3d080 | 3674 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3675 | { |
3676 | xtensa_isa isa = xtensa_default_isa; | |
3677 | int i; | |
43cd72b9 | 3678 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3679 | int target_op = -1; |
3680 | symbolS *sym; | |
3681 | fragS *target_frag; | |
3682 | ||
43cd72b9 BW |
3683 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 0 |
3684 | && xtensa_opcode_is_jump (isa, insn->opcode) == 0) | |
e0001a05 NC |
3685 | return FALSE; |
3686 | ||
3687 | for (i = 0; i < num_ops; i++) | |
3688 | { | |
43cd72b9 | 3689 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3690 | { |
3691 | target_op = i; | |
3692 | break; | |
3693 | } | |
3694 | } | |
3695 | if (target_op == -1) | |
3696 | return FALSE; | |
3697 | ||
3698 | if (insn->ntok <= target_op) | |
3699 | return FALSE; | |
3700 | ||
3701 | if (insn->tok[target_op].X_op != O_symbol) | |
3702 | return FALSE; | |
3703 | ||
3704 | sym = insn->tok[target_op].X_add_symbol; | |
3705 | if (sym == NULL) | |
3706 | return FALSE; | |
3707 | ||
3708 | if (insn->tok[target_op].X_add_number != 0) | |
3709 | return FALSE; | |
3710 | ||
3711 | target_frag = symbol_get_frag (sym); | |
3712 | if (target_frag == NULL) | |
3713 | return FALSE; | |
3714 | ||
c138bc38 | 3715 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3716 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3717 | return TRUE; | |
3718 | ||
3719 | return FALSE; | |
3720 | } | |
3721 | ||
3722 | ||
3723 | static void | |
7fa3d080 | 3724 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3725 | { |
3726 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3727 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3728 | |
7fa3d080 BW |
3729 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3730 | { | |
3731 | int i = 1; | |
3732 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3733 | && insn->tok[i].X_op == O_symbol) | |
3734 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3735 | return; | |
3736 | } | |
e0001a05 | 3737 | |
7fa3d080 BW |
3738 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3739 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3740 | { |
7fa3d080 BW |
3741 | int i; |
3742 | ||
3743 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3744 | { | |
3745 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3746 | && insn->tok[i].X_op == O_symbol) | |
3747 | { | |
3748 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3749 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3750 | if (S_IS_DEFINED (sym)) | |
3751 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3752 | } | |
3753 | } | |
e0001a05 | 3754 | } |
e0001a05 NC |
3755 | } |
3756 | ||
3757 | ||
43cd72b9 | 3758 | /* Return FALSE if no error. */ |
e0001a05 | 3759 | |
7fa3d080 BW |
3760 | static bfd_boolean |
3761 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3762 | { |
3763 | int num_ops = 0; | |
3764 | BuildOp *b_op; | |
3765 | ||
3766 | switch (instr_spec->typ) | |
3767 | { | |
3768 | case INSTR_INSTR: | |
3769 | new_insn->insn_type = ITYPE_INSN; | |
3770 | new_insn->opcode = instr_spec->opcode; | |
3771 | new_insn->is_specific_opcode = FALSE; | |
7c430684 | 3772 | new_insn->linenum = old_insn->linenum; |
e0001a05 NC |
3773 | break; |
3774 | case INSTR_LITERAL_DEF: | |
3775 | new_insn->insn_type = ITYPE_LITERAL; | |
3776 | new_insn->opcode = XTENSA_UNDEFINED; | |
3777 | new_insn->is_specific_opcode = FALSE; | |
7c430684 | 3778 | new_insn->linenum = old_insn->linenum; |
e0001a05 NC |
3779 | break; |
3780 | case INSTR_LABEL_DEF: | |
3781 | as_bad (_("INSTR_LABEL_DEF not supported yet")); | |
3782 | break; | |
3783 | } | |
3784 | ||
3785 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3786 | { | |
3787 | expressionS *exp; | |
3788 | const expressionS *src_exp; | |
3789 | ||
3790 | num_ops++; | |
3791 | switch (b_op->typ) | |
3792 | { | |
3793 | case OP_CONSTANT: | |
3794 | /* The expression must be the constant. */ | |
3795 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3796 | exp = &new_insn->tok[b_op->op_num]; | |
3797 | set_expr_const (exp, b_op->op_data); | |
3798 | break; | |
3799 | ||
3800 | case OP_OPERAND: | |
3801 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3802 | assert (b_op->op_data < (unsigned) old_insn->ntok); | |
3803 | src_exp = &old_insn->tok[b_op->op_data]; | |
3804 | exp = &new_insn->tok[b_op->op_num]; | |
3805 | copy_expr (exp, src_exp); | |
3806 | break; | |
3807 | ||
3808 | case OP_LITERAL: | |
3809 | case OP_LABEL: | |
3810 | as_bad (_("can't handle generation of literal/labels yet")); | |
3811 | assert (0); | |
3812 | ||
3813 | default: | |
3814 | as_bad (_("can't handle undefined OP TYPE")); | |
3815 | assert (0); | |
3816 | } | |
3817 | } | |
3818 | ||
3819 | new_insn->ntok = num_ops; | |
3820 | return FALSE; | |
3821 | } | |
3822 | ||
3823 | ||
43cd72b9 | 3824 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3825 | |
7fa3d080 BW |
3826 | static bfd_boolean |
3827 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3828 | { |
43cd72b9 | 3829 | TransitionRule *rule; |
e0001a05 | 3830 | BuildInstr *insn_spec; |
43cd72b9 BW |
3831 | |
3832 | if (old_insn->is_specific_opcode || !density_supported) | |
3833 | return FALSE; | |
3834 | ||
3835 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3836 | if (rule == NULL) |
3837 | return FALSE; | |
3838 | ||
3839 | insn_spec = rule->to_instr; | |
3840 | /* There should only be one. */ | |
3841 | assert (insn_spec != NULL); | |
3842 | assert (insn_spec->next == NULL); | |
3843 | if (insn_spec->next != NULL) | |
3844 | return FALSE; | |
3845 | ||
3846 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3847 | ||
3848 | return TRUE; | |
3849 | } | |
3850 | ||
3851 | ||
3852 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3853 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
3854 | tokens into the stack or relax it and place multiple |
3855 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
3856 | |
3857 | static bfd_boolean | |
7fa3d080 | 3858 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
3859 | { |
3860 | int noperands; | |
3861 | TInsn new_insn; | |
7c834684 BW |
3862 | bfd_boolean do_expand; |
3863 | ||
e0001a05 NC |
3864 | memset (&new_insn, 0, sizeof (TInsn)); |
3865 | ||
43cd72b9 BW |
3866 | /* Narrow it if we can. xg_simplify_insn now does all the |
3867 | appropriate checking (e.g., for the density option). */ | |
3868 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
3869 | orig_insn = &new_insn; | |
e0001a05 | 3870 | |
43cd72b9 BW |
3871 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
3872 | orig_insn->opcode); | |
e0001a05 NC |
3873 | if (orig_insn->ntok < noperands) |
3874 | { | |
3875 | as_bad (_("found %d operands for '%s': Expected %d"), | |
3876 | orig_insn->ntok, | |
3877 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3878 | noperands); | |
3879 | return TRUE; | |
3880 | } | |
3881 | if (orig_insn->ntok > noperands) | |
3882 | as_warn (_("found too many (%d) operands for '%s': Expected %d"), | |
3883 | orig_insn->ntok, | |
3884 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3885 | noperands); | |
3886 | ||
43cd72b9 | 3887 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 3888 | are too many, just cut out the extras here. */ |
e0001a05 NC |
3889 | orig_insn->ntok = noperands; |
3890 | ||
e0001a05 NC |
3891 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
3892 | return TRUE; | |
3893 | ||
7c834684 BW |
3894 | /* If the instruction will definitely need to be relaxed, it is better |
3895 | to expand it now for better scheduling. Decide whether to expand | |
3896 | now.... */ | |
3897 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
3898 | ||
3899 | /* Calls should be expanded to longcalls only in the backend relaxation | |
3900 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
3901 | adjacent. */ | |
3902 | if (is_direct_call_opcode (orig_insn->opcode)) | |
3903 | do_expand = FALSE; | |
e0001a05 NC |
3904 | |
3905 | if (tinsn_has_symbolic_operands (orig_insn)) | |
3906 | { | |
7c834684 BW |
3907 | /* The values of symbolic operands are not known yet, so only expand |
3908 | now if an operand is "complex" (e.g., difference of symbols) and | |
3909 | will have to be stored as a literal regardless of the value. */ | |
3910 | if (!tinsn_has_complex_operands (orig_insn)) | |
3911 | do_expand = FALSE; | |
e0001a05 | 3912 | } |
7c834684 BW |
3913 | else if (xg_immeds_fit (orig_insn)) |
3914 | do_expand = FALSE; | |
3915 | ||
3916 | if (do_expand) | |
3917 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 3918 | else |
7c834684 | 3919 | istack_push (istack, orig_insn); |
e0001a05 | 3920 | |
e0001a05 NC |
3921 | return FALSE; |
3922 | } | |
3923 | ||
3924 | ||
7fa3d080 BW |
3925 | /* Return TRUE if the section flags are marked linkonce |
3926 | or the name is .gnu.linkonce*. */ | |
3927 | ||
3928 | static bfd_boolean | |
3929 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
3930 | { | |
3931 | flagword flags, link_once_flags; | |
3932 | ||
3933 | flags = bfd_get_section_flags (abfd, sec); | |
3934 | link_once_flags = (flags & SEC_LINK_ONCE); | |
3935 | ||
3936 | /* Flags might not be set yet. */ | |
3937 | if (!link_once_flags) | |
3938 | { | |
3939 | static size_t len = sizeof ".gnu.linkonce.t."; | |
3940 | ||
3941 | if (strncmp (segment_name (sec), ".gnu.linkonce.t.", len - 1) == 0) | |
3942 | link_once_flags = SEC_LINK_ONCE; | |
3943 | } | |
3944 | return (link_once_flags != 0); | |
3945 | } | |
3946 | ||
3947 | ||
3948 | static void | |
3949 | xtensa_add_literal_sym (symbolS *sym) | |
3950 | { | |
3951 | sym_list *l; | |
3952 | ||
3953 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
3954 | l->sym = sym; | |
3955 | l->next = literal_syms; | |
3956 | literal_syms = l; | |
3957 | } | |
3958 | ||
3959 | ||
3960 | static symbolS * | |
3961 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
3962 | { | |
3963 | static int lit_num = 0; | |
3964 | static char name[256]; | |
3965 | symbolS *symbolP; | |
3966 | ||
3967 | sprintf (name, ".L_lit_sym%d", lit_num); | |
3968 | ||
3969 | /* Create a local symbol. If it is in a linkonce section, we have to | |
3970 | be careful to make sure that if it is used in a relocation that the | |
3971 | symbol will be in the output file. */ | |
3972 | if (get_is_linkonce_section (stdoutput, sec)) | |
3973 | { | |
3974 | symbolP = symbol_new (name, sec, 0, frag); | |
3975 | S_CLEAR_EXTERNAL (symbolP); | |
3976 | /* symbolP->local = 1; */ | |
3977 | } | |
3978 | else | |
3979 | symbolP = symbol_new (name, sec, 0, frag); | |
3980 | ||
3981 | xtensa_add_literal_sym (symbolP); | |
3982 | ||
3983 | frag->tc_frag_data.is_literal = TRUE; | |
3984 | lit_num++; | |
3985 | return symbolP; | |
3986 | } | |
3987 | ||
3988 | ||
e0001a05 NC |
3989 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
3990 | ||
7fa3d080 BW |
3991 | static symbolS * |
3992 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
3993 | { |
3994 | emit_state state; | |
3995 | symbolS *lit_sym = NULL; | |
3996 | ||
3997 | /* size = 4 for L32R. It could easily be larger when we move to | |
3998 | larger constants. Add a parameter later. */ | |
3999 | offsetT litsize = 4; | |
4000 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4001 | expressionS saved_loc; | |
43cd72b9 BW |
4002 | expressionS * emit_val; |
4003 | ||
e0001a05 NC |
4004 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4005 | ||
4006 | assert (insn->insn_type == ITYPE_LITERAL); | |
77cd6497 | 4007 | assert (insn->ntok == 1); /* must be only one token here */ |
e0001a05 NC |
4008 | |
4009 | xtensa_switch_to_literal_fragment (&state); | |
4010 | ||
43cd72b9 BW |
4011 | emit_val = &insn->tok[0]; |
4012 | if (emit_val->X_op == O_big) | |
4013 | { | |
4014 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4015 | if (size > litsize) | |
4016 | { | |
4017 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4018 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4019 | _("invalid immediate")); |
4020 | xtensa_restore_emit_state (&state); | |
4021 | return NULL; | |
4022 | } | |
4023 | } | |
4024 | ||
e0001a05 NC |
4025 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4026 | literals done with this function have a frag to themselves. That's | |
4027 | important for the way text section literals work. */ | |
4028 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4029 | record_alignment (now_seg, litalign); |
e0001a05 | 4030 | |
43cd72b9 BW |
4031 | if (emit_val->X_op == O_pltrel) |
4032 | { | |
4033 | char *p = frag_more (litsize); | |
4034 | xtensa_set_frag_assembly_state (frag_now); | |
4035 | if (emit_val->X_add_symbol) | |
4036 | emit_val->X_op = O_symbol; | |
4037 | else | |
4038 | emit_val->X_op = O_constant; | |
4039 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
4040 | litsize, emit_val, 0, BFD_RELOC_XTENSA_PLT); | |
4041 | } | |
4042 | else | |
4043 | emit_expr (emit_val, litsize); | |
e0001a05 NC |
4044 | |
4045 | assert (frag_now->tc_frag_data.literal_frag == NULL); | |
4046 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
4047 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4048 | lit_sym = frag_now->fr_symbol; | |
4049 | frag_now->tc_frag_data.is_literal = TRUE; | |
4050 | ||
4051 | /* Go back. */ | |
4052 | xtensa_restore_emit_state (&state); | |
4053 | return lit_sym; | |
4054 | } | |
4055 | ||
4056 | ||
4057 | static void | |
7fa3d080 | 4058 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4059 | { |
4060 | emit_state state; | |
43cd72b9 | 4061 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4062 | takes effect if something is placed here. */ |
4063 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4064 | fragS *lit_saved_frag; | |
4065 | ||
e0001a05 | 4066 | assert (size % 4 == 0); |
e0001a05 NC |
4067 | |
4068 | xtensa_switch_to_literal_fragment (&state); | |
4069 | ||
4070 | /* Force a 4-byte align here. */ | |
4071 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4072 | record_alignment (now_seg, litalign); |
e0001a05 NC |
4073 | |
4074 | xg_force_frag_space (size); | |
4075 | ||
4076 | lit_saved_frag = frag_now; | |
4077 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
4078 | frag_now->tc_frag_data.is_literal = TRUE; | |
4079 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
43cd72b9 | 4080 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4081 | |
4082 | /* Go back. */ | |
4083 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4084 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4085 | } |
4086 | ||
4087 | ||
e0001a05 | 4088 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4089 | Return TRUE on success. */ |
e0001a05 | 4090 | |
7fa3d080 BW |
4091 | static bfd_boolean |
4092 | xg_add_opcode_fix (TInsn *tinsn, | |
4093 | int opnum, | |
4094 | xtensa_format fmt, | |
4095 | int slot, | |
4096 | expressionS *expr, | |
4097 | fragS *fragP, | |
4098 | offsetT offset) | |
43cd72b9 BW |
4099 | { |
4100 | xtensa_opcode opcode = tinsn->opcode; | |
4101 | bfd_reloc_code_real_type reloc; | |
4102 | reloc_howto_type *howto; | |
4103 | int fmt_length; | |
e0001a05 NC |
4104 | fixS *the_fix; |
4105 | ||
43cd72b9 BW |
4106 | reloc = BFD_RELOC_NONE; |
4107 | ||
4108 | /* First try the special cases for "alternate" relocs. */ | |
4109 | if (opcode == xtensa_l32r_opcode) | |
4110 | { | |
4111 | if (fragP->tc_frag_data.use_absolute_literals) | |
4112 | reloc = encode_alt_reloc (slot); | |
4113 | } | |
4114 | else if (opcode == xtensa_const16_opcode) | |
4115 | { | |
4116 | if (expr->X_op == O_lo16) | |
4117 | { | |
4118 | reloc = encode_reloc (slot); | |
4119 | expr->X_op = O_symbol; | |
4120 | } | |
4121 | else if (expr->X_op == O_hi16) | |
4122 | { | |
4123 | reloc = encode_alt_reloc (slot); | |
4124 | expr->X_op = O_symbol; | |
4125 | } | |
4126 | } | |
4127 | ||
4128 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4129 | { |
43cd72b9 | 4130 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4131 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4132 | return FALSE; |
4133 | } | |
4134 | ||
43cd72b9 BW |
4135 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4136 | into the symbol table where the generic portions of the assembler | |
4137 | won't know what to do with them. */ | |
4138 | if (expr->X_op == O_lo16 || expr->X_op == O_hi16) | |
4139 | { | |
4140 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4141 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4142 | return FALSE; |
4143 | } | |
4144 | ||
4145 | /* Next try the generic relocs. */ | |
4146 | if (reloc == BFD_RELOC_NONE) | |
4147 | reloc = encode_reloc (slot); | |
4148 | if (reloc == BFD_RELOC_NONE) | |
4149 | { | |
4150 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4151 | return FALSE; | |
4152 | } | |
e0001a05 | 4153 | |
43cd72b9 | 4154 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4155 | if (!howto) |
4156 | { | |
43cd72b9 | 4157 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4158 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4159 | return FALSE; | |
4160 | } | |
4161 | ||
43cd72b9 BW |
4162 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
4163 | the_fix = fix_new_exp (fragP, offset, fmt_length, expr, | |
e0001a05 | 4164 | howto->pc_relative, reloc); |
d9740523 | 4165 | the_fix->fx_no_overflow = 1; |
e0001a05 | 4166 | |
7fa3d080 BW |
4167 | if (expr->X_add_symbol |
4168 | && (S_IS_EXTERNAL (expr->X_add_symbol) | |
4169 | || S_IS_WEAK (expr->X_add_symbol))) | |
4170 | the_fix->fx_plt = TRUE; | |
4171 | ||
4172 | the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol; | |
4173 | the_fix->tc_fix_data.X_add_number = expr->X_add_number; | |
4174 | the_fix->tc_fix_data.slot = slot; | |
c138bc38 | 4175 | |
7fa3d080 BW |
4176 | return TRUE; |
4177 | } | |
4178 | ||
4179 | ||
4180 | static bfd_boolean | |
4181 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4182 | char *buf, |
4183 | fragS *fragP, | |
4184 | offsetT offset, | |
4185 | bfd_boolean build_fix) | |
4186 | { | |
4187 | static xtensa_insnbuf insnbuf = NULL; | |
4188 | bfd_boolean has_symbolic_immed = FALSE; | |
4189 | bfd_boolean ok = TRUE; | |
b2d179be | 4190 | |
7fa3d080 BW |
4191 | if (!insnbuf) |
4192 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4193 | ||
4194 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4195 | if (has_symbolic_immed && build_fix) | |
4196 | { | |
4197 | /* Add a fixup. */ | |
b2d179be BW |
4198 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4199 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4200 | int opnum = get_relaxable_immed (tinsn->opcode); |
4201 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4202 | |
b2d179be | 4203 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4204 | ok = FALSE; |
4205 | } | |
4206 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4207 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4208 | (unsigned char *) buf, 0); | |
7fa3d080 | 4209 | return ok; |
e0001a05 NC |
4210 | } |
4211 | ||
4212 | ||
7fa3d080 BW |
4213 | static void |
4214 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4215 | { |
4216 | symbolS *sym = get_special_literal_symbol (); | |
4217 | int i; | |
4218 | if (lit_sym == 0) | |
4219 | return; | |
4220 | assert (insn->insn_type == ITYPE_INSN); | |
4221 | for (i = 0; i < insn->ntok; i++) | |
4222 | if (insn->tok[i].X_add_symbol == sym) | |
4223 | insn->tok[i].X_add_symbol = lit_sym; | |
4224 | ||
4225 | } | |
4226 | ||
4227 | ||
7fa3d080 BW |
4228 | static void |
4229 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4230 | { |
4231 | symbolS *sym = get_special_label_symbol (); | |
4232 | int i; | |
43cd72b9 | 4233 | /* assert (!insn->is_literal); */ |
e0001a05 NC |
4234 | for (i = 0; i < insn->ntok; i++) |
4235 | if (insn->tok[i].X_add_symbol == sym) | |
4236 | insn->tok[i].X_add_symbol = label_sym; | |
4237 | ||
4238 | } | |
4239 | ||
4240 | ||
43cd72b9 | 4241 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4242 | integer register. */ |
4243 | ||
4244 | static bfd_boolean | |
7fa3d080 | 4245 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4246 | { |
4247 | int i; | |
4248 | int num_ops; | |
4249 | xtensa_isa isa = xtensa_default_isa; | |
4250 | ||
43cd72b9 | 4251 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4252 | |
4253 | for (i = 0; i < num_ops; i++) | |
4254 | { | |
43cd72b9 BW |
4255 | char inout; |
4256 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4257 | if ((inout == 'o' || inout == 'm') | |
4258 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4259 | { |
43cd72b9 BW |
4260 | xtensa_regfile opnd_rf = |
4261 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4262 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4263 | { |
4264 | if ((insn->tok[i].X_op == O_register) | |
4265 | && (insn->tok[i].X_add_number == regnum)) | |
4266 | return TRUE; | |
4267 | } | |
4268 | } | |
4269 | } | |
4270 | return FALSE; | |
4271 | } | |
4272 | ||
4273 | ||
4274 | static bfd_boolean | |
7fa3d080 | 4275 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4276 | { |
4277 | xtensa_opcode opcode = tinsn->opcode; | |
4278 | ||
4279 | if (opcode == XTENSA_UNDEFINED) | |
4280 | return FALSE; | |
4281 | ||
4282 | if (opcode == xtensa_call0_opcode | |
4283 | || opcode == xtensa_callx0_opcode | |
4284 | || opcode == xtensa_call4_opcode | |
4285 | || opcode == xtensa_callx4_opcode | |
4286 | || opcode == xtensa_call8_opcode | |
4287 | || opcode == xtensa_callx8_opcode | |
4288 | || opcode == xtensa_call12_opcode | |
4289 | || opcode == xtensa_callx12_opcode | |
4290 | || opcode == xtensa_isync_opcode | |
4291 | || opcode == xtensa_ret_opcode | |
4292 | || opcode == xtensa_ret_n_opcode | |
4293 | || opcode == xtensa_retw_opcode | |
4294 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4295 | || opcode == xtensa_waiti_opcode |
4296 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4297 | return TRUE; |
c138bc38 | 4298 | |
e0001a05 NC |
4299 | return FALSE; |
4300 | } | |
4301 | ||
4302 | ||
4303 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4304 | This allows the debugger to add unaligned labels. | |
4305 | Also, the assembler generates stabs labels that need | |
4306 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4307 | ||
7fa3d080 BW |
4308 | static bfd_boolean |
4309 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4310 | { |
4311 | const char *name = S_GET_NAME (sym); | |
4312 | static size_t fake_size = 0; | |
4313 | ||
4314 | if (name | |
4315 | && name[0] == '.' | |
4316 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4317 | return TRUE; | |
4318 | ||
4319 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4320 | if (fake_size == 0) | |
4321 | fake_size = strlen (FAKE_LABEL_NAME); | |
4322 | ||
43cd72b9 | 4323 | if (name |
e0001a05 NC |
4324 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4325 | && (name[fake_size] == 'F' | |
4326 | || name[fake_size] == 'L' | |
4327 | || (name[fake_size] == 'e' | |
4328 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4329 | return TRUE; | |
4330 | ||
4331 | return FALSE; | |
4332 | } | |
4333 | ||
4334 | ||
7fa3d080 BW |
4335 | static fragS * |
4336 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4337 | { |
4338 | fragS *next_fragP = fragP->fr_next; | |
4339 | ||
c138bc38 | 4340 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4341 | So we have to skip until we find something legit. */ |
4342 | while (next_fragP && next_fragP->fr_fix == 0) | |
4343 | next_fragP = next_fragP->fr_next; | |
4344 | ||
4345 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4346 | return NULL; | |
4347 | ||
4348 | return next_fragP; | |
4349 | } | |
4350 | ||
4351 | ||
43cd72b9 | 4352 | static bfd_boolean |
7fa3d080 | 4353 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4354 | { |
4355 | xtensa_opcode out_opcode; | |
4356 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4357 | ||
4358 | if (next_fragP == NULL) | |
4359 | return FALSE; | |
4360 | ||
4361 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4362 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4363 | { | |
4364 | *opcode = out_opcode; | |
4365 | return TRUE; | |
4366 | } | |
4367 | return FALSE; | |
4368 | } | |
4369 | ||
4370 | ||
4371 | static int | |
7fa3d080 | 4372 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4373 | { |
e0001a05 NC |
4374 | static xtensa_insnbuf insnbuf = NULL; |
4375 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4376 | xtensa_format fmt; |
c138bc38 | 4377 | int fmt_size; |
e0001a05 NC |
4378 | |
4379 | if (!insnbuf) | |
4380 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4381 | ||
43cd72b9 BW |
4382 | if (fragP == NULL) |
4383 | return XTENSA_UNDEFINED; | |
4384 | ||
d77b99c9 BW |
4385 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4386 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4387 | |
4388 | fmt = xtensa_format_decode (isa, insnbuf); | |
4389 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4390 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4391 | fmt_size = xtensa_format_length (isa, fmt); |
4392 | ||
4393 | /* If the next format won't be changing due to relaxation, just | |
4394 | return the length of the first format. */ | |
4395 | if (fragP->fr_opcode != fragP->fr_literal) | |
4396 | return fmt_size; | |
4397 | ||
c138bc38 | 4398 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4399 | multi-slot instruction, we will return the more conservative |
4400 | number. This works because alignment on bigger instructions | |
4401 | is more restrictive than alignment on smaller instructions. | |
4402 | This is more conservative than we would like, but it happens | |
4403 | infrequently. */ | |
4404 | ||
4405 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4406 | return fmt_size; | |
4407 | ||
4408 | /* If we aren't doing one of our own relaxations or it isn't | |
4409 | slot-based, then the insn size won't change. */ | |
4410 | if (fragP->fr_type != rs_machine_dependent) | |
4411 | return fmt_size; | |
4412 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4413 | return fmt_size; | |
4414 | ||
4415 | /* If an instruction is about to grow, return the longer size. */ | |
4416 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
4417 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2) | |
4418 | return 3; | |
c138bc38 | 4419 | |
43cd72b9 BW |
4420 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4421 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4422 | |
43cd72b9 | 4423 | return fmt_size; |
e0001a05 NC |
4424 | } |
4425 | ||
4426 | ||
7fa3d080 BW |
4427 | static int |
4428 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4429 | { |
7fa3d080 BW |
4430 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4431 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4432 | } |
4433 | ||
4434 | ||
03aaa593 BW |
4435 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4436 | required two-byte instructions to be treated as three-byte instructions | |
4437 | for loop instruction alignment. This restriction was removed beginning | |
4438 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4439 | is that the first instruction of the loop must appear at an address that | |
4440 | does not cross a fetch boundary. */ | |
4441 | ||
4442 | static int | |
4443 | get_loop_align_size (int insn_size) | |
4444 | { | |
4445 | if (insn_size == XTENSA_UNDEFINED) | |
4446 | return xtensa_fetch_width; | |
4447 | ||
4448 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4449 | return 3; | |
4450 | ||
4451 | return insn_size; | |
4452 | } | |
4453 | ||
4454 | ||
e0001a05 NC |
4455 | /* If the next legit fragment is an end-of-loop marker, |
4456 | switch its state so it will instantiate a NOP. */ | |
4457 | ||
4458 | static void | |
1d19a770 | 4459 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4460 | { |
4461 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4462 | fragS *new_target = NULL; |
e0001a05 | 4463 | |
7b1cc377 | 4464 | if (align_targets) |
43cd72b9 BW |
4465 | { |
4466 | /* We are guaranteed there will be one of these... */ | |
4467 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4468 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4469 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4470 | next_fragP = next_fragP->fr_next; | |
4471 | ||
4472 | assert (next_fragP->fr_type == rs_machine_dependent | |
4473 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4474 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4475 | ||
4476 | /* ...and one of these. */ | |
4477 | new_target = next_fragP->fr_next; | |
4478 | while (!(new_target->fr_type == rs_machine_dependent | |
4479 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4480 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4481 | new_target = new_target->fr_next; | |
4482 | ||
4483 | assert (new_target->fr_type == rs_machine_dependent | |
4484 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4485 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4486 | } | |
43cd72b9 | 4487 | |
1d19a770 | 4488 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4489 | { |
1d19a770 BW |
4490 | if (next_fragP->fr_type == rs_machine_dependent |
4491 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4492 | { |
1d19a770 BW |
4493 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4494 | return; | |
e0001a05 | 4495 | } |
1d19a770 BW |
4496 | |
4497 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4498 | } |
4499 | } | |
4500 | ||
4501 | ||
4502 | static bfd_boolean | |
7fa3d080 | 4503 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4504 | { |
43cd72b9 | 4505 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4506 | so we have to skip until we find something legit. */ |
4507 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4508 | { | |
4509 | if (fragP->tc_frag_data.is_branch_target) | |
4510 | return TRUE; | |
4511 | if (fragP->fr_fix != 0) | |
4512 | break; | |
4513 | } | |
4514 | return FALSE; | |
4515 | } | |
4516 | ||
4517 | ||
4518 | static bfd_boolean | |
7fa3d080 | 4519 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4520 | { |
c138bc38 | 4521 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4522 | So we have to skip until we find something legit. */ |
4523 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4524 | { | |
4525 | if (fragP->tc_frag_data.is_loop_target) | |
4526 | return TRUE; | |
4527 | if (fragP->fr_fix != 0) | |
4528 | break; | |
4529 | } | |
4530 | return FALSE; | |
4531 | } | |
4532 | ||
4533 | ||
4534 | static addressT | |
7fa3d080 | 4535 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4536 | { |
4537 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4538 | xtensa_opcode next_opcode; |
e0001a05 | 4539 | |
43cd72b9 | 4540 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4541 | return 0; |
4542 | ||
43cd72b9 BW |
4543 | /* Sometimes an empty will end up here due to storage allocation issues, |
4544 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4545 | while (next_fragp->fr_fix == 0) |
4546 | next_fragp = next_fragp->fr_next; | |
4547 | ||
4548 | if (next_fragp->fr_type != rs_machine_dependent) | |
4549 | return 0; | |
4550 | ||
4551 | /* There is some implicit knowledge encoded in here. | |
4552 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4553 | been relaxed. Note that we can assume that the LOOP |
4554 | instruction is in slot 0 because loops aren't bundleable. */ | |
4555 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
e0001a05 NC |
4556 | return get_expanded_loop_offset (next_opcode); |
4557 | ||
4558 | return 0; | |
4559 | } | |
4560 | ||
4561 | ||
4562 | /* Mark a location where we can later insert literal frags. Update | |
4563 | the section's literal_pool_loc, so subsequent literals can be | |
4564 | placed nearest to their use. */ | |
4565 | ||
4566 | static void | |
7fa3d080 | 4567 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4568 | { |
4569 | /* Any labels pointing to the current location need | |
4570 | to be adjusted to after the literal pool. */ | |
4571 | emit_state s; | |
e0001a05 | 4572 | fragS *pool_location; |
e0001a05 | 4573 | |
43cd72b9 BW |
4574 | if (use_literal_section && !directive_state[directive_absolute_literals]) |
4575 | return; | |
4576 | ||
e0001a05 | 4577 | frag_align (2, 0, 0); |
43cd72b9 | 4578 | record_alignment (now_seg, 2); |
e0001a05 | 4579 | |
dd49a749 BW |
4580 | /* We stash info in these frags so we can later move the literal's |
4581 | fixes into this frchain's fix list. */ | |
e0001a05 | 4582 | pool_location = frag_now; |
dd49a749 BW |
4583 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
4584 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4585 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4586 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4587 | frag_now->tc_frag_data.lit_seg = now_seg; |
4588 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4589 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4590 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4591 | |
4592 | /* Now put a frag into the literal pool that points to this location. */ | |
4593 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4594 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4595 | frag_align (2, 0, 0); | |
4596 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4597 | |
4598 | /* Close whatever frag is there. */ | |
4599 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4600 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4601 | frag_now->tc_frag_data.literal_frag = pool_location; |
4602 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4603 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4604 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4605 | } |
4606 | ||
4607 | ||
43cd72b9 BW |
4608 | /* Build a nop of the correct size into tinsn. */ |
4609 | ||
4610 | static void | |
7fa3d080 | 4611 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4612 | { |
4613 | tinsn_init (tinsn); | |
4614 | switch (size) | |
4615 | { | |
4616 | case 2: | |
4617 | tinsn->opcode = xtensa_nop_n_opcode; | |
4618 | tinsn->ntok = 0; | |
4619 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4620 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4621 | break; | |
4622 | ||
4623 | case 3: | |
4624 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4625 | { | |
4626 | tinsn->opcode = xtensa_or_opcode; | |
4627 | set_expr_const (&tinsn->tok[0], 1); | |
4628 | set_expr_const (&tinsn->tok[1], 1); | |
4629 | set_expr_const (&tinsn->tok[2], 1); | |
4630 | tinsn->ntok = 3; | |
4631 | } | |
4632 | else | |
4633 | tinsn->opcode = xtensa_nop_opcode; | |
4634 | ||
4635 | assert (tinsn->opcode != XTENSA_UNDEFINED); | |
4636 | } | |
4637 | } | |
4638 | ||
4639 | ||
e0001a05 NC |
4640 | /* Assemble a NOP of the requested size in the buffer. User must have |
4641 | allocated "buf" with at least "size" bytes. */ | |
4642 | ||
7fa3d080 | 4643 | static void |
d77b99c9 | 4644 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4645 | { |
4646 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4647 | TInsn tinsn; |
e0001a05 | 4648 | |
43cd72b9 | 4649 | build_nop (&tinsn, size); |
e0001a05 | 4650 | |
43cd72b9 BW |
4651 | if (!insnbuf) |
4652 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4653 | |
43cd72b9 | 4654 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4655 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4656 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4657 | } |
4658 | ||
4659 | ||
4660 | /* Return the number of bytes for the offset of the expanded loop | |
4661 | instruction. This should be incorporated into the relaxation | |
4662 | specification but is hard-coded here. This is used to auto-align | |
4663 | the loop instruction. It is invalid to call this function if the | |
4664 | configuration does not have loops or if the opcode is not a loop | |
4665 | opcode. */ | |
4666 | ||
4667 | static addressT | |
7fa3d080 | 4668 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4669 | { |
4670 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4671 | This MUST correspond directly to the specification of the loop | |
4672 | expansion. It will be validated on fragment conversion. */ | |
43cd72b9 | 4673 | assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4674 | if (opcode == xtensa_loop_opcode) |
4675 | return 0; | |
4676 | if (opcode == xtensa_loopnez_opcode) | |
4677 | return 3; | |
4678 | if (opcode == xtensa_loopgtz_opcode) | |
4679 | return 6; | |
4680 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4681 | return 0; | |
4682 | } | |
4683 | ||
4684 | ||
7fa3d080 BW |
4685 | static fragS * |
4686 | get_literal_pool_location (segT seg) | |
e0001a05 NC |
4687 | { |
4688 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; | |
4689 | } | |
4690 | ||
4691 | ||
4692 | static void | |
7fa3d080 | 4693 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4694 | { |
4695 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4696 | } | |
4697 | ||
43cd72b9 BW |
4698 | |
4699 | /* Set frag assembly state should be called when a new frag is | |
4700 | opened and after a frag has been closed. */ | |
4701 | ||
7fa3d080 BW |
4702 | static void |
4703 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4704 | { |
4705 | if (!density_supported) | |
4706 | fragP->tc_frag_data.is_no_density = TRUE; | |
4707 | ||
4708 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4709 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4710 | "use_schedule" here. */ |
4711 | if (!directive_state[directive_transform]) | |
4712 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4713 | if (directive_state[directive_longcalls]) |
4714 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4715 | fragP->tc_frag_data.use_absolute_literals = |
4716 | directive_state[directive_absolute_literals]; | |
4717 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4718 | } | |
4719 | ||
4720 | ||
7fa3d080 BW |
4721 | static bfd_boolean |
4722 | relaxable_section (asection *sec) | |
43cd72b9 BW |
4723 | { |
4724 | return (sec->flags & SEC_DEBUGGING) == 0; | |
4725 | } | |
4726 | ||
4727 | ||
4728 | static void | |
7fa3d080 | 4729 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
4730 | { |
4731 | segT *seclist; | |
4732 | ||
4733 | /* Walk over each fragment of all of the current segments. For each | |
4734 | unmarked fragment, mark it with the same info as the previous | |
4735 | fragment. */ | |
4736 | for (seclist = &stdoutput->sections; | |
4737 | seclist && *seclist; | |
4738 | seclist = &(*seclist)->next) | |
4739 | { | |
4740 | segT sec = *seclist; | |
4741 | segment_info_type *seginfo; | |
4742 | fragS *fragP; | |
4743 | flagword flags; | |
4744 | flags = bfd_get_section_flags (stdoutput, sec); | |
4745 | if (flags & SEC_DEBUGGING) | |
4746 | continue; | |
4747 | if (!(flags & SEC_ALLOC)) | |
4748 | continue; | |
4749 | ||
4750 | seginfo = seg_info (sec); | |
4751 | if (seginfo && seginfo->frchainP) | |
4752 | { | |
4753 | fragS *last_fragP = 0; | |
4754 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4755 | fragP = fragP->fr_next) | |
4756 | { | |
4757 | if (fragP->fr_fix != 0 | |
4758 | && !fragP->tc_frag_data.is_assembly_state_set) | |
4759 | { | |
4760 | if (last_fragP == 0) | |
4761 | { | |
4762 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
4763 | _("assembly state not set for first frag in section %s"), | |
4764 | sec->name); | |
4765 | } | |
4766 | else | |
4767 | { | |
4768 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4769 | fragP->tc_frag_data.is_no_density = | |
4770 | last_fragP->tc_frag_data.is_no_density; | |
4771 | fragP->tc_frag_data.is_no_transform = | |
4772 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
4773 | fragP->tc_frag_data.use_longcalls = |
4774 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
4775 | fragP->tc_frag_data.use_absolute_literals = |
4776 | last_fragP->tc_frag_data.use_absolute_literals; | |
4777 | } | |
4778 | } | |
4779 | if (fragP->tc_frag_data.is_assembly_state_set) | |
4780 | last_fragP = fragP; | |
4781 | } | |
4782 | } | |
4783 | } | |
4784 | } | |
4785 | ||
4786 | ||
4787 | static void | |
7fa3d080 BW |
4788 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
4789 | asection *sec, | |
4790 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4791 | { |
4792 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4793 | segment_info_type *seginfo = seg_info (sec); | |
4794 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 4795 | |
43cd72b9 | 4796 | if (flags & SEC_CODE) |
c138bc38 | 4797 | { |
43cd72b9 BW |
4798 | xtensa_isa isa = xtensa_default_isa; |
4799 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
4800 | while (frag != NULL) | |
4801 | { | |
4802 | if (frag->tc_frag_data.is_branch_target) | |
4803 | { | |
4804 | int op_size; | |
664df4e4 | 4805 | addressT branch_align, frag_addr; |
43cd72b9 BW |
4806 | xtensa_format fmt; |
4807 | ||
d77b99c9 BW |
4808 | xtensa_insnbuf_from_chars |
4809 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4810 | fmt = xtensa_format_decode (isa, insnbuf); |
4811 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
4812 | branch_align = 1 << branch_align_power (sec); |
4813 | frag_addr = frag->fr_address % branch_align; | |
4814 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
4815 | as_warn_where (frag->fr_file, frag->fr_line, |
4816 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 4817 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4818 | } |
4819 | frag = frag->fr_next; | |
4820 | } | |
4821 | xtensa_insnbuf_free (isa, insnbuf); | |
4822 | } | |
4823 | } | |
4824 | ||
4825 | ||
4826 | static void | |
7fa3d080 BW |
4827 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
4828 | asection *sec, | |
4829 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4830 | { |
4831 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4832 | segment_info_type *seginfo = seg_info (sec); | |
4833 | fragS *frag = seginfo->frchainP->frch_root; | |
4834 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 4835 | |
43cd72b9 | 4836 | if (flags & SEC_CODE) |
c138bc38 | 4837 | { |
43cd72b9 BW |
4838 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
4839 | while (frag != NULL) | |
4840 | { | |
4841 | if (frag->tc_frag_data.is_first_loop_insn) | |
4842 | { | |
4843 | int op_size; | |
d77b99c9 | 4844 | addressT frag_addr; |
43cd72b9 BW |
4845 | xtensa_format fmt; |
4846 | ||
d77b99c9 BW |
4847 | xtensa_insnbuf_from_chars |
4848 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4849 | fmt = xtensa_format_decode (isa, insnbuf); |
4850 | op_size = xtensa_format_length (isa, fmt); | |
4851 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
4852 | ||
d77b99c9 | 4853 | if (frag_addr + op_size > xtensa_fetch_width) |
43cd72b9 BW |
4854 | as_warn_where (frag->fr_file, frag->fr_line, |
4855 | _("unaligned loop: %d bytes at 0x%lx"), | |
dd49a749 | 4856 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4857 | } |
4858 | frag = frag->fr_next; | |
4859 | } | |
4860 | xtensa_insnbuf_free (isa, insnbuf); | |
4861 | } | |
4862 | } | |
4863 | ||
4864 | ||
30f725a1 BW |
4865 | static int |
4866 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
4867 | { |
4868 | xtensa_isa isa = xtensa_default_isa; | |
4869 | static xtensa_insnbuf insnbuf = NULL; | |
4870 | static xtensa_insnbuf slotbuf = NULL; | |
4871 | xtensa_format fmt; | |
4872 | int slot; | |
4873 | bfd_boolean alt_reloc; | |
4874 | xtensa_opcode opcode; | |
4875 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
4876 | ||
4877 | (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc); | |
4878 | if (alt_reloc) | |
4879 | as_fatal (_("unexpected fix")); | |
4880 | ||
4881 | if (!insnbuf) | |
4882 | { | |
4883 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4884 | slotbuf = xtensa_insnbuf_alloc (isa); | |
4885 | } | |
4886 | ||
d77b99c9 | 4887 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
4888 | fmt = xtensa_format_decode (isa, insnbuf); |
4889 | if (fmt == XTENSA_UNDEFINED) | |
4890 | as_fatal (_("undecodable fix")); | |
4891 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
4892 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
4893 | if (opcode == XTENSA_UNDEFINED) | |
4894 | as_fatal (_("undecodable fix")); | |
4895 | ||
4896 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
4897 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 4898 | of a CONST16 operand. */ |
43cd72b9 | 4899 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 4900 | return 0; |
43cd72b9 BW |
4901 | |
4902 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
4903 | get_relaxable_immed (opcode), val, | |
4904 | fixP->fx_file, fixP->fx_line); | |
4905 | ||
4906 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 4907 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
4908 | |
4909 | return 1; | |
43cd72b9 BW |
4910 | } |
4911 | ||
e0001a05 NC |
4912 | \f |
4913 | /* External Functions and Other GAS Hooks. */ | |
4914 | ||
4915 | const char * | |
7fa3d080 | 4916 | xtensa_target_format (void) |
e0001a05 NC |
4917 | { |
4918 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
4919 | } | |
4920 | ||
4921 | ||
4922 | void | |
7fa3d080 | 4923 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
4924 | { |
4925 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
4926 | } | |
4927 | ||
4928 | ||
4929 | void | |
7fa3d080 | 4930 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
4931 | { |
4932 | if (target_big_endian) | |
4933 | number_to_chars_bigendian (buf, val, n); | |
4934 | else | |
4935 | number_to_chars_littleendian (buf, val, n); | |
4936 | } | |
4937 | ||
4938 | ||
4939 | /* This function is called once, at assembler startup time. It should | |
4940 | set up all the tables, etc. that the MD part of the assembler will | |
4941 | need. */ | |
4942 | ||
4943 | void | |
7fa3d080 | 4944 | md_begin (void) |
e0001a05 NC |
4945 | { |
4946 | segT current_section = now_seg; | |
4947 | int current_subsec = now_subseg; | |
4948 | xtensa_isa isa; | |
4949 | ||
43cd72b9 | 4950 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 4951 | isa = xtensa_default_isa; |
e0001a05 | 4952 | |
43cd72b9 BW |
4953 | linkrelax = 1; |
4954 | ||
4955 | /* Set up the .literal, .fini.literal and .init.literal sections. */ | |
e0001a05 NC |
4956 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
4957 | default_lit_sections.init_lit_seg_name = INIT_LITERAL_SECTION_NAME; | |
4958 | default_lit_sections.fini_lit_seg_name = FINI_LITERAL_SECTION_NAME; | |
4959 | default_lit_sections.lit_seg_name = LITERAL_SECTION_NAME; | |
43cd72b9 | 4960 | default_lit_sections.lit4_seg_name = LIT4_SECTION_NAME; |
e0001a05 NC |
4961 | |
4962 | subseg_set (current_section, current_subsec); | |
4963 | ||
43cd72b9 BW |
4964 | xg_init_vinsn (&cur_vinsn); |
4965 | ||
e0001a05 NC |
4966 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); |
4967 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
4968 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
4969 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
4970 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
4971 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
4972 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
4973 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
4974 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
4975 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 4976 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 4977 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
43cd72b9 BW |
4978 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
4979 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 4980 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
e0001a05 | 4981 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 4982 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
4983 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
4984 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
4985 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 4986 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
4987 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
4988 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
4989 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
4990 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
4991 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
4992 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 4993 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 4994 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 BW |
4995 | |
4996 | init_op_placement_info_table (); | |
4997 | ||
4998 | /* Set up the assembly state. */ | |
4999 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5000 | xtensa_set_frag_assembly_state (frag_now); | |
5001 | } | |
5002 | ||
5003 | ||
5004 | /* TC_INIT_FIX_DATA hook */ | |
5005 | ||
5006 | void | |
7fa3d080 | 5007 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5008 | { |
5009 | x->tc_fix_data.slot = 0; | |
5010 | x->tc_fix_data.X_add_symbol = NULL; | |
5011 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5012 | } |
5013 | ||
5014 | ||
5015 | /* tc_frob_label hook */ | |
5016 | ||
5017 | void | |
7fa3d080 | 5018 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5019 | { |
3ea38ac2 BW |
5020 | float freq; |
5021 | ||
5022 | if (cur_vinsn.inside_bundle) | |
5023 | { | |
5024 | as_bad (_("labels are not valid inside bundles")); | |
5025 | return; | |
5026 | } | |
5027 | ||
5028 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5029 | |
43cd72b9 BW |
5030 | /* Since the label was already attached to a frag associated with the |
5031 | previous basic block, it now needs to be reset to the current frag. */ | |
5032 | symbol_set_frag (sym, frag_now); | |
5033 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5034 | ||
82e7541d BW |
5035 | if (generating_literals) |
5036 | xtensa_add_literal_sym (sym); | |
5037 | else | |
5038 | xtensa_add_insn_label (sym); | |
5039 | ||
7b1cc377 BW |
5040 | if (symbol_get_tc (sym)->is_loop_target) |
5041 | { | |
5042 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5043 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5044 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5045 | ||
5046 | xtensa_set_frag_assembly_state (frag_now); | |
5047 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5048 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5049 | ||
5050 | xtensa_set_frag_assembly_state (frag_now); | |
5051 | xtensa_move_labels (frag_now, 0, TRUE); | |
07a53e5c | 5052 | } |
e0001a05 NC |
5053 | |
5054 | /* No target aligning in the absolute section. */ | |
61846f28 | 5055 | if (now_seg != absolute_section |
43cd72b9 | 5056 | && do_align_targets () |
61846f28 | 5057 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5058 | && !generating_literals) |
5059 | { | |
43cd72b9 BW |
5060 | xtensa_set_frag_assembly_state (frag_now); |
5061 | ||
43cd72b9 | 5062 | frag_var (rs_machine_dependent, |
7b1cc377 | 5063 | 0, (int) freq, |
e0001a05 NC |
5064 | RELAX_DESIRE_ALIGN_IF_TARGET, |
5065 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5066 | xtensa_set_frag_assembly_state (frag_now); |
82e7541d | 5067 | xtensa_move_labels (frag_now, 0, TRUE); |
43cd72b9 BW |
5068 | } |
5069 | ||
5070 | /* We need to mark the following properties even if we aren't aligning. */ | |
5071 | ||
5072 | /* If the label is already known to be a branch target, i.e., a | |
5073 | forward branch, mark the frag accordingly. Backward branches | |
5074 | are handled by xg_add_branch_and_loop_targets. */ | |
5075 | if (symbol_get_tc (sym)->is_branch_target) | |
5076 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5077 | ||
5078 | /* Loops only go forward, so they can be identified here. */ | |
5079 | if (symbol_get_tc (sym)->is_loop_target) | |
5080 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5081 | |
5082 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5083 | } |
5084 | ||
5085 | ||
5086 | /* tc_unrecognized_line hook */ | |
5087 | ||
5088 | int | |
7fa3d080 | 5089 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5090 | { |
5091 | switch (ch) | |
5092 | { | |
5093 | case '{' : | |
5094 | if (cur_vinsn.inside_bundle == 0) | |
5095 | { | |
5096 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5097 | when using --gstabs. Temporarily disable debug info. */ | |
5098 | generate_lineno_debug (); | |
5099 | if (debug_type == DEBUG_STABS) | |
5100 | { | |
5101 | xt_saved_debug_type = debug_type; | |
5102 | debug_type = DEBUG_NONE; | |
5103 | } | |
82e7541d | 5104 | |
43cd72b9 BW |
5105 | cur_vinsn.inside_bundle = 1; |
5106 | } | |
5107 | else | |
5108 | { | |
5109 | as_bad (_("extra opening brace")); | |
5110 | return 0; | |
5111 | } | |
5112 | break; | |
82e7541d | 5113 | |
43cd72b9 BW |
5114 | case '}' : |
5115 | if (cur_vinsn.inside_bundle) | |
5116 | finish_vinsn (&cur_vinsn); | |
5117 | else | |
5118 | { | |
5119 | as_bad (_("extra closing brace")); | |
5120 | return 0; | |
5121 | } | |
5122 | break; | |
5123 | default: | |
5124 | as_bad (_("syntax error")); | |
5125 | return 0; | |
e0001a05 | 5126 | } |
43cd72b9 | 5127 | return 1; |
e0001a05 NC |
5128 | } |
5129 | ||
5130 | ||
5131 | /* md_flush_pending_output hook */ | |
5132 | ||
5133 | void | |
7fa3d080 | 5134 | xtensa_flush_pending_output (void) |
e0001a05 | 5135 | { |
43cd72b9 BW |
5136 | if (cur_vinsn.inside_bundle) |
5137 | as_bad (_("missing closing brace")); | |
5138 | ||
e0001a05 NC |
5139 | /* If there is a non-zero instruction fragment, close it. */ |
5140 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5141 | { | |
5142 | frag_wane (frag_now); | |
5143 | frag_new (0); | |
43cd72b9 | 5144 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5145 | } |
5146 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5147 | |
5148 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5149 | } |
5150 | ||
5151 | ||
43cd72b9 BW |
5152 | /* We had an error while parsing an instruction. The string might look |
5153 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5154 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5155 | and the num_slots field will grow past the end of the array of slots, | |
5156 | and bad things happen. */ | |
5157 | ||
5158 | static void | |
7fa3d080 | 5159 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5160 | { |
5161 | if (cur_vinsn.inside_bundle) | |
5162 | { | |
5163 | if (*input_line_pointer == '}' | |
5164 | || *(input_line_pointer - 1) == '}' | |
5165 | || *(input_line_pointer - 2) == '}') | |
5166 | xg_clear_vinsn (&cur_vinsn); | |
5167 | } | |
5168 | } | |
5169 | ||
5170 | ||
e0001a05 | 5171 | void |
7fa3d080 | 5172 | md_assemble (char *str) |
e0001a05 NC |
5173 | { |
5174 | xtensa_isa isa = xtensa_default_isa; | |
7c430684 | 5175 | char *opname, *file_name; |
e0001a05 NC |
5176 | unsigned opnamelen; |
5177 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5178 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5179 | int num_args; |
e0001a05 | 5180 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5181 | |
e0001a05 NC |
5182 | tinsn_init (&orig_insn); |
5183 | ||
5184 | /* Split off the opcode. */ | |
5185 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
5186 | opname = xmalloc (opnamelen + 1); | |
5187 | memcpy (opname, str, opnamelen); | |
5188 | opname[opnamelen] = '\0'; | |
5189 | ||
5190 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5191 | if (num_args == -1) | |
5192 | { | |
5193 | as_bad (_("syntax error")); | |
5194 | return; | |
5195 | } | |
5196 | ||
5197 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5198 | return; | |
5199 | ||
5200 | /* Check for an underbar prefix. */ | |
5201 | if (*opname == '_') | |
5202 | { | |
5203 | has_underbar = TRUE; | |
5204 | opname += 1; | |
5205 | } | |
5206 | ||
5207 | orig_insn.insn_type = ITYPE_INSN; | |
5208 | orig_insn.ntok = 0; | |
43cd72b9 | 5209 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 NC |
5210 | |
5211 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); | |
5212 | if (orig_insn.opcode == XTENSA_UNDEFINED) | |
5213 | { | |
43cd72b9 BW |
5214 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5215 | if (fmt == XTENSA_UNDEFINED) | |
5216 | { | |
5217 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5218 | error_reset_cur_vinsn (); | |
5219 | return; | |
5220 | } | |
5221 | if (!cur_vinsn.inside_bundle) | |
5222 | { | |
5223 | as_bad (_("format names only valid inside bundles")); | |
5224 | error_reset_cur_vinsn (); | |
5225 | return; | |
5226 | } | |
5227 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5228 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5229 | opname); | |
5230 | cur_vinsn.format = fmt; | |
5231 | free (has_underbar ? opname - 1 : opname); | |
5232 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5233 | return; |
5234 | } | |
5235 | ||
e0001a05 NC |
5236 | /* Parse the arguments. */ |
5237 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5238 | { | |
5239 | as_bad (_("syntax error")); | |
43cd72b9 | 5240 | error_reset_cur_vinsn (); |
e0001a05 NC |
5241 | return; |
5242 | } | |
5243 | ||
5244 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5245 | free (has_underbar ? opname - 1 : opname); | |
5246 | opname = 0; | |
5247 | while (num_args-- > 0) | |
5248 | free (arg_strings[num_args]); | |
5249 | ||
43cd72b9 BW |
5250 | /* Get expressions for invisible operands. */ |
5251 | if (get_invisible_operands (&orig_insn)) | |
5252 | { | |
5253 | error_reset_cur_vinsn (); | |
5254 | return; | |
5255 | } | |
5256 | ||
e0001a05 NC |
5257 | /* Check for the right number and type of arguments. */ |
5258 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5259 | { |
43cd72b9 BW |
5260 | error_reset_cur_vinsn (); |
5261 | return; | |
e0001a05 NC |
5262 | } |
5263 | ||
7c430684 BW |
5264 | /* A FLIX bundle may be spread across multiple input lines. We want to |
5265 | report the first such line in the debug information. Record the line | |
5266 | number for each TInsn (assume the file name doesn't change), so the | |
5267 | first line can be found later. */ | |
5268 | as_where (&file_name, &orig_insn.linenum); | |
c138bc38 | 5269 | |
43cd72b9 BW |
5270 | xg_add_branch_and_loop_targets (&orig_insn); |
5271 | ||
431ad2d0 BW |
5272 | /* Check that immediate value for ENTRY is >= 16. */ |
5273 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5274 | { |
431ad2d0 BW |
5275 | expressionS *exp = &orig_insn.tok[2]; |
5276 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5277 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5278 | } |
5279 | ||
e0001a05 | 5280 | /* Finish it off: |
43cd72b9 BW |
5281 | assemble_tokens (opcode, tok, ntok); |
5282 | expand the tokens from the orig_insn into the | |
5283 | stack of instructions that will not expand | |
e0001a05 | 5284 | unless required at relaxation time. */ |
e0001a05 | 5285 | |
43cd72b9 BW |
5286 | if (!cur_vinsn.inside_bundle) |
5287 | emit_single_op (&orig_insn); | |
5288 | else /* We are inside a bundle. */ | |
e0001a05 | 5289 | { |
43cd72b9 BW |
5290 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5291 | cur_vinsn.num_slots++; | |
5292 | if (*input_line_pointer == '}' | |
5293 | || *(input_line_pointer - 1) == '}' | |
5294 | || *(input_line_pointer - 2) == '}') | |
5295 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5296 | } |
5297 | ||
43cd72b9 BW |
5298 | /* We've just emitted a new instruction so clear the list of labels. */ |
5299 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5300 | } |
5301 | ||
5302 | ||
43cd72b9 | 5303 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5304 | |
43cd72b9 BW |
5305 | /* For a .align directive, we mark the previous block with the alignment |
5306 | information. This will be placed in the object file in the | |
5307 | property section corresponding to this section. */ | |
e0001a05 | 5308 | |
43cd72b9 | 5309 | void |
7fa3d080 | 5310 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5311 | { |
5312 | if (linkrelax | |
b08b5071 | 5313 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5314 | && (fragP->fr_type == rs_align |
5315 | || fragP->fr_type == rs_align_code) | |
5316 | && fragP->fr_address + fragP->fr_fix > 0 | |
5317 | && fragP->fr_offset > 0 | |
5318 | && now_seg != bss_section) | |
e0001a05 | 5319 | { |
43cd72b9 BW |
5320 | fragP->tc_frag_data.is_align = TRUE; |
5321 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5322 | } |
5323 | ||
43cd72b9 | 5324 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5325 | { |
43cd72b9 BW |
5326 | int count; |
5327 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5328 | if (count != 0) | |
c138bc38 | 5329 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5330 | _("unaligned entry instruction")); |
e0001a05 | 5331 | } |
e0001a05 | 5332 | } |
43cd72b9 | 5333 | |
e0001a05 NC |
5334 | |
5335 | /* TC_FRAG_INIT hook */ | |
5336 | ||
5337 | void | |
7fa3d080 | 5338 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5339 | { |
43cd72b9 | 5340 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5341 | } |
5342 | ||
5343 | ||
5344 | symbolS * | |
7fa3d080 | 5345 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5346 | { |
5347 | return NULL; | |
5348 | } | |
5349 | ||
5350 | ||
5351 | /* Round up a section size to the appropriate boundary. */ | |
5352 | ||
5353 | valueT | |
7fa3d080 | 5354 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5355 | { |
5356 | return size; /* Byte alignment is fine. */ | |
5357 | } | |
5358 | ||
5359 | ||
5360 | long | |
7fa3d080 | 5361 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5362 | { |
5363 | char *insn_p; | |
5364 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5365 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5366 | int opnum; |
43cd72b9 | 5367 | uint32 opnd_value; |
e0001a05 | 5368 | xtensa_opcode opcode; |
43cd72b9 BW |
5369 | xtensa_format fmt; |
5370 | int slot; | |
e0001a05 NC |
5371 | xtensa_isa isa = xtensa_default_isa; |
5372 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5373 | bfd_boolean alt_reloc; |
e0001a05 | 5374 | |
e0001a05 | 5375 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5376 | return 0; |
e0001a05 NC |
5377 | |
5378 | if (!insnbuf) | |
43cd72b9 BW |
5379 | { |
5380 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5381 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5382 | } | |
e0001a05 NC |
5383 | |
5384 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5385 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5386 | fmt = xtensa_format_decode (isa, insnbuf); |
5387 | ||
5388 | if (fmt == XTENSA_UNDEFINED) | |
5389 | as_fatal (_("bad instruction format")); | |
5390 | ||
5391 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5392 | as_fatal (_("invalid relocation")); | |
5393 | ||
5394 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5395 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5396 | ||
30f725a1 BW |
5397 | /* Check for "alternate" relocations (operand not specified). None |
5398 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5399 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5400 | { | |
5401 | if (opcode != xtensa_l32r_opcode | |
5402 | && opcode != xtensa_const16_opcode) | |
5403 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5404 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5405 | return 0; |
e0001a05 NC |
5406 | } |
5407 | ||
43cd72b9 BW |
5408 | opnum = get_relaxable_immed (opcode); |
5409 | opnd_value = 0; | |
5410 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5411 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5412 | { |
5413 | as_bad_where (fixP->fx_file, | |
5414 | fixP->fx_line, | |
5415 | _("invalid relocation for operand %d of '%s'"), | |
5416 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5417 | return 0; |
e0001a05 | 5418 | } |
43cd72b9 BW |
5419 | return 0 - opnd_value; |
5420 | } | |
5421 | ||
5422 | ||
5423 | /* TC_FORCE_RELOCATION hook */ | |
5424 | ||
5425 | int | |
7fa3d080 | 5426 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5427 | { |
5428 | switch (fix->fx_r_type) | |
30f725a1 BW |
5429 | { |
5430 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5431 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5432 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5433 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5434 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5435 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5436 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5437 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5438 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5439 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5440 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5441 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5442 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5443 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5444 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5445 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5446 | return 1; |
5447 | default: | |
5448 | break; | |
e0001a05 NC |
5449 | } |
5450 | ||
43cd72b9 BW |
5451 | if (linkrelax && fix->fx_addsy |
5452 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5453 | return 1; | |
5454 | ||
5455 | return generic_force_reloc (fix); | |
5456 | } | |
5457 | ||
5458 | ||
30f725a1 BW |
5459 | /* TC_VALIDATE_FIX_SUB hook */ |
5460 | ||
5461 | int | |
5462 | xtensa_validate_fix_sub (fixS *fix) | |
5463 | { | |
5464 | segT add_symbol_segment, sub_symbol_segment; | |
5465 | ||
5466 | /* The difference of two symbols should be resolved by the assembler when | |
5467 | linkrelax is not set. If the linker may relax the section containing | |
5468 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5469 | the linker knows to adjust the difference value. */ | |
5470 | if (!linkrelax || fix->fx_addsy == NULL) | |
5471 | return 0; | |
5472 | ||
5473 | /* Make sure both symbols are in the same segment, and that segment is | |
5474 | "normal" and relaxable. If the segment is not "normal", then the | |
5475 | fix is not valid. If the segment is not "relaxable", then the fix | |
5476 | should have been handled earlier. */ | |
5477 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5478 | if (! SEG_NORMAL (add_symbol_segment) || | |
5479 | ! relaxable_section (add_symbol_segment)) | |
5480 | return 0; | |
5481 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5482 | return (sub_symbol_segment == add_symbol_segment); | |
5483 | } | |
5484 | ||
5485 | ||
43cd72b9 BW |
5486 | /* NO_PSEUDO_DOT hook */ |
5487 | ||
5488 | /* This function has nothing to do with pseudo dots, but this is the | |
5489 | nearest macro to where the check needs to take place. FIXME: This | |
5490 | seems wrong. */ | |
5491 | ||
5492 | bfd_boolean | |
7fa3d080 | 5493 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5494 | { |
5495 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5496 | as_bad (_("directives are not valid inside bundles")); | |
5497 | ||
5498 | /* This function must always return FALSE because it is called via a | |
5499 | macro that has nothing to do with bundling. */ | |
5500 | return FALSE; | |
e0001a05 NC |
5501 | } |
5502 | ||
5503 | ||
43cd72b9 | 5504 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5505 | |
5506 | void | |
7fa3d080 | 5507 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5508 | { |
43cd72b9 BW |
5509 | /* Set up the assembly state. */ |
5510 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5511 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5512 | } |
5513 | ||
5514 | ||
5515 | /* tc_fix_adjustable hook */ | |
5516 | ||
5517 | bfd_boolean | |
7fa3d080 | 5518 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 | 5519 | { |
43cd72b9 BW |
5520 | /* An offset is not allowed in combination with the difference of two |
5521 | symbols, but that cannot be easily detected after a local symbol | |
5522 | has been adjusted to a (section+offset) form. Return 0 so that such | |
5523 | an fix will not be adjusted. */ | |
5524 | if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset | |
5525 | && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy))) | |
5526 | return 0; | |
5527 | ||
e0001a05 NC |
5528 | /* We need the symbol name for the VTABLE entries. */ |
5529 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5530 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5531 | return 0; | |
5532 | ||
5533 | return 1; | |
5534 | } | |
5535 | ||
5536 | ||
5537 | void | |
55cf6793 | 5538 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5539 | { |
30f725a1 | 5540 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5541 | valueT val = 0; |
30f725a1 | 5542 | |
e7da6241 BW |
5543 | /* Subtracted symbols are only allowed for a few relocation types, and |
5544 | unless linkrelax is enabled, they should not make it to this point. */ | |
5545 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5546 | || fixP->fx_r_type == BFD_RELOC_16 | |
5547 | || fixP->fx_r_type == BFD_RELOC_8))) | |
5548 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
5549 | ||
30f725a1 | 5550 | switch (fixP->fx_r_type) |
e0001a05 | 5551 | { |
30f725a1 BW |
5552 | case BFD_RELOC_32: |
5553 | case BFD_RELOC_16: | |
5554 | case BFD_RELOC_8: | |
e7da6241 | 5555 | if (fixP->fx_subsy) |
30f725a1 BW |
5556 | { |
5557 | switch (fixP->fx_r_type) | |
5558 | { | |
5559 | case BFD_RELOC_8: | |
5560 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
5561 | break; | |
5562 | case BFD_RELOC_16: | |
5563 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
5564 | break; | |
5565 | case BFD_RELOC_32: | |
5566 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
5567 | break; | |
5568 | default: | |
5569 | break; | |
5570 | } | |
e0001a05 | 5571 | |
30f725a1 BW |
5572 | /* An offset is only allowed when it results from adjusting a |
5573 | local symbol into a section-relative offset. If the offset | |
5574 | came from the original expression, tc_fix_adjustable will have | |
5575 | prevented the fix from being converted to a section-relative | |
5576 | form so that we can flag the error here. */ | |
5577 | if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy)) | |
5578 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5579 | _("cannot represent subtraction with an offset")); | |
5580 | ||
5581 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5582 | - S_GET_VALUE (fixP->fx_subsy)); | |
5583 | ||
5584 | /* The difference value gets written out, and the DIFF reloc | |
5585 | identifies the address of the subtracted symbol (i.e., the one | |
5586 | with the lowest address). */ | |
5587 | *valP = val; | |
5588 | fixP->fx_offset -= val; | |
5589 | fixP->fx_subsy = NULL; | |
5590 | } | |
5591 | else if (! fixP->fx_addsy) | |
e0001a05 | 5592 | { |
30f725a1 | 5593 | val = *valP; |
e0001a05 | 5594 | fixP->fx_done = 1; |
30f725a1 | 5595 | } |
d47d412e BW |
5596 | /* fall through */ |
5597 | ||
5598 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
5599 | md_number_to_chars (fixpos, val, fixP->fx_size); |
5600 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5601 | break; | |
e0001a05 | 5602 | |
30f725a1 BW |
5603 | case BFD_RELOC_XTENSA_SLOT0_OP: |
5604 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
5605 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
5606 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
5607 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
5608 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
5609 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
5610 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
5611 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
5612 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
5613 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
5614 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
5615 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
5616 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
5617 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
5618 | if (linkrelax) | |
5619 | { | |
5620 | /* Write the tentative value of a PC-relative relocation to a | |
5621 | local symbol into the instruction. The value will be ignored | |
5622 | by the linker, and it makes the object file disassembly | |
5623 | readable when all branch targets are encoded in relocations. */ | |
5624 | ||
5625 | assert (fixP->fx_addsy); | |
5626 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg && !fixP->fx_plt | |
5627 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) | |
5628 | { | |
5629 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5630 | - md_pcrel_from (fixP)); | |
5631 | (void) xg_apply_fix_value (fixP, val); | |
5632 | } | |
5633 | } | |
5634 | else if (! fixP->fx_addsy) | |
5635 | { | |
5636 | val = *valP; | |
5637 | if (xg_apply_fix_value (fixP, val)) | |
5638 | fixP->fx_done = 1; | |
5639 | } | |
5640 | break; | |
e0001a05 | 5641 | |
30f725a1 BW |
5642 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
5643 | case BFD_RELOC_XTENSA_SLOT0_ALT: | |
5644 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5645 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5646 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5647 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5648 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5649 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5650 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5651 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5652 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5653 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5654 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5655 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5656 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5657 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
5658 | /* These all need to be resolved at link-time. Do nothing now. */ | |
5659 | break; | |
e0001a05 | 5660 | |
30f725a1 BW |
5661 | case BFD_RELOC_VTABLE_INHERIT: |
5662 | case BFD_RELOC_VTABLE_ENTRY: | |
5663 | fixP->fx_done = 0; | |
5664 | break; | |
e0001a05 | 5665 | |
30f725a1 BW |
5666 | default: |
5667 | as_bad (_("unhandled local relocation fix %s"), | |
5668 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
5669 | } |
5670 | } | |
5671 | ||
5672 | ||
5673 | char * | |
7fa3d080 | 5674 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 NC |
5675 | { |
5676 | int prec; | |
5677 | LITTLENUM_TYPE words[4]; | |
5678 | char *t; | |
5679 | int i; | |
5680 | ||
5681 | switch (type) | |
5682 | { | |
5683 | case 'f': | |
5684 | prec = 2; | |
5685 | break; | |
5686 | ||
5687 | case 'd': | |
5688 | prec = 4; | |
5689 | break; | |
5690 | ||
5691 | default: | |
5692 | *sizeP = 0; | |
5693 | return "bad call to md_atof"; | |
5694 | } | |
5695 | ||
5696 | t = atof_ieee (input_line_pointer, type, words); | |
5697 | if (t) | |
5698 | input_line_pointer = t; | |
5699 | ||
5700 | *sizeP = prec * 2; | |
5701 | ||
5702 | for (i = prec - 1; i >= 0; i--) | |
5703 | { | |
5704 | int idx = i; | |
5705 | if (target_big_endian) | |
5706 | idx = (prec - 1 - i); | |
5707 | ||
5708 | md_number_to_chars (litP, (valueT) words[idx], 2); | |
5709 | litP += 2; | |
5710 | } | |
5711 | ||
5712 | return NULL; | |
5713 | } | |
5714 | ||
5715 | ||
5716 | int | |
7fa3d080 | 5717 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 5718 | { |
34e41783 | 5719 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
5720 | } |
5721 | ||
5722 | ||
5723 | /* Translate internal representation of relocation info to BFD target | |
5724 | format. */ | |
5725 | ||
5726 | arelent * | |
30f725a1 | 5727 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
5728 | { |
5729 | arelent *reloc; | |
5730 | ||
5731 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
5732 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
5733 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
5734 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
5735 | ||
5736 | /* Make sure none of our internal relocations make it this far. | |
5737 | They'd better have been fully resolved by this point. */ | |
5738 | assert ((int) fixp->fx_r_type > 0); | |
5739 | ||
30f725a1 | 5740 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 5741 | |
e0001a05 NC |
5742 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
5743 | if (reloc->howto == NULL) | |
5744 | { | |
5745 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
5746 | _("cannot represent `%s' relocation in object file"), | |
5747 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
5748 | free (reloc->sym_ptr_ptr); |
5749 | free (reloc); | |
e0001a05 NC |
5750 | return NULL; |
5751 | } | |
5752 | ||
5753 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
43cd72b9 BW |
5754 | as_fatal (_("internal error? cannot generate `%s' relocation"), |
5755 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
e0001a05 | 5756 | |
e0001a05 NC |
5757 | return reloc; |
5758 | } | |
5759 | ||
7fa3d080 BW |
5760 | \f |
5761 | /* Checks for resource conflicts between instructions. */ | |
5762 | ||
c138bc38 BW |
5763 | /* The func unit stuff could be implemented as bit-vectors rather |
5764 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
5765 | slow, we will switch it. */ |
5766 | ||
c138bc38 | 5767 | resource_table * |
7fa3d080 BW |
5768 | new_resource_table (void *data, |
5769 | int cycles, | |
5770 | int nu, | |
5771 | unit_num_copies_func uncf, | |
5772 | opcode_num_units_func onuf, | |
5773 | opcode_funcUnit_use_unit_func ouuf, | |
5774 | opcode_funcUnit_use_stage_func ousf) | |
5775 | { | |
5776 | int i; | |
5777 | resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); | |
5778 | rt->data = data; | |
5779 | rt->cycles = cycles; | |
5780 | rt->allocated_cycles = cycles; | |
5781 | rt->num_units = nu; | |
5782 | rt->unit_num_copies = uncf; | |
5783 | rt->opcode_num_units = onuf; | |
5784 | rt->opcode_unit_use = ouuf; | |
5785 | rt->opcode_unit_stage = ousf; | |
5786 | ||
0bf60745 | 5787 | rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *)); |
7fa3d080 | 5788 | for (i = 0; i < cycles; i++) |
0bf60745 | 5789 | rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char)); |
7fa3d080 BW |
5790 | |
5791 | return rt; | |
5792 | } | |
5793 | ||
5794 | ||
c138bc38 | 5795 | void |
7fa3d080 BW |
5796 | clear_resource_table (resource_table *rt) |
5797 | { | |
5798 | int i, j; | |
5799 | for (i = 0; i < rt->allocated_cycles; i++) | |
5800 | for (j = 0; j < rt->num_units; j++) | |
5801 | rt->units[i][j] = 0; | |
5802 | } | |
5803 | ||
5804 | ||
5805 | /* We never shrink it, just fake it into thinking so. */ | |
5806 | ||
c138bc38 | 5807 | void |
7fa3d080 BW |
5808 | resize_resource_table (resource_table *rt, int cycles) |
5809 | { | |
5810 | int i, old_cycles; | |
5811 | ||
5812 | rt->cycles = cycles; | |
5813 | if (cycles <= rt->allocated_cycles) | |
5814 | return; | |
5815 | ||
5816 | old_cycles = rt->allocated_cycles; | |
5817 | rt->allocated_cycles = cycles; | |
5818 | ||
0bf60745 BW |
5819 | rt->units = xrealloc (rt->units, |
5820 | rt->allocated_cycles * sizeof (unsigned char *)); | |
7fa3d080 | 5821 | for (i = 0; i < old_cycles; i++) |
0bf60745 BW |
5822 | rt->units[i] = xrealloc (rt->units[i], |
5823 | rt->num_units * sizeof (unsigned char)); | |
7fa3d080 | 5824 | for (i = old_cycles; i < cycles; i++) |
0bf60745 | 5825 | rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char)); |
7fa3d080 BW |
5826 | } |
5827 | ||
5828 | ||
c138bc38 | 5829 | bfd_boolean |
7fa3d080 BW |
5830 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
5831 | { | |
5832 | int i; | |
5833 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5834 | ||
c138bc38 | 5835 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5836 | { |
5837 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5838 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
5839 | int copies_in_use = rt->units[stage + cycle][unit]; | |
5840 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
5841 | if (copies_in_use >= copies) | |
5842 | return FALSE; | |
5843 | } | |
5844 | return TRUE; | |
5845 | } | |
7fa3d080 | 5846 | |
c138bc38 BW |
5847 | |
5848 | void | |
7fa3d080 BW |
5849 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5850 | { | |
5851 | int i; | |
5852 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5853 | ||
c138bc38 | 5854 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5855 | { |
5856 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5857 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
5858 | /* Note that this allows resources to be oversubscribed. That's |
5859 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
5860 | resources_available reports when a resource is over-subscribed, |
5861 | so it's easy to tell. */ | |
5862 | rt->units[stage + cycle][unit]++; | |
5863 | } | |
5864 | } | |
5865 | ||
5866 | ||
c138bc38 | 5867 | void |
7fa3d080 BW |
5868 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5869 | { | |
5870 | int i; | |
5871 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5872 | ||
c138bc38 | 5873 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5874 | { |
5875 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5876 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
0bf60745 | 5877 | assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 5878 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
5879 | } |
5880 | } | |
c138bc38 | 5881 | |
7fa3d080 BW |
5882 | |
5883 | /* Wrapper functions make parameterized resource reservation | |
5884 | more convenient. */ | |
5885 | ||
c138bc38 | 5886 | int |
7fa3d080 BW |
5887 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
5888 | { | |
5889 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 5890 | return use->unit; |
7fa3d080 BW |
5891 | } |
5892 | ||
5893 | ||
c138bc38 | 5894 | int |
7fa3d080 BW |
5895 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
5896 | { | |
5897 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
5898 | return use->stage; | |
5899 | } | |
5900 | ||
5901 | ||
5902 | /* Note that this function does not check issue constraints, but | |
5903 | solely whether the hardware is available to execute the given | |
c138bc38 | 5904 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 5905 | write the same state, or access the same tieports. That is |
a1ace8d8 | 5906 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
5907 | |
5908 | static bfd_boolean | |
5909 | resources_conflict (vliw_insn *vinsn) | |
5910 | { | |
5911 | int i; | |
5912 | static resource_table *rt = NULL; | |
5913 | ||
5914 | /* This is the most common case by far. Optimize it. */ | |
5915 | if (vinsn->num_slots == 1) | |
5916 | return FALSE; | |
43cd72b9 | 5917 | |
c138bc38 | 5918 | if (rt == NULL) |
7fa3d080 BW |
5919 | { |
5920 | xtensa_isa isa = xtensa_default_isa; | |
5921 | rt = new_resource_table | |
5922 | (isa, xtensa_isa_num_pipe_stages (isa), | |
5923 | xtensa_isa_num_funcUnits (isa), | |
5924 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
5925 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
5926 | opcode_funcUnit_use_unit, | |
5927 | opcode_funcUnit_use_stage); | |
5928 | } | |
43cd72b9 | 5929 | |
7fa3d080 | 5930 | clear_resource_table (rt); |
43cd72b9 | 5931 | |
7fa3d080 BW |
5932 | for (i = 0; i < vinsn->num_slots; i++) |
5933 | { | |
5934 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
5935 | return TRUE; | |
5936 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
5937 | } | |
e0001a05 | 5938 | |
7fa3d080 BW |
5939 | return FALSE; |
5940 | } | |
e0001a05 | 5941 | |
7fa3d080 BW |
5942 | \f |
5943 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 5944 | |
7fa3d080 BW |
5945 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
5946 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 5947 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
5948 | |
5949 | ||
43cd72b9 BW |
5950 | /* We have reached the end of a bundle; emit into the frag. */ |
5951 | ||
e0001a05 | 5952 | static void |
7fa3d080 | 5953 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 5954 | { |
43cd72b9 BW |
5955 | IStack slotstack; |
5956 | int i; | |
5957 | char *file_name; | |
d77b99c9 | 5958 | unsigned line; |
e0001a05 | 5959 | |
43cd72b9 | 5960 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
5961 | { |
5962 | xg_clear_vinsn (vinsn); | |
5963 | return; | |
5964 | } | |
43cd72b9 BW |
5965 | |
5966 | /* First, find a format that works. */ | |
5967 | if (vinsn->format == XTENSA_UNDEFINED) | |
5968 | vinsn->format = xg_find_narrowest_format (vinsn); | |
5969 | ||
5970 | if (vinsn->format == XTENSA_UNDEFINED) | |
5971 | { | |
5972 | as_where (&file_name, &line); | |
5973 | as_bad_where (file_name, line, | |
5974 | _("couldn't find a valid instruction format")); | |
5975 | fprintf (stderr, _(" ops were: ")); | |
5976 | for (i = 0; i < vinsn->num_slots; i++) | |
5977 | fprintf (stderr, _(" %s;"), | |
5978 | xtensa_opcode_name (xtensa_default_isa, | |
5979 | vinsn->slots[i].opcode)); | |
5980 | fprintf (stderr, _("\n")); | |
5981 | xg_clear_vinsn (vinsn); | |
5982 | return; | |
5983 | } | |
5984 | ||
5985 | if (vinsn->num_slots | |
5986 | != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) | |
e0001a05 | 5987 | { |
43cd72b9 BW |
5988 | as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), |
5989 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
5990 | xtensa_format_num_slots (xtensa_default_isa, vinsn->format), | |
5991 | vinsn->num_slots); | |
5992 | xg_clear_vinsn (vinsn); | |
5993 | return; | |
5994 | } | |
e0001a05 | 5995 | |
c138bc38 | 5996 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
5997 | { |
5998 | as_where (&file_name, &line); | |
5999 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6000 | fprintf (stderr, " ops were: "); | |
6001 | for (i = 0; i < vinsn->num_slots; i++) | |
6002 | fprintf (stderr, " %s;", | |
6003 | xtensa_opcode_name (xtensa_default_isa, | |
6004 | vinsn->slots[i].opcode)); | |
6005 | fprintf (stderr, "\n"); | |
6006 | xg_clear_vinsn (vinsn); | |
6007 | return; | |
6008 | } | |
6009 | ||
6010 | for (i = 0; i < vinsn->num_slots; i++) | |
6011 | { | |
6012 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6013 | { |
43cd72b9 BW |
6014 | symbolS *lit_sym = NULL; |
6015 | int j; | |
6016 | bfd_boolean e = FALSE; | |
6017 | bfd_boolean saved_density = density_supported; | |
6018 | ||
6019 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6020 | if (vinsn->num_slots > 1) | |
6021 | density_supported = FALSE; | |
6022 | ||
6023 | istack_init (&slotstack); | |
6024 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6025 | { |
43cd72b9 BW |
6026 | vinsn->slots[i].opcode = |
6027 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6028 | vinsn->format, i); | |
6029 | vinsn->slots[i].ntok = 0; | |
6030 | } | |
e0001a05 | 6031 | |
43cd72b9 BW |
6032 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6033 | { | |
6034 | e = TRUE; | |
6035 | continue; | |
e0001a05 | 6036 | } |
e0001a05 | 6037 | |
43cd72b9 | 6038 | density_supported = saved_density; |
e0001a05 | 6039 | |
43cd72b9 BW |
6040 | if (e) |
6041 | { | |
6042 | xg_clear_vinsn (vinsn); | |
6043 | return; | |
6044 | } | |
e0001a05 | 6045 | |
0fa77c95 | 6046 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6047 | { |
6048 | TInsn *insn = &slotstack.insn[j]; | |
6049 | if (insn->insn_type == ITYPE_LITERAL) | |
6050 | { | |
6051 | assert (lit_sym == NULL); | |
6052 | lit_sym = xg_assemble_literal (insn); | |
6053 | } | |
6054 | else | |
6055 | { | |
0fa77c95 | 6056 | assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6057 | if (lit_sym) |
6058 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6059 | if (j != slotstack.ninsn - 1) |
6060 | emit_single_op (insn); | |
43cd72b9 BW |
6061 | } |
6062 | } | |
6063 | ||
6064 | if (vinsn->num_slots > 1) | |
6065 | { | |
6066 | if (opcode_fits_format_slot | |
6067 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6068 | vinsn->format, i)) | |
6069 | { | |
6070 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6071 | } | |
6072 | else | |
6073 | { | |
b2d179be | 6074 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6075 | if (vinsn->format == XTENSA_UNDEFINED) |
6076 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6077 | else | |
c138bc38 | 6078 | vinsn->slots[i].opcode |
43cd72b9 BW |
6079 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6080 | vinsn->format, i); | |
6081 | ||
6082 | vinsn->slots[i].ntok = 0; | |
6083 | } | |
6084 | } | |
6085 | else | |
6086 | { | |
6087 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6088 | vinsn->format = XTENSA_UNDEFINED; | |
6089 | } | |
6090 | } | |
6091 | } | |
6092 | ||
6093 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6094 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6095 | { |
6096 | as_where (&file_name, &line); | |
6097 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6098 | fprintf (stderr, " ops were: "); | |
6099 | for (i = 0; i < vinsn->num_slots; i++) | |
6100 | fprintf (stderr, " %s;", | |
6101 | xtensa_opcode_name (xtensa_default_isa, | |
6102 | vinsn->slots[i].opcode)); | |
6103 | fprintf (stderr, "\n"); | |
6104 | xg_clear_vinsn (vinsn); | |
6105 | return; | |
6106 | } | |
6107 | ||
6108 | /* First, find a format that works. */ | |
6109 | if (vinsn->format == XTENSA_UNDEFINED) | |
6110 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6111 | ||
6112 | xg_assemble_vliw_tokens (vinsn); | |
6113 | ||
6114 | xg_clear_vinsn (vinsn); | |
6115 | } | |
6116 | ||
6117 | ||
6118 | /* Given an vliw instruction, what conflicts are there in register | |
6119 | usage and in writes to states and queues? | |
6120 | ||
6121 | This function does two things: | |
6122 | 1. Reports an error when a vinsn contains illegal combinations | |
6123 | of writes to registers states or queues. | |
6124 | 2. Marks individual tinsns as not relaxable if the combination | |
6125 | contains antidependencies. | |
6126 | ||
6127 | Job 2 handles things like swap semantics in instructions that need | |
6128 | to be relaxed. For example, | |
6129 | ||
6130 | addi a0, a1, 100000 | |
6131 | ||
6132 | normally would be relaxed to | |
6133 | ||
6134 | l32r a0, some_label | |
6135 | add a0, a1, a0 | |
6136 | ||
6137 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6138 | ||
6139 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6140 | ||
6141 | then we can't relax it into | |
6142 | ||
6143 | l32r a0, some_label | |
6144 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6145 | ||
6146 | because the value of a0 is trashed before the second add can read it. */ | |
6147 | ||
7fa3d080 BW |
6148 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6149 | ||
43cd72b9 | 6150 | static bfd_boolean |
7fa3d080 | 6151 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6152 | { |
6153 | int i, j; | |
6154 | int branches = 0; | |
6155 | xtensa_isa isa = xtensa_default_isa; | |
6156 | ||
6157 | assert (!past_xtensa_end); | |
6158 | ||
6159 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6160 | { | |
6161 | TInsn *op1 = &vinsn->slots[i]; | |
6162 | if (op1->is_specific_opcode) | |
6163 | op1->keep_wide = TRUE; | |
6164 | else | |
6165 | op1->keep_wide = FALSE; | |
6166 | } | |
6167 | ||
6168 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6169 | { | |
6170 | TInsn *op1 = &vinsn->slots[i]; | |
6171 | ||
6172 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6173 | branches++; | |
6174 | ||
6175 | for (j = 0; j < vinsn->num_slots; j++) | |
6176 | { | |
6177 | if (i != j) | |
6178 | { | |
6179 | TInsn *op2 = &vinsn->slots[j]; | |
6180 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6181 | switch (conflict_type) | |
6182 | { | |
6183 | case 'c': | |
6184 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6185 | xtensa_opcode_name (isa, op1->opcode), i, | |
6186 | xtensa_opcode_name (isa, op2->opcode), j); | |
6187 | return TRUE; | |
6188 | case 'd': | |
6189 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6190 | xtensa_opcode_name (isa, op1->opcode), i, | |
6191 | xtensa_opcode_name (isa, op2->opcode), j); | |
6192 | return TRUE; | |
6193 | case 'e': | |
53dfbcc7 | 6194 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6195 | xtensa_opcode_name (isa, op1->opcode), i, |
6196 | xtensa_opcode_name (isa, op2->opcode), j); | |
6197 | return TRUE; | |
6198 | case 'f': | |
53dfbcc7 | 6199 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6200 | xtensa_opcode_name (isa, op1->opcode), i, |
6201 | xtensa_opcode_name (isa, op2->opcode), j); | |
6202 | return TRUE; | |
6203 | default: | |
6204 | /* Everything is OK. */ | |
6205 | break; | |
6206 | } | |
6207 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6208 | || conflict_type == 'a'); | |
6209 | } | |
6210 | } | |
6211 | } | |
6212 | ||
6213 | if (branches > 1) | |
6214 | { | |
6215 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6216 | return TRUE; | |
6217 | } | |
6218 | ||
6219 | return FALSE; | |
6220 | } | |
6221 | ||
6222 | ||
a1ace8d8 | 6223 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6224 | Cases found are: |
6225 | ||
6226 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6227 | case B: no relationship between what is read and written (both could | |
6228 | read the same reg though) | |
c138bc38 | 6229 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6230 | bundle) |
6231 | case D: t1 writes a state that t2 also writes | |
6232 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6233 | case F: two volatile queue accesses |
43cd72b9 BW |
6234 | */ |
6235 | ||
6236 | static char | |
7fa3d080 | 6237 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6238 | { |
6239 | xtensa_isa isa = xtensa_default_isa; | |
6240 | xtensa_regfile t1_regfile, t2_regfile; | |
6241 | int t1_reg, t2_reg; | |
6242 | int t1_base_reg, t1_last_reg; | |
6243 | int t2_base_reg, t2_last_reg; | |
6244 | char t1_inout, t2_inout; | |
6245 | int i, j; | |
6246 | char conflict = 'b'; | |
6247 | int t1_states; | |
6248 | int t2_states; | |
6249 | int t1_interfaces; | |
6250 | int t2_interfaces; | |
6251 | bfd_boolean t1_volatile = FALSE; | |
6252 | bfd_boolean t2_volatile = FALSE; | |
6253 | ||
6254 | /* Check registers. */ | |
6255 | for (j = 0; j < t2->ntok; j++) | |
6256 | { | |
6257 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6258 | continue; | |
6259 | ||
6260 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6261 | t2_base_reg = t2->tok[j].X_add_number; | |
6262 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6263 | ||
6264 | for (i = 0; i < t1->ntok; i++) | |
6265 | { | |
6266 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6267 | continue; | |
6268 | ||
6269 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6270 | ||
6271 | if (t1_regfile != t2_regfile) | |
6272 | continue; | |
6273 | ||
6274 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6275 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6276 | ||
6277 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6278 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6279 | { | |
6280 | if (t1_inout == 'm' || t1_inout == 'o' | |
6281 | || t2_inout == 'm' || t2_inout == 'o') | |
6282 | { | |
6283 | conflict = 'a'; | |
6284 | continue; | |
6285 | } | |
6286 | } | |
6287 | ||
6288 | t1_base_reg = t1->tok[i].X_add_number; | |
6289 | t1_last_reg = (t1_base_reg | |
6290 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6291 | ||
6292 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6293 | { | |
6294 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6295 | { | |
6296 | if (t1_reg != t2_reg) | |
6297 | continue; | |
6298 | ||
6299 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6300 | { |
6301 | conflict = 'a'; | |
6302 | continue; | |
6303 | } | |
43cd72b9 | 6304 | |
7fa3d080 BW |
6305 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6306 | { | |
6307 | conflict = 'a'; | |
6308 | continue; | |
6309 | } | |
43cd72b9 | 6310 | |
7fa3d080 BW |
6311 | if (t1_inout != 'i' && t2_inout != 'i') |
6312 | return 'c'; | |
6313 | } | |
6314 | } | |
6315 | } | |
6316 | } | |
43cd72b9 | 6317 | |
7fa3d080 BW |
6318 | /* Check states. */ |
6319 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6320 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6321 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6322 | { |
7fa3d080 BW |
6323 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6324 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6325 | for (i = 0; i < t1_states; i++) | |
6326 | { | |
6327 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6328 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
c138bc38 | 6329 | if (t1_so != t2_so) |
7fa3d080 | 6330 | continue; |
43cd72b9 | 6331 | |
7fa3d080 BW |
6332 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6333 | { | |
6334 | conflict = 'a'; | |
6335 | continue; | |
6336 | } | |
c138bc38 | 6337 | |
7fa3d080 BW |
6338 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6339 | { | |
6340 | conflict = 'a'; | |
6341 | continue; | |
6342 | } | |
c138bc38 | 6343 | |
7fa3d080 BW |
6344 | if (t1_inout != 'i' && t2_inout != 'i') |
6345 | return 'd'; | |
c138bc38 | 6346 | } |
7fa3d080 | 6347 | } |
43cd72b9 | 6348 | |
7fa3d080 BW |
6349 | /* Check tieports. */ |
6350 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6351 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6352 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6353 | { |
7fa3d080 BW |
6354 | xtensa_interface t2_int |
6355 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6356 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6357 | ||
53dfbcc7 | 6358 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6359 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6360 | t2_volatile = TRUE; |
a1ace8d8 | 6361 | |
7fa3d080 BW |
6362 | for (i = 0; i < t1_interfaces; i++) |
6363 | { | |
6364 | xtensa_interface t1_int | |
6365 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6366 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6367 | |
53dfbcc7 | 6368 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6369 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6370 | t1_volatile = TRUE; |
a1ace8d8 BW |
6371 | |
6372 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6373 | return 'f'; | |
c138bc38 | 6374 | |
7fa3d080 BW |
6375 | if (t1_int != t2_int) |
6376 | continue; | |
c138bc38 | 6377 | |
7fa3d080 BW |
6378 | if (t2_inout == 'i' && t1_inout == 'o') |
6379 | { | |
6380 | conflict = 'a'; | |
6381 | continue; | |
6382 | } | |
c138bc38 | 6383 | |
7fa3d080 BW |
6384 | if (t1_inout == 'i' && t2_inout == 'o') |
6385 | { | |
6386 | conflict = 'a'; | |
6387 | continue; | |
6388 | } | |
c138bc38 | 6389 | |
7fa3d080 BW |
6390 | if (t1_inout != 'i' && t2_inout != 'i') |
6391 | return 'e'; | |
6392 | } | |
43cd72b9 | 6393 | } |
c138bc38 | 6394 | |
7fa3d080 | 6395 | return conflict; |
43cd72b9 BW |
6396 | } |
6397 | ||
6398 | ||
6399 | static xtensa_format | |
7fa3d080 | 6400 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6401 | { |
6402 | /* Right now we assume that the ops within the vinsn are properly | |
6403 | ordered for the slots that the programmer wanted them in. In | |
6404 | other words, we don't rearrange the ops in hopes of finding a | |
6405 | better format. The scheduler handles that. */ | |
6406 | ||
6407 | xtensa_isa isa = xtensa_default_isa; | |
6408 | xtensa_format format; | |
6409 | vliw_insn v_copy = *vinsn; | |
6410 | xtensa_opcode nop_opcode = xtensa_nop_opcode; | |
6411 | ||
65738a7d BW |
6412 | if (vinsn->num_slots == 1) |
6413 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6414 | ||
43cd72b9 BW |
6415 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6416 | { | |
6417 | v_copy = *vinsn; | |
6418 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) | |
6419 | { | |
6420 | int slot; | |
6421 | int fit = 0; | |
6422 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6423 | { | |
6424 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6425 | { | |
6426 | v_copy.slots[slot].opcode = | |
6427 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6428 | v_copy.slots[slot].ntok = 0; | |
6429 | } | |
6430 | ||
6431 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6432 | format, slot)) | |
6433 | fit++; | |
7fa3d080 | 6434 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6435 | { |
7fa3d080 BW |
6436 | TInsn widened; |
6437 | /* Try the widened version. */ | |
6438 | if (!v_copy.slots[slot].keep_wide | |
6439 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6440 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6441 | &widened, TRUE) | |
7fa3d080 BW |
6442 | && opcode_fits_format_slot (widened.opcode, |
6443 | format, slot)) | |
43cd72b9 | 6444 | { |
7fa3d080 BW |
6445 | v_copy.slots[slot] = widened; |
6446 | fit++; | |
43cd72b9 BW |
6447 | } |
6448 | } | |
6449 | } | |
6450 | if (fit == v_copy.num_slots) | |
6451 | { | |
6452 | *vinsn = v_copy; | |
6453 | xtensa_format_encode (isa, format, vinsn->insnbuf); | |
6454 | vinsn->format = format; | |
6455 | break; | |
6456 | } | |
6457 | } | |
6458 | } | |
6459 | ||
6460 | if (format == xtensa_isa_num_formats (isa)) | |
6461 | return XTENSA_UNDEFINED; | |
6462 | ||
6463 | return format; | |
6464 | } | |
6465 | ||
6466 | ||
6467 | /* Return the additional space needed in a frag | |
6468 | for possible relaxations of any ops in a VLIW insn. | |
6469 | Also fill out the relaxations that might be required of | |
6470 | each tinsn in the vinsn. */ | |
6471 | ||
6472 | static int | |
e7da6241 | 6473 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6474 | { |
e7da6241 | 6475 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6476 | int extra_space = 0; |
6477 | int slot; | |
6478 | ||
6479 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6480 | { | |
6481 | TInsn *tinsn = &vinsn->slots[slot]; | |
6482 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6483 | { | |
6484 | /* A narrow instruction could be widened later to help | |
6485 | alignment issues. */ | |
84b08ed9 | 6486 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6487 | && !tinsn->is_specific_opcode |
6488 | && vinsn->num_slots == 1) | |
6489 | { | |
6490 | /* Difference in bytes between narrow and wide insns... */ | |
6491 | extra_space += 1; | |
6492 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6493 | } |
6494 | } | |
6495 | else | |
6496 | { | |
b08b5071 BW |
6497 | if (workaround_b_j_loop_end |
6498 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6499 | && use_transform ()) |
6500 | { | |
6501 | /* Add 2 of these. */ | |
6502 | extra_space += 3; /* for the nop size */ | |
6503 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6504 | } | |
c138bc38 | 6505 | |
43cd72b9 BW |
6506 | /* Need to assemble it with space for the relocation. */ |
6507 | if (xg_is_relaxable_insn (tinsn, 0) | |
6508 | && !tinsn->is_specific_opcode) | |
6509 | { | |
6510 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6511 | int max_literal_size = | |
6512 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6513 | |
43cd72b9 | 6514 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6515 | |
43cd72b9 | 6516 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6517 | extra_space += max_size; |
6518 | } | |
6519 | else | |
6520 | { | |
e7da6241 BW |
6521 | /* A fix record will be added for this instruction prior |
6522 | to relaxation, so make it end the frag. */ | |
6523 | finish_frag = TRUE; | |
43cd72b9 BW |
6524 | } |
6525 | } | |
6526 | } | |
e7da6241 | 6527 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6528 | return extra_space; |
6529 | } | |
6530 | ||
6531 | ||
6532 | static void | |
b2d179be | 6533 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6534 | { |
6535 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6536 | int slot, chosen_slot; |
43cd72b9 | 6537 | |
b2d179be BW |
6538 | vinsn->format = xg_get_single_format (tinsn->opcode); |
6539 | assert (vinsn->format != XTENSA_UNDEFINED); | |
6540 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); | |
43cd72b9 | 6541 | |
b2d179be BW |
6542 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6543 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6544 | { |
b2d179be BW |
6545 | if (slot == chosen_slot) |
6546 | vinsn->slots[slot] = *tinsn; | |
6547 | else | |
6548 | { | |
6549 | vinsn->slots[slot].opcode = | |
6550 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6551 | vinsn->slots[slot].ntok = 0; | |
6552 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6553 | } | |
43cd72b9 | 6554 | } |
43cd72b9 BW |
6555 | } |
6556 | ||
6557 | ||
6558 | static bfd_boolean | |
7fa3d080 | 6559 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6560 | { |
6561 | int i; | |
6562 | IStack istack; /* put instructions into here */ | |
6563 | symbolS *lit_sym = NULL; | |
6564 | symbolS *label_sym = NULL; | |
6565 | ||
6566 | istack_init (&istack); | |
6567 | ||
6568 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
6569 | Because the scheduling and bundling characteristics of movi and |
6570 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 6571 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 6572 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
6573 | || orig_insn->opcode == xtensa_movi_n_opcode) |
6574 | && !cur_vinsn.inside_bundle | |
43cd72b9 BW |
6575 | && (orig_insn->tok[1].X_op == O_symbol |
6576 | || orig_insn->tok[1].X_op == O_pltrel)) | |
6577 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); | |
6578 | else | |
6579 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6580 | return TRUE; | |
6581 | ||
6582 | for (i = 0; i < istack.ninsn; i++) | |
6583 | { | |
6584 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 6585 | switch (insn->insn_type) |
43cd72b9 BW |
6586 | { |
6587 | case ITYPE_LITERAL: | |
6588 | assert (lit_sym == NULL); | |
6589 | lit_sym = xg_assemble_literal (insn); | |
6590 | break; | |
6591 | case ITYPE_LABEL: | |
6592 | { | |
6593 | static int relaxed_sym_idx = 0; | |
6594 | char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); | |
6595 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); | |
6596 | colon (label); | |
6597 | assert (label_sym == NULL); | |
6598 | label_sym = symbol_find_or_make (label); | |
6599 | assert (label_sym); | |
6600 | free (label); | |
6601 | } | |
6602 | break; | |
6603 | case ITYPE_INSN: | |
b2d179be BW |
6604 | { |
6605 | vliw_insn v; | |
6606 | if (lit_sym) | |
6607 | xg_resolve_literals (insn, lit_sym); | |
6608 | if (label_sym) | |
6609 | xg_resolve_labels (insn, label_sym); | |
6610 | xg_init_vinsn (&v); | |
6611 | bundle_tinsn (insn, &v); | |
6612 | finish_vinsn (&v); | |
6613 | xg_free_vinsn (&v); | |
6614 | } | |
43cd72b9 BW |
6615 | break; |
6616 | default: | |
6617 | assert (0); | |
6618 | break; | |
6619 | } | |
6620 | } | |
6621 | return FALSE; | |
6622 | } | |
6623 | ||
6624 | ||
34e41783 BW |
6625 | static int |
6626 | total_frag_text_expansion (fragS *fragP) | |
6627 | { | |
6628 | int slot; | |
6629 | int total_expansion = 0; | |
6630 | ||
6631 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
6632 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; | |
6633 | ||
6634 | return total_expansion; | |
6635 | } | |
6636 | ||
6637 | ||
43cd72b9 BW |
6638 | /* Emit a vliw instruction to the current fragment. */ |
6639 | ||
7fa3d080 BW |
6640 | static void |
6641 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 6642 | { |
e7da6241 | 6643 | bfd_boolean finish_frag; |
43cd72b9 BW |
6644 | bfd_boolean is_jump = FALSE; |
6645 | bfd_boolean is_branch = FALSE; | |
6646 | xtensa_isa isa = xtensa_default_isa; | |
6647 | int i; | |
6648 | int insn_size; | |
6649 | int extra_space; | |
6650 | char *f = NULL; | |
6651 | int slot; | |
7c430684 BW |
6652 | unsigned current_line, best_linenum; |
6653 | char *current_file; | |
43cd72b9 | 6654 | |
7c430684 | 6655 | best_linenum = UINT_MAX; |
43cd72b9 BW |
6656 | |
6657 | if (generating_literals) | |
6658 | { | |
6659 | static int reported = 0; | |
6660 | if (reported < 4) | |
6661 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
6662 | _("cannot assemble into a literal fragment")); | |
6663 | if (reported == 3) | |
6664 | as_bad (_("...")); | |
6665 | reported++; | |
6666 | return; | |
6667 | } | |
6668 | ||
6669 | if (frag_now_fix () != 0 | |
b08b5071 | 6670 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 6671 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
b08b5071 | 6672 | || !use_transform () != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
6673 | || (directive_state[directive_longcalls] |
6674 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
6675 | || (directive_state[directive_absolute_literals] |
6676 | != frag_now->tc_frag_data.use_absolute_literals))) | |
6677 | { | |
6678 | frag_wane (frag_now); | |
6679 | frag_new (0); | |
6680 | xtensa_set_frag_assembly_state (frag_now); | |
6681 | } | |
6682 | ||
6683 | if (workaround_a0_b_retw | |
6684 | && vinsn->num_slots == 1 | |
6685 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
6686 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
6687 | && use_transform ()) | |
6688 | { | |
6689 | has_a0_b_retw = TRUE; | |
6690 | ||
6691 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
6692 | After the first assembly pass we will check all of them and | |
6693 | add a nop if needed. */ | |
6694 | frag_now->tc_frag_data.is_insn = TRUE; | |
6695 | frag_var (rs_machine_dependent, 4, 4, | |
6696 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6697 | frag_now->fr_symbol, | |
6698 | frag_now->fr_offset, | |
6699 | NULL); | |
6700 | xtensa_set_frag_assembly_state (frag_now); | |
6701 | frag_now->tc_frag_data.is_insn = TRUE; | |
6702 | frag_var (rs_machine_dependent, 4, 4, | |
6703 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6704 | frag_now->fr_symbol, | |
6705 | frag_now->fr_offset, | |
6706 | NULL); | |
6707 | xtensa_set_frag_assembly_state (frag_now); | |
6708 | } | |
6709 | ||
6710 | for (i = 0; i < vinsn->num_slots; i++) | |
6711 | { | |
6712 | /* See if the instruction implies an aligned section. */ | |
6713 | if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1) | |
6714 | record_alignment (now_seg, 2); | |
c138bc38 | 6715 | |
43cd72b9 | 6716 | /* Also determine the best line number for debug info. */ |
7c430684 BW |
6717 | best_linenum = vinsn->slots[i].linenum < best_linenum |
6718 | ? vinsn->slots[i].linenum : best_linenum; | |
43cd72b9 BW |
6719 | } |
6720 | ||
6721 | /* Special cases for instructions that force an alignment... */ | |
6722 | /* None of these opcodes are bundle-able. */ | |
6723 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
6724 | { | |
d77b99c9 | 6725 | int max_fill; |
c138bc38 | 6726 | |
43cd72b9 BW |
6727 | xtensa_set_frag_assembly_state (frag_now); |
6728 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 6729 | |
43cd72b9 BW |
6730 | max_fill = get_text_align_max_fill_size |
6731 | (get_text_align_power (xtensa_fetch_width), | |
6732 | TRUE, frag_now->tc_frag_data.is_no_density); | |
6733 | ||
6734 | if (use_transform ()) | |
6735 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
6736 | RELAX_ALIGN_NEXT_OPCODE, | |
6737 | frag_now->fr_symbol, | |
6738 | frag_now->fr_offset, | |
6739 | NULL); | |
6740 | else | |
c138bc38 | 6741 | frag_var (rs_machine_dependent, 0, 0, |
43cd72b9 BW |
6742 | RELAX_CHECK_ALIGN_NEXT_OPCODE, 0, 0, NULL); |
6743 | xtensa_set_frag_assembly_state (frag_now); | |
c138bc38 | 6744 | |
43cd72b9 BW |
6745 | xtensa_move_labels (frag_now, 0, FALSE); |
6746 | } | |
6747 | ||
b08b5071 | 6748 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
6749 | && !vinsn->slots[0].is_specific_opcode) |
6750 | { | |
6751 | xtensa_mark_literal_pool_location (); | |
6752 | xtensa_move_labels (frag_now, 0, TRUE); | |
6753 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); | |
6754 | } | |
6755 | ||
6756 | if (vinsn->num_slots == 1) | |
6757 | { | |
6758 | if (workaround_a0_b_retw && use_transform ()) | |
6759 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
6760 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
6761 | ||
6762 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
6763 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
6764 | } | |
6765 | else | |
6766 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
6767 | ||
6768 | insn_size = xtensa_format_length (isa, vinsn->format); | |
6769 | ||
e7da6241 | 6770 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
6771 | |
6772 | /* vinsn_to_insnbuf will produce the error. */ | |
6773 | if (vinsn->format != XTENSA_UNDEFINED) | |
6774 | { | |
d77b99c9 | 6775 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
6776 | xtensa_set_frag_assembly_state (frag_now); |
6777 | frag_now->tc_frag_data.is_insn = TRUE; | |
6778 | } | |
6779 | ||
e7da6241 | 6780 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
6781 | if (vinsn->format == XTENSA_UNDEFINED) |
6782 | return; | |
6783 | ||
d77b99c9 | 6784 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 6785 | |
7c430684 BW |
6786 | /* Temporarily set the logical line number to the one we want to appear |
6787 | in the debug information. */ | |
6788 | as_where (¤t_file, ¤t_line); | |
6789 | new_logical_line (current_file, best_linenum); | |
6790 | dwarf2_emit_insn (insn_size + extra_space); | |
6791 | new_logical_line (current_file, current_line); | |
43cd72b9 BW |
6792 | |
6793 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6794 | { | |
6795 | TInsn *tinsn = &vinsn->slots[slot]; | |
6796 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; | |
7c834684 | 6797 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 6798 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 BW |
6799 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
6800 | if (tinsn->literal_space != 0) | |
6801 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
6802 | ||
6803 | if (tinsn->subtype == RELAX_NARROW) | |
6804 | assert (vinsn->num_slots == 1); | |
6805 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) | |
6806 | is_jump = TRUE; | |
6807 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
6808 | is_branch = TRUE; | |
6809 | ||
e7da6241 BW |
6810 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
6811 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
6812 | finish_frag = TRUE; |
6813 | } | |
6814 | ||
6815 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 6816 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
6817 | |
6818 | if (finish_frag) | |
6819 | { | |
6820 | frag_variant (rs_machine_dependent, | |
6821 | extra_space, extra_space, RELAX_SLOTS, | |
6822 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
6823 | xtensa_set_frag_assembly_state (frag_now); | |
6824 | } | |
6825 | ||
6826 | /* Special cases for loops: | |
6827 | close_loop_end should be inserted AFTER short_loop. | |
6828 | Make sure that CLOSE loops are processed BEFORE short_loops | |
6829 | when converting them. */ | |
6830 | ||
6831 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
6832 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) | |
6833 | && !vinsn->slots[0].is_specific_opcode) | |
6834 | { | |
6835 | if (workaround_short_loop && use_transform ()) | |
6836 | { | |
6837 | maybe_has_short_loop = TRUE; | |
6838 | frag_now->tc_frag_data.is_insn = TRUE; | |
6839 | frag_var (rs_machine_dependent, 4, 4, | |
6840 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6841 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6842 | frag_now->tc_frag_data.is_insn = TRUE; | |
6843 | frag_var (rs_machine_dependent, 4, 4, | |
6844 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6845 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6846 | } | |
6847 | ||
6848 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
6849 | loop at least 12 bytes away from another loop's end. */ | |
6850 | if (workaround_close_loop_end && use_transform ()) | |
6851 | { | |
6852 | maybe_has_close_loop_end = TRUE; | |
6853 | frag_now->tc_frag_data.is_insn = TRUE; | |
6854 | frag_var (rs_machine_dependent, 12, 12, | |
6855 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
6856 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6857 | } | |
6858 | } | |
6859 | ||
6860 | if (use_transform ()) | |
6861 | { | |
6862 | if (is_jump) | |
6863 | { | |
6864 | assert (finish_frag); | |
6865 | frag_var (rs_machine_dependent, | |
6866 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6867 | RELAX_UNREACHABLE, | |
6868 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6869 | xtensa_set_frag_assembly_state (frag_now); | |
6870 | } | |
7b1cc377 | 6871 | else if (is_branch && do_align_targets ()) |
43cd72b9 BW |
6872 | { |
6873 | assert (finish_frag); | |
6874 | frag_var (rs_machine_dependent, | |
6875 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6876 | RELAX_MAYBE_UNREACHABLE, | |
6877 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6878 | xtensa_set_frag_assembly_state (frag_now); | |
6879 | frag_var (rs_machine_dependent, | |
6880 | 0, 0, | |
6881 | RELAX_MAYBE_DESIRE_ALIGN, | |
6882 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6883 | xtensa_set_frag_assembly_state (frag_now); | |
6884 | } | |
6885 | } | |
6886 | ||
6887 | /* Now, if the original opcode was a call... */ | |
6888 | if (do_align_targets () | |
6889 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
6890 | { | |
b08b5071 | 6891 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
6892 | frag_now->tc_frag_data.is_insn = TRUE; |
6893 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
6894 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6895 | xtensa_set_frag_assembly_state (frag_now); | |
6896 | } | |
6897 | ||
6898 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
6899 | { | |
6900 | frag_wane (frag_now); | |
6901 | frag_new (0); | |
6902 | xtensa_set_frag_assembly_state (frag_now); | |
6903 | } | |
6904 | } | |
6905 | ||
6906 | \f | |
7fa3d080 BW |
6907 | /* xtensa_end and helper functions. */ |
6908 | ||
6909 | static void xtensa_cleanup_align_frags (void); | |
6910 | static void xtensa_fix_target_frags (void); | |
6911 | static void xtensa_mark_narrow_branches (void); | |
6912 | static void xtensa_mark_zcl_first_insns (void); | |
6913 | static void xtensa_fix_a0_b_retw_frags (void); | |
6914 | static void xtensa_fix_b_j_loop_end_frags (void); | |
6915 | static void xtensa_fix_close_loop_end_frags (void); | |
6916 | static void xtensa_fix_short_loop_frags (void); | |
6917 | static void xtensa_sanity_check (void); | |
6918 | ||
43cd72b9 | 6919 | void |
7fa3d080 | 6920 | xtensa_end (void) |
43cd72b9 BW |
6921 | { |
6922 | directive_balance (); | |
6923 | xtensa_flush_pending_output (); | |
6924 | ||
6925 | past_xtensa_end = TRUE; | |
6926 | ||
6927 | xtensa_move_literals (); | |
6928 | ||
6929 | xtensa_reorder_segments (); | |
6930 | xtensa_cleanup_align_frags (); | |
6931 | xtensa_fix_target_frags (); | |
6932 | if (workaround_a0_b_retw && has_a0_b_retw) | |
6933 | xtensa_fix_a0_b_retw_frags (); | |
6934 | if (workaround_b_j_loop_end) | |
6935 | xtensa_fix_b_j_loop_end_frags (); | |
6936 | ||
6937 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
6938 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
6939 | xtensa_fix_close_loop_end_frags (); | |
6940 | ||
6941 | if (workaround_short_loop && maybe_has_short_loop) | |
6942 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
6943 | if (align_targets) |
6944 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
6945 | xtensa_mark_zcl_first_insns (); |
6946 | ||
6947 | xtensa_sanity_check (); | |
6948 | } | |
6949 | ||
6950 | ||
6951 | static void | |
7fa3d080 | 6952 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
6953 | { |
6954 | frchainS *frchP; | |
6955 | ||
6956 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
6957 | { | |
6958 | fragS *fragP; | |
6959 | /* Walk over all of the fragments in a subsection. */ | |
6960 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
6961 | { | |
6962 | if ((fragP->fr_type == rs_align | |
6963 | || fragP->fr_type == rs_align_code | |
6964 | || (fragP->fr_type == rs_machine_dependent | |
6965 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
6966 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
6967 | && fragP->fr_fix == 0) | |
6968 | { | |
6969 | fragS *next = fragP->fr_next; | |
6970 | ||
6971 | while (next | |
6972 | && next->fr_fix == 0 | |
6973 | && next->fr_type == rs_machine_dependent | |
6974 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
6975 | { | |
6976 | frag_wane (next); | |
6977 | next = next->fr_next; | |
6978 | } | |
6979 | } | |
6980 | /* If we don't widen branch targets, then they | |
6981 | will be easier to align. */ | |
6982 | if (fragP->tc_frag_data.is_branch_target | |
6983 | && fragP->fr_opcode == fragP->fr_literal | |
6984 | && fragP->fr_type == rs_machine_dependent | |
6985 | && fragP->fr_subtype == RELAX_SLOTS | |
6986 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
6987 | frag_wane (fragP); | |
c138bc38 | 6988 | if (fragP->fr_type == rs_machine_dependent |
43cd72b9 BW |
6989 | && fragP->fr_subtype == RELAX_UNREACHABLE) |
6990 | fragP->tc_frag_data.is_unreachable = TRUE; | |
6991 | } | |
6992 | } | |
6993 | } | |
6994 | ||
6995 | ||
6996 | /* Re-process all of the fragments looking to convert all of the | |
6997 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
6998 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 6999 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 7000 | |
43cd72b9 | 7001 | static void |
7fa3d080 | 7002 | xtensa_fix_target_frags (void) |
e0001a05 NC |
7003 | { |
7004 | frchainS *frchP; | |
7005 | ||
7006 | /* When this routine is called, all of the subsections are still intact | |
7007 | so we walk over subsections instead of sections. */ | |
7008 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7009 | { | |
e0001a05 NC |
7010 | fragS *fragP; |
7011 | ||
7012 | /* Walk over all of the fragments in a subsection. */ | |
7013 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7014 | { | |
7015 | if (fragP->fr_type == rs_machine_dependent | |
7016 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7017 | { | |
7b1cc377 | 7018 | if (next_frag_is_branch_target (fragP)) |
e0001a05 NC |
7019 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; |
7020 | else | |
7021 | frag_wane (fragP); | |
7022 | } | |
e0001a05 NC |
7023 | } |
7024 | } | |
7025 | } | |
7026 | ||
7027 | ||
7fa3d080 BW |
7028 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7029 | ||
43cd72b9 | 7030 | static void |
7fa3d080 | 7031 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
7032 | { |
7033 | frchainS *frchP; | |
7034 | ||
7035 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7036 | { | |
7037 | fragS *fragP; | |
7038 | /* Walk over all of the fragments in a subsection. */ | |
7039 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7040 | { | |
7041 | if (fragP->fr_type == rs_machine_dependent | |
7042 | && fragP->fr_subtype == RELAX_SLOTS | |
7043 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
7044 | { | |
7045 | vliw_insn vinsn; | |
43cd72b9 BW |
7046 | |
7047 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
7048 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
7049 | ||
43cd72b9 BW |
7050 | if (vinsn.num_slots == 1 |
7051 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
7052 | vinsn.slots[0].opcode) | |
7053 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 | |
7054 | && is_narrow_branch_guaranteed_in_range (fragP, | |
7055 | &vinsn.slots[0])) | |
7056 | { | |
7057 | fragP->fr_subtype = RELAX_SLOTS; | |
7058 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
b5e4a23d | 7059 | fragP->tc_frag_data.is_aligning_branch = 1; |
43cd72b9 BW |
7060 | } |
7061 | } | |
7062 | } | |
7063 | } | |
7064 | } | |
7065 | ||
7066 | ||
7067 | /* A branch is typically widened only when its target is out of | |
7068 | range. However, we would like to widen them to align a subsequent | |
7069 | branch target when possible. | |
7070 | ||
7071 | Because the branch relaxation code is so convoluted, the optimal solution | |
7072 | (combining the two cases) is difficult to get right in all circumstances. | |
7073 | We therefore go with an "almost as good" solution, where we only | |
7074 | use for alignment narrow branches that definitely will not expand to a | |
7075 | jump and a branch. These functions find and mark these cases. */ | |
7076 | ||
a67517f4 BW |
7077 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
7078 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
7079 | We start counting beginning with the frag after the 2-byte branch, so the | |
7080 | maximum offset is (4 - 2) + 63 = 65. */ | |
7081 | #define MAX_IMMED6 65 | |
43cd72b9 | 7082 | |
d77b99c9 | 7083 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 7084 | |
43cd72b9 | 7085 | static bfd_boolean |
7fa3d080 | 7086 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 BW |
7087 | { |
7088 | const expressionS *expr = &tinsn->tok[1]; | |
7089 | symbolS *symbolP = expr->X_add_symbol; | |
d77b99c9 | 7090 | offsetT max_distance = expr->X_add_number; |
e7da6241 BW |
7091 | fragS *target_frag; |
7092 | ||
7093 | if (expr->X_op != O_symbol) | |
7094 | return FALSE; | |
7095 | ||
7096 | target_frag = symbol_get_frag (symbolP); | |
7097 | ||
43cd72b9 BW |
7098 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
7099 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
7100 | return FALSE; | |
7101 | ||
7102 | /* The branch doesn't branch over it's own frag, | |
7103 | but over the subsequent ones. */ | |
7104 | fragP = fragP->fr_next; | |
7105 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
7106 | { | |
7107 | max_distance += unrelaxed_frag_max_size (fragP); | |
7108 | fragP = fragP->fr_next; | |
7109 | } | |
7110 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
7111 | return TRUE; | |
e0001a05 NC |
7112 | return FALSE; |
7113 | } | |
7114 | ||
7115 | ||
43cd72b9 | 7116 | static void |
7fa3d080 | 7117 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
7118 | { |
7119 | frchainS *frchP; | |
7120 | ||
7121 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7122 | { | |
7123 | fragS *fragP; | |
7124 | /* Walk over all of the fragments in a subsection. */ | |
7125 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7126 | { | |
7127 | if (fragP->fr_type == rs_machine_dependent | |
7128 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
7129 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
7130 | { | |
7131 | /* Find the loop frag. */ | |
7132 | fragS *targ_frag = next_non_empty_frag (fragP); | |
7133 | /* Find the first insn frag. */ | |
7134 | targ_frag = next_non_empty_frag (targ_frag); | |
7135 | ||
7136 | /* Of course, sometimes (mostly for toy test cases) a | |
7137 | zero-cost loop instruction is the last in a section. */ | |
c138bc38 | 7138 | if (targ_frag) |
03aaa593 BW |
7139 | { |
7140 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
7141 | /* Do not widen a frag that is the first instruction of a | |
7142 | zero-cost loop. It makes that loop harder to align. */ | |
7143 | if (targ_frag->fr_type == rs_machine_dependent | |
7144 | && targ_frag->fr_subtype == RELAX_SLOTS | |
7145 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
7146 | == RELAX_NARROW)) | |
7147 | { | |
7148 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
7149 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
7150 | else | |
7151 | { | |
7152 | frag_wane (targ_frag); | |
7153 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
7154 | } | |
7155 | } | |
7156 | } | |
d7c531cd BW |
7157 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) |
7158 | frag_wane (fragP); | |
43cd72b9 BW |
7159 | } |
7160 | } | |
7161 | } | |
7162 | } | |
7163 | ||
7164 | ||
e0001a05 NC |
7165 | /* Re-process all of the fragments looking to convert all of the |
7166 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
7167 | conditional branch or a retw/retw.n, convert this frag to one that | |
7168 | will generate a NOP. In any case close it off with a .fill 0. */ | |
7169 | ||
7fa3d080 BW |
7170 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
7171 | ||
e0001a05 | 7172 | static void |
7fa3d080 | 7173 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
7174 | { |
7175 | frchainS *frchP; | |
7176 | ||
7177 | /* When this routine is called, all of the subsections are still intact | |
7178 | so we walk over subsections instead of sections. */ | |
7179 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7180 | { | |
7181 | fragS *fragP; | |
7182 | ||
7183 | /* Walk over all of the fragments in a subsection. */ | |
7184 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7185 | { | |
7186 | if (fragP->fr_type == rs_machine_dependent | |
7187 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
7188 | { | |
7189 | if (next_instrs_are_b_retw (fragP)) | |
43cd72b9 | 7190 | { |
b08b5071 | 7191 | if (fragP->tc_frag_data.is_no_transform) |
43cd72b9 BW |
7192 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); |
7193 | else | |
7194 | relax_frag_add_nop (fragP); | |
7195 | } | |
7196 | frag_wane (fragP); | |
e0001a05 NC |
7197 | } |
7198 | } | |
7199 | } | |
7200 | } | |
7201 | ||
7202 | ||
7fa3d080 BW |
7203 | static bfd_boolean |
7204 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
7205 | { |
7206 | xtensa_opcode opcode; | |
43cd72b9 | 7207 | xtensa_format fmt; |
e0001a05 NC |
7208 | const fragS *next_fragP = next_non_empty_frag (fragP); |
7209 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 7210 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
7211 | xtensa_isa isa = xtensa_default_isa; |
7212 | int offset = 0; | |
43cd72b9 BW |
7213 | int slot; |
7214 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
7215 | |
7216 | if (!insnbuf) | |
43cd72b9 BW |
7217 | { |
7218 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7219 | slotbuf = xtensa_insnbuf_alloc (isa); | |
7220 | } | |
e0001a05 NC |
7221 | |
7222 | if (next_fragP == NULL) | |
7223 | return FALSE; | |
7224 | ||
7225 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
7226 | xtensa_insnbuf_from_chars |
7227 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7228 | fmt = xtensa_format_decode (isa, insnbuf); |
7229 | if (fmt == XTENSA_UNDEFINED) | |
7230 | return FALSE; | |
7231 | ||
7232 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
7233 | { | |
7234 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
7235 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
7236 | ||
7237 | branch_seen = (branch_seen | |
7238 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
7239 | } | |
e0001a05 | 7240 | |
43cd72b9 | 7241 | if (!branch_seen) |
e0001a05 NC |
7242 | return FALSE; |
7243 | ||
43cd72b9 | 7244 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7245 | if (offset == next_fragP->fr_fix) |
7246 | { | |
7247 | next_fragP = next_non_empty_frag (next_fragP); | |
7248 | offset = 0; | |
7249 | } | |
43cd72b9 | 7250 | |
e0001a05 NC |
7251 | if (next_fragP == NULL) |
7252 | return FALSE; | |
7253 | ||
7254 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
7255 | xtensa_insnbuf_from_chars |
7256 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7257 | fmt = xtensa_format_decode (isa, insnbuf); |
7258 | ||
7259 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
7260 | have no problems. */ | |
7261 | if (fmt == XTENSA_UNDEFINED | |
7262 | || xtensa_format_num_slots (isa, fmt) != 1) | |
7263 | return FALSE; | |
7264 | ||
7265 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
7266 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 7267 | |
b08b5071 | 7268 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 7269 | return TRUE; |
43cd72b9 | 7270 | |
e0001a05 NC |
7271 | return FALSE; |
7272 | } | |
7273 | ||
7274 | ||
7275 | /* Re-process all of the fragments looking to convert all of the | |
7276 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
7277 | loop end label, convert this frag to one that will generate a NOP. | |
7278 | In any case close it off with a .fill 0. */ | |
7279 | ||
7fa3d080 BW |
7280 | static bfd_boolean next_instr_is_loop_end (fragS *); |
7281 | ||
e0001a05 | 7282 | static void |
7fa3d080 | 7283 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
7284 | { |
7285 | frchainS *frchP; | |
7286 | ||
7287 | /* When this routine is called, all of the subsections are still intact | |
7288 | so we walk over subsections instead of sections. */ | |
7289 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7290 | { | |
7291 | fragS *fragP; | |
7292 | ||
7293 | /* Walk over all of the fragments in a subsection. */ | |
7294 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7295 | { | |
7296 | if (fragP->fr_type == rs_machine_dependent | |
7297 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
7298 | { | |
7299 | if (next_instr_is_loop_end (fragP)) | |
43cd72b9 | 7300 | { |
b08b5071 | 7301 | if (fragP->tc_frag_data.is_no_transform) |
43cd72b9 BW |
7302 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); |
7303 | else | |
7304 | relax_frag_add_nop (fragP); | |
7305 | } | |
7306 | frag_wane (fragP); | |
e0001a05 NC |
7307 | } |
7308 | } | |
7309 | } | |
7310 | } | |
7311 | ||
7312 | ||
7fa3d080 BW |
7313 | static bfd_boolean |
7314 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
7315 | { |
7316 | const fragS *next_fragP; | |
7317 | ||
7318 | if (next_frag_is_loop_target (fragP)) | |
7319 | return FALSE; | |
7320 | ||
7321 | next_fragP = next_non_empty_frag (fragP); | |
7322 | if (next_fragP == NULL) | |
7323 | return FALSE; | |
7324 | ||
7325 | if (!next_frag_is_loop_target (next_fragP)) | |
7326 | return FALSE; | |
7327 | ||
7328 | /* If the size is >= 3 then there is more than one instruction here. | |
7329 | The hardware bug will not fire. */ | |
7330 | if (next_fragP->fr_fix > 3) | |
7331 | return FALSE; | |
7332 | ||
7333 | return TRUE; | |
7334 | } | |
7335 | ||
7336 | ||
7337 | /* Re-process all of the fragments looking to convert all of the | |
7338 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
7339 | not MY loop's loop end within 12 bytes, add enough nops here to | |
7340 | make it at least 12 bytes away. In any case close it off with a | |
7341 | .fill 0. */ | |
7342 | ||
d77b99c9 BW |
7343 | static offsetT min_bytes_to_other_loop_end |
7344 | (fragS *, fragS *, offsetT, offsetT); | |
7fa3d080 | 7345 | |
e0001a05 | 7346 | static void |
7fa3d080 | 7347 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
7348 | { |
7349 | frchainS *frchP; | |
7350 | ||
7351 | /* When this routine is called, all of the subsections are still intact | |
7352 | so we walk over subsections instead of sections. */ | |
7353 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7354 | { | |
7355 | fragS *fragP; | |
7356 | ||
7357 | fragS *current_target = NULL; | |
7358 | offsetT current_offset = 0; | |
7359 | ||
7360 | /* Walk over all of the fragments in a subsection. */ | |
7361 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7362 | { | |
7363 | if (fragP->fr_type == rs_machine_dependent | |
43cd72b9 BW |
7364 | && ((fragP->fr_subtype == RELAX_IMMED) |
7365 | || ((fragP->fr_subtype == RELAX_SLOTS) | |
7366 | && (fragP->tc_frag_data.slot_subtypes[0] | |
7367 | == RELAX_IMMED)))) | |
e0001a05 NC |
7368 | { |
7369 | /* Read it. If the instruction is a loop, get the target. */ | |
43cd72b9 BW |
7370 | TInsn t_insn; |
7371 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
7372 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
7373 | t_insn.opcode) == 1) | |
e0001a05 | 7374 | { |
e0001a05 | 7375 | /* Get the current fragment target. */ |
43cd72b9 | 7376 | if (fragP->tc_frag_data.slot_symbols[0]) |
e0001a05 | 7377 | { |
43cd72b9 BW |
7378 | symbolS *sym = fragP->tc_frag_data.slot_symbols[0]; |
7379 | current_target = symbol_get_frag (sym); | |
e0001a05 NC |
7380 | current_offset = fragP->fr_offset; |
7381 | } | |
7382 | } | |
7383 | } | |
7384 | ||
7385 | if (current_target | |
7386 | && fragP->fr_type == rs_machine_dependent | |
7387 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
7388 | { | |
d77b99c9 BW |
7389 | offsetT min_bytes; |
7390 | int bytes_added = 0; | |
e0001a05 NC |
7391 | |
7392 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
7393 | /* Max out at 12. */ | |
7394 | min_bytes = min_bytes_to_other_loop_end | |
7395 | (fragP->fr_next, current_target, current_offset, | |
7396 | REQUIRED_LOOP_DIVIDING_BYTES); | |
7397 | ||
7398 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
7399 | { | |
b08b5071 | 7400 | if (fragP->tc_frag_data.is_no_transform) |
43cd72b9 BW |
7401 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); |
7402 | else | |
e0001a05 | 7403 | { |
43cd72b9 BW |
7404 | while (min_bytes + bytes_added |
7405 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
e0001a05 | 7406 | { |
43cd72b9 | 7407 | int length = 3; |
c138bc38 | 7408 | |
43cd72b9 BW |
7409 | if (fragP->fr_var < length) |
7410 | as_fatal (_("fr_var %lu < length %d"), | |
dd49a749 | 7411 | (long) fragP->fr_var, length); |
43cd72b9 BW |
7412 | else |
7413 | { | |
7414 | assemble_nop (length, | |
7415 | fragP->fr_literal + fragP->fr_fix); | |
7416 | fragP->fr_fix += length; | |
7417 | fragP->fr_var -= length; | |
7418 | } | |
7419 | bytes_added += length; | |
e0001a05 | 7420 | } |
e0001a05 NC |
7421 | } |
7422 | } | |
7423 | frag_wane (fragP); | |
7424 | } | |
43cd72b9 BW |
7425 | assert (fragP->fr_type != rs_machine_dependent |
7426 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); | |
e0001a05 NC |
7427 | } |
7428 | } | |
7429 | } | |
7430 | ||
7431 | ||
d77b99c9 | 7432 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 7433 | |
d77b99c9 | 7434 | static offsetT |
7fa3d080 BW |
7435 | min_bytes_to_other_loop_end (fragS *fragP, |
7436 | fragS *current_target, | |
7437 | offsetT current_offset, | |
d77b99c9 | 7438 | offsetT max_size) |
e0001a05 | 7439 | { |
d77b99c9 | 7440 | offsetT offset = 0; |
e0001a05 NC |
7441 | fragS *current_fragP; |
7442 | ||
7443 | for (current_fragP = fragP; | |
7444 | current_fragP; | |
7445 | current_fragP = current_fragP->fr_next) | |
7446 | { | |
7447 | if (current_fragP->tc_frag_data.is_loop_target | |
7448 | && current_fragP != current_target) | |
7449 | return offset + current_offset; | |
7450 | ||
7451 | offset += unrelaxed_frag_min_size (current_fragP); | |
7452 | ||
7453 | if (offset + current_offset >= max_size) | |
7454 | return max_size; | |
7455 | } | |
7456 | return max_size; | |
7457 | } | |
7458 | ||
7459 | ||
d77b99c9 | 7460 | static offsetT |
7fa3d080 | 7461 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 7462 | { |
d77b99c9 | 7463 | offsetT size = fragP->fr_fix; |
e0001a05 | 7464 | |
d77b99c9 | 7465 | /* Add fill size. */ |
e0001a05 NC |
7466 | if (fragP->fr_type == rs_fill) |
7467 | size += fragP->fr_offset; | |
7468 | ||
7469 | return size; | |
7470 | } | |
7471 | ||
7472 | ||
d77b99c9 | 7473 | static offsetT |
7fa3d080 | 7474 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 7475 | { |
d77b99c9 | 7476 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
7477 | switch (fragP->fr_type) |
7478 | { | |
7479 | case 0: | |
c138bc38 | 7480 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
7481 | end up with type 0. */ |
7482 | break; | |
7483 | case rs_fill: | |
7484 | case rs_org: | |
7485 | case rs_space: | |
7486 | size += fragP->fr_offset; | |
7487 | break; | |
7488 | case rs_align: | |
7489 | case rs_align_code: | |
7490 | case rs_align_test: | |
7491 | case rs_leb128: | |
7492 | case rs_cfa: | |
7493 | case rs_dwarf2dbg: | |
7494 | /* No further adjustments needed. */ | |
7495 | break; | |
7496 | case rs_machine_dependent: | |
7497 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
7498 | size += fragP->fr_var; | |
7499 | break; | |
7500 | default: | |
7501 | /* We had darn well better know how big it is. */ | |
7502 | assert (0); | |
7503 | break; | |
7504 | } | |
7505 | ||
7506 | return size; | |
7507 | } | |
7508 | ||
7509 | ||
e0001a05 NC |
7510 | /* Re-process all of the fragments looking to convert all |
7511 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
7512 | ||
7513 | A) | |
7514 | 1) the instruction size count to the loop end label | |
7515 | is too short (<= 2 instructions), | |
7516 | 2) loop has a jump or branch in it | |
7517 | ||
7518 | or B) | |
43cd72b9 | 7519 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
7520 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
7521 | 3) the instruction size count to the loop end label is too short | |
7522 | (<= 2 instructions) | |
7523 | then convert this frag (and maybe the next one) to generate a NOP. | |
7524 | In any case close it off with a .fill 0. */ | |
7525 | ||
d77b99c9 | 7526 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
7527 | static bfd_boolean branch_before_loop_end (fragS *); |
7528 | ||
e0001a05 | 7529 | static void |
7fa3d080 | 7530 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
7531 | { |
7532 | frchainS *frchP; | |
7533 | ||
7534 | /* When this routine is called, all of the subsections are still intact | |
7535 | so we walk over subsections instead of sections. */ | |
7536 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7537 | { | |
7538 | fragS *fragP; | |
7539 | fragS *current_target = NULL; | |
7540 | offsetT current_offset = 0; | |
7541 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; | |
7542 | ||
7543 | /* Walk over all of the fragments in a subsection. */ | |
7544 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7545 | { | |
43cd72b9 | 7546 | /* Check on the current loop. */ |
e0001a05 | 7547 | if (fragP->fr_type == rs_machine_dependent |
43cd72b9 BW |
7548 | && ((fragP->fr_subtype == RELAX_IMMED) |
7549 | || ((fragP->fr_subtype == RELAX_SLOTS) | |
7550 | && (fragP->tc_frag_data.slot_subtypes[0] | |
7551 | == RELAX_IMMED)))) | |
e0001a05 | 7552 | { |
43cd72b9 BW |
7553 | TInsn t_insn; |
7554 | ||
e0001a05 | 7555 | /* Read it. If the instruction is a loop, get the target. */ |
43cd72b9 BW |
7556 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); |
7557 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
7558 | t_insn.opcode) == 1) | |
e0001a05 | 7559 | { |
e0001a05 | 7560 | /* Get the current fragment target. */ |
43cd72b9 | 7561 | if (fragP->tc_frag_data.slot_symbols[0]) |
e0001a05 | 7562 | { |
43cd72b9 BW |
7563 | symbolS *sym = fragP->tc_frag_data.slot_symbols[0]; |
7564 | current_target = symbol_get_frag (sym); | |
e0001a05 | 7565 | current_offset = fragP->fr_offset; |
43cd72b9 | 7566 | current_opcode = t_insn.opcode; |
e0001a05 NC |
7567 | } |
7568 | } | |
7569 | } | |
7570 | ||
7571 | if (fragP->fr_type == rs_machine_dependent | |
7572 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7573 | { | |
d77b99c9 | 7574 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 |
e0001a05 | 7575 | && (branch_before_loop_end (fragP->fr_next) |
43cd72b9 | 7576 | || (workaround_all_short_loops |
e0001a05 | 7577 | && current_opcode != XTENSA_UNDEFINED |
b08b5071 | 7578 | && current_opcode != xtensa_loop_opcode))) |
43cd72b9 | 7579 | { |
b08b5071 | 7580 | if (fragP->tc_frag_data.is_no_transform) |
43cd72b9 BW |
7581 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); |
7582 | else | |
7583 | relax_frag_add_nop (fragP); | |
7584 | } | |
7585 | frag_wane (fragP); | |
e0001a05 NC |
7586 | } |
7587 | } | |
7588 | } | |
7589 | } | |
7590 | ||
7591 | ||
d77b99c9 | 7592 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 7593 | |
d77b99c9 | 7594 | static int |
7fa3d080 BW |
7595 | count_insns_to_loop_end (fragS *base_fragP, |
7596 | bfd_boolean count_relax_add, | |
d77b99c9 | 7597 | int max_count) |
e0001a05 NC |
7598 | { |
7599 | fragS *fragP = NULL; | |
d77b99c9 | 7600 | int insn_count = 0; |
e0001a05 NC |
7601 | |
7602 | fragP = base_fragP; | |
7603 | ||
7604 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
7605 | { | |
7606 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
7607 | if (insn_count >= max_count) | |
7608 | return max_count; | |
7609 | ||
7610 | if (count_relax_add) | |
7611 | { | |
7612 | if (fragP->fr_type == rs_machine_dependent | |
7613 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7614 | { | |
7615 | /* In order to add the appropriate number of | |
7616 | NOPs, we count an instruction for downstream | |
7617 | occurrences. */ | |
7618 | insn_count++; | |
7619 | if (insn_count >= max_count) | |
7620 | return max_count; | |
7621 | } | |
7622 | } | |
7623 | } | |
7624 | return insn_count; | |
7625 | } | |
7626 | ||
7627 | ||
d77b99c9 | 7628 | static int |
7fa3d080 | 7629 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 7630 | { |
43cd72b9 BW |
7631 | xtensa_isa isa = xtensa_default_isa; |
7632 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 7633 | int insn_count = 0; |
e0001a05 NC |
7634 | int offset = 0; |
7635 | ||
7636 | if (!fragP->tc_frag_data.is_insn) | |
7637 | return insn_count; | |
7638 | ||
43cd72b9 BW |
7639 | if (!insnbuf) |
7640 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7641 | ||
e0001a05 NC |
7642 | /* Decode the fixed instructions. */ |
7643 | while (offset < fragP->fr_fix) | |
7644 | { | |
43cd72b9 BW |
7645 | xtensa_format fmt; |
7646 | ||
d77b99c9 BW |
7647 | xtensa_insnbuf_from_chars |
7648 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7649 | fmt = xtensa_format_decode (isa, insnbuf); |
7650 | ||
7651 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
7652 | { |
7653 | as_fatal (_("undecodable instruction in instruction frag")); | |
7654 | return insn_count; | |
7655 | } | |
43cd72b9 | 7656 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7657 | insn_count++; |
7658 | } | |
7659 | ||
7660 | return insn_count; | |
7661 | } | |
7662 | ||
7663 | ||
7fa3d080 BW |
7664 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
7665 | ||
43cd72b9 | 7666 | static bfd_boolean |
7fa3d080 | 7667 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
7668 | { |
7669 | fragS *fragP; | |
7670 | ||
7671 | for (fragP = base_fragP; | |
7672 | fragP && !fragP->tc_frag_data.is_loop_target; | |
7673 | fragP = fragP->fr_next) | |
7674 | { | |
7675 | if (unrelaxed_frag_has_b_j (fragP)) | |
7676 | return TRUE; | |
7677 | } | |
7678 | return FALSE; | |
7679 | } | |
7680 | ||
7681 | ||
43cd72b9 | 7682 | static bfd_boolean |
7fa3d080 | 7683 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 7684 | { |
43cd72b9 BW |
7685 | static xtensa_insnbuf insnbuf = NULL; |
7686 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
7687 | int offset = 0; |
7688 | ||
7689 | if (!fragP->tc_frag_data.is_insn) | |
7690 | return FALSE; | |
7691 | ||
43cd72b9 BW |
7692 | if (!insnbuf) |
7693 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7694 | ||
e0001a05 NC |
7695 | /* Decode the fixed instructions. */ |
7696 | while (offset < fragP->fr_fix) | |
7697 | { | |
43cd72b9 BW |
7698 | xtensa_format fmt; |
7699 | int slot; | |
7700 | ||
d77b99c9 BW |
7701 | xtensa_insnbuf_from_chars |
7702 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7703 | fmt = xtensa_format_decode (isa, insnbuf); |
7704 | if (fmt == XTENSA_UNDEFINED) | |
7705 | return FALSE; | |
7706 | ||
7707 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 7708 | { |
43cd72b9 BW |
7709 | xtensa_opcode opcode = |
7710 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
7711 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
7712 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
7713 | return TRUE; | |
e0001a05 | 7714 | } |
43cd72b9 | 7715 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7716 | } |
7717 | return FALSE; | |
7718 | } | |
7719 | ||
7720 | ||
7721 | /* Checks to be made after initial assembly but before relaxation. */ | |
7722 | ||
7fa3d080 BW |
7723 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
7724 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
7725 | ||
e0001a05 | 7726 | static void |
7fa3d080 | 7727 | xtensa_sanity_check (void) |
e0001a05 NC |
7728 | { |
7729 | char *file_name; | |
d77b99c9 | 7730 | unsigned line; |
e0001a05 NC |
7731 | |
7732 | frchainS *frchP; | |
7733 | ||
7734 | as_where (&file_name, &line); | |
7735 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7736 | { | |
7737 | fragS *fragP; | |
7738 | ||
7739 | /* Walk over all of the fragments in a subsection. */ | |
7740 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7741 | { | |
7742 | /* Currently we only check for empty loops here. */ | |
7743 | if (fragP->fr_type == rs_machine_dependent | |
7744 | && fragP->fr_subtype == RELAX_IMMED) | |
7745 | { | |
7746 | static xtensa_insnbuf insnbuf = NULL; | |
7747 | TInsn t_insn; | |
7748 | ||
7749 | if (fragP->fr_opcode != NULL) | |
7750 | { | |
7751 | if (!insnbuf) | |
7752 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
43cd72b9 BW |
7753 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); |
7754 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
e0001a05 | 7755 | |
43cd72b9 BW |
7756 | if (xtensa_opcode_is_loop (xtensa_default_isa, |
7757 | t_insn.opcode) == 1) | |
e0001a05 NC |
7758 | { |
7759 | if (is_empty_loop (&t_insn, fragP)) | |
7760 | { | |
7761 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7762 | as_bad (_("invalid empty loop")); | |
7763 | } | |
7764 | if (!is_local_forward_loop (&t_insn, fragP)) | |
7765 | { | |
7766 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7767 | as_bad (_("loop target does not follow " | |
7768 | "loop instruction in section")); | |
7769 | } | |
7770 | } | |
7771 | } | |
7772 | } | |
7773 | } | |
7774 | } | |
7775 | new_logical_line (file_name, line); | |
7776 | } | |
7777 | ||
7778 | ||
7779 | #define LOOP_IMMED_OPN 1 | |
7780 | ||
43cd72b9 | 7781 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 7782 | |
7fa3d080 BW |
7783 | static bfd_boolean |
7784 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7785 | { |
7786 | const expressionS *expr; | |
7787 | symbolS *symbolP; | |
7788 | fragS *next_fragP; | |
7789 | ||
7790 | if (insn->insn_type != ITYPE_INSN) | |
7791 | return FALSE; | |
7792 | ||
43cd72b9 | 7793 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7794 | return FALSE; |
7795 | ||
7796 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7797 | return FALSE; | |
7798 | ||
7799 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7800 | ||
7801 | if (expr->X_op != O_symbol) | |
7802 | return FALSE; | |
7803 | ||
7804 | symbolP = expr->X_add_symbol; | |
7805 | if (!symbolP) | |
7806 | return FALSE; | |
7807 | ||
7808 | if (symbol_get_frag (symbolP) == NULL) | |
7809 | return FALSE; | |
7810 | ||
7811 | if (S_GET_VALUE (symbolP) != 0) | |
7812 | return FALSE; | |
7813 | ||
7814 | /* Walk through the zero-size fragments from this one. If we find | |
7815 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 7816 | |
e0001a05 NC |
7817 | for (next_fragP = fragP->fr_next; |
7818 | next_fragP != NULL; | |
7819 | next_fragP = next_fragP->fr_next) | |
7820 | { | |
7821 | if (next_fragP == symbol_get_frag (symbolP)) | |
7822 | return TRUE; | |
7823 | if (next_fragP->fr_fix != 0) | |
7824 | return FALSE; | |
7825 | } | |
7826 | return FALSE; | |
7827 | } | |
7828 | ||
7829 | ||
7fa3d080 BW |
7830 | static bfd_boolean |
7831 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7832 | { |
7833 | const expressionS *expr; | |
7834 | symbolS *symbolP; | |
7835 | fragS *next_fragP; | |
7836 | ||
7837 | if (insn->insn_type != ITYPE_INSN) | |
7838 | return FALSE; | |
7839 | ||
43cd72b9 | 7840 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) == 0) |
e0001a05 NC |
7841 | return FALSE; |
7842 | ||
7843 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7844 | return FALSE; | |
7845 | ||
7846 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7847 | ||
7848 | if (expr->X_op != O_symbol) | |
7849 | return FALSE; | |
7850 | ||
7851 | symbolP = expr->X_add_symbol; | |
7852 | if (!symbolP) | |
7853 | return FALSE; | |
7854 | ||
7855 | if (symbol_get_frag (symbolP) == NULL) | |
7856 | return FALSE; | |
7857 | ||
7858 | /* Walk through fragments until we find the target. | |
7859 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 7860 | |
e0001a05 NC |
7861 | for (next_fragP = fragP->fr_next; |
7862 | next_fragP != NULL; | |
7863 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
7864 | { |
7865 | if (next_fragP == symbol_get_frag (symbolP)) | |
7866 | return TRUE; | |
7867 | } | |
e0001a05 NC |
7868 | |
7869 | return FALSE; | |
7870 | } | |
7871 | ||
7872 | \f | |
7873 | /* Alignment Functions. */ | |
7874 | ||
d77b99c9 BW |
7875 | static int |
7876 | get_text_align_power (unsigned target_size) | |
e0001a05 | 7877 | { |
03aaa593 BW |
7878 | if (target_size <= 4) |
7879 | return 2; | |
7880 | assert (target_size == 8); | |
7881 | return 3; | |
e0001a05 NC |
7882 | } |
7883 | ||
7884 | ||
d77b99c9 | 7885 | static int |
7fa3d080 BW |
7886 | get_text_align_max_fill_size (int align_pow, |
7887 | bfd_boolean use_nops, | |
7888 | bfd_boolean use_no_density) | |
e0001a05 NC |
7889 | { |
7890 | if (!use_nops) | |
7891 | return (1 << align_pow); | |
7892 | if (use_no_density) | |
7893 | return 3 * (1 << align_pow); | |
7894 | ||
7895 | return 1 + (1 << align_pow); | |
7896 | } | |
7897 | ||
7898 | ||
d77b99c9 BW |
7899 | /* Calculate the minimum bytes of fill needed at "address" to align a |
7900 | target instruction of size "target_size" so that it does not cross a | |
7901 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
7902 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
7903 | be filled by NOP instructions. */ | |
e0001a05 | 7904 | |
d77b99c9 | 7905 | static int |
7fa3d080 BW |
7906 | get_text_align_fill_size (addressT address, |
7907 | int align_pow, | |
7908 | int target_size, | |
7909 | bfd_boolean use_nops, | |
7910 | bfd_boolean use_no_density) | |
e0001a05 | 7911 | { |
d77b99c9 BW |
7912 | addressT alignment, fill, fill_limit, fill_step; |
7913 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 7914 | |
d77b99c9 BW |
7915 | alignment = (1 << align_pow); |
7916 | assert (target_size > 0 && alignment >= (addressT) target_size); | |
c138bc38 | 7917 | |
e0001a05 NC |
7918 | if (!use_nops) |
7919 | { | |
d77b99c9 BW |
7920 | fill_limit = alignment; |
7921 | fill_step = 1; | |
e0001a05 | 7922 | } |
d77b99c9 | 7923 | else if (!use_no_density) |
e0001a05 | 7924 | { |
d77b99c9 BW |
7925 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
7926 | fill_limit = alignment * 2; | |
7927 | fill_step = 1; | |
7928 | skip_one = TRUE; | |
e0001a05 NC |
7929 | } |
7930 | else | |
7931 | { | |
d77b99c9 BW |
7932 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
7933 | fill_limit = alignment * 3; | |
7934 | fill_step = 3; | |
7935 | } | |
e0001a05 | 7936 | |
d77b99c9 BW |
7937 | /* Try all fill sizes until finding one that works. */ |
7938 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
7939 | { | |
7940 | if (skip_one && fill == 1) | |
7941 | continue; | |
7942 | if ((address + fill) >> align_pow | |
7943 | == (address + fill + target_size - 1) >> align_pow) | |
7944 | return fill; | |
e0001a05 NC |
7945 | } |
7946 | assert (0); | |
7947 | return 0; | |
7948 | } | |
7949 | ||
7950 | ||
664df4e4 BW |
7951 | static int |
7952 | branch_align_power (segT sec) | |
7953 | { | |
7954 | /* If the Xtensa processor has a fetch width of 8 bytes, and the section | |
7955 | is aligned to at least an 8-byte boundary, then a branch target need | |
7956 | only fit within an 8-byte aligned block of memory to avoid a stall. | |
7957 | Otherwise, try to fit branch targets within 4-byte aligned blocks | |
7958 | (which may be insufficient, e.g., if the section has no alignment, but | |
7959 | it's good enough). */ | |
7960 | if (xtensa_fetch_width == 8) | |
7961 | { | |
7962 | if (get_recorded_alignment (sec) >= 3) | |
7963 | return 3; | |
7964 | } | |
7965 | else | |
7966 | assert (xtensa_fetch_width == 4); | |
7967 | ||
7968 | return 2; | |
7969 | } | |
7970 | ||
7971 | ||
e0001a05 NC |
7972 | /* This will assert if it is not possible. */ |
7973 | ||
d77b99c9 BW |
7974 | static int |
7975 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 7976 | { |
d77b99c9 BW |
7977 | int count = 0; |
7978 | ||
e0001a05 NC |
7979 | if (use_no_density) |
7980 | { | |
7981 | assert (fill_size % 3 == 0); | |
7982 | return (fill_size / 3); | |
7983 | } | |
7984 | ||
7985 | assert (fill_size != 1); /* Bad argument. */ | |
7986 | ||
7987 | while (fill_size > 1) | |
7988 | { | |
d77b99c9 | 7989 | int insn_size = 3; |
e0001a05 NC |
7990 | if (fill_size == 2 || fill_size == 4) |
7991 | insn_size = 2; | |
7992 | fill_size -= insn_size; | |
7993 | count++; | |
7994 | } | |
7995 | assert (fill_size != 1); /* Bad algorithm. */ | |
7996 | return count; | |
7997 | } | |
7998 | ||
7999 | ||
d77b99c9 BW |
8000 | static int |
8001 | get_text_align_nth_nop_size (offsetT fill_size, | |
8002 | int n, | |
7fa3d080 | 8003 | bfd_boolean use_no_density) |
e0001a05 | 8004 | { |
d77b99c9 | 8005 | int count = 0; |
e0001a05 NC |
8006 | |
8007 | if (use_no_density) | |
8008 | return 3; | |
8009 | ||
d77b99c9 BW |
8010 | assert (fill_size != 1); /* Bad argument. */ |
8011 | ||
e0001a05 NC |
8012 | while (fill_size > 1) |
8013 | { | |
d77b99c9 | 8014 | int insn_size = 3; |
e0001a05 NC |
8015 | if (fill_size == 2 || fill_size == 4) |
8016 | insn_size = 2; | |
8017 | fill_size -= insn_size; | |
8018 | count++; | |
8019 | if (n + 1 == count) | |
8020 | return insn_size; | |
8021 | } | |
8022 | assert (0); | |
8023 | return 0; | |
8024 | } | |
8025 | ||
8026 | ||
8027 | /* For the given fragment, find the appropriate address | |
8028 | for it to begin at if we are using NOPs to align it. */ | |
8029 | ||
8030 | static addressT | |
7fa3d080 | 8031 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 8032 | { |
43cd72b9 BW |
8033 | /* The rule is: get next fragment's FIRST instruction. Find |
8034 | the smallest number of bytes that need to be added to | |
8035 | ensure that the next fragment's FIRST instruction will fit | |
8036 | in a single word. | |
c138bc38 | 8037 | |
43cd72b9 BW |
8038 | E.G., 2 bytes : 0, 1, 2 mod 4 |
8039 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 8040 | |
43cd72b9 BW |
8041 | If the FIRST instruction MIGHT be relaxed, |
8042 | assume that it will become a 3-byte instruction. | |
c138bc38 | 8043 | |
43cd72b9 BW |
8044 | Note again here that LOOP instructions are not bundleable, |
8045 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 8046 | |
d77b99c9 | 8047 | int fill_size = 0; |
43cd72b9 BW |
8048 | int first_insn_size; |
8049 | int loop_insn_size; | |
8050 | addressT pre_opcode_bytes; | |
d77b99c9 | 8051 | int align_power; |
43cd72b9 BW |
8052 | fragS *first_insn; |
8053 | xtensa_opcode opcode; | |
8054 | bfd_boolean is_loop; | |
e0001a05 | 8055 | |
43cd72b9 BW |
8056 | assert (fragP->fr_type == rs_machine_dependent); |
8057 | assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 8058 | |
43cd72b9 BW |
8059 | /* Find the loop frag. */ |
8060 | first_insn = next_non_empty_frag (fragP); | |
8061 | /* Now find the first insn frag. */ | |
8062 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 8063 | |
43cd72b9 BW |
8064 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
8065 | assert (is_loop); | |
8066 | loop_insn_size = xg_get_single_size (opcode); | |
e0001a05 | 8067 | |
43cd72b9 BW |
8068 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
8069 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 8070 | |
43cd72b9 BW |
8071 | /* For loops, the alignment depends on the size of the |
8072 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 8073 | |
43cd72b9 | 8074 | if (first_insn == NULL) |
03aaa593 BW |
8075 | first_insn_size = xtensa_fetch_width; |
8076 | else | |
8077 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 8078 | |
43cd72b9 | 8079 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
8080 | align_power = get_text_align_power (first_insn_size); |
8081 | record_alignment (now_seg, align_power); | |
c138bc38 | 8082 | |
43cd72b9 | 8083 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
8084 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
8085 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
8086 | |
8087 | return address + fill_size; | |
8088 | } | |
8089 | ||
8090 | ||
43cd72b9 BW |
8091 | /* 3 mechanisms for relaxing an alignment: |
8092 | ||
8093 | Align to a power of 2. | |
8094 | Align so the next fragment's instruction does not cross a word boundary. | |
8095 | Align the current instruction so that if the next instruction | |
8096 | were 3 bytes, it would not cross a word boundary. | |
8097 | ||
e0001a05 NC |
8098 | We can align with: |
8099 | ||
43cd72b9 BW |
8100 | zeros - This is easy; always insert zeros. |
8101 | nops - 3-byte and 2-byte instructions | |
8102 | 2 - 2-byte nop | |
8103 | 3 - 3-byte nop | |
8104 | 4 - 2 2-byte nops | |
8105 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
8106 | widening - widen previous instructions. */ |
8107 | ||
d77b99c9 BW |
8108 | static offsetT |
8109 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 8110 | { |
43cd72b9 BW |
8111 | addressT target_address, loop_insn_offset; |
8112 | int target_size; | |
8113 | xtensa_opcode loop_opcode; | |
8114 | bfd_boolean is_loop; | |
d77b99c9 BW |
8115 | int align_power; |
8116 | offsetT opt_diff; | |
5f9084e9 | 8117 | offsetT branch_align; |
e0001a05 | 8118 | |
43cd72b9 BW |
8119 | assert (fragP->fr_type == rs_machine_dependent); |
8120 | switch (fragP->fr_subtype) | |
e0001a05 | 8121 | { |
43cd72b9 BW |
8122 | case RELAX_DESIRE_ALIGN: |
8123 | target_size = next_frag_format_size (fragP); | |
8124 | if (target_size == XTENSA_UNDEFINED) | |
8125 | target_size = 3; | |
664df4e4 BW |
8126 | align_power = branch_align_power (now_seg); |
8127 | branch_align = 1 << align_power; | |
0e5cd789 BW |
8128 | /* Don't count on the section alignment being as large as the target. */ |
8129 | if (target_size > branch_align) | |
8130 | target_size = branch_align; | |
d77b99c9 | 8131 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
8132 | target_size, FALSE, FALSE); |
8133 | ||
664df4e4 BW |
8134 | *max_diff = (opt_diff + branch_align |
8135 | - (target_size + ((address + opt_diff) % branch_align))); | |
43cd72b9 BW |
8136 | assert (*max_diff >= opt_diff); |
8137 | return opt_diff; | |
e0001a05 | 8138 | |
43cd72b9 | 8139 | case RELAX_ALIGN_NEXT_OPCODE: |
03aaa593 | 8140 | target_size = get_loop_align_size (next_frag_format_size (fragP)); |
43cd72b9 BW |
8141 | loop_insn_offset = 0; |
8142 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
8143 | assert (is_loop); | |
8144 | ||
8145 | /* If the loop has been expanded then the LOOP instruction | |
8146 | could be at an offset from this fragment. */ | |
8147 | if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0] | |
8148 | != RELAX_IMMED) | |
8149 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); | |
8150 | ||
43cd72b9 BW |
8151 | /* In an ideal world, which is what we are shooting for here, |
8152 | we wouldn't need to use any NOPs immediately prior to the | |
8153 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
8154 | will call get_noop_aligned_address. */ | |
8155 | target_address = | |
8156 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
d77b99c9 BW |
8157 | align_power = get_text_align_power (target_size), |
8158 | opt_diff = get_text_align_fill_size (target_address, align_power, | |
43cd72b9 BW |
8159 | target_size, FALSE, FALSE); |
8160 | ||
8161 | *max_diff = xtensa_fetch_width | |
8162 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
8163 | - target_size + opt_diff; | |
8164 | assert (*max_diff >= opt_diff); | |
8165 | return opt_diff; | |
e0001a05 | 8166 | |
43cd72b9 BW |
8167 | default: |
8168 | break; | |
e0001a05 | 8169 | } |
43cd72b9 BW |
8170 | assert (0); |
8171 | return 0; | |
e0001a05 NC |
8172 | } |
8173 | ||
8174 | \f | |
8175 | /* md_relax_frag Hook and Helper Functions. */ | |
8176 | ||
7fa3d080 BW |
8177 | static long relax_frag_loop_align (fragS *, long); |
8178 | static long relax_frag_for_align (fragS *, long); | |
8179 | static long relax_frag_immed | |
8180 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
8181 | ||
8182 | ||
e0001a05 NC |
8183 | /* Return the number of bytes added to this fragment, given that the |
8184 | input has been stretched already by "stretch". */ | |
8185 | ||
8186 | long | |
7fa3d080 | 8187 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 8188 | { |
43cd72b9 | 8189 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
8190 | int unreported = fragP->tc_frag_data.unreported_expansion; |
8191 | long new_stretch = 0; | |
8192 | char *file_name; | |
d77b99c9 BW |
8193 | unsigned line; |
8194 | int lit_size; | |
43cd72b9 BW |
8195 | static xtensa_insnbuf vbuf = NULL; |
8196 | int slot, num_slots; | |
8197 | xtensa_format fmt; | |
e0001a05 NC |
8198 | |
8199 | as_where (&file_name, &line); | |
8200 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8201 | ||
8202 | fragP->tc_frag_data.unreported_expansion = 0; | |
8203 | ||
8204 | switch (fragP->fr_subtype) | |
8205 | { | |
8206 | case RELAX_ALIGN_NEXT_OPCODE: | |
8207 | /* Always convert. */ | |
43cd72b9 BW |
8208 | if (fragP->tc_frag_data.relax_seen) |
8209 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
8210 | break; |
8211 | ||
8212 | case RELAX_LOOP_END: | |
8213 | /* Do nothing. */ | |
8214 | break; | |
8215 | ||
8216 | case RELAX_LOOP_END_ADD_NOP: | |
8217 | /* Add a NOP and switch to .fill 0. */ | |
8218 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 8219 | frag_wane (fragP); |
e0001a05 NC |
8220 | break; |
8221 | ||
8222 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 8223 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
8224 | it or not. */ |
8225 | break; | |
8226 | ||
8227 | case RELAX_LITERAL: | |
8228 | case RELAX_LITERAL_FINAL: | |
8229 | return 0; | |
8230 | ||
8231 | case RELAX_LITERAL_NR: | |
8232 | lit_size = 4; | |
8233 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
8234 | assert (unreported == lit_size); | |
8235 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); | |
8236 | fragP->fr_var -= lit_size; | |
8237 | fragP->fr_fix += lit_size; | |
8238 | new_stretch = 4; | |
8239 | break; | |
8240 | ||
43cd72b9 BW |
8241 | case RELAX_SLOTS: |
8242 | if (vbuf == NULL) | |
8243 | vbuf = xtensa_insnbuf_alloc (isa); | |
8244 | ||
d77b99c9 BW |
8245 | xtensa_insnbuf_from_chars |
8246 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
8247 | fmt = xtensa_format_decode (isa, vbuf); |
8248 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 8249 | |
43cd72b9 BW |
8250 | for (slot = 0; slot < num_slots; slot++) |
8251 | { | |
8252 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
8253 | { | |
8254 | case RELAX_NARROW: | |
8255 | if (fragP->tc_frag_data.relax_seen) | |
8256 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8257 | break; | |
8258 | ||
8259 | case RELAX_IMMED: | |
8260 | case RELAX_IMMED_STEP1: | |
8261 | case RELAX_IMMED_STEP2: | |
8262 | /* Place the immediate. */ | |
8263 | new_stretch += relax_frag_immed | |
8264 | (now_seg, fragP, stretch, | |
8265 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8266 | fmt, slot, stretched_p, FALSE); | |
8267 | break; | |
8268 | ||
8269 | default: | |
8270 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
8271 | break; | |
8272 | } | |
8273 | } | |
e0001a05 NC |
8274 | break; |
8275 | ||
8276 | case RELAX_LITERAL_POOL_BEGIN: | |
8277 | case RELAX_LITERAL_POOL_END: | |
43cd72b9 BW |
8278 | case RELAX_MAYBE_UNREACHABLE: |
8279 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
8280 | /* No relaxation required. */ |
8281 | break; | |
8282 | ||
43cd72b9 BW |
8283 | case RELAX_FILL_NOP: |
8284 | case RELAX_UNREACHABLE: | |
8285 | if (fragP->tc_frag_data.relax_seen) | |
8286 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8287 | break; | |
8288 | ||
e0001a05 NC |
8289 | default: |
8290 | as_bad (_("bad relaxation state")); | |
8291 | } | |
8292 | ||
43cd72b9 | 8293 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 8294 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
8295 | { |
8296 | fragP->tc_frag_data.relax_seen = TRUE; | |
8297 | *stretched_p = 1; | |
8298 | } | |
8299 | ||
e0001a05 NC |
8300 | new_logical_line (file_name, line); |
8301 | return new_stretch; | |
8302 | } | |
8303 | ||
8304 | ||
8305 | static long | |
7fa3d080 | 8306 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
8307 | { |
8308 | addressT old_address, old_next_address, old_size; | |
8309 | addressT new_address, new_next_address, new_size; | |
8310 | addressT growth; | |
8311 | ||
43cd72b9 BW |
8312 | /* All the frags with relax_frag_for_alignment prior to this one in the |
8313 | section have been done, hopefully eliminating the need for a NOP here. | |
8314 | But, this will put it in if necessary. */ | |
e0001a05 NC |
8315 | |
8316 | /* Calculate the old address of this fragment and the next fragment. */ | |
8317 | old_address = fragP->fr_address - stretch; | |
8318 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 8319 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
8320 | old_size = old_next_address - old_address; |
8321 | ||
8322 | /* Calculate the new address of this fragment and the next fragment. */ | |
8323 | new_address = fragP->fr_address; | |
8324 | new_next_address = | |
8325 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
8326 | new_size = new_next_address - new_address; | |
8327 | ||
8328 | growth = new_size - old_size; | |
8329 | ||
8330 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 8331 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
8332 | return growth; |
8333 | } | |
8334 | ||
8335 | ||
43cd72b9 | 8336 | /* Add a NOP instruction. */ |
e0001a05 NC |
8337 | |
8338 | static long | |
7fa3d080 | 8339 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 8340 | { |
e0001a05 | 8341 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
8342 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
8343 | assemble_nop (length, nop_buf); | |
e0001a05 | 8344 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 8345 | |
e0001a05 NC |
8346 | if (fragP->fr_var < length) |
8347 | { | |
dd49a749 | 8348 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
8349 | return 0; |
8350 | } | |
8351 | ||
8352 | fragP->fr_fix += length; | |
8353 | fragP->fr_var -= length; | |
e0001a05 NC |
8354 | return length; |
8355 | } | |
8356 | ||
8357 | ||
7fa3d080 BW |
8358 | static long future_alignment_required (fragS *, long); |
8359 | ||
e0001a05 | 8360 | static long |
7fa3d080 | 8361 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 8362 | { |
43cd72b9 BW |
8363 | /* Overview of the relaxation procedure for alignment: |
8364 | We can widen with NOPs or by widening instructions or by filling | |
8365 | bytes after jump instructions. Find the opportune places and widen | |
8366 | them if necessary. */ | |
8367 | ||
8368 | long stretch_me; | |
8369 | long diff; | |
e0001a05 | 8370 | |
43cd72b9 BW |
8371 | assert (fragP->fr_subtype == RELAX_FILL_NOP |
8372 | || fragP->fr_subtype == RELAX_UNREACHABLE | |
8373 | || (fragP->fr_subtype == RELAX_SLOTS | |
8374 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
8375 | ||
8376 | stretch_me = future_alignment_required (fragP, stretch); | |
8377 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
8378 | if (diff == 0) | |
8379 | return 0; | |
e0001a05 | 8380 | |
43cd72b9 | 8381 | if (diff < 0) |
e0001a05 | 8382 | { |
43cd72b9 BW |
8383 | /* We expanded on a previous pass. Can we shrink now? */ |
8384 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
8385 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 8386 | { |
43cd72b9 BW |
8387 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
8388 | return -shrink; | |
e0001a05 NC |
8389 | } |
8390 | return 0; | |
8391 | } | |
8392 | ||
43cd72b9 BW |
8393 | /* Below here, diff > 0. */ |
8394 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 8395 | |
43cd72b9 | 8396 | return diff; |
e0001a05 NC |
8397 | } |
8398 | ||
8399 | ||
43cd72b9 BW |
8400 | /* Return the address of the next frag that should be aligned. |
8401 | ||
8402 | By "address" we mean the address it _would_ be at if there | |
8403 | is no action taken to align it between here and the target frag. | |
8404 | In other words, if no narrows and no fill nops are used between | |
8405 | here and the frag to align, _even_if_ some of the frags we use | |
8406 | to align targets have already expanded on a previous relaxation | |
8407 | pass. | |
8408 | ||
8409 | Also, count each frag that may be used to help align the target. | |
8410 | ||
8411 | Return 0 if there are no frags left in the chain that need to be | |
8412 | aligned. */ | |
8413 | ||
8414 | static addressT | |
7fa3d080 BW |
8415 | find_address_of_next_align_frag (fragS **fragPP, |
8416 | int *wide_nops, | |
8417 | int *narrow_nops, | |
8418 | int *widens, | |
8419 | bfd_boolean *paddable) | |
e0001a05 | 8420 | { |
43cd72b9 BW |
8421 | fragS *fragP = *fragPP; |
8422 | addressT address = fragP->fr_address; | |
8423 | ||
8424 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
8425 | |
8426 | while (fragP) | |
8427 | { | |
8428 | /* Limit this to a small search. */ | |
b5e4a23d | 8429 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
8430 | { |
8431 | *fragPP = fragP; | |
8432 | return 0; | |
8433 | } | |
e0001a05 NC |
8434 | address += fragP->fr_fix; |
8435 | ||
43cd72b9 BW |
8436 | if (fragP->fr_type == rs_fill) |
8437 | address += fragP->fr_offset * fragP->fr_var; | |
8438 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 8439 | { |
e0001a05 NC |
8440 | switch (fragP->fr_subtype) |
8441 | { | |
43cd72b9 BW |
8442 | case RELAX_UNREACHABLE: |
8443 | *paddable = TRUE; | |
8444 | break; | |
8445 | ||
8446 | case RELAX_FILL_NOP: | |
8447 | (*wide_nops)++; | |
8448 | if (!fragP->tc_frag_data.is_no_density) | |
8449 | (*narrow_nops)++; | |
8450 | break; | |
8451 | ||
8452 | case RELAX_SLOTS: | |
8453 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8454 | { | |
8455 | (*widens)++; | |
8456 | break; | |
8457 | } | |
34e41783 | 8458 | address += total_frag_text_expansion (fragP);; |
e0001a05 NC |
8459 | break; |
8460 | ||
8461 | case RELAX_IMMED: | |
43cd72b9 | 8462 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
8463 | break; |
8464 | ||
8465 | case RELAX_ALIGN_NEXT_OPCODE: | |
8466 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
8467 | *fragPP = fragP; |
8468 | return address; | |
8469 | ||
8470 | case RELAX_MAYBE_UNREACHABLE: | |
8471 | case RELAX_MAYBE_DESIRE_ALIGN: | |
8472 | /* Do nothing. */ | |
e0001a05 NC |
8473 | break; |
8474 | ||
8475 | default: | |
43cd72b9 BW |
8476 | /* Just punt if we don't know the type. */ |
8477 | *fragPP = fragP; | |
8478 | return 0; | |
e0001a05 | 8479 | } |
43cd72b9 | 8480 | } |
c138bc38 | 8481 | else |
43cd72b9 BW |
8482 | { |
8483 | /* Just punt if we don't know the type. */ | |
8484 | *fragPP = fragP; | |
8485 | return 0; | |
8486 | } | |
8487 | fragP = fragP->fr_next; | |
8488 | } | |
8489 | ||
8490 | *fragPP = fragP; | |
8491 | return 0; | |
8492 | } | |
8493 | ||
8494 | ||
7fa3d080 BW |
8495 | static long bytes_to_stretch (fragS *, int, int, int, int); |
8496 | ||
43cd72b9 | 8497 | static long |
7fa3d080 | 8498 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
8499 | { |
8500 | fragS *this_frag = fragP; | |
8501 | long address; | |
8502 | int num_widens = 0; | |
8503 | int wide_nops = 0; | |
8504 | int narrow_nops = 0; | |
8505 | bfd_boolean paddable = FALSE; | |
8506 | offsetT local_opt_diff; | |
8507 | offsetT opt_diff; | |
8508 | offsetT max_diff; | |
8509 | int stretch_amount = 0; | |
8510 | int local_stretch_amount; | |
8511 | int global_stretch_amount; | |
8512 | ||
7fa3d080 BW |
8513 | address = find_address_of_next_align_frag |
8514 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 8515 | |
b5e4a23d BW |
8516 | if (!address) |
8517 | { | |
8518 | if (this_frag->tc_frag_data.is_aligning_branch) | |
8519 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
8520 | else | |
8521 | frag_wane (this_frag); | |
8522 | } | |
8523 | else | |
43cd72b9 BW |
8524 | { |
8525 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
8526 | opt_diff = local_opt_diff; | |
8527 | assert (opt_diff >= 0); | |
8528 | assert (max_diff >= opt_diff); | |
c138bc38 | 8529 | if (max_diff == 0) |
43cd72b9 | 8530 | return 0; |
d2a033cd | 8531 | |
43cd72b9 BW |
8532 | if (fragP) |
8533 | fragP = fragP->fr_next; | |
8534 | ||
8535 | while (fragP && opt_diff < max_diff && address) | |
8536 | { | |
8537 | /* We only use these to determine if we can exit early | |
c138bc38 | 8538 | because there will be plenty of ways to align future |
43cd72b9 | 8539 | align frags. */ |
d77b99c9 | 8540 | int glob_widens = 0; |
43cd72b9 BW |
8541 | int dnn = 0; |
8542 | int dw = 0; | |
8543 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
8544 | address = find_address_of_next_align_frag |
8545 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 8546 | /* If there is a padable portion, then skip. */ |
664df4e4 | 8547 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 8548 | address = 0; |
43cd72b9 | 8549 | |
c138bc38 | 8550 | if (address) |
43cd72b9 BW |
8551 | { |
8552 | offsetT next_m_diff; | |
8553 | offsetT next_o_diff; | |
8554 | ||
8555 | /* Downrange frags haven't had stretch added to them yet. */ | |
8556 | address += stretch; | |
8557 | ||
8558 | /* The address also includes any text expansion from this | |
8559 | frag in a previous pass, but we don't want that. */ | |
8560 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
8561 | ||
8562 | /* Assume we are going to move at least opt_diff. In | |
8563 | reality, we might not be able to, but assuming that | |
8564 | we will helps catch cases where moving opt_diff pushes | |
8565 | the next target from aligned to unaligned. */ | |
8566 | address += opt_diff; | |
8567 | ||
8568 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
8569 | ||
8570 | /* Now cleanup for the adjustments to address. */ | |
8571 | next_o_diff += opt_diff; | |
8572 | next_m_diff += opt_diff; | |
8573 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
8574 | opt_diff = next_o_diff; | |
8575 | if (next_m_diff < max_diff) | |
8576 | max_diff = next_m_diff; | |
8577 | fragP = fragP->fr_next; | |
8578 | } | |
8579 | } | |
d2a033cd | 8580 | |
43cd72b9 BW |
8581 | /* If there are enough wideners in between, do it. */ |
8582 | if (paddable) | |
8583 | { | |
8584 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
8585 | { | |
8586 | assert (opt_diff <= UNREACHABLE_MAX_WIDTH); | |
8587 | return opt_diff; | |
8588 | } | |
8589 | return 0; | |
8590 | } | |
c138bc38 | 8591 | local_stretch_amount |
43cd72b9 BW |
8592 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
8593 | num_widens, local_opt_diff); | |
c138bc38 BW |
8594 | global_stretch_amount |
8595 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 8596 | num_widens, opt_diff); |
c138bc38 BW |
8597 | /* If the condition below is true, then the frag couldn't |
8598 | stretch the correct amount for the global case, so we just | |
8599 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
8600 | the correct alignment in the global case. */ |
8601 | if (global_stretch_amount < local_stretch_amount) | |
8602 | stretch_amount = local_stretch_amount; | |
8603 | else | |
8604 | stretch_amount = global_stretch_amount; | |
d2a033cd | 8605 | |
43cd72b9 BW |
8606 | if (this_frag->fr_subtype == RELAX_SLOTS |
8607 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8608 | assert (stretch_amount <= 1); | |
8609 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8610 | { | |
8611 | if (this_frag->tc_frag_data.is_no_density) | |
8612 | assert (stretch_amount == 3 || stretch_amount == 0); | |
8613 | else | |
8614 | assert (stretch_amount <= 3); | |
8615 | } | |
8616 | } | |
8617 | return stretch_amount; | |
8618 | } | |
8619 | ||
8620 | ||
8621 | /* The idea: widen everything you can to get a target or loop aligned, | |
8622 | then start using NOPs. | |
8623 | ||
8624 | When we must have a NOP, here is a table of how we decide | |
8625 | (so you don't have to fight through the control flow below): | |
8626 | ||
8627 | wide_nops = the number of wide NOPs available for aligning | |
8628 | narrow_nops = the number of narrow NOPs available for aligning | |
8629 | (a subset of wide_nops) | |
8630 | widens = the number of narrow instructions that should be widened | |
8631 | ||
8632 | Desired wide narrow | |
8633 | Diff nop nop widens | |
8634 | 1 0 0 1 | |
8635 | 2 0 1 0 | |
8636 | 3a 1 0 0 | |
8637 | b 0 1 1 (case 3a makes this case unnecessary) | |
8638 | 4a 1 0 1 | |
8639 | b 0 2 0 | |
8640 | c 0 1 2 (case 4a makes this case unnecessary) | |
8641 | 5a 1 0 2 | |
8642 | b 1 1 0 | |
8643 | c 0 2 1 (case 5b makes this case unnecessary) | |
8644 | 6a 2 0 0 | |
8645 | b 1 0 3 | |
8646 | c 0 1 4 (case 6b makes this case unneccesary) | |
8647 | d 1 1 1 (case 6a makes this case unnecessary) | |
8648 | e 0 2 2 (case 6a makes this case unnecessary) | |
8649 | f 0 3 0 (case 6a makes this case unnecessary) | |
8650 | 7a 1 0 4 | |
8651 | b 2 0 1 | |
8652 | c 1 1 2 (case 7b makes this case unnecessary) | |
8653 | d 0 1 5 (case 7a makes this case unnecessary) | |
8654 | e 0 2 3 (case 7b makes this case unnecessary) | |
8655 | f 0 3 1 (case 7b makes this case unnecessary) | |
8656 | g 1 2 1 (case 7b makes this case unnecessary) | |
8657 | */ | |
8658 | ||
8659 | static long | |
7fa3d080 BW |
8660 | bytes_to_stretch (fragS *this_frag, |
8661 | int wide_nops, | |
8662 | int narrow_nops, | |
8663 | int num_widens, | |
8664 | int desired_diff) | |
43cd72b9 BW |
8665 | { |
8666 | int bytes_short = desired_diff - num_widens; | |
8667 | ||
8668 | assert (desired_diff >= 0 && desired_diff < 8); | |
8669 | if (desired_diff == 0) | |
8670 | return 0; | |
c138bc38 | 8671 | |
43cd72b9 | 8672 | assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 8673 | |
43cd72b9 BW |
8674 | /* Always prefer widening to NOP-filling. */ |
8675 | if (bytes_short < 0) | |
8676 | { | |
8677 | /* There are enough RELAX_NARROW frags after this one | |
8678 | to align the target without widening this frag in any way. */ | |
8679 | return 0; | |
8680 | } | |
c138bc38 | 8681 | |
43cd72b9 BW |
8682 | if (bytes_short == 0) |
8683 | { | |
8684 | /* Widen every narrow between here and the align target | |
8685 | and the align target will be properly aligned. */ | |
8686 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8687 | return 0; | |
8688 | else | |
8689 | return 1; | |
8690 | } | |
c138bc38 | 8691 | |
43cd72b9 BW |
8692 | /* From here we will need at least one NOP to get an alignment. |
8693 | However, we may not be able to align at all, in which case, | |
8694 | don't widen. */ | |
8695 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8696 | { | |
8697 | switch (desired_diff) | |
8698 | { | |
8699 | case 1: | |
8700 | return 0; | |
8701 | case 2: | |
8702 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1) | |
8703 | return 2; /* case 2 */ | |
8704 | return 0; | |
c138bc38 | 8705 | case 3: |
43cd72b9 BW |
8706 | if (wide_nops > 1) |
8707 | return 0; | |
8708 | else | |
8709 | return 3; /* case 3a */ | |
8710 | case 4: | |
8711 | if (num_widens >= 1 && wide_nops == 1) | |
8712 | return 3; /* case 4a */ | |
8713 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2) | |
8714 | return 2; /* case 4b */ | |
8715 | return 0; | |
8716 | case 5: | |
8717 | if (num_widens >= 2 && wide_nops == 1) | |
8718 | return 3; /* case 5a */ | |
c138bc38 | 8719 | /* We will need two nops. Are there enough nops |
43cd72b9 BW |
8720 | between here and the align target? */ |
8721 | if (wide_nops < 2 || narrow_nops == 0) | |
8722 | return 0; | |
8723 | /* Are there other nops closer that can serve instead? */ | |
8724 | if (wide_nops > 2 && narrow_nops > 1) | |
8725 | return 0; | |
8726 | /* Take the density one first, because there might not be | |
8727 | another density one available. */ | |
8728 | if (!this_frag->tc_frag_data.is_no_density) | |
8729 | return 2; /* case 5b narrow */ | |
8730 | else | |
8731 | return 3; /* case 5b wide */ | |
8732 | return 0; | |
8733 | case 6: | |
8734 | if (wide_nops == 2) | |
8735 | return 3; /* case 6a */ | |
8736 | else if (num_widens >= 3 && wide_nops == 1) | |
8737 | return 3; /* case 6b */ | |
8738 | return 0; | |
8739 | case 7: | |
8740 | if (wide_nops == 1 && num_widens >= 4) | |
8741 | return 3; /* case 7a */ | |
8742 | else if (wide_nops == 2 && num_widens >= 1) | |
8743 | return 3; /* case 7b */ | |
8744 | return 0; | |
e0001a05 | 8745 | default: |
43cd72b9 | 8746 | assert (0); |
e0001a05 | 8747 | } |
e0001a05 | 8748 | } |
43cd72b9 BW |
8749 | else |
8750 | { | |
c138bc38 | 8751 | /* We will need a NOP no matter what, but should we widen |
43cd72b9 | 8752 | this instruction to help? |
e0001a05 | 8753 | |
03aaa593 | 8754 | This is a RELAX_NARROW frag. */ |
43cd72b9 BW |
8755 | switch (desired_diff) |
8756 | { | |
8757 | case 1: | |
8758 | assert (0); | |
8759 | return 0; | |
8760 | case 2: | |
8761 | case 3: | |
8762 | return 0; | |
8763 | case 4: | |
8764 | if (wide_nops >= 1 && num_widens == 1) | |
8765 | return 1; /* case 4a */ | |
8766 | return 0; | |
8767 | case 5: | |
8768 | if (wide_nops >= 1 && num_widens == 2) | |
8769 | return 1; /* case 5a */ | |
8770 | return 0; | |
8771 | case 6: | |
8772 | if (wide_nops >= 2) | |
8773 | return 0; /* case 6a */ | |
8774 | else if (wide_nops >= 1 && num_widens == 3) | |
8775 | return 1; /* case 6b */ | |
8776 | return 0; | |
8777 | case 7: | |
8778 | if (wide_nops >= 1 && num_widens == 4) | |
8779 | return 1; /* case 7a */ | |
8780 | else if (wide_nops >= 2 && num_widens == 1) | |
8781 | return 1; /* case 7b */ | |
8782 | return 0; | |
8783 | default: | |
8784 | assert (0); | |
8785 | return 0; | |
8786 | } | |
8787 | } | |
8788 | assert (0); | |
8789 | return 0; | |
e0001a05 NC |
8790 | } |
8791 | ||
8792 | ||
8793 | static long | |
7fa3d080 BW |
8794 | relax_frag_immed (segT segP, |
8795 | fragS *fragP, | |
8796 | long stretch, | |
8797 | int min_steps, | |
8798 | xtensa_format fmt, | |
8799 | int slot, | |
8800 | int *stretched_p, | |
8801 | bfd_boolean estimate_only) | |
e0001a05 | 8802 | { |
43cd72b9 | 8803 | TInsn tinsn; |
e0001a05 NC |
8804 | int old_size; |
8805 | bfd_boolean negatable_branch = FALSE; | |
8806 | bfd_boolean branch_jmp_to_next = FALSE; | |
43cd72b9 BW |
8807 | bfd_boolean wide_insn = FALSE; |
8808 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
8809 | IStack istack; |
8810 | offsetT frag_offset; | |
8811 | int num_steps; | |
8812 | fragS *lit_fragP; | |
8813 | int num_text_bytes, num_literal_bytes; | |
43cd72b9 | 8814 | int literal_diff, total_text_diff, this_text_diff, first; |
e0001a05 NC |
8815 | |
8816 | assert (fragP->fr_opcode != NULL); | |
8817 | ||
b5e4a23d BW |
8818 | xg_clear_vinsn (&cur_vinsn); |
8819 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 8820 | if (cur_vinsn.num_slots > 1) |
43cd72b9 BW |
8821 | wide_insn = TRUE; |
8822 | ||
b5e4a23d | 8823 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 8824 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 8825 | |
43cd72b9 BW |
8826 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode)) |
8827 | return 0; | |
e0001a05 | 8828 | |
b08b5071 | 8829 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 8830 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 8831 | |
43cd72b9 | 8832 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 8833 | |
43cd72b9 | 8834 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
8835 | |
8836 | /* Special case: replace a branch to the next instruction with a NOP. | |
8837 | This is required to work around a hardware bug in T1040.0 and also | |
8838 | serves as an optimization. */ | |
8839 | ||
8840 | if (branch_jmp_to_next | |
8841 | && ((old_size == 2) || (old_size == 3)) | |
8842 | && !next_frag_is_loop_target (fragP)) | |
8843 | return 0; | |
8844 | ||
8845 | /* Here is the fun stuff: Get the immediate field from this | |
8846 | instruction. If it fits, we are done. If not, find the next | |
8847 | instruction sequence that fits. */ | |
8848 | ||
8849 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
8850 | istack_init (&istack); | |
43cd72b9 | 8851 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 NC |
8852 | min_steps, stretch); |
8853 | if (num_steps < min_steps) | |
8854 | { | |
8855 | as_fatal (_("internal error: relaxation failed")); | |
8856 | return 0; | |
8857 | } | |
8858 | ||
8859 | if (num_steps > RELAX_IMMED_MAXSTEPS) | |
8860 | { | |
8861 | as_fatal (_("internal error: relaxation requires too many steps")); | |
8862 | return 0; | |
8863 | } | |
8864 | ||
43cd72b9 | 8865 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
8866 | |
8867 | /* Figure out the number of bytes needed. */ | |
8868 | lit_fragP = 0; | |
e0001a05 | 8869 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
43cd72b9 BW |
8870 | literal_diff = |
8871 | num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
8872 | first = 0; | |
8873 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
8874 | first++; | |
8875 | num_text_bytes = get_num_stack_text_bytes (&istack); | |
8876 | if (wide_insn) | |
8877 | { | |
8878 | num_text_bytes += old_size; | |
8879 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
8880 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
8881 | } | |
8882 | total_text_diff = num_text_bytes - old_size; | |
8883 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
8884 | |
8885 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
43cd72b9 BW |
8886 | assert (num_text_bytes >= 0); |
8887 | assert (literal_diff >= 0); | |
8888 | assert (total_text_diff >= 0); | |
e0001a05 | 8889 | |
43cd72b9 BW |
8890 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
8891 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
8892 | assert (fragP->tc_frag_data.text_expansion[slot] >= 0); | |
8893 | assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
8894 | |
8895 | /* Find the associated expandable literal for this. */ | |
8896 | if (literal_diff != 0) | |
8897 | { | |
43cd72b9 | 8898 | lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
8899 | if (lit_fragP) |
8900 | { | |
8901 | assert (literal_diff == 4); | |
8902 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; | |
8903 | ||
8904 | /* We expect that the literal section state has NOT been | |
8905 | modified yet. */ | |
8906 | assert (lit_fragP->fr_type == rs_machine_dependent | |
8907 | && lit_fragP->fr_subtype == RELAX_LITERAL); | |
8908 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
8909 | ||
8910 | /* We need to mark this section for another iteration | |
8911 | of relaxation. */ | |
8912 | (*stretched_p)++; | |
8913 | } | |
8914 | } | |
8915 | ||
43cd72b9 | 8916 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 8917 | update_next_frag_state (fragP); |
e0001a05 | 8918 | |
43cd72b9 | 8919 | return this_text_diff; |
e0001a05 NC |
8920 | } |
8921 | ||
8922 | \f | |
8923 | /* md_convert_frag Hook and Helper Functions. */ | |
8924 | ||
7fa3d080 BW |
8925 | static void convert_frag_align_next_opcode (fragS *); |
8926 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
8927 | static void convert_frag_fill_nop (fragS *); | |
8928 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
8929 | ||
e0001a05 | 8930 | void |
7fa3d080 | 8931 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 8932 | { |
43cd72b9 BW |
8933 | static xtensa_insnbuf vbuf = NULL; |
8934 | xtensa_isa isa = xtensa_default_isa; | |
8935 | int slot; | |
8936 | int num_slots; | |
8937 | xtensa_format fmt; | |
e0001a05 | 8938 | char *file_name; |
d77b99c9 | 8939 | unsigned line; |
e0001a05 NC |
8940 | |
8941 | as_where (&file_name, &line); | |
8942 | new_logical_line (fragp->fr_file, fragp->fr_line); | |
8943 | ||
8944 | switch (fragp->fr_subtype) | |
8945 | { | |
8946 | case RELAX_ALIGN_NEXT_OPCODE: | |
8947 | /* Always convert. */ | |
8948 | convert_frag_align_next_opcode (fragp); | |
8949 | break; | |
8950 | ||
8951 | case RELAX_DESIRE_ALIGN: | |
8952 | /* Do nothing. If not aligned already, too bad. */ | |
8953 | break; | |
8954 | ||
43cd72b9 BW |
8955 | case RELAX_LITERAL: |
8956 | case RELAX_LITERAL_FINAL: | |
8957 | break; | |
8958 | ||
8959 | case RELAX_SLOTS: | |
8960 | if (vbuf == NULL) | |
8961 | vbuf = xtensa_insnbuf_alloc (isa); | |
8962 | ||
d77b99c9 BW |
8963 | xtensa_insnbuf_from_chars |
8964 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
8965 | fmt = xtensa_format_decode (isa, vbuf); |
8966 | num_slots = xtensa_format_num_slots (isa, fmt); | |
8967 | ||
8968 | for (slot = 0; slot < num_slots; slot++) | |
8969 | { | |
8970 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
8971 | { | |
8972 | case RELAX_NARROW: | |
8973 | convert_frag_narrow (sec, fragp, fmt, slot); | |
8974 | break; | |
8975 | ||
8976 | case RELAX_IMMED: | |
8977 | case RELAX_IMMED_STEP1: | |
8978 | case RELAX_IMMED_STEP2: | |
8979 | /* Place the immediate. */ | |
8980 | convert_frag_immed | |
8981 | (sec, fragp, | |
8982 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8983 | fmt, slot); | |
8984 | break; | |
8985 | ||
8986 | default: | |
8987 | /* This is OK because some slots could have | |
8988 | relaxations and others have none. */ | |
8989 | break; | |
8990 | } | |
8991 | } | |
8992 | break; | |
8993 | ||
8994 | case RELAX_UNREACHABLE: | |
8995 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
8996 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
8997 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
8998 | frag_wane (fragp); | |
e0001a05 NC |
8999 | break; |
9000 | ||
43cd72b9 BW |
9001 | case RELAX_MAYBE_UNREACHABLE: |
9002 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9003 | frag_wane (fragp); | |
e0001a05 NC |
9004 | break; |
9005 | ||
43cd72b9 BW |
9006 | case RELAX_FILL_NOP: |
9007 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
9008 | break; |
9009 | ||
9010 | case RELAX_LITERAL_NR: | |
9011 | if (use_literal_section) | |
9012 | { | |
9013 | /* This should have been handled during relaxation. When | |
9014 | relaxing a code segment, literals sometimes need to be | |
9015 | added to the corresponding literal segment. If that | |
9016 | literal segment has already been relaxed, then we end up | |
9017 | in this situation. Marking the literal segments as data | |
9018 | would make this happen less often (since GAS always relaxes | |
9019 | code before data), but we could still get into trouble if | |
9020 | there are instructions in a segment that is not marked as | |
9021 | containing code. Until we can implement a better solution, | |
9022 | cheat and adjust the addresses of all the following frags. | |
9023 | This could break subsequent alignments, but the linker's | |
9024 | literal coalescing will do that anyway. */ | |
9025 | ||
9026 | fragS *f; | |
9027 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9028 | assert (fragp->tc_frag_data.unreported_expansion == 4); | |
9029 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); | |
9030 | fragp->fr_var -= 4; | |
9031 | fragp->fr_fix += 4; | |
9032 | for (f = fragp->fr_next; f; f = f->fr_next) | |
9033 | f->fr_address += 4; | |
9034 | } | |
9035 | else | |
9036 | as_bad (_("invalid relaxation fragment result")); | |
9037 | break; | |
9038 | } | |
9039 | ||
9040 | fragp->fr_var = 0; | |
9041 | new_logical_line (file_name, line); | |
9042 | } | |
9043 | ||
9044 | ||
7fa3d080 BW |
9045 | static void |
9046 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
9047 | { |
9048 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
9049 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
9050 | addressT aligned_address; | |
d77b99c9 BW |
9051 | offsetT fill_size; |
9052 | int nop, nop_count; | |
e0001a05 NC |
9053 | |
9054 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
9055 | fragp->fr_fix); | |
9056 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
9057 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
9058 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
9059 | ||
d77b99c9 | 9060 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 9061 | { |
d77b99c9 BW |
9062 | int nop_size; |
9063 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
9064 | |
9065 | assemble_nop (nop_size, nop_buf); | |
9066 | nop_buf += nop_size; | |
9067 | } | |
9068 | ||
9069 | fragp->fr_fix += fill_size; | |
9070 | fragp->fr_var -= fill_size; | |
9071 | } | |
9072 | ||
9073 | ||
9074 | static void | |
7fa3d080 | 9075 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 9076 | { |
43cd72b9 | 9077 | TInsn tinsn, single_target; |
84b08ed9 | 9078 | int size, old_size, diff; |
e0001a05 NC |
9079 | offsetT frag_offset; |
9080 | ||
43cd72b9 BW |
9081 | assert (slot == 0); |
9082 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); | |
9083 | ||
b5e4a23d | 9084 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 BW |
9085 | { |
9086 | assert (fragP->tc_frag_data.text_expansion[0] == 1 | |
9087 | || fragP->tc_frag_data.text_expansion[0] == 0); | |
9088 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
9089 | fmt, slot); | |
9090 | return; | |
9091 | } | |
9092 | ||
9093 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
9094 | { |
9095 | /* No conversion. */ | |
9096 | fragP->fr_var = 0; | |
9097 | return; | |
9098 | } | |
9099 | ||
9100 | assert (fragP->fr_opcode != NULL); | |
9101 | ||
43cd72b9 BW |
9102 | /* Frags in this relaxation state should only contain |
9103 | single instruction bundles. */ | |
9104 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
9105 | |
9106 | /* Just convert it to a wide form.... */ | |
9107 | size = 0; | |
43cd72b9 | 9108 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
9109 | |
9110 | tinsn_init (&single_target); | |
9111 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9112 | ||
84b08ed9 | 9113 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
9114 | { |
9115 | as_bad (_("unable to widen instruction")); | |
9116 | return; | |
9117 | } | |
9118 | ||
9119 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
9120 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
9121 | frag_offset, TRUE); | |
e0001a05 NC |
9122 | |
9123 | diff = size - old_size; | |
9124 | assert (diff >= 0); | |
9125 | assert (diff <= fragP->fr_var); | |
9126 | fragP->fr_var -= diff; | |
9127 | fragP->fr_fix += diff; | |
9128 | ||
9129 | /* clean it up */ | |
9130 | fragP->fr_var = 0; | |
9131 | } | |
9132 | ||
9133 | ||
9134 | static void | |
7fa3d080 | 9135 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
9136 | { |
9137 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
9138 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9139 | assert ((unsigned) size == (fragP->fr_next->fr_address | |
9140 | - fragP->fr_address - fragP->fr_fix)); | |
9141 | if (size == 0) | |
9142 | { | |
9143 | /* No conversion. */ | |
9144 | fragP->fr_var = 0; | |
9145 | return; | |
9146 | } | |
9147 | assemble_nop (size, loc); | |
9148 | fragP->tc_frag_data.is_insn = TRUE; | |
9149 | fragP->fr_var -= size; | |
9150 | fragP->fr_fix += size; | |
9151 | frag_wane (fragP); | |
9152 | } | |
9153 | ||
9154 | ||
7fa3d080 BW |
9155 | static fixS *fix_new_exp_in_seg |
9156 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
9157 | bfd_reloc_code_real_type); | |
9158 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
9159 | ||
43cd72b9 | 9160 | static void |
7fa3d080 BW |
9161 | convert_frag_immed (segT segP, |
9162 | fragS *fragP, | |
9163 | int min_steps, | |
9164 | xtensa_format fmt, | |
9165 | int slot) | |
e0001a05 NC |
9166 | { |
9167 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 9168 | TInsn orig_tinsn; |
e0001a05 | 9169 | bfd_boolean expanded = FALSE; |
e0001a05 | 9170 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 9171 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 BW |
9172 | xtensa_isa isa = xtensa_default_isa; |
9173 | bfd_boolean wide_insn = FALSE; | |
9174 | int bytes; | |
9175 | bfd_boolean is_loop; | |
e0001a05 | 9176 | |
43cd72b9 | 9177 | assert (fr_opcode != NULL); |
e0001a05 | 9178 | |
b5e4a23d | 9179 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 9180 | |
b5e4a23d | 9181 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 9182 | if (cur_vinsn.num_slots > 1) |
43cd72b9 | 9183 | wide_insn = TRUE; |
e0001a05 | 9184 | |
b5e4a23d | 9185 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
9186 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
9187 | ||
9188 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 9189 | |
b08b5071 | 9190 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9191 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
9192 | |
9193 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
9194 | { | |
9195 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
9196 | bytes = xtensa_format_length (isa, fmt); |
9197 | if (bytes >= 4) | |
9198 | { | |
b5e4a23d BW |
9199 | cur_vinsn.slots[slot].opcode = |
9200 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
9201 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
9202 | } |
9203 | else | |
9204 | { | |
9205 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9206 | assert (bytes == 2 || bytes == 3); | |
b5e4a23d | 9207 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
9208 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
9209 | } | |
e7da6241 | 9210 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 9211 | xtensa_insnbuf_to_chars |
b5e4a23d | 9212 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
9213 | fragP->fr_var = 0; |
9214 | } | |
7c834684 | 9215 | else |
e0001a05 | 9216 | { |
43cd72b9 BW |
9217 | /* Here is the fun stuff: Get the immediate field from this |
9218 | instruction. If it fits, we're done. If not, find the next | |
9219 | instruction sequence that fits. */ | |
9220 | ||
e0001a05 NC |
9221 | IStack istack; |
9222 | int i; | |
9223 | symbolS *lit_sym = NULL; | |
9224 | int total_size = 0; | |
43cd72b9 | 9225 | int target_offset = 0; |
e0001a05 NC |
9226 | int old_size; |
9227 | int diff; | |
9228 | symbolS *gen_label = NULL; | |
9229 | offsetT frag_offset; | |
43cd72b9 BW |
9230 | bfd_boolean first = TRUE; |
9231 | bfd_boolean last_is_jump; | |
e0001a05 | 9232 | |
43cd72b9 | 9233 | /* It does not fit. Find something that does and |
e0001a05 | 9234 | convert immediately. */ |
43cd72b9 | 9235 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 9236 | istack_init (&istack); |
43cd72b9 | 9237 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
9238 | segP, fragP, frag_offset, min_steps, 0); |
9239 | ||
43cd72b9 | 9240 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9241 | |
9242 | /* Assemble this right inline. */ | |
9243 | ||
9244 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 9245 | target_offset = 0; |
e0001a05 NC |
9246 | for (i = 0; i < istack.ninsn; i++) |
9247 | { | |
43cd72b9 | 9248 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9249 | fragS *lit_frag; |
9250 | ||
43cd72b9 | 9251 | switch (tinsn->insn_type) |
e0001a05 NC |
9252 | { |
9253 | case ITYPE_LITERAL: | |
9254 | if (lit_sym != NULL) | |
9255 | as_bad (_("multiple literals in expansion")); | |
9256 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 9257 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9258 | if (lit_frag == NULL) |
9259 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 9260 | if (tinsn->ntok != 1) |
e0001a05 NC |
9261 | as_bad (_("number of literal tokens != 1")); |
9262 | ||
9263 | /* Set the literal symbol and add a fixup. */ | |
9264 | lit_sym = lit_frag->fr_symbol; | |
9265 | break; | |
9266 | ||
9267 | case ITYPE_LABEL: | |
43cd72b9 BW |
9268 | if (align_targets && !is_loop) |
9269 | { | |
9270 | fragS *unreach = fragP->fr_next; | |
9271 | while (!(unreach->fr_type == rs_machine_dependent | |
9272 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9273 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
9274 | { | |
9275 | unreach = unreach->fr_next; | |
9276 | } | |
9277 | ||
9278 | assert (unreach->fr_type == rs_machine_dependent | |
9279 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9280 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
9281 | ||
9282 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
9283 | } | |
e0001a05 NC |
9284 | assert (gen_label == NULL); |
9285 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, | |
43cd72b9 BW |
9286 | fr_opcode - fragP->fr_literal |
9287 | + target_offset, fragP); | |
e0001a05 NC |
9288 | break; |
9289 | ||
9290 | case ITYPE_INSN: | |
43cd72b9 BW |
9291 | if (first && wide_insn) |
9292 | { | |
9293 | target_offset += xtensa_format_length (isa, fmt); | |
9294 | first = FALSE; | |
9295 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9296 | target_offset += xg_get_single_size (tinsn->opcode); | |
9297 | } | |
9298 | else | |
9299 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
9300 | break; |
9301 | } | |
9302 | } | |
9303 | ||
9304 | total_size = 0; | |
43cd72b9 BW |
9305 | first = TRUE; |
9306 | last_is_jump = FALSE; | |
e0001a05 NC |
9307 | for (i = 0; i < istack.ninsn; i++) |
9308 | { | |
43cd72b9 | 9309 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9310 | fragS *lit_frag; |
9311 | int size; | |
9312 | segT target_seg; | |
43cd72b9 | 9313 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 9314 | |
43cd72b9 | 9315 | switch (tinsn->insn_type) |
e0001a05 NC |
9316 | { |
9317 | case ITYPE_LITERAL: | |
43cd72b9 BW |
9318 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
9319 | /* Already checked. */ | |
e0001a05 NC |
9320 | assert (lit_frag != NULL); |
9321 | assert (lit_sym != NULL); | |
43cd72b9 BW |
9322 | assert (tinsn->ntok == 1); |
9323 | /* Add a fixup. */ | |
e0001a05 NC |
9324 | target_seg = S_GET_SEGMENT (lit_sym); |
9325 | assert (target_seg); | |
43cd72b9 BW |
9326 | if (tinsn->tok[0].X_op == O_pltrel) |
9327 | reloc_type = BFD_RELOC_XTENSA_PLT; | |
9328 | else | |
9329 | reloc_type = BFD_RELOC_32; | |
e0001a05 | 9330 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 9331 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
9332 | break; |
9333 | ||
9334 | case ITYPE_LABEL: | |
9335 | break; | |
9336 | ||
9337 | case ITYPE_INSN: | |
43cd72b9 BW |
9338 | xg_resolve_labels (tinsn, gen_label); |
9339 | xg_resolve_literals (tinsn, lit_sym); | |
9340 | if (wide_insn && first) | |
9341 | { | |
9342 | first = FALSE; | |
9343 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9344 | { | |
b5e4a23d | 9345 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
9346 | } |
9347 | else | |
9348 | { | |
b5e4a23d | 9349 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 9350 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 9351 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 9352 | } |
b5e4a23d BW |
9353 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
9354 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 9355 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
9356 | fragP->tc_frag_data.is_insn = TRUE; |
9357 | size = xtensa_format_length (isa, fmt); | |
9358 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9359 | { | |
43cd72b9 | 9360 | xg_emit_insn_to_buf |
b2d179be | 9361 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
9362 | immed_instr - fragP->fr_literal + size, TRUE); |
9363 | size += xg_get_single_size (tinsn->opcode); | |
9364 | } | |
9365 | } | |
9366 | else | |
9367 | { | |
43cd72b9 | 9368 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 9369 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 9370 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 9371 | } |
e0001a05 | 9372 | immed_instr += size; |
43cd72b9 | 9373 | total_size += size; |
e0001a05 NC |
9374 | break; |
9375 | } | |
9376 | } | |
9377 | ||
9378 | diff = total_size - old_size; | |
9379 | assert (diff >= 0); | |
9380 | if (diff != 0) | |
9381 | expanded = TRUE; | |
9382 | assert (diff <= fragP->fr_var); | |
9383 | fragP->fr_var -= diff; | |
9384 | fragP->fr_fix += diff; | |
9385 | } | |
9386 | ||
e0001a05 | 9387 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 9388 | if (is_loop) |
e0001a05 NC |
9389 | { |
9390 | symbolS *sym; | |
43cd72b9 | 9391 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
9392 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9393 | { | |
9394 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9395 | return; | |
9396 | } | |
43cd72b9 | 9397 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
9398 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9399 | { | |
9400 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9401 | return; | |
9402 | } | |
9403 | } | |
9404 | ||
43cd72b9 BW |
9405 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
9406 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 9407 | |
43cd72b9 | 9408 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
9409 | { |
9410 | /* Add an expansion note on the expanded instruction. */ | |
9411 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 9412 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 9413 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
9414 | } |
9415 | } | |
9416 | ||
9417 | ||
9418 | /* Add a new fix expression into the desired segment. We have to | |
9419 | switch to that segment to do this. */ | |
9420 | ||
9421 | static fixS * | |
7fa3d080 BW |
9422 | fix_new_exp_in_seg (segT new_seg, |
9423 | subsegT new_subseg, | |
9424 | fragS *frag, | |
9425 | int where, | |
9426 | int size, | |
9427 | expressionS *exp, | |
9428 | int pcrel, | |
9429 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
9430 | { |
9431 | fixS *new_fix; | |
9432 | segT seg = now_seg; | |
9433 | subsegT subseg = now_subseg; | |
43cd72b9 | 9434 | |
e0001a05 NC |
9435 | assert (new_seg != 0); |
9436 | subseg_set (new_seg, new_subseg); | |
9437 | ||
e0001a05 NC |
9438 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
9439 | subseg_set (seg, subseg); | |
9440 | return new_fix; | |
9441 | } | |
9442 | ||
9443 | ||
43cd72b9 BW |
9444 | /* Relax a loop instruction so that it can span loop >256 bytes. |
9445 | ||
9446 | loop as, .L1 | |
9447 | .L0: | |
9448 | rsr as, LEND | |
9449 | wsr as, LBEG | |
9450 | addi as, as, lo8 (label-.L1) | |
9451 | addmi as, as, mid8 (label-.L1) | |
9452 | wsr as, LEND | |
9453 | isync | |
9454 | rsr as, LCOUNT | |
9455 | addi as, as, 1 | |
9456 | .L1: | |
9457 | <<body>> | |
9458 | label: | |
9459 | */ | |
e0001a05 NC |
9460 | |
9461 | static void | |
7fa3d080 | 9462 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
9463 | { |
9464 | TInsn loop_insn; | |
9465 | TInsn addi_insn; | |
9466 | TInsn addmi_insn; | |
9467 | unsigned long target; | |
9468 | static xtensa_insnbuf insnbuf = NULL; | |
9469 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
9470 | xtensa_isa isa = xtensa_default_isa; | |
9471 | addressT loop_offset; | |
9472 | addressT addi_offset = 9; | |
9473 | addressT addmi_offset = 12; | |
43cd72b9 | 9474 | fragS *next_fragP; |
d77b99c9 | 9475 | int target_count; |
e0001a05 NC |
9476 | |
9477 | if (!insnbuf) | |
9478 | insnbuf = xtensa_insnbuf_alloc (isa); | |
9479 | ||
9480 | /* Get the loop offset. */ | |
43cd72b9 | 9481 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 9482 | |
43cd72b9 BW |
9483 | /* Validate that there really is a LOOP at the loop_offset. Because |
9484 | loops are not bundleable, we can assume that the instruction will be | |
9485 | in slot 0. */ | |
9486 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
9487 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
9488 | ||
9489 | assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); | |
e0001a05 NC |
9490 | addi_offset += loop_offset; |
9491 | addmi_offset += loop_offset; | |
9492 | ||
43cd72b9 | 9493 | assert (tinsn->ntok == 2); |
b08b5071 BW |
9494 | if (tinsn->tok[1].X_op == O_constant) |
9495 | target = tinsn->tok[1].X_add_number; | |
9496 | else if (tinsn->tok[1].X_op == O_symbol) | |
9497 | { | |
9498 | /* Find the fragment. */ | |
9499 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9500 | assert (S_GET_SEGMENT (sym) == segP | |
9501 | || S_GET_SEGMENT (sym) == absolute_section); | |
9502 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
9503 | } | |
9504 | else | |
9505 | { | |
9506 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
9507 | target = 0; | |
9508 | } | |
e0001a05 NC |
9509 | |
9510 | know (symbolP); | |
9511 | know (symbolP->sy_frag); | |
9512 | know (!(S_GET_SEGMENT (symbolP) == absolute_section) | |
9513 | || symbol_get_frag (symbolP) == &zero_address_frag); | |
9514 | ||
9515 | loop_length = target - (fragP->fr_address + fragP->fr_fix); | |
9516 | loop_length_hi = loop_length & ~0x0ff; | |
9517 | loop_length_lo = loop_length & 0x0ff; | |
9518 | if (loop_length_lo >= 128) | |
9519 | { | |
9520 | loop_length_lo -= 256; | |
9521 | loop_length_hi += 256; | |
9522 | } | |
9523 | ||
43cd72b9 | 9524 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
9525 | 32512. If the loop is larger than that, then we just fail. */ |
9526 | if (loop_length_hi > 32512) | |
9527 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9528 | _("loop too long for LOOP instruction")); | |
9529 | ||
43cd72b9 | 9530 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
e0001a05 NC |
9531 | assert (addi_insn.opcode == xtensa_addi_opcode); |
9532 | ||
43cd72b9 | 9533 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
e0001a05 NC |
9534 | assert (addmi_insn.opcode == xtensa_addmi_opcode); |
9535 | ||
9536 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
9537 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 9538 | |
e0001a05 | 9539 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
9540 | xtensa_insnbuf_to_chars |
9541 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
9542 | |
9543 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
9544 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
9545 | xtensa_insnbuf_to_chars |
9546 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
9547 | |
9548 | /* Walk through all of the frags from here to the loop end | |
9549 | and mark them as no_transform to keep them from being modified | |
9550 | by the linker. If we ever have a relocation for the | |
9551 | addi/addmi of the difference of two symbols we can remove this. */ | |
9552 | ||
9553 | target_count = 0; | |
9554 | for (next_fragP = fragP; next_fragP != NULL; | |
9555 | next_fragP = next_fragP->fr_next) | |
9556 | { | |
b08b5071 | 9557 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
9558 | if (next_fragP->tc_frag_data.is_loop_target) |
9559 | target_count++; | |
9560 | if (target_count == 2) | |
9561 | break; | |
9562 | } | |
e0001a05 NC |
9563 | } |
9564 | ||
b08b5071 BW |
9565 | \f |
9566 | /* A map that keeps information on a per-subsegment basis. This is | |
9567 | maintained during initial assembly, but is invalid once the | |
9568 | subsegments are smashed together. I.E., it cannot be used during | |
9569 | the relaxation. */ | |
e0001a05 | 9570 | |
b08b5071 | 9571 | typedef struct subseg_map_struct |
e0001a05 | 9572 | { |
b08b5071 BW |
9573 | /* the key */ |
9574 | segT seg; | |
9575 | subsegT subseg; | |
e0001a05 | 9576 | |
b08b5071 BW |
9577 | /* the data */ |
9578 | unsigned flags; | |
9579 | float total_freq; /* fall-through + branch target frequency */ | |
9580 | float target_freq; /* branch target frequency alone */ | |
9581 | ||
9582 | struct subseg_map_struct *next; | |
9583 | } subseg_map; | |
e0001a05 | 9584 | |
e0001a05 | 9585 | |
e0001a05 NC |
9586 | static subseg_map *sseg_map = NULL; |
9587 | ||
43cd72b9 | 9588 | static subseg_map * |
7fa3d080 | 9589 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
9590 | { |
9591 | subseg_map *subseg_e; | |
9592 | ||
9593 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 9594 | { |
43cd72b9 | 9595 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 9596 | break; |
e0001a05 | 9597 | } |
b08b5071 BW |
9598 | return subseg_e; |
9599 | } | |
9600 | ||
9601 | ||
9602 | static subseg_map * | |
9603 | add_subseg_info (segT seg, subsegT subseg) | |
9604 | { | |
9605 | subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); | |
43cd72b9 BW |
9606 | memset (subseg_e, 0, sizeof (subseg_map)); |
9607 | subseg_e->seg = seg; | |
9608 | subseg_e->subseg = subseg; | |
9609 | subseg_e->flags = 0; | |
9610 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
9611 | subseg_e->target_freq = 1.0; |
9612 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
9613 | subseg_e->next = sseg_map; |
9614 | sseg_map = subseg_e; | |
43cd72b9 BW |
9615 | return subseg_e; |
9616 | } | |
e0001a05 | 9617 | |
7fa3d080 BW |
9618 | |
9619 | static unsigned | |
9620 | get_last_insn_flags (segT seg, subsegT subseg) | |
9621 | { | |
9622 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9623 | if (subseg_e) |
9624 | return subseg_e->flags; | |
9625 | return 0; | |
7fa3d080 BW |
9626 | } |
9627 | ||
9628 | ||
43cd72b9 | 9629 | static void |
7fa3d080 BW |
9630 | set_last_insn_flags (segT seg, |
9631 | subsegT subseg, | |
9632 | unsigned fl, | |
9633 | bfd_boolean val) | |
43cd72b9 BW |
9634 | { |
9635 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9636 | if (! subseg_e) |
9637 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
9638 | if (val) |
9639 | subseg_e->flags |= fl; | |
9640 | else | |
9641 | subseg_e->flags &= ~fl; | |
9642 | } | |
9643 | ||
b08b5071 BW |
9644 | |
9645 | static float | |
9646 | get_subseg_total_freq (segT seg, subsegT subseg) | |
9647 | { | |
9648 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9649 | if (subseg_e) | |
9650 | return subseg_e->total_freq; | |
9651 | return 1.0; | |
9652 | } | |
9653 | ||
9654 | ||
9655 | static float | |
9656 | get_subseg_target_freq (segT seg, subsegT subseg) | |
9657 | { | |
9658 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9659 | if (subseg_e) | |
9660 | return subseg_e->target_freq; | |
9661 | return 1.0; | |
9662 | } | |
9663 | ||
9664 | ||
9665 | static void | |
9666 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
9667 | { | |
9668 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9669 | if (! subseg_e) | |
9670 | subseg_e = add_subseg_info (seg, subseg); | |
9671 | subseg_e->total_freq = total_f; | |
9672 | subseg_e->target_freq = target_f; | |
9673 | } | |
9674 | ||
e0001a05 NC |
9675 | \f |
9676 | /* Segment Lists and emit_state Stuff. */ | |
9677 | ||
e0001a05 | 9678 | static void |
7fa3d080 | 9679 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
9680 | { |
9681 | head = head->next; | |
9682 | while (head) | |
9683 | { | |
9684 | segT literal_section = head->seg; | |
9685 | ||
9686 | /* Move the literal section to the front of the section list. */ | |
9687 | assert (literal_section); | |
69852798 AM |
9688 | if (literal_section != stdoutput->sections) |
9689 | { | |
9690 | bfd_section_list_remove (stdoutput, literal_section); | |
9691 | bfd_section_list_prepend (stdoutput, literal_section); | |
9692 | } | |
e0001a05 NC |
9693 | head = head->next; |
9694 | } | |
9695 | } | |
9696 | ||
9697 | ||
7fa3d080 BW |
9698 | static void mark_literal_frags (seg_list *); |
9699 | ||
9700 | static void | |
9701 | xtensa_move_literals (void) | |
e0001a05 NC |
9702 | { |
9703 | seg_list *segment; | |
9704 | frchainS *frchain_from, *frchain_to; | |
9705 | fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after; | |
9706 | fragS **frag_splice; | |
9707 | emit_state state; | |
9708 | segT dest_seg; | |
9709 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 9710 | sym_list *lit; |
e0001a05 | 9711 | |
a7877748 BW |
9712 | mark_literal_frags (literal_head->next); |
9713 | mark_literal_frags (init_literal_head->next); | |
9714 | mark_literal_frags (fini_literal_head->next); | |
e0001a05 NC |
9715 | |
9716 | if (use_literal_section) | |
9717 | return; | |
9718 | ||
9719 | segment = literal_head->next; | |
9720 | while (segment) | |
9721 | { | |
9722 | frchain_from = seg_info (segment->seg)->frchainP; | |
9723 | search_frag = frchain_from->frch_root; | |
9724 | literal_pool = NULL; | |
9725 | frchain_to = NULL; | |
9726 | frag_splice = &(frchain_from->frch_root); | |
9727 | ||
9728 | while (!search_frag->tc_frag_data.literal_frag) | |
9729 | { | |
9730 | assert (search_frag->fr_fix == 0 | |
9731 | || search_frag->fr_type == rs_align); | |
9732 | search_frag = search_frag->fr_next; | |
9733 | } | |
9734 | ||
9735 | assert (search_frag->tc_frag_data.literal_frag->fr_subtype | |
9736 | == RELAX_LITERAL_POOL_BEGIN); | |
9737 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
9738 | ||
9739 | /* Make sure that all the frags in this series are closed, and | |
9740 | that there is at least one left over of zero-size. This | |
9741 | prevents us from making a segment with an frchain without any | |
9742 | frags in it. */ | |
9743 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9744 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
9745 | last_frag = frag_now; |
9746 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9747 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 9748 | |
43cd72b9 | 9749 | while (search_frag != frag_now) |
e0001a05 NC |
9750 | { |
9751 | next_frag = search_frag->fr_next; | |
9752 | ||
43cd72b9 | 9753 | /* First, move the frag out of the literal section and |
e0001a05 NC |
9754 | to the appropriate place. */ |
9755 | if (search_frag->tc_frag_data.literal_frag) | |
9756 | { | |
9757 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9758 | assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); | |
dd49a749 BW |
9759 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9760 | assert (frchain_to); | |
e0001a05 NC |
9761 | } |
9762 | insert_after = literal_pool; | |
43cd72b9 | 9763 | |
e0001a05 NC |
9764 | while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END) |
9765 | insert_after = insert_after->fr_next; | |
9766 | ||
dd49a749 | 9767 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
43cd72b9 | 9768 | |
e0001a05 NC |
9769 | *frag_splice = next_frag; |
9770 | search_frag->fr_next = insert_after->fr_next; | |
9771 | insert_after->fr_next = search_frag; | |
9772 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
9773 | ||
9774 | /* Now move any fixups associated with this frag to the | |
9775 | right section. */ | |
9776 | fix = frchain_from->fix_root; | |
9777 | fix_splice = &(frchain_from->fix_root); | |
9778 | while (fix) | |
9779 | { | |
9780 | next_fix = fix->fx_next; | |
9781 | if (fix->fx_frag == search_frag) | |
9782 | { | |
9783 | *fix_splice = next_fix; | |
9784 | fix->fx_next = frchain_to->fix_root; | |
9785 | frchain_to->fix_root = fix; | |
9786 | if (frchain_to->fix_tail == NULL) | |
9787 | frchain_to->fix_tail = fix; | |
9788 | } | |
9789 | else | |
9790 | fix_splice = &(fix->fx_next); | |
9791 | fix = next_fix; | |
9792 | } | |
9793 | search_frag = next_frag; | |
9794 | } | |
9795 | ||
9796 | if (frchain_from->fix_root != NULL) | |
9797 | { | |
9798 | frchain_from = seg_info (segment->seg)->frchainP; | |
9799 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
9800 | ||
9801 | assert (frchain_from->fix_root == NULL); | |
9802 | } | |
9803 | frchain_from->fix_tail = NULL; | |
9804 | xtensa_restore_emit_state (&state); | |
9805 | segment = segment->next; | |
9806 | } | |
9807 | ||
82e7541d BW |
9808 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
9809 | for (lit = literal_syms; lit; lit = lit->next) | |
9810 | { | |
9811 | symbolS *lit_sym = lit->sym; | |
9812 | segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; | |
43cd72b9 BW |
9813 | if (dest_seg) |
9814 | S_SET_SEGMENT (lit_sym, dest_seg); | |
82e7541d | 9815 | } |
e0001a05 NC |
9816 | } |
9817 | ||
9818 | ||
a7877748 BW |
9819 | /* Walk over all the frags for segments in a list and mark them as |
9820 | containing literals. As clunky as this is, we can't rely on frag_var | |
9821 | and frag_variant to get called in all situations. */ | |
9822 | ||
9823 | static void | |
7fa3d080 | 9824 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
9825 | { |
9826 | frchainS *frchain_from; | |
9827 | fragS *search_frag; | |
9828 | ||
9829 | while (segment) | |
9830 | { | |
9831 | frchain_from = seg_info (segment->seg)->frchainP; | |
9832 | search_frag = frchain_from->frch_root; | |
c138bc38 | 9833 | while (search_frag) |
a7877748 BW |
9834 | { |
9835 | search_frag->tc_frag_data.is_literal = TRUE; | |
9836 | search_frag = search_frag->fr_next; | |
9837 | } | |
9838 | segment = segment->next; | |
9839 | } | |
9840 | } | |
9841 | ||
9842 | ||
e0001a05 | 9843 | static void |
7fa3d080 | 9844 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
9845 | { |
9846 | /* Move all of the sections in the section list to come | |
9847 | after "after" in the gnu segment list. */ | |
9848 | ||
9849 | head = head->next; | |
9850 | while (head) | |
9851 | { | |
9852 | segT literal_section = head->seg; | |
9853 | ||
9854 | /* Move the literal section after "after". */ | |
9855 | assert (literal_section); | |
9856 | if (literal_section != after) | |
9857 | { | |
69852798 AM |
9858 | bfd_section_list_remove (stdoutput, literal_section); |
9859 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
9860 | } |
9861 | ||
9862 | head = head->next; | |
9863 | } | |
9864 | } | |
9865 | ||
9866 | ||
9867 | /* Push all the literal segments to the end of the gnu list. */ | |
9868 | ||
7fa3d080 BW |
9869 | static void |
9870 | xtensa_reorder_segments (void) | |
e0001a05 NC |
9871 | { |
9872 | segT sec; | |
b08b5071 | 9873 | segT last_sec = 0; |
e0001a05 NC |
9874 | int old_count = 0; |
9875 | int new_count = 0; | |
9876 | ||
9877 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
9878 | { |
9879 | last_sec = sec; | |
9880 | old_count++; | |
9881 | } | |
e0001a05 NC |
9882 | |
9883 | /* Now that we have the last section, push all the literal | |
9884 | sections to the end. */ | |
e0001a05 NC |
9885 | xtensa_reorder_seg_list (literal_head, last_sec); |
9886 | xtensa_reorder_seg_list (init_literal_head, last_sec); | |
9887 | xtensa_reorder_seg_list (fini_literal_head, last_sec); | |
9888 | ||
9889 | /* Now perform the final error check. */ | |
9890 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
9891 | new_count++; | |
9892 | assert (new_count == old_count); | |
9893 | } | |
9894 | ||
9895 | ||
e0001a05 NC |
9896 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
9897 | correct location. Return a emit_state which can be passed to | |
9898 | xtensa_restore_emit_state to return to current fragment. */ | |
9899 | ||
7fa3d080 BW |
9900 | static void |
9901 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
9902 | { |
9903 | if (directive_state[directive_absolute_literals]) | |
9904 | { | |
9905 | cache_literal_section (0, default_lit_sections.lit4_seg_name, | |
9906 | &default_lit_sections.lit4_seg, FALSE); | |
9907 | xtensa_switch_section_emit_state (result, | |
9908 | default_lit_sections.lit4_seg, 0); | |
9909 | } | |
9910 | else | |
9911 | xtensa_switch_to_non_abs_literal_fragment (result); | |
9912 | ||
9913 | /* Do a 4-byte align here. */ | |
9914 | frag_align (2, 0, 0); | |
9915 | record_alignment (now_seg, 2); | |
9916 | } | |
9917 | ||
9918 | ||
7fa3d080 BW |
9919 | static void |
9920 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 NC |
9921 | { |
9922 | /* When we mark a literal pool location, we want to put a frag in | |
9923 | the literal pool that points to it. But to do that, we want to | |
9924 | switch_to_literal_fragment. But literal sections don't have | |
9925 | literal pools, so their location is always null, so we would | |
9926 | recurse forever. This is kind of hacky, but it works. */ | |
9927 | ||
9928 | static bfd_boolean recursive = FALSE; | |
9929 | fragS *pool_location = get_literal_pool_location (now_seg); | |
c138bc38 | 9930 | bfd_boolean is_init = |
e0001a05 NC |
9931 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); |
9932 | ||
c138bc38 | 9933 | bfd_boolean is_fini = |
e0001a05 | 9934 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); |
e0001a05 | 9935 | |
43cd72b9 BW |
9936 | if (pool_location == NULL |
9937 | && !use_literal_section | |
e0001a05 NC |
9938 | && !recursive |
9939 | && !is_init && ! is_fini) | |
9940 | { | |
43cd72b9 | 9941 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); |
e0001a05 | 9942 | recursive = TRUE; |
61846f28 | 9943 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
9944 | recursive = FALSE; |
9945 | } | |
9946 | ||
9947 | /* Special case: If we are in the ".fini" or ".init" section, then | |
9948 | we will ALWAYS be generating to the ".fini.literal" and | |
9949 | ".init.literal" sections. */ | |
9950 | ||
9951 | if (is_init) | |
9952 | { | |
9953 | cache_literal_section (init_literal_head, | |
9954 | default_lit_sections.init_lit_seg_name, | |
43cd72b9 | 9955 | &default_lit_sections.init_lit_seg, TRUE); |
e0001a05 NC |
9956 | xtensa_switch_section_emit_state (result, |
9957 | default_lit_sections.init_lit_seg, 0); | |
9958 | } | |
9959 | else if (is_fini) | |
9960 | { | |
9961 | cache_literal_section (fini_literal_head, | |
9962 | default_lit_sections.fini_lit_seg_name, | |
43cd72b9 | 9963 | &default_lit_sections.fini_lit_seg, TRUE); |
e0001a05 NC |
9964 | xtensa_switch_section_emit_state (result, |
9965 | default_lit_sections.fini_lit_seg, 0); | |
9966 | } | |
43cd72b9 | 9967 | else |
e0001a05 NC |
9968 | { |
9969 | cache_literal_section (literal_head, | |
9970 | default_lit_sections.lit_seg_name, | |
43cd72b9 | 9971 | &default_lit_sections.lit_seg, TRUE); |
e0001a05 NC |
9972 | xtensa_switch_section_emit_state (result, |
9973 | default_lit_sections.lit_seg, 0); | |
9974 | } | |
9975 | ||
43cd72b9 BW |
9976 | if (!use_literal_section |
9977 | && !is_init && !is_fini | |
9978 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
9979 | { |
9980 | /* Close whatever frag is there. */ | |
9981 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9982 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
9983 | frag_now->tc_frag_data.literal_frag = pool_location; |
9984 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9985 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 9986 | } |
e0001a05 NC |
9987 | } |
9988 | ||
9989 | ||
9990 | /* Call this function before emitting data into the literal section. | |
9991 | This is a helper function for xtensa_switch_to_literal_fragment. | |
9992 | This is similar to a .section new_now_seg subseg. */ | |
9993 | ||
7fa3d080 BW |
9994 | static void |
9995 | xtensa_switch_section_emit_state (emit_state *state, | |
9996 | segT new_now_seg, | |
9997 | subsegT new_now_subseg) | |
e0001a05 NC |
9998 | { |
9999 | state->name = now_seg->name; | |
10000 | state->now_seg = now_seg; | |
10001 | state->now_subseg = now_subseg; | |
10002 | state->generating_literals = generating_literals; | |
10003 | generating_literals++; | |
2b0210eb | 10004 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
10005 | } |
10006 | ||
10007 | ||
10008 | /* Use to restore the emitting into the normal place. */ | |
10009 | ||
7fa3d080 BW |
10010 | static void |
10011 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
10012 | { |
10013 | generating_literals = state->generating_literals; | |
2b0210eb | 10014 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
10015 | } |
10016 | ||
10017 | ||
10018 | /* Get a segment of a given name. If the segment is already | |
10019 | present, return it; otherwise, create a new one. */ | |
10020 | ||
10021 | static void | |
7fa3d080 BW |
10022 | cache_literal_section (seg_list *head, |
10023 | const char *name, | |
b08b5071 | 10024 | segT *pseg, |
7fa3d080 | 10025 | bfd_boolean is_code) |
e0001a05 NC |
10026 | { |
10027 | segT current_section = now_seg; | |
10028 | int current_subsec = now_subseg; | |
b08b5071 | 10029 | segT seg; |
e0001a05 | 10030 | |
b08b5071 | 10031 | if (*pseg != 0) |
e0001a05 | 10032 | return; |
e0001a05 | 10033 | |
b08b5071 BW |
10034 | /* Check if the named section exists. */ |
10035 | for (seg = stdoutput->sections; seg; seg = seg->next) | |
10036 | { | |
10037 | if (!strcmp (segment_name (seg), name)) | |
10038 | break; | |
10039 | } | |
e0001a05 | 10040 | |
b08b5071 | 10041 | if (!seg) |
e0001a05 | 10042 | { |
b08b5071 BW |
10043 | /* Create a new literal section. */ |
10044 | seg = subseg_new (name, (subsegT) 0); | |
43cd72b9 | 10045 | if (head) |
b08b5071 BW |
10046 | { |
10047 | /* Add the newly created literal segment to the specified list. */ | |
10048 | seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); | |
10049 | n->seg = seg; | |
10050 | n->next = head->next; | |
10051 | head->next = n; | |
10052 | } | |
10053 | bfd_set_section_flags (stdoutput, seg, SEC_HAS_CONTENTS | | |
43cd72b9 BW |
10054 | SEC_READONLY | SEC_ALLOC | SEC_LOAD |
10055 | | (is_code ? SEC_CODE : SEC_DATA)); | |
b08b5071 | 10056 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
10057 | } |
10058 | ||
b08b5071 BW |
10059 | *pseg = seg; |
10060 | subseg_set (current_section, current_subsec); | |
e0001a05 NC |
10061 | } |
10062 | ||
43cd72b9 BW |
10063 | \f |
10064 | /* Property Tables Stuff. */ | |
10065 | ||
7fa3d080 BW |
10066 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
10067 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
10068 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
10069 | ||
10070 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
10071 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
10072 | ||
b08b5071 | 10073 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
10074 | static void xtensa_create_property_segments |
10075 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
10076 | static void xtensa_create_xproperty_segments | |
10077 | (frag_flags_fn, const char *, xt_section_type); | |
10078 | static segment_info_type *retrieve_segment_info (segT); | |
10079 | static segT retrieve_xtensa_section (char *); | |
10080 | static bfd_boolean section_has_property (segT, frag_predicate); | |
10081 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
10082 | static void add_xt_block_frags | |
10083 | (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate); | |
10084 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); | |
10085 | static void xtensa_frag_flags_init (frag_flags *); | |
10086 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
10087 | static bfd_vma frag_flags_to_number (const frag_flags *); | |
10088 | static void add_xt_prop_frags | |
10089 | (segT, segT, xtensa_block_info **, frag_flags_fn); | |
10090 | ||
10091 | /* Set up property tables after relaxation. */ | |
10092 | ||
10093 | void | |
10094 | xtensa_post_relax_hook (void) | |
10095 | { | |
10096 | xtensa_move_seg_list_to_beginning (literal_head); | |
10097 | xtensa_move_seg_list_to_beginning (init_literal_head); | |
10098 | xtensa_move_seg_list_to_beginning (fini_literal_head); | |
10099 | ||
10100 | xtensa_find_unmarked_state_frags (); | |
10101 | ||
b29757dc BW |
10102 | xtensa_create_property_segments (get_frag_is_literal, |
10103 | NULL, | |
10104 | XTENSA_LIT_SEC_NAME, | |
10105 | xt_literal_sec); | |
7fa3d080 BW |
10106 | xtensa_create_xproperty_segments (get_frag_property_flags, |
10107 | XTENSA_PROP_SEC_NAME, | |
10108 | xt_prop_sec); | |
10109 | ||
10110 | if (warn_unaligned_branch_targets) | |
10111 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
10112 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
10113 | } | |
10114 | ||
10115 | ||
43cd72b9 BW |
10116 | /* This function is only meaningful after xtensa_move_literals. */ |
10117 | ||
10118 | static bfd_boolean | |
7fa3d080 | 10119 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 BW |
10120 | { |
10121 | assert (fragP != NULL); | |
10122 | return fragP->tc_frag_data.is_literal; | |
10123 | } | |
10124 | ||
10125 | ||
43cd72b9 | 10126 | static void |
7fa3d080 BW |
10127 | xtensa_create_property_segments (frag_predicate property_function, |
10128 | frag_predicate end_property_function, | |
10129 | const char *section_name_base, | |
10130 | xt_section_type sec_type) | |
43cd72b9 BW |
10131 | { |
10132 | segT *seclist; | |
10133 | ||
10134 | /* Walk over all of the current segments. | |
10135 | Walk over each fragment | |
10136 | For each non-empty fragment, | |
10137 | Build a property record (append where possible). */ | |
10138 | ||
10139 | for (seclist = &stdoutput->sections; | |
10140 | seclist && *seclist; | |
10141 | seclist = &(*seclist)->next) | |
10142 | { | |
10143 | segT sec = *seclist; | |
10144 | flagword flags; | |
10145 | ||
10146 | flags = bfd_get_section_flags (stdoutput, sec); | |
10147 | if (flags & SEC_DEBUGGING) | |
10148 | continue; | |
10149 | if (!(flags & SEC_ALLOC)) | |
10150 | continue; | |
10151 | ||
10152 | if (section_has_property (sec, property_function)) | |
10153 | { | |
10154 | char *property_section_name = | |
10155 | xtensa_get_property_section_name (sec, section_name_base); | |
10156 | segT insn_sec = retrieve_xtensa_section (property_section_name); | |
10157 | segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); | |
10158 | xtensa_block_info **xt_blocks = | |
10159 | &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10160 | /* Walk over all of the frchains here and add new sections. */ | |
10161 | add_xt_block_frags (sec, insn_sec, xt_blocks, property_function, | |
10162 | end_property_function); | |
10163 | } | |
10164 | } | |
10165 | ||
10166 | /* Now we fill them out.... */ | |
10167 | ||
10168 | for (seclist = &stdoutput->sections; | |
10169 | seclist && *seclist; | |
10170 | seclist = &(*seclist)->next) | |
10171 | { | |
10172 | segment_info_type *seginfo; | |
10173 | xtensa_block_info *block; | |
10174 | segT sec = *seclist; | |
10175 | ||
10176 | seginfo = seg_info (sec); | |
10177 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10178 | ||
10179 | if (block) | |
10180 | { | |
10181 | xtensa_block_info *cur_block; | |
10182 | /* This is a section with some data. */ | |
10183 | int num_recs = 0; | |
d77b99c9 | 10184 | bfd_size_type rec_size; |
43cd72b9 BW |
10185 | |
10186 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10187 | num_recs++; | |
10188 | ||
10189 | rec_size = num_recs * 8; | |
10190 | bfd_set_section_size (stdoutput, sec, rec_size); | |
10191 | ||
10192 | /* In order to make this work with the assembler, we have to | |
10193 | build some frags and then build the "fixups" for it. It | |
10194 | would be easier to just set the contents then set the | |
10195 | arlents. */ | |
10196 | ||
10197 | if (num_recs) | |
10198 | { | |
10199 | /* Allocate a fragment and leak it. */ | |
10200 | fragS *fragP; | |
d77b99c9 | 10201 | bfd_size_type frag_size; |
43cd72b9 BW |
10202 | fixS *fixes; |
10203 | frchainS *frchainP; | |
10204 | int i; | |
10205 | char *frag_data; | |
10206 | ||
10207 | frag_size = sizeof (fragS) + rec_size; | |
10208 | fragP = (fragS *) xmalloc (frag_size); | |
e0001a05 | 10209 | |
43cd72b9 BW |
10210 | memset (fragP, 0, frag_size); |
10211 | fragP->fr_address = 0; | |
10212 | fragP->fr_next = NULL; | |
10213 | fragP->fr_fix = rec_size; | |
10214 | fragP->fr_var = 0; | |
10215 | fragP->fr_type = rs_fill; | |
10216 | /* The rest are zeros. */ | |
e0001a05 | 10217 | |
43cd72b9 BW |
10218 | frchainP = seginfo->frchainP; |
10219 | frchainP->frch_root = fragP; | |
10220 | frchainP->frch_last = fragP; | |
e0001a05 | 10221 | |
43cd72b9 BW |
10222 | fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); |
10223 | memset (fixes, 0, sizeof (fixS) * num_recs); | |
e0001a05 | 10224 | |
43cd72b9 BW |
10225 | seginfo->fix_root = fixes; |
10226 | seginfo->fix_tail = &fixes[num_recs - 1]; | |
10227 | cur_block = block; | |
10228 | frag_data = &fragP->fr_literal[0]; | |
10229 | for (i = 0; i < num_recs; i++) | |
10230 | { | |
10231 | fixS *fix = &fixes[i]; | |
10232 | assert (cur_block); | |
e0001a05 | 10233 | |
43cd72b9 BW |
10234 | /* Write the fixup. */ |
10235 | if (i != num_recs - 1) | |
10236 | fix->fx_next = &fixes[i + 1]; | |
10237 | else | |
10238 | fix->fx_next = NULL; | |
10239 | fix->fx_size = 4; | |
10240 | fix->fx_done = 0; | |
10241 | fix->fx_frag = fragP; | |
10242 | fix->fx_where = i * 8; | |
10243 | fix->fx_addsy = section_symbol (cur_block->sec); | |
10244 | fix->fx_offset = cur_block->offset; | |
10245 | fix->fx_r_type = BFD_RELOC_32; | |
10246 | fix->fx_file = "Internal Assembly"; | |
10247 | fix->fx_line = 0; | |
e0001a05 | 10248 | |
43cd72b9 BW |
10249 | /* Write the length. */ |
10250 | md_number_to_chars (&frag_data[4 + 8 * i], | |
10251 | cur_block->size, 4); | |
10252 | cur_block = cur_block->next; | |
10253 | } | |
10254 | } | |
10255 | } | |
10256 | } | |
e0001a05 NC |
10257 | } |
10258 | ||
10259 | ||
7fa3d080 BW |
10260 | static void |
10261 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
10262 | const char *section_name_base, | |
10263 | xt_section_type sec_type) | |
e0001a05 NC |
10264 | { |
10265 | segT *seclist; | |
10266 | ||
10267 | /* Walk over all of the current segments. | |
43cd72b9 BW |
10268 | Walk over each fragment. |
10269 | For each fragment that has instructions, | |
10270 | build an instruction record (append where possible). */ | |
e0001a05 NC |
10271 | |
10272 | for (seclist = &stdoutput->sections; | |
10273 | seclist && *seclist; | |
10274 | seclist = &(*seclist)->next) | |
10275 | { | |
10276 | segT sec = *seclist; | |
43cd72b9 BW |
10277 | flagword flags; |
10278 | ||
10279 | flags = bfd_get_section_flags (stdoutput, sec); | |
6624cbde BW |
10280 | if ((flags & SEC_DEBUGGING) |
10281 | || !(flags & SEC_ALLOC) | |
10282 | || (flags & SEC_MERGE)) | |
43cd72b9 BW |
10283 | continue; |
10284 | ||
10285 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 10286 | { |
b614a702 BW |
10287 | char *property_section_name = |
10288 | xtensa_get_property_section_name (sec, section_name_base); | |
e0001a05 NC |
10289 | segT insn_sec = retrieve_xtensa_section (property_section_name); |
10290 | segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); | |
43cd72b9 | 10291 | xtensa_block_info **xt_blocks = |
e0001a05 NC |
10292 | &xt_seg_info->tc_segment_info_data.blocks[sec_type]; |
10293 | /* Walk over all of the frchains here and add new sections. */ | |
43cd72b9 | 10294 | add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn); |
e0001a05 NC |
10295 | } |
10296 | } | |
10297 | ||
10298 | /* Now we fill them out.... */ | |
10299 | ||
10300 | for (seclist = &stdoutput->sections; | |
10301 | seclist && *seclist; | |
10302 | seclist = &(*seclist)->next) | |
10303 | { | |
10304 | segment_info_type *seginfo; | |
10305 | xtensa_block_info *block; | |
10306 | segT sec = *seclist; | |
43cd72b9 | 10307 | |
e0001a05 NC |
10308 | seginfo = seg_info (sec); |
10309 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10310 | ||
10311 | if (block) | |
10312 | { | |
10313 | xtensa_block_info *cur_block; | |
10314 | /* This is a section with some data. */ | |
43cd72b9 | 10315 | int num_recs = 0; |
d77b99c9 | 10316 | bfd_size_type rec_size; |
e0001a05 NC |
10317 | |
10318 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10319 | num_recs++; | |
10320 | ||
43cd72b9 | 10321 | rec_size = num_recs * (8 + 4); |
e0001a05 NC |
10322 | bfd_set_section_size (stdoutput, sec, rec_size); |
10323 | ||
43cd72b9 BW |
10324 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
10325 | ||
10326 | /* In order to make this work with the assembler, we have to build | |
10327 | some frags then build the "fixups" for it. It would be easier to | |
10328 | just set the contents then set the arlents. */ | |
e0001a05 NC |
10329 | |
10330 | if (num_recs) | |
10331 | { | |
43cd72b9 | 10332 | /* Allocate a fragment and (unfortunately) leak it. */ |
e0001a05 | 10333 | fragS *fragP; |
d77b99c9 | 10334 | bfd_size_type frag_size; |
e0001a05 NC |
10335 | fixS *fixes; |
10336 | frchainS *frchainP; | |
43cd72b9 | 10337 | int i; |
e0001a05 NC |
10338 | char *frag_data; |
10339 | ||
10340 | frag_size = sizeof (fragS) + rec_size; | |
10341 | fragP = (fragS *) xmalloc (frag_size); | |
10342 | ||
10343 | memset (fragP, 0, frag_size); | |
10344 | fragP->fr_address = 0; | |
10345 | fragP->fr_next = NULL; | |
10346 | fragP->fr_fix = rec_size; | |
10347 | fragP->fr_var = 0; | |
10348 | fragP->fr_type = rs_fill; | |
43cd72b9 | 10349 | /* The rest are zeros. */ |
e0001a05 NC |
10350 | |
10351 | frchainP = seginfo->frchainP; | |
10352 | frchainP->frch_root = fragP; | |
10353 | frchainP->frch_last = fragP; | |
10354 | ||
10355 | fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); | |
10356 | memset (fixes, 0, sizeof (fixS) * num_recs); | |
10357 | ||
10358 | seginfo->fix_root = fixes; | |
10359 | seginfo->fix_tail = &fixes[num_recs - 1]; | |
10360 | cur_block = block; | |
10361 | frag_data = &fragP->fr_literal[0]; | |
10362 | for (i = 0; i < num_recs; i++) | |
10363 | { | |
10364 | fixS *fix = &fixes[i]; | |
10365 | assert (cur_block); | |
10366 | ||
10367 | /* Write the fixup. */ | |
10368 | if (i != num_recs - 1) | |
10369 | fix->fx_next = &fixes[i + 1]; | |
10370 | else | |
10371 | fix->fx_next = NULL; | |
10372 | fix->fx_size = 4; | |
10373 | fix->fx_done = 0; | |
10374 | fix->fx_frag = fragP; | |
43cd72b9 | 10375 | fix->fx_where = i * (8 + 4); |
e0001a05 NC |
10376 | fix->fx_addsy = section_symbol (cur_block->sec); |
10377 | fix->fx_offset = cur_block->offset; | |
10378 | fix->fx_r_type = BFD_RELOC_32; | |
10379 | fix->fx_file = "Internal Assembly"; | |
10380 | fix->fx_line = 0; | |
10381 | ||
10382 | /* Write the length. */ | |
43cd72b9 | 10383 | md_number_to_chars (&frag_data[4 + (8+4) * i], |
e0001a05 | 10384 | cur_block->size, 4); |
43cd72b9 BW |
10385 | md_number_to_chars (&frag_data[8 + (8+4) * i], |
10386 | frag_flags_to_number (&cur_block->flags), | |
10387 | 4); | |
e0001a05 NC |
10388 | cur_block = cur_block->next; |
10389 | } | |
10390 | } | |
10391 | } | |
10392 | } | |
10393 | } | |
10394 | ||
10395 | ||
7fa3d080 BW |
10396 | static segment_info_type * |
10397 | retrieve_segment_info (segT seg) | |
e0001a05 NC |
10398 | { |
10399 | segment_info_type *seginfo; | |
10400 | seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg); | |
10401 | if (!seginfo) | |
10402 | { | |
10403 | frchainS *frchainP; | |
10404 | ||
10405 | seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo)); | |
7fa3d080 | 10406 | memset ((void *) seginfo, 0, sizeof (*seginfo)); |
e0001a05 NC |
10407 | seginfo->fix_root = NULL; |
10408 | seginfo->fix_tail = NULL; | |
10409 | seginfo->bfd_section = seg; | |
10410 | seginfo->sym = 0; | |
10411 | /* We will not be dealing with these, only our special ones. */ | |
65ec77d2 | 10412 | bfd_set_section_userdata (stdoutput, seg, (void *) seginfo); |
e0001a05 NC |
10413 | |
10414 | frchainP = (frchainS *) xmalloc (sizeof (frchainS)); | |
10415 | frchainP->frch_root = NULL; | |
10416 | frchainP->frch_last = NULL; | |
10417 | frchainP->frch_next = NULL; | |
10418 | frchainP->frch_seg = seg; | |
10419 | frchainP->frch_subseg = 0; | |
10420 | frchainP->fix_root = NULL; | |
10421 | frchainP->fix_tail = NULL; | |
10422 | /* Do not init the objstack. */ | |
10423 | /* obstack_begin (&frchainP->frch_obstack, chunksize); */ | |
10424 | /* frchainP->frch_frag_now = fragP; */ | |
10425 | frchainP->frch_frag_now = NULL; | |
10426 | ||
10427 | seginfo->frchainP = frchainP; | |
10428 | } | |
10429 | ||
10430 | return seginfo; | |
10431 | } | |
10432 | ||
10433 | ||
7fa3d080 BW |
10434 | static segT |
10435 | retrieve_xtensa_section (char *sec_name) | |
e0001a05 NC |
10436 | { |
10437 | bfd *abfd = stdoutput; | |
10438 | flagword flags, out_flags, link_once_flags; | |
10439 | segT s; | |
10440 | ||
10441 | flags = bfd_get_section_flags (abfd, now_seg); | |
10442 | link_once_flags = (flags & SEC_LINK_ONCE); | |
10443 | if (link_once_flags) | |
10444 | link_once_flags |= (flags & SEC_LINK_DUPLICATES); | |
10445 | out_flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY | link_once_flags); | |
10446 | ||
10447 | s = bfd_make_section_old_way (abfd, sec_name); | |
10448 | if (s == NULL) | |
10449 | as_bad (_("could not create section %s"), sec_name); | |
10450 | if (!bfd_set_section_flags (abfd, s, out_flags)) | |
10451 | as_bad (_("invalid flag combination on section %s"), sec_name); | |
10452 | ||
10453 | return s; | |
10454 | } | |
10455 | ||
10456 | ||
7fa3d080 BW |
10457 | static bfd_boolean |
10458 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
10459 | { |
10460 | segment_info_type *seginfo = seg_info (sec); | |
10461 | fragS *fragP; | |
10462 | ||
10463 | if (seginfo && seginfo->frchainP) | |
10464 | { | |
10465 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10466 | { | |
10467 | if (property_function (fragP) | |
10468 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10469 | return TRUE; | |
10470 | } | |
10471 | } | |
10472 | return FALSE; | |
10473 | } | |
10474 | ||
10475 | ||
7fa3d080 BW |
10476 | static bfd_boolean |
10477 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
10478 | { |
10479 | segment_info_type *seginfo = seg_info (sec); | |
10480 | fragS *fragP; | |
10481 | ||
10482 | if (seginfo && seginfo->frchainP) | |
10483 | { | |
10484 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10485 | { | |
10486 | frag_flags prop_flags; | |
10487 | property_function (fragP, &prop_flags); | |
10488 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
10489 | return TRUE; | |
10490 | } | |
10491 | } | |
10492 | return FALSE; | |
10493 | } | |
10494 | ||
10495 | ||
e0001a05 NC |
10496 | /* Two types of block sections exist right now: literal and insns. */ |
10497 | ||
7fa3d080 BW |
10498 | static void |
10499 | add_xt_block_frags (segT sec, | |
10500 | segT xt_block_sec, | |
10501 | xtensa_block_info **xt_block, | |
10502 | frag_predicate property_function, | |
10503 | frag_predicate end_property_function) | |
e0001a05 NC |
10504 | { |
10505 | segment_info_type *seg_info; | |
10506 | segment_info_type *xt_seg_info; | |
10507 | bfd_vma seg_offset; | |
10508 | fragS *fragP; | |
10509 | ||
10510 | xt_seg_info = retrieve_segment_info (xt_block_sec); | |
10511 | seg_info = retrieve_segment_info (sec); | |
10512 | ||
10513 | /* Build it if needed. */ | |
10514 | while (*xt_block != NULL) | |
10515 | xt_block = &(*xt_block)->next; | |
10516 | /* We are either at NULL at the beginning or at the end. */ | |
10517 | ||
10518 | /* Walk through the frags. */ | |
10519 | seg_offset = 0; | |
10520 | ||
10521 | if (seg_info->frchainP) | |
10522 | { | |
10523 | for (fragP = seg_info->frchainP->frch_root; | |
10524 | fragP; | |
10525 | fragP = fragP->fr_next) | |
10526 | { | |
10527 | if (property_function (fragP) | |
10528 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10529 | { | |
10530 | if (*xt_block != NULL) | |
10531 | { | |
10532 | if ((*xt_block)->offset + (*xt_block)->size | |
10533 | == fragP->fr_address) | |
10534 | (*xt_block)->size += fragP->fr_fix; | |
10535 | else | |
10536 | xt_block = &((*xt_block)->next); | |
10537 | } | |
10538 | if (*xt_block == NULL) | |
10539 | { | |
43cd72b9 BW |
10540 | xtensa_block_info *new_block = (xtensa_block_info *) |
10541 | xmalloc (sizeof (xtensa_block_info)); | |
10542 | new_block->sec = sec; | |
10543 | new_block->offset = fragP->fr_address; | |
10544 | new_block->size = fragP->fr_fix; | |
10545 | new_block->next = NULL; | |
10546 | xtensa_frag_flags_init (&new_block->flags); | |
10547 | *xt_block = new_block; | |
10548 | } | |
10549 | if (end_property_function | |
10550 | && end_property_function (fragP)) | |
10551 | { | |
10552 | xt_block = &((*xt_block)->next); | |
10553 | } | |
10554 | } | |
10555 | } | |
10556 | } | |
10557 | } | |
10558 | ||
10559 | ||
10560 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
10561 | ||
7fa3d080 BW |
10562 | static bfd_boolean |
10563 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
10564 | { |
10565 | if (prop_flags->is_literal | |
10566 | || prop_flags->is_insn | |
10567 | || prop_flags->is_data | |
10568 | || prop_flags->is_unreachable) | |
10569 | return FALSE; | |
10570 | return TRUE; | |
10571 | } | |
10572 | ||
10573 | ||
7fa3d080 BW |
10574 | static void |
10575 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
10576 | { |
10577 | memset (prop_flags, 0, sizeof (frag_flags)); | |
10578 | } | |
10579 | ||
10580 | ||
7fa3d080 BW |
10581 | static void |
10582 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
10583 | { |
10584 | xtensa_frag_flags_init (prop_flags); | |
10585 | if (fragP->tc_frag_data.is_literal) | |
10586 | prop_flags->is_literal = TRUE; | |
10587 | if (fragP->tc_frag_data.is_unreachable) | |
7fa3d080 | 10588 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
10589 | else if (fragP->tc_frag_data.is_insn) |
10590 | { | |
10591 | prop_flags->is_insn = TRUE; | |
10592 | if (fragP->tc_frag_data.is_loop_target) | |
10593 | prop_flags->insn.is_loop_target = TRUE; | |
10594 | if (fragP->tc_frag_data.is_branch_target) | |
10595 | prop_flags->insn.is_branch_target = TRUE; | |
10596 | if (fragP->tc_frag_data.is_specific_opcode | |
10597 | || fragP->tc_frag_data.is_no_transform) | |
10598 | prop_flags->insn.is_no_transform = TRUE; | |
10599 | if (fragP->tc_frag_data.is_no_density) | |
10600 | prop_flags->insn.is_no_density = TRUE; | |
10601 | if (fragP->tc_frag_data.use_absolute_literals) | |
10602 | prop_flags->insn.is_abslit = TRUE; | |
10603 | } | |
10604 | if (fragP->tc_frag_data.is_align) | |
10605 | { | |
10606 | prop_flags->is_align = TRUE; | |
10607 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
10608 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10609 | prop_flags->is_data = TRUE; | |
10610 | } | |
10611 | } | |
10612 | ||
10613 | ||
7fa3d080 BW |
10614 | static bfd_vma |
10615 | frag_flags_to_number (const frag_flags *prop_flags) | |
43cd72b9 BW |
10616 | { |
10617 | bfd_vma num = 0; | |
10618 | if (prop_flags->is_literal) | |
10619 | num |= XTENSA_PROP_LITERAL; | |
10620 | if (prop_flags->is_insn) | |
10621 | num |= XTENSA_PROP_INSN; | |
10622 | if (prop_flags->is_data) | |
10623 | num |= XTENSA_PROP_DATA; | |
10624 | if (prop_flags->is_unreachable) | |
10625 | num |= XTENSA_PROP_UNREACHABLE; | |
10626 | if (prop_flags->insn.is_loop_target) | |
10627 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
10628 | if (prop_flags->insn.is_branch_target) | |
10629 | { | |
10630 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
10631 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
10632 | } | |
10633 | ||
10634 | if (prop_flags->insn.is_no_density) | |
10635 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
10636 | if (prop_flags->insn.is_no_transform) | |
10637 | num |= XTENSA_PROP_INSN_NO_TRANSFORM; | |
10638 | if (prop_flags->insn.is_no_reorder) | |
10639 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
10640 | if (prop_flags->insn.is_abslit) | |
10641 | num |= XTENSA_PROP_INSN_ABSLIT; | |
10642 | ||
10643 | if (prop_flags->is_align) | |
10644 | { | |
10645 | num |= XTENSA_PROP_ALIGN; | |
10646 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
10647 | } | |
10648 | ||
10649 | return num; | |
10650 | } | |
10651 | ||
10652 | ||
10653 | static bfd_boolean | |
7fa3d080 BW |
10654 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
10655 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
10656 | { |
10657 | /* Cannot combine with an end marker. */ | |
10658 | ||
10659 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
10660 | return FALSE; | |
10661 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
10662 | return FALSE; | |
10663 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
10664 | return FALSE; | |
10665 | ||
10666 | if (prop_flags_1->is_insn) | |
10667 | { | |
10668 | /* Properties of the beginning of the frag. */ | |
10669 | if (prop_flags_2->insn.is_loop_target) | |
10670 | return FALSE; | |
10671 | if (prop_flags_2->insn.is_branch_target) | |
10672 | return FALSE; | |
10673 | if (prop_flags_1->insn.is_no_density != | |
10674 | prop_flags_2->insn.is_no_density) | |
10675 | return FALSE; | |
10676 | if (prop_flags_1->insn.is_no_transform != | |
10677 | prop_flags_2->insn.is_no_transform) | |
10678 | return FALSE; | |
10679 | if (prop_flags_1->insn.is_no_reorder != | |
10680 | prop_flags_2->insn.is_no_reorder) | |
10681 | return FALSE; | |
10682 | if (prop_flags_1->insn.is_abslit != | |
10683 | prop_flags_2->insn.is_abslit) | |
10684 | return FALSE; | |
10685 | } | |
10686 | ||
10687 | if (prop_flags_1->is_align) | |
10688 | return FALSE; | |
10689 | ||
10690 | return TRUE; | |
10691 | } | |
10692 | ||
10693 | ||
7fa3d080 BW |
10694 | static bfd_vma |
10695 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
10696 | { |
10697 | bfd_vma end_addr; | |
d77b99c9 | 10698 | unsigned align_bits; |
43cd72b9 BW |
10699 | |
10700 | if (!xt_block->flags.is_align) | |
10701 | return xt_block->size; | |
10702 | ||
10703 | end_addr = xt_block->offset + xt_block->size; | |
10704 | align_bits = xt_block->flags.alignment; | |
10705 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
10706 | return end_addr - xt_block->offset; | |
10707 | } | |
10708 | ||
10709 | ||
10710 | static bfd_boolean | |
7fa3d080 BW |
10711 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
10712 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
10713 | { |
10714 | if (xt_block->sec != xt_block_2->sec) | |
10715 | return FALSE; | |
10716 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
10717 | != xt_block_2->offset) | |
10718 | return FALSE; | |
10719 | ||
10720 | if (xt_block_2->size == 0 | |
10721 | && (!xt_block_2->flags.is_unreachable | |
10722 | || xt_block->flags.is_unreachable)) | |
10723 | { | |
10724 | if (xt_block_2->flags.is_align | |
10725 | && xt_block->flags.is_align) | |
10726 | { | |
10727 | /* Nothing needed. */ | |
10728 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
10729 | return TRUE; | |
10730 | } | |
10731 | else | |
10732 | { | |
10733 | if (xt_block_2->flags.is_align) | |
10734 | { | |
10735 | /* Push alignment to previous entry. */ | |
10736 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
10737 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10738 | } | |
10739 | return TRUE; | |
10740 | } | |
10741 | } | |
10742 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
10743 | &xt_block_2->flags)) | |
10744 | return FALSE; | |
10745 | ||
10746 | xt_block->size += xt_block_2->size; | |
10747 | ||
10748 | if (xt_block_2->flags.is_align) | |
10749 | { | |
10750 | xt_block->flags.is_align = TRUE; | |
10751 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10752 | } | |
10753 | ||
10754 | return TRUE; | |
10755 | } | |
10756 | ||
10757 | ||
7fa3d080 BW |
10758 | static void |
10759 | add_xt_prop_frags (segT sec, | |
10760 | segT xt_block_sec, | |
10761 | xtensa_block_info **xt_block, | |
10762 | frag_flags_fn property_function) | |
43cd72b9 BW |
10763 | { |
10764 | segment_info_type *seg_info; | |
10765 | segment_info_type *xt_seg_info; | |
10766 | bfd_vma seg_offset; | |
10767 | fragS *fragP; | |
10768 | ||
10769 | xt_seg_info = retrieve_segment_info (xt_block_sec); | |
10770 | seg_info = retrieve_segment_info (sec); | |
10771 | /* Build it if needed. */ | |
10772 | while (*xt_block != NULL) | |
10773 | { | |
10774 | xt_block = &(*xt_block)->next; | |
10775 | } | |
10776 | /* We are either at NULL at the beginning or at the end. */ | |
10777 | ||
10778 | /* Walk through the frags. */ | |
10779 | seg_offset = 0; | |
10780 | ||
10781 | if (seg_info->frchainP) | |
10782 | { | |
10783 | for (fragP = seg_info->frchainP->frch_root; fragP; | |
10784 | fragP = fragP->fr_next) | |
10785 | { | |
10786 | xtensa_block_info tmp_block; | |
10787 | tmp_block.sec = sec; | |
10788 | tmp_block.offset = fragP->fr_address; | |
10789 | tmp_block.size = fragP->fr_fix; | |
10790 | tmp_block.next = NULL; | |
10791 | property_function (fragP, &tmp_block.flags); | |
10792 | ||
10793 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
10794 | /* && fragP->fr_fix != 0) */ | |
10795 | { | |
10796 | if ((*xt_block) == NULL | |
10797 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
10798 | { | |
10799 | xtensa_block_info *new_block; | |
10800 | if ((*xt_block) != NULL) | |
10801 | xt_block = &(*xt_block)->next; | |
10802 | new_block = (xtensa_block_info *) | |
10803 | xmalloc (sizeof (xtensa_block_info)); | |
10804 | *new_block = tmp_block; | |
10805 | *xt_block = new_block; | |
10806 | } | |
10807 | } | |
10808 | } | |
10809 | } | |
10810 | } | |
10811 | ||
10812 | \f | |
10813 | /* op_placement_info_table */ | |
10814 | ||
10815 | /* op_placement_info makes it easier to determine which | |
10816 | ops can go in which slots. */ | |
10817 | ||
10818 | static void | |
7fa3d080 | 10819 | init_op_placement_info_table (void) |
43cd72b9 BW |
10820 | { |
10821 | xtensa_isa isa = xtensa_default_isa; | |
10822 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
10823 | xtensa_opcode opcode; | |
10824 | xtensa_format fmt; | |
10825 | int slot; | |
10826 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
10827 | ||
10828 | op_placement_table = (op_placement_info_table) | |
10829 | xmalloc (sizeof (op_placement_info) * num_opcodes); | |
10830 | assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); | |
10831 | ||
10832 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
10833 | { | |
10834 | op_placement_info *opi = &op_placement_table[opcode]; | |
10835 | /* FIXME: Make tinsn allocation dynamic. */ | |
10836 | if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS) | |
10837 | as_fatal (_("too many operands in instruction")); | |
43cd72b9 BW |
10838 | opi->narrowest = XTENSA_UNDEFINED; |
10839 | opi->narrowest_size = 0x7F; | |
b2d179be | 10840 | opi->narrowest_slot = 0; |
43cd72b9 BW |
10841 | opi->formats = 0; |
10842 | opi->num_formats = 0; | |
10843 | opi->issuef = 0; | |
10844 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
10845 | { | |
10846 | opi->slots[fmt] = 0; | |
10847 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
10848 | { | |
10849 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
10850 | { | |
10851 | int fmt_length = xtensa_format_length (isa, fmt); | |
10852 | opi->issuef++; | |
10853 | set_bit (fmt, opi->formats); | |
10854 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
10855 | if (fmt_length < opi->narrowest_size |
10856 | || (fmt_length == opi->narrowest_size | |
10857 | && (xtensa_format_num_slots (isa, fmt) | |
10858 | < xtensa_format_num_slots (isa, | |
10859 | opi->narrowest)))) | |
43cd72b9 BW |
10860 | { |
10861 | opi->narrowest = fmt; | |
10862 | opi->narrowest_size = fmt_length; | |
b2d179be | 10863 | opi->narrowest_slot = slot; |
43cd72b9 | 10864 | } |
e0001a05 NC |
10865 | } |
10866 | } | |
43cd72b9 BW |
10867 | if (opi->formats) |
10868 | opi->num_formats++; | |
e0001a05 NC |
10869 | } |
10870 | } | |
43cd72b9 BW |
10871 | xtensa_insnbuf_free (isa, ibuf); |
10872 | } | |
10873 | ||
10874 | ||
10875 | bfd_boolean | |
7fa3d080 | 10876 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
10877 | { |
10878 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
10879 | } | |
10880 | ||
10881 | ||
10882 | /* If the opcode is available in a single slot format, return its size. */ | |
10883 | ||
7fa3d080 BW |
10884 | static int |
10885 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 10886 | { |
b2d179be | 10887 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
10888 | } |
10889 | ||
10890 | ||
7fa3d080 BW |
10891 | static xtensa_format |
10892 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 10893 | { |
b2d179be BW |
10894 | return op_placement_table[opcode].narrowest; |
10895 | } | |
10896 | ||
10897 | ||
10898 | static int | |
10899 | xg_get_single_slot (xtensa_opcode opcode) | |
10900 | { | |
10901 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
10902 | } |
10903 | ||
10904 | \f | |
10905 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
10906 | ||
10907 | void | |
7fa3d080 | 10908 | istack_init (IStack *stack) |
e0001a05 NC |
10909 | { |
10910 | memset (stack, 0, sizeof (IStack)); | |
10911 | stack->ninsn = 0; | |
10912 | } | |
10913 | ||
10914 | ||
10915 | bfd_boolean | |
7fa3d080 | 10916 | istack_empty (IStack *stack) |
e0001a05 NC |
10917 | { |
10918 | return (stack->ninsn == 0); | |
10919 | } | |
10920 | ||
10921 | ||
10922 | bfd_boolean | |
7fa3d080 | 10923 | istack_full (IStack *stack) |
e0001a05 NC |
10924 | { |
10925 | return (stack->ninsn == MAX_ISTACK); | |
10926 | } | |
10927 | ||
10928 | ||
10929 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 10930 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
10931 | |
10932 | TInsn * | |
7fa3d080 | 10933 | istack_top (IStack *stack) |
e0001a05 NC |
10934 | { |
10935 | int rec = stack->ninsn - 1; | |
10936 | assert (!istack_empty (stack)); | |
10937 | return &stack->insn[rec]; | |
10938 | } | |
10939 | ||
10940 | ||
10941 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 10942 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
10943 | |
10944 | void | |
7fa3d080 | 10945 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
10946 | { |
10947 | int rec = stack->ninsn; | |
10948 | assert (!istack_full (stack)); | |
43cd72b9 | 10949 | stack->insn[rec] = *insn; |
e0001a05 NC |
10950 | stack->ninsn++; |
10951 | } | |
10952 | ||
10953 | ||
10954 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 10955 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
10956 | |
10957 | TInsn * | |
7fa3d080 | 10958 | istack_push_space (IStack *stack) |
e0001a05 NC |
10959 | { |
10960 | int rec = stack->ninsn; | |
10961 | TInsn *insn; | |
10962 | assert (!istack_full (stack)); | |
10963 | insn = &stack->insn[rec]; | |
10964 | memset (insn, 0, sizeof (TInsn)); | |
10965 | stack->ninsn++; | |
10966 | return insn; | |
10967 | } | |
10968 | ||
10969 | ||
10970 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 10971 | istack_empty () returns TRUE. */ |
e0001a05 NC |
10972 | |
10973 | void | |
7fa3d080 | 10974 | istack_pop (IStack *stack) |
e0001a05 NC |
10975 | { |
10976 | int rec = stack->ninsn - 1; | |
10977 | assert (!istack_empty (stack)); | |
10978 | stack->ninsn--; | |
10979 | memset (&stack->insn[rec], 0, sizeof (TInsn)); | |
10980 | } | |
10981 | ||
10982 | \f | |
10983 | /* TInsn functions. */ | |
10984 | ||
10985 | void | |
7fa3d080 | 10986 | tinsn_init (TInsn *dst) |
e0001a05 NC |
10987 | { |
10988 | memset (dst, 0, sizeof (TInsn)); | |
10989 | } | |
10990 | ||
10991 | ||
e0001a05 NC |
10992 | /* Get the ``num''th token of the TInsn. |
10993 | It is illegal to call this if num > insn->ntoks. */ | |
10994 | ||
10995 | expressionS * | |
7fa3d080 | 10996 | tinsn_get_tok (TInsn *insn, int num) |
e0001a05 NC |
10997 | { |
10998 | assert (num < insn->ntok); | |
10999 | return &insn->tok[num]; | |
11000 | } | |
11001 | ||
11002 | ||
43cd72b9 | 11003 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
11004 | |
11005 | static bfd_boolean | |
7fa3d080 | 11006 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
11007 | { |
11008 | int i; | |
11009 | int n = insn->ntok; | |
11010 | ||
11011 | assert (insn->insn_type == ITYPE_INSN); | |
11012 | ||
11013 | for (i = 0; i < n; ++i) | |
11014 | { | |
11015 | switch (insn->tok[i].X_op) | |
11016 | { | |
11017 | case O_register: | |
11018 | case O_constant: | |
11019 | break; | |
11020 | default: | |
11021 | return TRUE; | |
11022 | } | |
11023 | } | |
11024 | return FALSE; | |
11025 | } | |
11026 | ||
11027 | ||
11028 | bfd_boolean | |
7fa3d080 | 11029 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 11030 | { |
43cd72b9 | 11031 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
11032 | int i; |
11033 | int n = insn->ntok; | |
11034 | ||
11035 | assert (insn->insn_type == ITYPE_INSN); | |
11036 | ||
11037 | for (i = 0; i < n; ++i) | |
11038 | { | |
11039 | switch (insn->tok[i].X_op) | |
11040 | { | |
11041 | case O_register: | |
11042 | case O_constant: | |
11043 | break; | |
43cd72b9 BW |
11044 | case O_big: |
11045 | case O_illegal: | |
11046 | case O_absent: | |
11047 | /* Errors for these types are caught later. */ | |
11048 | break; | |
11049 | case O_hi16: | |
11050 | case O_lo16: | |
e0001a05 | 11051 | default: |
43cd72b9 BW |
11052 | /* Symbolic immediates are only allowed on the last immediate |
11053 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 11054 | support non-PC-relative relocations. */ |
43cd72b9 BW |
11055 | if (i != get_relaxable_immed (insn->opcode) |
11056 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
11057 | && insn->opcode != xtensa_const16_opcode)) | |
11058 | { | |
431ad2d0 | 11059 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
11060 | return TRUE; |
11061 | } | |
e0001a05 NC |
11062 | } |
11063 | } | |
11064 | return FALSE; | |
11065 | } | |
11066 | ||
11067 | ||
11068 | /* For assembly code with complex expressions (e.g. subtraction), | |
11069 | we have to build them in the literal pool so that | |
11070 | their results are calculated correctly after relaxation. | |
11071 | The relaxation only handles expressions that | |
11072 | boil down to SYMBOL + OFFSET. */ | |
11073 | ||
11074 | static bfd_boolean | |
7fa3d080 | 11075 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
11076 | { |
11077 | int i; | |
11078 | int n = insn->ntok; | |
11079 | assert (insn->insn_type == ITYPE_INSN); | |
11080 | for (i = 0; i < n; ++i) | |
11081 | { | |
11082 | switch (insn->tok[i].X_op) | |
11083 | { | |
11084 | case O_register: | |
11085 | case O_constant: | |
11086 | case O_symbol: | |
43cd72b9 BW |
11087 | case O_lo16: |
11088 | case O_hi16: | |
e0001a05 NC |
11089 | break; |
11090 | default: | |
11091 | return TRUE; | |
11092 | } | |
11093 | } | |
11094 | return FALSE; | |
11095 | } | |
11096 | ||
11097 | ||
b2d179be BW |
11098 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
11099 | Return TRUE if there is a symbol in the immediate field. This | |
11100 | function assumes that: | |
11101 | 1) The number of operands are correct. | |
11102 | 2) The insn_type is ITYPE_INSN. | |
11103 | 3) The opcode can be encoded in the specified format and slot. | |
11104 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
11105 | |
11106 | static bfd_boolean | |
7fa3d080 BW |
11107 | tinsn_to_slotbuf (xtensa_format fmt, |
11108 | int slot, | |
11109 | TInsn *tinsn, | |
11110 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
11111 | { |
11112 | xtensa_isa isa = xtensa_default_isa; | |
11113 | xtensa_opcode opcode = tinsn->opcode; | |
11114 | bfd_boolean has_fixup = FALSE; | |
11115 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11116 | int i; | |
11117 | ||
43cd72b9 BW |
11118 | assert (tinsn->insn_type == ITYPE_INSN); |
11119 | if (noperands != tinsn->ntok) | |
11120 | as_fatal (_("operand number mismatch")); | |
11121 | ||
11122 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
11123 | { | |
11124 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
11125 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
11126 | return FALSE; | |
11127 | } | |
11128 | ||
11129 | for (i = 0; i < noperands; i++) | |
11130 | { | |
11131 | expressionS *expr = &tinsn->tok[i]; | |
d77b99c9 BW |
11132 | int rc; |
11133 | unsigned line; | |
43cd72b9 BW |
11134 | char *file_name; |
11135 | uint32 opnd_value; | |
11136 | ||
11137 | switch (expr->X_op) | |
11138 | { | |
11139 | case O_register: | |
11140 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11141 | break; | |
11142 | /* The register number has already been checked in | |
11143 | expression_maybe_register, so we don't need to check here. */ | |
11144 | opnd_value = expr->X_add_number; | |
11145 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); | |
11146 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
11147 | opnd_value); | |
11148 | if (rc != 0) | |
11149 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
11150 | break; | |
11151 | ||
11152 | case O_constant: | |
11153 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11154 | break; | |
11155 | as_where (&file_name, &line); | |
11156 | /* It is a constant and we called this function | |
11157 | then we have to try to fit it. */ | |
11158 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
e0001a05 NC |
11159 | expr->X_add_number, file_name, line); |
11160 | break; | |
11161 | ||
e0001a05 NC |
11162 | default: |
11163 | has_fixup = TRUE; | |
11164 | break; | |
11165 | } | |
11166 | } | |
43cd72b9 | 11167 | |
e0001a05 NC |
11168 | return has_fixup; |
11169 | } | |
11170 | ||
11171 | ||
b2d179be BW |
11172 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
11173 | into a multi-slot instruction, fill the other slots with NOPs. | |
11174 | Return TRUE if there is a symbol in the immediate field. See also the | |
11175 | assumptions listed for tinsn_to_slotbuf. */ | |
11176 | ||
11177 | static bfd_boolean | |
11178 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
11179 | { | |
11180 | static xtensa_insnbuf slotbuf = 0; | |
11181 | static vliw_insn vinsn; | |
11182 | xtensa_isa isa = xtensa_default_isa; | |
11183 | bfd_boolean has_fixup = FALSE; | |
11184 | int i; | |
11185 | ||
11186 | if (!slotbuf) | |
11187 | { | |
11188 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11189 | xg_init_vinsn (&vinsn); | |
11190 | } | |
11191 | ||
11192 | xg_clear_vinsn (&vinsn); | |
11193 | ||
11194 | bundle_tinsn (tinsn, &vinsn); | |
11195 | ||
11196 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
11197 | ||
11198 | for (i = 0; i < vinsn.num_slots; i++) | |
11199 | { | |
11200 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
11201 | has_fixup |= | |
11202 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
11203 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
11204 | } | |
11205 | ||
11206 | return has_fixup; | |
11207 | } | |
11208 | ||
11209 | ||
43cd72b9 | 11210 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 11211 | |
7fa3d080 BW |
11212 | static bfd_boolean |
11213 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
11214 | { |
11215 | xtensa_isa isa = xtensa_default_isa; | |
11216 | xtensa_opcode opcode = insn->opcode; | |
11217 | ||
11218 | if (opcode == XTENSA_UNDEFINED) | |
11219 | { | |
11220 | as_bad (_("invalid opcode")); | |
11221 | return TRUE; | |
11222 | } | |
11223 | ||
43cd72b9 | 11224 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
11225 | { |
11226 | as_bad (_("too few operands")); | |
11227 | return TRUE; | |
11228 | } | |
11229 | ||
43cd72b9 | 11230 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
11231 | { |
11232 | as_bad (_("too many operands")); | |
11233 | return TRUE; | |
11234 | } | |
11235 | return FALSE; | |
11236 | } | |
11237 | ||
11238 | ||
11239 | /* Load an instruction from its encoded form. */ | |
11240 | ||
11241 | static void | |
7fa3d080 | 11242 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 11243 | { |
43cd72b9 | 11244 | vliw_insn vinsn; |
e0001a05 | 11245 | |
43cd72b9 BW |
11246 | xg_init_vinsn (&vinsn); |
11247 | vinsn_from_chars (&vinsn, f); | |
11248 | ||
11249 | *tinsn = vinsn.slots[slot]; | |
11250 | xg_free_vinsn (&vinsn); | |
11251 | } | |
e0001a05 | 11252 | |
43cd72b9 BW |
11253 | |
11254 | static void | |
7fa3d080 BW |
11255 | tinsn_from_insnbuf (TInsn *tinsn, |
11256 | xtensa_insnbuf slotbuf, | |
11257 | xtensa_format fmt, | |
11258 | int slot) | |
43cd72b9 BW |
11259 | { |
11260 | int i; | |
11261 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
11262 | |
11263 | /* Find the immed. */ | |
43cd72b9 BW |
11264 | tinsn_init (tinsn); |
11265 | tinsn->insn_type = ITYPE_INSN; | |
11266 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
11267 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
11268 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
11269 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 11270 | { |
43cd72b9 BW |
11271 | set_expr_const (&tinsn->tok[i], |
11272 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
11273 | tinsn->opcode, i)); | |
e0001a05 NC |
11274 | } |
11275 | } | |
11276 | ||
11277 | ||
11278 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
11279 | ||
11280 | static void | |
7fa3d080 | 11281 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 11282 | { |
43cd72b9 | 11283 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
11284 | int opnum; |
11285 | ||
43cd72b9 | 11286 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
11287 | { |
11288 | opnum = get_relaxable_immed (opcode); | |
43cd72b9 | 11289 | assert (opnum >= 0); |
e7da6241 BW |
11290 | set_expr_symbol_offset (&tinsn->tok[opnum], |
11291 | fragP->tc_frag_data.slot_symbols[slot], | |
11292 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 NC |
11293 | } |
11294 | } | |
11295 | ||
11296 | ||
11297 | static int | |
7fa3d080 | 11298 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
11299 | { |
11300 | int i; | |
11301 | int text_bytes = 0; | |
11302 | ||
11303 | for (i = 0; i < istack->ninsn; i++) | |
11304 | { | |
43cd72b9 BW |
11305 | TInsn *tinsn = &istack->insn[i]; |
11306 | if (tinsn->insn_type == ITYPE_INSN) | |
11307 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
11308 | } |
11309 | return text_bytes; | |
11310 | } | |
11311 | ||
11312 | ||
11313 | static int | |
7fa3d080 | 11314 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
11315 | { |
11316 | int i; | |
11317 | int lit_bytes = 0; | |
11318 | ||
11319 | for (i = 0; i < istack->ninsn; i++) | |
11320 | { | |
43cd72b9 BW |
11321 | TInsn *tinsn = &istack->insn[i]; |
11322 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
11323 | lit_bytes += 4; |
11324 | } | |
11325 | return lit_bytes; | |
11326 | } | |
11327 | ||
43cd72b9 BW |
11328 | \f |
11329 | /* vliw_insn functions. */ | |
11330 | ||
7fa3d080 BW |
11331 | static void |
11332 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11333 | { |
11334 | int i; | |
11335 | xtensa_isa isa = xtensa_default_isa; | |
11336 | ||
11337 | xg_clear_vinsn (v); | |
11338 | ||
11339 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
11340 | if (v->insnbuf == NULL) | |
11341 | as_fatal (_("out of memory")); | |
11342 | ||
11343 | for (i = 0; i < MAX_SLOTS; i++) | |
11344 | { | |
43cd72b9 BW |
11345 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
11346 | if (v->slotbuf[i] == NULL) | |
11347 | as_fatal (_("out of memory")); | |
11348 | } | |
11349 | } | |
11350 | ||
11351 | ||
7fa3d080 BW |
11352 | static void |
11353 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11354 | { |
11355 | int i; | |
65738a7d BW |
11356 | |
11357 | memset (v, 0, offsetof (vliw_insn, insnbuf)); | |
11358 | ||
43cd72b9 BW |
11359 | v->format = XTENSA_UNDEFINED; |
11360 | v->num_slots = 0; | |
11361 | v->inside_bundle = FALSE; | |
11362 | ||
11363 | if (xt_saved_debug_type != DEBUG_NONE) | |
11364 | debug_type = xt_saved_debug_type; | |
11365 | ||
11366 | for (i = 0; i < MAX_SLOTS; i++) | |
65738a7d | 11367 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
11368 | } |
11369 | ||
11370 | ||
7fa3d080 BW |
11371 | static bfd_boolean |
11372 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
11373 | { |
11374 | int i; | |
c138bc38 | 11375 | |
43cd72b9 BW |
11376 | for (i = 0; i < v->num_slots; i++) |
11377 | { | |
11378 | if (v->slots[i].is_specific_opcode) | |
11379 | return TRUE; | |
11380 | } | |
11381 | return FALSE; | |
11382 | } | |
11383 | ||
11384 | ||
7fa3d080 BW |
11385 | static void |
11386 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11387 | { |
11388 | int i; | |
11389 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
11390 | for (i = 0; i < MAX_SLOTS; i++) | |
11391 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); | |
11392 | } | |
11393 | ||
11394 | ||
e7da6241 BW |
11395 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
11396 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
11397 | |
11398 | static bfd_boolean | |
7fa3d080 BW |
11399 | vinsn_to_insnbuf (vliw_insn *vinsn, |
11400 | char *frag_offset, | |
11401 | fragS *fragP, | |
11402 | bfd_boolean record_fixup) | |
43cd72b9 BW |
11403 | { |
11404 | xtensa_isa isa = xtensa_default_isa; | |
11405 | xtensa_format fmt = vinsn->format; | |
11406 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
11407 | int slot; | |
11408 | bfd_boolean has_fixup = FALSE; | |
11409 | ||
11410 | xtensa_format_encode (isa, fmt, insnbuf); | |
11411 | ||
11412 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
11413 | { | |
11414 | TInsn *tinsn = &vinsn->slots[slot]; | |
11415 | bfd_boolean tinsn_has_fixup = | |
11416 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
11417 | vinsn->slotbuf[slot]); | |
11418 | ||
11419 | xtensa_format_set_slot (isa, fmt, slot, | |
11420 | insnbuf, vinsn->slotbuf[slot]); | |
e7da6241 | 11421 | if (tinsn_has_fixup) |
43cd72b9 BW |
11422 | { |
11423 | int i; | |
11424 | xtensa_opcode opcode = tinsn->opcode; | |
11425 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11426 | has_fixup = TRUE; | |
11427 | ||
11428 | for (i = 0; i < noperands; i++) | |
11429 | { | |
11430 | expressionS* expr = &tinsn->tok[i]; | |
11431 | switch (expr->X_op) | |
11432 | { | |
11433 | case O_symbol: | |
11434 | case O_lo16: | |
11435 | case O_hi16: | |
11436 | if (get_relaxable_immed (opcode) == i) | |
11437 | { | |
e7da6241 BW |
11438 | /* Add a fix record for the instruction, except if this |
11439 | function is being called prior to relaxation, i.e., | |
11440 | if record_fixup is false, and the instruction might | |
11441 | be relaxed later. */ | |
11442 | if (record_fixup | |
11443 | || tinsn->is_specific_opcode | |
11444 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 11445 | { |
e7da6241 BW |
11446 | xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP, |
11447 | frag_offset - fragP->fr_literal); | |
43cd72b9 BW |
11448 | } |
11449 | else | |
11450 | { | |
e7da6241 BW |
11451 | if (expr->X_op != O_symbol) |
11452 | as_bad (_("invalid operand")); | |
43cd72b9 BW |
11453 | tinsn->symbol = expr->X_add_symbol; |
11454 | tinsn->offset = expr->X_add_number; | |
11455 | } | |
11456 | } | |
11457 | else | |
e7da6241 | 11458 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
11459 | break; |
11460 | ||
11461 | case O_constant: | |
11462 | case O_register: | |
11463 | break; | |
11464 | ||
43cd72b9 | 11465 | default: |
e7da6241 | 11466 | as_bad (_("expression too complex")); |
43cd72b9 BW |
11467 | break; |
11468 | } | |
11469 | } | |
11470 | } | |
11471 | } | |
11472 | ||
11473 | return has_fixup; | |
11474 | } | |
11475 | ||
11476 | ||
11477 | static void | |
7fa3d080 | 11478 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
11479 | { |
11480 | static xtensa_insnbuf insnbuf = NULL; | |
11481 | static xtensa_insnbuf slotbuf = NULL; | |
11482 | int i; | |
11483 | xtensa_format fmt; | |
11484 | xtensa_isa isa = xtensa_default_isa; | |
11485 | ||
11486 | if (!insnbuf) | |
11487 | { | |
11488 | insnbuf = xtensa_insnbuf_alloc (isa); | |
11489 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11490 | } | |
11491 | ||
d77b99c9 | 11492 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
11493 | fmt = xtensa_format_decode (isa, insnbuf); |
11494 | if (fmt == XTENSA_UNDEFINED) | |
11495 | as_fatal (_("cannot decode instruction format")); | |
11496 | vinsn->format = fmt; | |
11497 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
11498 | ||
11499 | for (i = 0; i < vinsn->num_slots; i++) | |
11500 | { | |
11501 | TInsn *tinsn = &vinsn->slots[i]; | |
11502 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
11503 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
11504 | } | |
11505 | } | |
11506 | ||
e0001a05 NC |
11507 | \f |
11508 | /* Expression utilities. */ | |
11509 | ||
43cd72b9 | 11510 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
11511 | |
11512 | bfd_boolean | |
7fa3d080 | 11513 | expr_is_const (const expressionS *s) |
e0001a05 NC |
11514 | { |
11515 | return (s->X_op == O_constant); | |
11516 | } | |
11517 | ||
11518 | ||
11519 | /* Get the expression constant. | |
43cd72b9 | 11520 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
11521 | |
11522 | offsetT | |
7fa3d080 | 11523 | get_expr_const (const expressionS *s) |
e0001a05 NC |
11524 | { |
11525 | assert (expr_is_const (s)); | |
11526 | return s->X_add_number; | |
11527 | } | |
11528 | ||
11529 | ||
11530 | /* Set the expression to a constant value. */ | |
11531 | ||
11532 | void | |
7fa3d080 | 11533 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
11534 | { |
11535 | s->X_op = O_constant; | |
11536 | s->X_add_number = val; | |
11537 | s->X_add_symbol = NULL; | |
11538 | s->X_op_symbol = NULL; | |
11539 | } | |
11540 | ||
11541 | ||
43cd72b9 | 11542 | bfd_boolean |
7fa3d080 | 11543 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
11544 | { |
11545 | return (s->X_op == O_register); | |
11546 | } | |
11547 | ||
11548 | ||
11549 | /* Get the expression constant. | |
11550 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
11551 | ||
11552 | offsetT | |
7fa3d080 | 11553 | get_expr_register (const expressionS *s) |
43cd72b9 BW |
11554 | { |
11555 | assert (expr_is_register (s)); | |
11556 | return s->X_add_number; | |
11557 | } | |
11558 | ||
11559 | ||
e0001a05 NC |
11560 | /* Set the expression to a symbol + constant offset. */ |
11561 | ||
11562 | void | |
7fa3d080 | 11563 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
11564 | { |
11565 | s->X_op = O_symbol; | |
11566 | s->X_add_symbol = sym; | |
11567 | s->X_op_symbol = NULL; /* unused */ | |
11568 | s->X_add_number = offset; | |
11569 | } | |
11570 | ||
11571 | ||
43cd72b9 BW |
11572 | /* Return TRUE if the two expressions are equal. */ |
11573 | ||
e0001a05 | 11574 | bfd_boolean |
7fa3d080 | 11575 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
11576 | { |
11577 | if (s1->X_op != s2->X_op) | |
11578 | return FALSE; | |
11579 | if (s1->X_add_symbol != s2->X_add_symbol) | |
11580 | return FALSE; | |
11581 | if (s1->X_op_symbol != s2->X_op_symbol) | |
11582 | return FALSE; | |
11583 | if (s1->X_add_number != s2->X_add_number) | |
11584 | return FALSE; | |
11585 | return TRUE; | |
11586 | } | |
11587 | ||
11588 | ||
11589 | static void | |
7fa3d080 | 11590 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
11591 | { |
11592 | memcpy (dst, src, sizeof (expressionS)); | |
11593 | } | |
11594 | ||
11595 | \f | |
9456465c | 11596 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
11597 | |
11598 | struct rename_section_struct | |
11599 | { | |
11600 | char *old_name; | |
11601 | char *new_name; | |
11602 | struct rename_section_struct *next; | |
11603 | }; | |
11604 | ||
11605 | static struct rename_section_struct *section_rename; | |
11606 | ||
11607 | ||
9456465c BW |
11608 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
11609 | entries to the section_rename list. Note: Specifying multiple | |
11610 | renamings separated by colons is not documented and is retained only | |
11611 | for backward compatibility. */ | |
e0001a05 | 11612 | |
7fa3d080 BW |
11613 | static void |
11614 | build_section_rename (const char *arg) | |
e0001a05 | 11615 | { |
9456465c | 11616 | struct rename_section_struct *r; |
e0001a05 NC |
11617 | char *this_arg = NULL; |
11618 | char *next_arg = NULL; | |
11619 | ||
9456465c | 11620 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 11621 | { |
9456465c BW |
11622 | char *old_name, *new_name; |
11623 | ||
e0001a05 NC |
11624 | if (this_arg) |
11625 | { | |
11626 | next_arg = strchr (this_arg, ':'); | |
11627 | if (next_arg) | |
11628 | { | |
11629 | *next_arg = '\0'; | |
11630 | next_arg++; | |
11631 | } | |
11632 | } | |
e0001a05 | 11633 | |
9456465c BW |
11634 | old_name = this_arg; |
11635 | new_name = strchr (this_arg, '='); | |
e0001a05 | 11636 | |
9456465c BW |
11637 | if (*old_name == '\0') |
11638 | { | |
11639 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
11640 | continue; | |
11641 | } | |
11642 | if (!new_name || new_name[1] == '\0') | |
11643 | { | |
11644 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
11645 | old_name); | |
11646 | continue; | |
11647 | } | |
11648 | *new_name = '\0'; | |
11649 | new_name++; | |
e0001a05 | 11650 | |
9456465c BW |
11651 | /* Check for invalid section renaming. */ |
11652 | for (r = section_rename; r != NULL; r = r->next) | |
11653 | { | |
11654 | if (strcmp (r->old_name, old_name) == 0) | |
11655 | as_bad (_("section %s renamed multiple times"), old_name); | |
11656 | if (strcmp (r->new_name, new_name) == 0) | |
11657 | as_bad (_("multiple sections remapped to output section %s"), | |
11658 | new_name); | |
11659 | } | |
e0001a05 | 11660 | |
9456465c BW |
11661 | /* Now add it. */ |
11662 | r = (struct rename_section_struct *) | |
11663 | xmalloc (sizeof (struct rename_section_struct)); | |
11664 | r->old_name = xstrdup (old_name); | |
11665 | r->new_name = xstrdup (new_name); | |
11666 | r->next = section_rename; | |
11667 | section_rename = r; | |
e0001a05 | 11668 | } |
e0001a05 NC |
11669 | } |
11670 | ||
11671 | ||
9456465c BW |
11672 | char * |
11673 | xtensa_section_rename (char *name) | |
e0001a05 NC |
11674 | { |
11675 | struct rename_section_struct *r = section_rename; | |
11676 | ||
11677 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
11678 | { |
11679 | if (strcmp (r->old_name, name) == 0) | |
11680 | return r->new_name; | |
11681 | } | |
e0001a05 NC |
11682 | |
11683 | return name; | |
11684 | } |