Commit | Line | Data |
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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
63a7429b | 2 | Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
e0001a05 NC |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 | 20 | |
43cd72b9 | 21 | #include <limits.h> |
e0001a05 NC |
22 | #include "as.h" |
23 | #include "sb.h" | |
24 | #include "safe-ctype.h" | |
25 | #include "tc-xtensa.h" | |
e0001a05 NC |
26 | #include "subsegs.h" |
27 | #include "xtensa-relax.h" | |
28 | #include "xtensa-istack.h" | |
cda2eb9e | 29 | #include "dwarf2dbg.h" |
e0001a05 NC |
30 | #include "struc-symbol.h" |
31 | #include "xtensa-config.h" | |
32 | ||
2caa7ca0 BW |
33 | /* Provide default values for new configuration settings. */ |
34 | #ifndef XSHAL_ABI | |
35 | #define XSHAL_ABI 0 | |
36 | #endif | |
37 | ||
e0001a05 NC |
38 | #ifndef uint32 |
39 | #define uint32 unsigned int | |
40 | #endif | |
41 | #ifndef int32 | |
42 | #define int32 signed int | |
43 | #endif | |
44 | ||
45 | /* Notes: | |
46 | ||
e0001a05 NC |
47 | Naming conventions (used somewhat inconsistently): |
48 | The xtensa_ functions are exported | |
49 | The xg_ functions are internal | |
50 | ||
51 | We also have a couple of different extensibility mechanisms. | |
52 | 1) The idiom replacement: | |
53 | This is used when a line is first parsed to | |
54 | replace an instruction pattern with another instruction | |
55 | It is currently limited to replacements of instructions | |
56 | with constant operands. | |
57 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
58 | replacement patterns. When an instruction's immediate field | |
59 | does not fit the next instruction sequence is attempted. | |
60 | In addition, "narrow" opcodes are supported this way. */ | |
61 | ||
62 | ||
63 | /* Define characters with special meanings to GAS. */ | |
64 | const char comment_chars[] = "#"; | |
65 | const char line_comment_chars[] = "#"; | |
66 | const char line_separator_chars[] = ";"; | |
67 | const char EXP_CHARS[] = "eE"; | |
68 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
69 | ||
70 | ||
43cd72b9 BW |
71 | /* Flags to indicate whether the hardware supports the density and |
72 | absolute literals options. */ | |
e0001a05 | 73 | |
e0001a05 | 74 | bfd_boolean density_supported = XCHAL_HAVE_DENSITY; |
43cd72b9 BW |
75 | bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; |
76 | ||
77 | /* Maximum width we would pad an unreachable frag to get alignment. */ | |
78 | #define UNREACHABLE_MAX_WIDTH 8 | |
e0001a05 | 79 | |
43cd72b9 BW |
80 | static vliw_insn cur_vinsn; |
81 | ||
d77b99c9 | 82 | unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; |
43cd72b9 BW |
83 | |
84 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
85 | ||
86 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 87 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
88 | back end. */ |
89 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
90 | |
91 | /* Flags for properties of the last instruction in a segment. */ | |
92 | #define FLAG_IS_A0_WRITER 0x1 | |
93 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
94 | ||
95 | ||
96 | /* We define a special segment names ".literal" to place literals | |
97 | into. The .fini and .init sections are special because they | |
98 | contain code that is moved together by the linker. We give them | |
99 | their own special .fini.literal and .init.literal sections. */ | |
100 | ||
101 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 102 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 | 103 | #define INIT_SECTION_NAME xtensa_section_rename (".init") |
74869ac7 | 104 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
e0001a05 NC |
105 | |
106 | ||
43cd72b9 | 107 | /* This type is used for the directive_stack to keep track of the |
74869ac7 BW |
108 | state of the literal collection pools. If lit_prefix is set, it is |
109 | used to determine the literal section names; otherwise, the literal | |
110 | sections are determined based on the current text section. The | |
111 | lit_seg and lit4_seg fields cache these literal sections, with the | |
112 | current_text_seg field used a tag to indicate whether the cached | |
113 | values are valid. */ | |
e0001a05 NC |
114 | |
115 | typedef struct lit_state_struct | |
116 | { | |
74869ac7 BW |
117 | char *lit_prefix; |
118 | segT current_text_seg; | |
e0001a05 | 119 | segT lit_seg; |
43cd72b9 | 120 | segT lit4_seg; |
e0001a05 NC |
121 | } lit_state; |
122 | ||
123 | static lit_state default_lit_sections; | |
124 | ||
125 | ||
74869ac7 BW |
126 | /* We keep a list of literal segments. The seg_list type is the node |
127 | for this list. The literal_head pointer is the head of the list, | |
128 | with the literal_head_h dummy node at the start. */ | |
e0001a05 NC |
129 | |
130 | typedef struct seg_list_struct | |
131 | { | |
132 | struct seg_list_struct *next; | |
133 | segT seg; | |
134 | } seg_list; | |
135 | ||
136 | static seg_list literal_head_h; | |
137 | static seg_list *literal_head = &literal_head_h; | |
e0001a05 NC |
138 | |
139 | ||
82e7541d BW |
140 | /* Lists of symbols. We keep a list of symbols that label the current |
141 | instruction, so that we can adjust the symbols when inserting alignment | |
142 | for various instructions. We also keep a list of all the symbols on | |
143 | literals, so that we can fix up those symbols when the literals are | |
144 | later moved into the text sections. */ | |
145 | ||
146 | typedef struct sym_list_struct | |
147 | { | |
148 | struct sym_list_struct *next; | |
149 | symbolS *sym; | |
150 | } sym_list; | |
151 | ||
152 | static sym_list *insn_labels = NULL; | |
153 | static sym_list *free_insn_labels = NULL; | |
154 | static sym_list *saved_insn_labels = NULL; | |
155 | ||
156 | static sym_list *literal_syms; | |
157 | ||
158 | ||
43cd72b9 BW |
159 | /* Flags to determine whether to prefer const16 or l32r |
160 | if both options are available. */ | |
161 | int prefer_const16 = 0; | |
162 | int prefer_l32r = 0; | |
163 | ||
e0001a05 NC |
164 | /* Global flag to indicate when we are emitting literals. */ |
165 | int generating_literals = 0; | |
166 | ||
43cd72b9 BW |
167 | /* The following PROPERTY table definitions are copied from |
168 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
169 | ||
170 | /* Flags in the property tables to specify whether blocks of memory | |
171 | are literals, instructions, data, or unreachable. For | |
172 | instructions, blocks that begin loop targets and branch targets are | |
173 | designated. Blocks that do not allow density, instruction | |
174 | reordering or transformation are also specified. Finally, for | |
175 | branch targets, branch target alignment priority is included. | |
176 | Alignment of the next block is specified in the current block | |
177 | and the size of the current block does not include any fill required | |
178 | to align to the next block. */ | |
179 | ||
180 | #define XTENSA_PROP_LITERAL 0x00000001 | |
181 | #define XTENSA_PROP_INSN 0x00000002 | |
182 | #define XTENSA_PROP_DATA 0x00000004 | |
183 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
184 | /* Instruction only properties at beginning of code. */ | |
185 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
186 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
187 | /* Instruction only properties about code. */ | |
188 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
189 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
99ded152 BW |
190 | /* Historically, NO_TRANSFORM was a property of instructions, |
191 | but it should apply to literals under certain circumstances. */ | |
192 | #define XTENSA_PROP_NO_TRANSFORM 0x00000100 | |
43cd72b9 BW |
193 | |
194 | /* Branch target alignment information. This transmits information | |
195 | to the linker optimization about the priority of aligning a | |
196 | particular block for branch target alignment: None, low priority, | |
197 | high priority, or required. These only need to be checked in | |
198 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
199 | Common usage is | |
200 | ||
201 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
202 | case XTENSA_PROP_BT_ALIGN_NONE: | |
203 | case XTENSA_PROP_BT_ALIGN_LOW: | |
204 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
205 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
206 | */ | |
207 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
208 | ||
209 | /* No branch target alignment. */ | |
210 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
211 | /* Low priority branch target alignment. */ | |
212 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
213 | /* High priority branch target alignment. */ | |
214 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
215 | /* Required branch target alignment. */ | |
216 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
217 | ||
218 | #define GET_XTENSA_PROP_BT_ALIGN(flag) \ | |
219 | (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) | |
220 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ | |
221 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
222 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
223 | ||
224 | ||
225 | /* Alignment is specified in the block BEFORE the one that needs | |
226 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
227 | get the required alignment specified as a power of 2. Use | |
228 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
229 | alignment. Be careful of side effects since the SET will evaluate | |
230 | flags twice. Also, note that the SIZE of a block in the property | |
231 | table does not include the alignment size, so the alignment fill | |
232 | must be calculated to determine if two blocks are contiguous. | |
233 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
234 | possible future implementation. */ | |
235 | ||
236 | #define XTENSA_PROP_ALIGN 0x00000800 | |
237 | ||
238 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
239 | ||
240 | #define GET_XTENSA_PROP_ALIGNMENT(flag) \ | |
241 | (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) | |
242 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ | |
243 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
244 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
245 | ||
246 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
247 | ||
248 | ||
249 | /* Structure for saving instruction and alignment per-fragment data | |
250 | that will be written to the object file. This structure is | |
251 | equivalent to the actual data that will be written out to the file | |
252 | but is easier to use. We provide a conversion to file flags | |
253 | in frag_flags_to_number. */ | |
254 | ||
255 | typedef struct frag_flags_struct frag_flags; | |
256 | ||
257 | struct frag_flags_struct | |
258 | { | |
259 | /* is_literal should only be used after xtensa_move_literals. | |
260 | If you need to check if you are generating a literal fragment, | |
261 | then use the generating_literals global. */ | |
262 | ||
263 | unsigned is_literal : 1; | |
264 | unsigned is_insn : 1; | |
265 | unsigned is_data : 1; | |
266 | unsigned is_unreachable : 1; | |
267 | ||
99ded152 BW |
268 | /* is_specific_opcode implies no_transform. */ |
269 | unsigned is_no_transform : 1; | |
270 | ||
43cd72b9 BW |
271 | struct |
272 | { | |
273 | unsigned is_loop_target : 1; | |
274 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
275 | unsigned bt_align_priority : 2; | |
276 | ||
277 | unsigned is_no_density : 1; | |
278 | /* no_longcalls flag does not need to be placed in the object file. */ | |
43cd72b9 BW |
279 | |
280 | unsigned is_no_reorder : 1; | |
281 | ||
282 | /* Uses absolute literal addressing for l32r. */ | |
283 | unsigned is_abslit : 1; | |
284 | } insn; | |
285 | unsigned is_align : 1; | |
286 | unsigned alignment : 5; | |
287 | }; | |
288 | ||
289 | ||
290 | /* Structure for saving information about a block of property data | |
291 | for frags that have the same flags. */ | |
292 | struct xtensa_block_info_struct | |
293 | { | |
294 | segT sec; | |
295 | bfd_vma offset; | |
296 | size_t size; | |
297 | frag_flags flags; | |
298 | struct xtensa_block_info_struct *next; | |
299 | }; | |
300 | ||
e0001a05 NC |
301 | |
302 | /* Structure for saving the current state before emitting literals. */ | |
303 | typedef struct emit_state_struct | |
304 | { | |
305 | const char *name; | |
306 | segT now_seg; | |
307 | subsegT now_subseg; | |
308 | int generating_literals; | |
309 | } emit_state; | |
310 | ||
311 | ||
43cd72b9 BW |
312 | /* Opcode placement information */ |
313 | ||
314 | typedef unsigned long long bitfield; | |
315 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
316 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
317 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
318 | ||
319 | #define MAX_FORMATS 32 | |
320 | ||
321 | typedef struct op_placement_info_struct | |
322 | { | |
323 | int num_formats; | |
324 | /* A number describing how restrictive the issue is for this | |
325 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 326 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 327 | only one format but many slots in that format. The most |
c138bc38 | 328 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
329 | format. */ |
330 | int issuef; | |
43cd72b9 | 331 | xtensa_format narrowest; |
43cd72b9 | 332 | char narrowest_size; |
b2d179be | 333 | char narrowest_slot; |
43cd72b9 BW |
334 | |
335 | /* formats is a bitfield with the Nth bit set | |
336 | if the opcode fits in the Nth xtensa_format. */ | |
337 | bitfield formats; | |
338 | ||
339 | /* slots[N]'s Mth bit is set if the op fits in the | |
340 | Mth slot of the Nth xtensa_format. */ | |
341 | bitfield slots[MAX_FORMATS]; | |
342 | ||
343 | /* A count of the number of slots in a given format | |
344 | an op can fit (i.e., the bitcount of the slot field above). */ | |
345 | char slots_in_format[MAX_FORMATS]; | |
346 | ||
347 | } op_placement_info, *op_placement_info_table; | |
348 | ||
349 | op_placement_info_table op_placement_table; | |
350 | ||
351 | ||
352 | /* Extra expression types. */ | |
353 | ||
354 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
355 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
356 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
357 | ||
bbdd25a8 BW |
358 | struct suffix_reloc_map |
359 | { | |
360 | char *suffix; | |
361 | int length; | |
362 | bfd_reloc_code_real_type reloc; | |
363 | unsigned char operator; | |
364 | }; | |
365 | ||
366 | #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } | |
367 | ||
368 | static struct suffix_reloc_map suffix_relocs[] = | |
369 | { | |
370 | SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), | |
371 | SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), | |
372 | SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), | |
373 | { (char *) 0, 0, BFD_RELOC_UNUSED, 0 } | |
374 | }; | |
375 | ||
43cd72b9 | 376 | |
e0001a05 NC |
377 | /* Directives. */ |
378 | ||
379 | typedef enum | |
380 | { | |
381 | directive_none = 0, | |
382 | directive_literal, | |
383 | directive_density, | |
43cd72b9 | 384 | directive_transform, |
e0001a05 NC |
385 | directive_freeregs, |
386 | directive_longcalls, | |
43cd72b9 BW |
387 | directive_literal_prefix, |
388 | directive_schedule, | |
389 | directive_absolute_literals, | |
390 | directive_last_directive | |
e0001a05 NC |
391 | } directiveE; |
392 | ||
393 | typedef struct | |
394 | { | |
395 | const char *name; | |
396 | bfd_boolean can_be_negated; | |
397 | } directive_infoS; | |
398 | ||
399 | const directive_infoS directive_info[] = | |
400 | { | |
43cd72b9 BW |
401 | { "none", FALSE }, |
402 | { "literal", FALSE }, | |
403 | { "density", TRUE }, | |
404 | { "transform", TRUE }, | |
405 | { "freeregs", FALSE }, | |
406 | { "longcalls", TRUE }, | |
407 | { "literal_prefix", FALSE }, | |
408 | { "schedule", TRUE }, | |
409 | { "absolute-literals", TRUE } | |
e0001a05 NC |
410 | }; |
411 | ||
412 | bfd_boolean directive_state[] = | |
413 | { | |
414 | FALSE, /* none */ | |
415 | FALSE, /* literal */ | |
43cd72b9 | 416 | #if !XCHAL_HAVE_DENSITY |
e0001a05 NC |
417 | FALSE, /* density */ |
418 | #else | |
419 | TRUE, /* density */ | |
420 | #endif | |
43cd72b9 | 421 | TRUE, /* transform */ |
e0001a05 NC |
422 | FALSE, /* freeregs */ |
423 | FALSE, /* longcalls */ | |
43cd72b9 | 424 | FALSE, /* literal_prefix */ |
2caa7ca0 | 425 | FALSE, /* schedule */ |
43cd72b9 BW |
426 | #if XSHAL_USE_ABSOLUTE_LITERALS |
427 | TRUE /* absolute_literals */ | |
428 | #else | |
429 | FALSE /* absolute_literals */ | |
430 | #endif | |
e0001a05 NC |
431 | }; |
432 | ||
e0001a05 NC |
433 | |
434 | /* Directive functions. */ | |
435 | ||
7fa3d080 BW |
436 | static void xtensa_begin_directive (int); |
437 | static void xtensa_end_directive (int); | |
74869ac7 | 438 | static void xtensa_literal_prefix (void); |
7fa3d080 BW |
439 | static void xtensa_literal_position (int); |
440 | static void xtensa_literal_pseudo (int); | |
441 | static void xtensa_frequency_pseudo (int); | |
442 | static void xtensa_elf_cons (int); | |
e0001a05 | 443 | |
7fa3d080 | 444 | /* Parsing and Idiom Translation. */ |
e0001a05 | 445 | |
7fa3d080 | 446 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 447 | |
e0001a05 NC |
448 | /* Various Other Internal Functions. */ |
449 | ||
84b08ed9 BW |
450 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
451 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
452 | static void xtensa_mark_literal_pool_location (void); |
453 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
454 | static fragS *get_literal_pool_location (segT); | |
455 | static void set_literal_pool_location (segT, fragS *); | |
456 | static void xtensa_set_frag_assembly_state (fragS *); | |
457 | static void finish_vinsn (vliw_insn *); | |
458 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 459 | static int total_frag_text_expansion (fragS *); |
e0001a05 NC |
460 | |
461 | /* Alignment Functions. */ | |
462 | ||
d77b99c9 BW |
463 | static int get_text_align_power (unsigned); |
464 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 465 | static int branch_align_power (segT); |
e0001a05 NC |
466 | |
467 | /* Helpers for xtensa_relax_frag(). */ | |
468 | ||
7fa3d080 | 469 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 470 | |
b08b5071 | 471 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 472 | |
7fa3d080 BW |
473 | static unsigned get_last_insn_flags (segT, subsegT); |
474 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
475 | static float get_subseg_total_freq (segT, subsegT); |
476 | static float get_subseg_target_freq (segT, subsegT); | |
477 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
478 | |
479 | /* Segment list functions. */ | |
480 | ||
7fa3d080 BW |
481 | static void xtensa_move_literals (void); |
482 | static void xtensa_reorder_segments (void); | |
483 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
484 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
485 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
486 | static void xtensa_restore_emit_state (emit_state *); | |
74869ac7 | 487 | static segT cache_literal_section (bfd_boolean); |
e0001a05 | 488 | |
e0001a05 | 489 | /* Import from elf32-xtensa.c in BFD library. */ |
43cd72b9 | 490 | |
74869ac7 | 491 | extern asection *xtensa_get_property_section (asection *, const char *); |
e0001a05 | 492 | |
43cd72b9 BW |
493 | /* op_placement_info functions. */ |
494 | ||
7fa3d080 BW |
495 | static void init_op_placement_info_table (void); |
496 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
497 | static int xg_get_single_size (xtensa_opcode); | |
498 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 499 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 500 | |
e0001a05 | 501 | /* TInsn and IStack functions. */ |
43cd72b9 | 502 | |
7fa3d080 BW |
503 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
504 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
505 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
506 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
507 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
508 | static void tinsn_from_chars (TInsn *, char *, int); | |
509 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
510 | static int get_num_stack_text_bytes (IStack *); | |
511 | static int get_num_stack_literal_bytes (IStack *); | |
e0001a05 | 512 | |
43cd72b9 BW |
513 | /* vliw_insn functions. */ |
514 | ||
7fa3d080 BW |
515 | static void xg_init_vinsn (vliw_insn *); |
516 | static void xg_clear_vinsn (vliw_insn *); | |
517 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
518 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 519 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
520 | (vliw_insn *, char *, fragS *, bfd_boolean); |
521 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 522 | |
e0001a05 | 523 | /* Expression Utilities. */ |
43cd72b9 | 524 | |
7fa3d080 BW |
525 | bfd_boolean expr_is_const (const expressionS *); |
526 | offsetT get_expr_const (const expressionS *); | |
527 | void set_expr_const (expressionS *, offsetT); | |
528 | bfd_boolean expr_is_register (const expressionS *); | |
529 | offsetT get_expr_register (const expressionS *); | |
530 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
531 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
532 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 533 | |
9456465c BW |
534 | /* Section renaming. */ |
535 | ||
7fa3d080 | 536 | static void build_section_rename (const char *); |
e0001a05 | 537 | |
e0001a05 NC |
538 | |
539 | /* ISA imported from bfd. */ | |
540 | extern xtensa_isa xtensa_default_isa; | |
541 | ||
542 | extern int target_big_endian; | |
543 | ||
544 | static xtensa_opcode xtensa_addi_opcode; | |
545 | static xtensa_opcode xtensa_addmi_opcode; | |
546 | static xtensa_opcode xtensa_call0_opcode; | |
547 | static xtensa_opcode xtensa_call4_opcode; | |
548 | static xtensa_opcode xtensa_call8_opcode; | |
549 | static xtensa_opcode xtensa_call12_opcode; | |
550 | static xtensa_opcode xtensa_callx0_opcode; | |
551 | static xtensa_opcode xtensa_callx4_opcode; | |
552 | static xtensa_opcode xtensa_callx8_opcode; | |
553 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 554 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 555 | static xtensa_opcode xtensa_entry_opcode; |
d12f9798 | 556 | static xtensa_opcode xtensa_extui_opcode; |
43cd72b9 BW |
557 | static xtensa_opcode xtensa_movi_opcode; |
558 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 559 | static xtensa_opcode xtensa_isync_opcode; |
e0001a05 | 560 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 561 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
562 | static xtensa_opcode xtensa_loop_opcode; |
563 | static xtensa_opcode xtensa_loopnez_opcode; | |
564 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 565 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
566 | static xtensa_opcode xtensa_nop_n_opcode; |
567 | static xtensa_opcode xtensa_or_opcode; | |
568 | static xtensa_opcode xtensa_ret_opcode; | |
569 | static xtensa_opcode xtensa_ret_n_opcode; | |
570 | static xtensa_opcode xtensa_retw_opcode; | |
571 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 572 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 NC |
573 | static xtensa_opcode xtensa_waiti_opcode; |
574 | ||
575 | \f | |
576 | /* Command-line Options. */ | |
577 | ||
578 | bfd_boolean use_literal_section = TRUE; | |
579 | static bfd_boolean align_targets = TRUE; | |
43cd72b9 | 580 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 581 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
582 | static bfd_boolean workaround_a0_b_retw = FALSE; |
583 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
584 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 585 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 586 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 587 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 588 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
e0001a05 | 589 | |
43cd72b9 BW |
590 | /* When workaround_short_loops is TRUE, all loops with early exits must |
591 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
592 | to the workaround_short_loop flag. In addition to the | |
593 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
594 | must have at least 3 instructions. */ | |
e0001a05 | 595 | |
43cd72b9 | 596 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 597 | |
7fa3d080 BW |
598 | |
599 | static void | |
600 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
601 | { | |
602 | if (earliest > latest) | |
603 | as_fatal (_("illegal range of target hardware versions")); | |
604 | ||
605 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
606 | if (earliest < 105000 || latest < 105000) | |
607 | { | |
608 | workaround_a0_b_retw |= TRUE; | |
609 | workaround_b_j_loop_end |= TRUE; | |
610 | workaround_short_loop |= TRUE; | |
611 | workaround_close_loop_end |= TRUE; | |
612 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 613 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
614 | } |
615 | } | |
616 | ||
617 | ||
e0001a05 NC |
618 | enum |
619 | { | |
620 | option_density = OPTION_MD_BASE, | |
621 | option_no_density, | |
622 | ||
623 | option_relax, | |
624 | option_no_relax, | |
625 | ||
43cd72b9 BW |
626 | option_link_relax, |
627 | option_no_link_relax, | |
628 | ||
e0001a05 NC |
629 | option_generics, |
630 | option_no_generics, | |
631 | ||
43cd72b9 BW |
632 | option_transform, |
633 | option_no_transform, | |
634 | ||
e0001a05 NC |
635 | option_text_section_literals, |
636 | option_no_text_section_literals, | |
637 | ||
43cd72b9 BW |
638 | option_absolute_literals, |
639 | option_no_absolute_literals, | |
640 | ||
e0001a05 NC |
641 | option_align_targets, |
642 | option_no_align_targets, | |
643 | ||
43cd72b9 | 644 | option_warn_unaligned_targets, |
e0001a05 NC |
645 | |
646 | option_longcalls, | |
647 | option_no_longcalls, | |
648 | ||
649 | option_workaround_a0_b_retw, | |
650 | option_no_workaround_a0_b_retw, | |
651 | ||
652 | option_workaround_b_j_loop_end, | |
653 | option_no_workaround_b_j_loop_end, | |
654 | ||
655 | option_workaround_short_loop, | |
656 | option_no_workaround_short_loop, | |
657 | ||
658 | option_workaround_all_short_loops, | |
659 | option_no_workaround_all_short_loops, | |
660 | ||
661 | option_workaround_close_loop_end, | |
662 | option_no_workaround_close_loop_end, | |
663 | ||
664 | option_no_workarounds, | |
665 | ||
e0001a05 | 666 | option_rename_section_name, |
e0001a05 | 667 | |
43cd72b9 BW |
668 | option_prefer_l32r, |
669 | option_prefer_const16, | |
670 | ||
671 | option_target_hardware | |
e0001a05 NC |
672 | }; |
673 | ||
674 | const char *md_shortopts = ""; | |
675 | ||
676 | struct option md_longopts[] = | |
677 | { | |
43cd72b9 BW |
678 | { "density", no_argument, NULL, option_density }, |
679 | { "no-density", no_argument, NULL, option_no_density }, | |
680 | ||
681 | /* Both "relax" and "generics" are deprecated and treated as equivalent | |
682 | to the "transform" option. */ | |
683 | { "relax", no_argument, NULL, option_relax }, | |
684 | { "no-relax", no_argument, NULL, option_no_relax }, | |
685 | { "generics", no_argument, NULL, option_generics }, | |
686 | { "no-generics", no_argument, NULL, option_no_generics }, | |
687 | ||
688 | { "transform", no_argument, NULL, option_transform }, | |
689 | { "no-transform", no_argument, NULL, option_no_transform }, | |
690 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
691 | { "no-text-section-literals", no_argument, NULL, | |
692 | option_no_text_section_literals }, | |
693 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
694 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
695 | /* This option was changed from -align-target to -target-align |
696 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 697 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
698 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
699 | { "warn-unaligned-targets", no_argument, NULL, | |
700 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
701 | { "longcalls", no_argument, NULL, option_longcalls }, |
702 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
703 | ||
704 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
705 | option_no_workaround_a0_b_retw }, | |
706 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 707 | |
43cd72b9 BW |
708 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
709 | option_no_workaround_b_j_loop_end }, | |
710 | { "workaround-b-j-loop-end", no_argument, NULL, | |
711 | option_workaround_b_j_loop_end }, | |
e0001a05 | 712 | |
43cd72b9 BW |
713 | { "no-workaround-short-loops", no_argument, NULL, |
714 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
715 | { "workaround-short-loops", no_argument, NULL, |
716 | option_workaround_short_loop }, | |
e0001a05 | 717 | |
43cd72b9 BW |
718 | { "no-workaround-all-short-loops", no_argument, NULL, |
719 | option_no_workaround_all_short_loops }, | |
720 | { "workaround-all-short-loop", no_argument, NULL, | |
721 | option_workaround_all_short_loops }, | |
722 | ||
723 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
724 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
725 | ||
726 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
727 | ||
728 | { "no-workaround-close-loop-end", no_argument, NULL, | |
729 | option_no_workaround_close_loop_end }, | |
730 | { "workaround-close-loop-end", no_argument, NULL, | |
731 | option_workaround_close_loop_end }, | |
e0001a05 | 732 | |
7fa3d080 | 733 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 734 | |
43cd72b9 BW |
735 | { "link-relax", no_argument, NULL, option_link_relax }, |
736 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
737 | ||
738 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
739 | ||
740 | { NULL, no_argument, NULL, 0 } | |
e0001a05 NC |
741 | }; |
742 | ||
743 | size_t md_longopts_size = sizeof md_longopts; | |
744 | ||
745 | ||
746 | int | |
7fa3d080 | 747 | md_parse_option (int c, char *arg) |
e0001a05 NC |
748 | { |
749 | switch (c) | |
750 | { | |
751 | case option_density: | |
43cd72b9 | 752 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
753 | return 1; |
754 | case option_no_density: | |
43cd72b9 | 755 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 756 | return 1; |
43cd72b9 BW |
757 | case option_link_relax: |
758 | linkrelax = 1; | |
e0001a05 | 759 | return 1; |
43cd72b9 BW |
760 | case option_no_link_relax: |
761 | linkrelax = 0; | |
e0001a05 | 762 | return 1; |
43cd72b9 BW |
763 | case option_generics: |
764 | as_warn (_("--generics is deprecated; use --transform instead")); | |
765 | return md_parse_option (option_transform, arg); | |
766 | case option_no_generics: | |
767 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
768 | return md_parse_option (option_no_transform, arg); | |
769 | case option_relax: | |
770 | as_warn (_("--relax is deprecated; use --transform instead")); | |
771 | return md_parse_option (option_transform, arg); | |
772 | case option_no_relax: | |
773 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
774 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
775 | case option_longcalls: |
776 | directive_state[directive_longcalls] = TRUE; | |
777 | return 1; | |
778 | case option_no_longcalls: | |
779 | directive_state[directive_longcalls] = FALSE; | |
780 | return 1; | |
781 | case option_text_section_literals: | |
782 | use_literal_section = FALSE; | |
783 | return 1; | |
784 | case option_no_text_section_literals: | |
785 | use_literal_section = TRUE; | |
786 | return 1; | |
43cd72b9 BW |
787 | case option_absolute_literals: |
788 | if (!absolute_literals_supported) | |
789 | { | |
790 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
791 | return 0; | |
792 | } | |
793 | directive_state[directive_absolute_literals] = TRUE; | |
794 | return 1; | |
795 | case option_no_absolute_literals: | |
796 | directive_state[directive_absolute_literals] = FALSE; | |
797 | return 1; | |
798 | ||
e0001a05 NC |
799 | case option_workaround_a0_b_retw: |
800 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
801 | return 1; |
802 | case option_no_workaround_a0_b_retw: | |
803 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
804 | return 1; |
805 | case option_workaround_b_j_loop_end: | |
806 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
807 | return 1; |
808 | case option_no_workaround_b_j_loop_end: | |
809 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
810 | return 1; |
811 | ||
812 | case option_workaround_short_loop: | |
813 | workaround_short_loop = TRUE; | |
e0001a05 NC |
814 | return 1; |
815 | case option_no_workaround_short_loop: | |
816 | workaround_short_loop = FALSE; | |
e0001a05 NC |
817 | return 1; |
818 | ||
819 | case option_workaround_all_short_loops: | |
820 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
821 | return 1; |
822 | case option_no_workaround_all_short_loops: | |
823 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
824 | return 1; |
825 | ||
826 | case option_workaround_close_loop_end: | |
827 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
828 | return 1; |
829 | case option_no_workaround_close_loop_end: | |
830 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
831 | return 1; |
832 | ||
833 | case option_no_workarounds: | |
834 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 835 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 836 | workaround_short_loop = FALSE; |
e0001a05 | 837 | workaround_all_short_loops = FALSE; |
e0001a05 | 838 | workaround_close_loop_end = FALSE; |
e0001a05 | 839 | return 1; |
43cd72b9 | 840 | |
e0001a05 NC |
841 | case option_align_targets: |
842 | align_targets = TRUE; | |
843 | return 1; | |
844 | case option_no_align_targets: | |
845 | align_targets = FALSE; | |
846 | return 1; | |
847 | ||
43cd72b9 BW |
848 | case option_warn_unaligned_targets: |
849 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
850 | return 1; |
851 | ||
e0001a05 NC |
852 | case option_rename_section_name: |
853 | build_section_rename (arg); | |
854 | return 1; | |
e0001a05 NC |
855 | |
856 | case 'Q': | |
857 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
858 | should be emitted or not. FIXME: Not implemented. */ | |
859 | return 1; | |
c138bc38 | 860 | |
43cd72b9 BW |
861 | case option_prefer_l32r: |
862 | if (prefer_const16) | |
863 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
864 | prefer_l32r = 1; | |
865 | return 1; | |
866 | ||
867 | case option_prefer_const16: | |
868 | if (prefer_l32r) | |
869 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
870 | prefer_const16 = 1; | |
871 | return 1; | |
872 | ||
c138bc38 | 873 | case option_target_hardware: |
43cd72b9 BW |
874 | { |
875 | int earliest, latest = 0; | |
876 | if (*arg == 0 || *arg == '-') | |
877 | as_fatal (_("invalid target hardware version")); | |
878 | ||
879 | earliest = strtol (arg, &arg, 0); | |
880 | ||
881 | if (*arg == 0) | |
882 | latest = earliest; | |
883 | else if (*arg == '-') | |
884 | { | |
885 | if (*++arg == 0) | |
886 | as_fatal (_("invalid target hardware version")); | |
887 | latest = strtol (arg, &arg, 0); | |
888 | } | |
889 | if (*arg != 0) | |
890 | as_fatal (_("invalid target hardware version")); | |
891 | ||
892 | xtensa_setup_hw_workarounds (earliest, latest); | |
893 | return 1; | |
894 | } | |
895 | ||
896 | case option_transform: | |
897 | /* This option has no affect other than to use the defaults, | |
898 | which are already set. */ | |
899 | return 1; | |
900 | ||
901 | case option_no_transform: | |
902 | /* This option turns off all transformations of any kind. | |
903 | However, because we want to preserve the state of other | |
904 | directives, we only change its own field. Thus, before | |
905 | you perform any transformation, always check if transform | |
906 | is available. If you use the functions we provide for this | |
907 | purpose, you will be ok. */ | |
908 | directive_state[directive_transform] = FALSE; | |
909 | return 1; | |
910 | ||
e0001a05 NC |
911 | default: |
912 | return 0; | |
913 | } | |
914 | } | |
915 | ||
916 | ||
917 | void | |
7fa3d080 | 918 | md_show_usage (FILE *stream) |
e0001a05 | 919 | { |
43cd72b9 BW |
920 | fputs ("\n\ |
921 | Xtensa options:\n\ | |
9456465c BW |
922 | --[no-]text-section-literals\n\ |
923 | [Do not] put literals in the text section\n\ | |
924 | --[no-]absolute-literals\n\ | |
925 | [Do not] default to use non-PC-relative literals\n\ | |
926 | --[no-]target-align [Do not] try to align branch targets\n\ | |
927 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
928 | --[no-]transform [Do not] transform instructions\n\ | |
929 | --rename-section old=new Rename section 'old' to 'new'\n", stream); | |
e0001a05 NC |
930 | } |
931 | ||
7fa3d080 BW |
932 | \f |
933 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
934 | |
935 | static void | |
7fa3d080 | 936 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 937 | { |
7fa3d080 | 938 | sym_list *l; |
43cd72b9 | 939 | |
7fa3d080 BW |
940 | if (!free_insn_labels) |
941 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
942 | else | |
43cd72b9 | 943 | { |
7fa3d080 BW |
944 | l = free_insn_labels; |
945 | free_insn_labels = l->next; | |
946 | } | |
947 | ||
948 | l->sym = sym; | |
949 | l->next = insn_labels; | |
950 | insn_labels = l; | |
951 | } | |
952 | ||
953 | ||
954 | static void | |
955 | xtensa_clear_insn_labels (void) | |
956 | { | |
957 | sym_list **pl; | |
958 | ||
959 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
960 | ; | |
961 | *pl = insn_labels; | |
962 | insn_labels = NULL; | |
963 | } | |
964 | ||
965 | ||
7fa3d080 | 966 | static void |
c3ea6048 | 967 | xtensa_move_labels (fragS *new_frag, valueT new_offset) |
7fa3d080 BW |
968 | { |
969 | sym_list *lit; | |
970 | ||
971 | for (lit = insn_labels; lit; lit = lit->next) | |
972 | { | |
973 | symbolS *lit_sym = lit->sym; | |
c3ea6048 BW |
974 | S_SET_VALUE (lit_sym, new_offset); |
975 | symbol_set_frag (lit_sym, new_frag); | |
43cd72b9 BW |
976 | } |
977 | } | |
978 | ||
e0001a05 NC |
979 | \f |
980 | /* Directive data and functions. */ | |
981 | ||
982 | typedef struct state_stackS_struct | |
983 | { | |
984 | directiveE directive; | |
985 | bfd_boolean negated; | |
986 | bfd_boolean old_state; | |
987 | const char *file; | |
988 | unsigned int line; | |
989 | const void *datum; | |
990 | struct state_stackS_struct *prev; | |
991 | } state_stackS; | |
992 | ||
993 | state_stackS *directive_state_stack; | |
994 | ||
995 | const pseudo_typeS md_pseudo_table[] = | |
996 | { | |
43cd72b9 BW |
997 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
998 | { "literal_position", xtensa_literal_position, 0 }, | |
999 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1000 | { "long", xtensa_elf_cons, 4 }, | |
1001 | { "word", xtensa_elf_cons, 4 }, | |
1002 | { "short", xtensa_elf_cons, 2 }, | |
1003 | { "begin", xtensa_begin_directive, 0 }, | |
1004 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1005 | { "literal", xtensa_literal_pseudo, 0 }, |
1006 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1007 | { NULL, 0, 0 }, | |
e0001a05 NC |
1008 | }; |
1009 | ||
1010 | ||
7fa3d080 BW |
1011 | static bfd_boolean |
1012 | use_transform (void) | |
e0001a05 | 1013 | { |
43cd72b9 BW |
1014 | /* After md_end, you should be checking frag by frag, rather |
1015 | than state directives. */ | |
1016 | assert (!past_xtensa_end); | |
1017 | return directive_state[directive_transform]; | |
e0001a05 NC |
1018 | } |
1019 | ||
1020 | ||
7fa3d080 BW |
1021 | static bfd_boolean |
1022 | do_align_targets (void) | |
e0001a05 | 1023 | { |
7b1cc377 BW |
1024 | /* Do not use this function after md_end; just look at align_targets |
1025 | instead. There is no target-align directive, so alignment is either | |
1026 | enabled for all frags or not done at all. */ | |
43cd72b9 BW |
1027 | assert (!past_xtensa_end); |
1028 | return align_targets && use_transform (); | |
e0001a05 NC |
1029 | } |
1030 | ||
1031 | ||
1032 | static void | |
7fa3d080 | 1033 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 NC |
1034 | { |
1035 | char *file; | |
1036 | unsigned int line; | |
1037 | state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); | |
1038 | ||
1039 | as_where (&file, &line); | |
1040 | ||
1041 | stack->directive = directive; | |
1042 | stack->negated = negated; | |
1043 | stack->old_state = directive_state[directive]; | |
1044 | stack->file = file; | |
1045 | stack->line = line; | |
1046 | stack->datum = datum; | |
1047 | stack->prev = directive_state_stack; | |
1048 | directive_state_stack = stack; | |
1049 | ||
1050 | directive_state[directive] = !negated; | |
1051 | } | |
1052 | ||
7fa3d080 | 1053 | |
e0001a05 | 1054 | static void |
7fa3d080 BW |
1055 | directive_pop (directiveE *directive, |
1056 | bfd_boolean *negated, | |
1057 | const char **file, | |
1058 | unsigned int *line, | |
1059 | const void **datum) | |
e0001a05 NC |
1060 | { |
1061 | state_stackS *top = directive_state_stack; | |
1062 | ||
1063 | if (!directive_state_stack) | |
1064 | { | |
1065 | as_bad (_("unmatched end directive")); | |
1066 | *directive = directive_none; | |
1067 | return; | |
1068 | } | |
1069 | ||
1070 | directive_state[directive_state_stack->directive] = top->old_state; | |
1071 | *directive = top->directive; | |
1072 | *negated = top->negated; | |
1073 | *file = top->file; | |
1074 | *line = top->line; | |
1075 | *datum = top->datum; | |
1076 | directive_state_stack = top->prev; | |
1077 | free (top); | |
1078 | } | |
1079 | ||
1080 | ||
1081 | static void | |
7fa3d080 | 1082 | directive_balance (void) |
e0001a05 NC |
1083 | { |
1084 | while (directive_state_stack) | |
1085 | { | |
1086 | directiveE directive; | |
1087 | bfd_boolean negated; | |
1088 | const char *file; | |
1089 | unsigned int line; | |
1090 | const void *datum; | |
1091 | ||
1092 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1093 | as_warn_where ((char *) file, line, | |
1094 | _(".begin directive with no matching .end directive")); | |
1095 | } | |
1096 | } | |
1097 | ||
1098 | ||
1099 | static bfd_boolean | |
7fa3d080 | 1100 | inside_directive (directiveE dir) |
e0001a05 NC |
1101 | { |
1102 | state_stackS *top = directive_state_stack; | |
1103 | ||
1104 | while (top && top->directive != dir) | |
1105 | top = top->prev; | |
1106 | ||
1107 | return (top != NULL); | |
1108 | } | |
1109 | ||
1110 | ||
1111 | static void | |
7fa3d080 | 1112 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1113 | { |
1114 | int len; | |
1115 | unsigned i; | |
43cd72b9 | 1116 | char *directive_string; |
e0001a05 NC |
1117 | |
1118 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1119 | *negated = FALSE; | |
1120 | else | |
1121 | { | |
1122 | *negated = TRUE; | |
1123 | input_line_pointer += 3; | |
1124 | } | |
1125 | ||
1126 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1127 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1128 | ||
1129 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1130 | equivalent to .begin [no-]transform. We should remove it when | |
1131 | we stop accepting those options. */ | |
c138bc38 | 1132 | |
43cd72b9 BW |
1133 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1134 | { | |
1135 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1136 | directive_string = "transform"; | |
1137 | } | |
1138 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1139 | { | |
1140 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1141 | directive_string = "transform"; | |
c138bc38 | 1142 | } |
43cd72b9 BW |
1143 | else |
1144 | directive_string = input_line_pointer; | |
e0001a05 NC |
1145 | |
1146 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1147 | { | |
43cd72b9 | 1148 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1149 | { |
1150 | input_line_pointer += len; | |
1151 | *directive = (directiveE) i; | |
1152 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1153 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1154 | directive_info[i].name); |
1155 | return; | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | as_bad (_("unknown directive")); | |
1160 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1161 | } | |
1162 | ||
1163 | ||
1164 | static void | |
7fa3d080 | 1165 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1166 | { |
1167 | directiveE directive; | |
1168 | bfd_boolean negated; | |
1169 | emit_state *state; | |
e0001a05 NC |
1170 | lit_state *ls; |
1171 | ||
1172 | get_directive (&directive, &negated); | |
1173 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1174 | { | |
1175 | discard_rest_of_line (); | |
1176 | return; | |
1177 | } | |
1178 | ||
43cd72b9 BW |
1179 | if (cur_vinsn.inside_bundle) |
1180 | as_bad (_("directives are not valid inside bundles")); | |
1181 | ||
e0001a05 NC |
1182 | switch (directive) |
1183 | { | |
1184 | case directive_literal: | |
82e7541d BW |
1185 | if (!inside_directive (directive_literal)) |
1186 | { | |
1187 | /* Previous labels go with whatever follows this directive, not with | |
1188 | the literal, so save them now. */ | |
1189 | saved_insn_labels = insn_labels; | |
1190 | insn_labels = NULL; | |
1191 | } | |
43cd72b9 | 1192 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
e0001a05 NC |
1193 | state = (emit_state *) xmalloc (sizeof (emit_state)); |
1194 | xtensa_switch_to_literal_fragment (state); | |
1195 | directive_push (directive_literal, negated, state); | |
1196 | break; | |
1197 | ||
1198 | case directive_literal_prefix: | |
c138bc38 | 1199 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1200 | might produce a literal. */ |
1201 | md_flush_pending_output (); | |
e0001a05 NC |
1202 | /* Check to see if the current fragment is a literal |
1203 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1204 | if (generating_literals) |
e0001a05 NC |
1205 | { |
1206 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1207 | return; | |
1208 | } | |
1209 | ||
1210 | /* Allocate the literal state for this section and push | |
1211 | onto the directive stack. */ | |
1212 | ls = xmalloc (sizeof (lit_state)); | |
1213 | assert (ls); | |
1214 | ||
1215 | *ls = default_lit_sections; | |
e0001a05 NC |
1216 | directive_push (directive_literal_prefix, negated, ls); |
1217 | ||
e0001a05 | 1218 | /* Process the new prefix. */ |
74869ac7 | 1219 | xtensa_literal_prefix (); |
e0001a05 NC |
1220 | break; |
1221 | ||
1222 | case directive_freeregs: | |
1223 | /* This information is currently unused, but we'll accept the statement | |
1224 | and just discard the rest of the line. This won't check the syntax, | |
1225 | but it will accept every correct freeregs directive. */ | |
1226 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1227 | directive_push (directive_freeregs, negated, 0); | |
1228 | break; | |
1229 | ||
43cd72b9 BW |
1230 | case directive_schedule: |
1231 | md_flush_pending_output (); | |
1232 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1233 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1234 | directive_push (directive_schedule, negated, 0); | |
1235 | xtensa_set_frag_assembly_state (frag_now); | |
1236 | break; | |
1237 | ||
e0001a05 | 1238 | case directive_density: |
43cd72b9 BW |
1239 | as_warn (_(".begin [no-]density is ignored")); |
1240 | break; | |
1241 | ||
1242 | case directive_absolute_literals: | |
1243 | md_flush_pending_output (); | |
1244 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1245 | { |
43cd72b9 | 1246 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1247 | break; |
1248 | } | |
43cd72b9 BW |
1249 | xtensa_set_frag_assembly_state (frag_now); |
1250 | directive_push (directive, negated, 0); | |
1251 | break; | |
e0001a05 NC |
1252 | |
1253 | default: | |
43cd72b9 BW |
1254 | md_flush_pending_output (); |
1255 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1256 | directive_push (directive, negated, 0); |
1257 | break; | |
1258 | } | |
1259 | ||
1260 | demand_empty_rest_of_line (); | |
1261 | } | |
1262 | ||
1263 | ||
1264 | static void | |
7fa3d080 | 1265 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1266 | { |
1267 | directiveE begin_directive, end_directive; | |
1268 | bfd_boolean begin_negated, end_negated; | |
1269 | const char *file; | |
1270 | unsigned int line; | |
1271 | emit_state *state; | |
43cd72b9 | 1272 | emit_state **state_ptr; |
e0001a05 NC |
1273 | lit_state *s; |
1274 | ||
43cd72b9 BW |
1275 | if (cur_vinsn.inside_bundle) |
1276 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1277 | |
e0001a05 | 1278 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1279 | |
1280 | md_flush_pending_output (); | |
1281 | ||
1282 | switch (end_directive) | |
e0001a05 | 1283 | { |
43cd72b9 | 1284 | case (directiveE) XTENSA_UNDEFINED: |
e0001a05 NC |
1285 | discard_rest_of_line (); |
1286 | return; | |
e0001a05 | 1287 | |
43cd72b9 BW |
1288 | case directive_density: |
1289 | as_warn (_(".end [no-]density is ignored")); | |
e0001a05 | 1290 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1291 | break; |
1292 | ||
1293 | case directive_absolute_literals: | |
1294 | if (!absolute_literals_supported && !end_negated) | |
1295 | { | |
1296 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1297 | demand_empty_rest_of_line (); | |
1298 | return; | |
1299 | } | |
1300 | break; | |
1301 | ||
1302 | default: | |
1303 | break; | |
e0001a05 NC |
1304 | } |
1305 | ||
43cd72b9 | 1306 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1307 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1308 | (const void **) state_ptr); |
e0001a05 NC |
1309 | |
1310 | if (begin_directive != directive_none) | |
1311 | { | |
1312 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1313 | { | |
1314 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1315 | begin_negated ? "no-" : "", | |
1316 | directive_info[begin_directive].name, file, line); | |
1317 | } | |
1318 | else | |
1319 | { | |
1320 | switch (end_directive) | |
1321 | { | |
1322 | case directive_literal: | |
1323 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1324 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1325 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1326 | free (state); |
82e7541d BW |
1327 | if (!inside_directive (directive_literal)) |
1328 | { | |
1329 | /* Restore the list of current labels. */ | |
1330 | xtensa_clear_insn_labels (); | |
1331 | insn_labels = saved_insn_labels; | |
1332 | } | |
e0001a05 NC |
1333 | break; |
1334 | ||
e0001a05 NC |
1335 | case directive_literal_prefix: |
1336 | /* Restore the default collection sections from saved state. */ | |
1337 | s = (lit_state *) state; | |
1338 | assert (s); | |
e8247da7 | 1339 | default_lit_sections = *s; |
e0001a05 | 1340 | |
74869ac7 BW |
1341 | /* Free the state storage. */ |
1342 | free (s->lit_prefix); | |
e0001a05 NC |
1343 | free (s); |
1344 | break; | |
1345 | ||
43cd72b9 BW |
1346 | case directive_schedule: |
1347 | case directive_freeregs: | |
1348 | break; | |
1349 | ||
e0001a05 | 1350 | default: |
43cd72b9 | 1351 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1352 | break; |
1353 | } | |
1354 | } | |
1355 | } | |
1356 | ||
1357 | demand_empty_rest_of_line (); | |
1358 | } | |
1359 | ||
1360 | ||
1361 | /* Place an aligned literal fragment at the current location. */ | |
1362 | ||
1363 | static void | |
7fa3d080 | 1364 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1365 | { |
43cd72b9 BW |
1366 | md_flush_pending_output (); |
1367 | ||
e0001a05 NC |
1368 | if (inside_directive (directive_literal)) |
1369 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1370 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1371 | |
1372 | demand_empty_rest_of_line (); | |
82e7541d | 1373 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1374 | } |
1375 | ||
1376 | ||
43cd72b9 | 1377 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1378 | |
1379 | static void | |
7fa3d080 | 1380 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1381 | { |
1382 | emit_state state; | |
1745fcba | 1383 | char *p, *base_name; |
e0001a05 | 1384 | char c; |
e0001a05 NC |
1385 | segT dest_seg; |
1386 | ||
82e7541d BW |
1387 | if (inside_directive (directive_literal)) |
1388 | { | |
1389 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1390 | ignore_rest_of_line (); | |
1391 | return; | |
1392 | } | |
1393 | ||
43cd72b9 BW |
1394 | md_flush_pending_output (); |
1395 | ||
82e7541d BW |
1396 | /* Previous labels go with whatever follows this directive, not with |
1397 | the literal, so save them now. */ | |
1398 | saved_insn_labels = insn_labels; | |
1399 | insn_labels = NULL; | |
1400 | ||
e0001a05 NC |
1401 | /* If we are using text-section literals, then this is the right value... */ |
1402 | dest_seg = now_seg; | |
1403 | ||
1404 | base_name = input_line_pointer; | |
1405 | ||
1406 | xtensa_switch_to_literal_fragment (&state); | |
1407 | ||
43cd72b9 | 1408 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1409 | need to put them in the section we just switched to. */ |
43cd72b9 | 1410 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1411 | dest_seg = now_seg; |
1412 | ||
43cd72b9 BW |
1413 | /* All literals are aligned to four-byte boundaries. */ |
1414 | frag_align (2, 0, 0); | |
1415 | record_alignment (now_seg, 2); | |
e0001a05 NC |
1416 | |
1417 | c = get_symbol_end (); | |
1418 | /* Just after name is now '\0'. */ | |
1419 | p = input_line_pointer; | |
1420 | *p = c; | |
1421 | SKIP_WHITESPACE (); | |
1422 | ||
1423 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1424 | { | |
1425 | as_bad (_("expected comma or colon after symbol name; " | |
1426 | "rest of line ignored")); | |
1427 | ignore_rest_of_line (); | |
1428 | xtensa_restore_emit_state (&state); | |
1429 | return; | |
1430 | } | |
1431 | *p = 0; | |
1432 | ||
e0001a05 | 1433 | colon (base_name); |
e0001a05 | 1434 | |
e0001a05 | 1435 | *p = c; |
43cd72b9 | 1436 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1437 | |
43cd72b9 | 1438 | xtensa_elf_cons (4); |
e0001a05 NC |
1439 | |
1440 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1441 | |
1442 | /* Restore the list of current labels. */ | |
1443 | xtensa_clear_insn_labels (); | |
1444 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1445 | } |
1446 | ||
1447 | ||
1448 | static void | |
74869ac7 | 1449 | xtensa_literal_prefix (void) |
e0001a05 | 1450 | { |
74869ac7 BW |
1451 | char *name; |
1452 | int len; | |
1453 | ||
1454 | /* Parse the new prefix from the input_line_pointer. */ | |
1455 | SKIP_WHITESPACE (); | |
1456 | len = strspn (input_line_pointer, | |
1457 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1458 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
e0001a05 NC |
1459 | |
1460 | /* Get a null-terminated copy of the name. */ | |
1461 | name = xmalloc (len + 1); | |
1462 | assert (name); | |
74869ac7 | 1463 | strncpy (name, input_line_pointer, len); |
e0001a05 NC |
1464 | name[len] = 0; |
1465 | ||
74869ac7 BW |
1466 | /* Skip the name in the input line. */ |
1467 | input_line_pointer += len; | |
43cd72b9 | 1468 | |
74869ac7 | 1469 | default_lit_sections.lit_prefix = name; |
43cd72b9 | 1470 | |
74869ac7 | 1471 | /* Clear cached literal sections, since the prefix has changed. */ |
43cd72b9 BW |
1472 | default_lit_sections.lit_seg = NULL; |
1473 | default_lit_sections.lit4_seg = NULL; | |
43cd72b9 BW |
1474 | } |
1475 | ||
1476 | ||
1477 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1478 | ||
1479 | static void | |
7fa3d080 | 1480 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1481 | { |
1482 | float fall_through_f, target_f; | |
43cd72b9 BW |
1483 | |
1484 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1485 | if (fall_through_f < 0) | |
1486 | { | |
1487 | as_bad (_("fall through frequency must be greater than 0")); | |
1488 | ignore_rest_of_line (); | |
1489 | return; | |
1490 | } | |
1491 | ||
1492 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1493 | if (target_f < 0) | |
1494 | { | |
1495 | as_bad (_("branch target frequency must be greater than 0")); | |
1496 | ignore_rest_of_line (); | |
1497 | return; | |
1498 | } | |
1499 | ||
b08b5071 | 1500 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1501 | |
1502 | demand_empty_rest_of_line (); | |
1503 | } | |
1504 | ||
1505 | ||
1506 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1507 | Clobbers input_line_pointer, checks end-of-line. */ | |
1508 | ||
1509 | static void | |
7fa3d080 | 1510 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1511 | { |
1512 | expressionS exp; | |
1513 | bfd_reloc_code_real_type reloc; | |
1514 | ||
1515 | md_flush_pending_output (); | |
1516 | ||
1517 | if (cur_vinsn.inside_bundle) | |
1518 | as_bad (_("directives are not valid inside bundles")); | |
1519 | ||
1520 | if (is_it_end_of_statement ()) | |
1521 | { | |
1522 | demand_empty_rest_of_line (); | |
1523 | return; | |
1524 | } | |
1525 | ||
1526 | do | |
1527 | { | |
1528 | expression (&exp); | |
1529 | if (exp.X_op == O_symbol | |
1530 | && *input_line_pointer == '@' | |
1531 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1532 | != BFD_RELOC_NONE)) | |
1533 | { | |
1534 | reloc_howto_type *reloc_howto = | |
1535 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1536 | ||
1537 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1538 | as_bad (_("unsupported relocation")); | |
1539 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1540 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1541 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1542 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1543 | as_bad (_("opcode-specific %s relocation used outside " | |
1544 | "an instruction"), reloc_howto->name); | |
1545 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
1546 | as_bad (_("%s relocations do not fit in %d bytes"), | |
1547 | reloc_howto->name, nbytes); | |
1548 | else | |
1549 | { | |
1550 | char *p = frag_more ((int) nbytes); | |
1551 | xtensa_set_frag_assembly_state (frag_now); | |
1552 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1553 | nbytes, &exp, 0, reloc); | |
1554 | } | |
1555 | } | |
1556 | else | |
1557 | emit_expr (&exp, (unsigned int) nbytes); | |
1558 | } | |
1559 | while (*input_line_pointer++ == ','); | |
1560 | ||
1561 | input_line_pointer--; /* Put terminator back into stream. */ | |
1562 | demand_empty_rest_of_line (); | |
1563 | } | |
1564 | ||
7fa3d080 BW |
1565 | \f |
1566 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1567 | |
1568 | /* Parse @plt, etc. and return the desired relocation. */ | |
1569 | static bfd_reloc_code_real_type | |
7fa3d080 | 1570 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 | 1571 | { |
43cd72b9 BW |
1572 | char ident[20]; |
1573 | char *str = *str_p; | |
1574 | char *str2; | |
1575 | int ch; | |
1576 | int len; | |
bbdd25a8 | 1577 | struct suffix_reloc_map *ptr; |
43cd72b9 BW |
1578 | |
1579 | if (*str++ != '@') | |
1580 | return BFD_RELOC_NONE; | |
1581 | ||
1582 | for (ch = *str, str2 = ident; | |
1583 | (str2 < ident + sizeof (ident) - 1 | |
1584 | && (ISALNUM (ch) || ch == '@')); | |
1585 | ch = *++str) | |
1586 | { | |
1587 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1588 | } | |
1589 | ||
1590 | *str2 = '\0'; | |
1591 | len = str2 - ident; | |
1592 | ||
1593 | ch = ident[0]; | |
bbdd25a8 BW |
1594 | for (ptr = &suffix_relocs[0]; ptr->length > 0; ptr++) |
1595 | if (ch == ptr->suffix[0] | |
43cd72b9 | 1596 | && len == ptr->length |
bbdd25a8 | 1597 | && memcmp (ident, ptr->suffix, ptr->length) == 0) |
43cd72b9 BW |
1598 | { |
1599 | /* Now check for "identifier@suffix+constant". */ | |
1600 | if (*str == '-' || *str == '+') | |
1601 | { | |
1602 | char *orig_line = input_line_pointer; | |
1603 | expressionS new_exp; | |
1604 | ||
1605 | input_line_pointer = str; | |
1606 | expression (&new_exp); | |
1607 | if (new_exp.X_op == O_constant) | |
1608 | { | |
1609 | exp_p->X_add_number += new_exp.X_add_number; | |
1610 | str = input_line_pointer; | |
1611 | } | |
1612 | ||
1613 | if (&input_line_pointer != str_p) | |
1614 | input_line_pointer = orig_line; | |
1615 | } | |
1616 | ||
1617 | *str_p = str; | |
1618 | return ptr->reloc; | |
1619 | } | |
1620 | ||
1621 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1622 | } |
1623 | ||
e0001a05 | 1624 | |
bbdd25a8 BW |
1625 | /* Find the matching operator type. */ |
1626 | static unsigned char | |
1627 | map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) | |
1628 | { | |
1629 | struct suffix_reloc_map *sfx; | |
1630 | unsigned char operator = (unsigned char) -1; | |
1631 | ||
1632 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1633 | { | |
1634 | if (sfx->reloc == reloc) | |
1635 | { | |
1636 | operator = sfx->operator; | |
1637 | break; | |
1638 | } | |
1639 | } | |
1640 | assert (operator != (unsigned char) -1); | |
1641 | return operator; | |
1642 | } | |
1643 | ||
1644 | ||
1645 | /* Find the matching reloc type. */ | |
1646 | static bfd_reloc_code_real_type | |
1647 | map_operator_to_reloc (unsigned char operator) | |
1648 | { | |
1649 | struct suffix_reloc_map *sfx; | |
1650 | bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; | |
1651 | ||
1652 | for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) | |
1653 | { | |
1654 | if (sfx->operator == operator) | |
1655 | { | |
1656 | reloc = sfx->reloc; | |
1657 | break; | |
1658 | } | |
1659 | } | |
1660 | ||
1661 | if (reloc == BFD_RELOC_UNUSED) | |
1662 | return BFD_RELOC_32; | |
1663 | ||
1664 | return reloc; | |
1665 | } | |
1666 | ||
1667 | ||
e0001a05 | 1668 | static const char * |
7fa3d080 | 1669 | expression_end (const char *name) |
e0001a05 NC |
1670 | { |
1671 | while (1) | |
1672 | { | |
1673 | switch (*name) | |
1674 | { | |
43cd72b9 | 1675 | case '}': |
e0001a05 NC |
1676 | case ';': |
1677 | case '\0': | |
1678 | case ',': | |
43cd72b9 | 1679 | case ':': |
e0001a05 NC |
1680 | return name; |
1681 | case ' ': | |
1682 | case '\t': | |
1683 | ++name; | |
1684 | continue; | |
1685 | default: | |
1686 | return 0; | |
1687 | } | |
1688 | } | |
1689 | } | |
1690 | ||
1691 | ||
1692 | #define ERROR_REG_NUM ((unsigned) -1) | |
1693 | ||
1694 | static unsigned | |
7fa3d080 | 1695 | tc_get_register (const char *prefix) |
e0001a05 NC |
1696 | { |
1697 | unsigned reg; | |
1698 | const char *next_expr; | |
1699 | const char *old_line_pointer; | |
1700 | ||
1701 | SKIP_WHITESPACE (); | |
1702 | old_line_pointer = input_line_pointer; | |
1703 | ||
1704 | if (*input_line_pointer == '$') | |
1705 | ++input_line_pointer; | |
1706 | ||
1707 | /* Accept "sp" as a synonym for "a1". */ | |
1708 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1709 | && expression_end (input_line_pointer + 2)) | |
1710 | { | |
1711 | input_line_pointer += 2; | |
1712 | return 1; /* AR[1] */ | |
1713 | } | |
1714 | ||
1715 | while (*input_line_pointer++ == *prefix++) | |
1716 | ; | |
1717 | --input_line_pointer; | |
1718 | --prefix; | |
1719 | ||
1720 | if (*prefix) | |
1721 | { | |
1722 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1723 | return ERROR_REG_NUM; | |
1724 | } | |
1725 | ||
1726 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1727 | { | |
1728 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1729 | return ERROR_REG_NUM; | |
1730 | } | |
1731 | ||
1732 | reg = 0; | |
1733 | ||
1734 | while (ISDIGIT ((int) *input_line_pointer)) | |
1735 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1736 | ||
1737 | if (!(next_expr = expression_end (input_line_pointer))) | |
1738 | { | |
1739 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1740 | return ERROR_REG_NUM; | |
1741 | } | |
1742 | ||
1743 | input_line_pointer = (char *) next_expr; | |
1744 | ||
1745 | return reg; | |
1746 | } | |
1747 | ||
1748 | ||
e0001a05 | 1749 | static void |
7fa3d080 | 1750 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1751 | { |
43cd72b9 | 1752 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1753 | |
43cd72b9 BW |
1754 | /* Check if this is an immediate operand. */ |
1755 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1756 | { |
43cd72b9 | 1757 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1758 | segT t = expression (tok); |
43cd72b9 BW |
1759 | if (t == absolute_section |
1760 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 NC |
1761 | { |
1762 | assert (tok->X_op == O_constant); | |
1763 | tok->X_op = O_symbol; | |
1764 | tok->X_add_symbol = &abs_symbol; | |
1765 | } | |
43cd72b9 BW |
1766 | |
1767 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
bbdd25a8 BW |
1768 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) |
1769 | != BFD_RELOC_NONE)) | |
e0001a05 | 1770 | { |
bbdd25a8 | 1771 | if (reloc == BFD_RELOC_UNUSED) |
43cd72b9 | 1772 | { |
bbdd25a8 BW |
1773 | as_bad (_("unsupported relocation")); |
1774 | return; | |
1775 | } | |
43cd72b9 | 1776 | |
bbdd25a8 BW |
1777 | if (tok->X_op == O_constant) |
1778 | { | |
1779 | switch (reloc) | |
1780 | { | |
1781 | case BFD_RELOC_LO16: | |
43cd72b9 | 1782 | tok->X_add_number &= 0xffff; |
bbdd25a8 | 1783 | return; |
43cd72b9 | 1784 | |
bbdd25a8 | 1785 | case BFD_RELOC_HI16: |
43cd72b9 | 1786 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; |
bbdd25a8 BW |
1787 | return; |
1788 | ||
1789 | default: | |
1790 | break; | |
1791 | } | |
43cd72b9 | 1792 | } |
bbdd25a8 | 1793 | tok->X_op = map_suffix_reloc_to_operator (reloc); |
e0001a05 | 1794 | } |
e0001a05 NC |
1795 | } |
1796 | else | |
1797 | { | |
43cd72b9 BW |
1798 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1799 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1800 | |
1801 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1802 | { | |
1803 | uint32 buf = reg; | |
43cd72b9 | 1804 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1805 | as_bad (_("register number out of range")); |
1806 | } | |
1807 | ||
1808 | tok->X_op = O_register; | |
1809 | tok->X_add_symbol = 0; | |
1810 | tok->X_add_number = reg; | |
1811 | } | |
1812 | } | |
1813 | ||
1814 | ||
1815 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1816 | ||
1817 | static int | |
7fa3d080 | 1818 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1819 | { |
1820 | char *old_input_line_pointer; | |
1821 | bfd_boolean saw_comma = FALSE; | |
1822 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1823 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1824 | int num_args = 0; |
1825 | char *arg_end, *arg; | |
1826 | int arg_len; | |
43cd72b9 BW |
1827 | |
1828 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1829 | old_input_line_pointer = input_line_pointer; |
1830 | input_line_pointer = str; | |
1831 | ||
1832 | while (*input_line_pointer) | |
1833 | { | |
1834 | SKIP_WHITESPACE (); | |
1835 | switch (*input_line_pointer) | |
1836 | { | |
1837 | case '\0': | |
43cd72b9 | 1838 | case '}': |
e0001a05 NC |
1839 | goto fini; |
1840 | ||
43cd72b9 BW |
1841 | case ':': |
1842 | input_line_pointer++; | |
1843 | if (saw_comma || saw_colon || !saw_arg) | |
1844 | goto err; | |
1845 | saw_colon = TRUE; | |
1846 | break; | |
1847 | ||
e0001a05 NC |
1848 | case ',': |
1849 | input_line_pointer++; | |
43cd72b9 | 1850 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
1851 | goto err; |
1852 | saw_comma = TRUE; | |
1853 | break; | |
1854 | ||
1855 | default: | |
43cd72b9 | 1856 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
1857 | goto err; |
1858 | ||
1859 | arg_end = input_line_pointer + 1; | |
1860 | while (!expression_end (arg_end)) | |
1861 | arg_end += 1; | |
43cd72b9 | 1862 | |
e0001a05 | 1863 | arg_len = arg_end - input_line_pointer; |
43cd72b9 | 1864 | arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
1865 | args[num_args] = arg; |
1866 | ||
43cd72b9 BW |
1867 | if (saw_colon) |
1868 | *arg++ = ':'; | |
e0001a05 NC |
1869 | strncpy (arg, input_line_pointer, arg_len); |
1870 | arg[arg_len] = '\0'; | |
43cd72b9 | 1871 | |
e0001a05 NC |
1872 | input_line_pointer = arg_end; |
1873 | num_args += 1; | |
c138bc38 | 1874 | saw_comma = FALSE; |
43cd72b9 | 1875 | saw_colon = FALSE; |
c138bc38 | 1876 | saw_arg = TRUE; |
e0001a05 NC |
1877 | break; |
1878 | } | |
1879 | } | |
1880 | ||
1881 | fini: | |
43cd72b9 | 1882 | if (saw_comma || saw_colon) |
e0001a05 NC |
1883 | goto err; |
1884 | input_line_pointer = old_input_line_pointer; | |
1885 | return num_args; | |
1886 | ||
1887 | err: | |
43cd72b9 BW |
1888 | if (saw_comma) |
1889 | as_bad (_("extra comma")); | |
1890 | else if (saw_colon) | |
1891 | as_bad (_("extra colon")); | |
1892 | else if (!saw_arg) | |
c138bc38 | 1893 | as_bad (_("missing argument")); |
43cd72b9 BW |
1894 | else |
1895 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
1896 | input_line_pointer = old_input_line_pointer; |
1897 | return -1; | |
1898 | } | |
1899 | ||
1900 | ||
43cd72b9 | 1901 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
1902 | |
1903 | static bfd_boolean | |
7fa3d080 | 1904 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 1905 | { |
43cd72b9 | 1906 | expressionS *tok, *last_tok; |
e0001a05 NC |
1907 | xtensa_opcode opcode = insn->opcode; |
1908 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
1909 | xtensa_isa isa = xtensa_default_isa; |
1910 | int n, num_regs = 0; | |
e0001a05 | 1911 | int opcode_operand_count; |
43cd72b9 BW |
1912 | int opnd_cnt, last_opnd_cnt; |
1913 | unsigned int next_reg = 0; | |
e0001a05 NC |
1914 | char *old_input_line_pointer; |
1915 | ||
1916 | if (insn->insn_type == ITYPE_LITERAL) | |
1917 | opcode_operand_count = 1; | |
1918 | else | |
43cd72b9 | 1919 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 1920 | |
43cd72b9 | 1921 | tok = insn->tok; |
e0001a05 NC |
1922 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
1923 | ||
1924 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
1925 | old_input_line_pointer = input_line_pointer; |
1926 | ||
1927 | last_tok = 0; | |
1928 | last_opnd_cnt = -1; | |
1929 | opnd_cnt = 0; | |
1930 | ||
1931 | /* Skip invisible operands. */ | |
1932 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
1933 | { | |
1934 | opnd_cnt += 1; | |
1935 | tok++; | |
1936 | } | |
e0001a05 NC |
1937 | |
1938 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 1939 | { |
e0001a05 | 1940 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
1941 | if (*input_line_pointer == ':') |
1942 | { | |
1943 | xtensa_regfile opnd_rf; | |
1944 | input_line_pointer++; | |
1945 | if (num_regs == 0) | |
1946 | goto err; | |
1947 | assert (opnd_cnt > 0); | |
1948 | num_regs--; | |
1949 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
1950 | if (next_reg | |
1951 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
1952 | as_warn (_("incorrect register number, ignoring")); | |
1953 | next_reg++; | |
1954 | } | |
1955 | else | |
1956 | { | |
1957 | if (opnd_cnt >= opcode_operand_count) | |
1958 | { | |
1959 | as_warn (_("too many arguments")); | |
1960 | goto err; | |
1961 | } | |
1962 | assert (opnd_cnt < MAX_INSN_ARGS); | |
1963 | ||
1964 | expression_maybe_register (opcode, opnd_cnt, tok); | |
1965 | next_reg = tok->X_add_number + 1; | |
1966 | ||
1967 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
1968 | goto err; | |
1969 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
1970 | { | |
1971 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
1972 | /* minus 1 because we are seeing one right now */ | |
1973 | } | |
1974 | else | |
1975 | num_regs = 0; | |
e0001a05 | 1976 | |
43cd72b9 BW |
1977 | last_tok = tok; |
1978 | last_opnd_cnt = opnd_cnt; | |
e0001a05 | 1979 | |
43cd72b9 BW |
1980 | do |
1981 | { | |
1982 | opnd_cnt += 1; | |
1983 | tok++; | |
1984 | } | |
1985 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
1986 | } | |
1987 | } | |
e0001a05 | 1988 | |
43cd72b9 BW |
1989 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
1990 | goto err; | |
e0001a05 NC |
1991 | |
1992 | insn->ntok = tok - insn->tok; | |
c138bc38 | 1993 | had_error = FALSE; |
e0001a05 NC |
1994 | |
1995 | err: | |
43cd72b9 | 1996 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
1997 | return had_error; |
1998 | } | |
1999 | ||
2000 | ||
43cd72b9 | 2001 | static int |
7fa3d080 | 2002 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2003 | { |
2004 | xtensa_isa isa = xtensa_default_isa; | |
2005 | static xtensa_insnbuf slotbuf = NULL; | |
2006 | xtensa_format fmt; | |
2007 | xtensa_opcode opc = insn->opcode; | |
2008 | int slot, opnd, fmt_found; | |
2009 | unsigned val; | |
2010 | ||
2011 | if (!slotbuf) | |
2012 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2013 | ||
2014 | /* Find format/slot where this can be encoded. */ | |
2015 | fmt_found = 0; | |
2016 | slot = 0; | |
2017 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2018 | { | |
2019 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2020 | { | |
2021 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2022 | { | |
2023 | fmt_found = 1; | |
2024 | break; | |
2025 | } | |
2026 | } | |
2027 | if (fmt_found) break; | |
2028 | } | |
2029 | ||
2030 | if (!fmt_found) | |
2031 | { | |
2032 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2033 | return -1; | |
2034 | } | |
2035 | ||
2036 | /* First encode all the visible operands | |
2037 | (to deal with shared field operands). */ | |
2038 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2039 | { | |
2040 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2041 | && (insn->tok[opnd].X_op == O_register | |
2042 | || insn->tok[opnd].X_op == O_constant)) | |
2043 | { | |
2044 | val = insn->tok[opnd].X_add_number; | |
2045 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2046 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2047 | } | |
2048 | } | |
2049 | ||
2050 | /* Then pull out the values for the invisible ones. */ | |
2051 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2052 | { | |
2053 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2054 | { | |
2055 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2056 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2057 | insn->tok[opnd].X_add_number = val; | |
2058 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2059 | insn->tok[opnd].X_op = O_register; | |
2060 | else | |
2061 | insn->tok[opnd].X_op = O_constant; | |
2062 | } | |
2063 | } | |
2064 | ||
2065 | return 0; | |
2066 | } | |
2067 | ||
2068 | ||
e0001a05 | 2069 | static void |
7fa3d080 | 2070 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2071 | { |
2072 | char *cnt_arg, *new_arg; | |
2073 | cnt_arg = *cnt_argp; | |
2074 | ||
2075 | /* replace the argument with "31-(argument)" */ | |
2076 | new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); | |
2077 | sprintf (new_arg, "31-(%s)", cnt_arg); | |
2078 | ||
2079 | free (cnt_arg); | |
2080 | *cnt_argp = new_arg; | |
2081 | } | |
2082 | ||
2083 | ||
2084 | /* If "arg" is a constant expression, return non-zero with the value | |
2085 | in *valp. */ | |
2086 | ||
2087 | static int | |
7fa3d080 | 2088 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2089 | { |
2090 | expressionS exp; | |
2091 | char *save_ptr = input_line_pointer; | |
2092 | ||
2093 | input_line_pointer = arg; | |
2094 | expression (&exp); | |
2095 | input_line_pointer = save_ptr; | |
2096 | ||
2097 | if (exp.X_op == O_constant) | |
2098 | { | |
2099 | *valp = exp.X_add_number; | |
2100 | return 1; | |
2101 | } | |
2102 | ||
2103 | return 0; | |
2104 | } | |
2105 | ||
2106 | ||
2107 | static void | |
7fa3d080 | 2108 | xg_replace_opname (char **popname, char *newop) |
e0001a05 NC |
2109 | { |
2110 | free (*popname); | |
2111 | *popname = (char *) xmalloc (strlen (newop) + 1); | |
2112 | strcpy (*popname, newop); | |
2113 | } | |
2114 | ||
2115 | ||
2116 | static int | |
7fa3d080 BW |
2117 | xg_check_num_args (int *pnum_args, |
2118 | int expected_num, | |
2119 | char *opname, | |
2120 | char **arg_strings) | |
e0001a05 NC |
2121 | { |
2122 | int num_args = *pnum_args; | |
2123 | ||
43cd72b9 | 2124 | if (num_args < expected_num) |
e0001a05 NC |
2125 | { |
2126 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2127 | num_args, opname, expected_num); | |
2128 | return -1; | |
2129 | } | |
2130 | ||
2131 | if (num_args > expected_num) | |
2132 | { | |
2133 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2134 | num_args, opname, expected_num); | |
2135 | while (num_args-- > expected_num) | |
2136 | { | |
2137 | free (arg_strings[num_args]); | |
2138 | arg_strings[num_args] = 0; | |
2139 | } | |
2140 | *pnum_args = expected_num; | |
2141 | return -1; | |
2142 | } | |
2143 | ||
2144 | return 0; | |
2145 | } | |
2146 | ||
2147 | ||
43cd72b9 BW |
2148 | /* If the register is not specified as part of the opcode, |
2149 | then get it from the operand and move it to the opcode. */ | |
2150 | ||
e0001a05 | 2151 | static int |
7fa3d080 | 2152 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2153 | { |
43cd72b9 BW |
2154 | xtensa_isa isa = xtensa_default_isa; |
2155 | xtensa_sysreg sr; | |
e0001a05 | 2156 | char *opname, *new_opname; |
43cd72b9 BW |
2157 | const char *sr_name; |
2158 | int is_user, is_write; | |
e0001a05 NC |
2159 | |
2160 | opname = *popname; | |
2161 | if (*opname == '_') | |
80ca4e2c | 2162 | opname += 1; |
43cd72b9 BW |
2163 | is_user = (opname[1] == 'u'); |
2164 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2165 | |
43cd72b9 | 2166 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2167 | |
43cd72b9 BW |
2168 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2169 | return -1; | |
e0001a05 | 2170 | |
43cd72b9 BW |
2171 | /* Check if the argument is a symbolic register name. */ |
2172 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2173 | /* Handle WSR to "INTSET" as a special case. */ | |
2174 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2175 | && !strcasecmp (arg_strings[1], "intset")) | |
2176 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2177 | if (sr == XTENSA_UNDEFINED | |
2178 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2179 | { | |
2180 | /* Maybe it's a register number.... */ | |
2181 | offsetT val; | |
e0001a05 NC |
2182 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2183 | { | |
43cd72b9 BW |
2184 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2185 | arg_strings[1], opname); | |
e0001a05 NC |
2186 | return -1; |
2187 | } | |
43cd72b9 BW |
2188 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2189 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2190 | { |
43cd72b9 | 2191 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2192 | (long) val, opname); |
e0001a05 NC |
2193 | return -1; |
2194 | } | |
43cd72b9 | 2195 | } |
e0001a05 | 2196 | |
43cd72b9 BW |
2197 | /* Remove the last argument, which is now part of the opcode. */ |
2198 | free (arg_strings[1]); | |
2199 | arg_strings[1] = 0; | |
2200 | *pnum_args = 1; | |
2201 | ||
2202 | /* Translate the opcode. */ | |
2203 | sr_name = xtensa_sysreg_name (isa, sr); | |
2204 | /* Another special case for "WSR.INTSET".... */ | |
2205 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2206 | sr_name = "intset"; | |
2207 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
80ca4e2c | 2208 | sprintf (new_opname, "%s.%s", *popname, sr_name); |
43cd72b9 BW |
2209 | free (*popname); |
2210 | *popname = new_opname; | |
2211 | ||
2212 | return 0; | |
2213 | } | |
2214 | ||
2215 | ||
2216 | static int | |
7fa3d080 | 2217 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2218 | { |
2219 | xtensa_isa isa = xtensa_default_isa; | |
2220 | xtensa_sysreg sr; | |
2221 | char *opname, *new_opname; | |
2222 | const char *sr_name; | |
2223 | bfd_boolean has_underbar = FALSE; | |
2224 | ||
2225 | opname = *popname; | |
2226 | if (opname[0] == '_') | |
2227 | { | |
2228 | has_underbar = TRUE; | |
2229 | opname += 1; | |
2230 | } | |
2231 | ||
2232 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2233 | if (sr != XTENSA_UNDEFINED) | |
2234 | { | |
2235 | /* The new default name ("nnn") is different from the old default | |
2236 | name ("URnnn"). The old default is handled below, and we don't | |
2237 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2238 | default. */ | |
2239 | static char namebuf[10]; | |
2240 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2241 | if (strcmp (namebuf, opname + 1) == 0) | |
2242 | return 0; | |
2243 | } | |
2244 | else | |
2245 | { | |
2246 | offsetT val; | |
2247 | char *end; | |
2248 | ||
2249 | /* Only continue if the reg name is "URnnn". */ | |
2250 | if (opname[1] != 'u' || opname[2] != 'r') | |
2251 | return 0; | |
2252 | val = strtoul (opname + 3, &end, 10); | |
2253 | if (*end != '\0') | |
2254 | return 0; | |
2255 | ||
2256 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2257 | if (sr == XTENSA_UNDEFINED) | |
2258 | { | |
2259 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2260 | (long) val, opname); |
43cd72b9 BW |
2261 | return -1; |
2262 | } | |
2263 | } | |
2264 | ||
2265 | /* Translate the opcode. */ | |
2266 | sr_name = xtensa_sysreg_name (isa, sr); | |
2267 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
2268 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), | |
2269 | opname[0], sr_name); | |
2270 | free (*popname); | |
2271 | *popname = new_opname; | |
2272 | ||
2273 | return 0; | |
2274 | } | |
2275 | ||
2276 | ||
2277 | static int | |
7fa3d080 BW |
2278 | xtensa_translate_zero_immed (char *old_op, |
2279 | char *new_op, | |
2280 | char **popname, | |
2281 | int *pnum_args, | |
2282 | char **arg_strings) | |
43cd72b9 BW |
2283 | { |
2284 | char *opname; | |
2285 | offsetT val; | |
2286 | ||
2287 | opname = *popname; | |
2288 | assert (opname[0] != '_'); | |
2289 | ||
2290 | if (strcmp (opname, old_op) != 0) | |
2291 | return 0; | |
e0001a05 | 2292 | |
43cd72b9 BW |
2293 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2294 | return -1; | |
2295 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2296 | { | |
2297 | xg_replace_opname (popname, new_op); | |
2298 | free (arg_strings[1]); | |
2299 | arg_strings[1] = arg_strings[2]; | |
2300 | arg_strings[2] = 0; | |
2301 | *pnum_args = 2; | |
e0001a05 NC |
2302 | } |
2303 | ||
2304 | return 0; | |
2305 | } | |
2306 | ||
2307 | ||
2308 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2309 | Returns non-zero if an error was found. */ | |
2310 | ||
2311 | static int | |
7fa3d080 | 2312 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2313 | { |
2314 | char *opname = *popname; | |
2315 | bfd_boolean has_underbar = FALSE; | |
2316 | ||
2317 | if (*opname == '_') | |
2318 | { | |
2319 | has_underbar = TRUE; | |
2320 | opname += 1; | |
2321 | } | |
2322 | ||
2323 | if (strcmp (opname, "mov") == 0) | |
2324 | { | |
43cd72b9 | 2325 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2326 | xg_replace_opname (popname, "mov.n"); |
2327 | else | |
2328 | { | |
2329 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2330 | return -1; | |
2331 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2332 | arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); | |
2333 | strcpy (arg_strings[2], arg_strings[1]); | |
2334 | *pnum_args = 3; | |
2335 | } | |
2336 | return 0; | |
2337 | } | |
2338 | ||
2339 | if (strcmp (opname, "bbsi.l") == 0) | |
2340 | { | |
2341 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2342 | return -1; | |
2343 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2344 | if (target_big_endian) | |
2345 | xg_reverse_shift_count (&arg_strings[1]); | |
2346 | return 0; | |
2347 | } | |
2348 | ||
2349 | if (strcmp (opname, "bbci.l") == 0) | |
2350 | { | |
2351 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2352 | return -1; | |
2353 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2354 | if (target_big_endian) | |
2355 | xg_reverse_shift_count (&arg_strings[1]); | |
2356 | return 0; | |
2357 | } | |
2358 | ||
eb6d9dce BW |
2359 | /* Don't do anything special with NOPs inside FLIX instructions. They |
2360 | are handled elsewhere. Real NOP instructions are always available | |
2361 | in configurations with FLIX, so this should never be an issue but | |
2362 | check for it anyway. */ | |
2363 | if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED | |
43cd72b9 | 2364 | && strcmp (opname, "nop") == 0) |
e0001a05 | 2365 | { |
43cd72b9 | 2366 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2367 | xg_replace_opname (popname, "nop.n"); |
2368 | else | |
2369 | { | |
2370 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2371 | return -1; | |
2372 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2373 | arg_strings[0] = (char *) xmalloc (3); | |
2374 | arg_strings[1] = (char *) xmalloc (3); | |
2375 | arg_strings[2] = (char *) xmalloc (3); | |
2376 | strcpy (arg_strings[0], "a1"); | |
2377 | strcpy (arg_strings[1], "a1"); | |
2378 | strcpy (arg_strings[2], "a1"); | |
2379 | *pnum_args = 3; | |
2380 | } | |
2381 | return 0; | |
2382 | } | |
2383 | ||
43cd72b9 BW |
2384 | /* Recognize [RW]UR and [RWX]SR. */ |
2385 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2386 | && (opname[1] == 'u' || opname[1] == 's')) | |
2387 | || (opname[0] == 'x' && opname[1] == 's')) | |
2388 | && opname[2] == 'r' | |
2389 | && opname[3] == '\0') | |
e0001a05 NC |
2390 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2391 | ||
43cd72b9 BW |
2392 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2393 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2394 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2395 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2396 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2397 | |
43cd72b9 BW |
2398 | /* Relax branches that don't allow comparisons against an immediate value |
2399 | of zero to the corresponding branches with implicit zero immediates. */ | |
2400 | if (!has_underbar && use_transform ()) | |
2401 | { | |
2402 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2403 | pnum_args, arg_strings)) | |
2404 | return -1; | |
e0001a05 | 2405 | |
43cd72b9 BW |
2406 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2407 | pnum_args, arg_strings)) | |
2408 | return -1; | |
e0001a05 | 2409 | |
43cd72b9 BW |
2410 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2411 | pnum_args, arg_strings)) | |
2412 | return -1; | |
e0001a05 | 2413 | |
43cd72b9 BW |
2414 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2415 | pnum_args, arg_strings)) | |
2416 | return -1; | |
2417 | } | |
e0001a05 | 2418 | |
43cd72b9 BW |
2419 | return 0; |
2420 | } | |
e0001a05 | 2421 | |
43cd72b9 BW |
2422 | \f |
2423 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2424 | |
43cd72b9 BW |
2425 | /* Currently the assembler only allows us to use a single target per |
2426 | fragment. Because of this, only one operand for a given | |
2427 | instruction may be symbolic. If there is a PC-relative operand, | |
2428 | the last one is chosen. Otherwise, the result is the number of the | |
2429 | last immediate operand, and if there are none of those, we fail and | |
2430 | return -1. */ | |
e0001a05 | 2431 | |
7fa3d080 BW |
2432 | static int |
2433 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2434 | { |
2435 | int last_immed = -1; | |
2436 | int noperands, opi; | |
e0001a05 | 2437 | |
43cd72b9 BW |
2438 | if (opcode == XTENSA_UNDEFINED) |
2439 | return -1; | |
e0001a05 | 2440 | |
43cd72b9 BW |
2441 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2442 | for (opi = noperands - 1; opi >= 0; opi--) | |
2443 | { | |
2444 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2445 | continue; | |
2446 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2447 | return opi; | |
2448 | if (last_immed == -1 | |
2449 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2450 | last_immed = opi; | |
e0001a05 | 2451 | } |
43cd72b9 | 2452 | return last_immed; |
e0001a05 NC |
2453 | } |
2454 | ||
e0001a05 | 2455 | |
43cd72b9 | 2456 | static xtensa_opcode |
7fa3d080 | 2457 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2458 | { |
43cd72b9 BW |
2459 | static xtensa_insnbuf insnbuf = NULL; |
2460 | static xtensa_insnbuf slotbuf = NULL; | |
2461 | xtensa_isa isa = xtensa_default_isa; | |
2462 | xtensa_format fmt; | |
2463 | ||
2464 | if (!insnbuf) | |
e0001a05 | 2465 | { |
43cd72b9 BW |
2466 | insnbuf = xtensa_insnbuf_alloc (isa); |
2467 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2468 | } |
e0001a05 | 2469 | |
d77b99c9 | 2470 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2471 | fmt = xtensa_format_decode (isa, insnbuf); |
2472 | if (fmt == XTENSA_UNDEFINED) | |
2473 | return XTENSA_UNDEFINED; | |
e0001a05 | 2474 | |
43cd72b9 BW |
2475 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2476 | return XTENSA_UNDEFINED; | |
e0001a05 | 2477 | |
43cd72b9 BW |
2478 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2479 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2480 | } |
2481 | ||
2482 | ||
43cd72b9 | 2483 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2484 | |
43cd72b9 | 2485 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2486 | |
7fa3d080 BW |
2487 | static void |
2488 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2489 | { |
2490 | int num_opcodes, num_operands; | |
2491 | xtensa_opcode opcode; | |
2492 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2493 | |
43cd72b9 BW |
2494 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2495 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2496 | { |
43cd72b9 BW |
2497 | int opn; |
2498 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2499 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2500 | for (opn = 0; opn < num_operands; opn++) | |
2501 | { | |
2502 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2503 | continue; | |
2504 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2505 | { | |
2506 | xtensa_regfile opnd_rf = | |
2507 | xtensa_operand_regfile (isa, opcode, opn); | |
2508 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2509 | } | |
2510 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2511 | fputs ("[lLr] ", stderr); | |
2512 | else | |
2513 | fputs ("i ", stderr); | |
2514 | } | |
2515 | fprintf (stderr, "\n"); | |
e0001a05 | 2516 | } |
e0001a05 NC |
2517 | } |
2518 | ||
2519 | ||
43cd72b9 | 2520 | static void |
7fa3d080 | 2521 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2522 | { |
e0001a05 | 2523 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2524 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2525 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2526 | int op; | |
e0001a05 | 2527 | |
43cd72b9 | 2528 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2529 | |
43cd72b9 BW |
2530 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2531 | { | |
2532 | xtensa_opcode opcode; | |
2533 | const char *opname; | |
2534 | int operands; | |
2535 | ||
2536 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2537 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2538 | opname = xtensa_opcode_name (isa, opcode); | |
2539 | ||
2540 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2541 | fprintf (stderr, " operands = "); | |
2542 | for (operands = 0; | |
2543 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2544 | operands++) | |
2545 | { | |
2546 | unsigned int val; | |
2547 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2548 | continue; | |
2549 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2550 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2551 | fprintf (stderr, "%d ", val); | |
2552 | } | |
2553 | fprintf (stderr, "\n"); | |
2554 | } | |
2555 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2556 | } |
2557 | ||
43cd72b9 BW |
2558 | #endif /* TENSILICA_DEBUG */ |
2559 | ||
e0001a05 NC |
2560 | |
2561 | static bfd_boolean | |
7fa3d080 | 2562 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2563 | { |
43cd72b9 BW |
2564 | xtensa_isa isa = xtensa_default_isa; |
2565 | int n, num_operands; | |
e0001a05 | 2566 | |
64b607e6 | 2567 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
e0001a05 NC |
2568 | return FALSE; |
2569 | ||
43cd72b9 BW |
2570 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2571 | for (n = 0; n < num_operands; n++) | |
2572 | { | |
2573 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2574 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2575 | return TRUE; | |
2576 | } | |
2577 | return FALSE; | |
e0001a05 NC |
2578 | } |
2579 | ||
2580 | ||
43cd72b9 BW |
2581 | /* Convert from BFD relocation type code to slot and operand number. |
2582 | Returns non-zero on failure. */ | |
e0001a05 | 2583 | |
43cd72b9 | 2584 | static int |
7fa3d080 | 2585 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2586 | { |
43cd72b9 BW |
2587 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2588 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2589 | { |
43cd72b9 BW |
2590 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2591 | *is_alt = FALSE; | |
e0001a05 | 2592 | } |
43cd72b9 BW |
2593 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2594 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2595 | { |
43cd72b9 BW |
2596 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2597 | *is_alt = TRUE; | |
e0001a05 | 2598 | } |
43cd72b9 BW |
2599 | else |
2600 | return -1; | |
2601 | ||
2602 | return 0; | |
e0001a05 NC |
2603 | } |
2604 | ||
2605 | ||
43cd72b9 BW |
2606 | /* Convert from slot number to BFD relocation type code for the |
2607 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2608 | failure. */ | |
e0001a05 | 2609 | |
43cd72b9 | 2610 | static bfd_reloc_code_real_type |
7fa3d080 | 2611 | encode_reloc (int slot) |
e0001a05 | 2612 | { |
43cd72b9 BW |
2613 | if (slot < 0 || slot > 14) |
2614 | return BFD_RELOC_NONE; | |
2615 | ||
2616 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2617 | } |
2618 | ||
2619 | ||
43cd72b9 BW |
2620 | /* Convert from slot numbers to BFD relocation type code for the |
2621 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2622 | |
43cd72b9 | 2623 | static bfd_reloc_code_real_type |
7fa3d080 | 2624 | encode_alt_reloc (int slot) |
e0001a05 | 2625 | { |
43cd72b9 BW |
2626 | if (slot < 0 || slot > 14) |
2627 | return BFD_RELOC_NONE; | |
2628 | ||
2629 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2630 | } |
2631 | ||
2632 | ||
2633 | static void | |
7fa3d080 BW |
2634 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2635 | xtensa_format fmt, | |
2636 | int slot, | |
2637 | xtensa_opcode opcode, | |
2638 | int operand, | |
2639 | uint32 value, | |
2640 | const char *file, | |
2641 | unsigned int line) | |
e0001a05 | 2642 | { |
e0001a05 NC |
2643 | uint32 valbuf = value; |
2644 | ||
43cd72b9 | 2645 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2646 | { |
43cd72b9 BW |
2647 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2648 | == 1) | |
2649 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2650 | _("operand %d of '%s' has out of range value '%u'"), |
2651 | operand + 1, | |
2652 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2653 | value); | |
43cd72b9 BW |
2654 | else |
2655 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2656 | _("operand %d of '%s' has invalid value '%u'"), |
2657 | operand + 1, | |
2658 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2659 | value); | |
43cd72b9 | 2660 | return; |
e0001a05 NC |
2661 | } |
2662 | ||
43cd72b9 BW |
2663 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2664 | slotbuf, valbuf); | |
e0001a05 NC |
2665 | } |
2666 | ||
2667 | ||
2668 | static uint32 | |
7fa3d080 BW |
2669 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2670 | xtensa_format fmt, | |
2671 | int slot, | |
2672 | xtensa_opcode opcode, | |
2673 | int opnum) | |
e0001a05 | 2674 | { |
43cd72b9 BW |
2675 | uint32 val = 0; |
2676 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2677 | fmt, slot, slotbuf, &val); | |
2678 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2679 | return val; | |
e0001a05 NC |
2680 | } |
2681 | ||
e0001a05 | 2682 | \f |
7fa3d080 | 2683 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2684 | |
7fa3d080 BW |
2685 | /* The routine xg_instruction_matches_option_term must return TRUE |
2686 | when a given option term is true. The meaning of all of the option | |
2687 | terms is given interpretation by this function. This is needed when | |
2688 | an option depends on the state of a directive, but there are no such | |
2689 | options in use right now. */ | |
e0001a05 | 2690 | |
7fa3d080 BW |
2691 | static bfd_boolean |
2692 | xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED, | |
2693 | const ReqOrOption *option) | |
e0001a05 | 2694 | { |
7fa3d080 BW |
2695 | if (strcmp (option->option_name, "realnop") == 0 |
2696 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2697 | { | |
2698 | /* These conditions were evaluated statically when building the | |
2699 | relaxation table. There's no need to reevaluate them now. */ | |
2700 | return TRUE; | |
2701 | } | |
2702 | else | |
2703 | { | |
2704 | as_fatal (_("internal error: unknown option name '%s'"), | |
2705 | option->option_name); | |
2706 | } | |
e0001a05 NC |
2707 | } |
2708 | ||
2709 | ||
7fa3d080 BW |
2710 | static bfd_boolean |
2711 | xg_instruction_matches_or_options (TInsn *insn, | |
2712 | const ReqOrOptionList *or_option) | |
e0001a05 | 2713 | { |
7fa3d080 BW |
2714 | const ReqOrOption *option; |
2715 | /* Must match each of the AND terms. */ | |
2716 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2717 | { |
7fa3d080 BW |
2718 | if (xg_instruction_matches_option_term (insn, option)) |
2719 | return TRUE; | |
e0001a05 | 2720 | } |
7fa3d080 | 2721 | return FALSE; |
e0001a05 NC |
2722 | } |
2723 | ||
2724 | ||
7fa3d080 BW |
2725 | static bfd_boolean |
2726 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2727 | { |
7fa3d080 BW |
2728 | const ReqOption *req_options; |
2729 | /* Must match each of the AND terms. */ | |
2730 | for (req_options = options; | |
2731 | req_options != NULL; | |
2732 | req_options = req_options->next) | |
e0001a05 | 2733 | { |
7fa3d080 BW |
2734 | /* Must match one of the OR clauses. */ |
2735 | if (!xg_instruction_matches_or_options (insn, | |
2736 | req_options->or_option_terms)) | |
2737 | return FALSE; | |
e0001a05 | 2738 | } |
7fa3d080 | 2739 | return TRUE; |
e0001a05 NC |
2740 | } |
2741 | ||
2742 | ||
7fa3d080 | 2743 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2744 | |
7fa3d080 BW |
2745 | static bfd_boolean |
2746 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2747 | { |
7fa3d080 | 2748 | PreconditionList *condition_l; |
e0001a05 | 2749 | |
7fa3d080 BW |
2750 | if (rule->opcode != insn->opcode) |
2751 | return FALSE; | |
e0001a05 | 2752 | |
7fa3d080 BW |
2753 | for (condition_l = rule->conditions; |
2754 | condition_l != NULL; | |
2755 | condition_l = condition_l->next) | |
e0001a05 | 2756 | { |
7fa3d080 BW |
2757 | expressionS *exp1; |
2758 | expressionS *exp2; | |
2759 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2760 | |
7fa3d080 | 2761 | switch (cond->typ) |
e0001a05 | 2762 | { |
7fa3d080 BW |
2763 | case OP_CONSTANT: |
2764 | /* The expression must be the constant. */ | |
2765 | assert (cond->op_num < insn->ntok); | |
2766 | exp1 = &insn->tok[cond->op_num]; | |
2767 | if (expr_is_const (exp1)) | |
2768 | { | |
2769 | switch (cond->cmp) | |
2770 | { | |
2771 | case OP_EQUAL: | |
2772 | if (get_expr_const (exp1) != cond->op_data) | |
2773 | return FALSE; | |
2774 | break; | |
2775 | case OP_NOTEQUAL: | |
2776 | if (get_expr_const (exp1) == cond->op_data) | |
2777 | return FALSE; | |
2778 | break; | |
2779 | default: | |
2780 | return FALSE; | |
2781 | } | |
2782 | } | |
2783 | else if (expr_is_register (exp1)) | |
2784 | { | |
2785 | switch (cond->cmp) | |
2786 | { | |
2787 | case OP_EQUAL: | |
2788 | if (get_expr_register (exp1) != cond->op_data) | |
2789 | return FALSE; | |
2790 | break; | |
2791 | case OP_NOTEQUAL: | |
2792 | if (get_expr_register (exp1) == cond->op_data) | |
2793 | return FALSE; | |
2794 | break; | |
2795 | default: | |
2796 | return FALSE; | |
2797 | } | |
2798 | } | |
2799 | else | |
2800 | return FALSE; | |
2801 | break; | |
2802 | ||
2803 | case OP_OPERAND: | |
2804 | assert (cond->op_num < insn->ntok); | |
2805 | assert (cond->op_data < insn->ntok); | |
2806 | exp1 = &insn->tok[cond->op_num]; | |
2807 | exp2 = &insn->tok[cond->op_data]; | |
2808 | ||
2809 | switch (cond->cmp) | |
2810 | { | |
2811 | case OP_EQUAL: | |
2812 | if (!expr_is_equal (exp1, exp2)) | |
2813 | return FALSE; | |
2814 | break; | |
2815 | case OP_NOTEQUAL: | |
2816 | if (expr_is_equal (exp1, exp2)) | |
2817 | return FALSE; | |
2818 | break; | |
2819 | } | |
2820 | break; | |
2821 | ||
2822 | case OP_LITERAL: | |
2823 | case OP_LABEL: | |
2824 | default: | |
2825 | return FALSE; | |
2826 | } | |
2827 | } | |
2828 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2829 | return FALSE; | |
2830 | ||
2831 | return TRUE; | |
2832 | } | |
2833 | ||
2834 | ||
2835 | static int | |
2836 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2837 | { | |
2838 | bfd_boolean a_greater = FALSE; | |
2839 | bfd_boolean b_greater = FALSE; | |
2840 | ||
2841 | ReqOptionList *l_a = a->options; | |
2842 | ReqOptionList *l_b = b->options; | |
2843 | ||
2844 | /* We only care if they both are the same except for | |
2845 | a const16 vs. an l32r. */ | |
2846 | ||
2847 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2848 | { | |
2849 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2850 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2851 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2852 | { | |
2853 | if (l_or_a->is_true != l_or_b->is_true) | |
2854 | return 0; | |
2855 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2856 | { | |
2857 | /* This is the case we care about. */ | |
2858 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
2859 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
2860 | { | |
2861 | if (prefer_const16) | |
2862 | a_greater = TRUE; | |
2863 | else | |
2864 | b_greater = TRUE; | |
2865 | } | |
2866 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
2867 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
2868 | { | |
2869 | if (prefer_const16) | |
2870 | b_greater = TRUE; | |
2871 | else | |
2872 | a_greater = TRUE; | |
2873 | } | |
2874 | else | |
2875 | return 0; | |
2876 | } | |
2877 | l_or_a = l_or_a->next; | |
2878 | l_or_b = l_or_b->next; | |
2879 | } | |
2880 | if (l_or_a || l_or_b) | |
2881 | return 0; | |
2882 | ||
2883 | l_a = l_a->next; | |
2884 | l_b = l_b->next; | |
2885 | } | |
2886 | if (l_a || l_b) | |
2887 | return 0; | |
2888 | ||
2889 | /* Incomparable if the substitution was used differently in two cases. */ | |
2890 | if (a_greater && b_greater) | |
2891 | return 0; | |
2892 | ||
2893 | if (b_greater) | |
2894 | return 1; | |
2895 | if (a_greater) | |
2896 | return -1; | |
2897 | ||
2898 | return 0; | |
2899 | } | |
2900 | ||
2901 | ||
2902 | static TransitionRule * | |
2903 | xg_instruction_match (TInsn *insn) | |
2904 | { | |
2905 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
2906 | TransitionList *l; | |
2907 | assert (insn->opcode < table->num_opcodes); | |
2908 | ||
2909 | /* Walk through all of the possible transitions. */ | |
2910 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2911 | { | |
2912 | TransitionRule *rule = l->rule; | |
2913 | if (xg_instruction_matches_rule (insn, rule)) | |
2914 | return rule; | |
2915 | } | |
2916 | return NULL; | |
2917 | } | |
2918 | ||
2919 | \f | |
2920 | /* Various Other Internal Functions. */ | |
2921 | ||
2922 | static bfd_boolean | |
2923 | is_unique_insn_expansion (TransitionRule *r) | |
2924 | { | |
2925 | if (!r->to_instr || r->to_instr->next != NULL) | |
2926 | return FALSE; | |
2927 | if (r->to_instr->typ != INSTR_INSTR) | |
2928 | return FALSE; | |
2929 | return TRUE; | |
2930 | } | |
2931 | ||
2932 | ||
84b08ed9 BW |
2933 | /* Check if there is exactly one relaxation for INSN that converts it to |
2934 | another instruction of equal or larger size. If so, and if TARG is | |
2935 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
2936 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
2937 | instruction, i.e., ignore relaxations that convert to an instruction of | |
2938 | equal size. In some contexts where this function is used, only | |
c138bc38 | 2939 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
2940 | exclude cases like ADDI being "widened" to an ADDMI, which may |
2941 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 2942 | |
84b08ed9 BW |
2943 | bfd_boolean |
2944 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
2945 | { |
2946 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
2947 | TransitionList *l; | |
84b08ed9 | 2948 | TransitionRule *match = 0; |
7fa3d080 | 2949 | |
7fa3d080 BW |
2950 | assert (insn->insn_type == ITYPE_INSN); |
2951 | assert (insn->opcode < table->num_opcodes); | |
2952 | ||
2953 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2954 | { | |
2955 | TransitionRule *rule = l->rule; | |
2956 | ||
2957 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
2958 | && is_unique_insn_expansion (rule) |
2959 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
2960 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 2961 | { |
84b08ed9 BW |
2962 | if (match) |
2963 | return FALSE; | |
2964 | match = rule; | |
7fa3d080 BW |
2965 | } |
2966 | } | |
84b08ed9 BW |
2967 | if (!match) |
2968 | return FALSE; | |
2969 | ||
2970 | if (targ) | |
2971 | xg_build_to_insn (targ, insn, match->to_instr); | |
2972 | return TRUE; | |
7fa3d080 BW |
2973 | } |
2974 | ||
2975 | ||
2976 | /* Return the maximum number of bytes this opcode can expand to. */ | |
2977 | ||
2978 | static int | |
2979 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
2980 | { | |
2981 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
2982 | TransitionList *l; | |
2983 | int max_size = xg_get_single_size (opcode); | |
2984 | ||
2985 | assert (opcode < table->num_opcodes); | |
2986 | ||
2987 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
2988 | { | |
2989 | TransitionRule *rule = l->rule; | |
2990 | BuildInstr *build_list; | |
2991 | int this_size = 0; | |
2992 | ||
2993 | if (!rule) | |
2994 | continue; | |
2995 | build_list = rule->to_instr; | |
2996 | if (is_unique_insn_expansion (rule)) | |
2997 | { | |
2998 | assert (build_list->typ == INSTR_INSTR); | |
2999 | this_size = xg_get_max_insn_widen_size (build_list->opcode); | |
3000 | } | |
3001 | else | |
3002 | for (; build_list != NULL; build_list = build_list->next) | |
3003 | { | |
3004 | switch (build_list->typ) | |
3005 | { | |
3006 | case INSTR_INSTR: | |
3007 | this_size += xg_get_single_size (build_list->opcode); | |
3008 | break; | |
3009 | case INSTR_LITERAL_DEF: | |
3010 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3011 | default: |
3012 | break; | |
3013 | } | |
3014 | } | |
3015 | if (this_size > max_size) | |
3016 | max_size = this_size; | |
3017 | } | |
3018 | return max_size; | |
3019 | } | |
3020 | ||
3021 | ||
3022 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3023 | ||
7fa3d080 BW |
3024 | static int |
3025 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3026 | { |
43cd72b9 | 3027 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3028 | TransitionList *l; |
3029 | int max_size = 0; | |
3030 | ||
3031 | assert (opcode < table->num_opcodes); | |
3032 | ||
3033 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3034 | { | |
3035 | TransitionRule *rule = l->rule; | |
3036 | BuildInstr *build_list; | |
3037 | int this_size = 0; | |
3038 | ||
3039 | if (!rule) | |
3040 | continue; | |
3041 | build_list = rule->to_instr; | |
3042 | if (is_unique_insn_expansion (rule)) | |
3043 | { | |
3044 | assert (build_list->typ == INSTR_INSTR); | |
3045 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); | |
3046 | } | |
3047 | else | |
3048 | for (; build_list != NULL; build_list = build_list->next) | |
3049 | { | |
3050 | switch (build_list->typ) | |
3051 | { | |
3052 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3053 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3054 | this_size += 4; |
3055 | break; | |
3056 | case INSTR_INSTR: | |
3057 | case INSTR_LABEL_DEF: | |
3058 | default: | |
3059 | break; | |
3060 | } | |
3061 | } | |
3062 | if (this_size > max_size) | |
3063 | max_size = this_size; | |
3064 | } | |
3065 | return max_size; | |
3066 | } | |
3067 | ||
3068 | ||
7fa3d080 BW |
3069 | static bfd_boolean |
3070 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3071 | { | |
3072 | int steps_taken = 0; | |
3073 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3074 | TransitionList *l; | |
3075 | ||
3076 | assert (insn->insn_type == ITYPE_INSN); | |
3077 | assert (insn->opcode < table->num_opcodes); | |
3078 | ||
3079 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3080 | { | |
3081 | TransitionRule *rule = l->rule; | |
3082 | ||
3083 | if (xg_instruction_matches_rule (insn, rule)) | |
3084 | { | |
3085 | if (steps_taken == lateral_steps) | |
3086 | return TRUE; | |
3087 | steps_taken++; | |
3088 | } | |
3089 | } | |
3090 | return FALSE; | |
3091 | } | |
3092 | ||
3093 | ||
3094 | static symbolS * | |
3095 | get_special_literal_symbol (void) | |
3096 | { | |
3097 | static symbolS *sym = NULL; | |
3098 | ||
3099 | if (sym == NULL) | |
3100 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3101 | return sym; | |
3102 | } | |
3103 | ||
3104 | ||
3105 | static symbolS * | |
3106 | get_special_label_symbol (void) | |
3107 | { | |
3108 | static symbolS *sym = NULL; | |
3109 | ||
3110 | if (sym == NULL) | |
3111 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3112 | return sym; | |
3113 | } | |
3114 | ||
3115 | ||
3116 | static bfd_boolean | |
3117 | xg_valid_literal_expression (const expressionS *exp) | |
3118 | { | |
3119 | switch (exp->X_op) | |
3120 | { | |
3121 | case O_constant: | |
3122 | case O_symbol: | |
3123 | case O_big: | |
3124 | case O_uminus: | |
3125 | case O_subtract: | |
3126 | case O_pltrel: | |
3127 | return TRUE; | |
3128 | default: | |
3129 | return FALSE; | |
3130 | } | |
3131 | } | |
3132 | ||
3133 | ||
3134 | /* This will check to see if the value can be converted into the | |
3135 | operand type. It will return TRUE if it does not fit. */ | |
3136 | ||
3137 | static bfd_boolean | |
3138 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3139 | { | |
3140 | uint32 valbuf = value; | |
3141 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3142 | return TRUE; | |
3143 | return FALSE; | |
3144 | } | |
3145 | ||
3146 | ||
3147 | /* Assumes: All immeds are constants. Check that all constants fit | |
3148 | into their immeds; return FALSE if not. */ | |
3149 | ||
3150 | static bfd_boolean | |
3151 | xg_immeds_fit (const TInsn *insn) | |
3152 | { | |
3153 | xtensa_isa isa = xtensa_default_isa; | |
3154 | int i; | |
3155 | ||
3156 | int n = insn->ntok; | |
3157 | assert (insn->insn_type == ITYPE_INSN); | |
3158 | for (i = 0; i < n; ++i) | |
3159 | { | |
3160 | const expressionS *expr = &insn->tok[i]; | |
3161 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3162 | continue; | |
3163 | ||
3164 | switch (expr->X_op) | |
3165 | { | |
3166 | case O_register: | |
3167 | case O_constant: | |
3168 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3169 | return FALSE; | |
3170 | break; | |
3171 | ||
3172 | default: | |
3173 | /* The symbol should have a fixup associated with it. */ | |
3174 | assert (FALSE); | |
3175 | break; | |
3176 | } | |
3177 | } | |
3178 | return TRUE; | |
3179 | } | |
3180 | ||
3181 | ||
3182 | /* This should only be called after we have an initial | |
3183 | estimate of the addresses. */ | |
3184 | ||
3185 | static bfd_boolean | |
3186 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3187 | segT pc_seg, | |
3188 | fragS *pc_frag, | |
3189 | offsetT pc_offset, | |
3190 | long stretch) | |
e0001a05 | 3191 | { |
7fa3d080 BW |
3192 | xtensa_isa isa = xtensa_default_isa; |
3193 | symbolS *symbolP; | |
3194 | fragS *sym_frag; | |
3195 | offsetT target, pc; | |
3196 | uint32 new_offset; | |
3197 | int i; | |
3198 | int n = insn->ntok; | |
e0001a05 NC |
3199 | |
3200 | assert (insn->insn_type == ITYPE_INSN); | |
e0001a05 | 3201 | |
7fa3d080 | 3202 | for (i = 0; i < n; ++i) |
e0001a05 | 3203 | { |
7fa3d080 BW |
3204 | const expressionS *expr = &insn->tok[i]; |
3205 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3206 | continue; | |
e0001a05 | 3207 | |
7fa3d080 | 3208 | switch (expr->X_op) |
e0001a05 | 3209 | { |
7fa3d080 BW |
3210 | case O_register: |
3211 | case O_constant: | |
3212 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3213 | return FALSE; | |
3214 | break; | |
e0001a05 | 3215 | |
7fa3d080 BW |
3216 | case O_lo16: |
3217 | case O_hi16: | |
3218 | /* Check for the worst case. */ | |
3219 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3220 | return FALSE; | |
3221 | break; | |
e0001a05 | 3222 | |
7fa3d080 | 3223 | case O_symbol: |
7c834684 | 3224 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3225 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3226 | if (pc_frag == 0 |
3227 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3228 | return FALSE; |
e0001a05 | 3229 | |
7c834684 BW |
3230 | /* If it is a weak symbol, then assume it won't reach. */ |
3231 | if (S_IS_WEAK (expr->X_add_symbol)) | |
7fa3d080 | 3232 | return FALSE; |
e0001a05 | 3233 | |
7c834684 BW |
3234 | if (is_direct_call_opcode (insn->opcode) |
3235 | && ! pc_frag->tc_frag_data.use_longcalls) | |
3236 | { | |
3237 | /* If callee is undefined or in a different segment, be | |
3238 | optimistic and assume it will be in range. */ | |
3239 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
3240 | return TRUE; | |
3241 | } | |
3242 | ||
3243 | /* Only references within a segment can be known to fit in the | |
3244 | operands at assembly time. */ | |
3245 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
7fa3d080 | 3246 | return FALSE; |
e0001a05 | 3247 | |
7fa3d080 BW |
3248 | symbolP = expr->X_add_symbol; |
3249 | sym_frag = symbol_get_frag (symbolP); | |
3250 | target = S_GET_VALUE (symbolP) + expr->X_add_number; | |
3251 | pc = pc_frag->fr_address + pc_offset; | |
e0001a05 | 3252 | |
7fa3d080 BW |
3253 | /* If frag has yet to be reached on this pass, assume it |
3254 | will move by STRETCH just as we did. If this is not so, | |
3255 | it will be because some frag between grows, and that will | |
3256 | force another pass. Beware zero-length frags. There | |
3257 | should be a faster way to do this. */ | |
3258 | ||
3259 | if (stretch != 0 | |
3260 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3261 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3262 | { | |
3263 | target += stretch; | |
3264 | } | |
c138bc38 | 3265 | |
7fa3d080 BW |
3266 | new_offset = target; |
3267 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3268 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3269 | return FALSE; | |
3270 | break; | |
3271 | ||
3272 | default: | |
3273 | /* The symbol should have a fixup associated with it. */ | |
3274 | return FALSE; | |
3275 | } | |
3276 | } | |
3277 | ||
3278 | return TRUE; | |
e0001a05 NC |
3279 | } |
3280 | ||
3281 | ||
43cd72b9 | 3282 | /* Return TRUE on success. */ |
e0001a05 | 3283 | |
7fa3d080 BW |
3284 | static bfd_boolean |
3285 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3286 | { |
3287 | BuildOp *op; | |
3288 | symbolS *sym; | |
3289 | ||
60242db2 | 3290 | tinsn_init (targ); |
7c430684 | 3291 | targ->linenum = insn->linenum; |
e0001a05 NC |
3292 | switch (bi->typ) |
3293 | { | |
3294 | case INSTR_INSTR: | |
3295 | op = bi->ops; | |
3296 | targ->opcode = bi->opcode; | |
3297 | targ->insn_type = ITYPE_INSN; | |
3298 | targ->is_specific_opcode = FALSE; | |
3299 | ||
3300 | for (; op != NULL; op = op->next) | |
3301 | { | |
3302 | int op_num = op->op_num; | |
3303 | int op_data = op->op_data; | |
3304 | ||
3305 | assert (op->op_num < MAX_INSN_ARGS); | |
3306 | ||
3307 | if (targ->ntok <= op_num) | |
3308 | targ->ntok = op_num + 1; | |
3309 | ||
3310 | switch (op->typ) | |
3311 | { | |
3312 | case OP_CONSTANT: | |
3313 | set_expr_const (&targ->tok[op_num], op_data); | |
3314 | break; | |
3315 | case OP_OPERAND: | |
3316 | assert (op_data < insn->ntok); | |
3317 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3318 | break; | |
3319 | case OP_LITERAL: | |
3320 | sym = get_special_literal_symbol (); | |
3321 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3322 | break; | |
3323 | case OP_LABEL: | |
3324 | sym = get_special_label_symbol (); | |
3325 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3326 | break; | |
43cd72b9 BW |
3327 | case OP_OPERAND_HI16U: |
3328 | case OP_OPERAND_LOW16U: | |
3329 | assert (op_data < insn->ntok); | |
3330 | if (expr_is_const (&insn->tok[op_data])) | |
3331 | { | |
3332 | long val; | |
3333 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3334 | val = xg_apply_userdef_op_fn (op->typ, | |
3335 | targ->tok[op_num]. | |
3336 | X_add_number); | |
3337 | targ->tok[op_num].X_add_number = val; | |
3338 | } | |
3339 | else | |
3340 | { | |
3341 | /* For const16 we can create relocations for these. */ | |
3342 | if (targ->opcode == XTENSA_UNDEFINED | |
3343 | || (targ->opcode != xtensa_const16_opcode)) | |
3344 | return FALSE; | |
3345 | assert (op_data < insn->ntok); | |
3346 | /* Need to build a O_lo16 or O_hi16. */ | |
3347 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3348 | if (targ->tok[op_num].X_op == O_symbol) | |
3349 | { | |
3350 | if (op->typ == OP_OPERAND_HI16U) | |
3351 | targ->tok[op_num].X_op = O_hi16; | |
3352 | else if (op->typ == OP_OPERAND_LOW16U) | |
3353 | targ->tok[op_num].X_op = O_lo16; | |
3354 | else | |
3355 | return FALSE; | |
3356 | } | |
3357 | } | |
3358 | break; | |
e0001a05 NC |
3359 | default: |
3360 | /* currently handles: | |
3361 | OP_OPERAND_LOW8 | |
3362 | OP_OPERAND_HI24S | |
3363 | OP_OPERAND_F32MINUS */ | |
3364 | if (xg_has_userdef_op_fn (op->typ)) | |
3365 | { | |
3366 | assert (op_data < insn->ntok); | |
3367 | if (expr_is_const (&insn->tok[op_data])) | |
3368 | { | |
3369 | long val; | |
3370 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3371 | val = xg_apply_userdef_op_fn (op->typ, | |
3372 | targ->tok[op_num]. | |
3373 | X_add_number); | |
3374 | targ->tok[op_num].X_add_number = val; | |
3375 | } | |
3376 | else | |
3377 | return FALSE; /* We cannot use a relocation for this. */ | |
3378 | break; | |
3379 | } | |
3380 | assert (0); | |
3381 | break; | |
3382 | } | |
3383 | } | |
3384 | break; | |
3385 | ||
3386 | case INSTR_LITERAL_DEF: | |
3387 | op = bi->ops; | |
3388 | targ->opcode = XTENSA_UNDEFINED; | |
3389 | targ->insn_type = ITYPE_LITERAL; | |
3390 | targ->is_specific_opcode = FALSE; | |
3391 | for (; op != NULL; op = op->next) | |
3392 | { | |
3393 | int op_num = op->op_num; | |
3394 | int op_data = op->op_data; | |
3395 | assert (op->op_num < MAX_INSN_ARGS); | |
3396 | ||
3397 | if (targ->ntok <= op_num) | |
3398 | targ->ntok = op_num + 1; | |
3399 | ||
3400 | switch (op->typ) | |
3401 | { | |
3402 | case OP_OPERAND: | |
3403 | assert (op_data < insn->ntok); | |
43cd72b9 BW |
3404 | /* We can only pass resolvable literals through. */ |
3405 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3406 | return FALSE; | |
e0001a05 NC |
3407 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3408 | break; | |
3409 | case OP_LITERAL: | |
3410 | case OP_CONSTANT: | |
3411 | case OP_LABEL: | |
3412 | default: | |
3413 | assert (0); | |
3414 | break; | |
3415 | } | |
3416 | } | |
3417 | break; | |
3418 | ||
3419 | case INSTR_LABEL_DEF: | |
3420 | op = bi->ops; | |
3421 | targ->opcode = XTENSA_UNDEFINED; | |
3422 | targ->insn_type = ITYPE_LABEL; | |
3423 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3424 | /* Literal with no ops is a label? */ |
e0001a05 NC |
3425 | assert (op == NULL); |
3426 | break; | |
3427 | ||
3428 | default: | |
3429 | assert (0); | |
3430 | } | |
3431 | ||
3432 | return TRUE; | |
3433 | } | |
3434 | ||
3435 | ||
43cd72b9 | 3436 | /* Return TRUE on success. */ |
e0001a05 | 3437 | |
7fa3d080 BW |
3438 | static bfd_boolean |
3439 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3440 | { |
3441 | for (; bi != NULL; bi = bi->next) | |
3442 | { | |
3443 | TInsn *next_insn = istack_push_space (istack); | |
3444 | ||
3445 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3446 | return FALSE; | |
3447 | } | |
3448 | return TRUE; | |
3449 | } | |
3450 | ||
3451 | ||
43cd72b9 | 3452 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3453 | |
7fa3d080 BW |
3454 | static bfd_boolean |
3455 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3456 | { |
3457 | int stack_size = istack->ninsn; | |
3458 | int steps_taken = 0; | |
43cd72b9 | 3459 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3460 | TransitionList *l; |
3461 | ||
3462 | assert (insn->insn_type == ITYPE_INSN); | |
3463 | assert (insn->opcode < table->num_opcodes); | |
3464 | ||
3465 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3466 | { | |
3467 | TransitionRule *rule = l->rule; | |
3468 | ||
3469 | if (xg_instruction_matches_rule (insn, rule)) | |
3470 | { | |
3471 | if (lateral_steps == steps_taken) | |
3472 | { | |
3473 | int i; | |
3474 | ||
3475 | /* This is it. Expand the rule to the stack. */ | |
3476 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3477 | return FALSE; | |
3478 | ||
3479 | /* Check to see if it fits. */ | |
3480 | for (i = stack_size; i < istack->ninsn; i++) | |
3481 | { | |
3482 | TInsn *insn = &istack->insn[i]; | |
3483 | ||
3484 | if (insn->insn_type == ITYPE_INSN | |
3485 | && !tinsn_has_symbolic_operands (insn) | |
3486 | && !xg_immeds_fit (insn)) | |
3487 | { | |
3488 | istack->ninsn = stack_size; | |
3489 | return FALSE; | |
3490 | } | |
3491 | } | |
3492 | return TRUE; | |
3493 | } | |
3494 | steps_taken++; | |
3495 | } | |
3496 | } | |
3497 | return FALSE; | |
3498 | } | |
3499 | ||
43cd72b9 | 3500 | \f |
43cd72b9 | 3501 | /* Relax the assembly instruction at least "min_steps". |
b81bf389 BW |
3502 | Return the number of steps taken. |
3503 | ||
3504 | For relaxation to correctly terminate, every relaxation chain must | |
3505 | terminate in one of two ways: | |
3506 | ||
3507 | 1. If the chain from one instruction to the next consists entirely of | |
3508 | single instructions, then the chain *must* handle all possible | |
3509 | immediates without failing. It must not ever fail because an | |
3510 | immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation | |
3511 | chain is one example. L32R loads 32 bits, and there cannot be an | |
3512 | immediate larger than 32 bits, so it satisfies this condition. | |
3513 | Single instruction relaxation chains are as defined by | |
3514 | xg_is_single_relaxable_instruction. | |
3515 | ||
3516 | 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., | |
3517 | BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J | |
3518 | ||
3519 | Strictly speaking, in most cases you can violate condition 1 and be OK | |
3520 | -- in particular when the last two instructions have the same single | |
3521 | size. But nevertheless, you should guarantee the above two conditions. | |
3522 | ||
3523 | We could fix this so that single-instruction expansions correctly | |
3524 | terminate when they can't handle the range, but the error messages are | |
3525 | worse, and it actually turns out that in every case but one (18-bit wide | |
3526 | branches), you need a multi-instruction expansion to get the full range | |
3527 | anyway. And because 18-bit branches are handled identically to 15-bit | |
3528 | branches, there isn't any point in changing it. */ | |
e0001a05 | 3529 | |
7fa3d080 BW |
3530 | static int |
3531 | xg_assembly_relax (IStack *istack, | |
3532 | TInsn *insn, | |
3533 | segT pc_seg, | |
3534 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3535 | offsetT pc_offset, /* offset in fragment */ | |
3536 | int min_steps, /* minimum conversion steps */ | |
3537 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3538 | { |
3539 | int steps_taken = 0; | |
3540 | ||
b81bf389 BW |
3541 | /* Some of its immeds don't fit. Try to build a relaxed version. |
3542 | This may go through a couple of stages of single instruction | |
3543 | transformations before we get there. */ | |
e0001a05 NC |
3544 | |
3545 | TInsn single_target; | |
3546 | TInsn current_insn; | |
3547 | int lateral_steps = 0; | |
3548 | int istack_size = istack->ninsn; | |
3549 | ||
3550 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3551 | && steps_taken >= min_steps) | |
3552 | { | |
3553 | istack_push (istack, insn); | |
3554 | return steps_taken; | |
3555 | } | |
43cd72b9 | 3556 | current_insn = *insn; |
e0001a05 | 3557 | |
7c834684 | 3558 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3559 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3560 | { |
21af2bbd | 3561 | steps_taken++; |
e0001a05 NC |
3562 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3563 | stretch)) | |
3564 | { | |
e0001a05 NC |
3565 | if (steps_taken >= min_steps) |
3566 | { | |
3567 | istack_push (istack, &single_target); | |
3568 | return steps_taken; | |
3569 | } | |
3570 | } | |
43cd72b9 | 3571 | current_insn = single_target; |
e0001a05 NC |
3572 | } |
3573 | ||
3574 | /* Now check for a multi-instruction expansion. */ | |
3575 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3576 | { | |
3577 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3578 | stretch)) | |
3579 | { | |
3580 | if (steps_taken >= min_steps) | |
3581 | { | |
3582 | istack_push (istack, ¤t_insn); | |
3583 | return steps_taken; | |
3584 | } | |
3585 | } | |
3586 | steps_taken++; | |
3587 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3588 | { | |
3589 | if (steps_taken >= min_steps) | |
3590 | return steps_taken; | |
3591 | } | |
3592 | lateral_steps++; | |
3593 | istack->ninsn = istack_size; | |
3594 | } | |
3595 | ||
3596 | /* It's not going to work -- use the original. */ | |
3597 | istack_push (istack, insn); | |
3598 | return steps_taken; | |
3599 | } | |
3600 | ||
3601 | ||
3602 | static void | |
7fa3d080 | 3603 | xg_force_frag_space (int size) |
e0001a05 NC |
3604 | { |
3605 | /* This may have the side effect of creating a new fragment for the | |
3606 | space to go into. I just do not like the name of the "frag" | |
3607 | functions. */ | |
3608 | frag_grow (size); | |
3609 | } | |
3610 | ||
3611 | ||
7fa3d080 BW |
3612 | static void |
3613 | xg_finish_frag (char *last_insn, | |
3614 | enum xtensa_relax_statesE frag_state, | |
3615 | enum xtensa_relax_statesE slot0_state, | |
3616 | int max_growth, | |
3617 | bfd_boolean is_insn) | |
e0001a05 NC |
3618 | { |
3619 | /* Finish off this fragment so that it has at LEAST the desired | |
3620 | max_growth. If it doesn't fit in this fragment, close this one | |
3621 | and start a new one. In either case, return a pointer to the | |
3622 | beginning of the growth area. */ | |
3623 | ||
3624 | fragS *old_frag; | |
43cd72b9 | 3625 | |
e0001a05 NC |
3626 | xg_force_frag_space (max_growth); |
3627 | ||
3628 | old_frag = frag_now; | |
3629 | ||
3630 | frag_now->fr_opcode = last_insn; | |
3631 | if (is_insn) | |
3632 | frag_now->tc_frag_data.is_insn = TRUE; | |
3633 | ||
3634 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3635 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3636 | ||
3637 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3638 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3639 | |
3640 | /* Just to make sure that we did not split it up. */ | |
3641 | assert (old_frag->fr_next == frag_now); | |
3642 | } | |
3643 | ||
3644 | ||
7fa3d080 BW |
3645 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3646 | ||
3647 | static bfd_boolean | |
3648 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3649 | { | |
3650 | if (fragP == NULL) | |
3651 | return FALSE; | |
3652 | ||
3653 | for (; fragP; fragP = fragP->fr_next) | |
3654 | { | |
3655 | if (fragP == target) | |
3656 | return TRUE; | |
3657 | if (fragP->fr_fix != 0) | |
3658 | return FALSE; | |
3659 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3660 | return FALSE; | |
3661 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3662 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3663 | return FALSE; | |
3664 | if (fragP->fr_type == rs_space) | |
3665 | return FALSE; | |
3666 | } | |
3667 | return FALSE; | |
3668 | } | |
3669 | ||
3670 | ||
e0001a05 | 3671 | static bfd_boolean |
7fa3d080 | 3672 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3673 | { |
3674 | xtensa_isa isa = xtensa_default_isa; | |
3675 | int i; | |
43cd72b9 | 3676 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3677 | int target_op = -1; |
3678 | symbolS *sym; | |
3679 | fragS *target_frag; | |
3680 | ||
64b607e6 BW |
3681 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3682 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
e0001a05 NC |
3683 | return FALSE; |
3684 | ||
3685 | for (i = 0; i < num_ops; i++) | |
3686 | { | |
43cd72b9 | 3687 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3688 | { |
3689 | target_op = i; | |
3690 | break; | |
3691 | } | |
3692 | } | |
3693 | if (target_op == -1) | |
3694 | return FALSE; | |
3695 | ||
3696 | if (insn->ntok <= target_op) | |
3697 | return FALSE; | |
3698 | ||
3699 | if (insn->tok[target_op].X_op != O_symbol) | |
3700 | return FALSE; | |
3701 | ||
3702 | sym = insn->tok[target_op].X_add_symbol; | |
3703 | if (sym == NULL) | |
3704 | return FALSE; | |
3705 | ||
3706 | if (insn->tok[target_op].X_add_number != 0) | |
3707 | return FALSE; | |
3708 | ||
3709 | target_frag = symbol_get_frag (sym); | |
3710 | if (target_frag == NULL) | |
3711 | return FALSE; | |
3712 | ||
c138bc38 | 3713 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3714 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3715 | return TRUE; | |
3716 | ||
3717 | return FALSE; | |
3718 | } | |
3719 | ||
3720 | ||
3721 | static void | |
7fa3d080 | 3722 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3723 | { |
3724 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3725 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3726 | |
7fa3d080 BW |
3727 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3728 | { | |
3729 | int i = 1; | |
3730 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3731 | && insn->tok[i].X_op == O_symbol) | |
3732 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3733 | return; | |
3734 | } | |
e0001a05 | 3735 | |
7fa3d080 BW |
3736 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3737 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3738 | { |
7fa3d080 BW |
3739 | int i; |
3740 | ||
3741 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3742 | { | |
3743 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3744 | && insn->tok[i].X_op == O_symbol) | |
3745 | { | |
3746 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3747 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3748 | if (S_IS_DEFINED (sym)) | |
3749 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3750 | } | |
3751 | } | |
e0001a05 | 3752 | } |
e0001a05 NC |
3753 | } |
3754 | ||
3755 | ||
43cd72b9 | 3756 | /* Return FALSE if no error. */ |
e0001a05 | 3757 | |
7fa3d080 BW |
3758 | static bfd_boolean |
3759 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3760 | { |
3761 | int num_ops = 0; | |
3762 | BuildOp *b_op; | |
3763 | ||
3764 | switch (instr_spec->typ) | |
3765 | { | |
3766 | case INSTR_INSTR: | |
3767 | new_insn->insn_type = ITYPE_INSN; | |
3768 | new_insn->opcode = instr_spec->opcode; | |
3769 | new_insn->is_specific_opcode = FALSE; | |
7c430684 | 3770 | new_insn->linenum = old_insn->linenum; |
e0001a05 NC |
3771 | break; |
3772 | case INSTR_LITERAL_DEF: | |
3773 | new_insn->insn_type = ITYPE_LITERAL; | |
3774 | new_insn->opcode = XTENSA_UNDEFINED; | |
3775 | new_insn->is_specific_opcode = FALSE; | |
7c430684 | 3776 | new_insn->linenum = old_insn->linenum; |
e0001a05 NC |
3777 | break; |
3778 | case INSTR_LABEL_DEF: | |
3779 | as_bad (_("INSTR_LABEL_DEF not supported yet")); | |
3780 | break; | |
3781 | } | |
3782 | ||
3783 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3784 | { | |
3785 | expressionS *exp; | |
3786 | const expressionS *src_exp; | |
3787 | ||
3788 | num_ops++; | |
3789 | switch (b_op->typ) | |
3790 | { | |
3791 | case OP_CONSTANT: | |
3792 | /* The expression must be the constant. */ | |
3793 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3794 | exp = &new_insn->tok[b_op->op_num]; | |
3795 | set_expr_const (exp, b_op->op_data); | |
3796 | break; | |
3797 | ||
3798 | case OP_OPERAND: | |
3799 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3800 | assert (b_op->op_data < (unsigned) old_insn->ntok); | |
3801 | src_exp = &old_insn->tok[b_op->op_data]; | |
3802 | exp = &new_insn->tok[b_op->op_num]; | |
3803 | copy_expr (exp, src_exp); | |
3804 | break; | |
3805 | ||
3806 | case OP_LITERAL: | |
3807 | case OP_LABEL: | |
3808 | as_bad (_("can't handle generation of literal/labels yet")); | |
3809 | assert (0); | |
3810 | ||
3811 | default: | |
3812 | as_bad (_("can't handle undefined OP TYPE")); | |
3813 | assert (0); | |
3814 | } | |
3815 | } | |
3816 | ||
3817 | new_insn->ntok = num_ops; | |
3818 | return FALSE; | |
3819 | } | |
3820 | ||
3821 | ||
43cd72b9 | 3822 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3823 | |
7fa3d080 BW |
3824 | static bfd_boolean |
3825 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3826 | { |
43cd72b9 | 3827 | TransitionRule *rule; |
e0001a05 | 3828 | BuildInstr *insn_spec; |
43cd72b9 BW |
3829 | |
3830 | if (old_insn->is_specific_opcode || !density_supported) | |
3831 | return FALSE; | |
3832 | ||
3833 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3834 | if (rule == NULL) |
3835 | return FALSE; | |
3836 | ||
3837 | insn_spec = rule->to_instr; | |
3838 | /* There should only be one. */ | |
3839 | assert (insn_spec != NULL); | |
3840 | assert (insn_spec->next == NULL); | |
3841 | if (insn_spec->next != NULL) | |
3842 | return FALSE; | |
3843 | ||
3844 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3845 | ||
3846 | return TRUE; | |
3847 | } | |
3848 | ||
3849 | ||
3850 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3851 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
3852 | tokens into the stack or relax it and place multiple |
3853 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
3854 | |
3855 | static bfd_boolean | |
7fa3d080 | 3856 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
3857 | { |
3858 | int noperands; | |
3859 | TInsn new_insn; | |
7c834684 BW |
3860 | bfd_boolean do_expand; |
3861 | ||
60242db2 | 3862 | tinsn_init (&new_insn); |
e0001a05 | 3863 | |
43cd72b9 BW |
3864 | /* Narrow it if we can. xg_simplify_insn now does all the |
3865 | appropriate checking (e.g., for the density option). */ | |
3866 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
3867 | orig_insn = &new_insn; | |
e0001a05 | 3868 | |
43cd72b9 BW |
3869 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
3870 | orig_insn->opcode); | |
e0001a05 NC |
3871 | if (orig_insn->ntok < noperands) |
3872 | { | |
3873 | as_bad (_("found %d operands for '%s': Expected %d"), | |
3874 | orig_insn->ntok, | |
3875 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3876 | noperands); | |
3877 | return TRUE; | |
3878 | } | |
3879 | if (orig_insn->ntok > noperands) | |
3880 | as_warn (_("found too many (%d) operands for '%s': Expected %d"), | |
3881 | orig_insn->ntok, | |
3882 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3883 | noperands); | |
3884 | ||
43cd72b9 | 3885 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 3886 | are too many, just cut out the extras here. */ |
e0001a05 NC |
3887 | orig_insn->ntok = noperands; |
3888 | ||
e0001a05 NC |
3889 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
3890 | return TRUE; | |
3891 | ||
d12f9798 BW |
3892 | /* Special case for extui opcode which has constraints not handled |
3893 | by the ordinary operand encoding checks. The number of operands | |
3894 | and related syntax issues have already been checked. */ | |
3895 | if (orig_insn->opcode == xtensa_extui_opcode) | |
3896 | { | |
3897 | int shiftimm = orig_insn->tok[2].X_add_number; | |
3898 | int maskimm = orig_insn->tok[3].X_add_number; | |
3899 | if (shiftimm + maskimm > 32) | |
3900 | { | |
3901 | as_bad (_("immediate operands sum to greater than 32")); | |
3902 | return TRUE; | |
3903 | } | |
3904 | } | |
3905 | ||
7c834684 BW |
3906 | /* If the instruction will definitely need to be relaxed, it is better |
3907 | to expand it now for better scheduling. Decide whether to expand | |
3908 | now.... */ | |
3909 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
3910 | ||
3911 | /* Calls should be expanded to longcalls only in the backend relaxation | |
3912 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
3913 | adjacent. */ | |
3914 | if (is_direct_call_opcode (orig_insn->opcode)) | |
3915 | do_expand = FALSE; | |
e0001a05 NC |
3916 | |
3917 | if (tinsn_has_symbolic_operands (orig_insn)) | |
3918 | { | |
7c834684 BW |
3919 | /* The values of symbolic operands are not known yet, so only expand |
3920 | now if an operand is "complex" (e.g., difference of symbols) and | |
3921 | will have to be stored as a literal regardless of the value. */ | |
3922 | if (!tinsn_has_complex_operands (orig_insn)) | |
3923 | do_expand = FALSE; | |
e0001a05 | 3924 | } |
7c834684 BW |
3925 | else if (xg_immeds_fit (orig_insn)) |
3926 | do_expand = FALSE; | |
3927 | ||
3928 | if (do_expand) | |
3929 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 3930 | else |
7c834684 | 3931 | istack_push (istack, orig_insn); |
e0001a05 | 3932 | |
e0001a05 NC |
3933 | return FALSE; |
3934 | } | |
3935 | ||
3936 | ||
7fa3d080 | 3937 | /* Return TRUE if the section flags are marked linkonce |
74869ac7 BW |
3938 | or the name is .gnu.linkonce.*. */ |
3939 | ||
3940 | static int linkonce_len = sizeof (".gnu.linkonce.") - 1; | |
7fa3d080 BW |
3941 | |
3942 | static bfd_boolean | |
3943 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
3944 | { | |
3945 | flagword flags, link_once_flags; | |
3946 | ||
3947 | flags = bfd_get_section_flags (abfd, sec); | |
3948 | link_once_flags = (flags & SEC_LINK_ONCE); | |
3949 | ||
3950 | /* Flags might not be set yet. */ | |
74869ac7 BW |
3951 | if (!link_once_flags |
3952 | && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) | |
3953 | link_once_flags = SEC_LINK_ONCE; | |
7fa3d080 | 3954 | |
7fa3d080 BW |
3955 | return (link_once_flags != 0); |
3956 | } | |
3957 | ||
3958 | ||
3959 | static void | |
3960 | xtensa_add_literal_sym (symbolS *sym) | |
3961 | { | |
3962 | sym_list *l; | |
3963 | ||
3964 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
3965 | l->sym = sym; | |
3966 | l->next = literal_syms; | |
3967 | literal_syms = l; | |
3968 | } | |
3969 | ||
3970 | ||
3971 | static symbolS * | |
3972 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
3973 | { | |
3974 | static int lit_num = 0; | |
3975 | static char name[256]; | |
3976 | symbolS *symbolP; | |
3977 | ||
3978 | sprintf (name, ".L_lit_sym%d", lit_num); | |
3979 | ||
3980 | /* Create a local symbol. If it is in a linkonce section, we have to | |
3981 | be careful to make sure that if it is used in a relocation that the | |
3982 | symbol will be in the output file. */ | |
3983 | if (get_is_linkonce_section (stdoutput, sec)) | |
3984 | { | |
3985 | symbolP = symbol_new (name, sec, 0, frag); | |
3986 | S_CLEAR_EXTERNAL (symbolP); | |
3987 | /* symbolP->local = 1; */ | |
3988 | } | |
3989 | else | |
3990 | symbolP = symbol_new (name, sec, 0, frag); | |
3991 | ||
3992 | xtensa_add_literal_sym (symbolP); | |
3993 | ||
7fa3d080 BW |
3994 | lit_num++; |
3995 | return symbolP; | |
3996 | } | |
3997 | ||
3998 | ||
e0001a05 NC |
3999 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
4000 | ||
7fa3d080 BW |
4001 | static symbolS * |
4002 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
4003 | { |
4004 | emit_state state; | |
4005 | symbolS *lit_sym = NULL; | |
bbdd25a8 BW |
4006 | bfd_reloc_code_real_type reloc; |
4007 | char *p; | |
e0001a05 NC |
4008 | |
4009 | /* size = 4 for L32R. It could easily be larger when we move to | |
4010 | larger constants. Add a parameter later. */ | |
4011 | offsetT litsize = 4; | |
4012 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4013 | expressionS saved_loc; | |
43cd72b9 BW |
4014 | expressionS * emit_val; |
4015 | ||
e0001a05 NC |
4016 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4017 | ||
4018 | assert (insn->insn_type == ITYPE_LITERAL); | |
77cd6497 | 4019 | assert (insn->ntok == 1); /* must be only one token here */ |
e0001a05 NC |
4020 | |
4021 | xtensa_switch_to_literal_fragment (&state); | |
4022 | ||
43cd72b9 BW |
4023 | emit_val = &insn->tok[0]; |
4024 | if (emit_val->X_op == O_big) | |
4025 | { | |
4026 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4027 | if (size > litsize) | |
4028 | { | |
4029 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4030 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4031 | _("invalid immediate")); |
4032 | xtensa_restore_emit_state (&state); | |
4033 | return NULL; | |
4034 | } | |
4035 | } | |
4036 | ||
e0001a05 NC |
4037 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4038 | literals done with this function have a frag to themselves. That's | |
4039 | important for the way text section literals work. */ | |
4040 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4041 | record_alignment (now_seg, litalign); |
e0001a05 | 4042 | |
bbdd25a8 | 4043 | switch (emit_val->X_op) |
43cd72b9 | 4044 | { |
bbdd25a8 BW |
4045 | case O_pltrel: |
4046 | p = frag_more (litsize); | |
43cd72b9 | 4047 | xtensa_set_frag_assembly_state (frag_now); |
bbdd25a8 | 4048 | reloc = map_operator_to_reloc (emit_val->X_op); |
43cd72b9 BW |
4049 | if (emit_val->X_add_symbol) |
4050 | emit_val->X_op = O_symbol; | |
4051 | else | |
4052 | emit_val->X_op = O_constant; | |
4053 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
bbdd25a8 BW |
4054 | litsize, emit_val, 0, reloc); |
4055 | break; | |
4056 | ||
4057 | default: | |
4058 | emit_expr (emit_val, litsize); | |
4059 | break; | |
43cd72b9 | 4060 | } |
e0001a05 NC |
4061 | |
4062 | assert (frag_now->tc_frag_data.literal_frag == NULL); | |
4063 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
4064 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4065 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4066 | |
4067 | /* Go back. */ | |
4068 | xtensa_restore_emit_state (&state); | |
4069 | return lit_sym; | |
4070 | } | |
4071 | ||
4072 | ||
4073 | static void | |
7fa3d080 | 4074 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4075 | { |
4076 | emit_state state; | |
43cd72b9 | 4077 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4078 | takes effect if something is placed here. */ |
4079 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4080 | fragS *lit_saved_frag; | |
4081 | ||
e0001a05 | 4082 | assert (size % 4 == 0); |
e0001a05 NC |
4083 | |
4084 | xtensa_switch_to_literal_fragment (&state); | |
4085 | ||
4086 | /* Force a 4-byte align here. */ | |
4087 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4088 | record_alignment (now_seg, litalign); |
e0001a05 NC |
4089 | |
4090 | xg_force_frag_space (size); | |
4091 | ||
4092 | lit_saved_frag = frag_now; | |
4093 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4094 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
43cd72b9 | 4095 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4096 | |
4097 | /* Go back. */ | |
4098 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4099 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4100 | } |
4101 | ||
4102 | ||
e0001a05 | 4103 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4104 | Return TRUE on success. */ |
e0001a05 | 4105 | |
7fa3d080 BW |
4106 | static bfd_boolean |
4107 | xg_add_opcode_fix (TInsn *tinsn, | |
4108 | int opnum, | |
4109 | xtensa_format fmt, | |
4110 | int slot, | |
4111 | expressionS *expr, | |
4112 | fragS *fragP, | |
4113 | offsetT offset) | |
43cd72b9 BW |
4114 | { |
4115 | xtensa_opcode opcode = tinsn->opcode; | |
4116 | bfd_reloc_code_real_type reloc; | |
4117 | reloc_howto_type *howto; | |
4118 | int fmt_length; | |
e0001a05 NC |
4119 | fixS *the_fix; |
4120 | ||
43cd72b9 BW |
4121 | reloc = BFD_RELOC_NONE; |
4122 | ||
4123 | /* First try the special cases for "alternate" relocs. */ | |
4124 | if (opcode == xtensa_l32r_opcode) | |
4125 | { | |
4126 | if (fragP->tc_frag_data.use_absolute_literals) | |
4127 | reloc = encode_alt_reloc (slot); | |
4128 | } | |
4129 | else if (opcode == xtensa_const16_opcode) | |
4130 | { | |
4131 | if (expr->X_op == O_lo16) | |
4132 | { | |
4133 | reloc = encode_reloc (slot); | |
4134 | expr->X_op = O_symbol; | |
4135 | } | |
4136 | else if (expr->X_op == O_hi16) | |
4137 | { | |
4138 | reloc = encode_alt_reloc (slot); | |
4139 | expr->X_op = O_symbol; | |
4140 | } | |
4141 | } | |
4142 | ||
4143 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4144 | { |
43cd72b9 | 4145 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4146 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4147 | return FALSE; |
4148 | } | |
4149 | ||
43cd72b9 BW |
4150 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4151 | into the symbol table where the generic portions of the assembler | |
4152 | won't know what to do with them. */ | |
4153 | if (expr->X_op == O_lo16 || expr->X_op == O_hi16) | |
4154 | { | |
4155 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4156 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4157 | return FALSE; |
4158 | } | |
4159 | ||
4160 | /* Next try the generic relocs. */ | |
4161 | if (reloc == BFD_RELOC_NONE) | |
4162 | reloc = encode_reloc (slot); | |
4163 | if (reloc == BFD_RELOC_NONE) | |
4164 | { | |
4165 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4166 | return FALSE; | |
4167 | } | |
e0001a05 | 4168 | |
43cd72b9 | 4169 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4170 | if (!howto) |
4171 | { | |
43cd72b9 | 4172 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4173 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4174 | return FALSE; | |
4175 | } | |
4176 | ||
43cd72b9 BW |
4177 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
4178 | the_fix = fix_new_exp (fragP, offset, fmt_length, expr, | |
e0001a05 | 4179 | howto->pc_relative, reloc); |
d9740523 | 4180 | the_fix->fx_no_overflow = 1; |
7fa3d080 BW |
4181 | the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol; |
4182 | the_fix->tc_fix_data.X_add_number = expr->X_add_number; | |
4183 | the_fix->tc_fix_data.slot = slot; | |
c138bc38 | 4184 | |
7fa3d080 BW |
4185 | return TRUE; |
4186 | } | |
4187 | ||
4188 | ||
4189 | static bfd_boolean | |
4190 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4191 | char *buf, |
4192 | fragS *fragP, | |
4193 | offsetT offset, | |
4194 | bfd_boolean build_fix) | |
4195 | { | |
4196 | static xtensa_insnbuf insnbuf = NULL; | |
4197 | bfd_boolean has_symbolic_immed = FALSE; | |
4198 | bfd_boolean ok = TRUE; | |
b2d179be | 4199 | |
7fa3d080 BW |
4200 | if (!insnbuf) |
4201 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4202 | ||
4203 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4204 | if (has_symbolic_immed && build_fix) | |
4205 | { | |
4206 | /* Add a fixup. */ | |
b2d179be BW |
4207 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4208 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4209 | int opnum = get_relaxable_immed (tinsn->opcode); |
4210 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4211 | |
b2d179be | 4212 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4213 | ok = FALSE; |
4214 | } | |
4215 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4216 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4217 | (unsigned char *) buf, 0); | |
7fa3d080 | 4218 | return ok; |
e0001a05 NC |
4219 | } |
4220 | ||
4221 | ||
7fa3d080 BW |
4222 | static void |
4223 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4224 | { |
4225 | symbolS *sym = get_special_literal_symbol (); | |
4226 | int i; | |
4227 | if (lit_sym == 0) | |
4228 | return; | |
4229 | assert (insn->insn_type == ITYPE_INSN); | |
4230 | for (i = 0; i < insn->ntok; i++) | |
4231 | if (insn->tok[i].X_add_symbol == sym) | |
4232 | insn->tok[i].X_add_symbol = lit_sym; | |
4233 | ||
4234 | } | |
4235 | ||
4236 | ||
7fa3d080 BW |
4237 | static void |
4238 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4239 | { |
4240 | symbolS *sym = get_special_label_symbol (); | |
4241 | int i; | |
e0001a05 NC |
4242 | for (i = 0; i < insn->ntok; i++) |
4243 | if (insn->tok[i].X_add_symbol == sym) | |
4244 | insn->tok[i].X_add_symbol = label_sym; | |
4245 | ||
4246 | } | |
4247 | ||
4248 | ||
43cd72b9 | 4249 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4250 | integer register. */ |
4251 | ||
4252 | static bfd_boolean | |
7fa3d080 | 4253 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4254 | { |
4255 | int i; | |
4256 | int num_ops; | |
4257 | xtensa_isa isa = xtensa_default_isa; | |
4258 | ||
43cd72b9 | 4259 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4260 | |
4261 | for (i = 0; i < num_ops; i++) | |
4262 | { | |
43cd72b9 BW |
4263 | char inout; |
4264 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4265 | if ((inout == 'o' || inout == 'm') | |
4266 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4267 | { |
43cd72b9 BW |
4268 | xtensa_regfile opnd_rf = |
4269 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4270 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4271 | { |
4272 | if ((insn->tok[i].X_op == O_register) | |
4273 | && (insn->tok[i].X_add_number == regnum)) | |
4274 | return TRUE; | |
4275 | } | |
4276 | } | |
4277 | } | |
4278 | return FALSE; | |
4279 | } | |
4280 | ||
4281 | ||
4282 | static bfd_boolean | |
7fa3d080 | 4283 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4284 | { |
4285 | xtensa_opcode opcode = tinsn->opcode; | |
4286 | ||
4287 | if (opcode == XTENSA_UNDEFINED) | |
4288 | return FALSE; | |
4289 | ||
4290 | if (opcode == xtensa_call0_opcode | |
4291 | || opcode == xtensa_callx0_opcode | |
4292 | || opcode == xtensa_call4_opcode | |
4293 | || opcode == xtensa_callx4_opcode | |
4294 | || opcode == xtensa_call8_opcode | |
4295 | || opcode == xtensa_callx8_opcode | |
4296 | || opcode == xtensa_call12_opcode | |
4297 | || opcode == xtensa_callx12_opcode | |
4298 | || opcode == xtensa_isync_opcode | |
4299 | || opcode == xtensa_ret_opcode | |
4300 | || opcode == xtensa_ret_n_opcode | |
4301 | || opcode == xtensa_retw_opcode | |
4302 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4303 | || opcode == xtensa_waiti_opcode |
4304 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4305 | return TRUE; |
c138bc38 | 4306 | |
e0001a05 NC |
4307 | return FALSE; |
4308 | } | |
4309 | ||
4310 | ||
4311 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4312 | This allows the debugger to add unaligned labels. | |
4313 | Also, the assembler generates stabs labels that need | |
4314 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4315 | ||
7fa3d080 BW |
4316 | static bfd_boolean |
4317 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4318 | { |
4319 | const char *name = S_GET_NAME (sym); | |
4320 | static size_t fake_size = 0; | |
4321 | ||
4322 | if (name | |
4323 | && name[0] == '.' | |
4324 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4325 | return TRUE; | |
4326 | ||
4327 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4328 | if (fake_size == 0) | |
4329 | fake_size = strlen (FAKE_LABEL_NAME); | |
4330 | ||
43cd72b9 | 4331 | if (name |
e0001a05 NC |
4332 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4333 | && (name[fake_size] == 'F' | |
4334 | || name[fake_size] == 'L' | |
4335 | || (name[fake_size] == 'e' | |
4336 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4337 | return TRUE; | |
4338 | ||
4339 | return FALSE; | |
4340 | } | |
4341 | ||
4342 | ||
7fa3d080 BW |
4343 | static fragS * |
4344 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4345 | { |
4346 | fragS *next_fragP = fragP->fr_next; | |
4347 | ||
c138bc38 | 4348 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4349 | So we have to skip until we find something legit. */ |
4350 | while (next_fragP && next_fragP->fr_fix == 0) | |
4351 | next_fragP = next_fragP->fr_next; | |
4352 | ||
4353 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4354 | return NULL; | |
4355 | ||
4356 | return next_fragP; | |
4357 | } | |
4358 | ||
4359 | ||
43cd72b9 | 4360 | static bfd_boolean |
7fa3d080 | 4361 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4362 | { |
4363 | xtensa_opcode out_opcode; | |
4364 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4365 | ||
4366 | if (next_fragP == NULL) | |
4367 | return FALSE; | |
4368 | ||
4369 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4370 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4371 | { | |
4372 | *opcode = out_opcode; | |
4373 | return TRUE; | |
4374 | } | |
4375 | return FALSE; | |
4376 | } | |
4377 | ||
4378 | ||
4379 | static int | |
7fa3d080 | 4380 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4381 | { |
e0001a05 NC |
4382 | static xtensa_insnbuf insnbuf = NULL; |
4383 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4384 | xtensa_format fmt; |
c138bc38 | 4385 | int fmt_size; |
e0001a05 NC |
4386 | |
4387 | if (!insnbuf) | |
4388 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4389 | ||
43cd72b9 BW |
4390 | if (fragP == NULL) |
4391 | return XTENSA_UNDEFINED; | |
4392 | ||
d77b99c9 BW |
4393 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4394 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4395 | |
4396 | fmt = xtensa_format_decode (isa, insnbuf); | |
4397 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4398 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4399 | fmt_size = xtensa_format_length (isa, fmt); |
4400 | ||
4401 | /* If the next format won't be changing due to relaxation, just | |
4402 | return the length of the first format. */ | |
4403 | if (fragP->fr_opcode != fragP->fr_literal) | |
4404 | return fmt_size; | |
4405 | ||
c138bc38 | 4406 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4407 | multi-slot instruction, we will return the more conservative |
4408 | number. This works because alignment on bigger instructions | |
4409 | is more restrictive than alignment on smaller instructions. | |
4410 | This is more conservative than we would like, but it happens | |
4411 | infrequently. */ | |
4412 | ||
4413 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4414 | return fmt_size; | |
4415 | ||
4416 | /* If we aren't doing one of our own relaxations or it isn't | |
4417 | slot-based, then the insn size won't change. */ | |
4418 | if (fragP->fr_type != rs_machine_dependent) | |
4419 | return fmt_size; | |
4420 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4421 | return fmt_size; | |
4422 | ||
4423 | /* If an instruction is about to grow, return the longer size. */ | |
4424 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
b81bf389 BW |
4425 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 |
4426 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) | |
43cd72b9 | 4427 | return 3; |
c138bc38 | 4428 | |
43cd72b9 BW |
4429 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4430 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4431 | |
43cd72b9 | 4432 | return fmt_size; |
e0001a05 NC |
4433 | } |
4434 | ||
4435 | ||
7fa3d080 BW |
4436 | static int |
4437 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4438 | { |
7fa3d080 BW |
4439 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4440 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4441 | } |
4442 | ||
4443 | ||
03aaa593 BW |
4444 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4445 | required two-byte instructions to be treated as three-byte instructions | |
4446 | for loop instruction alignment. This restriction was removed beginning | |
4447 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4448 | is that the first instruction of the loop must appear at an address that | |
4449 | does not cross a fetch boundary. */ | |
4450 | ||
4451 | static int | |
4452 | get_loop_align_size (int insn_size) | |
4453 | { | |
4454 | if (insn_size == XTENSA_UNDEFINED) | |
4455 | return xtensa_fetch_width; | |
4456 | ||
4457 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4458 | return 3; | |
4459 | ||
4460 | return insn_size; | |
4461 | } | |
4462 | ||
4463 | ||
e0001a05 NC |
4464 | /* If the next legit fragment is an end-of-loop marker, |
4465 | switch its state so it will instantiate a NOP. */ | |
4466 | ||
4467 | static void | |
1d19a770 | 4468 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4469 | { |
4470 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4471 | fragS *new_target = NULL; |
e0001a05 | 4472 | |
7b1cc377 | 4473 | if (align_targets) |
43cd72b9 BW |
4474 | { |
4475 | /* We are guaranteed there will be one of these... */ | |
4476 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4477 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4478 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4479 | next_fragP = next_fragP->fr_next; | |
4480 | ||
4481 | assert (next_fragP->fr_type == rs_machine_dependent | |
4482 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4483 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4484 | ||
4485 | /* ...and one of these. */ | |
4486 | new_target = next_fragP->fr_next; | |
4487 | while (!(new_target->fr_type == rs_machine_dependent | |
4488 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4489 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4490 | new_target = new_target->fr_next; | |
4491 | ||
4492 | assert (new_target->fr_type == rs_machine_dependent | |
4493 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4494 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4495 | } | |
43cd72b9 | 4496 | |
1d19a770 | 4497 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4498 | { |
1d19a770 BW |
4499 | if (next_fragP->fr_type == rs_machine_dependent |
4500 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4501 | { |
1d19a770 BW |
4502 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4503 | return; | |
e0001a05 | 4504 | } |
1d19a770 BW |
4505 | |
4506 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4507 | } |
4508 | } | |
4509 | ||
4510 | ||
4511 | static bfd_boolean | |
7fa3d080 | 4512 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4513 | { |
43cd72b9 | 4514 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4515 | so we have to skip until we find something legit. */ |
4516 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4517 | { | |
4518 | if (fragP->tc_frag_data.is_branch_target) | |
4519 | return TRUE; | |
4520 | if (fragP->fr_fix != 0) | |
4521 | break; | |
4522 | } | |
4523 | return FALSE; | |
4524 | } | |
4525 | ||
4526 | ||
4527 | static bfd_boolean | |
7fa3d080 | 4528 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4529 | { |
c138bc38 | 4530 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4531 | So we have to skip until we find something legit. */ |
4532 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4533 | { | |
4534 | if (fragP->tc_frag_data.is_loop_target) | |
4535 | return TRUE; | |
4536 | if (fragP->fr_fix != 0) | |
4537 | break; | |
4538 | } | |
4539 | return FALSE; | |
4540 | } | |
4541 | ||
4542 | ||
4543 | static addressT | |
7fa3d080 | 4544 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4545 | { |
4546 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4547 | xtensa_opcode next_opcode; |
e0001a05 | 4548 | |
43cd72b9 | 4549 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4550 | return 0; |
4551 | ||
43cd72b9 BW |
4552 | /* Sometimes an empty will end up here due to storage allocation issues, |
4553 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4554 | while (next_fragp->fr_fix == 0) |
4555 | next_fragp = next_fragp->fr_next; | |
4556 | ||
4557 | if (next_fragp->fr_type != rs_machine_dependent) | |
4558 | return 0; | |
4559 | ||
4560 | /* There is some implicit knowledge encoded in here. | |
4561 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4562 | been relaxed. Note that we can assume that the LOOP |
4563 | instruction is in slot 0 because loops aren't bundleable. */ | |
4564 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
e0001a05 NC |
4565 | return get_expanded_loop_offset (next_opcode); |
4566 | ||
4567 | return 0; | |
4568 | } | |
4569 | ||
4570 | ||
4571 | /* Mark a location where we can later insert literal frags. Update | |
4572 | the section's literal_pool_loc, so subsequent literals can be | |
4573 | placed nearest to their use. */ | |
4574 | ||
4575 | static void | |
7fa3d080 | 4576 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4577 | { |
4578 | /* Any labels pointing to the current location need | |
4579 | to be adjusted to after the literal pool. */ | |
4580 | emit_state s; | |
e0001a05 | 4581 | fragS *pool_location; |
e0001a05 | 4582 | |
1f2a7e38 | 4583 | if (use_literal_section) |
43cd72b9 BW |
4584 | return; |
4585 | ||
dd49a749 BW |
4586 | /* We stash info in these frags so we can later move the literal's |
4587 | fixes into this frchain's fix list. */ | |
e0001a05 | 4588 | pool_location = frag_now; |
dd49a749 | 4589 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
c48aaca0 | 4590 | frag_now->tc_frag_data.literal_frag = frag_now; |
dd49a749 | 4591 | frag_variant (rs_machine_dependent, 0, 0, |
e0001a05 | 4592 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4593 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4594 | frag_now->tc_frag_data.lit_seg = now_seg; |
4595 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4596 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4597 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4598 | |
4599 | /* Now put a frag into the literal pool that points to this location. */ | |
4600 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4601 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4602 | frag_align (2, 0, 0); | |
4603 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4604 | |
4605 | /* Close whatever frag is there. */ | |
4606 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4607 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4608 | frag_now->tc_frag_data.literal_frag = pool_location; |
4609 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4610 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4611 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4612 | } |
4613 | ||
4614 | ||
43cd72b9 BW |
4615 | /* Build a nop of the correct size into tinsn. */ |
4616 | ||
4617 | static void | |
7fa3d080 | 4618 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4619 | { |
4620 | tinsn_init (tinsn); | |
4621 | switch (size) | |
4622 | { | |
4623 | case 2: | |
4624 | tinsn->opcode = xtensa_nop_n_opcode; | |
4625 | tinsn->ntok = 0; | |
4626 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4627 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4628 | break; | |
4629 | ||
4630 | case 3: | |
4631 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4632 | { | |
4633 | tinsn->opcode = xtensa_or_opcode; | |
4634 | set_expr_const (&tinsn->tok[0], 1); | |
4635 | set_expr_const (&tinsn->tok[1], 1); | |
4636 | set_expr_const (&tinsn->tok[2], 1); | |
4637 | tinsn->ntok = 3; | |
4638 | } | |
4639 | else | |
4640 | tinsn->opcode = xtensa_nop_opcode; | |
4641 | ||
4642 | assert (tinsn->opcode != XTENSA_UNDEFINED); | |
4643 | } | |
4644 | } | |
4645 | ||
4646 | ||
e0001a05 NC |
4647 | /* Assemble a NOP of the requested size in the buffer. User must have |
4648 | allocated "buf" with at least "size" bytes. */ | |
4649 | ||
7fa3d080 | 4650 | static void |
d77b99c9 | 4651 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4652 | { |
4653 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4654 | TInsn tinsn; |
e0001a05 | 4655 | |
43cd72b9 | 4656 | build_nop (&tinsn, size); |
e0001a05 | 4657 | |
43cd72b9 BW |
4658 | if (!insnbuf) |
4659 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4660 | |
43cd72b9 | 4661 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4662 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4663 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4664 | } |
4665 | ||
4666 | ||
4667 | /* Return the number of bytes for the offset of the expanded loop | |
4668 | instruction. This should be incorporated into the relaxation | |
4669 | specification but is hard-coded here. This is used to auto-align | |
4670 | the loop instruction. It is invalid to call this function if the | |
4671 | configuration does not have loops or if the opcode is not a loop | |
4672 | opcode. */ | |
4673 | ||
4674 | static addressT | |
7fa3d080 | 4675 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4676 | { |
4677 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4678 | This MUST correspond directly to the specification of the loop | |
4679 | expansion. It will be validated on fragment conversion. */ | |
43cd72b9 | 4680 | assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4681 | if (opcode == xtensa_loop_opcode) |
4682 | return 0; | |
4683 | if (opcode == xtensa_loopnez_opcode) | |
4684 | return 3; | |
4685 | if (opcode == xtensa_loopgtz_opcode) | |
4686 | return 6; | |
4687 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4688 | return 0; | |
4689 | } | |
4690 | ||
4691 | ||
7fa3d080 BW |
4692 | static fragS * |
4693 | get_literal_pool_location (segT seg) | |
e0001a05 NC |
4694 | { |
4695 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; | |
4696 | } | |
4697 | ||
4698 | ||
4699 | static void | |
7fa3d080 | 4700 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4701 | { |
4702 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4703 | } | |
4704 | ||
43cd72b9 BW |
4705 | |
4706 | /* Set frag assembly state should be called when a new frag is | |
4707 | opened and after a frag has been closed. */ | |
4708 | ||
7fa3d080 BW |
4709 | static void |
4710 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4711 | { |
4712 | if (!density_supported) | |
4713 | fragP->tc_frag_data.is_no_density = TRUE; | |
4714 | ||
4715 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4716 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4717 | "use_schedule" here. */ |
4718 | if (!directive_state[directive_transform]) | |
4719 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4720 | if (directive_state[directive_longcalls]) |
4721 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4722 | fragP->tc_frag_data.use_absolute_literals = |
4723 | directive_state[directive_absolute_literals]; | |
4724 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4725 | } | |
4726 | ||
4727 | ||
7fa3d080 BW |
4728 | static bfd_boolean |
4729 | relaxable_section (asection *sec) | |
43cd72b9 | 4730 | { |
11ac2671 BW |
4731 | return ((sec->flags & SEC_DEBUGGING) == 0 |
4732 | && strcmp (sec->name, ".eh_frame") != 0); | |
43cd72b9 BW |
4733 | } |
4734 | ||
4735 | ||
99ded152 BW |
4736 | static void |
4737 | xtensa_mark_frags_for_org (void) | |
4738 | { | |
4739 | segT *seclist; | |
4740 | ||
4741 | /* Walk over each fragment of all of the current segments. If we find | |
4742 | a .org frag in any of the segments, mark all frags prior to it as | |
4743 | "no transform", which will prevent linker optimizations from messing | |
4744 | up the .org distance. This should be done after | |
4745 | xtensa_find_unmarked_state_frags, because we don't want to worry here | |
4746 | about that function trashing the data we save here. */ | |
4747 | ||
4748 | for (seclist = &stdoutput->sections; | |
4749 | seclist && *seclist; | |
4750 | seclist = &(*seclist)->next) | |
4751 | { | |
4752 | segT sec = *seclist; | |
4753 | segment_info_type *seginfo; | |
4754 | fragS *fragP; | |
4755 | flagword flags; | |
4756 | flags = bfd_get_section_flags (stdoutput, sec); | |
4757 | if (flags & SEC_DEBUGGING) | |
4758 | continue; | |
4759 | if (!(flags & SEC_ALLOC)) | |
4760 | continue; | |
4761 | ||
4762 | seginfo = seg_info (sec); | |
4763 | if (seginfo && seginfo->frchainP) | |
4764 | { | |
4765 | fragS *last_fragP = seginfo->frchainP->frch_root; | |
4766 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4767 | fragP = fragP->fr_next) | |
4768 | { | |
4769 | /* cvt_frag_to_fill has changed the fr_type of org frags to | |
4770 | rs_fill, so use the value as cached in rs_subtype here. */ | |
4771 | if (fragP->fr_subtype == RELAX_ORG) | |
4772 | { | |
4773 | while (last_fragP != fragP->fr_next) | |
4774 | { | |
4775 | last_fragP->tc_frag_data.is_no_transform = TRUE; | |
4776 | last_fragP = last_fragP->fr_next; | |
4777 | } | |
4778 | } | |
4779 | } | |
4780 | } | |
4781 | } | |
4782 | } | |
4783 | ||
4784 | ||
43cd72b9 | 4785 | static void |
7fa3d080 | 4786 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
4787 | { |
4788 | segT *seclist; | |
4789 | ||
4790 | /* Walk over each fragment of all of the current segments. For each | |
4791 | unmarked fragment, mark it with the same info as the previous | |
4792 | fragment. */ | |
4793 | for (seclist = &stdoutput->sections; | |
4794 | seclist && *seclist; | |
4795 | seclist = &(*seclist)->next) | |
4796 | { | |
4797 | segT sec = *seclist; | |
4798 | segment_info_type *seginfo; | |
4799 | fragS *fragP; | |
4800 | flagword flags; | |
4801 | flags = bfd_get_section_flags (stdoutput, sec); | |
4802 | if (flags & SEC_DEBUGGING) | |
4803 | continue; | |
4804 | if (!(flags & SEC_ALLOC)) | |
4805 | continue; | |
4806 | ||
4807 | seginfo = seg_info (sec); | |
4808 | if (seginfo && seginfo->frchainP) | |
4809 | { | |
4810 | fragS *last_fragP = 0; | |
4811 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4812 | fragP = fragP->fr_next) | |
4813 | { | |
4814 | if (fragP->fr_fix != 0 | |
4815 | && !fragP->tc_frag_data.is_assembly_state_set) | |
4816 | { | |
4817 | if (last_fragP == 0) | |
4818 | { | |
4819 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
4820 | _("assembly state not set for first frag in section %s"), | |
4821 | sec->name); | |
4822 | } | |
4823 | else | |
4824 | { | |
4825 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4826 | fragP->tc_frag_data.is_no_density = | |
4827 | last_fragP->tc_frag_data.is_no_density; | |
4828 | fragP->tc_frag_data.is_no_transform = | |
4829 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
4830 | fragP->tc_frag_data.use_longcalls = |
4831 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
4832 | fragP->tc_frag_data.use_absolute_literals = |
4833 | last_fragP->tc_frag_data.use_absolute_literals; | |
4834 | } | |
4835 | } | |
4836 | if (fragP->tc_frag_data.is_assembly_state_set) | |
4837 | last_fragP = fragP; | |
4838 | } | |
4839 | } | |
4840 | } | |
4841 | } | |
4842 | ||
4843 | ||
4844 | static void | |
7fa3d080 BW |
4845 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
4846 | asection *sec, | |
4847 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4848 | { |
4849 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4850 | segment_info_type *seginfo = seg_info (sec); | |
4851 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 4852 | |
43cd72b9 | 4853 | if (flags & SEC_CODE) |
c138bc38 | 4854 | { |
43cd72b9 BW |
4855 | xtensa_isa isa = xtensa_default_isa; |
4856 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
4857 | while (frag != NULL) | |
4858 | { | |
4859 | if (frag->tc_frag_data.is_branch_target) | |
4860 | { | |
4861 | int op_size; | |
664df4e4 | 4862 | addressT branch_align, frag_addr; |
43cd72b9 BW |
4863 | xtensa_format fmt; |
4864 | ||
d77b99c9 BW |
4865 | xtensa_insnbuf_from_chars |
4866 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4867 | fmt = xtensa_format_decode (isa, insnbuf); |
4868 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
4869 | branch_align = 1 << branch_align_power (sec); |
4870 | frag_addr = frag->fr_address % branch_align; | |
4871 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
4872 | as_warn_where (frag->fr_file, frag->fr_line, |
4873 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 4874 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4875 | } |
4876 | frag = frag->fr_next; | |
4877 | } | |
4878 | xtensa_insnbuf_free (isa, insnbuf); | |
4879 | } | |
4880 | } | |
4881 | ||
4882 | ||
4883 | static void | |
7fa3d080 BW |
4884 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
4885 | asection *sec, | |
4886 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4887 | { |
4888 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4889 | segment_info_type *seginfo = seg_info (sec); | |
4890 | fragS *frag = seginfo->frchainP->frch_root; | |
4891 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 4892 | |
43cd72b9 | 4893 | if (flags & SEC_CODE) |
c138bc38 | 4894 | { |
43cd72b9 BW |
4895 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
4896 | while (frag != NULL) | |
4897 | { | |
4898 | if (frag->tc_frag_data.is_first_loop_insn) | |
4899 | { | |
4900 | int op_size; | |
d77b99c9 | 4901 | addressT frag_addr; |
43cd72b9 BW |
4902 | xtensa_format fmt; |
4903 | ||
d77b99c9 BW |
4904 | xtensa_insnbuf_from_chars |
4905 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4906 | fmt = xtensa_format_decode (isa, insnbuf); |
4907 | op_size = xtensa_format_length (isa, fmt); | |
4908 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
4909 | ||
d77b99c9 | 4910 | if (frag_addr + op_size > xtensa_fetch_width) |
43cd72b9 BW |
4911 | as_warn_where (frag->fr_file, frag->fr_line, |
4912 | _("unaligned loop: %d bytes at 0x%lx"), | |
dd49a749 | 4913 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4914 | } |
4915 | frag = frag->fr_next; | |
4916 | } | |
4917 | xtensa_insnbuf_free (isa, insnbuf); | |
4918 | } | |
4919 | } | |
4920 | ||
4921 | ||
30f725a1 BW |
4922 | static int |
4923 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
4924 | { |
4925 | xtensa_isa isa = xtensa_default_isa; | |
4926 | static xtensa_insnbuf insnbuf = NULL; | |
4927 | static xtensa_insnbuf slotbuf = NULL; | |
4928 | xtensa_format fmt; | |
4929 | int slot; | |
4930 | bfd_boolean alt_reloc; | |
4931 | xtensa_opcode opcode; | |
4932 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
4933 | ||
4934 | (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc); | |
4935 | if (alt_reloc) | |
4936 | as_fatal (_("unexpected fix")); | |
4937 | ||
4938 | if (!insnbuf) | |
4939 | { | |
4940 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4941 | slotbuf = xtensa_insnbuf_alloc (isa); | |
4942 | } | |
4943 | ||
d77b99c9 | 4944 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
4945 | fmt = xtensa_format_decode (isa, insnbuf); |
4946 | if (fmt == XTENSA_UNDEFINED) | |
4947 | as_fatal (_("undecodable fix")); | |
4948 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
4949 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
4950 | if (opcode == XTENSA_UNDEFINED) | |
4951 | as_fatal (_("undecodable fix")); | |
4952 | ||
4953 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
4954 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 4955 | of a CONST16 operand. */ |
43cd72b9 | 4956 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 4957 | return 0; |
43cd72b9 BW |
4958 | |
4959 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
4960 | get_relaxable_immed (opcode), val, | |
4961 | fixP->fx_file, fixP->fx_line); | |
4962 | ||
4963 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 4964 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
4965 | |
4966 | return 1; | |
43cd72b9 BW |
4967 | } |
4968 | ||
e0001a05 NC |
4969 | \f |
4970 | /* External Functions and Other GAS Hooks. */ | |
4971 | ||
4972 | const char * | |
7fa3d080 | 4973 | xtensa_target_format (void) |
e0001a05 NC |
4974 | { |
4975 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
4976 | } | |
4977 | ||
4978 | ||
4979 | void | |
7fa3d080 | 4980 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
4981 | { |
4982 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
4983 | } | |
4984 | ||
4985 | ||
4986 | void | |
7fa3d080 | 4987 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
4988 | { |
4989 | if (target_big_endian) | |
4990 | number_to_chars_bigendian (buf, val, n); | |
4991 | else | |
4992 | number_to_chars_littleendian (buf, val, n); | |
4993 | } | |
4994 | ||
4995 | ||
4996 | /* This function is called once, at assembler startup time. It should | |
4997 | set up all the tables, etc. that the MD part of the assembler will | |
4998 | need. */ | |
4999 | ||
5000 | void | |
7fa3d080 | 5001 | md_begin (void) |
e0001a05 NC |
5002 | { |
5003 | segT current_section = now_seg; | |
5004 | int current_subsec = now_subseg; | |
5005 | xtensa_isa isa; | |
5006 | ||
43cd72b9 | 5007 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 5008 | isa = xtensa_default_isa; |
e0001a05 | 5009 | |
43cd72b9 BW |
5010 | linkrelax = 1; |
5011 | ||
74869ac7 | 5012 | /* Set up the literal sections. */ |
e0001a05 | 5013 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
e0001a05 NC |
5014 | |
5015 | subseg_set (current_section, current_subsec); | |
5016 | ||
43cd72b9 BW |
5017 | xg_init_vinsn (&cur_vinsn); |
5018 | ||
e0001a05 NC |
5019 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); |
5020 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
5021 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
5022 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
5023 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
5024 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
5025 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
5026 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
5027 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
5028 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 5029 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 5030 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
d12f9798 | 5031 | xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); |
43cd72b9 BW |
5032 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
5033 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 5034 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
e0001a05 | 5035 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 5036 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
5037 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
5038 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
5039 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 5040 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
5041 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
5042 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
5043 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
5044 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
5045 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
5046 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 5047 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 5048 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 BW |
5049 | |
5050 | init_op_placement_info_table (); | |
5051 | ||
5052 | /* Set up the assembly state. */ | |
5053 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5054 | xtensa_set_frag_assembly_state (frag_now); | |
5055 | } | |
5056 | ||
5057 | ||
5058 | /* TC_INIT_FIX_DATA hook */ | |
5059 | ||
5060 | void | |
7fa3d080 | 5061 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5062 | { |
5063 | x->tc_fix_data.slot = 0; | |
5064 | x->tc_fix_data.X_add_symbol = NULL; | |
5065 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5066 | } |
5067 | ||
5068 | ||
5069 | /* tc_frob_label hook */ | |
5070 | ||
5071 | void | |
7fa3d080 | 5072 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5073 | { |
3ea38ac2 BW |
5074 | float freq; |
5075 | ||
5076 | if (cur_vinsn.inside_bundle) | |
5077 | { | |
5078 | as_bad (_("labels are not valid inside bundles")); | |
5079 | return; | |
5080 | } | |
5081 | ||
5082 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5083 | |
43cd72b9 BW |
5084 | /* Since the label was already attached to a frag associated with the |
5085 | previous basic block, it now needs to be reset to the current frag. */ | |
5086 | symbol_set_frag (sym, frag_now); | |
5087 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5088 | ||
82e7541d BW |
5089 | if (generating_literals) |
5090 | xtensa_add_literal_sym (sym); | |
5091 | else | |
5092 | xtensa_add_insn_label (sym); | |
5093 | ||
7b1cc377 BW |
5094 | if (symbol_get_tc (sym)->is_loop_target) |
5095 | { | |
5096 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5097 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5098 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5099 | ||
5100 | xtensa_set_frag_assembly_state (frag_now); | |
5101 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5102 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5103 | ||
5104 | xtensa_set_frag_assembly_state (frag_now); | |
c3ea6048 | 5105 | xtensa_move_labels (frag_now, 0); |
07a53e5c | 5106 | } |
e0001a05 NC |
5107 | |
5108 | /* No target aligning in the absolute section. */ | |
61846f28 | 5109 | if (now_seg != absolute_section |
43cd72b9 | 5110 | && do_align_targets () |
61846f28 | 5111 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5112 | && !generating_literals) |
5113 | { | |
43cd72b9 BW |
5114 | xtensa_set_frag_assembly_state (frag_now); |
5115 | ||
43cd72b9 | 5116 | frag_var (rs_machine_dependent, |
7b1cc377 | 5117 | 0, (int) freq, |
e0001a05 NC |
5118 | RELAX_DESIRE_ALIGN_IF_TARGET, |
5119 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5120 | xtensa_set_frag_assembly_state (frag_now); |
c3ea6048 | 5121 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
5122 | } |
5123 | ||
5124 | /* We need to mark the following properties even if we aren't aligning. */ | |
5125 | ||
5126 | /* If the label is already known to be a branch target, i.e., a | |
5127 | forward branch, mark the frag accordingly. Backward branches | |
5128 | are handled by xg_add_branch_and_loop_targets. */ | |
5129 | if (symbol_get_tc (sym)->is_branch_target) | |
5130 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5131 | ||
5132 | /* Loops only go forward, so they can be identified here. */ | |
5133 | if (symbol_get_tc (sym)->is_loop_target) | |
5134 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5135 | |
5136 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5137 | } |
5138 | ||
5139 | ||
5140 | /* tc_unrecognized_line hook */ | |
5141 | ||
5142 | int | |
7fa3d080 | 5143 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5144 | { |
5145 | switch (ch) | |
5146 | { | |
5147 | case '{' : | |
5148 | if (cur_vinsn.inside_bundle == 0) | |
5149 | { | |
5150 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5151 | when using --gstabs. Temporarily disable debug info. */ | |
5152 | generate_lineno_debug (); | |
5153 | if (debug_type == DEBUG_STABS) | |
5154 | { | |
5155 | xt_saved_debug_type = debug_type; | |
5156 | debug_type = DEBUG_NONE; | |
5157 | } | |
82e7541d | 5158 | |
43cd72b9 BW |
5159 | cur_vinsn.inside_bundle = 1; |
5160 | } | |
5161 | else | |
5162 | { | |
5163 | as_bad (_("extra opening brace")); | |
5164 | return 0; | |
5165 | } | |
5166 | break; | |
82e7541d | 5167 | |
43cd72b9 BW |
5168 | case '}' : |
5169 | if (cur_vinsn.inside_bundle) | |
5170 | finish_vinsn (&cur_vinsn); | |
5171 | else | |
5172 | { | |
5173 | as_bad (_("extra closing brace")); | |
5174 | return 0; | |
5175 | } | |
5176 | break; | |
5177 | default: | |
5178 | as_bad (_("syntax error")); | |
5179 | return 0; | |
e0001a05 | 5180 | } |
43cd72b9 | 5181 | return 1; |
e0001a05 NC |
5182 | } |
5183 | ||
5184 | ||
5185 | /* md_flush_pending_output hook */ | |
5186 | ||
5187 | void | |
7fa3d080 | 5188 | xtensa_flush_pending_output (void) |
e0001a05 | 5189 | { |
a3582eee BW |
5190 | /* This line fixes a bug where automatically generated gstabs info |
5191 | separates a function label from its entry instruction, ending up | |
5192 | with the literal position between the function label and the entry | |
5193 | instruction and crashing code. It only happens with --gstabs and | |
5194 | --text-section-literals, and when several other obscure relaxation | |
5195 | conditions are met. */ | |
5196 | if (outputting_stabs_line_debug) | |
5197 | return; | |
5198 | ||
43cd72b9 BW |
5199 | if (cur_vinsn.inside_bundle) |
5200 | as_bad (_("missing closing brace")); | |
5201 | ||
e0001a05 NC |
5202 | /* If there is a non-zero instruction fragment, close it. */ |
5203 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5204 | { | |
5205 | frag_wane (frag_now); | |
5206 | frag_new (0); | |
43cd72b9 | 5207 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5208 | } |
5209 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5210 | |
5211 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5212 | } |
5213 | ||
5214 | ||
43cd72b9 BW |
5215 | /* We had an error while parsing an instruction. The string might look |
5216 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5217 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5218 | and the num_slots field will grow past the end of the array of slots, | |
5219 | and bad things happen. */ | |
5220 | ||
5221 | static void | |
7fa3d080 | 5222 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5223 | { |
5224 | if (cur_vinsn.inside_bundle) | |
5225 | { | |
5226 | if (*input_line_pointer == '}' | |
5227 | || *(input_line_pointer - 1) == '}' | |
5228 | || *(input_line_pointer - 2) == '}') | |
5229 | xg_clear_vinsn (&cur_vinsn); | |
5230 | } | |
5231 | } | |
5232 | ||
5233 | ||
e0001a05 | 5234 | void |
7fa3d080 | 5235 | md_assemble (char *str) |
e0001a05 NC |
5236 | { |
5237 | xtensa_isa isa = xtensa_default_isa; | |
7c430684 | 5238 | char *opname, *file_name; |
e0001a05 NC |
5239 | unsigned opnamelen; |
5240 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5241 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5242 | int num_args; |
e0001a05 | 5243 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5244 | |
e0001a05 NC |
5245 | tinsn_init (&orig_insn); |
5246 | ||
5247 | /* Split off the opcode. */ | |
5248 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
5249 | opname = xmalloc (opnamelen + 1); | |
5250 | memcpy (opname, str, opnamelen); | |
5251 | opname[opnamelen] = '\0'; | |
5252 | ||
5253 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5254 | if (num_args == -1) | |
5255 | { | |
5256 | as_bad (_("syntax error")); | |
5257 | return; | |
5258 | } | |
5259 | ||
5260 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5261 | return; | |
5262 | ||
5263 | /* Check for an underbar prefix. */ | |
5264 | if (*opname == '_') | |
5265 | { | |
5266 | has_underbar = TRUE; | |
5267 | opname += 1; | |
5268 | } | |
5269 | ||
5270 | orig_insn.insn_type = ITYPE_INSN; | |
5271 | orig_insn.ntok = 0; | |
43cd72b9 | 5272 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 NC |
5273 | |
5274 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); | |
5275 | if (orig_insn.opcode == XTENSA_UNDEFINED) | |
5276 | { | |
43cd72b9 BW |
5277 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5278 | if (fmt == XTENSA_UNDEFINED) | |
5279 | { | |
5280 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5281 | error_reset_cur_vinsn (); | |
5282 | return; | |
5283 | } | |
5284 | if (!cur_vinsn.inside_bundle) | |
5285 | { | |
5286 | as_bad (_("format names only valid inside bundles")); | |
5287 | error_reset_cur_vinsn (); | |
5288 | return; | |
5289 | } | |
5290 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5291 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5292 | opname); | |
5293 | cur_vinsn.format = fmt; | |
5294 | free (has_underbar ? opname - 1 : opname); | |
5295 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5296 | return; |
5297 | } | |
5298 | ||
e0001a05 NC |
5299 | /* Parse the arguments. */ |
5300 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5301 | { | |
5302 | as_bad (_("syntax error")); | |
43cd72b9 | 5303 | error_reset_cur_vinsn (); |
e0001a05 NC |
5304 | return; |
5305 | } | |
5306 | ||
5307 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5308 | free (has_underbar ? opname - 1 : opname); | |
5309 | opname = 0; | |
5310 | while (num_args-- > 0) | |
5311 | free (arg_strings[num_args]); | |
5312 | ||
43cd72b9 BW |
5313 | /* Get expressions for invisible operands. */ |
5314 | if (get_invisible_operands (&orig_insn)) | |
5315 | { | |
5316 | error_reset_cur_vinsn (); | |
5317 | return; | |
5318 | } | |
5319 | ||
e0001a05 NC |
5320 | /* Check for the right number and type of arguments. */ |
5321 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5322 | { |
43cd72b9 BW |
5323 | error_reset_cur_vinsn (); |
5324 | return; | |
e0001a05 NC |
5325 | } |
5326 | ||
7c430684 BW |
5327 | /* A FLIX bundle may be spread across multiple input lines. We want to |
5328 | report the first such line in the debug information. Record the line | |
5329 | number for each TInsn (assume the file name doesn't change), so the | |
5330 | first line can be found later. */ | |
5331 | as_where (&file_name, &orig_insn.linenum); | |
c138bc38 | 5332 | |
43cd72b9 BW |
5333 | xg_add_branch_and_loop_targets (&orig_insn); |
5334 | ||
431ad2d0 BW |
5335 | /* Check that immediate value for ENTRY is >= 16. */ |
5336 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5337 | { |
431ad2d0 BW |
5338 | expressionS *exp = &orig_insn.tok[2]; |
5339 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5340 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5341 | } |
5342 | ||
e0001a05 | 5343 | /* Finish it off: |
43cd72b9 BW |
5344 | assemble_tokens (opcode, tok, ntok); |
5345 | expand the tokens from the orig_insn into the | |
5346 | stack of instructions that will not expand | |
e0001a05 | 5347 | unless required at relaxation time. */ |
e0001a05 | 5348 | |
43cd72b9 BW |
5349 | if (!cur_vinsn.inside_bundle) |
5350 | emit_single_op (&orig_insn); | |
5351 | else /* We are inside a bundle. */ | |
e0001a05 | 5352 | { |
43cd72b9 BW |
5353 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5354 | cur_vinsn.num_slots++; | |
5355 | if (*input_line_pointer == '}' | |
5356 | || *(input_line_pointer - 1) == '}' | |
5357 | || *(input_line_pointer - 2) == '}') | |
5358 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5359 | } |
5360 | ||
43cd72b9 BW |
5361 | /* We've just emitted a new instruction so clear the list of labels. */ |
5362 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5363 | } |
5364 | ||
5365 | ||
43cd72b9 | 5366 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5367 | |
43cd72b9 BW |
5368 | /* For a .align directive, we mark the previous block with the alignment |
5369 | information. This will be placed in the object file in the | |
5370 | property section corresponding to this section. */ | |
e0001a05 | 5371 | |
43cd72b9 | 5372 | void |
7fa3d080 | 5373 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5374 | { |
5375 | if (linkrelax | |
b08b5071 | 5376 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5377 | && (fragP->fr_type == rs_align |
5378 | || fragP->fr_type == rs_align_code) | |
5379 | && fragP->fr_address + fragP->fr_fix > 0 | |
5380 | && fragP->fr_offset > 0 | |
5381 | && now_seg != bss_section) | |
e0001a05 | 5382 | { |
43cd72b9 BW |
5383 | fragP->tc_frag_data.is_align = TRUE; |
5384 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5385 | } |
5386 | ||
43cd72b9 | 5387 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5388 | { |
43cd72b9 BW |
5389 | int count; |
5390 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5391 | if (count != 0) | |
c138bc38 | 5392 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5393 | _("unaligned entry instruction")); |
e0001a05 | 5394 | } |
99ded152 BW |
5395 | |
5396 | if (linkrelax && fragP->fr_type == rs_org) | |
5397 | fragP->fr_subtype = RELAX_ORG; | |
e0001a05 | 5398 | } |
43cd72b9 | 5399 | |
e0001a05 NC |
5400 | |
5401 | /* TC_FRAG_INIT hook */ | |
5402 | ||
5403 | void | |
7fa3d080 | 5404 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5405 | { |
43cd72b9 | 5406 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5407 | } |
5408 | ||
5409 | ||
5410 | symbolS * | |
7fa3d080 | 5411 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5412 | { |
5413 | return NULL; | |
5414 | } | |
5415 | ||
5416 | ||
5417 | /* Round up a section size to the appropriate boundary. */ | |
5418 | ||
5419 | valueT | |
7fa3d080 | 5420 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5421 | { |
5422 | return size; /* Byte alignment is fine. */ | |
5423 | } | |
5424 | ||
5425 | ||
5426 | long | |
7fa3d080 | 5427 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5428 | { |
5429 | char *insn_p; | |
5430 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5431 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5432 | int opnum; |
43cd72b9 | 5433 | uint32 opnd_value; |
e0001a05 | 5434 | xtensa_opcode opcode; |
43cd72b9 BW |
5435 | xtensa_format fmt; |
5436 | int slot; | |
e0001a05 NC |
5437 | xtensa_isa isa = xtensa_default_isa; |
5438 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5439 | bfd_boolean alt_reloc; |
e0001a05 | 5440 | |
e0001a05 | 5441 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5442 | return 0; |
e0001a05 NC |
5443 | |
5444 | if (!insnbuf) | |
43cd72b9 BW |
5445 | { |
5446 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5447 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5448 | } | |
e0001a05 NC |
5449 | |
5450 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5451 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5452 | fmt = xtensa_format_decode (isa, insnbuf); |
5453 | ||
5454 | if (fmt == XTENSA_UNDEFINED) | |
5455 | as_fatal (_("bad instruction format")); | |
5456 | ||
5457 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5458 | as_fatal (_("invalid relocation")); | |
5459 | ||
5460 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5461 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5462 | ||
30f725a1 BW |
5463 | /* Check for "alternate" relocations (operand not specified). None |
5464 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5465 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5466 | { | |
5467 | if (opcode != xtensa_l32r_opcode | |
5468 | && opcode != xtensa_const16_opcode) | |
5469 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5470 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5471 | return 0; |
e0001a05 NC |
5472 | } |
5473 | ||
43cd72b9 BW |
5474 | opnum = get_relaxable_immed (opcode); |
5475 | opnd_value = 0; | |
5476 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5477 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5478 | { |
5479 | as_bad_where (fixP->fx_file, | |
5480 | fixP->fx_line, | |
5481 | _("invalid relocation for operand %d of '%s'"), | |
5482 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5483 | return 0; |
e0001a05 | 5484 | } |
43cd72b9 BW |
5485 | return 0 - opnd_value; |
5486 | } | |
5487 | ||
5488 | ||
5489 | /* TC_FORCE_RELOCATION hook */ | |
5490 | ||
5491 | int | |
7fa3d080 | 5492 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5493 | { |
5494 | switch (fix->fx_r_type) | |
30f725a1 BW |
5495 | { |
5496 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5497 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5498 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5499 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5500 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5501 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5502 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5503 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5504 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5505 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5506 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5507 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5508 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5509 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5510 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5511 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5512 | return 1; |
5513 | default: | |
5514 | break; | |
e0001a05 NC |
5515 | } |
5516 | ||
43cd72b9 BW |
5517 | if (linkrelax && fix->fx_addsy |
5518 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5519 | return 1; | |
5520 | ||
5521 | return generic_force_reloc (fix); | |
5522 | } | |
5523 | ||
5524 | ||
30f725a1 BW |
5525 | /* TC_VALIDATE_FIX_SUB hook */ |
5526 | ||
5527 | int | |
5528 | xtensa_validate_fix_sub (fixS *fix) | |
5529 | { | |
5530 | segT add_symbol_segment, sub_symbol_segment; | |
5531 | ||
5532 | /* The difference of two symbols should be resolved by the assembler when | |
5533 | linkrelax is not set. If the linker may relax the section containing | |
5534 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5535 | the linker knows to adjust the difference value. */ | |
5536 | if (!linkrelax || fix->fx_addsy == NULL) | |
5537 | return 0; | |
5538 | ||
5539 | /* Make sure both symbols are in the same segment, and that segment is | |
5540 | "normal" and relaxable. If the segment is not "normal", then the | |
5541 | fix is not valid. If the segment is not "relaxable", then the fix | |
5542 | should have been handled earlier. */ | |
5543 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5544 | if (! SEG_NORMAL (add_symbol_segment) || | |
5545 | ! relaxable_section (add_symbol_segment)) | |
5546 | return 0; | |
5547 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5548 | return (sub_symbol_segment == add_symbol_segment); | |
5549 | } | |
5550 | ||
5551 | ||
43cd72b9 BW |
5552 | /* NO_PSEUDO_DOT hook */ |
5553 | ||
5554 | /* This function has nothing to do with pseudo dots, but this is the | |
5555 | nearest macro to where the check needs to take place. FIXME: This | |
5556 | seems wrong. */ | |
5557 | ||
5558 | bfd_boolean | |
7fa3d080 | 5559 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5560 | { |
5561 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5562 | as_bad (_("directives are not valid inside bundles")); | |
5563 | ||
5564 | /* This function must always return FALSE because it is called via a | |
5565 | macro that has nothing to do with bundling. */ | |
5566 | return FALSE; | |
e0001a05 NC |
5567 | } |
5568 | ||
5569 | ||
43cd72b9 | 5570 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5571 | |
5572 | void | |
7fa3d080 | 5573 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5574 | { |
43cd72b9 BW |
5575 | /* Set up the assembly state. */ |
5576 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5577 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5578 | } |
5579 | ||
5580 | ||
5581 | /* tc_fix_adjustable hook */ | |
5582 | ||
5583 | bfd_boolean | |
7fa3d080 | 5584 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 | 5585 | { |
43cd72b9 BW |
5586 | /* An offset is not allowed in combination with the difference of two |
5587 | symbols, but that cannot be easily detected after a local symbol | |
5588 | has been adjusted to a (section+offset) form. Return 0 so that such | |
5589 | an fix will not be adjusted. */ | |
5590 | if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset | |
5591 | && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy))) | |
5592 | return 0; | |
5593 | ||
e0001a05 NC |
5594 | /* We need the symbol name for the VTABLE entries. */ |
5595 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5596 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5597 | return 0; | |
5598 | ||
5599 | return 1; | |
5600 | } | |
5601 | ||
5602 | ||
6a7eedfe BW |
5603 | /* tc_symbol_new_hook */ |
5604 | ||
5605 | symbolS *expr_symbols = NULL; | |
5606 | ||
5607 | void | |
5608 | xtensa_symbol_new_hook (symbolS *sym) | |
5609 | { | |
5610 | if (S_GET_SEGMENT (sym) == expr_section) | |
5611 | { | |
5612 | symbol_get_tc (sym)->next_expr_symbol = expr_symbols; | |
5613 | expr_symbols = sym; | |
5614 | } | |
5615 | } | |
5616 | ||
5617 | ||
5618 | ||
e0001a05 | 5619 | void |
55cf6793 | 5620 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5621 | { |
30f725a1 | 5622 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5623 | valueT val = 0; |
30f725a1 | 5624 | |
e7da6241 BW |
5625 | /* Subtracted symbols are only allowed for a few relocation types, and |
5626 | unless linkrelax is enabled, they should not make it to this point. */ | |
5627 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5628 | || fixP->fx_r_type == BFD_RELOC_16 | |
5629 | || fixP->fx_r_type == BFD_RELOC_8))) | |
5630 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
5631 | ||
30f725a1 | 5632 | switch (fixP->fx_r_type) |
e0001a05 | 5633 | { |
30f725a1 BW |
5634 | case BFD_RELOC_32: |
5635 | case BFD_RELOC_16: | |
5636 | case BFD_RELOC_8: | |
e7da6241 | 5637 | if (fixP->fx_subsy) |
30f725a1 BW |
5638 | { |
5639 | switch (fixP->fx_r_type) | |
5640 | { | |
5641 | case BFD_RELOC_8: | |
5642 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
5643 | break; | |
5644 | case BFD_RELOC_16: | |
5645 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
5646 | break; | |
5647 | case BFD_RELOC_32: | |
5648 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
5649 | break; | |
5650 | default: | |
5651 | break; | |
5652 | } | |
e0001a05 | 5653 | |
30f725a1 BW |
5654 | /* An offset is only allowed when it results from adjusting a |
5655 | local symbol into a section-relative offset. If the offset | |
5656 | came from the original expression, tc_fix_adjustable will have | |
5657 | prevented the fix from being converted to a section-relative | |
5658 | form so that we can flag the error here. */ | |
5659 | if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy)) | |
5660 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5661 | _("cannot represent subtraction with an offset")); | |
5662 | ||
5663 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5664 | - S_GET_VALUE (fixP->fx_subsy)); | |
5665 | ||
5666 | /* The difference value gets written out, and the DIFF reloc | |
5667 | identifies the address of the subtracted symbol (i.e., the one | |
5668 | with the lowest address). */ | |
5669 | *valP = val; | |
5670 | fixP->fx_offset -= val; | |
5671 | fixP->fx_subsy = NULL; | |
5672 | } | |
5673 | else if (! fixP->fx_addsy) | |
e0001a05 | 5674 | { |
30f725a1 | 5675 | val = *valP; |
e0001a05 | 5676 | fixP->fx_done = 1; |
30f725a1 | 5677 | } |
d47d412e BW |
5678 | /* fall through */ |
5679 | ||
5680 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
5681 | md_number_to_chars (fixpos, val, fixP->fx_size); |
5682 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5683 | break; | |
e0001a05 | 5684 | |
30f725a1 BW |
5685 | case BFD_RELOC_XTENSA_SLOT0_OP: |
5686 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
5687 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
5688 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
5689 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
5690 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
5691 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
5692 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
5693 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
5694 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
5695 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
5696 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
5697 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
5698 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
5699 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
5700 | if (linkrelax) | |
5701 | { | |
5702 | /* Write the tentative value of a PC-relative relocation to a | |
5703 | local symbol into the instruction. The value will be ignored | |
5704 | by the linker, and it makes the object file disassembly | |
5705 | readable when all branch targets are encoded in relocations. */ | |
5706 | ||
5707 | assert (fixP->fx_addsy); | |
20ee54e8 | 5708 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg |
30f725a1 BW |
5709 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) |
5710 | { | |
5711 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5712 | - md_pcrel_from (fixP)); | |
5713 | (void) xg_apply_fix_value (fixP, val); | |
5714 | } | |
5715 | } | |
5716 | else if (! fixP->fx_addsy) | |
5717 | { | |
5718 | val = *valP; | |
5719 | if (xg_apply_fix_value (fixP, val)) | |
5720 | fixP->fx_done = 1; | |
5721 | } | |
5722 | break; | |
e0001a05 | 5723 | |
30f725a1 BW |
5724 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
5725 | case BFD_RELOC_XTENSA_SLOT0_ALT: | |
5726 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5727 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5728 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5729 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5730 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5731 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5732 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5733 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5734 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5735 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5736 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5737 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5738 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5739 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
5740 | /* These all need to be resolved at link-time. Do nothing now. */ | |
5741 | break; | |
e0001a05 | 5742 | |
30f725a1 BW |
5743 | case BFD_RELOC_VTABLE_INHERIT: |
5744 | case BFD_RELOC_VTABLE_ENTRY: | |
5745 | fixP->fx_done = 0; | |
5746 | break; | |
e0001a05 | 5747 | |
30f725a1 BW |
5748 | default: |
5749 | as_bad (_("unhandled local relocation fix %s"), | |
5750 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
5751 | } |
5752 | } | |
5753 | ||
5754 | ||
5755 | char * | |
7fa3d080 | 5756 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 | 5757 | { |
499ac353 | 5758 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
e0001a05 NC |
5759 | } |
5760 | ||
5761 | ||
5762 | int | |
7fa3d080 | 5763 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 5764 | { |
34e41783 | 5765 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
5766 | } |
5767 | ||
5768 | ||
5769 | /* Translate internal representation of relocation info to BFD target | |
5770 | format. */ | |
5771 | ||
5772 | arelent * | |
30f725a1 | 5773 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
5774 | { |
5775 | arelent *reloc; | |
5776 | ||
5777 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
5778 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
5779 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
5780 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
5781 | ||
5782 | /* Make sure none of our internal relocations make it this far. | |
5783 | They'd better have been fully resolved by this point. */ | |
5784 | assert ((int) fixp->fx_r_type > 0); | |
5785 | ||
30f725a1 | 5786 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 5787 | |
e0001a05 NC |
5788 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
5789 | if (reloc->howto == NULL) | |
5790 | { | |
5791 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
5792 | _("cannot represent `%s' relocation in object file"), | |
5793 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
5794 | free (reloc->sym_ptr_ptr); |
5795 | free (reloc); | |
e0001a05 NC |
5796 | return NULL; |
5797 | } | |
5798 | ||
5799 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
43cd72b9 BW |
5800 | as_fatal (_("internal error? cannot generate `%s' relocation"), |
5801 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
e0001a05 | 5802 | |
e0001a05 NC |
5803 | return reloc; |
5804 | } | |
5805 | ||
7fa3d080 BW |
5806 | \f |
5807 | /* Checks for resource conflicts between instructions. */ | |
5808 | ||
c138bc38 BW |
5809 | /* The func unit stuff could be implemented as bit-vectors rather |
5810 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
5811 | slow, we will switch it. */ |
5812 | ||
c138bc38 | 5813 | resource_table * |
7fa3d080 BW |
5814 | new_resource_table (void *data, |
5815 | int cycles, | |
5816 | int nu, | |
5817 | unit_num_copies_func uncf, | |
5818 | opcode_num_units_func onuf, | |
5819 | opcode_funcUnit_use_unit_func ouuf, | |
5820 | opcode_funcUnit_use_stage_func ousf) | |
5821 | { | |
5822 | int i; | |
5823 | resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); | |
5824 | rt->data = data; | |
5825 | rt->cycles = cycles; | |
5826 | rt->allocated_cycles = cycles; | |
5827 | rt->num_units = nu; | |
5828 | rt->unit_num_copies = uncf; | |
5829 | rt->opcode_num_units = onuf; | |
5830 | rt->opcode_unit_use = ouuf; | |
5831 | rt->opcode_unit_stage = ousf; | |
5832 | ||
0bf60745 | 5833 | rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *)); |
7fa3d080 | 5834 | for (i = 0; i < cycles; i++) |
0bf60745 | 5835 | rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char)); |
7fa3d080 BW |
5836 | |
5837 | return rt; | |
5838 | } | |
5839 | ||
5840 | ||
c138bc38 | 5841 | void |
7fa3d080 BW |
5842 | clear_resource_table (resource_table *rt) |
5843 | { | |
5844 | int i, j; | |
5845 | for (i = 0; i < rt->allocated_cycles; i++) | |
5846 | for (j = 0; j < rt->num_units; j++) | |
5847 | rt->units[i][j] = 0; | |
5848 | } | |
5849 | ||
5850 | ||
5851 | /* We never shrink it, just fake it into thinking so. */ | |
5852 | ||
c138bc38 | 5853 | void |
7fa3d080 BW |
5854 | resize_resource_table (resource_table *rt, int cycles) |
5855 | { | |
5856 | int i, old_cycles; | |
5857 | ||
5858 | rt->cycles = cycles; | |
5859 | if (cycles <= rt->allocated_cycles) | |
5860 | return; | |
5861 | ||
5862 | old_cycles = rt->allocated_cycles; | |
5863 | rt->allocated_cycles = cycles; | |
5864 | ||
0bf60745 BW |
5865 | rt->units = xrealloc (rt->units, |
5866 | rt->allocated_cycles * sizeof (unsigned char *)); | |
7fa3d080 | 5867 | for (i = 0; i < old_cycles; i++) |
0bf60745 BW |
5868 | rt->units[i] = xrealloc (rt->units[i], |
5869 | rt->num_units * sizeof (unsigned char)); | |
7fa3d080 | 5870 | for (i = old_cycles; i < cycles; i++) |
0bf60745 | 5871 | rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char)); |
7fa3d080 BW |
5872 | } |
5873 | ||
5874 | ||
c138bc38 | 5875 | bfd_boolean |
7fa3d080 BW |
5876 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
5877 | { | |
5878 | int i; | |
5879 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5880 | ||
c138bc38 | 5881 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5882 | { |
5883 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5884 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
5885 | int copies_in_use = rt->units[stage + cycle][unit]; | |
5886 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
5887 | if (copies_in_use >= copies) | |
5888 | return FALSE; | |
5889 | } | |
5890 | return TRUE; | |
5891 | } | |
7fa3d080 | 5892 | |
c138bc38 BW |
5893 | |
5894 | void | |
7fa3d080 BW |
5895 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5896 | { | |
5897 | int i; | |
5898 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5899 | ||
c138bc38 | 5900 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5901 | { |
5902 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5903 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
5904 | /* Note that this allows resources to be oversubscribed. That's |
5905 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
5906 | resources_available reports when a resource is over-subscribed, |
5907 | so it's easy to tell. */ | |
5908 | rt->units[stage + cycle][unit]++; | |
5909 | } | |
5910 | } | |
5911 | ||
5912 | ||
c138bc38 | 5913 | void |
7fa3d080 BW |
5914 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5915 | { | |
5916 | int i; | |
5917 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5918 | ||
c138bc38 | 5919 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5920 | { |
5921 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5922 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
0bf60745 | 5923 | assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 5924 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
5925 | } |
5926 | } | |
c138bc38 | 5927 | |
7fa3d080 BW |
5928 | |
5929 | /* Wrapper functions make parameterized resource reservation | |
5930 | more convenient. */ | |
5931 | ||
c138bc38 | 5932 | int |
7fa3d080 BW |
5933 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
5934 | { | |
5935 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 5936 | return use->unit; |
7fa3d080 BW |
5937 | } |
5938 | ||
5939 | ||
c138bc38 | 5940 | int |
7fa3d080 BW |
5941 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
5942 | { | |
5943 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
5944 | return use->stage; | |
5945 | } | |
5946 | ||
5947 | ||
5948 | /* Note that this function does not check issue constraints, but | |
5949 | solely whether the hardware is available to execute the given | |
c138bc38 | 5950 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 5951 | write the same state, or access the same tieports. That is |
a1ace8d8 | 5952 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
5953 | |
5954 | static bfd_boolean | |
5955 | resources_conflict (vliw_insn *vinsn) | |
5956 | { | |
5957 | int i; | |
5958 | static resource_table *rt = NULL; | |
5959 | ||
5960 | /* This is the most common case by far. Optimize it. */ | |
5961 | if (vinsn->num_slots == 1) | |
5962 | return FALSE; | |
43cd72b9 | 5963 | |
c138bc38 | 5964 | if (rt == NULL) |
7fa3d080 BW |
5965 | { |
5966 | xtensa_isa isa = xtensa_default_isa; | |
5967 | rt = new_resource_table | |
5968 | (isa, xtensa_isa_num_pipe_stages (isa), | |
5969 | xtensa_isa_num_funcUnits (isa), | |
5970 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
5971 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
5972 | opcode_funcUnit_use_unit, | |
5973 | opcode_funcUnit_use_stage); | |
5974 | } | |
43cd72b9 | 5975 | |
7fa3d080 | 5976 | clear_resource_table (rt); |
43cd72b9 | 5977 | |
7fa3d080 BW |
5978 | for (i = 0; i < vinsn->num_slots; i++) |
5979 | { | |
5980 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
5981 | return TRUE; | |
5982 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
5983 | } | |
e0001a05 | 5984 | |
7fa3d080 BW |
5985 | return FALSE; |
5986 | } | |
e0001a05 | 5987 | |
7fa3d080 BW |
5988 | \f |
5989 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 5990 | |
7fa3d080 BW |
5991 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
5992 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 5993 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
5994 | |
5995 | ||
43cd72b9 BW |
5996 | /* We have reached the end of a bundle; emit into the frag. */ |
5997 | ||
e0001a05 | 5998 | static void |
7fa3d080 | 5999 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 6000 | { |
43cd72b9 BW |
6001 | IStack slotstack; |
6002 | int i; | |
6003 | char *file_name; | |
d77b99c9 | 6004 | unsigned line; |
e0001a05 | 6005 | |
43cd72b9 | 6006 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
6007 | { |
6008 | xg_clear_vinsn (vinsn); | |
6009 | return; | |
6010 | } | |
43cd72b9 BW |
6011 | |
6012 | /* First, find a format that works. */ | |
6013 | if (vinsn->format == XTENSA_UNDEFINED) | |
6014 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6015 | ||
6016 | if (vinsn->format == XTENSA_UNDEFINED) | |
6017 | { | |
6018 | as_where (&file_name, &line); | |
6019 | as_bad_where (file_name, line, | |
6020 | _("couldn't find a valid instruction format")); | |
6021 | fprintf (stderr, _(" ops were: ")); | |
6022 | for (i = 0; i < vinsn->num_slots; i++) | |
6023 | fprintf (stderr, _(" %s;"), | |
6024 | xtensa_opcode_name (xtensa_default_isa, | |
6025 | vinsn->slots[i].opcode)); | |
6026 | fprintf (stderr, _("\n")); | |
6027 | xg_clear_vinsn (vinsn); | |
6028 | return; | |
6029 | } | |
6030 | ||
6031 | if (vinsn->num_slots | |
6032 | != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) | |
e0001a05 | 6033 | { |
43cd72b9 BW |
6034 | as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), |
6035 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
6036 | xtensa_format_num_slots (xtensa_default_isa, vinsn->format), | |
6037 | vinsn->num_slots); | |
6038 | xg_clear_vinsn (vinsn); | |
6039 | return; | |
6040 | } | |
e0001a05 | 6041 | |
c138bc38 | 6042 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6043 | { |
6044 | as_where (&file_name, &line); | |
6045 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6046 | fprintf (stderr, " ops were: "); | |
6047 | for (i = 0; i < vinsn->num_slots; i++) | |
6048 | fprintf (stderr, " %s;", | |
6049 | xtensa_opcode_name (xtensa_default_isa, | |
6050 | vinsn->slots[i].opcode)); | |
6051 | fprintf (stderr, "\n"); | |
6052 | xg_clear_vinsn (vinsn); | |
6053 | return; | |
6054 | } | |
6055 | ||
6056 | for (i = 0; i < vinsn->num_slots; i++) | |
6057 | { | |
6058 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6059 | { |
43cd72b9 BW |
6060 | symbolS *lit_sym = NULL; |
6061 | int j; | |
6062 | bfd_boolean e = FALSE; | |
6063 | bfd_boolean saved_density = density_supported; | |
6064 | ||
6065 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6066 | if (vinsn->num_slots > 1) | |
6067 | density_supported = FALSE; | |
6068 | ||
6069 | istack_init (&slotstack); | |
6070 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6071 | { |
43cd72b9 BW |
6072 | vinsn->slots[i].opcode = |
6073 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6074 | vinsn->format, i); | |
6075 | vinsn->slots[i].ntok = 0; | |
6076 | } | |
e0001a05 | 6077 | |
43cd72b9 BW |
6078 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6079 | { | |
6080 | e = TRUE; | |
6081 | continue; | |
e0001a05 | 6082 | } |
e0001a05 | 6083 | |
43cd72b9 | 6084 | density_supported = saved_density; |
e0001a05 | 6085 | |
43cd72b9 BW |
6086 | if (e) |
6087 | { | |
6088 | xg_clear_vinsn (vinsn); | |
6089 | return; | |
6090 | } | |
e0001a05 | 6091 | |
0fa77c95 | 6092 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6093 | { |
6094 | TInsn *insn = &slotstack.insn[j]; | |
6095 | if (insn->insn_type == ITYPE_LITERAL) | |
6096 | { | |
6097 | assert (lit_sym == NULL); | |
6098 | lit_sym = xg_assemble_literal (insn); | |
6099 | } | |
6100 | else | |
6101 | { | |
0fa77c95 | 6102 | assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6103 | if (lit_sym) |
6104 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6105 | if (j != slotstack.ninsn - 1) |
6106 | emit_single_op (insn); | |
43cd72b9 BW |
6107 | } |
6108 | } | |
6109 | ||
6110 | if (vinsn->num_slots > 1) | |
6111 | { | |
6112 | if (opcode_fits_format_slot | |
6113 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6114 | vinsn->format, i)) | |
6115 | { | |
6116 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6117 | } | |
6118 | else | |
6119 | { | |
b2d179be | 6120 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6121 | if (vinsn->format == XTENSA_UNDEFINED) |
6122 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6123 | else | |
c138bc38 | 6124 | vinsn->slots[i].opcode |
43cd72b9 BW |
6125 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6126 | vinsn->format, i); | |
6127 | ||
6128 | vinsn->slots[i].ntok = 0; | |
6129 | } | |
6130 | } | |
6131 | else | |
6132 | { | |
6133 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6134 | vinsn->format = XTENSA_UNDEFINED; | |
6135 | } | |
6136 | } | |
6137 | } | |
6138 | ||
6139 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6140 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6141 | { |
6142 | as_where (&file_name, &line); | |
6143 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6144 | fprintf (stderr, " ops were: "); | |
6145 | for (i = 0; i < vinsn->num_slots; i++) | |
6146 | fprintf (stderr, " %s;", | |
6147 | xtensa_opcode_name (xtensa_default_isa, | |
6148 | vinsn->slots[i].opcode)); | |
6149 | fprintf (stderr, "\n"); | |
6150 | xg_clear_vinsn (vinsn); | |
6151 | return; | |
6152 | } | |
6153 | ||
6154 | /* First, find a format that works. */ | |
6155 | if (vinsn->format == XTENSA_UNDEFINED) | |
6156 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6157 | ||
6158 | xg_assemble_vliw_tokens (vinsn); | |
6159 | ||
6160 | xg_clear_vinsn (vinsn); | |
6161 | } | |
6162 | ||
6163 | ||
6164 | /* Given an vliw instruction, what conflicts are there in register | |
6165 | usage and in writes to states and queues? | |
6166 | ||
6167 | This function does two things: | |
6168 | 1. Reports an error when a vinsn contains illegal combinations | |
6169 | of writes to registers states or queues. | |
6170 | 2. Marks individual tinsns as not relaxable if the combination | |
6171 | contains antidependencies. | |
6172 | ||
6173 | Job 2 handles things like swap semantics in instructions that need | |
6174 | to be relaxed. For example, | |
6175 | ||
6176 | addi a0, a1, 100000 | |
6177 | ||
6178 | normally would be relaxed to | |
6179 | ||
6180 | l32r a0, some_label | |
6181 | add a0, a1, a0 | |
6182 | ||
6183 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6184 | ||
6185 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6186 | ||
6187 | then we can't relax it into | |
6188 | ||
6189 | l32r a0, some_label | |
6190 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6191 | ||
6192 | because the value of a0 is trashed before the second add can read it. */ | |
6193 | ||
7fa3d080 BW |
6194 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6195 | ||
43cd72b9 | 6196 | static bfd_boolean |
7fa3d080 | 6197 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6198 | { |
6199 | int i, j; | |
6200 | int branches = 0; | |
6201 | xtensa_isa isa = xtensa_default_isa; | |
6202 | ||
6203 | assert (!past_xtensa_end); | |
6204 | ||
6205 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6206 | { | |
6207 | TInsn *op1 = &vinsn->slots[i]; | |
6208 | if (op1->is_specific_opcode) | |
6209 | op1->keep_wide = TRUE; | |
6210 | else | |
6211 | op1->keep_wide = FALSE; | |
6212 | } | |
6213 | ||
6214 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6215 | { | |
6216 | TInsn *op1 = &vinsn->slots[i]; | |
6217 | ||
6218 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6219 | branches++; | |
6220 | ||
6221 | for (j = 0; j < vinsn->num_slots; j++) | |
6222 | { | |
6223 | if (i != j) | |
6224 | { | |
6225 | TInsn *op2 = &vinsn->slots[j]; | |
6226 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6227 | switch (conflict_type) | |
6228 | { | |
6229 | case 'c': | |
6230 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6231 | xtensa_opcode_name (isa, op1->opcode), i, | |
6232 | xtensa_opcode_name (isa, op2->opcode), j); | |
6233 | return TRUE; | |
6234 | case 'd': | |
6235 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6236 | xtensa_opcode_name (isa, op1->opcode), i, | |
6237 | xtensa_opcode_name (isa, op2->opcode), j); | |
6238 | return TRUE; | |
6239 | case 'e': | |
53dfbcc7 | 6240 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6241 | xtensa_opcode_name (isa, op1->opcode), i, |
6242 | xtensa_opcode_name (isa, op2->opcode), j); | |
6243 | return TRUE; | |
6244 | case 'f': | |
53dfbcc7 | 6245 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6246 | xtensa_opcode_name (isa, op1->opcode), i, |
6247 | xtensa_opcode_name (isa, op2->opcode), j); | |
6248 | return TRUE; | |
6249 | default: | |
6250 | /* Everything is OK. */ | |
6251 | break; | |
6252 | } | |
6253 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6254 | || conflict_type == 'a'); | |
6255 | } | |
6256 | } | |
6257 | } | |
6258 | ||
6259 | if (branches > 1) | |
6260 | { | |
6261 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6262 | return TRUE; | |
6263 | } | |
6264 | ||
6265 | return FALSE; | |
6266 | } | |
6267 | ||
6268 | ||
a1ace8d8 | 6269 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6270 | Cases found are: |
6271 | ||
6272 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6273 | case B: no relationship between what is read and written (both could | |
6274 | read the same reg though) | |
c138bc38 | 6275 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6276 | bundle) |
6277 | case D: t1 writes a state that t2 also writes | |
6278 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6279 | case F: two volatile queue accesses |
43cd72b9 BW |
6280 | */ |
6281 | ||
6282 | static char | |
7fa3d080 | 6283 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6284 | { |
6285 | xtensa_isa isa = xtensa_default_isa; | |
6286 | xtensa_regfile t1_regfile, t2_regfile; | |
6287 | int t1_reg, t2_reg; | |
6288 | int t1_base_reg, t1_last_reg; | |
6289 | int t2_base_reg, t2_last_reg; | |
6290 | char t1_inout, t2_inout; | |
6291 | int i, j; | |
6292 | char conflict = 'b'; | |
6293 | int t1_states; | |
6294 | int t2_states; | |
6295 | int t1_interfaces; | |
6296 | int t2_interfaces; | |
6297 | bfd_boolean t1_volatile = FALSE; | |
6298 | bfd_boolean t2_volatile = FALSE; | |
6299 | ||
6300 | /* Check registers. */ | |
6301 | for (j = 0; j < t2->ntok; j++) | |
6302 | { | |
6303 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6304 | continue; | |
6305 | ||
6306 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6307 | t2_base_reg = t2->tok[j].X_add_number; | |
6308 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6309 | ||
6310 | for (i = 0; i < t1->ntok; i++) | |
6311 | { | |
6312 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6313 | continue; | |
6314 | ||
6315 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6316 | ||
6317 | if (t1_regfile != t2_regfile) | |
6318 | continue; | |
6319 | ||
6320 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6321 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6322 | ||
6323 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6324 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6325 | { | |
6326 | if (t1_inout == 'm' || t1_inout == 'o' | |
6327 | || t2_inout == 'm' || t2_inout == 'o') | |
6328 | { | |
6329 | conflict = 'a'; | |
6330 | continue; | |
6331 | } | |
6332 | } | |
6333 | ||
6334 | t1_base_reg = t1->tok[i].X_add_number; | |
6335 | t1_last_reg = (t1_base_reg | |
6336 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6337 | ||
6338 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6339 | { | |
6340 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6341 | { | |
6342 | if (t1_reg != t2_reg) | |
6343 | continue; | |
6344 | ||
6345 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6346 | { |
6347 | conflict = 'a'; | |
6348 | continue; | |
6349 | } | |
43cd72b9 | 6350 | |
7fa3d080 BW |
6351 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6352 | { | |
6353 | conflict = 'a'; | |
6354 | continue; | |
6355 | } | |
43cd72b9 | 6356 | |
7fa3d080 BW |
6357 | if (t1_inout != 'i' && t2_inout != 'i') |
6358 | return 'c'; | |
6359 | } | |
6360 | } | |
6361 | } | |
6362 | } | |
43cd72b9 | 6363 | |
7fa3d080 BW |
6364 | /* Check states. */ |
6365 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6366 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6367 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6368 | { |
7fa3d080 BW |
6369 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6370 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6371 | for (i = 0; i < t1_states; i++) | |
6372 | { | |
6373 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6374 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
c138bc38 | 6375 | if (t1_so != t2_so) |
7fa3d080 | 6376 | continue; |
43cd72b9 | 6377 | |
7fa3d080 BW |
6378 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6379 | { | |
6380 | conflict = 'a'; | |
6381 | continue; | |
6382 | } | |
c138bc38 | 6383 | |
7fa3d080 BW |
6384 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6385 | { | |
6386 | conflict = 'a'; | |
6387 | continue; | |
6388 | } | |
c138bc38 | 6389 | |
7fa3d080 BW |
6390 | if (t1_inout != 'i' && t2_inout != 'i') |
6391 | return 'd'; | |
c138bc38 | 6392 | } |
7fa3d080 | 6393 | } |
43cd72b9 | 6394 | |
7fa3d080 BW |
6395 | /* Check tieports. */ |
6396 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6397 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6398 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6399 | { |
7fa3d080 BW |
6400 | xtensa_interface t2_int |
6401 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6402 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6403 | ||
53dfbcc7 | 6404 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6405 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6406 | t2_volatile = TRUE; |
a1ace8d8 | 6407 | |
7fa3d080 BW |
6408 | for (i = 0; i < t1_interfaces; i++) |
6409 | { | |
6410 | xtensa_interface t1_int | |
6411 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6412 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6413 | |
53dfbcc7 | 6414 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6415 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6416 | t1_volatile = TRUE; |
a1ace8d8 BW |
6417 | |
6418 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6419 | return 'f'; | |
c138bc38 | 6420 | |
7fa3d080 BW |
6421 | if (t1_int != t2_int) |
6422 | continue; | |
c138bc38 | 6423 | |
7fa3d080 BW |
6424 | if (t2_inout == 'i' && t1_inout == 'o') |
6425 | { | |
6426 | conflict = 'a'; | |
6427 | continue; | |
6428 | } | |
c138bc38 | 6429 | |
7fa3d080 BW |
6430 | if (t1_inout == 'i' && t2_inout == 'o') |
6431 | { | |
6432 | conflict = 'a'; | |
6433 | continue; | |
6434 | } | |
c138bc38 | 6435 | |
7fa3d080 BW |
6436 | if (t1_inout != 'i' && t2_inout != 'i') |
6437 | return 'e'; | |
6438 | } | |
43cd72b9 | 6439 | } |
c138bc38 | 6440 | |
7fa3d080 | 6441 | return conflict; |
43cd72b9 BW |
6442 | } |
6443 | ||
6444 | ||
6445 | static xtensa_format | |
7fa3d080 | 6446 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6447 | { |
6448 | /* Right now we assume that the ops within the vinsn are properly | |
6449 | ordered for the slots that the programmer wanted them in. In | |
6450 | other words, we don't rearrange the ops in hopes of finding a | |
6451 | better format. The scheduler handles that. */ | |
6452 | ||
6453 | xtensa_isa isa = xtensa_default_isa; | |
6454 | xtensa_format format; | |
6455 | vliw_insn v_copy = *vinsn; | |
6456 | xtensa_opcode nop_opcode = xtensa_nop_opcode; | |
6457 | ||
65738a7d BW |
6458 | if (vinsn->num_slots == 1) |
6459 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6460 | ||
43cd72b9 BW |
6461 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6462 | { | |
6463 | v_copy = *vinsn; | |
6464 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) | |
6465 | { | |
6466 | int slot; | |
6467 | int fit = 0; | |
6468 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6469 | { | |
6470 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6471 | { | |
6472 | v_copy.slots[slot].opcode = | |
6473 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6474 | v_copy.slots[slot].ntok = 0; | |
6475 | } | |
6476 | ||
6477 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6478 | format, slot)) | |
6479 | fit++; | |
7fa3d080 | 6480 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6481 | { |
7fa3d080 BW |
6482 | TInsn widened; |
6483 | /* Try the widened version. */ | |
6484 | if (!v_copy.slots[slot].keep_wide | |
6485 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6486 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6487 | &widened, TRUE) | |
7fa3d080 BW |
6488 | && opcode_fits_format_slot (widened.opcode, |
6489 | format, slot)) | |
43cd72b9 | 6490 | { |
7fa3d080 BW |
6491 | v_copy.slots[slot] = widened; |
6492 | fit++; | |
43cd72b9 BW |
6493 | } |
6494 | } | |
6495 | } | |
6496 | if (fit == v_copy.num_slots) | |
6497 | { | |
6498 | *vinsn = v_copy; | |
6499 | xtensa_format_encode (isa, format, vinsn->insnbuf); | |
6500 | vinsn->format = format; | |
6501 | break; | |
6502 | } | |
6503 | } | |
6504 | } | |
6505 | ||
6506 | if (format == xtensa_isa_num_formats (isa)) | |
6507 | return XTENSA_UNDEFINED; | |
6508 | ||
6509 | return format; | |
6510 | } | |
6511 | ||
6512 | ||
6513 | /* Return the additional space needed in a frag | |
6514 | for possible relaxations of any ops in a VLIW insn. | |
6515 | Also fill out the relaxations that might be required of | |
6516 | each tinsn in the vinsn. */ | |
6517 | ||
6518 | static int | |
e7da6241 | 6519 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6520 | { |
e7da6241 | 6521 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6522 | int extra_space = 0; |
6523 | int slot; | |
6524 | ||
6525 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6526 | { | |
6527 | TInsn *tinsn = &vinsn->slots[slot]; | |
6528 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6529 | { | |
6530 | /* A narrow instruction could be widened later to help | |
6531 | alignment issues. */ | |
84b08ed9 | 6532 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6533 | && !tinsn->is_specific_opcode |
6534 | && vinsn->num_slots == 1) | |
6535 | { | |
6536 | /* Difference in bytes between narrow and wide insns... */ | |
6537 | extra_space += 1; | |
6538 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6539 | } |
6540 | } | |
6541 | else | |
6542 | { | |
b08b5071 BW |
6543 | if (workaround_b_j_loop_end |
6544 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6545 | && use_transform ()) |
6546 | { | |
6547 | /* Add 2 of these. */ | |
6548 | extra_space += 3; /* for the nop size */ | |
6549 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6550 | } | |
c138bc38 | 6551 | |
43cd72b9 BW |
6552 | /* Need to assemble it with space for the relocation. */ |
6553 | if (xg_is_relaxable_insn (tinsn, 0) | |
6554 | && !tinsn->is_specific_opcode) | |
6555 | { | |
6556 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6557 | int max_literal_size = | |
6558 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6559 | |
43cd72b9 | 6560 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6561 | |
43cd72b9 | 6562 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6563 | extra_space += max_size; |
6564 | } | |
6565 | else | |
6566 | { | |
e7da6241 BW |
6567 | /* A fix record will be added for this instruction prior |
6568 | to relaxation, so make it end the frag. */ | |
6569 | finish_frag = TRUE; | |
43cd72b9 BW |
6570 | } |
6571 | } | |
6572 | } | |
e7da6241 | 6573 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6574 | return extra_space; |
6575 | } | |
6576 | ||
6577 | ||
6578 | static void | |
b2d179be | 6579 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6580 | { |
6581 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6582 | int slot, chosen_slot; |
43cd72b9 | 6583 | |
b2d179be BW |
6584 | vinsn->format = xg_get_single_format (tinsn->opcode); |
6585 | assert (vinsn->format != XTENSA_UNDEFINED); | |
6586 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); | |
43cd72b9 | 6587 | |
b2d179be BW |
6588 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6589 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6590 | { |
b2d179be BW |
6591 | if (slot == chosen_slot) |
6592 | vinsn->slots[slot] = *tinsn; | |
6593 | else | |
6594 | { | |
6595 | vinsn->slots[slot].opcode = | |
6596 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6597 | vinsn->slots[slot].ntok = 0; | |
6598 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6599 | } | |
43cd72b9 | 6600 | } |
43cd72b9 BW |
6601 | } |
6602 | ||
6603 | ||
6604 | static bfd_boolean | |
7fa3d080 | 6605 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6606 | { |
6607 | int i; | |
6608 | IStack istack; /* put instructions into here */ | |
6609 | symbolS *lit_sym = NULL; | |
6610 | symbolS *label_sym = NULL; | |
6611 | ||
6612 | istack_init (&istack); | |
6613 | ||
6614 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
6615 | Because the scheduling and bundling characteristics of movi and |
6616 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 6617 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 6618 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
6619 | || orig_insn->opcode == xtensa_movi_n_opcode) |
6620 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 6621 | && (orig_insn->tok[1].X_op == O_symbol |
482fd9f9 BW |
6622 | || orig_insn->tok[1].X_op == O_pltrel) |
6623 | && !orig_insn->is_specific_opcode && use_transform ()) | |
43cd72b9 BW |
6624 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
6625 | else | |
6626 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6627 | return TRUE; | |
6628 | ||
6629 | for (i = 0; i < istack.ninsn; i++) | |
6630 | { | |
6631 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 6632 | switch (insn->insn_type) |
43cd72b9 BW |
6633 | { |
6634 | case ITYPE_LITERAL: | |
6635 | assert (lit_sym == NULL); | |
6636 | lit_sym = xg_assemble_literal (insn); | |
6637 | break; | |
6638 | case ITYPE_LABEL: | |
6639 | { | |
6640 | static int relaxed_sym_idx = 0; | |
6641 | char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); | |
6642 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); | |
6643 | colon (label); | |
6644 | assert (label_sym == NULL); | |
6645 | label_sym = symbol_find_or_make (label); | |
6646 | assert (label_sym); | |
6647 | free (label); | |
6648 | } | |
6649 | break; | |
6650 | case ITYPE_INSN: | |
b2d179be BW |
6651 | { |
6652 | vliw_insn v; | |
6653 | if (lit_sym) | |
6654 | xg_resolve_literals (insn, lit_sym); | |
6655 | if (label_sym) | |
6656 | xg_resolve_labels (insn, label_sym); | |
6657 | xg_init_vinsn (&v); | |
6658 | bundle_tinsn (insn, &v); | |
6659 | finish_vinsn (&v); | |
6660 | xg_free_vinsn (&v); | |
6661 | } | |
43cd72b9 BW |
6662 | break; |
6663 | default: | |
6664 | assert (0); | |
6665 | break; | |
6666 | } | |
6667 | } | |
6668 | return FALSE; | |
6669 | } | |
6670 | ||
6671 | ||
34e41783 BW |
6672 | static int |
6673 | total_frag_text_expansion (fragS *fragP) | |
6674 | { | |
6675 | int slot; | |
6676 | int total_expansion = 0; | |
6677 | ||
6678 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
6679 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; | |
6680 | ||
6681 | return total_expansion; | |
6682 | } | |
6683 | ||
6684 | ||
43cd72b9 BW |
6685 | /* Emit a vliw instruction to the current fragment. */ |
6686 | ||
7fa3d080 BW |
6687 | static void |
6688 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 6689 | { |
e7da6241 | 6690 | bfd_boolean finish_frag; |
43cd72b9 BW |
6691 | bfd_boolean is_jump = FALSE; |
6692 | bfd_boolean is_branch = FALSE; | |
6693 | xtensa_isa isa = xtensa_default_isa; | |
6694 | int i; | |
6695 | int insn_size; | |
6696 | int extra_space; | |
6697 | char *f = NULL; | |
6698 | int slot; | |
7c430684 BW |
6699 | unsigned current_line, best_linenum; |
6700 | char *current_file; | |
43cd72b9 | 6701 | |
7c430684 | 6702 | best_linenum = UINT_MAX; |
43cd72b9 BW |
6703 | |
6704 | if (generating_literals) | |
6705 | { | |
6706 | static int reported = 0; | |
6707 | if (reported < 4) | |
6708 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
6709 | _("cannot assemble into a literal fragment")); | |
6710 | if (reported == 3) | |
6711 | as_bad (_("...")); | |
6712 | reported++; | |
6713 | return; | |
6714 | } | |
6715 | ||
6716 | if (frag_now_fix () != 0 | |
b08b5071 | 6717 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 6718 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
b08b5071 | 6719 | || !use_transform () != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
6720 | || (directive_state[directive_longcalls] |
6721 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
6722 | || (directive_state[directive_absolute_literals] |
6723 | != frag_now->tc_frag_data.use_absolute_literals))) | |
6724 | { | |
6725 | frag_wane (frag_now); | |
6726 | frag_new (0); | |
6727 | xtensa_set_frag_assembly_state (frag_now); | |
6728 | } | |
6729 | ||
6730 | if (workaround_a0_b_retw | |
6731 | && vinsn->num_slots == 1 | |
6732 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
6733 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
6734 | && use_transform ()) | |
6735 | { | |
6736 | has_a0_b_retw = TRUE; | |
6737 | ||
6738 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
6739 | After the first assembly pass we will check all of them and | |
6740 | add a nop if needed. */ | |
6741 | frag_now->tc_frag_data.is_insn = TRUE; | |
6742 | frag_var (rs_machine_dependent, 4, 4, | |
6743 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6744 | frag_now->fr_symbol, | |
6745 | frag_now->fr_offset, | |
6746 | NULL); | |
6747 | xtensa_set_frag_assembly_state (frag_now); | |
6748 | frag_now->tc_frag_data.is_insn = TRUE; | |
6749 | frag_var (rs_machine_dependent, 4, 4, | |
6750 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6751 | frag_now->fr_symbol, | |
6752 | frag_now->fr_offset, | |
6753 | NULL); | |
6754 | xtensa_set_frag_assembly_state (frag_now); | |
6755 | } | |
6756 | ||
6757 | for (i = 0; i < vinsn->num_slots; i++) | |
6758 | { | |
6759 | /* See if the instruction implies an aligned section. */ | |
6760 | if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1) | |
6761 | record_alignment (now_seg, 2); | |
c138bc38 | 6762 | |
43cd72b9 | 6763 | /* Also determine the best line number for debug info. */ |
7c430684 BW |
6764 | best_linenum = vinsn->slots[i].linenum < best_linenum |
6765 | ? vinsn->slots[i].linenum : best_linenum; | |
43cd72b9 BW |
6766 | } |
6767 | ||
6768 | /* Special cases for instructions that force an alignment... */ | |
6769 | /* None of these opcodes are bundle-able. */ | |
6770 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
6771 | { | |
d77b99c9 | 6772 | int max_fill; |
c138bc38 | 6773 | |
05d58145 BW |
6774 | /* Remember the symbol that marks the end of the loop in the frag |
6775 | that marks the start of the loop. This way we can easily find | |
6776 | the end of the loop at the beginning, without adding special code | |
6777 | to mark the loop instructions themselves. */ | |
6778 | symbolS *target_sym = NULL; | |
6779 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
6780 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
6781 | ||
43cd72b9 BW |
6782 | xtensa_set_frag_assembly_state (frag_now); |
6783 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 6784 | |
43cd72b9 BW |
6785 | max_fill = get_text_align_max_fill_size |
6786 | (get_text_align_power (xtensa_fetch_width), | |
6787 | TRUE, frag_now->tc_frag_data.is_no_density); | |
6788 | ||
6789 | if (use_transform ()) | |
6790 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 6791 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6792 | else |
c138bc38 | 6793 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 6794 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6795 | xtensa_set_frag_assembly_state (frag_now); |
43cd72b9 BW |
6796 | } |
6797 | ||
b08b5071 | 6798 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
6799 | && !vinsn->slots[0].is_specific_opcode) |
6800 | { | |
6801 | xtensa_mark_literal_pool_location (); | |
c3ea6048 | 6802 | xtensa_move_labels (frag_now, 0); |
43cd72b9 BW |
6803 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); |
6804 | } | |
6805 | ||
6806 | if (vinsn->num_slots == 1) | |
6807 | { | |
6808 | if (workaround_a0_b_retw && use_transform ()) | |
6809 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
6810 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
6811 | ||
6812 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
6813 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
6814 | } | |
6815 | else | |
6816 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
6817 | ||
6818 | insn_size = xtensa_format_length (isa, vinsn->format); | |
6819 | ||
e7da6241 | 6820 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
6821 | |
6822 | /* vinsn_to_insnbuf will produce the error. */ | |
6823 | if (vinsn->format != XTENSA_UNDEFINED) | |
6824 | { | |
d77b99c9 | 6825 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
6826 | xtensa_set_frag_assembly_state (frag_now); |
6827 | frag_now->tc_frag_data.is_insn = TRUE; | |
6828 | } | |
6829 | ||
e7da6241 | 6830 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
6831 | if (vinsn->format == XTENSA_UNDEFINED) |
6832 | return; | |
6833 | ||
d77b99c9 | 6834 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 6835 | |
7c430684 BW |
6836 | /* Temporarily set the logical line number to the one we want to appear |
6837 | in the debug information. */ | |
6838 | as_where (¤t_file, ¤t_line); | |
6839 | new_logical_line (current_file, best_linenum); | |
6840 | dwarf2_emit_insn (insn_size + extra_space); | |
6841 | new_logical_line (current_file, current_line); | |
43cd72b9 BW |
6842 | |
6843 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6844 | { | |
6845 | TInsn *tinsn = &vinsn->slots[slot]; | |
6846 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; | |
7c834684 | 6847 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 6848 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 BW |
6849 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
6850 | if (tinsn->literal_space != 0) | |
6851 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
6852 | ||
6853 | if (tinsn->subtype == RELAX_NARROW) | |
6854 | assert (vinsn->num_slots == 1); | |
6855 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) | |
6856 | is_jump = TRUE; | |
6857 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
6858 | is_branch = TRUE; | |
6859 | ||
e7da6241 BW |
6860 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
6861 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
6862 | finish_frag = TRUE; |
6863 | } | |
6864 | ||
6865 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 6866 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
6867 | |
6868 | if (finish_frag) | |
6869 | { | |
6870 | frag_variant (rs_machine_dependent, | |
6871 | extra_space, extra_space, RELAX_SLOTS, | |
6872 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
6873 | xtensa_set_frag_assembly_state (frag_now); | |
6874 | } | |
6875 | ||
6876 | /* Special cases for loops: | |
6877 | close_loop_end should be inserted AFTER short_loop. | |
6878 | Make sure that CLOSE loops are processed BEFORE short_loops | |
6879 | when converting them. */ | |
6880 | ||
6881 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 6882 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
6883 | && !vinsn->slots[0].is_specific_opcode) |
6884 | { | |
6885 | if (workaround_short_loop && use_transform ()) | |
6886 | { | |
6887 | maybe_has_short_loop = TRUE; | |
6888 | frag_now->tc_frag_data.is_insn = TRUE; | |
6889 | frag_var (rs_machine_dependent, 4, 4, | |
6890 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6891 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6892 | frag_now->tc_frag_data.is_insn = TRUE; | |
6893 | frag_var (rs_machine_dependent, 4, 4, | |
6894 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6895 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6896 | } | |
6897 | ||
6898 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
6899 | loop at least 12 bytes away from another loop's end. */ | |
6900 | if (workaround_close_loop_end && use_transform ()) | |
6901 | { | |
6902 | maybe_has_close_loop_end = TRUE; | |
6903 | frag_now->tc_frag_data.is_insn = TRUE; | |
6904 | frag_var (rs_machine_dependent, 12, 12, | |
6905 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
6906 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6907 | } | |
6908 | } | |
6909 | ||
6910 | if (use_transform ()) | |
6911 | { | |
6912 | if (is_jump) | |
6913 | { | |
6914 | assert (finish_frag); | |
6915 | frag_var (rs_machine_dependent, | |
6916 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6917 | RELAX_UNREACHABLE, | |
6918 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6919 | xtensa_set_frag_assembly_state (frag_now); | |
6920 | } | |
7b1cc377 | 6921 | else if (is_branch && do_align_targets ()) |
43cd72b9 BW |
6922 | { |
6923 | assert (finish_frag); | |
6924 | frag_var (rs_machine_dependent, | |
6925 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6926 | RELAX_MAYBE_UNREACHABLE, | |
6927 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6928 | xtensa_set_frag_assembly_state (frag_now); | |
6929 | frag_var (rs_machine_dependent, | |
6930 | 0, 0, | |
6931 | RELAX_MAYBE_DESIRE_ALIGN, | |
6932 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6933 | xtensa_set_frag_assembly_state (frag_now); | |
6934 | } | |
6935 | } | |
6936 | ||
6937 | /* Now, if the original opcode was a call... */ | |
6938 | if (do_align_targets () | |
6939 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
6940 | { | |
b08b5071 | 6941 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
6942 | frag_now->tc_frag_data.is_insn = TRUE; |
6943 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
6944 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6945 | xtensa_set_frag_assembly_state (frag_now); | |
6946 | } | |
6947 | ||
6948 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
6949 | { | |
6950 | frag_wane (frag_now); | |
6951 | frag_new (0); | |
6952 | xtensa_set_frag_assembly_state (frag_now); | |
6953 | } | |
6954 | } | |
6955 | ||
6956 | \f | |
7fa3d080 BW |
6957 | /* xtensa_end and helper functions. */ |
6958 | ||
6959 | static void xtensa_cleanup_align_frags (void); | |
6960 | static void xtensa_fix_target_frags (void); | |
6961 | static void xtensa_mark_narrow_branches (void); | |
6962 | static void xtensa_mark_zcl_first_insns (void); | |
6a7eedfe | 6963 | static void xtensa_mark_difference_of_two_symbols (void); |
7fa3d080 BW |
6964 | static void xtensa_fix_a0_b_retw_frags (void); |
6965 | static void xtensa_fix_b_j_loop_end_frags (void); | |
6966 | static void xtensa_fix_close_loop_end_frags (void); | |
6967 | static void xtensa_fix_short_loop_frags (void); | |
6968 | static void xtensa_sanity_check (void); | |
2caa7ca0 | 6969 | static void xtensa_add_config_info (void); |
7fa3d080 | 6970 | |
43cd72b9 | 6971 | void |
7fa3d080 | 6972 | xtensa_end (void) |
43cd72b9 BW |
6973 | { |
6974 | directive_balance (); | |
6975 | xtensa_flush_pending_output (); | |
6976 | ||
6977 | past_xtensa_end = TRUE; | |
6978 | ||
6979 | xtensa_move_literals (); | |
6980 | ||
6981 | xtensa_reorder_segments (); | |
6982 | xtensa_cleanup_align_frags (); | |
6983 | xtensa_fix_target_frags (); | |
6984 | if (workaround_a0_b_retw && has_a0_b_retw) | |
6985 | xtensa_fix_a0_b_retw_frags (); | |
6986 | if (workaround_b_j_loop_end) | |
6987 | xtensa_fix_b_j_loop_end_frags (); | |
6988 | ||
6989 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
6990 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
6991 | xtensa_fix_close_loop_end_frags (); | |
6992 | ||
6993 | if (workaround_short_loop && maybe_has_short_loop) | |
6994 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
6995 | if (align_targets) |
6996 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
6997 | xtensa_mark_zcl_first_insns (); |
6998 | ||
6999 | xtensa_sanity_check (); | |
2caa7ca0 BW |
7000 | |
7001 | xtensa_add_config_info (); | |
43cd72b9 BW |
7002 | } |
7003 | ||
7004 | ||
7005 | static void | |
7fa3d080 | 7006 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
7007 | { |
7008 | frchainS *frchP; | |
c9049d30 | 7009 | asection *s; |
43cd72b9 | 7010 | |
c9049d30 AM |
7011 | for (s = stdoutput->sections; s; s = s->next) |
7012 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7013 | { | |
7014 | fragS *fragP; | |
7015 | /* Walk over all of the fragments in a subsection. */ | |
7016 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7017 | { | |
7018 | if ((fragP->fr_type == rs_align | |
7019 | || fragP->fr_type == rs_align_code | |
7020 | || (fragP->fr_type == rs_machine_dependent | |
7021 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
7022 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
7023 | && fragP->fr_fix == 0) | |
7024 | { | |
7025 | fragS *next = fragP->fr_next; | |
7026 | ||
7027 | while (next | |
7028 | && next->fr_fix == 0 | |
7029 | && next->fr_type == rs_machine_dependent | |
7030 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7031 | { | |
7032 | frag_wane (next); | |
7033 | next = next->fr_next; | |
7034 | } | |
7035 | } | |
7036 | /* If we don't widen branch targets, then they | |
7037 | will be easier to align. */ | |
7038 | if (fragP->tc_frag_data.is_branch_target | |
7039 | && fragP->fr_opcode == fragP->fr_literal | |
7040 | && fragP->fr_type == rs_machine_dependent | |
7041 | && fragP->fr_subtype == RELAX_SLOTS | |
7042 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
7043 | frag_wane (fragP); | |
7044 | if (fragP->fr_type == rs_machine_dependent | |
7045 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
7046 | fragP->tc_frag_data.is_unreachable = TRUE; | |
7047 | } | |
7048 | } | |
43cd72b9 BW |
7049 | } |
7050 | ||
7051 | ||
7052 | /* Re-process all of the fragments looking to convert all of the | |
7053 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
7054 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 7055 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 7056 | |
43cd72b9 | 7057 | static void |
7fa3d080 | 7058 | xtensa_fix_target_frags (void) |
e0001a05 NC |
7059 | { |
7060 | frchainS *frchP; | |
c9049d30 | 7061 | asection *s; |
e0001a05 NC |
7062 | |
7063 | /* When this routine is called, all of the subsections are still intact | |
7064 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7065 | for (s = stdoutput->sections; s; s = s->next) |
7066 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7067 | { | |
7068 | fragS *fragP; | |
e0001a05 | 7069 | |
c9049d30 AM |
7070 | /* Walk over all of the fragments in a subsection. */ |
7071 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7072 | { | |
7073 | if (fragP->fr_type == rs_machine_dependent | |
7074 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7075 | { | |
7076 | if (next_frag_is_branch_target (fragP)) | |
7077 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
7078 | else | |
7079 | frag_wane (fragP); | |
7080 | } | |
7081 | } | |
7082 | } | |
e0001a05 NC |
7083 | } |
7084 | ||
7085 | ||
7fa3d080 BW |
7086 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7087 | ||
43cd72b9 | 7088 | static void |
7fa3d080 | 7089 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
7090 | { |
7091 | frchainS *frchP; | |
c9049d30 | 7092 | asection *s; |
43cd72b9 | 7093 | |
c9049d30 AM |
7094 | for (s = stdoutput->sections; s; s = s->next) |
7095 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7096 | { | |
7097 | fragS *fragP; | |
7098 | /* Walk over all of the fragments in a subsection. */ | |
7099 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7100 | { | |
7101 | if (fragP->fr_type == rs_machine_dependent | |
7102 | && fragP->fr_subtype == RELAX_SLOTS | |
7103 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
7104 | { | |
7105 | vliw_insn vinsn; | |
7106 | ||
7107 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
7108 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
7109 | ||
7110 | if (vinsn.num_slots == 1 | |
7111 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 7112 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
7113 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
7114 | && is_narrow_branch_guaranteed_in_range (fragP, | |
7115 | &vinsn.slots[0])) | |
7116 | { | |
7117 | fragP->fr_subtype = RELAX_SLOTS; | |
7118 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
7119 | fragP->tc_frag_data.is_aligning_branch = 1; | |
7120 | } | |
7121 | } | |
7122 | } | |
7123 | } | |
43cd72b9 BW |
7124 | } |
7125 | ||
7126 | ||
7127 | /* A branch is typically widened only when its target is out of | |
7128 | range. However, we would like to widen them to align a subsequent | |
7129 | branch target when possible. | |
7130 | ||
7131 | Because the branch relaxation code is so convoluted, the optimal solution | |
7132 | (combining the two cases) is difficult to get right in all circumstances. | |
7133 | We therefore go with an "almost as good" solution, where we only | |
7134 | use for alignment narrow branches that definitely will not expand to a | |
7135 | jump and a branch. These functions find and mark these cases. */ | |
7136 | ||
a67517f4 BW |
7137 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
7138 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
7139 | We start counting beginning with the frag after the 2-byte branch, so the | |
7140 | maximum offset is (4 - 2) + 63 = 65. */ | |
7141 | #define MAX_IMMED6 65 | |
43cd72b9 | 7142 | |
d77b99c9 | 7143 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 7144 | |
43cd72b9 | 7145 | static bfd_boolean |
7fa3d080 | 7146 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 BW |
7147 | { |
7148 | const expressionS *expr = &tinsn->tok[1]; | |
7149 | symbolS *symbolP = expr->X_add_symbol; | |
d77b99c9 | 7150 | offsetT max_distance = expr->X_add_number; |
e7da6241 BW |
7151 | fragS *target_frag; |
7152 | ||
7153 | if (expr->X_op != O_symbol) | |
7154 | return FALSE; | |
7155 | ||
7156 | target_frag = symbol_get_frag (symbolP); | |
7157 | ||
43cd72b9 BW |
7158 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
7159 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
7160 | return FALSE; | |
7161 | ||
7162 | /* The branch doesn't branch over it's own frag, | |
7163 | but over the subsequent ones. */ | |
7164 | fragP = fragP->fr_next; | |
7165 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
7166 | { | |
7167 | max_distance += unrelaxed_frag_max_size (fragP); | |
7168 | fragP = fragP->fr_next; | |
7169 | } | |
7170 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
7171 | return TRUE; | |
e0001a05 NC |
7172 | return FALSE; |
7173 | } | |
7174 | ||
7175 | ||
43cd72b9 | 7176 | static void |
7fa3d080 | 7177 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
7178 | { |
7179 | frchainS *frchP; | |
c9049d30 | 7180 | asection *s; |
43cd72b9 | 7181 | |
c9049d30 AM |
7182 | for (s = stdoutput->sections; s; s = s->next) |
7183 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7184 | { | |
7185 | fragS *fragP; | |
7186 | /* Walk over all of the fragments in a subsection. */ | |
7187 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7188 | { | |
7189 | if (fragP->fr_type == rs_machine_dependent | |
7190 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
7191 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
7192 | { | |
7193 | /* Find the loop frag. */ | |
7194 | fragS *targ_frag = next_non_empty_frag (fragP); | |
7195 | /* Find the first insn frag. */ | |
7196 | targ_frag = next_non_empty_frag (targ_frag); | |
7197 | ||
7198 | /* Of course, sometimes (mostly for toy test cases) a | |
7199 | zero-cost loop instruction is the last in a section. */ | |
7200 | if (targ_frag) | |
7201 | { | |
7202 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
7203 | /* Do not widen a frag that is the first instruction of a | |
7204 | zero-cost loop. It makes that loop harder to align. */ | |
7205 | if (targ_frag->fr_type == rs_machine_dependent | |
7206 | && targ_frag->fr_subtype == RELAX_SLOTS | |
7207 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
7208 | == RELAX_NARROW)) | |
7209 | { | |
7210 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
7211 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
7212 | else | |
7213 | { | |
7214 | frag_wane (targ_frag); | |
7215 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
7216 | } | |
7217 | } | |
7218 | } | |
7219 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
7220 | frag_wane (fragP); | |
7221 | } | |
7222 | } | |
7223 | } | |
43cd72b9 BW |
7224 | } |
7225 | ||
7226 | ||
6a7eedfe BW |
7227 | /* Some difference-of-symbols expressions make it out to the linker. Some |
7228 | don't. If one does, then the linker can optimize between the two labels. | |
7229 | If it doesn't, then the linker shouldn't. */ | |
7230 | ||
7231 | static void | |
7232 | xtensa_mark_difference_of_two_symbols (void) | |
7233 | { | |
7234 | symbolS *expr_sym; | |
7235 | ||
7236 | for (expr_sym = expr_symbols; expr_sym; | |
7237 | expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) | |
7238 | { | |
7239 | expressionS *expr = symbol_get_value_expression (expr_sym); | |
7240 | ||
7241 | if (expr->X_op == O_subtract) | |
7242 | { | |
7243 | symbolS *left = expr->X_add_symbol; | |
7244 | symbolS *right = expr->X_op_symbol; | |
7245 | ||
7246 | /* Difference of two symbols not in the same section | |
7247 | are handled with relocations in the linker. */ | |
7248 | if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) | |
7249 | { | |
7250 | fragS *start; | |
7251 | fragS *end; | |
7252 | ||
7253 | if (symbol_get_frag (left)->fr_address | |
7254 | <= symbol_get_frag (right)->fr_address) | |
7255 | { | |
7256 | start = symbol_get_frag (left); | |
7257 | end = symbol_get_frag (right); | |
7258 | } | |
7259 | else | |
7260 | { | |
7261 | start = symbol_get_frag (right); | |
7262 | end = symbol_get_frag (left); | |
7263 | } | |
7264 | do | |
7265 | { | |
7266 | start->tc_frag_data.is_no_transform = 1; | |
7267 | start = start->fr_next; | |
7268 | } | |
7269 | while (start && start->fr_address < end->fr_address); | |
7270 | } | |
7271 | } | |
7272 | } | |
7273 | } | |
7274 | ||
7275 | ||
e0001a05 NC |
7276 | /* Re-process all of the fragments looking to convert all of the |
7277 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
7278 | conditional branch or a retw/retw.n, convert this frag to one that | |
7279 | will generate a NOP. In any case close it off with a .fill 0. */ | |
7280 | ||
7fa3d080 BW |
7281 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
7282 | ||
e0001a05 | 7283 | static void |
7fa3d080 | 7284 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
7285 | { |
7286 | frchainS *frchP; | |
c9049d30 | 7287 | asection *s; |
e0001a05 NC |
7288 | |
7289 | /* When this routine is called, all of the subsections are still intact | |
7290 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7291 | for (s = stdoutput->sections; s; s = s->next) |
7292 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7293 | { | |
7294 | fragS *fragP; | |
e0001a05 | 7295 | |
c9049d30 AM |
7296 | /* Walk over all of the fragments in a subsection. */ |
7297 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7298 | { | |
7299 | if (fragP->fr_type == rs_machine_dependent | |
7300 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
7301 | { | |
7302 | if (next_instrs_are_b_retw (fragP)) | |
7303 | { | |
7304 | if (fragP->tc_frag_data.is_no_transform) | |
7305 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
7306 | else | |
7307 | relax_frag_add_nop (fragP); | |
7308 | } | |
7309 | frag_wane (fragP); | |
7310 | } | |
7311 | } | |
7312 | } | |
e0001a05 NC |
7313 | } |
7314 | ||
7315 | ||
7fa3d080 BW |
7316 | static bfd_boolean |
7317 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
7318 | { |
7319 | xtensa_opcode opcode; | |
43cd72b9 | 7320 | xtensa_format fmt; |
e0001a05 NC |
7321 | const fragS *next_fragP = next_non_empty_frag (fragP); |
7322 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 7323 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
7324 | xtensa_isa isa = xtensa_default_isa; |
7325 | int offset = 0; | |
43cd72b9 BW |
7326 | int slot; |
7327 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
7328 | |
7329 | if (!insnbuf) | |
43cd72b9 BW |
7330 | { |
7331 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7332 | slotbuf = xtensa_insnbuf_alloc (isa); | |
7333 | } | |
e0001a05 NC |
7334 | |
7335 | if (next_fragP == NULL) | |
7336 | return FALSE; | |
7337 | ||
7338 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
7339 | xtensa_insnbuf_from_chars |
7340 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7341 | fmt = xtensa_format_decode (isa, insnbuf); |
7342 | if (fmt == XTENSA_UNDEFINED) | |
7343 | return FALSE; | |
7344 | ||
7345 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
7346 | { | |
7347 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
7348 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
7349 | ||
7350 | branch_seen = (branch_seen | |
7351 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
7352 | } | |
e0001a05 | 7353 | |
43cd72b9 | 7354 | if (!branch_seen) |
e0001a05 NC |
7355 | return FALSE; |
7356 | ||
43cd72b9 | 7357 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7358 | if (offset == next_fragP->fr_fix) |
7359 | { | |
7360 | next_fragP = next_non_empty_frag (next_fragP); | |
7361 | offset = 0; | |
7362 | } | |
43cd72b9 | 7363 | |
e0001a05 NC |
7364 | if (next_fragP == NULL) |
7365 | return FALSE; | |
7366 | ||
7367 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
7368 | xtensa_insnbuf_from_chars |
7369 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7370 | fmt = xtensa_format_decode (isa, insnbuf); |
7371 | ||
7372 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
7373 | have no problems. */ | |
7374 | if (fmt == XTENSA_UNDEFINED | |
7375 | || xtensa_format_num_slots (isa, fmt) != 1) | |
7376 | return FALSE; | |
7377 | ||
7378 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
7379 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 7380 | |
b08b5071 | 7381 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 7382 | return TRUE; |
43cd72b9 | 7383 | |
e0001a05 NC |
7384 | return FALSE; |
7385 | } | |
7386 | ||
7387 | ||
7388 | /* Re-process all of the fragments looking to convert all of the | |
7389 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
7390 | loop end label, convert this frag to one that will generate a NOP. | |
7391 | In any case close it off with a .fill 0. */ | |
7392 | ||
7fa3d080 BW |
7393 | static bfd_boolean next_instr_is_loop_end (fragS *); |
7394 | ||
e0001a05 | 7395 | static void |
7fa3d080 | 7396 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
7397 | { |
7398 | frchainS *frchP; | |
c9049d30 | 7399 | asection *s; |
e0001a05 NC |
7400 | |
7401 | /* When this routine is called, all of the subsections are still intact | |
7402 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7403 | for (s = stdoutput->sections; s; s = s->next) |
7404 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7405 | { | |
7406 | fragS *fragP; | |
e0001a05 | 7407 | |
c9049d30 AM |
7408 | /* Walk over all of the fragments in a subsection. */ |
7409 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7410 | { | |
7411 | if (fragP->fr_type == rs_machine_dependent | |
7412 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
7413 | { | |
7414 | if (next_instr_is_loop_end (fragP)) | |
7415 | { | |
7416 | if (fragP->tc_frag_data.is_no_transform) | |
7417 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
7418 | else | |
7419 | relax_frag_add_nop (fragP); | |
7420 | } | |
7421 | frag_wane (fragP); | |
7422 | } | |
7423 | } | |
7424 | } | |
e0001a05 NC |
7425 | } |
7426 | ||
7427 | ||
7fa3d080 BW |
7428 | static bfd_boolean |
7429 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
7430 | { |
7431 | const fragS *next_fragP; | |
7432 | ||
7433 | if (next_frag_is_loop_target (fragP)) | |
7434 | return FALSE; | |
7435 | ||
7436 | next_fragP = next_non_empty_frag (fragP); | |
7437 | if (next_fragP == NULL) | |
7438 | return FALSE; | |
7439 | ||
7440 | if (!next_frag_is_loop_target (next_fragP)) | |
7441 | return FALSE; | |
7442 | ||
7443 | /* If the size is >= 3 then there is more than one instruction here. | |
7444 | The hardware bug will not fire. */ | |
7445 | if (next_fragP->fr_fix > 3) | |
7446 | return FALSE; | |
7447 | ||
7448 | return TRUE; | |
7449 | } | |
7450 | ||
7451 | ||
7452 | /* Re-process all of the fragments looking to convert all of the | |
7453 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
7454 | not MY loop's loop end within 12 bytes, add enough nops here to | |
7455 | make it at least 12 bytes away. In any case close it off with a | |
7456 | .fill 0. */ | |
7457 | ||
d77b99c9 | 7458 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 7459 | (fragS *, fragS *, offsetT); |
7fa3d080 | 7460 | |
e0001a05 | 7461 | static void |
7fa3d080 | 7462 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
7463 | { |
7464 | frchainS *frchP; | |
c9049d30 | 7465 | asection *s; |
e0001a05 NC |
7466 | |
7467 | /* When this routine is called, all of the subsections are still intact | |
7468 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7469 | for (s = stdoutput->sections; s; s = s->next) |
7470 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7471 | { | |
7472 | fragS *fragP; | |
e0001a05 | 7473 | |
c9049d30 | 7474 | fragS *current_target = NULL; |
e0001a05 | 7475 | |
c9049d30 AM |
7476 | /* Walk over all of the fragments in a subsection. */ |
7477 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7478 | { | |
7479 | if (fragP->fr_type == rs_machine_dependent | |
7480 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7481 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 7482 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 7483 | |
c9049d30 AM |
7484 | if (current_target |
7485 | && fragP->fr_type == rs_machine_dependent | |
7486 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
7487 | { | |
7488 | offsetT min_bytes; | |
7489 | int bytes_added = 0; | |
e0001a05 NC |
7490 | |
7491 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
7492 | /* Max out at 12. */ |
7493 | min_bytes = min_bytes_to_other_loop_end | |
7494 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
7495 | ||
7496 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
7497 | { | |
7498 | if (fragP->tc_frag_data.is_no_transform) | |
7499 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
7500 | else | |
7501 | { | |
7502 | while (min_bytes + bytes_added | |
7503 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
7504 | { | |
7505 | int length = 3; | |
7506 | ||
7507 | if (fragP->fr_var < length) | |
7508 | as_fatal (_("fr_var %lu < length %d"), | |
7509 | (long) fragP->fr_var, length); | |
7510 | else | |
7511 | { | |
7512 | assemble_nop (length, | |
7513 | fragP->fr_literal + fragP->fr_fix); | |
7514 | fragP->fr_fix += length; | |
7515 | fragP->fr_var -= length; | |
7516 | } | |
7517 | bytes_added += length; | |
7518 | } | |
7519 | } | |
7520 | } | |
7521 | frag_wane (fragP); | |
7522 | } | |
7523 | assert (fragP->fr_type != rs_machine_dependent | |
7524 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); | |
7525 | } | |
7526 | } | |
e0001a05 NC |
7527 | } |
7528 | ||
7529 | ||
d77b99c9 | 7530 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 7531 | |
d77b99c9 | 7532 | static offsetT |
7fa3d080 BW |
7533 | min_bytes_to_other_loop_end (fragS *fragP, |
7534 | fragS *current_target, | |
d77b99c9 | 7535 | offsetT max_size) |
e0001a05 | 7536 | { |
d77b99c9 | 7537 | offsetT offset = 0; |
e0001a05 NC |
7538 | fragS *current_fragP; |
7539 | ||
7540 | for (current_fragP = fragP; | |
7541 | current_fragP; | |
7542 | current_fragP = current_fragP->fr_next) | |
7543 | { | |
7544 | if (current_fragP->tc_frag_data.is_loop_target | |
7545 | && current_fragP != current_target) | |
05d58145 | 7546 | return offset; |
e0001a05 NC |
7547 | |
7548 | offset += unrelaxed_frag_min_size (current_fragP); | |
7549 | ||
05d58145 | 7550 | if (offset >= max_size) |
e0001a05 NC |
7551 | return max_size; |
7552 | } | |
7553 | return max_size; | |
7554 | } | |
7555 | ||
7556 | ||
d77b99c9 | 7557 | static offsetT |
7fa3d080 | 7558 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 7559 | { |
d77b99c9 | 7560 | offsetT size = fragP->fr_fix; |
e0001a05 | 7561 | |
d77b99c9 | 7562 | /* Add fill size. */ |
e0001a05 NC |
7563 | if (fragP->fr_type == rs_fill) |
7564 | size += fragP->fr_offset; | |
7565 | ||
7566 | return size; | |
7567 | } | |
7568 | ||
7569 | ||
d77b99c9 | 7570 | static offsetT |
7fa3d080 | 7571 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 7572 | { |
d77b99c9 | 7573 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
7574 | switch (fragP->fr_type) |
7575 | { | |
7576 | case 0: | |
c138bc38 | 7577 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
7578 | end up with type 0. */ |
7579 | break; | |
7580 | case rs_fill: | |
7581 | case rs_org: | |
7582 | case rs_space: | |
7583 | size += fragP->fr_offset; | |
7584 | break; | |
7585 | case rs_align: | |
7586 | case rs_align_code: | |
7587 | case rs_align_test: | |
7588 | case rs_leb128: | |
7589 | case rs_cfa: | |
7590 | case rs_dwarf2dbg: | |
7591 | /* No further adjustments needed. */ | |
7592 | break; | |
7593 | case rs_machine_dependent: | |
7594 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
7595 | size += fragP->fr_var; | |
7596 | break; | |
7597 | default: | |
7598 | /* We had darn well better know how big it is. */ | |
7599 | assert (0); | |
7600 | break; | |
7601 | } | |
7602 | ||
7603 | return size; | |
7604 | } | |
7605 | ||
7606 | ||
e0001a05 NC |
7607 | /* Re-process all of the fragments looking to convert all |
7608 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
7609 | ||
7610 | A) | |
7611 | 1) the instruction size count to the loop end label | |
7612 | is too short (<= 2 instructions), | |
7613 | 2) loop has a jump or branch in it | |
7614 | ||
7615 | or B) | |
43cd72b9 | 7616 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
7617 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
7618 | 3) the instruction size count to the loop end label is too short | |
7619 | (<= 2 instructions) | |
7620 | then convert this frag (and maybe the next one) to generate a NOP. | |
7621 | In any case close it off with a .fill 0. */ | |
7622 | ||
d77b99c9 | 7623 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
7624 | static bfd_boolean branch_before_loop_end (fragS *); |
7625 | ||
e0001a05 | 7626 | static void |
7fa3d080 | 7627 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
7628 | { |
7629 | frchainS *frchP; | |
c9049d30 | 7630 | asection *s; |
e0001a05 NC |
7631 | |
7632 | /* When this routine is called, all of the subsections are still intact | |
7633 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7634 | for (s = stdoutput->sections; s; s = s->next) |
7635 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7636 | { | |
7637 | fragS *fragP; | |
7638 | fragS *current_target = NULL; | |
7639 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; | |
e0001a05 | 7640 | |
c9049d30 AM |
7641 | /* Walk over all of the fragments in a subsection. */ |
7642 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7643 | { | |
7644 | if (fragP->fr_type == rs_machine_dependent | |
7645 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7646 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
7647 | { | |
7648 | TInsn t_insn; | |
7649 | fragS *loop_frag = next_non_empty_frag (fragP); | |
7650 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
7651 | current_target = symbol_get_frag (fragP->fr_symbol); | |
7652 | current_opcode = t_insn.opcode; | |
7653 | assert (xtensa_opcode_is_loop (xtensa_default_isa, | |
64b607e6 | 7654 | current_opcode) == 1); |
c9049d30 | 7655 | } |
e0001a05 | 7656 | |
c9049d30 AM |
7657 | if (fragP->fr_type == rs_machine_dependent |
7658 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7659 | { | |
7660 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 | |
7661 | && (branch_before_loop_end (fragP->fr_next) | |
7662 | || (workaround_all_short_loops | |
7663 | && current_opcode != XTENSA_UNDEFINED | |
7664 | && current_opcode != xtensa_loop_opcode))) | |
7665 | { | |
7666 | if (fragP->tc_frag_data.is_no_transform) | |
7667 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
7668 | else | |
7669 | relax_frag_add_nop (fragP); | |
7670 | } | |
7671 | frag_wane (fragP); | |
7672 | } | |
7673 | } | |
7674 | } | |
e0001a05 NC |
7675 | } |
7676 | ||
7677 | ||
d77b99c9 | 7678 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 7679 | |
d77b99c9 | 7680 | static int |
7fa3d080 BW |
7681 | count_insns_to_loop_end (fragS *base_fragP, |
7682 | bfd_boolean count_relax_add, | |
d77b99c9 | 7683 | int max_count) |
e0001a05 NC |
7684 | { |
7685 | fragS *fragP = NULL; | |
d77b99c9 | 7686 | int insn_count = 0; |
e0001a05 NC |
7687 | |
7688 | fragP = base_fragP; | |
7689 | ||
7690 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
7691 | { | |
7692 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
7693 | if (insn_count >= max_count) | |
7694 | return max_count; | |
7695 | ||
7696 | if (count_relax_add) | |
7697 | { | |
7698 | if (fragP->fr_type == rs_machine_dependent | |
7699 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7700 | { | |
7701 | /* In order to add the appropriate number of | |
7702 | NOPs, we count an instruction for downstream | |
7703 | occurrences. */ | |
7704 | insn_count++; | |
7705 | if (insn_count >= max_count) | |
7706 | return max_count; | |
7707 | } | |
7708 | } | |
7709 | } | |
7710 | return insn_count; | |
7711 | } | |
7712 | ||
7713 | ||
d77b99c9 | 7714 | static int |
7fa3d080 | 7715 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 7716 | { |
43cd72b9 BW |
7717 | xtensa_isa isa = xtensa_default_isa; |
7718 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 7719 | int insn_count = 0; |
e0001a05 NC |
7720 | int offset = 0; |
7721 | ||
7722 | if (!fragP->tc_frag_data.is_insn) | |
7723 | return insn_count; | |
7724 | ||
43cd72b9 BW |
7725 | if (!insnbuf) |
7726 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7727 | ||
e0001a05 NC |
7728 | /* Decode the fixed instructions. */ |
7729 | while (offset < fragP->fr_fix) | |
7730 | { | |
43cd72b9 BW |
7731 | xtensa_format fmt; |
7732 | ||
d77b99c9 BW |
7733 | xtensa_insnbuf_from_chars |
7734 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7735 | fmt = xtensa_format_decode (isa, insnbuf); |
7736 | ||
7737 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
7738 | { |
7739 | as_fatal (_("undecodable instruction in instruction frag")); | |
7740 | return insn_count; | |
7741 | } | |
43cd72b9 | 7742 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7743 | insn_count++; |
7744 | } | |
7745 | ||
7746 | return insn_count; | |
7747 | } | |
7748 | ||
7749 | ||
7fa3d080 BW |
7750 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
7751 | ||
43cd72b9 | 7752 | static bfd_boolean |
7fa3d080 | 7753 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
7754 | { |
7755 | fragS *fragP; | |
7756 | ||
7757 | for (fragP = base_fragP; | |
7758 | fragP && !fragP->tc_frag_data.is_loop_target; | |
7759 | fragP = fragP->fr_next) | |
7760 | { | |
7761 | if (unrelaxed_frag_has_b_j (fragP)) | |
7762 | return TRUE; | |
7763 | } | |
7764 | return FALSE; | |
7765 | } | |
7766 | ||
7767 | ||
43cd72b9 | 7768 | static bfd_boolean |
7fa3d080 | 7769 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 7770 | { |
43cd72b9 BW |
7771 | static xtensa_insnbuf insnbuf = NULL; |
7772 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
7773 | int offset = 0; |
7774 | ||
7775 | if (!fragP->tc_frag_data.is_insn) | |
7776 | return FALSE; | |
7777 | ||
43cd72b9 BW |
7778 | if (!insnbuf) |
7779 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7780 | ||
e0001a05 NC |
7781 | /* Decode the fixed instructions. */ |
7782 | while (offset < fragP->fr_fix) | |
7783 | { | |
43cd72b9 BW |
7784 | xtensa_format fmt; |
7785 | int slot; | |
7786 | ||
d77b99c9 BW |
7787 | xtensa_insnbuf_from_chars |
7788 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7789 | fmt = xtensa_format_decode (isa, insnbuf); |
7790 | if (fmt == XTENSA_UNDEFINED) | |
7791 | return FALSE; | |
7792 | ||
7793 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 7794 | { |
43cd72b9 BW |
7795 | xtensa_opcode opcode = |
7796 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
7797 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
7798 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
7799 | return TRUE; | |
e0001a05 | 7800 | } |
43cd72b9 | 7801 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7802 | } |
7803 | return FALSE; | |
7804 | } | |
7805 | ||
7806 | ||
7807 | /* Checks to be made after initial assembly but before relaxation. */ | |
7808 | ||
7fa3d080 BW |
7809 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
7810 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
7811 | ||
e0001a05 | 7812 | static void |
7fa3d080 | 7813 | xtensa_sanity_check (void) |
e0001a05 NC |
7814 | { |
7815 | char *file_name; | |
d77b99c9 | 7816 | unsigned line; |
e0001a05 | 7817 | frchainS *frchP; |
c9049d30 | 7818 | asection *s; |
e0001a05 NC |
7819 | |
7820 | as_where (&file_name, &line); | |
c9049d30 AM |
7821 | for (s = stdoutput->sections; s; s = s->next) |
7822 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7823 | { | |
7824 | fragS *fragP; | |
e0001a05 | 7825 | |
c9049d30 AM |
7826 | /* Walk over all of the fragments in a subsection. */ |
7827 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7828 | { | |
c9049d30 | 7829 | if (fragP->fr_type == rs_machine_dependent |
a7284bf1 BW |
7830 | && fragP->fr_subtype == RELAX_SLOTS |
7831 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
c9049d30 AM |
7832 | { |
7833 | static xtensa_insnbuf insnbuf = NULL; | |
7834 | TInsn t_insn; | |
7835 | ||
7836 | if (fragP->fr_opcode != NULL) | |
7837 | { | |
7838 | if (!insnbuf) | |
7839 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7840 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
7841 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
7842 | ||
7843 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
7844 | t_insn.opcode) == 1) | |
7845 | { | |
7846 | if (is_empty_loop (&t_insn, fragP)) | |
7847 | { | |
7848 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7849 | as_bad (_("invalid empty loop")); | |
7850 | } | |
7851 | if (!is_local_forward_loop (&t_insn, fragP)) | |
7852 | { | |
7853 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7854 | as_bad (_("loop target does not follow " | |
7855 | "loop instruction in section")); | |
7856 | } | |
7857 | } | |
7858 | } | |
7859 | } | |
7860 | } | |
7861 | } | |
e0001a05 NC |
7862 | new_logical_line (file_name, line); |
7863 | } | |
7864 | ||
7865 | ||
7866 | #define LOOP_IMMED_OPN 1 | |
7867 | ||
43cd72b9 | 7868 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 7869 | |
7fa3d080 BW |
7870 | static bfd_boolean |
7871 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7872 | { |
7873 | const expressionS *expr; | |
7874 | symbolS *symbolP; | |
7875 | fragS *next_fragP; | |
7876 | ||
7877 | if (insn->insn_type != ITYPE_INSN) | |
7878 | return FALSE; | |
7879 | ||
43cd72b9 | 7880 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7881 | return FALSE; |
7882 | ||
7883 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7884 | return FALSE; | |
7885 | ||
7886 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7887 | ||
7888 | if (expr->X_op != O_symbol) | |
7889 | return FALSE; | |
7890 | ||
7891 | symbolP = expr->X_add_symbol; | |
7892 | if (!symbolP) | |
7893 | return FALSE; | |
7894 | ||
7895 | if (symbol_get_frag (symbolP) == NULL) | |
7896 | return FALSE; | |
7897 | ||
7898 | if (S_GET_VALUE (symbolP) != 0) | |
7899 | return FALSE; | |
7900 | ||
7901 | /* Walk through the zero-size fragments from this one. If we find | |
7902 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 7903 | |
e0001a05 NC |
7904 | for (next_fragP = fragP->fr_next; |
7905 | next_fragP != NULL; | |
7906 | next_fragP = next_fragP->fr_next) | |
7907 | { | |
7908 | if (next_fragP == symbol_get_frag (symbolP)) | |
7909 | return TRUE; | |
7910 | if (next_fragP->fr_fix != 0) | |
7911 | return FALSE; | |
7912 | } | |
7913 | return FALSE; | |
7914 | } | |
7915 | ||
7916 | ||
7fa3d080 BW |
7917 | static bfd_boolean |
7918 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7919 | { |
7920 | const expressionS *expr; | |
7921 | symbolS *symbolP; | |
7922 | fragS *next_fragP; | |
7923 | ||
7924 | if (insn->insn_type != ITYPE_INSN) | |
7925 | return FALSE; | |
7926 | ||
64b607e6 | 7927 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7928 | return FALSE; |
7929 | ||
7930 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7931 | return FALSE; | |
7932 | ||
7933 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7934 | ||
7935 | if (expr->X_op != O_symbol) | |
7936 | return FALSE; | |
7937 | ||
7938 | symbolP = expr->X_add_symbol; | |
7939 | if (!symbolP) | |
7940 | return FALSE; | |
7941 | ||
7942 | if (symbol_get_frag (symbolP) == NULL) | |
7943 | return FALSE; | |
7944 | ||
7945 | /* Walk through fragments until we find the target. | |
7946 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 7947 | |
e0001a05 NC |
7948 | for (next_fragP = fragP->fr_next; |
7949 | next_fragP != NULL; | |
7950 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
7951 | { |
7952 | if (next_fragP == symbol_get_frag (symbolP)) | |
7953 | return TRUE; | |
7954 | } | |
e0001a05 NC |
7955 | |
7956 | return FALSE; | |
7957 | } | |
7958 | ||
2caa7ca0 BW |
7959 | |
7960 | #define XTINFO_NAME "Xtensa_Info" | |
7961 | #define XTINFO_NAMESZ 12 | |
7962 | #define XTINFO_TYPE 1 | |
7963 | ||
7964 | static void | |
7965 | xtensa_add_config_info (void) | |
7966 | { | |
7967 | asection *info_sec; | |
7968 | char *data, *p; | |
7969 | int sz; | |
7970 | ||
7971 | info_sec = subseg_new (".xtensa.info", 0); | |
7972 | bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY); | |
7973 | ||
7974 | data = xmalloc (100); | |
7975 | sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", | |
7976 | XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI); | |
7977 | sz = strlen (data) + 1; | |
7978 | ||
7979 | /* Add enough null terminators to pad to a word boundary. */ | |
7980 | do | |
7981 | data[sz++] = 0; | |
7982 | while ((sz & 3) != 0); | |
7983 | ||
7984 | /* Follow the standard note section layout: | |
7985 | First write the length of the name string. */ | |
7986 | p = frag_more (4); | |
7987 | md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); | |
7988 | ||
7989 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
7990 | p = frag_more (4); | |
7991 | md_number_to_chars (p, (valueT) sz, 4); | |
7992 | ||
7993 | /* Write the note type. */ | |
7994 | p = frag_more (4); | |
7995 | md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); | |
7996 | ||
7997 | /* Write the name field. */ | |
7998 | p = frag_more (XTINFO_NAMESZ); | |
7999 | memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); | |
8000 | ||
8001 | /* Finally, write the descriptor. */ | |
8002 | p = frag_more (sz); | |
8003 | memcpy (p, data, sz); | |
8004 | ||
8005 | free (data); | |
8006 | } | |
8007 | ||
e0001a05 NC |
8008 | \f |
8009 | /* Alignment Functions. */ | |
8010 | ||
d77b99c9 BW |
8011 | static int |
8012 | get_text_align_power (unsigned target_size) | |
e0001a05 | 8013 | { |
03aaa593 BW |
8014 | if (target_size <= 4) |
8015 | return 2; | |
8016 | assert (target_size == 8); | |
8017 | return 3; | |
e0001a05 NC |
8018 | } |
8019 | ||
8020 | ||
d77b99c9 | 8021 | static int |
7fa3d080 BW |
8022 | get_text_align_max_fill_size (int align_pow, |
8023 | bfd_boolean use_nops, | |
8024 | bfd_boolean use_no_density) | |
e0001a05 NC |
8025 | { |
8026 | if (!use_nops) | |
8027 | return (1 << align_pow); | |
8028 | if (use_no_density) | |
8029 | return 3 * (1 << align_pow); | |
8030 | ||
8031 | return 1 + (1 << align_pow); | |
8032 | } | |
8033 | ||
8034 | ||
d77b99c9 BW |
8035 | /* Calculate the minimum bytes of fill needed at "address" to align a |
8036 | target instruction of size "target_size" so that it does not cross a | |
8037 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
8038 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
8039 | be filled by NOP instructions. */ | |
e0001a05 | 8040 | |
d77b99c9 | 8041 | static int |
7fa3d080 BW |
8042 | get_text_align_fill_size (addressT address, |
8043 | int align_pow, | |
8044 | int target_size, | |
8045 | bfd_boolean use_nops, | |
8046 | bfd_boolean use_no_density) | |
e0001a05 | 8047 | { |
d77b99c9 BW |
8048 | addressT alignment, fill, fill_limit, fill_step; |
8049 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 8050 | |
d77b99c9 BW |
8051 | alignment = (1 << align_pow); |
8052 | assert (target_size > 0 && alignment >= (addressT) target_size); | |
c138bc38 | 8053 | |
e0001a05 NC |
8054 | if (!use_nops) |
8055 | { | |
d77b99c9 BW |
8056 | fill_limit = alignment; |
8057 | fill_step = 1; | |
e0001a05 | 8058 | } |
d77b99c9 | 8059 | else if (!use_no_density) |
e0001a05 | 8060 | { |
d77b99c9 BW |
8061 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
8062 | fill_limit = alignment * 2; | |
8063 | fill_step = 1; | |
8064 | skip_one = TRUE; | |
e0001a05 NC |
8065 | } |
8066 | else | |
8067 | { | |
d77b99c9 BW |
8068 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
8069 | fill_limit = alignment * 3; | |
8070 | fill_step = 3; | |
8071 | } | |
e0001a05 | 8072 | |
d77b99c9 BW |
8073 | /* Try all fill sizes until finding one that works. */ |
8074 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
8075 | { | |
8076 | if (skip_one && fill == 1) | |
8077 | continue; | |
8078 | if ((address + fill) >> align_pow | |
8079 | == (address + fill + target_size - 1) >> align_pow) | |
8080 | return fill; | |
e0001a05 NC |
8081 | } |
8082 | assert (0); | |
8083 | return 0; | |
8084 | } | |
8085 | ||
8086 | ||
664df4e4 BW |
8087 | static int |
8088 | branch_align_power (segT sec) | |
8089 | { | |
8090 | /* If the Xtensa processor has a fetch width of 8 bytes, and the section | |
8091 | is aligned to at least an 8-byte boundary, then a branch target need | |
8092 | only fit within an 8-byte aligned block of memory to avoid a stall. | |
8093 | Otherwise, try to fit branch targets within 4-byte aligned blocks | |
8094 | (which may be insufficient, e.g., if the section has no alignment, but | |
8095 | it's good enough). */ | |
8096 | if (xtensa_fetch_width == 8) | |
8097 | { | |
8098 | if (get_recorded_alignment (sec) >= 3) | |
8099 | return 3; | |
8100 | } | |
8101 | else | |
8102 | assert (xtensa_fetch_width == 4); | |
8103 | ||
8104 | return 2; | |
8105 | } | |
8106 | ||
8107 | ||
e0001a05 NC |
8108 | /* This will assert if it is not possible. */ |
8109 | ||
d77b99c9 BW |
8110 | static int |
8111 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 8112 | { |
d77b99c9 BW |
8113 | int count = 0; |
8114 | ||
e0001a05 NC |
8115 | if (use_no_density) |
8116 | { | |
8117 | assert (fill_size % 3 == 0); | |
8118 | return (fill_size / 3); | |
8119 | } | |
8120 | ||
8121 | assert (fill_size != 1); /* Bad argument. */ | |
8122 | ||
8123 | while (fill_size > 1) | |
8124 | { | |
d77b99c9 | 8125 | int insn_size = 3; |
e0001a05 NC |
8126 | if (fill_size == 2 || fill_size == 4) |
8127 | insn_size = 2; | |
8128 | fill_size -= insn_size; | |
8129 | count++; | |
8130 | } | |
8131 | assert (fill_size != 1); /* Bad algorithm. */ | |
8132 | return count; | |
8133 | } | |
8134 | ||
8135 | ||
d77b99c9 BW |
8136 | static int |
8137 | get_text_align_nth_nop_size (offsetT fill_size, | |
8138 | int n, | |
7fa3d080 | 8139 | bfd_boolean use_no_density) |
e0001a05 | 8140 | { |
d77b99c9 | 8141 | int count = 0; |
e0001a05 NC |
8142 | |
8143 | if (use_no_density) | |
8144 | return 3; | |
8145 | ||
d77b99c9 BW |
8146 | assert (fill_size != 1); /* Bad argument. */ |
8147 | ||
e0001a05 NC |
8148 | while (fill_size > 1) |
8149 | { | |
d77b99c9 | 8150 | int insn_size = 3; |
e0001a05 NC |
8151 | if (fill_size == 2 || fill_size == 4) |
8152 | insn_size = 2; | |
8153 | fill_size -= insn_size; | |
8154 | count++; | |
8155 | if (n + 1 == count) | |
8156 | return insn_size; | |
8157 | } | |
8158 | assert (0); | |
8159 | return 0; | |
8160 | } | |
8161 | ||
8162 | ||
8163 | /* For the given fragment, find the appropriate address | |
8164 | for it to begin at if we are using NOPs to align it. */ | |
8165 | ||
8166 | static addressT | |
7fa3d080 | 8167 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 8168 | { |
43cd72b9 BW |
8169 | /* The rule is: get next fragment's FIRST instruction. Find |
8170 | the smallest number of bytes that need to be added to | |
8171 | ensure that the next fragment's FIRST instruction will fit | |
8172 | in a single word. | |
c138bc38 | 8173 | |
43cd72b9 BW |
8174 | E.G., 2 bytes : 0, 1, 2 mod 4 |
8175 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 8176 | |
43cd72b9 BW |
8177 | If the FIRST instruction MIGHT be relaxed, |
8178 | assume that it will become a 3-byte instruction. | |
c138bc38 | 8179 | |
43cd72b9 BW |
8180 | Note again here that LOOP instructions are not bundleable, |
8181 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 8182 | |
d77b99c9 | 8183 | int fill_size = 0; |
43cd72b9 BW |
8184 | int first_insn_size; |
8185 | int loop_insn_size; | |
8186 | addressT pre_opcode_bytes; | |
d77b99c9 | 8187 | int align_power; |
43cd72b9 BW |
8188 | fragS *first_insn; |
8189 | xtensa_opcode opcode; | |
8190 | bfd_boolean is_loop; | |
e0001a05 | 8191 | |
43cd72b9 BW |
8192 | assert (fragP->fr_type == rs_machine_dependent); |
8193 | assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 8194 | |
43cd72b9 BW |
8195 | /* Find the loop frag. */ |
8196 | first_insn = next_non_empty_frag (fragP); | |
8197 | /* Now find the first insn frag. */ | |
8198 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 8199 | |
43cd72b9 BW |
8200 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
8201 | assert (is_loop); | |
8202 | loop_insn_size = xg_get_single_size (opcode); | |
e0001a05 | 8203 | |
43cd72b9 BW |
8204 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
8205 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 8206 | |
43cd72b9 BW |
8207 | /* For loops, the alignment depends on the size of the |
8208 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 8209 | |
43cd72b9 | 8210 | if (first_insn == NULL) |
03aaa593 BW |
8211 | first_insn_size = xtensa_fetch_width; |
8212 | else | |
8213 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 8214 | |
43cd72b9 | 8215 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
8216 | align_power = get_text_align_power (first_insn_size); |
8217 | record_alignment (now_seg, align_power); | |
c138bc38 | 8218 | |
43cd72b9 | 8219 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
8220 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
8221 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
8222 | |
8223 | return address + fill_size; | |
8224 | } | |
8225 | ||
8226 | ||
43cd72b9 BW |
8227 | /* 3 mechanisms for relaxing an alignment: |
8228 | ||
8229 | Align to a power of 2. | |
8230 | Align so the next fragment's instruction does not cross a word boundary. | |
8231 | Align the current instruction so that if the next instruction | |
8232 | were 3 bytes, it would not cross a word boundary. | |
8233 | ||
e0001a05 NC |
8234 | We can align with: |
8235 | ||
43cd72b9 BW |
8236 | zeros - This is easy; always insert zeros. |
8237 | nops - 3-byte and 2-byte instructions | |
8238 | 2 - 2-byte nop | |
8239 | 3 - 3-byte nop | |
8240 | 4 - 2 2-byte nops | |
8241 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
8242 | widening - widen previous instructions. */ |
8243 | ||
d77b99c9 BW |
8244 | static offsetT |
8245 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 8246 | { |
43cd72b9 BW |
8247 | addressT target_address, loop_insn_offset; |
8248 | int target_size; | |
8249 | xtensa_opcode loop_opcode; | |
8250 | bfd_boolean is_loop; | |
d77b99c9 BW |
8251 | int align_power; |
8252 | offsetT opt_diff; | |
5f9084e9 | 8253 | offsetT branch_align; |
e0001a05 | 8254 | |
43cd72b9 BW |
8255 | assert (fragP->fr_type == rs_machine_dependent); |
8256 | switch (fragP->fr_subtype) | |
e0001a05 | 8257 | { |
43cd72b9 BW |
8258 | case RELAX_DESIRE_ALIGN: |
8259 | target_size = next_frag_format_size (fragP); | |
8260 | if (target_size == XTENSA_UNDEFINED) | |
8261 | target_size = 3; | |
664df4e4 BW |
8262 | align_power = branch_align_power (now_seg); |
8263 | branch_align = 1 << align_power; | |
0e5cd789 BW |
8264 | /* Don't count on the section alignment being as large as the target. */ |
8265 | if (target_size > branch_align) | |
8266 | target_size = branch_align; | |
d77b99c9 | 8267 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
8268 | target_size, FALSE, FALSE); |
8269 | ||
664df4e4 BW |
8270 | *max_diff = (opt_diff + branch_align |
8271 | - (target_size + ((address + opt_diff) % branch_align))); | |
43cd72b9 BW |
8272 | assert (*max_diff >= opt_diff); |
8273 | return opt_diff; | |
e0001a05 | 8274 | |
43cd72b9 | 8275 | case RELAX_ALIGN_NEXT_OPCODE: |
03aaa593 | 8276 | target_size = get_loop_align_size (next_frag_format_size (fragP)); |
43cd72b9 BW |
8277 | loop_insn_offset = 0; |
8278 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
8279 | assert (is_loop); | |
8280 | ||
8281 | /* If the loop has been expanded then the LOOP instruction | |
8282 | could be at an offset from this fragment. */ | |
8283 | if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0] | |
8284 | != RELAX_IMMED) | |
8285 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); | |
8286 | ||
43cd72b9 BW |
8287 | /* In an ideal world, which is what we are shooting for here, |
8288 | we wouldn't need to use any NOPs immediately prior to the | |
8289 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
8290 | will call get_noop_aligned_address. */ | |
8291 | target_address = | |
8292 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
d77b99c9 BW |
8293 | align_power = get_text_align_power (target_size), |
8294 | opt_diff = get_text_align_fill_size (target_address, align_power, | |
43cd72b9 BW |
8295 | target_size, FALSE, FALSE); |
8296 | ||
8297 | *max_diff = xtensa_fetch_width | |
8298 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
8299 | - target_size + opt_diff; | |
8300 | assert (*max_diff >= opt_diff); | |
8301 | return opt_diff; | |
e0001a05 | 8302 | |
43cd72b9 BW |
8303 | default: |
8304 | break; | |
e0001a05 | 8305 | } |
43cd72b9 BW |
8306 | assert (0); |
8307 | return 0; | |
e0001a05 NC |
8308 | } |
8309 | ||
8310 | \f | |
8311 | /* md_relax_frag Hook and Helper Functions. */ | |
8312 | ||
7fa3d080 BW |
8313 | static long relax_frag_loop_align (fragS *, long); |
8314 | static long relax_frag_for_align (fragS *, long); | |
8315 | static long relax_frag_immed | |
8316 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
8317 | ||
8318 | ||
e0001a05 NC |
8319 | /* Return the number of bytes added to this fragment, given that the |
8320 | input has been stretched already by "stretch". */ | |
8321 | ||
8322 | long | |
7fa3d080 | 8323 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 8324 | { |
43cd72b9 | 8325 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
8326 | int unreported = fragP->tc_frag_data.unreported_expansion; |
8327 | long new_stretch = 0; | |
8328 | char *file_name; | |
d77b99c9 BW |
8329 | unsigned line; |
8330 | int lit_size; | |
43cd72b9 BW |
8331 | static xtensa_insnbuf vbuf = NULL; |
8332 | int slot, num_slots; | |
8333 | xtensa_format fmt; | |
e0001a05 NC |
8334 | |
8335 | as_where (&file_name, &line); | |
8336 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8337 | ||
8338 | fragP->tc_frag_data.unreported_expansion = 0; | |
8339 | ||
8340 | switch (fragP->fr_subtype) | |
8341 | { | |
8342 | case RELAX_ALIGN_NEXT_OPCODE: | |
8343 | /* Always convert. */ | |
43cd72b9 BW |
8344 | if (fragP->tc_frag_data.relax_seen) |
8345 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
8346 | break; |
8347 | ||
8348 | case RELAX_LOOP_END: | |
8349 | /* Do nothing. */ | |
8350 | break; | |
8351 | ||
8352 | case RELAX_LOOP_END_ADD_NOP: | |
8353 | /* Add a NOP and switch to .fill 0. */ | |
8354 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 8355 | frag_wane (fragP); |
e0001a05 NC |
8356 | break; |
8357 | ||
8358 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 8359 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
8360 | it or not. */ |
8361 | break; | |
8362 | ||
8363 | case RELAX_LITERAL: | |
8364 | case RELAX_LITERAL_FINAL: | |
8365 | return 0; | |
8366 | ||
8367 | case RELAX_LITERAL_NR: | |
8368 | lit_size = 4; | |
8369 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
8370 | assert (unreported == lit_size); | |
8371 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); | |
8372 | fragP->fr_var -= lit_size; | |
8373 | fragP->fr_fix += lit_size; | |
8374 | new_stretch = 4; | |
8375 | break; | |
8376 | ||
43cd72b9 BW |
8377 | case RELAX_SLOTS: |
8378 | if (vbuf == NULL) | |
8379 | vbuf = xtensa_insnbuf_alloc (isa); | |
8380 | ||
d77b99c9 BW |
8381 | xtensa_insnbuf_from_chars |
8382 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
8383 | fmt = xtensa_format_decode (isa, vbuf); |
8384 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 8385 | |
43cd72b9 BW |
8386 | for (slot = 0; slot < num_slots; slot++) |
8387 | { | |
8388 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
8389 | { | |
8390 | case RELAX_NARROW: | |
8391 | if (fragP->tc_frag_data.relax_seen) | |
8392 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8393 | break; | |
8394 | ||
8395 | case RELAX_IMMED: | |
8396 | case RELAX_IMMED_STEP1: | |
8397 | case RELAX_IMMED_STEP2: | |
b81bf389 | 8398 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
8399 | /* Place the immediate. */ |
8400 | new_stretch += relax_frag_immed | |
8401 | (now_seg, fragP, stretch, | |
8402 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8403 | fmt, slot, stretched_p, FALSE); | |
8404 | break; | |
8405 | ||
8406 | default: | |
8407 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
8408 | break; | |
8409 | } | |
8410 | } | |
e0001a05 NC |
8411 | break; |
8412 | ||
8413 | case RELAX_LITERAL_POOL_BEGIN: | |
8414 | case RELAX_LITERAL_POOL_END: | |
43cd72b9 BW |
8415 | case RELAX_MAYBE_UNREACHABLE: |
8416 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
8417 | /* No relaxation required. */ |
8418 | break; | |
8419 | ||
43cd72b9 BW |
8420 | case RELAX_FILL_NOP: |
8421 | case RELAX_UNREACHABLE: | |
8422 | if (fragP->tc_frag_data.relax_seen) | |
8423 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8424 | break; | |
8425 | ||
e0001a05 NC |
8426 | default: |
8427 | as_bad (_("bad relaxation state")); | |
8428 | } | |
8429 | ||
43cd72b9 | 8430 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 8431 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
8432 | { |
8433 | fragP->tc_frag_data.relax_seen = TRUE; | |
8434 | *stretched_p = 1; | |
8435 | } | |
8436 | ||
e0001a05 NC |
8437 | new_logical_line (file_name, line); |
8438 | return new_stretch; | |
8439 | } | |
8440 | ||
8441 | ||
8442 | static long | |
7fa3d080 | 8443 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
8444 | { |
8445 | addressT old_address, old_next_address, old_size; | |
8446 | addressT new_address, new_next_address, new_size; | |
8447 | addressT growth; | |
8448 | ||
43cd72b9 BW |
8449 | /* All the frags with relax_frag_for_alignment prior to this one in the |
8450 | section have been done, hopefully eliminating the need for a NOP here. | |
8451 | But, this will put it in if necessary. */ | |
e0001a05 NC |
8452 | |
8453 | /* Calculate the old address of this fragment and the next fragment. */ | |
8454 | old_address = fragP->fr_address - stretch; | |
8455 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 8456 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
8457 | old_size = old_next_address - old_address; |
8458 | ||
8459 | /* Calculate the new address of this fragment and the next fragment. */ | |
8460 | new_address = fragP->fr_address; | |
8461 | new_next_address = | |
8462 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
8463 | new_size = new_next_address - new_address; | |
8464 | ||
8465 | growth = new_size - old_size; | |
8466 | ||
8467 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 8468 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
8469 | return growth; |
8470 | } | |
8471 | ||
8472 | ||
43cd72b9 | 8473 | /* Add a NOP instruction. */ |
e0001a05 NC |
8474 | |
8475 | static long | |
7fa3d080 | 8476 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 8477 | { |
e0001a05 | 8478 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
8479 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
8480 | assemble_nop (length, nop_buf); | |
e0001a05 | 8481 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 8482 | |
e0001a05 NC |
8483 | if (fragP->fr_var < length) |
8484 | { | |
dd49a749 | 8485 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
8486 | return 0; |
8487 | } | |
8488 | ||
8489 | fragP->fr_fix += length; | |
8490 | fragP->fr_var -= length; | |
e0001a05 NC |
8491 | return length; |
8492 | } | |
8493 | ||
8494 | ||
7fa3d080 BW |
8495 | static long future_alignment_required (fragS *, long); |
8496 | ||
e0001a05 | 8497 | static long |
7fa3d080 | 8498 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 8499 | { |
43cd72b9 BW |
8500 | /* Overview of the relaxation procedure for alignment: |
8501 | We can widen with NOPs or by widening instructions or by filling | |
8502 | bytes after jump instructions. Find the opportune places and widen | |
8503 | them if necessary. */ | |
8504 | ||
8505 | long stretch_me; | |
8506 | long diff; | |
e0001a05 | 8507 | |
43cd72b9 BW |
8508 | assert (fragP->fr_subtype == RELAX_FILL_NOP |
8509 | || fragP->fr_subtype == RELAX_UNREACHABLE | |
8510 | || (fragP->fr_subtype == RELAX_SLOTS | |
8511 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
8512 | ||
8513 | stretch_me = future_alignment_required (fragP, stretch); | |
8514 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
8515 | if (diff == 0) | |
8516 | return 0; | |
e0001a05 | 8517 | |
43cd72b9 | 8518 | if (diff < 0) |
e0001a05 | 8519 | { |
43cd72b9 BW |
8520 | /* We expanded on a previous pass. Can we shrink now? */ |
8521 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
8522 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 8523 | { |
43cd72b9 BW |
8524 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
8525 | return -shrink; | |
e0001a05 NC |
8526 | } |
8527 | return 0; | |
8528 | } | |
8529 | ||
43cd72b9 BW |
8530 | /* Below here, diff > 0. */ |
8531 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 8532 | |
43cd72b9 | 8533 | return diff; |
e0001a05 NC |
8534 | } |
8535 | ||
8536 | ||
43cd72b9 BW |
8537 | /* Return the address of the next frag that should be aligned. |
8538 | ||
8539 | By "address" we mean the address it _would_ be at if there | |
8540 | is no action taken to align it between here and the target frag. | |
8541 | In other words, if no narrows and no fill nops are used between | |
8542 | here and the frag to align, _even_if_ some of the frags we use | |
8543 | to align targets have already expanded on a previous relaxation | |
8544 | pass. | |
8545 | ||
8546 | Also, count each frag that may be used to help align the target. | |
8547 | ||
8548 | Return 0 if there are no frags left in the chain that need to be | |
8549 | aligned. */ | |
8550 | ||
8551 | static addressT | |
7fa3d080 BW |
8552 | find_address_of_next_align_frag (fragS **fragPP, |
8553 | int *wide_nops, | |
8554 | int *narrow_nops, | |
8555 | int *widens, | |
8556 | bfd_boolean *paddable) | |
e0001a05 | 8557 | { |
43cd72b9 BW |
8558 | fragS *fragP = *fragPP; |
8559 | addressT address = fragP->fr_address; | |
8560 | ||
8561 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
8562 | |
8563 | while (fragP) | |
8564 | { | |
8565 | /* Limit this to a small search. */ | |
b5e4a23d | 8566 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
8567 | { |
8568 | *fragPP = fragP; | |
8569 | return 0; | |
8570 | } | |
e0001a05 NC |
8571 | address += fragP->fr_fix; |
8572 | ||
43cd72b9 BW |
8573 | if (fragP->fr_type == rs_fill) |
8574 | address += fragP->fr_offset * fragP->fr_var; | |
8575 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 8576 | { |
e0001a05 NC |
8577 | switch (fragP->fr_subtype) |
8578 | { | |
43cd72b9 BW |
8579 | case RELAX_UNREACHABLE: |
8580 | *paddable = TRUE; | |
8581 | break; | |
8582 | ||
8583 | case RELAX_FILL_NOP: | |
8584 | (*wide_nops)++; | |
8585 | if (!fragP->tc_frag_data.is_no_density) | |
8586 | (*narrow_nops)++; | |
8587 | break; | |
8588 | ||
8589 | case RELAX_SLOTS: | |
8590 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8591 | { | |
8592 | (*widens)++; | |
8593 | break; | |
8594 | } | |
34e41783 | 8595 | address += total_frag_text_expansion (fragP);; |
e0001a05 NC |
8596 | break; |
8597 | ||
8598 | case RELAX_IMMED: | |
43cd72b9 | 8599 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
8600 | break; |
8601 | ||
8602 | case RELAX_ALIGN_NEXT_OPCODE: | |
8603 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
8604 | *fragPP = fragP; |
8605 | return address; | |
8606 | ||
8607 | case RELAX_MAYBE_UNREACHABLE: | |
8608 | case RELAX_MAYBE_DESIRE_ALIGN: | |
8609 | /* Do nothing. */ | |
e0001a05 NC |
8610 | break; |
8611 | ||
8612 | default: | |
43cd72b9 BW |
8613 | /* Just punt if we don't know the type. */ |
8614 | *fragPP = fragP; | |
8615 | return 0; | |
e0001a05 | 8616 | } |
43cd72b9 | 8617 | } |
c138bc38 | 8618 | else |
43cd72b9 BW |
8619 | { |
8620 | /* Just punt if we don't know the type. */ | |
8621 | *fragPP = fragP; | |
8622 | return 0; | |
8623 | } | |
8624 | fragP = fragP->fr_next; | |
8625 | } | |
8626 | ||
8627 | *fragPP = fragP; | |
8628 | return 0; | |
8629 | } | |
8630 | ||
8631 | ||
7fa3d080 BW |
8632 | static long bytes_to_stretch (fragS *, int, int, int, int); |
8633 | ||
43cd72b9 | 8634 | static long |
7fa3d080 | 8635 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
8636 | { |
8637 | fragS *this_frag = fragP; | |
8638 | long address; | |
8639 | int num_widens = 0; | |
8640 | int wide_nops = 0; | |
8641 | int narrow_nops = 0; | |
8642 | bfd_boolean paddable = FALSE; | |
8643 | offsetT local_opt_diff; | |
8644 | offsetT opt_diff; | |
8645 | offsetT max_diff; | |
8646 | int stretch_amount = 0; | |
8647 | int local_stretch_amount; | |
8648 | int global_stretch_amount; | |
8649 | ||
7fa3d080 BW |
8650 | address = find_address_of_next_align_frag |
8651 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 8652 | |
b5e4a23d BW |
8653 | if (!address) |
8654 | { | |
8655 | if (this_frag->tc_frag_data.is_aligning_branch) | |
8656 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
8657 | else | |
8658 | frag_wane (this_frag); | |
8659 | } | |
8660 | else | |
43cd72b9 BW |
8661 | { |
8662 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
8663 | opt_diff = local_opt_diff; | |
8664 | assert (opt_diff >= 0); | |
8665 | assert (max_diff >= opt_diff); | |
c138bc38 | 8666 | if (max_diff == 0) |
43cd72b9 | 8667 | return 0; |
d2a033cd | 8668 | |
43cd72b9 BW |
8669 | if (fragP) |
8670 | fragP = fragP->fr_next; | |
8671 | ||
8672 | while (fragP && opt_diff < max_diff && address) | |
8673 | { | |
8674 | /* We only use these to determine if we can exit early | |
c138bc38 | 8675 | because there will be plenty of ways to align future |
43cd72b9 | 8676 | align frags. */ |
d77b99c9 | 8677 | int glob_widens = 0; |
43cd72b9 BW |
8678 | int dnn = 0; |
8679 | int dw = 0; | |
8680 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
8681 | address = find_address_of_next_align_frag |
8682 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 8683 | /* If there is a padable portion, then skip. */ |
664df4e4 | 8684 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 8685 | address = 0; |
43cd72b9 | 8686 | |
c138bc38 | 8687 | if (address) |
43cd72b9 BW |
8688 | { |
8689 | offsetT next_m_diff; | |
8690 | offsetT next_o_diff; | |
8691 | ||
8692 | /* Downrange frags haven't had stretch added to them yet. */ | |
8693 | address += stretch; | |
8694 | ||
8695 | /* The address also includes any text expansion from this | |
8696 | frag in a previous pass, but we don't want that. */ | |
8697 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
8698 | ||
8699 | /* Assume we are going to move at least opt_diff. In | |
8700 | reality, we might not be able to, but assuming that | |
8701 | we will helps catch cases where moving opt_diff pushes | |
8702 | the next target from aligned to unaligned. */ | |
8703 | address += opt_diff; | |
8704 | ||
8705 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
8706 | ||
8707 | /* Now cleanup for the adjustments to address. */ | |
8708 | next_o_diff += opt_diff; | |
8709 | next_m_diff += opt_diff; | |
8710 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
8711 | opt_diff = next_o_diff; | |
8712 | if (next_m_diff < max_diff) | |
8713 | max_diff = next_m_diff; | |
8714 | fragP = fragP->fr_next; | |
8715 | } | |
8716 | } | |
d2a033cd | 8717 | |
43cd72b9 BW |
8718 | /* If there are enough wideners in between, do it. */ |
8719 | if (paddable) | |
8720 | { | |
8721 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
8722 | { | |
8723 | assert (opt_diff <= UNREACHABLE_MAX_WIDTH); | |
8724 | return opt_diff; | |
8725 | } | |
8726 | return 0; | |
8727 | } | |
c138bc38 | 8728 | local_stretch_amount |
43cd72b9 BW |
8729 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
8730 | num_widens, local_opt_diff); | |
c138bc38 BW |
8731 | global_stretch_amount |
8732 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 8733 | num_widens, opt_diff); |
c138bc38 BW |
8734 | /* If the condition below is true, then the frag couldn't |
8735 | stretch the correct amount for the global case, so we just | |
8736 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
8737 | the correct alignment in the global case. */ |
8738 | if (global_stretch_amount < local_stretch_amount) | |
8739 | stretch_amount = local_stretch_amount; | |
8740 | else | |
8741 | stretch_amount = global_stretch_amount; | |
d2a033cd | 8742 | |
43cd72b9 BW |
8743 | if (this_frag->fr_subtype == RELAX_SLOTS |
8744 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8745 | assert (stretch_amount <= 1); | |
8746 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8747 | { | |
8748 | if (this_frag->tc_frag_data.is_no_density) | |
8749 | assert (stretch_amount == 3 || stretch_amount == 0); | |
8750 | else | |
8751 | assert (stretch_amount <= 3); | |
8752 | } | |
8753 | } | |
8754 | return stretch_amount; | |
8755 | } | |
8756 | ||
8757 | ||
8758 | /* The idea: widen everything you can to get a target or loop aligned, | |
8759 | then start using NOPs. | |
8760 | ||
8761 | When we must have a NOP, here is a table of how we decide | |
8762 | (so you don't have to fight through the control flow below): | |
8763 | ||
8764 | wide_nops = the number of wide NOPs available for aligning | |
8765 | narrow_nops = the number of narrow NOPs available for aligning | |
8766 | (a subset of wide_nops) | |
8767 | widens = the number of narrow instructions that should be widened | |
8768 | ||
8769 | Desired wide narrow | |
8770 | Diff nop nop widens | |
8771 | 1 0 0 1 | |
8772 | 2 0 1 0 | |
8773 | 3a 1 0 0 | |
8774 | b 0 1 1 (case 3a makes this case unnecessary) | |
8775 | 4a 1 0 1 | |
8776 | b 0 2 0 | |
8777 | c 0 1 2 (case 4a makes this case unnecessary) | |
8778 | 5a 1 0 2 | |
8779 | b 1 1 0 | |
8780 | c 0 2 1 (case 5b makes this case unnecessary) | |
8781 | 6a 2 0 0 | |
8782 | b 1 0 3 | |
708587a4 | 8783 | c 0 1 4 (case 6b makes this case unnecessary) |
43cd72b9 BW |
8784 | d 1 1 1 (case 6a makes this case unnecessary) |
8785 | e 0 2 2 (case 6a makes this case unnecessary) | |
8786 | f 0 3 0 (case 6a makes this case unnecessary) | |
8787 | 7a 1 0 4 | |
8788 | b 2 0 1 | |
8789 | c 1 1 2 (case 7b makes this case unnecessary) | |
8790 | d 0 1 5 (case 7a makes this case unnecessary) | |
8791 | e 0 2 3 (case 7b makes this case unnecessary) | |
8792 | f 0 3 1 (case 7b makes this case unnecessary) | |
8793 | g 1 2 1 (case 7b makes this case unnecessary) | |
8794 | */ | |
8795 | ||
8796 | static long | |
7fa3d080 BW |
8797 | bytes_to_stretch (fragS *this_frag, |
8798 | int wide_nops, | |
8799 | int narrow_nops, | |
8800 | int num_widens, | |
8801 | int desired_diff) | |
43cd72b9 BW |
8802 | { |
8803 | int bytes_short = desired_diff - num_widens; | |
8804 | ||
8805 | assert (desired_diff >= 0 && desired_diff < 8); | |
8806 | if (desired_diff == 0) | |
8807 | return 0; | |
c138bc38 | 8808 | |
43cd72b9 | 8809 | assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 8810 | |
43cd72b9 BW |
8811 | /* Always prefer widening to NOP-filling. */ |
8812 | if (bytes_short < 0) | |
8813 | { | |
8814 | /* There are enough RELAX_NARROW frags after this one | |
8815 | to align the target without widening this frag in any way. */ | |
8816 | return 0; | |
8817 | } | |
c138bc38 | 8818 | |
43cd72b9 BW |
8819 | if (bytes_short == 0) |
8820 | { | |
8821 | /* Widen every narrow between here and the align target | |
8822 | and the align target will be properly aligned. */ | |
8823 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8824 | return 0; | |
8825 | else | |
8826 | return 1; | |
8827 | } | |
c138bc38 | 8828 | |
43cd72b9 BW |
8829 | /* From here we will need at least one NOP to get an alignment. |
8830 | However, we may not be able to align at all, in which case, | |
8831 | don't widen. */ | |
8832 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8833 | { | |
8834 | switch (desired_diff) | |
8835 | { | |
8836 | case 1: | |
8837 | return 0; | |
8838 | case 2: | |
8839 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1) | |
8840 | return 2; /* case 2 */ | |
8841 | return 0; | |
c138bc38 | 8842 | case 3: |
43cd72b9 BW |
8843 | if (wide_nops > 1) |
8844 | return 0; | |
8845 | else | |
8846 | return 3; /* case 3a */ | |
8847 | case 4: | |
8848 | if (num_widens >= 1 && wide_nops == 1) | |
8849 | return 3; /* case 4a */ | |
8850 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2) | |
8851 | return 2; /* case 4b */ | |
8852 | return 0; | |
8853 | case 5: | |
8854 | if (num_widens >= 2 && wide_nops == 1) | |
8855 | return 3; /* case 5a */ | |
c138bc38 | 8856 | /* We will need two nops. Are there enough nops |
43cd72b9 BW |
8857 | between here and the align target? */ |
8858 | if (wide_nops < 2 || narrow_nops == 0) | |
8859 | return 0; | |
8860 | /* Are there other nops closer that can serve instead? */ | |
8861 | if (wide_nops > 2 && narrow_nops > 1) | |
8862 | return 0; | |
8863 | /* Take the density one first, because there might not be | |
8864 | another density one available. */ | |
8865 | if (!this_frag->tc_frag_data.is_no_density) | |
8866 | return 2; /* case 5b narrow */ | |
8867 | else | |
8868 | return 3; /* case 5b wide */ | |
8869 | return 0; | |
8870 | case 6: | |
8871 | if (wide_nops == 2) | |
8872 | return 3; /* case 6a */ | |
8873 | else if (num_widens >= 3 && wide_nops == 1) | |
8874 | return 3; /* case 6b */ | |
8875 | return 0; | |
8876 | case 7: | |
8877 | if (wide_nops == 1 && num_widens >= 4) | |
8878 | return 3; /* case 7a */ | |
8879 | else if (wide_nops == 2 && num_widens >= 1) | |
8880 | return 3; /* case 7b */ | |
8881 | return 0; | |
e0001a05 | 8882 | default: |
43cd72b9 | 8883 | assert (0); |
e0001a05 | 8884 | } |
e0001a05 | 8885 | } |
43cd72b9 BW |
8886 | else |
8887 | { | |
c138bc38 | 8888 | /* We will need a NOP no matter what, but should we widen |
43cd72b9 | 8889 | this instruction to help? |
e0001a05 | 8890 | |
03aaa593 | 8891 | This is a RELAX_NARROW frag. */ |
43cd72b9 BW |
8892 | switch (desired_diff) |
8893 | { | |
8894 | case 1: | |
8895 | assert (0); | |
8896 | return 0; | |
8897 | case 2: | |
8898 | case 3: | |
8899 | return 0; | |
8900 | case 4: | |
8901 | if (wide_nops >= 1 && num_widens == 1) | |
8902 | return 1; /* case 4a */ | |
8903 | return 0; | |
8904 | case 5: | |
8905 | if (wide_nops >= 1 && num_widens == 2) | |
8906 | return 1; /* case 5a */ | |
8907 | return 0; | |
8908 | case 6: | |
8909 | if (wide_nops >= 2) | |
8910 | return 0; /* case 6a */ | |
8911 | else if (wide_nops >= 1 && num_widens == 3) | |
8912 | return 1; /* case 6b */ | |
8913 | return 0; | |
8914 | case 7: | |
8915 | if (wide_nops >= 1 && num_widens == 4) | |
8916 | return 1; /* case 7a */ | |
8917 | else if (wide_nops >= 2 && num_widens == 1) | |
8918 | return 1; /* case 7b */ | |
8919 | return 0; | |
8920 | default: | |
8921 | assert (0); | |
8922 | return 0; | |
8923 | } | |
8924 | } | |
8925 | assert (0); | |
8926 | return 0; | |
e0001a05 NC |
8927 | } |
8928 | ||
8929 | ||
8930 | static long | |
7fa3d080 BW |
8931 | relax_frag_immed (segT segP, |
8932 | fragS *fragP, | |
8933 | long stretch, | |
8934 | int min_steps, | |
8935 | xtensa_format fmt, | |
8936 | int slot, | |
8937 | int *stretched_p, | |
8938 | bfd_boolean estimate_only) | |
e0001a05 | 8939 | { |
43cd72b9 | 8940 | TInsn tinsn; |
e0001a05 NC |
8941 | int old_size; |
8942 | bfd_boolean negatable_branch = FALSE; | |
8943 | bfd_boolean branch_jmp_to_next = FALSE; | |
43cd72b9 BW |
8944 | bfd_boolean wide_insn = FALSE; |
8945 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
8946 | IStack istack; |
8947 | offsetT frag_offset; | |
8948 | int num_steps; | |
8949 | fragS *lit_fragP; | |
8950 | int num_text_bytes, num_literal_bytes; | |
43cd72b9 | 8951 | int literal_diff, total_text_diff, this_text_diff, first; |
e0001a05 NC |
8952 | |
8953 | assert (fragP->fr_opcode != NULL); | |
8954 | ||
b5e4a23d BW |
8955 | xg_clear_vinsn (&cur_vinsn); |
8956 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 8957 | if (cur_vinsn.num_slots > 1) |
43cd72b9 BW |
8958 | wide_insn = TRUE; |
8959 | ||
b5e4a23d | 8960 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 8961 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 8962 | |
64b607e6 | 8963 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 8964 | return 0; |
e0001a05 | 8965 | |
b08b5071 | 8966 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 8967 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 8968 | |
43cd72b9 | 8969 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 8970 | |
43cd72b9 | 8971 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
8972 | |
8973 | /* Special case: replace a branch to the next instruction with a NOP. | |
8974 | This is required to work around a hardware bug in T1040.0 and also | |
8975 | serves as an optimization. */ | |
8976 | ||
8977 | if (branch_jmp_to_next | |
8978 | && ((old_size == 2) || (old_size == 3)) | |
8979 | && !next_frag_is_loop_target (fragP)) | |
8980 | return 0; | |
8981 | ||
8982 | /* Here is the fun stuff: Get the immediate field from this | |
8983 | instruction. If it fits, we are done. If not, find the next | |
8984 | instruction sequence that fits. */ | |
8985 | ||
8986 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
8987 | istack_init (&istack); | |
43cd72b9 | 8988 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 NC |
8989 | min_steps, stretch); |
8990 | if (num_steps < min_steps) | |
8991 | { | |
8992 | as_fatal (_("internal error: relaxation failed")); | |
8993 | return 0; | |
8994 | } | |
8995 | ||
8996 | if (num_steps > RELAX_IMMED_MAXSTEPS) | |
8997 | { | |
8998 | as_fatal (_("internal error: relaxation requires too many steps")); | |
8999 | return 0; | |
9000 | } | |
9001 | ||
43cd72b9 | 9002 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
9003 | |
9004 | /* Figure out the number of bytes needed. */ | |
9005 | lit_fragP = 0; | |
e0001a05 | 9006 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
43cd72b9 BW |
9007 | literal_diff = |
9008 | num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
9009 | first = 0; | |
9010 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
9011 | first++; | |
9012 | num_text_bytes = get_num_stack_text_bytes (&istack); | |
9013 | if (wide_insn) | |
9014 | { | |
9015 | num_text_bytes += old_size; | |
9016 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
9017 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
9018 | } | |
9019 | total_text_diff = num_text_bytes - old_size; | |
9020 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
9021 | |
9022 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
43cd72b9 BW |
9023 | assert (num_text_bytes >= 0); |
9024 | assert (literal_diff >= 0); | |
9025 | assert (total_text_diff >= 0); | |
e0001a05 | 9026 | |
43cd72b9 BW |
9027 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
9028 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
9029 | assert (fragP->tc_frag_data.text_expansion[slot] >= 0); | |
9030 | assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
9031 | |
9032 | /* Find the associated expandable literal for this. */ | |
9033 | if (literal_diff != 0) | |
9034 | { | |
43cd72b9 | 9035 | lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9036 | if (lit_fragP) |
9037 | { | |
9038 | assert (literal_diff == 4); | |
9039 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; | |
9040 | ||
9041 | /* We expect that the literal section state has NOT been | |
9042 | modified yet. */ | |
9043 | assert (lit_fragP->fr_type == rs_machine_dependent | |
9044 | && lit_fragP->fr_subtype == RELAX_LITERAL); | |
9045 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
9046 | ||
9047 | /* We need to mark this section for another iteration | |
9048 | of relaxation. */ | |
9049 | (*stretched_p)++; | |
9050 | } | |
9051 | } | |
9052 | ||
43cd72b9 | 9053 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 9054 | update_next_frag_state (fragP); |
e0001a05 | 9055 | |
43cd72b9 | 9056 | return this_text_diff; |
e0001a05 NC |
9057 | } |
9058 | ||
9059 | \f | |
9060 | /* md_convert_frag Hook and Helper Functions. */ | |
9061 | ||
7fa3d080 BW |
9062 | static void convert_frag_align_next_opcode (fragS *); |
9063 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
9064 | static void convert_frag_fill_nop (fragS *); | |
9065 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
9066 | ||
e0001a05 | 9067 | void |
7fa3d080 | 9068 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 9069 | { |
43cd72b9 BW |
9070 | static xtensa_insnbuf vbuf = NULL; |
9071 | xtensa_isa isa = xtensa_default_isa; | |
9072 | int slot; | |
9073 | int num_slots; | |
9074 | xtensa_format fmt; | |
e0001a05 | 9075 | char *file_name; |
d77b99c9 | 9076 | unsigned line; |
e0001a05 NC |
9077 | |
9078 | as_where (&file_name, &line); | |
9079 | new_logical_line (fragp->fr_file, fragp->fr_line); | |
9080 | ||
9081 | switch (fragp->fr_subtype) | |
9082 | { | |
9083 | case RELAX_ALIGN_NEXT_OPCODE: | |
9084 | /* Always convert. */ | |
9085 | convert_frag_align_next_opcode (fragp); | |
9086 | break; | |
9087 | ||
9088 | case RELAX_DESIRE_ALIGN: | |
9089 | /* Do nothing. If not aligned already, too bad. */ | |
9090 | break; | |
9091 | ||
43cd72b9 BW |
9092 | case RELAX_LITERAL: |
9093 | case RELAX_LITERAL_FINAL: | |
9094 | break; | |
9095 | ||
9096 | case RELAX_SLOTS: | |
9097 | if (vbuf == NULL) | |
9098 | vbuf = xtensa_insnbuf_alloc (isa); | |
9099 | ||
d77b99c9 BW |
9100 | xtensa_insnbuf_from_chars |
9101 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
9102 | fmt = xtensa_format_decode (isa, vbuf); |
9103 | num_slots = xtensa_format_num_slots (isa, fmt); | |
9104 | ||
9105 | for (slot = 0; slot < num_slots; slot++) | |
9106 | { | |
9107 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
9108 | { | |
9109 | case RELAX_NARROW: | |
9110 | convert_frag_narrow (sec, fragp, fmt, slot); | |
9111 | break; | |
9112 | ||
9113 | case RELAX_IMMED: | |
9114 | case RELAX_IMMED_STEP1: | |
9115 | case RELAX_IMMED_STEP2: | |
b81bf389 | 9116 | case RELAX_IMMED_STEP3: |
43cd72b9 BW |
9117 | /* Place the immediate. */ |
9118 | convert_frag_immed | |
9119 | (sec, fragp, | |
9120 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
9121 | fmt, slot); | |
9122 | break; | |
9123 | ||
9124 | default: | |
9125 | /* This is OK because some slots could have | |
9126 | relaxations and others have none. */ | |
9127 | break; | |
9128 | } | |
9129 | } | |
9130 | break; | |
9131 | ||
9132 | case RELAX_UNREACHABLE: | |
9133 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
9134 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
9135 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
9136 | frag_wane (fragp); | |
e0001a05 NC |
9137 | break; |
9138 | ||
43cd72b9 BW |
9139 | case RELAX_MAYBE_UNREACHABLE: |
9140 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9141 | frag_wane (fragp); | |
e0001a05 NC |
9142 | break; |
9143 | ||
43cd72b9 BW |
9144 | case RELAX_FILL_NOP: |
9145 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
9146 | break; |
9147 | ||
9148 | case RELAX_LITERAL_NR: | |
9149 | if (use_literal_section) | |
9150 | { | |
9151 | /* This should have been handled during relaxation. When | |
9152 | relaxing a code segment, literals sometimes need to be | |
9153 | added to the corresponding literal segment. If that | |
9154 | literal segment has already been relaxed, then we end up | |
9155 | in this situation. Marking the literal segments as data | |
9156 | would make this happen less often (since GAS always relaxes | |
9157 | code before data), but we could still get into trouble if | |
9158 | there are instructions in a segment that is not marked as | |
9159 | containing code. Until we can implement a better solution, | |
9160 | cheat and adjust the addresses of all the following frags. | |
9161 | This could break subsequent alignments, but the linker's | |
9162 | literal coalescing will do that anyway. */ | |
9163 | ||
9164 | fragS *f; | |
9165 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9166 | assert (fragp->tc_frag_data.unreported_expansion == 4); | |
9167 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); | |
9168 | fragp->fr_var -= 4; | |
9169 | fragp->fr_fix += 4; | |
9170 | for (f = fragp->fr_next; f; f = f->fr_next) | |
9171 | f->fr_address += 4; | |
9172 | } | |
9173 | else | |
9174 | as_bad (_("invalid relaxation fragment result")); | |
9175 | break; | |
9176 | } | |
9177 | ||
9178 | fragp->fr_var = 0; | |
9179 | new_logical_line (file_name, line); | |
9180 | } | |
9181 | ||
9182 | ||
7fa3d080 BW |
9183 | static void |
9184 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
9185 | { |
9186 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
9187 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
9188 | addressT aligned_address; | |
d77b99c9 BW |
9189 | offsetT fill_size; |
9190 | int nop, nop_count; | |
e0001a05 NC |
9191 | |
9192 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
9193 | fragp->fr_fix); | |
9194 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
9195 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
9196 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
9197 | ||
d77b99c9 | 9198 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 9199 | { |
d77b99c9 BW |
9200 | int nop_size; |
9201 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
9202 | |
9203 | assemble_nop (nop_size, nop_buf); | |
9204 | nop_buf += nop_size; | |
9205 | } | |
9206 | ||
9207 | fragp->fr_fix += fill_size; | |
9208 | fragp->fr_var -= fill_size; | |
9209 | } | |
9210 | ||
9211 | ||
9212 | static void | |
7fa3d080 | 9213 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 9214 | { |
43cd72b9 | 9215 | TInsn tinsn, single_target; |
84b08ed9 | 9216 | int size, old_size, diff; |
e0001a05 NC |
9217 | offsetT frag_offset; |
9218 | ||
43cd72b9 BW |
9219 | assert (slot == 0); |
9220 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); | |
9221 | ||
b5e4a23d | 9222 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 BW |
9223 | { |
9224 | assert (fragP->tc_frag_data.text_expansion[0] == 1 | |
9225 | || fragP->tc_frag_data.text_expansion[0] == 0); | |
9226 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
9227 | fmt, slot); | |
9228 | return; | |
9229 | } | |
9230 | ||
9231 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
9232 | { |
9233 | /* No conversion. */ | |
9234 | fragP->fr_var = 0; | |
9235 | return; | |
9236 | } | |
9237 | ||
9238 | assert (fragP->fr_opcode != NULL); | |
9239 | ||
43cd72b9 BW |
9240 | /* Frags in this relaxation state should only contain |
9241 | single instruction bundles. */ | |
9242 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
9243 | |
9244 | /* Just convert it to a wide form.... */ | |
9245 | size = 0; | |
43cd72b9 | 9246 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
9247 | |
9248 | tinsn_init (&single_target); | |
9249 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9250 | ||
84b08ed9 | 9251 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
9252 | { |
9253 | as_bad (_("unable to widen instruction")); | |
9254 | return; | |
9255 | } | |
9256 | ||
9257 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
9258 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
9259 | frag_offset, TRUE); | |
e0001a05 NC |
9260 | |
9261 | diff = size - old_size; | |
9262 | assert (diff >= 0); | |
9263 | assert (diff <= fragP->fr_var); | |
9264 | fragP->fr_var -= diff; | |
9265 | fragP->fr_fix += diff; | |
9266 | ||
9267 | /* clean it up */ | |
9268 | fragP->fr_var = 0; | |
9269 | } | |
9270 | ||
9271 | ||
9272 | static void | |
7fa3d080 | 9273 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
9274 | { |
9275 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
9276 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9277 | assert ((unsigned) size == (fragP->fr_next->fr_address | |
9278 | - fragP->fr_address - fragP->fr_fix)); | |
9279 | if (size == 0) | |
9280 | { | |
9281 | /* No conversion. */ | |
9282 | fragP->fr_var = 0; | |
9283 | return; | |
9284 | } | |
9285 | assemble_nop (size, loc); | |
9286 | fragP->tc_frag_data.is_insn = TRUE; | |
9287 | fragP->fr_var -= size; | |
9288 | fragP->fr_fix += size; | |
9289 | frag_wane (fragP); | |
9290 | } | |
9291 | ||
9292 | ||
7fa3d080 BW |
9293 | static fixS *fix_new_exp_in_seg |
9294 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
9295 | bfd_reloc_code_real_type); | |
9296 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
9297 | ||
43cd72b9 | 9298 | static void |
7fa3d080 BW |
9299 | convert_frag_immed (segT segP, |
9300 | fragS *fragP, | |
9301 | int min_steps, | |
9302 | xtensa_format fmt, | |
9303 | int slot) | |
e0001a05 NC |
9304 | { |
9305 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 9306 | TInsn orig_tinsn; |
e0001a05 | 9307 | bfd_boolean expanded = FALSE; |
e0001a05 | 9308 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 9309 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 BW |
9310 | xtensa_isa isa = xtensa_default_isa; |
9311 | bfd_boolean wide_insn = FALSE; | |
9312 | int bytes; | |
9313 | bfd_boolean is_loop; | |
e0001a05 | 9314 | |
43cd72b9 | 9315 | assert (fr_opcode != NULL); |
e0001a05 | 9316 | |
b5e4a23d | 9317 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 9318 | |
b5e4a23d | 9319 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 9320 | if (cur_vinsn.num_slots > 1) |
43cd72b9 | 9321 | wide_insn = TRUE; |
e0001a05 | 9322 | |
b5e4a23d | 9323 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
9324 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
9325 | ||
9326 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 9327 | |
b08b5071 | 9328 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9329 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
9330 | |
9331 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
9332 | { | |
9333 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
9334 | bytes = xtensa_format_length (isa, fmt); |
9335 | if (bytes >= 4) | |
9336 | { | |
b5e4a23d BW |
9337 | cur_vinsn.slots[slot].opcode = |
9338 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
9339 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
9340 | } |
9341 | else | |
9342 | { | |
9343 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9344 | assert (bytes == 2 || bytes == 3); | |
b5e4a23d | 9345 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
9346 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
9347 | } | |
e7da6241 | 9348 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 9349 | xtensa_insnbuf_to_chars |
b5e4a23d | 9350 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
9351 | fragP->fr_var = 0; |
9352 | } | |
7c834684 | 9353 | else |
e0001a05 | 9354 | { |
43cd72b9 BW |
9355 | /* Here is the fun stuff: Get the immediate field from this |
9356 | instruction. If it fits, we're done. If not, find the next | |
9357 | instruction sequence that fits. */ | |
9358 | ||
e0001a05 NC |
9359 | IStack istack; |
9360 | int i; | |
9361 | symbolS *lit_sym = NULL; | |
9362 | int total_size = 0; | |
43cd72b9 | 9363 | int target_offset = 0; |
e0001a05 NC |
9364 | int old_size; |
9365 | int diff; | |
9366 | symbolS *gen_label = NULL; | |
9367 | offsetT frag_offset; | |
43cd72b9 BW |
9368 | bfd_boolean first = TRUE; |
9369 | bfd_boolean last_is_jump; | |
e0001a05 | 9370 | |
43cd72b9 | 9371 | /* It does not fit. Find something that does and |
e0001a05 | 9372 | convert immediately. */ |
43cd72b9 | 9373 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 9374 | istack_init (&istack); |
43cd72b9 | 9375 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
9376 | segP, fragP, frag_offset, min_steps, 0); |
9377 | ||
43cd72b9 | 9378 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9379 | |
9380 | /* Assemble this right inline. */ | |
9381 | ||
9382 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 9383 | target_offset = 0; |
e0001a05 NC |
9384 | for (i = 0; i < istack.ninsn; i++) |
9385 | { | |
43cd72b9 | 9386 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9387 | fragS *lit_frag; |
9388 | ||
43cd72b9 | 9389 | switch (tinsn->insn_type) |
e0001a05 NC |
9390 | { |
9391 | case ITYPE_LITERAL: | |
9392 | if (lit_sym != NULL) | |
9393 | as_bad (_("multiple literals in expansion")); | |
9394 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 9395 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9396 | if (lit_frag == NULL) |
9397 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 9398 | if (tinsn->ntok != 1) |
e0001a05 NC |
9399 | as_bad (_("number of literal tokens != 1")); |
9400 | ||
9401 | /* Set the literal symbol and add a fixup. */ | |
9402 | lit_sym = lit_frag->fr_symbol; | |
9403 | break; | |
9404 | ||
9405 | case ITYPE_LABEL: | |
43cd72b9 BW |
9406 | if (align_targets && !is_loop) |
9407 | { | |
9408 | fragS *unreach = fragP->fr_next; | |
9409 | while (!(unreach->fr_type == rs_machine_dependent | |
9410 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9411 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
9412 | { | |
9413 | unreach = unreach->fr_next; | |
9414 | } | |
9415 | ||
9416 | assert (unreach->fr_type == rs_machine_dependent | |
9417 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9418 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
9419 | ||
9420 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
9421 | } | |
e0001a05 NC |
9422 | assert (gen_label == NULL); |
9423 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, | |
43cd72b9 BW |
9424 | fr_opcode - fragP->fr_literal |
9425 | + target_offset, fragP); | |
e0001a05 NC |
9426 | break; |
9427 | ||
9428 | case ITYPE_INSN: | |
43cd72b9 BW |
9429 | if (first && wide_insn) |
9430 | { | |
9431 | target_offset += xtensa_format_length (isa, fmt); | |
9432 | first = FALSE; | |
9433 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9434 | target_offset += xg_get_single_size (tinsn->opcode); | |
9435 | } | |
9436 | else | |
9437 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
9438 | break; |
9439 | } | |
9440 | } | |
9441 | ||
9442 | total_size = 0; | |
43cd72b9 BW |
9443 | first = TRUE; |
9444 | last_is_jump = FALSE; | |
e0001a05 NC |
9445 | for (i = 0; i < istack.ninsn; i++) |
9446 | { | |
43cd72b9 | 9447 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9448 | fragS *lit_frag; |
9449 | int size; | |
9450 | segT target_seg; | |
43cd72b9 | 9451 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 9452 | |
43cd72b9 | 9453 | switch (tinsn->insn_type) |
e0001a05 NC |
9454 | { |
9455 | case ITYPE_LITERAL: | |
43cd72b9 BW |
9456 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
9457 | /* Already checked. */ | |
e0001a05 NC |
9458 | assert (lit_frag != NULL); |
9459 | assert (lit_sym != NULL); | |
43cd72b9 BW |
9460 | assert (tinsn->ntok == 1); |
9461 | /* Add a fixup. */ | |
e0001a05 NC |
9462 | target_seg = S_GET_SEGMENT (lit_sym); |
9463 | assert (target_seg); | |
bbdd25a8 | 9464 | reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op); |
e0001a05 | 9465 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 9466 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
9467 | break; |
9468 | ||
9469 | case ITYPE_LABEL: | |
9470 | break; | |
9471 | ||
9472 | case ITYPE_INSN: | |
43cd72b9 BW |
9473 | xg_resolve_labels (tinsn, gen_label); |
9474 | xg_resolve_literals (tinsn, lit_sym); | |
9475 | if (wide_insn && first) | |
9476 | { | |
9477 | first = FALSE; | |
9478 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9479 | { | |
b5e4a23d | 9480 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
9481 | } |
9482 | else | |
9483 | { | |
b5e4a23d | 9484 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 9485 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 9486 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 9487 | } |
b5e4a23d BW |
9488 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
9489 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 9490 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
9491 | fragP->tc_frag_data.is_insn = TRUE; |
9492 | size = xtensa_format_length (isa, fmt); | |
9493 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9494 | { | |
43cd72b9 | 9495 | xg_emit_insn_to_buf |
b2d179be | 9496 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
9497 | immed_instr - fragP->fr_literal + size, TRUE); |
9498 | size += xg_get_single_size (tinsn->opcode); | |
9499 | } | |
9500 | } | |
9501 | else | |
9502 | { | |
43cd72b9 | 9503 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 9504 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 9505 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 9506 | } |
e0001a05 | 9507 | immed_instr += size; |
43cd72b9 | 9508 | total_size += size; |
e0001a05 NC |
9509 | break; |
9510 | } | |
9511 | } | |
9512 | ||
9513 | diff = total_size - old_size; | |
9514 | assert (diff >= 0); | |
9515 | if (diff != 0) | |
9516 | expanded = TRUE; | |
9517 | assert (diff <= fragP->fr_var); | |
9518 | fragP->fr_var -= diff; | |
9519 | fragP->fr_fix += diff; | |
9520 | } | |
9521 | ||
e0001a05 | 9522 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 9523 | if (is_loop) |
e0001a05 NC |
9524 | { |
9525 | symbolS *sym; | |
43cd72b9 | 9526 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
9527 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9528 | { | |
9529 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9530 | return; | |
9531 | } | |
43cd72b9 | 9532 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
9533 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9534 | { | |
9535 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9536 | return; | |
9537 | } | |
9538 | } | |
9539 | ||
43cd72b9 BW |
9540 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
9541 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 9542 | |
43cd72b9 | 9543 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
9544 | { |
9545 | /* Add an expansion note on the expanded instruction. */ | |
9546 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 9547 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 9548 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
9549 | } |
9550 | } | |
9551 | ||
9552 | ||
9553 | /* Add a new fix expression into the desired segment. We have to | |
9554 | switch to that segment to do this. */ | |
9555 | ||
9556 | static fixS * | |
7fa3d080 BW |
9557 | fix_new_exp_in_seg (segT new_seg, |
9558 | subsegT new_subseg, | |
9559 | fragS *frag, | |
9560 | int where, | |
9561 | int size, | |
9562 | expressionS *exp, | |
9563 | int pcrel, | |
9564 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
9565 | { |
9566 | fixS *new_fix; | |
9567 | segT seg = now_seg; | |
9568 | subsegT subseg = now_subseg; | |
43cd72b9 | 9569 | |
e0001a05 NC |
9570 | assert (new_seg != 0); |
9571 | subseg_set (new_seg, new_subseg); | |
9572 | ||
e0001a05 NC |
9573 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
9574 | subseg_set (seg, subseg); | |
9575 | return new_fix; | |
9576 | } | |
9577 | ||
9578 | ||
43cd72b9 BW |
9579 | /* Relax a loop instruction so that it can span loop >256 bytes. |
9580 | ||
9581 | loop as, .L1 | |
9582 | .L0: | |
9583 | rsr as, LEND | |
9584 | wsr as, LBEG | |
9585 | addi as, as, lo8 (label-.L1) | |
9586 | addmi as, as, mid8 (label-.L1) | |
9587 | wsr as, LEND | |
9588 | isync | |
9589 | rsr as, LCOUNT | |
9590 | addi as, as, 1 | |
9591 | .L1: | |
9592 | <<body>> | |
9593 | label: | |
9594 | */ | |
e0001a05 NC |
9595 | |
9596 | static void | |
7fa3d080 | 9597 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
9598 | { |
9599 | TInsn loop_insn; | |
9600 | TInsn addi_insn; | |
9601 | TInsn addmi_insn; | |
9602 | unsigned long target; | |
9603 | static xtensa_insnbuf insnbuf = NULL; | |
9604 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
9605 | xtensa_isa isa = xtensa_default_isa; | |
9606 | addressT loop_offset; | |
9607 | addressT addi_offset = 9; | |
9608 | addressT addmi_offset = 12; | |
43cd72b9 | 9609 | fragS *next_fragP; |
d77b99c9 | 9610 | int target_count; |
e0001a05 NC |
9611 | |
9612 | if (!insnbuf) | |
9613 | insnbuf = xtensa_insnbuf_alloc (isa); | |
9614 | ||
9615 | /* Get the loop offset. */ | |
43cd72b9 | 9616 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 9617 | |
43cd72b9 BW |
9618 | /* Validate that there really is a LOOP at the loop_offset. Because |
9619 | loops are not bundleable, we can assume that the instruction will be | |
9620 | in slot 0. */ | |
9621 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
9622 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
9623 | ||
9624 | assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); | |
e0001a05 NC |
9625 | addi_offset += loop_offset; |
9626 | addmi_offset += loop_offset; | |
9627 | ||
43cd72b9 | 9628 | assert (tinsn->ntok == 2); |
b08b5071 BW |
9629 | if (tinsn->tok[1].X_op == O_constant) |
9630 | target = tinsn->tok[1].X_add_number; | |
9631 | else if (tinsn->tok[1].X_op == O_symbol) | |
9632 | { | |
9633 | /* Find the fragment. */ | |
9634 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9635 | assert (S_GET_SEGMENT (sym) == segP | |
9636 | || S_GET_SEGMENT (sym) == absolute_section); | |
9637 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
9638 | } | |
9639 | else | |
9640 | { | |
9641 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
9642 | target = 0; | |
9643 | } | |
e0001a05 | 9644 | |
e0001a05 NC |
9645 | loop_length = target - (fragP->fr_address + fragP->fr_fix); |
9646 | loop_length_hi = loop_length & ~0x0ff; | |
9647 | loop_length_lo = loop_length & 0x0ff; | |
9648 | if (loop_length_lo >= 128) | |
9649 | { | |
9650 | loop_length_lo -= 256; | |
9651 | loop_length_hi += 256; | |
9652 | } | |
9653 | ||
43cd72b9 | 9654 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
9655 | 32512. If the loop is larger than that, then we just fail. */ |
9656 | if (loop_length_hi > 32512) | |
9657 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9658 | _("loop too long for LOOP instruction")); | |
9659 | ||
43cd72b9 | 9660 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
e0001a05 NC |
9661 | assert (addi_insn.opcode == xtensa_addi_opcode); |
9662 | ||
43cd72b9 | 9663 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
e0001a05 NC |
9664 | assert (addmi_insn.opcode == xtensa_addmi_opcode); |
9665 | ||
9666 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
9667 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 9668 | |
e0001a05 | 9669 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
9670 | xtensa_insnbuf_to_chars |
9671 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
9672 | |
9673 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
9674 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
9675 | xtensa_insnbuf_to_chars |
9676 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
9677 | |
9678 | /* Walk through all of the frags from here to the loop end | |
9679 | and mark them as no_transform to keep them from being modified | |
9680 | by the linker. If we ever have a relocation for the | |
9681 | addi/addmi of the difference of two symbols we can remove this. */ | |
9682 | ||
9683 | target_count = 0; | |
9684 | for (next_fragP = fragP; next_fragP != NULL; | |
9685 | next_fragP = next_fragP->fr_next) | |
9686 | { | |
b08b5071 | 9687 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
9688 | if (next_fragP->tc_frag_data.is_loop_target) |
9689 | target_count++; | |
9690 | if (target_count == 2) | |
9691 | break; | |
9692 | } | |
e0001a05 NC |
9693 | } |
9694 | ||
b08b5071 BW |
9695 | \f |
9696 | /* A map that keeps information on a per-subsegment basis. This is | |
9697 | maintained during initial assembly, but is invalid once the | |
9698 | subsegments are smashed together. I.E., it cannot be used during | |
9699 | the relaxation. */ | |
e0001a05 | 9700 | |
b08b5071 | 9701 | typedef struct subseg_map_struct |
e0001a05 | 9702 | { |
b08b5071 BW |
9703 | /* the key */ |
9704 | segT seg; | |
9705 | subsegT subseg; | |
e0001a05 | 9706 | |
b08b5071 BW |
9707 | /* the data */ |
9708 | unsigned flags; | |
9709 | float total_freq; /* fall-through + branch target frequency */ | |
9710 | float target_freq; /* branch target frequency alone */ | |
9711 | ||
9712 | struct subseg_map_struct *next; | |
9713 | } subseg_map; | |
e0001a05 | 9714 | |
e0001a05 | 9715 | |
e0001a05 NC |
9716 | static subseg_map *sseg_map = NULL; |
9717 | ||
43cd72b9 | 9718 | static subseg_map * |
7fa3d080 | 9719 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
9720 | { |
9721 | subseg_map *subseg_e; | |
9722 | ||
9723 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 9724 | { |
43cd72b9 | 9725 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 9726 | break; |
e0001a05 | 9727 | } |
b08b5071 BW |
9728 | return subseg_e; |
9729 | } | |
9730 | ||
9731 | ||
9732 | static subseg_map * | |
9733 | add_subseg_info (segT seg, subsegT subseg) | |
9734 | { | |
9735 | subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); | |
43cd72b9 BW |
9736 | memset (subseg_e, 0, sizeof (subseg_map)); |
9737 | subseg_e->seg = seg; | |
9738 | subseg_e->subseg = subseg; | |
9739 | subseg_e->flags = 0; | |
9740 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
9741 | subseg_e->target_freq = 1.0; |
9742 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
9743 | subseg_e->next = sseg_map; |
9744 | sseg_map = subseg_e; | |
43cd72b9 BW |
9745 | return subseg_e; |
9746 | } | |
e0001a05 | 9747 | |
7fa3d080 BW |
9748 | |
9749 | static unsigned | |
9750 | get_last_insn_flags (segT seg, subsegT subseg) | |
9751 | { | |
9752 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9753 | if (subseg_e) |
9754 | return subseg_e->flags; | |
9755 | return 0; | |
7fa3d080 BW |
9756 | } |
9757 | ||
9758 | ||
43cd72b9 | 9759 | static void |
7fa3d080 BW |
9760 | set_last_insn_flags (segT seg, |
9761 | subsegT subseg, | |
9762 | unsigned fl, | |
9763 | bfd_boolean val) | |
43cd72b9 BW |
9764 | { |
9765 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9766 | if (! subseg_e) |
9767 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
9768 | if (val) |
9769 | subseg_e->flags |= fl; | |
9770 | else | |
9771 | subseg_e->flags &= ~fl; | |
9772 | } | |
9773 | ||
b08b5071 BW |
9774 | |
9775 | static float | |
9776 | get_subseg_total_freq (segT seg, subsegT subseg) | |
9777 | { | |
9778 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9779 | if (subseg_e) | |
9780 | return subseg_e->total_freq; | |
9781 | return 1.0; | |
9782 | } | |
9783 | ||
9784 | ||
9785 | static float | |
9786 | get_subseg_target_freq (segT seg, subsegT subseg) | |
9787 | { | |
9788 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9789 | if (subseg_e) | |
9790 | return subseg_e->target_freq; | |
9791 | return 1.0; | |
9792 | } | |
9793 | ||
9794 | ||
9795 | static void | |
9796 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
9797 | { | |
9798 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9799 | if (! subseg_e) | |
9800 | subseg_e = add_subseg_info (seg, subseg); | |
9801 | subseg_e->total_freq = total_f; | |
9802 | subseg_e->target_freq = target_f; | |
9803 | } | |
9804 | ||
e0001a05 NC |
9805 | \f |
9806 | /* Segment Lists and emit_state Stuff. */ | |
9807 | ||
e0001a05 | 9808 | static void |
7fa3d080 | 9809 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
9810 | { |
9811 | head = head->next; | |
9812 | while (head) | |
9813 | { | |
9814 | segT literal_section = head->seg; | |
9815 | ||
9816 | /* Move the literal section to the front of the section list. */ | |
9817 | assert (literal_section); | |
69852798 AM |
9818 | if (literal_section != stdoutput->sections) |
9819 | { | |
9820 | bfd_section_list_remove (stdoutput, literal_section); | |
9821 | bfd_section_list_prepend (stdoutput, literal_section); | |
9822 | } | |
e0001a05 NC |
9823 | head = head->next; |
9824 | } | |
9825 | } | |
9826 | ||
9827 | ||
7fa3d080 BW |
9828 | static void mark_literal_frags (seg_list *); |
9829 | ||
9830 | static void | |
9831 | xtensa_move_literals (void) | |
e0001a05 NC |
9832 | { |
9833 | seg_list *segment; | |
9834 | frchainS *frchain_from, *frchain_to; | |
9835 | fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after; | |
9836 | fragS **frag_splice; | |
9837 | emit_state state; | |
9838 | segT dest_seg; | |
9839 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 9840 | sym_list *lit; |
e0001a05 | 9841 | |
a7877748 | 9842 | mark_literal_frags (literal_head->next); |
e0001a05 NC |
9843 | |
9844 | if (use_literal_section) | |
9845 | return; | |
9846 | ||
74869ac7 | 9847 | for (segment = literal_head->next; segment; segment = segment->next) |
e0001a05 | 9848 | { |
74869ac7 BW |
9849 | /* Keep the literals for .init and .fini in separate sections. */ |
9850 | if (!strcmp (segment_name (segment->seg), INIT_SECTION_NAME) | |
9851 | || !strcmp (segment_name (segment->seg), FINI_SECTION_NAME)) | |
9852 | continue; | |
9853 | ||
e0001a05 NC |
9854 | frchain_from = seg_info (segment->seg)->frchainP; |
9855 | search_frag = frchain_from->frch_root; | |
9856 | literal_pool = NULL; | |
9857 | frchain_to = NULL; | |
9858 | frag_splice = &(frchain_from->frch_root); | |
9859 | ||
9860 | while (!search_frag->tc_frag_data.literal_frag) | |
9861 | { | |
9862 | assert (search_frag->fr_fix == 0 | |
9863 | || search_frag->fr_type == rs_align); | |
9864 | search_frag = search_frag->fr_next; | |
9865 | } | |
9866 | ||
9867 | assert (search_frag->tc_frag_data.literal_frag->fr_subtype | |
9868 | == RELAX_LITERAL_POOL_BEGIN); | |
9869 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
9870 | ||
9871 | /* Make sure that all the frags in this series are closed, and | |
9872 | that there is at least one left over of zero-size. This | |
9873 | prevents us from making a segment with an frchain without any | |
9874 | frags in it. */ | |
9875 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9876 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
9877 | last_frag = frag_now; |
9878 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9879 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 9880 | |
43cd72b9 | 9881 | while (search_frag != frag_now) |
e0001a05 NC |
9882 | { |
9883 | next_frag = search_frag->fr_next; | |
9884 | ||
43cd72b9 | 9885 | /* First, move the frag out of the literal section and |
e0001a05 NC |
9886 | to the appropriate place. */ |
9887 | if (search_frag->tc_frag_data.literal_frag) | |
9888 | { | |
9889 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9890 | assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); | |
dd49a749 BW |
9891 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9892 | assert (frchain_to); | |
e0001a05 | 9893 | } |
c48aaca0 | 9894 | insert_after = literal_pool->tc_frag_data.literal_frag; |
dd49a749 | 9895 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
43cd72b9 | 9896 | |
e0001a05 NC |
9897 | *frag_splice = next_frag; |
9898 | search_frag->fr_next = insert_after->fr_next; | |
9899 | insert_after->fr_next = search_frag; | |
9900 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
c48aaca0 | 9901 | literal_pool->tc_frag_data.literal_frag = search_frag; |
e0001a05 NC |
9902 | |
9903 | /* Now move any fixups associated with this frag to the | |
9904 | right section. */ | |
9905 | fix = frchain_from->fix_root; | |
9906 | fix_splice = &(frchain_from->fix_root); | |
9907 | while (fix) | |
9908 | { | |
9909 | next_fix = fix->fx_next; | |
9910 | if (fix->fx_frag == search_frag) | |
9911 | { | |
9912 | *fix_splice = next_fix; | |
9913 | fix->fx_next = frchain_to->fix_root; | |
9914 | frchain_to->fix_root = fix; | |
9915 | if (frchain_to->fix_tail == NULL) | |
9916 | frchain_to->fix_tail = fix; | |
9917 | } | |
9918 | else | |
9919 | fix_splice = &(fix->fx_next); | |
9920 | fix = next_fix; | |
9921 | } | |
9922 | search_frag = next_frag; | |
9923 | } | |
9924 | ||
9925 | if (frchain_from->fix_root != NULL) | |
9926 | { | |
9927 | frchain_from = seg_info (segment->seg)->frchainP; | |
9928 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
9929 | ||
9930 | assert (frchain_from->fix_root == NULL); | |
9931 | } | |
9932 | frchain_from->fix_tail = NULL; | |
9933 | xtensa_restore_emit_state (&state); | |
e0001a05 NC |
9934 | } |
9935 | ||
82e7541d BW |
9936 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
9937 | for (lit = literal_syms; lit; lit = lit->next) | |
9938 | { | |
9939 | symbolS *lit_sym = lit->sym; | |
9940 | segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; | |
43cd72b9 BW |
9941 | if (dest_seg) |
9942 | S_SET_SEGMENT (lit_sym, dest_seg); | |
82e7541d | 9943 | } |
e0001a05 NC |
9944 | } |
9945 | ||
9946 | ||
a7877748 BW |
9947 | /* Walk over all the frags for segments in a list and mark them as |
9948 | containing literals. As clunky as this is, we can't rely on frag_var | |
9949 | and frag_variant to get called in all situations. */ | |
9950 | ||
9951 | static void | |
7fa3d080 | 9952 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
9953 | { |
9954 | frchainS *frchain_from; | |
9955 | fragS *search_frag; | |
9956 | ||
9957 | while (segment) | |
9958 | { | |
9959 | frchain_from = seg_info (segment->seg)->frchainP; | |
9960 | search_frag = frchain_from->frch_root; | |
c138bc38 | 9961 | while (search_frag) |
a7877748 BW |
9962 | { |
9963 | search_frag->tc_frag_data.is_literal = TRUE; | |
9964 | search_frag = search_frag->fr_next; | |
9965 | } | |
9966 | segment = segment->next; | |
9967 | } | |
9968 | } | |
9969 | ||
9970 | ||
e0001a05 | 9971 | static void |
7fa3d080 | 9972 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
9973 | { |
9974 | /* Move all of the sections in the section list to come | |
9975 | after "after" in the gnu segment list. */ | |
9976 | ||
9977 | head = head->next; | |
9978 | while (head) | |
9979 | { | |
9980 | segT literal_section = head->seg; | |
9981 | ||
9982 | /* Move the literal section after "after". */ | |
9983 | assert (literal_section); | |
9984 | if (literal_section != after) | |
9985 | { | |
69852798 AM |
9986 | bfd_section_list_remove (stdoutput, literal_section); |
9987 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
9988 | } |
9989 | ||
9990 | head = head->next; | |
9991 | } | |
9992 | } | |
9993 | ||
9994 | ||
9995 | /* Push all the literal segments to the end of the gnu list. */ | |
9996 | ||
7fa3d080 BW |
9997 | static void |
9998 | xtensa_reorder_segments (void) | |
e0001a05 NC |
9999 | { |
10000 | segT sec; | |
b08b5071 | 10001 | segT last_sec = 0; |
e0001a05 NC |
10002 | int old_count = 0; |
10003 | int new_count = 0; | |
10004 | ||
10005 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
10006 | { |
10007 | last_sec = sec; | |
10008 | old_count++; | |
10009 | } | |
e0001a05 NC |
10010 | |
10011 | /* Now that we have the last section, push all the literal | |
10012 | sections to the end. */ | |
e0001a05 | 10013 | xtensa_reorder_seg_list (literal_head, last_sec); |
e0001a05 NC |
10014 | |
10015 | /* Now perform the final error check. */ | |
10016 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
10017 | new_count++; | |
10018 | assert (new_count == old_count); | |
10019 | } | |
10020 | ||
10021 | ||
e0001a05 NC |
10022 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
10023 | correct location. Return a emit_state which can be passed to | |
10024 | xtensa_restore_emit_state to return to current fragment. */ | |
10025 | ||
7fa3d080 BW |
10026 | static void |
10027 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
10028 | { |
10029 | if (directive_state[directive_absolute_literals]) | |
10030 | { | |
74869ac7 BW |
10031 | segT lit4_seg = cache_literal_section (TRUE); |
10032 | xtensa_switch_section_emit_state (result, lit4_seg, 0); | |
43cd72b9 BW |
10033 | } |
10034 | else | |
10035 | xtensa_switch_to_non_abs_literal_fragment (result); | |
10036 | ||
10037 | /* Do a 4-byte align here. */ | |
10038 | frag_align (2, 0, 0); | |
10039 | record_alignment (now_seg, 2); | |
10040 | } | |
10041 | ||
10042 | ||
7fa3d080 BW |
10043 | static void |
10044 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 | 10045 | { |
e0001a05 NC |
10046 | static bfd_boolean recursive = FALSE; |
10047 | fragS *pool_location = get_literal_pool_location (now_seg); | |
74869ac7 | 10048 | segT lit_seg; |
c138bc38 | 10049 | bfd_boolean is_init = |
e0001a05 | 10050 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); |
c138bc38 | 10051 | bfd_boolean is_fini = |
e0001a05 | 10052 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); |
e0001a05 | 10053 | |
43cd72b9 BW |
10054 | if (pool_location == NULL |
10055 | && !use_literal_section | |
e0001a05 NC |
10056 | && !recursive |
10057 | && !is_init && ! is_fini) | |
10058 | { | |
43cd72b9 | 10059 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); |
74869ac7 BW |
10060 | |
10061 | /* When we mark a literal pool location, we want to put a frag in | |
10062 | the literal pool that points to it. But to do that, we want to | |
10063 | switch_to_literal_fragment. But literal sections don't have | |
10064 | literal pools, so their location is always null, so we would | |
10065 | recurse forever. This is kind of hacky, but it works. */ | |
10066 | ||
e0001a05 | 10067 | recursive = TRUE; |
61846f28 | 10068 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
10069 | recursive = FALSE; |
10070 | } | |
10071 | ||
74869ac7 BW |
10072 | lit_seg = cache_literal_section (FALSE); |
10073 | xtensa_switch_section_emit_state (result, lit_seg, 0); | |
e0001a05 | 10074 | |
43cd72b9 BW |
10075 | if (!use_literal_section |
10076 | && !is_init && !is_fini | |
10077 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
10078 | { |
10079 | /* Close whatever frag is there. */ | |
10080 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10081 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
10082 | frag_now->tc_frag_data.literal_frag = pool_location; |
10083 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10084 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 10085 | } |
e0001a05 NC |
10086 | } |
10087 | ||
10088 | ||
10089 | /* Call this function before emitting data into the literal section. | |
10090 | This is a helper function for xtensa_switch_to_literal_fragment. | |
10091 | This is similar to a .section new_now_seg subseg. */ | |
10092 | ||
7fa3d080 BW |
10093 | static void |
10094 | xtensa_switch_section_emit_state (emit_state *state, | |
10095 | segT new_now_seg, | |
10096 | subsegT new_now_subseg) | |
e0001a05 NC |
10097 | { |
10098 | state->name = now_seg->name; | |
10099 | state->now_seg = now_seg; | |
10100 | state->now_subseg = now_subseg; | |
10101 | state->generating_literals = generating_literals; | |
10102 | generating_literals++; | |
2b0210eb | 10103 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
10104 | } |
10105 | ||
10106 | ||
10107 | /* Use to restore the emitting into the normal place. */ | |
10108 | ||
7fa3d080 BW |
10109 | static void |
10110 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
10111 | { |
10112 | generating_literals = state->generating_literals; | |
2b0210eb | 10113 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
10114 | } |
10115 | ||
10116 | ||
74869ac7 | 10117 | /* Predicate function used to look up a section in a particular group. */ |
e0001a05 | 10118 | |
74869ac7 BW |
10119 | static bfd_boolean |
10120 | match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) | |
e0001a05 | 10121 | { |
74869ac7 BW |
10122 | const char *gname = inf; |
10123 | const char *group_name = elf_group_name (sec); | |
10124 | ||
10125 | return (group_name == gname | |
10126 | || (group_name != NULL | |
10127 | && gname != NULL | |
10128 | && strcmp (group_name, gname) == 0)); | |
10129 | } | |
e0001a05 | 10130 | |
e0001a05 | 10131 | |
74869ac7 BW |
10132 | /* Get the literal section to be used for the current text section. |
10133 | The result may be cached in the default_lit_sections structure. */ | |
10134 | ||
10135 | static segT | |
10136 | cache_literal_section (bfd_boolean use_abs_literals) | |
10137 | { | |
10138 | const char *text_name, *group_name = 0; | |
10139 | char *base_name, *name, *suffix; | |
10140 | segT *pcached; | |
10141 | segT seg, current_section; | |
10142 | int current_subsec; | |
10143 | bfd_boolean linkonce = FALSE; | |
10144 | ||
10145 | /* Save the current section/subsection. */ | |
10146 | current_section = now_seg; | |
10147 | current_subsec = now_subseg; | |
10148 | ||
10149 | /* Clear the cached values if they are no longer valid. */ | |
10150 | if (now_seg != default_lit_sections.current_text_seg) | |
b08b5071 | 10151 | { |
74869ac7 BW |
10152 | default_lit_sections.current_text_seg = now_seg; |
10153 | default_lit_sections.lit_seg = NULL; | |
10154 | default_lit_sections.lit4_seg = NULL; | |
10155 | } | |
10156 | ||
10157 | /* Check if the literal section is already cached. */ | |
10158 | if (use_abs_literals) | |
10159 | pcached = &default_lit_sections.lit4_seg; | |
10160 | else | |
10161 | pcached = &default_lit_sections.lit_seg; | |
10162 | ||
10163 | if (*pcached) | |
10164 | return *pcached; | |
10165 | ||
10166 | text_name = default_lit_sections.lit_prefix; | |
10167 | if (! text_name || ! *text_name) | |
10168 | { | |
10169 | text_name = segment_name (current_section); | |
10170 | group_name = elf_group_name (current_section); | |
10171 | linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; | |
10172 | } | |
10173 | ||
10174 | base_name = use_abs_literals ? ".lit4" : ".literal"; | |
10175 | if (group_name) | |
10176 | { | |
10177 | name = xmalloc (strlen (base_name) + strlen (group_name) + 2); | |
10178 | sprintf (name, "%s.%s", base_name, group_name); | |
10179 | } | |
10180 | else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) | |
10181 | { | |
10182 | suffix = strchr (text_name + linkonce_len, '.'); | |
10183 | ||
10184 | name = xmalloc (linkonce_len + strlen (base_name) + 1 | |
10185 | + (suffix ? strlen (suffix) : 0)); | |
10186 | strcpy (name, ".gnu.linkonce"); | |
10187 | strcat (name, base_name); | |
10188 | if (suffix) | |
10189 | strcat (name, suffix); | |
10190 | linkonce = TRUE; | |
10191 | } | |
10192 | else | |
10193 | { | |
10194 | /* If the section name ends with ".text", then replace that suffix | |
10195 | instead of appending an additional suffix. */ | |
10196 | size_t len = strlen (text_name); | |
10197 | if (len >= 5 && strcmp (text_name + len - 5, ".text") == 0) | |
10198 | len -= 5; | |
10199 | ||
10200 | name = xmalloc (len + strlen (base_name) + 1); | |
10201 | strcpy (name, text_name); | |
10202 | strcpy (name + len, base_name); | |
b08b5071 | 10203 | } |
e0001a05 | 10204 | |
74869ac7 BW |
10205 | /* Canonicalize section names to allow renaming literal sections. |
10206 | The group name, if any, came from the current text section and | |
10207 | has already been canonicalized. */ | |
10208 | name = tc_canonicalize_symbol_name (name); | |
10209 | ||
10210 | seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, | |
10211 | (void *) group_name); | |
10212 | if (! seg) | |
e0001a05 | 10213 | { |
74869ac7 BW |
10214 | flagword flags; |
10215 | ||
10216 | seg = subseg_force_new (name, 0); | |
10217 | ||
10218 | if (! use_abs_literals) | |
b08b5071 | 10219 | { |
74869ac7 | 10220 | /* Add the newly created literal segment to the list. */ |
b08b5071 BW |
10221 | seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); |
10222 | n->seg = seg; | |
74869ac7 BW |
10223 | n->next = literal_head->next; |
10224 | literal_head->next = n; | |
b08b5071 | 10225 | } |
74869ac7 BW |
10226 | |
10227 | flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD | |
10228 | | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) | |
10229 | | (use_abs_literals ? SEC_DATA : SEC_CODE)); | |
10230 | ||
10231 | elf_group_name (seg) = group_name; | |
10232 | ||
10233 | bfd_set_section_flags (stdoutput, seg, flags); | |
b08b5071 | 10234 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
10235 | } |
10236 | ||
74869ac7 | 10237 | *pcached = seg; |
b08b5071 | 10238 | subseg_set (current_section, current_subsec); |
74869ac7 | 10239 | return seg; |
e0001a05 NC |
10240 | } |
10241 | ||
43cd72b9 BW |
10242 | \f |
10243 | /* Property Tables Stuff. */ | |
10244 | ||
7fa3d080 BW |
10245 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
10246 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
10247 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
10248 | ||
10249 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
10250 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
10251 | ||
b08b5071 | 10252 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
10253 | static void xtensa_create_property_segments |
10254 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
10255 | static void xtensa_create_xproperty_segments | |
10256 | (frag_flags_fn, const char *, xt_section_type); | |
10257 | static segment_info_type *retrieve_segment_info (segT); | |
7fa3d080 BW |
10258 | static bfd_boolean section_has_property (segT, frag_predicate); |
10259 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
10260 | static void add_xt_block_frags | |
10261 | (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate); | |
10262 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); | |
10263 | static void xtensa_frag_flags_init (frag_flags *); | |
10264 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
10265 | static bfd_vma frag_flags_to_number (const frag_flags *); | |
10266 | static void add_xt_prop_frags | |
10267 | (segT, segT, xtensa_block_info **, frag_flags_fn); | |
10268 | ||
10269 | /* Set up property tables after relaxation. */ | |
10270 | ||
10271 | void | |
10272 | xtensa_post_relax_hook (void) | |
10273 | { | |
10274 | xtensa_move_seg_list_to_beginning (literal_head); | |
7fa3d080 BW |
10275 | |
10276 | xtensa_find_unmarked_state_frags (); | |
99ded152 | 10277 | xtensa_mark_frags_for_org (); |
6a7eedfe | 10278 | xtensa_mark_difference_of_two_symbols (); |
7fa3d080 | 10279 | |
b29757dc BW |
10280 | xtensa_create_property_segments (get_frag_is_literal, |
10281 | NULL, | |
10282 | XTENSA_LIT_SEC_NAME, | |
10283 | xt_literal_sec); | |
7fa3d080 BW |
10284 | xtensa_create_xproperty_segments (get_frag_property_flags, |
10285 | XTENSA_PROP_SEC_NAME, | |
10286 | xt_prop_sec); | |
10287 | ||
10288 | if (warn_unaligned_branch_targets) | |
10289 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
10290 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
10291 | } | |
10292 | ||
10293 | ||
43cd72b9 BW |
10294 | /* This function is only meaningful after xtensa_move_literals. */ |
10295 | ||
10296 | static bfd_boolean | |
7fa3d080 | 10297 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 BW |
10298 | { |
10299 | assert (fragP != NULL); | |
10300 | return fragP->tc_frag_data.is_literal; | |
10301 | } | |
10302 | ||
10303 | ||
43cd72b9 | 10304 | static void |
7fa3d080 BW |
10305 | xtensa_create_property_segments (frag_predicate property_function, |
10306 | frag_predicate end_property_function, | |
10307 | const char *section_name_base, | |
10308 | xt_section_type sec_type) | |
43cd72b9 BW |
10309 | { |
10310 | segT *seclist; | |
10311 | ||
10312 | /* Walk over all of the current segments. | |
10313 | Walk over each fragment | |
10314 | For each non-empty fragment, | |
10315 | Build a property record (append where possible). */ | |
10316 | ||
10317 | for (seclist = &stdoutput->sections; | |
10318 | seclist && *seclist; | |
10319 | seclist = &(*seclist)->next) | |
10320 | { | |
10321 | segT sec = *seclist; | |
10322 | flagword flags; | |
10323 | ||
10324 | flags = bfd_get_section_flags (stdoutput, sec); | |
10325 | if (flags & SEC_DEBUGGING) | |
10326 | continue; | |
10327 | if (!(flags & SEC_ALLOC)) | |
10328 | continue; | |
10329 | ||
10330 | if (section_has_property (sec, property_function)) | |
10331 | { | |
74869ac7 BW |
10332 | segT insn_sec = |
10333 | xtensa_get_property_section (sec, section_name_base); | |
43cd72b9 BW |
10334 | segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); |
10335 | xtensa_block_info **xt_blocks = | |
10336 | &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10337 | /* Walk over all of the frchains here and add new sections. */ | |
10338 | add_xt_block_frags (sec, insn_sec, xt_blocks, property_function, | |
10339 | end_property_function); | |
10340 | } | |
10341 | } | |
10342 | ||
10343 | /* Now we fill them out.... */ | |
10344 | ||
10345 | for (seclist = &stdoutput->sections; | |
10346 | seclist && *seclist; | |
10347 | seclist = &(*seclist)->next) | |
10348 | { | |
10349 | segment_info_type *seginfo; | |
10350 | xtensa_block_info *block; | |
10351 | segT sec = *seclist; | |
10352 | ||
10353 | seginfo = seg_info (sec); | |
10354 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10355 | ||
10356 | if (block) | |
10357 | { | |
10358 | xtensa_block_info *cur_block; | |
10359 | /* This is a section with some data. */ | |
10360 | int num_recs = 0; | |
d77b99c9 | 10361 | bfd_size_type rec_size; |
43cd72b9 BW |
10362 | |
10363 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10364 | num_recs++; | |
10365 | ||
10366 | rec_size = num_recs * 8; | |
10367 | bfd_set_section_size (stdoutput, sec, rec_size); | |
10368 | ||
10369 | /* In order to make this work with the assembler, we have to | |
10370 | build some frags and then build the "fixups" for it. It | |
10371 | would be easier to just set the contents then set the | |
10372 | arlents. */ | |
10373 | ||
10374 | if (num_recs) | |
10375 | { | |
10376 | /* Allocate a fragment and leak it. */ | |
10377 | fragS *fragP; | |
d77b99c9 | 10378 | bfd_size_type frag_size; |
43cd72b9 BW |
10379 | fixS *fixes; |
10380 | frchainS *frchainP; | |
10381 | int i; | |
10382 | char *frag_data; | |
10383 | ||
10384 | frag_size = sizeof (fragS) + rec_size; | |
10385 | fragP = (fragS *) xmalloc (frag_size); | |
e0001a05 | 10386 | |
43cd72b9 BW |
10387 | memset (fragP, 0, frag_size); |
10388 | fragP->fr_address = 0; | |
10389 | fragP->fr_next = NULL; | |
10390 | fragP->fr_fix = rec_size; | |
10391 | fragP->fr_var = 0; | |
10392 | fragP->fr_type = rs_fill; | |
10393 | /* The rest are zeros. */ | |
e0001a05 | 10394 | |
43cd72b9 BW |
10395 | frchainP = seginfo->frchainP; |
10396 | frchainP->frch_root = fragP; | |
10397 | frchainP->frch_last = fragP; | |
e0001a05 | 10398 | |
43cd72b9 BW |
10399 | fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); |
10400 | memset (fixes, 0, sizeof (fixS) * num_recs); | |
e0001a05 | 10401 | |
43cd72b9 BW |
10402 | seginfo->fix_root = fixes; |
10403 | seginfo->fix_tail = &fixes[num_recs - 1]; | |
10404 | cur_block = block; | |
10405 | frag_data = &fragP->fr_literal[0]; | |
10406 | for (i = 0; i < num_recs; i++) | |
10407 | { | |
10408 | fixS *fix = &fixes[i]; | |
10409 | assert (cur_block); | |
e0001a05 | 10410 | |
43cd72b9 BW |
10411 | /* Write the fixup. */ |
10412 | if (i != num_recs - 1) | |
10413 | fix->fx_next = &fixes[i + 1]; | |
10414 | else | |
10415 | fix->fx_next = NULL; | |
10416 | fix->fx_size = 4; | |
10417 | fix->fx_done = 0; | |
10418 | fix->fx_frag = fragP; | |
10419 | fix->fx_where = i * 8; | |
10420 | fix->fx_addsy = section_symbol (cur_block->sec); | |
10421 | fix->fx_offset = cur_block->offset; | |
10422 | fix->fx_r_type = BFD_RELOC_32; | |
10423 | fix->fx_file = "Internal Assembly"; | |
10424 | fix->fx_line = 0; | |
e0001a05 | 10425 | |
43cd72b9 BW |
10426 | /* Write the length. */ |
10427 | md_number_to_chars (&frag_data[4 + 8 * i], | |
10428 | cur_block->size, 4); | |
10429 | cur_block = cur_block->next; | |
10430 | } | |
10431 | } | |
10432 | } | |
10433 | } | |
e0001a05 NC |
10434 | } |
10435 | ||
10436 | ||
7fa3d080 BW |
10437 | static void |
10438 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
10439 | const char *section_name_base, | |
10440 | xt_section_type sec_type) | |
e0001a05 NC |
10441 | { |
10442 | segT *seclist; | |
10443 | ||
10444 | /* Walk over all of the current segments. | |
43cd72b9 BW |
10445 | Walk over each fragment. |
10446 | For each fragment that has instructions, | |
10447 | build an instruction record (append where possible). */ | |
e0001a05 NC |
10448 | |
10449 | for (seclist = &stdoutput->sections; | |
10450 | seclist && *seclist; | |
10451 | seclist = &(*seclist)->next) | |
10452 | { | |
10453 | segT sec = *seclist; | |
43cd72b9 BW |
10454 | flagword flags; |
10455 | ||
10456 | flags = bfd_get_section_flags (stdoutput, sec); | |
6624cbde BW |
10457 | if ((flags & SEC_DEBUGGING) |
10458 | || !(flags & SEC_ALLOC) | |
10459 | || (flags & SEC_MERGE)) | |
43cd72b9 BW |
10460 | continue; |
10461 | ||
10462 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 10463 | { |
74869ac7 BW |
10464 | segT insn_sec = |
10465 | xtensa_get_property_section (sec, section_name_base); | |
e0001a05 | 10466 | segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); |
43cd72b9 | 10467 | xtensa_block_info **xt_blocks = |
e0001a05 NC |
10468 | &xt_seg_info->tc_segment_info_data.blocks[sec_type]; |
10469 | /* Walk over all of the frchains here and add new sections. */ | |
43cd72b9 | 10470 | add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn); |
e0001a05 NC |
10471 | } |
10472 | } | |
10473 | ||
10474 | /* Now we fill them out.... */ | |
10475 | ||
10476 | for (seclist = &stdoutput->sections; | |
10477 | seclist && *seclist; | |
10478 | seclist = &(*seclist)->next) | |
10479 | { | |
10480 | segment_info_type *seginfo; | |
10481 | xtensa_block_info *block; | |
10482 | segT sec = *seclist; | |
43cd72b9 | 10483 | |
e0001a05 NC |
10484 | seginfo = seg_info (sec); |
10485 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10486 | ||
10487 | if (block) | |
10488 | { | |
10489 | xtensa_block_info *cur_block; | |
10490 | /* This is a section with some data. */ | |
43cd72b9 | 10491 | int num_recs = 0; |
d77b99c9 | 10492 | bfd_size_type rec_size; |
e0001a05 NC |
10493 | |
10494 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10495 | num_recs++; | |
10496 | ||
43cd72b9 | 10497 | rec_size = num_recs * (8 + 4); |
e0001a05 NC |
10498 | bfd_set_section_size (stdoutput, sec, rec_size); |
10499 | ||
43cd72b9 BW |
10500 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
10501 | ||
10502 | /* In order to make this work with the assembler, we have to build | |
10503 | some frags then build the "fixups" for it. It would be easier to | |
10504 | just set the contents then set the arlents. */ | |
e0001a05 NC |
10505 | |
10506 | if (num_recs) | |
10507 | { | |
43cd72b9 | 10508 | /* Allocate a fragment and (unfortunately) leak it. */ |
e0001a05 | 10509 | fragS *fragP; |
d77b99c9 | 10510 | bfd_size_type frag_size; |
e0001a05 NC |
10511 | fixS *fixes; |
10512 | frchainS *frchainP; | |
43cd72b9 | 10513 | int i; |
e0001a05 NC |
10514 | char *frag_data; |
10515 | ||
10516 | frag_size = sizeof (fragS) + rec_size; | |
10517 | fragP = (fragS *) xmalloc (frag_size); | |
10518 | ||
10519 | memset (fragP, 0, frag_size); | |
10520 | fragP->fr_address = 0; | |
10521 | fragP->fr_next = NULL; | |
10522 | fragP->fr_fix = rec_size; | |
10523 | fragP->fr_var = 0; | |
10524 | fragP->fr_type = rs_fill; | |
43cd72b9 | 10525 | /* The rest are zeros. */ |
e0001a05 NC |
10526 | |
10527 | frchainP = seginfo->frchainP; | |
10528 | frchainP->frch_root = fragP; | |
10529 | frchainP->frch_last = fragP; | |
10530 | ||
10531 | fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); | |
10532 | memset (fixes, 0, sizeof (fixS) * num_recs); | |
10533 | ||
10534 | seginfo->fix_root = fixes; | |
10535 | seginfo->fix_tail = &fixes[num_recs - 1]; | |
10536 | cur_block = block; | |
10537 | frag_data = &fragP->fr_literal[0]; | |
10538 | for (i = 0; i < num_recs; i++) | |
10539 | { | |
10540 | fixS *fix = &fixes[i]; | |
10541 | assert (cur_block); | |
10542 | ||
10543 | /* Write the fixup. */ | |
10544 | if (i != num_recs - 1) | |
10545 | fix->fx_next = &fixes[i + 1]; | |
10546 | else | |
10547 | fix->fx_next = NULL; | |
10548 | fix->fx_size = 4; | |
10549 | fix->fx_done = 0; | |
10550 | fix->fx_frag = fragP; | |
43cd72b9 | 10551 | fix->fx_where = i * (8 + 4); |
e0001a05 NC |
10552 | fix->fx_addsy = section_symbol (cur_block->sec); |
10553 | fix->fx_offset = cur_block->offset; | |
10554 | fix->fx_r_type = BFD_RELOC_32; | |
10555 | fix->fx_file = "Internal Assembly"; | |
10556 | fix->fx_line = 0; | |
10557 | ||
10558 | /* Write the length. */ | |
43cd72b9 | 10559 | md_number_to_chars (&frag_data[4 + (8+4) * i], |
e0001a05 | 10560 | cur_block->size, 4); |
43cd72b9 BW |
10561 | md_number_to_chars (&frag_data[8 + (8+4) * i], |
10562 | frag_flags_to_number (&cur_block->flags), | |
10563 | 4); | |
e0001a05 NC |
10564 | cur_block = cur_block->next; |
10565 | } | |
10566 | } | |
10567 | } | |
10568 | } | |
10569 | } | |
10570 | ||
10571 | ||
7fa3d080 BW |
10572 | static segment_info_type * |
10573 | retrieve_segment_info (segT seg) | |
e0001a05 NC |
10574 | { |
10575 | segment_info_type *seginfo; | |
10576 | seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg); | |
10577 | if (!seginfo) | |
10578 | { | |
10579 | frchainS *frchainP; | |
10580 | ||
10581 | seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo)); | |
7fa3d080 | 10582 | memset ((void *) seginfo, 0, sizeof (*seginfo)); |
e0001a05 NC |
10583 | seginfo->fix_root = NULL; |
10584 | seginfo->fix_tail = NULL; | |
10585 | seginfo->bfd_section = seg; | |
10586 | seginfo->sym = 0; | |
10587 | /* We will not be dealing with these, only our special ones. */ | |
65ec77d2 | 10588 | bfd_set_section_userdata (stdoutput, seg, (void *) seginfo); |
e0001a05 NC |
10589 | |
10590 | frchainP = (frchainS *) xmalloc (sizeof (frchainS)); | |
10591 | frchainP->frch_root = NULL; | |
10592 | frchainP->frch_last = NULL; | |
10593 | frchainP->frch_next = NULL; | |
e0001a05 NC |
10594 | frchainP->frch_subseg = 0; |
10595 | frchainP->fix_root = NULL; | |
10596 | frchainP->fix_tail = NULL; | |
10597 | /* Do not init the objstack. */ | |
10598 | /* obstack_begin (&frchainP->frch_obstack, chunksize); */ | |
10599 | /* frchainP->frch_frag_now = fragP; */ | |
10600 | frchainP->frch_frag_now = NULL; | |
10601 | ||
10602 | seginfo->frchainP = frchainP; | |
10603 | } | |
10604 | ||
10605 | return seginfo; | |
10606 | } | |
10607 | ||
10608 | ||
7fa3d080 BW |
10609 | static bfd_boolean |
10610 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
10611 | { |
10612 | segment_info_type *seginfo = seg_info (sec); | |
10613 | fragS *fragP; | |
10614 | ||
10615 | if (seginfo && seginfo->frchainP) | |
10616 | { | |
10617 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10618 | { | |
10619 | if (property_function (fragP) | |
10620 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10621 | return TRUE; | |
10622 | } | |
10623 | } | |
10624 | return FALSE; | |
10625 | } | |
10626 | ||
10627 | ||
7fa3d080 BW |
10628 | static bfd_boolean |
10629 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
10630 | { |
10631 | segment_info_type *seginfo = seg_info (sec); | |
10632 | fragS *fragP; | |
10633 | ||
10634 | if (seginfo && seginfo->frchainP) | |
10635 | { | |
10636 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10637 | { | |
10638 | frag_flags prop_flags; | |
10639 | property_function (fragP, &prop_flags); | |
10640 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
10641 | return TRUE; | |
10642 | } | |
10643 | } | |
10644 | return FALSE; | |
10645 | } | |
10646 | ||
10647 | ||
e0001a05 NC |
10648 | /* Two types of block sections exist right now: literal and insns. */ |
10649 | ||
7fa3d080 BW |
10650 | static void |
10651 | add_xt_block_frags (segT sec, | |
10652 | segT xt_block_sec, | |
10653 | xtensa_block_info **xt_block, | |
10654 | frag_predicate property_function, | |
10655 | frag_predicate end_property_function) | |
e0001a05 NC |
10656 | { |
10657 | segment_info_type *seg_info; | |
10658 | segment_info_type *xt_seg_info; | |
10659 | bfd_vma seg_offset; | |
10660 | fragS *fragP; | |
10661 | ||
10662 | xt_seg_info = retrieve_segment_info (xt_block_sec); | |
10663 | seg_info = retrieve_segment_info (sec); | |
10664 | ||
10665 | /* Build it if needed. */ | |
10666 | while (*xt_block != NULL) | |
10667 | xt_block = &(*xt_block)->next; | |
10668 | /* We are either at NULL at the beginning or at the end. */ | |
10669 | ||
10670 | /* Walk through the frags. */ | |
10671 | seg_offset = 0; | |
10672 | ||
10673 | if (seg_info->frchainP) | |
10674 | { | |
10675 | for (fragP = seg_info->frchainP->frch_root; | |
10676 | fragP; | |
10677 | fragP = fragP->fr_next) | |
10678 | { | |
10679 | if (property_function (fragP) | |
10680 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10681 | { | |
10682 | if (*xt_block != NULL) | |
10683 | { | |
10684 | if ((*xt_block)->offset + (*xt_block)->size | |
10685 | == fragP->fr_address) | |
10686 | (*xt_block)->size += fragP->fr_fix; | |
10687 | else | |
10688 | xt_block = &((*xt_block)->next); | |
10689 | } | |
10690 | if (*xt_block == NULL) | |
10691 | { | |
43cd72b9 BW |
10692 | xtensa_block_info *new_block = (xtensa_block_info *) |
10693 | xmalloc (sizeof (xtensa_block_info)); | |
10694 | new_block->sec = sec; | |
10695 | new_block->offset = fragP->fr_address; | |
10696 | new_block->size = fragP->fr_fix; | |
10697 | new_block->next = NULL; | |
10698 | xtensa_frag_flags_init (&new_block->flags); | |
10699 | *xt_block = new_block; | |
10700 | } | |
10701 | if (end_property_function | |
10702 | && end_property_function (fragP)) | |
10703 | { | |
10704 | xt_block = &((*xt_block)->next); | |
10705 | } | |
10706 | } | |
10707 | } | |
10708 | } | |
10709 | } | |
10710 | ||
10711 | ||
10712 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
10713 | ||
7fa3d080 BW |
10714 | static bfd_boolean |
10715 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
10716 | { |
10717 | if (prop_flags->is_literal | |
10718 | || prop_flags->is_insn | |
10719 | || prop_flags->is_data | |
10720 | || prop_flags->is_unreachable) | |
10721 | return FALSE; | |
10722 | return TRUE; | |
10723 | } | |
10724 | ||
10725 | ||
7fa3d080 BW |
10726 | static void |
10727 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
10728 | { |
10729 | memset (prop_flags, 0, sizeof (frag_flags)); | |
10730 | } | |
10731 | ||
10732 | ||
7fa3d080 BW |
10733 | static void |
10734 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
10735 | { |
10736 | xtensa_frag_flags_init (prop_flags); | |
10737 | if (fragP->tc_frag_data.is_literal) | |
10738 | prop_flags->is_literal = TRUE; | |
99ded152 BW |
10739 | if (fragP->tc_frag_data.is_specific_opcode |
10740 | || fragP->tc_frag_data.is_no_transform) | |
10741 | prop_flags->is_no_transform = TRUE; | |
43cd72b9 | 10742 | if (fragP->tc_frag_data.is_unreachable) |
7fa3d080 | 10743 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
10744 | else if (fragP->tc_frag_data.is_insn) |
10745 | { | |
10746 | prop_flags->is_insn = TRUE; | |
10747 | if (fragP->tc_frag_data.is_loop_target) | |
10748 | prop_flags->insn.is_loop_target = TRUE; | |
10749 | if (fragP->tc_frag_data.is_branch_target) | |
10750 | prop_flags->insn.is_branch_target = TRUE; | |
43cd72b9 BW |
10751 | if (fragP->tc_frag_data.is_no_density) |
10752 | prop_flags->insn.is_no_density = TRUE; | |
10753 | if (fragP->tc_frag_data.use_absolute_literals) | |
10754 | prop_flags->insn.is_abslit = TRUE; | |
10755 | } | |
10756 | if (fragP->tc_frag_data.is_align) | |
10757 | { | |
10758 | prop_flags->is_align = TRUE; | |
10759 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
10760 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10761 | prop_flags->is_data = TRUE; | |
10762 | } | |
10763 | } | |
10764 | ||
10765 | ||
7fa3d080 BW |
10766 | static bfd_vma |
10767 | frag_flags_to_number (const frag_flags *prop_flags) | |
43cd72b9 BW |
10768 | { |
10769 | bfd_vma num = 0; | |
10770 | if (prop_flags->is_literal) | |
10771 | num |= XTENSA_PROP_LITERAL; | |
10772 | if (prop_flags->is_insn) | |
10773 | num |= XTENSA_PROP_INSN; | |
10774 | if (prop_flags->is_data) | |
10775 | num |= XTENSA_PROP_DATA; | |
10776 | if (prop_flags->is_unreachable) | |
10777 | num |= XTENSA_PROP_UNREACHABLE; | |
10778 | if (prop_flags->insn.is_loop_target) | |
10779 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
10780 | if (prop_flags->insn.is_branch_target) | |
10781 | { | |
10782 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
10783 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
10784 | } | |
10785 | ||
10786 | if (prop_flags->insn.is_no_density) | |
10787 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
99ded152 BW |
10788 | if (prop_flags->is_no_transform) |
10789 | num |= XTENSA_PROP_NO_TRANSFORM; | |
43cd72b9 BW |
10790 | if (prop_flags->insn.is_no_reorder) |
10791 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
10792 | if (prop_flags->insn.is_abslit) | |
10793 | num |= XTENSA_PROP_INSN_ABSLIT; | |
10794 | ||
10795 | if (prop_flags->is_align) | |
10796 | { | |
10797 | num |= XTENSA_PROP_ALIGN; | |
10798 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
10799 | } | |
10800 | ||
10801 | return num; | |
10802 | } | |
10803 | ||
10804 | ||
10805 | static bfd_boolean | |
7fa3d080 BW |
10806 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
10807 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
10808 | { |
10809 | /* Cannot combine with an end marker. */ | |
10810 | ||
10811 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
10812 | return FALSE; | |
10813 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
10814 | return FALSE; | |
10815 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
10816 | return FALSE; | |
10817 | ||
10818 | if (prop_flags_1->is_insn) | |
10819 | { | |
10820 | /* Properties of the beginning of the frag. */ | |
10821 | if (prop_flags_2->insn.is_loop_target) | |
10822 | return FALSE; | |
10823 | if (prop_flags_2->insn.is_branch_target) | |
10824 | return FALSE; | |
10825 | if (prop_flags_1->insn.is_no_density != | |
10826 | prop_flags_2->insn.is_no_density) | |
10827 | return FALSE; | |
99ded152 BW |
10828 | if (prop_flags_1->is_no_transform != |
10829 | prop_flags_2->is_no_transform) | |
43cd72b9 BW |
10830 | return FALSE; |
10831 | if (prop_flags_1->insn.is_no_reorder != | |
10832 | prop_flags_2->insn.is_no_reorder) | |
10833 | return FALSE; | |
10834 | if (prop_flags_1->insn.is_abslit != | |
10835 | prop_flags_2->insn.is_abslit) | |
10836 | return FALSE; | |
10837 | } | |
10838 | ||
10839 | if (prop_flags_1->is_align) | |
10840 | return FALSE; | |
10841 | ||
10842 | return TRUE; | |
10843 | } | |
10844 | ||
10845 | ||
7fa3d080 BW |
10846 | static bfd_vma |
10847 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
10848 | { |
10849 | bfd_vma end_addr; | |
d77b99c9 | 10850 | unsigned align_bits; |
43cd72b9 BW |
10851 | |
10852 | if (!xt_block->flags.is_align) | |
10853 | return xt_block->size; | |
10854 | ||
10855 | end_addr = xt_block->offset + xt_block->size; | |
10856 | align_bits = xt_block->flags.alignment; | |
10857 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
10858 | return end_addr - xt_block->offset; | |
10859 | } | |
10860 | ||
10861 | ||
10862 | static bfd_boolean | |
7fa3d080 BW |
10863 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
10864 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
10865 | { |
10866 | if (xt_block->sec != xt_block_2->sec) | |
10867 | return FALSE; | |
10868 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
10869 | != xt_block_2->offset) | |
10870 | return FALSE; | |
10871 | ||
10872 | if (xt_block_2->size == 0 | |
10873 | && (!xt_block_2->flags.is_unreachable | |
10874 | || xt_block->flags.is_unreachable)) | |
10875 | { | |
10876 | if (xt_block_2->flags.is_align | |
10877 | && xt_block->flags.is_align) | |
10878 | { | |
10879 | /* Nothing needed. */ | |
10880 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
10881 | return TRUE; | |
10882 | } | |
10883 | else | |
10884 | { | |
10885 | if (xt_block_2->flags.is_align) | |
10886 | { | |
10887 | /* Push alignment to previous entry. */ | |
10888 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
10889 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10890 | } | |
10891 | return TRUE; | |
10892 | } | |
10893 | } | |
10894 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
10895 | &xt_block_2->flags)) | |
10896 | return FALSE; | |
10897 | ||
10898 | xt_block->size += xt_block_2->size; | |
10899 | ||
10900 | if (xt_block_2->flags.is_align) | |
10901 | { | |
10902 | xt_block->flags.is_align = TRUE; | |
10903 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10904 | } | |
10905 | ||
10906 | return TRUE; | |
10907 | } | |
10908 | ||
10909 | ||
7fa3d080 BW |
10910 | static void |
10911 | add_xt_prop_frags (segT sec, | |
10912 | segT xt_block_sec, | |
10913 | xtensa_block_info **xt_block, | |
10914 | frag_flags_fn property_function) | |
43cd72b9 BW |
10915 | { |
10916 | segment_info_type *seg_info; | |
10917 | segment_info_type *xt_seg_info; | |
10918 | bfd_vma seg_offset; | |
10919 | fragS *fragP; | |
10920 | ||
10921 | xt_seg_info = retrieve_segment_info (xt_block_sec); | |
10922 | seg_info = retrieve_segment_info (sec); | |
10923 | /* Build it if needed. */ | |
10924 | while (*xt_block != NULL) | |
10925 | { | |
10926 | xt_block = &(*xt_block)->next; | |
10927 | } | |
10928 | /* We are either at NULL at the beginning or at the end. */ | |
10929 | ||
10930 | /* Walk through the frags. */ | |
10931 | seg_offset = 0; | |
10932 | ||
10933 | if (seg_info->frchainP) | |
10934 | { | |
10935 | for (fragP = seg_info->frchainP->frch_root; fragP; | |
10936 | fragP = fragP->fr_next) | |
10937 | { | |
10938 | xtensa_block_info tmp_block; | |
10939 | tmp_block.sec = sec; | |
10940 | tmp_block.offset = fragP->fr_address; | |
10941 | tmp_block.size = fragP->fr_fix; | |
10942 | tmp_block.next = NULL; | |
10943 | property_function (fragP, &tmp_block.flags); | |
10944 | ||
10945 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
10946 | /* && fragP->fr_fix != 0) */ | |
10947 | { | |
10948 | if ((*xt_block) == NULL | |
10949 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
10950 | { | |
10951 | xtensa_block_info *new_block; | |
10952 | if ((*xt_block) != NULL) | |
10953 | xt_block = &(*xt_block)->next; | |
10954 | new_block = (xtensa_block_info *) | |
10955 | xmalloc (sizeof (xtensa_block_info)); | |
10956 | *new_block = tmp_block; | |
10957 | *xt_block = new_block; | |
10958 | } | |
10959 | } | |
10960 | } | |
10961 | } | |
10962 | } | |
10963 | ||
10964 | \f | |
10965 | /* op_placement_info_table */ | |
10966 | ||
10967 | /* op_placement_info makes it easier to determine which | |
10968 | ops can go in which slots. */ | |
10969 | ||
10970 | static void | |
7fa3d080 | 10971 | init_op_placement_info_table (void) |
43cd72b9 BW |
10972 | { |
10973 | xtensa_isa isa = xtensa_default_isa; | |
10974 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
10975 | xtensa_opcode opcode; | |
10976 | xtensa_format fmt; | |
10977 | int slot; | |
10978 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
10979 | ||
10980 | op_placement_table = (op_placement_info_table) | |
10981 | xmalloc (sizeof (op_placement_info) * num_opcodes); | |
10982 | assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); | |
10983 | ||
10984 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
10985 | { | |
10986 | op_placement_info *opi = &op_placement_table[opcode]; | |
10987 | /* FIXME: Make tinsn allocation dynamic. */ | |
10988 | if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS) | |
10989 | as_fatal (_("too many operands in instruction")); | |
43cd72b9 BW |
10990 | opi->narrowest = XTENSA_UNDEFINED; |
10991 | opi->narrowest_size = 0x7F; | |
b2d179be | 10992 | opi->narrowest_slot = 0; |
43cd72b9 BW |
10993 | opi->formats = 0; |
10994 | opi->num_formats = 0; | |
10995 | opi->issuef = 0; | |
10996 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
10997 | { | |
10998 | opi->slots[fmt] = 0; | |
10999 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
11000 | { | |
11001 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
11002 | { | |
11003 | int fmt_length = xtensa_format_length (isa, fmt); | |
11004 | opi->issuef++; | |
11005 | set_bit (fmt, opi->formats); | |
11006 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
11007 | if (fmt_length < opi->narrowest_size |
11008 | || (fmt_length == opi->narrowest_size | |
11009 | && (xtensa_format_num_slots (isa, fmt) | |
11010 | < xtensa_format_num_slots (isa, | |
11011 | opi->narrowest)))) | |
43cd72b9 BW |
11012 | { |
11013 | opi->narrowest = fmt; | |
11014 | opi->narrowest_size = fmt_length; | |
b2d179be | 11015 | opi->narrowest_slot = slot; |
43cd72b9 | 11016 | } |
e0001a05 NC |
11017 | } |
11018 | } | |
43cd72b9 BW |
11019 | if (opi->formats) |
11020 | opi->num_formats++; | |
e0001a05 NC |
11021 | } |
11022 | } | |
43cd72b9 BW |
11023 | xtensa_insnbuf_free (isa, ibuf); |
11024 | } | |
11025 | ||
11026 | ||
11027 | bfd_boolean | |
7fa3d080 | 11028 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
11029 | { |
11030 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
11031 | } | |
11032 | ||
11033 | ||
11034 | /* If the opcode is available in a single slot format, return its size. */ | |
11035 | ||
7fa3d080 BW |
11036 | static int |
11037 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 11038 | { |
b2d179be | 11039 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
11040 | } |
11041 | ||
11042 | ||
7fa3d080 BW |
11043 | static xtensa_format |
11044 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 11045 | { |
b2d179be BW |
11046 | return op_placement_table[opcode].narrowest; |
11047 | } | |
11048 | ||
11049 | ||
11050 | static int | |
11051 | xg_get_single_slot (xtensa_opcode opcode) | |
11052 | { | |
11053 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
11054 | } |
11055 | ||
11056 | \f | |
11057 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
11058 | ||
11059 | void | |
7fa3d080 | 11060 | istack_init (IStack *stack) |
e0001a05 NC |
11061 | { |
11062 | memset (stack, 0, sizeof (IStack)); | |
11063 | stack->ninsn = 0; | |
11064 | } | |
11065 | ||
11066 | ||
11067 | bfd_boolean | |
7fa3d080 | 11068 | istack_empty (IStack *stack) |
e0001a05 NC |
11069 | { |
11070 | return (stack->ninsn == 0); | |
11071 | } | |
11072 | ||
11073 | ||
11074 | bfd_boolean | |
7fa3d080 | 11075 | istack_full (IStack *stack) |
e0001a05 NC |
11076 | { |
11077 | return (stack->ninsn == MAX_ISTACK); | |
11078 | } | |
11079 | ||
11080 | ||
11081 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 11082 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
11083 | |
11084 | TInsn * | |
7fa3d080 | 11085 | istack_top (IStack *stack) |
e0001a05 NC |
11086 | { |
11087 | int rec = stack->ninsn - 1; | |
11088 | assert (!istack_empty (stack)); | |
11089 | return &stack->insn[rec]; | |
11090 | } | |
11091 | ||
11092 | ||
11093 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 11094 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11095 | |
11096 | void | |
7fa3d080 | 11097 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
11098 | { |
11099 | int rec = stack->ninsn; | |
11100 | assert (!istack_full (stack)); | |
43cd72b9 | 11101 | stack->insn[rec] = *insn; |
e0001a05 NC |
11102 | stack->ninsn++; |
11103 | } | |
11104 | ||
11105 | ||
11106 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 11107 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11108 | |
11109 | TInsn * | |
7fa3d080 | 11110 | istack_push_space (IStack *stack) |
e0001a05 NC |
11111 | { |
11112 | int rec = stack->ninsn; | |
11113 | TInsn *insn; | |
11114 | assert (!istack_full (stack)); | |
11115 | insn = &stack->insn[rec]; | |
60242db2 | 11116 | tinsn_init (insn); |
e0001a05 NC |
11117 | stack->ninsn++; |
11118 | return insn; | |
11119 | } | |
11120 | ||
11121 | ||
11122 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 11123 | istack_empty () returns TRUE. */ |
e0001a05 NC |
11124 | |
11125 | void | |
7fa3d080 | 11126 | istack_pop (IStack *stack) |
e0001a05 NC |
11127 | { |
11128 | int rec = stack->ninsn - 1; | |
11129 | assert (!istack_empty (stack)); | |
11130 | stack->ninsn--; | |
60242db2 | 11131 | tinsn_init (&stack->insn[rec]); |
e0001a05 NC |
11132 | } |
11133 | ||
11134 | \f | |
11135 | /* TInsn functions. */ | |
11136 | ||
11137 | void | |
7fa3d080 | 11138 | tinsn_init (TInsn *dst) |
e0001a05 NC |
11139 | { |
11140 | memset (dst, 0, sizeof (TInsn)); | |
11141 | } | |
11142 | ||
11143 | ||
43cd72b9 | 11144 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
11145 | |
11146 | static bfd_boolean | |
7fa3d080 | 11147 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
11148 | { |
11149 | int i; | |
11150 | int n = insn->ntok; | |
11151 | ||
11152 | assert (insn->insn_type == ITYPE_INSN); | |
11153 | ||
11154 | for (i = 0; i < n; ++i) | |
11155 | { | |
11156 | switch (insn->tok[i].X_op) | |
11157 | { | |
11158 | case O_register: | |
11159 | case O_constant: | |
11160 | break; | |
11161 | default: | |
11162 | return TRUE; | |
11163 | } | |
11164 | } | |
11165 | return FALSE; | |
11166 | } | |
11167 | ||
11168 | ||
11169 | bfd_boolean | |
7fa3d080 | 11170 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 11171 | { |
43cd72b9 | 11172 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
11173 | int i; |
11174 | int n = insn->ntok; | |
11175 | ||
11176 | assert (insn->insn_type == ITYPE_INSN); | |
11177 | ||
11178 | for (i = 0; i < n; ++i) | |
11179 | { | |
11180 | switch (insn->tok[i].X_op) | |
11181 | { | |
11182 | case O_register: | |
11183 | case O_constant: | |
11184 | break; | |
43cd72b9 BW |
11185 | case O_big: |
11186 | case O_illegal: | |
11187 | case O_absent: | |
11188 | /* Errors for these types are caught later. */ | |
11189 | break; | |
11190 | case O_hi16: | |
11191 | case O_lo16: | |
e0001a05 | 11192 | default: |
43cd72b9 BW |
11193 | /* Symbolic immediates are only allowed on the last immediate |
11194 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 11195 | support non-PC-relative relocations. */ |
43cd72b9 BW |
11196 | if (i != get_relaxable_immed (insn->opcode) |
11197 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
11198 | && insn->opcode != xtensa_const16_opcode)) | |
11199 | { | |
431ad2d0 | 11200 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
11201 | return TRUE; |
11202 | } | |
e0001a05 NC |
11203 | } |
11204 | } | |
11205 | return FALSE; | |
11206 | } | |
11207 | ||
11208 | ||
11209 | /* For assembly code with complex expressions (e.g. subtraction), | |
11210 | we have to build them in the literal pool so that | |
11211 | their results are calculated correctly after relaxation. | |
11212 | The relaxation only handles expressions that | |
11213 | boil down to SYMBOL + OFFSET. */ | |
11214 | ||
11215 | static bfd_boolean | |
7fa3d080 | 11216 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
11217 | { |
11218 | int i; | |
11219 | int n = insn->ntok; | |
11220 | assert (insn->insn_type == ITYPE_INSN); | |
11221 | for (i = 0; i < n; ++i) | |
11222 | { | |
11223 | switch (insn->tok[i].X_op) | |
11224 | { | |
11225 | case O_register: | |
11226 | case O_constant: | |
11227 | case O_symbol: | |
43cd72b9 BW |
11228 | case O_lo16: |
11229 | case O_hi16: | |
e0001a05 NC |
11230 | break; |
11231 | default: | |
11232 | return TRUE; | |
11233 | } | |
11234 | } | |
11235 | return FALSE; | |
11236 | } | |
11237 | ||
11238 | ||
b2d179be BW |
11239 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
11240 | Return TRUE if there is a symbol in the immediate field. This | |
11241 | function assumes that: | |
11242 | 1) The number of operands are correct. | |
11243 | 2) The insn_type is ITYPE_INSN. | |
11244 | 3) The opcode can be encoded in the specified format and slot. | |
11245 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
11246 | |
11247 | static bfd_boolean | |
7fa3d080 BW |
11248 | tinsn_to_slotbuf (xtensa_format fmt, |
11249 | int slot, | |
11250 | TInsn *tinsn, | |
11251 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
11252 | { |
11253 | xtensa_isa isa = xtensa_default_isa; | |
11254 | xtensa_opcode opcode = tinsn->opcode; | |
11255 | bfd_boolean has_fixup = FALSE; | |
11256 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11257 | int i; | |
11258 | ||
43cd72b9 BW |
11259 | assert (tinsn->insn_type == ITYPE_INSN); |
11260 | if (noperands != tinsn->ntok) | |
11261 | as_fatal (_("operand number mismatch")); | |
11262 | ||
11263 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
11264 | { | |
11265 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
11266 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
11267 | return FALSE; | |
11268 | } | |
11269 | ||
11270 | for (i = 0; i < noperands; i++) | |
11271 | { | |
11272 | expressionS *expr = &tinsn->tok[i]; | |
d77b99c9 BW |
11273 | int rc; |
11274 | unsigned line; | |
43cd72b9 BW |
11275 | char *file_name; |
11276 | uint32 opnd_value; | |
11277 | ||
11278 | switch (expr->X_op) | |
11279 | { | |
11280 | case O_register: | |
11281 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11282 | break; | |
11283 | /* The register number has already been checked in | |
11284 | expression_maybe_register, so we don't need to check here. */ | |
11285 | opnd_value = expr->X_add_number; | |
11286 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); | |
11287 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
11288 | opnd_value); | |
11289 | if (rc != 0) | |
11290 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
11291 | break; | |
11292 | ||
11293 | case O_constant: | |
11294 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11295 | break; | |
11296 | as_where (&file_name, &line); | |
11297 | /* It is a constant and we called this function | |
11298 | then we have to try to fit it. */ | |
11299 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
e0001a05 NC |
11300 | expr->X_add_number, file_name, line); |
11301 | break; | |
11302 | ||
e0001a05 NC |
11303 | default: |
11304 | has_fixup = TRUE; | |
11305 | break; | |
11306 | } | |
11307 | } | |
43cd72b9 | 11308 | |
e0001a05 NC |
11309 | return has_fixup; |
11310 | } | |
11311 | ||
11312 | ||
b2d179be BW |
11313 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
11314 | into a multi-slot instruction, fill the other slots with NOPs. | |
11315 | Return TRUE if there is a symbol in the immediate field. See also the | |
11316 | assumptions listed for tinsn_to_slotbuf. */ | |
11317 | ||
11318 | static bfd_boolean | |
11319 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
11320 | { | |
11321 | static xtensa_insnbuf slotbuf = 0; | |
11322 | static vliw_insn vinsn; | |
11323 | xtensa_isa isa = xtensa_default_isa; | |
11324 | bfd_boolean has_fixup = FALSE; | |
11325 | int i; | |
11326 | ||
11327 | if (!slotbuf) | |
11328 | { | |
11329 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11330 | xg_init_vinsn (&vinsn); | |
11331 | } | |
11332 | ||
11333 | xg_clear_vinsn (&vinsn); | |
11334 | ||
11335 | bundle_tinsn (tinsn, &vinsn); | |
11336 | ||
11337 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
11338 | ||
11339 | for (i = 0; i < vinsn.num_slots; i++) | |
11340 | { | |
11341 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
11342 | has_fixup |= | |
11343 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
11344 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
11345 | } | |
11346 | ||
11347 | return has_fixup; | |
11348 | } | |
11349 | ||
11350 | ||
43cd72b9 | 11351 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 11352 | |
7fa3d080 BW |
11353 | static bfd_boolean |
11354 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
11355 | { |
11356 | xtensa_isa isa = xtensa_default_isa; | |
11357 | xtensa_opcode opcode = insn->opcode; | |
11358 | ||
11359 | if (opcode == XTENSA_UNDEFINED) | |
11360 | { | |
11361 | as_bad (_("invalid opcode")); | |
11362 | return TRUE; | |
11363 | } | |
11364 | ||
43cd72b9 | 11365 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
11366 | { |
11367 | as_bad (_("too few operands")); | |
11368 | return TRUE; | |
11369 | } | |
11370 | ||
43cd72b9 | 11371 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
11372 | { |
11373 | as_bad (_("too many operands")); | |
11374 | return TRUE; | |
11375 | } | |
11376 | return FALSE; | |
11377 | } | |
11378 | ||
11379 | ||
11380 | /* Load an instruction from its encoded form. */ | |
11381 | ||
11382 | static void | |
7fa3d080 | 11383 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 11384 | { |
43cd72b9 | 11385 | vliw_insn vinsn; |
e0001a05 | 11386 | |
43cd72b9 BW |
11387 | xg_init_vinsn (&vinsn); |
11388 | vinsn_from_chars (&vinsn, f); | |
11389 | ||
11390 | *tinsn = vinsn.slots[slot]; | |
11391 | xg_free_vinsn (&vinsn); | |
11392 | } | |
e0001a05 | 11393 | |
43cd72b9 BW |
11394 | |
11395 | static void | |
7fa3d080 BW |
11396 | tinsn_from_insnbuf (TInsn *tinsn, |
11397 | xtensa_insnbuf slotbuf, | |
11398 | xtensa_format fmt, | |
11399 | int slot) | |
43cd72b9 BW |
11400 | { |
11401 | int i; | |
11402 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
11403 | |
11404 | /* Find the immed. */ | |
43cd72b9 BW |
11405 | tinsn_init (tinsn); |
11406 | tinsn->insn_type = ITYPE_INSN; | |
11407 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
11408 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
11409 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
11410 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 11411 | { |
43cd72b9 BW |
11412 | set_expr_const (&tinsn->tok[i], |
11413 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
11414 | tinsn->opcode, i)); | |
e0001a05 NC |
11415 | } |
11416 | } | |
11417 | ||
11418 | ||
11419 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
11420 | ||
11421 | static void | |
7fa3d080 | 11422 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 11423 | { |
43cd72b9 | 11424 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
11425 | int opnum; |
11426 | ||
43cd72b9 | 11427 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
11428 | { |
11429 | opnum = get_relaxable_immed (opcode); | |
43cd72b9 | 11430 | assert (opnum >= 0); |
e7da6241 BW |
11431 | set_expr_symbol_offset (&tinsn->tok[opnum], |
11432 | fragP->tc_frag_data.slot_symbols[slot], | |
11433 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 NC |
11434 | } |
11435 | } | |
11436 | ||
11437 | ||
11438 | static int | |
7fa3d080 | 11439 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
11440 | { |
11441 | int i; | |
11442 | int text_bytes = 0; | |
11443 | ||
11444 | for (i = 0; i < istack->ninsn; i++) | |
11445 | { | |
43cd72b9 BW |
11446 | TInsn *tinsn = &istack->insn[i]; |
11447 | if (tinsn->insn_type == ITYPE_INSN) | |
11448 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
11449 | } |
11450 | return text_bytes; | |
11451 | } | |
11452 | ||
11453 | ||
11454 | static int | |
7fa3d080 | 11455 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
11456 | { |
11457 | int i; | |
11458 | int lit_bytes = 0; | |
11459 | ||
11460 | for (i = 0; i < istack->ninsn; i++) | |
11461 | { | |
43cd72b9 BW |
11462 | TInsn *tinsn = &istack->insn[i]; |
11463 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
11464 | lit_bytes += 4; |
11465 | } | |
11466 | return lit_bytes; | |
11467 | } | |
11468 | ||
43cd72b9 BW |
11469 | \f |
11470 | /* vliw_insn functions. */ | |
11471 | ||
7fa3d080 BW |
11472 | static void |
11473 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11474 | { |
11475 | int i; | |
11476 | xtensa_isa isa = xtensa_default_isa; | |
11477 | ||
11478 | xg_clear_vinsn (v); | |
11479 | ||
11480 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
11481 | if (v->insnbuf == NULL) | |
11482 | as_fatal (_("out of memory")); | |
11483 | ||
11484 | for (i = 0; i < MAX_SLOTS; i++) | |
11485 | { | |
43cd72b9 BW |
11486 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
11487 | if (v->slotbuf[i] == NULL) | |
11488 | as_fatal (_("out of memory")); | |
11489 | } | |
11490 | } | |
11491 | ||
11492 | ||
7fa3d080 BW |
11493 | static void |
11494 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11495 | { |
11496 | int i; | |
65738a7d BW |
11497 | |
11498 | memset (v, 0, offsetof (vliw_insn, insnbuf)); | |
11499 | ||
43cd72b9 BW |
11500 | v->format = XTENSA_UNDEFINED; |
11501 | v->num_slots = 0; | |
11502 | v->inside_bundle = FALSE; | |
11503 | ||
11504 | if (xt_saved_debug_type != DEBUG_NONE) | |
11505 | debug_type = xt_saved_debug_type; | |
11506 | ||
11507 | for (i = 0; i < MAX_SLOTS; i++) | |
65738a7d | 11508 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
11509 | } |
11510 | ||
11511 | ||
7fa3d080 BW |
11512 | static bfd_boolean |
11513 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
11514 | { |
11515 | int i; | |
c138bc38 | 11516 | |
43cd72b9 BW |
11517 | for (i = 0; i < v->num_slots; i++) |
11518 | { | |
11519 | if (v->slots[i].is_specific_opcode) | |
11520 | return TRUE; | |
11521 | } | |
11522 | return FALSE; | |
11523 | } | |
11524 | ||
11525 | ||
7fa3d080 BW |
11526 | static void |
11527 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11528 | { |
11529 | int i; | |
11530 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
11531 | for (i = 0; i < MAX_SLOTS; i++) | |
11532 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); | |
11533 | } | |
11534 | ||
11535 | ||
e7da6241 BW |
11536 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
11537 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
11538 | |
11539 | static bfd_boolean | |
7fa3d080 BW |
11540 | vinsn_to_insnbuf (vliw_insn *vinsn, |
11541 | char *frag_offset, | |
11542 | fragS *fragP, | |
11543 | bfd_boolean record_fixup) | |
43cd72b9 BW |
11544 | { |
11545 | xtensa_isa isa = xtensa_default_isa; | |
11546 | xtensa_format fmt = vinsn->format; | |
11547 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
11548 | int slot; | |
11549 | bfd_boolean has_fixup = FALSE; | |
11550 | ||
11551 | xtensa_format_encode (isa, fmt, insnbuf); | |
11552 | ||
11553 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
11554 | { | |
11555 | TInsn *tinsn = &vinsn->slots[slot]; | |
11556 | bfd_boolean tinsn_has_fixup = | |
11557 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
11558 | vinsn->slotbuf[slot]); | |
11559 | ||
11560 | xtensa_format_set_slot (isa, fmt, slot, | |
11561 | insnbuf, vinsn->slotbuf[slot]); | |
e7da6241 | 11562 | if (tinsn_has_fixup) |
43cd72b9 BW |
11563 | { |
11564 | int i; | |
11565 | xtensa_opcode opcode = tinsn->opcode; | |
11566 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11567 | has_fixup = TRUE; | |
11568 | ||
11569 | for (i = 0; i < noperands; i++) | |
11570 | { | |
11571 | expressionS* expr = &tinsn->tok[i]; | |
11572 | switch (expr->X_op) | |
11573 | { | |
11574 | case O_symbol: | |
11575 | case O_lo16: | |
11576 | case O_hi16: | |
11577 | if (get_relaxable_immed (opcode) == i) | |
11578 | { | |
e7da6241 BW |
11579 | /* Add a fix record for the instruction, except if this |
11580 | function is being called prior to relaxation, i.e., | |
11581 | if record_fixup is false, and the instruction might | |
11582 | be relaxed later. */ | |
11583 | if (record_fixup | |
11584 | || tinsn->is_specific_opcode | |
11585 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 11586 | { |
e7da6241 BW |
11587 | xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP, |
11588 | frag_offset - fragP->fr_literal); | |
43cd72b9 BW |
11589 | } |
11590 | else | |
11591 | { | |
e7da6241 BW |
11592 | if (expr->X_op != O_symbol) |
11593 | as_bad (_("invalid operand")); | |
43cd72b9 BW |
11594 | tinsn->symbol = expr->X_add_symbol; |
11595 | tinsn->offset = expr->X_add_number; | |
11596 | } | |
11597 | } | |
11598 | else | |
e7da6241 | 11599 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
11600 | break; |
11601 | ||
11602 | case O_constant: | |
11603 | case O_register: | |
11604 | break; | |
11605 | ||
43cd72b9 | 11606 | default: |
e7da6241 | 11607 | as_bad (_("expression too complex")); |
43cd72b9 BW |
11608 | break; |
11609 | } | |
11610 | } | |
11611 | } | |
11612 | } | |
11613 | ||
11614 | return has_fixup; | |
11615 | } | |
11616 | ||
11617 | ||
11618 | static void | |
7fa3d080 | 11619 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
11620 | { |
11621 | static xtensa_insnbuf insnbuf = NULL; | |
11622 | static xtensa_insnbuf slotbuf = NULL; | |
11623 | int i; | |
11624 | xtensa_format fmt; | |
11625 | xtensa_isa isa = xtensa_default_isa; | |
11626 | ||
11627 | if (!insnbuf) | |
11628 | { | |
11629 | insnbuf = xtensa_insnbuf_alloc (isa); | |
11630 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11631 | } | |
11632 | ||
d77b99c9 | 11633 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
11634 | fmt = xtensa_format_decode (isa, insnbuf); |
11635 | if (fmt == XTENSA_UNDEFINED) | |
11636 | as_fatal (_("cannot decode instruction format")); | |
11637 | vinsn->format = fmt; | |
11638 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
11639 | ||
11640 | for (i = 0; i < vinsn->num_slots; i++) | |
11641 | { | |
11642 | TInsn *tinsn = &vinsn->slots[i]; | |
11643 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
11644 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
11645 | } | |
11646 | } | |
11647 | ||
e0001a05 NC |
11648 | \f |
11649 | /* Expression utilities. */ | |
11650 | ||
43cd72b9 | 11651 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
11652 | |
11653 | bfd_boolean | |
7fa3d080 | 11654 | expr_is_const (const expressionS *s) |
e0001a05 NC |
11655 | { |
11656 | return (s->X_op == O_constant); | |
11657 | } | |
11658 | ||
11659 | ||
11660 | /* Get the expression constant. | |
43cd72b9 | 11661 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
11662 | |
11663 | offsetT | |
7fa3d080 | 11664 | get_expr_const (const expressionS *s) |
e0001a05 NC |
11665 | { |
11666 | assert (expr_is_const (s)); | |
11667 | return s->X_add_number; | |
11668 | } | |
11669 | ||
11670 | ||
11671 | /* Set the expression to a constant value. */ | |
11672 | ||
11673 | void | |
7fa3d080 | 11674 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
11675 | { |
11676 | s->X_op = O_constant; | |
11677 | s->X_add_number = val; | |
11678 | s->X_add_symbol = NULL; | |
11679 | s->X_op_symbol = NULL; | |
11680 | } | |
11681 | ||
11682 | ||
43cd72b9 | 11683 | bfd_boolean |
7fa3d080 | 11684 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
11685 | { |
11686 | return (s->X_op == O_register); | |
11687 | } | |
11688 | ||
11689 | ||
11690 | /* Get the expression constant. | |
11691 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
11692 | ||
11693 | offsetT | |
7fa3d080 | 11694 | get_expr_register (const expressionS *s) |
43cd72b9 BW |
11695 | { |
11696 | assert (expr_is_register (s)); | |
11697 | return s->X_add_number; | |
11698 | } | |
11699 | ||
11700 | ||
e0001a05 NC |
11701 | /* Set the expression to a symbol + constant offset. */ |
11702 | ||
11703 | void | |
7fa3d080 | 11704 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
11705 | { |
11706 | s->X_op = O_symbol; | |
11707 | s->X_add_symbol = sym; | |
11708 | s->X_op_symbol = NULL; /* unused */ | |
11709 | s->X_add_number = offset; | |
11710 | } | |
11711 | ||
11712 | ||
43cd72b9 BW |
11713 | /* Return TRUE if the two expressions are equal. */ |
11714 | ||
e0001a05 | 11715 | bfd_boolean |
7fa3d080 | 11716 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
11717 | { |
11718 | if (s1->X_op != s2->X_op) | |
11719 | return FALSE; | |
11720 | if (s1->X_add_symbol != s2->X_add_symbol) | |
11721 | return FALSE; | |
11722 | if (s1->X_op_symbol != s2->X_op_symbol) | |
11723 | return FALSE; | |
11724 | if (s1->X_add_number != s2->X_add_number) | |
11725 | return FALSE; | |
11726 | return TRUE; | |
11727 | } | |
11728 | ||
11729 | ||
11730 | static void | |
7fa3d080 | 11731 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
11732 | { |
11733 | memcpy (dst, src, sizeof (expressionS)); | |
11734 | } | |
11735 | ||
11736 | \f | |
9456465c | 11737 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
11738 | |
11739 | struct rename_section_struct | |
11740 | { | |
11741 | char *old_name; | |
11742 | char *new_name; | |
11743 | struct rename_section_struct *next; | |
11744 | }; | |
11745 | ||
11746 | static struct rename_section_struct *section_rename; | |
11747 | ||
11748 | ||
9456465c BW |
11749 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
11750 | entries to the section_rename list. Note: Specifying multiple | |
11751 | renamings separated by colons is not documented and is retained only | |
11752 | for backward compatibility. */ | |
e0001a05 | 11753 | |
7fa3d080 BW |
11754 | static void |
11755 | build_section_rename (const char *arg) | |
e0001a05 | 11756 | { |
9456465c | 11757 | struct rename_section_struct *r; |
e0001a05 NC |
11758 | char *this_arg = NULL; |
11759 | char *next_arg = NULL; | |
11760 | ||
9456465c | 11761 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 11762 | { |
9456465c BW |
11763 | char *old_name, *new_name; |
11764 | ||
e0001a05 NC |
11765 | if (this_arg) |
11766 | { | |
11767 | next_arg = strchr (this_arg, ':'); | |
11768 | if (next_arg) | |
11769 | { | |
11770 | *next_arg = '\0'; | |
11771 | next_arg++; | |
11772 | } | |
11773 | } | |
e0001a05 | 11774 | |
9456465c BW |
11775 | old_name = this_arg; |
11776 | new_name = strchr (this_arg, '='); | |
e0001a05 | 11777 | |
9456465c BW |
11778 | if (*old_name == '\0') |
11779 | { | |
11780 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
11781 | continue; | |
11782 | } | |
11783 | if (!new_name || new_name[1] == '\0') | |
11784 | { | |
11785 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
11786 | old_name); | |
11787 | continue; | |
11788 | } | |
11789 | *new_name = '\0'; | |
11790 | new_name++; | |
e0001a05 | 11791 | |
9456465c BW |
11792 | /* Check for invalid section renaming. */ |
11793 | for (r = section_rename; r != NULL; r = r->next) | |
11794 | { | |
11795 | if (strcmp (r->old_name, old_name) == 0) | |
11796 | as_bad (_("section %s renamed multiple times"), old_name); | |
11797 | if (strcmp (r->new_name, new_name) == 0) | |
11798 | as_bad (_("multiple sections remapped to output section %s"), | |
11799 | new_name); | |
11800 | } | |
e0001a05 | 11801 | |
9456465c BW |
11802 | /* Now add it. */ |
11803 | r = (struct rename_section_struct *) | |
11804 | xmalloc (sizeof (struct rename_section_struct)); | |
11805 | r->old_name = xstrdup (old_name); | |
11806 | r->new_name = xstrdup (new_name); | |
11807 | r->next = section_rename; | |
11808 | section_rename = r; | |
e0001a05 | 11809 | } |
e0001a05 NC |
11810 | } |
11811 | ||
11812 | ||
9456465c BW |
11813 | char * |
11814 | xtensa_section_rename (char *name) | |
e0001a05 NC |
11815 | { |
11816 | struct rename_section_struct *r = section_rename; | |
11817 | ||
11818 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
11819 | { |
11820 | if (strcmp (r->old_name, name) == 0) | |
11821 | return r->new_name; | |
11822 | } | |
e0001a05 NC |
11823 | |
11824 | return name; | |
11825 | } |