Commit | Line | Data |
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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
d47d412e | 2 | Copyright 2003, 2004, 2005, 2006 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 | 20 | |
43cd72b9 | 21 | #include <limits.h> |
e0001a05 NC |
22 | #include "as.h" |
23 | #include "sb.h" | |
24 | #include "safe-ctype.h" | |
25 | #include "tc-xtensa.h" | |
e0001a05 NC |
26 | #include "subsegs.h" |
27 | #include "xtensa-relax.h" | |
28 | #include "xtensa-istack.h" | |
cda2eb9e | 29 | #include "dwarf2dbg.h" |
e0001a05 NC |
30 | #include "struc-symbol.h" |
31 | #include "xtensa-config.h" | |
32 | ||
2caa7ca0 BW |
33 | /* Provide default values for new configuration settings. */ |
34 | #ifndef XSHAL_ABI | |
35 | #define XSHAL_ABI 0 | |
36 | #endif | |
37 | ||
e0001a05 NC |
38 | #ifndef uint32 |
39 | #define uint32 unsigned int | |
40 | #endif | |
41 | #ifndef int32 | |
42 | #define int32 signed int | |
43 | #endif | |
44 | ||
45 | /* Notes: | |
46 | ||
e0001a05 NC |
47 | Naming conventions (used somewhat inconsistently): |
48 | The xtensa_ functions are exported | |
49 | The xg_ functions are internal | |
50 | ||
51 | We also have a couple of different extensibility mechanisms. | |
52 | 1) The idiom replacement: | |
53 | This is used when a line is first parsed to | |
54 | replace an instruction pattern with another instruction | |
55 | It is currently limited to replacements of instructions | |
56 | with constant operands. | |
57 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
58 | replacement patterns. When an instruction's immediate field | |
59 | does not fit the next instruction sequence is attempted. | |
60 | In addition, "narrow" opcodes are supported this way. */ | |
61 | ||
62 | ||
63 | /* Define characters with special meanings to GAS. */ | |
64 | const char comment_chars[] = "#"; | |
65 | const char line_comment_chars[] = "#"; | |
66 | const char line_separator_chars[] = ";"; | |
67 | const char EXP_CHARS[] = "eE"; | |
68 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
69 | ||
70 | ||
43cd72b9 BW |
71 | /* Flags to indicate whether the hardware supports the density and |
72 | absolute literals options. */ | |
e0001a05 | 73 | |
e0001a05 | 74 | bfd_boolean density_supported = XCHAL_HAVE_DENSITY; |
43cd72b9 BW |
75 | bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; |
76 | ||
77 | /* Maximum width we would pad an unreachable frag to get alignment. */ | |
78 | #define UNREACHABLE_MAX_WIDTH 8 | |
e0001a05 | 79 | |
43cd72b9 BW |
80 | static vliw_insn cur_vinsn; |
81 | ||
d77b99c9 | 82 | unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; |
43cd72b9 BW |
83 | |
84 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
85 | ||
86 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 87 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
88 | back end. */ |
89 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
90 | |
91 | /* Flags for properties of the last instruction in a segment. */ | |
92 | #define FLAG_IS_A0_WRITER 0x1 | |
93 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
94 | ||
95 | ||
96 | /* We define a special segment names ".literal" to place literals | |
97 | into. The .fini and .init sections are special because they | |
98 | contain code that is moved together by the linker. We give them | |
99 | their own special .fini.literal and .init.literal sections. */ | |
100 | ||
101 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 102 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 | 103 | #define INIT_SECTION_NAME xtensa_section_rename (".init") |
74869ac7 | 104 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
e0001a05 NC |
105 | |
106 | ||
43cd72b9 | 107 | /* This type is used for the directive_stack to keep track of the |
74869ac7 BW |
108 | state of the literal collection pools. If lit_prefix is set, it is |
109 | used to determine the literal section names; otherwise, the literal | |
110 | sections are determined based on the current text section. The | |
111 | lit_seg and lit4_seg fields cache these literal sections, with the | |
112 | current_text_seg field used a tag to indicate whether the cached | |
113 | values are valid. */ | |
e0001a05 NC |
114 | |
115 | typedef struct lit_state_struct | |
116 | { | |
74869ac7 BW |
117 | char *lit_prefix; |
118 | segT current_text_seg; | |
e0001a05 | 119 | segT lit_seg; |
43cd72b9 | 120 | segT lit4_seg; |
e0001a05 NC |
121 | } lit_state; |
122 | ||
123 | static lit_state default_lit_sections; | |
124 | ||
125 | ||
74869ac7 BW |
126 | /* We keep a list of literal segments. The seg_list type is the node |
127 | for this list. The literal_head pointer is the head of the list, | |
128 | with the literal_head_h dummy node at the start. */ | |
e0001a05 NC |
129 | |
130 | typedef struct seg_list_struct | |
131 | { | |
132 | struct seg_list_struct *next; | |
133 | segT seg; | |
134 | } seg_list; | |
135 | ||
136 | static seg_list literal_head_h; | |
137 | static seg_list *literal_head = &literal_head_h; | |
e0001a05 NC |
138 | |
139 | ||
82e7541d BW |
140 | /* Lists of symbols. We keep a list of symbols that label the current |
141 | instruction, so that we can adjust the symbols when inserting alignment | |
142 | for various instructions. We also keep a list of all the symbols on | |
143 | literals, so that we can fix up those symbols when the literals are | |
144 | later moved into the text sections. */ | |
145 | ||
146 | typedef struct sym_list_struct | |
147 | { | |
148 | struct sym_list_struct *next; | |
149 | symbolS *sym; | |
150 | } sym_list; | |
151 | ||
152 | static sym_list *insn_labels = NULL; | |
153 | static sym_list *free_insn_labels = NULL; | |
154 | static sym_list *saved_insn_labels = NULL; | |
155 | ||
156 | static sym_list *literal_syms; | |
157 | ||
158 | ||
43cd72b9 BW |
159 | /* Flags to determine whether to prefer const16 or l32r |
160 | if both options are available. */ | |
161 | int prefer_const16 = 0; | |
162 | int prefer_l32r = 0; | |
163 | ||
e0001a05 NC |
164 | /* Global flag to indicate when we are emitting literals. */ |
165 | int generating_literals = 0; | |
166 | ||
43cd72b9 BW |
167 | /* The following PROPERTY table definitions are copied from |
168 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
169 | ||
170 | /* Flags in the property tables to specify whether blocks of memory | |
171 | are literals, instructions, data, or unreachable. For | |
172 | instructions, blocks that begin loop targets and branch targets are | |
173 | designated. Blocks that do not allow density, instruction | |
174 | reordering or transformation are also specified. Finally, for | |
175 | branch targets, branch target alignment priority is included. | |
176 | Alignment of the next block is specified in the current block | |
177 | and the size of the current block does not include any fill required | |
178 | to align to the next block. */ | |
179 | ||
180 | #define XTENSA_PROP_LITERAL 0x00000001 | |
181 | #define XTENSA_PROP_INSN 0x00000002 | |
182 | #define XTENSA_PROP_DATA 0x00000004 | |
183 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
184 | /* Instruction only properties at beginning of code. */ | |
185 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
186 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
187 | /* Instruction only properties about code. */ | |
188 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
189 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
190 | #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100 | |
191 | ||
192 | /* Branch target alignment information. This transmits information | |
193 | to the linker optimization about the priority of aligning a | |
194 | particular block for branch target alignment: None, low priority, | |
195 | high priority, or required. These only need to be checked in | |
196 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
197 | Common usage is | |
198 | ||
199 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
200 | case XTENSA_PROP_BT_ALIGN_NONE: | |
201 | case XTENSA_PROP_BT_ALIGN_LOW: | |
202 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
203 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
204 | */ | |
205 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
206 | ||
207 | /* No branch target alignment. */ | |
208 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
209 | /* Low priority branch target alignment. */ | |
210 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
211 | /* High priority branch target alignment. */ | |
212 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
213 | /* Required branch target alignment. */ | |
214 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
215 | ||
216 | #define GET_XTENSA_PROP_BT_ALIGN(flag) \ | |
217 | (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) | |
218 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ | |
219 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
220 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
221 | ||
222 | ||
223 | /* Alignment is specified in the block BEFORE the one that needs | |
224 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
225 | get the required alignment specified as a power of 2. Use | |
226 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
227 | alignment. Be careful of side effects since the SET will evaluate | |
228 | flags twice. Also, note that the SIZE of a block in the property | |
229 | table does not include the alignment size, so the alignment fill | |
230 | must be calculated to determine if two blocks are contiguous. | |
231 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
232 | possible future implementation. */ | |
233 | ||
234 | #define XTENSA_PROP_ALIGN 0x00000800 | |
235 | ||
236 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
237 | ||
238 | #define GET_XTENSA_PROP_ALIGNMENT(flag) \ | |
239 | (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) | |
240 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ | |
241 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
242 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
243 | ||
244 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
245 | ||
246 | ||
247 | /* Structure for saving instruction and alignment per-fragment data | |
248 | that will be written to the object file. This structure is | |
249 | equivalent to the actual data that will be written out to the file | |
250 | but is easier to use. We provide a conversion to file flags | |
251 | in frag_flags_to_number. */ | |
252 | ||
253 | typedef struct frag_flags_struct frag_flags; | |
254 | ||
255 | struct frag_flags_struct | |
256 | { | |
257 | /* is_literal should only be used after xtensa_move_literals. | |
258 | If you need to check if you are generating a literal fragment, | |
259 | then use the generating_literals global. */ | |
260 | ||
261 | unsigned is_literal : 1; | |
262 | unsigned is_insn : 1; | |
263 | unsigned is_data : 1; | |
264 | unsigned is_unreachable : 1; | |
265 | ||
266 | struct | |
267 | { | |
268 | unsigned is_loop_target : 1; | |
269 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
270 | unsigned bt_align_priority : 2; | |
271 | ||
272 | unsigned is_no_density : 1; | |
273 | /* no_longcalls flag does not need to be placed in the object file. */ | |
274 | /* is_specific_opcode implies no_transform. */ | |
275 | unsigned is_no_transform : 1; | |
276 | ||
277 | unsigned is_no_reorder : 1; | |
278 | ||
279 | /* Uses absolute literal addressing for l32r. */ | |
280 | unsigned is_abslit : 1; | |
281 | } insn; | |
282 | unsigned is_align : 1; | |
283 | unsigned alignment : 5; | |
284 | }; | |
285 | ||
286 | ||
287 | /* Structure for saving information about a block of property data | |
288 | for frags that have the same flags. */ | |
289 | struct xtensa_block_info_struct | |
290 | { | |
291 | segT sec; | |
292 | bfd_vma offset; | |
293 | size_t size; | |
294 | frag_flags flags; | |
295 | struct xtensa_block_info_struct *next; | |
296 | }; | |
297 | ||
e0001a05 NC |
298 | |
299 | /* Structure for saving the current state before emitting literals. */ | |
300 | typedef struct emit_state_struct | |
301 | { | |
302 | const char *name; | |
303 | segT now_seg; | |
304 | subsegT now_subseg; | |
305 | int generating_literals; | |
306 | } emit_state; | |
307 | ||
308 | ||
43cd72b9 BW |
309 | /* Opcode placement information */ |
310 | ||
311 | typedef unsigned long long bitfield; | |
312 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
313 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
314 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
315 | ||
316 | #define MAX_FORMATS 32 | |
317 | ||
318 | typedef struct op_placement_info_struct | |
319 | { | |
320 | int num_formats; | |
321 | /* A number describing how restrictive the issue is for this | |
322 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 323 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 324 | only one format but many slots in that format. The most |
c138bc38 | 325 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
326 | format. */ |
327 | int issuef; | |
43cd72b9 | 328 | xtensa_format narrowest; |
43cd72b9 | 329 | char narrowest_size; |
b2d179be | 330 | char narrowest_slot; |
43cd72b9 BW |
331 | |
332 | /* formats is a bitfield with the Nth bit set | |
333 | if the opcode fits in the Nth xtensa_format. */ | |
334 | bitfield formats; | |
335 | ||
336 | /* slots[N]'s Mth bit is set if the op fits in the | |
337 | Mth slot of the Nth xtensa_format. */ | |
338 | bitfield slots[MAX_FORMATS]; | |
339 | ||
340 | /* A count of the number of slots in a given format | |
341 | an op can fit (i.e., the bitcount of the slot field above). */ | |
342 | char slots_in_format[MAX_FORMATS]; | |
343 | ||
344 | } op_placement_info, *op_placement_info_table; | |
345 | ||
346 | op_placement_info_table op_placement_table; | |
347 | ||
348 | ||
349 | /* Extra expression types. */ | |
350 | ||
351 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
352 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
353 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
354 | ||
355 | ||
e0001a05 NC |
356 | /* Directives. */ |
357 | ||
358 | typedef enum | |
359 | { | |
360 | directive_none = 0, | |
361 | directive_literal, | |
362 | directive_density, | |
43cd72b9 | 363 | directive_transform, |
e0001a05 NC |
364 | directive_freeregs, |
365 | directive_longcalls, | |
43cd72b9 BW |
366 | directive_literal_prefix, |
367 | directive_schedule, | |
368 | directive_absolute_literals, | |
369 | directive_last_directive | |
e0001a05 NC |
370 | } directiveE; |
371 | ||
372 | typedef struct | |
373 | { | |
374 | const char *name; | |
375 | bfd_boolean can_be_negated; | |
376 | } directive_infoS; | |
377 | ||
378 | const directive_infoS directive_info[] = | |
379 | { | |
43cd72b9 BW |
380 | { "none", FALSE }, |
381 | { "literal", FALSE }, | |
382 | { "density", TRUE }, | |
383 | { "transform", TRUE }, | |
384 | { "freeregs", FALSE }, | |
385 | { "longcalls", TRUE }, | |
386 | { "literal_prefix", FALSE }, | |
387 | { "schedule", TRUE }, | |
388 | { "absolute-literals", TRUE } | |
e0001a05 NC |
389 | }; |
390 | ||
391 | bfd_boolean directive_state[] = | |
392 | { | |
393 | FALSE, /* none */ | |
394 | FALSE, /* literal */ | |
43cd72b9 | 395 | #if !XCHAL_HAVE_DENSITY |
e0001a05 NC |
396 | FALSE, /* density */ |
397 | #else | |
398 | TRUE, /* density */ | |
399 | #endif | |
43cd72b9 | 400 | TRUE, /* transform */ |
e0001a05 NC |
401 | FALSE, /* freeregs */ |
402 | FALSE, /* longcalls */ | |
43cd72b9 | 403 | FALSE, /* literal_prefix */ |
2caa7ca0 | 404 | FALSE, /* schedule */ |
43cd72b9 BW |
405 | #if XSHAL_USE_ABSOLUTE_LITERALS |
406 | TRUE /* absolute_literals */ | |
407 | #else | |
408 | FALSE /* absolute_literals */ | |
409 | #endif | |
e0001a05 NC |
410 | }; |
411 | ||
e0001a05 NC |
412 | |
413 | /* Directive functions. */ | |
414 | ||
7fa3d080 BW |
415 | static void xtensa_begin_directive (int); |
416 | static void xtensa_end_directive (int); | |
74869ac7 | 417 | static void xtensa_literal_prefix (void); |
7fa3d080 BW |
418 | static void xtensa_literal_position (int); |
419 | static void xtensa_literal_pseudo (int); | |
420 | static void xtensa_frequency_pseudo (int); | |
421 | static void xtensa_elf_cons (int); | |
e0001a05 | 422 | |
7fa3d080 | 423 | /* Parsing and Idiom Translation. */ |
e0001a05 | 424 | |
7fa3d080 | 425 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 426 | |
e0001a05 NC |
427 | /* Various Other Internal Functions. */ |
428 | ||
84b08ed9 BW |
429 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
430 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
431 | static void xtensa_mark_literal_pool_location (void); |
432 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
433 | static fragS *get_literal_pool_location (segT); | |
434 | static void set_literal_pool_location (segT, fragS *); | |
435 | static void xtensa_set_frag_assembly_state (fragS *); | |
436 | static void finish_vinsn (vliw_insn *); | |
437 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 438 | static int total_frag_text_expansion (fragS *); |
e0001a05 NC |
439 | |
440 | /* Alignment Functions. */ | |
441 | ||
d77b99c9 BW |
442 | static int get_text_align_power (unsigned); |
443 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 444 | static int branch_align_power (segT); |
e0001a05 NC |
445 | |
446 | /* Helpers for xtensa_relax_frag(). */ | |
447 | ||
7fa3d080 | 448 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 449 | |
b08b5071 | 450 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 451 | |
7fa3d080 BW |
452 | static unsigned get_last_insn_flags (segT, subsegT); |
453 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
454 | static float get_subseg_total_freq (segT, subsegT); |
455 | static float get_subseg_target_freq (segT, subsegT); | |
456 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
457 | |
458 | /* Segment list functions. */ | |
459 | ||
7fa3d080 BW |
460 | static void xtensa_move_literals (void); |
461 | static void xtensa_reorder_segments (void); | |
462 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
463 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
464 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
465 | static void xtensa_restore_emit_state (emit_state *); | |
74869ac7 | 466 | static segT cache_literal_section (bfd_boolean); |
e0001a05 | 467 | |
e0001a05 | 468 | /* Import from elf32-xtensa.c in BFD library. */ |
43cd72b9 | 469 | |
74869ac7 | 470 | extern asection *xtensa_get_property_section (asection *, const char *); |
e0001a05 | 471 | |
43cd72b9 BW |
472 | /* op_placement_info functions. */ |
473 | ||
7fa3d080 BW |
474 | static void init_op_placement_info_table (void); |
475 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
476 | static int xg_get_single_size (xtensa_opcode); | |
477 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 478 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 479 | |
e0001a05 | 480 | /* TInsn and IStack functions. */ |
43cd72b9 | 481 | |
7fa3d080 BW |
482 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
483 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
484 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
485 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
486 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
487 | static void tinsn_from_chars (TInsn *, char *, int); | |
488 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
489 | static int get_num_stack_text_bytes (IStack *); | |
490 | static int get_num_stack_literal_bytes (IStack *); | |
e0001a05 | 491 | |
43cd72b9 BW |
492 | /* vliw_insn functions. */ |
493 | ||
7fa3d080 BW |
494 | static void xg_init_vinsn (vliw_insn *); |
495 | static void xg_clear_vinsn (vliw_insn *); | |
496 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
497 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 498 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
499 | (vliw_insn *, char *, fragS *, bfd_boolean); |
500 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 501 | |
e0001a05 | 502 | /* Expression Utilities. */ |
43cd72b9 | 503 | |
7fa3d080 BW |
504 | bfd_boolean expr_is_const (const expressionS *); |
505 | offsetT get_expr_const (const expressionS *); | |
506 | void set_expr_const (expressionS *, offsetT); | |
507 | bfd_boolean expr_is_register (const expressionS *); | |
508 | offsetT get_expr_register (const expressionS *); | |
509 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
510 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
511 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 512 | |
9456465c BW |
513 | /* Section renaming. */ |
514 | ||
7fa3d080 | 515 | static void build_section_rename (const char *); |
e0001a05 | 516 | |
e0001a05 NC |
517 | |
518 | /* ISA imported from bfd. */ | |
519 | extern xtensa_isa xtensa_default_isa; | |
520 | ||
521 | extern int target_big_endian; | |
522 | ||
523 | static xtensa_opcode xtensa_addi_opcode; | |
524 | static xtensa_opcode xtensa_addmi_opcode; | |
525 | static xtensa_opcode xtensa_call0_opcode; | |
526 | static xtensa_opcode xtensa_call4_opcode; | |
527 | static xtensa_opcode xtensa_call8_opcode; | |
528 | static xtensa_opcode xtensa_call12_opcode; | |
529 | static xtensa_opcode xtensa_callx0_opcode; | |
530 | static xtensa_opcode xtensa_callx4_opcode; | |
531 | static xtensa_opcode xtensa_callx8_opcode; | |
532 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 533 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 534 | static xtensa_opcode xtensa_entry_opcode; |
43cd72b9 BW |
535 | static xtensa_opcode xtensa_movi_opcode; |
536 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 537 | static xtensa_opcode xtensa_isync_opcode; |
e0001a05 | 538 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 539 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
540 | static xtensa_opcode xtensa_loop_opcode; |
541 | static xtensa_opcode xtensa_loopnez_opcode; | |
542 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 543 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
544 | static xtensa_opcode xtensa_nop_n_opcode; |
545 | static xtensa_opcode xtensa_or_opcode; | |
546 | static xtensa_opcode xtensa_ret_opcode; | |
547 | static xtensa_opcode xtensa_ret_n_opcode; | |
548 | static xtensa_opcode xtensa_retw_opcode; | |
549 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 550 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 NC |
551 | static xtensa_opcode xtensa_waiti_opcode; |
552 | ||
553 | \f | |
554 | /* Command-line Options. */ | |
555 | ||
556 | bfd_boolean use_literal_section = TRUE; | |
557 | static bfd_boolean align_targets = TRUE; | |
43cd72b9 | 558 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 559 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
560 | static bfd_boolean workaround_a0_b_retw = FALSE; |
561 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
562 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 563 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 564 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 565 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 566 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
e0001a05 | 567 | |
43cd72b9 BW |
568 | /* When workaround_short_loops is TRUE, all loops with early exits must |
569 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
570 | to the workaround_short_loop flag. In addition to the | |
571 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
572 | must have at least 3 instructions. */ | |
e0001a05 | 573 | |
43cd72b9 | 574 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 575 | |
7fa3d080 BW |
576 | |
577 | static void | |
578 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
579 | { | |
580 | if (earliest > latest) | |
581 | as_fatal (_("illegal range of target hardware versions")); | |
582 | ||
583 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
584 | if (earliest < 105000 || latest < 105000) | |
585 | { | |
586 | workaround_a0_b_retw |= TRUE; | |
587 | workaround_b_j_loop_end |= TRUE; | |
588 | workaround_short_loop |= TRUE; | |
589 | workaround_close_loop_end |= TRUE; | |
590 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 591 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
592 | } |
593 | } | |
594 | ||
595 | ||
e0001a05 NC |
596 | enum |
597 | { | |
598 | option_density = OPTION_MD_BASE, | |
599 | option_no_density, | |
600 | ||
601 | option_relax, | |
602 | option_no_relax, | |
603 | ||
43cd72b9 BW |
604 | option_link_relax, |
605 | option_no_link_relax, | |
606 | ||
e0001a05 NC |
607 | option_generics, |
608 | option_no_generics, | |
609 | ||
43cd72b9 BW |
610 | option_transform, |
611 | option_no_transform, | |
612 | ||
e0001a05 NC |
613 | option_text_section_literals, |
614 | option_no_text_section_literals, | |
615 | ||
43cd72b9 BW |
616 | option_absolute_literals, |
617 | option_no_absolute_literals, | |
618 | ||
e0001a05 NC |
619 | option_align_targets, |
620 | option_no_align_targets, | |
621 | ||
43cd72b9 | 622 | option_warn_unaligned_targets, |
e0001a05 NC |
623 | |
624 | option_longcalls, | |
625 | option_no_longcalls, | |
626 | ||
627 | option_workaround_a0_b_retw, | |
628 | option_no_workaround_a0_b_retw, | |
629 | ||
630 | option_workaround_b_j_loop_end, | |
631 | option_no_workaround_b_j_loop_end, | |
632 | ||
633 | option_workaround_short_loop, | |
634 | option_no_workaround_short_loop, | |
635 | ||
636 | option_workaround_all_short_loops, | |
637 | option_no_workaround_all_short_loops, | |
638 | ||
639 | option_workaround_close_loop_end, | |
640 | option_no_workaround_close_loop_end, | |
641 | ||
642 | option_no_workarounds, | |
643 | ||
e0001a05 | 644 | option_rename_section_name, |
e0001a05 | 645 | |
43cd72b9 BW |
646 | option_prefer_l32r, |
647 | option_prefer_const16, | |
648 | ||
649 | option_target_hardware | |
e0001a05 NC |
650 | }; |
651 | ||
652 | const char *md_shortopts = ""; | |
653 | ||
654 | struct option md_longopts[] = | |
655 | { | |
43cd72b9 BW |
656 | { "density", no_argument, NULL, option_density }, |
657 | { "no-density", no_argument, NULL, option_no_density }, | |
658 | ||
659 | /* Both "relax" and "generics" are deprecated and treated as equivalent | |
660 | to the "transform" option. */ | |
661 | { "relax", no_argument, NULL, option_relax }, | |
662 | { "no-relax", no_argument, NULL, option_no_relax }, | |
663 | { "generics", no_argument, NULL, option_generics }, | |
664 | { "no-generics", no_argument, NULL, option_no_generics }, | |
665 | ||
666 | { "transform", no_argument, NULL, option_transform }, | |
667 | { "no-transform", no_argument, NULL, option_no_transform }, | |
668 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
669 | { "no-text-section-literals", no_argument, NULL, | |
670 | option_no_text_section_literals }, | |
671 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
672 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
673 | /* This option was changed from -align-target to -target-align |
674 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 675 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
676 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
677 | { "warn-unaligned-targets", no_argument, NULL, | |
678 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
679 | { "longcalls", no_argument, NULL, option_longcalls }, |
680 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
681 | ||
682 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
683 | option_no_workaround_a0_b_retw }, | |
684 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 685 | |
43cd72b9 BW |
686 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
687 | option_no_workaround_b_j_loop_end }, | |
688 | { "workaround-b-j-loop-end", no_argument, NULL, | |
689 | option_workaround_b_j_loop_end }, | |
e0001a05 | 690 | |
43cd72b9 BW |
691 | { "no-workaround-short-loops", no_argument, NULL, |
692 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
693 | { "workaround-short-loops", no_argument, NULL, |
694 | option_workaround_short_loop }, | |
e0001a05 | 695 | |
43cd72b9 BW |
696 | { "no-workaround-all-short-loops", no_argument, NULL, |
697 | option_no_workaround_all_short_loops }, | |
698 | { "workaround-all-short-loop", no_argument, NULL, | |
699 | option_workaround_all_short_loops }, | |
700 | ||
701 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
702 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
703 | ||
704 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
705 | ||
706 | { "no-workaround-close-loop-end", no_argument, NULL, | |
707 | option_no_workaround_close_loop_end }, | |
708 | { "workaround-close-loop-end", no_argument, NULL, | |
709 | option_workaround_close_loop_end }, | |
e0001a05 | 710 | |
7fa3d080 | 711 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 712 | |
43cd72b9 BW |
713 | { "link-relax", no_argument, NULL, option_link_relax }, |
714 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
715 | ||
716 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
717 | ||
718 | { NULL, no_argument, NULL, 0 } | |
e0001a05 NC |
719 | }; |
720 | ||
721 | size_t md_longopts_size = sizeof md_longopts; | |
722 | ||
723 | ||
724 | int | |
7fa3d080 | 725 | md_parse_option (int c, char *arg) |
e0001a05 NC |
726 | { |
727 | switch (c) | |
728 | { | |
729 | case option_density: | |
43cd72b9 | 730 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
731 | return 1; |
732 | case option_no_density: | |
43cd72b9 | 733 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 734 | return 1; |
43cd72b9 BW |
735 | case option_link_relax: |
736 | linkrelax = 1; | |
e0001a05 | 737 | return 1; |
43cd72b9 BW |
738 | case option_no_link_relax: |
739 | linkrelax = 0; | |
e0001a05 | 740 | return 1; |
43cd72b9 BW |
741 | case option_generics: |
742 | as_warn (_("--generics is deprecated; use --transform instead")); | |
743 | return md_parse_option (option_transform, arg); | |
744 | case option_no_generics: | |
745 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
746 | return md_parse_option (option_no_transform, arg); | |
747 | case option_relax: | |
748 | as_warn (_("--relax is deprecated; use --transform instead")); | |
749 | return md_parse_option (option_transform, arg); | |
750 | case option_no_relax: | |
751 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
752 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
753 | case option_longcalls: |
754 | directive_state[directive_longcalls] = TRUE; | |
755 | return 1; | |
756 | case option_no_longcalls: | |
757 | directive_state[directive_longcalls] = FALSE; | |
758 | return 1; | |
759 | case option_text_section_literals: | |
760 | use_literal_section = FALSE; | |
761 | return 1; | |
762 | case option_no_text_section_literals: | |
763 | use_literal_section = TRUE; | |
764 | return 1; | |
43cd72b9 BW |
765 | case option_absolute_literals: |
766 | if (!absolute_literals_supported) | |
767 | { | |
768 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
769 | return 0; | |
770 | } | |
771 | directive_state[directive_absolute_literals] = TRUE; | |
772 | return 1; | |
773 | case option_no_absolute_literals: | |
774 | directive_state[directive_absolute_literals] = FALSE; | |
775 | return 1; | |
776 | ||
e0001a05 NC |
777 | case option_workaround_a0_b_retw: |
778 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
779 | return 1; |
780 | case option_no_workaround_a0_b_retw: | |
781 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
782 | return 1; |
783 | case option_workaround_b_j_loop_end: | |
784 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
785 | return 1; |
786 | case option_no_workaround_b_j_loop_end: | |
787 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
788 | return 1; |
789 | ||
790 | case option_workaround_short_loop: | |
791 | workaround_short_loop = TRUE; | |
e0001a05 NC |
792 | return 1; |
793 | case option_no_workaround_short_loop: | |
794 | workaround_short_loop = FALSE; | |
e0001a05 NC |
795 | return 1; |
796 | ||
797 | case option_workaround_all_short_loops: | |
798 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
799 | return 1; |
800 | case option_no_workaround_all_short_loops: | |
801 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
802 | return 1; |
803 | ||
804 | case option_workaround_close_loop_end: | |
805 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
806 | return 1; |
807 | case option_no_workaround_close_loop_end: | |
808 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
809 | return 1; |
810 | ||
811 | case option_no_workarounds: | |
812 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 813 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 814 | workaround_short_loop = FALSE; |
e0001a05 | 815 | workaround_all_short_loops = FALSE; |
e0001a05 | 816 | workaround_close_loop_end = FALSE; |
e0001a05 | 817 | return 1; |
43cd72b9 | 818 | |
e0001a05 NC |
819 | case option_align_targets: |
820 | align_targets = TRUE; | |
821 | return 1; | |
822 | case option_no_align_targets: | |
823 | align_targets = FALSE; | |
824 | return 1; | |
825 | ||
43cd72b9 BW |
826 | case option_warn_unaligned_targets: |
827 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
828 | return 1; |
829 | ||
e0001a05 NC |
830 | case option_rename_section_name: |
831 | build_section_rename (arg); | |
832 | return 1; | |
e0001a05 NC |
833 | |
834 | case 'Q': | |
835 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
836 | should be emitted or not. FIXME: Not implemented. */ | |
837 | return 1; | |
c138bc38 | 838 | |
43cd72b9 BW |
839 | case option_prefer_l32r: |
840 | if (prefer_const16) | |
841 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
842 | prefer_l32r = 1; | |
843 | return 1; | |
844 | ||
845 | case option_prefer_const16: | |
846 | if (prefer_l32r) | |
847 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
848 | prefer_const16 = 1; | |
849 | return 1; | |
850 | ||
c138bc38 | 851 | case option_target_hardware: |
43cd72b9 BW |
852 | { |
853 | int earliest, latest = 0; | |
854 | if (*arg == 0 || *arg == '-') | |
855 | as_fatal (_("invalid target hardware version")); | |
856 | ||
857 | earliest = strtol (arg, &arg, 0); | |
858 | ||
859 | if (*arg == 0) | |
860 | latest = earliest; | |
861 | else if (*arg == '-') | |
862 | { | |
863 | if (*++arg == 0) | |
864 | as_fatal (_("invalid target hardware version")); | |
865 | latest = strtol (arg, &arg, 0); | |
866 | } | |
867 | if (*arg != 0) | |
868 | as_fatal (_("invalid target hardware version")); | |
869 | ||
870 | xtensa_setup_hw_workarounds (earliest, latest); | |
871 | return 1; | |
872 | } | |
873 | ||
874 | case option_transform: | |
875 | /* This option has no affect other than to use the defaults, | |
876 | which are already set. */ | |
877 | return 1; | |
878 | ||
879 | case option_no_transform: | |
880 | /* This option turns off all transformations of any kind. | |
881 | However, because we want to preserve the state of other | |
882 | directives, we only change its own field. Thus, before | |
883 | you perform any transformation, always check if transform | |
884 | is available. If you use the functions we provide for this | |
885 | purpose, you will be ok. */ | |
886 | directive_state[directive_transform] = FALSE; | |
887 | return 1; | |
888 | ||
e0001a05 NC |
889 | default: |
890 | return 0; | |
891 | } | |
892 | } | |
893 | ||
894 | ||
895 | void | |
7fa3d080 | 896 | md_show_usage (FILE *stream) |
e0001a05 | 897 | { |
43cd72b9 BW |
898 | fputs ("\n\ |
899 | Xtensa options:\n\ | |
9456465c BW |
900 | --[no-]text-section-literals\n\ |
901 | [Do not] put literals in the text section\n\ | |
902 | --[no-]absolute-literals\n\ | |
903 | [Do not] default to use non-PC-relative literals\n\ | |
904 | --[no-]target-align [Do not] try to align branch targets\n\ | |
905 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
906 | --[no-]transform [Do not] transform instructions\n\ | |
907 | --rename-section old=new Rename section 'old' to 'new'\n", stream); | |
e0001a05 NC |
908 | } |
909 | ||
7fa3d080 BW |
910 | \f |
911 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
912 | |
913 | static void | |
7fa3d080 | 914 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 915 | { |
7fa3d080 | 916 | sym_list *l; |
43cd72b9 | 917 | |
7fa3d080 BW |
918 | if (!free_insn_labels) |
919 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
920 | else | |
43cd72b9 | 921 | { |
7fa3d080 BW |
922 | l = free_insn_labels; |
923 | free_insn_labels = l->next; | |
924 | } | |
925 | ||
926 | l->sym = sym; | |
927 | l->next = insn_labels; | |
928 | insn_labels = l; | |
929 | } | |
930 | ||
931 | ||
932 | static void | |
933 | xtensa_clear_insn_labels (void) | |
934 | { | |
935 | sym_list **pl; | |
936 | ||
937 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
938 | ; | |
939 | *pl = insn_labels; | |
940 | insn_labels = NULL; | |
941 | } | |
942 | ||
943 | ||
c138bc38 BW |
944 | /* The "loops_ok" argument is provided to allow ignoring labels that |
945 | define loop ends. This fixes a bug where the NOPs to align a | |
7fa3d080 BW |
946 | loop opcode were included in a previous zero-cost loop: |
947 | ||
948 | loop a0, loopend | |
949 | <loop1 body> | |
950 | loopend: | |
951 | ||
952 | loop a2, loopend2 | |
953 | <loop2 body> | |
954 | ||
955 | would become: | |
956 | ||
957 | loop a0, loopend | |
958 | <loop1 body> | |
959 | nop.n <===== bad! | |
960 | loopend: | |
961 | ||
962 | loop a2, loopend2 | |
963 | <loop2 body> | |
964 | ||
965 | This argument is used to prevent moving the NOP to before the | |
966 | loop-end label, which is what you want in this special case. */ | |
967 | ||
968 | static void | |
969 | xtensa_move_labels (fragS *new_frag, valueT new_offset, bfd_boolean loops_ok) | |
970 | { | |
971 | sym_list *lit; | |
972 | ||
973 | for (lit = insn_labels; lit; lit = lit->next) | |
974 | { | |
975 | symbolS *lit_sym = lit->sym; | |
976 | if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target) | |
977 | { | |
978 | S_SET_VALUE (lit_sym, new_offset); | |
979 | symbol_set_frag (lit_sym, new_frag); | |
980 | } | |
43cd72b9 BW |
981 | } |
982 | } | |
983 | ||
e0001a05 NC |
984 | \f |
985 | /* Directive data and functions. */ | |
986 | ||
987 | typedef struct state_stackS_struct | |
988 | { | |
989 | directiveE directive; | |
990 | bfd_boolean negated; | |
991 | bfd_boolean old_state; | |
992 | const char *file; | |
993 | unsigned int line; | |
994 | const void *datum; | |
995 | struct state_stackS_struct *prev; | |
996 | } state_stackS; | |
997 | ||
998 | state_stackS *directive_state_stack; | |
999 | ||
1000 | const pseudo_typeS md_pseudo_table[] = | |
1001 | { | |
43cd72b9 BW |
1002 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1003 | { "literal_position", xtensa_literal_position, 0 }, | |
1004 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1005 | { "long", xtensa_elf_cons, 4 }, | |
1006 | { "word", xtensa_elf_cons, 4 }, | |
1007 | { "short", xtensa_elf_cons, 2 }, | |
1008 | { "begin", xtensa_begin_directive, 0 }, | |
1009 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1010 | { "literal", xtensa_literal_pseudo, 0 }, |
1011 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1012 | { NULL, 0, 0 }, | |
e0001a05 NC |
1013 | }; |
1014 | ||
1015 | ||
7fa3d080 BW |
1016 | static bfd_boolean |
1017 | use_transform (void) | |
e0001a05 | 1018 | { |
43cd72b9 BW |
1019 | /* After md_end, you should be checking frag by frag, rather |
1020 | than state directives. */ | |
1021 | assert (!past_xtensa_end); | |
1022 | return directive_state[directive_transform]; | |
e0001a05 NC |
1023 | } |
1024 | ||
1025 | ||
7fa3d080 BW |
1026 | static bfd_boolean |
1027 | do_align_targets (void) | |
e0001a05 | 1028 | { |
7b1cc377 BW |
1029 | /* Do not use this function after md_end; just look at align_targets |
1030 | instead. There is no target-align directive, so alignment is either | |
1031 | enabled for all frags or not done at all. */ | |
43cd72b9 BW |
1032 | assert (!past_xtensa_end); |
1033 | return align_targets && use_transform (); | |
e0001a05 NC |
1034 | } |
1035 | ||
1036 | ||
1037 | static void | |
7fa3d080 | 1038 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 NC |
1039 | { |
1040 | char *file; | |
1041 | unsigned int line; | |
1042 | state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); | |
1043 | ||
1044 | as_where (&file, &line); | |
1045 | ||
1046 | stack->directive = directive; | |
1047 | stack->negated = negated; | |
1048 | stack->old_state = directive_state[directive]; | |
1049 | stack->file = file; | |
1050 | stack->line = line; | |
1051 | stack->datum = datum; | |
1052 | stack->prev = directive_state_stack; | |
1053 | directive_state_stack = stack; | |
1054 | ||
1055 | directive_state[directive] = !negated; | |
1056 | } | |
1057 | ||
7fa3d080 | 1058 | |
e0001a05 | 1059 | static void |
7fa3d080 BW |
1060 | directive_pop (directiveE *directive, |
1061 | bfd_boolean *negated, | |
1062 | const char **file, | |
1063 | unsigned int *line, | |
1064 | const void **datum) | |
e0001a05 NC |
1065 | { |
1066 | state_stackS *top = directive_state_stack; | |
1067 | ||
1068 | if (!directive_state_stack) | |
1069 | { | |
1070 | as_bad (_("unmatched end directive")); | |
1071 | *directive = directive_none; | |
1072 | return; | |
1073 | } | |
1074 | ||
1075 | directive_state[directive_state_stack->directive] = top->old_state; | |
1076 | *directive = top->directive; | |
1077 | *negated = top->negated; | |
1078 | *file = top->file; | |
1079 | *line = top->line; | |
1080 | *datum = top->datum; | |
1081 | directive_state_stack = top->prev; | |
1082 | free (top); | |
1083 | } | |
1084 | ||
1085 | ||
1086 | static void | |
7fa3d080 | 1087 | directive_balance (void) |
e0001a05 NC |
1088 | { |
1089 | while (directive_state_stack) | |
1090 | { | |
1091 | directiveE directive; | |
1092 | bfd_boolean negated; | |
1093 | const char *file; | |
1094 | unsigned int line; | |
1095 | const void *datum; | |
1096 | ||
1097 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1098 | as_warn_where ((char *) file, line, | |
1099 | _(".begin directive with no matching .end directive")); | |
1100 | } | |
1101 | } | |
1102 | ||
1103 | ||
1104 | static bfd_boolean | |
7fa3d080 | 1105 | inside_directive (directiveE dir) |
e0001a05 NC |
1106 | { |
1107 | state_stackS *top = directive_state_stack; | |
1108 | ||
1109 | while (top && top->directive != dir) | |
1110 | top = top->prev; | |
1111 | ||
1112 | return (top != NULL); | |
1113 | } | |
1114 | ||
1115 | ||
1116 | static void | |
7fa3d080 | 1117 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1118 | { |
1119 | int len; | |
1120 | unsigned i; | |
43cd72b9 | 1121 | char *directive_string; |
e0001a05 NC |
1122 | |
1123 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1124 | *negated = FALSE; | |
1125 | else | |
1126 | { | |
1127 | *negated = TRUE; | |
1128 | input_line_pointer += 3; | |
1129 | } | |
1130 | ||
1131 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1132 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1133 | ||
1134 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1135 | equivalent to .begin [no-]transform. We should remove it when | |
1136 | we stop accepting those options. */ | |
c138bc38 | 1137 | |
43cd72b9 BW |
1138 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1139 | { | |
1140 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1141 | directive_string = "transform"; | |
1142 | } | |
1143 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1144 | { | |
1145 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1146 | directive_string = "transform"; | |
c138bc38 | 1147 | } |
43cd72b9 BW |
1148 | else |
1149 | directive_string = input_line_pointer; | |
e0001a05 NC |
1150 | |
1151 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1152 | { | |
43cd72b9 | 1153 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1154 | { |
1155 | input_line_pointer += len; | |
1156 | *directive = (directiveE) i; | |
1157 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1158 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1159 | directive_info[i].name); |
1160 | return; | |
1161 | } | |
1162 | } | |
1163 | ||
1164 | as_bad (_("unknown directive")); | |
1165 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1166 | } | |
1167 | ||
1168 | ||
1169 | static void | |
7fa3d080 | 1170 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1171 | { |
1172 | directiveE directive; | |
1173 | bfd_boolean negated; | |
1174 | emit_state *state; | |
e0001a05 NC |
1175 | lit_state *ls; |
1176 | ||
1177 | get_directive (&directive, &negated); | |
1178 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1179 | { | |
1180 | discard_rest_of_line (); | |
1181 | return; | |
1182 | } | |
1183 | ||
43cd72b9 BW |
1184 | if (cur_vinsn.inside_bundle) |
1185 | as_bad (_("directives are not valid inside bundles")); | |
1186 | ||
e0001a05 NC |
1187 | switch (directive) |
1188 | { | |
1189 | case directive_literal: | |
82e7541d BW |
1190 | if (!inside_directive (directive_literal)) |
1191 | { | |
1192 | /* Previous labels go with whatever follows this directive, not with | |
1193 | the literal, so save them now. */ | |
1194 | saved_insn_labels = insn_labels; | |
1195 | insn_labels = NULL; | |
1196 | } | |
43cd72b9 | 1197 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
e0001a05 NC |
1198 | state = (emit_state *) xmalloc (sizeof (emit_state)); |
1199 | xtensa_switch_to_literal_fragment (state); | |
1200 | directive_push (directive_literal, negated, state); | |
1201 | break; | |
1202 | ||
1203 | case directive_literal_prefix: | |
c138bc38 | 1204 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1205 | might produce a literal. */ |
1206 | md_flush_pending_output (); | |
e0001a05 NC |
1207 | /* Check to see if the current fragment is a literal |
1208 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1209 | if (generating_literals) |
e0001a05 NC |
1210 | { |
1211 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1212 | return; | |
1213 | } | |
1214 | ||
1215 | /* Allocate the literal state for this section and push | |
1216 | onto the directive stack. */ | |
1217 | ls = xmalloc (sizeof (lit_state)); | |
1218 | assert (ls); | |
1219 | ||
1220 | *ls = default_lit_sections; | |
e0001a05 NC |
1221 | directive_push (directive_literal_prefix, negated, ls); |
1222 | ||
e0001a05 | 1223 | /* Process the new prefix. */ |
74869ac7 | 1224 | xtensa_literal_prefix (); |
e0001a05 NC |
1225 | break; |
1226 | ||
1227 | case directive_freeregs: | |
1228 | /* This information is currently unused, but we'll accept the statement | |
1229 | and just discard the rest of the line. This won't check the syntax, | |
1230 | but it will accept every correct freeregs directive. */ | |
1231 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1232 | directive_push (directive_freeregs, negated, 0); | |
1233 | break; | |
1234 | ||
43cd72b9 BW |
1235 | case directive_schedule: |
1236 | md_flush_pending_output (); | |
1237 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1238 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1239 | directive_push (directive_schedule, negated, 0); | |
1240 | xtensa_set_frag_assembly_state (frag_now); | |
1241 | break; | |
1242 | ||
e0001a05 | 1243 | case directive_density: |
43cd72b9 BW |
1244 | as_warn (_(".begin [no-]density is ignored")); |
1245 | break; | |
1246 | ||
1247 | case directive_absolute_literals: | |
1248 | md_flush_pending_output (); | |
1249 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1250 | { |
43cd72b9 | 1251 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1252 | break; |
1253 | } | |
43cd72b9 BW |
1254 | xtensa_set_frag_assembly_state (frag_now); |
1255 | directive_push (directive, negated, 0); | |
1256 | break; | |
e0001a05 NC |
1257 | |
1258 | default: | |
43cd72b9 BW |
1259 | md_flush_pending_output (); |
1260 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1261 | directive_push (directive, negated, 0); |
1262 | break; | |
1263 | } | |
1264 | ||
1265 | demand_empty_rest_of_line (); | |
1266 | } | |
1267 | ||
1268 | ||
1269 | static void | |
7fa3d080 | 1270 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1271 | { |
1272 | directiveE begin_directive, end_directive; | |
1273 | bfd_boolean begin_negated, end_negated; | |
1274 | const char *file; | |
1275 | unsigned int line; | |
1276 | emit_state *state; | |
43cd72b9 | 1277 | emit_state **state_ptr; |
e0001a05 NC |
1278 | lit_state *s; |
1279 | ||
43cd72b9 BW |
1280 | if (cur_vinsn.inside_bundle) |
1281 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1282 | |
e0001a05 | 1283 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1284 | |
1285 | md_flush_pending_output (); | |
1286 | ||
1287 | switch (end_directive) | |
e0001a05 | 1288 | { |
43cd72b9 | 1289 | case (directiveE) XTENSA_UNDEFINED: |
e0001a05 NC |
1290 | discard_rest_of_line (); |
1291 | return; | |
e0001a05 | 1292 | |
43cd72b9 BW |
1293 | case directive_density: |
1294 | as_warn (_(".end [no-]density is ignored")); | |
e0001a05 | 1295 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1296 | break; |
1297 | ||
1298 | case directive_absolute_literals: | |
1299 | if (!absolute_literals_supported && !end_negated) | |
1300 | { | |
1301 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1302 | demand_empty_rest_of_line (); | |
1303 | return; | |
1304 | } | |
1305 | break; | |
1306 | ||
1307 | default: | |
1308 | break; | |
e0001a05 NC |
1309 | } |
1310 | ||
43cd72b9 | 1311 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1312 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1313 | (const void **) state_ptr); |
e0001a05 NC |
1314 | |
1315 | if (begin_directive != directive_none) | |
1316 | { | |
1317 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1318 | { | |
1319 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1320 | begin_negated ? "no-" : "", | |
1321 | directive_info[begin_directive].name, file, line); | |
1322 | } | |
1323 | else | |
1324 | { | |
1325 | switch (end_directive) | |
1326 | { | |
1327 | case directive_literal: | |
1328 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1329 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1330 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1331 | free (state); |
82e7541d BW |
1332 | if (!inside_directive (directive_literal)) |
1333 | { | |
1334 | /* Restore the list of current labels. */ | |
1335 | xtensa_clear_insn_labels (); | |
1336 | insn_labels = saved_insn_labels; | |
1337 | } | |
e0001a05 NC |
1338 | break; |
1339 | ||
e0001a05 NC |
1340 | case directive_literal_prefix: |
1341 | /* Restore the default collection sections from saved state. */ | |
1342 | s = (lit_state *) state; | |
1343 | assert (s); | |
e8247da7 | 1344 | default_lit_sections = *s; |
e0001a05 | 1345 | |
74869ac7 BW |
1346 | /* Free the state storage. */ |
1347 | free (s->lit_prefix); | |
e0001a05 NC |
1348 | free (s); |
1349 | break; | |
1350 | ||
43cd72b9 BW |
1351 | case directive_schedule: |
1352 | case directive_freeregs: | |
1353 | break; | |
1354 | ||
e0001a05 | 1355 | default: |
43cd72b9 | 1356 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1357 | break; |
1358 | } | |
1359 | } | |
1360 | } | |
1361 | ||
1362 | demand_empty_rest_of_line (); | |
1363 | } | |
1364 | ||
1365 | ||
1366 | /* Place an aligned literal fragment at the current location. */ | |
1367 | ||
1368 | static void | |
7fa3d080 | 1369 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1370 | { |
43cd72b9 BW |
1371 | md_flush_pending_output (); |
1372 | ||
e0001a05 NC |
1373 | if (inside_directive (directive_literal)) |
1374 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1375 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1376 | |
1377 | demand_empty_rest_of_line (); | |
82e7541d | 1378 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1379 | } |
1380 | ||
1381 | ||
43cd72b9 | 1382 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1383 | |
1384 | static void | |
7fa3d080 | 1385 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1386 | { |
1387 | emit_state state; | |
1745fcba | 1388 | char *p, *base_name; |
e0001a05 | 1389 | char c; |
e0001a05 NC |
1390 | segT dest_seg; |
1391 | ||
82e7541d BW |
1392 | if (inside_directive (directive_literal)) |
1393 | { | |
1394 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1395 | ignore_rest_of_line (); | |
1396 | return; | |
1397 | } | |
1398 | ||
43cd72b9 BW |
1399 | md_flush_pending_output (); |
1400 | ||
82e7541d BW |
1401 | /* Previous labels go with whatever follows this directive, not with |
1402 | the literal, so save them now. */ | |
1403 | saved_insn_labels = insn_labels; | |
1404 | insn_labels = NULL; | |
1405 | ||
e0001a05 NC |
1406 | /* If we are using text-section literals, then this is the right value... */ |
1407 | dest_seg = now_seg; | |
1408 | ||
1409 | base_name = input_line_pointer; | |
1410 | ||
1411 | xtensa_switch_to_literal_fragment (&state); | |
1412 | ||
43cd72b9 | 1413 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1414 | need to put them in the section we just switched to. */ |
43cd72b9 | 1415 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1416 | dest_seg = now_seg; |
1417 | ||
43cd72b9 BW |
1418 | /* All literals are aligned to four-byte boundaries. */ |
1419 | frag_align (2, 0, 0); | |
1420 | record_alignment (now_seg, 2); | |
e0001a05 NC |
1421 | |
1422 | c = get_symbol_end (); | |
1423 | /* Just after name is now '\0'. */ | |
1424 | p = input_line_pointer; | |
1425 | *p = c; | |
1426 | SKIP_WHITESPACE (); | |
1427 | ||
1428 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1429 | { | |
1430 | as_bad (_("expected comma or colon after symbol name; " | |
1431 | "rest of line ignored")); | |
1432 | ignore_rest_of_line (); | |
1433 | xtensa_restore_emit_state (&state); | |
1434 | return; | |
1435 | } | |
1436 | *p = 0; | |
1437 | ||
e0001a05 | 1438 | colon (base_name); |
e0001a05 | 1439 | |
e0001a05 | 1440 | *p = c; |
43cd72b9 | 1441 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1442 | |
43cd72b9 | 1443 | xtensa_elf_cons (4); |
e0001a05 NC |
1444 | |
1445 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1446 | |
1447 | /* Restore the list of current labels. */ | |
1448 | xtensa_clear_insn_labels (); | |
1449 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1450 | } |
1451 | ||
1452 | ||
1453 | static void | |
74869ac7 | 1454 | xtensa_literal_prefix (void) |
e0001a05 | 1455 | { |
74869ac7 BW |
1456 | char *name; |
1457 | int len; | |
1458 | ||
1459 | /* Parse the new prefix from the input_line_pointer. */ | |
1460 | SKIP_WHITESPACE (); | |
1461 | len = strspn (input_line_pointer, | |
1462 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1463 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
e0001a05 NC |
1464 | |
1465 | /* Get a null-terminated copy of the name. */ | |
1466 | name = xmalloc (len + 1); | |
1467 | assert (name); | |
74869ac7 | 1468 | strncpy (name, input_line_pointer, len); |
e0001a05 NC |
1469 | name[len] = 0; |
1470 | ||
74869ac7 BW |
1471 | /* Skip the name in the input line. */ |
1472 | input_line_pointer += len; | |
43cd72b9 | 1473 | |
74869ac7 | 1474 | default_lit_sections.lit_prefix = name; |
43cd72b9 | 1475 | |
74869ac7 | 1476 | /* Clear cached literal sections, since the prefix has changed. */ |
43cd72b9 BW |
1477 | default_lit_sections.lit_seg = NULL; |
1478 | default_lit_sections.lit4_seg = NULL; | |
43cd72b9 BW |
1479 | } |
1480 | ||
1481 | ||
1482 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1483 | ||
1484 | static void | |
7fa3d080 | 1485 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1486 | { |
1487 | float fall_through_f, target_f; | |
43cd72b9 BW |
1488 | |
1489 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1490 | if (fall_through_f < 0) | |
1491 | { | |
1492 | as_bad (_("fall through frequency must be greater than 0")); | |
1493 | ignore_rest_of_line (); | |
1494 | return; | |
1495 | } | |
1496 | ||
1497 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1498 | if (target_f < 0) | |
1499 | { | |
1500 | as_bad (_("branch target frequency must be greater than 0")); | |
1501 | ignore_rest_of_line (); | |
1502 | return; | |
1503 | } | |
1504 | ||
b08b5071 | 1505 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1506 | |
1507 | demand_empty_rest_of_line (); | |
1508 | } | |
1509 | ||
1510 | ||
1511 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1512 | Clobbers input_line_pointer, checks end-of-line. */ | |
1513 | ||
1514 | static void | |
7fa3d080 | 1515 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1516 | { |
1517 | expressionS exp; | |
1518 | bfd_reloc_code_real_type reloc; | |
1519 | ||
1520 | md_flush_pending_output (); | |
1521 | ||
1522 | if (cur_vinsn.inside_bundle) | |
1523 | as_bad (_("directives are not valid inside bundles")); | |
1524 | ||
1525 | if (is_it_end_of_statement ()) | |
1526 | { | |
1527 | demand_empty_rest_of_line (); | |
1528 | return; | |
1529 | } | |
1530 | ||
1531 | do | |
1532 | { | |
1533 | expression (&exp); | |
1534 | if (exp.X_op == O_symbol | |
1535 | && *input_line_pointer == '@' | |
1536 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1537 | != BFD_RELOC_NONE)) | |
1538 | { | |
1539 | reloc_howto_type *reloc_howto = | |
1540 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1541 | ||
1542 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1543 | as_bad (_("unsupported relocation")); | |
1544 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1545 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1546 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1547 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1548 | as_bad (_("opcode-specific %s relocation used outside " | |
1549 | "an instruction"), reloc_howto->name); | |
1550 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
1551 | as_bad (_("%s relocations do not fit in %d bytes"), | |
1552 | reloc_howto->name, nbytes); | |
1553 | else | |
1554 | { | |
1555 | char *p = frag_more ((int) nbytes); | |
1556 | xtensa_set_frag_assembly_state (frag_now); | |
1557 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1558 | nbytes, &exp, 0, reloc); | |
1559 | } | |
1560 | } | |
1561 | else | |
1562 | emit_expr (&exp, (unsigned int) nbytes); | |
1563 | } | |
1564 | while (*input_line_pointer++ == ','); | |
1565 | ||
1566 | input_line_pointer--; /* Put terminator back into stream. */ | |
1567 | demand_empty_rest_of_line (); | |
1568 | } | |
1569 | ||
7fa3d080 BW |
1570 | \f |
1571 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1572 | |
1573 | /* Parse @plt, etc. and return the desired relocation. */ | |
1574 | static bfd_reloc_code_real_type | |
7fa3d080 | 1575 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 BW |
1576 | { |
1577 | struct map_bfd | |
1578 | { | |
1579 | char *string; | |
1580 | int length; | |
1581 | bfd_reloc_code_real_type reloc; | |
1582 | }; | |
1583 | ||
1584 | char ident[20]; | |
1585 | char *str = *str_p; | |
1586 | char *str2; | |
1587 | int ch; | |
1588 | int len; | |
1589 | struct map_bfd *ptr; | |
1590 | ||
1591 | #define MAP(str,reloc) { str, sizeof (str) - 1, reloc } | |
e0001a05 | 1592 | |
43cd72b9 BW |
1593 | static struct map_bfd mapping[] = |
1594 | { | |
1595 | MAP ("l", BFD_RELOC_LO16), | |
1596 | MAP ("h", BFD_RELOC_HI16), | |
1597 | MAP ("plt", BFD_RELOC_XTENSA_PLT), | |
1598 | { (char *) 0, 0, BFD_RELOC_UNUSED } | |
1599 | }; | |
1600 | ||
1601 | if (*str++ != '@') | |
1602 | return BFD_RELOC_NONE; | |
1603 | ||
1604 | for (ch = *str, str2 = ident; | |
1605 | (str2 < ident + sizeof (ident) - 1 | |
1606 | && (ISALNUM (ch) || ch == '@')); | |
1607 | ch = *++str) | |
1608 | { | |
1609 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1610 | } | |
1611 | ||
1612 | *str2 = '\0'; | |
1613 | len = str2 - ident; | |
1614 | ||
1615 | ch = ident[0]; | |
1616 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
1617 | if (ch == ptr->string[0] | |
1618 | && len == ptr->length | |
1619 | && memcmp (ident, ptr->string, ptr->length) == 0) | |
1620 | { | |
1621 | /* Now check for "identifier@suffix+constant". */ | |
1622 | if (*str == '-' || *str == '+') | |
1623 | { | |
1624 | char *orig_line = input_line_pointer; | |
1625 | expressionS new_exp; | |
1626 | ||
1627 | input_line_pointer = str; | |
1628 | expression (&new_exp); | |
1629 | if (new_exp.X_op == O_constant) | |
1630 | { | |
1631 | exp_p->X_add_number += new_exp.X_add_number; | |
1632 | str = input_line_pointer; | |
1633 | } | |
1634 | ||
1635 | if (&input_line_pointer != str_p) | |
1636 | input_line_pointer = orig_line; | |
1637 | } | |
1638 | ||
1639 | *str_p = str; | |
1640 | return ptr->reloc; | |
1641 | } | |
1642 | ||
1643 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1644 | } |
1645 | ||
e0001a05 NC |
1646 | |
1647 | static const char * | |
7fa3d080 | 1648 | expression_end (const char *name) |
e0001a05 NC |
1649 | { |
1650 | while (1) | |
1651 | { | |
1652 | switch (*name) | |
1653 | { | |
43cd72b9 | 1654 | case '}': |
e0001a05 NC |
1655 | case ';': |
1656 | case '\0': | |
1657 | case ',': | |
43cd72b9 | 1658 | case ':': |
e0001a05 NC |
1659 | return name; |
1660 | case ' ': | |
1661 | case '\t': | |
1662 | ++name; | |
1663 | continue; | |
1664 | default: | |
1665 | return 0; | |
1666 | } | |
1667 | } | |
1668 | } | |
1669 | ||
1670 | ||
1671 | #define ERROR_REG_NUM ((unsigned) -1) | |
1672 | ||
1673 | static unsigned | |
7fa3d080 | 1674 | tc_get_register (const char *prefix) |
e0001a05 NC |
1675 | { |
1676 | unsigned reg; | |
1677 | const char *next_expr; | |
1678 | const char *old_line_pointer; | |
1679 | ||
1680 | SKIP_WHITESPACE (); | |
1681 | old_line_pointer = input_line_pointer; | |
1682 | ||
1683 | if (*input_line_pointer == '$') | |
1684 | ++input_line_pointer; | |
1685 | ||
1686 | /* Accept "sp" as a synonym for "a1". */ | |
1687 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1688 | && expression_end (input_line_pointer + 2)) | |
1689 | { | |
1690 | input_line_pointer += 2; | |
1691 | return 1; /* AR[1] */ | |
1692 | } | |
1693 | ||
1694 | while (*input_line_pointer++ == *prefix++) | |
1695 | ; | |
1696 | --input_line_pointer; | |
1697 | --prefix; | |
1698 | ||
1699 | if (*prefix) | |
1700 | { | |
1701 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1702 | return ERROR_REG_NUM; | |
1703 | } | |
1704 | ||
1705 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1706 | { | |
1707 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1708 | return ERROR_REG_NUM; | |
1709 | } | |
1710 | ||
1711 | reg = 0; | |
1712 | ||
1713 | while (ISDIGIT ((int) *input_line_pointer)) | |
1714 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1715 | ||
1716 | if (!(next_expr = expression_end (input_line_pointer))) | |
1717 | { | |
1718 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1719 | return ERROR_REG_NUM; | |
1720 | } | |
1721 | ||
1722 | input_line_pointer = (char *) next_expr; | |
1723 | ||
1724 | return reg; | |
1725 | } | |
1726 | ||
1727 | ||
e0001a05 | 1728 | static void |
7fa3d080 | 1729 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1730 | { |
43cd72b9 | 1731 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1732 | |
43cd72b9 BW |
1733 | /* Check if this is an immediate operand. */ |
1734 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1735 | { |
43cd72b9 | 1736 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1737 | segT t = expression (tok); |
43cd72b9 BW |
1738 | if (t == absolute_section |
1739 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 NC |
1740 | { |
1741 | assert (tok->X_op == O_constant); | |
1742 | tok->X_op = O_symbol; | |
1743 | tok->X_add_symbol = &abs_symbol; | |
1744 | } | |
43cd72b9 BW |
1745 | |
1746 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
1747 | && (reloc = xtensa_elf_suffix (&input_line_pointer, tok)) | |
1748 | && (reloc != BFD_RELOC_NONE)) | |
e0001a05 | 1749 | { |
43cd72b9 BW |
1750 | switch (reloc) |
1751 | { | |
1752 | default: | |
1753 | case BFD_RELOC_UNUSED: | |
1754 | as_bad (_("unsupported relocation")); | |
1755 | break; | |
1756 | ||
1757 | case BFD_RELOC_XTENSA_PLT: | |
1758 | tok->X_op = O_pltrel; | |
1759 | break; | |
1760 | ||
1761 | case BFD_RELOC_LO16: | |
1762 | if (tok->X_op == O_constant) | |
1763 | tok->X_add_number &= 0xffff; | |
1764 | else | |
1765 | tok->X_op = O_lo16; | |
1766 | break; | |
1767 | ||
1768 | case BFD_RELOC_HI16: | |
1769 | if (tok->X_op == O_constant) | |
1770 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; | |
1771 | else | |
1772 | tok->X_op = O_hi16; | |
1773 | break; | |
1774 | } | |
e0001a05 | 1775 | } |
e0001a05 NC |
1776 | } |
1777 | else | |
1778 | { | |
43cd72b9 BW |
1779 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1780 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1781 | |
1782 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1783 | { | |
1784 | uint32 buf = reg; | |
43cd72b9 | 1785 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1786 | as_bad (_("register number out of range")); |
1787 | } | |
1788 | ||
1789 | tok->X_op = O_register; | |
1790 | tok->X_add_symbol = 0; | |
1791 | tok->X_add_number = reg; | |
1792 | } | |
1793 | } | |
1794 | ||
1795 | ||
1796 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1797 | ||
1798 | static int | |
7fa3d080 | 1799 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1800 | { |
1801 | char *old_input_line_pointer; | |
1802 | bfd_boolean saw_comma = FALSE; | |
1803 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1804 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1805 | int num_args = 0; |
1806 | char *arg_end, *arg; | |
1807 | int arg_len; | |
43cd72b9 BW |
1808 | |
1809 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1810 | old_input_line_pointer = input_line_pointer; |
1811 | input_line_pointer = str; | |
1812 | ||
1813 | while (*input_line_pointer) | |
1814 | { | |
1815 | SKIP_WHITESPACE (); | |
1816 | switch (*input_line_pointer) | |
1817 | { | |
1818 | case '\0': | |
43cd72b9 | 1819 | case '}': |
e0001a05 NC |
1820 | goto fini; |
1821 | ||
43cd72b9 BW |
1822 | case ':': |
1823 | input_line_pointer++; | |
1824 | if (saw_comma || saw_colon || !saw_arg) | |
1825 | goto err; | |
1826 | saw_colon = TRUE; | |
1827 | break; | |
1828 | ||
e0001a05 NC |
1829 | case ',': |
1830 | input_line_pointer++; | |
43cd72b9 | 1831 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
1832 | goto err; |
1833 | saw_comma = TRUE; | |
1834 | break; | |
1835 | ||
1836 | default: | |
43cd72b9 | 1837 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
1838 | goto err; |
1839 | ||
1840 | arg_end = input_line_pointer + 1; | |
1841 | while (!expression_end (arg_end)) | |
1842 | arg_end += 1; | |
43cd72b9 | 1843 | |
e0001a05 | 1844 | arg_len = arg_end - input_line_pointer; |
43cd72b9 | 1845 | arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
1846 | args[num_args] = arg; |
1847 | ||
43cd72b9 BW |
1848 | if (saw_colon) |
1849 | *arg++ = ':'; | |
e0001a05 NC |
1850 | strncpy (arg, input_line_pointer, arg_len); |
1851 | arg[arg_len] = '\0'; | |
43cd72b9 | 1852 | |
e0001a05 NC |
1853 | input_line_pointer = arg_end; |
1854 | num_args += 1; | |
c138bc38 | 1855 | saw_comma = FALSE; |
43cd72b9 | 1856 | saw_colon = FALSE; |
c138bc38 | 1857 | saw_arg = TRUE; |
e0001a05 NC |
1858 | break; |
1859 | } | |
1860 | } | |
1861 | ||
1862 | fini: | |
43cd72b9 | 1863 | if (saw_comma || saw_colon) |
e0001a05 NC |
1864 | goto err; |
1865 | input_line_pointer = old_input_line_pointer; | |
1866 | return num_args; | |
1867 | ||
1868 | err: | |
43cd72b9 BW |
1869 | if (saw_comma) |
1870 | as_bad (_("extra comma")); | |
1871 | else if (saw_colon) | |
1872 | as_bad (_("extra colon")); | |
1873 | else if (!saw_arg) | |
c138bc38 | 1874 | as_bad (_("missing argument")); |
43cd72b9 BW |
1875 | else |
1876 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
1877 | input_line_pointer = old_input_line_pointer; |
1878 | return -1; | |
1879 | } | |
1880 | ||
1881 | ||
43cd72b9 | 1882 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
1883 | |
1884 | static bfd_boolean | |
7fa3d080 | 1885 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 1886 | { |
43cd72b9 | 1887 | expressionS *tok, *last_tok; |
e0001a05 NC |
1888 | xtensa_opcode opcode = insn->opcode; |
1889 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
1890 | xtensa_isa isa = xtensa_default_isa; |
1891 | int n, num_regs = 0; | |
e0001a05 | 1892 | int opcode_operand_count; |
43cd72b9 BW |
1893 | int opnd_cnt, last_opnd_cnt; |
1894 | unsigned int next_reg = 0; | |
e0001a05 NC |
1895 | char *old_input_line_pointer; |
1896 | ||
1897 | if (insn->insn_type == ITYPE_LITERAL) | |
1898 | opcode_operand_count = 1; | |
1899 | else | |
43cd72b9 | 1900 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 1901 | |
43cd72b9 | 1902 | tok = insn->tok; |
e0001a05 NC |
1903 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
1904 | ||
1905 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
1906 | old_input_line_pointer = input_line_pointer; |
1907 | ||
1908 | last_tok = 0; | |
1909 | last_opnd_cnt = -1; | |
1910 | opnd_cnt = 0; | |
1911 | ||
1912 | /* Skip invisible operands. */ | |
1913 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
1914 | { | |
1915 | opnd_cnt += 1; | |
1916 | tok++; | |
1917 | } | |
e0001a05 NC |
1918 | |
1919 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 1920 | { |
e0001a05 | 1921 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
1922 | if (*input_line_pointer == ':') |
1923 | { | |
1924 | xtensa_regfile opnd_rf; | |
1925 | input_line_pointer++; | |
1926 | if (num_regs == 0) | |
1927 | goto err; | |
1928 | assert (opnd_cnt > 0); | |
1929 | num_regs--; | |
1930 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
1931 | if (next_reg | |
1932 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
1933 | as_warn (_("incorrect register number, ignoring")); | |
1934 | next_reg++; | |
1935 | } | |
1936 | else | |
1937 | { | |
1938 | if (opnd_cnt >= opcode_operand_count) | |
1939 | { | |
1940 | as_warn (_("too many arguments")); | |
1941 | goto err; | |
1942 | } | |
1943 | assert (opnd_cnt < MAX_INSN_ARGS); | |
1944 | ||
1945 | expression_maybe_register (opcode, opnd_cnt, tok); | |
1946 | next_reg = tok->X_add_number + 1; | |
1947 | ||
1948 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
1949 | goto err; | |
1950 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
1951 | { | |
1952 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
1953 | /* minus 1 because we are seeing one right now */ | |
1954 | } | |
1955 | else | |
1956 | num_regs = 0; | |
e0001a05 | 1957 | |
43cd72b9 BW |
1958 | last_tok = tok; |
1959 | last_opnd_cnt = opnd_cnt; | |
e0001a05 | 1960 | |
43cd72b9 BW |
1961 | do |
1962 | { | |
1963 | opnd_cnt += 1; | |
1964 | tok++; | |
1965 | } | |
1966 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
1967 | } | |
1968 | } | |
e0001a05 | 1969 | |
43cd72b9 BW |
1970 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
1971 | goto err; | |
e0001a05 NC |
1972 | |
1973 | insn->ntok = tok - insn->tok; | |
c138bc38 | 1974 | had_error = FALSE; |
e0001a05 NC |
1975 | |
1976 | err: | |
43cd72b9 | 1977 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
1978 | return had_error; |
1979 | } | |
1980 | ||
1981 | ||
43cd72b9 | 1982 | static int |
7fa3d080 | 1983 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
1984 | { |
1985 | xtensa_isa isa = xtensa_default_isa; | |
1986 | static xtensa_insnbuf slotbuf = NULL; | |
1987 | xtensa_format fmt; | |
1988 | xtensa_opcode opc = insn->opcode; | |
1989 | int slot, opnd, fmt_found; | |
1990 | unsigned val; | |
1991 | ||
1992 | if (!slotbuf) | |
1993 | slotbuf = xtensa_insnbuf_alloc (isa); | |
1994 | ||
1995 | /* Find format/slot where this can be encoded. */ | |
1996 | fmt_found = 0; | |
1997 | slot = 0; | |
1998 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
1999 | { | |
2000 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2001 | { | |
2002 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2003 | { | |
2004 | fmt_found = 1; | |
2005 | break; | |
2006 | } | |
2007 | } | |
2008 | if (fmt_found) break; | |
2009 | } | |
2010 | ||
2011 | if (!fmt_found) | |
2012 | { | |
2013 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2014 | return -1; | |
2015 | } | |
2016 | ||
2017 | /* First encode all the visible operands | |
2018 | (to deal with shared field operands). */ | |
2019 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2020 | { | |
2021 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2022 | && (insn->tok[opnd].X_op == O_register | |
2023 | || insn->tok[opnd].X_op == O_constant)) | |
2024 | { | |
2025 | val = insn->tok[opnd].X_add_number; | |
2026 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2027 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2028 | } | |
2029 | } | |
2030 | ||
2031 | /* Then pull out the values for the invisible ones. */ | |
2032 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2033 | { | |
2034 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2035 | { | |
2036 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2037 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2038 | insn->tok[opnd].X_add_number = val; | |
2039 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2040 | insn->tok[opnd].X_op = O_register; | |
2041 | else | |
2042 | insn->tok[opnd].X_op = O_constant; | |
2043 | } | |
2044 | } | |
2045 | ||
2046 | return 0; | |
2047 | } | |
2048 | ||
2049 | ||
e0001a05 | 2050 | static void |
7fa3d080 | 2051 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2052 | { |
2053 | char *cnt_arg, *new_arg; | |
2054 | cnt_arg = *cnt_argp; | |
2055 | ||
2056 | /* replace the argument with "31-(argument)" */ | |
2057 | new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); | |
2058 | sprintf (new_arg, "31-(%s)", cnt_arg); | |
2059 | ||
2060 | free (cnt_arg); | |
2061 | *cnt_argp = new_arg; | |
2062 | } | |
2063 | ||
2064 | ||
2065 | /* If "arg" is a constant expression, return non-zero with the value | |
2066 | in *valp. */ | |
2067 | ||
2068 | static int | |
7fa3d080 | 2069 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2070 | { |
2071 | expressionS exp; | |
2072 | char *save_ptr = input_line_pointer; | |
2073 | ||
2074 | input_line_pointer = arg; | |
2075 | expression (&exp); | |
2076 | input_line_pointer = save_ptr; | |
2077 | ||
2078 | if (exp.X_op == O_constant) | |
2079 | { | |
2080 | *valp = exp.X_add_number; | |
2081 | return 1; | |
2082 | } | |
2083 | ||
2084 | return 0; | |
2085 | } | |
2086 | ||
2087 | ||
2088 | static void | |
7fa3d080 | 2089 | xg_replace_opname (char **popname, char *newop) |
e0001a05 NC |
2090 | { |
2091 | free (*popname); | |
2092 | *popname = (char *) xmalloc (strlen (newop) + 1); | |
2093 | strcpy (*popname, newop); | |
2094 | } | |
2095 | ||
2096 | ||
2097 | static int | |
7fa3d080 BW |
2098 | xg_check_num_args (int *pnum_args, |
2099 | int expected_num, | |
2100 | char *opname, | |
2101 | char **arg_strings) | |
e0001a05 NC |
2102 | { |
2103 | int num_args = *pnum_args; | |
2104 | ||
43cd72b9 | 2105 | if (num_args < expected_num) |
e0001a05 NC |
2106 | { |
2107 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2108 | num_args, opname, expected_num); | |
2109 | return -1; | |
2110 | } | |
2111 | ||
2112 | if (num_args > expected_num) | |
2113 | { | |
2114 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2115 | num_args, opname, expected_num); | |
2116 | while (num_args-- > expected_num) | |
2117 | { | |
2118 | free (arg_strings[num_args]); | |
2119 | arg_strings[num_args] = 0; | |
2120 | } | |
2121 | *pnum_args = expected_num; | |
2122 | return -1; | |
2123 | } | |
2124 | ||
2125 | return 0; | |
2126 | } | |
2127 | ||
2128 | ||
43cd72b9 BW |
2129 | /* If the register is not specified as part of the opcode, |
2130 | then get it from the operand and move it to the opcode. */ | |
2131 | ||
e0001a05 | 2132 | static int |
7fa3d080 | 2133 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2134 | { |
43cd72b9 BW |
2135 | xtensa_isa isa = xtensa_default_isa; |
2136 | xtensa_sysreg sr; | |
e0001a05 | 2137 | char *opname, *new_opname; |
43cd72b9 BW |
2138 | const char *sr_name; |
2139 | int is_user, is_write; | |
e0001a05 NC |
2140 | |
2141 | opname = *popname; | |
2142 | if (*opname == '_') | |
80ca4e2c | 2143 | opname += 1; |
43cd72b9 BW |
2144 | is_user = (opname[1] == 'u'); |
2145 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2146 | |
43cd72b9 | 2147 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2148 | |
43cd72b9 BW |
2149 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2150 | return -1; | |
e0001a05 | 2151 | |
43cd72b9 BW |
2152 | /* Check if the argument is a symbolic register name. */ |
2153 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2154 | /* Handle WSR to "INTSET" as a special case. */ | |
2155 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2156 | && !strcasecmp (arg_strings[1], "intset")) | |
2157 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2158 | if (sr == XTENSA_UNDEFINED | |
2159 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2160 | { | |
2161 | /* Maybe it's a register number.... */ | |
2162 | offsetT val; | |
e0001a05 NC |
2163 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2164 | { | |
43cd72b9 BW |
2165 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2166 | arg_strings[1], opname); | |
e0001a05 NC |
2167 | return -1; |
2168 | } | |
43cd72b9 BW |
2169 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2170 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2171 | { |
43cd72b9 | 2172 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2173 | (long) val, opname); |
e0001a05 NC |
2174 | return -1; |
2175 | } | |
43cd72b9 | 2176 | } |
e0001a05 | 2177 | |
43cd72b9 BW |
2178 | /* Remove the last argument, which is now part of the opcode. */ |
2179 | free (arg_strings[1]); | |
2180 | arg_strings[1] = 0; | |
2181 | *pnum_args = 1; | |
2182 | ||
2183 | /* Translate the opcode. */ | |
2184 | sr_name = xtensa_sysreg_name (isa, sr); | |
2185 | /* Another special case for "WSR.INTSET".... */ | |
2186 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2187 | sr_name = "intset"; | |
2188 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
80ca4e2c | 2189 | sprintf (new_opname, "%s.%s", *popname, sr_name); |
43cd72b9 BW |
2190 | free (*popname); |
2191 | *popname = new_opname; | |
2192 | ||
2193 | return 0; | |
2194 | } | |
2195 | ||
2196 | ||
2197 | static int | |
7fa3d080 | 2198 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2199 | { |
2200 | xtensa_isa isa = xtensa_default_isa; | |
2201 | xtensa_sysreg sr; | |
2202 | char *opname, *new_opname; | |
2203 | const char *sr_name; | |
2204 | bfd_boolean has_underbar = FALSE; | |
2205 | ||
2206 | opname = *popname; | |
2207 | if (opname[0] == '_') | |
2208 | { | |
2209 | has_underbar = TRUE; | |
2210 | opname += 1; | |
2211 | } | |
2212 | ||
2213 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2214 | if (sr != XTENSA_UNDEFINED) | |
2215 | { | |
2216 | /* The new default name ("nnn") is different from the old default | |
2217 | name ("URnnn"). The old default is handled below, and we don't | |
2218 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2219 | default. */ | |
2220 | static char namebuf[10]; | |
2221 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2222 | if (strcmp (namebuf, opname + 1) == 0) | |
2223 | return 0; | |
2224 | } | |
2225 | else | |
2226 | { | |
2227 | offsetT val; | |
2228 | char *end; | |
2229 | ||
2230 | /* Only continue if the reg name is "URnnn". */ | |
2231 | if (opname[1] != 'u' || opname[2] != 'r') | |
2232 | return 0; | |
2233 | val = strtoul (opname + 3, &end, 10); | |
2234 | if (*end != '\0') | |
2235 | return 0; | |
2236 | ||
2237 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2238 | if (sr == XTENSA_UNDEFINED) | |
2239 | { | |
2240 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2241 | (long) val, opname); |
43cd72b9 BW |
2242 | return -1; |
2243 | } | |
2244 | } | |
2245 | ||
2246 | /* Translate the opcode. */ | |
2247 | sr_name = xtensa_sysreg_name (isa, sr); | |
2248 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
2249 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), | |
2250 | opname[0], sr_name); | |
2251 | free (*popname); | |
2252 | *popname = new_opname; | |
2253 | ||
2254 | return 0; | |
2255 | } | |
2256 | ||
2257 | ||
2258 | static int | |
7fa3d080 BW |
2259 | xtensa_translate_zero_immed (char *old_op, |
2260 | char *new_op, | |
2261 | char **popname, | |
2262 | int *pnum_args, | |
2263 | char **arg_strings) | |
43cd72b9 BW |
2264 | { |
2265 | char *opname; | |
2266 | offsetT val; | |
2267 | ||
2268 | opname = *popname; | |
2269 | assert (opname[0] != '_'); | |
2270 | ||
2271 | if (strcmp (opname, old_op) != 0) | |
2272 | return 0; | |
e0001a05 | 2273 | |
43cd72b9 BW |
2274 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2275 | return -1; | |
2276 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2277 | { | |
2278 | xg_replace_opname (popname, new_op); | |
2279 | free (arg_strings[1]); | |
2280 | arg_strings[1] = arg_strings[2]; | |
2281 | arg_strings[2] = 0; | |
2282 | *pnum_args = 2; | |
e0001a05 NC |
2283 | } |
2284 | ||
2285 | return 0; | |
2286 | } | |
2287 | ||
2288 | ||
2289 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2290 | Returns non-zero if an error was found. */ | |
2291 | ||
2292 | static int | |
7fa3d080 | 2293 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2294 | { |
2295 | char *opname = *popname; | |
2296 | bfd_boolean has_underbar = FALSE; | |
2297 | ||
43cd72b9 BW |
2298 | if (cur_vinsn.inside_bundle) |
2299 | return 0; | |
2300 | ||
e0001a05 NC |
2301 | if (*opname == '_') |
2302 | { | |
2303 | has_underbar = TRUE; | |
2304 | opname += 1; | |
2305 | } | |
2306 | ||
2307 | if (strcmp (opname, "mov") == 0) | |
2308 | { | |
43cd72b9 | 2309 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2310 | xg_replace_opname (popname, "mov.n"); |
2311 | else | |
2312 | { | |
2313 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2314 | return -1; | |
2315 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2316 | arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); | |
2317 | strcpy (arg_strings[2], arg_strings[1]); | |
2318 | *pnum_args = 3; | |
2319 | } | |
2320 | return 0; | |
2321 | } | |
2322 | ||
2323 | if (strcmp (opname, "bbsi.l") == 0) | |
2324 | { | |
2325 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2326 | return -1; | |
2327 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2328 | if (target_big_endian) | |
2329 | xg_reverse_shift_count (&arg_strings[1]); | |
2330 | return 0; | |
2331 | } | |
2332 | ||
2333 | if (strcmp (opname, "bbci.l") == 0) | |
2334 | { | |
2335 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2336 | return -1; | |
2337 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2338 | if (target_big_endian) | |
2339 | xg_reverse_shift_count (&arg_strings[1]); | |
2340 | return 0; | |
2341 | } | |
2342 | ||
43cd72b9 BW |
2343 | if (xtensa_nop_opcode == XTENSA_UNDEFINED |
2344 | && strcmp (opname, "nop") == 0) | |
e0001a05 | 2345 | { |
43cd72b9 | 2346 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2347 | xg_replace_opname (popname, "nop.n"); |
2348 | else | |
2349 | { | |
2350 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2351 | return -1; | |
2352 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2353 | arg_strings[0] = (char *) xmalloc (3); | |
2354 | arg_strings[1] = (char *) xmalloc (3); | |
2355 | arg_strings[2] = (char *) xmalloc (3); | |
2356 | strcpy (arg_strings[0], "a1"); | |
2357 | strcpy (arg_strings[1], "a1"); | |
2358 | strcpy (arg_strings[2], "a1"); | |
2359 | *pnum_args = 3; | |
2360 | } | |
2361 | return 0; | |
2362 | } | |
2363 | ||
43cd72b9 BW |
2364 | /* Recognize [RW]UR and [RWX]SR. */ |
2365 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2366 | && (opname[1] == 'u' || opname[1] == 's')) | |
2367 | || (opname[0] == 'x' && opname[1] == 's')) | |
2368 | && opname[2] == 'r' | |
2369 | && opname[3] == '\0') | |
e0001a05 NC |
2370 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2371 | ||
43cd72b9 BW |
2372 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2373 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2374 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2375 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2376 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2377 | |
43cd72b9 BW |
2378 | /* Relax branches that don't allow comparisons against an immediate value |
2379 | of zero to the corresponding branches with implicit zero immediates. */ | |
2380 | if (!has_underbar && use_transform ()) | |
2381 | { | |
2382 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2383 | pnum_args, arg_strings)) | |
2384 | return -1; | |
e0001a05 | 2385 | |
43cd72b9 BW |
2386 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2387 | pnum_args, arg_strings)) | |
2388 | return -1; | |
e0001a05 | 2389 | |
43cd72b9 BW |
2390 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2391 | pnum_args, arg_strings)) | |
2392 | return -1; | |
e0001a05 | 2393 | |
43cd72b9 BW |
2394 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2395 | pnum_args, arg_strings)) | |
2396 | return -1; | |
2397 | } | |
e0001a05 | 2398 | |
43cd72b9 BW |
2399 | return 0; |
2400 | } | |
e0001a05 | 2401 | |
43cd72b9 BW |
2402 | \f |
2403 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2404 | |
43cd72b9 BW |
2405 | /* Currently the assembler only allows us to use a single target per |
2406 | fragment. Because of this, only one operand for a given | |
2407 | instruction may be symbolic. If there is a PC-relative operand, | |
2408 | the last one is chosen. Otherwise, the result is the number of the | |
2409 | last immediate operand, and if there are none of those, we fail and | |
2410 | return -1. */ | |
e0001a05 | 2411 | |
7fa3d080 BW |
2412 | static int |
2413 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2414 | { |
2415 | int last_immed = -1; | |
2416 | int noperands, opi; | |
e0001a05 | 2417 | |
43cd72b9 BW |
2418 | if (opcode == XTENSA_UNDEFINED) |
2419 | return -1; | |
e0001a05 | 2420 | |
43cd72b9 BW |
2421 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2422 | for (opi = noperands - 1; opi >= 0; opi--) | |
2423 | { | |
2424 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2425 | continue; | |
2426 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2427 | return opi; | |
2428 | if (last_immed == -1 | |
2429 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2430 | last_immed = opi; | |
e0001a05 | 2431 | } |
43cd72b9 | 2432 | return last_immed; |
e0001a05 NC |
2433 | } |
2434 | ||
e0001a05 | 2435 | |
43cd72b9 | 2436 | static xtensa_opcode |
7fa3d080 | 2437 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2438 | { |
43cd72b9 BW |
2439 | static xtensa_insnbuf insnbuf = NULL; |
2440 | static xtensa_insnbuf slotbuf = NULL; | |
2441 | xtensa_isa isa = xtensa_default_isa; | |
2442 | xtensa_format fmt; | |
2443 | ||
2444 | if (!insnbuf) | |
e0001a05 | 2445 | { |
43cd72b9 BW |
2446 | insnbuf = xtensa_insnbuf_alloc (isa); |
2447 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2448 | } |
e0001a05 | 2449 | |
d77b99c9 | 2450 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2451 | fmt = xtensa_format_decode (isa, insnbuf); |
2452 | if (fmt == XTENSA_UNDEFINED) | |
2453 | return XTENSA_UNDEFINED; | |
e0001a05 | 2454 | |
43cd72b9 BW |
2455 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2456 | return XTENSA_UNDEFINED; | |
e0001a05 | 2457 | |
43cd72b9 BW |
2458 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2459 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2460 | } |
2461 | ||
2462 | ||
43cd72b9 | 2463 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2464 | |
43cd72b9 | 2465 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2466 | |
7fa3d080 BW |
2467 | static void |
2468 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2469 | { |
2470 | int num_opcodes, num_operands; | |
2471 | xtensa_opcode opcode; | |
2472 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2473 | |
43cd72b9 BW |
2474 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2475 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2476 | { |
43cd72b9 BW |
2477 | int opn; |
2478 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2479 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2480 | for (opn = 0; opn < num_operands; opn++) | |
2481 | { | |
2482 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2483 | continue; | |
2484 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2485 | { | |
2486 | xtensa_regfile opnd_rf = | |
2487 | xtensa_operand_regfile (isa, opcode, opn); | |
2488 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2489 | } | |
2490 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2491 | fputs ("[lLr] ", stderr); | |
2492 | else | |
2493 | fputs ("i ", stderr); | |
2494 | } | |
2495 | fprintf (stderr, "\n"); | |
e0001a05 | 2496 | } |
e0001a05 NC |
2497 | } |
2498 | ||
2499 | ||
43cd72b9 | 2500 | static void |
7fa3d080 | 2501 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2502 | { |
e0001a05 | 2503 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2504 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2505 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2506 | int op; | |
e0001a05 | 2507 | |
43cd72b9 | 2508 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2509 | |
43cd72b9 BW |
2510 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2511 | { | |
2512 | xtensa_opcode opcode; | |
2513 | const char *opname; | |
2514 | int operands; | |
2515 | ||
2516 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2517 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2518 | opname = xtensa_opcode_name (isa, opcode); | |
2519 | ||
2520 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2521 | fprintf (stderr, " operands = "); | |
2522 | for (operands = 0; | |
2523 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2524 | operands++) | |
2525 | { | |
2526 | unsigned int val; | |
2527 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2528 | continue; | |
2529 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2530 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2531 | fprintf (stderr, "%d ", val); | |
2532 | } | |
2533 | fprintf (stderr, "\n"); | |
2534 | } | |
2535 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2536 | } |
2537 | ||
43cd72b9 BW |
2538 | #endif /* TENSILICA_DEBUG */ |
2539 | ||
e0001a05 NC |
2540 | |
2541 | static bfd_boolean | |
7fa3d080 | 2542 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2543 | { |
43cd72b9 BW |
2544 | xtensa_isa isa = xtensa_default_isa; |
2545 | int n, num_operands; | |
e0001a05 | 2546 | |
64b607e6 | 2547 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
e0001a05 NC |
2548 | return FALSE; |
2549 | ||
43cd72b9 BW |
2550 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2551 | for (n = 0; n < num_operands; n++) | |
2552 | { | |
2553 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2554 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2555 | return TRUE; | |
2556 | } | |
2557 | return FALSE; | |
e0001a05 NC |
2558 | } |
2559 | ||
2560 | ||
43cd72b9 BW |
2561 | /* Convert from BFD relocation type code to slot and operand number. |
2562 | Returns non-zero on failure. */ | |
e0001a05 | 2563 | |
43cd72b9 | 2564 | static int |
7fa3d080 | 2565 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2566 | { |
43cd72b9 BW |
2567 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2568 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2569 | { |
43cd72b9 BW |
2570 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2571 | *is_alt = FALSE; | |
e0001a05 | 2572 | } |
43cd72b9 BW |
2573 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2574 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2575 | { |
43cd72b9 BW |
2576 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2577 | *is_alt = TRUE; | |
e0001a05 | 2578 | } |
43cd72b9 BW |
2579 | else |
2580 | return -1; | |
2581 | ||
2582 | return 0; | |
e0001a05 NC |
2583 | } |
2584 | ||
2585 | ||
43cd72b9 BW |
2586 | /* Convert from slot number to BFD relocation type code for the |
2587 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2588 | failure. */ | |
e0001a05 | 2589 | |
43cd72b9 | 2590 | static bfd_reloc_code_real_type |
7fa3d080 | 2591 | encode_reloc (int slot) |
e0001a05 | 2592 | { |
43cd72b9 BW |
2593 | if (slot < 0 || slot > 14) |
2594 | return BFD_RELOC_NONE; | |
2595 | ||
2596 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2597 | } |
2598 | ||
2599 | ||
43cd72b9 BW |
2600 | /* Convert from slot numbers to BFD relocation type code for the |
2601 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2602 | |
43cd72b9 | 2603 | static bfd_reloc_code_real_type |
7fa3d080 | 2604 | encode_alt_reloc (int slot) |
e0001a05 | 2605 | { |
43cd72b9 BW |
2606 | if (slot < 0 || slot > 14) |
2607 | return BFD_RELOC_NONE; | |
2608 | ||
2609 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2610 | } |
2611 | ||
2612 | ||
2613 | static void | |
7fa3d080 BW |
2614 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2615 | xtensa_format fmt, | |
2616 | int slot, | |
2617 | xtensa_opcode opcode, | |
2618 | int operand, | |
2619 | uint32 value, | |
2620 | const char *file, | |
2621 | unsigned int line) | |
e0001a05 | 2622 | { |
e0001a05 NC |
2623 | uint32 valbuf = value; |
2624 | ||
43cd72b9 | 2625 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2626 | { |
43cd72b9 BW |
2627 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2628 | == 1) | |
2629 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2630 | _("operand %d of '%s' has out of range value '%u'"), |
2631 | operand + 1, | |
2632 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2633 | value); | |
43cd72b9 BW |
2634 | else |
2635 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2636 | _("operand %d of '%s' has invalid value '%u'"), |
2637 | operand + 1, | |
2638 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2639 | value); | |
43cd72b9 | 2640 | return; |
e0001a05 NC |
2641 | } |
2642 | ||
43cd72b9 BW |
2643 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2644 | slotbuf, valbuf); | |
e0001a05 NC |
2645 | } |
2646 | ||
2647 | ||
2648 | static uint32 | |
7fa3d080 BW |
2649 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2650 | xtensa_format fmt, | |
2651 | int slot, | |
2652 | xtensa_opcode opcode, | |
2653 | int opnum) | |
e0001a05 | 2654 | { |
43cd72b9 BW |
2655 | uint32 val = 0; |
2656 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2657 | fmt, slot, slotbuf, &val); | |
2658 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2659 | return val; | |
e0001a05 NC |
2660 | } |
2661 | ||
e0001a05 | 2662 | \f |
7fa3d080 | 2663 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2664 | |
7fa3d080 BW |
2665 | /* The routine xg_instruction_matches_option_term must return TRUE |
2666 | when a given option term is true. The meaning of all of the option | |
2667 | terms is given interpretation by this function. This is needed when | |
2668 | an option depends on the state of a directive, but there are no such | |
2669 | options in use right now. */ | |
e0001a05 | 2670 | |
7fa3d080 BW |
2671 | static bfd_boolean |
2672 | xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED, | |
2673 | const ReqOrOption *option) | |
e0001a05 | 2674 | { |
7fa3d080 BW |
2675 | if (strcmp (option->option_name, "realnop") == 0 |
2676 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2677 | { | |
2678 | /* These conditions were evaluated statically when building the | |
2679 | relaxation table. There's no need to reevaluate them now. */ | |
2680 | return TRUE; | |
2681 | } | |
2682 | else | |
2683 | { | |
2684 | as_fatal (_("internal error: unknown option name '%s'"), | |
2685 | option->option_name); | |
2686 | } | |
e0001a05 NC |
2687 | } |
2688 | ||
2689 | ||
7fa3d080 BW |
2690 | static bfd_boolean |
2691 | xg_instruction_matches_or_options (TInsn *insn, | |
2692 | const ReqOrOptionList *or_option) | |
e0001a05 | 2693 | { |
7fa3d080 BW |
2694 | const ReqOrOption *option; |
2695 | /* Must match each of the AND terms. */ | |
2696 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2697 | { |
7fa3d080 BW |
2698 | if (xg_instruction_matches_option_term (insn, option)) |
2699 | return TRUE; | |
e0001a05 | 2700 | } |
7fa3d080 | 2701 | return FALSE; |
e0001a05 NC |
2702 | } |
2703 | ||
2704 | ||
7fa3d080 BW |
2705 | static bfd_boolean |
2706 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2707 | { |
7fa3d080 BW |
2708 | const ReqOption *req_options; |
2709 | /* Must match each of the AND terms. */ | |
2710 | for (req_options = options; | |
2711 | req_options != NULL; | |
2712 | req_options = req_options->next) | |
e0001a05 | 2713 | { |
7fa3d080 BW |
2714 | /* Must match one of the OR clauses. */ |
2715 | if (!xg_instruction_matches_or_options (insn, | |
2716 | req_options->or_option_terms)) | |
2717 | return FALSE; | |
e0001a05 | 2718 | } |
7fa3d080 | 2719 | return TRUE; |
e0001a05 NC |
2720 | } |
2721 | ||
2722 | ||
7fa3d080 | 2723 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2724 | |
7fa3d080 BW |
2725 | static bfd_boolean |
2726 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2727 | { |
7fa3d080 | 2728 | PreconditionList *condition_l; |
e0001a05 | 2729 | |
7fa3d080 BW |
2730 | if (rule->opcode != insn->opcode) |
2731 | return FALSE; | |
e0001a05 | 2732 | |
7fa3d080 BW |
2733 | for (condition_l = rule->conditions; |
2734 | condition_l != NULL; | |
2735 | condition_l = condition_l->next) | |
e0001a05 | 2736 | { |
7fa3d080 BW |
2737 | expressionS *exp1; |
2738 | expressionS *exp2; | |
2739 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2740 | |
7fa3d080 | 2741 | switch (cond->typ) |
e0001a05 | 2742 | { |
7fa3d080 BW |
2743 | case OP_CONSTANT: |
2744 | /* The expression must be the constant. */ | |
2745 | assert (cond->op_num < insn->ntok); | |
2746 | exp1 = &insn->tok[cond->op_num]; | |
2747 | if (expr_is_const (exp1)) | |
2748 | { | |
2749 | switch (cond->cmp) | |
2750 | { | |
2751 | case OP_EQUAL: | |
2752 | if (get_expr_const (exp1) != cond->op_data) | |
2753 | return FALSE; | |
2754 | break; | |
2755 | case OP_NOTEQUAL: | |
2756 | if (get_expr_const (exp1) == cond->op_data) | |
2757 | return FALSE; | |
2758 | break; | |
2759 | default: | |
2760 | return FALSE; | |
2761 | } | |
2762 | } | |
2763 | else if (expr_is_register (exp1)) | |
2764 | { | |
2765 | switch (cond->cmp) | |
2766 | { | |
2767 | case OP_EQUAL: | |
2768 | if (get_expr_register (exp1) != cond->op_data) | |
2769 | return FALSE; | |
2770 | break; | |
2771 | case OP_NOTEQUAL: | |
2772 | if (get_expr_register (exp1) == cond->op_data) | |
2773 | return FALSE; | |
2774 | break; | |
2775 | default: | |
2776 | return FALSE; | |
2777 | } | |
2778 | } | |
2779 | else | |
2780 | return FALSE; | |
2781 | break; | |
2782 | ||
2783 | case OP_OPERAND: | |
2784 | assert (cond->op_num < insn->ntok); | |
2785 | assert (cond->op_data < insn->ntok); | |
2786 | exp1 = &insn->tok[cond->op_num]; | |
2787 | exp2 = &insn->tok[cond->op_data]; | |
2788 | ||
2789 | switch (cond->cmp) | |
2790 | { | |
2791 | case OP_EQUAL: | |
2792 | if (!expr_is_equal (exp1, exp2)) | |
2793 | return FALSE; | |
2794 | break; | |
2795 | case OP_NOTEQUAL: | |
2796 | if (expr_is_equal (exp1, exp2)) | |
2797 | return FALSE; | |
2798 | break; | |
2799 | } | |
2800 | break; | |
2801 | ||
2802 | case OP_LITERAL: | |
2803 | case OP_LABEL: | |
2804 | default: | |
2805 | return FALSE; | |
2806 | } | |
2807 | } | |
2808 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2809 | return FALSE; | |
2810 | ||
2811 | return TRUE; | |
2812 | } | |
2813 | ||
2814 | ||
2815 | static int | |
2816 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2817 | { | |
2818 | bfd_boolean a_greater = FALSE; | |
2819 | bfd_boolean b_greater = FALSE; | |
2820 | ||
2821 | ReqOptionList *l_a = a->options; | |
2822 | ReqOptionList *l_b = b->options; | |
2823 | ||
2824 | /* We only care if they both are the same except for | |
2825 | a const16 vs. an l32r. */ | |
2826 | ||
2827 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2828 | { | |
2829 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2830 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2831 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2832 | { | |
2833 | if (l_or_a->is_true != l_or_b->is_true) | |
2834 | return 0; | |
2835 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2836 | { | |
2837 | /* This is the case we care about. */ | |
2838 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
2839 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
2840 | { | |
2841 | if (prefer_const16) | |
2842 | a_greater = TRUE; | |
2843 | else | |
2844 | b_greater = TRUE; | |
2845 | } | |
2846 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
2847 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
2848 | { | |
2849 | if (prefer_const16) | |
2850 | b_greater = TRUE; | |
2851 | else | |
2852 | a_greater = TRUE; | |
2853 | } | |
2854 | else | |
2855 | return 0; | |
2856 | } | |
2857 | l_or_a = l_or_a->next; | |
2858 | l_or_b = l_or_b->next; | |
2859 | } | |
2860 | if (l_or_a || l_or_b) | |
2861 | return 0; | |
2862 | ||
2863 | l_a = l_a->next; | |
2864 | l_b = l_b->next; | |
2865 | } | |
2866 | if (l_a || l_b) | |
2867 | return 0; | |
2868 | ||
2869 | /* Incomparable if the substitution was used differently in two cases. */ | |
2870 | if (a_greater && b_greater) | |
2871 | return 0; | |
2872 | ||
2873 | if (b_greater) | |
2874 | return 1; | |
2875 | if (a_greater) | |
2876 | return -1; | |
2877 | ||
2878 | return 0; | |
2879 | } | |
2880 | ||
2881 | ||
2882 | static TransitionRule * | |
2883 | xg_instruction_match (TInsn *insn) | |
2884 | { | |
2885 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
2886 | TransitionList *l; | |
2887 | assert (insn->opcode < table->num_opcodes); | |
2888 | ||
2889 | /* Walk through all of the possible transitions. */ | |
2890 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2891 | { | |
2892 | TransitionRule *rule = l->rule; | |
2893 | if (xg_instruction_matches_rule (insn, rule)) | |
2894 | return rule; | |
2895 | } | |
2896 | return NULL; | |
2897 | } | |
2898 | ||
2899 | \f | |
2900 | /* Various Other Internal Functions. */ | |
2901 | ||
2902 | static bfd_boolean | |
2903 | is_unique_insn_expansion (TransitionRule *r) | |
2904 | { | |
2905 | if (!r->to_instr || r->to_instr->next != NULL) | |
2906 | return FALSE; | |
2907 | if (r->to_instr->typ != INSTR_INSTR) | |
2908 | return FALSE; | |
2909 | return TRUE; | |
2910 | } | |
2911 | ||
2912 | ||
84b08ed9 BW |
2913 | /* Check if there is exactly one relaxation for INSN that converts it to |
2914 | another instruction of equal or larger size. If so, and if TARG is | |
2915 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
2916 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
2917 | instruction, i.e., ignore relaxations that convert to an instruction of | |
2918 | equal size. In some contexts where this function is used, only | |
c138bc38 | 2919 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
2920 | exclude cases like ADDI being "widened" to an ADDMI, which may |
2921 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 2922 | |
84b08ed9 BW |
2923 | bfd_boolean |
2924 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
2925 | { |
2926 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
2927 | TransitionList *l; | |
84b08ed9 | 2928 | TransitionRule *match = 0; |
7fa3d080 | 2929 | |
7fa3d080 BW |
2930 | assert (insn->insn_type == ITYPE_INSN); |
2931 | assert (insn->opcode < table->num_opcodes); | |
2932 | ||
2933 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2934 | { | |
2935 | TransitionRule *rule = l->rule; | |
2936 | ||
2937 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
2938 | && is_unique_insn_expansion (rule) |
2939 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
2940 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 2941 | { |
84b08ed9 BW |
2942 | if (match) |
2943 | return FALSE; | |
2944 | match = rule; | |
7fa3d080 BW |
2945 | } |
2946 | } | |
84b08ed9 BW |
2947 | if (!match) |
2948 | return FALSE; | |
2949 | ||
2950 | if (targ) | |
2951 | xg_build_to_insn (targ, insn, match->to_instr); | |
2952 | return TRUE; | |
7fa3d080 BW |
2953 | } |
2954 | ||
2955 | ||
2956 | /* Return the maximum number of bytes this opcode can expand to. */ | |
2957 | ||
2958 | static int | |
2959 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
2960 | { | |
2961 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
2962 | TransitionList *l; | |
2963 | int max_size = xg_get_single_size (opcode); | |
2964 | ||
2965 | assert (opcode < table->num_opcodes); | |
2966 | ||
2967 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
2968 | { | |
2969 | TransitionRule *rule = l->rule; | |
2970 | BuildInstr *build_list; | |
2971 | int this_size = 0; | |
2972 | ||
2973 | if (!rule) | |
2974 | continue; | |
2975 | build_list = rule->to_instr; | |
2976 | if (is_unique_insn_expansion (rule)) | |
2977 | { | |
2978 | assert (build_list->typ == INSTR_INSTR); | |
2979 | this_size = xg_get_max_insn_widen_size (build_list->opcode); | |
2980 | } | |
2981 | else | |
2982 | for (; build_list != NULL; build_list = build_list->next) | |
2983 | { | |
2984 | switch (build_list->typ) | |
2985 | { | |
2986 | case INSTR_INSTR: | |
2987 | this_size += xg_get_single_size (build_list->opcode); | |
2988 | break; | |
2989 | case INSTR_LITERAL_DEF: | |
2990 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
2991 | default: |
2992 | break; | |
2993 | } | |
2994 | } | |
2995 | if (this_size > max_size) | |
2996 | max_size = this_size; | |
2997 | } | |
2998 | return max_size; | |
2999 | } | |
3000 | ||
3001 | ||
3002 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3003 | ||
7fa3d080 BW |
3004 | static int |
3005 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3006 | { |
43cd72b9 | 3007 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3008 | TransitionList *l; |
3009 | int max_size = 0; | |
3010 | ||
3011 | assert (opcode < table->num_opcodes); | |
3012 | ||
3013 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3014 | { | |
3015 | TransitionRule *rule = l->rule; | |
3016 | BuildInstr *build_list; | |
3017 | int this_size = 0; | |
3018 | ||
3019 | if (!rule) | |
3020 | continue; | |
3021 | build_list = rule->to_instr; | |
3022 | if (is_unique_insn_expansion (rule)) | |
3023 | { | |
3024 | assert (build_list->typ == INSTR_INSTR); | |
3025 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); | |
3026 | } | |
3027 | else | |
3028 | for (; build_list != NULL; build_list = build_list->next) | |
3029 | { | |
3030 | switch (build_list->typ) | |
3031 | { | |
3032 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3033 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3034 | this_size += 4; |
3035 | break; | |
3036 | case INSTR_INSTR: | |
3037 | case INSTR_LABEL_DEF: | |
3038 | default: | |
3039 | break; | |
3040 | } | |
3041 | } | |
3042 | if (this_size > max_size) | |
3043 | max_size = this_size; | |
3044 | } | |
3045 | return max_size; | |
3046 | } | |
3047 | ||
3048 | ||
7fa3d080 BW |
3049 | static bfd_boolean |
3050 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3051 | { | |
3052 | int steps_taken = 0; | |
3053 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3054 | TransitionList *l; | |
3055 | ||
3056 | assert (insn->insn_type == ITYPE_INSN); | |
3057 | assert (insn->opcode < table->num_opcodes); | |
3058 | ||
3059 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3060 | { | |
3061 | TransitionRule *rule = l->rule; | |
3062 | ||
3063 | if (xg_instruction_matches_rule (insn, rule)) | |
3064 | { | |
3065 | if (steps_taken == lateral_steps) | |
3066 | return TRUE; | |
3067 | steps_taken++; | |
3068 | } | |
3069 | } | |
3070 | return FALSE; | |
3071 | } | |
3072 | ||
3073 | ||
3074 | static symbolS * | |
3075 | get_special_literal_symbol (void) | |
3076 | { | |
3077 | static symbolS *sym = NULL; | |
3078 | ||
3079 | if (sym == NULL) | |
3080 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3081 | return sym; | |
3082 | } | |
3083 | ||
3084 | ||
3085 | static symbolS * | |
3086 | get_special_label_symbol (void) | |
3087 | { | |
3088 | static symbolS *sym = NULL; | |
3089 | ||
3090 | if (sym == NULL) | |
3091 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3092 | return sym; | |
3093 | } | |
3094 | ||
3095 | ||
3096 | static bfd_boolean | |
3097 | xg_valid_literal_expression (const expressionS *exp) | |
3098 | { | |
3099 | switch (exp->X_op) | |
3100 | { | |
3101 | case O_constant: | |
3102 | case O_symbol: | |
3103 | case O_big: | |
3104 | case O_uminus: | |
3105 | case O_subtract: | |
3106 | case O_pltrel: | |
3107 | return TRUE; | |
3108 | default: | |
3109 | return FALSE; | |
3110 | } | |
3111 | } | |
3112 | ||
3113 | ||
3114 | /* This will check to see if the value can be converted into the | |
3115 | operand type. It will return TRUE if it does not fit. */ | |
3116 | ||
3117 | static bfd_boolean | |
3118 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3119 | { | |
3120 | uint32 valbuf = value; | |
3121 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3122 | return TRUE; | |
3123 | return FALSE; | |
3124 | } | |
3125 | ||
3126 | ||
3127 | /* Assumes: All immeds are constants. Check that all constants fit | |
3128 | into their immeds; return FALSE if not. */ | |
3129 | ||
3130 | static bfd_boolean | |
3131 | xg_immeds_fit (const TInsn *insn) | |
3132 | { | |
3133 | xtensa_isa isa = xtensa_default_isa; | |
3134 | int i; | |
3135 | ||
3136 | int n = insn->ntok; | |
3137 | assert (insn->insn_type == ITYPE_INSN); | |
3138 | for (i = 0; i < n; ++i) | |
3139 | { | |
3140 | const expressionS *expr = &insn->tok[i]; | |
3141 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3142 | continue; | |
3143 | ||
3144 | switch (expr->X_op) | |
3145 | { | |
3146 | case O_register: | |
3147 | case O_constant: | |
3148 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3149 | return FALSE; | |
3150 | break; | |
3151 | ||
3152 | default: | |
3153 | /* The symbol should have a fixup associated with it. */ | |
3154 | assert (FALSE); | |
3155 | break; | |
3156 | } | |
3157 | } | |
3158 | return TRUE; | |
3159 | } | |
3160 | ||
3161 | ||
3162 | /* This should only be called after we have an initial | |
3163 | estimate of the addresses. */ | |
3164 | ||
3165 | static bfd_boolean | |
3166 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3167 | segT pc_seg, | |
3168 | fragS *pc_frag, | |
3169 | offsetT pc_offset, | |
3170 | long stretch) | |
e0001a05 | 3171 | { |
7fa3d080 BW |
3172 | xtensa_isa isa = xtensa_default_isa; |
3173 | symbolS *symbolP; | |
3174 | fragS *sym_frag; | |
3175 | offsetT target, pc; | |
3176 | uint32 new_offset; | |
3177 | int i; | |
3178 | int n = insn->ntok; | |
e0001a05 NC |
3179 | |
3180 | assert (insn->insn_type == ITYPE_INSN); | |
e0001a05 | 3181 | |
7fa3d080 | 3182 | for (i = 0; i < n; ++i) |
e0001a05 | 3183 | { |
7fa3d080 BW |
3184 | const expressionS *expr = &insn->tok[i]; |
3185 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3186 | continue; | |
e0001a05 | 3187 | |
7fa3d080 | 3188 | switch (expr->X_op) |
e0001a05 | 3189 | { |
7fa3d080 BW |
3190 | case O_register: |
3191 | case O_constant: | |
3192 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3193 | return FALSE; | |
3194 | break; | |
e0001a05 | 3195 | |
7fa3d080 BW |
3196 | case O_lo16: |
3197 | case O_hi16: | |
3198 | /* Check for the worst case. */ | |
3199 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3200 | return FALSE; | |
3201 | break; | |
e0001a05 | 3202 | |
7fa3d080 | 3203 | case O_symbol: |
7c834684 | 3204 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3205 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3206 | if (pc_frag == 0 |
3207 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3208 | return FALSE; |
e0001a05 | 3209 | |
7c834684 BW |
3210 | /* If it is a weak symbol, then assume it won't reach. */ |
3211 | if (S_IS_WEAK (expr->X_add_symbol)) | |
7fa3d080 | 3212 | return FALSE; |
e0001a05 | 3213 | |
7c834684 BW |
3214 | if (is_direct_call_opcode (insn->opcode) |
3215 | && ! pc_frag->tc_frag_data.use_longcalls) | |
3216 | { | |
3217 | /* If callee is undefined or in a different segment, be | |
3218 | optimistic and assume it will be in range. */ | |
3219 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
3220 | return TRUE; | |
3221 | } | |
3222 | ||
3223 | /* Only references within a segment can be known to fit in the | |
3224 | operands at assembly time. */ | |
3225 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
7fa3d080 | 3226 | return FALSE; |
e0001a05 | 3227 | |
7fa3d080 BW |
3228 | symbolP = expr->X_add_symbol; |
3229 | sym_frag = symbol_get_frag (symbolP); | |
3230 | target = S_GET_VALUE (symbolP) + expr->X_add_number; | |
3231 | pc = pc_frag->fr_address + pc_offset; | |
e0001a05 | 3232 | |
7fa3d080 BW |
3233 | /* If frag has yet to be reached on this pass, assume it |
3234 | will move by STRETCH just as we did. If this is not so, | |
3235 | it will be because some frag between grows, and that will | |
3236 | force another pass. Beware zero-length frags. There | |
3237 | should be a faster way to do this. */ | |
3238 | ||
3239 | if (stretch != 0 | |
3240 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3241 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3242 | { | |
3243 | target += stretch; | |
3244 | } | |
c138bc38 | 3245 | |
7fa3d080 BW |
3246 | new_offset = target; |
3247 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3248 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3249 | return FALSE; | |
3250 | break; | |
3251 | ||
3252 | default: | |
3253 | /* The symbol should have a fixup associated with it. */ | |
3254 | return FALSE; | |
3255 | } | |
3256 | } | |
3257 | ||
3258 | return TRUE; | |
e0001a05 NC |
3259 | } |
3260 | ||
3261 | ||
43cd72b9 | 3262 | /* Return TRUE on success. */ |
e0001a05 | 3263 | |
7fa3d080 BW |
3264 | static bfd_boolean |
3265 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3266 | { |
3267 | BuildOp *op; | |
3268 | symbolS *sym; | |
3269 | ||
3270 | memset (targ, 0, sizeof (TInsn)); | |
7c430684 | 3271 | targ->linenum = insn->linenum; |
e0001a05 NC |
3272 | switch (bi->typ) |
3273 | { | |
3274 | case INSTR_INSTR: | |
3275 | op = bi->ops; | |
3276 | targ->opcode = bi->opcode; | |
3277 | targ->insn_type = ITYPE_INSN; | |
3278 | targ->is_specific_opcode = FALSE; | |
3279 | ||
3280 | for (; op != NULL; op = op->next) | |
3281 | { | |
3282 | int op_num = op->op_num; | |
3283 | int op_data = op->op_data; | |
3284 | ||
3285 | assert (op->op_num < MAX_INSN_ARGS); | |
3286 | ||
3287 | if (targ->ntok <= op_num) | |
3288 | targ->ntok = op_num + 1; | |
3289 | ||
3290 | switch (op->typ) | |
3291 | { | |
3292 | case OP_CONSTANT: | |
3293 | set_expr_const (&targ->tok[op_num], op_data); | |
3294 | break; | |
3295 | case OP_OPERAND: | |
3296 | assert (op_data < insn->ntok); | |
3297 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3298 | break; | |
3299 | case OP_LITERAL: | |
3300 | sym = get_special_literal_symbol (); | |
3301 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3302 | break; | |
3303 | case OP_LABEL: | |
3304 | sym = get_special_label_symbol (); | |
3305 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3306 | break; | |
43cd72b9 BW |
3307 | case OP_OPERAND_HI16U: |
3308 | case OP_OPERAND_LOW16U: | |
3309 | assert (op_data < insn->ntok); | |
3310 | if (expr_is_const (&insn->tok[op_data])) | |
3311 | { | |
3312 | long val; | |
3313 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3314 | val = xg_apply_userdef_op_fn (op->typ, | |
3315 | targ->tok[op_num]. | |
3316 | X_add_number); | |
3317 | targ->tok[op_num].X_add_number = val; | |
3318 | } | |
3319 | else | |
3320 | { | |
3321 | /* For const16 we can create relocations for these. */ | |
3322 | if (targ->opcode == XTENSA_UNDEFINED | |
3323 | || (targ->opcode != xtensa_const16_opcode)) | |
3324 | return FALSE; | |
3325 | assert (op_data < insn->ntok); | |
3326 | /* Need to build a O_lo16 or O_hi16. */ | |
3327 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3328 | if (targ->tok[op_num].X_op == O_symbol) | |
3329 | { | |
3330 | if (op->typ == OP_OPERAND_HI16U) | |
3331 | targ->tok[op_num].X_op = O_hi16; | |
3332 | else if (op->typ == OP_OPERAND_LOW16U) | |
3333 | targ->tok[op_num].X_op = O_lo16; | |
3334 | else | |
3335 | return FALSE; | |
3336 | } | |
3337 | } | |
3338 | break; | |
e0001a05 NC |
3339 | default: |
3340 | /* currently handles: | |
3341 | OP_OPERAND_LOW8 | |
3342 | OP_OPERAND_HI24S | |
3343 | OP_OPERAND_F32MINUS */ | |
3344 | if (xg_has_userdef_op_fn (op->typ)) | |
3345 | { | |
3346 | assert (op_data < insn->ntok); | |
3347 | if (expr_is_const (&insn->tok[op_data])) | |
3348 | { | |
3349 | long val; | |
3350 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3351 | val = xg_apply_userdef_op_fn (op->typ, | |
3352 | targ->tok[op_num]. | |
3353 | X_add_number); | |
3354 | targ->tok[op_num].X_add_number = val; | |
3355 | } | |
3356 | else | |
3357 | return FALSE; /* We cannot use a relocation for this. */ | |
3358 | break; | |
3359 | } | |
3360 | assert (0); | |
3361 | break; | |
3362 | } | |
3363 | } | |
3364 | break; | |
3365 | ||
3366 | case INSTR_LITERAL_DEF: | |
3367 | op = bi->ops; | |
3368 | targ->opcode = XTENSA_UNDEFINED; | |
3369 | targ->insn_type = ITYPE_LITERAL; | |
3370 | targ->is_specific_opcode = FALSE; | |
3371 | for (; op != NULL; op = op->next) | |
3372 | { | |
3373 | int op_num = op->op_num; | |
3374 | int op_data = op->op_data; | |
3375 | assert (op->op_num < MAX_INSN_ARGS); | |
3376 | ||
3377 | if (targ->ntok <= op_num) | |
3378 | targ->ntok = op_num + 1; | |
3379 | ||
3380 | switch (op->typ) | |
3381 | { | |
3382 | case OP_OPERAND: | |
3383 | assert (op_data < insn->ntok); | |
43cd72b9 BW |
3384 | /* We can only pass resolvable literals through. */ |
3385 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3386 | return FALSE; | |
e0001a05 NC |
3387 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3388 | break; | |
3389 | case OP_LITERAL: | |
3390 | case OP_CONSTANT: | |
3391 | case OP_LABEL: | |
3392 | default: | |
3393 | assert (0); | |
3394 | break; | |
3395 | } | |
3396 | } | |
3397 | break; | |
3398 | ||
3399 | case INSTR_LABEL_DEF: | |
3400 | op = bi->ops; | |
3401 | targ->opcode = XTENSA_UNDEFINED; | |
3402 | targ->insn_type = ITYPE_LABEL; | |
3403 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3404 | /* Literal with no ops is a label? */ |
e0001a05 NC |
3405 | assert (op == NULL); |
3406 | break; | |
3407 | ||
3408 | default: | |
3409 | assert (0); | |
3410 | } | |
3411 | ||
3412 | return TRUE; | |
3413 | } | |
3414 | ||
3415 | ||
43cd72b9 | 3416 | /* Return TRUE on success. */ |
e0001a05 | 3417 | |
7fa3d080 BW |
3418 | static bfd_boolean |
3419 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3420 | { |
3421 | for (; bi != NULL; bi = bi->next) | |
3422 | { | |
3423 | TInsn *next_insn = istack_push_space (istack); | |
3424 | ||
3425 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3426 | return FALSE; | |
3427 | } | |
3428 | return TRUE; | |
3429 | } | |
3430 | ||
3431 | ||
43cd72b9 | 3432 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3433 | |
7fa3d080 BW |
3434 | static bfd_boolean |
3435 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3436 | { |
3437 | int stack_size = istack->ninsn; | |
3438 | int steps_taken = 0; | |
43cd72b9 | 3439 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3440 | TransitionList *l; |
3441 | ||
3442 | assert (insn->insn_type == ITYPE_INSN); | |
3443 | assert (insn->opcode < table->num_opcodes); | |
3444 | ||
3445 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3446 | { | |
3447 | TransitionRule *rule = l->rule; | |
3448 | ||
3449 | if (xg_instruction_matches_rule (insn, rule)) | |
3450 | { | |
3451 | if (lateral_steps == steps_taken) | |
3452 | { | |
3453 | int i; | |
3454 | ||
3455 | /* This is it. Expand the rule to the stack. */ | |
3456 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3457 | return FALSE; | |
3458 | ||
3459 | /* Check to see if it fits. */ | |
3460 | for (i = stack_size; i < istack->ninsn; i++) | |
3461 | { | |
3462 | TInsn *insn = &istack->insn[i]; | |
3463 | ||
3464 | if (insn->insn_type == ITYPE_INSN | |
3465 | && !tinsn_has_symbolic_operands (insn) | |
3466 | && !xg_immeds_fit (insn)) | |
3467 | { | |
3468 | istack->ninsn = stack_size; | |
3469 | return FALSE; | |
3470 | } | |
3471 | } | |
3472 | return TRUE; | |
3473 | } | |
3474 | steps_taken++; | |
3475 | } | |
3476 | } | |
3477 | return FALSE; | |
3478 | } | |
3479 | ||
43cd72b9 | 3480 | \f |
43cd72b9 BW |
3481 | /* Relax the assembly instruction at least "min_steps". |
3482 | Return the number of steps taken. */ | |
e0001a05 | 3483 | |
7fa3d080 BW |
3484 | static int |
3485 | xg_assembly_relax (IStack *istack, | |
3486 | TInsn *insn, | |
3487 | segT pc_seg, | |
3488 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3489 | offsetT pc_offset, /* offset in fragment */ | |
3490 | int min_steps, /* minimum conversion steps */ | |
3491 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3492 | { |
3493 | int steps_taken = 0; | |
3494 | ||
3495 | /* assert (has no symbolic operands) | |
3496 | Some of its immeds don't fit. | |
3497 | Try to build a relaxed version. | |
3498 | This may go through a couple of stages | |
3499 | of single instruction transformations before | |
3500 | we get there. */ | |
3501 | ||
3502 | TInsn single_target; | |
3503 | TInsn current_insn; | |
3504 | int lateral_steps = 0; | |
3505 | int istack_size = istack->ninsn; | |
3506 | ||
3507 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3508 | && steps_taken >= min_steps) | |
3509 | { | |
3510 | istack_push (istack, insn); | |
3511 | return steps_taken; | |
3512 | } | |
43cd72b9 | 3513 | current_insn = *insn; |
e0001a05 | 3514 | |
7c834684 | 3515 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3516 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3517 | { |
21af2bbd | 3518 | steps_taken++; |
e0001a05 NC |
3519 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3520 | stretch)) | |
3521 | { | |
e0001a05 NC |
3522 | if (steps_taken >= min_steps) |
3523 | { | |
3524 | istack_push (istack, &single_target); | |
3525 | return steps_taken; | |
3526 | } | |
3527 | } | |
43cd72b9 | 3528 | current_insn = single_target; |
e0001a05 NC |
3529 | } |
3530 | ||
3531 | /* Now check for a multi-instruction expansion. */ | |
3532 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3533 | { | |
3534 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3535 | stretch)) | |
3536 | { | |
3537 | if (steps_taken >= min_steps) | |
3538 | { | |
3539 | istack_push (istack, ¤t_insn); | |
3540 | return steps_taken; | |
3541 | } | |
3542 | } | |
3543 | steps_taken++; | |
3544 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3545 | { | |
3546 | if (steps_taken >= min_steps) | |
3547 | return steps_taken; | |
3548 | } | |
3549 | lateral_steps++; | |
3550 | istack->ninsn = istack_size; | |
3551 | } | |
3552 | ||
3553 | /* It's not going to work -- use the original. */ | |
3554 | istack_push (istack, insn); | |
3555 | return steps_taken; | |
3556 | } | |
3557 | ||
3558 | ||
3559 | static void | |
7fa3d080 | 3560 | xg_force_frag_space (int size) |
e0001a05 NC |
3561 | { |
3562 | /* This may have the side effect of creating a new fragment for the | |
3563 | space to go into. I just do not like the name of the "frag" | |
3564 | functions. */ | |
3565 | frag_grow (size); | |
3566 | } | |
3567 | ||
3568 | ||
7fa3d080 BW |
3569 | static void |
3570 | xg_finish_frag (char *last_insn, | |
3571 | enum xtensa_relax_statesE frag_state, | |
3572 | enum xtensa_relax_statesE slot0_state, | |
3573 | int max_growth, | |
3574 | bfd_boolean is_insn) | |
e0001a05 NC |
3575 | { |
3576 | /* Finish off this fragment so that it has at LEAST the desired | |
3577 | max_growth. If it doesn't fit in this fragment, close this one | |
3578 | and start a new one. In either case, return a pointer to the | |
3579 | beginning of the growth area. */ | |
3580 | ||
3581 | fragS *old_frag; | |
43cd72b9 | 3582 | |
e0001a05 NC |
3583 | xg_force_frag_space (max_growth); |
3584 | ||
3585 | old_frag = frag_now; | |
3586 | ||
3587 | frag_now->fr_opcode = last_insn; | |
3588 | if (is_insn) | |
3589 | frag_now->tc_frag_data.is_insn = TRUE; | |
3590 | ||
3591 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3592 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3593 | ||
3594 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3595 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3596 | |
3597 | /* Just to make sure that we did not split it up. */ | |
3598 | assert (old_frag->fr_next == frag_now); | |
3599 | } | |
3600 | ||
3601 | ||
7fa3d080 BW |
3602 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3603 | ||
3604 | static bfd_boolean | |
3605 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3606 | { | |
3607 | if (fragP == NULL) | |
3608 | return FALSE; | |
3609 | ||
3610 | for (; fragP; fragP = fragP->fr_next) | |
3611 | { | |
3612 | if (fragP == target) | |
3613 | return TRUE; | |
3614 | if (fragP->fr_fix != 0) | |
3615 | return FALSE; | |
3616 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3617 | return FALSE; | |
3618 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3619 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3620 | return FALSE; | |
3621 | if (fragP->fr_type == rs_space) | |
3622 | return FALSE; | |
3623 | } | |
3624 | return FALSE; | |
3625 | } | |
3626 | ||
3627 | ||
e0001a05 | 3628 | static bfd_boolean |
7fa3d080 | 3629 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3630 | { |
3631 | xtensa_isa isa = xtensa_default_isa; | |
3632 | int i; | |
43cd72b9 | 3633 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3634 | int target_op = -1; |
3635 | symbolS *sym; | |
3636 | fragS *target_frag; | |
3637 | ||
64b607e6 BW |
3638 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3639 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
e0001a05 NC |
3640 | return FALSE; |
3641 | ||
3642 | for (i = 0; i < num_ops; i++) | |
3643 | { | |
43cd72b9 | 3644 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3645 | { |
3646 | target_op = i; | |
3647 | break; | |
3648 | } | |
3649 | } | |
3650 | if (target_op == -1) | |
3651 | return FALSE; | |
3652 | ||
3653 | if (insn->ntok <= target_op) | |
3654 | return FALSE; | |
3655 | ||
3656 | if (insn->tok[target_op].X_op != O_symbol) | |
3657 | return FALSE; | |
3658 | ||
3659 | sym = insn->tok[target_op].X_add_symbol; | |
3660 | if (sym == NULL) | |
3661 | return FALSE; | |
3662 | ||
3663 | if (insn->tok[target_op].X_add_number != 0) | |
3664 | return FALSE; | |
3665 | ||
3666 | target_frag = symbol_get_frag (sym); | |
3667 | if (target_frag == NULL) | |
3668 | return FALSE; | |
3669 | ||
c138bc38 | 3670 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3671 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3672 | return TRUE; | |
3673 | ||
3674 | return FALSE; | |
3675 | } | |
3676 | ||
3677 | ||
3678 | static void | |
7fa3d080 | 3679 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3680 | { |
3681 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3682 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3683 | |
7fa3d080 BW |
3684 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3685 | { | |
3686 | int i = 1; | |
3687 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3688 | && insn->tok[i].X_op == O_symbol) | |
3689 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3690 | return; | |
3691 | } | |
e0001a05 | 3692 | |
7fa3d080 BW |
3693 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3694 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3695 | { |
7fa3d080 BW |
3696 | int i; |
3697 | ||
3698 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3699 | { | |
3700 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3701 | && insn->tok[i].X_op == O_symbol) | |
3702 | { | |
3703 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3704 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3705 | if (S_IS_DEFINED (sym)) | |
3706 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3707 | } | |
3708 | } | |
e0001a05 | 3709 | } |
e0001a05 NC |
3710 | } |
3711 | ||
3712 | ||
43cd72b9 | 3713 | /* Return FALSE if no error. */ |
e0001a05 | 3714 | |
7fa3d080 BW |
3715 | static bfd_boolean |
3716 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3717 | { |
3718 | int num_ops = 0; | |
3719 | BuildOp *b_op; | |
3720 | ||
3721 | switch (instr_spec->typ) | |
3722 | { | |
3723 | case INSTR_INSTR: | |
3724 | new_insn->insn_type = ITYPE_INSN; | |
3725 | new_insn->opcode = instr_spec->opcode; | |
3726 | new_insn->is_specific_opcode = FALSE; | |
7c430684 | 3727 | new_insn->linenum = old_insn->linenum; |
e0001a05 NC |
3728 | break; |
3729 | case INSTR_LITERAL_DEF: | |
3730 | new_insn->insn_type = ITYPE_LITERAL; | |
3731 | new_insn->opcode = XTENSA_UNDEFINED; | |
3732 | new_insn->is_specific_opcode = FALSE; | |
7c430684 | 3733 | new_insn->linenum = old_insn->linenum; |
e0001a05 NC |
3734 | break; |
3735 | case INSTR_LABEL_DEF: | |
3736 | as_bad (_("INSTR_LABEL_DEF not supported yet")); | |
3737 | break; | |
3738 | } | |
3739 | ||
3740 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3741 | { | |
3742 | expressionS *exp; | |
3743 | const expressionS *src_exp; | |
3744 | ||
3745 | num_ops++; | |
3746 | switch (b_op->typ) | |
3747 | { | |
3748 | case OP_CONSTANT: | |
3749 | /* The expression must be the constant. */ | |
3750 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3751 | exp = &new_insn->tok[b_op->op_num]; | |
3752 | set_expr_const (exp, b_op->op_data); | |
3753 | break; | |
3754 | ||
3755 | case OP_OPERAND: | |
3756 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3757 | assert (b_op->op_data < (unsigned) old_insn->ntok); | |
3758 | src_exp = &old_insn->tok[b_op->op_data]; | |
3759 | exp = &new_insn->tok[b_op->op_num]; | |
3760 | copy_expr (exp, src_exp); | |
3761 | break; | |
3762 | ||
3763 | case OP_LITERAL: | |
3764 | case OP_LABEL: | |
3765 | as_bad (_("can't handle generation of literal/labels yet")); | |
3766 | assert (0); | |
3767 | ||
3768 | default: | |
3769 | as_bad (_("can't handle undefined OP TYPE")); | |
3770 | assert (0); | |
3771 | } | |
3772 | } | |
3773 | ||
3774 | new_insn->ntok = num_ops; | |
3775 | return FALSE; | |
3776 | } | |
3777 | ||
3778 | ||
43cd72b9 | 3779 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3780 | |
7fa3d080 BW |
3781 | static bfd_boolean |
3782 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3783 | { |
43cd72b9 | 3784 | TransitionRule *rule; |
e0001a05 | 3785 | BuildInstr *insn_spec; |
43cd72b9 BW |
3786 | |
3787 | if (old_insn->is_specific_opcode || !density_supported) | |
3788 | return FALSE; | |
3789 | ||
3790 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3791 | if (rule == NULL) |
3792 | return FALSE; | |
3793 | ||
3794 | insn_spec = rule->to_instr; | |
3795 | /* There should only be one. */ | |
3796 | assert (insn_spec != NULL); | |
3797 | assert (insn_spec->next == NULL); | |
3798 | if (insn_spec->next != NULL) | |
3799 | return FALSE; | |
3800 | ||
3801 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3802 | ||
3803 | return TRUE; | |
3804 | } | |
3805 | ||
3806 | ||
3807 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3808 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
3809 | tokens into the stack or relax it and place multiple |
3810 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
3811 | |
3812 | static bfd_boolean | |
7fa3d080 | 3813 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
3814 | { |
3815 | int noperands; | |
3816 | TInsn new_insn; | |
7c834684 BW |
3817 | bfd_boolean do_expand; |
3818 | ||
e0001a05 NC |
3819 | memset (&new_insn, 0, sizeof (TInsn)); |
3820 | ||
43cd72b9 BW |
3821 | /* Narrow it if we can. xg_simplify_insn now does all the |
3822 | appropriate checking (e.g., for the density option). */ | |
3823 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
3824 | orig_insn = &new_insn; | |
e0001a05 | 3825 | |
43cd72b9 BW |
3826 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
3827 | orig_insn->opcode); | |
e0001a05 NC |
3828 | if (orig_insn->ntok < noperands) |
3829 | { | |
3830 | as_bad (_("found %d operands for '%s': Expected %d"), | |
3831 | orig_insn->ntok, | |
3832 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3833 | noperands); | |
3834 | return TRUE; | |
3835 | } | |
3836 | if (orig_insn->ntok > noperands) | |
3837 | as_warn (_("found too many (%d) operands for '%s': Expected %d"), | |
3838 | orig_insn->ntok, | |
3839 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3840 | noperands); | |
3841 | ||
43cd72b9 | 3842 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 3843 | are too many, just cut out the extras here. */ |
e0001a05 NC |
3844 | orig_insn->ntok = noperands; |
3845 | ||
e0001a05 NC |
3846 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
3847 | return TRUE; | |
3848 | ||
7c834684 BW |
3849 | /* If the instruction will definitely need to be relaxed, it is better |
3850 | to expand it now for better scheduling. Decide whether to expand | |
3851 | now.... */ | |
3852 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
3853 | ||
3854 | /* Calls should be expanded to longcalls only in the backend relaxation | |
3855 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
3856 | adjacent. */ | |
3857 | if (is_direct_call_opcode (orig_insn->opcode)) | |
3858 | do_expand = FALSE; | |
e0001a05 NC |
3859 | |
3860 | if (tinsn_has_symbolic_operands (orig_insn)) | |
3861 | { | |
7c834684 BW |
3862 | /* The values of symbolic operands are not known yet, so only expand |
3863 | now if an operand is "complex" (e.g., difference of symbols) and | |
3864 | will have to be stored as a literal regardless of the value. */ | |
3865 | if (!tinsn_has_complex_operands (orig_insn)) | |
3866 | do_expand = FALSE; | |
e0001a05 | 3867 | } |
7c834684 BW |
3868 | else if (xg_immeds_fit (orig_insn)) |
3869 | do_expand = FALSE; | |
3870 | ||
3871 | if (do_expand) | |
3872 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 3873 | else |
7c834684 | 3874 | istack_push (istack, orig_insn); |
e0001a05 | 3875 | |
e0001a05 NC |
3876 | return FALSE; |
3877 | } | |
3878 | ||
3879 | ||
7fa3d080 | 3880 | /* Return TRUE if the section flags are marked linkonce |
74869ac7 BW |
3881 | or the name is .gnu.linkonce.*. */ |
3882 | ||
3883 | static int linkonce_len = sizeof (".gnu.linkonce.") - 1; | |
7fa3d080 BW |
3884 | |
3885 | static bfd_boolean | |
3886 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
3887 | { | |
3888 | flagword flags, link_once_flags; | |
3889 | ||
3890 | flags = bfd_get_section_flags (abfd, sec); | |
3891 | link_once_flags = (flags & SEC_LINK_ONCE); | |
3892 | ||
3893 | /* Flags might not be set yet. */ | |
74869ac7 BW |
3894 | if (!link_once_flags |
3895 | && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) | |
3896 | link_once_flags = SEC_LINK_ONCE; | |
7fa3d080 | 3897 | |
7fa3d080 BW |
3898 | return (link_once_flags != 0); |
3899 | } | |
3900 | ||
3901 | ||
3902 | static void | |
3903 | xtensa_add_literal_sym (symbolS *sym) | |
3904 | { | |
3905 | sym_list *l; | |
3906 | ||
3907 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
3908 | l->sym = sym; | |
3909 | l->next = literal_syms; | |
3910 | literal_syms = l; | |
3911 | } | |
3912 | ||
3913 | ||
3914 | static symbolS * | |
3915 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
3916 | { | |
3917 | static int lit_num = 0; | |
3918 | static char name[256]; | |
3919 | symbolS *symbolP; | |
3920 | ||
3921 | sprintf (name, ".L_lit_sym%d", lit_num); | |
3922 | ||
3923 | /* Create a local symbol. If it is in a linkonce section, we have to | |
3924 | be careful to make sure that if it is used in a relocation that the | |
3925 | symbol will be in the output file. */ | |
3926 | if (get_is_linkonce_section (stdoutput, sec)) | |
3927 | { | |
3928 | symbolP = symbol_new (name, sec, 0, frag); | |
3929 | S_CLEAR_EXTERNAL (symbolP); | |
3930 | /* symbolP->local = 1; */ | |
3931 | } | |
3932 | else | |
3933 | symbolP = symbol_new (name, sec, 0, frag); | |
3934 | ||
3935 | xtensa_add_literal_sym (symbolP); | |
3936 | ||
7fa3d080 BW |
3937 | lit_num++; |
3938 | return symbolP; | |
3939 | } | |
3940 | ||
3941 | ||
e0001a05 NC |
3942 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
3943 | ||
7fa3d080 BW |
3944 | static symbolS * |
3945 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
3946 | { |
3947 | emit_state state; | |
3948 | symbolS *lit_sym = NULL; | |
3949 | ||
3950 | /* size = 4 for L32R. It could easily be larger when we move to | |
3951 | larger constants. Add a parameter later. */ | |
3952 | offsetT litsize = 4; | |
3953 | offsetT litalign = 2; /* 2^2 = 4 */ | |
3954 | expressionS saved_loc; | |
43cd72b9 BW |
3955 | expressionS * emit_val; |
3956 | ||
e0001a05 NC |
3957 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
3958 | ||
3959 | assert (insn->insn_type == ITYPE_LITERAL); | |
77cd6497 | 3960 | assert (insn->ntok == 1); /* must be only one token here */ |
e0001a05 NC |
3961 | |
3962 | xtensa_switch_to_literal_fragment (&state); | |
3963 | ||
43cd72b9 BW |
3964 | emit_val = &insn->tok[0]; |
3965 | if (emit_val->X_op == O_big) | |
3966 | { | |
3967 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
3968 | if (size > litsize) | |
3969 | { | |
3970 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 3971 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
3972 | _("invalid immediate")); |
3973 | xtensa_restore_emit_state (&state); | |
3974 | return NULL; | |
3975 | } | |
3976 | } | |
3977 | ||
e0001a05 NC |
3978 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
3979 | literals done with this function have a frag to themselves. That's | |
3980 | important for the way text section literals work. */ | |
3981 | frag_align (litalign, 0, 0); | |
43cd72b9 | 3982 | record_alignment (now_seg, litalign); |
e0001a05 | 3983 | |
43cd72b9 BW |
3984 | if (emit_val->X_op == O_pltrel) |
3985 | { | |
3986 | char *p = frag_more (litsize); | |
3987 | xtensa_set_frag_assembly_state (frag_now); | |
3988 | if (emit_val->X_add_symbol) | |
3989 | emit_val->X_op = O_symbol; | |
3990 | else | |
3991 | emit_val->X_op = O_constant; | |
3992 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
3993 | litsize, emit_val, 0, BFD_RELOC_XTENSA_PLT); | |
3994 | } | |
3995 | else | |
3996 | emit_expr (emit_val, litsize); | |
e0001a05 NC |
3997 | |
3998 | assert (frag_now->tc_frag_data.literal_frag == NULL); | |
3999 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
4000 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4001 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4002 | |
4003 | /* Go back. */ | |
4004 | xtensa_restore_emit_state (&state); | |
4005 | return lit_sym; | |
4006 | } | |
4007 | ||
4008 | ||
4009 | static void | |
7fa3d080 | 4010 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4011 | { |
4012 | emit_state state; | |
43cd72b9 | 4013 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4014 | takes effect if something is placed here. */ |
4015 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4016 | fragS *lit_saved_frag; | |
4017 | ||
e0001a05 | 4018 | assert (size % 4 == 0); |
e0001a05 NC |
4019 | |
4020 | xtensa_switch_to_literal_fragment (&state); | |
4021 | ||
4022 | /* Force a 4-byte align here. */ | |
4023 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4024 | record_alignment (now_seg, litalign); |
e0001a05 NC |
4025 | |
4026 | xg_force_frag_space (size); | |
4027 | ||
4028 | lit_saved_frag = frag_now; | |
4029 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4030 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
43cd72b9 | 4031 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4032 | |
4033 | /* Go back. */ | |
4034 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4035 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4036 | } |
4037 | ||
4038 | ||
e0001a05 | 4039 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4040 | Return TRUE on success. */ |
e0001a05 | 4041 | |
7fa3d080 BW |
4042 | static bfd_boolean |
4043 | xg_add_opcode_fix (TInsn *tinsn, | |
4044 | int opnum, | |
4045 | xtensa_format fmt, | |
4046 | int slot, | |
4047 | expressionS *expr, | |
4048 | fragS *fragP, | |
4049 | offsetT offset) | |
43cd72b9 BW |
4050 | { |
4051 | xtensa_opcode opcode = tinsn->opcode; | |
4052 | bfd_reloc_code_real_type reloc; | |
4053 | reloc_howto_type *howto; | |
4054 | int fmt_length; | |
e0001a05 NC |
4055 | fixS *the_fix; |
4056 | ||
43cd72b9 BW |
4057 | reloc = BFD_RELOC_NONE; |
4058 | ||
4059 | /* First try the special cases for "alternate" relocs. */ | |
4060 | if (opcode == xtensa_l32r_opcode) | |
4061 | { | |
4062 | if (fragP->tc_frag_data.use_absolute_literals) | |
4063 | reloc = encode_alt_reloc (slot); | |
4064 | } | |
4065 | else if (opcode == xtensa_const16_opcode) | |
4066 | { | |
4067 | if (expr->X_op == O_lo16) | |
4068 | { | |
4069 | reloc = encode_reloc (slot); | |
4070 | expr->X_op = O_symbol; | |
4071 | } | |
4072 | else if (expr->X_op == O_hi16) | |
4073 | { | |
4074 | reloc = encode_alt_reloc (slot); | |
4075 | expr->X_op = O_symbol; | |
4076 | } | |
4077 | } | |
4078 | ||
4079 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4080 | { |
43cd72b9 | 4081 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4082 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4083 | return FALSE; |
4084 | } | |
4085 | ||
43cd72b9 BW |
4086 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4087 | into the symbol table where the generic portions of the assembler | |
4088 | won't know what to do with them. */ | |
4089 | if (expr->X_op == O_lo16 || expr->X_op == O_hi16) | |
4090 | { | |
4091 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4092 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4093 | return FALSE; |
4094 | } | |
4095 | ||
4096 | /* Next try the generic relocs. */ | |
4097 | if (reloc == BFD_RELOC_NONE) | |
4098 | reloc = encode_reloc (slot); | |
4099 | if (reloc == BFD_RELOC_NONE) | |
4100 | { | |
4101 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4102 | return FALSE; | |
4103 | } | |
e0001a05 | 4104 | |
43cd72b9 | 4105 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4106 | if (!howto) |
4107 | { | |
43cd72b9 | 4108 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4109 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4110 | return FALSE; | |
4111 | } | |
4112 | ||
43cd72b9 BW |
4113 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
4114 | the_fix = fix_new_exp (fragP, offset, fmt_length, expr, | |
e0001a05 | 4115 | howto->pc_relative, reloc); |
d9740523 | 4116 | the_fix->fx_no_overflow = 1; |
e0001a05 | 4117 | |
7fa3d080 BW |
4118 | if (expr->X_add_symbol |
4119 | && (S_IS_EXTERNAL (expr->X_add_symbol) | |
4120 | || S_IS_WEAK (expr->X_add_symbol))) | |
20ee54e8 | 4121 | the_fix->fx_tcbit = TRUE; |
7fa3d080 BW |
4122 | |
4123 | the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol; | |
4124 | the_fix->tc_fix_data.X_add_number = expr->X_add_number; | |
4125 | the_fix->tc_fix_data.slot = slot; | |
c138bc38 | 4126 | |
7fa3d080 BW |
4127 | return TRUE; |
4128 | } | |
4129 | ||
4130 | ||
4131 | static bfd_boolean | |
4132 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4133 | char *buf, |
4134 | fragS *fragP, | |
4135 | offsetT offset, | |
4136 | bfd_boolean build_fix) | |
4137 | { | |
4138 | static xtensa_insnbuf insnbuf = NULL; | |
4139 | bfd_boolean has_symbolic_immed = FALSE; | |
4140 | bfd_boolean ok = TRUE; | |
b2d179be | 4141 | |
7fa3d080 BW |
4142 | if (!insnbuf) |
4143 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4144 | ||
4145 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4146 | if (has_symbolic_immed && build_fix) | |
4147 | { | |
4148 | /* Add a fixup. */ | |
b2d179be BW |
4149 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4150 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4151 | int opnum = get_relaxable_immed (tinsn->opcode); |
4152 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4153 | |
b2d179be | 4154 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4155 | ok = FALSE; |
4156 | } | |
4157 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4158 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4159 | (unsigned char *) buf, 0); | |
7fa3d080 | 4160 | return ok; |
e0001a05 NC |
4161 | } |
4162 | ||
4163 | ||
7fa3d080 BW |
4164 | static void |
4165 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4166 | { |
4167 | symbolS *sym = get_special_literal_symbol (); | |
4168 | int i; | |
4169 | if (lit_sym == 0) | |
4170 | return; | |
4171 | assert (insn->insn_type == ITYPE_INSN); | |
4172 | for (i = 0; i < insn->ntok; i++) | |
4173 | if (insn->tok[i].X_add_symbol == sym) | |
4174 | insn->tok[i].X_add_symbol = lit_sym; | |
4175 | ||
4176 | } | |
4177 | ||
4178 | ||
7fa3d080 BW |
4179 | static void |
4180 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4181 | { |
4182 | symbolS *sym = get_special_label_symbol (); | |
4183 | int i; | |
e0001a05 NC |
4184 | for (i = 0; i < insn->ntok; i++) |
4185 | if (insn->tok[i].X_add_symbol == sym) | |
4186 | insn->tok[i].X_add_symbol = label_sym; | |
4187 | ||
4188 | } | |
4189 | ||
4190 | ||
43cd72b9 | 4191 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4192 | integer register. */ |
4193 | ||
4194 | static bfd_boolean | |
7fa3d080 | 4195 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4196 | { |
4197 | int i; | |
4198 | int num_ops; | |
4199 | xtensa_isa isa = xtensa_default_isa; | |
4200 | ||
43cd72b9 | 4201 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4202 | |
4203 | for (i = 0; i < num_ops; i++) | |
4204 | { | |
43cd72b9 BW |
4205 | char inout; |
4206 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4207 | if ((inout == 'o' || inout == 'm') | |
4208 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4209 | { |
43cd72b9 BW |
4210 | xtensa_regfile opnd_rf = |
4211 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4212 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4213 | { |
4214 | if ((insn->tok[i].X_op == O_register) | |
4215 | && (insn->tok[i].X_add_number == regnum)) | |
4216 | return TRUE; | |
4217 | } | |
4218 | } | |
4219 | } | |
4220 | return FALSE; | |
4221 | } | |
4222 | ||
4223 | ||
4224 | static bfd_boolean | |
7fa3d080 | 4225 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4226 | { |
4227 | xtensa_opcode opcode = tinsn->opcode; | |
4228 | ||
4229 | if (opcode == XTENSA_UNDEFINED) | |
4230 | return FALSE; | |
4231 | ||
4232 | if (opcode == xtensa_call0_opcode | |
4233 | || opcode == xtensa_callx0_opcode | |
4234 | || opcode == xtensa_call4_opcode | |
4235 | || opcode == xtensa_callx4_opcode | |
4236 | || opcode == xtensa_call8_opcode | |
4237 | || opcode == xtensa_callx8_opcode | |
4238 | || opcode == xtensa_call12_opcode | |
4239 | || opcode == xtensa_callx12_opcode | |
4240 | || opcode == xtensa_isync_opcode | |
4241 | || opcode == xtensa_ret_opcode | |
4242 | || opcode == xtensa_ret_n_opcode | |
4243 | || opcode == xtensa_retw_opcode | |
4244 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4245 | || opcode == xtensa_waiti_opcode |
4246 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4247 | return TRUE; |
c138bc38 | 4248 | |
e0001a05 NC |
4249 | return FALSE; |
4250 | } | |
4251 | ||
4252 | ||
4253 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4254 | This allows the debugger to add unaligned labels. | |
4255 | Also, the assembler generates stabs labels that need | |
4256 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4257 | ||
7fa3d080 BW |
4258 | static bfd_boolean |
4259 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4260 | { |
4261 | const char *name = S_GET_NAME (sym); | |
4262 | static size_t fake_size = 0; | |
4263 | ||
4264 | if (name | |
4265 | && name[0] == '.' | |
4266 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4267 | return TRUE; | |
4268 | ||
4269 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4270 | if (fake_size == 0) | |
4271 | fake_size = strlen (FAKE_LABEL_NAME); | |
4272 | ||
43cd72b9 | 4273 | if (name |
e0001a05 NC |
4274 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4275 | && (name[fake_size] == 'F' | |
4276 | || name[fake_size] == 'L' | |
4277 | || (name[fake_size] == 'e' | |
4278 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4279 | return TRUE; | |
4280 | ||
4281 | return FALSE; | |
4282 | } | |
4283 | ||
4284 | ||
7fa3d080 BW |
4285 | static fragS * |
4286 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4287 | { |
4288 | fragS *next_fragP = fragP->fr_next; | |
4289 | ||
c138bc38 | 4290 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4291 | So we have to skip until we find something legit. */ |
4292 | while (next_fragP && next_fragP->fr_fix == 0) | |
4293 | next_fragP = next_fragP->fr_next; | |
4294 | ||
4295 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4296 | return NULL; | |
4297 | ||
4298 | return next_fragP; | |
4299 | } | |
4300 | ||
4301 | ||
43cd72b9 | 4302 | static bfd_boolean |
7fa3d080 | 4303 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4304 | { |
4305 | xtensa_opcode out_opcode; | |
4306 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4307 | ||
4308 | if (next_fragP == NULL) | |
4309 | return FALSE; | |
4310 | ||
4311 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4312 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4313 | { | |
4314 | *opcode = out_opcode; | |
4315 | return TRUE; | |
4316 | } | |
4317 | return FALSE; | |
4318 | } | |
4319 | ||
4320 | ||
4321 | static int | |
7fa3d080 | 4322 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4323 | { |
e0001a05 NC |
4324 | static xtensa_insnbuf insnbuf = NULL; |
4325 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4326 | xtensa_format fmt; |
c138bc38 | 4327 | int fmt_size; |
e0001a05 NC |
4328 | |
4329 | if (!insnbuf) | |
4330 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4331 | ||
43cd72b9 BW |
4332 | if (fragP == NULL) |
4333 | return XTENSA_UNDEFINED; | |
4334 | ||
d77b99c9 BW |
4335 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4336 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4337 | |
4338 | fmt = xtensa_format_decode (isa, insnbuf); | |
4339 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4340 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4341 | fmt_size = xtensa_format_length (isa, fmt); |
4342 | ||
4343 | /* If the next format won't be changing due to relaxation, just | |
4344 | return the length of the first format. */ | |
4345 | if (fragP->fr_opcode != fragP->fr_literal) | |
4346 | return fmt_size; | |
4347 | ||
c138bc38 | 4348 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4349 | multi-slot instruction, we will return the more conservative |
4350 | number. This works because alignment on bigger instructions | |
4351 | is more restrictive than alignment on smaller instructions. | |
4352 | This is more conservative than we would like, but it happens | |
4353 | infrequently. */ | |
4354 | ||
4355 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4356 | return fmt_size; | |
4357 | ||
4358 | /* If we aren't doing one of our own relaxations or it isn't | |
4359 | slot-based, then the insn size won't change. */ | |
4360 | if (fragP->fr_type != rs_machine_dependent) | |
4361 | return fmt_size; | |
4362 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4363 | return fmt_size; | |
4364 | ||
4365 | /* If an instruction is about to grow, return the longer size. */ | |
4366 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
4367 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2) | |
4368 | return 3; | |
c138bc38 | 4369 | |
43cd72b9 BW |
4370 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4371 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4372 | |
43cd72b9 | 4373 | return fmt_size; |
e0001a05 NC |
4374 | } |
4375 | ||
4376 | ||
7fa3d080 BW |
4377 | static int |
4378 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4379 | { |
7fa3d080 BW |
4380 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4381 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4382 | } |
4383 | ||
4384 | ||
03aaa593 BW |
4385 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4386 | required two-byte instructions to be treated as three-byte instructions | |
4387 | for loop instruction alignment. This restriction was removed beginning | |
4388 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4389 | is that the first instruction of the loop must appear at an address that | |
4390 | does not cross a fetch boundary. */ | |
4391 | ||
4392 | static int | |
4393 | get_loop_align_size (int insn_size) | |
4394 | { | |
4395 | if (insn_size == XTENSA_UNDEFINED) | |
4396 | return xtensa_fetch_width; | |
4397 | ||
4398 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4399 | return 3; | |
4400 | ||
4401 | return insn_size; | |
4402 | } | |
4403 | ||
4404 | ||
e0001a05 NC |
4405 | /* If the next legit fragment is an end-of-loop marker, |
4406 | switch its state so it will instantiate a NOP. */ | |
4407 | ||
4408 | static void | |
1d19a770 | 4409 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4410 | { |
4411 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4412 | fragS *new_target = NULL; |
e0001a05 | 4413 | |
7b1cc377 | 4414 | if (align_targets) |
43cd72b9 BW |
4415 | { |
4416 | /* We are guaranteed there will be one of these... */ | |
4417 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4418 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4419 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4420 | next_fragP = next_fragP->fr_next; | |
4421 | ||
4422 | assert (next_fragP->fr_type == rs_machine_dependent | |
4423 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4424 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4425 | ||
4426 | /* ...and one of these. */ | |
4427 | new_target = next_fragP->fr_next; | |
4428 | while (!(new_target->fr_type == rs_machine_dependent | |
4429 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4430 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4431 | new_target = new_target->fr_next; | |
4432 | ||
4433 | assert (new_target->fr_type == rs_machine_dependent | |
4434 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4435 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4436 | } | |
43cd72b9 | 4437 | |
1d19a770 | 4438 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4439 | { |
1d19a770 BW |
4440 | if (next_fragP->fr_type == rs_machine_dependent |
4441 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4442 | { |
1d19a770 BW |
4443 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4444 | return; | |
e0001a05 | 4445 | } |
1d19a770 BW |
4446 | |
4447 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4448 | } |
4449 | } | |
4450 | ||
4451 | ||
4452 | static bfd_boolean | |
7fa3d080 | 4453 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4454 | { |
43cd72b9 | 4455 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4456 | so we have to skip until we find something legit. */ |
4457 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4458 | { | |
4459 | if (fragP->tc_frag_data.is_branch_target) | |
4460 | return TRUE; | |
4461 | if (fragP->fr_fix != 0) | |
4462 | break; | |
4463 | } | |
4464 | return FALSE; | |
4465 | } | |
4466 | ||
4467 | ||
4468 | static bfd_boolean | |
7fa3d080 | 4469 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4470 | { |
c138bc38 | 4471 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4472 | So we have to skip until we find something legit. */ |
4473 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4474 | { | |
4475 | if (fragP->tc_frag_data.is_loop_target) | |
4476 | return TRUE; | |
4477 | if (fragP->fr_fix != 0) | |
4478 | break; | |
4479 | } | |
4480 | return FALSE; | |
4481 | } | |
4482 | ||
4483 | ||
4484 | static addressT | |
7fa3d080 | 4485 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4486 | { |
4487 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4488 | xtensa_opcode next_opcode; |
e0001a05 | 4489 | |
43cd72b9 | 4490 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4491 | return 0; |
4492 | ||
43cd72b9 BW |
4493 | /* Sometimes an empty will end up here due to storage allocation issues, |
4494 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4495 | while (next_fragp->fr_fix == 0) |
4496 | next_fragp = next_fragp->fr_next; | |
4497 | ||
4498 | if (next_fragp->fr_type != rs_machine_dependent) | |
4499 | return 0; | |
4500 | ||
4501 | /* There is some implicit knowledge encoded in here. | |
4502 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4503 | been relaxed. Note that we can assume that the LOOP |
4504 | instruction is in slot 0 because loops aren't bundleable. */ | |
4505 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
e0001a05 NC |
4506 | return get_expanded_loop_offset (next_opcode); |
4507 | ||
4508 | return 0; | |
4509 | } | |
4510 | ||
4511 | ||
4512 | /* Mark a location where we can later insert literal frags. Update | |
4513 | the section's literal_pool_loc, so subsequent literals can be | |
4514 | placed nearest to their use. */ | |
4515 | ||
4516 | static void | |
7fa3d080 | 4517 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4518 | { |
4519 | /* Any labels pointing to the current location need | |
4520 | to be adjusted to after the literal pool. */ | |
4521 | emit_state s; | |
e0001a05 | 4522 | fragS *pool_location; |
e0001a05 | 4523 | |
1f2a7e38 | 4524 | if (use_literal_section) |
43cd72b9 BW |
4525 | return; |
4526 | ||
dd49a749 BW |
4527 | /* We stash info in these frags so we can later move the literal's |
4528 | fixes into this frchain's fix list. */ | |
e0001a05 | 4529 | pool_location = frag_now; |
dd49a749 BW |
4530 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
4531 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4532 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4533 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4534 | frag_now->tc_frag_data.lit_seg = now_seg; |
4535 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4536 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4537 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4538 | |
4539 | /* Now put a frag into the literal pool that points to this location. */ | |
4540 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4541 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4542 | frag_align (2, 0, 0); | |
4543 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4544 | |
4545 | /* Close whatever frag is there. */ | |
4546 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4547 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4548 | frag_now->tc_frag_data.literal_frag = pool_location; |
4549 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4550 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4551 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4552 | } |
4553 | ||
4554 | ||
43cd72b9 BW |
4555 | /* Build a nop of the correct size into tinsn. */ |
4556 | ||
4557 | static void | |
7fa3d080 | 4558 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4559 | { |
4560 | tinsn_init (tinsn); | |
4561 | switch (size) | |
4562 | { | |
4563 | case 2: | |
4564 | tinsn->opcode = xtensa_nop_n_opcode; | |
4565 | tinsn->ntok = 0; | |
4566 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4567 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4568 | break; | |
4569 | ||
4570 | case 3: | |
4571 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4572 | { | |
4573 | tinsn->opcode = xtensa_or_opcode; | |
4574 | set_expr_const (&tinsn->tok[0], 1); | |
4575 | set_expr_const (&tinsn->tok[1], 1); | |
4576 | set_expr_const (&tinsn->tok[2], 1); | |
4577 | tinsn->ntok = 3; | |
4578 | } | |
4579 | else | |
4580 | tinsn->opcode = xtensa_nop_opcode; | |
4581 | ||
4582 | assert (tinsn->opcode != XTENSA_UNDEFINED); | |
4583 | } | |
4584 | } | |
4585 | ||
4586 | ||
e0001a05 NC |
4587 | /* Assemble a NOP of the requested size in the buffer. User must have |
4588 | allocated "buf" with at least "size" bytes. */ | |
4589 | ||
7fa3d080 | 4590 | static void |
d77b99c9 | 4591 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4592 | { |
4593 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4594 | TInsn tinsn; |
e0001a05 | 4595 | |
43cd72b9 | 4596 | build_nop (&tinsn, size); |
e0001a05 | 4597 | |
43cd72b9 BW |
4598 | if (!insnbuf) |
4599 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4600 | |
43cd72b9 | 4601 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4602 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4603 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4604 | } |
4605 | ||
4606 | ||
4607 | /* Return the number of bytes for the offset of the expanded loop | |
4608 | instruction. This should be incorporated into the relaxation | |
4609 | specification but is hard-coded here. This is used to auto-align | |
4610 | the loop instruction. It is invalid to call this function if the | |
4611 | configuration does not have loops or if the opcode is not a loop | |
4612 | opcode. */ | |
4613 | ||
4614 | static addressT | |
7fa3d080 | 4615 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4616 | { |
4617 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4618 | This MUST correspond directly to the specification of the loop | |
4619 | expansion. It will be validated on fragment conversion. */ | |
43cd72b9 | 4620 | assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4621 | if (opcode == xtensa_loop_opcode) |
4622 | return 0; | |
4623 | if (opcode == xtensa_loopnez_opcode) | |
4624 | return 3; | |
4625 | if (opcode == xtensa_loopgtz_opcode) | |
4626 | return 6; | |
4627 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4628 | return 0; | |
4629 | } | |
4630 | ||
4631 | ||
7fa3d080 BW |
4632 | static fragS * |
4633 | get_literal_pool_location (segT seg) | |
e0001a05 NC |
4634 | { |
4635 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; | |
4636 | } | |
4637 | ||
4638 | ||
4639 | static void | |
7fa3d080 | 4640 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4641 | { |
4642 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4643 | } | |
4644 | ||
43cd72b9 BW |
4645 | |
4646 | /* Set frag assembly state should be called when a new frag is | |
4647 | opened and after a frag has been closed. */ | |
4648 | ||
7fa3d080 BW |
4649 | static void |
4650 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4651 | { |
4652 | if (!density_supported) | |
4653 | fragP->tc_frag_data.is_no_density = TRUE; | |
4654 | ||
4655 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4656 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4657 | "use_schedule" here. */ |
4658 | if (!directive_state[directive_transform]) | |
4659 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4660 | if (directive_state[directive_longcalls]) |
4661 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4662 | fragP->tc_frag_data.use_absolute_literals = |
4663 | directive_state[directive_absolute_literals]; | |
4664 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4665 | } | |
4666 | ||
4667 | ||
7fa3d080 BW |
4668 | static bfd_boolean |
4669 | relaxable_section (asection *sec) | |
43cd72b9 BW |
4670 | { |
4671 | return (sec->flags & SEC_DEBUGGING) == 0; | |
4672 | } | |
4673 | ||
4674 | ||
4675 | static void | |
7fa3d080 | 4676 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
4677 | { |
4678 | segT *seclist; | |
4679 | ||
4680 | /* Walk over each fragment of all of the current segments. For each | |
4681 | unmarked fragment, mark it with the same info as the previous | |
4682 | fragment. */ | |
4683 | for (seclist = &stdoutput->sections; | |
4684 | seclist && *seclist; | |
4685 | seclist = &(*seclist)->next) | |
4686 | { | |
4687 | segT sec = *seclist; | |
4688 | segment_info_type *seginfo; | |
4689 | fragS *fragP; | |
4690 | flagword flags; | |
4691 | flags = bfd_get_section_flags (stdoutput, sec); | |
4692 | if (flags & SEC_DEBUGGING) | |
4693 | continue; | |
4694 | if (!(flags & SEC_ALLOC)) | |
4695 | continue; | |
4696 | ||
4697 | seginfo = seg_info (sec); | |
4698 | if (seginfo && seginfo->frchainP) | |
4699 | { | |
4700 | fragS *last_fragP = 0; | |
4701 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4702 | fragP = fragP->fr_next) | |
4703 | { | |
4704 | if (fragP->fr_fix != 0 | |
4705 | && !fragP->tc_frag_data.is_assembly_state_set) | |
4706 | { | |
4707 | if (last_fragP == 0) | |
4708 | { | |
4709 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
4710 | _("assembly state not set for first frag in section %s"), | |
4711 | sec->name); | |
4712 | } | |
4713 | else | |
4714 | { | |
4715 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4716 | fragP->tc_frag_data.is_no_density = | |
4717 | last_fragP->tc_frag_data.is_no_density; | |
4718 | fragP->tc_frag_data.is_no_transform = | |
4719 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
4720 | fragP->tc_frag_data.use_longcalls = |
4721 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
4722 | fragP->tc_frag_data.use_absolute_literals = |
4723 | last_fragP->tc_frag_data.use_absolute_literals; | |
4724 | } | |
4725 | } | |
4726 | if (fragP->tc_frag_data.is_assembly_state_set) | |
4727 | last_fragP = fragP; | |
4728 | } | |
4729 | } | |
4730 | } | |
4731 | } | |
4732 | ||
4733 | ||
4734 | static void | |
7fa3d080 BW |
4735 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
4736 | asection *sec, | |
4737 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4738 | { |
4739 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4740 | segment_info_type *seginfo = seg_info (sec); | |
4741 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 4742 | |
43cd72b9 | 4743 | if (flags & SEC_CODE) |
c138bc38 | 4744 | { |
43cd72b9 BW |
4745 | xtensa_isa isa = xtensa_default_isa; |
4746 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
4747 | while (frag != NULL) | |
4748 | { | |
4749 | if (frag->tc_frag_data.is_branch_target) | |
4750 | { | |
4751 | int op_size; | |
664df4e4 | 4752 | addressT branch_align, frag_addr; |
43cd72b9 BW |
4753 | xtensa_format fmt; |
4754 | ||
d77b99c9 BW |
4755 | xtensa_insnbuf_from_chars |
4756 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4757 | fmt = xtensa_format_decode (isa, insnbuf); |
4758 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
4759 | branch_align = 1 << branch_align_power (sec); |
4760 | frag_addr = frag->fr_address % branch_align; | |
4761 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
4762 | as_warn_where (frag->fr_file, frag->fr_line, |
4763 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 4764 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4765 | } |
4766 | frag = frag->fr_next; | |
4767 | } | |
4768 | xtensa_insnbuf_free (isa, insnbuf); | |
4769 | } | |
4770 | } | |
4771 | ||
4772 | ||
4773 | static void | |
7fa3d080 BW |
4774 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
4775 | asection *sec, | |
4776 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4777 | { |
4778 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4779 | segment_info_type *seginfo = seg_info (sec); | |
4780 | fragS *frag = seginfo->frchainP->frch_root; | |
4781 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 4782 | |
43cd72b9 | 4783 | if (flags & SEC_CODE) |
c138bc38 | 4784 | { |
43cd72b9 BW |
4785 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
4786 | while (frag != NULL) | |
4787 | { | |
4788 | if (frag->tc_frag_data.is_first_loop_insn) | |
4789 | { | |
4790 | int op_size; | |
d77b99c9 | 4791 | addressT frag_addr; |
43cd72b9 BW |
4792 | xtensa_format fmt; |
4793 | ||
d77b99c9 BW |
4794 | xtensa_insnbuf_from_chars |
4795 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4796 | fmt = xtensa_format_decode (isa, insnbuf); |
4797 | op_size = xtensa_format_length (isa, fmt); | |
4798 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
4799 | ||
d77b99c9 | 4800 | if (frag_addr + op_size > xtensa_fetch_width) |
43cd72b9 BW |
4801 | as_warn_where (frag->fr_file, frag->fr_line, |
4802 | _("unaligned loop: %d bytes at 0x%lx"), | |
dd49a749 | 4803 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4804 | } |
4805 | frag = frag->fr_next; | |
4806 | } | |
4807 | xtensa_insnbuf_free (isa, insnbuf); | |
4808 | } | |
4809 | } | |
4810 | ||
4811 | ||
30f725a1 BW |
4812 | static int |
4813 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
4814 | { |
4815 | xtensa_isa isa = xtensa_default_isa; | |
4816 | static xtensa_insnbuf insnbuf = NULL; | |
4817 | static xtensa_insnbuf slotbuf = NULL; | |
4818 | xtensa_format fmt; | |
4819 | int slot; | |
4820 | bfd_boolean alt_reloc; | |
4821 | xtensa_opcode opcode; | |
4822 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
4823 | ||
4824 | (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc); | |
4825 | if (alt_reloc) | |
4826 | as_fatal (_("unexpected fix")); | |
4827 | ||
4828 | if (!insnbuf) | |
4829 | { | |
4830 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4831 | slotbuf = xtensa_insnbuf_alloc (isa); | |
4832 | } | |
4833 | ||
d77b99c9 | 4834 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
4835 | fmt = xtensa_format_decode (isa, insnbuf); |
4836 | if (fmt == XTENSA_UNDEFINED) | |
4837 | as_fatal (_("undecodable fix")); | |
4838 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
4839 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
4840 | if (opcode == XTENSA_UNDEFINED) | |
4841 | as_fatal (_("undecodable fix")); | |
4842 | ||
4843 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
4844 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 4845 | of a CONST16 operand. */ |
43cd72b9 | 4846 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 4847 | return 0; |
43cd72b9 BW |
4848 | |
4849 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
4850 | get_relaxable_immed (opcode), val, | |
4851 | fixP->fx_file, fixP->fx_line); | |
4852 | ||
4853 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 4854 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
4855 | |
4856 | return 1; | |
43cd72b9 BW |
4857 | } |
4858 | ||
e0001a05 NC |
4859 | \f |
4860 | /* External Functions and Other GAS Hooks. */ | |
4861 | ||
4862 | const char * | |
7fa3d080 | 4863 | xtensa_target_format (void) |
e0001a05 NC |
4864 | { |
4865 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
4866 | } | |
4867 | ||
4868 | ||
4869 | void | |
7fa3d080 | 4870 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
4871 | { |
4872 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
4873 | } | |
4874 | ||
4875 | ||
4876 | void | |
7fa3d080 | 4877 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
4878 | { |
4879 | if (target_big_endian) | |
4880 | number_to_chars_bigendian (buf, val, n); | |
4881 | else | |
4882 | number_to_chars_littleendian (buf, val, n); | |
4883 | } | |
4884 | ||
4885 | ||
4886 | /* This function is called once, at assembler startup time. It should | |
4887 | set up all the tables, etc. that the MD part of the assembler will | |
4888 | need. */ | |
4889 | ||
4890 | void | |
7fa3d080 | 4891 | md_begin (void) |
e0001a05 NC |
4892 | { |
4893 | segT current_section = now_seg; | |
4894 | int current_subsec = now_subseg; | |
4895 | xtensa_isa isa; | |
4896 | ||
43cd72b9 | 4897 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 4898 | isa = xtensa_default_isa; |
e0001a05 | 4899 | |
43cd72b9 BW |
4900 | linkrelax = 1; |
4901 | ||
74869ac7 | 4902 | /* Set up the literal sections. */ |
e0001a05 | 4903 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
e0001a05 NC |
4904 | |
4905 | subseg_set (current_section, current_subsec); | |
4906 | ||
43cd72b9 BW |
4907 | xg_init_vinsn (&cur_vinsn); |
4908 | ||
e0001a05 NC |
4909 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); |
4910 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
4911 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
4912 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
4913 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
4914 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
4915 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
4916 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
4917 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
4918 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 4919 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 4920 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
43cd72b9 BW |
4921 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
4922 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 4923 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
e0001a05 | 4924 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 4925 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
4926 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
4927 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
4928 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 4929 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
4930 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
4931 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
4932 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
4933 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
4934 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
4935 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 4936 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 4937 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 BW |
4938 | |
4939 | init_op_placement_info_table (); | |
4940 | ||
4941 | /* Set up the assembly state. */ | |
4942 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
4943 | xtensa_set_frag_assembly_state (frag_now); | |
4944 | } | |
4945 | ||
4946 | ||
4947 | /* TC_INIT_FIX_DATA hook */ | |
4948 | ||
4949 | void | |
7fa3d080 | 4950 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
4951 | { |
4952 | x->tc_fix_data.slot = 0; | |
4953 | x->tc_fix_data.X_add_symbol = NULL; | |
4954 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
4955 | } |
4956 | ||
4957 | ||
4958 | /* tc_frob_label hook */ | |
4959 | ||
4960 | void | |
7fa3d080 | 4961 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 4962 | { |
3ea38ac2 BW |
4963 | float freq; |
4964 | ||
4965 | if (cur_vinsn.inside_bundle) | |
4966 | { | |
4967 | as_bad (_("labels are not valid inside bundles")); | |
4968 | return; | |
4969 | } | |
4970 | ||
4971 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 4972 | |
43cd72b9 BW |
4973 | /* Since the label was already attached to a frag associated with the |
4974 | previous basic block, it now needs to be reset to the current frag. */ | |
4975 | symbol_set_frag (sym, frag_now); | |
4976 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
4977 | ||
82e7541d BW |
4978 | if (generating_literals) |
4979 | xtensa_add_literal_sym (sym); | |
4980 | else | |
4981 | xtensa_add_insn_label (sym); | |
4982 | ||
7b1cc377 BW |
4983 | if (symbol_get_tc (sym)->is_loop_target) |
4984 | { | |
4985 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 4986 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
4987 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
4988 | ||
4989 | xtensa_set_frag_assembly_state (frag_now); | |
4990 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
4991 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
4992 | ||
4993 | xtensa_set_frag_assembly_state (frag_now); | |
4994 | xtensa_move_labels (frag_now, 0, TRUE); | |
07a53e5c | 4995 | } |
e0001a05 NC |
4996 | |
4997 | /* No target aligning in the absolute section. */ | |
61846f28 | 4998 | if (now_seg != absolute_section |
43cd72b9 | 4999 | && do_align_targets () |
61846f28 | 5000 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5001 | && !generating_literals) |
5002 | { | |
43cd72b9 BW |
5003 | xtensa_set_frag_assembly_state (frag_now); |
5004 | ||
43cd72b9 | 5005 | frag_var (rs_machine_dependent, |
7b1cc377 | 5006 | 0, (int) freq, |
e0001a05 NC |
5007 | RELAX_DESIRE_ALIGN_IF_TARGET, |
5008 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5009 | xtensa_set_frag_assembly_state (frag_now); |
82e7541d | 5010 | xtensa_move_labels (frag_now, 0, TRUE); |
43cd72b9 BW |
5011 | } |
5012 | ||
5013 | /* We need to mark the following properties even if we aren't aligning. */ | |
5014 | ||
5015 | /* If the label is already known to be a branch target, i.e., a | |
5016 | forward branch, mark the frag accordingly. Backward branches | |
5017 | are handled by xg_add_branch_and_loop_targets. */ | |
5018 | if (symbol_get_tc (sym)->is_branch_target) | |
5019 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5020 | ||
5021 | /* Loops only go forward, so they can be identified here. */ | |
5022 | if (symbol_get_tc (sym)->is_loop_target) | |
5023 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5024 | |
5025 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5026 | } |
5027 | ||
5028 | ||
5029 | /* tc_unrecognized_line hook */ | |
5030 | ||
5031 | int | |
7fa3d080 | 5032 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5033 | { |
5034 | switch (ch) | |
5035 | { | |
5036 | case '{' : | |
5037 | if (cur_vinsn.inside_bundle == 0) | |
5038 | { | |
5039 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5040 | when using --gstabs. Temporarily disable debug info. */ | |
5041 | generate_lineno_debug (); | |
5042 | if (debug_type == DEBUG_STABS) | |
5043 | { | |
5044 | xt_saved_debug_type = debug_type; | |
5045 | debug_type = DEBUG_NONE; | |
5046 | } | |
82e7541d | 5047 | |
43cd72b9 BW |
5048 | cur_vinsn.inside_bundle = 1; |
5049 | } | |
5050 | else | |
5051 | { | |
5052 | as_bad (_("extra opening brace")); | |
5053 | return 0; | |
5054 | } | |
5055 | break; | |
82e7541d | 5056 | |
43cd72b9 BW |
5057 | case '}' : |
5058 | if (cur_vinsn.inside_bundle) | |
5059 | finish_vinsn (&cur_vinsn); | |
5060 | else | |
5061 | { | |
5062 | as_bad (_("extra closing brace")); | |
5063 | return 0; | |
5064 | } | |
5065 | break; | |
5066 | default: | |
5067 | as_bad (_("syntax error")); | |
5068 | return 0; | |
e0001a05 | 5069 | } |
43cd72b9 | 5070 | return 1; |
e0001a05 NC |
5071 | } |
5072 | ||
5073 | ||
5074 | /* md_flush_pending_output hook */ | |
5075 | ||
5076 | void | |
7fa3d080 | 5077 | xtensa_flush_pending_output (void) |
e0001a05 | 5078 | { |
43cd72b9 BW |
5079 | if (cur_vinsn.inside_bundle) |
5080 | as_bad (_("missing closing brace")); | |
5081 | ||
e0001a05 NC |
5082 | /* If there is a non-zero instruction fragment, close it. */ |
5083 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5084 | { | |
5085 | frag_wane (frag_now); | |
5086 | frag_new (0); | |
43cd72b9 | 5087 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5088 | } |
5089 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5090 | |
5091 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5092 | } |
5093 | ||
5094 | ||
43cd72b9 BW |
5095 | /* We had an error while parsing an instruction. The string might look |
5096 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5097 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5098 | and the num_slots field will grow past the end of the array of slots, | |
5099 | and bad things happen. */ | |
5100 | ||
5101 | static void | |
7fa3d080 | 5102 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5103 | { |
5104 | if (cur_vinsn.inside_bundle) | |
5105 | { | |
5106 | if (*input_line_pointer == '}' | |
5107 | || *(input_line_pointer - 1) == '}' | |
5108 | || *(input_line_pointer - 2) == '}') | |
5109 | xg_clear_vinsn (&cur_vinsn); | |
5110 | } | |
5111 | } | |
5112 | ||
5113 | ||
e0001a05 | 5114 | void |
7fa3d080 | 5115 | md_assemble (char *str) |
e0001a05 NC |
5116 | { |
5117 | xtensa_isa isa = xtensa_default_isa; | |
7c430684 | 5118 | char *opname, *file_name; |
e0001a05 NC |
5119 | unsigned opnamelen; |
5120 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5121 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5122 | int num_args; |
e0001a05 | 5123 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5124 | |
e0001a05 NC |
5125 | tinsn_init (&orig_insn); |
5126 | ||
5127 | /* Split off the opcode. */ | |
5128 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
5129 | opname = xmalloc (opnamelen + 1); | |
5130 | memcpy (opname, str, opnamelen); | |
5131 | opname[opnamelen] = '\0'; | |
5132 | ||
5133 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5134 | if (num_args == -1) | |
5135 | { | |
5136 | as_bad (_("syntax error")); | |
5137 | return; | |
5138 | } | |
5139 | ||
5140 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5141 | return; | |
5142 | ||
5143 | /* Check for an underbar prefix. */ | |
5144 | if (*opname == '_') | |
5145 | { | |
5146 | has_underbar = TRUE; | |
5147 | opname += 1; | |
5148 | } | |
5149 | ||
5150 | orig_insn.insn_type = ITYPE_INSN; | |
5151 | orig_insn.ntok = 0; | |
43cd72b9 | 5152 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 NC |
5153 | |
5154 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); | |
5155 | if (orig_insn.opcode == XTENSA_UNDEFINED) | |
5156 | { | |
43cd72b9 BW |
5157 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5158 | if (fmt == XTENSA_UNDEFINED) | |
5159 | { | |
5160 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5161 | error_reset_cur_vinsn (); | |
5162 | return; | |
5163 | } | |
5164 | if (!cur_vinsn.inside_bundle) | |
5165 | { | |
5166 | as_bad (_("format names only valid inside bundles")); | |
5167 | error_reset_cur_vinsn (); | |
5168 | return; | |
5169 | } | |
5170 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5171 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5172 | opname); | |
5173 | cur_vinsn.format = fmt; | |
5174 | free (has_underbar ? opname - 1 : opname); | |
5175 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5176 | return; |
5177 | } | |
5178 | ||
e0001a05 NC |
5179 | /* Parse the arguments. */ |
5180 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5181 | { | |
5182 | as_bad (_("syntax error")); | |
43cd72b9 | 5183 | error_reset_cur_vinsn (); |
e0001a05 NC |
5184 | return; |
5185 | } | |
5186 | ||
5187 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5188 | free (has_underbar ? opname - 1 : opname); | |
5189 | opname = 0; | |
5190 | while (num_args-- > 0) | |
5191 | free (arg_strings[num_args]); | |
5192 | ||
43cd72b9 BW |
5193 | /* Get expressions for invisible operands. */ |
5194 | if (get_invisible_operands (&orig_insn)) | |
5195 | { | |
5196 | error_reset_cur_vinsn (); | |
5197 | return; | |
5198 | } | |
5199 | ||
e0001a05 NC |
5200 | /* Check for the right number and type of arguments. */ |
5201 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5202 | { |
43cd72b9 BW |
5203 | error_reset_cur_vinsn (); |
5204 | return; | |
e0001a05 NC |
5205 | } |
5206 | ||
7c430684 BW |
5207 | /* A FLIX bundle may be spread across multiple input lines. We want to |
5208 | report the first such line in the debug information. Record the line | |
5209 | number for each TInsn (assume the file name doesn't change), so the | |
5210 | first line can be found later. */ | |
5211 | as_where (&file_name, &orig_insn.linenum); | |
c138bc38 | 5212 | |
43cd72b9 BW |
5213 | xg_add_branch_and_loop_targets (&orig_insn); |
5214 | ||
431ad2d0 BW |
5215 | /* Check that immediate value for ENTRY is >= 16. */ |
5216 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5217 | { |
431ad2d0 BW |
5218 | expressionS *exp = &orig_insn.tok[2]; |
5219 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5220 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5221 | } |
5222 | ||
e0001a05 | 5223 | /* Finish it off: |
43cd72b9 BW |
5224 | assemble_tokens (opcode, tok, ntok); |
5225 | expand the tokens from the orig_insn into the | |
5226 | stack of instructions that will not expand | |
e0001a05 | 5227 | unless required at relaxation time. */ |
e0001a05 | 5228 | |
43cd72b9 BW |
5229 | if (!cur_vinsn.inside_bundle) |
5230 | emit_single_op (&orig_insn); | |
5231 | else /* We are inside a bundle. */ | |
e0001a05 | 5232 | { |
43cd72b9 BW |
5233 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5234 | cur_vinsn.num_slots++; | |
5235 | if (*input_line_pointer == '}' | |
5236 | || *(input_line_pointer - 1) == '}' | |
5237 | || *(input_line_pointer - 2) == '}') | |
5238 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5239 | } |
5240 | ||
43cd72b9 BW |
5241 | /* We've just emitted a new instruction so clear the list of labels. */ |
5242 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5243 | } |
5244 | ||
5245 | ||
43cd72b9 | 5246 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5247 | |
43cd72b9 BW |
5248 | /* For a .align directive, we mark the previous block with the alignment |
5249 | information. This will be placed in the object file in the | |
5250 | property section corresponding to this section. */ | |
e0001a05 | 5251 | |
43cd72b9 | 5252 | void |
7fa3d080 | 5253 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5254 | { |
5255 | if (linkrelax | |
b08b5071 | 5256 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5257 | && (fragP->fr_type == rs_align |
5258 | || fragP->fr_type == rs_align_code) | |
5259 | && fragP->fr_address + fragP->fr_fix > 0 | |
5260 | && fragP->fr_offset > 0 | |
5261 | && now_seg != bss_section) | |
e0001a05 | 5262 | { |
43cd72b9 BW |
5263 | fragP->tc_frag_data.is_align = TRUE; |
5264 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5265 | } |
5266 | ||
43cd72b9 | 5267 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5268 | { |
43cd72b9 BW |
5269 | int count; |
5270 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5271 | if (count != 0) | |
c138bc38 | 5272 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5273 | _("unaligned entry instruction")); |
e0001a05 | 5274 | } |
e0001a05 | 5275 | } |
43cd72b9 | 5276 | |
e0001a05 NC |
5277 | |
5278 | /* TC_FRAG_INIT hook */ | |
5279 | ||
5280 | void | |
7fa3d080 | 5281 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5282 | { |
43cd72b9 | 5283 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5284 | } |
5285 | ||
5286 | ||
5287 | symbolS * | |
7fa3d080 | 5288 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5289 | { |
5290 | return NULL; | |
5291 | } | |
5292 | ||
5293 | ||
5294 | /* Round up a section size to the appropriate boundary. */ | |
5295 | ||
5296 | valueT | |
7fa3d080 | 5297 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5298 | { |
5299 | return size; /* Byte alignment is fine. */ | |
5300 | } | |
5301 | ||
5302 | ||
5303 | long | |
7fa3d080 | 5304 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5305 | { |
5306 | char *insn_p; | |
5307 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5308 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5309 | int opnum; |
43cd72b9 | 5310 | uint32 opnd_value; |
e0001a05 | 5311 | xtensa_opcode opcode; |
43cd72b9 BW |
5312 | xtensa_format fmt; |
5313 | int slot; | |
e0001a05 NC |
5314 | xtensa_isa isa = xtensa_default_isa; |
5315 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5316 | bfd_boolean alt_reloc; |
e0001a05 | 5317 | |
e0001a05 | 5318 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5319 | return 0; |
e0001a05 NC |
5320 | |
5321 | if (!insnbuf) | |
43cd72b9 BW |
5322 | { |
5323 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5324 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5325 | } | |
e0001a05 NC |
5326 | |
5327 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5328 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5329 | fmt = xtensa_format_decode (isa, insnbuf); |
5330 | ||
5331 | if (fmt == XTENSA_UNDEFINED) | |
5332 | as_fatal (_("bad instruction format")); | |
5333 | ||
5334 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5335 | as_fatal (_("invalid relocation")); | |
5336 | ||
5337 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5338 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5339 | ||
30f725a1 BW |
5340 | /* Check for "alternate" relocations (operand not specified). None |
5341 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5342 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5343 | { | |
5344 | if (opcode != xtensa_l32r_opcode | |
5345 | && opcode != xtensa_const16_opcode) | |
5346 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5347 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5348 | return 0; |
e0001a05 NC |
5349 | } |
5350 | ||
43cd72b9 BW |
5351 | opnum = get_relaxable_immed (opcode); |
5352 | opnd_value = 0; | |
5353 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5354 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5355 | { |
5356 | as_bad_where (fixP->fx_file, | |
5357 | fixP->fx_line, | |
5358 | _("invalid relocation for operand %d of '%s'"), | |
5359 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5360 | return 0; |
e0001a05 | 5361 | } |
43cd72b9 BW |
5362 | return 0 - opnd_value; |
5363 | } | |
5364 | ||
5365 | ||
5366 | /* TC_FORCE_RELOCATION hook */ | |
5367 | ||
5368 | int | |
7fa3d080 | 5369 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5370 | { |
5371 | switch (fix->fx_r_type) | |
30f725a1 BW |
5372 | { |
5373 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5374 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5375 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5376 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5377 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5378 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5379 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5380 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5381 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5382 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5383 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5384 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5385 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5386 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5387 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5388 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5389 | return 1; |
5390 | default: | |
5391 | break; | |
e0001a05 NC |
5392 | } |
5393 | ||
43cd72b9 BW |
5394 | if (linkrelax && fix->fx_addsy |
5395 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5396 | return 1; | |
5397 | ||
5398 | return generic_force_reloc (fix); | |
5399 | } | |
5400 | ||
5401 | ||
30f725a1 BW |
5402 | /* TC_VALIDATE_FIX_SUB hook */ |
5403 | ||
5404 | int | |
5405 | xtensa_validate_fix_sub (fixS *fix) | |
5406 | { | |
5407 | segT add_symbol_segment, sub_symbol_segment; | |
5408 | ||
5409 | /* The difference of two symbols should be resolved by the assembler when | |
5410 | linkrelax is not set. If the linker may relax the section containing | |
5411 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5412 | the linker knows to adjust the difference value. */ | |
5413 | if (!linkrelax || fix->fx_addsy == NULL) | |
5414 | return 0; | |
5415 | ||
5416 | /* Make sure both symbols are in the same segment, and that segment is | |
5417 | "normal" and relaxable. If the segment is not "normal", then the | |
5418 | fix is not valid. If the segment is not "relaxable", then the fix | |
5419 | should have been handled earlier. */ | |
5420 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5421 | if (! SEG_NORMAL (add_symbol_segment) || | |
5422 | ! relaxable_section (add_symbol_segment)) | |
5423 | return 0; | |
5424 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5425 | return (sub_symbol_segment == add_symbol_segment); | |
5426 | } | |
5427 | ||
5428 | ||
43cd72b9 BW |
5429 | /* NO_PSEUDO_DOT hook */ |
5430 | ||
5431 | /* This function has nothing to do with pseudo dots, but this is the | |
5432 | nearest macro to where the check needs to take place. FIXME: This | |
5433 | seems wrong. */ | |
5434 | ||
5435 | bfd_boolean | |
7fa3d080 | 5436 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5437 | { |
5438 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5439 | as_bad (_("directives are not valid inside bundles")); | |
5440 | ||
5441 | /* This function must always return FALSE because it is called via a | |
5442 | macro that has nothing to do with bundling. */ | |
5443 | return FALSE; | |
e0001a05 NC |
5444 | } |
5445 | ||
5446 | ||
43cd72b9 | 5447 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5448 | |
5449 | void | |
7fa3d080 | 5450 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5451 | { |
43cd72b9 BW |
5452 | /* Set up the assembly state. */ |
5453 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5454 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5455 | } |
5456 | ||
5457 | ||
5458 | /* tc_fix_adjustable hook */ | |
5459 | ||
5460 | bfd_boolean | |
7fa3d080 | 5461 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 | 5462 | { |
43cd72b9 BW |
5463 | /* An offset is not allowed in combination with the difference of two |
5464 | symbols, but that cannot be easily detected after a local symbol | |
5465 | has been adjusted to a (section+offset) form. Return 0 so that such | |
5466 | an fix will not be adjusted. */ | |
5467 | if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset | |
5468 | && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy))) | |
5469 | return 0; | |
5470 | ||
e0001a05 NC |
5471 | /* We need the symbol name for the VTABLE entries. */ |
5472 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5473 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5474 | return 0; | |
5475 | ||
5476 | return 1; | |
5477 | } | |
5478 | ||
5479 | ||
5480 | void | |
55cf6793 | 5481 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5482 | { |
30f725a1 | 5483 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5484 | valueT val = 0; |
30f725a1 | 5485 | |
e7da6241 BW |
5486 | /* Subtracted symbols are only allowed for a few relocation types, and |
5487 | unless linkrelax is enabled, they should not make it to this point. */ | |
5488 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5489 | || fixP->fx_r_type == BFD_RELOC_16 | |
5490 | || fixP->fx_r_type == BFD_RELOC_8))) | |
5491 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
5492 | ||
30f725a1 | 5493 | switch (fixP->fx_r_type) |
e0001a05 | 5494 | { |
30f725a1 BW |
5495 | case BFD_RELOC_32: |
5496 | case BFD_RELOC_16: | |
5497 | case BFD_RELOC_8: | |
e7da6241 | 5498 | if (fixP->fx_subsy) |
30f725a1 BW |
5499 | { |
5500 | switch (fixP->fx_r_type) | |
5501 | { | |
5502 | case BFD_RELOC_8: | |
5503 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
5504 | break; | |
5505 | case BFD_RELOC_16: | |
5506 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
5507 | break; | |
5508 | case BFD_RELOC_32: | |
5509 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
5510 | break; | |
5511 | default: | |
5512 | break; | |
5513 | } | |
e0001a05 | 5514 | |
30f725a1 BW |
5515 | /* An offset is only allowed when it results from adjusting a |
5516 | local symbol into a section-relative offset. If the offset | |
5517 | came from the original expression, tc_fix_adjustable will have | |
5518 | prevented the fix from being converted to a section-relative | |
5519 | form so that we can flag the error here. */ | |
5520 | if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy)) | |
5521 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5522 | _("cannot represent subtraction with an offset")); | |
5523 | ||
5524 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5525 | - S_GET_VALUE (fixP->fx_subsy)); | |
5526 | ||
5527 | /* The difference value gets written out, and the DIFF reloc | |
5528 | identifies the address of the subtracted symbol (i.e., the one | |
5529 | with the lowest address). */ | |
5530 | *valP = val; | |
5531 | fixP->fx_offset -= val; | |
5532 | fixP->fx_subsy = NULL; | |
5533 | } | |
5534 | else if (! fixP->fx_addsy) | |
e0001a05 | 5535 | { |
30f725a1 | 5536 | val = *valP; |
e0001a05 | 5537 | fixP->fx_done = 1; |
30f725a1 | 5538 | } |
d47d412e BW |
5539 | /* fall through */ |
5540 | ||
5541 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
5542 | md_number_to_chars (fixpos, val, fixP->fx_size); |
5543 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5544 | break; | |
e0001a05 | 5545 | |
30f725a1 BW |
5546 | case BFD_RELOC_XTENSA_SLOT0_OP: |
5547 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
5548 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
5549 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
5550 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
5551 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
5552 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
5553 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
5554 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
5555 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
5556 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
5557 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
5558 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
5559 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
5560 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
5561 | if (linkrelax) | |
5562 | { | |
5563 | /* Write the tentative value of a PC-relative relocation to a | |
5564 | local symbol into the instruction. The value will be ignored | |
5565 | by the linker, and it makes the object file disassembly | |
5566 | readable when all branch targets are encoded in relocations. */ | |
5567 | ||
5568 | assert (fixP->fx_addsy); | |
20ee54e8 AM |
5569 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg |
5570 | && !fixP->fx_tcbit | |
30f725a1 BW |
5571 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) |
5572 | { | |
5573 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5574 | - md_pcrel_from (fixP)); | |
5575 | (void) xg_apply_fix_value (fixP, val); | |
5576 | } | |
5577 | } | |
5578 | else if (! fixP->fx_addsy) | |
5579 | { | |
5580 | val = *valP; | |
5581 | if (xg_apply_fix_value (fixP, val)) | |
5582 | fixP->fx_done = 1; | |
5583 | } | |
5584 | break; | |
e0001a05 | 5585 | |
30f725a1 BW |
5586 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
5587 | case BFD_RELOC_XTENSA_SLOT0_ALT: | |
5588 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5589 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5590 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5591 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5592 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5593 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5594 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5595 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5596 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5597 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5598 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5599 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5600 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5601 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
5602 | /* These all need to be resolved at link-time. Do nothing now. */ | |
5603 | break; | |
e0001a05 | 5604 | |
30f725a1 BW |
5605 | case BFD_RELOC_VTABLE_INHERIT: |
5606 | case BFD_RELOC_VTABLE_ENTRY: | |
5607 | fixP->fx_done = 0; | |
5608 | break; | |
e0001a05 | 5609 | |
30f725a1 BW |
5610 | default: |
5611 | as_bad (_("unhandled local relocation fix %s"), | |
5612 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
5613 | } |
5614 | } | |
5615 | ||
5616 | ||
5617 | char * | |
7fa3d080 | 5618 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 NC |
5619 | { |
5620 | int prec; | |
5621 | LITTLENUM_TYPE words[4]; | |
5622 | char *t; | |
5623 | int i; | |
5624 | ||
5625 | switch (type) | |
5626 | { | |
5627 | case 'f': | |
5628 | prec = 2; | |
5629 | break; | |
5630 | ||
5631 | case 'd': | |
5632 | prec = 4; | |
5633 | break; | |
5634 | ||
5635 | default: | |
5636 | *sizeP = 0; | |
5637 | return "bad call to md_atof"; | |
5638 | } | |
5639 | ||
5640 | t = atof_ieee (input_line_pointer, type, words); | |
5641 | if (t) | |
5642 | input_line_pointer = t; | |
5643 | ||
5644 | *sizeP = prec * 2; | |
5645 | ||
5646 | for (i = prec - 1; i >= 0; i--) | |
5647 | { | |
5648 | int idx = i; | |
5649 | if (target_big_endian) | |
5650 | idx = (prec - 1 - i); | |
5651 | ||
5652 | md_number_to_chars (litP, (valueT) words[idx], 2); | |
5653 | litP += 2; | |
5654 | } | |
5655 | ||
5656 | return NULL; | |
5657 | } | |
5658 | ||
5659 | ||
5660 | int | |
7fa3d080 | 5661 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 5662 | { |
34e41783 | 5663 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
5664 | } |
5665 | ||
5666 | ||
5667 | /* Translate internal representation of relocation info to BFD target | |
5668 | format. */ | |
5669 | ||
5670 | arelent * | |
30f725a1 | 5671 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
5672 | { |
5673 | arelent *reloc; | |
5674 | ||
5675 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
5676 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
5677 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
5678 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
5679 | ||
5680 | /* Make sure none of our internal relocations make it this far. | |
5681 | They'd better have been fully resolved by this point. */ | |
5682 | assert ((int) fixp->fx_r_type > 0); | |
5683 | ||
30f725a1 | 5684 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 5685 | |
e0001a05 NC |
5686 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
5687 | if (reloc->howto == NULL) | |
5688 | { | |
5689 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
5690 | _("cannot represent `%s' relocation in object file"), | |
5691 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
5692 | free (reloc->sym_ptr_ptr); |
5693 | free (reloc); | |
e0001a05 NC |
5694 | return NULL; |
5695 | } | |
5696 | ||
5697 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
43cd72b9 BW |
5698 | as_fatal (_("internal error? cannot generate `%s' relocation"), |
5699 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
e0001a05 | 5700 | |
e0001a05 NC |
5701 | return reloc; |
5702 | } | |
5703 | ||
7fa3d080 BW |
5704 | \f |
5705 | /* Checks for resource conflicts between instructions. */ | |
5706 | ||
c138bc38 BW |
5707 | /* The func unit stuff could be implemented as bit-vectors rather |
5708 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
5709 | slow, we will switch it. */ |
5710 | ||
c138bc38 | 5711 | resource_table * |
7fa3d080 BW |
5712 | new_resource_table (void *data, |
5713 | int cycles, | |
5714 | int nu, | |
5715 | unit_num_copies_func uncf, | |
5716 | opcode_num_units_func onuf, | |
5717 | opcode_funcUnit_use_unit_func ouuf, | |
5718 | opcode_funcUnit_use_stage_func ousf) | |
5719 | { | |
5720 | int i; | |
5721 | resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); | |
5722 | rt->data = data; | |
5723 | rt->cycles = cycles; | |
5724 | rt->allocated_cycles = cycles; | |
5725 | rt->num_units = nu; | |
5726 | rt->unit_num_copies = uncf; | |
5727 | rt->opcode_num_units = onuf; | |
5728 | rt->opcode_unit_use = ouuf; | |
5729 | rt->opcode_unit_stage = ousf; | |
5730 | ||
0bf60745 | 5731 | rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *)); |
7fa3d080 | 5732 | for (i = 0; i < cycles; i++) |
0bf60745 | 5733 | rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char)); |
7fa3d080 BW |
5734 | |
5735 | return rt; | |
5736 | } | |
5737 | ||
5738 | ||
c138bc38 | 5739 | void |
7fa3d080 BW |
5740 | clear_resource_table (resource_table *rt) |
5741 | { | |
5742 | int i, j; | |
5743 | for (i = 0; i < rt->allocated_cycles; i++) | |
5744 | for (j = 0; j < rt->num_units; j++) | |
5745 | rt->units[i][j] = 0; | |
5746 | } | |
5747 | ||
5748 | ||
5749 | /* We never shrink it, just fake it into thinking so. */ | |
5750 | ||
c138bc38 | 5751 | void |
7fa3d080 BW |
5752 | resize_resource_table (resource_table *rt, int cycles) |
5753 | { | |
5754 | int i, old_cycles; | |
5755 | ||
5756 | rt->cycles = cycles; | |
5757 | if (cycles <= rt->allocated_cycles) | |
5758 | return; | |
5759 | ||
5760 | old_cycles = rt->allocated_cycles; | |
5761 | rt->allocated_cycles = cycles; | |
5762 | ||
0bf60745 BW |
5763 | rt->units = xrealloc (rt->units, |
5764 | rt->allocated_cycles * sizeof (unsigned char *)); | |
7fa3d080 | 5765 | for (i = 0; i < old_cycles; i++) |
0bf60745 BW |
5766 | rt->units[i] = xrealloc (rt->units[i], |
5767 | rt->num_units * sizeof (unsigned char)); | |
7fa3d080 | 5768 | for (i = old_cycles; i < cycles; i++) |
0bf60745 | 5769 | rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char)); |
7fa3d080 BW |
5770 | } |
5771 | ||
5772 | ||
c138bc38 | 5773 | bfd_boolean |
7fa3d080 BW |
5774 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
5775 | { | |
5776 | int i; | |
5777 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5778 | ||
c138bc38 | 5779 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5780 | { |
5781 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5782 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
5783 | int copies_in_use = rt->units[stage + cycle][unit]; | |
5784 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
5785 | if (copies_in_use >= copies) | |
5786 | return FALSE; | |
5787 | } | |
5788 | return TRUE; | |
5789 | } | |
7fa3d080 | 5790 | |
c138bc38 BW |
5791 | |
5792 | void | |
7fa3d080 BW |
5793 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5794 | { | |
5795 | int i; | |
5796 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5797 | ||
c138bc38 | 5798 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5799 | { |
5800 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5801 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
5802 | /* Note that this allows resources to be oversubscribed. That's |
5803 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
5804 | resources_available reports when a resource is over-subscribed, |
5805 | so it's easy to tell. */ | |
5806 | rt->units[stage + cycle][unit]++; | |
5807 | } | |
5808 | } | |
5809 | ||
5810 | ||
c138bc38 | 5811 | void |
7fa3d080 BW |
5812 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5813 | { | |
5814 | int i; | |
5815 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5816 | ||
c138bc38 | 5817 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5818 | { |
5819 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5820 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
0bf60745 | 5821 | assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 5822 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
5823 | } |
5824 | } | |
c138bc38 | 5825 | |
7fa3d080 BW |
5826 | |
5827 | /* Wrapper functions make parameterized resource reservation | |
5828 | more convenient. */ | |
5829 | ||
c138bc38 | 5830 | int |
7fa3d080 BW |
5831 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
5832 | { | |
5833 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 5834 | return use->unit; |
7fa3d080 BW |
5835 | } |
5836 | ||
5837 | ||
c138bc38 | 5838 | int |
7fa3d080 BW |
5839 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
5840 | { | |
5841 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
5842 | return use->stage; | |
5843 | } | |
5844 | ||
5845 | ||
5846 | /* Note that this function does not check issue constraints, but | |
5847 | solely whether the hardware is available to execute the given | |
c138bc38 | 5848 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 5849 | write the same state, or access the same tieports. That is |
a1ace8d8 | 5850 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
5851 | |
5852 | static bfd_boolean | |
5853 | resources_conflict (vliw_insn *vinsn) | |
5854 | { | |
5855 | int i; | |
5856 | static resource_table *rt = NULL; | |
5857 | ||
5858 | /* This is the most common case by far. Optimize it. */ | |
5859 | if (vinsn->num_slots == 1) | |
5860 | return FALSE; | |
43cd72b9 | 5861 | |
c138bc38 | 5862 | if (rt == NULL) |
7fa3d080 BW |
5863 | { |
5864 | xtensa_isa isa = xtensa_default_isa; | |
5865 | rt = new_resource_table | |
5866 | (isa, xtensa_isa_num_pipe_stages (isa), | |
5867 | xtensa_isa_num_funcUnits (isa), | |
5868 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
5869 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
5870 | opcode_funcUnit_use_unit, | |
5871 | opcode_funcUnit_use_stage); | |
5872 | } | |
43cd72b9 | 5873 | |
7fa3d080 | 5874 | clear_resource_table (rt); |
43cd72b9 | 5875 | |
7fa3d080 BW |
5876 | for (i = 0; i < vinsn->num_slots; i++) |
5877 | { | |
5878 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
5879 | return TRUE; | |
5880 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
5881 | } | |
e0001a05 | 5882 | |
7fa3d080 BW |
5883 | return FALSE; |
5884 | } | |
e0001a05 | 5885 | |
7fa3d080 BW |
5886 | \f |
5887 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 5888 | |
7fa3d080 BW |
5889 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
5890 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 5891 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
5892 | |
5893 | ||
43cd72b9 BW |
5894 | /* We have reached the end of a bundle; emit into the frag. */ |
5895 | ||
e0001a05 | 5896 | static void |
7fa3d080 | 5897 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 5898 | { |
43cd72b9 BW |
5899 | IStack slotstack; |
5900 | int i; | |
5901 | char *file_name; | |
d77b99c9 | 5902 | unsigned line; |
e0001a05 | 5903 | |
43cd72b9 | 5904 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
5905 | { |
5906 | xg_clear_vinsn (vinsn); | |
5907 | return; | |
5908 | } | |
43cd72b9 BW |
5909 | |
5910 | /* First, find a format that works. */ | |
5911 | if (vinsn->format == XTENSA_UNDEFINED) | |
5912 | vinsn->format = xg_find_narrowest_format (vinsn); | |
5913 | ||
5914 | if (vinsn->format == XTENSA_UNDEFINED) | |
5915 | { | |
5916 | as_where (&file_name, &line); | |
5917 | as_bad_where (file_name, line, | |
5918 | _("couldn't find a valid instruction format")); | |
5919 | fprintf (stderr, _(" ops were: ")); | |
5920 | for (i = 0; i < vinsn->num_slots; i++) | |
5921 | fprintf (stderr, _(" %s;"), | |
5922 | xtensa_opcode_name (xtensa_default_isa, | |
5923 | vinsn->slots[i].opcode)); | |
5924 | fprintf (stderr, _("\n")); | |
5925 | xg_clear_vinsn (vinsn); | |
5926 | return; | |
5927 | } | |
5928 | ||
5929 | if (vinsn->num_slots | |
5930 | != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) | |
e0001a05 | 5931 | { |
43cd72b9 BW |
5932 | as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), |
5933 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
5934 | xtensa_format_num_slots (xtensa_default_isa, vinsn->format), | |
5935 | vinsn->num_slots); | |
5936 | xg_clear_vinsn (vinsn); | |
5937 | return; | |
5938 | } | |
e0001a05 | 5939 | |
c138bc38 | 5940 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
5941 | { |
5942 | as_where (&file_name, &line); | |
5943 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
5944 | fprintf (stderr, " ops were: "); | |
5945 | for (i = 0; i < vinsn->num_slots; i++) | |
5946 | fprintf (stderr, " %s;", | |
5947 | xtensa_opcode_name (xtensa_default_isa, | |
5948 | vinsn->slots[i].opcode)); | |
5949 | fprintf (stderr, "\n"); | |
5950 | xg_clear_vinsn (vinsn); | |
5951 | return; | |
5952 | } | |
5953 | ||
5954 | for (i = 0; i < vinsn->num_slots; i++) | |
5955 | { | |
5956 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 5957 | { |
43cd72b9 BW |
5958 | symbolS *lit_sym = NULL; |
5959 | int j; | |
5960 | bfd_boolean e = FALSE; | |
5961 | bfd_boolean saved_density = density_supported; | |
5962 | ||
5963 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
5964 | if (vinsn->num_slots > 1) | |
5965 | density_supported = FALSE; | |
5966 | ||
5967 | istack_init (&slotstack); | |
5968 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 5969 | { |
43cd72b9 BW |
5970 | vinsn->slots[i].opcode = |
5971 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
5972 | vinsn->format, i); | |
5973 | vinsn->slots[i].ntok = 0; | |
5974 | } | |
e0001a05 | 5975 | |
43cd72b9 BW |
5976 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
5977 | { | |
5978 | e = TRUE; | |
5979 | continue; | |
e0001a05 | 5980 | } |
e0001a05 | 5981 | |
43cd72b9 | 5982 | density_supported = saved_density; |
e0001a05 | 5983 | |
43cd72b9 BW |
5984 | if (e) |
5985 | { | |
5986 | xg_clear_vinsn (vinsn); | |
5987 | return; | |
5988 | } | |
e0001a05 | 5989 | |
0fa77c95 | 5990 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
5991 | { |
5992 | TInsn *insn = &slotstack.insn[j]; | |
5993 | if (insn->insn_type == ITYPE_LITERAL) | |
5994 | { | |
5995 | assert (lit_sym == NULL); | |
5996 | lit_sym = xg_assemble_literal (insn); | |
5997 | } | |
5998 | else | |
5999 | { | |
0fa77c95 | 6000 | assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6001 | if (lit_sym) |
6002 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6003 | if (j != slotstack.ninsn - 1) |
6004 | emit_single_op (insn); | |
43cd72b9 BW |
6005 | } |
6006 | } | |
6007 | ||
6008 | if (vinsn->num_slots > 1) | |
6009 | { | |
6010 | if (opcode_fits_format_slot | |
6011 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6012 | vinsn->format, i)) | |
6013 | { | |
6014 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6015 | } | |
6016 | else | |
6017 | { | |
b2d179be | 6018 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6019 | if (vinsn->format == XTENSA_UNDEFINED) |
6020 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6021 | else | |
c138bc38 | 6022 | vinsn->slots[i].opcode |
43cd72b9 BW |
6023 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6024 | vinsn->format, i); | |
6025 | ||
6026 | vinsn->slots[i].ntok = 0; | |
6027 | } | |
6028 | } | |
6029 | else | |
6030 | { | |
6031 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6032 | vinsn->format = XTENSA_UNDEFINED; | |
6033 | } | |
6034 | } | |
6035 | } | |
6036 | ||
6037 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6038 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6039 | { |
6040 | as_where (&file_name, &line); | |
6041 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6042 | fprintf (stderr, " ops were: "); | |
6043 | for (i = 0; i < vinsn->num_slots; i++) | |
6044 | fprintf (stderr, " %s;", | |
6045 | xtensa_opcode_name (xtensa_default_isa, | |
6046 | vinsn->slots[i].opcode)); | |
6047 | fprintf (stderr, "\n"); | |
6048 | xg_clear_vinsn (vinsn); | |
6049 | return; | |
6050 | } | |
6051 | ||
6052 | /* First, find a format that works. */ | |
6053 | if (vinsn->format == XTENSA_UNDEFINED) | |
6054 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6055 | ||
6056 | xg_assemble_vliw_tokens (vinsn); | |
6057 | ||
6058 | xg_clear_vinsn (vinsn); | |
6059 | } | |
6060 | ||
6061 | ||
6062 | /* Given an vliw instruction, what conflicts are there in register | |
6063 | usage and in writes to states and queues? | |
6064 | ||
6065 | This function does two things: | |
6066 | 1. Reports an error when a vinsn contains illegal combinations | |
6067 | of writes to registers states or queues. | |
6068 | 2. Marks individual tinsns as not relaxable if the combination | |
6069 | contains antidependencies. | |
6070 | ||
6071 | Job 2 handles things like swap semantics in instructions that need | |
6072 | to be relaxed. For example, | |
6073 | ||
6074 | addi a0, a1, 100000 | |
6075 | ||
6076 | normally would be relaxed to | |
6077 | ||
6078 | l32r a0, some_label | |
6079 | add a0, a1, a0 | |
6080 | ||
6081 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6082 | ||
6083 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6084 | ||
6085 | then we can't relax it into | |
6086 | ||
6087 | l32r a0, some_label | |
6088 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6089 | ||
6090 | because the value of a0 is trashed before the second add can read it. */ | |
6091 | ||
7fa3d080 BW |
6092 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6093 | ||
43cd72b9 | 6094 | static bfd_boolean |
7fa3d080 | 6095 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6096 | { |
6097 | int i, j; | |
6098 | int branches = 0; | |
6099 | xtensa_isa isa = xtensa_default_isa; | |
6100 | ||
6101 | assert (!past_xtensa_end); | |
6102 | ||
6103 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6104 | { | |
6105 | TInsn *op1 = &vinsn->slots[i]; | |
6106 | if (op1->is_specific_opcode) | |
6107 | op1->keep_wide = TRUE; | |
6108 | else | |
6109 | op1->keep_wide = FALSE; | |
6110 | } | |
6111 | ||
6112 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6113 | { | |
6114 | TInsn *op1 = &vinsn->slots[i]; | |
6115 | ||
6116 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6117 | branches++; | |
6118 | ||
6119 | for (j = 0; j < vinsn->num_slots; j++) | |
6120 | { | |
6121 | if (i != j) | |
6122 | { | |
6123 | TInsn *op2 = &vinsn->slots[j]; | |
6124 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6125 | switch (conflict_type) | |
6126 | { | |
6127 | case 'c': | |
6128 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6129 | xtensa_opcode_name (isa, op1->opcode), i, | |
6130 | xtensa_opcode_name (isa, op2->opcode), j); | |
6131 | return TRUE; | |
6132 | case 'd': | |
6133 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6134 | xtensa_opcode_name (isa, op1->opcode), i, | |
6135 | xtensa_opcode_name (isa, op2->opcode), j); | |
6136 | return TRUE; | |
6137 | case 'e': | |
53dfbcc7 | 6138 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6139 | xtensa_opcode_name (isa, op1->opcode), i, |
6140 | xtensa_opcode_name (isa, op2->opcode), j); | |
6141 | return TRUE; | |
6142 | case 'f': | |
53dfbcc7 | 6143 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6144 | xtensa_opcode_name (isa, op1->opcode), i, |
6145 | xtensa_opcode_name (isa, op2->opcode), j); | |
6146 | return TRUE; | |
6147 | default: | |
6148 | /* Everything is OK. */ | |
6149 | break; | |
6150 | } | |
6151 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6152 | || conflict_type == 'a'); | |
6153 | } | |
6154 | } | |
6155 | } | |
6156 | ||
6157 | if (branches > 1) | |
6158 | { | |
6159 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6160 | return TRUE; | |
6161 | } | |
6162 | ||
6163 | return FALSE; | |
6164 | } | |
6165 | ||
6166 | ||
a1ace8d8 | 6167 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6168 | Cases found are: |
6169 | ||
6170 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6171 | case B: no relationship between what is read and written (both could | |
6172 | read the same reg though) | |
c138bc38 | 6173 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6174 | bundle) |
6175 | case D: t1 writes a state that t2 also writes | |
6176 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6177 | case F: two volatile queue accesses |
43cd72b9 BW |
6178 | */ |
6179 | ||
6180 | static char | |
7fa3d080 | 6181 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6182 | { |
6183 | xtensa_isa isa = xtensa_default_isa; | |
6184 | xtensa_regfile t1_regfile, t2_regfile; | |
6185 | int t1_reg, t2_reg; | |
6186 | int t1_base_reg, t1_last_reg; | |
6187 | int t2_base_reg, t2_last_reg; | |
6188 | char t1_inout, t2_inout; | |
6189 | int i, j; | |
6190 | char conflict = 'b'; | |
6191 | int t1_states; | |
6192 | int t2_states; | |
6193 | int t1_interfaces; | |
6194 | int t2_interfaces; | |
6195 | bfd_boolean t1_volatile = FALSE; | |
6196 | bfd_boolean t2_volatile = FALSE; | |
6197 | ||
6198 | /* Check registers. */ | |
6199 | for (j = 0; j < t2->ntok; j++) | |
6200 | { | |
6201 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6202 | continue; | |
6203 | ||
6204 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6205 | t2_base_reg = t2->tok[j].X_add_number; | |
6206 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6207 | ||
6208 | for (i = 0; i < t1->ntok; i++) | |
6209 | { | |
6210 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6211 | continue; | |
6212 | ||
6213 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6214 | ||
6215 | if (t1_regfile != t2_regfile) | |
6216 | continue; | |
6217 | ||
6218 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6219 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6220 | ||
6221 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6222 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6223 | { | |
6224 | if (t1_inout == 'm' || t1_inout == 'o' | |
6225 | || t2_inout == 'm' || t2_inout == 'o') | |
6226 | { | |
6227 | conflict = 'a'; | |
6228 | continue; | |
6229 | } | |
6230 | } | |
6231 | ||
6232 | t1_base_reg = t1->tok[i].X_add_number; | |
6233 | t1_last_reg = (t1_base_reg | |
6234 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6235 | ||
6236 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6237 | { | |
6238 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6239 | { | |
6240 | if (t1_reg != t2_reg) | |
6241 | continue; | |
6242 | ||
6243 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6244 | { |
6245 | conflict = 'a'; | |
6246 | continue; | |
6247 | } | |
43cd72b9 | 6248 | |
7fa3d080 BW |
6249 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6250 | { | |
6251 | conflict = 'a'; | |
6252 | continue; | |
6253 | } | |
43cd72b9 | 6254 | |
7fa3d080 BW |
6255 | if (t1_inout != 'i' && t2_inout != 'i') |
6256 | return 'c'; | |
6257 | } | |
6258 | } | |
6259 | } | |
6260 | } | |
43cd72b9 | 6261 | |
7fa3d080 BW |
6262 | /* Check states. */ |
6263 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6264 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6265 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6266 | { |
7fa3d080 BW |
6267 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6268 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6269 | for (i = 0; i < t1_states; i++) | |
6270 | { | |
6271 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6272 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
c138bc38 | 6273 | if (t1_so != t2_so) |
7fa3d080 | 6274 | continue; |
43cd72b9 | 6275 | |
7fa3d080 BW |
6276 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6277 | { | |
6278 | conflict = 'a'; | |
6279 | continue; | |
6280 | } | |
c138bc38 | 6281 | |
7fa3d080 BW |
6282 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6283 | { | |
6284 | conflict = 'a'; | |
6285 | continue; | |
6286 | } | |
c138bc38 | 6287 | |
7fa3d080 BW |
6288 | if (t1_inout != 'i' && t2_inout != 'i') |
6289 | return 'd'; | |
c138bc38 | 6290 | } |
7fa3d080 | 6291 | } |
43cd72b9 | 6292 | |
7fa3d080 BW |
6293 | /* Check tieports. */ |
6294 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6295 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6296 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6297 | { |
7fa3d080 BW |
6298 | xtensa_interface t2_int |
6299 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6300 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6301 | ||
53dfbcc7 | 6302 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6303 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6304 | t2_volatile = TRUE; |
a1ace8d8 | 6305 | |
7fa3d080 BW |
6306 | for (i = 0; i < t1_interfaces; i++) |
6307 | { | |
6308 | xtensa_interface t1_int | |
6309 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6310 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6311 | |
53dfbcc7 | 6312 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6313 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6314 | t1_volatile = TRUE; |
a1ace8d8 BW |
6315 | |
6316 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6317 | return 'f'; | |
c138bc38 | 6318 | |
7fa3d080 BW |
6319 | if (t1_int != t2_int) |
6320 | continue; | |
c138bc38 | 6321 | |
7fa3d080 BW |
6322 | if (t2_inout == 'i' && t1_inout == 'o') |
6323 | { | |
6324 | conflict = 'a'; | |
6325 | continue; | |
6326 | } | |
c138bc38 | 6327 | |
7fa3d080 BW |
6328 | if (t1_inout == 'i' && t2_inout == 'o') |
6329 | { | |
6330 | conflict = 'a'; | |
6331 | continue; | |
6332 | } | |
c138bc38 | 6333 | |
7fa3d080 BW |
6334 | if (t1_inout != 'i' && t2_inout != 'i') |
6335 | return 'e'; | |
6336 | } | |
43cd72b9 | 6337 | } |
c138bc38 | 6338 | |
7fa3d080 | 6339 | return conflict; |
43cd72b9 BW |
6340 | } |
6341 | ||
6342 | ||
6343 | static xtensa_format | |
7fa3d080 | 6344 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6345 | { |
6346 | /* Right now we assume that the ops within the vinsn are properly | |
6347 | ordered for the slots that the programmer wanted them in. In | |
6348 | other words, we don't rearrange the ops in hopes of finding a | |
6349 | better format. The scheduler handles that. */ | |
6350 | ||
6351 | xtensa_isa isa = xtensa_default_isa; | |
6352 | xtensa_format format; | |
6353 | vliw_insn v_copy = *vinsn; | |
6354 | xtensa_opcode nop_opcode = xtensa_nop_opcode; | |
6355 | ||
65738a7d BW |
6356 | if (vinsn->num_slots == 1) |
6357 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6358 | ||
43cd72b9 BW |
6359 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6360 | { | |
6361 | v_copy = *vinsn; | |
6362 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) | |
6363 | { | |
6364 | int slot; | |
6365 | int fit = 0; | |
6366 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6367 | { | |
6368 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6369 | { | |
6370 | v_copy.slots[slot].opcode = | |
6371 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6372 | v_copy.slots[slot].ntok = 0; | |
6373 | } | |
6374 | ||
6375 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6376 | format, slot)) | |
6377 | fit++; | |
7fa3d080 | 6378 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6379 | { |
7fa3d080 BW |
6380 | TInsn widened; |
6381 | /* Try the widened version. */ | |
6382 | if (!v_copy.slots[slot].keep_wide | |
6383 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6384 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6385 | &widened, TRUE) | |
7fa3d080 BW |
6386 | && opcode_fits_format_slot (widened.opcode, |
6387 | format, slot)) | |
43cd72b9 | 6388 | { |
7fa3d080 BW |
6389 | v_copy.slots[slot] = widened; |
6390 | fit++; | |
43cd72b9 BW |
6391 | } |
6392 | } | |
6393 | } | |
6394 | if (fit == v_copy.num_slots) | |
6395 | { | |
6396 | *vinsn = v_copy; | |
6397 | xtensa_format_encode (isa, format, vinsn->insnbuf); | |
6398 | vinsn->format = format; | |
6399 | break; | |
6400 | } | |
6401 | } | |
6402 | } | |
6403 | ||
6404 | if (format == xtensa_isa_num_formats (isa)) | |
6405 | return XTENSA_UNDEFINED; | |
6406 | ||
6407 | return format; | |
6408 | } | |
6409 | ||
6410 | ||
6411 | /* Return the additional space needed in a frag | |
6412 | for possible relaxations of any ops in a VLIW insn. | |
6413 | Also fill out the relaxations that might be required of | |
6414 | each tinsn in the vinsn. */ | |
6415 | ||
6416 | static int | |
e7da6241 | 6417 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6418 | { |
e7da6241 | 6419 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6420 | int extra_space = 0; |
6421 | int slot; | |
6422 | ||
6423 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6424 | { | |
6425 | TInsn *tinsn = &vinsn->slots[slot]; | |
6426 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6427 | { | |
6428 | /* A narrow instruction could be widened later to help | |
6429 | alignment issues. */ | |
84b08ed9 | 6430 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6431 | && !tinsn->is_specific_opcode |
6432 | && vinsn->num_slots == 1) | |
6433 | { | |
6434 | /* Difference in bytes between narrow and wide insns... */ | |
6435 | extra_space += 1; | |
6436 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6437 | } |
6438 | } | |
6439 | else | |
6440 | { | |
b08b5071 BW |
6441 | if (workaround_b_j_loop_end |
6442 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6443 | && use_transform ()) |
6444 | { | |
6445 | /* Add 2 of these. */ | |
6446 | extra_space += 3; /* for the nop size */ | |
6447 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6448 | } | |
c138bc38 | 6449 | |
43cd72b9 BW |
6450 | /* Need to assemble it with space for the relocation. */ |
6451 | if (xg_is_relaxable_insn (tinsn, 0) | |
6452 | && !tinsn->is_specific_opcode) | |
6453 | { | |
6454 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6455 | int max_literal_size = | |
6456 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6457 | |
43cd72b9 | 6458 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6459 | |
43cd72b9 | 6460 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6461 | extra_space += max_size; |
6462 | } | |
6463 | else | |
6464 | { | |
e7da6241 BW |
6465 | /* A fix record will be added for this instruction prior |
6466 | to relaxation, so make it end the frag. */ | |
6467 | finish_frag = TRUE; | |
43cd72b9 BW |
6468 | } |
6469 | } | |
6470 | } | |
e7da6241 | 6471 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6472 | return extra_space; |
6473 | } | |
6474 | ||
6475 | ||
6476 | static void | |
b2d179be | 6477 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6478 | { |
6479 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6480 | int slot, chosen_slot; |
43cd72b9 | 6481 | |
b2d179be BW |
6482 | vinsn->format = xg_get_single_format (tinsn->opcode); |
6483 | assert (vinsn->format != XTENSA_UNDEFINED); | |
6484 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); | |
43cd72b9 | 6485 | |
b2d179be BW |
6486 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6487 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6488 | { |
b2d179be BW |
6489 | if (slot == chosen_slot) |
6490 | vinsn->slots[slot] = *tinsn; | |
6491 | else | |
6492 | { | |
6493 | vinsn->slots[slot].opcode = | |
6494 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6495 | vinsn->slots[slot].ntok = 0; | |
6496 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6497 | } | |
43cd72b9 | 6498 | } |
43cd72b9 BW |
6499 | } |
6500 | ||
6501 | ||
6502 | static bfd_boolean | |
7fa3d080 | 6503 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6504 | { |
6505 | int i; | |
6506 | IStack istack; /* put instructions into here */ | |
6507 | symbolS *lit_sym = NULL; | |
6508 | symbolS *label_sym = NULL; | |
6509 | ||
6510 | istack_init (&istack); | |
6511 | ||
6512 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
6513 | Because the scheduling and bundling characteristics of movi and |
6514 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 6515 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 6516 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
6517 | || orig_insn->opcode == xtensa_movi_n_opcode) |
6518 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 6519 | && (orig_insn->tok[1].X_op == O_symbol |
482fd9f9 BW |
6520 | || orig_insn->tok[1].X_op == O_pltrel) |
6521 | && !orig_insn->is_specific_opcode && use_transform ()) | |
43cd72b9 BW |
6522 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
6523 | else | |
6524 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6525 | return TRUE; | |
6526 | ||
6527 | for (i = 0; i < istack.ninsn; i++) | |
6528 | { | |
6529 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 6530 | switch (insn->insn_type) |
43cd72b9 BW |
6531 | { |
6532 | case ITYPE_LITERAL: | |
6533 | assert (lit_sym == NULL); | |
6534 | lit_sym = xg_assemble_literal (insn); | |
6535 | break; | |
6536 | case ITYPE_LABEL: | |
6537 | { | |
6538 | static int relaxed_sym_idx = 0; | |
6539 | char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); | |
6540 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); | |
6541 | colon (label); | |
6542 | assert (label_sym == NULL); | |
6543 | label_sym = symbol_find_or_make (label); | |
6544 | assert (label_sym); | |
6545 | free (label); | |
6546 | } | |
6547 | break; | |
6548 | case ITYPE_INSN: | |
b2d179be BW |
6549 | { |
6550 | vliw_insn v; | |
6551 | if (lit_sym) | |
6552 | xg_resolve_literals (insn, lit_sym); | |
6553 | if (label_sym) | |
6554 | xg_resolve_labels (insn, label_sym); | |
6555 | xg_init_vinsn (&v); | |
6556 | bundle_tinsn (insn, &v); | |
6557 | finish_vinsn (&v); | |
6558 | xg_free_vinsn (&v); | |
6559 | } | |
43cd72b9 BW |
6560 | break; |
6561 | default: | |
6562 | assert (0); | |
6563 | break; | |
6564 | } | |
6565 | } | |
6566 | return FALSE; | |
6567 | } | |
6568 | ||
6569 | ||
34e41783 BW |
6570 | static int |
6571 | total_frag_text_expansion (fragS *fragP) | |
6572 | { | |
6573 | int slot; | |
6574 | int total_expansion = 0; | |
6575 | ||
6576 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
6577 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; | |
6578 | ||
6579 | return total_expansion; | |
6580 | } | |
6581 | ||
6582 | ||
43cd72b9 BW |
6583 | /* Emit a vliw instruction to the current fragment. */ |
6584 | ||
7fa3d080 BW |
6585 | static void |
6586 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 6587 | { |
e7da6241 | 6588 | bfd_boolean finish_frag; |
43cd72b9 BW |
6589 | bfd_boolean is_jump = FALSE; |
6590 | bfd_boolean is_branch = FALSE; | |
6591 | xtensa_isa isa = xtensa_default_isa; | |
6592 | int i; | |
6593 | int insn_size; | |
6594 | int extra_space; | |
6595 | char *f = NULL; | |
6596 | int slot; | |
7c430684 BW |
6597 | unsigned current_line, best_linenum; |
6598 | char *current_file; | |
43cd72b9 | 6599 | |
7c430684 | 6600 | best_linenum = UINT_MAX; |
43cd72b9 BW |
6601 | |
6602 | if (generating_literals) | |
6603 | { | |
6604 | static int reported = 0; | |
6605 | if (reported < 4) | |
6606 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
6607 | _("cannot assemble into a literal fragment")); | |
6608 | if (reported == 3) | |
6609 | as_bad (_("...")); | |
6610 | reported++; | |
6611 | return; | |
6612 | } | |
6613 | ||
6614 | if (frag_now_fix () != 0 | |
b08b5071 | 6615 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 6616 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
b08b5071 | 6617 | || !use_transform () != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
6618 | || (directive_state[directive_longcalls] |
6619 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
6620 | || (directive_state[directive_absolute_literals] |
6621 | != frag_now->tc_frag_data.use_absolute_literals))) | |
6622 | { | |
6623 | frag_wane (frag_now); | |
6624 | frag_new (0); | |
6625 | xtensa_set_frag_assembly_state (frag_now); | |
6626 | } | |
6627 | ||
6628 | if (workaround_a0_b_retw | |
6629 | && vinsn->num_slots == 1 | |
6630 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
6631 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
6632 | && use_transform ()) | |
6633 | { | |
6634 | has_a0_b_retw = TRUE; | |
6635 | ||
6636 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
6637 | After the first assembly pass we will check all of them and | |
6638 | add a nop if needed. */ | |
6639 | frag_now->tc_frag_data.is_insn = TRUE; | |
6640 | frag_var (rs_machine_dependent, 4, 4, | |
6641 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6642 | frag_now->fr_symbol, | |
6643 | frag_now->fr_offset, | |
6644 | NULL); | |
6645 | xtensa_set_frag_assembly_state (frag_now); | |
6646 | frag_now->tc_frag_data.is_insn = TRUE; | |
6647 | frag_var (rs_machine_dependent, 4, 4, | |
6648 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6649 | frag_now->fr_symbol, | |
6650 | frag_now->fr_offset, | |
6651 | NULL); | |
6652 | xtensa_set_frag_assembly_state (frag_now); | |
6653 | } | |
6654 | ||
6655 | for (i = 0; i < vinsn->num_slots; i++) | |
6656 | { | |
6657 | /* See if the instruction implies an aligned section. */ | |
6658 | if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1) | |
6659 | record_alignment (now_seg, 2); | |
c138bc38 | 6660 | |
43cd72b9 | 6661 | /* Also determine the best line number for debug info. */ |
7c430684 BW |
6662 | best_linenum = vinsn->slots[i].linenum < best_linenum |
6663 | ? vinsn->slots[i].linenum : best_linenum; | |
43cd72b9 BW |
6664 | } |
6665 | ||
6666 | /* Special cases for instructions that force an alignment... */ | |
6667 | /* None of these opcodes are bundle-able. */ | |
6668 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
6669 | { | |
d77b99c9 | 6670 | int max_fill; |
c138bc38 | 6671 | |
05d58145 BW |
6672 | /* Remember the symbol that marks the end of the loop in the frag |
6673 | that marks the start of the loop. This way we can easily find | |
6674 | the end of the loop at the beginning, without adding special code | |
6675 | to mark the loop instructions themselves. */ | |
6676 | symbolS *target_sym = NULL; | |
6677 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
6678 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
6679 | ||
43cd72b9 BW |
6680 | xtensa_set_frag_assembly_state (frag_now); |
6681 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 6682 | |
43cd72b9 BW |
6683 | max_fill = get_text_align_max_fill_size |
6684 | (get_text_align_power (xtensa_fetch_width), | |
6685 | TRUE, frag_now->tc_frag_data.is_no_density); | |
6686 | ||
6687 | if (use_transform ()) | |
6688 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 6689 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6690 | else |
c138bc38 | 6691 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 6692 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6693 | xtensa_set_frag_assembly_state (frag_now); |
c138bc38 | 6694 | |
43cd72b9 BW |
6695 | xtensa_move_labels (frag_now, 0, FALSE); |
6696 | } | |
6697 | ||
b08b5071 | 6698 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
6699 | && !vinsn->slots[0].is_specific_opcode) |
6700 | { | |
6701 | xtensa_mark_literal_pool_location (); | |
6702 | xtensa_move_labels (frag_now, 0, TRUE); | |
6703 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); | |
6704 | } | |
6705 | ||
6706 | if (vinsn->num_slots == 1) | |
6707 | { | |
6708 | if (workaround_a0_b_retw && use_transform ()) | |
6709 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
6710 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
6711 | ||
6712 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
6713 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
6714 | } | |
6715 | else | |
6716 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
6717 | ||
6718 | insn_size = xtensa_format_length (isa, vinsn->format); | |
6719 | ||
e7da6241 | 6720 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
6721 | |
6722 | /* vinsn_to_insnbuf will produce the error. */ | |
6723 | if (vinsn->format != XTENSA_UNDEFINED) | |
6724 | { | |
d77b99c9 | 6725 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
6726 | xtensa_set_frag_assembly_state (frag_now); |
6727 | frag_now->tc_frag_data.is_insn = TRUE; | |
6728 | } | |
6729 | ||
e7da6241 | 6730 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
6731 | if (vinsn->format == XTENSA_UNDEFINED) |
6732 | return; | |
6733 | ||
d77b99c9 | 6734 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 6735 | |
7c430684 BW |
6736 | /* Temporarily set the logical line number to the one we want to appear |
6737 | in the debug information. */ | |
6738 | as_where (¤t_file, ¤t_line); | |
6739 | new_logical_line (current_file, best_linenum); | |
6740 | dwarf2_emit_insn (insn_size + extra_space); | |
6741 | new_logical_line (current_file, current_line); | |
43cd72b9 BW |
6742 | |
6743 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6744 | { | |
6745 | TInsn *tinsn = &vinsn->slots[slot]; | |
6746 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; | |
7c834684 | 6747 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 6748 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 BW |
6749 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
6750 | if (tinsn->literal_space != 0) | |
6751 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
6752 | ||
6753 | if (tinsn->subtype == RELAX_NARROW) | |
6754 | assert (vinsn->num_slots == 1); | |
6755 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) | |
6756 | is_jump = TRUE; | |
6757 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
6758 | is_branch = TRUE; | |
6759 | ||
e7da6241 BW |
6760 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
6761 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
6762 | finish_frag = TRUE; |
6763 | } | |
6764 | ||
6765 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 6766 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
6767 | |
6768 | if (finish_frag) | |
6769 | { | |
6770 | frag_variant (rs_machine_dependent, | |
6771 | extra_space, extra_space, RELAX_SLOTS, | |
6772 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
6773 | xtensa_set_frag_assembly_state (frag_now); | |
6774 | } | |
6775 | ||
6776 | /* Special cases for loops: | |
6777 | close_loop_end should be inserted AFTER short_loop. | |
6778 | Make sure that CLOSE loops are processed BEFORE short_loops | |
6779 | when converting them. */ | |
6780 | ||
6781 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 6782 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
6783 | && !vinsn->slots[0].is_specific_opcode) |
6784 | { | |
6785 | if (workaround_short_loop && use_transform ()) | |
6786 | { | |
6787 | maybe_has_short_loop = TRUE; | |
6788 | frag_now->tc_frag_data.is_insn = TRUE; | |
6789 | frag_var (rs_machine_dependent, 4, 4, | |
6790 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6791 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6792 | frag_now->tc_frag_data.is_insn = TRUE; | |
6793 | frag_var (rs_machine_dependent, 4, 4, | |
6794 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6795 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6796 | } | |
6797 | ||
6798 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
6799 | loop at least 12 bytes away from another loop's end. */ | |
6800 | if (workaround_close_loop_end && use_transform ()) | |
6801 | { | |
6802 | maybe_has_close_loop_end = TRUE; | |
6803 | frag_now->tc_frag_data.is_insn = TRUE; | |
6804 | frag_var (rs_machine_dependent, 12, 12, | |
6805 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
6806 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6807 | } | |
6808 | } | |
6809 | ||
6810 | if (use_transform ()) | |
6811 | { | |
6812 | if (is_jump) | |
6813 | { | |
6814 | assert (finish_frag); | |
6815 | frag_var (rs_machine_dependent, | |
6816 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6817 | RELAX_UNREACHABLE, | |
6818 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6819 | xtensa_set_frag_assembly_state (frag_now); | |
6820 | } | |
7b1cc377 | 6821 | else if (is_branch && do_align_targets ()) |
43cd72b9 BW |
6822 | { |
6823 | assert (finish_frag); | |
6824 | frag_var (rs_machine_dependent, | |
6825 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6826 | RELAX_MAYBE_UNREACHABLE, | |
6827 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6828 | xtensa_set_frag_assembly_state (frag_now); | |
6829 | frag_var (rs_machine_dependent, | |
6830 | 0, 0, | |
6831 | RELAX_MAYBE_DESIRE_ALIGN, | |
6832 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6833 | xtensa_set_frag_assembly_state (frag_now); | |
6834 | } | |
6835 | } | |
6836 | ||
6837 | /* Now, if the original opcode was a call... */ | |
6838 | if (do_align_targets () | |
6839 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
6840 | { | |
b08b5071 | 6841 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
6842 | frag_now->tc_frag_data.is_insn = TRUE; |
6843 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
6844 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6845 | xtensa_set_frag_assembly_state (frag_now); | |
6846 | } | |
6847 | ||
6848 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
6849 | { | |
6850 | frag_wane (frag_now); | |
6851 | frag_new (0); | |
6852 | xtensa_set_frag_assembly_state (frag_now); | |
6853 | } | |
6854 | } | |
6855 | ||
6856 | \f | |
7fa3d080 BW |
6857 | /* xtensa_end and helper functions. */ |
6858 | ||
6859 | static void xtensa_cleanup_align_frags (void); | |
6860 | static void xtensa_fix_target_frags (void); | |
6861 | static void xtensa_mark_narrow_branches (void); | |
6862 | static void xtensa_mark_zcl_first_insns (void); | |
6863 | static void xtensa_fix_a0_b_retw_frags (void); | |
6864 | static void xtensa_fix_b_j_loop_end_frags (void); | |
6865 | static void xtensa_fix_close_loop_end_frags (void); | |
6866 | static void xtensa_fix_short_loop_frags (void); | |
6867 | static void xtensa_sanity_check (void); | |
2caa7ca0 | 6868 | static void xtensa_add_config_info (void); |
7fa3d080 | 6869 | |
43cd72b9 | 6870 | void |
7fa3d080 | 6871 | xtensa_end (void) |
43cd72b9 BW |
6872 | { |
6873 | directive_balance (); | |
6874 | xtensa_flush_pending_output (); | |
6875 | ||
6876 | past_xtensa_end = TRUE; | |
6877 | ||
6878 | xtensa_move_literals (); | |
6879 | ||
6880 | xtensa_reorder_segments (); | |
6881 | xtensa_cleanup_align_frags (); | |
6882 | xtensa_fix_target_frags (); | |
6883 | if (workaround_a0_b_retw && has_a0_b_retw) | |
6884 | xtensa_fix_a0_b_retw_frags (); | |
6885 | if (workaround_b_j_loop_end) | |
6886 | xtensa_fix_b_j_loop_end_frags (); | |
6887 | ||
6888 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
6889 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
6890 | xtensa_fix_close_loop_end_frags (); | |
6891 | ||
6892 | if (workaround_short_loop && maybe_has_short_loop) | |
6893 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
6894 | if (align_targets) |
6895 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
6896 | xtensa_mark_zcl_first_insns (); |
6897 | ||
6898 | xtensa_sanity_check (); | |
2caa7ca0 BW |
6899 | |
6900 | xtensa_add_config_info (); | |
43cd72b9 BW |
6901 | } |
6902 | ||
6903 | ||
6904 | static void | |
7fa3d080 | 6905 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
6906 | { |
6907 | frchainS *frchP; | |
c9049d30 | 6908 | asection *s; |
43cd72b9 | 6909 | |
c9049d30 AM |
6910 | for (s = stdoutput->sections; s; s = s->next) |
6911 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
6912 | { | |
6913 | fragS *fragP; | |
6914 | /* Walk over all of the fragments in a subsection. */ | |
6915 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
6916 | { | |
6917 | if ((fragP->fr_type == rs_align | |
6918 | || fragP->fr_type == rs_align_code | |
6919 | || (fragP->fr_type == rs_machine_dependent | |
6920 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
6921 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
6922 | && fragP->fr_fix == 0) | |
6923 | { | |
6924 | fragS *next = fragP->fr_next; | |
6925 | ||
6926 | while (next | |
6927 | && next->fr_fix == 0 | |
6928 | && next->fr_type == rs_machine_dependent | |
6929 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
6930 | { | |
6931 | frag_wane (next); | |
6932 | next = next->fr_next; | |
6933 | } | |
6934 | } | |
6935 | /* If we don't widen branch targets, then they | |
6936 | will be easier to align. */ | |
6937 | if (fragP->tc_frag_data.is_branch_target | |
6938 | && fragP->fr_opcode == fragP->fr_literal | |
6939 | && fragP->fr_type == rs_machine_dependent | |
6940 | && fragP->fr_subtype == RELAX_SLOTS | |
6941 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
6942 | frag_wane (fragP); | |
6943 | if (fragP->fr_type == rs_machine_dependent | |
6944 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
6945 | fragP->tc_frag_data.is_unreachable = TRUE; | |
6946 | } | |
6947 | } | |
43cd72b9 BW |
6948 | } |
6949 | ||
6950 | ||
6951 | /* Re-process all of the fragments looking to convert all of the | |
6952 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
6953 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 6954 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 6955 | |
43cd72b9 | 6956 | static void |
7fa3d080 | 6957 | xtensa_fix_target_frags (void) |
e0001a05 NC |
6958 | { |
6959 | frchainS *frchP; | |
c9049d30 | 6960 | asection *s; |
e0001a05 NC |
6961 | |
6962 | /* When this routine is called, all of the subsections are still intact | |
6963 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
6964 | for (s = stdoutput->sections; s; s = s->next) |
6965 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
6966 | { | |
6967 | fragS *fragP; | |
e0001a05 | 6968 | |
c9049d30 AM |
6969 | /* Walk over all of the fragments in a subsection. */ |
6970 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
6971 | { | |
6972 | if (fragP->fr_type == rs_machine_dependent | |
6973 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
6974 | { | |
6975 | if (next_frag_is_branch_target (fragP)) | |
6976 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
6977 | else | |
6978 | frag_wane (fragP); | |
6979 | } | |
6980 | } | |
6981 | } | |
e0001a05 NC |
6982 | } |
6983 | ||
6984 | ||
7fa3d080 BW |
6985 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
6986 | ||
43cd72b9 | 6987 | static void |
7fa3d080 | 6988 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
6989 | { |
6990 | frchainS *frchP; | |
c9049d30 | 6991 | asection *s; |
43cd72b9 | 6992 | |
c9049d30 AM |
6993 | for (s = stdoutput->sections; s; s = s->next) |
6994 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
6995 | { | |
6996 | fragS *fragP; | |
6997 | /* Walk over all of the fragments in a subsection. */ | |
6998 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
6999 | { | |
7000 | if (fragP->fr_type == rs_machine_dependent | |
7001 | && fragP->fr_subtype == RELAX_SLOTS | |
7002 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
7003 | { | |
7004 | vliw_insn vinsn; | |
7005 | ||
7006 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
7007 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
7008 | ||
7009 | if (vinsn.num_slots == 1 | |
7010 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 7011 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
7012 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
7013 | && is_narrow_branch_guaranteed_in_range (fragP, | |
7014 | &vinsn.slots[0])) | |
7015 | { | |
7016 | fragP->fr_subtype = RELAX_SLOTS; | |
7017 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
7018 | fragP->tc_frag_data.is_aligning_branch = 1; | |
7019 | } | |
7020 | } | |
7021 | } | |
7022 | } | |
43cd72b9 BW |
7023 | } |
7024 | ||
7025 | ||
7026 | /* A branch is typically widened only when its target is out of | |
7027 | range. However, we would like to widen them to align a subsequent | |
7028 | branch target when possible. | |
7029 | ||
7030 | Because the branch relaxation code is so convoluted, the optimal solution | |
7031 | (combining the two cases) is difficult to get right in all circumstances. | |
7032 | We therefore go with an "almost as good" solution, where we only | |
7033 | use for alignment narrow branches that definitely will not expand to a | |
7034 | jump and a branch. These functions find and mark these cases. */ | |
7035 | ||
a67517f4 BW |
7036 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
7037 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
7038 | We start counting beginning with the frag after the 2-byte branch, so the | |
7039 | maximum offset is (4 - 2) + 63 = 65. */ | |
7040 | #define MAX_IMMED6 65 | |
43cd72b9 | 7041 | |
d77b99c9 | 7042 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 7043 | |
43cd72b9 | 7044 | static bfd_boolean |
7fa3d080 | 7045 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 BW |
7046 | { |
7047 | const expressionS *expr = &tinsn->tok[1]; | |
7048 | symbolS *symbolP = expr->X_add_symbol; | |
d77b99c9 | 7049 | offsetT max_distance = expr->X_add_number; |
e7da6241 BW |
7050 | fragS *target_frag; |
7051 | ||
7052 | if (expr->X_op != O_symbol) | |
7053 | return FALSE; | |
7054 | ||
7055 | target_frag = symbol_get_frag (symbolP); | |
7056 | ||
43cd72b9 BW |
7057 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
7058 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
7059 | return FALSE; | |
7060 | ||
7061 | /* The branch doesn't branch over it's own frag, | |
7062 | but over the subsequent ones. */ | |
7063 | fragP = fragP->fr_next; | |
7064 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
7065 | { | |
7066 | max_distance += unrelaxed_frag_max_size (fragP); | |
7067 | fragP = fragP->fr_next; | |
7068 | } | |
7069 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
7070 | return TRUE; | |
e0001a05 NC |
7071 | return FALSE; |
7072 | } | |
7073 | ||
7074 | ||
43cd72b9 | 7075 | static void |
7fa3d080 | 7076 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
7077 | { |
7078 | frchainS *frchP; | |
c9049d30 | 7079 | asection *s; |
43cd72b9 | 7080 | |
c9049d30 AM |
7081 | for (s = stdoutput->sections; s; s = s->next) |
7082 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7083 | { | |
7084 | fragS *fragP; | |
7085 | /* Walk over all of the fragments in a subsection. */ | |
7086 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7087 | { | |
7088 | if (fragP->fr_type == rs_machine_dependent | |
7089 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
7090 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
7091 | { | |
7092 | /* Find the loop frag. */ | |
7093 | fragS *targ_frag = next_non_empty_frag (fragP); | |
7094 | /* Find the first insn frag. */ | |
7095 | targ_frag = next_non_empty_frag (targ_frag); | |
7096 | ||
7097 | /* Of course, sometimes (mostly for toy test cases) a | |
7098 | zero-cost loop instruction is the last in a section. */ | |
7099 | if (targ_frag) | |
7100 | { | |
7101 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
7102 | /* Do not widen a frag that is the first instruction of a | |
7103 | zero-cost loop. It makes that loop harder to align. */ | |
7104 | if (targ_frag->fr_type == rs_machine_dependent | |
7105 | && targ_frag->fr_subtype == RELAX_SLOTS | |
7106 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
7107 | == RELAX_NARROW)) | |
7108 | { | |
7109 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
7110 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
7111 | else | |
7112 | { | |
7113 | frag_wane (targ_frag); | |
7114 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
7115 | } | |
7116 | } | |
7117 | } | |
7118 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
7119 | frag_wane (fragP); | |
7120 | } | |
7121 | } | |
7122 | } | |
43cd72b9 BW |
7123 | } |
7124 | ||
7125 | ||
e0001a05 NC |
7126 | /* Re-process all of the fragments looking to convert all of the |
7127 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
7128 | conditional branch or a retw/retw.n, convert this frag to one that | |
7129 | will generate a NOP. In any case close it off with a .fill 0. */ | |
7130 | ||
7fa3d080 BW |
7131 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
7132 | ||
e0001a05 | 7133 | static void |
7fa3d080 | 7134 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
7135 | { |
7136 | frchainS *frchP; | |
c9049d30 | 7137 | asection *s; |
e0001a05 NC |
7138 | |
7139 | /* When this routine is called, all of the subsections are still intact | |
7140 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7141 | for (s = stdoutput->sections; s; s = s->next) |
7142 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7143 | { | |
7144 | fragS *fragP; | |
e0001a05 | 7145 | |
c9049d30 AM |
7146 | /* Walk over all of the fragments in a subsection. */ |
7147 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7148 | { | |
7149 | if (fragP->fr_type == rs_machine_dependent | |
7150 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
7151 | { | |
7152 | if (next_instrs_are_b_retw (fragP)) | |
7153 | { | |
7154 | if (fragP->tc_frag_data.is_no_transform) | |
7155 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
7156 | else | |
7157 | relax_frag_add_nop (fragP); | |
7158 | } | |
7159 | frag_wane (fragP); | |
7160 | } | |
7161 | } | |
7162 | } | |
e0001a05 NC |
7163 | } |
7164 | ||
7165 | ||
7fa3d080 BW |
7166 | static bfd_boolean |
7167 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
7168 | { |
7169 | xtensa_opcode opcode; | |
43cd72b9 | 7170 | xtensa_format fmt; |
e0001a05 NC |
7171 | const fragS *next_fragP = next_non_empty_frag (fragP); |
7172 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 7173 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
7174 | xtensa_isa isa = xtensa_default_isa; |
7175 | int offset = 0; | |
43cd72b9 BW |
7176 | int slot; |
7177 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
7178 | |
7179 | if (!insnbuf) | |
43cd72b9 BW |
7180 | { |
7181 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7182 | slotbuf = xtensa_insnbuf_alloc (isa); | |
7183 | } | |
e0001a05 NC |
7184 | |
7185 | if (next_fragP == NULL) | |
7186 | return FALSE; | |
7187 | ||
7188 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
7189 | xtensa_insnbuf_from_chars |
7190 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7191 | fmt = xtensa_format_decode (isa, insnbuf); |
7192 | if (fmt == XTENSA_UNDEFINED) | |
7193 | return FALSE; | |
7194 | ||
7195 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
7196 | { | |
7197 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
7198 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
7199 | ||
7200 | branch_seen = (branch_seen | |
7201 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
7202 | } | |
e0001a05 | 7203 | |
43cd72b9 | 7204 | if (!branch_seen) |
e0001a05 NC |
7205 | return FALSE; |
7206 | ||
43cd72b9 | 7207 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7208 | if (offset == next_fragP->fr_fix) |
7209 | { | |
7210 | next_fragP = next_non_empty_frag (next_fragP); | |
7211 | offset = 0; | |
7212 | } | |
43cd72b9 | 7213 | |
e0001a05 NC |
7214 | if (next_fragP == NULL) |
7215 | return FALSE; | |
7216 | ||
7217 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
7218 | xtensa_insnbuf_from_chars |
7219 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7220 | fmt = xtensa_format_decode (isa, insnbuf); |
7221 | ||
7222 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
7223 | have no problems. */ | |
7224 | if (fmt == XTENSA_UNDEFINED | |
7225 | || xtensa_format_num_slots (isa, fmt) != 1) | |
7226 | return FALSE; | |
7227 | ||
7228 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
7229 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 7230 | |
b08b5071 | 7231 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 7232 | return TRUE; |
43cd72b9 | 7233 | |
e0001a05 NC |
7234 | return FALSE; |
7235 | } | |
7236 | ||
7237 | ||
7238 | /* Re-process all of the fragments looking to convert all of the | |
7239 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
7240 | loop end label, convert this frag to one that will generate a NOP. | |
7241 | In any case close it off with a .fill 0. */ | |
7242 | ||
7fa3d080 BW |
7243 | static bfd_boolean next_instr_is_loop_end (fragS *); |
7244 | ||
e0001a05 | 7245 | static void |
7fa3d080 | 7246 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
7247 | { |
7248 | frchainS *frchP; | |
c9049d30 | 7249 | asection *s; |
e0001a05 NC |
7250 | |
7251 | /* When this routine is called, all of the subsections are still intact | |
7252 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7253 | for (s = stdoutput->sections; s; s = s->next) |
7254 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7255 | { | |
7256 | fragS *fragP; | |
e0001a05 | 7257 | |
c9049d30 AM |
7258 | /* Walk over all of the fragments in a subsection. */ |
7259 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7260 | { | |
7261 | if (fragP->fr_type == rs_machine_dependent | |
7262 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
7263 | { | |
7264 | if (next_instr_is_loop_end (fragP)) | |
7265 | { | |
7266 | if (fragP->tc_frag_data.is_no_transform) | |
7267 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
7268 | else | |
7269 | relax_frag_add_nop (fragP); | |
7270 | } | |
7271 | frag_wane (fragP); | |
7272 | } | |
7273 | } | |
7274 | } | |
e0001a05 NC |
7275 | } |
7276 | ||
7277 | ||
7fa3d080 BW |
7278 | static bfd_boolean |
7279 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
7280 | { |
7281 | const fragS *next_fragP; | |
7282 | ||
7283 | if (next_frag_is_loop_target (fragP)) | |
7284 | return FALSE; | |
7285 | ||
7286 | next_fragP = next_non_empty_frag (fragP); | |
7287 | if (next_fragP == NULL) | |
7288 | return FALSE; | |
7289 | ||
7290 | if (!next_frag_is_loop_target (next_fragP)) | |
7291 | return FALSE; | |
7292 | ||
7293 | /* If the size is >= 3 then there is more than one instruction here. | |
7294 | The hardware bug will not fire. */ | |
7295 | if (next_fragP->fr_fix > 3) | |
7296 | return FALSE; | |
7297 | ||
7298 | return TRUE; | |
7299 | } | |
7300 | ||
7301 | ||
7302 | /* Re-process all of the fragments looking to convert all of the | |
7303 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
7304 | not MY loop's loop end within 12 bytes, add enough nops here to | |
7305 | make it at least 12 bytes away. In any case close it off with a | |
7306 | .fill 0. */ | |
7307 | ||
d77b99c9 | 7308 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 7309 | (fragS *, fragS *, offsetT); |
7fa3d080 | 7310 | |
e0001a05 | 7311 | static void |
7fa3d080 | 7312 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
7313 | { |
7314 | frchainS *frchP; | |
c9049d30 | 7315 | asection *s; |
e0001a05 NC |
7316 | |
7317 | /* When this routine is called, all of the subsections are still intact | |
7318 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7319 | for (s = stdoutput->sections; s; s = s->next) |
7320 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7321 | { | |
7322 | fragS *fragP; | |
e0001a05 | 7323 | |
c9049d30 | 7324 | fragS *current_target = NULL; |
e0001a05 | 7325 | |
c9049d30 AM |
7326 | /* Walk over all of the fragments in a subsection. */ |
7327 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7328 | { | |
7329 | if (fragP->fr_type == rs_machine_dependent | |
7330 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7331 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 7332 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 7333 | |
c9049d30 AM |
7334 | if (current_target |
7335 | && fragP->fr_type == rs_machine_dependent | |
7336 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
7337 | { | |
7338 | offsetT min_bytes; | |
7339 | int bytes_added = 0; | |
e0001a05 NC |
7340 | |
7341 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
7342 | /* Max out at 12. */ |
7343 | min_bytes = min_bytes_to_other_loop_end | |
7344 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
7345 | ||
7346 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
7347 | { | |
7348 | if (fragP->tc_frag_data.is_no_transform) | |
7349 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
7350 | else | |
7351 | { | |
7352 | while (min_bytes + bytes_added | |
7353 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
7354 | { | |
7355 | int length = 3; | |
7356 | ||
7357 | if (fragP->fr_var < length) | |
7358 | as_fatal (_("fr_var %lu < length %d"), | |
7359 | (long) fragP->fr_var, length); | |
7360 | else | |
7361 | { | |
7362 | assemble_nop (length, | |
7363 | fragP->fr_literal + fragP->fr_fix); | |
7364 | fragP->fr_fix += length; | |
7365 | fragP->fr_var -= length; | |
7366 | } | |
7367 | bytes_added += length; | |
7368 | } | |
7369 | } | |
7370 | } | |
7371 | frag_wane (fragP); | |
7372 | } | |
7373 | assert (fragP->fr_type != rs_machine_dependent | |
7374 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); | |
7375 | } | |
7376 | } | |
e0001a05 NC |
7377 | } |
7378 | ||
7379 | ||
d77b99c9 | 7380 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 7381 | |
d77b99c9 | 7382 | static offsetT |
7fa3d080 BW |
7383 | min_bytes_to_other_loop_end (fragS *fragP, |
7384 | fragS *current_target, | |
d77b99c9 | 7385 | offsetT max_size) |
e0001a05 | 7386 | { |
d77b99c9 | 7387 | offsetT offset = 0; |
e0001a05 NC |
7388 | fragS *current_fragP; |
7389 | ||
7390 | for (current_fragP = fragP; | |
7391 | current_fragP; | |
7392 | current_fragP = current_fragP->fr_next) | |
7393 | { | |
7394 | if (current_fragP->tc_frag_data.is_loop_target | |
7395 | && current_fragP != current_target) | |
05d58145 | 7396 | return offset; |
e0001a05 NC |
7397 | |
7398 | offset += unrelaxed_frag_min_size (current_fragP); | |
7399 | ||
05d58145 | 7400 | if (offset >= max_size) |
e0001a05 NC |
7401 | return max_size; |
7402 | } | |
7403 | return max_size; | |
7404 | } | |
7405 | ||
7406 | ||
d77b99c9 | 7407 | static offsetT |
7fa3d080 | 7408 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 7409 | { |
d77b99c9 | 7410 | offsetT size = fragP->fr_fix; |
e0001a05 | 7411 | |
d77b99c9 | 7412 | /* Add fill size. */ |
e0001a05 NC |
7413 | if (fragP->fr_type == rs_fill) |
7414 | size += fragP->fr_offset; | |
7415 | ||
7416 | return size; | |
7417 | } | |
7418 | ||
7419 | ||
d77b99c9 | 7420 | static offsetT |
7fa3d080 | 7421 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 7422 | { |
d77b99c9 | 7423 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
7424 | switch (fragP->fr_type) |
7425 | { | |
7426 | case 0: | |
c138bc38 | 7427 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
7428 | end up with type 0. */ |
7429 | break; | |
7430 | case rs_fill: | |
7431 | case rs_org: | |
7432 | case rs_space: | |
7433 | size += fragP->fr_offset; | |
7434 | break; | |
7435 | case rs_align: | |
7436 | case rs_align_code: | |
7437 | case rs_align_test: | |
7438 | case rs_leb128: | |
7439 | case rs_cfa: | |
7440 | case rs_dwarf2dbg: | |
7441 | /* No further adjustments needed. */ | |
7442 | break; | |
7443 | case rs_machine_dependent: | |
7444 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
7445 | size += fragP->fr_var; | |
7446 | break; | |
7447 | default: | |
7448 | /* We had darn well better know how big it is. */ | |
7449 | assert (0); | |
7450 | break; | |
7451 | } | |
7452 | ||
7453 | return size; | |
7454 | } | |
7455 | ||
7456 | ||
e0001a05 NC |
7457 | /* Re-process all of the fragments looking to convert all |
7458 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
7459 | ||
7460 | A) | |
7461 | 1) the instruction size count to the loop end label | |
7462 | is too short (<= 2 instructions), | |
7463 | 2) loop has a jump or branch in it | |
7464 | ||
7465 | or B) | |
43cd72b9 | 7466 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
7467 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
7468 | 3) the instruction size count to the loop end label is too short | |
7469 | (<= 2 instructions) | |
7470 | then convert this frag (and maybe the next one) to generate a NOP. | |
7471 | In any case close it off with a .fill 0. */ | |
7472 | ||
d77b99c9 | 7473 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
7474 | static bfd_boolean branch_before_loop_end (fragS *); |
7475 | ||
e0001a05 | 7476 | static void |
7fa3d080 | 7477 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
7478 | { |
7479 | frchainS *frchP; | |
c9049d30 | 7480 | asection *s; |
e0001a05 NC |
7481 | |
7482 | /* When this routine is called, all of the subsections are still intact | |
7483 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7484 | for (s = stdoutput->sections; s; s = s->next) |
7485 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7486 | { | |
7487 | fragS *fragP; | |
7488 | fragS *current_target = NULL; | |
7489 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; | |
e0001a05 | 7490 | |
c9049d30 AM |
7491 | /* Walk over all of the fragments in a subsection. */ |
7492 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7493 | { | |
7494 | if (fragP->fr_type == rs_machine_dependent | |
7495 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7496 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
7497 | { | |
7498 | TInsn t_insn; | |
7499 | fragS *loop_frag = next_non_empty_frag (fragP); | |
7500 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
7501 | current_target = symbol_get_frag (fragP->fr_symbol); | |
7502 | current_opcode = t_insn.opcode; | |
7503 | assert (xtensa_opcode_is_loop (xtensa_default_isa, | |
64b607e6 | 7504 | current_opcode) == 1); |
c9049d30 | 7505 | } |
e0001a05 | 7506 | |
c9049d30 AM |
7507 | if (fragP->fr_type == rs_machine_dependent |
7508 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7509 | { | |
7510 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 | |
7511 | && (branch_before_loop_end (fragP->fr_next) | |
7512 | || (workaround_all_short_loops | |
7513 | && current_opcode != XTENSA_UNDEFINED | |
7514 | && current_opcode != xtensa_loop_opcode))) | |
7515 | { | |
7516 | if (fragP->tc_frag_data.is_no_transform) | |
7517 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
7518 | else | |
7519 | relax_frag_add_nop (fragP); | |
7520 | } | |
7521 | frag_wane (fragP); | |
7522 | } | |
7523 | } | |
7524 | } | |
e0001a05 NC |
7525 | } |
7526 | ||
7527 | ||
d77b99c9 | 7528 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 7529 | |
d77b99c9 | 7530 | static int |
7fa3d080 BW |
7531 | count_insns_to_loop_end (fragS *base_fragP, |
7532 | bfd_boolean count_relax_add, | |
d77b99c9 | 7533 | int max_count) |
e0001a05 NC |
7534 | { |
7535 | fragS *fragP = NULL; | |
d77b99c9 | 7536 | int insn_count = 0; |
e0001a05 NC |
7537 | |
7538 | fragP = base_fragP; | |
7539 | ||
7540 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
7541 | { | |
7542 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
7543 | if (insn_count >= max_count) | |
7544 | return max_count; | |
7545 | ||
7546 | if (count_relax_add) | |
7547 | { | |
7548 | if (fragP->fr_type == rs_machine_dependent | |
7549 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7550 | { | |
7551 | /* In order to add the appropriate number of | |
7552 | NOPs, we count an instruction for downstream | |
7553 | occurrences. */ | |
7554 | insn_count++; | |
7555 | if (insn_count >= max_count) | |
7556 | return max_count; | |
7557 | } | |
7558 | } | |
7559 | } | |
7560 | return insn_count; | |
7561 | } | |
7562 | ||
7563 | ||
d77b99c9 | 7564 | static int |
7fa3d080 | 7565 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 7566 | { |
43cd72b9 BW |
7567 | xtensa_isa isa = xtensa_default_isa; |
7568 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 7569 | int insn_count = 0; |
e0001a05 NC |
7570 | int offset = 0; |
7571 | ||
7572 | if (!fragP->tc_frag_data.is_insn) | |
7573 | return insn_count; | |
7574 | ||
43cd72b9 BW |
7575 | if (!insnbuf) |
7576 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7577 | ||
e0001a05 NC |
7578 | /* Decode the fixed instructions. */ |
7579 | while (offset < fragP->fr_fix) | |
7580 | { | |
43cd72b9 BW |
7581 | xtensa_format fmt; |
7582 | ||
d77b99c9 BW |
7583 | xtensa_insnbuf_from_chars |
7584 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7585 | fmt = xtensa_format_decode (isa, insnbuf); |
7586 | ||
7587 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
7588 | { |
7589 | as_fatal (_("undecodable instruction in instruction frag")); | |
7590 | return insn_count; | |
7591 | } | |
43cd72b9 | 7592 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7593 | insn_count++; |
7594 | } | |
7595 | ||
7596 | return insn_count; | |
7597 | } | |
7598 | ||
7599 | ||
7fa3d080 BW |
7600 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
7601 | ||
43cd72b9 | 7602 | static bfd_boolean |
7fa3d080 | 7603 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
7604 | { |
7605 | fragS *fragP; | |
7606 | ||
7607 | for (fragP = base_fragP; | |
7608 | fragP && !fragP->tc_frag_data.is_loop_target; | |
7609 | fragP = fragP->fr_next) | |
7610 | { | |
7611 | if (unrelaxed_frag_has_b_j (fragP)) | |
7612 | return TRUE; | |
7613 | } | |
7614 | return FALSE; | |
7615 | } | |
7616 | ||
7617 | ||
43cd72b9 | 7618 | static bfd_boolean |
7fa3d080 | 7619 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 7620 | { |
43cd72b9 BW |
7621 | static xtensa_insnbuf insnbuf = NULL; |
7622 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
7623 | int offset = 0; |
7624 | ||
7625 | if (!fragP->tc_frag_data.is_insn) | |
7626 | return FALSE; | |
7627 | ||
43cd72b9 BW |
7628 | if (!insnbuf) |
7629 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7630 | ||
e0001a05 NC |
7631 | /* Decode the fixed instructions. */ |
7632 | while (offset < fragP->fr_fix) | |
7633 | { | |
43cd72b9 BW |
7634 | xtensa_format fmt; |
7635 | int slot; | |
7636 | ||
d77b99c9 BW |
7637 | xtensa_insnbuf_from_chars |
7638 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7639 | fmt = xtensa_format_decode (isa, insnbuf); |
7640 | if (fmt == XTENSA_UNDEFINED) | |
7641 | return FALSE; | |
7642 | ||
7643 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 7644 | { |
43cd72b9 BW |
7645 | xtensa_opcode opcode = |
7646 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
7647 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
7648 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
7649 | return TRUE; | |
e0001a05 | 7650 | } |
43cd72b9 | 7651 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7652 | } |
7653 | return FALSE; | |
7654 | } | |
7655 | ||
7656 | ||
7657 | /* Checks to be made after initial assembly but before relaxation. */ | |
7658 | ||
7fa3d080 BW |
7659 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
7660 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
7661 | ||
e0001a05 | 7662 | static void |
7fa3d080 | 7663 | xtensa_sanity_check (void) |
e0001a05 NC |
7664 | { |
7665 | char *file_name; | |
d77b99c9 | 7666 | unsigned line; |
e0001a05 | 7667 | frchainS *frchP; |
c9049d30 | 7668 | asection *s; |
e0001a05 NC |
7669 | |
7670 | as_where (&file_name, &line); | |
c9049d30 AM |
7671 | for (s = stdoutput->sections; s; s = s->next) |
7672 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7673 | { | |
7674 | fragS *fragP; | |
e0001a05 | 7675 | |
c9049d30 AM |
7676 | /* Walk over all of the fragments in a subsection. */ |
7677 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7678 | { | |
c9049d30 | 7679 | if (fragP->fr_type == rs_machine_dependent |
a7284bf1 BW |
7680 | && fragP->fr_subtype == RELAX_SLOTS |
7681 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
c9049d30 AM |
7682 | { |
7683 | static xtensa_insnbuf insnbuf = NULL; | |
7684 | TInsn t_insn; | |
7685 | ||
7686 | if (fragP->fr_opcode != NULL) | |
7687 | { | |
7688 | if (!insnbuf) | |
7689 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7690 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
7691 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
7692 | ||
7693 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
7694 | t_insn.opcode) == 1) | |
7695 | { | |
7696 | if (is_empty_loop (&t_insn, fragP)) | |
7697 | { | |
7698 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7699 | as_bad (_("invalid empty loop")); | |
7700 | } | |
7701 | if (!is_local_forward_loop (&t_insn, fragP)) | |
7702 | { | |
7703 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7704 | as_bad (_("loop target does not follow " | |
7705 | "loop instruction in section")); | |
7706 | } | |
7707 | } | |
7708 | } | |
7709 | } | |
7710 | } | |
7711 | } | |
e0001a05 NC |
7712 | new_logical_line (file_name, line); |
7713 | } | |
7714 | ||
7715 | ||
7716 | #define LOOP_IMMED_OPN 1 | |
7717 | ||
43cd72b9 | 7718 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 7719 | |
7fa3d080 BW |
7720 | static bfd_boolean |
7721 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7722 | { |
7723 | const expressionS *expr; | |
7724 | symbolS *symbolP; | |
7725 | fragS *next_fragP; | |
7726 | ||
7727 | if (insn->insn_type != ITYPE_INSN) | |
7728 | return FALSE; | |
7729 | ||
43cd72b9 | 7730 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7731 | return FALSE; |
7732 | ||
7733 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7734 | return FALSE; | |
7735 | ||
7736 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7737 | ||
7738 | if (expr->X_op != O_symbol) | |
7739 | return FALSE; | |
7740 | ||
7741 | symbolP = expr->X_add_symbol; | |
7742 | if (!symbolP) | |
7743 | return FALSE; | |
7744 | ||
7745 | if (symbol_get_frag (symbolP) == NULL) | |
7746 | return FALSE; | |
7747 | ||
7748 | if (S_GET_VALUE (symbolP) != 0) | |
7749 | return FALSE; | |
7750 | ||
7751 | /* Walk through the zero-size fragments from this one. If we find | |
7752 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 7753 | |
e0001a05 NC |
7754 | for (next_fragP = fragP->fr_next; |
7755 | next_fragP != NULL; | |
7756 | next_fragP = next_fragP->fr_next) | |
7757 | { | |
7758 | if (next_fragP == symbol_get_frag (symbolP)) | |
7759 | return TRUE; | |
7760 | if (next_fragP->fr_fix != 0) | |
7761 | return FALSE; | |
7762 | } | |
7763 | return FALSE; | |
7764 | } | |
7765 | ||
7766 | ||
7fa3d080 BW |
7767 | static bfd_boolean |
7768 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7769 | { |
7770 | const expressionS *expr; | |
7771 | symbolS *symbolP; | |
7772 | fragS *next_fragP; | |
7773 | ||
7774 | if (insn->insn_type != ITYPE_INSN) | |
7775 | return FALSE; | |
7776 | ||
64b607e6 | 7777 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7778 | return FALSE; |
7779 | ||
7780 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7781 | return FALSE; | |
7782 | ||
7783 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7784 | ||
7785 | if (expr->X_op != O_symbol) | |
7786 | return FALSE; | |
7787 | ||
7788 | symbolP = expr->X_add_symbol; | |
7789 | if (!symbolP) | |
7790 | return FALSE; | |
7791 | ||
7792 | if (symbol_get_frag (symbolP) == NULL) | |
7793 | return FALSE; | |
7794 | ||
7795 | /* Walk through fragments until we find the target. | |
7796 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 7797 | |
e0001a05 NC |
7798 | for (next_fragP = fragP->fr_next; |
7799 | next_fragP != NULL; | |
7800 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
7801 | { |
7802 | if (next_fragP == symbol_get_frag (symbolP)) | |
7803 | return TRUE; | |
7804 | } | |
e0001a05 NC |
7805 | |
7806 | return FALSE; | |
7807 | } | |
7808 | ||
2caa7ca0 BW |
7809 | |
7810 | #define XTINFO_NAME "Xtensa_Info" | |
7811 | #define XTINFO_NAMESZ 12 | |
7812 | #define XTINFO_TYPE 1 | |
7813 | ||
7814 | static void | |
7815 | xtensa_add_config_info (void) | |
7816 | { | |
7817 | asection *info_sec; | |
7818 | char *data, *p; | |
7819 | int sz; | |
7820 | ||
7821 | info_sec = subseg_new (".xtensa.info", 0); | |
7822 | bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY); | |
7823 | ||
7824 | data = xmalloc (100); | |
7825 | sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", | |
7826 | XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI); | |
7827 | sz = strlen (data) + 1; | |
7828 | ||
7829 | /* Add enough null terminators to pad to a word boundary. */ | |
7830 | do | |
7831 | data[sz++] = 0; | |
7832 | while ((sz & 3) != 0); | |
7833 | ||
7834 | /* Follow the standard note section layout: | |
7835 | First write the length of the name string. */ | |
7836 | p = frag_more (4); | |
7837 | md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); | |
7838 | ||
7839 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
7840 | p = frag_more (4); | |
7841 | md_number_to_chars (p, (valueT) sz, 4); | |
7842 | ||
7843 | /* Write the note type. */ | |
7844 | p = frag_more (4); | |
7845 | md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); | |
7846 | ||
7847 | /* Write the name field. */ | |
7848 | p = frag_more (XTINFO_NAMESZ); | |
7849 | memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); | |
7850 | ||
7851 | /* Finally, write the descriptor. */ | |
7852 | p = frag_more (sz); | |
7853 | memcpy (p, data, sz); | |
7854 | ||
7855 | free (data); | |
7856 | } | |
7857 | ||
e0001a05 NC |
7858 | \f |
7859 | /* Alignment Functions. */ | |
7860 | ||
d77b99c9 BW |
7861 | static int |
7862 | get_text_align_power (unsigned target_size) | |
e0001a05 | 7863 | { |
03aaa593 BW |
7864 | if (target_size <= 4) |
7865 | return 2; | |
7866 | assert (target_size == 8); | |
7867 | return 3; | |
e0001a05 NC |
7868 | } |
7869 | ||
7870 | ||
d77b99c9 | 7871 | static int |
7fa3d080 BW |
7872 | get_text_align_max_fill_size (int align_pow, |
7873 | bfd_boolean use_nops, | |
7874 | bfd_boolean use_no_density) | |
e0001a05 NC |
7875 | { |
7876 | if (!use_nops) | |
7877 | return (1 << align_pow); | |
7878 | if (use_no_density) | |
7879 | return 3 * (1 << align_pow); | |
7880 | ||
7881 | return 1 + (1 << align_pow); | |
7882 | } | |
7883 | ||
7884 | ||
d77b99c9 BW |
7885 | /* Calculate the minimum bytes of fill needed at "address" to align a |
7886 | target instruction of size "target_size" so that it does not cross a | |
7887 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
7888 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
7889 | be filled by NOP instructions. */ | |
e0001a05 | 7890 | |
d77b99c9 | 7891 | static int |
7fa3d080 BW |
7892 | get_text_align_fill_size (addressT address, |
7893 | int align_pow, | |
7894 | int target_size, | |
7895 | bfd_boolean use_nops, | |
7896 | bfd_boolean use_no_density) | |
e0001a05 | 7897 | { |
d77b99c9 BW |
7898 | addressT alignment, fill, fill_limit, fill_step; |
7899 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 7900 | |
d77b99c9 BW |
7901 | alignment = (1 << align_pow); |
7902 | assert (target_size > 0 && alignment >= (addressT) target_size); | |
c138bc38 | 7903 | |
e0001a05 NC |
7904 | if (!use_nops) |
7905 | { | |
d77b99c9 BW |
7906 | fill_limit = alignment; |
7907 | fill_step = 1; | |
e0001a05 | 7908 | } |
d77b99c9 | 7909 | else if (!use_no_density) |
e0001a05 | 7910 | { |
d77b99c9 BW |
7911 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
7912 | fill_limit = alignment * 2; | |
7913 | fill_step = 1; | |
7914 | skip_one = TRUE; | |
e0001a05 NC |
7915 | } |
7916 | else | |
7917 | { | |
d77b99c9 BW |
7918 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
7919 | fill_limit = alignment * 3; | |
7920 | fill_step = 3; | |
7921 | } | |
e0001a05 | 7922 | |
d77b99c9 BW |
7923 | /* Try all fill sizes until finding one that works. */ |
7924 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
7925 | { | |
7926 | if (skip_one && fill == 1) | |
7927 | continue; | |
7928 | if ((address + fill) >> align_pow | |
7929 | == (address + fill + target_size - 1) >> align_pow) | |
7930 | return fill; | |
e0001a05 NC |
7931 | } |
7932 | assert (0); | |
7933 | return 0; | |
7934 | } | |
7935 | ||
7936 | ||
664df4e4 BW |
7937 | static int |
7938 | branch_align_power (segT sec) | |
7939 | { | |
7940 | /* If the Xtensa processor has a fetch width of 8 bytes, and the section | |
7941 | is aligned to at least an 8-byte boundary, then a branch target need | |
7942 | only fit within an 8-byte aligned block of memory to avoid a stall. | |
7943 | Otherwise, try to fit branch targets within 4-byte aligned blocks | |
7944 | (which may be insufficient, e.g., if the section has no alignment, but | |
7945 | it's good enough). */ | |
7946 | if (xtensa_fetch_width == 8) | |
7947 | { | |
7948 | if (get_recorded_alignment (sec) >= 3) | |
7949 | return 3; | |
7950 | } | |
7951 | else | |
7952 | assert (xtensa_fetch_width == 4); | |
7953 | ||
7954 | return 2; | |
7955 | } | |
7956 | ||
7957 | ||
e0001a05 NC |
7958 | /* This will assert if it is not possible. */ |
7959 | ||
d77b99c9 BW |
7960 | static int |
7961 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 7962 | { |
d77b99c9 BW |
7963 | int count = 0; |
7964 | ||
e0001a05 NC |
7965 | if (use_no_density) |
7966 | { | |
7967 | assert (fill_size % 3 == 0); | |
7968 | return (fill_size / 3); | |
7969 | } | |
7970 | ||
7971 | assert (fill_size != 1); /* Bad argument. */ | |
7972 | ||
7973 | while (fill_size > 1) | |
7974 | { | |
d77b99c9 | 7975 | int insn_size = 3; |
e0001a05 NC |
7976 | if (fill_size == 2 || fill_size == 4) |
7977 | insn_size = 2; | |
7978 | fill_size -= insn_size; | |
7979 | count++; | |
7980 | } | |
7981 | assert (fill_size != 1); /* Bad algorithm. */ | |
7982 | return count; | |
7983 | } | |
7984 | ||
7985 | ||
d77b99c9 BW |
7986 | static int |
7987 | get_text_align_nth_nop_size (offsetT fill_size, | |
7988 | int n, | |
7fa3d080 | 7989 | bfd_boolean use_no_density) |
e0001a05 | 7990 | { |
d77b99c9 | 7991 | int count = 0; |
e0001a05 NC |
7992 | |
7993 | if (use_no_density) | |
7994 | return 3; | |
7995 | ||
d77b99c9 BW |
7996 | assert (fill_size != 1); /* Bad argument. */ |
7997 | ||
e0001a05 NC |
7998 | while (fill_size > 1) |
7999 | { | |
d77b99c9 | 8000 | int insn_size = 3; |
e0001a05 NC |
8001 | if (fill_size == 2 || fill_size == 4) |
8002 | insn_size = 2; | |
8003 | fill_size -= insn_size; | |
8004 | count++; | |
8005 | if (n + 1 == count) | |
8006 | return insn_size; | |
8007 | } | |
8008 | assert (0); | |
8009 | return 0; | |
8010 | } | |
8011 | ||
8012 | ||
8013 | /* For the given fragment, find the appropriate address | |
8014 | for it to begin at if we are using NOPs to align it. */ | |
8015 | ||
8016 | static addressT | |
7fa3d080 | 8017 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 8018 | { |
43cd72b9 BW |
8019 | /* The rule is: get next fragment's FIRST instruction. Find |
8020 | the smallest number of bytes that need to be added to | |
8021 | ensure that the next fragment's FIRST instruction will fit | |
8022 | in a single word. | |
c138bc38 | 8023 | |
43cd72b9 BW |
8024 | E.G., 2 bytes : 0, 1, 2 mod 4 |
8025 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 8026 | |
43cd72b9 BW |
8027 | If the FIRST instruction MIGHT be relaxed, |
8028 | assume that it will become a 3-byte instruction. | |
c138bc38 | 8029 | |
43cd72b9 BW |
8030 | Note again here that LOOP instructions are not bundleable, |
8031 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 8032 | |
d77b99c9 | 8033 | int fill_size = 0; |
43cd72b9 BW |
8034 | int first_insn_size; |
8035 | int loop_insn_size; | |
8036 | addressT pre_opcode_bytes; | |
d77b99c9 | 8037 | int align_power; |
43cd72b9 BW |
8038 | fragS *first_insn; |
8039 | xtensa_opcode opcode; | |
8040 | bfd_boolean is_loop; | |
e0001a05 | 8041 | |
43cd72b9 BW |
8042 | assert (fragP->fr_type == rs_machine_dependent); |
8043 | assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 8044 | |
43cd72b9 BW |
8045 | /* Find the loop frag. */ |
8046 | first_insn = next_non_empty_frag (fragP); | |
8047 | /* Now find the first insn frag. */ | |
8048 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 8049 | |
43cd72b9 BW |
8050 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
8051 | assert (is_loop); | |
8052 | loop_insn_size = xg_get_single_size (opcode); | |
e0001a05 | 8053 | |
43cd72b9 BW |
8054 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
8055 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 8056 | |
43cd72b9 BW |
8057 | /* For loops, the alignment depends on the size of the |
8058 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 8059 | |
43cd72b9 | 8060 | if (first_insn == NULL) |
03aaa593 BW |
8061 | first_insn_size = xtensa_fetch_width; |
8062 | else | |
8063 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 8064 | |
43cd72b9 | 8065 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
8066 | align_power = get_text_align_power (first_insn_size); |
8067 | record_alignment (now_seg, align_power); | |
c138bc38 | 8068 | |
43cd72b9 | 8069 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
8070 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
8071 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
8072 | |
8073 | return address + fill_size; | |
8074 | } | |
8075 | ||
8076 | ||
43cd72b9 BW |
8077 | /* 3 mechanisms for relaxing an alignment: |
8078 | ||
8079 | Align to a power of 2. | |
8080 | Align so the next fragment's instruction does not cross a word boundary. | |
8081 | Align the current instruction so that if the next instruction | |
8082 | were 3 bytes, it would not cross a word boundary. | |
8083 | ||
e0001a05 NC |
8084 | We can align with: |
8085 | ||
43cd72b9 BW |
8086 | zeros - This is easy; always insert zeros. |
8087 | nops - 3-byte and 2-byte instructions | |
8088 | 2 - 2-byte nop | |
8089 | 3 - 3-byte nop | |
8090 | 4 - 2 2-byte nops | |
8091 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
8092 | widening - widen previous instructions. */ |
8093 | ||
d77b99c9 BW |
8094 | static offsetT |
8095 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 8096 | { |
43cd72b9 BW |
8097 | addressT target_address, loop_insn_offset; |
8098 | int target_size; | |
8099 | xtensa_opcode loop_opcode; | |
8100 | bfd_boolean is_loop; | |
d77b99c9 BW |
8101 | int align_power; |
8102 | offsetT opt_diff; | |
5f9084e9 | 8103 | offsetT branch_align; |
e0001a05 | 8104 | |
43cd72b9 BW |
8105 | assert (fragP->fr_type == rs_machine_dependent); |
8106 | switch (fragP->fr_subtype) | |
e0001a05 | 8107 | { |
43cd72b9 BW |
8108 | case RELAX_DESIRE_ALIGN: |
8109 | target_size = next_frag_format_size (fragP); | |
8110 | if (target_size == XTENSA_UNDEFINED) | |
8111 | target_size = 3; | |
664df4e4 BW |
8112 | align_power = branch_align_power (now_seg); |
8113 | branch_align = 1 << align_power; | |
0e5cd789 BW |
8114 | /* Don't count on the section alignment being as large as the target. */ |
8115 | if (target_size > branch_align) | |
8116 | target_size = branch_align; | |
d77b99c9 | 8117 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
8118 | target_size, FALSE, FALSE); |
8119 | ||
664df4e4 BW |
8120 | *max_diff = (opt_diff + branch_align |
8121 | - (target_size + ((address + opt_diff) % branch_align))); | |
43cd72b9 BW |
8122 | assert (*max_diff >= opt_diff); |
8123 | return opt_diff; | |
e0001a05 | 8124 | |
43cd72b9 | 8125 | case RELAX_ALIGN_NEXT_OPCODE: |
03aaa593 | 8126 | target_size = get_loop_align_size (next_frag_format_size (fragP)); |
43cd72b9 BW |
8127 | loop_insn_offset = 0; |
8128 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
8129 | assert (is_loop); | |
8130 | ||
8131 | /* If the loop has been expanded then the LOOP instruction | |
8132 | could be at an offset from this fragment. */ | |
8133 | if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0] | |
8134 | != RELAX_IMMED) | |
8135 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); | |
8136 | ||
43cd72b9 BW |
8137 | /* In an ideal world, which is what we are shooting for here, |
8138 | we wouldn't need to use any NOPs immediately prior to the | |
8139 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
8140 | will call get_noop_aligned_address. */ | |
8141 | target_address = | |
8142 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
d77b99c9 BW |
8143 | align_power = get_text_align_power (target_size), |
8144 | opt_diff = get_text_align_fill_size (target_address, align_power, | |
43cd72b9 BW |
8145 | target_size, FALSE, FALSE); |
8146 | ||
8147 | *max_diff = xtensa_fetch_width | |
8148 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
8149 | - target_size + opt_diff; | |
8150 | assert (*max_diff >= opt_diff); | |
8151 | return opt_diff; | |
e0001a05 | 8152 | |
43cd72b9 BW |
8153 | default: |
8154 | break; | |
e0001a05 | 8155 | } |
43cd72b9 BW |
8156 | assert (0); |
8157 | return 0; | |
e0001a05 NC |
8158 | } |
8159 | ||
8160 | \f | |
8161 | /* md_relax_frag Hook and Helper Functions. */ | |
8162 | ||
7fa3d080 BW |
8163 | static long relax_frag_loop_align (fragS *, long); |
8164 | static long relax_frag_for_align (fragS *, long); | |
8165 | static long relax_frag_immed | |
8166 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
8167 | ||
8168 | ||
e0001a05 NC |
8169 | /* Return the number of bytes added to this fragment, given that the |
8170 | input has been stretched already by "stretch". */ | |
8171 | ||
8172 | long | |
7fa3d080 | 8173 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 8174 | { |
43cd72b9 | 8175 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
8176 | int unreported = fragP->tc_frag_data.unreported_expansion; |
8177 | long new_stretch = 0; | |
8178 | char *file_name; | |
d77b99c9 BW |
8179 | unsigned line; |
8180 | int lit_size; | |
43cd72b9 BW |
8181 | static xtensa_insnbuf vbuf = NULL; |
8182 | int slot, num_slots; | |
8183 | xtensa_format fmt; | |
e0001a05 NC |
8184 | |
8185 | as_where (&file_name, &line); | |
8186 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8187 | ||
8188 | fragP->tc_frag_data.unreported_expansion = 0; | |
8189 | ||
8190 | switch (fragP->fr_subtype) | |
8191 | { | |
8192 | case RELAX_ALIGN_NEXT_OPCODE: | |
8193 | /* Always convert. */ | |
43cd72b9 BW |
8194 | if (fragP->tc_frag_data.relax_seen) |
8195 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
8196 | break; |
8197 | ||
8198 | case RELAX_LOOP_END: | |
8199 | /* Do nothing. */ | |
8200 | break; | |
8201 | ||
8202 | case RELAX_LOOP_END_ADD_NOP: | |
8203 | /* Add a NOP and switch to .fill 0. */ | |
8204 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 8205 | frag_wane (fragP); |
e0001a05 NC |
8206 | break; |
8207 | ||
8208 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 8209 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
8210 | it or not. */ |
8211 | break; | |
8212 | ||
8213 | case RELAX_LITERAL: | |
8214 | case RELAX_LITERAL_FINAL: | |
8215 | return 0; | |
8216 | ||
8217 | case RELAX_LITERAL_NR: | |
8218 | lit_size = 4; | |
8219 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
8220 | assert (unreported == lit_size); | |
8221 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); | |
8222 | fragP->fr_var -= lit_size; | |
8223 | fragP->fr_fix += lit_size; | |
8224 | new_stretch = 4; | |
8225 | break; | |
8226 | ||
43cd72b9 BW |
8227 | case RELAX_SLOTS: |
8228 | if (vbuf == NULL) | |
8229 | vbuf = xtensa_insnbuf_alloc (isa); | |
8230 | ||
d77b99c9 BW |
8231 | xtensa_insnbuf_from_chars |
8232 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
8233 | fmt = xtensa_format_decode (isa, vbuf); |
8234 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 8235 | |
43cd72b9 BW |
8236 | for (slot = 0; slot < num_slots; slot++) |
8237 | { | |
8238 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
8239 | { | |
8240 | case RELAX_NARROW: | |
8241 | if (fragP->tc_frag_data.relax_seen) | |
8242 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8243 | break; | |
8244 | ||
8245 | case RELAX_IMMED: | |
8246 | case RELAX_IMMED_STEP1: | |
8247 | case RELAX_IMMED_STEP2: | |
8248 | /* Place the immediate. */ | |
8249 | new_stretch += relax_frag_immed | |
8250 | (now_seg, fragP, stretch, | |
8251 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8252 | fmt, slot, stretched_p, FALSE); | |
8253 | break; | |
8254 | ||
8255 | default: | |
8256 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
8257 | break; | |
8258 | } | |
8259 | } | |
e0001a05 NC |
8260 | break; |
8261 | ||
8262 | case RELAX_LITERAL_POOL_BEGIN: | |
8263 | case RELAX_LITERAL_POOL_END: | |
43cd72b9 BW |
8264 | case RELAX_MAYBE_UNREACHABLE: |
8265 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
8266 | /* No relaxation required. */ |
8267 | break; | |
8268 | ||
43cd72b9 BW |
8269 | case RELAX_FILL_NOP: |
8270 | case RELAX_UNREACHABLE: | |
8271 | if (fragP->tc_frag_data.relax_seen) | |
8272 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8273 | break; | |
8274 | ||
e0001a05 NC |
8275 | default: |
8276 | as_bad (_("bad relaxation state")); | |
8277 | } | |
8278 | ||
43cd72b9 | 8279 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 8280 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
8281 | { |
8282 | fragP->tc_frag_data.relax_seen = TRUE; | |
8283 | *stretched_p = 1; | |
8284 | } | |
8285 | ||
e0001a05 NC |
8286 | new_logical_line (file_name, line); |
8287 | return new_stretch; | |
8288 | } | |
8289 | ||
8290 | ||
8291 | static long | |
7fa3d080 | 8292 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
8293 | { |
8294 | addressT old_address, old_next_address, old_size; | |
8295 | addressT new_address, new_next_address, new_size; | |
8296 | addressT growth; | |
8297 | ||
43cd72b9 BW |
8298 | /* All the frags with relax_frag_for_alignment prior to this one in the |
8299 | section have been done, hopefully eliminating the need for a NOP here. | |
8300 | But, this will put it in if necessary. */ | |
e0001a05 NC |
8301 | |
8302 | /* Calculate the old address of this fragment and the next fragment. */ | |
8303 | old_address = fragP->fr_address - stretch; | |
8304 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 8305 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
8306 | old_size = old_next_address - old_address; |
8307 | ||
8308 | /* Calculate the new address of this fragment and the next fragment. */ | |
8309 | new_address = fragP->fr_address; | |
8310 | new_next_address = | |
8311 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
8312 | new_size = new_next_address - new_address; | |
8313 | ||
8314 | growth = new_size - old_size; | |
8315 | ||
8316 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 8317 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
8318 | return growth; |
8319 | } | |
8320 | ||
8321 | ||
43cd72b9 | 8322 | /* Add a NOP instruction. */ |
e0001a05 NC |
8323 | |
8324 | static long | |
7fa3d080 | 8325 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 8326 | { |
e0001a05 | 8327 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
8328 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
8329 | assemble_nop (length, nop_buf); | |
e0001a05 | 8330 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 8331 | |
e0001a05 NC |
8332 | if (fragP->fr_var < length) |
8333 | { | |
dd49a749 | 8334 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
8335 | return 0; |
8336 | } | |
8337 | ||
8338 | fragP->fr_fix += length; | |
8339 | fragP->fr_var -= length; | |
e0001a05 NC |
8340 | return length; |
8341 | } | |
8342 | ||
8343 | ||
7fa3d080 BW |
8344 | static long future_alignment_required (fragS *, long); |
8345 | ||
e0001a05 | 8346 | static long |
7fa3d080 | 8347 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 8348 | { |
43cd72b9 BW |
8349 | /* Overview of the relaxation procedure for alignment: |
8350 | We can widen with NOPs or by widening instructions or by filling | |
8351 | bytes after jump instructions. Find the opportune places and widen | |
8352 | them if necessary. */ | |
8353 | ||
8354 | long stretch_me; | |
8355 | long diff; | |
e0001a05 | 8356 | |
43cd72b9 BW |
8357 | assert (fragP->fr_subtype == RELAX_FILL_NOP |
8358 | || fragP->fr_subtype == RELAX_UNREACHABLE | |
8359 | || (fragP->fr_subtype == RELAX_SLOTS | |
8360 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
8361 | ||
8362 | stretch_me = future_alignment_required (fragP, stretch); | |
8363 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
8364 | if (diff == 0) | |
8365 | return 0; | |
e0001a05 | 8366 | |
43cd72b9 | 8367 | if (diff < 0) |
e0001a05 | 8368 | { |
43cd72b9 BW |
8369 | /* We expanded on a previous pass. Can we shrink now? */ |
8370 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
8371 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 8372 | { |
43cd72b9 BW |
8373 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
8374 | return -shrink; | |
e0001a05 NC |
8375 | } |
8376 | return 0; | |
8377 | } | |
8378 | ||
43cd72b9 BW |
8379 | /* Below here, diff > 0. */ |
8380 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 8381 | |
43cd72b9 | 8382 | return diff; |
e0001a05 NC |
8383 | } |
8384 | ||
8385 | ||
43cd72b9 BW |
8386 | /* Return the address of the next frag that should be aligned. |
8387 | ||
8388 | By "address" we mean the address it _would_ be at if there | |
8389 | is no action taken to align it between here and the target frag. | |
8390 | In other words, if no narrows and no fill nops are used between | |
8391 | here and the frag to align, _even_if_ some of the frags we use | |
8392 | to align targets have already expanded on a previous relaxation | |
8393 | pass. | |
8394 | ||
8395 | Also, count each frag that may be used to help align the target. | |
8396 | ||
8397 | Return 0 if there are no frags left in the chain that need to be | |
8398 | aligned. */ | |
8399 | ||
8400 | static addressT | |
7fa3d080 BW |
8401 | find_address_of_next_align_frag (fragS **fragPP, |
8402 | int *wide_nops, | |
8403 | int *narrow_nops, | |
8404 | int *widens, | |
8405 | bfd_boolean *paddable) | |
e0001a05 | 8406 | { |
43cd72b9 BW |
8407 | fragS *fragP = *fragPP; |
8408 | addressT address = fragP->fr_address; | |
8409 | ||
8410 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
8411 | |
8412 | while (fragP) | |
8413 | { | |
8414 | /* Limit this to a small search. */ | |
b5e4a23d | 8415 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
8416 | { |
8417 | *fragPP = fragP; | |
8418 | return 0; | |
8419 | } | |
e0001a05 NC |
8420 | address += fragP->fr_fix; |
8421 | ||
43cd72b9 BW |
8422 | if (fragP->fr_type == rs_fill) |
8423 | address += fragP->fr_offset * fragP->fr_var; | |
8424 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 8425 | { |
e0001a05 NC |
8426 | switch (fragP->fr_subtype) |
8427 | { | |
43cd72b9 BW |
8428 | case RELAX_UNREACHABLE: |
8429 | *paddable = TRUE; | |
8430 | break; | |
8431 | ||
8432 | case RELAX_FILL_NOP: | |
8433 | (*wide_nops)++; | |
8434 | if (!fragP->tc_frag_data.is_no_density) | |
8435 | (*narrow_nops)++; | |
8436 | break; | |
8437 | ||
8438 | case RELAX_SLOTS: | |
8439 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8440 | { | |
8441 | (*widens)++; | |
8442 | break; | |
8443 | } | |
34e41783 | 8444 | address += total_frag_text_expansion (fragP);; |
e0001a05 NC |
8445 | break; |
8446 | ||
8447 | case RELAX_IMMED: | |
43cd72b9 | 8448 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
8449 | break; |
8450 | ||
8451 | case RELAX_ALIGN_NEXT_OPCODE: | |
8452 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
8453 | *fragPP = fragP; |
8454 | return address; | |
8455 | ||
8456 | case RELAX_MAYBE_UNREACHABLE: | |
8457 | case RELAX_MAYBE_DESIRE_ALIGN: | |
8458 | /* Do nothing. */ | |
e0001a05 NC |
8459 | break; |
8460 | ||
8461 | default: | |
43cd72b9 BW |
8462 | /* Just punt if we don't know the type. */ |
8463 | *fragPP = fragP; | |
8464 | return 0; | |
e0001a05 | 8465 | } |
43cd72b9 | 8466 | } |
c138bc38 | 8467 | else |
43cd72b9 BW |
8468 | { |
8469 | /* Just punt if we don't know the type. */ | |
8470 | *fragPP = fragP; | |
8471 | return 0; | |
8472 | } | |
8473 | fragP = fragP->fr_next; | |
8474 | } | |
8475 | ||
8476 | *fragPP = fragP; | |
8477 | return 0; | |
8478 | } | |
8479 | ||
8480 | ||
7fa3d080 BW |
8481 | static long bytes_to_stretch (fragS *, int, int, int, int); |
8482 | ||
43cd72b9 | 8483 | static long |
7fa3d080 | 8484 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
8485 | { |
8486 | fragS *this_frag = fragP; | |
8487 | long address; | |
8488 | int num_widens = 0; | |
8489 | int wide_nops = 0; | |
8490 | int narrow_nops = 0; | |
8491 | bfd_boolean paddable = FALSE; | |
8492 | offsetT local_opt_diff; | |
8493 | offsetT opt_diff; | |
8494 | offsetT max_diff; | |
8495 | int stretch_amount = 0; | |
8496 | int local_stretch_amount; | |
8497 | int global_stretch_amount; | |
8498 | ||
7fa3d080 BW |
8499 | address = find_address_of_next_align_frag |
8500 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 8501 | |
b5e4a23d BW |
8502 | if (!address) |
8503 | { | |
8504 | if (this_frag->tc_frag_data.is_aligning_branch) | |
8505 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
8506 | else | |
8507 | frag_wane (this_frag); | |
8508 | } | |
8509 | else | |
43cd72b9 BW |
8510 | { |
8511 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
8512 | opt_diff = local_opt_diff; | |
8513 | assert (opt_diff >= 0); | |
8514 | assert (max_diff >= opt_diff); | |
c138bc38 | 8515 | if (max_diff == 0) |
43cd72b9 | 8516 | return 0; |
d2a033cd | 8517 | |
43cd72b9 BW |
8518 | if (fragP) |
8519 | fragP = fragP->fr_next; | |
8520 | ||
8521 | while (fragP && opt_diff < max_diff && address) | |
8522 | { | |
8523 | /* We only use these to determine if we can exit early | |
c138bc38 | 8524 | because there will be plenty of ways to align future |
43cd72b9 | 8525 | align frags. */ |
d77b99c9 | 8526 | int glob_widens = 0; |
43cd72b9 BW |
8527 | int dnn = 0; |
8528 | int dw = 0; | |
8529 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
8530 | address = find_address_of_next_align_frag |
8531 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 8532 | /* If there is a padable portion, then skip. */ |
664df4e4 | 8533 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 8534 | address = 0; |
43cd72b9 | 8535 | |
c138bc38 | 8536 | if (address) |
43cd72b9 BW |
8537 | { |
8538 | offsetT next_m_diff; | |
8539 | offsetT next_o_diff; | |
8540 | ||
8541 | /* Downrange frags haven't had stretch added to them yet. */ | |
8542 | address += stretch; | |
8543 | ||
8544 | /* The address also includes any text expansion from this | |
8545 | frag in a previous pass, but we don't want that. */ | |
8546 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
8547 | ||
8548 | /* Assume we are going to move at least opt_diff. In | |
8549 | reality, we might not be able to, but assuming that | |
8550 | we will helps catch cases where moving opt_diff pushes | |
8551 | the next target from aligned to unaligned. */ | |
8552 | address += opt_diff; | |
8553 | ||
8554 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
8555 | ||
8556 | /* Now cleanup for the adjustments to address. */ | |
8557 | next_o_diff += opt_diff; | |
8558 | next_m_diff += opt_diff; | |
8559 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
8560 | opt_diff = next_o_diff; | |
8561 | if (next_m_diff < max_diff) | |
8562 | max_diff = next_m_diff; | |
8563 | fragP = fragP->fr_next; | |
8564 | } | |
8565 | } | |
d2a033cd | 8566 | |
43cd72b9 BW |
8567 | /* If there are enough wideners in between, do it. */ |
8568 | if (paddable) | |
8569 | { | |
8570 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
8571 | { | |
8572 | assert (opt_diff <= UNREACHABLE_MAX_WIDTH); | |
8573 | return opt_diff; | |
8574 | } | |
8575 | return 0; | |
8576 | } | |
c138bc38 | 8577 | local_stretch_amount |
43cd72b9 BW |
8578 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
8579 | num_widens, local_opt_diff); | |
c138bc38 BW |
8580 | global_stretch_amount |
8581 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 8582 | num_widens, opt_diff); |
c138bc38 BW |
8583 | /* If the condition below is true, then the frag couldn't |
8584 | stretch the correct amount for the global case, so we just | |
8585 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
8586 | the correct alignment in the global case. */ |
8587 | if (global_stretch_amount < local_stretch_amount) | |
8588 | stretch_amount = local_stretch_amount; | |
8589 | else | |
8590 | stretch_amount = global_stretch_amount; | |
d2a033cd | 8591 | |
43cd72b9 BW |
8592 | if (this_frag->fr_subtype == RELAX_SLOTS |
8593 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8594 | assert (stretch_amount <= 1); | |
8595 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8596 | { | |
8597 | if (this_frag->tc_frag_data.is_no_density) | |
8598 | assert (stretch_amount == 3 || stretch_amount == 0); | |
8599 | else | |
8600 | assert (stretch_amount <= 3); | |
8601 | } | |
8602 | } | |
8603 | return stretch_amount; | |
8604 | } | |
8605 | ||
8606 | ||
8607 | /* The idea: widen everything you can to get a target or loop aligned, | |
8608 | then start using NOPs. | |
8609 | ||
8610 | When we must have a NOP, here is a table of how we decide | |
8611 | (so you don't have to fight through the control flow below): | |
8612 | ||
8613 | wide_nops = the number of wide NOPs available for aligning | |
8614 | narrow_nops = the number of narrow NOPs available for aligning | |
8615 | (a subset of wide_nops) | |
8616 | widens = the number of narrow instructions that should be widened | |
8617 | ||
8618 | Desired wide narrow | |
8619 | Diff nop nop widens | |
8620 | 1 0 0 1 | |
8621 | 2 0 1 0 | |
8622 | 3a 1 0 0 | |
8623 | b 0 1 1 (case 3a makes this case unnecessary) | |
8624 | 4a 1 0 1 | |
8625 | b 0 2 0 | |
8626 | c 0 1 2 (case 4a makes this case unnecessary) | |
8627 | 5a 1 0 2 | |
8628 | b 1 1 0 | |
8629 | c 0 2 1 (case 5b makes this case unnecessary) | |
8630 | 6a 2 0 0 | |
8631 | b 1 0 3 | |
708587a4 | 8632 | c 0 1 4 (case 6b makes this case unnecessary) |
43cd72b9 BW |
8633 | d 1 1 1 (case 6a makes this case unnecessary) |
8634 | e 0 2 2 (case 6a makes this case unnecessary) | |
8635 | f 0 3 0 (case 6a makes this case unnecessary) | |
8636 | 7a 1 0 4 | |
8637 | b 2 0 1 | |
8638 | c 1 1 2 (case 7b makes this case unnecessary) | |
8639 | d 0 1 5 (case 7a makes this case unnecessary) | |
8640 | e 0 2 3 (case 7b makes this case unnecessary) | |
8641 | f 0 3 1 (case 7b makes this case unnecessary) | |
8642 | g 1 2 1 (case 7b makes this case unnecessary) | |
8643 | */ | |
8644 | ||
8645 | static long | |
7fa3d080 BW |
8646 | bytes_to_stretch (fragS *this_frag, |
8647 | int wide_nops, | |
8648 | int narrow_nops, | |
8649 | int num_widens, | |
8650 | int desired_diff) | |
43cd72b9 BW |
8651 | { |
8652 | int bytes_short = desired_diff - num_widens; | |
8653 | ||
8654 | assert (desired_diff >= 0 && desired_diff < 8); | |
8655 | if (desired_diff == 0) | |
8656 | return 0; | |
c138bc38 | 8657 | |
43cd72b9 | 8658 | assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 8659 | |
43cd72b9 BW |
8660 | /* Always prefer widening to NOP-filling. */ |
8661 | if (bytes_short < 0) | |
8662 | { | |
8663 | /* There are enough RELAX_NARROW frags after this one | |
8664 | to align the target without widening this frag in any way. */ | |
8665 | return 0; | |
8666 | } | |
c138bc38 | 8667 | |
43cd72b9 BW |
8668 | if (bytes_short == 0) |
8669 | { | |
8670 | /* Widen every narrow between here and the align target | |
8671 | and the align target will be properly aligned. */ | |
8672 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8673 | return 0; | |
8674 | else | |
8675 | return 1; | |
8676 | } | |
c138bc38 | 8677 | |
43cd72b9 BW |
8678 | /* From here we will need at least one NOP to get an alignment. |
8679 | However, we may not be able to align at all, in which case, | |
8680 | don't widen. */ | |
8681 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8682 | { | |
8683 | switch (desired_diff) | |
8684 | { | |
8685 | case 1: | |
8686 | return 0; | |
8687 | case 2: | |
8688 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1) | |
8689 | return 2; /* case 2 */ | |
8690 | return 0; | |
c138bc38 | 8691 | case 3: |
43cd72b9 BW |
8692 | if (wide_nops > 1) |
8693 | return 0; | |
8694 | else | |
8695 | return 3; /* case 3a */ | |
8696 | case 4: | |
8697 | if (num_widens >= 1 && wide_nops == 1) | |
8698 | return 3; /* case 4a */ | |
8699 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2) | |
8700 | return 2; /* case 4b */ | |
8701 | return 0; | |
8702 | case 5: | |
8703 | if (num_widens >= 2 && wide_nops == 1) | |
8704 | return 3; /* case 5a */ | |
c138bc38 | 8705 | /* We will need two nops. Are there enough nops |
43cd72b9 BW |
8706 | between here and the align target? */ |
8707 | if (wide_nops < 2 || narrow_nops == 0) | |
8708 | return 0; | |
8709 | /* Are there other nops closer that can serve instead? */ | |
8710 | if (wide_nops > 2 && narrow_nops > 1) | |
8711 | return 0; | |
8712 | /* Take the density one first, because there might not be | |
8713 | another density one available. */ | |
8714 | if (!this_frag->tc_frag_data.is_no_density) | |
8715 | return 2; /* case 5b narrow */ | |
8716 | else | |
8717 | return 3; /* case 5b wide */ | |
8718 | return 0; | |
8719 | case 6: | |
8720 | if (wide_nops == 2) | |
8721 | return 3; /* case 6a */ | |
8722 | else if (num_widens >= 3 && wide_nops == 1) | |
8723 | return 3; /* case 6b */ | |
8724 | return 0; | |
8725 | case 7: | |
8726 | if (wide_nops == 1 && num_widens >= 4) | |
8727 | return 3; /* case 7a */ | |
8728 | else if (wide_nops == 2 && num_widens >= 1) | |
8729 | return 3; /* case 7b */ | |
8730 | return 0; | |
e0001a05 | 8731 | default: |
43cd72b9 | 8732 | assert (0); |
e0001a05 | 8733 | } |
e0001a05 | 8734 | } |
43cd72b9 BW |
8735 | else |
8736 | { | |
c138bc38 | 8737 | /* We will need a NOP no matter what, but should we widen |
43cd72b9 | 8738 | this instruction to help? |
e0001a05 | 8739 | |
03aaa593 | 8740 | This is a RELAX_NARROW frag. */ |
43cd72b9 BW |
8741 | switch (desired_diff) |
8742 | { | |
8743 | case 1: | |
8744 | assert (0); | |
8745 | return 0; | |
8746 | case 2: | |
8747 | case 3: | |
8748 | return 0; | |
8749 | case 4: | |
8750 | if (wide_nops >= 1 && num_widens == 1) | |
8751 | return 1; /* case 4a */ | |
8752 | return 0; | |
8753 | case 5: | |
8754 | if (wide_nops >= 1 && num_widens == 2) | |
8755 | return 1; /* case 5a */ | |
8756 | return 0; | |
8757 | case 6: | |
8758 | if (wide_nops >= 2) | |
8759 | return 0; /* case 6a */ | |
8760 | else if (wide_nops >= 1 && num_widens == 3) | |
8761 | return 1; /* case 6b */ | |
8762 | return 0; | |
8763 | case 7: | |
8764 | if (wide_nops >= 1 && num_widens == 4) | |
8765 | return 1; /* case 7a */ | |
8766 | else if (wide_nops >= 2 && num_widens == 1) | |
8767 | return 1; /* case 7b */ | |
8768 | return 0; | |
8769 | default: | |
8770 | assert (0); | |
8771 | return 0; | |
8772 | } | |
8773 | } | |
8774 | assert (0); | |
8775 | return 0; | |
e0001a05 NC |
8776 | } |
8777 | ||
8778 | ||
8779 | static long | |
7fa3d080 BW |
8780 | relax_frag_immed (segT segP, |
8781 | fragS *fragP, | |
8782 | long stretch, | |
8783 | int min_steps, | |
8784 | xtensa_format fmt, | |
8785 | int slot, | |
8786 | int *stretched_p, | |
8787 | bfd_boolean estimate_only) | |
e0001a05 | 8788 | { |
43cd72b9 | 8789 | TInsn tinsn; |
e0001a05 NC |
8790 | int old_size; |
8791 | bfd_boolean negatable_branch = FALSE; | |
8792 | bfd_boolean branch_jmp_to_next = FALSE; | |
43cd72b9 BW |
8793 | bfd_boolean wide_insn = FALSE; |
8794 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
8795 | IStack istack; |
8796 | offsetT frag_offset; | |
8797 | int num_steps; | |
8798 | fragS *lit_fragP; | |
8799 | int num_text_bytes, num_literal_bytes; | |
43cd72b9 | 8800 | int literal_diff, total_text_diff, this_text_diff, first; |
e0001a05 NC |
8801 | |
8802 | assert (fragP->fr_opcode != NULL); | |
8803 | ||
b5e4a23d BW |
8804 | xg_clear_vinsn (&cur_vinsn); |
8805 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 8806 | if (cur_vinsn.num_slots > 1) |
43cd72b9 BW |
8807 | wide_insn = TRUE; |
8808 | ||
b5e4a23d | 8809 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 8810 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 8811 | |
64b607e6 | 8812 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 8813 | return 0; |
e0001a05 | 8814 | |
b08b5071 | 8815 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 8816 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 8817 | |
43cd72b9 | 8818 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 8819 | |
43cd72b9 | 8820 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
8821 | |
8822 | /* Special case: replace a branch to the next instruction with a NOP. | |
8823 | This is required to work around a hardware bug in T1040.0 and also | |
8824 | serves as an optimization. */ | |
8825 | ||
8826 | if (branch_jmp_to_next | |
8827 | && ((old_size == 2) || (old_size == 3)) | |
8828 | && !next_frag_is_loop_target (fragP)) | |
8829 | return 0; | |
8830 | ||
8831 | /* Here is the fun stuff: Get the immediate field from this | |
8832 | instruction. If it fits, we are done. If not, find the next | |
8833 | instruction sequence that fits. */ | |
8834 | ||
8835 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
8836 | istack_init (&istack); | |
43cd72b9 | 8837 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 NC |
8838 | min_steps, stretch); |
8839 | if (num_steps < min_steps) | |
8840 | { | |
8841 | as_fatal (_("internal error: relaxation failed")); | |
8842 | return 0; | |
8843 | } | |
8844 | ||
8845 | if (num_steps > RELAX_IMMED_MAXSTEPS) | |
8846 | { | |
8847 | as_fatal (_("internal error: relaxation requires too many steps")); | |
8848 | return 0; | |
8849 | } | |
8850 | ||
43cd72b9 | 8851 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
8852 | |
8853 | /* Figure out the number of bytes needed. */ | |
8854 | lit_fragP = 0; | |
e0001a05 | 8855 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
43cd72b9 BW |
8856 | literal_diff = |
8857 | num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
8858 | first = 0; | |
8859 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
8860 | first++; | |
8861 | num_text_bytes = get_num_stack_text_bytes (&istack); | |
8862 | if (wide_insn) | |
8863 | { | |
8864 | num_text_bytes += old_size; | |
8865 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
8866 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
8867 | } | |
8868 | total_text_diff = num_text_bytes - old_size; | |
8869 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
8870 | |
8871 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
43cd72b9 BW |
8872 | assert (num_text_bytes >= 0); |
8873 | assert (literal_diff >= 0); | |
8874 | assert (total_text_diff >= 0); | |
e0001a05 | 8875 | |
43cd72b9 BW |
8876 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
8877 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
8878 | assert (fragP->tc_frag_data.text_expansion[slot] >= 0); | |
8879 | assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
8880 | |
8881 | /* Find the associated expandable literal for this. */ | |
8882 | if (literal_diff != 0) | |
8883 | { | |
43cd72b9 | 8884 | lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
8885 | if (lit_fragP) |
8886 | { | |
8887 | assert (literal_diff == 4); | |
8888 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; | |
8889 | ||
8890 | /* We expect that the literal section state has NOT been | |
8891 | modified yet. */ | |
8892 | assert (lit_fragP->fr_type == rs_machine_dependent | |
8893 | && lit_fragP->fr_subtype == RELAX_LITERAL); | |
8894 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
8895 | ||
8896 | /* We need to mark this section for another iteration | |
8897 | of relaxation. */ | |
8898 | (*stretched_p)++; | |
8899 | } | |
8900 | } | |
8901 | ||
43cd72b9 | 8902 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 8903 | update_next_frag_state (fragP); |
e0001a05 | 8904 | |
43cd72b9 | 8905 | return this_text_diff; |
e0001a05 NC |
8906 | } |
8907 | ||
8908 | \f | |
8909 | /* md_convert_frag Hook and Helper Functions. */ | |
8910 | ||
7fa3d080 BW |
8911 | static void convert_frag_align_next_opcode (fragS *); |
8912 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
8913 | static void convert_frag_fill_nop (fragS *); | |
8914 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
8915 | ||
e0001a05 | 8916 | void |
7fa3d080 | 8917 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 8918 | { |
43cd72b9 BW |
8919 | static xtensa_insnbuf vbuf = NULL; |
8920 | xtensa_isa isa = xtensa_default_isa; | |
8921 | int slot; | |
8922 | int num_slots; | |
8923 | xtensa_format fmt; | |
e0001a05 | 8924 | char *file_name; |
d77b99c9 | 8925 | unsigned line; |
e0001a05 NC |
8926 | |
8927 | as_where (&file_name, &line); | |
8928 | new_logical_line (fragp->fr_file, fragp->fr_line); | |
8929 | ||
8930 | switch (fragp->fr_subtype) | |
8931 | { | |
8932 | case RELAX_ALIGN_NEXT_OPCODE: | |
8933 | /* Always convert. */ | |
8934 | convert_frag_align_next_opcode (fragp); | |
8935 | break; | |
8936 | ||
8937 | case RELAX_DESIRE_ALIGN: | |
8938 | /* Do nothing. If not aligned already, too bad. */ | |
8939 | break; | |
8940 | ||
43cd72b9 BW |
8941 | case RELAX_LITERAL: |
8942 | case RELAX_LITERAL_FINAL: | |
8943 | break; | |
8944 | ||
8945 | case RELAX_SLOTS: | |
8946 | if (vbuf == NULL) | |
8947 | vbuf = xtensa_insnbuf_alloc (isa); | |
8948 | ||
d77b99c9 BW |
8949 | xtensa_insnbuf_from_chars |
8950 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
8951 | fmt = xtensa_format_decode (isa, vbuf); |
8952 | num_slots = xtensa_format_num_slots (isa, fmt); | |
8953 | ||
8954 | for (slot = 0; slot < num_slots; slot++) | |
8955 | { | |
8956 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
8957 | { | |
8958 | case RELAX_NARROW: | |
8959 | convert_frag_narrow (sec, fragp, fmt, slot); | |
8960 | break; | |
8961 | ||
8962 | case RELAX_IMMED: | |
8963 | case RELAX_IMMED_STEP1: | |
8964 | case RELAX_IMMED_STEP2: | |
8965 | /* Place the immediate. */ | |
8966 | convert_frag_immed | |
8967 | (sec, fragp, | |
8968 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8969 | fmt, slot); | |
8970 | break; | |
8971 | ||
8972 | default: | |
8973 | /* This is OK because some slots could have | |
8974 | relaxations and others have none. */ | |
8975 | break; | |
8976 | } | |
8977 | } | |
8978 | break; | |
8979 | ||
8980 | case RELAX_UNREACHABLE: | |
8981 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
8982 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
8983 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
8984 | frag_wane (fragp); | |
e0001a05 NC |
8985 | break; |
8986 | ||
43cd72b9 BW |
8987 | case RELAX_MAYBE_UNREACHABLE: |
8988 | case RELAX_MAYBE_DESIRE_ALIGN: | |
8989 | frag_wane (fragp); | |
e0001a05 NC |
8990 | break; |
8991 | ||
43cd72b9 BW |
8992 | case RELAX_FILL_NOP: |
8993 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
8994 | break; |
8995 | ||
8996 | case RELAX_LITERAL_NR: | |
8997 | if (use_literal_section) | |
8998 | { | |
8999 | /* This should have been handled during relaxation. When | |
9000 | relaxing a code segment, literals sometimes need to be | |
9001 | added to the corresponding literal segment. If that | |
9002 | literal segment has already been relaxed, then we end up | |
9003 | in this situation. Marking the literal segments as data | |
9004 | would make this happen less often (since GAS always relaxes | |
9005 | code before data), but we could still get into trouble if | |
9006 | there are instructions in a segment that is not marked as | |
9007 | containing code. Until we can implement a better solution, | |
9008 | cheat and adjust the addresses of all the following frags. | |
9009 | This could break subsequent alignments, but the linker's | |
9010 | literal coalescing will do that anyway. */ | |
9011 | ||
9012 | fragS *f; | |
9013 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9014 | assert (fragp->tc_frag_data.unreported_expansion == 4); | |
9015 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); | |
9016 | fragp->fr_var -= 4; | |
9017 | fragp->fr_fix += 4; | |
9018 | for (f = fragp->fr_next; f; f = f->fr_next) | |
9019 | f->fr_address += 4; | |
9020 | } | |
9021 | else | |
9022 | as_bad (_("invalid relaxation fragment result")); | |
9023 | break; | |
9024 | } | |
9025 | ||
9026 | fragp->fr_var = 0; | |
9027 | new_logical_line (file_name, line); | |
9028 | } | |
9029 | ||
9030 | ||
7fa3d080 BW |
9031 | static void |
9032 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
9033 | { |
9034 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
9035 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
9036 | addressT aligned_address; | |
d77b99c9 BW |
9037 | offsetT fill_size; |
9038 | int nop, nop_count; | |
e0001a05 NC |
9039 | |
9040 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
9041 | fragp->fr_fix); | |
9042 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
9043 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
9044 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
9045 | ||
d77b99c9 | 9046 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 9047 | { |
d77b99c9 BW |
9048 | int nop_size; |
9049 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
9050 | |
9051 | assemble_nop (nop_size, nop_buf); | |
9052 | nop_buf += nop_size; | |
9053 | } | |
9054 | ||
9055 | fragp->fr_fix += fill_size; | |
9056 | fragp->fr_var -= fill_size; | |
9057 | } | |
9058 | ||
9059 | ||
9060 | static void | |
7fa3d080 | 9061 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 9062 | { |
43cd72b9 | 9063 | TInsn tinsn, single_target; |
84b08ed9 | 9064 | int size, old_size, diff; |
e0001a05 NC |
9065 | offsetT frag_offset; |
9066 | ||
43cd72b9 BW |
9067 | assert (slot == 0); |
9068 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); | |
9069 | ||
b5e4a23d | 9070 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 BW |
9071 | { |
9072 | assert (fragP->tc_frag_data.text_expansion[0] == 1 | |
9073 | || fragP->tc_frag_data.text_expansion[0] == 0); | |
9074 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
9075 | fmt, slot); | |
9076 | return; | |
9077 | } | |
9078 | ||
9079 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
9080 | { |
9081 | /* No conversion. */ | |
9082 | fragP->fr_var = 0; | |
9083 | return; | |
9084 | } | |
9085 | ||
9086 | assert (fragP->fr_opcode != NULL); | |
9087 | ||
43cd72b9 BW |
9088 | /* Frags in this relaxation state should only contain |
9089 | single instruction bundles. */ | |
9090 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
9091 | |
9092 | /* Just convert it to a wide form.... */ | |
9093 | size = 0; | |
43cd72b9 | 9094 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
9095 | |
9096 | tinsn_init (&single_target); | |
9097 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9098 | ||
84b08ed9 | 9099 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
9100 | { |
9101 | as_bad (_("unable to widen instruction")); | |
9102 | return; | |
9103 | } | |
9104 | ||
9105 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
9106 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
9107 | frag_offset, TRUE); | |
e0001a05 NC |
9108 | |
9109 | diff = size - old_size; | |
9110 | assert (diff >= 0); | |
9111 | assert (diff <= fragP->fr_var); | |
9112 | fragP->fr_var -= diff; | |
9113 | fragP->fr_fix += diff; | |
9114 | ||
9115 | /* clean it up */ | |
9116 | fragP->fr_var = 0; | |
9117 | } | |
9118 | ||
9119 | ||
9120 | static void | |
7fa3d080 | 9121 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
9122 | { |
9123 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
9124 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9125 | assert ((unsigned) size == (fragP->fr_next->fr_address | |
9126 | - fragP->fr_address - fragP->fr_fix)); | |
9127 | if (size == 0) | |
9128 | { | |
9129 | /* No conversion. */ | |
9130 | fragP->fr_var = 0; | |
9131 | return; | |
9132 | } | |
9133 | assemble_nop (size, loc); | |
9134 | fragP->tc_frag_data.is_insn = TRUE; | |
9135 | fragP->fr_var -= size; | |
9136 | fragP->fr_fix += size; | |
9137 | frag_wane (fragP); | |
9138 | } | |
9139 | ||
9140 | ||
7fa3d080 BW |
9141 | static fixS *fix_new_exp_in_seg |
9142 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
9143 | bfd_reloc_code_real_type); | |
9144 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
9145 | ||
43cd72b9 | 9146 | static void |
7fa3d080 BW |
9147 | convert_frag_immed (segT segP, |
9148 | fragS *fragP, | |
9149 | int min_steps, | |
9150 | xtensa_format fmt, | |
9151 | int slot) | |
e0001a05 NC |
9152 | { |
9153 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 9154 | TInsn orig_tinsn; |
e0001a05 | 9155 | bfd_boolean expanded = FALSE; |
e0001a05 | 9156 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 9157 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 BW |
9158 | xtensa_isa isa = xtensa_default_isa; |
9159 | bfd_boolean wide_insn = FALSE; | |
9160 | int bytes; | |
9161 | bfd_boolean is_loop; | |
e0001a05 | 9162 | |
43cd72b9 | 9163 | assert (fr_opcode != NULL); |
e0001a05 | 9164 | |
b5e4a23d | 9165 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 9166 | |
b5e4a23d | 9167 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 9168 | if (cur_vinsn.num_slots > 1) |
43cd72b9 | 9169 | wide_insn = TRUE; |
e0001a05 | 9170 | |
b5e4a23d | 9171 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
9172 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
9173 | ||
9174 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 9175 | |
b08b5071 | 9176 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9177 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
9178 | |
9179 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
9180 | { | |
9181 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
9182 | bytes = xtensa_format_length (isa, fmt); |
9183 | if (bytes >= 4) | |
9184 | { | |
b5e4a23d BW |
9185 | cur_vinsn.slots[slot].opcode = |
9186 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
9187 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
9188 | } |
9189 | else | |
9190 | { | |
9191 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9192 | assert (bytes == 2 || bytes == 3); | |
b5e4a23d | 9193 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
9194 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
9195 | } | |
e7da6241 | 9196 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 9197 | xtensa_insnbuf_to_chars |
b5e4a23d | 9198 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
9199 | fragP->fr_var = 0; |
9200 | } | |
7c834684 | 9201 | else |
e0001a05 | 9202 | { |
43cd72b9 BW |
9203 | /* Here is the fun stuff: Get the immediate field from this |
9204 | instruction. If it fits, we're done. If not, find the next | |
9205 | instruction sequence that fits. */ | |
9206 | ||
e0001a05 NC |
9207 | IStack istack; |
9208 | int i; | |
9209 | symbolS *lit_sym = NULL; | |
9210 | int total_size = 0; | |
43cd72b9 | 9211 | int target_offset = 0; |
e0001a05 NC |
9212 | int old_size; |
9213 | int diff; | |
9214 | symbolS *gen_label = NULL; | |
9215 | offsetT frag_offset; | |
43cd72b9 BW |
9216 | bfd_boolean first = TRUE; |
9217 | bfd_boolean last_is_jump; | |
e0001a05 | 9218 | |
43cd72b9 | 9219 | /* It does not fit. Find something that does and |
e0001a05 | 9220 | convert immediately. */ |
43cd72b9 | 9221 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 9222 | istack_init (&istack); |
43cd72b9 | 9223 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
9224 | segP, fragP, frag_offset, min_steps, 0); |
9225 | ||
43cd72b9 | 9226 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9227 | |
9228 | /* Assemble this right inline. */ | |
9229 | ||
9230 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 9231 | target_offset = 0; |
e0001a05 NC |
9232 | for (i = 0; i < istack.ninsn; i++) |
9233 | { | |
43cd72b9 | 9234 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9235 | fragS *lit_frag; |
9236 | ||
43cd72b9 | 9237 | switch (tinsn->insn_type) |
e0001a05 NC |
9238 | { |
9239 | case ITYPE_LITERAL: | |
9240 | if (lit_sym != NULL) | |
9241 | as_bad (_("multiple literals in expansion")); | |
9242 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 9243 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9244 | if (lit_frag == NULL) |
9245 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 9246 | if (tinsn->ntok != 1) |
e0001a05 NC |
9247 | as_bad (_("number of literal tokens != 1")); |
9248 | ||
9249 | /* Set the literal symbol and add a fixup. */ | |
9250 | lit_sym = lit_frag->fr_symbol; | |
9251 | break; | |
9252 | ||
9253 | case ITYPE_LABEL: | |
43cd72b9 BW |
9254 | if (align_targets && !is_loop) |
9255 | { | |
9256 | fragS *unreach = fragP->fr_next; | |
9257 | while (!(unreach->fr_type == rs_machine_dependent | |
9258 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9259 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
9260 | { | |
9261 | unreach = unreach->fr_next; | |
9262 | } | |
9263 | ||
9264 | assert (unreach->fr_type == rs_machine_dependent | |
9265 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9266 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
9267 | ||
9268 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
9269 | } | |
e0001a05 NC |
9270 | assert (gen_label == NULL); |
9271 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, | |
43cd72b9 BW |
9272 | fr_opcode - fragP->fr_literal |
9273 | + target_offset, fragP); | |
e0001a05 NC |
9274 | break; |
9275 | ||
9276 | case ITYPE_INSN: | |
43cd72b9 BW |
9277 | if (first && wide_insn) |
9278 | { | |
9279 | target_offset += xtensa_format_length (isa, fmt); | |
9280 | first = FALSE; | |
9281 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9282 | target_offset += xg_get_single_size (tinsn->opcode); | |
9283 | } | |
9284 | else | |
9285 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
9286 | break; |
9287 | } | |
9288 | } | |
9289 | ||
9290 | total_size = 0; | |
43cd72b9 BW |
9291 | first = TRUE; |
9292 | last_is_jump = FALSE; | |
e0001a05 NC |
9293 | for (i = 0; i < istack.ninsn; i++) |
9294 | { | |
43cd72b9 | 9295 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9296 | fragS *lit_frag; |
9297 | int size; | |
9298 | segT target_seg; | |
43cd72b9 | 9299 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 9300 | |
43cd72b9 | 9301 | switch (tinsn->insn_type) |
e0001a05 NC |
9302 | { |
9303 | case ITYPE_LITERAL: | |
43cd72b9 BW |
9304 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
9305 | /* Already checked. */ | |
e0001a05 NC |
9306 | assert (lit_frag != NULL); |
9307 | assert (lit_sym != NULL); | |
43cd72b9 BW |
9308 | assert (tinsn->ntok == 1); |
9309 | /* Add a fixup. */ | |
e0001a05 NC |
9310 | target_seg = S_GET_SEGMENT (lit_sym); |
9311 | assert (target_seg); | |
43cd72b9 BW |
9312 | if (tinsn->tok[0].X_op == O_pltrel) |
9313 | reloc_type = BFD_RELOC_XTENSA_PLT; | |
9314 | else | |
9315 | reloc_type = BFD_RELOC_32; | |
e0001a05 | 9316 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 9317 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
9318 | break; |
9319 | ||
9320 | case ITYPE_LABEL: | |
9321 | break; | |
9322 | ||
9323 | case ITYPE_INSN: | |
43cd72b9 BW |
9324 | xg_resolve_labels (tinsn, gen_label); |
9325 | xg_resolve_literals (tinsn, lit_sym); | |
9326 | if (wide_insn && first) | |
9327 | { | |
9328 | first = FALSE; | |
9329 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9330 | { | |
b5e4a23d | 9331 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
9332 | } |
9333 | else | |
9334 | { | |
b5e4a23d | 9335 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 9336 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 9337 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 9338 | } |
b5e4a23d BW |
9339 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
9340 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 9341 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
9342 | fragP->tc_frag_data.is_insn = TRUE; |
9343 | size = xtensa_format_length (isa, fmt); | |
9344 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9345 | { | |
43cd72b9 | 9346 | xg_emit_insn_to_buf |
b2d179be | 9347 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
9348 | immed_instr - fragP->fr_literal + size, TRUE); |
9349 | size += xg_get_single_size (tinsn->opcode); | |
9350 | } | |
9351 | } | |
9352 | else | |
9353 | { | |
43cd72b9 | 9354 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 9355 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 9356 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 9357 | } |
e0001a05 | 9358 | immed_instr += size; |
43cd72b9 | 9359 | total_size += size; |
e0001a05 NC |
9360 | break; |
9361 | } | |
9362 | } | |
9363 | ||
9364 | diff = total_size - old_size; | |
9365 | assert (diff >= 0); | |
9366 | if (diff != 0) | |
9367 | expanded = TRUE; | |
9368 | assert (diff <= fragP->fr_var); | |
9369 | fragP->fr_var -= diff; | |
9370 | fragP->fr_fix += diff; | |
9371 | } | |
9372 | ||
e0001a05 | 9373 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 9374 | if (is_loop) |
e0001a05 NC |
9375 | { |
9376 | symbolS *sym; | |
43cd72b9 | 9377 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
9378 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9379 | { | |
9380 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9381 | return; | |
9382 | } | |
43cd72b9 | 9383 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
9384 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9385 | { | |
9386 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9387 | return; | |
9388 | } | |
9389 | } | |
9390 | ||
43cd72b9 BW |
9391 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
9392 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 9393 | |
43cd72b9 | 9394 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
9395 | { |
9396 | /* Add an expansion note on the expanded instruction. */ | |
9397 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 9398 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 9399 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
9400 | } |
9401 | } | |
9402 | ||
9403 | ||
9404 | /* Add a new fix expression into the desired segment. We have to | |
9405 | switch to that segment to do this. */ | |
9406 | ||
9407 | static fixS * | |
7fa3d080 BW |
9408 | fix_new_exp_in_seg (segT new_seg, |
9409 | subsegT new_subseg, | |
9410 | fragS *frag, | |
9411 | int where, | |
9412 | int size, | |
9413 | expressionS *exp, | |
9414 | int pcrel, | |
9415 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
9416 | { |
9417 | fixS *new_fix; | |
9418 | segT seg = now_seg; | |
9419 | subsegT subseg = now_subseg; | |
43cd72b9 | 9420 | |
e0001a05 NC |
9421 | assert (new_seg != 0); |
9422 | subseg_set (new_seg, new_subseg); | |
9423 | ||
e0001a05 NC |
9424 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
9425 | subseg_set (seg, subseg); | |
9426 | return new_fix; | |
9427 | } | |
9428 | ||
9429 | ||
43cd72b9 BW |
9430 | /* Relax a loop instruction so that it can span loop >256 bytes. |
9431 | ||
9432 | loop as, .L1 | |
9433 | .L0: | |
9434 | rsr as, LEND | |
9435 | wsr as, LBEG | |
9436 | addi as, as, lo8 (label-.L1) | |
9437 | addmi as, as, mid8 (label-.L1) | |
9438 | wsr as, LEND | |
9439 | isync | |
9440 | rsr as, LCOUNT | |
9441 | addi as, as, 1 | |
9442 | .L1: | |
9443 | <<body>> | |
9444 | label: | |
9445 | */ | |
e0001a05 NC |
9446 | |
9447 | static void | |
7fa3d080 | 9448 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
9449 | { |
9450 | TInsn loop_insn; | |
9451 | TInsn addi_insn; | |
9452 | TInsn addmi_insn; | |
9453 | unsigned long target; | |
9454 | static xtensa_insnbuf insnbuf = NULL; | |
9455 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
9456 | xtensa_isa isa = xtensa_default_isa; | |
9457 | addressT loop_offset; | |
9458 | addressT addi_offset = 9; | |
9459 | addressT addmi_offset = 12; | |
43cd72b9 | 9460 | fragS *next_fragP; |
d77b99c9 | 9461 | int target_count; |
e0001a05 NC |
9462 | |
9463 | if (!insnbuf) | |
9464 | insnbuf = xtensa_insnbuf_alloc (isa); | |
9465 | ||
9466 | /* Get the loop offset. */ | |
43cd72b9 | 9467 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 9468 | |
43cd72b9 BW |
9469 | /* Validate that there really is a LOOP at the loop_offset. Because |
9470 | loops are not bundleable, we can assume that the instruction will be | |
9471 | in slot 0. */ | |
9472 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
9473 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
9474 | ||
9475 | assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); | |
e0001a05 NC |
9476 | addi_offset += loop_offset; |
9477 | addmi_offset += loop_offset; | |
9478 | ||
43cd72b9 | 9479 | assert (tinsn->ntok == 2); |
b08b5071 BW |
9480 | if (tinsn->tok[1].X_op == O_constant) |
9481 | target = tinsn->tok[1].X_add_number; | |
9482 | else if (tinsn->tok[1].X_op == O_symbol) | |
9483 | { | |
9484 | /* Find the fragment. */ | |
9485 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9486 | assert (S_GET_SEGMENT (sym) == segP | |
9487 | || S_GET_SEGMENT (sym) == absolute_section); | |
9488 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
9489 | } | |
9490 | else | |
9491 | { | |
9492 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
9493 | target = 0; | |
9494 | } | |
e0001a05 NC |
9495 | |
9496 | know (symbolP); | |
9497 | know (symbolP->sy_frag); | |
9498 | know (!(S_GET_SEGMENT (symbolP) == absolute_section) | |
9499 | || symbol_get_frag (symbolP) == &zero_address_frag); | |
9500 | ||
9501 | loop_length = target - (fragP->fr_address + fragP->fr_fix); | |
9502 | loop_length_hi = loop_length & ~0x0ff; | |
9503 | loop_length_lo = loop_length & 0x0ff; | |
9504 | if (loop_length_lo >= 128) | |
9505 | { | |
9506 | loop_length_lo -= 256; | |
9507 | loop_length_hi += 256; | |
9508 | } | |
9509 | ||
43cd72b9 | 9510 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
9511 | 32512. If the loop is larger than that, then we just fail. */ |
9512 | if (loop_length_hi > 32512) | |
9513 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9514 | _("loop too long for LOOP instruction")); | |
9515 | ||
43cd72b9 | 9516 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
e0001a05 NC |
9517 | assert (addi_insn.opcode == xtensa_addi_opcode); |
9518 | ||
43cd72b9 | 9519 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
e0001a05 NC |
9520 | assert (addmi_insn.opcode == xtensa_addmi_opcode); |
9521 | ||
9522 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
9523 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 9524 | |
e0001a05 | 9525 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
9526 | xtensa_insnbuf_to_chars |
9527 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
9528 | |
9529 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
9530 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
9531 | xtensa_insnbuf_to_chars |
9532 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
9533 | |
9534 | /* Walk through all of the frags from here to the loop end | |
9535 | and mark them as no_transform to keep them from being modified | |
9536 | by the linker. If we ever have a relocation for the | |
9537 | addi/addmi of the difference of two symbols we can remove this. */ | |
9538 | ||
9539 | target_count = 0; | |
9540 | for (next_fragP = fragP; next_fragP != NULL; | |
9541 | next_fragP = next_fragP->fr_next) | |
9542 | { | |
b08b5071 | 9543 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
9544 | if (next_fragP->tc_frag_data.is_loop_target) |
9545 | target_count++; | |
9546 | if (target_count == 2) | |
9547 | break; | |
9548 | } | |
e0001a05 NC |
9549 | } |
9550 | ||
b08b5071 BW |
9551 | \f |
9552 | /* A map that keeps information on a per-subsegment basis. This is | |
9553 | maintained during initial assembly, but is invalid once the | |
9554 | subsegments are smashed together. I.E., it cannot be used during | |
9555 | the relaxation. */ | |
e0001a05 | 9556 | |
b08b5071 | 9557 | typedef struct subseg_map_struct |
e0001a05 | 9558 | { |
b08b5071 BW |
9559 | /* the key */ |
9560 | segT seg; | |
9561 | subsegT subseg; | |
e0001a05 | 9562 | |
b08b5071 BW |
9563 | /* the data */ |
9564 | unsigned flags; | |
9565 | float total_freq; /* fall-through + branch target frequency */ | |
9566 | float target_freq; /* branch target frequency alone */ | |
9567 | ||
9568 | struct subseg_map_struct *next; | |
9569 | } subseg_map; | |
e0001a05 | 9570 | |
e0001a05 | 9571 | |
e0001a05 NC |
9572 | static subseg_map *sseg_map = NULL; |
9573 | ||
43cd72b9 | 9574 | static subseg_map * |
7fa3d080 | 9575 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
9576 | { |
9577 | subseg_map *subseg_e; | |
9578 | ||
9579 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 9580 | { |
43cd72b9 | 9581 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 9582 | break; |
e0001a05 | 9583 | } |
b08b5071 BW |
9584 | return subseg_e; |
9585 | } | |
9586 | ||
9587 | ||
9588 | static subseg_map * | |
9589 | add_subseg_info (segT seg, subsegT subseg) | |
9590 | { | |
9591 | subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); | |
43cd72b9 BW |
9592 | memset (subseg_e, 0, sizeof (subseg_map)); |
9593 | subseg_e->seg = seg; | |
9594 | subseg_e->subseg = subseg; | |
9595 | subseg_e->flags = 0; | |
9596 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
9597 | subseg_e->target_freq = 1.0; |
9598 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
9599 | subseg_e->next = sseg_map; |
9600 | sseg_map = subseg_e; | |
43cd72b9 BW |
9601 | return subseg_e; |
9602 | } | |
e0001a05 | 9603 | |
7fa3d080 BW |
9604 | |
9605 | static unsigned | |
9606 | get_last_insn_flags (segT seg, subsegT subseg) | |
9607 | { | |
9608 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9609 | if (subseg_e) |
9610 | return subseg_e->flags; | |
9611 | return 0; | |
7fa3d080 BW |
9612 | } |
9613 | ||
9614 | ||
43cd72b9 | 9615 | static void |
7fa3d080 BW |
9616 | set_last_insn_flags (segT seg, |
9617 | subsegT subseg, | |
9618 | unsigned fl, | |
9619 | bfd_boolean val) | |
43cd72b9 BW |
9620 | { |
9621 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9622 | if (! subseg_e) |
9623 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
9624 | if (val) |
9625 | subseg_e->flags |= fl; | |
9626 | else | |
9627 | subseg_e->flags &= ~fl; | |
9628 | } | |
9629 | ||
b08b5071 BW |
9630 | |
9631 | static float | |
9632 | get_subseg_total_freq (segT seg, subsegT subseg) | |
9633 | { | |
9634 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9635 | if (subseg_e) | |
9636 | return subseg_e->total_freq; | |
9637 | return 1.0; | |
9638 | } | |
9639 | ||
9640 | ||
9641 | static float | |
9642 | get_subseg_target_freq (segT seg, subsegT subseg) | |
9643 | { | |
9644 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9645 | if (subseg_e) | |
9646 | return subseg_e->target_freq; | |
9647 | return 1.0; | |
9648 | } | |
9649 | ||
9650 | ||
9651 | static void | |
9652 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
9653 | { | |
9654 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9655 | if (! subseg_e) | |
9656 | subseg_e = add_subseg_info (seg, subseg); | |
9657 | subseg_e->total_freq = total_f; | |
9658 | subseg_e->target_freq = target_f; | |
9659 | } | |
9660 | ||
e0001a05 NC |
9661 | \f |
9662 | /* Segment Lists and emit_state Stuff. */ | |
9663 | ||
e0001a05 | 9664 | static void |
7fa3d080 | 9665 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
9666 | { |
9667 | head = head->next; | |
9668 | while (head) | |
9669 | { | |
9670 | segT literal_section = head->seg; | |
9671 | ||
9672 | /* Move the literal section to the front of the section list. */ | |
9673 | assert (literal_section); | |
69852798 AM |
9674 | if (literal_section != stdoutput->sections) |
9675 | { | |
9676 | bfd_section_list_remove (stdoutput, literal_section); | |
9677 | bfd_section_list_prepend (stdoutput, literal_section); | |
9678 | } | |
e0001a05 NC |
9679 | head = head->next; |
9680 | } | |
9681 | } | |
9682 | ||
9683 | ||
7fa3d080 BW |
9684 | static void mark_literal_frags (seg_list *); |
9685 | ||
9686 | static void | |
9687 | xtensa_move_literals (void) | |
e0001a05 NC |
9688 | { |
9689 | seg_list *segment; | |
9690 | frchainS *frchain_from, *frchain_to; | |
9691 | fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after; | |
9692 | fragS **frag_splice; | |
9693 | emit_state state; | |
9694 | segT dest_seg; | |
9695 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 9696 | sym_list *lit; |
e0001a05 | 9697 | |
a7877748 | 9698 | mark_literal_frags (literal_head->next); |
e0001a05 NC |
9699 | |
9700 | if (use_literal_section) | |
9701 | return; | |
9702 | ||
74869ac7 | 9703 | for (segment = literal_head->next; segment; segment = segment->next) |
e0001a05 | 9704 | { |
74869ac7 BW |
9705 | /* Keep the literals for .init and .fini in separate sections. */ |
9706 | if (!strcmp (segment_name (segment->seg), INIT_SECTION_NAME) | |
9707 | || !strcmp (segment_name (segment->seg), FINI_SECTION_NAME)) | |
9708 | continue; | |
9709 | ||
e0001a05 NC |
9710 | frchain_from = seg_info (segment->seg)->frchainP; |
9711 | search_frag = frchain_from->frch_root; | |
9712 | literal_pool = NULL; | |
9713 | frchain_to = NULL; | |
9714 | frag_splice = &(frchain_from->frch_root); | |
9715 | ||
9716 | while (!search_frag->tc_frag_data.literal_frag) | |
9717 | { | |
9718 | assert (search_frag->fr_fix == 0 | |
9719 | || search_frag->fr_type == rs_align); | |
9720 | search_frag = search_frag->fr_next; | |
9721 | } | |
9722 | ||
9723 | assert (search_frag->tc_frag_data.literal_frag->fr_subtype | |
9724 | == RELAX_LITERAL_POOL_BEGIN); | |
9725 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
9726 | ||
9727 | /* Make sure that all the frags in this series are closed, and | |
9728 | that there is at least one left over of zero-size. This | |
9729 | prevents us from making a segment with an frchain without any | |
9730 | frags in it. */ | |
9731 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9732 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
9733 | last_frag = frag_now; |
9734 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9735 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 9736 | |
43cd72b9 | 9737 | while (search_frag != frag_now) |
e0001a05 NC |
9738 | { |
9739 | next_frag = search_frag->fr_next; | |
9740 | ||
43cd72b9 | 9741 | /* First, move the frag out of the literal section and |
e0001a05 NC |
9742 | to the appropriate place. */ |
9743 | if (search_frag->tc_frag_data.literal_frag) | |
9744 | { | |
9745 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9746 | assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); | |
dd49a749 BW |
9747 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9748 | assert (frchain_to); | |
e0001a05 NC |
9749 | } |
9750 | insert_after = literal_pool; | |
43cd72b9 | 9751 | |
e0001a05 NC |
9752 | while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END) |
9753 | insert_after = insert_after->fr_next; | |
9754 | ||
dd49a749 | 9755 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
43cd72b9 | 9756 | |
e0001a05 NC |
9757 | *frag_splice = next_frag; |
9758 | search_frag->fr_next = insert_after->fr_next; | |
9759 | insert_after->fr_next = search_frag; | |
9760 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
9761 | ||
9762 | /* Now move any fixups associated with this frag to the | |
9763 | right section. */ | |
9764 | fix = frchain_from->fix_root; | |
9765 | fix_splice = &(frchain_from->fix_root); | |
9766 | while (fix) | |
9767 | { | |
9768 | next_fix = fix->fx_next; | |
9769 | if (fix->fx_frag == search_frag) | |
9770 | { | |
9771 | *fix_splice = next_fix; | |
9772 | fix->fx_next = frchain_to->fix_root; | |
9773 | frchain_to->fix_root = fix; | |
9774 | if (frchain_to->fix_tail == NULL) | |
9775 | frchain_to->fix_tail = fix; | |
9776 | } | |
9777 | else | |
9778 | fix_splice = &(fix->fx_next); | |
9779 | fix = next_fix; | |
9780 | } | |
9781 | search_frag = next_frag; | |
9782 | } | |
9783 | ||
9784 | if (frchain_from->fix_root != NULL) | |
9785 | { | |
9786 | frchain_from = seg_info (segment->seg)->frchainP; | |
9787 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
9788 | ||
9789 | assert (frchain_from->fix_root == NULL); | |
9790 | } | |
9791 | frchain_from->fix_tail = NULL; | |
9792 | xtensa_restore_emit_state (&state); | |
e0001a05 NC |
9793 | } |
9794 | ||
82e7541d BW |
9795 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
9796 | for (lit = literal_syms; lit; lit = lit->next) | |
9797 | { | |
9798 | symbolS *lit_sym = lit->sym; | |
9799 | segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; | |
43cd72b9 BW |
9800 | if (dest_seg) |
9801 | S_SET_SEGMENT (lit_sym, dest_seg); | |
82e7541d | 9802 | } |
e0001a05 NC |
9803 | } |
9804 | ||
9805 | ||
a7877748 BW |
9806 | /* Walk over all the frags for segments in a list and mark them as |
9807 | containing literals. As clunky as this is, we can't rely on frag_var | |
9808 | and frag_variant to get called in all situations. */ | |
9809 | ||
9810 | static void | |
7fa3d080 | 9811 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
9812 | { |
9813 | frchainS *frchain_from; | |
9814 | fragS *search_frag; | |
9815 | ||
9816 | while (segment) | |
9817 | { | |
9818 | frchain_from = seg_info (segment->seg)->frchainP; | |
9819 | search_frag = frchain_from->frch_root; | |
c138bc38 | 9820 | while (search_frag) |
a7877748 BW |
9821 | { |
9822 | search_frag->tc_frag_data.is_literal = TRUE; | |
9823 | search_frag = search_frag->fr_next; | |
9824 | } | |
9825 | segment = segment->next; | |
9826 | } | |
9827 | } | |
9828 | ||
9829 | ||
e0001a05 | 9830 | static void |
7fa3d080 | 9831 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
9832 | { |
9833 | /* Move all of the sections in the section list to come | |
9834 | after "after" in the gnu segment list. */ | |
9835 | ||
9836 | head = head->next; | |
9837 | while (head) | |
9838 | { | |
9839 | segT literal_section = head->seg; | |
9840 | ||
9841 | /* Move the literal section after "after". */ | |
9842 | assert (literal_section); | |
9843 | if (literal_section != after) | |
9844 | { | |
69852798 AM |
9845 | bfd_section_list_remove (stdoutput, literal_section); |
9846 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
9847 | } |
9848 | ||
9849 | head = head->next; | |
9850 | } | |
9851 | } | |
9852 | ||
9853 | ||
9854 | /* Push all the literal segments to the end of the gnu list. */ | |
9855 | ||
7fa3d080 BW |
9856 | static void |
9857 | xtensa_reorder_segments (void) | |
e0001a05 NC |
9858 | { |
9859 | segT sec; | |
b08b5071 | 9860 | segT last_sec = 0; |
e0001a05 NC |
9861 | int old_count = 0; |
9862 | int new_count = 0; | |
9863 | ||
9864 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
9865 | { |
9866 | last_sec = sec; | |
9867 | old_count++; | |
9868 | } | |
e0001a05 NC |
9869 | |
9870 | /* Now that we have the last section, push all the literal | |
9871 | sections to the end. */ | |
e0001a05 | 9872 | xtensa_reorder_seg_list (literal_head, last_sec); |
e0001a05 NC |
9873 | |
9874 | /* Now perform the final error check. */ | |
9875 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
9876 | new_count++; | |
9877 | assert (new_count == old_count); | |
9878 | } | |
9879 | ||
9880 | ||
e0001a05 NC |
9881 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
9882 | correct location. Return a emit_state which can be passed to | |
9883 | xtensa_restore_emit_state to return to current fragment. */ | |
9884 | ||
7fa3d080 BW |
9885 | static void |
9886 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
9887 | { |
9888 | if (directive_state[directive_absolute_literals]) | |
9889 | { | |
74869ac7 BW |
9890 | segT lit4_seg = cache_literal_section (TRUE); |
9891 | xtensa_switch_section_emit_state (result, lit4_seg, 0); | |
43cd72b9 BW |
9892 | } |
9893 | else | |
9894 | xtensa_switch_to_non_abs_literal_fragment (result); | |
9895 | ||
9896 | /* Do a 4-byte align here. */ | |
9897 | frag_align (2, 0, 0); | |
9898 | record_alignment (now_seg, 2); | |
9899 | } | |
9900 | ||
9901 | ||
7fa3d080 BW |
9902 | static void |
9903 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 | 9904 | { |
e0001a05 NC |
9905 | static bfd_boolean recursive = FALSE; |
9906 | fragS *pool_location = get_literal_pool_location (now_seg); | |
74869ac7 | 9907 | segT lit_seg; |
c138bc38 | 9908 | bfd_boolean is_init = |
e0001a05 | 9909 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); |
c138bc38 | 9910 | bfd_boolean is_fini = |
e0001a05 | 9911 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); |
e0001a05 | 9912 | |
43cd72b9 BW |
9913 | if (pool_location == NULL |
9914 | && !use_literal_section | |
e0001a05 NC |
9915 | && !recursive |
9916 | && !is_init && ! is_fini) | |
9917 | { | |
43cd72b9 | 9918 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); |
74869ac7 BW |
9919 | |
9920 | /* When we mark a literal pool location, we want to put a frag in | |
9921 | the literal pool that points to it. But to do that, we want to | |
9922 | switch_to_literal_fragment. But literal sections don't have | |
9923 | literal pools, so their location is always null, so we would | |
9924 | recurse forever. This is kind of hacky, but it works. */ | |
9925 | ||
e0001a05 | 9926 | recursive = TRUE; |
61846f28 | 9927 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
9928 | recursive = FALSE; |
9929 | } | |
9930 | ||
74869ac7 BW |
9931 | lit_seg = cache_literal_section (FALSE); |
9932 | xtensa_switch_section_emit_state (result, lit_seg, 0); | |
e0001a05 | 9933 | |
43cd72b9 BW |
9934 | if (!use_literal_section |
9935 | && !is_init && !is_fini | |
9936 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
9937 | { |
9938 | /* Close whatever frag is there. */ | |
9939 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9940 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
9941 | frag_now->tc_frag_data.literal_frag = pool_location; |
9942 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9943 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 9944 | } |
e0001a05 NC |
9945 | } |
9946 | ||
9947 | ||
9948 | /* Call this function before emitting data into the literal section. | |
9949 | This is a helper function for xtensa_switch_to_literal_fragment. | |
9950 | This is similar to a .section new_now_seg subseg. */ | |
9951 | ||
7fa3d080 BW |
9952 | static void |
9953 | xtensa_switch_section_emit_state (emit_state *state, | |
9954 | segT new_now_seg, | |
9955 | subsegT new_now_subseg) | |
e0001a05 NC |
9956 | { |
9957 | state->name = now_seg->name; | |
9958 | state->now_seg = now_seg; | |
9959 | state->now_subseg = now_subseg; | |
9960 | state->generating_literals = generating_literals; | |
9961 | generating_literals++; | |
2b0210eb | 9962 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
9963 | } |
9964 | ||
9965 | ||
9966 | /* Use to restore the emitting into the normal place. */ | |
9967 | ||
7fa3d080 BW |
9968 | static void |
9969 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
9970 | { |
9971 | generating_literals = state->generating_literals; | |
2b0210eb | 9972 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
9973 | } |
9974 | ||
9975 | ||
74869ac7 | 9976 | /* Predicate function used to look up a section in a particular group. */ |
e0001a05 | 9977 | |
74869ac7 BW |
9978 | static bfd_boolean |
9979 | match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) | |
e0001a05 | 9980 | { |
74869ac7 BW |
9981 | const char *gname = inf; |
9982 | const char *group_name = elf_group_name (sec); | |
9983 | ||
9984 | return (group_name == gname | |
9985 | || (group_name != NULL | |
9986 | && gname != NULL | |
9987 | && strcmp (group_name, gname) == 0)); | |
9988 | } | |
e0001a05 | 9989 | |
e0001a05 | 9990 | |
74869ac7 BW |
9991 | /* Get the literal section to be used for the current text section. |
9992 | The result may be cached in the default_lit_sections structure. */ | |
9993 | ||
9994 | static segT | |
9995 | cache_literal_section (bfd_boolean use_abs_literals) | |
9996 | { | |
9997 | const char *text_name, *group_name = 0; | |
9998 | char *base_name, *name, *suffix; | |
9999 | segT *pcached; | |
10000 | segT seg, current_section; | |
10001 | int current_subsec; | |
10002 | bfd_boolean linkonce = FALSE; | |
10003 | ||
10004 | /* Save the current section/subsection. */ | |
10005 | current_section = now_seg; | |
10006 | current_subsec = now_subseg; | |
10007 | ||
10008 | /* Clear the cached values if they are no longer valid. */ | |
10009 | if (now_seg != default_lit_sections.current_text_seg) | |
b08b5071 | 10010 | { |
74869ac7 BW |
10011 | default_lit_sections.current_text_seg = now_seg; |
10012 | default_lit_sections.lit_seg = NULL; | |
10013 | default_lit_sections.lit4_seg = NULL; | |
10014 | } | |
10015 | ||
10016 | /* Check if the literal section is already cached. */ | |
10017 | if (use_abs_literals) | |
10018 | pcached = &default_lit_sections.lit4_seg; | |
10019 | else | |
10020 | pcached = &default_lit_sections.lit_seg; | |
10021 | ||
10022 | if (*pcached) | |
10023 | return *pcached; | |
10024 | ||
10025 | text_name = default_lit_sections.lit_prefix; | |
10026 | if (! text_name || ! *text_name) | |
10027 | { | |
10028 | text_name = segment_name (current_section); | |
10029 | group_name = elf_group_name (current_section); | |
10030 | linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; | |
10031 | } | |
10032 | ||
10033 | base_name = use_abs_literals ? ".lit4" : ".literal"; | |
10034 | if (group_name) | |
10035 | { | |
10036 | name = xmalloc (strlen (base_name) + strlen (group_name) + 2); | |
10037 | sprintf (name, "%s.%s", base_name, group_name); | |
10038 | } | |
10039 | else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) | |
10040 | { | |
10041 | suffix = strchr (text_name + linkonce_len, '.'); | |
10042 | ||
10043 | name = xmalloc (linkonce_len + strlen (base_name) + 1 | |
10044 | + (suffix ? strlen (suffix) : 0)); | |
10045 | strcpy (name, ".gnu.linkonce"); | |
10046 | strcat (name, base_name); | |
10047 | if (suffix) | |
10048 | strcat (name, suffix); | |
10049 | linkonce = TRUE; | |
10050 | } | |
10051 | else | |
10052 | { | |
10053 | /* If the section name ends with ".text", then replace that suffix | |
10054 | instead of appending an additional suffix. */ | |
10055 | size_t len = strlen (text_name); | |
10056 | if (len >= 5 && strcmp (text_name + len - 5, ".text") == 0) | |
10057 | len -= 5; | |
10058 | ||
10059 | name = xmalloc (len + strlen (base_name) + 1); | |
10060 | strcpy (name, text_name); | |
10061 | strcpy (name + len, base_name); | |
b08b5071 | 10062 | } |
e0001a05 | 10063 | |
74869ac7 BW |
10064 | /* Canonicalize section names to allow renaming literal sections. |
10065 | The group name, if any, came from the current text section and | |
10066 | has already been canonicalized. */ | |
10067 | name = tc_canonicalize_symbol_name (name); | |
10068 | ||
10069 | seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, | |
10070 | (void *) group_name); | |
10071 | if (! seg) | |
e0001a05 | 10072 | { |
74869ac7 BW |
10073 | flagword flags; |
10074 | ||
10075 | seg = subseg_force_new (name, 0); | |
10076 | ||
10077 | if (! use_abs_literals) | |
b08b5071 | 10078 | { |
74869ac7 | 10079 | /* Add the newly created literal segment to the list. */ |
b08b5071 BW |
10080 | seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); |
10081 | n->seg = seg; | |
74869ac7 BW |
10082 | n->next = literal_head->next; |
10083 | literal_head->next = n; | |
b08b5071 | 10084 | } |
74869ac7 BW |
10085 | |
10086 | flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD | |
10087 | | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) | |
10088 | | (use_abs_literals ? SEC_DATA : SEC_CODE)); | |
10089 | ||
10090 | elf_group_name (seg) = group_name; | |
10091 | ||
10092 | bfd_set_section_flags (stdoutput, seg, flags); | |
b08b5071 | 10093 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
10094 | } |
10095 | ||
74869ac7 | 10096 | *pcached = seg; |
b08b5071 | 10097 | subseg_set (current_section, current_subsec); |
74869ac7 | 10098 | return seg; |
e0001a05 NC |
10099 | } |
10100 | ||
43cd72b9 BW |
10101 | \f |
10102 | /* Property Tables Stuff. */ | |
10103 | ||
7fa3d080 BW |
10104 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
10105 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
10106 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
10107 | ||
10108 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
10109 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
10110 | ||
b08b5071 | 10111 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
10112 | static void xtensa_create_property_segments |
10113 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
10114 | static void xtensa_create_xproperty_segments | |
10115 | (frag_flags_fn, const char *, xt_section_type); | |
10116 | static segment_info_type *retrieve_segment_info (segT); | |
7fa3d080 BW |
10117 | static bfd_boolean section_has_property (segT, frag_predicate); |
10118 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
10119 | static void add_xt_block_frags | |
10120 | (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate); | |
10121 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); | |
10122 | static void xtensa_frag_flags_init (frag_flags *); | |
10123 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
10124 | static bfd_vma frag_flags_to_number (const frag_flags *); | |
10125 | static void add_xt_prop_frags | |
10126 | (segT, segT, xtensa_block_info **, frag_flags_fn); | |
10127 | ||
10128 | /* Set up property tables after relaxation. */ | |
10129 | ||
10130 | void | |
10131 | xtensa_post_relax_hook (void) | |
10132 | { | |
10133 | xtensa_move_seg_list_to_beginning (literal_head); | |
7fa3d080 BW |
10134 | |
10135 | xtensa_find_unmarked_state_frags (); | |
10136 | ||
b29757dc BW |
10137 | xtensa_create_property_segments (get_frag_is_literal, |
10138 | NULL, | |
10139 | XTENSA_LIT_SEC_NAME, | |
10140 | xt_literal_sec); | |
7fa3d080 BW |
10141 | xtensa_create_xproperty_segments (get_frag_property_flags, |
10142 | XTENSA_PROP_SEC_NAME, | |
10143 | xt_prop_sec); | |
10144 | ||
10145 | if (warn_unaligned_branch_targets) | |
10146 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
10147 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
10148 | } | |
10149 | ||
10150 | ||
43cd72b9 BW |
10151 | /* This function is only meaningful after xtensa_move_literals. */ |
10152 | ||
10153 | static bfd_boolean | |
7fa3d080 | 10154 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 BW |
10155 | { |
10156 | assert (fragP != NULL); | |
10157 | return fragP->tc_frag_data.is_literal; | |
10158 | } | |
10159 | ||
10160 | ||
43cd72b9 | 10161 | static void |
7fa3d080 BW |
10162 | xtensa_create_property_segments (frag_predicate property_function, |
10163 | frag_predicate end_property_function, | |
10164 | const char *section_name_base, | |
10165 | xt_section_type sec_type) | |
43cd72b9 BW |
10166 | { |
10167 | segT *seclist; | |
10168 | ||
10169 | /* Walk over all of the current segments. | |
10170 | Walk over each fragment | |
10171 | For each non-empty fragment, | |
10172 | Build a property record (append where possible). */ | |
10173 | ||
10174 | for (seclist = &stdoutput->sections; | |
10175 | seclist && *seclist; | |
10176 | seclist = &(*seclist)->next) | |
10177 | { | |
10178 | segT sec = *seclist; | |
10179 | flagword flags; | |
10180 | ||
10181 | flags = bfd_get_section_flags (stdoutput, sec); | |
10182 | if (flags & SEC_DEBUGGING) | |
10183 | continue; | |
10184 | if (!(flags & SEC_ALLOC)) | |
10185 | continue; | |
10186 | ||
10187 | if (section_has_property (sec, property_function)) | |
10188 | { | |
74869ac7 BW |
10189 | segT insn_sec = |
10190 | xtensa_get_property_section (sec, section_name_base); | |
43cd72b9 BW |
10191 | segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); |
10192 | xtensa_block_info **xt_blocks = | |
10193 | &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10194 | /* Walk over all of the frchains here and add new sections. */ | |
10195 | add_xt_block_frags (sec, insn_sec, xt_blocks, property_function, | |
10196 | end_property_function); | |
10197 | } | |
10198 | } | |
10199 | ||
10200 | /* Now we fill them out.... */ | |
10201 | ||
10202 | for (seclist = &stdoutput->sections; | |
10203 | seclist && *seclist; | |
10204 | seclist = &(*seclist)->next) | |
10205 | { | |
10206 | segment_info_type *seginfo; | |
10207 | xtensa_block_info *block; | |
10208 | segT sec = *seclist; | |
10209 | ||
10210 | seginfo = seg_info (sec); | |
10211 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10212 | ||
10213 | if (block) | |
10214 | { | |
10215 | xtensa_block_info *cur_block; | |
10216 | /* This is a section with some data. */ | |
10217 | int num_recs = 0; | |
d77b99c9 | 10218 | bfd_size_type rec_size; |
43cd72b9 BW |
10219 | |
10220 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10221 | num_recs++; | |
10222 | ||
10223 | rec_size = num_recs * 8; | |
10224 | bfd_set_section_size (stdoutput, sec, rec_size); | |
10225 | ||
10226 | /* In order to make this work with the assembler, we have to | |
10227 | build some frags and then build the "fixups" for it. It | |
10228 | would be easier to just set the contents then set the | |
10229 | arlents. */ | |
10230 | ||
10231 | if (num_recs) | |
10232 | { | |
10233 | /* Allocate a fragment and leak it. */ | |
10234 | fragS *fragP; | |
d77b99c9 | 10235 | bfd_size_type frag_size; |
43cd72b9 BW |
10236 | fixS *fixes; |
10237 | frchainS *frchainP; | |
10238 | int i; | |
10239 | char *frag_data; | |
10240 | ||
10241 | frag_size = sizeof (fragS) + rec_size; | |
10242 | fragP = (fragS *) xmalloc (frag_size); | |
e0001a05 | 10243 | |
43cd72b9 BW |
10244 | memset (fragP, 0, frag_size); |
10245 | fragP->fr_address = 0; | |
10246 | fragP->fr_next = NULL; | |
10247 | fragP->fr_fix = rec_size; | |
10248 | fragP->fr_var = 0; | |
10249 | fragP->fr_type = rs_fill; | |
10250 | /* The rest are zeros. */ | |
e0001a05 | 10251 | |
43cd72b9 BW |
10252 | frchainP = seginfo->frchainP; |
10253 | frchainP->frch_root = fragP; | |
10254 | frchainP->frch_last = fragP; | |
e0001a05 | 10255 | |
43cd72b9 BW |
10256 | fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); |
10257 | memset (fixes, 0, sizeof (fixS) * num_recs); | |
e0001a05 | 10258 | |
43cd72b9 BW |
10259 | seginfo->fix_root = fixes; |
10260 | seginfo->fix_tail = &fixes[num_recs - 1]; | |
10261 | cur_block = block; | |
10262 | frag_data = &fragP->fr_literal[0]; | |
10263 | for (i = 0; i < num_recs; i++) | |
10264 | { | |
10265 | fixS *fix = &fixes[i]; | |
10266 | assert (cur_block); | |
e0001a05 | 10267 | |
43cd72b9 BW |
10268 | /* Write the fixup. */ |
10269 | if (i != num_recs - 1) | |
10270 | fix->fx_next = &fixes[i + 1]; | |
10271 | else | |
10272 | fix->fx_next = NULL; | |
10273 | fix->fx_size = 4; | |
10274 | fix->fx_done = 0; | |
10275 | fix->fx_frag = fragP; | |
10276 | fix->fx_where = i * 8; | |
10277 | fix->fx_addsy = section_symbol (cur_block->sec); | |
10278 | fix->fx_offset = cur_block->offset; | |
10279 | fix->fx_r_type = BFD_RELOC_32; | |
10280 | fix->fx_file = "Internal Assembly"; | |
10281 | fix->fx_line = 0; | |
e0001a05 | 10282 | |
43cd72b9 BW |
10283 | /* Write the length. */ |
10284 | md_number_to_chars (&frag_data[4 + 8 * i], | |
10285 | cur_block->size, 4); | |
10286 | cur_block = cur_block->next; | |
10287 | } | |
10288 | } | |
10289 | } | |
10290 | } | |
e0001a05 NC |
10291 | } |
10292 | ||
10293 | ||
7fa3d080 BW |
10294 | static void |
10295 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
10296 | const char *section_name_base, | |
10297 | xt_section_type sec_type) | |
e0001a05 NC |
10298 | { |
10299 | segT *seclist; | |
10300 | ||
10301 | /* Walk over all of the current segments. | |
43cd72b9 BW |
10302 | Walk over each fragment. |
10303 | For each fragment that has instructions, | |
10304 | build an instruction record (append where possible). */ | |
e0001a05 NC |
10305 | |
10306 | for (seclist = &stdoutput->sections; | |
10307 | seclist && *seclist; | |
10308 | seclist = &(*seclist)->next) | |
10309 | { | |
10310 | segT sec = *seclist; | |
43cd72b9 BW |
10311 | flagword flags; |
10312 | ||
10313 | flags = bfd_get_section_flags (stdoutput, sec); | |
6624cbde BW |
10314 | if ((flags & SEC_DEBUGGING) |
10315 | || !(flags & SEC_ALLOC) | |
10316 | || (flags & SEC_MERGE)) | |
43cd72b9 BW |
10317 | continue; |
10318 | ||
10319 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 10320 | { |
74869ac7 BW |
10321 | segT insn_sec = |
10322 | xtensa_get_property_section (sec, section_name_base); | |
e0001a05 | 10323 | segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); |
43cd72b9 | 10324 | xtensa_block_info **xt_blocks = |
e0001a05 NC |
10325 | &xt_seg_info->tc_segment_info_data.blocks[sec_type]; |
10326 | /* Walk over all of the frchains here and add new sections. */ | |
43cd72b9 | 10327 | add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn); |
e0001a05 NC |
10328 | } |
10329 | } | |
10330 | ||
10331 | /* Now we fill them out.... */ | |
10332 | ||
10333 | for (seclist = &stdoutput->sections; | |
10334 | seclist && *seclist; | |
10335 | seclist = &(*seclist)->next) | |
10336 | { | |
10337 | segment_info_type *seginfo; | |
10338 | xtensa_block_info *block; | |
10339 | segT sec = *seclist; | |
43cd72b9 | 10340 | |
e0001a05 NC |
10341 | seginfo = seg_info (sec); |
10342 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10343 | ||
10344 | if (block) | |
10345 | { | |
10346 | xtensa_block_info *cur_block; | |
10347 | /* This is a section with some data. */ | |
43cd72b9 | 10348 | int num_recs = 0; |
d77b99c9 | 10349 | bfd_size_type rec_size; |
e0001a05 NC |
10350 | |
10351 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10352 | num_recs++; | |
10353 | ||
43cd72b9 | 10354 | rec_size = num_recs * (8 + 4); |
e0001a05 NC |
10355 | bfd_set_section_size (stdoutput, sec, rec_size); |
10356 | ||
43cd72b9 BW |
10357 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
10358 | ||
10359 | /* In order to make this work with the assembler, we have to build | |
10360 | some frags then build the "fixups" for it. It would be easier to | |
10361 | just set the contents then set the arlents. */ | |
e0001a05 NC |
10362 | |
10363 | if (num_recs) | |
10364 | { | |
43cd72b9 | 10365 | /* Allocate a fragment and (unfortunately) leak it. */ |
e0001a05 | 10366 | fragS *fragP; |
d77b99c9 | 10367 | bfd_size_type frag_size; |
e0001a05 NC |
10368 | fixS *fixes; |
10369 | frchainS *frchainP; | |
43cd72b9 | 10370 | int i; |
e0001a05 NC |
10371 | char *frag_data; |
10372 | ||
10373 | frag_size = sizeof (fragS) + rec_size; | |
10374 | fragP = (fragS *) xmalloc (frag_size); | |
10375 | ||
10376 | memset (fragP, 0, frag_size); | |
10377 | fragP->fr_address = 0; | |
10378 | fragP->fr_next = NULL; | |
10379 | fragP->fr_fix = rec_size; | |
10380 | fragP->fr_var = 0; | |
10381 | fragP->fr_type = rs_fill; | |
43cd72b9 | 10382 | /* The rest are zeros. */ |
e0001a05 NC |
10383 | |
10384 | frchainP = seginfo->frchainP; | |
10385 | frchainP->frch_root = fragP; | |
10386 | frchainP->frch_last = fragP; | |
10387 | ||
10388 | fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); | |
10389 | memset (fixes, 0, sizeof (fixS) * num_recs); | |
10390 | ||
10391 | seginfo->fix_root = fixes; | |
10392 | seginfo->fix_tail = &fixes[num_recs - 1]; | |
10393 | cur_block = block; | |
10394 | frag_data = &fragP->fr_literal[0]; | |
10395 | for (i = 0; i < num_recs; i++) | |
10396 | { | |
10397 | fixS *fix = &fixes[i]; | |
10398 | assert (cur_block); | |
10399 | ||
10400 | /* Write the fixup. */ | |
10401 | if (i != num_recs - 1) | |
10402 | fix->fx_next = &fixes[i + 1]; | |
10403 | else | |
10404 | fix->fx_next = NULL; | |
10405 | fix->fx_size = 4; | |
10406 | fix->fx_done = 0; | |
10407 | fix->fx_frag = fragP; | |
43cd72b9 | 10408 | fix->fx_where = i * (8 + 4); |
e0001a05 NC |
10409 | fix->fx_addsy = section_symbol (cur_block->sec); |
10410 | fix->fx_offset = cur_block->offset; | |
10411 | fix->fx_r_type = BFD_RELOC_32; | |
10412 | fix->fx_file = "Internal Assembly"; | |
10413 | fix->fx_line = 0; | |
10414 | ||
10415 | /* Write the length. */ | |
43cd72b9 | 10416 | md_number_to_chars (&frag_data[4 + (8+4) * i], |
e0001a05 | 10417 | cur_block->size, 4); |
43cd72b9 BW |
10418 | md_number_to_chars (&frag_data[8 + (8+4) * i], |
10419 | frag_flags_to_number (&cur_block->flags), | |
10420 | 4); | |
e0001a05 NC |
10421 | cur_block = cur_block->next; |
10422 | } | |
10423 | } | |
10424 | } | |
10425 | } | |
10426 | } | |
10427 | ||
10428 | ||
7fa3d080 BW |
10429 | static segment_info_type * |
10430 | retrieve_segment_info (segT seg) | |
e0001a05 NC |
10431 | { |
10432 | segment_info_type *seginfo; | |
10433 | seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg); | |
10434 | if (!seginfo) | |
10435 | { | |
10436 | frchainS *frchainP; | |
10437 | ||
10438 | seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo)); | |
7fa3d080 | 10439 | memset ((void *) seginfo, 0, sizeof (*seginfo)); |
e0001a05 NC |
10440 | seginfo->fix_root = NULL; |
10441 | seginfo->fix_tail = NULL; | |
10442 | seginfo->bfd_section = seg; | |
10443 | seginfo->sym = 0; | |
10444 | /* We will not be dealing with these, only our special ones. */ | |
65ec77d2 | 10445 | bfd_set_section_userdata (stdoutput, seg, (void *) seginfo); |
e0001a05 NC |
10446 | |
10447 | frchainP = (frchainS *) xmalloc (sizeof (frchainS)); | |
10448 | frchainP->frch_root = NULL; | |
10449 | frchainP->frch_last = NULL; | |
10450 | frchainP->frch_next = NULL; | |
e0001a05 NC |
10451 | frchainP->frch_subseg = 0; |
10452 | frchainP->fix_root = NULL; | |
10453 | frchainP->fix_tail = NULL; | |
10454 | /* Do not init the objstack. */ | |
10455 | /* obstack_begin (&frchainP->frch_obstack, chunksize); */ | |
10456 | /* frchainP->frch_frag_now = fragP; */ | |
10457 | frchainP->frch_frag_now = NULL; | |
10458 | ||
10459 | seginfo->frchainP = frchainP; | |
10460 | } | |
10461 | ||
10462 | return seginfo; | |
10463 | } | |
10464 | ||
10465 | ||
7fa3d080 BW |
10466 | static bfd_boolean |
10467 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
10468 | { |
10469 | segment_info_type *seginfo = seg_info (sec); | |
10470 | fragS *fragP; | |
10471 | ||
10472 | if (seginfo && seginfo->frchainP) | |
10473 | { | |
10474 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10475 | { | |
10476 | if (property_function (fragP) | |
10477 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10478 | return TRUE; | |
10479 | } | |
10480 | } | |
10481 | return FALSE; | |
10482 | } | |
10483 | ||
10484 | ||
7fa3d080 BW |
10485 | static bfd_boolean |
10486 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
10487 | { |
10488 | segment_info_type *seginfo = seg_info (sec); | |
10489 | fragS *fragP; | |
10490 | ||
10491 | if (seginfo && seginfo->frchainP) | |
10492 | { | |
10493 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10494 | { | |
10495 | frag_flags prop_flags; | |
10496 | property_function (fragP, &prop_flags); | |
10497 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
10498 | return TRUE; | |
10499 | } | |
10500 | } | |
10501 | return FALSE; | |
10502 | } | |
10503 | ||
10504 | ||
e0001a05 NC |
10505 | /* Two types of block sections exist right now: literal and insns. */ |
10506 | ||
7fa3d080 BW |
10507 | static void |
10508 | add_xt_block_frags (segT sec, | |
10509 | segT xt_block_sec, | |
10510 | xtensa_block_info **xt_block, | |
10511 | frag_predicate property_function, | |
10512 | frag_predicate end_property_function) | |
e0001a05 NC |
10513 | { |
10514 | segment_info_type *seg_info; | |
10515 | segment_info_type *xt_seg_info; | |
10516 | bfd_vma seg_offset; | |
10517 | fragS *fragP; | |
10518 | ||
10519 | xt_seg_info = retrieve_segment_info (xt_block_sec); | |
10520 | seg_info = retrieve_segment_info (sec); | |
10521 | ||
10522 | /* Build it if needed. */ | |
10523 | while (*xt_block != NULL) | |
10524 | xt_block = &(*xt_block)->next; | |
10525 | /* We are either at NULL at the beginning or at the end. */ | |
10526 | ||
10527 | /* Walk through the frags. */ | |
10528 | seg_offset = 0; | |
10529 | ||
10530 | if (seg_info->frchainP) | |
10531 | { | |
10532 | for (fragP = seg_info->frchainP->frch_root; | |
10533 | fragP; | |
10534 | fragP = fragP->fr_next) | |
10535 | { | |
10536 | if (property_function (fragP) | |
10537 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10538 | { | |
10539 | if (*xt_block != NULL) | |
10540 | { | |
10541 | if ((*xt_block)->offset + (*xt_block)->size | |
10542 | == fragP->fr_address) | |
10543 | (*xt_block)->size += fragP->fr_fix; | |
10544 | else | |
10545 | xt_block = &((*xt_block)->next); | |
10546 | } | |
10547 | if (*xt_block == NULL) | |
10548 | { | |
43cd72b9 BW |
10549 | xtensa_block_info *new_block = (xtensa_block_info *) |
10550 | xmalloc (sizeof (xtensa_block_info)); | |
10551 | new_block->sec = sec; | |
10552 | new_block->offset = fragP->fr_address; | |
10553 | new_block->size = fragP->fr_fix; | |
10554 | new_block->next = NULL; | |
10555 | xtensa_frag_flags_init (&new_block->flags); | |
10556 | *xt_block = new_block; | |
10557 | } | |
10558 | if (end_property_function | |
10559 | && end_property_function (fragP)) | |
10560 | { | |
10561 | xt_block = &((*xt_block)->next); | |
10562 | } | |
10563 | } | |
10564 | } | |
10565 | } | |
10566 | } | |
10567 | ||
10568 | ||
10569 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
10570 | ||
7fa3d080 BW |
10571 | static bfd_boolean |
10572 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
10573 | { |
10574 | if (prop_flags->is_literal | |
10575 | || prop_flags->is_insn | |
10576 | || prop_flags->is_data | |
10577 | || prop_flags->is_unreachable) | |
10578 | return FALSE; | |
10579 | return TRUE; | |
10580 | } | |
10581 | ||
10582 | ||
7fa3d080 BW |
10583 | static void |
10584 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
10585 | { |
10586 | memset (prop_flags, 0, sizeof (frag_flags)); | |
10587 | } | |
10588 | ||
10589 | ||
7fa3d080 BW |
10590 | static void |
10591 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
10592 | { |
10593 | xtensa_frag_flags_init (prop_flags); | |
10594 | if (fragP->tc_frag_data.is_literal) | |
10595 | prop_flags->is_literal = TRUE; | |
10596 | if (fragP->tc_frag_data.is_unreachable) | |
7fa3d080 | 10597 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
10598 | else if (fragP->tc_frag_data.is_insn) |
10599 | { | |
10600 | prop_flags->is_insn = TRUE; | |
10601 | if (fragP->tc_frag_data.is_loop_target) | |
10602 | prop_flags->insn.is_loop_target = TRUE; | |
10603 | if (fragP->tc_frag_data.is_branch_target) | |
10604 | prop_flags->insn.is_branch_target = TRUE; | |
10605 | if (fragP->tc_frag_data.is_specific_opcode | |
10606 | || fragP->tc_frag_data.is_no_transform) | |
10607 | prop_flags->insn.is_no_transform = TRUE; | |
10608 | if (fragP->tc_frag_data.is_no_density) | |
10609 | prop_flags->insn.is_no_density = TRUE; | |
10610 | if (fragP->tc_frag_data.use_absolute_literals) | |
10611 | prop_flags->insn.is_abslit = TRUE; | |
10612 | } | |
10613 | if (fragP->tc_frag_data.is_align) | |
10614 | { | |
10615 | prop_flags->is_align = TRUE; | |
10616 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
10617 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10618 | prop_flags->is_data = TRUE; | |
10619 | } | |
10620 | } | |
10621 | ||
10622 | ||
7fa3d080 BW |
10623 | static bfd_vma |
10624 | frag_flags_to_number (const frag_flags *prop_flags) | |
43cd72b9 BW |
10625 | { |
10626 | bfd_vma num = 0; | |
10627 | if (prop_flags->is_literal) | |
10628 | num |= XTENSA_PROP_LITERAL; | |
10629 | if (prop_flags->is_insn) | |
10630 | num |= XTENSA_PROP_INSN; | |
10631 | if (prop_flags->is_data) | |
10632 | num |= XTENSA_PROP_DATA; | |
10633 | if (prop_flags->is_unreachable) | |
10634 | num |= XTENSA_PROP_UNREACHABLE; | |
10635 | if (prop_flags->insn.is_loop_target) | |
10636 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
10637 | if (prop_flags->insn.is_branch_target) | |
10638 | { | |
10639 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
10640 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
10641 | } | |
10642 | ||
10643 | if (prop_flags->insn.is_no_density) | |
10644 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
10645 | if (prop_flags->insn.is_no_transform) | |
10646 | num |= XTENSA_PROP_INSN_NO_TRANSFORM; | |
10647 | if (prop_flags->insn.is_no_reorder) | |
10648 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
10649 | if (prop_flags->insn.is_abslit) | |
10650 | num |= XTENSA_PROP_INSN_ABSLIT; | |
10651 | ||
10652 | if (prop_flags->is_align) | |
10653 | { | |
10654 | num |= XTENSA_PROP_ALIGN; | |
10655 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
10656 | } | |
10657 | ||
10658 | return num; | |
10659 | } | |
10660 | ||
10661 | ||
10662 | static bfd_boolean | |
7fa3d080 BW |
10663 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
10664 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
10665 | { |
10666 | /* Cannot combine with an end marker. */ | |
10667 | ||
10668 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
10669 | return FALSE; | |
10670 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
10671 | return FALSE; | |
10672 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
10673 | return FALSE; | |
10674 | ||
10675 | if (prop_flags_1->is_insn) | |
10676 | { | |
10677 | /* Properties of the beginning of the frag. */ | |
10678 | if (prop_flags_2->insn.is_loop_target) | |
10679 | return FALSE; | |
10680 | if (prop_flags_2->insn.is_branch_target) | |
10681 | return FALSE; | |
10682 | if (prop_flags_1->insn.is_no_density != | |
10683 | prop_flags_2->insn.is_no_density) | |
10684 | return FALSE; | |
10685 | if (prop_flags_1->insn.is_no_transform != | |
10686 | prop_flags_2->insn.is_no_transform) | |
10687 | return FALSE; | |
10688 | if (prop_flags_1->insn.is_no_reorder != | |
10689 | prop_flags_2->insn.is_no_reorder) | |
10690 | return FALSE; | |
10691 | if (prop_flags_1->insn.is_abslit != | |
10692 | prop_flags_2->insn.is_abslit) | |
10693 | return FALSE; | |
10694 | } | |
10695 | ||
10696 | if (prop_flags_1->is_align) | |
10697 | return FALSE; | |
10698 | ||
10699 | return TRUE; | |
10700 | } | |
10701 | ||
10702 | ||
7fa3d080 BW |
10703 | static bfd_vma |
10704 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
10705 | { |
10706 | bfd_vma end_addr; | |
d77b99c9 | 10707 | unsigned align_bits; |
43cd72b9 BW |
10708 | |
10709 | if (!xt_block->flags.is_align) | |
10710 | return xt_block->size; | |
10711 | ||
10712 | end_addr = xt_block->offset + xt_block->size; | |
10713 | align_bits = xt_block->flags.alignment; | |
10714 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
10715 | return end_addr - xt_block->offset; | |
10716 | } | |
10717 | ||
10718 | ||
10719 | static bfd_boolean | |
7fa3d080 BW |
10720 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
10721 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
10722 | { |
10723 | if (xt_block->sec != xt_block_2->sec) | |
10724 | return FALSE; | |
10725 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
10726 | != xt_block_2->offset) | |
10727 | return FALSE; | |
10728 | ||
10729 | if (xt_block_2->size == 0 | |
10730 | && (!xt_block_2->flags.is_unreachable | |
10731 | || xt_block->flags.is_unreachable)) | |
10732 | { | |
10733 | if (xt_block_2->flags.is_align | |
10734 | && xt_block->flags.is_align) | |
10735 | { | |
10736 | /* Nothing needed. */ | |
10737 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
10738 | return TRUE; | |
10739 | } | |
10740 | else | |
10741 | { | |
10742 | if (xt_block_2->flags.is_align) | |
10743 | { | |
10744 | /* Push alignment to previous entry. */ | |
10745 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
10746 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10747 | } | |
10748 | return TRUE; | |
10749 | } | |
10750 | } | |
10751 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
10752 | &xt_block_2->flags)) | |
10753 | return FALSE; | |
10754 | ||
10755 | xt_block->size += xt_block_2->size; | |
10756 | ||
10757 | if (xt_block_2->flags.is_align) | |
10758 | { | |
10759 | xt_block->flags.is_align = TRUE; | |
10760 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10761 | } | |
10762 | ||
10763 | return TRUE; | |
10764 | } | |
10765 | ||
10766 | ||
7fa3d080 BW |
10767 | static void |
10768 | add_xt_prop_frags (segT sec, | |
10769 | segT xt_block_sec, | |
10770 | xtensa_block_info **xt_block, | |
10771 | frag_flags_fn property_function) | |
43cd72b9 BW |
10772 | { |
10773 | segment_info_type *seg_info; | |
10774 | segment_info_type *xt_seg_info; | |
10775 | bfd_vma seg_offset; | |
10776 | fragS *fragP; | |
10777 | ||
10778 | xt_seg_info = retrieve_segment_info (xt_block_sec); | |
10779 | seg_info = retrieve_segment_info (sec); | |
10780 | /* Build it if needed. */ | |
10781 | while (*xt_block != NULL) | |
10782 | { | |
10783 | xt_block = &(*xt_block)->next; | |
10784 | } | |
10785 | /* We are either at NULL at the beginning or at the end. */ | |
10786 | ||
10787 | /* Walk through the frags. */ | |
10788 | seg_offset = 0; | |
10789 | ||
10790 | if (seg_info->frchainP) | |
10791 | { | |
10792 | for (fragP = seg_info->frchainP->frch_root; fragP; | |
10793 | fragP = fragP->fr_next) | |
10794 | { | |
10795 | xtensa_block_info tmp_block; | |
10796 | tmp_block.sec = sec; | |
10797 | tmp_block.offset = fragP->fr_address; | |
10798 | tmp_block.size = fragP->fr_fix; | |
10799 | tmp_block.next = NULL; | |
10800 | property_function (fragP, &tmp_block.flags); | |
10801 | ||
10802 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
10803 | /* && fragP->fr_fix != 0) */ | |
10804 | { | |
10805 | if ((*xt_block) == NULL | |
10806 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
10807 | { | |
10808 | xtensa_block_info *new_block; | |
10809 | if ((*xt_block) != NULL) | |
10810 | xt_block = &(*xt_block)->next; | |
10811 | new_block = (xtensa_block_info *) | |
10812 | xmalloc (sizeof (xtensa_block_info)); | |
10813 | *new_block = tmp_block; | |
10814 | *xt_block = new_block; | |
10815 | } | |
10816 | } | |
10817 | } | |
10818 | } | |
10819 | } | |
10820 | ||
10821 | \f | |
10822 | /* op_placement_info_table */ | |
10823 | ||
10824 | /* op_placement_info makes it easier to determine which | |
10825 | ops can go in which slots. */ | |
10826 | ||
10827 | static void | |
7fa3d080 | 10828 | init_op_placement_info_table (void) |
43cd72b9 BW |
10829 | { |
10830 | xtensa_isa isa = xtensa_default_isa; | |
10831 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
10832 | xtensa_opcode opcode; | |
10833 | xtensa_format fmt; | |
10834 | int slot; | |
10835 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
10836 | ||
10837 | op_placement_table = (op_placement_info_table) | |
10838 | xmalloc (sizeof (op_placement_info) * num_opcodes); | |
10839 | assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); | |
10840 | ||
10841 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
10842 | { | |
10843 | op_placement_info *opi = &op_placement_table[opcode]; | |
10844 | /* FIXME: Make tinsn allocation dynamic. */ | |
10845 | if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS) | |
10846 | as_fatal (_("too many operands in instruction")); | |
43cd72b9 BW |
10847 | opi->narrowest = XTENSA_UNDEFINED; |
10848 | opi->narrowest_size = 0x7F; | |
b2d179be | 10849 | opi->narrowest_slot = 0; |
43cd72b9 BW |
10850 | opi->formats = 0; |
10851 | opi->num_formats = 0; | |
10852 | opi->issuef = 0; | |
10853 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
10854 | { | |
10855 | opi->slots[fmt] = 0; | |
10856 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
10857 | { | |
10858 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
10859 | { | |
10860 | int fmt_length = xtensa_format_length (isa, fmt); | |
10861 | opi->issuef++; | |
10862 | set_bit (fmt, opi->formats); | |
10863 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
10864 | if (fmt_length < opi->narrowest_size |
10865 | || (fmt_length == opi->narrowest_size | |
10866 | && (xtensa_format_num_slots (isa, fmt) | |
10867 | < xtensa_format_num_slots (isa, | |
10868 | opi->narrowest)))) | |
43cd72b9 BW |
10869 | { |
10870 | opi->narrowest = fmt; | |
10871 | opi->narrowest_size = fmt_length; | |
b2d179be | 10872 | opi->narrowest_slot = slot; |
43cd72b9 | 10873 | } |
e0001a05 NC |
10874 | } |
10875 | } | |
43cd72b9 BW |
10876 | if (opi->formats) |
10877 | opi->num_formats++; | |
e0001a05 NC |
10878 | } |
10879 | } | |
43cd72b9 BW |
10880 | xtensa_insnbuf_free (isa, ibuf); |
10881 | } | |
10882 | ||
10883 | ||
10884 | bfd_boolean | |
7fa3d080 | 10885 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
10886 | { |
10887 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
10888 | } | |
10889 | ||
10890 | ||
10891 | /* If the opcode is available in a single slot format, return its size. */ | |
10892 | ||
7fa3d080 BW |
10893 | static int |
10894 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 10895 | { |
b2d179be | 10896 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
10897 | } |
10898 | ||
10899 | ||
7fa3d080 BW |
10900 | static xtensa_format |
10901 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 10902 | { |
b2d179be BW |
10903 | return op_placement_table[opcode].narrowest; |
10904 | } | |
10905 | ||
10906 | ||
10907 | static int | |
10908 | xg_get_single_slot (xtensa_opcode opcode) | |
10909 | { | |
10910 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
10911 | } |
10912 | ||
10913 | \f | |
10914 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
10915 | ||
10916 | void | |
7fa3d080 | 10917 | istack_init (IStack *stack) |
e0001a05 NC |
10918 | { |
10919 | memset (stack, 0, sizeof (IStack)); | |
10920 | stack->ninsn = 0; | |
10921 | } | |
10922 | ||
10923 | ||
10924 | bfd_boolean | |
7fa3d080 | 10925 | istack_empty (IStack *stack) |
e0001a05 NC |
10926 | { |
10927 | return (stack->ninsn == 0); | |
10928 | } | |
10929 | ||
10930 | ||
10931 | bfd_boolean | |
7fa3d080 | 10932 | istack_full (IStack *stack) |
e0001a05 NC |
10933 | { |
10934 | return (stack->ninsn == MAX_ISTACK); | |
10935 | } | |
10936 | ||
10937 | ||
10938 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 10939 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
10940 | |
10941 | TInsn * | |
7fa3d080 | 10942 | istack_top (IStack *stack) |
e0001a05 NC |
10943 | { |
10944 | int rec = stack->ninsn - 1; | |
10945 | assert (!istack_empty (stack)); | |
10946 | return &stack->insn[rec]; | |
10947 | } | |
10948 | ||
10949 | ||
10950 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 10951 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
10952 | |
10953 | void | |
7fa3d080 | 10954 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
10955 | { |
10956 | int rec = stack->ninsn; | |
10957 | assert (!istack_full (stack)); | |
43cd72b9 | 10958 | stack->insn[rec] = *insn; |
e0001a05 NC |
10959 | stack->ninsn++; |
10960 | } | |
10961 | ||
10962 | ||
10963 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 10964 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
10965 | |
10966 | TInsn * | |
7fa3d080 | 10967 | istack_push_space (IStack *stack) |
e0001a05 NC |
10968 | { |
10969 | int rec = stack->ninsn; | |
10970 | TInsn *insn; | |
10971 | assert (!istack_full (stack)); | |
10972 | insn = &stack->insn[rec]; | |
10973 | memset (insn, 0, sizeof (TInsn)); | |
10974 | stack->ninsn++; | |
10975 | return insn; | |
10976 | } | |
10977 | ||
10978 | ||
10979 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 10980 | istack_empty () returns TRUE. */ |
e0001a05 NC |
10981 | |
10982 | void | |
7fa3d080 | 10983 | istack_pop (IStack *stack) |
e0001a05 NC |
10984 | { |
10985 | int rec = stack->ninsn - 1; | |
10986 | assert (!istack_empty (stack)); | |
10987 | stack->ninsn--; | |
10988 | memset (&stack->insn[rec], 0, sizeof (TInsn)); | |
10989 | } | |
10990 | ||
10991 | \f | |
10992 | /* TInsn functions. */ | |
10993 | ||
10994 | void | |
7fa3d080 | 10995 | tinsn_init (TInsn *dst) |
e0001a05 NC |
10996 | { |
10997 | memset (dst, 0, sizeof (TInsn)); | |
10998 | } | |
10999 | ||
11000 | ||
e0001a05 NC |
11001 | /* Get the ``num''th token of the TInsn. |
11002 | It is illegal to call this if num > insn->ntoks. */ | |
11003 | ||
11004 | expressionS * | |
7fa3d080 | 11005 | tinsn_get_tok (TInsn *insn, int num) |
e0001a05 NC |
11006 | { |
11007 | assert (num < insn->ntok); | |
11008 | return &insn->tok[num]; | |
11009 | } | |
11010 | ||
11011 | ||
43cd72b9 | 11012 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
11013 | |
11014 | static bfd_boolean | |
7fa3d080 | 11015 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
11016 | { |
11017 | int i; | |
11018 | int n = insn->ntok; | |
11019 | ||
11020 | assert (insn->insn_type == ITYPE_INSN); | |
11021 | ||
11022 | for (i = 0; i < n; ++i) | |
11023 | { | |
11024 | switch (insn->tok[i].X_op) | |
11025 | { | |
11026 | case O_register: | |
11027 | case O_constant: | |
11028 | break; | |
11029 | default: | |
11030 | return TRUE; | |
11031 | } | |
11032 | } | |
11033 | return FALSE; | |
11034 | } | |
11035 | ||
11036 | ||
11037 | bfd_boolean | |
7fa3d080 | 11038 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 11039 | { |
43cd72b9 | 11040 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
11041 | int i; |
11042 | int n = insn->ntok; | |
11043 | ||
11044 | assert (insn->insn_type == ITYPE_INSN); | |
11045 | ||
11046 | for (i = 0; i < n; ++i) | |
11047 | { | |
11048 | switch (insn->tok[i].X_op) | |
11049 | { | |
11050 | case O_register: | |
11051 | case O_constant: | |
11052 | break; | |
43cd72b9 BW |
11053 | case O_big: |
11054 | case O_illegal: | |
11055 | case O_absent: | |
11056 | /* Errors for these types are caught later. */ | |
11057 | break; | |
11058 | case O_hi16: | |
11059 | case O_lo16: | |
e0001a05 | 11060 | default: |
43cd72b9 BW |
11061 | /* Symbolic immediates are only allowed on the last immediate |
11062 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 11063 | support non-PC-relative relocations. */ |
43cd72b9 BW |
11064 | if (i != get_relaxable_immed (insn->opcode) |
11065 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
11066 | && insn->opcode != xtensa_const16_opcode)) | |
11067 | { | |
431ad2d0 | 11068 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
11069 | return TRUE; |
11070 | } | |
e0001a05 NC |
11071 | } |
11072 | } | |
11073 | return FALSE; | |
11074 | } | |
11075 | ||
11076 | ||
11077 | /* For assembly code with complex expressions (e.g. subtraction), | |
11078 | we have to build them in the literal pool so that | |
11079 | their results are calculated correctly after relaxation. | |
11080 | The relaxation only handles expressions that | |
11081 | boil down to SYMBOL + OFFSET. */ | |
11082 | ||
11083 | static bfd_boolean | |
7fa3d080 | 11084 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
11085 | { |
11086 | int i; | |
11087 | int n = insn->ntok; | |
11088 | assert (insn->insn_type == ITYPE_INSN); | |
11089 | for (i = 0; i < n; ++i) | |
11090 | { | |
11091 | switch (insn->tok[i].X_op) | |
11092 | { | |
11093 | case O_register: | |
11094 | case O_constant: | |
11095 | case O_symbol: | |
43cd72b9 BW |
11096 | case O_lo16: |
11097 | case O_hi16: | |
e0001a05 NC |
11098 | break; |
11099 | default: | |
11100 | return TRUE; | |
11101 | } | |
11102 | } | |
11103 | return FALSE; | |
11104 | } | |
11105 | ||
11106 | ||
b2d179be BW |
11107 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
11108 | Return TRUE if there is a symbol in the immediate field. This | |
11109 | function assumes that: | |
11110 | 1) The number of operands are correct. | |
11111 | 2) The insn_type is ITYPE_INSN. | |
11112 | 3) The opcode can be encoded in the specified format and slot. | |
11113 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
11114 | |
11115 | static bfd_boolean | |
7fa3d080 BW |
11116 | tinsn_to_slotbuf (xtensa_format fmt, |
11117 | int slot, | |
11118 | TInsn *tinsn, | |
11119 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
11120 | { |
11121 | xtensa_isa isa = xtensa_default_isa; | |
11122 | xtensa_opcode opcode = tinsn->opcode; | |
11123 | bfd_boolean has_fixup = FALSE; | |
11124 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11125 | int i; | |
11126 | ||
43cd72b9 BW |
11127 | assert (tinsn->insn_type == ITYPE_INSN); |
11128 | if (noperands != tinsn->ntok) | |
11129 | as_fatal (_("operand number mismatch")); | |
11130 | ||
11131 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
11132 | { | |
11133 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
11134 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
11135 | return FALSE; | |
11136 | } | |
11137 | ||
11138 | for (i = 0; i < noperands; i++) | |
11139 | { | |
11140 | expressionS *expr = &tinsn->tok[i]; | |
d77b99c9 BW |
11141 | int rc; |
11142 | unsigned line; | |
43cd72b9 BW |
11143 | char *file_name; |
11144 | uint32 opnd_value; | |
11145 | ||
11146 | switch (expr->X_op) | |
11147 | { | |
11148 | case O_register: | |
11149 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11150 | break; | |
11151 | /* The register number has already been checked in | |
11152 | expression_maybe_register, so we don't need to check here. */ | |
11153 | opnd_value = expr->X_add_number; | |
11154 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); | |
11155 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
11156 | opnd_value); | |
11157 | if (rc != 0) | |
11158 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
11159 | break; | |
11160 | ||
11161 | case O_constant: | |
11162 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11163 | break; | |
11164 | as_where (&file_name, &line); | |
11165 | /* It is a constant and we called this function | |
11166 | then we have to try to fit it. */ | |
11167 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
e0001a05 NC |
11168 | expr->X_add_number, file_name, line); |
11169 | break; | |
11170 | ||
e0001a05 NC |
11171 | default: |
11172 | has_fixup = TRUE; | |
11173 | break; | |
11174 | } | |
11175 | } | |
43cd72b9 | 11176 | |
e0001a05 NC |
11177 | return has_fixup; |
11178 | } | |
11179 | ||
11180 | ||
b2d179be BW |
11181 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
11182 | into a multi-slot instruction, fill the other slots with NOPs. | |
11183 | Return TRUE if there is a symbol in the immediate field. See also the | |
11184 | assumptions listed for tinsn_to_slotbuf. */ | |
11185 | ||
11186 | static bfd_boolean | |
11187 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
11188 | { | |
11189 | static xtensa_insnbuf slotbuf = 0; | |
11190 | static vliw_insn vinsn; | |
11191 | xtensa_isa isa = xtensa_default_isa; | |
11192 | bfd_boolean has_fixup = FALSE; | |
11193 | int i; | |
11194 | ||
11195 | if (!slotbuf) | |
11196 | { | |
11197 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11198 | xg_init_vinsn (&vinsn); | |
11199 | } | |
11200 | ||
11201 | xg_clear_vinsn (&vinsn); | |
11202 | ||
11203 | bundle_tinsn (tinsn, &vinsn); | |
11204 | ||
11205 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
11206 | ||
11207 | for (i = 0; i < vinsn.num_slots; i++) | |
11208 | { | |
11209 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
11210 | has_fixup |= | |
11211 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
11212 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
11213 | } | |
11214 | ||
11215 | return has_fixup; | |
11216 | } | |
11217 | ||
11218 | ||
43cd72b9 | 11219 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 11220 | |
7fa3d080 BW |
11221 | static bfd_boolean |
11222 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
11223 | { |
11224 | xtensa_isa isa = xtensa_default_isa; | |
11225 | xtensa_opcode opcode = insn->opcode; | |
11226 | ||
11227 | if (opcode == XTENSA_UNDEFINED) | |
11228 | { | |
11229 | as_bad (_("invalid opcode")); | |
11230 | return TRUE; | |
11231 | } | |
11232 | ||
43cd72b9 | 11233 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
11234 | { |
11235 | as_bad (_("too few operands")); | |
11236 | return TRUE; | |
11237 | } | |
11238 | ||
43cd72b9 | 11239 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
11240 | { |
11241 | as_bad (_("too many operands")); | |
11242 | return TRUE; | |
11243 | } | |
11244 | return FALSE; | |
11245 | } | |
11246 | ||
11247 | ||
11248 | /* Load an instruction from its encoded form. */ | |
11249 | ||
11250 | static void | |
7fa3d080 | 11251 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 11252 | { |
43cd72b9 | 11253 | vliw_insn vinsn; |
e0001a05 | 11254 | |
43cd72b9 BW |
11255 | xg_init_vinsn (&vinsn); |
11256 | vinsn_from_chars (&vinsn, f); | |
11257 | ||
11258 | *tinsn = vinsn.slots[slot]; | |
11259 | xg_free_vinsn (&vinsn); | |
11260 | } | |
e0001a05 | 11261 | |
43cd72b9 BW |
11262 | |
11263 | static void | |
7fa3d080 BW |
11264 | tinsn_from_insnbuf (TInsn *tinsn, |
11265 | xtensa_insnbuf slotbuf, | |
11266 | xtensa_format fmt, | |
11267 | int slot) | |
43cd72b9 BW |
11268 | { |
11269 | int i; | |
11270 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
11271 | |
11272 | /* Find the immed. */ | |
43cd72b9 BW |
11273 | tinsn_init (tinsn); |
11274 | tinsn->insn_type = ITYPE_INSN; | |
11275 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
11276 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
11277 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
11278 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 11279 | { |
43cd72b9 BW |
11280 | set_expr_const (&tinsn->tok[i], |
11281 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
11282 | tinsn->opcode, i)); | |
e0001a05 NC |
11283 | } |
11284 | } | |
11285 | ||
11286 | ||
11287 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
11288 | ||
11289 | static void | |
7fa3d080 | 11290 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 11291 | { |
43cd72b9 | 11292 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
11293 | int opnum; |
11294 | ||
43cd72b9 | 11295 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
11296 | { |
11297 | opnum = get_relaxable_immed (opcode); | |
43cd72b9 | 11298 | assert (opnum >= 0); |
e7da6241 BW |
11299 | set_expr_symbol_offset (&tinsn->tok[opnum], |
11300 | fragP->tc_frag_data.slot_symbols[slot], | |
11301 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 NC |
11302 | } |
11303 | } | |
11304 | ||
11305 | ||
11306 | static int | |
7fa3d080 | 11307 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
11308 | { |
11309 | int i; | |
11310 | int text_bytes = 0; | |
11311 | ||
11312 | for (i = 0; i < istack->ninsn; i++) | |
11313 | { | |
43cd72b9 BW |
11314 | TInsn *tinsn = &istack->insn[i]; |
11315 | if (tinsn->insn_type == ITYPE_INSN) | |
11316 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
11317 | } |
11318 | return text_bytes; | |
11319 | } | |
11320 | ||
11321 | ||
11322 | static int | |
7fa3d080 | 11323 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
11324 | { |
11325 | int i; | |
11326 | int lit_bytes = 0; | |
11327 | ||
11328 | for (i = 0; i < istack->ninsn; i++) | |
11329 | { | |
43cd72b9 BW |
11330 | TInsn *tinsn = &istack->insn[i]; |
11331 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
11332 | lit_bytes += 4; |
11333 | } | |
11334 | return lit_bytes; | |
11335 | } | |
11336 | ||
43cd72b9 BW |
11337 | \f |
11338 | /* vliw_insn functions. */ | |
11339 | ||
7fa3d080 BW |
11340 | static void |
11341 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11342 | { |
11343 | int i; | |
11344 | xtensa_isa isa = xtensa_default_isa; | |
11345 | ||
11346 | xg_clear_vinsn (v); | |
11347 | ||
11348 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
11349 | if (v->insnbuf == NULL) | |
11350 | as_fatal (_("out of memory")); | |
11351 | ||
11352 | for (i = 0; i < MAX_SLOTS; i++) | |
11353 | { | |
43cd72b9 BW |
11354 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
11355 | if (v->slotbuf[i] == NULL) | |
11356 | as_fatal (_("out of memory")); | |
11357 | } | |
11358 | } | |
11359 | ||
11360 | ||
7fa3d080 BW |
11361 | static void |
11362 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11363 | { |
11364 | int i; | |
65738a7d BW |
11365 | |
11366 | memset (v, 0, offsetof (vliw_insn, insnbuf)); | |
11367 | ||
43cd72b9 BW |
11368 | v->format = XTENSA_UNDEFINED; |
11369 | v->num_slots = 0; | |
11370 | v->inside_bundle = FALSE; | |
11371 | ||
11372 | if (xt_saved_debug_type != DEBUG_NONE) | |
11373 | debug_type = xt_saved_debug_type; | |
11374 | ||
11375 | for (i = 0; i < MAX_SLOTS; i++) | |
65738a7d | 11376 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
11377 | } |
11378 | ||
11379 | ||
7fa3d080 BW |
11380 | static bfd_boolean |
11381 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
11382 | { |
11383 | int i; | |
c138bc38 | 11384 | |
43cd72b9 BW |
11385 | for (i = 0; i < v->num_slots; i++) |
11386 | { | |
11387 | if (v->slots[i].is_specific_opcode) | |
11388 | return TRUE; | |
11389 | } | |
11390 | return FALSE; | |
11391 | } | |
11392 | ||
11393 | ||
7fa3d080 BW |
11394 | static void |
11395 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11396 | { |
11397 | int i; | |
11398 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
11399 | for (i = 0; i < MAX_SLOTS; i++) | |
11400 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); | |
11401 | } | |
11402 | ||
11403 | ||
e7da6241 BW |
11404 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
11405 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
11406 | |
11407 | static bfd_boolean | |
7fa3d080 BW |
11408 | vinsn_to_insnbuf (vliw_insn *vinsn, |
11409 | char *frag_offset, | |
11410 | fragS *fragP, | |
11411 | bfd_boolean record_fixup) | |
43cd72b9 BW |
11412 | { |
11413 | xtensa_isa isa = xtensa_default_isa; | |
11414 | xtensa_format fmt = vinsn->format; | |
11415 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
11416 | int slot; | |
11417 | bfd_boolean has_fixup = FALSE; | |
11418 | ||
11419 | xtensa_format_encode (isa, fmt, insnbuf); | |
11420 | ||
11421 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
11422 | { | |
11423 | TInsn *tinsn = &vinsn->slots[slot]; | |
11424 | bfd_boolean tinsn_has_fixup = | |
11425 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
11426 | vinsn->slotbuf[slot]); | |
11427 | ||
11428 | xtensa_format_set_slot (isa, fmt, slot, | |
11429 | insnbuf, vinsn->slotbuf[slot]); | |
e7da6241 | 11430 | if (tinsn_has_fixup) |
43cd72b9 BW |
11431 | { |
11432 | int i; | |
11433 | xtensa_opcode opcode = tinsn->opcode; | |
11434 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11435 | has_fixup = TRUE; | |
11436 | ||
11437 | for (i = 0; i < noperands; i++) | |
11438 | { | |
11439 | expressionS* expr = &tinsn->tok[i]; | |
11440 | switch (expr->X_op) | |
11441 | { | |
11442 | case O_symbol: | |
11443 | case O_lo16: | |
11444 | case O_hi16: | |
11445 | if (get_relaxable_immed (opcode) == i) | |
11446 | { | |
e7da6241 BW |
11447 | /* Add a fix record for the instruction, except if this |
11448 | function is being called prior to relaxation, i.e., | |
11449 | if record_fixup is false, and the instruction might | |
11450 | be relaxed later. */ | |
11451 | if (record_fixup | |
11452 | || tinsn->is_specific_opcode | |
11453 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 11454 | { |
e7da6241 BW |
11455 | xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP, |
11456 | frag_offset - fragP->fr_literal); | |
43cd72b9 BW |
11457 | } |
11458 | else | |
11459 | { | |
e7da6241 BW |
11460 | if (expr->X_op != O_symbol) |
11461 | as_bad (_("invalid operand")); | |
43cd72b9 BW |
11462 | tinsn->symbol = expr->X_add_symbol; |
11463 | tinsn->offset = expr->X_add_number; | |
11464 | } | |
11465 | } | |
11466 | else | |
e7da6241 | 11467 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
11468 | break; |
11469 | ||
11470 | case O_constant: | |
11471 | case O_register: | |
11472 | break; | |
11473 | ||
43cd72b9 | 11474 | default: |
e7da6241 | 11475 | as_bad (_("expression too complex")); |
43cd72b9 BW |
11476 | break; |
11477 | } | |
11478 | } | |
11479 | } | |
11480 | } | |
11481 | ||
11482 | return has_fixup; | |
11483 | } | |
11484 | ||
11485 | ||
11486 | static void | |
7fa3d080 | 11487 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
11488 | { |
11489 | static xtensa_insnbuf insnbuf = NULL; | |
11490 | static xtensa_insnbuf slotbuf = NULL; | |
11491 | int i; | |
11492 | xtensa_format fmt; | |
11493 | xtensa_isa isa = xtensa_default_isa; | |
11494 | ||
11495 | if (!insnbuf) | |
11496 | { | |
11497 | insnbuf = xtensa_insnbuf_alloc (isa); | |
11498 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11499 | } | |
11500 | ||
d77b99c9 | 11501 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
11502 | fmt = xtensa_format_decode (isa, insnbuf); |
11503 | if (fmt == XTENSA_UNDEFINED) | |
11504 | as_fatal (_("cannot decode instruction format")); | |
11505 | vinsn->format = fmt; | |
11506 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
11507 | ||
11508 | for (i = 0; i < vinsn->num_slots; i++) | |
11509 | { | |
11510 | TInsn *tinsn = &vinsn->slots[i]; | |
11511 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
11512 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
11513 | } | |
11514 | } | |
11515 | ||
e0001a05 NC |
11516 | \f |
11517 | /* Expression utilities. */ | |
11518 | ||
43cd72b9 | 11519 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
11520 | |
11521 | bfd_boolean | |
7fa3d080 | 11522 | expr_is_const (const expressionS *s) |
e0001a05 NC |
11523 | { |
11524 | return (s->X_op == O_constant); | |
11525 | } | |
11526 | ||
11527 | ||
11528 | /* Get the expression constant. | |
43cd72b9 | 11529 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
11530 | |
11531 | offsetT | |
7fa3d080 | 11532 | get_expr_const (const expressionS *s) |
e0001a05 NC |
11533 | { |
11534 | assert (expr_is_const (s)); | |
11535 | return s->X_add_number; | |
11536 | } | |
11537 | ||
11538 | ||
11539 | /* Set the expression to a constant value. */ | |
11540 | ||
11541 | void | |
7fa3d080 | 11542 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
11543 | { |
11544 | s->X_op = O_constant; | |
11545 | s->X_add_number = val; | |
11546 | s->X_add_symbol = NULL; | |
11547 | s->X_op_symbol = NULL; | |
11548 | } | |
11549 | ||
11550 | ||
43cd72b9 | 11551 | bfd_boolean |
7fa3d080 | 11552 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
11553 | { |
11554 | return (s->X_op == O_register); | |
11555 | } | |
11556 | ||
11557 | ||
11558 | /* Get the expression constant. | |
11559 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
11560 | ||
11561 | offsetT | |
7fa3d080 | 11562 | get_expr_register (const expressionS *s) |
43cd72b9 BW |
11563 | { |
11564 | assert (expr_is_register (s)); | |
11565 | return s->X_add_number; | |
11566 | } | |
11567 | ||
11568 | ||
e0001a05 NC |
11569 | /* Set the expression to a symbol + constant offset. */ |
11570 | ||
11571 | void | |
7fa3d080 | 11572 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
11573 | { |
11574 | s->X_op = O_symbol; | |
11575 | s->X_add_symbol = sym; | |
11576 | s->X_op_symbol = NULL; /* unused */ | |
11577 | s->X_add_number = offset; | |
11578 | } | |
11579 | ||
11580 | ||
43cd72b9 BW |
11581 | /* Return TRUE if the two expressions are equal. */ |
11582 | ||
e0001a05 | 11583 | bfd_boolean |
7fa3d080 | 11584 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
11585 | { |
11586 | if (s1->X_op != s2->X_op) | |
11587 | return FALSE; | |
11588 | if (s1->X_add_symbol != s2->X_add_symbol) | |
11589 | return FALSE; | |
11590 | if (s1->X_op_symbol != s2->X_op_symbol) | |
11591 | return FALSE; | |
11592 | if (s1->X_add_number != s2->X_add_number) | |
11593 | return FALSE; | |
11594 | return TRUE; | |
11595 | } | |
11596 | ||
11597 | ||
11598 | static void | |
7fa3d080 | 11599 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
11600 | { |
11601 | memcpy (dst, src, sizeof (expressionS)); | |
11602 | } | |
11603 | ||
11604 | \f | |
9456465c | 11605 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
11606 | |
11607 | struct rename_section_struct | |
11608 | { | |
11609 | char *old_name; | |
11610 | char *new_name; | |
11611 | struct rename_section_struct *next; | |
11612 | }; | |
11613 | ||
11614 | static struct rename_section_struct *section_rename; | |
11615 | ||
11616 | ||
9456465c BW |
11617 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
11618 | entries to the section_rename list. Note: Specifying multiple | |
11619 | renamings separated by colons is not documented and is retained only | |
11620 | for backward compatibility. */ | |
e0001a05 | 11621 | |
7fa3d080 BW |
11622 | static void |
11623 | build_section_rename (const char *arg) | |
e0001a05 | 11624 | { |
9456465c | 11625 | struct rename_section_struct *r; |
e0001a05 NC |
11626 | char *this_arg = NULL; |
11627 | char *next_arg = NULL; | |
11628 | ||
9456465c | 11629 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 11630 | { |
9456465c BW |
11631 | char *old_name, *new_name; |
11632 | ||
e0001a05 NC |
11633 | if (this_arg) |
11634 | { | |
11635 | next_arg = strchr (this_arg, ':'); | |
11636 | if (next_arg) | |
11637 | { | |
11638 | *next_arg = '\0'; | |
11639 | next_arg++; | |
11640 | } | |
11641 | } | |
e0001a05 | 11642 | |
9456465c BW |
11643 | old_name = this_arg; |
11644 | new_name = strchr (this_arg, '='); | |
e0001a05 | 11645 | |
9456465c BW |
11646 | if (*old_name == '\0') |
11647 | { | |
11648 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
11649 | continue; | |
11650 | } | |
11651 | if (!new_name || new_name[1] == '\0') | |
11652 | { | |
11653 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
11654 | old_name); | |
11655 | continue; | |
11656 | } | |
11657 | *new_name = '\0'; | |
11658 | new_name++; | |
e0001a05 | 11659 | |
9456465c BW |
11660 | /* Check for invalid section renaming. */ |
11661 | for (r = section_rename; r != NULL; r = r->next) | |
11662 | { | |
11663 | if (strcmp (r->old_name, old_name) == 0) | |
11664 | as_bad (_("section %s renamed multiple times"), old_name); | |
11665 | if (strcmp (r->new_name, new_name) == 0) | |
11666 | as_bad (_("multiple sections remapped to output section %s"), | |
11667 | new_name); | |
11668 | } | |
e0001a05 | 11669 | |
9456465c BW |
11670 | /* Now add it. */ |
11671 | r = (struct rename_section_struct *) | |
11672 | xmalloc (sizeof (struct rename_section_struct)); | |
11673 | r->old_name = xstrdup (old_name); | |
11674 | r->new_name = xstrdup (new_name); | |
11675 | r->next = section_rename; | |
11676 | section_rename = r; | |
e0001a05 | 11677 | } |
e0001a05 NC |
11678 | } |
11679 | ||
11680 | ||
9456465c BW |
11681 | char * |
11682 | xtensa_section_rename (char *name) | |
e0001a05 NC |
11683 | { |
11684 | struct rename_section_struct *r = section_rename; | |
11685 | ||
11686 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
11687 | { |
11688 | if (strcmp (r->old_name, name) == 0) | |
11689 | return r->new_name; | |
11690 | } | |
e0001a05 NC |
11691 | |
11692 | return name; | |
11693 | } |