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2007-11-07 Joseph Myers <joseph@codesourcery.com>
[deliverable/binutils-gdb.git] / gas / config / tc-xtensa.c
CommitLineData
e0001a05 1/* tc-xtensa.c -- Assemble Xtensa instructions.
63a7429b 2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
e0001a05
NC		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
e0001a05
NC		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
4b4da160
NC		 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
e0001a05 20
43cd72b9 21#include <limits.h>
e0001a05
NC		 22#include "as.h"
23#include "sb.h"
24#include "safe-ctype.h"
25#include "tc-xtensa.h"
e0001a05
NC		 26#include "subsegs.h"
27#include "xtensa-relax.h"
28#include "xtensa-istack.h"
cda2eb9e 29#include "dwarf2dbg.h"
e0001a05
NC		 30#include "struc-symbol.h"
31#include "xtensa-config.h"
32
2caa7ca0
BW		 33/* Provide default values for new configuration settings. */
34#ifndef XSHAL_ABI
35#define XSHAL_ABI 0
36#endif
37
e0001a05
NC		 38#ifndef uint32
39#define uint32 unsigned int
40#endif
41#ifndef int32
42#define int32 signed int
43#endif
44
45/* Notes:
46
e0001a05
NC		 47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
50
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
61
62
63/* Define characters with special meanings to GAS. */
64const char comment_chars[] = "#";
65const char line_comment_chars[] = "#";
66const char line_separator_chars[] = ";";
67const char EXP_CHARS[] = "eE";
68const char FLT_CHARS[] = "rRsSfFdDxXpP";
69
70
43cd72b9
BW		 71/* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
e0001a05 73
e0001a05 74bfd_boolean density_supported = XCHAL_HAVE_DENSITY;
43cd72b9
BW		 75bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
76
77/* Maximum width we would pad an unreachable frag to get alignment. */
78#define UNREACHABLE_MAX_WIDTH 8
e0001a05 79
43cd72b9
BW		 80static vliw_insn cur_vinsn;
81
d77b99c9 82unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
43cd72b9
BW		 83
84static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
85
86/* Some functions are only valid in the front end. This variable
c138bc38 87 allows us to assert that we haven't crossed over into the
43cd72b9
BW		 88 back end. */
89static bfd_boolean past_xtensa_end = FALSE;
e0001a05
NC		 90
91/* Flags for properties of the last instruction in a segment. */
92#define FLAG_IS_A0_WRITER 0x1
93#define FLAG_IS_BAD_LOOPEND 0x2
94
95
96/* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
100
101#define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
43cd72b9 102#define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
e0001a05 103#define INIT_SECTION_NAME xtensa_section_rename (".init")
74869ac7 104#define FINI_SECTION_NAME xtensa_section_rename (".fini")
e0001a05
NC		 105
106
43cd72b9 107/* This type is used for the directive_stack to keep track of the
74869ac7
BW		 108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
113 values are valid. */
e0001a05
NC		 114
115typedef struct lit_state_struct
116{
74869ac7
BW		 117 char *lit_prefix;
118 segT current_text_seg;
e0001a05 119 segT lit_seg;
43cd72b9 120 segT lit4_seg;
e0001a05
NC		 121} lit_state;
122
123static lit_state default_lit_sections;
124
125
74869ac7
BW		 126/* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
e0001a05
NC		 129
130typedef struct seg_list_struct
131{
132 struct seg_list_struct *next;
133 segT seg;
134} seg_list;
135
136static seg_list literal_head_h;
137static seg_list *literal_head = &literal_head_h;
e0001a05
NC		 138
139
82e7541d
BW		 140/* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
145
146typedef struct sym_list_struct
147{
148 struct sym_list_struct *next;
149 symbolS *sym;
150} sym_list;
151
152static sym_list *insn_labels = NULL;
153static sym_list *free_insn_labels = NULL;
154static sym_list *saved_insn_labels = NULL;
155
156static sym_list *literal_syms;
157
158
43cd72b9
BW		 159/* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161int prefer_const16 = 0;
162int prefer_l32r = 0;
163
e0001a05
NC		 164/* Global flag to indicate when we are emitting literals. */
165int generating_literals = 0;
166
43cd72b9
BW		 167/* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
169
170/* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
179
180#define XTENSA_PROP_LITERAL 0x00000001
181#define XTENSA_PROP_INSN 0x00000002
182#define XTENSA_PROP_DATA 0x00000004
183#define XTENSA_PROP_UNREACHABLE 0x00000008
184/* Instruction only properties at beginning of code. */
185#define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186#define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187/* Instruction only properties about code. */
188#define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189#define XTENSA_PROP_INSN_NO_REORDER 0x00000080
99ded152
BW		 190/* Historically, NO_TRANSFORM was a property of instructions,
191 but it should apply to literals under certain circumstances. */
192#define XTENSA_PROP_NO_TRANSFORM 0x00000100
43cd72b9
BW		 193
194/* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 Common usage is
200
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
206*/
207#define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
208
209/* No branch target alignment. */
210#define XTENSA_PROP_BT_ALIGN_NONE 0x0
211/* Low priority branch target alignment. */
212#define XTENSA_PROP_BT_ALIGN_LOW 0x1
213/* High priority branch target alignment. */
214#define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215/* Required branch target alignment. */
216#define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
217
218#define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220#define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223
224
225/* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
235
236#define XTENSA_PROP_ALIGN 0x00000800
237
238#define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
239
240#define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242#define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
245
246#define XTENSA_PROP_INSN_ABSLIT 0x00020000
247
248
249/* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
254
255typedef struct frag_flags_struct frag_flags;
256
257struct frag_flags_struct
258{
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
262
263 unsigned is_literal : 1;
264 unsigned is_insn : 1;
265 unsigned is_data : 1;
266 unsigned is_unreachable : 1;
267
99ded152
BW		 268 /* is_specific_opcode implies no_transform. */
269 unsigned is_no_transform : 1;
270
43cd72b9
BW		 271 struct
272 {
273 unsigned is_loop_target : 1;
274 unsigned is_branch_target : 1; /* Branch targets have a priority. */
275 unsigned bt_align_priority : 2;
276
277 unsigned is_no_density : 1;
278 /* no_longcalls flag does not need to be placed in the object file. */
43cd72b9
BW		 279
280 unsigned is_no_reorder : 1;
281
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit : 1;
284 } insn;
285 unsigned is_align : 1;
286 unsigned alignment : 5;
287};
288
289
290/* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292struct xtensa_block_info_struct
293{
294 segT sec;
295 bfd_vma offset;
296 size_t size;
297 frag_flags flags;
298 struct xtensa_block_info_struct *next;
299};
300
e0001a05
NC		 301
302/* Structure for saving the current state before emitting literals. */
303typedef struct emit_state_struct
304{
305 const char *name;
306 segT now_seg;
307 subsegT now_subseg;
308 int generating_literals;
309} emit_state;
310
311
43cd72b9
BW		 312/* Opcode placement information */
313
314typedef unsigned long long bitfield;
315#define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
316#define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
317#define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318
319#define MAX_FORMATS 32
320
321typedef struct op_placement_info_struct
322{
323 int num_formats;
324 /* A number describing how restrictive the issue is for this
325 opcode. For example, an opcode that fits lots of different
c138bc38 326 formats has a high freedom, as does an opcode that fits
43cd72b9 327 only one format but many slots in that format. The most
c138bc38 328 restrictive is the opcode that fits only one slot in one
43cd72b9
BW		 329 format. */
330 int issuef;
43cd72b9 331 xtensa_format narrowest;
43cd72b9 332 char narrowest_size;
b2d179be 333 char narrowest_slot;
43cd72b9
BW		 334
335 /* formats is a bitfield with the Nth bit set
336 if the opcode fits in the Nth xtensa_format. */
337 bitfield formats;
338
339 /* slots[N]'s Mth bit is set if the op fits in the
340 Mth slot of the Nth xtensa_format. */
341 bitfield slots[MAX_FORMATS];
342
343 /* A count of the number of slots in a given format
344 an op can fit (i.e., the bitcount of the slot field above). */
345 char slots_in_format[MAX_FORMATS];
346
347} op_placement_info, *op_placement_info_table;
348
349op_placement_info_table op_placement_table;
350
351
352/* Extra expression types. */
353
354#define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
355#define O_hi16 O_md2 /* use high 16 bits of symbolic value */
356#define O_lo16 O_md3 /* use low 16 bits of symbolic value */
357
bbdd25a8
BW		 358struct suffix_reloc_map
359{
360 char *suffix;
361 int length;
362 bfd_reloc_code_real_type reloc;
363 unsigned char operator;
364};
365
366#define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
367
368static struct suffix_reloc_map suffix_relocs[] =
369{
370 SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16),
371 SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16),
372 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel),
373 { (char *) 0, 0, BFD_RELOC_UNUSED, 0 }
374};
375
43cd72b9 376
e0001a05
NC		 377/* Directives. */
378
379typedef enum
380{
381 directive_none = 0,
382 directive_literal,
383 directive_density,
43cd72b9 384 directive_transform,
e0001a05
NC		 385 directive_freeregs,
386 directive_longcalls,
43cd72b9
BW		 387 directive_literal_prefix,
388 directive_schedule,
389 directive_absolute_literals,
390 directive_last_directive
e0001a05
NC		 391} directiveE;
392
393typedef struct
394{
395 const char *name;
396 bfd_boolean can_be_negated;
397} directive_infoS;
398
399const directive_infoS directive_info[] =
400{
43cd72b9
BW		 401 { "none", FALSE },
402 { "literal", FALSE },
403 { "density", TRUE },
404 { "transform", TRUE },
405 { "freeregs", FALSE },
406 { "longcalls", TRUE },
407 { "literal_prefix", FALSE },
408 { "schedule", TRUE },
409 { "absolute-literals", TRUE }
e0001a05
NC		 410};
411
412bfd_boolean directive_state[] =
413{
414 FALSE, /* none */
415 FALSE, /* literal */
43cd72b9 416#if !XCHAL_HAVE_DENSITY
e0001a05
NC		 417 FALSE, /* density */
418#else
419 TRUE, /* density */
420#endif
43cd72b9 421 TRUE, /* transform */
e0001a05
NC		 422 FALSE, /* freeregs */
423 FALSE, /* longcalls */
43cd72b9 424 FALSE, /* literal_prefix */
2caa7ca0 425 FALSE, /* schedule */
43cd72b9
BW		 426#if XSHAL_USE_ABSOLUTE_LITERALS
427 TRUE /* absolute_literals */
428#else
429 FALSE /* absolute_literals */
430#endif
e0001a05
NC		 431};
432
e0001a05
NC		 433
434/* Directive functions. */
435
7fa3d080
BW		 436static void xtensa_begin_directive (int);
437static void xtensa_end_directive (int);
74869ac7 438static void xtensa_literal_prefix (void);
7fa3d080
BW		 439static void xtensa_literal_position (int);
440static void xtensa_literal_pseudo (int);
441static void xtensa_frequency_pseudo (int);
442static void xtensa_elf_cons (int);
e0001a05 443
7fa3d080 444/* Parsing and Idiom Translation. */
e0001a05 445
7fa3d080 446static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *);
e0001a05 447
e0001a05
NC		 448/* Various Other Internal Functions. */
449
84b08ed9
BW		 450extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean);
451static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *);
7fa3d080
BW		 452static void xtensa_mark_literal_pool_location (void);
453static addressT get_expanded_loop_offset (xtensa_opcode);
454static fragS *get_literal_pool_location (segT);
455static void set_literal_pool_location (segT, fragS *);
456static void xtensa_set_frag_assembly_state (fragS *);
457static void finish_vinsn (vliw_insn *);
458static bfd_boolean emit_single_op (TInsn *);
34e41783 459static int total_frag_text_expansion (fragS *);
e0001a05
NC		 460
461/* Alignment Functions. */
462
d77b99c9
BW		 463static int get_text_align_power (unsigned);
464static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean);
664df4e4 465static int branch_align_power (segT);
e0001a05
NC		 466
467/* Helpers for xtensa_relax_frag(). */
468
7fa3d080 469static long relax_frag_add_nop (fragS *);
e0001a05 470
b08b5071 471/* Accessors for additional per-subsegment information. */
e0001a05 472
7fa3d080
BW		 473static unsigned get_last_insn_flags (segT, subsegT);
474static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean);
b08b5071
BW		 475static float get_subseg_total_freq (segT, subsegT);
476static float get_subseg_target_freq (segT, subsegT);
477static void set_subseg_freq (segT, subsegT, float, float);
e0001a05
NC		 478
479/* Segment list functions. */
480
7fa3d080
BW		 481static void xtensa_move_literals (void);
482static void xtensa_reorder_segments (void);
483static void xtensa_switch_to_literal_fragment (emit_state *);
484static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
485static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
486static void xtensa_restore_emit_state (emit_state *);
74869ac7 487static segT cache_literal_section (bfd_boolean);
e0001a05 488
e0001a05 489/* Import from elf32-xtensa.c in BFD library. */
43cd72b9 490
74869ac7 491extern asection *xtensa_get_property_section (asection *, const char *);
e0001a05 492
43cd72b9
BW		 493/* op_placement_info functions. */
494
7fa3d080
BW		 495static void init_op_placement_info_table (void);
496extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
497static int xg_get_single_size (xtensa_opcode);
498static xtensa_format xg_get_single_format (xtensa_opcode);
b2d179be 499static int xg_get_single_slot (xtensa_opcode);
43cd72b9 500
e0001a05 501/* TInsn and IStack functions. */
43cd72b9 502
7fa3d080
BW		 503static bfd_boolean tinsn_has_symbolic_operands (const TInsn *);
504static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *);
505static bfd_boolean tinsn_has_complex_operands (const TInsn *);
506static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
507static bfd_boolean tinsn_check_arguments (const TInsn *);
508static void tinsn_from_chars (TInsn *, char *, int);
509static void tinsn_immed_from_frag (TInsn *, fragS *, int);
510static int get_num_stack_text_bytes (IStack *);
511static int get_num_stack_literal_bytes (IStack *);
e0001a05 512
43cd72b9
BW		 513/* vliw_insn functions. */
514
7fa3d080
BW		 515static void xg_init_vinsn (vliw_insn *);
516static void xg_clear_vinsn (vliw_insn *);
517static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *);
518static void xg_free_vinsn (vliw_insn *);
43cd72b9 519static bfd_boolean vinsn_to_insnbuf
7fa3d080
BW		 520 (vliw_insn *, char *, fragS *, bfd_boolean);
521static void vinsn_from_chars (vliw_insn *, char *);
43cd72b9 522
e0001a05 523/* Expression Utilities. */
43cd72b9 524
7fa3d080
BW		 525bfd_boolean expr_is_const (const expressionS *);
526offsetT get_expr_const (const expressionS *);
527void set_expr_const (expressionS *, offsetT);
528bfd_boolean expr_is_register (const expressionS *);
529offsetT get_expr_register (const expressionS *);
530void set_expr_symbol_offset (expressionS *, symbolS *, offsetT);
7fa3d080
BW		 531bfd_boolean expr_is_equal (expressionS *, expressionS *);
532static void copy_expr (expressionS *, const expressionS *);
e0001a05 533
9456465c
BW		 534/* Section renaming. */
535
7fa3d080 536static void build_section_rename (const char *);
e0001a05 537
e0001a05
NC		 538
539/* ISA imported from bfd. */
540extern xtensa_isa xtensa_default_isa;
541
542extern int target_big_endian;
543
544static xtensa_opcode xtensa_addi_opcode;
545static xtensa_opcode xtensa_addmi_opcode;
546static xtensa_opcode xtensa_call0_opcode;
547static xtensa_opcode xtensa_call4_opcode;
548static xtensa_opcode xtensa_call8_opcode;
549static xtensa_opcode xtensa_call12_opcode;
550static xtensa_opcode xtensa_callx0_opcode;
551static xtensa_opcode xtensa_callx4_opcode;
552static xtensa_opcode xtensa_callx8_opcode;
553static xtensa_opcode xtensa_callx12_opcode;
43cd72b9 554static xtensa_opcode xtensa_const16_opcode;
e0001a05 555static xtensa_opcode xtensa_entry_opcode;
d12f9798 556static xtensa_opcode xtensa_extui_opcode;
43cd72b9
BW		 557static xtensa_opcode xtensa_movi_opcode;
558static xtensa_opcode xtensa_movi_n_opcode;
e0001a05 559static xtensa_opcode xtensa_isync_opcode;
e0001a05 560static xtensa_opcode xtensa_jx_opcode;
43cd72b9 561static xtensa_opcode xtensa_l32r_opcode;
e0001a05
NC		 562static xtensa_opcode xtensa_loop_opcode;
563static xtensa_opcode xtensa_loopnez_opcode;
564static xtensa_opcode xtensa_loopgtz_opcode;
43cd72b9 565static xtensa_opcode xtensa_nop_opcode;
e0001a05
NC		 566static xtensa_opcode xtensa_nop_n_opcode;
567static xtensa_opcode xtensa_or_opcode;
568static xtensa_opcode xtensa_ret_opcode;
569static xtensa_opcode xtensa_ret_n_opcode;
570static xtensa_opcode xtensa_retw_opcode;
571static xtensa_opcode xtensa_retw_n_opcode;
43cd72b9 572static xtensa_opcode xtensa_rsr_lcount_opcode;
e0001a05
NC		 573static xtensa_opcode xtensa_waiti_opcode;
574
575\f
576/* Command-line Options. */
577
578bfd_boolean use_literal_section = TRUE;
579static bfd_boolean align_targets = TRUE;
43cd72b9 580static bfd_boolean warn_unaligned_branch_targets = FALSE;
e0001a05 581static bfd_boolean has_a0_b_retw = FALSE;
43cd72b9
BW		 582static bfd_boolean workaround_a0_b_retw = FALSE;
583static bfd_boolean workaround_b_j_loop_end = FALSE;
584static bfd_boolean workaround_short_loop = FALSE;
e0001a05 585static bfd_boolean maybe_has_short_loop = FALSE;
43cd72b9 586static bfd_boolean workaround_close_loop_end = FALSE;
e0001a05 587static bfd_boolean maybe_has_close_loop_end = FALSE;
03aaa593 588static bfd_boolean enforce_three_byte_loop_align = FALSE;
e0001a05 589
43cd72b9
BW		 590/* When workaround_short_loops is TRUE, all loops with early exits must
591 have at least 3 instructions. workaround_all_short_loops is a modifier
592 to the workaround_short_loop flag. In addition to the
593 workaround_short_loop actions, all straightline loopgtz and loopnez
594 must have at least 3 instructions. */
e0001a05 595
43cd72b9 596static bfd_boolean workaround_all_short_loops = FALSE;
e0001a05 597
7fa3d080
BW		 598
599static void
600xtensa_setup_hw_workarounds (int earliest, int latest)
601{
602 if (earliest > latest)
603 as_fatal (_("illegal range of target hardware versions"));
604
605 /* Enable all workarounds for pre-T1050.0 hardware. */
606 if (earliest < 105000 || latest < 105000)
607 {
608 workaround_a0_b_retw |= TRUE;
609 workaround_b_j_loop_end |= TRUE;
610 workaround_short_loop |= TRUE;
611 workaround_close_loop_end |= TRUE;
612 workaround_all_short_loops |= TRUE;
03aaa593 613 enforce_three_byte_loop_align = TRUE;
7fa3d080
BW		 614 }
615}
616
617
e0001a05
NC		 618enum
619{
620 option_density = OPTION_MD_BASE,
621 option_no_density,
622
623 option_relax,
624 option_no_relax,
625
43cd72b9
BW		 626 option_link_relax,
627 option_no_link_relax,
628
e0001a05
NC		 629 option_generics,
630 option_no_generics,
631
43cd72b9
BW		 632 option_transform,
633 option_no_transform,
634
e0001a05
NC		 635 option_text_section_literals,
636 option_no_text_section_literals,
637
43cd72b9
BW		 638 option_absolute_literals,
639 option_no_absolute_literals,
640
e0001a05
NC		 641 option_align_targets,
642 option_no_align_targets,
643
43cd72b9 644 option_warn_unaligned_targets,
e0001a05
NC		 645
646 option_longcalls,
647 option_no_longcalls,
648
649 option_workaround_a0_b_retw,
650 option_no_workaround_a0_b_retw,
651
652 option_workaround_b_j_loop_end,
653 option_no_workaround_b_j_loop_end,
654
655 option_workaround_short_loop,
656 option_no_workaround_short_loop,
657
658 option_workaround_all_short_loops,
659 option_no_workaround_all_short_loops,
660
661 option_workaround_close_loop_end,
662 option_no_workaround_close_loop_end,
663
664 option_no_workarounds,
665
e0001a05 666 option_rename_section_name,
e0001a05 667
43cd72b9
BW		 668 option_prefer_l32r,
669 option_prefer_const16,
670
671 option_target_hardware
e0001a05
NC		 672};
673
674const char *md_shortopts = "";
675
676struct option md_longopts[] =
677{
43cd72b9
BW		 678 { "density", no_argument, NULL, option_density },
679 { "no-density", no_argument, NULL, option_no_density },
680
681 /* Both "relax" and "generics" are deprecated and treated as equivalent
682 to the "transform" option. */
683 { "relax", no_argument, NULL, option_relax },
684 { "no-relax", no_argument, NULL, option_no_relax },
685 { "generics", no_argument, NULL, option_generics },
686 { "no-generics", no_argument, NULL, option_no_generics },
687
688 { "transform", no_argument, NULL, option_transform },
689 { "no-transform", no_argument, NULL, option_no_transform },
690 { "text-section-literals", no_argument, NULL, option_text_section_literals },
691 { "no-text-section-literals", no_argument, NULL,
692 option_no_text_section_literals },
693 { "absolute-literals", no_argument, NULL, option_absolute_literals },
694 { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals },
e0001a05
NC		 695 /* This option was changed from -align-target to -target-align
696 because it conflicted with the "-al" option. */
43cd72b9 697 { "target-align", no_argument, NULL, option_align_targets },
7fa3d080
BW		 698 { "no-target-align", no_argument, NULL, option_no_align_targets },
699 { "warn-unaligned-targets", no_argument, NULL,
700 option_warn_unaligned_targets },
43cd72b9
BW		 701 { "longcalls", no_argument, NULL, option_longcalls },
702 { "no-longcalls", no_argument, NULL, option_no_longcalls },
703
704 { "no-workaround-a0-b-retw", no_argument, NULL,
705 option_no_workaround_a0_b_retw },
706 { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw },
e0001a05 707
43cd72b9
BW		 708 { "no-workaround-b-j-loop-end", no_argument, NULL,
709 option_no_workaround_b_j_loop_end },
710 { "workaround-b-j-loop-end", no_argument, NULL,
711 option_workaround_b_j_loop_end },
e0001a05 712
43cd72b9
BW		 713 { "no-workaround-short-loops", no_argument, NULL,
714 option_no_workaround_short_loop },
7fa3d080
BW		 715 { "workaround-short-loops", no_argument, NULL,
716 option_workaround_short_loop },
e0001a05 717
43cd72b9
BW		 718 { "no-workaround-all-short-loops", no_argument, NULL,
719 option_no_workaround_all_short_loops },
720 { "workaround-all-short-loop", no_argument, NULL,
721 option_workaround_all_short_loops },
722
723 { "prefer-l32r", no_argument, NULL, option_prefer_l32r },
724 { "prefer-const16", no_argument, NULL, option_prefer_const16 },
725
726 { "no-workarounds", no_argument, NULL, option_no_workarounds },
727
728 { "no-workaround-close-loop-end", no_argument, NULL,
729 option_no_workaround_close_loop_end },
730 { "workaround-close-loop-end", no_argument, NULL,
731 option_workaround_close_loop_end },
e0001a05 732
7fa3d080 733 { "rename-section", required_argument, NULL, option_rename_section_name },
e0001a05 734
43cd72b9
BW		 735 { "link-relax", no_argument, NULL, option_link_relax },
736 { "no-link-relax", no_argument, NULL, option_no_link_relax },
737
738 { "target-hardware", required_argument, NULL, option_target_hardware },
739
740 { NULL, no_argument, NULL, 0 }
e0001a05
NC		 741};
742
743size_t md_longopts_size = sizeof md_longopts;
744
745
746int
7fa3d080 747md_parse_option (int c, char *arg)
e0001a05
NC		 748{
749 switch (c)
750 {
751 case option_density:
43cd72b9 752 as_warn (_("--density option is ignored"));
e0001a05
NC		 753 return 1;
754 case option_no_density:
43cd72b9 755 as_warn (_("--no-density option is ignored"));
e0001a05 756 return 1;
43cd72b9
BW		 757 case option_link_relax:
758 linkrelax = 1;
e0001a05 759 return 1;
43cd72b9
BW		 760 case option_no_link_relax:
761 linkrelax = 0;
e0001a05 762 return 1;
43cd72b9
BW		 763 case option_generics:
764 as_warn (_("--generics is deprecated; use --transform instead"));
765 return md_parse_option (option_transform, arg);
766 case option_no_generics:
767 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
768 return md_parse_option (option_no_transform, arg);
769 case option_relax:
770 as_warn (_("--relax is deprecated; use --transform instead"));
771 return md_parse_option (option_transform, arg);
772 case option_no_relax:
773 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
774 return md_parse_option (option_no_transform, arg);
e0001a05
NC		 775 case option_longcalls:
776 directive_state[directive_longcalls] = TRUE;
777 return 1;
778 case option_no_longcalls:
779 directive_state[directive_longcalls] = FALSE;
780 return 1;
781 case option_text_section_literals:
782 use_literal_section = FALSE;
783 return 1;
784 case option_no_text_section_literals:
785 use_literal_section = TRUE;
786 return 1;
43cd72b9
BW		 787 case option_absolute_literals:
788 if (!absolute_literals_supported)
789 {
790 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
791 return 0;
792 }
793 directive_state[directive_absolute_literals] = TRUE;
794 return 1;
795 case option_no_absolute_literals:
796 directive_state[directive_absolute_literals] = FALSE;
797 return 1;
798
e0001a05
NC		 799 case option_workaround_a0_b_retw:
800 workaround_a0_b_retw = TRUE;
e0001a05
NC		 801 return 1;
802 case option_no_workaround_a0_b_retw:
803 workaround_a0_b_retw = FALSE;
e0001a05
NC		 804 return 1;
805 case option_workaround_b_j_loop_end:
806 workaround_b_j_loop_end = TRUE;
e0001a05
NC		 807 return 1;
808 case option_no_workaround_b_j_loop_end:
809 workaround_b_j_loop_end = FALSE;
e0001a05
NC		 810 return 1;
811
812 case option_workaround_short_loop:
813 workaround_short_loop = TRUE;
e0001a05
NC		 814 return 1;
815 case option_no_workaround_short_loop:
816 workaround_short_loop = FALSE;
e0001a05
NC		 817 return 1;
818
819 case option_workaround_all_short_loops:
820 workaround_all_short_loops = TRUE;
e0001a05
NC		 821 return 1;
822 case option_no_workaround_all_short_loops:
823 workaround_all_short_loops = FALSE;
e0001a05
NC		 824 return 1;
825
826 case option_workaround_close_loop_end:
827 workaround_close_loop_end = TRUE;
e0001a05
NC		 828 return 1;
829 case option_no_workaround_close_loop_end:
830 workaround_close_loop_end = FALSE;
e0001a05
NC		 831 return 1;
832
833 case option_no_workarounds:
834 workaround_a0_b_retw = FALSE;
e0001a05 835 workaround_b_j_loop_end = FALSE;
e0001a05 836 workaround_short_loop = FALSE;
e0001a05 837 workaround_all_short_loops = FALSE;
e0001a05 838 workaround_close_loop_end = FALSE;
e0001a05 839 return 1;
43cd72b9 840
e0001a05
NC		 841 case option_align_targets:
842 align_targets = TRUE;
843 return 1;
844 case option_no_align_targets:
845 align_targets = FALSE;
846 return 1;
847
43cd72b9
BW		 848 case option_warn_unaligned_targets:
849 warn_unaligned_branch_targets = TRUE;
e0001a05
NC		 850 return 1;
851
e0001a05
NC		 852 case option_rename_section_name:
853 build_section_rename (arg);
854 return 1;
e0001a05
NC		 855
856 case 'Q':
857 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
858 should be emitted or not. FIXME: Not implemented. */
859 return 1;
c138bc38 860
43cd72b9
BW		 861 case option_prefer_l32r:
862 if (prefer_const16)
863 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
864 prefer_l32r = 1;
865 return 1;
866
867 case option_prefer_const16:
868 if (prefer_l32r)
869 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
870 prefer_const16 = 1;
871 return 1;
872
c138bc38 873 case option_target_hardware:
43cd72b9
BW		 874 {
875 int earliest, latest = 0;
876 if (*arg == 0 || *arg == '-')
877 as_fatal (_("invalid target hardware version"));
878
879 earliest = strtol (arg, &arg, 0);
880
881 if (*arg == 0)
882 latest = earliest;
883 else if (*arg == '-')
884 {
885 if (*++arg == 0)
886 as_fatal (_("invalid target hardware version"));
887 latest = strtol (arg, &arg, 0);
888 }
889 if (*arg != 0)
890 as_fatal (_("invalid target hardware version"));
891
892 xtensa_setup_hw_workarounds (earliest, latest);
893 return 1;
894 }
895
896 case option_transform:
897 /* This option has no affect other than to use the defaults,
898 which are already set. */
899 return 1;
900
901 case option_no_transform:
902 /* This option turns off all transformations of any kind.
903 However, because we want to preserve the state of other
904 directives, we only change its own field. Thus, before
905 you perform any transformation, always check if transform
906 is available. If you use the functions we provide for this
907 purpose, you will be ok. */
908 directive_state[directive_transform] = FALSE;
909 return 1;
910
e0001a05
NC		 911 default:
912 return 0;
913 }
914}
915
916
917void
7fa3d080 918md_show_usage (FILE *stream)
e0001a05 919{
43cd72b9
BW		 920 fputs ("\n\
921Xtensa options:\n\
9456465c
BW		 922 --[no-]text-section-literals\n\
923 [Do not] put literals in the text section\n\
924 --[no-]absolute-literals\n\
925 [Do not] default to use non-PC-relative literals\n\
926 --[no-]target-align [Do not] try to align branch targets\n\
927 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
928 --[no-]transform [Do not] transform instructions\n\
929 --rename-section old=new Rename section 'old' to 'new'\n", stream);
e0001a05
NC		 930}
931
7fa3d080
BW		 932\f
933/* Functions related to the list of current label symbols. */
43cd72b9
BW		 934
935static void
7fa3d080 936xtensa_add_insn_label (symbolS *sym)
43cd72b9 937{
7fa3d080 938 sym_list *l;
43cd72b9 939
7fa3d080
BW		 940 if (!free_insn_labels)
941 l = (sym_list *) xmalloc (sizeof (sym_list));
942 else
43cd72b9 943 {
7fa3d080
BW		 944 l = free_insn_labels;
945 free_insn_labels = l->next;
946 }
947
948 l->sym = sym;
949 l->next = insn_labels;
950 insn_labels = l;
951}
952
953
954static void
955xtensa_clear_insn_labels (void)
956{
957 sym_list **pl;
958
959 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
960 ;
961 *pl = insn_labels;
962 insn_labels = NULL;
963}
964
965
7fa3d080 966static void
c3ea6048 967xtensa_move_labels (fragS *new_frag, valueT new_offset)
7fa3d080
BW		 968{
969 sym_list *lit;
970
971 for (lit = insn_labels; lit; lit = lit->next)
972 {
973 symbolS *lit_sym = lit->sym;
c3ea6048
BW		 974 S_SET_VALUE (lit_sym, new_offset);
975 symbol_set_frag (lit_sym, new_frag);
43cd72b9
BW		 976 }
977}
978
e0001a05
NC		 979\f
980/* Directive data and functions. */
981
982typedef struct state_stackS_struct
983{
984 directiveE directive;
985 bfd_boolean negated;
986 bfd_boolean old_state;
987 const char *file;
988 unsigned int line;
989 const void *datum;
990 struct state_stackS_struct *prev;
991} state_stackS;
992
993state_stackS *directive_state_stack;
994
995const pseudo_typeS md_pseudo_table[] =
996{
43cd72b9
BW		 997 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
998 { "literal_position", xtensa_literal_position, 0 },
999 { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */
1000 { "long", xtensa_elf_cons, 4 },
1001 { "word", xtensa_elf_cons, 4 },
1002 { "short", xtensa_elf_cons, 2 },
1003 { "begin", xtensa_begin_directive, 0 },
1004 { "end", xtensa_end_directive, 0 },
43cd72b9
BW		 1005 { "literal", xtensa_literal_pseudo, 0 },
1006 { "frequency", xtensa_frequency_pseudo, 0 },
1007 { NULL, 0, 0 },
e0001a05
NC		 1008};
1009
1010
7fa3d080
BW		 1011static bfd_boolean
1012use_transform (void)
e0001a05 1013{
43cd72b9
BW		 1014 /* After md_end, you should be checking frag by frag, rather
1015 than state directives. */
1016 assert (!past_xtensa_end);
1017 return directive_state[directive_transform];
e0001a05
NC		 1018}
1019
1020
7fa3d080
BW		 1021static bfd_boolean
1022do_align_targets (void)
e0001a05 1023{
7b1cc377
BW		 1024 /* Do not use this function after md_end; just look at align_targets
1025 instead. There is no target-align directive, so alignment is either
1026 enabled for all frags or not done at all. */
43cd72b9
BW		 1027 assert (!past_xtensa_end);
1028 return align_targets && use_transform ();
e0001a05
NC		 1029}
1030
1031
1032static void
7fa3d080 1033directive_push (directiveE directive, bfd_boolean negated, const void *datum)
e0001a05
NC		 1034{
1035 char *file;
1036 unsigned int line;
1037 state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS));
1038
1039 as_where (&file, &line);
1040
1041 stack->directive = directive;
1042 stack->negated = negated;
1043 stack->old_state = directive_state[directive];
1044 stack->file = file;
1045 stack->line = line;
1046 stack->datum = datum;
1047 stack->prev = directive_state_stack;
1048 directive_state_stack = stack;
1049
1050 directive_state[directive] = !negated;
1051}
1052
7fa3d080 1053
e0001a05 1054static void
7fa3d080
BW		 1055directive_pop (directiveE *directive,
1056 bfd_boolean *negated,
1057 const char **file,
1058 unsigned int *line,
1059 const void **datum)
e0001a05
NC		 1060{
1061 state_stackS *top = directive_state_stack;
1062
1063 if (!directive_state_stack)
1064 {
1065 as_bad (_("unmatched end directive"));
1066 *directive = directive_none;
1067 return;
1068 }
1069
1070 directive_state[directive_state_stack->directive] = top->old_state;
1071 *directive = top->directive;
1072 *negated = top->negated;
1073 *file = top->file;
1074 *line = top->line;
1075 *datum = top->datum;
1076 directive_state_stack = top->prev;
1077 free (top);
1078}
1079
1080
1081static void
7fa3d080 1082directive_balance (void)
e0001a05
NC		 1083{
1084 while (directive_state_stack)
1085 {
1086 directiveE directive;
1087 bfd_boolean negated;
1088 const char *file;
1089 unsigned int line;
1090 const void *datum;
1091
1092 directive_pop (&directive, &negated, &file, &line, &datum);
1093 as_warn_where ((char *) file, line,
1094 _(".begin directive with no matching .end directive"));
1095 }
1096}
1097
1098
1099static bfd_boolean
7fa3d080 1100inside_directive (directiveE dir)
e0001a05
NC		 1101{
1102 state_stackS *top = directive_state_stack;
1103
1104 while (top && top->directive != dir)
1105 top = top->prev;
1106
1107 return (top != NULL);
1108}
1109
1110
1111static void
7fa3d080 1112get_directive (directiveE *directive, bfd_boolean *negated)
e0001a05
NC		 1113{
1114 int len;
1115 unsigned i;
43cd72b9 1116 char *directive_string;
e0001a05
NC		 1117
1118 if (strncmp (input_line_pointer, "no-", 3) != 0)
1119 *negated = FALSE;
1120 else
1121 {
1122 *negated = TRUE;
1123 input_line_pointer += 3;
1124 }
1125
1126 len = strspn (input_line_pointer,
43cd72b9
BW		 1127 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1128
1129 /* This code is a hack to make .begin [no-][generics|relax] exactly
1130 equivalent to .begin [no-]transform. We should remove it when
1131 we stop accepting those options. */
c138bc38 1132
43cd72b9
BW		 1133 if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0)
1134 {
1135 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1136 directive_string = "transform";
1137 }
1138 else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0)
1139 {
1140 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1141 directive_string = "transform";
c138bc38 1142 }
43cd72b9
BW		 1143 else
1144 directive_string = input_line_pointer;
e0001a05
NC		 1145
1146 for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i)
1147 {
43cd72b9 1148 if (strncmp (directive_string, directive_info[i].name, len) == 0)
e0001a05
NC		 1149 {
1150 input_line_pointer += len;
1151 *directive = (directiveE) i;
1152 if (*negated && !directive_info[i].can_be_negated)
43cd72b9 1153 as_bad (_("directive %s cannot be negated"),
e0001a05
NC		 1154 directive_info[i].name);
1155 return;
1156 }
1157 }
1158
1159 as_bad (_("unknown directive"));
1160 *directive = (directiveE) XTENSA_UNDEFINED;
1161}
1162
1163
1164static void
7fa3d080 1165xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
e0001a05
NC		 1166{
1167 directiveE directive;
1168 bfd_boolean negated;
1169 emit_state *state;
e0001a05
NC		 1170 lit_state *ls;
1171
1172 get_directive (&directive, &negated);
1173 if (directive == (directiveE) XTENSA_UNDEFINED)
1174 {
1175 discard_rest_of_line ();
1176 return;
1177 }
1178
43cd72b9
BW		 1179 if (cur_vinsn.inside_bundle)
1180 as_bad (_("directives are not valid inside bundles"));
1181
e0001a05
NC		 1182 switch (directive)
1183 {
1184 case directive_literal:
82e7541d
BW		 1185 if (!inside_directive (directive_literal))
1186 {
1187 /* Previous labels go with whatever follows this directive, not with
1188 the literal, so save them now. */
1189 saved_insn_labels = insn_labels;
1190 insn_labels = NULL;
1191 }
43cd72b9 1192 as_warn (_(".begin literal is deprecated; use .literal instead"));
e0001a05
NC		 1193 state = (emit_state *) xmalloc (sizeof (emit_state));
1194 xtensa_switch_to_literal_fragment (state);
1195 directive_push (directive_literal, negated, state);
1196 break;
1197
1198 case directive_literal_prefix:
c138bc38 1199 /* Have to flush pending output because a movi relaxed to an l32r
43cd72b9
BW		 1200 might produce a literal. */
1201 md_flush_pending_output ();
e0001a05
NC		 1202 /* Check to see if the current fragment is a literal
1203 fragment. If it is, then this operation is not allowed. */
43cd72b9 1204 if (generating_literals)
e0001a05
NC		 1205 {
1206 as_bad (_("cannot set literal_prefix inside literal fragment"));
1207 return;
1208 }
1209
1210 /* Allocate the literal state for this section and push
1211 onto the directive stack. */
1212 ls = xmalloc (sizeof (lit_state));
1213 assert (ls);
1214
1215 *ls = default_lit_sections;
e0001a05
NC		 1216 directive_push (directive_literal_prefix, negated, ls);
1217
e0001a05 1218 /* Process the new prefix. */
74869ac7 1219 xtensa_literal_prefix ();
e0001a05
NC		 1220 break;
1221
1222 case directive_freeregs:
1223 /* This information is currently unused, but we'll accept the statement
1224 and just discard the rest of the line. This won't check the syntax,
1225 but it will accept every correct freeregs directive. */
1226 input_line_pointer += strcspn (input_line_pointer, "\n");
1227 directive_push (directive_freeregs, negated, 0);
1228 break;
1229
43cd72b9
BW		 1230 case directive_schedule:
1231 md_flush_pending_output ();
1232 frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
1233 frag_now->fr_symbol, frag_now->fr_offset, NULL);
1234 directive_push (directive_schedule, negated, 0);
1235 xtensa_set_frag_assembly_state (frag_now);
1236 break;
1237
e0001a05 1238 case directive_density:
43cd72b9
BW		 1239 as_warn (_(".begin [no-]density is ignored"));
1240 break;
1241
1242 case directive_absolute_literals:
1243 md_flush_pending_output ();
1244 if (!absolute_literals_supported && !negated)
e0001a05 1245 {
43cd72b9 1246 as_warn (_("Xtensa absolute literals option not supported; ignored"));
e0001a05
NC		 1247 break;
1248 }
43cd72b9
BW		 1249 xtensa_set_frag_assembly_state (frag_now);
1250 directive_push (directive, negated, 0);
1251 break;
e0001a05
NC		 1252
1253 default:
43cd72b9
BW		 1254 md_flush_pending_output ();
1255 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 1256 directive_push (directive, negated, 0);
1257 break;
1258 }
1259
1260 demand_empty_rest_of_line ();
1261}
1262
1263
1264static void
7fa3d080 1265xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
e0001a05
NC		 1266{
1267 directiveE begin_directive, end_directive;
1268 bfd_boolean begin_negated, end_negated;
1269 const char *file;
1270 unsigned int line;
1271 emit_state *state;
43cd72b9 1272 emit_state **state_ptr;
e0001a05
NC		 1273 lit_state *s;
1274
43cd72b9
BW		 1275 if (cur_vinsn.inside_bundle)
1276 as_bad (_("directives are not valid inside bundles"));
82e7541d 1277
e0001a05 1278 get_directive (&end_directive, &end_negated);
43cd72b9
BW		 1279
1280 md_flush_pending_output ();
1281
1282 switch (end_directive)
e0001a05 1283 {
43cd72b9 1284 case (directiveE) XTENSA_UNDEFINED:
e0001a05
NC		 1285 discard_rest_of_line ();
1286 return;
e0001a05 1287
43cd72b9
BW		 1288 case directive_density:
1289 as_warn (_(".end [no-]density is ignored"));
e0001a05 1290 demand_empty_rest_of_line ();
43cd72b9
BW		 1291 break;
1292
1293 case directive_absolute_literals:
1294 if (!absolute_literals_supported && !end_negated)
1295 {
1296 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1297 demand_empty_rest_of_line ();
1298 return;
1299 }
1300 break;
1301
1302 default:
1303 break;
e0001a05
NC		 1304 }
1305
43cd72b9 1306 state_ptr = &state; /* use state_ptr to avoid type-punning warning */
e0001a05 1307 directive_pop (&begin_directive, &begin_negated, &file, &line,
43cd72b9 1308 (const void **) state_ptr);
e0001a05
NC		 1309
1310 if (begin_directive != directive_none)
1311 {
1312 if (begin_directive != end_directive || begin_negated != end_negated)
1313 {
1314 as_bad (_("does not match begin %s%s at %s:%d"),
1315 begin_negated ? "no-" : "",
1316 directive_info[begin_directive].name, file, line);
1317 }
1318 else
1319 {
1320 switch (end_directive)
1321 {
1322 case directive_literal:
1323 frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL);
1324 xtensa_restore_emit_state (state);
43cd72b9 1325 xtensa_set_frag_assembly_state (frag_now);
e0001a05 1326 free (state);
82e7541d
BW		 1327 if (!inside_directive (directive_literal))
1328 {
1329 /* Restore the list of current labels. */
1330 xtensa_clear_insn_labels ();
1331 insn_labels = saved_insn_labels;
1332 }
e0001a05
NC		 1333 break;
1334
e0001a05
NC		 1335 case directive_literal_prefix:
1336 /* Restore the default collection sections from saved state. */
1337 s = (lit_state *) state;
1338 assert (s);
e8247da7 1339 default_lit_sections = *s;
e0001a05 1340
74869ac7
BW		 1341 /* Free the state storage. */
1342 free (s->lit_prefix);
e0001a05
NC		 1343 free (s);
1344 break;
1345
43cd72b9
BW		 1346 case directive_schedule:
1347 case directive_freeregs:
1348 break;
1349
e0001a05 1350 default:
43cd72b9 1351 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 1352 break;
1353 }
1354 }
1355 }
1356
1357 demand_empty_rest_of_line ();
1358}
1359
1360
1361/* Place an aligned literal fragment at the current location. */
1362
1363static void
7fa3d080 1364xtensa_literal_position (int ignore ATTRIBUTE_UNUSED)
e0001a05 1365{
43cd72b9
BW		 1366 md_flush_pending_output ();
1367
e0001a05
NC		 1368 if (inside_directive (directive_literal))
1369 as_warn (_(".literal_position inside literal directive; ignoring"));
43cd72b9 1370 xtensa_mark_literal_pool_location ();
e0001a05
NC		 1371
1372 demand_empty_rest_of_line ();
82e7541d 1373 xtensa_clear_insn_labels ();
e0001a05
NC		 1374}
1375
1376
43cd72b9 1377/* Support .literal label, expr, ... */
e0001a05
NC		 1378
1379static void
7fa3d080 1380xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED)
e0001a05
NC		 1381{
1382 emit_state state;
1745fcba 1383 char *p, *base_name;
e0001a05 1384 char c;
e0001a05
NC		 1385 segT dest_seg;
1386
82e7541d
BW		 1387 if (inside_directive (directive_literal))
1388 {
1389 as_bad (_(".literal not allowed inside .begin literal region"));
1390 ignore_rest_of_line ();
1391 return;
1392 }
1393
43cd72b9
BW		 1394 md_flush_pending_output ();
1395
82e7541d
BW		 1396 /* Previous labels go with whatever follows this directive, not with
1397 the literal, so save them now. */
1398 saved_insn_labels = insn_labels;
1399 insn_labels = NULL;
1400
e0001a05
NC		 1401 /* If we are using text-section literals, then this is the right value... */
1402 dest_seg = now_seg;
1403
1404 base_name = input_line_pointer;
1405
1406 xtensa_switch_to_literal_fragment (&state);
1407
43cd72b9 1408 /* ...but if we aren't using text-section-literals, then we
e0001a05 1409 need to put them in the section we just switched to. */
43cd72b9 1410 if (use_literal_section || directive_state[directive_absolute_literals])
e0001a05
NC		 1411 dest_seg = now_seg;
1412
43cd72b9
BW		 1413 /* All literals are aligned to four-byte boundaries. */
1414 frag_align (2, 0, 0);
1415 record_alignment (now_seg, 2);
e0001a05
NC		 1416
1417 c = get_symbol_end ();
1418 /* Just after name is now '\0'. */
1419 p = input_line_pointer;
1420 *p = c;
1421 SKIP_WHITESPACE ();
1422
1423 if (*input_line_pointer != ',' && *input_line_pointer != ':')
1424 {
1425 as_bad (_("expected comma or colon after symbol name; "
1426 "rest of line ignored"));
1427 ignore_rest_of_line ();
1428 xtensa_restore_emit_state (&state);
1429 return;
1430 }
1431 *p = 0;
1432
e0001a05 1433 colon (base_name);
e0001a05 1434
e0001a05 1435 *p = c;
43cd72b9 1436 input_line_pointer++; /* skip ',' or ':' */
e0001a05 1437
43cd72b9 1438 xtensa_elf_cons (4);
e0001a05
NC		 1439
1440 xtensa_restore_emit_state (&state);
82e7541d
BW		 1441
1442 /* Restore the list of current labels. */
1443 xtensa_clear_insn_labels ();
1444 insn_labels = saved_insn_labels;
e0001a05
NC		 1445}
1446
1447
1448static void
74869ac7 1449xtensa_literal_prefix (void)
e0001a05 1450{
74869ac7
BW		 1451 char *name;
1452 int len;
1453
1454 /* Parse the new prefix from the input_line_pointer. */
1455 SKIP_WHITESPACE ();
1456 len = strspn (input_line_pointer,
1457 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1458 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
e0001a05
NC		 1459
1460 /* Get a null-terminated copy of the name. */
1461 name = xmalloc (len + 1);
1462 assert (name);
74869ac7 1463 strncpy (name, input_line_pointer, len);
e0001a05
NC		 1464 name[len] = 0;
1465
74869ac7
BW		 1466 /* Skip the name in the input line. */
1467 input_line_pointer += len;
43cd72b9 1468
74869ac7 1469 default_lit_sections.lit_prefix = name;
43cd72b9 1470
74869ac7 1471 /* Clear cached literal sections, since the prefix has changed. */
43cd72b9
BW		 1472 default_lit_sections.lit_seg = NULL;
1473 default_lit_sections.lit4_seg = NULL;
43cd72b9
BW		 1474}
1475
1476
1477/* Support ".frequency branch_target_frequency fall_through_frequency". */
1478
1479static void
7fa3d080 1480xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED)
43cd72b9
BW		 1481{
1482 float fall_through_f, target_f;
43cd72b9
BW		 1483
1484 fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer);
1485 if (fall_through_f < 0)
1486 {
1487 as_bad (_("fall through frequency must be greater than 0"));
1488 ignore_rest_of_line ();
1489 return;
1490 }
1491
1492 target_f = (float) strtod (input_line_pointer, &input_line_pointer);
1493 if (target_f < 0)
1494 {
1495 as_bad (_("branch target frequency must be greater than 0"));
1496 ignore_rest_of_line ();
1497 return;
1498 }
1499
b08b5071 1500 set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f);
43cd72b9
BW		 1501
1502 demand_empty_rest_of_line ();
1503}
1504
1505
1506/* Like normal .long/.short/.word, except support @plt, etc.
1507 Clobbers input_line_pointer, checks end-of-line. */
1508
1509static void
7fa3d080 1510xtensa_elf_cons (int nbytes)
43cd72b9
BW		 1511{
1512 expressionS exp;
1513 bfd_reloc_code_real_type reloc;
1514
1515 md_flush_pending_output ();
1516
1517 if (cur_vinsn.inside_bundle)
1518 as_bad (_("directives are not valid inside bundles"));
1519
1520 if (is_it_end_of_statement ())
1521 {
1522 demand_empty_rest_of_line ();
1523 return;
1524 }
1525
1526 do
1527 {
1528 expression (&exp);
1529 if (exp.X_op == O_symbol
1530 && *input_line_pointer == '@'
1531 && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp))
1532 != BFD_RELOC_NONE))
1533 {
1534 reloc_howto_type *reloc_howto =
1535 bfd_reloc_type_lookup (stdoutput, reloc);
1536
1537 if (reloc == BFD_RELOC_UNUSED || !reloc_howto)
1538 as_bad (_("unsupported relocation"));
1539 else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP
1540 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
1541 || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
1542 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT))
1543 as_bad (_("opcode-specific %s relocation used outside "
1544 "an instruction"), reloc_howto->name);
1545 else if (nbytes != (int) bfd_get_reloc_size (reloc_howto))
1546 as_bad (_("%s relocations do not fit in %d bytes"),
1547 reloc_howto->name, nbytes);
1548 else
1549 {
1550 char *p = frag_more ((int) nbytes);
1551 xtensa_set_frag_assembly_state (frag_now);
1552 fix_new_exp (frag_now, p - frag_now->fr_literal,
1553 nbytes, &exp, 0, reloc);
1554 }
1555 }
1556 else
1557 emit_expr (&exp, (unsigned int) nbytes);
1558 }
1559 while (*input_line_pointer++ == ',');
1560
1561 input_line_pointer--; /* Put terminator back into stream. */
1562 demand_empty_rest_of_line ();
1563}
1564
7fa3d080
BW		 1565\f
1566/* Parsing and Idiom Translation. */
43cd72b9
BW		 1567
1568/* Parse @plt, etc. and return the desired relocation. */
1569static bfd_reloc_code_real_type
7fa3d080 1570xtensa_elf_suffix (char **str_p, expressionS *exp_p)
43cd72b9 1571{
43cd72b9
BW		 1572 char ident[20];
1573 char *str = *str_p;
1574 char *str2;
1575 int ch;
1576 int len;
bbdd25a8 1577 struct suffix_reloc_map *ptr;
43cd72b9
BW		 1578
1579 if (*str++ != '@')
1580 return BFD_RELOC_NONE;
1581
1582 for (ch = *str, str2 = ident;
1583 (str2 < ident + sizeof (ident) - 1
1584 && (ISALNUM (ch) || ch == '@'));
1585 ch = *++str)
1586 {
1587 *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch);
1588 }
1589
1590 *str2 = '\0';
1591 len = str2 - ident;
1592
1593 ch = ident[0];
bbdd25a8
BW		 1594 for (ptr = &suffix_relocs[0]; ptr->length > 0; ptr++)
1595 if (ch == ptr->suffix[0]
43cd72b9 1596 && len == ptr->length
bbdd25a8 1597 && memcmp (ident, ptr->suffix, ptr->length) == 0)
43cd72b9
BW		 1598 {
1599 /* Now check for "identifier@suffix+constant". */
1600 if (*str == '-' || *str == '+')
1601 {
1602 char *orig_line = input_line_pointer;
1603 expressionS new_exp;
1604
1605 input_line_pointer = str;
1606 expression (&new_exp);
1607 if (new_exp.X_op == O_constant)
1608 {
1609 exp_p->X_add_number += new_exp.X_add_number;
1610 str = input_line_pointer;
1611 }
1612
1613 if (&input_line_pointer != str_p)
1614 input_line_pointer = orig_line;
1615 }
1616
1617 *str_p = str;
1618 return ptr->reloc;
1619 }
1620
1621 return BFD_RELOC_UNUSED;
e0001a05
NC		 1622}
1623
e0001a05 1624
bbdd25a8
BW		 1625/* Find the matching operator type. */
1626static unsigned char
1627map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc)
1628{
1629 struct suffix_reloc_map *sfx;
1630 unsigned char operator = (unsigned char) -1;
1631
1632 for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++)
1633 {
1634 if (sfx->reloc == reloc)
1635 {
1636 operator = sfx->operator;
1637 break;
1638 }
1639 }
1640 assert (operator != (unsigned char) -1);
1641 return operator;
1642}
1643
1644
1645/* Find the matching reloc type. */
1646static bfd_reloc_code_real_type
1647map_operator_to_reloc (unsigned char operator)
1648{
1649 struct suffix_reloc_map *sfx;
1650 bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
1651
1652 for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++)
1653 {
1654 if (sfx->operator == operator)
1655 {
1656 reloc = sfx->reloc;
1657 break;
1658 }
1659 }
1660
1661 if (reloc == BFD_RELOC_UNUSED)
1662 return BFD_RELOC_32;
1663
1664 return reloc;
1665}
1666
1667
e0001a05 1668static const char *
7fa3d080 1669expression_end (const char *name)
e0001a05
NC		 1670{
1671 while (1)
1672 {
1673 switch (*name)
1674 {
43cd72b9 1675 case '}':
e0001a05
NC		 1676 case ';':
1677 case '\0':
1678 case ',':
43cd72b9 1679 case ':':
e0001a05
NC		 1680 return name;
1681 case ' ':
1682 case '\t':
1683 ++name;
1684 continue;
1685 default:
1686 return 0;
1687 }
1688 }
1689}
1690
1691
1692#define ERROR_REG_NUM ((unsigned) -1)
1693
1694static unsigned
7fa3d080 1695tc_get_register (const char *prefix)
e0001a05
NC		 1696{
1697 unsigned reg;
1698 const char *next_expr;
1699 const char *old_line_pointer;
1700
1701 SKIP_WHITESPACE ();
1702 old_line_pointer = input_line_pointer;
1703
1704 if (*input_line_pointer == '$')
1705 ++input_line_pointer;
1706
1707 /* Accept "sp" as a synonym for "a1". */
1708 if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p'
1709 && expression_end (input_line_pointer + 2))
1710 {
1711 input_line_pointer += 2;
1712 return 1; /* AR[1] */
1713 }
1714
1715 while (*input_line_pointer++ == *prefix++)
1716 ;
1717 --input_line_pointer;
1718 --prefix;
1719
1720 if (*prefix)
1721 {
1722 as_bad (_("bad register name: %s"), old_line_pointer);
1723 return ERROR_REG_NUM;
1724 }
1725
1726 if (!ISDIGIT ((unsigned char) *input_line_pointer))
1727 {
1728 as_bad (_("bad register number: %s"), input_line_pointer);
1729 return ERROR_REG_NUM;
1730 }
1731
1732 reg = 0;
1733
1734 while (ISDIGIT ((int) *input_line_pointer))
1735 reg = reg * 10 + *input_line_pointer++ - '0';
1736
1737 if (!(next_expr = expression_end (input_line_pointer)))
1738 {
1739 as_bad (_("bad register name: %s"), old_line_pointer);
1740 return ERROR_REG_NUM;
1741 }
1742
1743 input_line_pointer = (char *) next_expr;
1744
1745 return reg;
1746}
1747
1748
e0001a05 1749static void
7fa3d080 1750expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok)
e0001a05 1751{
43cd72b9 1752 xtensa_isa isa = xtensa_default_isa;
e0001a05 1753
43cd72b9
BW		 1754 /* Check if this is an immediate operand. */
1755 if (xtensa_operand_is_register (isa, opc, opnd) == 0)
e0001a05 1756 {
43cd72b9 1757 bfd_reloc_code_real_type reloc;
e0001a05 1758 segT t = expression (tok);
43cd72b9
BW		 1759 if (t == absolute_section
1760 && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
e0001a05
NC		 1761 {
1762 assert (tok->X_op == O_constant);
1763 tok->X_op = O_symbol;
1764 tok->X_add_symbol = &abs_symbol;
1765 }
43cd72b9
BW		 1766
1767 if ((tok->X_op == O_constant || tok->X_op == O_symbol)
bbdd25a8
BW		 1768 && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok))
1769 != BFD_RELOC_NONE))
e0001a05 1770 {
bbdd25a8 1771 if (reloc == BFD_RELOC_UNUSED)
43cd72b9 1772 {
bbdd25a8
BW		 1773 as_bad (_("unsupported relocation"));
1774 return;
1775 }
43cd72b9 1776
bbdd25a8
BW		 1777 if (tok->X_op == O_constant)
1778 {
1779 switch (reloc)
1780 {
1781 case BFD_RELOC_LO16:
43cd72b9 1782 tok->X_add_number &= 0xffff;
bbdd25a8 1783 return;
43cd72b9 1784
bbdd25a8 1785 case BFD_RELOC_HI16:
43cd72b9 1786 tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
bbdd25a8
BW		 1787 return;
1788
1789 default:
1790 break;
1791 }
43cd72b9 1792 }
bbdd25a8 1793 tok->X_op = map_suffix_reloc_to_operator (reloc);
e0001a05 1794 }
e0001a05
NC		 1795 }
1796 else
1797 {
43cd72b9
BW		 1798 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
1799 unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf));
e0001a05
NC		 1800
1801 if (reg != ERROR_REG_NUM) /* Already errored */
1802 {
1803 uint32 buf = reg;
43cd72b9 1804 if (xtensa_operand_encode (isa, opc, opnd, &buf))
e0001a05
NC		 1805 as_bad (_("register number out of range"));
1806 }
1807
1808 tok->X_op = O_register;
1809 tok->X_add_symbol = 0;
1810 tok->X_add_number = reg;
1811 }
1812}
1813
1814
1815/* Split up the arguments for an opcode or pseudo-op. */
1816
1817static int
7fa3d080 1818tokenize_arguments (char **args, char *str)
e0001a05
NC		 1819{
1820 char *old_input_line_pointer;
1821 bfd_boolean saw_comma = FALSE;
1822 bfd_boolean saw_arg = FALSE;
43cd72b9 1823 bfd_boolean saw_colon = FALSE;
e0001a05
NC		 1824 int num_args = 0;
1825 char *arg_end, *arg;
1826 int arg_len;
43cd72b9
BW		 1827
1828 /* Save and restore input_line_pointer around this function. */
e0001a05
NC		 1829 old_input_line_pointer = input_line_pointer;
1830 input_line_pointer = str;
1831
1832 while (*input_line_pointer)
1833 {
1834 SKIP_WHITESPACE ();
1835 switch (*input_line_pointer)
1836 {
1837 case '\0':
43cd72b9 1838 case '}':
e0001a05
NC		 1839 goto fini;
1840
43cd72b9
BW		 1841 case ':':
1842 input_line_pointer++;
1843 if (saw_comma || saw_colon || !saw_arg)
1844 goto err;
1845 saw_colon = TRUE;
1846 break;
1847
e0001a05
NC		 1848 case ',':
1849 input_line_pointer++;
43cd72b9 1850 if (saw_comma || saw_colon || !saw_arg)
e0001a05
NC		 1851 goto err;
1852 saw_comma = TRUE;
1853 break;
1854
1855 default:
43cd72b9 1856 if (!saw_comma && !saw_colon && saw_arg)
e0001a05
NC		 1857 goto err;
1858
1859 arg_end = input_line_pointer + 1;
1860 while (!expression_end (arg_end))
1861 arg_end += 1;
43cd72b9 1862
e0001a05 1863 arg_len = arg_end - input_line_pointer;
43cd72b9 1864 arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1);
e0001a05
NC		 1865 args[num_args] = arg;
1866
43cd72b9
BW		 1867 if (saw_colon)
1868 *arg++ = ':';
e0001a05
NC		 1869 strncpy (arg, input_line_pointer, arg_len);
1870 arg[arg_len] = '\0';
43cd72b9 1871
e0001a05
NC		 1872 input_line_pointer = arg_end;
1873 num_args += 1;
c138bc38 1874 saw_comma = FALSE;
43cd72b9 1875 saw_colon = FALSE;
c138bc38 1876 saw_arg = TRUE;
e0001a05
NC		 1877 break;
1878 }
1879 }
1880
1881fini:
43cd72b9 1882 if (saw_comma || saw_colon)
e0001a05
NC		 1883 goto err;
1884 input_line_pointer = old_input_line_pointer;
1885 return num_args;
1886
1887err:
43cd72b9
BW		 1888 if (saw_comma)
1889 as_bad (_("extra comma"));
1890 else if (saw_colon)
1891 as_bad (_("extra colon"));
1892 else if (!saw_arg)
c138bc38 1893 as_bad (_("missing argument"));
43cd72b9
BW		 1894 else
1895 as_bad (_("missing comma or colon"));
e0001a05
NC		 1896 input_line_pointer = old_input_line_pointer;
1897 return -1;
1898}
1899
1900
43cd72b9 1901/* Parse the arguments to an opcode. Return TRUE on error. */
e0001a05
NC		 1902
1903static bfd_boolean
7fa3d080 1904parse_arguments (TInsn *insn, int num_args, char **arg_strings)
e0001a05 1905{
43cd72b9 1906 expressionS *tok, *last_tok;
e0001a05
NC		 1907 xtensa_opcode opcode = insn->opcode;
1908 bfd_boolean had_error = TRUE;
43cd72b9
BW		 1909 xtensa_isa isa = xtensa_default_isa;
1910 int n, num_regs = 0;
e0001a05 1911 int opcode_operand_count;
43cd72b9
BW		 1912 int opnd_cnt, last_opnd_cnt;
1913 unsigned int next_reg = 0;
e0001a05
NC		 1914 char *old_input_line_pointer;
1915
1916 if (insn->insn_type == ITYPE_LITERAL)
1917 opcode_operand_count = 1;
1918 else
43cd72b9 1919 opcode_operand_count = xtensa_opcode_num_operands (isa, opcode);
e0001a05 1920
43cd72b9 1921 tok = insn->tok;
e0001a05
NC		 1922 memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS);
1923
1924 /* Save and restore input_line_pointer around this function. */
43cd72b9
BW		 1925 old_input_line_pointer = input_line_pointer;
1926
1927 last_tok = 0;
1928 last_opnd_cnt = -1;
1929 opnd_cnt = 0;
1930
1931 /* Skip invisible operands. */
1932 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0)
1933 {
1934 opnd_cnt += 1;
1935 tok++;
1936 }
e0001a05
NC		 1937
1938 for (n = 0; n < num_args; n++)
43cd72b9 1939 {
e0001a05 1940 input_line_pointer = arg_strings[n];
43cd72b9
BW		 1941 if (*input_line_pointer == ':')
1942 {
1943 xtensa_regfile opnd_rf;
1944 input_line_pointer++;
1945 if (num_regs == 0)
1946 goto err;
1947 assert (opnd_cnt > 0);
1948 num_regs--;
1949 opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt);
1950 if (next_reg
1951 != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)))
1952 as_warn (_("incorrect register number, ignoring"));
1953 next_reg++;
1954 }
1955 else
1956 {
1957 if (opnd_cnt >= opcode_operand_count)
1958 {
1959 as_warn (_("too many arguments"));
1960 goto err;
1961 }
1962 assert (opnd_cnt < MAX_INSN_ARGS);
1963
1964 expression_maybe_register (opcode, opnd_cnt, tok);
1965 next_reg = tok->X_add_number + 1;
1966
1967 if (tok->X_op == O_illegal || tok->X_op == O_absent)
1968 goto err;
1969 if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1)
1970 {
1971 num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1;
1972 /* minus 1 because we are seeing one right now */
1973 }
1974 else
1975 num_regs = 0;
e0001a05 1976
43cd72b9
BW		 1977 last_tok = tok;
1978 last_opnd_cnt = opnd_cnt;
e0001a05 1979
43cd72b9
BW		 1980 do
1981 {
1982 opnd_cnt += 1;
1983 tok++;
1984 }
1985 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0);
1986 }
1987 }
e0001a05 1988
43cd72b9
BW		 1989 if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1))
1990 goto err;
e0001a05
NC		 1991
1992 insn->ntok = tok - insn->tok;
c138bc38 1993 had_error = FALSE;
e0001a05
NC		 1994
1995 err:
43cd72b9 1996 input_line_pointer = old_input_line_pointer;
e0001a05
NC		 1997 return had_error;
1998}
1999
2000
43cd72b9 2001static int
7fa3d080 2002get_invisible_operands (TInsn *insn)
43cd72b9
BW		 2003{
2004 xtensa_isa isa = xtensa_default_isa;
2005 static xtensa_insnbuf slotbuf = NULL;
2006 xtensa_format fmt;
2007 xtensa_opcode opc = insn->opcode;
2008 int slot, opnd, fmt_found;
2009 unsigned val;
2010
2011 if (!slotbuf)
2012 slotbuf = xtensa_insnbuf_alloc (isa);
2013
2014 /* Find format/slot where this can be encoded. */
2015 fmt_found = 0;
2016 slot = 0;
2017 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
2018 {
2019 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
2020 {
2021 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0)
2022 {
2023 fmt_found = 1;
2024 break;
2025 }
2026 }
2027 if (fmt_found) break;
2028 }
2029
2030 if (!fmt_found)
2031 {
2032 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc));
2033 return -1;
2034 }
2035
2036 /* First encode all the visible operands
2037 (to deal with shared field operands). */
2038 for (opnd = 0; opnd < insn->ntok; opnd++)
2039 {
2040 if (xtensa_operand_is_visible (isa, opc, opnd) == 1
2041 && (insn->tok[opnd].X_op == O_register
2042 || insn->tok[opnd].X_op == O_constant))
2043 {
2044 val = insn->tok[opnd].X_add_number;
2045 xtensa_operand_encode (isa, opc, opnd, &val);
2046 xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val);
2047 }
2048 }
2049
2050 /* Then pull out the values for the invisible ones. */
2051 for (opnd = 0; opnd < insn->ntok; opnd++)
2052 {
2053 if (xtensa_operand_is_visible (isa, opc, opnd) == 0)
2054 {
2055 xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val);
2056 xtensa_operand_decode (isa, opc, opnd, &val);
2057 insn->tok[opnd].X_add_number = val;
2058 if (xtensa_operand_is_register (isa, opc, opnd) == 1)
2059 insn->tok[opnd].X_op = O_register;
2060 else
2061 insn->tok[opnd].X_op = O_constant;
2062 }
2063 }
2064
2065 return 0;
2066}
2067
2068
e0001a05 2069static void
7fa3d080 2070xg_reverse_shift_count (char **cnt_argp)
e0001a05
NC		 2071{
2072 char *cnt_arg, *new_arg;
2073 cnt_arg = *cnt_argp;
2074
2075 /* replace the argument with "31-(argument)" */
2076 new_arg = (char *) xmalloc (strlen (cnt_arg) + 6);
2077 sprintf (new_arg, "31-(%s)", cnt_arg);
2078
2079 free (cnt_arg);
2080 *cnt_argp = new_arg;
2081}
2082
2083
2084/* If "arg" is a constant expression, return non-zero with the value
2085 in *valp. */
2086
2087static int
7fa3d080 2088xg_arg_is_constant (char *arg, offsetT *valp)
e0001a05
NC		 2089{
2090 expressionS exp;
2091 char *save_ptr = input_line_pointer;
2092
2093 input_line_pointer = arg;
2094 expression (&exp);
2095 input_line_pointer = save_ptr;
2096
2097 if (exp.X_op == O_constant)
2098 {
2099 *valp = exp.X_add_number;
2100 return 1;
2101 }
2102
2103 return 0;
2104}
2105
2106
2107static void
7fa3d080 2108xg_replace_opname (char **popname, char *newop)
e0001a05
NC		 2109{
2110 free (*popname);
2111 *popname = (char *) xmalloc (strlen (newop) + 1);
2112 strcpy (*popname, newop);
2113}
2114
2115
2116static int
7fa3d080
BW		 2117xg_check_num_args (int *pnum_args,
2118 int expected_num,
2119 char *opname,
2120 char **arg_strings)
e0001a05
NC		 2121{
2122 int num_args = *pnum_args;
2123
43cd72b9 2124 if (num_args < expected_num)
e0001a05
NC		 2125 {
2126 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2127 num_args, opname, expected_num);
2128 return -1;
2129 }
2130
2131 if (num_args > expected_num)
2132 {
2133 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2134 num_args, opname, expected_num);
2135 while (num_args-- > expected_num)
2136 {
2137 free (arg_strings[num_args]);
2138 arg_strings[num_args] = 0;
2139 }
2140 *pnum_args = expected_num;
2141 return -1;
2142 }
2143
2144 return 0;
2145}
2146
2147
43cd72b9
BW		 2148/* If the register is not specified as part of the opcode,
2149 then get it from the operand and move it to the opcode. */
2150
e0001a05 2151static int
7fa3d080 2152xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings)
e0001a05 2153{
43cd72b9
BW		 2154 xtensa_isa isa = xtensa_default_isa;
2155 xtensa_sysreg sr;
e0001a05 2156 char *opname, *new_opname;
43cd72b9
BW		 2157 const char *sr_name;
2158 int is_user, is_write;
e0001a05
NC		 2159
2160 opname = *popname;
2161 if (*opname == '_')
80ca4e2c 2162 opname += 1;
43cd72b9
BW		 2163 is_user = (opname[1] == 'u');
2164 is_write = (opname[0] == 'w');
e0001a05 2165
43cd72b9 2166 /* Opname == [rw]ur or [rwx]sr... */
e0001a05 2167
43cd72b9
BW		 2168 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2169 return -1;
e0001a05 2170
43cd72b9
BW		 2171 /* Check if the argument is a symbolic register name. */
2172 sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]);
2173 /* Handle WSR to "INTSET" as a special case. */
2174 if (sr == XTENSA_UNDEFINED && is_write && !is_user
2175 && !strcasecmp (arg_strings[1], "intset"))
2176 sr = xtensa_sysreg_lookup_name (isa, "interrupt");
2177 if (sr == XTENSA_UNDEFINED
2178 || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user)
2179 {
2180 /* Maybe it's a register number.... */
2181 offsetT val;
e0001a05
NC		 2182 if (!xg_arg_is_constant (arg_strings[1], &val))
2183 {
43cd72b9
BW		 2184 as_bad (_("invalid register '%s' for '%s' instruction"),
2185 arg_strings[1], opname);
e0001a05
NC		 2186 return -1;
2187 }
43cd72b9
BW		 2188 sr = xtensa_sysreg_lookup (isa, val, is_user);
2189 if (sr == XTENSA_UNDEFINED)
e0001a05 2190 {
43cd72b9 2191 as_bad (_("invalid register number (%ld) for '%s' instruction"),
dd49a749 2192 (long) val, opname);
e0001a05
NC		 2193 return -1;
2194 }
43cd72b9 2195 }
e0001a05 2196
43cd72b9
BW		 2197 /* Remove the last argument, which is now part of the opcode. */
2198 free (arg_strings[1]);
2199 arg_strings[1] = 0;
2200 *pnum_args = 1;
2201
2202 /* Translate the opcode. */
2203 sr_name = xtensa_sysreg_name (isa, sr);
2204 /* Another special case for "WSR.INTSET".... */
2205 if (is_write && !is_user && !strcasecmp ("interrupt", sr_name))
2206 sr_name = "intset";
2207 new_opname = (char *) xmalloc (strlen (sr_name) + 6);
80ca4e2c 2208 sprintf (new_opname, "%s.%s", *popname, sr_name);
43cd72b9
BW		 2209 free (*popname);
2210 *popname = new_opname;
2211
2212 return 0;
2213}
2214
2215
2216static int
7fa3d080 2217xtensa_translate_old_userreg_ops (char **popname)
43cd72b9
BW		 2218{
2219 xtensa_isa isa = xtensa_default_isa;
2220 xtensa_sysreg sr;
2221 char *opname, *new_opname;
2222 const char *sr_name;
2223 bfd_boolean has_underbar = FALSE;
2224
2225 opname = *popname;
2226 if (opname[0] == '_')
2227 {
2228 has_underbar = TRUE;
2229 opname += 1;
2230 }
2231
2232 sr = xtensa_sysreg_lookup_name (isa, opname + 1);
2233 if (sr != XTENSA_UNDEFINED)
2234 {
2235 /* The new default name ("nnn") is different from the old default
2236 name ("URnnn"). The old default is handled below, and we don't
2237 want to recognize [RW]nnn, so do nothing if the name is the (new)
2238 default. */
2239 static char namebuf[10];
2240 sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr));
2241 if (strcmp (namebuf, opname + 1) == 0)
2242 return 0;
2243 }
2244 else
2245 {
2246 offsetT val;
2247 char *end;
2248
2249 /* Only continue if the reg name is "URnnn". */
2250 if (opname[1] != 'u' || opname[2] != 'r')
2251 return 0;
2252 val = strtoul (opname + 3, &end, 10);
2253 if (*end != '\0')
2254 return 0;
2255
2256 sr = xtensa_sysreg_lookup (isa, val, 1);
2257 if (sr == XTENSA_UNDEFINED)
2258 {
2259 as_bad (_("invalid register number (%ld) for '%s'"),
dd49a749 2260 (long) val, opname);
43cd72b9
BW		 2261 return -1;
2262 }
2263 }
2264
2265 /* Translate the opcode. */
2266 sr_name = xtensa_sysreg_name (isa, sr);
2267 new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2268 sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""),
2269 opname[0], sr_name);
2270 free (*popname);
2271 *popname = new_opname;
2272
2273 return 0;
2274}
2275
2276
2277static int
7fa3d080
BW		 2278xtensa_translate_zero_immed (char *old_op,
2279 char *new_op,
2280 char **popname,
2281 int *pnum_args,
2282 char **arg_strings)
43cd72b9
BW		 2283{
2284 char *opname;
2285 offsetT val;
2286
2287 opname = *popname;
2288 assert (opname[0] != '_');
2289
2290 if (strcmp (opname, old_op) != 0)
2291 return 0;
e0001a05 2292
43cd72b9
BW		 2293 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2294 return -1;
2295 if (xg_arg_is_constant (arg_strings[1], &val) && val == 0)
2296 {
2297 xg_replace_opname (popname, new_op);
2298 free (arg_strings[1]);
2299 arg_strings[1] = arg_strings[2];
2300 arg_strings[2] = 0;
2301 *pnum_args = 2;
e0001a05
NC		 2302 }
2303
2304 return 0;
2305}
2306
2307
2308/* If the instruction is an idiom (i.e., a built-in macro), translate it.
2309 Returns non-zero if an error was found. */
2310
2311static int
7fa3d080 2312xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
e0001a05
NC		 2313{
2314 char *opname = *popname;
2315 bfd_boolean has_underbar = FALSE;
2316
2317 if (*opname == '_')
2318 {
2319 has_underbar = TRUE;
2320 opname += 1;
2321 }
2322
2323 if (strcmp (opname, "mov") == 0)
2324 {
43cd72b9 2325 if (use_transform () && !has_underbar && density_supported)
e0001a05
NC		 2326 xg_replace_opname (popname, "mov.n");
2327 else
2328 {
2329 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2330 return -1;
2331 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2332 arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1);
2333 strcpy (arg_strings[2], arg_strings[1]);
2334 *pnum_args = 3;
2335 }
2336 return 0;
2337 }
2338
2339 if (strcmp (opname, "bbsi.l") == 0)
2340 {
2341 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2342 return -1;
2343 xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi"));
2344 if (target_big_endian)
2345 xg_reverse_shift_count (&arg_strings[1]);
2346 return 0;
2347 }
2348
2349 if (strcmp (opname, "bbci.l") == 0)
2350 {
2351 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2352 return -1;
2353 xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci"));
2354 if (target_big_endian)
2355 xg_reverse_shift_count (&arg_strings[1]);
2356 return 0;
2357 }
2358
eb6d9dce
BW		 2359 /* Don't do anything special with NOPs inside FLIX instructions. They
2360 are handled elsewhere. Real NOP instructions are always available
2361 in configurations with FLIX, so this should never be an issue but
2362 check for it anyway. */
2363 if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED
43cd72b9 2364 && strcmp (opname, "nop") == 0)
e0001a05 2365 {
43cd72b9 2366 if (use_transform () && !has_underbar && density_supported)
e0001a05
NC		 2367 xg_replace_opname (popname, "nop.n");
2368 else
2369 {
2370 if (xg_check_num_args (pnum_args, 0, opname, arg_strings))
2371 return -1;
2372 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2373 arg_strings[0] = (char *) xmalloc (3);
2374 arg_strings[1] = (char *) xmalloc (3);
2375 arg_strings[2] = (char *) xmalloc (3);
2376 strcpy (arg_strings[0], "a1");
2377 strcpy (arg_strings[1], "a1");
2378 strcpy (arg_strings[2], "a1");
2379 *pnum_args = 3;
2380 }
2381 return 0;
2382 }
2383
43cd72b9
BW		 2384 /* Recognize [RW]UR and [RWX]SR. */
2385 if ((((opname[0] == 'r' || opname[0] == 'w')
2386 && (opname[1] == 'u' || opname[1] == 's'))
2387 || (opname[0] == 'x' && opname[1] == 's'))
2388 && opname[2] == 'r'
2389 && opname[3] == '\0')
e0001a05
NC		 2390 return xg_translate_sysreg_op (popname, pnum_args, arg_strings);
2391
43cd72b9
BW		 2392 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2393 [RW]<name> if <name> is the non-default name of a user register. */
2394 if ((opname[0] == 'r' || opname[0] == 'w')
2395 && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED)
2396 return xtensa_translate_old_userreg_ops (popname);
e0001a05 2397
43cd72b9
BW		 2398 /* Relax branches that don't allow comparisons against an immediate value
2399 of zero to the corresponding branches with implicit zero immediates. */
2400 if (!has_underbar && use_transform ())
2401 {
2402 if (xtensa_translate_zero_immed ("bnei", "bnez", popname,
2403 pnum_args, arg_strings))
2404 return -1;
e0001a05 2405
43cd72b9
BW		 2406 if (xtensa_translate_zero_immed ("beqi", "beqz", popname,
2407 pnum_args, arg_strings))
2408 return -1;
e0001a05 2409
43cd72b9
BW		 2410 if (xtensa_translate_zero_immed ("bgei", "bgez", popname,
2411 pnum_args, arg_strings))
2412 return -1;
e0001a05 2413
43cd72b9
BW		 2414 if (xtensa_translate_zero_immed ("blti", "bltz", popname,
2415 pnum_args, arg_strings))
2416 return -1;
2417 }
e0001a05 2418
43cd72b9
BW		 2419 return 0;
2420}
e0001a05 2421
43cd72b9
BW		 2422\f
2423/* Functions for dealing with the Xtensa ISA. */
e0001a05 2424
43cd72b9
BW		 2425/* Currently the assembler only allows us to use a single target per
2426 fragment. Because of this, only one operand for a given
2427 instruction may be symbolic. If there is a PC-relative operand,
2428 the last one is chosen. Otherwise, the result is the number of the
2429 last immediate operand, and if there are none of those, we fail and
2430 return -1. */
e0001a05 2431
7fa3d080
BW		 2432static int
2433get_relaxable_immed (xtensa_opcode opcode)
43cd72b9
BW		 2434{
2435 int last_immed = -1;
2436 int noperands, opi;
e0001a05 2437
43cd72b9
BW		 2438 if (opcode == XTENSA_UNDEFINED)
2439 return -1;
e0001a05 2440
43cd72b9
BW		 2441 noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode);
2442 for (opi = noperands - 1; opi >= 0; opi--)
2443 {
2444 if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0)
2445 continue;
2446 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1)
2447 return opi;
2448 if (last_immed == -1
2449 && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0)
2450 last_immed = opi;
e0001a05 2451 }
43cd72b9 2452 return last_immed;
e0001a05
NC		 2453}
2454
e0001a05 2455
43cd72b9 2456static xtensa_opcode
7fa3d080 2457get_opcode_from_buf (const char *buf, int slot)
e0001a05 2458{
43cd72b9
BW		 2459 static xtensa_insnbuf insnbuf = NULL;
2460 static xtensa_insnbuf slotbuf = NULL;
2461 xtensa_isa isa = xtensa_default_isa;
2462 xtensa_format fmt;
2463
2464 if (!insnbuf)
e0001a05 2465 {
43cd72b9
BW		 2466 insnbuf = xtensa_insnbuf_alloc (isa);
2467 slotbuf = xtensa_insnbuf_alloc (isa);
e0001a05 2468 }
e0001a05 2469
d77b99c9 2470 xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0);
43cd72b9
BW		 2471 fmt = xtensa_format_decode (isa, insnbuf);
2472 if (fmt == XTENSA_UNDEFINED)
2473 return XTENSA_UNDEFINED;
e0001a05 2474
43cd72b9
BW		 2475 if (slot >= xtensa_format_num_slots (isa, fmt))
2476 return XTENSA_UNDEFINED;
e0001a05 2477
43cd72b9
BW		 2478 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
2479 return xtensa_opcode_decode (isa, fmt, slot, slotbuf);
e0001a05
NC		 2480}
2481
2482
43cd72b9 2483#ifdef TENSILICA_DEBUG
e0001a05 2484
43cd72b9 2485/* For debugging, print out the mapping of opcode numbers to opcodes. */
e0001a05 2486
7fa3d080
BW		 2487static void
2488xtensa_print_insn_table (void)
43cd72b9
BW		 2489{
2490 int num_opcodes, num_operands;
2491 xtensa_opcode opcode;
2492 xtensa_isa isa = xtensa_default_isa;
e0001a05 2493
43cd72b9
BW		 2494 num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
2495 for (opcode = 0; opcode < num_opcodes; opcode++)
e0001a05 2496 {
43cd72b9
BW		 2497 int opn;
2498 fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode));
2499 num_operands = xtensa_opcode_num_operands (isa, opcode);
2500 for (opn = 0; opn < num_operands; opn++)
2501 {
2502 if (xtensa_operand_is_visible (isa, opcode, opn) == 0)
2503 continue;
2504 if (xtensa_operand_is_register (isa, opcode, opn) == 1)
2505 {
2506 xtensa_regfile opnd_rf =
2507 xtensa_operand_regfile (isa, opcode, opn);
2508 fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf));
2509 }
2510 else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1)
2511 fputs ("[lLr] ", stderr);
2512 else
2513 fputs ("i ", stderr);
2514 }
2515 fprintf (stderr, "\n");
e0001a05 2516 }
e0001a05
NC		 2517}
2518
2519
43cd72b9 2520static void
7fa3d080 2521print_vliw_insn (xtensa_insnbuf vbuf)
e0001a05 2522{
e0001a05 2523 xtensa_isa isa = xtensa_default_isa;
43cd72b9
BW		 2524 xtensa_format f = xtensa_format_decode (isa, vbuf);
2525 xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa);
2526 int op;
e0001a05 2527
43cd72b9 2528 fprintf (stderr, "format = %d\n", f);
e0001a05 2529
43cd72b9
BW		 2530 for (op = 0; op < xtensa_format_num_slots (isa, f); op++)
2531 {
2532 xtensa_opcode opcode;
2533 const char *opname;
2534 int operands;
2535
2536 xtensa_format_get_slot (isa, f, op, vbuf, sbuf);
2537 opcode = xtensa_opcode_decode (isa, f, op, sbuf);
2538 opname = xtensa_opcode_name (isa, opcode);
2539
2540 fprintf (stderr, "op in slot %i is %s;\n", op, opname);
2541 fprintf (stderr, " operands = ");
2542 for (operands = 0;
2543 operands < xtensa_opcode_num_operands (isa, opcode);
2544 operands++)
2545 {
2546 unsigned int val;
2547 if (xtensa_operand_is_visible (isa, opcode, operands) == 0)
2548 continue;
2549 xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val);
2550 xtensa_operand_decode (isa, opcode, operands, &val);
2551 fprintf (stderr, "%d ", val);
2552 }
2553 fprintf (stderr, "\n");
2554 }
2555 xtensa_insnbuf_free (isa, sbuf);
e0001a05
NC		 2556}
2557
43cd72b9
BW		 2558#endif /* TENSILICA_DEBUG */
2559
e0001a05
NC		 2560
2561static bfd_boolean
7fa3d080 2562is_direct_call_opcode (xtensa_opcode opcode)
e0001a05 2563{
43cd72b9
BW		 2564 xtensa_isa isa = xtensa_default_isa;
2565 int n, num_operands;
e0001a05 2566
64b607e6 2567 if (xtensa_opcode_is_call (isa, opcode) != 1)
e0001a05
NC		 2568 return FALSE;
2569
43cd72b9
BW		 2570 num_operands = xtensa_opcode_num_operands (isa, opcode);
2571 for (n = 0; n < num_operands; n++)
2572 {
2573 if (xtensa_operand_is_register (isa, opcode, n) == 0
2574 && xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
2575 return TRUE;
2576 }
2577 return FALSE;
e0001a05
NC		 2578}
2579
2580
43cd72b9
BW		 2581/* Convert from BFD relocation type code to slot and operand number.
2582 Returns non-zero on failure. */
e0001a05 2583
43cd72b9 2584static int
7fa3d080 2585decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt)
e0001a05 2586{
43cd72b9
BW		 2587 if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
2588 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
e0001a05 2589 {
43cd72b9
BW		 2590 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
2591 *is_alt = FALSE;
e0001a05 2592 }
43cd72b9
BW		 2593 else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
2594 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
e0001a05 2595 {
43cd72b9
BW		 2596 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
2597 *is_alt = TRUE;
e0001a05 2598 }
43cd72b9
BW		 2599 else
2600 return -1;
2601
2602 return 0;
e0001a05
NC		 2603}
2604
2605
43cd72b9
BW		 2606/* Convert from slot number to BFD relocation type code for the
2607 standard PC-relative relocations. Return BFD_RELOC_NONE on
2608 failure. */
e0001a05 2609
43cd72b9 2610static bfd_reloc_code_real_type
7fa3d080 2611encode_reloc (int slot)
e0001a05 2612{
43cd72b9
BW		 2613 if (slot < 0 || slot > 14)
2614 return BFD_RELOC_NONE;
2615
2616 return BFD_RELOC_XTENSA_SLOT0_OP + slot;
e0001a05
NC		 2617}
2618
2619
43cd72b9
BW		 2620/* Convert from slot numbers to BFD relocation type code for the
2621 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
e0001a05 2622
43cd72b9 2623static bfd_reloc_code_real_type
7fa3d080 2624encode_alt_reloc (int slot)
e0001a05 2625{
43cd72b9
BW		 2626 if (slot < 0 || slot > 14)
2627 return BFD_RELOC_NONE;
2628
2629 return BFD_RELOC_XTENSA_SLOT0_ALT + slot;
e0001a05
NC		 2630}
2631
2632
2633static void
7fa3d080
BW		 2634xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf,
2635 xtensa_format fmt,
2636 int slot,
2637 xtensa_opcode opcode,
2638 int operand,
2639 uint32 value,
2640 const char *file,
2641 unsigned int line)
e0001a05 2642{
e0001a05
NC		 2643 uint32 valbuf = value;
2644
43cd72b9 2645 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
e0001a05 2646 {
43cd72b9
BW		 2647 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
2648 == 1)
2649 as_bad_where ((char *) file, line,
d7c531cd
BW		 2650 _("operand %d of '%s' has out of range value '%u'"),
2651 operand + 1,
2652 xtensa_opcode_name (xtensa_default_isa, opcode),
2653 value);
43cd72b9
BW		 2654 else
2655 as_bad_where ((char *) file, line,
d7c531cd
BW		 2656 _("operand %d of '%s' has invalid value '%u'"),
2657 operand + 1,
2658 xtensa_opcode_name (xtensa_default_isa, opcode),
2659 value);
43cd72b9 2660 return;
e0001a05
NC		 2661 }
2662
43cd72b9
BW		 2663 xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot,
2664 slotbuf, valbuf);
e0001a05
NC		 2665}
2666
2667
2668static uint32
7fa3d080
BW		 2669xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf,
2670 xtensa_format fmt,
2671 int slot,
2672 xtensa_opcode opcode,
2673 int opnum)
e0001a05 2674{
43cd72b9
BW		 2675 uint32 val = 0;
2676 (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum,
2677 fmt, slot, slotbuf, &val);
2678 (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val);
2679 return val;
e0001a05
NC		 2680}
2681
e0001a05 2682\f
7fa3d080 2683/* Checks for rules from xtensa-relax tables. */
e0001a05 2684
7fa3d080
BW		 2685/* The routine xg_instruction_matches_option_term must return TRUE
2686 when a given option term is true. The meaning of all of the option
2687 terms is given interpretation by this function. This is needed when
2688 an option depends on the state of a directive, but there are no such
2689 options in use right now. */
e0001a05 2690
7fa3d080
BW		 2691static bfd_boolean
2692xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED,
2693 const ReqOrOption *option)
e0001a05 2694{
7fa3d080
BW		 2695 if (strcmp (option->option_name, "realnop") == 0
2696 || strncmp (option->option_name, "IsaUse", 6) == 0)
2697 {
2698 /* These conditions were evaluated statically when building the
2699 relaxation table. There's no need to reevaluate them now. */
2700 return TRUE;
2701 }
2702 else
2703 {
2704 as_fatal (_("internal error: unknown option name '%s'"),
2705 option->option_name);
2706 }
e0001a05
NC		 2707}
2708
2709
7fa3d080
BW		 2710static bfd_boolean
2711xg_instruction_matches_or_options (TInsn *insn,
2712 const ReqOrOptionList *or_option)
e0001a05 2713{
7fa3d080
BW		 2714 const ReqOrOption *option;
2715 /* Must match each of the AND terms. */
2716 for (option = or_option; option != NULL; option = option->next)
e0001a05 2717 {
7fa3d080
BW		 2718 if (xg_instruction_matches_option_term (insn, option))
2719 return TRUE;
e0001a05 2720 }
7fa3d080 2721 return FALSE;
e0001a05
NC		 2722}
2723
2724
7fa3d080
BW		 2725static bfd_boolean
2726xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options)
e0001a05 2727{
7fa3d080
BW		 2728 const ReqOption *req_options;
2729 /* Must match each of the AND terms. */
2730 for (req_options = options;
2731 req_options != NULL;
2732 req_options = req_options->next)
e0001a05 2733 {
7fa3d080
BW		 2734 /* Must match one of the OR clauses. */
2735 if (!xg_instruction_matches_or_options (insn,
2736 req_options->or_option_terms))
2737 return FALSE;
e0001a05 2738 }
7fa3d080 2739 return TRUE;
e0001a05
NC		 2740}
2741
2742
7fa3d080 2743/* Return the transition rule that matches or NULL if none matches. */
e0001a05 2744
7fa3d080
BW		 2745static bfd_boolean
2746xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule)
e0001a05 2747{
7fa3d080 2748 PreconditionList *condition_l;
e0001a05 2749
7fa3d080
BW		 2750 if (rule->opcode != insn->opcode)
2751 return FALSE;
e0001a05 2752
7fa3d080
BW		 2753 for (condition_l = rule->conditions;
2754 condition_l != NULL;
2755 condition_l = condition_l->next)
e0001a05 2756 {
7fa3d080
BW		 2757 expressionS *exp1;
2758 expressionS *exp2;
2759 Precondition *cond = condition_l->precond;
e0001a05 2760
7fa3d080 2761 switch (cond->typ)
e0001a05 2762 {
7fa3d080
BW		 2763 case OP_CONSTANT:
2764 /* The expression must be the constant. */
2765 assert (cond->op_num < insn->ntok);
2766 exp1 = &insn->tok[cond->op_num];
2767 if (expr_is_const (exp1))
2768 {
2769 switch (cond->cmp)
2770 {
2771 case OP_EQUAL:
2772 if (get_expr_const (exp1) != cond->op_data)
2773 return FALSE;
2774 break;
2775 case OP_NOTEQUAL:
2776 if (get_expr_const (exp1) == cond->op_data)
2777 return FALSE;
2778 break;
2779 default:
2780 return FALSE;
2781 }
2782 }
2783 else if (expr_is_register (exp1))
2784 {
2785 switch (cond->cmp)
2786 {
2787 case OP_EQUAL:
2788 if (get_expr_register (exp1) != cond->op_data)
2789 return FALSE;
2790 break;
2791 case OP_NOTEQUAL:
2792 if (get_expr_register (exp1) == cond->op_data)
2793 return FALSE;
2794 break;
2795 default:
2796 return FALSE;
2797 }
2798 }
2799 else
2800 return FALSE;
2801 break;
2802
2803 case OP_OPERAND:
2804 assert (cond->op_num < insn->ntok);
2805 assert (cond->op_data < insn->ntok);
2806 exp1 = &insn->tok[cond->op_num];
2807 exp2 = &insn->tok[cond->op_data];
2808
2809 switch (cond->cmp)
2810 {
2811 case OP_EQUAL:
2812 if (!expr_is_equal (exp1, exp2))
2813 return FALSE;
2814 break;
2815 case OP_NOTEQUAL:
2816 if (expr_is_equal (exp1, exp2))
2817 return FALSE;
2818 break;
2819 }
2820 break;
2821
2822 case OP_LITERAL:
2823 case OP_LABEL:
2824 default:
2825 return FALSE;
2826 }
2827 }
2828 if (!xg_instruction_matches_options (insn, rule->options))
2829 return FALSE;
2830
2831 return TRUE;
2832}
2833
2834
2835static int
2836transition_rule_cmp (const TransitionRule *a, const TransitionRule *b)
2837{
2838 bfd_boolean a_greater = FALSE;
2839 bfd_boolean b_greater = FALSE;
2840
2841 ReqOptionList *l_a = a->options;
2842 ReqOptionList *l_b = b->options;
2843
2844 /* We only care if they both are the same except for
2845 a const16 vs. an l32r. */
2846
2847 while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2848 {
2849 ReqOrOptionList *l_or_a = l_a->or_option_terms;
2850 ReqOrOptionList *l_or_b = l_b->or_option_terms;
2851 while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2852 {
2853 if (l_or_a->is_true != l_or_b->is_true)
2854 return 0;
2855 if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0)
2856 {
2857 /* This is the case we care about. */
2858 if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0
2859 && strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
2860 {
2861 if (prefer_const16)
2862 a_greater = TRUE;
2863 else
2864 b_greater = TRUE;
2865 }
2866 else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
2867 && strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
2868 {
2869 if (prefer_const16)
2870 b_greater = TRUE;
2871 else
2872 a_greater = TRUE;
2873 }
2874 else
2875 return 0;
2876 }
2877 l_or_a = l_or_a->next;
2878 l_or_b = l_or_b->next;
2879 }
2880 if (l_or_a || l_or_b)
2881 return 0;
2882
2883 l_a = l_a->next;
2884 l_b = l_b->next;
2885 }
2886 if (l_a || l_b)
2887 return 0;
2888
2889 /* Incomparable if the substitution was used differently in two cases. */
2890 if (a_greater && b_greater)
2891 return 0;
2892
2893 if (b_greater)
2894 return 1;
2895 if (a_greater)
2896 return -1;
2897
2898 return 0;
2899}
2900
2901
2902static TransitionRule *
2903xg_instruction_match (TInsn *insn)
2904{
2905 TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp);
2906 TransitionList *l;
2907 assert (insn->opcode < table->num_opcodes);
2908
2909 /* Walk through all of the possible transitions. */
2910 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
2911 {
2912 TransitionRule *rule = l->rule;
2913 if (xg_instruction_matches_rule (insn, rule))
2914 return rule;
2915 }
2916 return NULL;
2917}
2918
2919\f
2920/* Various Other Internal Functions. */
2921
2922static bfd_boolean
2923is_unique_insn_expansion (TransitionRule *r)
2924{
2925 if (!r->to_instr || r->to_instr->next != NULL)
2926 return FALSE;
2927 if (r->to_instr->typ != INSTR_INSTR)
2928 return FALSE;
2929 return TRUE;
2930}
2931
2932
84b08ed9
BW		 2933/* Check if there is exactly one relaxation for INSN that converts it to
2934 another instruction of equal or larger size. If so, and if TARG is
2935 non-null, go ahead and generate the relaxed instruction into TARG. If
2936 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2937 instruction, i.e., ignore relaxations that convert to an instruction of
2938 equal size. In some contexts where this function is used, only
c138bc38 2939 a single widening is allowed and the NARROW_ONLY argument is used to
84b08ed9
BW		 2940 exclude cases like ADDI being "widened" to an ADDMI, which may
2941 later be relaxed to an ADDMI/ADDI pair. */
7fa3d080 2942
84b08ed9
BW		 2943bfd_boolean
2944xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only)
7fa3d080
BW		 2945{
2946 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
2947 TransitionList *l;
84b08ed9 2948 TransitionRule *match = 0;
7fa3d080 2949
7fa3d080
BW		 2950 assert (insn->insn_type == ITYPE_INSN);
2951 assert (insn->opcode < table->num_opcodes);
2952
2953 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
2954 {
2955 TransitionRule *rule = l->rule;
2956
2957 if (xg_instruction_matches_rule (insn, rule)
84b08ed9
BW		 2958 && is_unique_insn_expansion (rule)
2959 && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0)
2960 <= xg_get_single_size (rule->to_instr->opcode)))
7fa3d080 2961 {
84b08ed9
BW		 2962 if (match)
2963 return FALSE;
2964 match = rule;
7fa3d080
BW		 2965 }
2966 }
84b08ed9
BW		 2967 if (!match)
2968 return FALSE;
2969
2970 if (targ)
2971 xg_build_to_insn (targ, insn, match->to_instr);
2972 return TRUE;
7fa3d080
BW		 2973}
2974
2975
2976/* Return the maximum number of bytes this opcode can expand to. */
2977
2978static int
2979xg_get_max_insn_widen_size (xtensa_opcode opcode)
2980{
2981 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
2982 TransitionList *l;
2983 int max_size = xg_get_single_size (opcode);
2984
2985 assert (opcode < table->num_opcodes);
2986
2987 for (l = table->table[opcode]; l != NULL; l = l->next)
2988 {
2989 TransitionRule *rule = l->rule;
2990 BuildInstr *build_list;
2991 int this_size = 0;
2992
2993 if (!rule)
2994 continue;
2995 build_list = rule->to_instr;
2996 if (is_unique_insn_expansion (rule))
2997 {
2998 assert (build_list->typ == INSTR_INSTR);
2999 this_size = xg_get_max_insn_widen_size (build_list->opcode);
3000 }
3001 else
3002 for (; build_list != NULL; build_list = build_list->next)
3003 {
3004 switch (build_list->typ)
3005 {
3006 case INSTR_INSTR:
3007 this_size += xg_get_single_size (build_list->opcode);
3008 break;
3009 case INSTR_LITERAL_DEF:
3010 case INSTR_LABEL_DEF:
e0001a05
NC		 3011 default:
3012 break;
3013 }
3014 }
3015 if (this_size > max_size)
3016 max_size = this_size;
3017 }
3018 return max_size;
3019}
3020
3021
3022/* Return the maximum number of literal bytes this opcode can generate. */
3023
7fa3d080
BW		 3024static int
3025xg_get_max_insn_widen_literal_size (xtensa_opcode opcode)
e0001a05 3026{
43cd72b9 3027 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3028 TransitionList *l;
3029 int max_size = 0;
3030
3031 assert (opcode < table->num_opcodes);
3032
3033 for (l = table->table[opcode]; l != NULL; l = l->next)
3034 {
3035 TransitionRule *rule = l->rule;
3036 BuildInstr *build_list;
3037 int this_size = 0;
3038
3039 if (!rule)
3040 continue;
3041 build_list = rule->to_instr;
3042 if (is_unique_insn_expansion (rule))
3043 {
3044 assert (build_list->typ == INSTR_INSTR);
3045 this_size = xg_get_max_insn_widen_literal_size (build_list->opcode);
3046 }
3047 else
3048 for (; build_list != NULL; build_list = build_list->next)
3049 {
3050 switch (build_list->typ)
3051 {
3052 case INSTR_LITERAL_DEF:
43cd72b9 3053 /* Hard-coded 4-byte literal. */
e0001a05
NC		 3054 this_size += 4;
3055 break;
3056 case INSTR_INSTR:
3057 case INSTR_LABEL_DEF:
3058 default:
3059 break;
3060 }
3061 }
3062 if (this_size > max_size)
3063 max_size = this_size;
3064 }
3065 return max_size;
3066}
3067
3068
7fa3d080
BW		 3069static bfd_boolean
3070xg_is_relaxable_insn (TInsn *insn, int lateral_steps)
3071{
3072 int steps_taken = 0;
3073 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3074 TransitionList *l;
3075
3076 assert (insn->insn_type == ITYPE_INSN);
3077 assert (insn->opcode < table->num_opcodes);
3078
3079 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3080 {
3081 TransitionRule *rule = l->rule;
3082
3083 if (xg_instruction_matches_rule (insn, rule))
3084 {
3085 if (steps_taken == lateral_steps)
3086 return TRUE;
3087 steps_taken++;
3088 }
3089 }
3090 return FALSE;
3091}
3092
3093
3094static symbolS *
3095get_special_literal_symbol (void)
3096{
3097 static symbolS *sym = NULL;
3098
3099 if (sym == NULL)
3100 sym = symbol_find_or_make ("SPECIAL_LITERAL0\001");
3101 return sym;
3102}
3103
3104
3105static symbolS *
3106get_special_label_symbol (void)
3107{
3108 static symbolS *sym = NULL;
3109
3110 if (sym == NULL)
3111 sym = symbol_find_or_make ("SPECIAL_LABEL0\001");
3112 return sym;
3113}
3114
3115
3116static bfd_boolean
3117xg_valid_literal_expression (const expressionS *exp)
3118{
3119 switch (exp->X_op)
3120 {
3121 case O_constant:
3122 case O_symbol:
3123 case O_big:
3124 case O_uminus:
3125 case O_subtract:
3126 case O_pltrel:
3127 return TRUE;
3128 default:
3129 return FALSE;
3130 }
3131}
3132
3133
3134/* This will check to see if the value can be converted into the
3135 operand type. It will return TRUE if it does not fit. */
3136
3137static bfd_boolean
3138xg_check_operand (int32 value, xtensa_opcode opcode, int operand)
3139{
3140 uint32 valbuf = value;
3141 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
3142 return TRUE;
3143 return FALSE;
3144}
3145
3146
3147/* Assumes: All immeds are constants. Check that all constants fit
3148 into their immeds; return FALSE if not. */
3149
3150static bfd_boolean
3151xg_immeds_fit (const TInsn *insn)
3152{
3153 xtensa_isa isa = xtensa_default_isa;
3154 int i;
3155
3156 int n = insn->ntok;
3157 assert (insn->insn_type == ITYPE_INSN);
3158 for (i = 0; i < n; ++i)
3159 {
3160 const expressionS *expr = &insn->tok[i];
3161 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3162 continue;
3163
3164 switch (expr->X_op)
3165 {
3166 case O_register:
3167 case O_constant:
3168 if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3169 return FALSE;
3170 break;
3171
3172 default:
3173 /* The symbol should have a fixup associated with it. */
3174 assert (FALSE);
3175 break;
3176 }
3177 }
3178 return TRUE;
3179}
3180
3181
3182/* This should only be called after we have an initial
3183 estimate of the addresses. */
3184
3185static bfd_boolean
3186xg_symbolic_immeds_fit (const TInsn *insn,
3187 segT pc_seg,
3188 fragS *pc_frag,
3189 offsetT pc_offset,
3190 long stretch)
e0001a05 3191{
7fa3d080
BW		 3192 xtensa_isa isa = xtensa_default_isa;
3193 symbolS *symbolP;
3194 fragS *sym_frag;
3195 offsetT target, pc;
3196 uint32 new_offset;
3197 int i;
3198 int n = insn->ntok;
e0001a05
NC		 3199
3200 assert (insn->insn_type == ITYPE_INSN);
e0001a05 3201
7fa3d080 3202 for (i = 0; i < n; ++i)
e0001a05 3203 {
7fa3d080
BW		 3204 const expressionS *expr = &insn->tok[i];
3205 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3206 continue;
e0001a05 3207
7fa3d080 3208 switch (expr->X_op)
e0001a05 3209 {
7fa3d080
BW		 3210 case O_register:
3211 case O_constant:
3212 if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3213 return FALSE;
3214 break;
e0001a05 3215
7fa3d080
BW		 3216 case O_lo16:
3217 case O_hi16:
3218 /* Check for the worst case. */
3219 if (xg_check_operand (0xffff, insn->opcode, i))
3220 return FALSE;
3221 break;
e0001a05 3222
7fa3d080 3223 case O_symbol:
7c834684 3224 /* We only allow symbols for PC-relative references.
7fa3d080 3225 If pc_frag == 0, then we don't have frag locations yet. */
7c834684
BW		 3226 if (pc_frag == 0
3227 || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0)
7fa3d080 3228 return FALSE;
e0001a05 3229
7c834684
BW		 3230 /* If it is a weak symbol, then assume it won't reach. */
3231 if (S_IS_WEAK (expr->X_add_symbol))
7fa3d080 3232 return FALSE;
e0001a05 3233
7c834684
BW		 3234 if (is_direct_call_opcode (insn->opcode)
3235 && ! pc_frag->tc_frag_data.use_longcalls)
3236 {
3237 /* If callee is undefined or in a different segment, be
3238 optimistic and assume it will be in range. */
3239 if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg)
3240 return TRUE;
3241 }
3242
3243 /* Only references within a segment can be known to fit in the
3244 operands at assembly time. */
3245 if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg)
7fa3d080 3246 return FALSE;
e0001a05 3247
7fa3d080
BW		 3248 symbolP = expr->X_add_symbol;
3249 sym_frag = symbol_get_frag (symbolP);
3250 target = S_GET_VALUE (symbolP) + expr->X_add_number;
3251 pc = pc_frag->fr_address + pc_offset;
e0001a05 3252
7fa3d080
BW		 3253 /* If frag has yet to be reached on this pass, assume it
3254 will move by STRETCH just as we did. If this is not so,
3255 it will be because some frag between grows, and that will
3256 force another pass. Beware zero-length frags. There
3257 should be a faster way to do this. */
3258
3259 if (stretch != 0
3260 && sym_frag->relax_marker != pc_frag->relax_marker
3261 && S_GET_SEGMENT (symbolP) == pc_seg)
3262 {
3263 target += stretch;
3264 }
c138bc38 3265
7fa3d080
BW		 3266 new_offset = target;
3267 xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
3268 if (xg_check_operand (new_offset, insn->opcode, i))
3269 return FALSE;
3270 break;
3271
3272 default:
3273 /* The symbol should have a fixup associated with it. */
3274 return FALSE;
3275 }
3276 }
3277
3278 return TRUE;
e0001a05
NC		 3279}
3280
3281
43cd72b9 3282/* Return TRUE on success. */
e0001a05 3283
7fa3d080
BW		 3284static bfd_boolean
3285xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
e0001a05
NC		 3286{
3287 BuildOp *op;
3288 symbolS *sym;
3289
60242db2 3290 tinsn_init (targ);
7c430684 3291 targ->linenum = insn->linenum;
e0001a05
NC		 3292 switch (bi->typ)
3293 {
3294 case INSTR_INSTR:
3295 op = bi->ops;
3296 targ->opcode = bi->opcode;
3297 targ->insn_type = ITYPE_INSN;
3298 targ->is_specific_opcode = FALSE;
3299
3300 for (; op != NULL; op = op->next)
3301 {
3302 int op_num = op->op_num;
3303 int op_data = op->op_data;
3304
3305 assert (op->op_num < MAX_INSN_ARGS);
3306
3307 if (targ->ntok <= op_num)
3308 targ->ntok = op_num + 1;
3309
3310 switch (op->typ)
3311 {
3312 case OP_CONSTANT:
3313 set_expr_const (&targ->tok[op_num], op_data);
3314 break;
3315 case OP_OPERAND:
3316 assert (op_data < insn->ntok);
3317 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3318 break;
3319 case OP_LITERAL:
3320 sym = get_special_literal_symbol ();
3321 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3322 break;
3323 case OP_LABEL:
3324 sym = get_special_label_symbol ();
3325 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3326 break;
43cd72b9
BW		 3327 case OP_OPERAND_HI16U:
3328 case OP_OPERAND_LOW16U:
3329 assert (op_data < insn->ntok);
3330 if (expr_is_const (&insn->tok[op_data]))
3331 {
3332 long val;
3333 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3334 val = xg_apply_userdef_op_fn (op->typ,
3335 targ->tok[op_num].
3336 X_add_number);
3337 targ->tok[op_num].X_add_number = val;
3338 }
3339 else
3340 {
3341 /* For const16 we can create relocations for these. */
3342 if (targ->opcode == XTENSA_UNDEFINED
3343 || (targ->opcode != xtensa_const16_opcode))
3344 return FALSE;
3345 assert (op_data < insn->ntok);
3346 /* Need to build a O_lo16 or O_hi16. */
3347 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3348 if (targ->tok[op_num].X_op == O_symbol)
3349 {
3350 if (op->typ == OP_OPERAND_HI16U)
3351 targ->tok[op_num].X_op = O_hi16;
3352 else if (op->typ == OP_OPERAND_LOW16U)
3353 targ->tok[op_num].X_op = O_lo16;
3354 else
3355 return FALSE;
3356 }
3357 }
3358 break;
e0001a05
NC		 3359 default:
3360 /* currently handles:
3361 OP_OPERAND_LOW8
3362 OP_OPERAND_HI24S
3363 OP_OPERAND_F32MINUS */
3364 if (xg_has_userdef_op_fn (op->typ))
3365 {
3366 assert (op_data < insn->ntok);
3367 if (expr_is_const (&insn->tok[op_data]))
3368 {
3369 long val;
3370 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3371 val = xg_apply_userdef_op_fn (op->typ,
3372 targ->tok[op_num].
3373 X_add_number);
3374 targ->tok[op_num].X_add_number = val;
3375 }
3376 else
3377 return FALSE; /* We cannot use a relocation for this. */
3378 break;
3379 }
3380 assert (0);
3381 break;
3382 }
3383 }
3384 break;
3385
3386 case INSTR_LITERAL_DEF:
3387 op = bi->ops;
3388 targ->opcode = XTENSA_UNDEFINED;
3389 targ->insn_type = ITYPE_LITERAL;
3390 targ->is_specific_opcode = FALSE;
3391 for (; op != NULL; op = op->next)
3392 {
3393 int op_num = op->op_num;
3394 int op_data = op->op_data;
3395 assert (op->op_num < MAX_INSN_ARGS);
3396
3397 if (targ->ntok <= op_num)
3398 targ->ntok = op_num + 1;
3399
3400 switch (op->typ)
3401 {
3402 case OP_OPERAND:
3403 assert (op_data < insn->ntok);
43cd72b9
BW		 3404 /* We can only pass resolvable literals through. */
3405 if (!xg_valid_literal_expression (&insn->tok[op_data]))
3406 return FALSE;
e0001a05
NC		 3407 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3408 break;
3409 case OP_LITERAL:
3410 case OP_CONSTANT:
3411 case OP_LABEL:
3412 default:
3413 assert (0);
3414 break;
3415 }
3416 }
3417 break;
3418
3419 case INSTR_LABEL_DEF:
3420 op = bi->ops;
3421 targ->opcode = XTENSA_UNDEFINED;
3422 targ->insn_type = ITYPE_LABEL;
3423 targ->is_specific_opcode = FALSE;
43cd72b9 3424 /* Literal with no ops is a label? */
e0001a05
NC		 3425 assert (op == NULL);
3426 break;
3427
3428 default:
3429 assert (0);
3430 }
3431
3432 return TRUE;
3433}
3434
3435
43cd72b9 3436/* Return TRUE on success. */
e0001a05 3437
7fa3d080
BW		 3438static bfd_boolean
3439xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi)
e0001a05
NC		 3440{
3441 for (; bi != NULL; bi = bi->next)
3442 {
3443 TInsn *next_insn = istack_push_space (istack);
3444
3445 if (!xg_build_to_insn (next_insn, insn, bi))
3446 return FALSE;
3447 }
3448 return TRUE;
3449}
3450
3451
43cd72b9 3452/* Return TRUE on valid expansion. */
e0001a05 3453
7fa3d080
BW		 3454static bfd_boolean
3455xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
e0001a05
NC		 3456{
3457 int stack_size = istack->ninsn;
3458 int steps_taken = 0;
43cd72b9 3459 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
e0001a05
NC		 3460 TransitionList *l;
3461
3462 assert (insn->insn_type == ITYPE_INSN);
3463 assert (insn->opcode < table->num_opcodes);
3464
3465 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3466 {
3467 TransitionRule *rule = l->rule;
3468
3469 if (xg_instruction_matches_rule (insn, rule))
3470 {
3471 if (lateral_steps == steps_taken)
3472 {
3473 int i;
3474
3475 /* This is it. Expand the rule to the stack. */
3476 if (!xg_build_to_stack (istack, insn, rule->to_instr))
3477 return FALSE;
3478
3479 /* Check to see if it fits. */
3480 for (i = stack_size; i < istack->ninsn; i++)
3481 {
3482 TInsn *insn = &istack->insn[i];
3483
3484 if (insn->insn_type == ITYPE_INSN
3485 && !tinsn_has_symbolic_operands (insn)
3486 && !xg_immeds_fit (insn))
3487 {
3488 istack->ninsn = stack_size;
3489 return FALSE;
3490 }
3491 }
3492 return TRUE;
3493 }
3494 steps_taken++;
3495 }
3496 }
3497 return FALSE;
3498}
3499
43cd72b9 3500\f
43cd72b9 3501/* Relax the assembly instruction at least "min_steps".
b81bf389
BW		 3502 Return the number of steps taken.
3503
3504 For relaxation to correctly terminate, every relaxation chain must
3505 terminate in one of two ways:
3506
3507 1. If the chain from one instruction to the next consists entirely of
3508 single instructions, then the chain *must* handle all possible
3509 immediates without failing. It must not ever fail because an
3510 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3511 chain is one example. L32R loads 32 bits, and there cannot be an
3512 immediate larger than 32 bits, so it satisfies this condition.
3513 Single instruction relaxation chains are as defined by
3514 xg_is_single_relaxable_instruction.
3515
3516 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3517 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3518
3519 Strictly speaking, in most cases you can violate condition 1 and be OK
3520 -- in particular when the last two instructions have the same single
3521 size. But nevertheless, you should guarantee the above two conditions.
3522
3523 We could fix this so that single-instruction expansions correctly
3524 terminate when they can't handle the range, but the error messages are
3525 worse, and it actually turns out that in every case but one (18-bit wide
3526 branches), you need a multi-instruction expansion to get the full range
3527 anyway. And because 18-bit branches are handled identically to 15-bit
3528 branches, there isn't any point in changing it. */
e0001a05 3529
7fa3d080
BW		 3530static int
3531xg_assembly_relax (IStack *istack,
3532 TInsn *insn,
3533 segT pc_seg,
3534 fragS *pc_frag, /* if pc_frag == 0, not pc-relative */
3535 offsetT pc_offset, /* offset in fragment */
3536 int min_steps, /* minimum conversion steps */
3537 long stretch) /* number of bytes stretched so far */
e0001a05
NC		 3538{
3539 int steps_taken = 0;
3540
b81bf389
BW		 3541 /* Some of its immeds don't fit. Try to build a relaxed version.
3542 This may go through a couple of stages of single instruction
3543 transformations before we get there. */
e0001a05
NC		 3544
3545 TInsn single_target;
3546 TInsn current_insn;
3547 int lateral_steps = 0;
3548 int istack_size = istack->ninsn;
3549
3550 if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
3551 && steps_taken >= min_steps)
3552 {
3553 istack_push (istack, insn);
3554 return steps_taken;
3555 }
43cd72b9 3556 current_insn = *insn;
e0001a05 3557
7c834684 3558 /* Walk through all of the single instruction expansions. */
84b08ed9 3559 while (xg_is_single_relaxable_insn (&current_insn, &single_target, FALSE))
e0001a05 3560 {
21af2bbd 3561 steps_taken++;
e0001a05
NC		 3562 if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
3563 stretch))
3564 {
e0001a05
NC		 3565 if (steps_taken >= min_steps)
3566 {
3567 istack_push (istack, &single_target);
3568 return steps_taken;
3569 }
3570 }
43cd72b9 3571 current_insn = single_target;
e0001a05
NC		 3572 }
3573
3574 /* Now check for a multi-instruction expansion. */
3575 while (xg_is_relaxable_insn (&current_insn, lateral_steps))
3576 {
3577 if (xg_symbolic_immeds_fit (&current_insn, pc_seg, pc_frag, pc_offset,
3578 stretch))
3579 {
3580 if (steps_taken >= min_steps)
3581 {
3582 istack_push (istack, &current_insn);
3583 return steps_taken;
3584 }
3585 }
3586 steps_taken++;
3587 if (xg_expand_to_stack (istack, &current_insn, lateral_steps))
3588 {
3589 if (steps_taken >= min_steps)
3590 return steps_taken;
3591 }
3592 lateral_steps++;
3593 istack->ninsn = istack_size;
3594 }
3595
3596 /* It's not going to work -- use the original. */
3597 istack_push (istack, insn);
3598 return steps_taken;
3599}
3600
3601
3602static void
7fa3d080 3603xg_force_frag_space (int size)
e0001a05
NC		 3604{
3605 /* This may have the side effect of creating a new fragment for the
3606 space to go into. I just do not like the name of the "frag"
3607 functions. */
3608 frag_grow (size);
3609}
3610
3611
7fa3d080
BW		 3612static void
3613xg_finish_frag (char *last_insn,
3614 enum xtensa_relax_statesE frag_state,
3615 enum xtensa_relax_statesE slot0_state,
3616 int max_growth,
3617 bfd_boolean is_insn)
e0001a05
NC		 3618{
3619 /* Finish off this fragment so that it has at LEAST the desired
3620 max_growth. If it doesn't fit in this fragment, close this one
3621 and start a new one. In either case, return a pointer to the
3622 beginning of the growth area. */
3623
3624 fragS *old_frag;
43cd72b9 3625
e0001a05
NC		 3626 xg_force_frag_space (max_growth);
3627
3628 old_frag = frag_now;
3629
3630 frag_now->fr_opcode = last_insn;
3631 if (is_insn)
3632 frag_now->tc_frag_data.is_insn = TRUE;
3633
3634 frag_var (rs_machine_dependent, max_growth, max_growth,
43cd72b9
BW		 3635 frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
3636
3637 old_frag->tc_frag_data.slot_subtypes[0] = slot0_state;
3638 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 3639
3640 /* Just to make sure that we did not split it up. */
3641 assert (old_frag->fr_next == frag_now);
3642}
3643
3644
7fa3d080
BW		 3645/* Return TRUE if the target frag is one of the next non-empty frags. */
3646
3647static bfd_boolean
3648is_next_frag_target (const fragS *fragP, const fragS *target)
3649{
3650 if (fragP == NULL)
3651 return FALSE;
3652
3653 for (; fragP; fragP = fragP->fr_next)
3654 {
3655 if (fragP == target)
3656 return TRUE;
3657 if (fragP->fr_fix != 0)
3658 return FALSE;
3659 if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
3660 return FALSE;
3661 if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
3662 && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
3663 return FALSE;
3664 if (fragP->fr_type == rs_space)
3665 return FALSE;
3666 }
3667 return FALSE;
3668}
3669
3670
e0001a05 3671static bfd_boolean
7fa3d080 3672is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
e0001a05
NC		 3673{
3674 xtensa_isa isa = xtensa_default_isa;
3675 int i;
43cd72b9 3676 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
e0001a05
NC		 3677 int target_op = -1;
3678 symbolS *sym;
3679 fragS *target_frag;
3680
64b607e6
BW		 3681 if (xtensa_opcode_is_branch (isa, insn->opcode) != 1
3682 && xtensa_opcode_is_jump (isa, insn->opcode) != 1)
e0001a05
NC		 3683 return FALSE;
3684
3685 for (i = 0; i < num_ops; i++)
3686 {
43cd72b9 3687 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1)
e0001a05
NC		 3688 {
3689 target_op = i;
3690 break;
3691 }
3692 }
3693 if (target_op == -1)
3694 return FALSE;
3695
3696 if (insn->ntok <= target_op)
3697 return FALSE;
3698
3699 if (insn->tok[target_op].X_op != O_symbol)
3700 return FALSE;
3701
3702 sym = insn->tok[target_op].X_add_symbol;
3703 if (sym == NULL)
3704 return FALSE;
3705
3706 if (insn->tok[target_op].X_add_number != 0)
3707 return FALSE;
3708
3709 target_frag = symbol_get_frag (sym);
3710 if (target_frag == NULL)
3711 return FALSE;
3712
c138bc38 3713 if (is_next_frag_target (fragP->fr_next, target_frag)
e0001a05
NC		 3714 && S_GET_VALUE (sym) == target_frag->fr_address)
3715 return TRUE;
3716
3717 return FALSE;
3718}
3719
3720
3721static void
7fa3d080 3722xg_add_branch_and_loop_targets (TInsn *insn)
e0001a05
NC		 3723{
3724 xtensa_isa isa = xtensa_default_isa;
7fa3d080 3725 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
43cd72b9 3726
7fa3d080
BW		 3727 if (xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3728 {
3729 int i = 1;
3730 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3731 && insn->tok[i].X_op == O_symbol)
3732 symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
3733 return;
3734 }
e0001a05 3735
7fa3d080
BW		 3736 if (xtensa_opcode_is_branch (isa, insn->opcode) == 1
3737 || xtensa_opcode_is_loop (isa, insn->opcode) == 1)
e0001a05 3738 {
7fa3d080
BW		 3739 int i;
3740
3741 for (i = 0; i < insn->ntok && i < num_ops; i++)
3742 {
3743 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3744 && insn->tok[i].X_op == O_symbol)
3745 {
3746 symbolS *sym = insn->tok[i].X_add_symbol;
3747 symbol_get_tc (sym)->is_branch_target = TRUE;
3748 if (S_IS_DEFINED (sym))
3749 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
3750 }
3751 }
e0001a05 3752 }
e0001a05
NC		 3753}
3754
3755
43cd72b9 3756/* Return FALSE if no error. */
e0001a05 3757
7fa3d080
BW		 3758static bfd_boolean
3759xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn)
e0001a05
NC		 3760{
3761 int num_ops = 0;
3762 BuildOp *b_op;
3763
3764 switch (instr_spec->typ)
3765 {
3766 case INSTR_INSTR:
3767 new_insn->insn_type = ITYPE_INSN;
3768 new_insn->opcode = instr_spec->opcode;
3769 new_insn->is_specific_opcode = FALSE;
7c430684 3770 new_insn->linenum = old_insn->linenum;
e0001a05
NC		 3771 break;
3772 case INSTR_LITERAL_DEF:
3773 new_insn->insn_type = ITYPE_LITERAL;
3774 new_insn->opcode = XTENSA_UNDEFINED;
3775 new_insn->is_specific_opcode = FALSE;
7c430684 3776 new_insn->linenum = old_insn->linenum;
e0001a05
NC		 3777 break;
3778 case INSTR_LABEL_DEF:
3779 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3780 break;
3781 }
3782
3783 for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next)
3784 {
3785 expressionS *exp;
3786 const expressionS *src_exp;
3787
3788 num_ops++;
3789 switch (b_op->typ)
3790 {
3791 case OP_CONSTANT:
3792 /* The expression must be the constant. */
3793 assert (b_op->op_num < MAX_INSN_ARGS);
3794 exp = &new_insn->tok[b_op->op_num];
3795 set_expr_const (exp, b_op->op_data);
3796 break;
3797
3798 case OP_OPERAND:
3799 assert (b_op->op_num < MAX_INSN_ARGS);
3800 assert (b_op->op_data < (unsigned) old_insn->ntok);
3801 src_exp = &old_insn->tok[b_op->op_data];
3802 exp = &new_insn->tok[b_op->op_num];
3803 copy_expr (exp, src_exp);
3804 break;
3805
3806 case OP_LITERAL:
3807 case OP_LABEL:
3808 as_bad (_("can't handle generation of literal/labels yet"));
3809 assert (0);
3810
3811 default:
3812 as_bad (_("can't handle undefined OP TYPE"));
3813 assert (0);
3814 }
3815 }
3816
3817 new_insn->ntok = num_ops;
3818 return FALSE;
3819}
3820
3821
43cd72b9 3822/* Return TRUE if it was simplified. */
e0001a05 3823
7fa3d080
BW		 3824static bfd_boolean
3825xg_simplify_insn (TInsn *old_insn, TInsn *new_insn)
e0001a05 3826{
43cd72b9 3827 TransitionRule *rule;
e0001a05 3828 BuildInstr *insn_spec;
43cd72b9
BW		 3829
3830 if (old_insn->is_specific_opcode || !density_supported)
3831 return FALSE;
3832
3833 rule = xg_instruction_match (old_insn);
e0001a05
NC		 3834 if (rule == NULL)
3835 return FALSE;
3836
3837 insn_spec = rule->to_instr;
3838 /* There should only be one. */
3839 assert (insn_spec != NULL);
3840 assert (insn_spec->next == NULL);
3841 if (insn_spec->next != NULL)
3842 return FALSE;
3843
3844 xg_build_token_insn (insn_spec, old_insn, new_insn);
3845
3846 return TRUE;
3847}
3848
3849
3850/* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3851 l32i.n. (2) Check the number of operands. (3) Place the instruction
7c834684
BW		 3852 tokens into the stack or relax it and place multiple
3853 instructions/literals onto the stack. Return FALSE if no error. */
e0001a05
NC		 3854
3855static bfd_boolean
7fa3d080 3856xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
e0001a05
NC		 3857{
3858 int noperands;
3859 TInsn new_insn;
7c834684
BW		 3860 bfd_boolean do_expand;
3861
60242db2 3862 tinsn_init (&new_insn);
e0001a05 3863
43cd72b9
BW		 3864 /* Narrow it if we can. xg_simplify_insn now does all the
3865 appropriate checking (e.g., for the density option). */
3866 if (xg_simplify_insn (orig_insn, &new_insn))
3867 orig_insn = &new_insn;
e0001a05 3868
43cd72b9
BW		 3869 noperands = xtensa_opcode_num_operands (xtensa_default_isa,
3870 orig_insn->opcode);
e0001a05
NC		 3871 if (orig_insn->ntok < noperands)
3872 {
3873 as_bad (_("found %d operands for '%s': Expected %d"),
3874 orig_insn->ntok,
3875 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
3876 noperands);
3877 return TRUE;
3878 }
3879 if (orig_insn->ntok > noperands)
3880 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3881 orig_insn->ntok,
3882 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
3883 noperands);
3884
43cd72b9 3885 /* If there are not enough operands, we will assert above. If there
e0001a05 3886 are too many, just cut out the extras here. */
e0001a05
NC		 3887 orig_insn->ntok = noperands;
3888
e0001a05
NC		 3889 if (tinsn_has_invalid_symbolic_operands (orig_insn))
3890 return TRUE;
3891
d12f9798
BW		 3892 /* Special case for extui opcode which has constraints not handled
3893 by the ordinary operand encoding checks. The number of operands
3894 and related syntax issues have already been checked. */
3895 if (orig_insn->opcode == xtensa_extui_opcode)
3896 {
3897 int shiftimm = orig_insn->tok[2].X_add_number;
3898 int maskimm = orig_insn->tok[3].X_add_number;
3899 if (shiftimm + maskimm > 32)
3900 {
3901 as_bad (_("immediate operands sum to greater than 32"));
3902 return TRUE;
3903 }
3904 }
3905
7c834684
BW		 3906 /* If the instruction will definitely need to be relaxed, it is better
3907 to expand it now for better scheduling. Decide whether to expand
3908 now.... */
3909 do_expand = (!orig_insn->is_specific_opcode && use_transform ());
3910
3911 /* Calls should be expanded to longcalls only in the backend relaxation
3912 so that the assembly scheduler will keep the L32R/CALLX instructions
3913 adjacent. */
3914 if (is_direct_call_opcode (orig_insn->opcode))
3915 do_expand = FALSE;
e0001a05
NC		 3916
3917 if (tinsn_has_symbolic_operands (orig_insn))
3918 {
7c834684
BW		 3919 /* The values of symbolic operands are not known yet, so only expand
3920 now if an operand is "complex" (e.g., difference of symbols) and
3921 will have to be stored as a literal regardless of the value. */
3922 if (!tinsn_has_complex_operands (orig_insn))
3923 do_expand = FALSE;
e0001a05 3924 }
7c834684
BW		 3925 else if (xg_immeds_fit (orig_insn))
3926 do_expand = FALSE;
3927
3928 if (do_expand)
3929 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
e0001a05 3930 else
7c834684 3931 istack_push (istack, orig_insn);
e0001a05 3932
e0001a05
NC		 3933 return FALSE;
3934}
3935
3936
7fa3d080 3937/* Return TRUE if the section flags are marked linkonce
74869ac7
BW		 3938 or the name is .gnu.linkonce.*. */
3939
3940static int linkonce_len = sizeof (".gnu.linkonce.") - 1;
7fa3d080
BW		 3941
3942static bfd_boolean
3943get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
3944{
3945 flagword flags, link_once_flags;
3946
3947 flags = bfd_get_section_flags (abfd, sec);
3948 link_once_flags = (flags & SEC_LINK_ONCE);
3949
3950 /* Flags might not be set yet. */
74869ac7
BW		 3951 if (!link_once_flags
3952 && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0)
3953 link_once_flags = SEC_LINK_ONCE;
7fa3d080 3954
7fa3d080
BW		 3955 return (link_once_flags != 0);
3956}
3957
3958
3959static void
3960xtensa_add_literal_sym (symbolS *sym)
3961{
3962 sym_list *l;
3963
3964 l = (sym_list *) xmalloc (sizeof (sym_list));
3965 l->sym = sym;
3966 l->next = literal_syms;
3967 literal_syms = l;
3968}
3969
3970
3971static symbolS *
3972xtensa_create_literal_symbol (segT sec, fragS *frag)
3973{
3974 static int lit_num = 0;
3975 static char name[256];
3976 symbolS *symbolP;
3977
3978 sprintf (name, ".L_lit_sym%d", lit_num);
3979
3980 /* Create a local symbol. If it is in a linkonce section, we have to
3981 be careful to make sure that if it is used in a relocation that the
3982 symbol will be in the output file. */
3983 if (get_is_linkonce_section (stdoutput, sec))
3984 {
3985 symbolP = symbol_new (name, sec, 0, frag);
3986 S_CLEAR_EXTERNAL (symbolP);
3987 /* symbolP->local = 1; */
3988 }
3989 else
3990 symbolP = symbol_new (name, sec, 0, frag);
3991
3992 xtensa_add_literal_sym (symbolP);
3993
7fa3d080
BW		 3994 lit_num++;
3995 return symbolP;
3996}
3997
3998
e0001a05
NC		 3999/* Currently all literals that are generated here are 32-bit L32R targets. */
4000
7fa3d080
BW		 4001static symbolS *
4002xg_assemble_literal (/* const */ TInsn *insn)
e0001a05
NC		 4003{
4004 emit_state state;
4005 symbolS *lit_sym = NULL;
bbdd25a8
BW		 4006 bfd_reloc_code_real_type reloc;
4007 char *p;
e0001a05
NC		 4008
4009 /* size = 4 for L32R. It could easily be larger when we move to
4010 larger constants. Add a parameter later. */
4011 offsetT litsize = 4;
4012 offsetT litalign = 2; /* 2^2 = 4 */
4013 expressionS saved_loc;
43cd72b9
BW		 4014 expressionS * emit_val;
4015
e0001a05
NC		 4016 set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
4017
4018 assert (insn->insn_type == ITYPE_LITERAL);
77cd6497 4019 assert (insn->ntok == 1); /* must be only one token here */
e0001a05
NC		 4020
4021 xtensa_switch_to_literal_fragment (&state);
4022
43cd72b9
BW		 4023 emit_val = &insn->tok[0];
4024 if (emit_val->X_op == O_big)
4025 {
4026 int size = emit_val->X_add_number * CHARS_PER_LITTLENUM;
4027 if (size > litsize)
4028 {
4029 /* This happens when someone writes a "movi a2, big_number". */
c138bc38 4030 as_bad_where (frag_now->fr_file, frag_now->fr_line,
43cd72b9
BW		 4031 _("invalid immediate"));
4032 xtensa_restore_emit_state (&state);
4033 return NULL;
4034 }
4035 }
4036
e0001a05
NC		 4037 /* Force a 4-byte align here. Note that this opens a new frag, so all
4038 literals done with this function have a frag to themselves. That's
4039 important for the way text section literals work. */
4040 frag_align (litalign, 0, 0);
43cd72b9 4041 record_alignment (now_seg, litalign);
e0001a05 4042
bbdd25a8 4043 switch (emit_val->X_op)
43cd72b9 4044 {
bbdd25a8
BW		 4045 case O_pltrel:
4046 p = frag_more (litsize);
43cd72b9 4047 xtensa_set_frag_assembly_state (frag_now);
bbdd25a8 4048 reloc = map_operator_to_reloc (emit_val->X_op);
43cd72b9
BW		 4049 if (emit_val->X_add_symbol)
4050 emit_val->X_op = O_symbol;
4051 else
4052 emit_val->X_op = O_constant;
4053 fix_new_exp (frag_now, p - frag_now->fr_literal,
bbdd25a8
BW		 4054 litsize, emit_val, 0, reloc);
4055 break;
4056
4057 default:
4058 emit_expr (emit_val, litsize);
4059 break;
43cd72b9 4060 }
e0001a05
NC		 4061
4062 assert (frag_now->tc_frag_data.literal_frag == NULL);
4063 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4064 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4065 lit_sym = frag_now->fr_symbol;
e0001a05
NC		 4066
4067 /* Go back. */
4068 xtensa_restore_emit_state (&state);
4069 return lit_sym;
4070}
4071
4072
4073static void
7fa3d080 4074xg_assemble_literal_space (/* const */ int size, int slot)
e0001a05
NC		 4075{
4076 emit_state state;
43cd72b9 4077 /* We might have to do something about this alignment. It only
e0001a05
NC		 4078 takes effect if something is placed here. */
4079 offsetT litalign = 2; /* 2^2 = 4 */
4080 fragS *lit_saved_frag;
4081
e0001a05 4082 assert (size % 4 == 0);
e0001a05
NC		 4083
4084 xtensa_switch_to_literal_fragment (&state);
4085
4086 /* Force a 4-byte align here. */
4087 frag_align (litalign, 0, 0);
43cd72b9 4088 record_alignment (now_seg, litalign);
e0001a05
NC		 4089
4090 xg_force_frag_space (size);
4091
4092 lit_saved_frag = frag_now;
4093 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
e0001a05 4094 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
43cd72b9 4095 xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE);
e0001a05
NC		 4096
4097 /* Go back. */
4098 xtensa_restore_emit_state (&state);
43cd72b9 4099 frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag;
e0001a05
NC		 4100}
4101
4102
e0001a05 4103/* Put in a fixup record based on the opcode.
43cd72b9 4104 Return TRUE on success. */
e0001a05 4105
7fa3d080
BW		 4106static bfd_boolean
4107xg_add_opcode_fix (TInsn *tinsn,
4108 int opnum,
4109 xtensa_format fmt,
4110 int slot,
4111 expressionS *expr,
4112 fragS *fragP,
4113 offsetT offset)
43cd72b9
BW		 4114{
4115 xtensa_opcode opcode = tinsn->opcode;
4116 bfd_reloc_code_real_type reloc;
4117 reloc_howto_type *howto;
4118 int fmt_length;
e0001a05
NC		 4119 fixS *the_fix;
4120
43cd72b9
BW		 4121 reloc = BFD_RELOC_NONE;
4122
4123 /* First try the special cases for "alternate" relocs. */
4124 if (opcode == xtensa_l32r_opcode)
4125 {
4126 if (fragP->tc_frag_data.use_absolute_literals)
4127 reloc = encode_alt_reloc (slot);
4128 }
4129 else if (opcode == xtensa_const16_opcode)
4130 {
4131 if (expr->X_op == O_lo16)
4132 {
4133 reloc = encode_reloc (slot);
4134 expr->X_op = O_symbol;
4135 }
4136 else if (expr->X_op == O_hi16)
4137 {
4138 reloc = encode_alt_reloc (slot);
4139 expr->X_op = O_symbol;
4140 }
4141 }
4142
4143 if (opnum != get_relaxable_immed (opcode))
e0001a05 4144 {
43cd72b9 4145 as_bad (_("invalid relocation for operand %i of '%s'"),
431ad2d0 4146 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
e0001a05
NC		 4147 return FALSE;
4148 }
4149
43cd72b9
BW		 4150 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4151 into the symbol table where the generic portions of the assembler
4152 won't know what to do with them. */
4153 if (expr->X_op == O_lo16 || expr->X_op == O_hi16)
4154 {
4155 as_bad (_("invalid expression for operand %i of '%s'"),
431ad2d0 4156 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
43cd72b9
BW		 4157 return FALSE;
4158 }
4159
4160 /* Next try the generic relocs. */
4161 if (reloc == BFD_RELOC_NONE)
4162 reloc = encode_reloc (slot);
4163 if (reloc == BFD_RELOC_NONE)
4164 {
4165 as_bad (_("invalid relocation in instruction slot %i"), slot);
4166 return FALSE;
4167 }
e0001a05 4168
43cd72b9 4169 howto = bfd_reloc_type_lookup (stdoutput, reloc);
e0001a05
NC		 4170 if (!howto)
4171 {
43cd72b9 4172 as_bad (_("undefined symbol for opcode \"%s\""),
e0001a05
NC		 4173 xtensa_opcode_name (xtensa_default_isa, opcode));
4174 return FALSE;
4175 }
4176
43cd72b9
BW		 4177 fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
4178 the_fix = fix_new_exp (fragP, offset, fmt_length, expr,
e0001a05 4179 howto->pc_relative, reloc);
d9740523 4180 the_fix->fx_no_overflow = 1;
7fa3d080
BW		 4181 the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol;
4182 the_fix->tc_fix_data.X_add_number = expr->X_add_number;
4183 the_fix->tc_fix_data.slot = slot;
c138bc38 4184
7fa3d080
BW		 4185 return TRUE;
4186}
4187
4188
4189static bfd_boolean
4190xg_emit_insn_to_buf (TInsn *tinsn,
7fa3d080
BW		 4191 char *buf,
4192 fragS *fragP,
4193 offsetT offset,
4194 bfd_boolean build_fix)
4195{
4196 static xtensa_insnbuf insnbuf = NULL;
4197 bfd_boolean has_symbolic_immed = FALSE;
4198 bfd_boolean ok = TRUE;
b2d179be 4199
7fa3d080
BW		 4200 if (!insnbuf)
4201 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4202
4203 has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf);
4204 if (has_symbolic_immed && build_fix)
4205 {
4206 /* Add a fixup. */
b2d179be
BW		 4207 xtensa_format fmt = xg_get_single_format (tinsn->opcode);
4208 int slot = xg_get_single_slot (tinsn->opcode);
7fa3d080
BW		 4209 int opnum = get_relaxable_immed (tinsn->opcode);
4210 expressionS *exp = &tinsn->tok[opnum];
43cd72b9 4211
b2d179be 4212 if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset))
7fa3d080
BW		 4213 ok = FALSE;
4214 }
4215 fragP->tc_frag_data.is_insn = TRUE;
d77b99c9
BW		 4216 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4217 (unsigned char *) buf, 0);
7fa3d080 4218 return ok;
e0001a05
NC		 4219}
4220
4221
7fa3d080
BW		 4222static void
4223xg_resolve_literals (TInsn *insn, symbolS *lit_sym)
e0001a05
NC		 4224{
4225 symbolS *sym = get_special_literal_symbol ();
4226 int i;
4227 if (lit_sym == 0)
4228 return;
4229 assert (insn->insn_type == ITYPE_INSN);
4230 for (i = 0; i < insn->ntok; i++)
4231 if (insn->tok[i].X_add_symbol == sym)
4232 insn->tok[i].X_add_symbol = lit_sym;
4233
4234}
4235
4236
7fa3d080
BW		 4237static void
4238xg_resolve_labels (TInsn *insn, symbolS *label_sym)
e0001a05
NC		 4239{
4240 symbolS *sym = get_special_label_symbol ();
4241 int i;
e0001a05
NC		 4242 for (i = 0; i < insn->ntok; i++)
4243 if (insn->tok[i].X_add_symbol == sym)
4244 insn->tok[i].X_add_symbol = label_sym;
4245
4246}
4247
4248
43cd72b9 4249/* Return TRUE if the instruction can write to the specified
e0001a05
NC		 4250 integer register. */
4251
4252static bfd_boolean
7fa3d080 4253is_register_writer (const TInsn *insn, const char *regset, int regnum)
e0001a05
NC		 4254{
4255 int i;
4256 int num_ops;
4257 xtensa_isa isa = xtensa_default_isa;
4258
43cd72b9 4259 num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
e0001a05
NC		 4260
4261 for (i = 0; i < num_ops; i++)
4262 {
43cd72b9
BW		 4263 char inout;
4264 inout = xtensa_operand_inout (isa, insn->opcode, i);
4265 if ((inout == 'o' || inout == 'm')
4266 && xtensa_operand_is_register (isa, insn->opcode, i) == 1)
e0001a05 4267 {
43cd72b9
BW		 4268 xtensa_regfile opnd_rf =
4269 xtensa_operand_regfile (isa, insn->opcode, i);
4270 if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset))
e0001a05
NC		 4271 {
4272 if ((insn->tok[i].X_op == O_register)
4273 && (insn->tok[i].X_add_number == regnum))
4274 return TRUE;
4275 }
4276 }
4277 }
4278 return FALSE;
4279}
4280
4281
4282static bfd_boolean
7fa3d080 4283is_bad_loopend_opcode (const TInsn *tinsn)
e0001a05
NC		 4284{
4285 xtensa_opcode opcode = tinsn->opcode;
4286
4287 if (opcode == XTENSA_UNDEFINED)
4288 return FALSE;
4289
4290 if (opcode == xtensa_call0_opcode
4291 || opcode == xtensa_callx0_opcode
4292 || opcode == xtensa_call4_opcode
4293 || opcode == xtensa_callx4_opcode
4294 || opcode == xtensa_call8_opcode
4295 || opcode == xtensa_callx8_opcode
4296 || opcode == xtensa_call12_opcode
4297 || opcode == xtensa_callx12_opcode
4298 || opcode == xtensa_isync_opcode
4299 || opcode == xtensa_ret_opcode
4300 || opcode == xtensa_ret_n_opcode
4301 || opcode == xtensa_retw_opcode
4302 || opcode == xtensa_retw_n_opcode
43cd72b9
BW		 4303 || opcode == xtensa_waiti_opcode
4304 || opcode == xtensa_rsr_lcount_opcode)
e0001a05 4305 return TRUE;
c138bc38 4306
e0001a05
NC		 4307 return FALSE;
4308}
4309
4310
4311/* Labels that begin with ".Ln" or ".LM" are unaligned.
4312 This allows the debugger to add unaligned labels.
4313 Also, the assembler generates stabs labels that need
4314 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4315
7fa3d080
BW		 4316static bfd_boolean
4317is_unaligned_label (symbolS *sym)
e0001a05
NC		 4318{
4319 const char *name = S_GET_NAME (sym);
4320 static size_t fake_size = 0;
4321
4322 if (name
4323 && name[0] == '.'
4324 && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M'))
4325 return TRUE;
4326
4327 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4328 if (fake_size == 0)
4329 fake_size = strlen (FAKE_LABEL_NAME);
4330
43cd72b9 4331 if (name
e0001a05
NC		 4332 && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0
4333 && (name[fake_size] == 'F'
4334 || name[fake_size] == 'L'
4335 || (name[fake_size] == 'e'
4336 && strncmp ("endfunc", name+fake_size, 7) == 0)))
4337 return TRUE;
4338
4339 return FALSE;
4340}
4341
4342
7fa3d080
BW		 4343static fragS *
4344next_non_empty_frag (const fragS *fragP)
e0001a05
NC		 4345{
4346 fragS *next_fragP = fragP->fr_next;
4347
c138bc38 4348 /* Sometimes an empty will end up here due storage allocation issues.
e0001a05
NC		 4349 So we have to skip until we find something legit. */
4350 while (next_fragP && next_fragP->fr_fix == 0)
4351 next_fragP = next_fragP->fr_next;
4352
4353 if (next_fragP == NULL || next_fragP->fr_fix == 0)
4354 return NULL;
4355
4356 return next_fragP;
4357}
4358
4359
43cd72b9 4360static bfd_boolean
7fa3d080 4361next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode)
43cd72b9
BW		 4362{
4363 xtensa_opcode out_opcode;
4364 const fragS *next_fragP = next_non_empty_frag (fragP);
4365
4366 if (next_fragP == NULL)
4367 return FALSE;
4368
4369 out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
4370 if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
4371 {
4372 *opcode = out_opcode;
4373 return TRUE;
4374 }
4375 return FALSE;
4376}
4377
4378
4379static int
7fa3d080 4380frag_format_size (const fragS *fragP)
43cd72b9 4381{
e0001a05
NC		 4382 static xtensa_insnbuf insnbuf = NULL;
4383 xtensa_isa isa = xtensa_default_isa;
43cd72b9 4384 xtensa_format fmt;
c138bc38 4385 int fmt_size;
e0001a05
NC		 4386
4387 if (!insnbuf)
4388 insnbuf = xtensa_insnbuf_alloc (isa);
4389
43cd72b9
BW		 4390 if (fragP == NULL)
4391 return XTENSA_UNDEFINED;
4392
d77b99c9
BW		 4393 xtensa_insnbuf_from_chars (isa, insnbuf,
4394 (unsigned char *) fragP->fr_literal, 0);
43cd72b9
BW		 4395
4396 fmt = xtensa_format_decode (isa, insnbuf);
4397 if (fmt == XTENSA_UNDEFINED)
e0001a05 4398 return XTENSA_UNDEFINED;
43cd72b9
BW		 4399 fmt_size = xtensa_format_length (isa, fmt);
4400
4401 /* If the next format won't be changing due to relaxation, just
4402 return the length of the first format. */
4403 if (fragP->fr_opcode != fragP->fr_literal)
4404 return fmt_size;
4405
c138bc38 4406 /* If during relaxation we have to pull an instruction out of a
43cd72b9
BW		 4407 multi-slot instruction, we will return the more conservative
4408 number. This works because alignment on bigger instructions
4409 is more restrictive than alignment on smaller instructions.
4410 This is more conservative than we would like, but it happens
4411 infrequently. */
4412
4413 if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1)
4414 return fmt_size;
4415
4416 /* If we aren't doing one of our own relaxations or it isn't
4417 slot-based, then the insn size won't change. */
4418 if (fragP->fr_type != rs_machine_dependent)
4419 return fmt_size;
4420 if (fragP->fr_subtype != RELAX_SLOTS)
4421 return fmt_size;
4422
4423 /* If an instruction is about to grow, return the longer size. */
4424 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
b81bf389
BW		 4425 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2
4426 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3)
43cd72b9 4427 return 3;
c138bc38 4428
43cd72b9
BW		 4429 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
4430 return 2 + fragP->tc_frag_data.text_expansion[0];
e0001a05 4431
43cd72b9 4432 return fmt_size;
e0001a05
NC		 4433}
4434
4435
7fa3d080
BW		 4436static int
4437next_frag_format_size (const fragS *fragP)
e0001a05 4438{
7fa3d080
BW		 4439 const fragS *next_fragP = next_non_empty_frag (fragP);
4440 return frag_format_size (next_fragP);
e0001a05
NC		 4441}
4442
4443
03aaa593
BW		 4444/* In early Xtensa Processors, for reasons that are unclear, the ISA
4445 required two-byte instructions to be treated as three-byte instructions
4446 for loop instruction alignment. This restriction was removed beginning
4447 with Xtensa LX. Now the only requirement on loop instruction alignment
4448 is that the first instruction of the loop must appear at an address that
4449 does not cross a fetch boundary. */
4450
4451static int
4452get_loop_align_size (int insn_size)
4453{
4454 if (insn_size == XTENSA_UNDEFINED)
4455 return xtensa_fetch_width;
4456
4457 if (enforce_three_byte_loop_align && insn_size == 2)
4458 return 3;
4459
4460 return insn_size;
4461}
4462
4463
e0001a05
NC		 4464/* If the next legit fragment is an end-of-loop marker,
4465 switch its state so it will instantiate a NOP. */
4466
4467static void
1d19a770 4468update_next_frag_state (fragS *fragP)
e0001a05
NC		 4469{
4470 fragS *next_fragP = fragP->fr_next;
43cd72b9 4471 fragS *new_target = NULL;
e0001a05 4472
7b1cc377 4473 if (align_targets)
43cd72b9
BW		 4474 {
4475 /* We are guaranteed there will be one of these... */
4476 while (!(next_fragP->fr_type == rs_machine_dependent
4477 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4478 || next_fragP->fr_subtype == RELAX_UNREACHABLE)))
4479 next_fragP = next_fragP->fr_next;
4480
4481 assert (next_fragP->fr_type == rs_machine_dependent
4482 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4483 || next_fragP->fr_subtype == RELAX_UNREACHABLE));
4484
4485 /* ...and one of these. */
4486 new_target = next_fragP->fr_next;
4487 while (!(new_target->fr_type == rs_machine_dependent
4488 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4489 || new_target->fr_subtype == RELAX_DESIRE_ALIGN)))
4490 new_target = new_target->fr_next;
4491
4492 assert (new_target->fr_type == rs_machine_dependent
4493 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4494 || new_target->fr_subtype == RELAX_DESIRE_ALIGN));
4495 }
43cd72b9 4496
1d19a770 4497 while (next_fragP && next_fragP->fr_fix == 0)
43cd72b9 4498 {
1d19a770
BW		 4499 if (next_fragP->fr_type == rs_machine_dependent
4500 && next_fragP->fr_subtype == RELAX_LOOP_END)
43cd72b9 4501 {
1d19a770
BW		 4502 next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP;
4503 return;
e0001a05 4504 }
1d19a770
BW		 4505
4506 next_fragP = next_fragP->fr_next;
e0001a05
NC		 4507 }
4508}
4509
4510
4511static bfd_boolean
7fa3d080 4512next_frag_is_branch_target (const fragS *fragP)
e0001a05 4513{
43cd72b9 4514 /* Sometimes an empty will end up here due to storage allocation issues,
e0001a05
NC		 4515 so we have to skip until we find something legit. */
4516 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4517 {
4518 if (fragP->tc_frag_data.is_branch_target)
4519 return TRUE;
4520 if (fragP->fr_fix != 0)
4521 break;
4522 }
4523 return FALSE;
4524}
4525
4526
4527static bfd_boolean
7fa3d080 4528next_frag_is_loop_target (const fragS *fragP)
e0001a05 4529{
c138bc38 4530 /* Sometimes an empty will end up here due storage allocation issues.
e0001a05
NC		 4531 So we have to skip until we find something legit. */
4532 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4533 {
4534 if (fragP->tc_frag_data.is_loop_target)
4535 return TRUE;
4536 if (fragP->fr_fix != 0)
4537 break;
4538 }
4539 return FALSE;
4540}
4541
4542
4543static addressT
7fa3d080 4544next_frag_pre_opcode_bytes (const fragS *fragp)
e0001a05
NC		 4545{
4546 const fragS *next_fragp = fragp->fr_next;
43cd72b9 4547 xtensa_opcode next_opcode;
e0001a05 4548
43cd72b9 4549 if (!next_frag_opcode_is_loop (fragp, &next_opcode))
e0001a05
NC		 4550 return 0;
4551
43cd72b9
BW		 4552 /* Sometimes an empty will end up here due to storage allocation issues,
4553 so we have to skip until we find something legit. */
e0001a05
NC		 4554 while (next_fragp->fr_fix == 0)
4555 next_fragp = next_fragp->fr_next;
4556
4557 if (next_fragp->fr_type != rs_machine_dependent)
4558 return 0;
4559
4560 /* There is some implicit knowledge encoded in here.
4561 The LOOP instructions that are NOT RELAX_IMMED have
43cd72b9
BW		 4562 been relaxed. Note that we can assume that the LOOP
4563 instruction is in slot 0 because loops aren't bundleable. */
4564 if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED)
e0001a05
NC		 4565 return get_expanded_loop_offset (next_opcode);
4566
4567 return 0;
4568}
4569
4570
4571/* Mark a location where we can later insert literal frags. Update
4572 the section's literal_pool_loc, so subsequent literals can be
4573 placed nearest to their use. */
4574
4575static void
7fa3d080 4576xtensa_mark_literal_pool_location (void)
e0001a05
NC		 4577{
4578 /* Any labels pointing to the current location need
4579 to be adjusted to after the literal pool. */
4580 emit_state s;
e0001a05 4581 fragS *pool_location;
e0001a05 4582
1f2a7e38 4583 if (use_literal_section)
43cd72b9
BW		 4584 return;
4585
dd49a749
BW		 4586 /* We stash info in these frags so we can later move the literal's
4587 fixes into this frchain's fix list. */
e0001a05 4588 pool_location = frag_now;
dd49a749 4589 frag_now->tc_frag_data.lit_frchain = frchain_now;
c48aaca0 4590 frag_now->tc_frag_data.literal_frag = frag_now;
dd49a749 4591 frag_variant (rs_machine_dependent, 0, 0,
e0001a05 4592 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
43cd72b9 4593 xtensa_set_frag_assembly_state (frag_now);
dd49a749
BW		 4594 frag_now->tc_frag_data.lit_seg = now_seg;
4595 frag_variant (rs_machine_dependent, 0, 0,
e0001a05 4596 RELAX_LITERAL_POOL_END, NULL, 0, NULL);
43cd72b9 4597 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 4598
4599 /* Now put a frag into the literal pool that points to this location. */
4600 set_literal_pool_location (now_seg, pool_location);
43cd72b9
BW		 4601 xtensa_switch_to_non_abs_literal_fragment (&s);
4602 frag_align (2, 0, 0);
4603 record_alignment (now_seg, 2);
e0001a05
NC		 4604
4605 /* Close whatever frag is there. */
4606 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 4607 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 4608 frag_now->tc_frag_data.literal_frag = pool_location;
4609 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4610 xtensa_restore_emit_state (&s);
43cd72b9 4611 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 4612}
4613
4614
43cd72b9
BW		 4615/* Build a nop of the correct size into tinsn. */
4616
4617static void
7fa3d080 4618build_nop (TInsn *tinsn, int size)
43cd72b9
BW		 4619{
4620 tinsn_init (tinsn);
4621 switch (size)
4622 {
4623 case 2:
4624 tinsn->opcode = xtensa_nop_n_opcode;
4625 tinsn->ntok = 0;
4626 if (tinsn->opcode == XTENSA_UNDEFINED)
4627 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4628 break;
4629
4630 case 3:
4631 if (xtensa_nop_opcode == XTENSA_UNDEFINED)
4632 {
4633 tinsn->opcode = xtensa_or_opcode;
4634 set_expr_const (&tinsn->tok[0], 1);
4635 set_expr_const (&tinsn->tok[1], 1);
4636 set_expr_const (&tinsn->tok[2], 1);
4637 tinsn->ntok = 3;
4638 }
4639 else
4640 tinsn->opcode = xtensa_nop_opcode;
4641
4642 assert (tinsn->opcode != XTENSA_UNDEFINED);
4643 }
4644}
4645
4646
e0001a05
NC		 4647/* Assemble a NOP of the requested size in the buffer. User must have
4648 allocated "buf" with at least "size" bytes. */
4649
7fa3d080 4650static void
d77b99c9 4651assemble_nop (int size, char *buf)
e0001a05
NC		 4652{
4653 static xtensa_insnbuf insnbuf = NULL;
43cd72b9 4654 TInsn tinsn;
e0001a05 4655
43cd72b9 4656 build_nop (&tinsn, size);
e0001a05 4657
43cd72b9
BW		 4658 if (!insnbuf)
4659 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
e0001a05 4660
43cd72b9 4661 tinsn_to_insnbuf (&tinsn, insnbuf);
d77b99c9
BW		 4662 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4663 (unsigned char *) buf, 0);
e0001a05
NC		 4664}
4665
4666
4667/* Return the number of bytes for the offset of the expanded loop
4668 instruction. This should be incorporated into the relaxation
4669 specification but is hard-coded here. This is used to auto-align
4670 the loop instruction. It is invalid to call this function if the
4671 configuration does not have loops or if the opcode is not a loop
4672 opcode. */
4673
4674static addressT
7fa3d080 4675get_expanded_loop_offset (xtensa_opcode opcode)
e0001a05
NC		 4676{
4677 /* This is the OFFSET of the loop instruction in the expanded loop.
4678 This MUST correspond directly to the specification of the loop
4679 expansion. It will be validated on fragment conversion. */
43cd72b9 4680 assert (opcode != XTENSA_UNDEFINED);
e0001a05
NC		 4681 if (opcode == xtensa_loop_opcode)
4682 return 0;
4683 if (opcode == xtensa_loopnez_opcode)
4684 return 3;
4685 if (opcode == xtensa_loopgtz_opcode)
4686 return 6;
4687 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4688 return 0;
4689}
4690
4691
7fa3d080
BW		 4692static fragS *
4693get_literal_pool_location (segT seg)
e0001a05
NC		 4694{
4695 return seg_info (seg)->tc_segment_info_data.literal_pool_loc;
4696}
4697
4698
4699static void
7fa3d080 4700set_literal_pool_location (segT seg, fragS *literal_pool_loc)
e0001a05
NC		 4701{
4702 seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc;
4703}
4704
43cd72b9
BW		 4705
4706/* Set frag assembly state should be called when a new frag is
4707 opened and after a frag has been closed. */
4708
7fa3d080
BW		 4709static void
4710xtensa_set_frag_assembly_state (fragS *fragP)
43cd72b9
BW		 4711{
4712 if (!density_supported)
4713 fragP->tc_frag_data.is_no_density = TRUE;
4714
4715 /* This function is called from subsegs_finish, which is called
c138bc38 4716 after xtensa_end, so we can't use "use_transform" or
43cd72b9
BW		 4717 "use_schedule" here. */
4718 if (!directive_state[directive_transform])
4719 fragP->tc_frag_data.is_no_transform = TRUE;
7c834684
BW		 4720 if (directive_state[directive_longcalls])
4721 fragP->tc_frag_data.use_longcalls = TRUE;
43cd72b9
BW		 4722 fragP->tc_frag_data.use_absolute_literals =
4723 directive_state[directive_absolute_literals];
4724 fragP->tc_frag_data.is_assembly_state_set = TRUE;
4725}
4726
4727
7fa3d080
BW		 4728static bfd_boolean
4729relaxable_section (asection *sec)
43cd72b9
BW		 4730{
4731 return (sec->flags & SEC_DEBUGGING) == 0;
4732}
4733
4734
99ded152
BW		 4735static void
4736xtensa_mark_frags_for_org (void)
4737{
4738 segT *seclist;
4739
4740 /* Walk over each fragment of all of the current segments. If we find
4741 a .org frag in any of the segments, mark all frags prior to it as
4742 "no transform", which will prevent linker optimizations from messing
4743 up the .org distance. This should be done after
4744 xtensa_find_unmarked_state_frags, because we don't want to worry here
4745 about that function trashing the data we save here. */
4746
4747 for (seclist = &stdoutput->sections;
4748 seclist && *seclist;
4749 seclist = &(*seclist)->next)
4750 {
4751 segT sec = *seclist;
4752 segment_info_type *seginfo;
4753 fragS *fragP;
4754 flagword flags;
4755 flags = bfd_get_section_flags (stdoutput, sec);
4756 if (flags & SEC_DEBUGGING)
4757 continue;
4758 if (!(flags & SEC_ALLOC))
4759 continue;
4760
4761 seginfo = seg_info (sec);
4762 if (seginfo && seginfo->frchainP)
4763 {
4764 fragS *last_fragP = seginfo->frchainP->frch_root;
4765 for (fragP = seginfo->frchainP->frch_root; fragP;
4766 fragP = fragP->fr_next)
4767 {
4768 /* cvt_frag_to_fill has changed the fr_type of org frags to
4769 rs_fill, so use the value as cached in rs_subtype here. */
4770 if (fragP->fr_subtype == RELAX_ORG)
4771 {
4772 while (last_fragP != fragP->fr_next)
4773 {
4774 last_fragP->tc_frag_data.is_no_transform = TRUE;
4775 last_fragP = last_fragP->fr_next;
4776 }
4777 }
4778 }
4779 }
4780 }
4781}
4782
4783
43cd72b9 4784static void
7fa3d080 4785xtensa_find_unmarked_state_frags (void)
43cd72b9
BW		 4786{
4787 segT *seclist;
4788
4789 /* Walk over each fragment of all of the current segments. For each
4790 unmarked fragment, mark it with the same info as the previous
4791 fragment. */
4792 for (seclist = &stdoutput->sections;
4793 seclist && *seclist;
4794 seclist = &(*seclist)->next)
4795 {
4796 segT sec = *seclist;
4797 segment_info_type *seginfo;
4798 fragS *fragP;
4799 flagword flags;
4800 flags = bfd_get_section_flags (stdoutput, sec);
4801 if (flags & SEC_DEBUGGING)
4802 continue;
4803 if (!(flags & SEC_ALLOC))
4804 continue;
4805
4806 seginfo = seg_info (sec);
4807 if (seginfo && seginfo->frchainP)
4808 {
4809 fragS *last_fragP = 0;
4810 for (fragP = seginfo->frchainP->frch_root; fragP;
4811 fragP = fragP->fr_next)
4812 {
4813 if (fragP->fr_fix != 0
4814 && !fragP->tc_frag_data.is_assembly_state_set)
4815 {
4816 if (last_fragP == 0)
4817 {
4818 as_warn_where (fragP->fr_file, fragP->fr_line,
4819 _("assembly state not set for first frag in section %s"),
4820 sec->name);
4821 }
4822 else
4823 {
4824 fragP->tc_frag_data.is_assembly_state_set = TRUE;
4825 fragP->tc_frag_data.is_no_density =
4826 last_fragP->tc_frag_data.is_no_density;
4827 fragP->tc_frag_data.is_no_transform =
4828 last_fragP->tc_frag_data.is_no_transform;
7c834684
BW		 4829 fragP->tc_frag_data.use_longcalls =
4830 last_fragP->tc_frag_data.use_longcalls;
43cd72b9
BW		 4831 fragP->tc_frag_data.use_absolute_literals =
4832 last_fragP->tc_frag_data.use_absolute_literals;
4833 }
4834 }
4835 if (fragP->tc_frag_data.is_assembly_state_set)
4836 last_fragP = fragP;
4837 }
4838 }
4839 }
4840}
4841
4842
4843static void
7fa3d080
BW		 4844xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED,
4845 asection *sec,
4846 void *unused ATTRIBUTE_UNUSED)
43cd72b9
BW		 4847{
4848 flagword flags = bfd_get_section_flags (abfd, sec);
4849 segment_info_type *seginfo = seg_info (sec);
4850 fragS *frag = seginfo->frchainP->frch_root;
c138bc38 4851
43cd72b9 4852 if (flags & SEC_CODE)
c138bc38 4853 {
43cd72b9
BW		 4854 xtensa_isa isa = xtensa_default_isa;
4855 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
4856 while (frag != NULL)
4857 {
4858 if (frag->tc_frag_data.is_branch_target)
4859 {
4860 int op_size;
664df4e4 4861 addressT branch_align, frag_addr;
43cd72b9
BW		 4862 xtensa_format fmt;
4863
d77b99c9
BW		 4864 xtensa_insnbuf_from_chars
4865 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
43cd72b9
BW		 4866 fmt = xtensa_format_decode (isa, insnbuf);
4867 op_size = xtensa_format_length (isa, fmt);
664df4e4
BW		 4868 branch_align = 1 << branch_align_power (sec);
4869 frag_addr = frag->fr_address % branch_align;
4870 if (frag_addr + op_size > branch_align)
43cd72b9
BW		 4871 as_warn_where (frag->fr_file, frag->fr_line,
4872 _("unaligned branch target: %d bytes at 0x%lx"),
dd49a749 4873 op_size, (long) frag->fr_address);
43cd72b9
BW		 4874 }
4875 frag = frag->fr_next;
4876 }
4877 xtensa_insnbuf_free (isa, insnbuf);
4878 }
4879}
4880
4881
4882static void
7fa3d080
BW		 4883xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED,
4884 asection *sec,
4885 void *unused ATTRIBUTE_UNUSED)
43cd72b9
BW		 4886{
4887 flagword flags = bfd_get_section_flags (abfd, sec);
4888 segment_info_type *seginfo = seg_info (sec);
4889 fragS *frag = seginfo->frchainP->frch_root;
4890 xtensa_isa isa = xtensa_default_isa;
c138bc38 4891
43cd72b9 4892 if (flags & SEC_CODE)
c138bc38 4893 {
43cd72b9
BW		 4894 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
4895 while (frag != NULL)
4896 {
4897 if (frag->tc_frag_data.is_first_loop_insn)
4898 {
4899 int op_size;
d77b99c9 4900 addressT frag_addr;
43cd72b9
BW		 4901 xtensa_format fmt;
4902
d77b99c9
BW		 4903 xtensa_insnbuf_from_chars
4904 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
43cd72b9
BW		 4905 fmt = xtensa_format_decode (isa, insnbuf);
4906 op_size = xtensa_format_length (isa, fmt);
4907 frag_addr = frag->fr_address % xtensa_fetch_width;
4908
d77b99c9 4909 if (frag_addr + op_size > xtensa_fetch_width)
43cd72b9
BW		 4910 as_warn_where (frag->fr_file, frag->fr_line,
4911 _("unaligned loop: %d bytes at 0x%lx"),
dd49a749 4912 op_size, (long) frag->fr_address);
43cd72b9
BW		 4913 }
4914 frag = frag->fr_next;
4915 }
4916 xtensa_insnbuf_free (isa, insnbuf);
4917 }
4918}
4919
4920
30f725a1
BW		 4921static int
4922xg_apply_fix_value (fixS *fixP, valueT val)
43cd72b9
BW		 4923{
4924 xtensa_isa isa = xtensa_default_isa;
4925 static xtensa_insnbuf insnbuf = NULL;
4926 static xtensa_insnbuf slotbuf = NULL;
4927 xtensa_format fmt;
4928 int slot;
4929 bfd_boolean alt_reloc;
4930 xtensa_opcode opcode;
4931 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
4932
4933 (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc);
4934 if (alt_reloc)
4935 as_fatal (_("unexpected fix"));
4936
4937 if (!insnbuf)
4938 {
4939 insnbuf = xtensa_insnbuf_alloc (isa);
4940 slotbuf = xtensa_insnbuf_alloc (isa);
4941 }
4942
d77b99c9 4943 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
43cd72b9
BW		 4944 fmt = xtensa_format_decode (isa, insnbuf);
4945 if (fmt == XTENSA_UNDEFINED)
4946 as_fatal (_("undecodable fix"));
4947 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
4948 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
4949 if (opcode == XTENSA_UNDEFINED)
4950 as_fatal (_("undecodable fix"));
4951
4952 /* CONST16 immediates are not PC-relative, despite the fact that we
4953 reuse the normal PC-relative operand relocations for the low part
30f725a1 4954 of a CONST16 operand. */
43cd72b9 4955 if (opcode == xtensa_const16_opcode)
30f725a1 4956 return 0;
43cd72b9
BW		 4957
4958 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode,
4959 get_relaxable_immed (opcode), val,
4960 fixP->fx_file, fixP->fx_line);
4961
4962 xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf);
d77b99c9 4963 xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
30f725a1
BW		 4964
4965 return 1;
43cd72b9
BW		 4966}
4967
e0001a05
NC		 4968\f
4969/* External Functions and Other GAS Hooks. */
4970
4971const char *
7fa3d080 4972xtensa_target_format (void)
e0001a05
NC		 4973{
4974 return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le");
4975}
4976
4977
4978void
7fa3d080 4979xtensa_file_arch_init (bfd *abfd)
e0001a05
NC		 4980{
4981 bfd_set_private_flags (abfd, 0x100 | 0x200);
4982}
4983
4984
4985void
7fa3d080 4986md_number_to_chars (char *buf, valueT val, int n)
e0001a05
NC		 4987{
4988 if (target_big_endian)
4989 number_to_chars_bigendian (buf, val, n);
4990 else
4991 number_to_chars_littleendian (buf, val, n);
4992}
4993
4994
4995/* This function is called once, at assembler startup time. It should
4996 set up all the tables, etc. that the MD part of the assembler will
4997 need. */
4998
4999void
7fa3d080 5000md_begin (void)
e0001a05
NC		 5001{
5002 segT current_section = now_seg;
5003 int current_subsec = now_subseg;
5004 xtensa_isa isa;
5005
43cd72b9 5006 xtensa_default_isa = xtensa_isa_init (0, 0);
e0001a05 5007 isa = xtensa_default_isa;
e0001a05 5008
43cd72b9
BW		 5009 linkrelax = 1;
5010
74869ac7 5011 /* Set up the literal sections. */
e0001a05 5012 memset (&default_lit_sections, 0, sizeof (default_lit_sections));
e0001a05
NC		 5013
5014 subseg_set (current_section, current_subsec);
5015
43cd72b9
BW		 5016 xg_init_vinsn (&cur_vinsn);
5017
e0001a05
NC		 5018 xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi");
5019 xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi");
5020 xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0");
5021 xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4");
5022 xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8");
5023 xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12");
5024 xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0");
5025 xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4");
5026 xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8");
5027 xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12");
43cd72b9 5028 xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16");
e0001a05 5029 xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry");
d12f9798 5030 xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui");
43cd72b9
BW		 5031 xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
5032 xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
e0001a05 5033 xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
e0001a05 5034 xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
43cd72b9 5035 xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
e0001a05
NC		 5036 xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
5037 xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez");
5038 xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz");
43cd72b9 5039 xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop");
e0001a05
NC		 5040 xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n");
5041 xtensa_or_opcode = xtensa_opcode_lookup (isa, "or");
5042 xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret");
5043 xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n");
5044 xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw");
5045 xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n");
43cd72b9 5046 xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
e0001a05 5047 xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
43cd72b9
BW		 5048
5049 init_op_placement_info_table ();
5050
5051 /* Set up the assembly state. */
5052 if (!frag_now->tc_frag_data.is_assembly_state_set)
5053 xtensa_set_frag_assembly_state (frag_now);
5054}
5055
5056
5057/* TC_INIT_FIX_DATA hook */
5058
5059void
7fa3d080 5060xtensa_init_fix_data (fixS *x)
43cd72b9
BW		 5061{
5062 x->tc_fix_data.slot = 0;
5063 x->tc_fix_data.X_add_symbol = NULL;
5064 x->tc_fix_data.X_add_number = 0;
e0001a05
NC		 5065}
5066
5067
5068/* tc_frob_label hook */
5069
5070void
7fa3d080 5071xtensa_frob_label (symbolS *sym)
e0001a05 5072{
3ea38ac2
BW		 5073 float freq;
5074
5075 if (cur_vinsn.inside_bundle)
5076 {
5077 as_bad (_("labels are not valid inside bundles"));
5078 return;
5079 }
5080
5081 freq = get_subseg_target_freq (now_seg, now_subseg);
7b1cc377 5082
43cd72b9
BW		 5083 /* Since the label was already attached to a frag associated with the
5084 previous basic block, it now needs to be reset to the current frag. */
5085 symbol_set_frag (sym, frag_now);
5086 S_SET_VALUE (sym, (valueT) frag_now_fix ());
5087
82e7541d
BW		 5088 if (generating_literals)
5089 xtensa_add_literal_sym (sym);
5090 else
5091 xtensa_add_insn_label (sym);
5092
7b1cc377
BW		 5093 if (symbol_get_tc (sym)->is_loop_target)
5094 {
5095 if ((get_last_insn_flags (now_seg, now_subseg)
e0001a05 5096 & FLAG_IS_BAD_LOOPEND) != 0)
7b1cc377
BW		 5097 as_bad (_("invalid last instruction for a zero-overhead loop"));
5098
5099 xtensa_set_frag_assembly_state (frag_now);
5100 frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END,
5101 frag_now->fr_symbol, frag_now->fr_offset, NULL);
5102
5103 xtensa_set_frag_assembly_state (frag_now);
c3ea6048 5104 xtensa_move_labels (frag_now, 0);
07a53e5c 5105 }
e0001a05
NC		 5106
5107 /* No target aligning in the absolute section. */
61846f28 5108 if (now_seg != absolute_section
43cd72b9 5109 && do_align_targets ()
61846f28 5110 && !is_unaligned_label (sym)
43cd72b9
BW		 5111 && !generating_literals)
5112 {
43cd72b9
BW		 5113 xtensa_set_frag_assembly_state (frag_now);
5114
43cd72b9 5115 frag_var (rs_machine_dependent,
7b1cc377 5116 0, (int) freq,
e0001a05
NC		 5117 RELAX_DESIRE_ALIGN_IF_TARGET,
5118 frag_now->fr_symbol, frag_now->fr_offset, NULL);
43cd72b9 5119 xtensa_set_frag_assembly_state (frag_now);
c3ea6048 5120 xtensa_move_labels (frag_now, 0);
43cd72b9
BW		 5121 }
5122
5123 /* We need to mark the following properties even if we aren't aligning. */
5124
5125 /* If the label is already known to be a branch target, i.e., a
5126 forward branch, mark the frag accordingly. Backward branches
5127 are handled by xg_add_branch_and_loop_targets. */
5128 if (symbol_get_tc (sym)->is_branch_target)
5129 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
5130
5131 /* Loops only go forward, so they can be identified here. */
5132 if (symbol_get_tc (sym)->is_loop_target)
5133 symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
07a53e5c
RH		 5134
5135 dwarf2_emit_label (sym);
43cd72b9
BW		 5136}
5137
5138
5139/* tc_unrecognized_line hook */
5140
5141int
7fa3d080 5142xtensa_unrecognized_line (int ch)
43cd72b9
BW		 5143{
5144 switch (ch)
5145 {
5146 case '{' :
5147 if (cur_vinsn.inside_bundle == 0)
5148 {
5149 /* PR8110: Cannot emit line number info inside a FLIX bundle
5150 when using --gstabs. Temporarily disable debug info. */
5151 generate_lineno_debug ();
5152 if (debug_type == DEBUG_STABS)
5153 {
5154 xt_saved_debug_type = debug_type;
5155 debug_type = DEBUG_NONE;
5156 }
82e7541d 5157
43cd72b9
BW		 5158 cur_vinsn.inside_bundle = 1;
5159 }
5160 else
5161 {
5162 as_bad (_("extra opening brace"));
5163 return 0;
5164 }
5165 break;
82e7541d 5166
43cd72b9
BW		 5167 case '}' :
5168 if (cur_vinsn.inside_bundle)
5169 finish_vinsn (&cur_vinsn);
5170 else
5171 {
5172 as_bad (_("extra closing brace"));
5173 return 0;
5174 }
5175 break;
5176 default:
5177 as_bad (_("syntax error"));
5178 return 0;
e0001a05 5179 }
43cd72b9 5180 return 1;
e0001a05
NC		 5181}
5182
5183
5184/* md_flush_pending_output hook */
5185
5186void
7fa3d080 5187xtensa_flush_pending_output (void)
e0001a05 5188{
a3582eee
BW		 5189 /* This line fixes a bug where automatically generated gstabs info
5190 separates a function label from its entry instruction, ending up
5191 with the literal position between the function label and the entry
5192 instruction and crashing code. It only happens with --gstabs and
5193 --text-section-literals, and when several other obscure relaxation
5194 conditions are met. */
5195 if (outputting_stabs_line_debug)
5196 return;
5197
43cd72b9
BW		 5198 if (cur_vinsn.inside_bundle)
5199 as_bad (_("missing closing brace"));
5200
e0001a05
NC		 5201 /* If there is a non-zero instruction fragment, close it. */
5202 if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn)
5203 {
5204 frag_wane (frag_now);
5205 frag_new (0);
43cd72b9 5206 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 5207 }
5208 frag_now->tc_frag_data.is_insn = FALSE;
82e7541d
BW		 5209
5210 xtensa_clear_insn_labels ();
e0001a05
NC		 5211}
5212
5213
43cd72b9
BW		 5214/* We had an error while parsing an instruction. The string might look
5215 like this: "insn arg1, arg2 }". If so, we need to see the closing
5216 brace and reset some fields. Otherwise, the vinsn never gets closed
5217 and the num_slots field will grow past the end of the array of slots,
5218 and bad things happen. */
5219
5220static void
7fa3d080 5221error_reset_cur_vinsn (void)
43cd72b9
BW		 5222{
5223 if (cur_vinsn.inside_bundle)
5224 {
5225 if (*input_line_pointer == '}'
5226 || *(input_line_pointer - 1) == '}'
5227 || *(input_line_pointer - 2) == '}')
5228 xg_clear_vinsn (&cur_vinsn);
5229 }
5230}
5231
5232
e0001a05 5233void
7fa3d080 5234md_assemble (char *str)
e0001a05
NC		 5235{
5236 xtensa_isa isa = xtensa_default_isa;
7c430684 5237 char *opname, *file_name;
e0001a05
NC		 5238 unsigned opnamelen;
5239 bfd_boolean has_underbar = FALSE;
43cd72b9 5240 char *arg_strings[MAX_INSN_ARGS];
e0001a05 5241 int num_args;
e0001a05 5242 TInsn orig_insn; /* Original instruction from the input. */
e0001a05 5243
e0001a05
NC		 5244 tinsn_init (&orig_insn);
5245
5246 /* Split off the opcode. */
5247 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5248 opname = xmalloc (opnamelen + 1);
5249 memcpy (opname, str, opnamelen);
5250 opname[opnamelen] = '\0';
5251
5252 num_args = tokenize_arguments (arg_strings, str + opnamelen);
5253 if (num_args == -1)
5254 {
5255 as_bad (_("syntax error"));
5256 return;
5257 }
5258
5259 if (xg_translate_idioms (&opname, &num_args, arg_strings))
5260 return;
5261
5262 /* Check for an underbar prefix. */
5263 if (*opname == '_')
5264 {
5265 has_underbar = TRUE;
5266 opname += 1;
5267 }
5268
5269 orig_insn.insn_type = ITYPE_INSN;
5270 orig_insn.ntok = 0;
43cd72b9 5271 orig_insn.is_specific_opcode = (has_underbar || !use_transform ());
e0001a05
NC		 5272
5273 orig_insn.opcode = xtensa_opcode_lookup (isa, opname);
5274 if (orig_insn.opcode == XTENSA_UNDEFINED)
5275 {
43cd72b9
BW		 5276 xtensa_format fmt = xtensa_format_lookup (isa, opname);
5277 if (fmt == XTENSA_UNDEFINED)
5278 {
5279 as_bad (_("unknown opcode or format name '%s'"), opname);
5280 error_reset_cur_vinsn ();
5281 return;
5282 }
5283 if (!cur_vinsn.inside_bundle)
5284 {
5285 as_bad (_("format names only valid inside bundles"));
5286 error_reset_cur_vinsn ();
5287 return;
5288 }
5289 if (cur_vinsn.format != XTENSA_UNDEFINED)
5290 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5291 opname);
5292 cur_vinsn.format = fmt;
5293 free (has_underbar ? opname - 1 : opname);
5294 error_reset_cur_vinsn ();
e0001a05
NC		 5295 return;
5296 }
5297
e0001a05
NC		 5298 /* Parse the arguments. */
5299 if (parse_arguments (&orig_insn, num_args, arg_strings))
5300 {
5301 as_bad (_("syntax error"));
43cd72b9 5302 error_reset_cur_vinsn ();
e0001a05
NC		 5303 return;
5304 }
5305
5306 /* Free the opcode and argument strings, now that they've been parsed. */
5307 free (has_underbar ? opname - 1 : opname);
5308 opname = 0;
5309 while (num_args-- > 0)
5310 free (arg_strings[num_args]);
5311
43cd72b9
BW		 5312 /* Get expressions for invisible operands. */
5313 if (get_invisible_operands (&orig_insn))
5314 {
5315 error_reset_cur_vinsn ();
5316 return;
5317 }
5318
e0001a05
NC		 5319 /* Check for the right number and type of arguments. */
5320 if (tinsn_check_arguments (&orig_insn))
e0001a05 5321 {
43cd72b9
BW		 5322 error_reset_cur_vinsn ();
5323 return;
e0001a05
NC		 5324 }
5325
7c430684
BW		 5326 /* A FLIX bundle may be spread across multiple input lines. We want to
5327 report the first such line in the debug information. Record the line
5328 number for each TInsn (assume the file name doesn't change), so the
5329 first line can be found later. */
5330 as_where (&file_name, &orig_insn.linenum);
c138bc38 5331
43cd72b9
BW		 5332 xg_add_branch_and_loop_targets (&orig_insn);
5333
431ad2d0
BW		 5334 /* Check that immediate value for ENTRY is >= 16. */
5335 if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3)
e0001a05 5336 {
431ad2d0
BW		 5337 expressionS *exp = &orig_insn.tok[2];
5338 if (exp->X_op == O_constant && exp->X_add_number < 16)
5339 as_warn (_("entry instruction with stack decrement < 16"));
e0001a05
NC		 5340 }
5341
e0001a05 5342 /* Finish it off:
43cd72b9
BW		 5343 assemble_tokens (opcode, tok, ntok);
5344 expand the tokens from the orig_insn into the
5345 stack of instructions that will not expand
e0001a05 5346 unless required at relaxation time. */
e0001a05 5347
43cd72b9
BW		 5348 if (!cur_vinsn.inside_bundle)
5349 emit_single_op (&orig_insn);
5350 else /* We are inside a bundle. */
e0001a05 5351 {
43cd72b9
BW		 5352 cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn;
5353 cur_vinsn.num_slots++;
5354 if (*input_line_pointer == '}'
5355 || *(input_line_pointer - 1) == '}'
5356 || *(input_line_pointer - 2) == '}')
5357 finish_vinsn (&cur_vinsn);
e0001a05
NC		 5358 }
5359
43cd72b9
BW		 5360 /* We've just emitted a new instruction so clear the list of labels. */
5361 xtensa_clear_insn_labels ();
e0001a05
NC		 5362}
5363
5364
43cd72b9 5365/* HANDLE_ALIGN hook */
e0001a05 5366
43cd72b9
BW		 5367/* For a .align directive, we mark the previous block with the alignment
5368 information. This will be placed in the object file in the
5369 property section corresponding to this section. */
e0001a05 5370
43cd72b9 5371void
7fa3d080 5372xtensa_handle_align (fragS *fragP)
43cd72b9
BW		 5373{
5374 if (linkrelax
b08b5071 5375 && ! fragP->tc_frag_data.is_literal
43cd72b9
BW		 5376 && (fragP->fr_type == rs_align
5377 || fragP->fr_type == rs_align_code)
5378 && fragP->fr_address + fragP->fr_fix > 0
5379 && fragP->fr_offset > 0
5380 && now_seg != bss_section)
e0001a05 5381 {
43cd72b9
BW		 5382 fragP->tc_frag_data.is_align = TRUE;
5383 fragP->tc_frag_data.alignment = fragP->fr_offset;
e0001a05
NC		 5384 }
5385
43cd72b9 5386 if (fragP->fr_type == rs_align_test)
e0001a05 5387 {
43cd72b9
BW		 5388 int count;
5389 count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5390 if (count != 0)
c138bc38 5391 as_bad_where (fragP->fr_file, fragP->fr_line,
43cd72b9 5392 _("unaligned entry instruction"));
e0001a05 5393 }
99ded152
BW		 5394
5395 if (linkrelax && fragP->fr_type == rs_org)
5396 fragP->fr_subtype = RELAX_ORG;
e0001a05 5397}
43cd72b9 5398
e0001a05
NC		 5399
5400/* TC_FRAG_INIT hook */
5401
5402void
7fa3d080 5403xtensa_frag_init (fragS *frag)
e0001a05 5404{
43cd72b9 5405 xtensa_set_frag_assembly_state (frag);
e0001a05
NC		 5406}
5407
5408
5409symbolS *
7fa3d080 5410md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
e0001a05
NC		 5411{
5412 return NULL;
5413}
5414
5415
5416/* Round up a section size to the appropriate boundary. */
5417
5418valueT
7fa3d080 5419md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
e0001a05
NC		 5420{
5421 return size; /* Byte alignment is fine. */
5422}
5423
5424
5425long
7fa3d080 5426md_pcrel_from (fixS *fixP)
e0001a05
NC		 5427{
5428 char *insn_p;
5429 static xtensa_insnbuf insnbuf = NULL;
43cd72b9 5430 static xtensa_insnbuf slotbuf = NULL;
e0001a05 5431 int opnum;
43cd72b9 5432 uint32 opnd_value;
e0001a05 5433 xtensa_opcode opcode;
43cd72b9
BW		 5434 xtensa_format fmt;
5435 int slot;
e0001a05
NC		 5436 xtensa_isa isa = xtensa_default_isa;
5437 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
43cd72b9 5438 bfd_boolean alt_reloc;
e0001a05 5439
e0001a05 5440 if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
30f725a1 5441 return 0;
e0001a05
NC		 5442
5443 if (!insnbuf)
43cd72b9
BW		 5444 {
5445 insnbuf = xtensa_insnbuf_alloc (isa);
5446 slotbuf = xtensa_insnbuf_alloc (isa);
5447 }
e0001a05
NC		 5448
5449 insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where];
d77b99c9 5450 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0);
43cd72b9
BW		 5451 fmt = xtensa_format_decode (isa, insnbuf);
5452
5453 if (fmt == XTENSA_UNDEFINED)
5454 as_fatal (_("bad instruction format"));
5455
5456 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0)
5457 as_fatal (_("invalid relocation"));
5458
5459 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5460 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5461
30f725a1
BW		 5462 /* Check for "alternate" relocations (operand not specified). None
5463 of the current uses for these are really PC-relative. */
43cd72b9
BW		 5464 if (alt_reloc || opcode == xtensa_const16_opcode)
5465 {
5466 if (opcode != xtensa_l32r_opcode
5467 && opcode != xtensa_const16_opcode)
5468 as_fatal (_("invalid relocation for '%s' instruction"),
5469 xtensa_opcode_name (isa, opcode));
30f725a1 5470 return 0;
e0001a05
NC		 5471 }
5472
43cd72b9
BW		 5473 opnum = get_relaxable_immed (opcode);
5474 opnd_value = 0;
5475 if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1
5476 || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr))
e0001a05
NC		 5477 {
5478 as_bad_where (fixP->fx_file,
5479 fixP->fx_line,
5480 _("invalid relocation for operand %d of '%s'"),
5481 opnum, xtensa_opcode_name (isa, opcode));
30f725a1 5482 return 0;
e0001a05 5483 }
43cd72b9
BW		 5484 return 0 - opnd_value;
5485}
5486
5487
5488/* TC_FORCE_RELOCATION hook */
5489
5490int
7fa3d080 5491xtensa_force_relocation (fixS *fix)
43cd72b9
BW		 5492{
5493 switch (fix->fx_r_type)
30f725a1
BW		 5494 {
5495 case BFD_RELOC_XTENSA_ASM_EXPAND:
43cd72b9
BW		 5496 case BFD_RELOC_XTENSA_SLOT0_ALT:
5497 case BFD_RELOC_XTENSA_SLOT1_ALT:
5498 case BFD_RELOC_XTENSA_SLOT2_ALT:
5499 case BFD_RELOC_XTENSA_SLOT3_ALT:
5500 case BFD_RELOC_XTENSA_SLOT4_ALT:
5501 case BFD_RELOC_XTENSA_SLOT5_ALT:
5502 case BFD_RELOC_XTENSA_SLOT6_ALT:
5503 case BFD_RELOC_XTENSA_SLOT7_ALT:
5504 case BFD_RELOC_XTENSA_SLOT8_ALT:
5505 case BFD_RELOC_XTENSA_SLOT9_ALT:
5506 case BFD_RELOC_XTENSA_SLOT10_ALT:
5507 case BFD_RELOC_XTENSA_SLOT11_ALT:
5508 case BFD_RELOC_XTENSA_SLOT12_ALT:
5509 case BFD_RELOC_XTENSA_SLOT13_ALT:
5510 case BFD_RELOC_XTENSA_SLOT14_ALT:
43cd72b9
BW		 5511 return 1;
5512 default:
5513 break;
e0001a05
NC		 5514 }
5515
43cd72b9
BW		 5516 if (linkrelax && fix->fx_addsy
5517 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
5518 return 1;
5519
5520 return generic_force_reloc (fix);
5521}
5522
5523
30f725a1
BW		 5524/* TC_VALIDATE_FIX_SUB hook */
5525
5526int
5527xtensa_validate_fix_sub (fixS *fix)
5528{
5529 segT add_symbol_segment, sub_symbol_segment;
5530
5531 /* The difference of two symbols should be resolved by the assembler when
5532 linkrelax is not set. If the linker may relax the section containing
5533 the symbols, then an Xtensa DIFF relocation must be generated so that
5534 the linker knows to adjust the difference value. */
5535 if (!linkrelax || fix->fx_addsy == NULL)
5536 return 0;
5537
5538 /* Make sure both symbols are in the same segment, and that segment is
5539 "normal" and relaxable. If the segment is not "normal", then the
5540 fix is not valid. If the segment is not "relaxable", then the fix
5541 should have been handled earlier. */
5542 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
5543 if (! SEG_NORMAL (add_symbol_segment) ||
5544 ! relaxable_section (add_symbol_segment))
5545 return 0;
5546 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
5547 return (sub_symbol_segment == add_symbol_segment);
5548}
5549
5550
43cd72b9
BW		 5551/* NO_PSEUDO_DOT hook */
5552
5553/* This function has nothing to do with pseudo dots, but this is the
5554 nearest macro to where the check needs to take place. FIXME: This
5555 seems wrong. */
5556
5557bfd_boolean
7fa3d080 5558xtensa_check_inside_bundle (void)
43cd72b9
BW		 5559{
5560 if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
5561 as_bad (_("directives are not valid inside bundles"));
5562
5563 /* This function must always return FALSE because it is called via a
5564 macro that has nothing to do with bundling. */
5565 return FALSE;
e0001a05
NC		 5566}
5567
5568
43cd72b9 5569/* md_elf_section_change_hook */
e0001a05
NC		 5570
5571void
7fa3d080 5572xtensa_elf_section_change_hook (void)
e0001a05 5573{
43cd72b9
BW		 5574 /* Set up the assembly state. */
5575 if (!frag_now->tc_frag_data.is_assembly_state_set)
5576 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 5577}
5578
5579
5580/* tc_fix_adjustable hook */
5581
5582bfd_boolean
7fa3d080 5583xtensa_fix_adjustable (fixS *fixP)
e0001a05 5584{
43cd72b9
BW		 5585 /* An offset is not allowed in combination with the difference of two
5586 symbols, but that cannot be easily detected after a local symbol
5587 has been adjusted to a (section+offset) form. Return 0 so that such
5588 an fix will not be adjusted. */
5589 if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset
5590 && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy)))
5591 return 0;
5592
e0001a05
NC		 5593 /* We need the symbol name for the VTABLE entries. */
5594 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5595 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5596 return 0;
5597
5598 return 1;
5599}
5600
5601
6a7eedfe
BW		 5602/* tc_symbol_new_hook */
5603
5604symbolS *expr_symbols = NULL;
5605
5606void
5607xtensa_symbol_new_hook (symbolS *sym)
5608{
5609 if (S_GET_SEGMENT (sym) == expr_section)
5610 {
5611 symbol_get_tc (sym)->next_expr_symbol = expr_symbols;
5612 expr_symbols = sym;
5613 }
5614}
5615
5616
5617
e0001a05 5618void
55cf6793 5619md_apply_fix (fixS *fixP, valueT *valP, segT seg)
e0001a05 5620{
30f725a1 5621 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
d47d412e 5622 valueT val = 0;
30f725a1 5623
e7da6241
BW		 5624 /* Subtracted symbols are only allowed for a few relocation types, and
5625 unless linkrelax is enabled, they should not make it to this point. */
5626 if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32
5627 || fixP->fx_r_type == BFD_RELOC_16
5628 || fixP->fx_r_type == BFD_RELOC_8)))
5629 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
5630
30f725a1 5631 switch (fixP->fx_r_type)
e0001a05 5632 {
30f725a1
BW		 5633 case BFD_RELOC_32:
5634 case BFD_RELOC_16:
5635 case BFD_RELOC_8:
e7da6241 5636 if (fixP->fx_subsy)
30f725a1
BW		 5637 {
5638 switch (fixP->fx_r_type)
5639 {
5640 case BFD_RELOC_8:
5641 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8;
5642 break;
5643 case BFD_RELOC_16:
5644 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16;
5645 break;
5646 case BFD_RELOC_32:
5647 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32;
5648 break;
5649 default:
5650 break;
5651 }
e0001a05 5652
30f725a1
BW		 5653 /* An offset is only allowed when it results from adjusting a
5654 local symbol into a section-relative offset. If the offset
5655 came from the original expression, tc_fix_adjustable will have
5656 prevented the fix from being converted to a section-relative
5657 form so that we can flag the error here. */
5658 if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy))
5659 as_bad_where (fixP->fx_file, fixP->fx_line,
5660 _("cannot represent subtraction with an offset"));
5661
5662 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
5663 - S_GET_VALUE (fixP->fx_subsy));
5664
5665 /* The difference value gets written out, and the DIFF reloc
5666 identifies the address of the subtracted symbol (i.e., the one
5667 with the lowest address). */
5668 *valP = val;
5669 fixP->fx_offset -= val;
5670 fixP->fx_subsy = NULL;
5671 }
5672 else if (! fixP->fx_addsy)
e0001a05 5673 {
30f725a1 5674 val = *valP;
e0001a05 5675 fixP->fx_done = 1;
30f725a1 5676 }
d47d412e
BW		 5677 /* fall through */
5678
5679 case BFD_RELOC_XTENSA_PLT:
30f725a1
BW		 5680 md_number_to_chars (fixpos, val, fixP->fx_size);
5681 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */
5682 break;
e0001a05 5683
30f725a1
BW		 5684 case BFD_RELOC_XTENSA_SLOT0_OP:
5685 case BFD_RELOC_XTENSA_SLOT1_OP:
5686 case BFD_RELOC_XTENSA_SLOT2_OP:
5687 case BFD_RELOC_XTENSA_SLOT3_OP:
5688 case BFD_RELOC_XTENSA_SLOT4_OP:
5689 case BFD_RELOC_XTENSA_SLOT5_OP:
5690 case BFD_RELOC_XTENSA_SLOT6_OP:
5691 case BFD_RELOC_XTENSA_SLOT7_OP:
5692 case BFD_RELOC_XTENSA_SLOT8_OP:
5693 case BFD_RELOC_XTENSA_SLOT9_OP:
5694 case BFD_RELOC_XTENSA_SLOT10_OP:
5695 case BFD_RELOC_XTENSA_SLOT11_OP:
5696 case BFD_RELOC_XTENSA_SLOT12_OP:
5697 case BFD_RELOC_XTENSA_SLOT13_OP:
5698 case BFD_RELOC_XTENSA_SLOT14_OP:
5699 if (linkrelax)
5700 {
5701 /* Write the tentative value of a PC-relative relocation to a
5702 local symbol into the instruction. The value will be ignored
5703 by the linker, and it makes the object file disassembly
5704 readable when all branch targets are encoded in relocations. */
5705
5706 assert (fixP->fx_addsy);
20ee54e8 5707 if (S_GET_SEGMENT (fixP->fx_addsy) == seg
30f725a1
BW		 5708 && !S_FORCE_RELOC (fixP->fx_addsy, 1))
5709 {
5710 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
5711 - md_pcrel_from (fixP));
5712 (void) xg_apply_fix_value (fixP, val);
5713 }
5714 }
5715 else if (! fixP->fx_addsy)
5716 {
5717 val = *valP;
5718 if (xg_apply_fix_value (fixP, val))
5719 fixP->fx_done = 1;
5720 }
5721 break;
e0001a05 5722
30f725a1
BW		 5723 case BFD_RELOC_XTENSA_ASM_EXPAND:
5724 case BFD_RELOC_XTENSA_SLOT0_ALT:
5725 case BFD_RELOC_XTENSA_SLOT1_ALT:
5726 case BFD_RELOC_XTENSA_SLOT2_ALT:
5727 case BFD_RELOC_XTENSA_SLOT3_ALT:
5728 case BFD_RELOC_XTENSA_SLOT4_ALT:
5729 case BFD_RELOC_XTENSA_SLOT5_ALT:
5730 case BFD_RELOC_XTENSA_SLOT6_ALT:
5731 case BFD_RELOC_XTENSA_SLOT7_ALT:
5732 case BFD_RELOC_XTENSA_SLOT8_ALT:
5733 case BFD_RELOC_XTENSA_SLOT9_ALT:
5734 case BFD_RELOC_XTENSA_SLOT10_ALT:
5735 case BFD_RELOC_XTENSA_SLOT11_ALT:
5736 case BFD_RELOC_XTENSA_SLOT12_ALT:
5737 case BFD_RELOC_XTENSA_SLOT13_ALT:
5738 case BFD_RELOC_XTENSA_SLOT14_ALT:
5739 /* These all need to be resolved at link-time. Do nothing now. */
5740 break;
e0001a05 5741
30f725a1
BW		 5742 case BFD_RELOC_VTABLE_INHERIT:
5743 case BFD_RELOC_VTABLE_ENTRY:
5744 fixP->fx_done = 0;
5745 break;
e0001a05 5746
30f725a1
BW		 5747 default:
5748 as_bad (_("unhandled local relocation fix %s"),
5749 bfd_get_reloc_code_name (fixP->fx_r_type));
e0001a05
NC		 5750 }
5751}
5752
5753
5754char *
7fa3d080 5755md_atof (int type, char *litP, int *sizeP)
e0001a05 5756{
499ac353 5757 return ieee_md_atof (type, litP, sizeP, target_big_endian);
e0001a05
NC		 5758}
5759
5760
5761int
7fa3d080 5762md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED)
e0001a05 5763{
34e41783 5764 return total_frag_text_expansion (fragP);
e0001a05
NC		 5765}
5766
5767
5768/* Translate internal representation of relocation info to BFD target
5769 format. */
5770
5771arelent *
30f725a1 5772tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
e0001a05
NC		 5773{
5774 arelent *reloc;
5775
5776 reloc = (arelent *) xmalloc (sizeof (arelent));
5777 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5778 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5779 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5780
5781 /* Make sure none of our internal relocations make it this far.
5782 They'd better have been fully resolved by this point. */
5783 assert ((int) fixp->fx_r_type > 0);
5784
30f725a1 5785 reloc->addend = fixp->fx_offset;
43cd72b9 5786
e0001a05
NC		 5787 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
5788 if (reloc->howto == NULL)
5789 {
5790 as_bad_where (fixp->fx_file, fixp->fx_line,
5791 _("cannot represent `%s' relocation in object file"),
5792 bfd_get_reloc_code_name (fixp->fx_r_type));
43cd72b9
BW		 5793 free (reloc->sym_ptr_ptr);
5794 free (reloc);
e0001a05
NC		 5795 return NULL;
5796 }
5797
5798 if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
43cd72b9
BW		 5799 as_fatal (_("internal error? cannot generate `%s' relocation"),
5800 bfd_get_reloc_code_name (fixp->fx_r_type));
e0001a05 5801
e0001a05
NC		 5802 return reloc;
5803}
5804
7fa3d080
BW		 5805\f
5806/* Checks for resource conflicts between instructions. */
5807
c138bc38
BW		 5808/* The func unit stuff could be implemented as bit-vectors rather
5809 than the iterative approach here. If it ends up being too
7fa3d080
BW		 5810 slow, we will switch it. */
5811
c138bc38 5812resource_table *
7fa3d080
BW		 5813new_resource_table (void *data,
5814 int cycles,
5815 int nu,
5816 unit_num_copies_func uncf,
5817 opcode_num_units_func onuf,
5818 opcode_funcUnit_use_unit_func ouuf,
5819 opcode_funcUnit_use_stage_func ousf)
5820{
5821 int i;
5822 resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table));
5823 rt->data = data;
5824 rt->cycles = cycles;
5825 rt->allocated_cycles = cycles;
5826 rt->num_units = nu;
5827 rt->unit_num_copies = uncf;
5828 rt->opcode_num_units = onuf;
5829 rt->opcode_unit_use = ouuf;
5830 rt->opcode_unit_stage = ousf;
5831
0bf60745 5832 rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *));
7fa3d080 5833 for (i = 0; i < cycles; i++)
0bf60745 5834 rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char));
7fa3d080
BW		 5835
5836 return rt;
5837}
5838
5839
c138bc38 5840void
7fa3d080
BW		 5841clear_resource_table (resource_table *rt)
5842{
5843 int i, j;
5844 for (i = 0; i < rt->allocated_cycles; i++)
5845 for (j = 0; j < rt->num_units; j++)
5846 rt->units[i][j] = 0;
5847}
5848
5849
5850/* We never shrink it, just fake it into thinking so. */
5851
c138bc38 5852void
7fa3d080
BW		 5853resize_resource_table (resource_table *rt, int cycles)
5854{
5855 int i, old_cycles;
5856
5857 rt->cycles = cycles;
5858 if (cycles <= rt->allocated_cycles)
5859 return;
5860
5861 old_cycles = rt->allocated_cycles;
5862 rt->allocated_cycles = cycles;
5863
0bf60745
BW		 5864 rt->units = xrealloc (rt->units,
5865 rt->allocated_cycles * sizeof (unsigned char *));
7fa3d080 5866 for (i = 0; i < old_cycles; i++)
0bf60745
BW		 5867 rt->units[i] = xrealloc (rt->units[i],
5868 rt->num_units * sizeof (unsigned char));
7fa3d080 5869 for (i = old_cycles; i < cycles; i++)
0bf60745 5870 rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char));
7fa3d080
BW		 5871}
5872
5873
c138bc38 5874bfd_boolean
7fa3d080
BW		 5875resources_available (resource_table *rt, xtensa_opcode opcode, int cycle)
5876{
5877 int i;
5878 int uses = (rt->opcode_num_units) (rt->data, opcode);
5879
c138bc38 5880 for (i = 0; i < uses; i++)
7fa3d080
BW		 5881 {
5882 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5883 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
5884 int copies_in_use = rt->units[stage + cycle][unit];
5885 int copies = (rt->unit_num_copies) (rt->data, unit);
5886 if (copies_in_use >= copies)
5887 return FALSE;
5888 }
5889 return TRUE;
5890}
7fa3d080 5891
c138bc38
BW		 5892
5893void
7fa3d080
BW		 5894reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
5895{
5896 int i;
5897 int uses = (rt->opcode_num_units) (rt->data, opcode);
5898
c138bc38 5899 for (i = 0; i < uses; i++)
7fa3d080
BW		 5900 {
5901 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5902 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
c138bc38
BW		 5903 /* Note that this allows resources to be oversubscribed. That's
5904 essential to the way the optional scheduler works.
7fa3d080
BW		 5905 resources_available reports when a resource is over-subscribed,
5906 so it's easy to tell. */
5907 rt->units[stage + cycle][unit]++;
5908 }
5909}
5910
5911
c138bc38 5912void
7fa3d080
BW		 5913release_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
5914{
5915 int i;
5916 int uses = (rt->opcode_num_units) (rt->data, opcode);
5917
c138bc38 5918 for (i = 0; i < uses; i++)
7fa3d080
BW		 5919 {
5920 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5921 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
0bf60745 5922 assert (rt->units[stage + cycle][unit] > 0);
7fa3d080 5923 rt->units[stage + cycle][unit]--;
7fa3d080
BW		 5924 }
5925}
c138bc38 5926
7fa3d080
BW		 5927
5928/* Wrapper functions make parameterized resource reservation
5929 more convenient. */
5930
c138bc38 5931int
7fa3d080
BW		 5932opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx)
5933{
5934 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
c138bc38 5935 return use->unit;
7fa3d080
BW		 5936}
5937
5938
c138bc38 5939int
7fa3d080
BW		 5940opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx)
5941{
5942 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
5943 return use->stage;
5944}
5945
5946
5947/* Note that this function does not check issue constraints, but
5948 solely whether the hardware is available to execute the given
c138bc38 5949 instructions together. It also doesn't check if the tinsns
7fa3d080 5950 write the same state, or access the same tieports. That is
a1ace8d8 5951 checked by check_t1_t2_reads_and_writes. */
7fa3d080
BW		 5952
5953static bfd_boolean
5954resources_conflict (vliw_insn *vinsn)
5955{
5956 int i;
5957 static resource_table *rt = NULL;
5958
5959 /* This is the most common case by far. Optimize it. */
5960 if (vinsn->num_slots == 1)
5961 return FALSE;
43cd72b9 5962
c138bc38 5963 if (rt == NULL)
7fa3d080
BW		 5964 {
5965 xtensa_isa isa = xtensa_default_isa;
5966 rt = new_resource_table
5967 (isa, xtensa_isa_num_pipe_stages (isa),
5968 xtensa_isa_num_funcUnits (isa),
5969 (unit_num_copies_func) xtensa_funcUnit_num_copies,
5970 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses,
5971 opcode_funcUnit_use_unit,
5972 opcode_funcUnit_use_stage);
5973 }
43cd72b9 5974
7fa3d080 5975 clear_resource_table (rt);
43cd72b9 5976
7fa3d080
BW		 5977 for (i = 0; i < vinsn->num_slots; i++)
5978 {
5979 if (!resources_available (rt, vinsn->slots[i].opcode, 0))
5980 return TRUE;
5981 reserve_resources (rt, vinsn->slots[i].opcode, 0);
5982 }
e0001a05 5983
7fa3d080
BW		 5984 return FALSE;
5985}
e0001a05 5986
7fa3d080
BW		 5987\f
5988/* finish_vinsn, emit_single_op and helper functions. */
e0001a05 5989
7fa3d080
BW		 5990static bfd_boolean find_vinsn_conflicts (vliw_insn *);
5991static xtensa_format xg_find_narrowest_format (vliw_insn *);
7fa3d080 5992static void xg_assemble_vliw_tokens (vliw_insn *);
e0001a05
NC		 5993
5994
43cd72b9
BW		 5995/* We have reached the end of a bundle; emit into the frag. */
5996
e0001a05 5997static void
7fa3d080 5998finish_vinsn (vliw_insn *vinsn)
e0001a05 5999{
43cd72b9
BW		 6000 IStack slotstack;
6001 int i;
6002 char *file_name;
d77b99c9 6003 unsigned line;
e0001a05 6004
43cd72b9 6005 if (find_vinsn_conflicts (vinsn))
a1ace8d8
BW		 6006 {
6007 xg_clear_vinsn (vinsn);
6008 return;
6009 }
43cd72b9
BW		 6010
6011 /* First, find a format that works. */
6012 if (vinsn->format == XTENSA_UNDEFINED)
6013 vinsn->format = xg_find_narrowest_format (vinsn);
6014
6015 if (vinsn->format == XTENSA_UNDEFINED)
6016 {
6017 as_where (&file_name, &line);
6018 as_bad_where (file_name, line,
6019 _("couldn't find a valid instruction format"));
6020 fprintf (stderr, _(" ops were: "));
6021 for (i = 0; i < vinsn->num_slots; i++)
6022 fprintf (stderr, _(" %s;"),
6023 xtensa_opcode_name (xtensa_default_isa,
6024 vinsn->slots[i].opcode));
6025 fprintf (stderr, _("\n"));
6026 xg_clear_vinsn (vinsn);
6027 return;
6028 }
6029
6030 if (vinsn->num_slots
6031 != xtensa_format_num_slots (xtensa_default_isa, vinsn->format))
e0001a05 6032 {
43cd72b9
BW		 6033 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6034 xtensa_format_name (xtensa_default_isa, vinsn->format),
6035 xtensa_format_num_slots (xtensa_default_isa, vinsn->format),
6036 vinsn->num_slots);
6037 xg_clear_vinsn (vinsn);
6038 return;
6039 }
e0001a05 6040
c138bc38 6041 if (resources_conflict (vinsn))
43cd72b9
BW		 6042 {
6043 as_where (&file_name, &line);
6044 as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6045 fprintf (stderr, " ops were: ");
6046 for (i = 0; i < vinsn->num_slots; i++)
6047 fprintf (stderr, " %s;",
6048 xtensa_opcode_name (xtensa_default_isa,
6049 vinsn->slots[i].opcode));
6050 fprintf (stderr, "\n");
6051 xg_clear_vinsn (vinsn);
6052 return;
6053 }
6054
6055 for (i = 0; i < vinsn->num_slots; i++)
6056 {
6057 if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
e0001a05 6058 {
43cd72b9
BW		 6059 symbolS *lit_sym = NULL;
6060 int j;
6061 bfd_boolean e = FALSE;
6062 bfd_boolean saved_density = density_supported;
6063
6064 /* We don't want to narrow ops inside multi-slot bundles. */
6065 if (vinsn->num_slots > 1)
6066 density_supported = FALSE;
6067
6068 istack_init (&slotstack);
6069 if (vinsn->slots[i].opcode == xtensa_nop_opcode)
e0001a05 6070 {
43cd72b9
BW		 6071 vinsn->slots[i].opcode =
6072 xtensa_format_slot_nop_opcode (xtensa_default_isa,
6073 vinsn->format, i);
6074 vinsn->slots[i].ntok = 0;
6075 }
e0001a05 6076
43cd72b9
BW		 6077 if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
6078 {
6079 e = TRUE;
6080 continue;
e0001a05 6081 }
e0001a05 6082
43cd72b9 6083 density_supported = saved_density;
e0001a05 6084
43cd72b9
BW		 6085 if (e)
6086 {
6087 xg_clear_vinsn (vinsn);
6088 return;
6089 }
e0001a05 6090
0fa77c95 6091 for (j = 0; j < slotstack.ninsn; j++)
43cd72b9
BW		 6092 {
6093 TInsn *insn = &slotstack.insn[j];
6094 if (insn->insn_type == ITYPE_LITERAL)
6095 {
6096 assert (lit_sym == NULL);
6097 lit_sym = xg_assemble_literal (insn);
6098 }
6099 else
6100 {
0fa77c95 6101 assert (insn->insn_type == ITYPE_INSN);
43cd72b9
BW		 6102 if (lit_sym)
6103 xg_resolve_literals (insn, lit_sym);
0fa77c95
BW		 6104 if (j != slotstack.ninsn - 1)
6105 emit_single_op (insn);
43cd72b9
BW		 6106 }
6107 }
6108
6109 if (vinsn->num_slots > 1)
6110 {
6111 if (opcode_fits_format_slot
6112 (slotstack.insn[slotstack.ninsn - 1].opcode,
6113 vinsn->format, i))
6114 {
6115 vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
6116 }
6117 else
6118 {
b2d179be 6119 emit_single_op (&slotstack.insn[slotstack.ninsn - 1]);
43cd72b9
BW		 6120 if (vinsn->format == XTENSA_UNDEFINED)
6121 vinsn->slots[i].opcode = xtensa_nop_opcode;
6122 else
c138bc38 6123 vinsn->slots[i].opcode
43cd72b9
BW		 6124 = xtensa_format_slot_nop_opcode (xtensa_default_isa,
6125 vinsn->format, i);
6126
6127 vinsn->slots[i].ntok = 0;
6128 }
6129 }
6130 else
6131 {
6132 vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
6133 vinsn->format = XTENSA_UNDEFINED;
6134 }
6135 }
6136 }
6137
6138 /* Now check resource conflicts on the modified bundle. */
c138bc38 6139 if (resources_conflict (vinsn))
43cd72b9
BW		 6140 {
6141 as_where (&file_name, &line);
6142 as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6143 fprintf (stderr, " ops were: ");
6144 for (i = 0; i < vinsn->num_slots; i++)
6145 fprintf (stderr, " %s;",
6146 xtensa_opcode_name (xtensa_default_isa,
6147 vinsn->slots[i].opcode));
6148 fprintf (stderr, "\n");
6149 xg_clear_vinsn (vinsn);
6150 return;
6151 }
6152
6153 /* First, find a format that works. */
6154 if (vinsn->format == XTENSA_UNDEFINED)
6155 vinsn->format = xg_find_narrowest_format (vinsn);
6156
6157 xg_assemble_vliw_tokens (vinsn);
6158
6159 xg_clear_vinsn (vinsn);
6160}
6161
6162
6163/* Given an vliw instruction, what conflicts are there in register
6164 usage and in writes to states and queues?
6165
6166 This function does two things:
6167 1. Reports an error when a vinsn contains illegal combinations
6168 of writes to registers states or queues.
6169 2. Marks individual tinsns as not relaxable if the combination
6170 contains antidependencies.
6171
6172 Job 2 handles things like swap semantics in instructions that need
6173 to be relaxed. For example,
6174
6175 addi a0, a1, 100000
6176
6177 normally would be relaxed to
6178
6179 l32r a0, some_label
6180 add a0, a1, a0
6181
6182 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6183
6184 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6185
6186 then we can't relax it into
6187
6188 l32r a0, some_label
6189 { add a0, a1, a0 ; add a2, a0, a4 ; }
6190
6191 because the value of a0 is trashed before the second add can read it. */
6192
7fa3d080
BW		 6193static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
6194
43cd72b9 6195static bfd_boolean
7fa3d080 6196find_vinsn_conflicts (vliw_insn *vinsn)
43cd72b9
BW		 6197{
6198 int i, j;
6199 int branches = 0;
6200 xtensa_isa isa = xtensa_default_isa;
6201
6202 assert (!past_xtensa_end);
6203
6204 for (i = 0 ; i < vinsn->num_slots; i++)
6205 {
6206 TInsn *op1 = &vinsn->slots[i];
6207 if (op1->is_specific_opcode)
6208 op1->keep_wide = TRUE;
6209 else
6210 op1->keep_wide = FALSE;
6211 }
6212
6213 for (i = 0 ; i < vinsn->num_slots; i++)
6214 {
6215 TInsn *op1 = &vinsn->slots[i];
6216
6217 if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
6218 branches++;
6219
6220 for (j = 0; j < vinsn->num_slots; j++)
6221 {
6222 if (i != j)
6223 {
6224 TInsn *op2 = &vinsn->slots[j];
6225 char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
6226 switch (conflict_type)
6227 {
6228 case 'c':
6229 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6230 xtensa_opcode_name (isa, op1->opcode), i,
6231 xtensa_opcode_name (isa, op2->opcode), j);
6232 return TRUE;
6233 case 'd':
6234 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6235 xtensa_opcode_name (isa, op1->opcode), i,
6236 xtensa_opcode_name (isa, op2->opcode), j);
6237 return TRUE;
6238 case 'e':
53dfbcc7 6239 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
43cd72b9
BW		 6240 xtensa_opcode_name (isa, op1->opcode), i,
6241 xtensa_opcode_name (isa, op2->opcode), j);
6242 return TRUE;
6243 case 'f':
53dfbcc7 6244 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
43cd72b9
BW		 6245 xtensa_opcode_name (isa, op1->opcode), i,
6246 xtensa_opcode_name (isa, op2->opcode), j);
6247 return TRUE;
6248 default:
6249 /* Everything is OK. */
6250 break;
6251 }
6252 op2->is_specific_opcode = (op2->is_specific_opcode
6253 || conflict_type == 'a');
6254 }
6255 }
6256 }
6257
6258 if (branches > 1)
6259 {
6260 as_bad (_("multiple branches or jumps in the same bundle"));
6261 return TRUE;
6262 }
6263
6264 return FALSE;
6265}
6266
6267
a1ace8d8 6268/* Check how the state used by t1 and t2 relate.
43cd72b9
BW		 6269 Cases found are:
6270
6271 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6272 case B: no relationship between what is read and written (both could
6273 read the same reg though)
c138bc38 6274 case C: t1 writes a register t2 writes (a register conflict within a
43cd72b9
BW		 6275 bundle)
6276 case D: t1 writes a state that t2 also writes
6277 case E: t1 writes a tie queue that t2 also writes
a1ace8d8 6278 case F: two volatile queue accesses
43cd72b9
BW		 6279*/
6280
6281static char
7fa3d080 6282check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2)
43cd72b9
BW		 6283{
6284 xtensa_isa isa = xtensa_default_isa;
6285 xtensa_regfile t1_regfile, t2_regfile;
6286 int t1_reg, t2_reg;
6287 int t1_base_reg, t1_last_reg;
6288 int t2_base_reg, t2_last_reg;
6289 char t1_inout, t2_inout;
6290 int i, j;
6291 char conflict = 'b';
6292 int t1_states;
6293 int t2_states;
6294 int t1_interfaces;
6295 int t2_interfaces;
6296 bfd_boolean t1_volatile = FALSE;
6297 bfd_boolean t2_volatile = FALSE;
6298
6299 /* Check registers. */
6300 for (j = 0; j < t2->ntok; j++)
6301 {
6302 if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
6303 continue;
6304
6305 t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
6306 t2_base_reg = t2->tok[j].X_add_number;
6307 t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
6308
6309 for (i = 0; i < t1->ntok; i++)
6310 {
6311 if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
6312 continue;
6313
6314 t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
6315
6316 if (t1_regfile != t2_regfile)
6317 continue;
6318
6319 t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
6320 t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
6321
6322 if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
6323 || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
6324 {
6325 if (t1_inout == 'm' || t1_inout == 'o'
6326 || t2_inout == 'm' || t2_inout == 'o')
6327 {
6328 conflict = 'a';
6329 continue;
6330 }
6331 }
6332
6333 t1_base_reg = t1->tok[i].X_add_number;
6334 t1_last_reg = (t1_base_reg
6335 + xtensa_operand_num_regs (isa, t1->opcode, i));
6336
6337 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
6338 {
6339 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
6340 {
6341 if (t1_reg != t2_reg)
6342 continue;
6343
6344 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
7fa3d080
BW		 6345 {
6346 conflict = 'a';
6347 continue;
6348 }
43cd72b9 6349
7fa3d080
BW		 6350 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6351 {
6352 conflict = 'a';
6353 continue;
6354 }
43cd72b9 6355
7fa3d080
BW		 6356 if (t1_inout != 'i' && t2_inout != 'i')
6357 return 'c';
6358 }
6359 }
6360 }
6361 }
43cd72b9 6362
7fa3d080
BW		 6363 /* Check states. */
6364 t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
6365 t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
6366 for (j = 0; j < t2_states; j++)
43cd72b9 6367 {
7fa3d080
BW		 6368 xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
6369 t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
6370 for (i = 0; i < t1_states; i++)
6371 {
6372 xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
6373 t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
c138bc38 6374 if (t1_so != t2_so)
7fa3d080 6375 continue;
43cd72b9 6376
7fa3d080
BW		 6377 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6378 {
6379 conflict = 'a';
6380 continue;
6381 }
c138bc38 6382
7fa3d080
BW		 6383 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6384 {
6385 conflict = 'a';
6386 continue;
6387 }
c138bc38 6388
7fa3d080
BW		 6389 if (t1_inout != 'i' && t2_inout != 'i')
6390 return 'd';
c138bc38 6391 }
7fa3d080 6392 }
43cd72b9 6393
7fa3d080
BW		 6394 /* Check tieports. */
6395 t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
6396 t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
c138bc38 6397 for (j = 0; j < t2_interfaces; j++)
43cd72b9 6398 {
7fa3d080
BW		 6399 xtensa_interface t2_int
6400 = xtensa_interfaceOperand_interface (isa, t2->opcode, j);
a1ace8d8
BW		 6401 int t2_class = xtensa_interface_class_id (isa, t2_int);
6402
53dfbcc7 6403 t2_inout = xtensa_interface_inout (isa, t2_int);
a1ace8d8 6404 if (xtensa_interface_has_side_effect (isa, t2_int) == 1)
7fa3d080 6405 t2_volatile = TRUE;
a1ace8d8 6406
7fa3d080
BW		 6407 for (i = 0; i < t1_interfaces; i++)
6408 {
6409 xtensa_interface t1_int
6410 = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
2eccd1b4 6411 int t1_class = xtensa_interface_class_id (isa, t1_int);
a1ace8d8 6412
53dfbcc7 6413 t1_inout = xtensa_interface_inout (isa, t1_int);
a1ace8d8 6414 if (xtensa_interface_has_side_effect (isa, t1_int) == 1)
7fa3d080 6415 t1_volatile = TRUE;
a1ace8d8
BW		 6416
6417 if (t1_volatile && t2_volatile && (t1_class == t2_class))
6418 return 'f';
c138bc38 6419
7fa3d080
BW		 6420 if (t1_int != t2_int)
6421 continue;
c138bc38 6422
7fa3d080
BW		 6423 if (t2_inout == 'i' && t1_inout == 'o')
6424 {
6425 conflict = 'a';
6426 continue;
6427 }
c138bc38 6428
7fa3d080
BW		 6429 if (t1_inout == 'i' && t2_inout == 'o')
6430 {
6431 conflict = 'a';
6432 continue;
6433 }
c138bc38 6434
7fa3d080
BW		 6435 if (t1_inout != 'i' && t2_inout != 'i')
6436 return 'e';
6437 }
43cd72b9 6438 }
c138bc38 6439
7fa3d080 6440 return conflict;
43cd72b9
BW		 6441}
6442
6443
6444static xtensa_format
7fa3d080 6445xg_find_narrowest_format (vliw_insn *vinsn)
43cd72b9
BW		 6446{
6447 /* Right now we assume that the ops within the vinsn are properly
6448 ordered for the slots that the programmer wanted them in. In
6449 other words, we don't rearrange the ops in hopes of finding a
6450 better format. The scheduler handles that. */
6451
6452 xtensa_isa isa = xtensa_default_isa;
6453 xtensa_format format;
6454 vliw_insn v_copy = *vinsn;
6455 xtensa_opcode nop_opcode = xtensa_nop_opcode;
6456
65738a7d
BW		 6457 if (vinsn->num_slots == 1)
6458 return xg_get_single_format (vinsn->slots[0].opcode);
6459
43cd72b9
BW		 6460 for (format = 0; format < xtensa_isa_num_formats (isa); format++)
6461 {
6462 v_copy = *vinsn;
6463 if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
6464 {
6465 int slot;
6466 int fit = 0;
6467 for (slot = 0; slot < v_copy.num_slots; slot++)
6468 {
6469 if (v_copy.slots[slot].opcode == nop_opcode)
6470 {
6471 v_copy.slots[slot].opcode =
6472 xtensa_format_slot_nop_opcode (isa, format, slot);
6473 v_copy.slots[slot].ntok = 0;
6474 }
6475
6476 if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
6477 format, slot))
6478 fit++;
7fa3d080 6479 else if (v_copy.num_slots > 1)
43cd72b9 6480 {
7fa3d080
BW		 6481 TInsn widened;
6482 /* Try the widened version. */
6483 if (!v_copy.slots[slot].keep_wide
6484 && !v_copy.slots[slot].is_specific_opcode
84b08ed9
BW		 6485 && xg_is_single_relaxable_insn (&v_copy.slots[slot],
6486 &widened, TRUE)
7fa3d080
BW		 6487 && opcode_fits_format_slot (widened.opcode,
6488 format, slot))
43cd72b9 6489 {
7fa3d080
BW		 6490 v_copy.slots[slot] = widened;
6491 fit++;
43cd72b9
BW		 6492 }
6493 }
6494 }
6495 if (fit == v_copy.num_slots)
6496 {
6497 *vinsn = v_copy;
6498 xtensa_format_encode (isa, format, vinsn->insnbuf);
6499 vinsn->format = format;
6500 break;
6501 }
6502 }
6503 }
6504
6505 if (format == xtensa_isa_num_formats (isa))
6506 return XTENSA_UNDEFINED;
6507
6508 return format;
6509}
6510
6511
6512/* Return the additional space needed in a frag
6513 for possible relaxations of any ops in a VLIW insn.
6514 Also fill out the relaxations that might be required of
6515 each tinsn in the vinsn. */
6516
6517static int
e7da6241 6518relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag)
43cd72b9 6519{
e7da6241 6520 bfd_boolean finish_frag = FALSE;
43cd72b9
BW		 6521 int extra_space = 0;
6522 int slot;
6523
6524 for (slot = 0; slot < vinsn->num_slots; slot++)
6525 {
6526 TInsn *tinsn = &vinsn->slots[slot];
6527 if (!tinsn_has_symbolic_operands (tinsn))
6528 {
6529 /* A narrow instruction could be widened later to help
6530 alignment issues. */
84b08ed9 6531 if (xg_is_single_relaxable_insn (tinsn, 0, TRUE)
43cd72b9
BW		 6532 && !tinsn->is_specific_opcode
6533 && vinsn->num_slots == 1)
6534 {
6535 /* Difference in bytes between narrow and wide insns... */
6536 extra_space += 1;
6537 tinsn->subtype = RELAX_NARROW;
43cd72b9
BW		 6538 }
6539 }
6540 else
6541 {
b08b5071
BW		 6542 if (workaround_b_j_loop_end
6543 && tinsn->opcode == xtensa_jx_opcode
43cd72b9
BW		 6544 && use_transform ())
6545 {
6546 /* Add 2 of these. */
6547 extra_space += 3; /* for the nop size */
6548 tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
6549 }
c138bc38 6550
43cd72b9
BW		 6551 /* Need to assemble it with space for the relocation. */
6552 if (xg_is_relaxable_insn (tinsn, 0)
6553 && !tinsn->is_specific_opcode)
6554 {
6555 int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
6556 int max_literal_size =
6557 xg_get_max_insn_widen_literal_size (tinsn->opcode);
c138bc38 6558
43cd72b9 6559 tinsn->literal_space = max_literal_size;
c138bc38 6560
43cd72b9 6561 tinsn->subtype = RELAX_IMMED;
43cd72b9
BW		 6562 extra_space += max_size;
6563 }
6564 else
6565 {
e7da6241
BW		 6566 /* A fix record will be added for this instruction prior
6567 to relaxation, so make it end the frag. */
6568 finish_frag = TRUE;
43cd72b9
BW		 6569 }
6570 }
6571 }
e7da6241 6572 *pfinish_frag = finish_frag;
43cd72b9
BW		 6573 return extra_space;
6574}
6575
6576
6577static void
b2d179be 6578bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn)
43cd72b9
BW		 6579{
6580 xtensa_isa isa = xtensa_default_isa;
b2d179be 6581 int slot, chosen_slot;
43cd72b9 6582
b2d179be
BW		 6583 vinsn->format = xg_get_single_format (tinsn->opcode);
6584 assert (vinsn->format != XTENSA_UNDEFINED);
6585 vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format);
43cd72b9 6586
b2d179be
BW		 6587 chosen_slot = xg_get_single_slot (tinsn->opcode);
6588 for (slot = 0; slot < vinsn->num_slots; slot++)
43cd72b9 6589 {
b2d179be
BW		 6590 if (slot == chosen_slot)
6591 vinsn->slots[slot] = *tinsn;
6592 else
6593 {
6594 vinsn->slots[slot].opcode =
6595 xtensa_format_slot_nop_opcode (isa, vinsn->format, slot);
6596 vinsn->slots[slot].ntok = 0;
6597 vinsn->slots[slot].insn_type = ITYPE_INSN;
6598 }
43cd72b9 6599 }
43cd72b9
BW		 6600}
6601
6602
6603static bfd_boolean
7fa3d080 6604emit_single_op (TInsn *orig_insn)
43cd72b9
BW		 6605{
6606 int i;
6607 IStack istack; /* put instructions into here */
6608 symbolS *lit_sym = NULL;
6609 symbolS *label_sym = NULL;
6610
6611 istack_init (&istack);
6612
6613 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
c138bc38
BW		 6614 Because the scheduling and bundling characteristics of movi and
6615 l32r or const16 are so different, we can do much better if we relax
43cd72b9 6616 it prior to scheduling and bundling, rather than after. */
c138bc38 6617 if ((orig_insn->opcode == xtensa_movi_opcode
b08b5071
BW		 6618 || orig_insn->opcode == xtensa_movi_n_opcode)
6619 && !cur_vinsn.inside_bundle
43cd72b9 6620 && (orig_insn->tok[1].X_op == O_symbol
482fd9f9
BW		 6621 || orig_insn->tok[1].X_op == O_pltrel)
6622 && !orig_insn->is_specific_opcode && use_transform ())
43cd72b9
BW		 6623 xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
6624 else
6625 if (xg_expand_assembly_insn (&istack, orig_insn))
6626 return TRUE;
6627
6628 for (i = 0; i < istack.ninsn; i++)
6629 {
6630 TInsn *insn = &istack.insn[i];
c138bc38 6631 switch (insn->insn_type)
43cd72b9
BW		 6632 {
6633 case ITYPE_LITERAL:
6634 assert (lit_sym == NULL);
6635 lit_sym = xg_assemble_literal (insn);
6636 break;
6637 case ITYPE_LABEL:
6638 {
6639 static int relaxed_sym_idx = 0;
6640 char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12);
6641 sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
6642 colon (label);
6643 assert (label_sym == NULL);
6644 label_sym = symbol_find_or_make (label);
6645 assert (label_sym);
6646 free (label);
6647 }
6648 break;
6649 case ITYPE_INSN:
b2d179be
BW		 6650 {
6651 vliw_insn v;
6652 if (lit_sym)
6653 xg_resolve_literals (insn, lit_sym);
6654 if (label_sym)
6655 xg_resolve_labels (insn, label_sym);
6656 xg_init_vinsn (&v);
6657 bundle_tinsn (insn, &v);
6658 finish_vinsn (&v);
6659 xg_free_vinsn (&v);
6660 }
43cd72b9
BW		 6661 break;
6662 default:
6663 assert (0);
6664 break;
6665 }
6666 }
6667 return FALSE;
6668}
6669
6670
34e41783
BW		 6671static int
6672total_frag_text_expansion (fragS *fragP)
6673{
6674 int slot;
6675 int total_expansion = 0;
6676
6677 for (slot = 0; slot < MAX_SLOTS; slot++)
6678 total_expansion += fragP->tc_frag_data.text_expansion[slot];
6679
6680 return total_expansion;
6681}
6682
6683
43cd72b9
BW		 6684/* Emit a vliw instruction to the current fragment. */
6685
7fa3d080
BW		 6686static void
6687xg_assemble_vliw_tokens (vliw_insn *vinsn)
43cd72b9 6688{
e7da6241 6689 bfd_boolean finish_frag;
43cd72b9
BW		 6690 bfd_boolean is_jump = FALSE;
6691 bfd_boolean is_branch = FALSE;
6692 xtensa_isa isa = xtensa_default_isa;
6693 int i;
6694 int insn_size;
6695 int extra_space;
6696 char *f = NULL;
6697 int slot;
7c430684
BW		 6698 unsigned current_line, best_linenum;
6699 char *current_file;
43cd72b9 6700
7c430684 6701 best_linenum = UINT_MAX;
43cd72b9
BW		 6702
6703 if (generating_literals)
6704 {
6705 static int reported = 0;
6706 if (reported < 4)
6707 as_bad_where (frag_now->fr_file, frag_now->fr_line,
6708 _("cannot assemble into a literal fragment"));
6709 if (reported == 3)
6710 as_bad (_("..."));
6711 reported++;
6712 return;
6713 }
6714
6715 if (frag_now_fix () != 0
b08b5071 6716 && (! frag_now->tc_frag_data.is_insn
43cd72b9 6717 || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
b08b5071 6718 || !use_transform () != frag_now->tc_frag_data.is_no_transform
7c834684
BW		 6719 || (directive_state[directive_longcalls]
6720 != frag_now->tc_frag_data.use_longcalls)
43cd72b9
BW		 6721 || (directive_state[directive_absolute_literals]
6722 != frag_now->tc_frag_data.use_absolute_literals)))
6723 {
6724 frag_wane (frag_now);
6725 frag_new (0);
6726 xtensa_set_frag_assembly_state (frag_now);
6727 }
6728
6729 if (workaround_a0_b_retw
6730 && vinsn->num_slots == 1
6731 && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
6732 && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
6733 && use_transform ())
6734 {
6735 has_a0_b_retw = TRUE;
6736
6737 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6738 After the first assembly pass we will check all of them and
6739 add a nop if needed. */
6740 frag_now->tc_frag_data.is_insn = TRUE;
6741 frag_var (rs_machine_dependent, 4, 4,
6742 RELAX_ADD_NOP_IF_A0_B_RETW,
6743 frag_now->fr_symbol,
6744 frag_now->fr_offset,
6745 NULL);
6746 xtensa_set_frag_assembly_state (frag_now);
6747 frag_now->tc_frag_data.is_insn = TRUE;
6748 frag_var (rs_machine_dependent, 4, 4,
6749 RELAX_ADD_NOP_IF_A0_B_RETW,
6750 frag_now->fr_symbol,
6751 frag_now->fr_offset,
6752 NULL);
6753 xtensa_set_frag_assembly_state (frag_now);
6754 }
6755
6756 for (i = 0; i < vinsn->num_slots; i++)
6757 {
6758 /* See if the instruction implies an aligned section. */
6759 if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1)
6760 record_alignment (now_seg, 2);
c138bc38 6761
43cd72b9 6762 /* Also determine the best line number for debug info. */
7c430684
BW		 6763 best_linenum = vinsn->slots[i].linenum < best_linenum
6764 ? vinsn->slots[i].linenum : best_linenum;
43cd72b9
BW		 6765 }
6766
6767 /* Special cases for instructions that force an alignment... */
6768 /* None of these opcodes are bundle-able. */
6769 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
6770 {
d77b99c9 6771 int max_fill;
c138bc38 6772
05d58145
BW		 6773 /* Remember the symbol that marks the end of the loop in the frag
6774 that marks the start of the loop. This way we can easily find
6775 the end of the loop at the beginning, without adding special code
6776 to mark the loop instructions themselves. */
6777 symbolS *target_sym = NULL;
6778 if (vinsn->slots[0].tok[1].X_op == O_symbol)
6779 target_sym = vinsn->slots[0].tok[1].X_add_symbol;
6780
43cd72b9
BW		 6781 xtensa_set_frag_assembly_state (frag_now);
6782 frag_now->tc_frag_data.is_insn = TRUE;
c138bc38 6783
43cd72b9
BW		 6784 max_fill = get_text_align_max_fill_size
6785 (get_text_align_power (xtensa_fetch_width),
6786 TRUE, frag_now->tc_frag_data.is_no_density);
6787
6788 if (use_transform ())
6789 frag_var (rs_machine_dependent, max_fill, max_fill,
05d58145 6790 RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
43cd72b9 6791 else
c138bc38 6792 frag_var (rs_machine_dependent, 0, 0,
05d58145 6793 RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
43cd72b9 6794 xtensa_set_frag_assembly_state (frag_now);
43cd72b9
BW		 6795 }
6796
b08b5071 6797 if (vinsn->slots[0].opcode == xtensa_entry_opcode
43cd72b9
BW		 6798 && !vinsn->slots[0].is_specific_opcode)
6799 {
6800 xtensa_mark_literal_pool_location ();
c3ea6048 6801 xtensa_move_labels (frag_now, 0);
43cd72b9
BW		 6802 frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
6803 }
6804
6805 if (vinsn->num_slots == 1)
6806 {
6807 if (workaround_a0_b_retw && use_transform ())
6808 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
6809 is_register_writer (&vinsn->slots[0], "a", 0));
6810
6811 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
6812 is_bad_loopend_opcode (&vinsn->slots[0]));
6813 }
6814 else
6815 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
6816
6817 insn_size = xtensa_format_length (isa, vinsn->format);
6818
e7da6241 6819 extra_space = relaxation_requirements (vinsn, &finish_frag);
43cd72b9
BW		 6820
6821 /* vinsn_to_insnbuf will produce the error. */
6822 if (vinsn->format != XTENSA_UNDEFINED)
6823 {
d77b99c9 6824 f = frag_more (insn_size + extra_space);
43cd72b9
BW		 6825 xtensa_set_frag_assembly_state (frag_now);
6826 frag_now->tc_frag_data.is_insn = TRUE;
6827 }
6828
e7da6241 6829 vinsn_to_insnbuf (vinsn, f, frag_now, FALSE);
43cd72b9
BW		 6830 if (vinsn->format == XTENSA_UNDEFINED)
6831 return;
6832
d77b99c9 6833 xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0);
c138bc38 6834
7c430684
BW		 6835 /* Temporarily set the logical line number to the one we want to appear
6836 in the debug information. */
6837 as_where (&current_file, &current_line);
6838 new_logical_line (current_file, best_linenum);
6839 dwarf2_emit_insn (insn_size + extra_space);
6840 new_logical_line (current_file, current_line);
43cd72b9
BW		 6841
6842 for (slot = 0; slot < vinsn->num_slots; slot++)
6843 {
6844 TInsn *tinsn = &vinsn->slots[slot];
6845 frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
7c834684 6846 frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol;
7c834684 6847 frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset;
43cd72b9
BW		 6848 frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
6849 if (tinsn->literal_space != 0)
6850 xg_assemble_literal_space (tinsn->literal_space, slot);
6851
6852 if (tinsn->subtype == RELAX_NARROW)
6853 assert (vinsn->num_slots == 1);
6854 if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
6855 is_jump = TRUE;
6856 if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
6857 is_branch = TRUE;
6858
e7da6241
BW		 6859 if (tinsn->subtype || tinsn->symbol || tinsn->offset
6860 || tinsn->literal_frag || is_jump || is_branch)
43cd72b9
BW		 6861 finish_frag = TRUE;
6862 }
6863
6864 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
b08b5071 6865 frag_now->tc_frag_data.is_specific_opcode = TRUE;
43cd72b9
BW		 6866
6867 if (finish_frag)
6868 {
6869 frag_variant (rs_machine_dependent,
6870 extra_space, extra_space, RELAX_SLOTS,
6871 frag_now->fr_symbol, frag_now->fr_offset, f);
6872 xtensa_set_frag_assembly_state (frag_now);
6873 }
6874
6875 /* Special cases for loops:
6876 close_loop_end should be inserted AFTER short_loop.
6877 Make sure that CLOSE loops are processed BEFORE short_loops
6878 when converting them. */
6879
6880 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
64b607e6 6881 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1
43cd72b9
BW		 6882 && !vinsn->slots[0].is_specific_opcode)
6883 {
6884 if (workaround_short_loop && use_transform ())
6885 {
6886 maybe_has_short_loop = TRUE;
6887 frag_now->tc_frag_data.is_insn = TRUE;
6888 frag_var (rs_machine_dependent, 4, 4,
6889 RELAX_ADD_NOP_IF_SHORT_LOOP,
6890 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6891 frag_now->tc_frag_data.is_insn = TRUE;
6892 frag_var (rs_machine_dependent, 4, 4,
6893 RELAX_ADD_NOP_IF_SHORT_LOOP,
6894 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6895 }
6896
6897 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6898 loop at least 12 bytes away from another loop's end. */
6899 if (workaround_close_loop_end && use_transform ())
6900 {
6901 maybe_has_close_loop_end = TRUE;
6902 frag_now->tc_frag_data.is_insn = TRUE;
6903 frag_var (rs_machine_dependent, 12, 12,
6904 RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
6905 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6906 }
6907 }
6908
6909 if (use_transform ())
6910 {
6911 if (is_jump)
6912 {
6913 assert (finish_frag);
6914 frag_var (rs_machine_dependent,
6915 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
6916 RELAX_UNREACHABLE,
6917 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6918 xtensa_set_frag_assembly_state (frag_now);
6919 }
7b1cc377 6920 else if (is_branch && do_align_targets ())
43cd72b9
BW		 6921 {
6922 assert (finish_frag);
6923 frag_var (rs_machine_dependent,
6924 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
6925 RELAX_MAYBE_UNREACHABLE,
6926 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6927 xtensa_set_frag_assembly_state (frag_now);
6928 frag_var (rs_machine_dependent,
6929 0, 0,
6930 RELAX_MAYBE_DESIRE_ALIGN,
6931 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6932 xtensa_set_frag_assembly_state (frag_now);
6933 }
6934 }
6935
6936 /* Now, if the original opcode was a call... */
6937 if (do_align_targets ()
6938 && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
6939 {
b08b5071 6940 float freq = get_subseg_total_freq (now_seg, now_subseg);
43cd72b9
BW		 6941 frag_now->tc_frag_data.is_insn = TRUE;
6942 frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
6943 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6944 xtensa_set_frag_assembly_state (frag_now);
6945 }
6946
6947 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
6948 {
6949 frag_wane (frag_now);
6950 frag_new (0);
6951 xtensa_set_frag_assembly_state (frag_now);
6952 }
6953}
6954
6955\f
7fa3d080
BW		 6956/* xtensa_end and helper functions. */
6957
6958static void xtensa_cleanup_align_frags (void);
6959static void xtensa_fix_target_frags (void);
6960static void xtensa_mark_narrow_branches (void);
6961static void xtensa_mark_zcl_first_insns (void);
6a7eedfe 6962static void xtensa_mark_difference_of_two_symbols (void);
7fa3d080
BW		 6963static void xtensa_fix_a0_b_retw_frags (void);
6964static void xtensa_fix_b_j_loop_end_frags (void);
6965static void xtensa_fix_close_loop_end_frags (void);
6966static void xtensa_fix_short_loop_frags (void);
6967static void xtensa_sanity_check (void);
2caa7ca0 6968static void xtensa_add_config_info (void);
7fa3d080 6969
43cd72b9 6970void
7fa3d080 6971xtensa_end (void)
43cd72b9
BW		 6972{
6973 directive_balance ();
6974 xtensa_flush_pending_output ();
6975
6976 past_xtensa_end = TRUE;
6977
6978 xtensa_move_literals ();
6979
6980 xtensa_reorder_segments ();
6981 xtensa_cleanup_align_frags ();
6982 xtensa_fix_target_frags ();
6983 if (workaround_a0_b_retw && has_a0_b_retw)
6984 xtensa_fix_a0_b_retw_frags ();
6985 if (workaround_b_j_loop_end)
6986 xtensa_fix_b_j_loop_end_frags ();
6987
6988 /* "close_loop_end" should be processed BEFORE "short_loop". */
6989 if (workaround_close_loop_end && maybe_has_close_loop_end)
6990 xtensa_fix_close_loop_end_frags ();
6991
6992 if (workaround_short_loop && maybe_has_short_loop)
6993 xtensa_fix_short_loop_frags ();
03aaa593
BW		 6994 if (align_targets)
6995 xtensa_mark_narrow_branches ();
43cd72b9
BW		 6996 xtensa_mark_zcl_first_insns ();
6997
6998 xtensa_sanity_check ();
2caa7ca0
BW		 6999
7000 xtensa_add_config_info ();
43cd72b9
BW		 7001}
7002
7003
7004static void
7fa3d080 7005xtensa_cleanup_align_frags (void)
43cd72b9
BW		 7006{
7007 frchainS *frchP;
c9049d30 7008 asection *s;
43cd72b9 7009
c9049d30
AM		 7010 for (s = stdoutput->sections; s; s = s->next)
7011 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7012 {
7013 fragS *fragP;
7014 /* Walk over all of the fragments in a subsection. */
7015 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7016 {
7017 if ((fragP->fr_type == rs_align
7018 || fragP->fr_type == rs_align_code
7019 || (fragP->fr_type == rs_machine_dependent
7020 && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
7021 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
7022 && fragP->fr_fix == 0)
7023 {
7024 fragS *next = fragP->fr_next;
7025
7026 while (next
7027 && next->fr_fix == 0
7028 && next->fr_type == rs_machine_dependent
7029 && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7030 {
7031 frag_wane (next);
7032 next = next->fr_next;
7033 }
7034 }
7035 /* If we don't widen branch targets, then they
7036 will be easier to align. */
7037 if (fragP->tc_frag_data.is_branch_target
7038 && fragP->fr_opcode == fragP->fr_literal
7039 && fragP->fr_type == rs_machine_dependent
7040 && fragP->fr_subtype == RELAX_SLOTS
7041 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
7042 frag_wane (fragP);
7043 if (fragP->fr_type == rs_machine_dependent
7044 && fragP->fr_subtype == RELAX_UNREACHABLE)
7045 fragP->tc_frag_data.is_unreachable = TRUE;
7046 }
7047 }
43cd72b9
BW		 7048}
7049
7050
7051/* Re-process all of the fragments looking to convert all of the
7052 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7053 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7b1cc377 7054 Otherwise, convert to a .fill 0. */
7fa3d080 7055
43cd72b9 7056static void
7fa3d080 7057xtensa_fix_target_frags (void)
e0001a05
NC		 7058{
7059 frchainS *frchP;
c9049d30 7060 asection *s;
e0001a05
NC		 7061
7062 /* When this routine is called, all of the subsections are still intact
7063 so we walk over subsections instead of sections. */
c9049d30
AM		 7064 for (s = stdoutput->sections; s; s = s->next)
7065 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7066 {
7067 fragS *fragP;
e0001a05 7068
c9049d30
AM		 7069 /* Walk over all of the fragments in a subsection. */
7070 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7071 {
7072 if (fragP->fr_type == rs_machine_dependent
7073 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7074 {
7075 if (next_frag_is_branch_target (fragP))
7076 fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7077 else
7078 frag_wane (fragP);
7079 }
7080 }
7081 }
e0001a05
NC		 7082}
7083
7084
7fa3d080
BW		 7085static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
7086
43cd72b9 7087static void
7fa3d080 7088xtensa_mark_narrow_branches (void)
43cd72b9
BW		 7089{
7090 frchainS *frchP;
c9049d30 7091 asection *s;
43cd72b9 7092
c9049d30
AM		 7093 for (s = stdoutput->sections; s; s = s->next)
7094 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7095 {
7096 fragS *fragP;
7097 /* Walk over all of the fragments in a subsection. */
7098 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7099 {
7100 if (fragP->fr_type == rs_machine_dependent
7101 && fragP->fr_subtype == RELAX_SLOTS
7102 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
7103 {
7104 vliw_insn vinsn;
7105
7106 vinsn_from_chars (&vinsn, fragP->fr_opcode);
7107 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
7108
7109 if (vinsn.num_slots == 1
7110 && xtensa_opcode_is_branch (xtensa_default_isa,
64b607e6 7111 vinsn.slots[0].opcode) == 1
c9049d30
AM		 7112 && xg_get_single_size (vinsn.slots[0].opcode) == 2
7113 && is_narrow_branch_guaranteed_in_range (fragP,
7114 &vinsn.slots[0]))
7115 {
7116 fragP->fr_subtype = RELAX_SLOTS;
7117 fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
7118 fragP->tc_frag_data.is_aligning_branch = 1;
7119 }
7120 }
7121 }
7122 }
43cd72b9
BW		 7123}
7124
7125
7126/* A branch is typically widened only when its target is out of
7127 range. However, we would like to widen them to align a subsequent
7128 branch target when possible.
7129
7130 Because the branch relaxation code is so convoluted, the optimal solution
7131 (combining the two cases) is difficult to get right in all circumstances.
7132 We therefore go with an "almost as good" solution, where we only
7133 use for alignment narrow branches that definitely will not expand to a
7134 jump and a branch. These functions find and mark these cases. */
7135
a67517f4
BW		 7136/* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7137 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7138 We start counting beginning with the frag after the 2-byte branch, so the
7139 maximum offset is (4 - 2) + 63 = 65. */
7140#define MAX_IMMED6 65
43cd72b9 7141
d77b99c9 7142static offsetT unrelaxed_frag_max_size (fragS *);
7fa3d080 7143
43cd72b9 7144static bfd_boolean
7fa3d080 7145is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn)
43cd72b9
BW		 7146{
7147 const expressionS *expr = &tinsn->tok[1];
7148 symbolS *symbolP = expr->X_add_symbol;
d77b99c9 7149 offsetT max_distance = expr->X_add_number;
e7da6241
BW		 7150 fragS *target_frag;
7151
7152 if (expr->X_op != O_symbol)
7153 return FALSE;
7154
7155 target_frag = symbol_get_frag (symbolP);
7156
43cd72b9
BW		 7157 max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
7158 if (is_branch_jmp_to_next (tinsn, fragP))
7159 return FALSE;
7160
7161 /* The branch doesn't branch over it's own frag,
7162 but over the subsequent ones. */
7163 fragP = fragP->fr_next;
7164 while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6)
7165 {
7166 max_distance += unrelaxed_frag_max_size (fragP);
7167 fragP = fragP->fr_next;
7168 }
7169 if (max_distance <= MAX_IMMED6 && fragP == target_frag)
7170 return TRUE;
e0001a05
NC		 7171 return FALSE;
7172}
7173
7174
43cd72b9 7175static void
7fa3d080 7176xtensa_mark_zcl_first_insns (void)
43cd72b9
BW		 7177{
7178 frchainS *frchP;
c9049d30 7179 asection *s;
43cd72b9 7180
c9049d30
AM		 7181 for (s = stdoutput->sections; s; s = s->next)
7182 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7183 {
7184 fragS *fragP;
7185 /* Walk over all of the fragments in a subsection. */
7186 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7187 {
7188 if (fragP->fr_type == rs_machine_dependent
7189 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
7190 || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
7191 {
7192 /* Find the loop frag. */
7193 fragS *targ_frag = next_non_empty_frag (fragP);
7194 /* Find the first insn frag. */
7195 targ_frag = next_non_empty_frag (targ_frag);
7196
7197 /* Of course, sometimes (mostly for toy test cases) a
7198 zero-cost loop instruction is the last in a section. */
7199 if (targ_frag)
7200 {
7201 targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
7202 /* Do not widen a frag that is the first instruction of a
7203 zero-cost loop. It makes that loop harder to align. */
7204 if (targ_frag->fr_type == rs_machine_dependent
7205 && targ_frag->fr_subtype == RELAX_SLOTS
7206 && (targ_frag->tc_frag_data.slot_subtypes[0]
7207 == RELAX_NARROW))
7208 {
7209 if (targ_frag->tc_frag_data.is_aligning_branch)
7210 targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
7211 else
7212 {
7213 frag_wane (targ_frag);
7214 targ_frag->tc_frag_data.slot_subtypes[0] = 0;
7215 }
7216 }
7217 }
7218 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
7219 frag_wane (fragP);
7220 }
7221 }
7222 }
43cd72b9
BW		 7223}
7224
7225
6a7eedfe
BW		 7226/* Some difference-of-symbols expressions make it out to the linker. Some
7227 don't. If one does, then the linker can optimize between the two labels.
7228 If it doesn't, then the linker shouldn't. */
7229
7230static void
7231xtensa_mark_difference_of_two_symbols (void)
7232{
7233 symbolS *expr_sym;
7234
7235 for (expr_sym = expr_symbols; expr_sym;
7236 expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol)
7237 {
7238 expressionS *expr = symbol_get_value_expression (expr_sym);
7239
7240 if (expr->X_op == O_subtract)
7241 {
7242 symbolS *left = expr->X_add_symbol;
7243 symbolS *right = expr->X_op_symbol;
7244
7245 /* Difference of two symbols not in the same section
7246 are handled with relocations in the linker. */
7247 if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right))
7248 {
7249 fragS *start;
7250 fragS *end;
7251
7252 if (symbol_get_frag (left)->fr_address
7253 <= symbol_get_frag (right)->fr_address)
7254 {
7255 start = symbol_get_frag (left);
7256 end = symbol_get_frag (right);
7257 }
7258 else
7259 {
7260 start = symbol_get_frag (right);
7261 end = symbol_get_frag (left);
7262 }
7263 do
7264 {
7265 start->tc_frag_data.is_no_transform = 1;
7266 start = start->fr_next;
7267 }
7268 while (start && start->fr_address < end->fr_address);
7269 }
7270 }
7271 }
7272}
7273
7274
e0001a05
NC		 7275/* Re-process all of the fragments looking to convert all of the
7276 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7277 conditional branch or a retw/retw.n, convert this frag to one that
7278 will generate a NOP. In any case close it off with a .fill 0. */
7279
7fa3d080
BW		 7280static bfd_boolean next_instrs_are_b_retw (fragS *);
7281
e0001a05 7282static void
7fa3d080 7283xtensa_fix_a0_b_retw_frags (void)
e0001a05
NC		 7284{
7285 frchainS *frchP;
c9049d30 7286 asection *s;
e0001a05
NC		 7287
7288 /* When this routine is called, all of the subsections are still intact
7289 so we walk over subsections instead of sections. */
c9049d30
AM		 7290 for (s = stdoutput->sections; s; s = s->next)
7291 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7292 {
7293 fragS *fragP;
e0001a05 7294
c9049d30
AM		 7295 /* Walk over all of the fragments in a subsection. */
7296 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7297 {
7298 if (fragP->fr_type == rs_machine_dependent
7299 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
7300 {
7301 if (next_instrs_are_b_retw (fragP))
7302 {
7303 if (fragP->tc_frag_data.is_no_transform)
7304 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7305 else
7306 relax_frag_add_nop (fragP);
7307 }
7308 frag_wane (fragP);
7309 }
7310 }
7311 }
e0001a05
NC		 7312}
7313
7314
7fa3d080
BW		 7315static bfd_boolean
7316next_instrs_are_b_retw (fragS *fragP)
e0001a05
NC		 7317{
7318 xtensa_opcode opcode;
43cd72b9 7319 xtensa_format fmt;
e0001a05
NC		 7320 const fragS *next_fragP = next_non_empty_frag (fragP);
7321 static xtensa_insnbuf insnbuf = NULL;
43cd72b9 7322 static xtensa_insnbuf slotbuf = NULL;
e0001a05
NC		 7323 xtensa_isa isa = xtensa_default_isa;
7324 int offset = 0;
43cd72b9
BW		 7325 int slot;
7326 bfd_boolean branch_seen = FALSE;
e0001a05
NC		 7327
7328 if (!insnbuf)
43cd72b9
BW		 7329 {
7330 insnbuf = xtensa_insnbuf_alloc (isa);
7331 slotbuf = xtensa_insnbuf_alloc (isa);
7332 }
e0001a05
NC		 7333
7334 if (next_fragP == NULL)
7335 return FALSE;
7336
7337 /* Check for the conditional branch. */
d77b99c9
BW		 7338 xtensa_insnbuf_from_chars
7339 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
43cd72b9
BW		 7340 fmt = xtensa_format_decode (isa, insnbuf);
7341 if (fmt == XTENSA_UNDEFINED)
7342 return FALSE;
7343
7344 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
7345 {
7346 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
7347 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
7348
7349 branch_seen = (branch_seen
7350 || xtensa_opcode_is_branch (isa, opcode) == 1);
7351 }
e0001a05 7352
43cd72b9 7353 if (!branch_seen)
e0001a05
NC		 7354 return FALSE;
7355
43cd72b9 7356 offset += xtensa_format_length (isa, fmt);
e0001a05
NC		 7357 if (offset == next_fragP->fr_fix)
7358 {
7359 next_fragP = next_non_empty_frag (next_fragP);
7360 offset = 0;
7361 }
43cd72b9 7362
e0001a05
NC		 7363 if (next_fragP == NULL)
7364 return FALSE;
7365
7366 /* Check for the retw/retw.n. */
d77b99c9
BW		 7367 xtensa_insnbuf_from_chars
7368 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
43cd72b9
BW		 7369 fmt = xtensa_format_decode (isa, insnbuf);
7370
7371 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7372 have no problems. */
7373 if (fmt == XTENSA_UNDEFINED
7374 || xtensa_format_num_slots (isa, fmt) != 1)
7375 return FALSE;
7376
7377 xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
7378 opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
e0001a05 7379
b08b5071 7380 if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode)
e0001a05 7381 return TRUE;
43cd72b9 7382
e0001a05
NC		 7383 return FALSE;
7384}
7385
7386
7387/* Re-process all of the fragments looking to convert all of the
7388 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7389 loop end label, convert this frag to one that will generate a NOP.
7390 In any case close it off with a .fill 0. */
7391
7fa3d080
BW		 7392static bfd_boolean next_instr_is_loop_end (fragS *);
7393
e0001a05 7394static void
7fa3d080 7395xtensa_fix_b_j_loop_end_frags (void)
e0001a05
NC		 7396{
7397 frchainS *frchP;
c9049d30 7398 asection *s;
e0001a05
NC		 7399
7400 /* When this routine is called, all of the subsections are still intact
7401 so we walk over subsections instead of sections. */
c9049d30
AM		 7402 for (s = stdoutput->sections; s; s = s->next)
7403 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7404 {
7405 fragS *fragP;
e0001a05 7406
c9049d30
AM		 7407 /* Walk over all of the fragments in a subsection. */
7408 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7409 {
7410 if (fragP->fr_type == rs_machine_dependent
7411 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
7412 {
7413 if (next_instr_is_loop_end (fragP))
7414 {
7415 if (fragP->tc_frag_data.is_no_transform)
7416 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7417 else
7418 relax_frag_add_nop (fragP);
7419 }
7420 frag_wane (fragP);
7421 }
7422 }
7423 }
e0001a05
NC		 7424}
7425
7426
7fa3d080
BW		 7427static bfd_boolean
7428next_instr_is_loop_end (fragS *fragP)
e0001a05
NC		 7429{
7430 const fragS *next_fragP;
7431
7432 if (next_frag_is_loop_target (fragP))
7433 return FALSE;
7434
7435 next_fragP = next_non_empty_frag (fragP);
7436 if (next_fragP == NULL)
7437 return FALSE;
7438
7439 if (!next_frag_is_loop_target (next_fragP))
7440 return FALSE;
7441
7442 /* If the size is >= 3 then there is more than one instruction here.
7443 The hardware bug will not fire. */
7444 if (next_fragP->fr_fix > 3)
7445 return FALSE;
7446
7447 return TRUE;
7448}
7449
7450
7451/* Re-process all of the fragments looking to convert all of the
7452 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7453 not MY loop's loop end within 12 bytes, add enough nops here to
7454 make it at least 12 bytes away. In any case close it off with a
7455 .fill 0. */
7456
d77b99c9 7457static offsetT min_bytes_to_other_loop_end
05d58145 7458 (fragS *, fragS *, offsetT);
7fa3d080 7459
e0001a05 7460static void
7fa3d080 7461xtensa_fix_close_loop_end_frags (void)
e0001a05
NC		 7462{
7463 frchainS *frchP;
c9049d30 7464 asection *s;
e0001a05
NC		 7465
7466 /* When this routine is called, all of the subsections are still intact
7467 so we walk over subsections instead of sections. */
c9049d30
AM		 7468 for (s = stdoutput->sections; s; s = s->next)
7469 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7470 {
7471 fragS *fragP;
e0001a05 7472
c9049d30 7473 fragS *current_target = NULL;
e0001a05 7474
c9049d30
AM		 7475 /* Walk over all of the fragments in a subsection. */
7476 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7477 {
7478 if (fragP->fr_type == rs_machine_dependent
7479 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
7480 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
05d58145 7481 current_target = symbol_get_frag (fragP->fr_symbol);
e0001a05 7482
c9049d30
AM		 7483 if (current_target
7484 && fragP->fr_type == rs_machine_dependent
7485 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
7486 {
7487 offsetT min_bytes;
7488 int bytes_added = 0;
e0001a05
NC		 7489
7490#define REQUIRED_LOOP_DIVIDING_BYTES 12
c9049d30
AM		 7491 /* Max out at 12. */
7492 min_bytes = min_bytes_to_other_loop_end
7493 (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES);
7494
7495 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
7496 {
7497 if (fragP->tc_frag_data.is_no_transform)
7498 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7499 else
7500 {
7501 while (min_bytes + bytes_added
7502 < REQUIRED_LOOP_DIVIDING_BYTES)
7503 {
7504 int length = 3;
7505
7506 if (fragP->fr_var < length)
7507 as_fatal (_("fr_var %lu < length %d"),
7508 (long) fragP->fr_var, length);
7509 else
7510 {
7511 assemble_nop (length,
7512 fragP->fr_literal + fragP->fr_fix);
7513 fragP->fr_fix += length;
7514 fragP->fr_var -= length;
7515 }
7516 bytes_added += length;
7517 }
7518 }
7519 }
7520 frag_wane (fragP);
7521 }
7522 assert (fragP->fr_type != rs_machine_dependent
7523 || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
7524 }
7525 }
e0001a05
NC		 7526}
7527
7528
d77b99c9 7529static offsetT unrelaxed_frag_min_size (fragS *);
7fa3d080 7530
d77b99c9 7531static offsetT
7fa3d080
BW		 7532min_bytes_to_other_loop_end (fragS *fragP,
7533 fragS *current_target,
d77b99c9 7534 offsetT max_size)
e0001a05 7535{
d77b99c9 7536 offsetT offset = 0;
e0001a05
NC		 7537 fragS *current_fragP;
7538
7539 for (current_fragP = fragP;
7540 current_fragP;
7541 current_fragP = current_fragP->fr_next)
7542 {
7543 if (current_fragP->tc_frag_data.is_loop_target
7544 && current_fragP != current_target)
05d58145 7545 return offset;
e0001a05
NC		 7546
7547 offset += unrelaxed_frag_min_size (current_fragP);
7548
05d58145 7549 if (offset >= max_size)
e0001a05
NC		 7550 return max_size;
7551 }
7552 return max_size;
7553}
7554
7555
d77b99c9 7556static offsetT
7fa3d080 7557unrelaxed_frag_min_size (fragS *fragP)
e0001a05 7558{
d77b99c9 7559 offsetT size = fragP->fr_fix;
e0001a05 7560
d77b99c9 7561 /* Add fill size. */
e0001a05
NC		 7562 if (fragP->fr_type == rs_fill)
7563 size += fragP->fr_offset;
7564
7565 return size;
7566}
7567
7568
d77b99c9 7569static offsetT
7fa3d080 7570unrelaxed_frag_max_size (fragS *fragP)
43cd72b9 7571{
d77b99c9 7572 offsetT size = fragP->fr_fix;
43cd72b9
BW		 7573 switch (fragP->fr_type)
7574 {
7575 case 0:
c138bc38 7576 /* Empty frags created by the obstack allocation scheme
43cd72b9
BW		 7577 end up with type 0. */
7578 break;
7579 case rs_fill:
7580 case rs_org:
7581 case rs_space:
7582 size += fragP->fr_offset;
7583 break;
7584 case rs_align:
7585 case rs_align_code:
7586 case rs_align_test:
7587 case rs_leb128:
7588 case rs_cfa:
7589 case rs_dwarf2dbg:
7590 /* No further adjustments needed. */
7591 break;
7592 case rs_machine_dependent:
7593 if (fragP->fr_subtype != RELAX_DESIRE_ALIGN)
7594 size += fragP->fr_var;
7595 break;
7596 default:
7597 /* We had darn well better know how big it is. */
7598 assert (0);
7599 break;
7600 }
7601
7602 return size;
7603}
7604
7605
e0001a05
NC		 7606/* Re-process all of the fragments looking to convert all
7607 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7608
7609 A)
7610 1) the instruction size count to the loop end label
7611 is too short (<= 2 instructions),
7612 2) loop has a jump or branch in it
7613
7614 or B)
43cd72b9 7615 1) workaround_all_short_loops is TRUE
e0001a05
NC		 7616 2) The generating loop was a 'loopgtz' or 'loopnez'
7617 3) the instruction size count to the loop end label is too short
7618 (<= 2 instructions)
7619 then convert this frag (and maybe the next one) to generate a NOP.
7620 In any case close it off with a .fill 0. */
7621
d77b99c9 7622static int count_insns_to_loop_end (fragS *, bfd_boolean, int);
7fa3d080
BW		 7623static bfd_boolean branch_before_loop_end (fragS *);
7624
e0001a05 7625static void
7fa3d080 7626xtensa_fix_short_loop_frags (void)
e0001a05
NC		 7627{
7628 frchainS *frchP;
c9049d30 7629 asection *s;
e0001a05
NC		 7630
7631 /* When this routine is called, all of the subsections are still intact
7632 so we walk over subsections instead of sections. */
c9049d30
AM		 7633 for (s = stdoutput->sections; s; s = s->next)
7634 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7635 {
7636 fragS *fragP;
7637 fragS *current_target = NULL;
7638 xtensa_opcode current_opcode = XTENSA_UNDEFINED;
e0001a05 7639
c9049d30
AM		 7640 /* Walk over all of the fragments in a subsection. */
7641 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7642 {
7643 if (fragP->fr_type == rs_machine_dependent
7644 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
7645 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
7646 {
7647 TInsn t_insn;
7648 fragS *loop_frag = next_non_empty_frag (fragP);
7649 tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0);
7650 current_target = symbol_get_frag (fragP->fr_symbol);
7651 current_opcode = t_insn.opcode;
7652 assert (xtensa_opcode_is_loop (xtensa_default_isa,
64b607e6 7653 current_opcode) == 1);
c9049d30 7654 }
e0001a05 7655
c9049d30
AM		 7656 if (fragP->fr_type == rs_machine_dependent
7657 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7658 {
7659 if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3
7660 && (branch_before_loop_end (fragP->fr_next)
7661 || (workaround_all_short_loops
7662 && current_opcode != XTENSA_UNDEFINED
7663 && current_opcode != xtensa_loop_opcode)))
7664 {
7665 if (fragP->tc_frag_data.is_no_transform)
7666 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7667 else
7668 relax_frag_add_nop (fragP);
7669 }
7670 frag_wane (fragP);
7671 }
7672 }
7673 }
e0001a05
NC		 7674}
7675
7676
d77b99c9 7677static int unrelaxed_frag_min_insn_count (fragS *);
7fa3d080 7678
d77b99c9 7679static int
7fa3d080
BW		 7680count_insns_to_loop_end (fragS *base_fragP,
7681 bfd_boolean count_relax_add,
d77b99c9 7682 int max_count)
e0001a05
NC		 7683{
7684 fragS *fragP = NULL;
d77b99c9 7685 int insn_count = 0;
e0001a05
NC		 7686
7687 fragP = base_fragP;
7688
7689 for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next)
7690 {
7691 insn_count += unrelaxed_frag_min_insn_count (fragP);
7692 if (insn_count >= max_count)
7693 return max_count;
7694
7695 if (count_relax_add)
7696 {
7697 if (fragP->fr_type == rs_machine_dependent
7698 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7699 {
7700 /* In order to add the appropriate number of
7701 NOPs, we count an instruction for downstream
7702 occurrences. */
7703 insn_count++;
7704 if (insn_count >= max_count)
7705 return max_count;
7706 }
7707 }
7708 }
7709 return insn_count;
7710}
7711
7712
d77b99c9 7713static int
7fa3d080 7714unrelaxed_frag_min_insn_count (fragS *fragP)
e0001a05 7715{
43cd72b9
BW		 7716 xtensa_isa isa = xtensa_default_isa;
7717 static xtensa_insnbuf insnbuf = NULL;
d77b99c9 7718 int insn_count = 0;
e0001a05
NC		 7719 int offset = 0;
7720
7721 if (!fragP->tc_frag_data.is_insn)
7722 return insn_count;
7723
43cd72b9
BW		 7724 if (!insnbuf)
7725 insnbuf = xtensa_insnbuf_alloc (isa);
7726
e0001a05
NC		 7727 /* Decode the fixed instructions. */
7728 while (offset < fragP->fr_fix)
7729 {
43cd72b9
BW		 7730 xtensa_format fmt;
7731
d77b99c9
BW		 7732 xtensa_insnbuf_from_chars
7733 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
43cd72b9
BW		 7734 fmt = xtensa_format_decode (isa, insnbuf);
7735
7736 if (fmt == XTENSA_UNDEFINED)
e0001a05
NC		 7737 {
7738 as_fatal (_("undecodable instruction in instruction frag"));
7739 return insn_count;
7740 }
43cd72b9 7741 offset += xtensa_format_length (isa, fmt);
e0001a05
NC		 7742 insn_count++;
7743 }
7744
7745 return insn_count;
7746}
7747
7748
7fa3d080
BW		 7749static bfd_boolean unrelaxed_frag_has_b_j (fragS *);
7750
43cd72b9 7751static bfd_boolean
7fa3d080 7752branch_before_loop_end (fragS *base_fragP)
e0001a05
NC		 7753{
7754 fragS *fragP;
7755
7756 for (fragP = base_fragP;
7757 fragP && !fragP->tc_frag_data.is_loop_target;
7758 fragP = fragP->fr_next)
7759 {
7760 if (unrelaxed_frag_has_b_j (fragP))
7761 return TRUE;
7762 }
7763 return FALSE;
7764}
7765
7766
43cd72b9 7767static bfd_boolean
7fa3d080 7768unrelaxed_frag_has_b_j (fragS *fragP)
e0001a05 7769{
43cd72b9
BW		 7770 static xtensa_insnbuf insnbuf = NULL;
7771 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 7772 int offset = 0;
7773
7774 if (!fragP->tc_frag_data.is_insn)
7775 return FALSE;
7776
43cd72b9
BW		 7777 if (!insnbuf)
7778 insnbuf = xtensa_insnbuf_alloc (isa);
7779
e0001a05
NC		 7780 /* Decode the fixed instructions. */
7781 while (offset < fragP->fr_fix)
7782 {
43cd72b9
BW		 7783 xtensa_format fmt;
7784 int slot;
7785
d77b99c9
BW		 7786 xtensa_insnbuf_from_chars
7787 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
43cd72b9
BW		 7788 fmt = xtensa_format_decode (isa, insnbuf);
7789 if (fmt == XTENSA_UNDEFINED)
7790 return FALSE;
7791
7792 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
e0001a05 7793 {
43cd72b9
BW		 7794 xtensa_opcode opcode =
7795 get_opcode_from_buf (fragP->fr_literal + offset, slot);
7796 if (xtensa_opcode_is_branch (isa, opcode) == 1
7797 || xtensa_opcode_is_jump (isa, opcode) == 1)
7798 return TRUE;
e0001a05 7799 }
43cd72b9 7800 offset += xtensa_format_length (isa, fmt);
e0001a05
NC		 7801 }
7802 return FALSE;
7803}
7804
7805
7806/* Checks to be made after initial assembly but before relaxation. */
7807
7fa3d080
BW		 7808static bfd_boolean is_empty_loop (const TInsn *, fragS *);
7809static bfd_boolean is_local_forward_loop (const TInsn *, fragS *);
7810
e0001a05 7811static void
7fa3d080 7812xtensa_sanity_check (void)
e0001a05
NC		 7813{
7814 char *file_name;
d77b99c9 7815 unsigned line;
e0001a05 7816 frchainS *frchP;
c9049d30 7817 asection *s;
e0001a05
NC		 7818
7819 as_where (&file_name, &line);
c9049d30
AM		 7820 for (s = stdoutput->sections; s; s = s->next)
7821 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7822 {
7823 fragS *fragP;
e0001a05 7824
c9049d30
AM		 7825 /* Walk over all of the fragments in a subsection. */
7826 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7827 {
c9049d30 7828 if (fragP->fr_type == rs_machine_dependent
a7284bf1
BW		 7829 && fragP->fr_subtype == RELAX_SLOTS
7830 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
c9049d30
AM		 7831 {
7832 static xtensa_insnbuf insnbuf = NULL;
7833 TInsn t_insn;
7834
7835 if (fragP->fr_opcode != NULL)
7836 {
7837 if (!insnbuf)
7838 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
7839 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7840 tinsn_immed_from_frag (&t_insn, fragP, 0);
7841
7842 if (xtensa_opcode_is_loop (xtensa_default_isa,
7843 t_insn.opcode) == 1)
7844 {
7845 if (is_empty_loop (&t_insn, fragP))
7846 {
7847 new_logical_line (fragP->fr_file, fragP->fr_line);
7848 as_bad (_("invalid empty loop"));
7849 }
7850 if (!is_local_forward_loop (&t_insn, fragP))
7851 {
7852 new_logical_line (fragP->fr_file, fragP->fr_line);
7853 as_bad (_("loop target does not follow "
7854 "loop instruction in section"));
7855 }
7856 }
7857 }
7858 }
7859 }
7860 }
e0001a05
NC		 7861 new_logical_line (file_name, line);
7862}
7863
7864
7865#define LOOP_IMMED_OPN 1
7866
43cd72b9 7867/* Return TRUE if the loop target is the next non-zero fragment. */
e0001a05 7868
7fa3d080
BW		 7869static bfd_boolean
7870is_empty_loop (const TInsn *insn, fragS *fragP)
e0001a05
NC		 7871{
7872 const expressionS *expr;
7873 symbolS *symbolP;
7874 fragS *next_fragP;
7875
7876 if (insn->insn_type != ITYPE_INSN)
7877 return FALSE;
7878
43cd72b9 7879 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
e0001a05
NC		 7880 return FALSE;
7881
7882 if (insn->ntok <= LOOP_IMMED_OPN)
7883 return FALSE;
7884
7885 expr = &insn->tok[LOOP_IMMED_OPN];
7886
7887 if (expr->X_op != O_symbol)
7888 return FALSE;
7889
7890 symbolP = expr->X_add_symbol;
7891 if (!symbolP)
7892 return FALSE;
7893
7894 if (symbol_get_frag (symbolP) == NULL)
7895 return FALSE;
7896
7897 if (S_GET_VALUE (symbolP) != 0)
7898 return FALSE;
7899
7900 /* Walk through the zero-size fragments from this one. If we find
7901 the target fragment, then this is a zero-size loop. */
43cd72b9 7902
e0001a05
NC		 7903 for (next_fragP = fragP->fr_next;
7904 next_fragP != NULL;
7905 next_fragP = next_fragP->fr_next)
7906 {
7907 if (next_fragP == symbol_get_frag (symbolP))
7908 return TRUE;
7909 if (next_fragP->fr_fix != 0)
7910 return FALSE;
7911 }
7912 return FALSE;
7913}
7914
7915
7fa3d080
BW		 7916static bfd_boolean
7917is_local_forward_loop (const TInsn *insn, fragS *fragP)
e0001a05
NC		 7918{
7919 const expressionS *expr;
7920 symbolS *symbolP;
7921 fragS *next_fragP;
7922
7923 if (insn->insn_type != ITYPE_INSN)
7924 return FALSE;
7925
64b607e6 7926 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
e0001a05
NC		 7927 return FALSE;
7928
7929 if (insn->ntok <= LOOP_IMMED_OPN)
7930 return FALSE;
7931
7932 expr = &insn->tok[LOOP_IMMED_OPN];
7933
7934 if (expr->X_op != O_symbol)
7935 return FALSE;
7936
7937 symbolP = expr->X_add_symbol;
7938 if (!symbolP)
7939 return FALSE;
7940
7941 if (symbol_get_frag (symbolP) == NULL)
7942 return FALSE;
7943
7944 /* Walk through fragments until we find the target.
7945 If we do not find the target, then this is an invalid loop. */
43cd72b9 7946
e0001a05
NC		 7947 for (next_fragP = fragP->fr_next;
7948 next_fragP != NULL;
7949 next_fragP = next_fragP->fr_next)
43cd72b9
BW		 7950 {
7951 if (next_fragP == symbol_get_frag (symbolP))
7952 return TRUE;
7953 }
e0001a05
NC		 7954
7955 return FALSE;
7956}
7957
2caa7ca0
BW		 7958
7959#define XTINFO_NAME "Xtensa_Info"
7960#define XTINFO_NAMESZ 12
7961#define XTINFO_TYPE 1
7962
7963static void
7964xtensa_add_config_info (void)
7965{
7966 asection *info_sec;
7967 char *data, *p;
7968 int sz;
7969
7970 info_sec = subseg_new (".xtensa.info", 0);
7971 bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY);
7972
7973 data = xmalloc (100);
7974 sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
7975 XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI);
7976 sz = strlen (data) + 1;
7977
7978 /* Add enough null terminators to pad to a word boundary. */
7979 do
7980 data[sz++] = 0;
7981 while ((sz & 3) != 0);
7982
7983 /* Follow the standard note section layout:
7984 First write the length of the name string. */
7985 p = frag_more (4);
7986 md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4);
7987
7988 /* Next comes the length of the "descriptor", i.e., the actual data. */
7989 p = frag_more (4);
7990 md_number_to_chars (p, (valueT) sz, 4);
7991
7992 /* Write the note type. */
7993 p = frag_more (4);
7994 md_number_to_chars (p, (valueT) XTINFO_TYPE, 4);
7995
7996 /* Write the name field. */
7997 p = frag_more (XTINFO_NAMESZ);
7998 memcpy (p, XTINFO_NAME, XTINFO_NAMESZ);
7999
8000 /* Finally, write the descriptor. */
8001 p = frag_more (sz);
8002 memcpy (p, data, sz);
8003
8004 free (data);
8005}
8006
e0001a05
NC		 8007\f
8008/* Alignment Functions. */
8009
d77b99c9
BW		 8010static int
8011get_text_align_power (unsigned target_size)
e0001a05 8012{
03aaa593
BW		 8013 if (target_size <= 4)
8014 return 2;
8015 assert (target_size == 8);
8016 return 3;
e0001a05
NC		 8017}
8018
8019
d77b99c9 8020static int
7fa3d080
BW		 8021get_text_align_max_fill_size (int align_pow,
8022 bfd_boolean use_nops,
8023 bfd_boolean use_no_density)
e0001a05
NC		 8024{
8025 if (!use_nops)
8026 return (1 << align_pow);
8027 if (use_no_density)
8028 return 3 * (1 << align_pow);
8029
8030 return 1 + (1 << align_pow);
8031}
8032
8033
d77b99c9
BW		 8034/* Calculate the minimum bytes of fill needed at "address" to align a
8035 target instruction of size "target_size" so that it does not cross a
8036 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8037 the fill can be an arbitrary number of bytes. Otherwise, the space must
8038 be filled by NOP instructions. */
e0001a05 8039
d77b99c9 8040static int
7fa3d080
BW		 8041get_text_align_fill_size (addressT address,
8042 int align_pow,
8043 int target_size,
8044 bfd_boolean use_nops,
8045 bfd_boolean use_no_density)
e0001a05 8046{
d77b99c9
BW		 8047 addressT alignment, fill, fill_limit, fill_step;
8048 bfd_boolean skip_one = FALSE;
e0001a05 8049
d77b99c9
BW		 8050 alignment = (1 << align_pow);
8051 assert (target_size > 0 && alignment >= (addressT) target_size);
c138bc38 8052
e0001a05
NC		 8053 if (!use_nops)
8054 {
d77b99c9
BW		 8055 fill_limit = alignment;
8056 fill_step = 1;
e0001a05 8057 }
d77b99c9 8058 else if (!use_no_density)
e0001a05 8059 {
d77b99c9
BW		 8060 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8061 fill_limit = alignment * 2;
8062 fill_step = 1;
8063 skip_one = TRUE;
e0001a05
NC		 8064 }
8065 else
8066 {
d77b99c9
BW		 8067 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8068 fill_limit = alignment * 3;
8069 fill_step = 3;
8070 }
e0001a05 8071
d77b99c9
BW		 8072 /* Try all fill sizes until finding one that works. */
8073 for (fill = 0; fill < fill_limit; fill += fill_step)
8074 {
8075 if (skip_one && fill == 1)
8076 continue;
8077 if ((address + fill) >> align_pow
8078 == (address + fill + target_size - 1) >> align_pow)
8079 return fill;
e0001a05
NC		 8080 }
8081 assert (0);
8082 return 0;
8083}
8084
8085
664df4e4
BW		 8086static int
8087branch_align_power (segT sec)
8088{
8089 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8090 is aligned to at least an 8-byte boundary, then a branch target need
8091 only fit within an 8-byte aligned block of memory to avoid a stall.
8092 Otherwise, try to fit branch targets within 4-byte aligned blocks
8093 (which may be insufficient, e.g., if the section has no alignment, but
8094 it's good enough). */
8095 if (xtensa_fetch_width == 8)
8096 {
8097 if (get_recorded_alignment (sec) >= 3)
8098 return 3;
8099 }
8100 else
8101 assert (xtensa_fetch_width == 4);
8102
8103 return 2;
8104}
8105
8106
e0001a05
NC		 8107/* This will assert if it is not possible. */
8108
d77b99c9
BW		 8109static int
8110get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density)
e0001a05 8111{
d77b99c9
BW		 8112 int count = 0;
8113
e0001a05
NC		 8114 if (use_no_density)
8115 {
8116 assert (fill_size % 3 == 0);
8117 return (fill_size / 3);
8118 }
8119
8120 assert (fill_size != 1); /* Bad argument. */
8121
8122 while (fill_size > 1)
8123 {
d77b99c9 8124 int insn_size = 3;
e0001a05
NC		 8125 if (fill_size == 2 || fill_size == 4)
8126 insn_size = 2;
8127 fill_size -= insn_size;
8128 count++;
8129 }
8130 assert (fill_size != 1); /* Bad algorithm. */
8131 return count;
8132}
8133
8134
d77b99c9
BW		 8135static int
8136get_text_align_nth_nop_size (offsetT fill_size,
8137 int n,
7fa3d080 8138 bfd_boolean use_no_density)
e0001a05 8139{
d77b99c9 8140 int count = 0;
e0001a05
NC		 8141
8142 if (use_no_density)
8143 return 3;
8144
d77b99c9
BW		 8145 assert (fill_size != 1); /* Bad argument. */
8146
e0001a05
NC		 8147 while (fill_size > 1)
8148 {
d77b99c9 8149 int insn_size = 3;
e0001a05
NC		 8150 if (fill_size == 2 || fill_size == 4)
8151 insn_size = 2;
8152 fill_size -= insn_size;
8153 count++;
8154 if (n + 1 == count)
8155 return insn_size;
8156 }
8157 assert (0);
8158 return 0;
8159}
8160
8161
8162/* For the given fragment, find the appropriate address
8163 for it to begin at if we are using NOPs to align it. */
8164
8165static addressT
7fa3d080 8166get_noop_aligned_address (fragS *fragP, addressT address)
e0001a05 8167{
43cd72b9
BW		 8168 /* The rule is: get next fragment's FIRST instruction. Find
8169 the smallest number of bytes that need to be added to
8170 ensure that the next fragment's FIRST instruction will fit
8171 in a single word.
c138bc38 8172
43cd72b9
BW		 8173 E.G., 2 bytes : 0, 1, 2 mod 4
8174 3 bytes: 0, 1 mod 4
c138bc38 8175
43cd72b9
BW		 8176 If the FIRST instruction MIGHT be relaxed,
8177 assume that it will become a 3-byte instruction.
c138bc38 8178
43cd72b9
BW		 8179 Note again here that LOOP instructions are not bundleable,
8180 and this relaxation only applies to LOOP opcodes. */
c138bc38 8181
d77b99c9 8182 int fill_size = 0;
43cd72b9
BW		 8183 int first_insn_size;
8184 int loop_insn_size;
8185 addressT pre_opcode_bytes;
d77b99c9 8186 int align_power;
43cd72b9
BW		 8187 fragS *first_insn;
8188 xtensa_opcode opcode;
8189 bfd_boolean is_loop;
e0001a05 8190
43cd72b9
BW		 8191 assert (fragP->fr_type == rs_machine_dependent);
8192 assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
e0001a05 8193
43cd72b9
BW		 8194 /* Find the loop frag. */
8195 first_insn = next_non_empty_frag (fragP);
8196 /* Now find the first insn frag. */
8197 first_insn = next_non_empty_frag (first_insn);
e0001a05 8198
43cd72b9
BW		 8199 is_loop = next_frag_opcode_is_loop (fragP, &opcode);
8200 assert (is_loop);
8201 loop_insn_size = xg_get_single_size (opcode);
e0001a05 8202
43cd72b9
BW		 8203 pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
8204 pre_opcode_bytes += loop_insn_size;
e0001a05 8205
43cd72b9
BW		 8206 /* For loops, the alignment depends on the size of the
8207 instruction following the loop, not the LOOP instruction. */
e0001a05 8208
43cd72b9 8209 if (first_insn == NULL)
03aaa593
BW		 8210 first_insn_size = xtensa_fetch_width;
8211 else
8212 first_insn_size = get_loop_align_size (frag_format_size (first_insn));
e0001a05 8213
43cd72b9 8214 /* If it was 8, then we'll need a larger alignment for the section. */
d77b99c9
BW		 8215 align_power = get_text_align_power (first_insn_size);
8216 record_alignment (now_seg, align_power);
c138bc38 8217
43cd72b9 8218 fill_size = get_text_align_fill_size
d77b99c9
BW		 8219 (address + pre_opcode_bytes, align_power, first_insn_size, TRUE,
8220 fragP->tc_frag_data.is_no_density);
e0001a05
NC		 8221
8222 return address + fill_size;
8223}
8224
8225
43cd72b9
BW		 8226/* 3 mechanisms for relaxing an alignment:
8227
8228 Align to a power of 2.
8229 Align so the next fragment's instruction does not cross a word boundary.
8230 Align the current instruction so that if the next instruction
8231 were 3 bytes, it would not cross a word boundary.
8232
e0001a05
NC		 8233 We can align with:
8234
43cd72b9
BW		 8235 zeros - This is easy; always insert zeros.
8236 nops - 3-byte and 2-byte instructions
8237 2 - 2-byte nop
8238 3 - 3-byte nop
8239 4 - 2 2-byte nops
8240 >=5 : 3-byte instruction + fn (n-3)
e0001a05
NC		 8241 widening - widen previous instructions. */
8242
d77b99c9
BW		 8243static offsetT
8244get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff)
e0001a05 8245{
43cd72b9
BW		 8246 addressT target_address, loop_insn_offset;
8247 int target_size;
8248 xtensa_opcode loop_opcode;
8249 bfd_boolean is_loop;
d77b99c9
BW		 8250 int align_power;
8251 offsetT opt_diff;
5f9084e9 8252 offsetT branch_align;
e0001a05 8253
43cd72b9
BW		 8254 assert (fragP->fr_type == rs_machine_dependent);
8255 switch (fragP->fr_subtype)
e0001a05 8256 {
43cd72b9
BW		 8257 case RELAX_DESIRE_ALIGN:
8258 target_size = next_frag_format_size (fragP);
8259 if (target_size == XTENSA_UNDEFINED)
8260 target_size = 3;
664df4e4
BW		 8261 align_power = branch_align_power (now_seg);
8262 branch_align = 1 << align_power;
0e5cd789
BW		 8263 /* Don't count on the section alignment being as large as the target. */
8264 if (target_size > branch_align)
8265 target_size = branch_align;
d77b99c9 8266 opt_diff = get_text_align_fill_size (address, align_power,
43cd72b9
BW		 8267 target_size, FALSE, FALSE);
8268
664df4e4
BW		 8269 *max_diff = (opt_diff + branch_align
8270 - (target_size + ((address + opt_diff) % branch_align)));
43cd72b9
BW		 8271 assert (*max_diff >= opt_diff);
8272 return opt_diff;
e0001a05 8273
43cd72b9 8274 case RELAX_ALIGN_NEXT_OPCODE:
03aaa593 8275 target_size = get_loop_align_size (next_frag_format_size (fragP));
43cd72b9
BW		 8276 loop_insn_offset = 0;
8277 is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode);
8278 assert (is_loop);
8279
8280 /* If the loop has been expanded then the LOOP instruction
8281 could be at an offset from this fragment. */
8282 if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0]
8283 != RELAX_IMMED)
8284 loop_insn_offset = get_expanded_loop_offset (loop_opcode);
8285
43cd72b9
BW		 8286 /* In an ideal world, which is what we are shooting for here,
8287 we wouldn't need to use any NOPs immediately prior to the
8288 LOOP instruction. If this approach fails, relax_frag_loop_align
8289 will call get_noop_aligned_address. */
8290 target_address =
8291 address + loop_insn_offset + xg_get_single_size (loop_opcode);
d77b99c9
BW		 8292 align_power = get_text_align_power (target_size),
8293 opt_diff = get_text_align_fill_size (target_address, align_power,
43cd72b9
BW		 8294 target_size, FALSE, FALSE);
8295
8296 *max_diff = xtensa_fetch_width
8297 - ((target_address + opt_diff) % xtensa_fetch_width)
8298 - target_size + opt_diff;
8299 assert (*max_diff >= opt_diff);
8300 return opt_diff;
e0001a05 8301
43cd72b9
BW		 8302 default:
8303 break;
e0001a05 8304 }
43cd72b9
BW		 8305 assert (0);
8306 return 0;
e0001a05
NC		 8307}
8308
8309\f
8310/* md_relax_frag Hook and Helper Functions. */
8311
7fa3d080
BW		 8312static long relax_frag_loop_align (fragS *, long);
8313static long relax_frag_for_align (fragS *, long);
8314static long relax_frag_immed
8315 (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean);
8316
8317
e0001a05
NC		 8318/* Return the number of bytes added to this fragment, given that the
8319 input has been stretched already by "stretch". */
8320
8321long
7fa3d080 8322xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
e0001a05 8323{
43cd72b9 8324 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 8325 int unreported = fragP->tc_frag_data.unreported_expansion;
8326 long new_stretch = 0;
8327 char *file_name;
d77b99c9
BW		 8328 unsigned line;
8329 int lit_size;
43cd72b9
BW		 8330 static xtensa_insnbuf vbuf = NULL;
8331 int slot, num_slots;
8332 xtensa_format fmt;
e0001a05
NC		 8333
8334 as_where (&file_name, &line);
8335 new_logical_line (fragP->fr_file, fragP->fr_line);
8336
8337 fragP->tc_frag_data.unreported_expansion = 0;
8338
8339 switch (fragP->fr_subtype)
8340 {
8341 case RELAX_ALIGN_NEXT_OPCODE:
8342 /* Always convert. */
43cd72b9
BW		 8343 if (fragP->tc_frag_data.relax_seen)
8344 new_stretch = relax_frag_loop_align (fragP, stretch);
e0001a05
NC		 8345 break;
8346
8347 case RELAX_LOOP_END:
8348 /* Do nothing. */
8349 break;
8350
8351 case RELAX_LOOP_END_ADD_NOP:
8352 /* Add a NOP and switch to .fill 0. */
8353 new_stretch = relax_frag_add_nop (fragP);
43cd72b9 8354 frag_wane (fragP);
e0001a05
NC		 8355 break;
8356
8357 case RELAX_DESIRE_ALIGN:
43cd72b9 8358 /* Do nothing. The narrowing before this frag will either align
e0001a05
NC		 8359 it or not. */
8360 break;
8361
8362 case RELAX_LITERAL:
8363 case RELAX_LITERAL_FINAL:
8364 return 0;
8365
8366 case RELAX_LITERAL_NR:
8367 lit_size = 4;
8368 fragP->fr_subtype = RELAX_LITERAL_FINAL;
8369 assert (unreported == lit_size);
8370 memset (&fragP->fr_literal[fragP->fr_fix], 0, 4);
8371 fragP->fr_var -= lit_size;
8372 fragP->fr_fix += lit_size;
8373 new_stretch = 4;
8374 break;
8375
43cd72b9
BW		 8376 case RELAX_SLOTS:
8377 if (vbuf == NULL)
8378 vbuf = xtensa_insnbuf_alloc (isa);
8379
d77b99c9
BW		 8380 xtensa_insnbuf_from_chars
8381 (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0);
43cd72b9
BW		 8382 fmt = xtensa_format_decode (isa, vbuf);
8383 num_slots = xtensa_format_num_slots (isa, fmt);
e0001a05 8384
43cd72b9
BW		 8385 for (slot = 0; slot < num_slots; slot++)
8386 {
8387 switch (fragP->tc_frag_data.slot_subtypes[slot])
8388 {
8389 case RELAX_NARROW:
8390 if (fragP->tc_frag_data.relax_seen)
8391 new_stretch += relax_frag_for_align (fragP, stretch);
8392 break;
8393
8394 case RELAX_IMMED:
8395 case RELAX_IMMED_STEP1:
8396 case RELAX_IMMED_STEP2:
b81bf389 8397 case RELAX_IMMED_STEP3:
43cd72b9
BW		 8398 /* Place the immediate. */
8399 new_stretch += relax_frag_immed
8400 (now_seg, fragP, stretch,
8401 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
8402 fmt, slot, stretched_p, FALSE);
8403 break;
8404
8405 default:
8406 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8407 break;
8408 }
8409 }
e0001a05
NC		 8410 break;
8411
8412 case RELAX_LITERAL_POOL_BEGIN:
8413 case RELAX_LITERAL_POOL_END:
43cd72b9
BW		 8414 case RELAX_MAYBE_UNREACHABLE:
8415 case RELAX_MAYBE_DESIRE_ALIGN:
e0001a05
NC		 8416 /* No relaxation required. */
8417 break;
8418
43cd72b9
BW		 8419 case RELAX_FILL_NOP:
8420 case RELAX_UNREACHABLE:
8421 if (fragP->tc_frag_data.relax_seen)
8422 new_stretch += relax_frag_for_align (fragP, stretch);
8423 break;
8424
e0001a05
NC		 8425 default:
8426 as_bad (_("bad relaxation state"));
8427 }
8428
43cd72b9 8429 /* Tell gas we need another relaxation pass. */
c138bc38 8430 if (! fragP->tc_frag_data.relax_seen)
43cd72b9
BW		 8431 {
8432 fragP->tc_frag_data.relax_seen = TRUE;
8433 *stretched_p = 1;
8434 }
8435
e0001a05
NC		 8436 new_logical_line (file_name, line);
8437 return new_stretch;
8438}
8439
8440
8441static long
7fa3d080 8442relax_frag_loop_align (fragS *fragP, long stretch)
e0001a05
NC		 8443{
8444 addressT old_address, old_next_address, old_size;
8445 addressT new_address, new_next_address, new_size;
8446 addressT growth;
8447
43cd72b9
BW		 8448 /* All the frags with relax_frag_for_alignment prior to this one in the
8449 section have been done, hopefully eliminating the need for a NOP here.
8450 But, this will put it in if necessary. */
e0001a05
NC		 8451
8452 /* Calculate the old address of this fragment and the next fragment. */
8453 old_address = fragP->fr_address - stretch;
8454 old_next_address = (fragP->fr_address - stretch + fragP->fr_fix +
43cd72b9 8455 fragP->tc_frag_data.text_expansion[0]);
e0001a05
NC		 8456 old_size = old_next_address - old_address;
8457
8458 /* Calculate the new address of this fragment and the next fragment. */
8459 new_address = fragP->fr_address;
8460 new_next_address =
8461 get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix);
8462 new_size = new_next_address - new_address;
8463
8464 growth = new_size - old_size;
8465
8466 /* Fix up the text_expansion field and return the new growth. */
43cd72b9 8467 fragP->tc_frag_data.text_expansion[0] += growth;
e0001a05
NC		 8468 return growth;
8469}
8470
8471
43cd72b9 8472/* Add a NOP instruction. */
e0001a05
NC		 8473
8474static long
7fa3d080 8475relax_frag_add_nop (fragS *fragP)
e0001a05 8476{
e0001a05 8477 char *nop_buf = fragP->fr_literal + fragP->fr_fix;
43cd72b9
BW		 8478 int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
8479 assemble_nop (length, nop_buf);
e0001a05 8480 fragP->tc_frag_data.is_insn = TRUE;
e0001a05 8481
e0001a05
NC		 8482 if (fragP->fr_var < length)
8483 {
dd49a749 8484 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length);
e0001a05
NC		 8485 return 0;
8486 }
8487
8488 fragP->fr_fix += length;
8489 fragP->fr_var -= length;
e0001a05
NC		 8490 return length;
8491}
8492
8493
7fa3d080
BW		 8494static long future_alignment_required (fragS *, long);
8495
e0001a05 8496static long
7fa3d080 8497relax_frag_for_align (fragS *fragP, long stretch)
e0001a05 8498{
43cd72b9
BW		 8499 /* Overview of the relaxation procedure for alignment:
8500 We can widen with NOPs or by widening instructions or by filling
8501 bytes after jump instructions. Find the opportune places and widen
8502 them if necessary. */
8503
8504 long stretch_me;
8505 long diff;
e0001a05 8506
43cd72b9
BW		 8507 assert (fragP->fr_subtype == RELAX_FILL_NOP
8508 || fragP->fr_subtype == RELAX_UNREACHABLE
8509 || (fragP->fr_subtype == RELAX_SLOTS
8510 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW));
8511
8512 stretch_me = future_alignment_required (fragP, stretch);
8513 diff = stretch_me - fragP->tc_frag_data.text_expansion[0];
8514 if (diff == 0)
8515 return 0;
e0001a05 8516
43cd72b9 8517 if (diff < 0)
e0001a05 8518 {
43cd72b9
BW		 8519 /* We expanded on a previous pass. Can we shrink now? */
8520 long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me;
8521 if (shrink <= stretch && stretch > 0)
e0001a05 8522 {
43cd72b9
BW		 8523 fragP->tc_frag_data.text_expansion[0] = stretch_me;
8524 return -shrink;
e0001a05
NC		 8525 }
8526 return 0;
8527 }
8528
43cd72b9
BW		 8529 /* Below here, diff > 0. */
8530 fragP->tc_frag_data.text_expansion[0] = stretch_me;
e0001a05 8531
43cd72b9 8532 return diff;
e0001a05
NC		 8533}
8534
8535
43cd72b9
BW		 8536/* Return the address of the next frag that should be aligned.
8537
8538 By "address" we mean the address it _would_ be at if there
8539 is no action taken to align it between here and the target frag.
8540 In other words, if no narrows and no fill nops are used between
8541 here and the frag to align, _even_if_ some of the frags we use
8542 to align targets have already expanded on a previous relaxation
8543 pass.
8544
8545 Also, count each frag that may be used to help align the target.
8546
8547 Return 0 if there are no frags left in the chain that need to be
8548 aligned. */
8549
8550static addressT
7fa3d080
BW		 8551find_address_of_next_align_frag (fragS **fragPP,
8552 int *wide_nops,
8553 int *narrow_nops,
8554 int *widens,
8555 bfd_boolean *paddable)
e0001a05 8556{
43cd72b9
BW		 8557 fragS *fragP = *fragPP;
8558 addressT address = fragP->fr_address;
8559
8560 /* Do not reset the counts to 0. */
e0001a05
NC		 8561
8562 while (fragP)
8563 {
8564 /* Limit this to a small search. */
b5e4a23d 8565 if (*widens >= (int) xtensa_fetch_width)
43cd72b9
BW		 8566 {
8567 *fragPP = fragP;
8568 return 0;
8569 }
e0001a05
NC		 8570 address += fragP->fr_fix;
8571
43cd72b9
BW		 8572 if (fragP->fr_type == rs_fill)
8573 address += fragP->fr_offset * fragP->fr_var;
8574 else if (fragP->fr_type == rs_machine_dependent)
e0001a05 8575 {
e0001a05
NC		 8576 switch (fragP->fr_subtype)
8577 {
43cd72b9
BW		 8578 case RELAX_UNREACHABLE:
8579 *paddable = TRUE;
8580 break;
8581
8582 case RELAX_FILL_NOP:
8583 (*wide_nops)++;
8584 if (!fragP->tc_frag_data.is_no_density)
8585 (*narrow_nops)++;
8586 break;
8587
8588 case RELAX_SLOTS:
8589 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8590 {
8591 (*widens)++;
8592 break;
8593 }
34e41783 8594 address += total_frag_text_expansion (fragP);;
e0001a05
NC		 8595 break;
8596
8597 case RELAX_IMMED:
43cd72b9 8598 address += fragP->tc_frag_data.text_expansion[0];
e0001a05
NC		 8599 break;
8600
8601 case RELAX_ALIGN_NEXT_OPCODE:
8602 case RELAX_DESIRE_ALIGN:
43cd72b9
BW		 8603 *fragPP = fragP;
8604 return address;
8605
8606 case RELAX_MAYBE_UNREACHABLE:
8607 case RELAX_MAYBE_DESIRE_ALIGN:
8608 /* Do nothing. */
e0001a05
NC		 8609 break;
8610
8611 default:
43cd72b9
BW		 8612 /* Just punt if we don't know the type. */
8613 *fragPP = fragP;
8614 return 0;
e0001a05 8615 }
43cd72b9 8616 }
c138bc38 8617 else
43cd72b9
BW		 8618 {
8619 /* Just punt if we don't know the type. */
8620 *fragPP = fragP;
8621 return 0;
8622 }
8623 fragP = fragP->fr_next;
8624 }
8625
8626 *fragPP = fragP;
8627 return 0;
8628}
8629
8630
7fa3d080
BW		 8631static long bytes_to_stretch (fragS *, int, int, int, int);
8632
43cd72b9 8633static long
7fa3d080 8634future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED)
43cd72b9
BW		 8635{
8636 fragS *this_frag = fragP;
8637 long address;
8638 int num_widens = 0;
8639 int wide_nops = 0;
8640 int narrow_nops = 0;
8641 bfd_boolean paddable = FALSE;
8642 offsetT local_opt_diff;
8643 offsetT opt_diff;
8644 offsetT max_diff;
8645 int stretch_amount = 0;
8646 int local_stretch_amount;
8647 int global_stretch_amount;
8648
7fa3d080
BW		 8649 address = find_address_of_next_align_frag
8650 (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable);
43cd72b9 8651
b5e4a23d
BW		 8652 if (!address)
8653 {
8654 if (this_frag->tc_frag_data.is_aligning_branch)
8655 this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
8656 else
8657 frag_wane (this_frag);
8658 }
8659 else
43cd72b9
BW		 8660 {
8661 local_opt_diff = get_aligned_diff (fragP, address, &max_diff);
8662 opt_diff = local_opt_diff;
8663 assert (opt_diff >= 0);
8664 assert (max_diff >= opt_diff);
c138bc38 8665 if (max_diff == 0)
43cd72b9 8666 return 0;
d2a033cd 8667
43cd72b9
BW		 8668 if (fragP)
8669 fragP = fragP->fr_next;
8670
8671 while (fragP && opt_diff < max_diff && address)
8672 {
8673 /* We only use these to determine if we can exit early
c138bc38 8674 because there will be plenty of ways to align future
43cd72b9 8675 align frags. */
d77b99c9 8676 int glob_widens = 0;
43cd72b9
BW		 8677 int dnn = 0;
8678 int dw = 0;
8679 bfd_boolean glob_pad = 0;
7fa3d080
BW		 8680 address = find_address_of_next_align_frag
8681 (&fragP, &glob_widens, &dnn, &dw, &glob_pad);
43cd72b9 8682 /* If there is a padable portion, then skip. */
664df4e4 8683 if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg)))
b5e4a23d 8684 address = 0;
43cd72b9 8685
c138bc38 8686 if (address)
43cd72b9
BW		 8687 {
8688 offsetT next_m_diff;
8689 offsetT next_o_diff;
8690
8691 /* Downrange frags haven't had stretch added to them yet. */
8692 address += stretch;
8693
8694 /* The address also includes any text expansion from this
8695 frag in a previous pass, but we don't want that. */
8696 address -= this_frag->tc_frag_data.text_expansion[0];
8697
8698 /* Assume we are going to move at least opt_diff. In
8699 reality, we might not be able to, but assuming that
8700 we will helps catch cases where moving opt_diff pushes
8701 the next target from aligned to unaligned. */
8702 address += opt_diff;
8703
8704 next_o_diff = get_aligned_diff (fragP, address, &next_m_diff);
8705
8706 /* Now cleanup for the adjustments to address. */
8707 next_o_diff += opt_diff;
8708 next_m_diff += opt_diff;
8709 if (next_o_diff <= max_diff && next_o_diff > opt_diff)
8710 opt_diff = next_o_diff;
8711 if (next_m_diff < max_diff)
8712 max_diff = next_m_diff;
8713 fragP = fragP->fr_next;
8714 }
8715 }
d2a033cd 8716
43cd72b9
BW		 8717 /* If there are enough wideners in between, do it. */
8718 if (paddable)
8719 {
8720 if (this_frag->fr_subtype == RELAX_UNREACHABLE)
8721 {
8722 assert (opt_diff <= UNREACHABLE_MAX_WIDTH);
8723 return opt_diff;
8724 }
8725 return 0;
8726 }
c138bc38 8727 local_stretch_amount
43cd72b9
BW		 8728 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
8729 num_widens, local_opt_diff);
c138bc38
BW		 8730 global_stretch_amount
8731 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
43cd72b9 8732 num_widens, opt_diff);
c138bc38
BW		 8733 /* If the condition below is true, then the frag couldn't
8734 stretch the correct amount for the global case, so we just
8735 optimize locally. We'll rely on the subsequent frags to get
43cd72b9
BW		 8736 the correct alignment in the global case. */
8737 if (global_stretch_amount < local_stretch_amount)
8738 stretch_amount = local_stretch_amount;
8739 else
8740 stretch_amount = global_stretch_amount;
d2a033cd 8741
43cd72b9
BW		 8742 if (this_frag->fr_subtype == RELAX_SLOTS
8743 && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8744 assert (stretch_amount <= 1);
8745 else if (this_frag->fr_subtype == RELAX_FILL_NOP)
8746 {
8747 if (this_frag->tc_frag_data.is_no_density)
8748 assert (stretch_amount == 3 || stretch_amount == 0);
8749 else
8750 assert (stretch_amount <= 3);
8751 }
8752 }
8753 return stretch_amount;
8754}
8755
8756
8757/* The idea: widen everything you can to get a target or loop aligned,
8758 then start using NOPs.
8759
8760 When we must have a NOP, here is a table of how we decide
8761 (so you don't have to fight through the control flow below):
8762
8763 wide_nops = the number of wide NOPs available for aligning
8764 narrow_nops = the number of narrow NOPs available for aligning
8765 (a subset of wide_nops)
8766 widens = the number of narrow instructions that should be widened
8767
8768 Desired wide narrow
8769 Diff nop nop widens
8770 1 0 0 1
8771 2 0 1 0
8772 3a 1 0 0
8773 b 0 1 1 (case 3a makes this case unnecessary)
8774 4a 1 0 1
8775 b 0 2 0
8776 c 0 1 2 (case 4a makes this case unnecessary)
8777 5a 1 0 2
8778 b 1 1 0
8779 c 0 2 1 (case 5b makes this case unnecessary)
8780 6a 2 0 0
8781 b 1 0 3
708587a4 8782 c 0 1 4 (case 6b makes this case unnecessary)
43cd72b9
BW		 8783 d 1 1 1 (case 6a makes this case unnecessary)
8784 e 0 2 2 (case 6a makes this case unnecessary)
8785 f 0 3 0 (case 6a makes this case unnecessary)
8786 7a 1 0 4
8787 b 2 0 1
8788 c 1 1 2 (case 7b makes this case unnecessary)
8789 d 0 1 5 (case 7a makes this case unnecessary)
8790 e 0 2 3 (case 7b makes this case unnecessary)
8791 f 0 3 1 (case 7b makes this case unnecessary)
8792 g 1 2 1 (case 7b makes this case unnecessary)
8793*/
8794
8795static long
7fa3d080
BW		 8796bytes_to_stretch (fragS *this_frag,
8797 int wide_nops,
8798 int narrow_nops,
8799 int num_widens,
8800 int desired_diff)
43cd72b9
BW		 8801{
8802 int bytes_short = desired_diff - num_widens;
8803
8804 assert (desired_diff >= 0 && desired_diff < 8);
8805 if (desired_diff == 0)
8806 return 0;
c138bc38 8807
43cd72b9 8808 assert (wide_nops > 0 || num_widens > 0);
e0001a05 8809
43cd72b9
BW		 8810 /* Always prefer widening to NOP-filling. */
8811 if (bytes_short < 0)
8812 {
8813 /* There are enough RELAX_NARROW frags after this one
8814 to align the target without widening this frag in any way. */
8815 return 0;
8816 }
c138bc38 8817
43cd72b9
BW		 8818 if (bytes_short == 0)
8819 {
8820 /* Widen every narrow between here and the align target
8821 and the align target will be properly aligned. */
8822 if (this_frag->fr_subtype == RELAX_FILL_NOP)
8823 return 0;
8824 else
8825 return 1;
8826 }
c138bc38 8827
43cd72b9
BW		 8828 /* From here we will need at least one NOP to get an alignment.
8829 However, we may not be able to align at all, in which case,
8830 don't widen. */
8831 if (this_frag->fr_subtype == RELAX_FILL_NOP)
8832 {
8833 switch (desired_diff)
8834 {
8835 case 1:
8836 return 0;
8837 case 2:
8838 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1)
8839 return 2; /* case 2 */
8840 return 0;
c138bc38 8841 case 3:
43cd72b9
BW		 8842 if (wide_nops > 1)
8843 return 0;
8844 else
8845 return 3; /* case 3a */
8846 case 4:
8847 if (num_widens >= 1 && wide_nops == 1)
8848 return 3; /* case 4a */
8849 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2)
8850 return 2; /* case 4b */
8851 return 0;
8852 case 5:
8853 if (num_widens >= 2 && wide_nops == 1)
8854 return 3; /* case 5a */
c138bc38 8855 /* We will need two nops. Are there enough nops
43cd72b9
BW		 8856 between here and the align target? */
8857 if (wide_nops < 2 || narrow_nops == 0)
8858 return 0;
8859 /* Are there other nops closer that can serve instead? */
8860 if (wide_nops > 2 && narrow_nops > 1)
8861 return 0;
8862 /* Take the density one first, because there might not be
8863 another density one available. */
8864 if (!this_frag->tc_frag_data.is_no_density)
8865 return 2; /* case 5b narrow */
8866 else
8867 return 3; /* case 5b wide */
8868 return 0;
8869 case 6:
8870 if (wide_nops == 2)
8871 return 3; /* case 6a */
8872 else if (num_widens >= 3 && wide_nops == 1)
8873 return 3; /* case 6b */
8874 return 0;
8875 case 7:
8876 if (wide_nops == 1 && num_widens >= 4)
8877 return 3; /* case 7a */
8878 else if (wide_nops == 2 && num_widens >= 1)
8879 return 3; /* case 7b */
8880 return 0;
e0001a05 8881 default:
43cd72b9 8882 assert (0);
e0001a05 8883 }
e0001a05 8884 }
43cd72b9
BW		 8885 else
8886 {
c138bc38 8887 /* We will need a NOP no matter what, but should we widen
43cd72b9 8888 this instruction to help?
e0001a05 8889
03aaa593 8890 This is a RELAX_NARROW frag. */
43cd72b9
BW		 8891 switch (desired_diff)
8892 {
8893 case 1:
8894 assert (0);
8895 return 0;
8896 case 2:
8897 case 3:
8898 return 0;
8899 case 4:
8900 if (wide_nops >= 1 && num_widens == 1)
8901 return 1; /* case 4a */
8902 return 0;
8903 case 5:
8904 if (wide_nops >= 1 && num_widens == 2)
8905 return 1; /* case 5a */
8906 return 0;
8907 case 6:
8908 if (wide_nops >= 2)
8909 return 0; /* case 6a */
8910 else if (wide_nops >= 1 && num_widens == 3)
8911 return 1; /* case 6b */
8912 return 0;
8913 case 7:
8914 if (wide_nops >= 1 && num_widens == 4)
8915 return 1; /* case 7a */
8916 else if (wide_nops >= 2 && num_widens == 1)
8917 return 1; /* case 7b */
8918 return 0;
8919 default:
8920 assert (0);
8921 return 0;
8922 }
8923 }
8924 assert (0);
8925 return 0;
e0001a05
NC		 8926}
8927
8928
8929static long
7fa3d080
BW		 8930relax_frag_immed (segT segP,
8931 fragS *fragP,
8932 long stretch,
8933 int min_steps,
8934 xtensa_format fmt,
8935 int slot,
8936 int *stretched_p,
8937 bfd_boolean estimate_only)
e0001a05 8938{
43cd72b9 8939 TInsn tinsn;
e0001a05
NC		 8940 int old_size;
8941 bfd_boolean negatable_branch = FALSE;
8942 bfd_boolean branch_jmp_to_next = FALSE;
43cd72b9
BW		 8943 bfd_boolean wide_insn = FALSE;
8944 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 8945 IStack istack;
8946 offsetT frag_offset;
8947 int num_steps;
8948 fragS *lit_fragP;
8949 int num_text_bytes, num_literal_bytes;
43cd72b9 8950 int literal_diff, total_text_diff, this_text_diff, first;
e0001a05
NC		 8951
8952 assert (fragP->fr_opcode != NULL);
8953
b5e4a23d
BW		 8954 xg_clear_vinsn (&cur_vinsn);
8955 vinsn_from_chars (&cur_vinsn, fragP->fr_opcode);
b2d179be 8956 if (cur_vinsn.num_slots > 1)
43cd72b9
BW		 8957 wide_insn = TRUE;
8958
b5e4a23d 8959 tinsn = cur_vinsn.slots[slot];
43cd72b9 8960 tinsn_immed_from_frag (&tinsn, fragP, slot);
e0001a05 8961
64b607e6 8962 if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1)
43cd72b9 8963 return 0;
e0001a05 8964
b08b5071 8965 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
43cd72b9 8966 branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP);
e0001a05 8967
43cd72b9 8968 negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1);
e0001a05 8969
43cd72b9 8970 old_size = xtensa_format_length (isa, fmt);
e0001a05
NC		 8971
8972 /* Special case: replace a branch to the next instruction with a NOP.
8973 This is required to work around a hardware bug in T1040.0 and also
8974 serves as an optimization. */
8975
8976 if (branch_jmp_to_next
8977 && ((old_size == 2) || (old_size == 3))
8978 && !next_frag_is_loop_target (fragP))
8979 return 0;
8980
8981 /* Here is the fun stuff: Get the immediate field from this
8982 instruction. If it fits, we are done. If not, find the next
8983 instruction sequence that fits. */
8984
8985 frag_offset = fragP->fr_opcode - fragP->fr_literal;
8986 istack_init (&istack);
43cd72b9 8987 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset,
e0001a05
NC		 8988 min_steps, stretch);
8989 if (num_steps < min_steps)
8990 {
8991 as_fatal (_("internal error: relaxation failed"));
8992 return 0;
8993 }
8994
8995 if (num_steps > RELAX_IMMED_MAXSTEPS)
8996 {
8997 as_fatal (_("internal error: relaxation requires too many steps"));
8998 return 0;
8999 }
9000
43cd72b9 9001 fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps;
e0001a05
NC		 9002
9003 /* Figure out the number of bytes needed. */
9004 lit_fragP = 0;
e0001a05 9005 num_literal_bytes = get_num_stack_literal_bytes (&istack);
43cd72b9
BW		 9006 literal_diff =
9007 num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
9008 first = 0;
9009 while (istack.insn[first].opcode == XTENSA_UNDEFINED)
9010 first++;
9011 num_text_bytes = get_num_stack_text_bytes (&istack);
9012 if (wide_insn)
9013 {
9014 num_text_bytes += old_size;
9015 if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot))
9016 num_text_bytes -= xg_get_single_size (istack.insn[first].opcode);
9017 }
9018 total_text_diff = num_text_bytes - old_size;
9019 this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot];
e0001a05
NC		 9020
9021 /* It MUST get larger. If not, we could get an infinite loop. */
43cd72b9
BW		 9022 assert (num_text_bytes >= 0);
9023 assert (literal_diff >= 0);
9024 assert (total_text_diff >= 0);
e0001a05 9025
43cd72b9
BW		 9026 fragP->tc_frag_data.text_expansion[slot] = total_text_diff;
9027 fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes;
9028 assert (fragP->tc_frag_data.text_expansion[slot] >= 0);
9029 assert (fragP->tc_frag_data.literal_expansion[slot] >= 0);
e0001a05
NC		 9030
9031 /* Find the associated expandable literal for this. */
9032 if (literal_diff != 0)
9033 {
43cd72b9 9034 lit_fragP = fragP->tc_frag_data.literal_frags[slot];
e0001a05
NC		 9035 if (lit_fragP)
9036 {
9037 assert (literal_diff == 4);
9038 lit_fragP->tc_frag_data.unreported_expansion += literal_diff;
9039
9040 /* We expect that the literal section state has NOT been
9041 modified yet. */
9042 assert (lit_fragP->fr_type == rs_machine_dependent
9043 && lit_fragP->fr_subtype == RELAX_LITERAL);
9044 lit_fragP->fr_subtype = RELAX_LITERAL_NR;
9045
9046 /* We need to mark this section for another iteration
9047 of relaxation. */
9048 (*stretched_p)++;
9049 }
9050 }
9051
43cd72b9 9052 if (negatable_branch && istack.ninsn > 1)
1d19a770 9053 update_next_frag_state (fragP);
e0001a05 9054
43cd72b9 9055 return this_text_diff;
e0001a05
NC		 9056}
9057
9058\f
9059/* md_convert_frag Hook and Helper Functions. */
9060
7fa3d080
BW		 9061static void convert_frag_align_next_opcode (fragS *);
9062static void convert_frag_narrow (segT, fragS *, xtensa_format, int);
9063static void convert_frag_fill_nop (fragS *);
9064static void convert_frag_immed (segT, fragS *, int, xtensa_format, int);
9065
e0001a05 9066void
7fa3d080 9067md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
e0001a05 9068{
43cd72b9
BW		 9069 static xtensa_insnbuf vbuf = NULL;
9070 xtensa_isa isa = xtensa_default_isa;
9071 int slot;
9072 int num_slots;
9073 xtensa_format fmt;
e0001a05 9074 char *file_name;
d77b99c9 9075 unsigned line;
e0001a05
NC		 9076
9077 as_where (&file_name, &line);
9078 new_logical_line (fragp->fr_file, fragp->fr_line);
9079
9080 switch (fragp->fr_subtype)
9081 {
9082 case RELAX_ALIGN_NEXT_OPCODE:
9083 /* Always convert. */
9084 convert_frag_align_next_opcode (fragp);
9085 break;
9086
9087 case RELAX_DESIRE_ALIGN:
9088 /* Do nothing. If not aligned already, too bad. */
9089 break;
9090
43cd72b9
BW		 9091 case RELAX_LITERAL:
9092 case RELAX_LITERAL_FINAL:
9093 break;
9094
9095 case RELAX_SLOTS:
9096 if (vbuf == NULL)
9097 vbuf = xtensa_insnbuf_alloc (isa);
9098
d77b99c9
BW		 9099 xtensa_insnbuf_from_chars
9100 (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0);
43cd72b9
BW		 9101 fmt = xtensa_format_decode (isa, vbuf);
9102 num_slots = xtensa_format_num_slots (isa, fmt);
9103
9104 for (slot = 0; slot < num_slots; slot++)
9105 {
9106 switch (fragp->tc_frag_data.slot_subtypes[slot])
9107 {
9108 case RELAX_NARROW:
9109 convert_frag_narrow (sec, fragp, fmt, slot);
9110 break;
9111
9112 case RELAX_IMMED:
9113 case RELAX_IMMED_STEP1:
9114 case RELAX_IMMED_STEP2:
b81bf389 9115 case RELAX_IMMED_STEP3:
43cd72b9
BW		 9116 /* Place the immediate. */
9117 convert_frag_immed
9118 (sec, fragp,
9119 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
9120 fmt, slot);
9121 break;
9122
9123 default:
9124 /* This is OK because some slots could have
9125 relaxations and others have none. */
9126 break;
9127 }
9128 }
9129 break;
9130
9131 case RELAX_UNREACHABLE:
9132 memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var);
9133 fragp->fr_fix += fragp->tc_frag_data.text_expansion[0];
9134 fragp->fr_var -= fragp->tc_frag_data.text_expansion[0];
9135 frag_wane (fragp);
e0001a05
NC		 9136 break;
9137
43cd72b9
BW		 9138 case RELAX_MAYBE_UNREACHABLE:
9139 case RELAX_MAYBE_DESIRE_ALIGN:
9140 frag_wane (fragp);
e0001a05
NC		 9141 break;
9142
43cd72b9
BW		 9143 case RELAX_FILL_NOP:
9144 convert_frag_fill_nop (fragp);
e0001a05
NC		 9145 break;
9146
9147 case RELAX_LITERAL_NR:
9148 if (use_literal_section)
9149 {
9150 /* This should have been handled during relaxation. When
9151 relaxing a code segment, literals sometimes need to be
9152 added to the corresponding literal segment. If that
9153 literal segment has already been relaxed, then we end up
9154 in this situation. Marking the literal segments as data
9155 would make this happen less often (since GAS always relaxes
9156 code before data), but we could still get into trouble if
9157 there are instructions in a segment that is not marked as
9158 containing code. Until we can implement a better solution,
9159 cheat and adjust the addresses of all the following frags.
9160 This could break subsequent alignments, but the linker's
9161 literal coalescing will do that anyway. */
9162
9163 fragS *f;
9164 fragp->fr_subtype = RELAX_LITERAL_FINAL;
9165 assert (fragp->tc_frag_data.unreported_expansion == 4);
9166 memset (&fragp->fr_literal[fragp->fr_fix], 0, 4);
9167 fragp->fr_var -= 4;
9168 fragp->fr_fix += 4;
9169 for (f = fragp->fr_next; f; f = f->fr_next)
9170 f->fr_address += 4;
9171 }
9172 else
9173 as_bad (_("invalid relaxation fragment result"));
9174 break;
9175 }
9176
9177 fragp->fr_var = 0;
9178 new_logical_line (file_name, line);
9179}
9180
9181
7fa3d080
BW		 9182static void
9183convert_frag_align_next_opcode (fragS *fragp)
e0001a05
NC		 9184{
9185 char *nop_buf; /* Location for Writing. */
e0001a05
NC		 9186 bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density;
9187 addressT aligned_address;
d77b99c9
BW		 9188 offsetT fill_size;
9189 int nop, nop_count;
e0001a05
NC		 9190
9191 aligned_address = get_noop_aligned_address (fragp, fragp->fr_address +
9192 fragp->fr_fix);
9193 fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix);
9194 nop_count = get_text_align_nop_count (fill_size, use_no_density);
9195 nop_buf = fragp->fr_literal + fragp->fr_fix;
9196
d77b99c9 9197 for (nop = 0; nop < nop_count; nop++)
e0001a05 9198 {
d77b99c9
BW		 9199 int nop_size;
9200 nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density);
e0001a05
NC		 9201
9202 assemble_nop (nop_size, nop_buf);
9203 nop_buf += nop_size;
9204 }
9205
9206 fragp->fr_fix += fill_size;
9207 fragp->fr_var -= fill_size;
9208}
9209
9210
9211static void
7fa3d080 9212convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
e0001a05 9213{
43cd72b9 9214 TInsn tinsn, single_target;
84b08ed9 9215 int size, old_size, diff;
e0001a05
NC		 9216 offsetT frag_offset;
9217
43cd72b9
BW		 9218 assert (slot == 0);
9219 tinsn_from_chars (&tinsn, fragP->fr_opcode, 0);
9220
b5e4a23d 9221 if (fragP->tc_frag_data.is_aligning_branch == 1)
43cd72b9
BW		 9222 {
9223 assert (fragP->tc_frag_data.text_expansion[0] == 1
9224 || fragP->tc_frag_data.text_expansion[0] == 0);
9225 convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0],
9226 fmt, slot);
9227 return;
9228 }
9229
9230 if (fragP->tc_frag_data.text_expansion[0] == 0)
e0001a05
NC		 9231 {
9232 /* No conversion. */
9233 fragP->fr_var = 0;
9234 return;
9235 }
9236
9237 assert (fragP->fr_opcode != NULL);
9238
43cd72b9
BW		 9239 /* Frags in this relaxation state should only contain
9240 single instruction bundles. */
9241 tinsn_immed_from_frag (&tinsn, fragP, 0);
e0001a05
NC		 9242
9243 /* Just convert it to a wide form.... */
9244 size = 0;
43cd72b9 9245 old_size = xg_get_single_size (tinsn.opcode);
e0001a05
NC		 9246
9247 tinsn_init (&single_target);
9248 frag_offset = fragP->fr_opcode - fragP->fr_literal;
9249
84b08ed9 9250 if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE))
43cd72b9
BW		 9251 {
9252 as_bad (_("unable to widen instruction"));
9253 return;
9254 }
9255
9256 size = xg_get_single_size (single_target.opcode);
b2d179be
BW		 9257 xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP,
9258 frag_offset, TRUE);
e0001a05
NC		 9259
9260 diff = size - old_size;
9261 assert (diff >= 0);
9262 assert (diff <= fragP->fr_var);
9263 fragP->fr_var -= diff;
9264 fragP->fr_fix += diff;
9265
9266 /* clean it up */
9267 fragP->fr_var = 0;
9268}
9269
9270
9271static void
7fa3d080 9272convert_frag_fill_nop (fragS *fragP)
43cd72b9
BW		 9273{
9274 char *loc = &fragP->fr_literal[fragP->fr_fix];
9275 int size = fragP->tc_frag_data.text_expansion[0];
9276 assert ((unsigned) size == (fragP->fr_next->fr_address
9277 - fragP->fr_address - fragP->fr_fix));
9278 if (size == 0)
9279 {
9280 /* No conversion. */
9281 fragP->fr_var = 0;
9282 return;
9283 }
9284 assemble_nop (size, loc);
9285 fragP->tc_frag_data.is_insn = TRUE;
9286 fragP->fr_var -= size;
9287 fragP->fr_fix += size;
9288 frag_wane (fragP);
9289}
9290
9291
7fa3d080
BW		 9292static fixS *fix_new_exp_in_seg
9293 (segT, subsegT, fragS *, int, int, expressionS *, int,
9294 bfd_reloc_code_real_type);
9295static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *);
9296
43cd72b9 9297static void
7fa3d080
BW		 9298convert_frag_immed (segT segP,
9299 fragS *fragP,
9300 int min_steps,
9301 xtensa_format fmt,
9302 int slot)
e0001a05
NC		 9303{
9304 char *immed_instr = fragP->fr_opcode;
43cd72b9 9305 TInsn orig_tinsn;
e0001a05 9306 bfd_boolean expanded = FALSE;
e0001a05 9307 bfd_boolean branch_jmp_to_next = FALSE;
43cd72b9 9308 char *fr_opcode = fragP->fr_opcode;
43cd72b9
BW		 9309 xtensa_isa isa = xtensa_default_isa;
9310 bfd_boolean wide_insn = FALSE;
9311 int bytes;
9312 bfd_boolean is_loop;
e0001a05 9313
43cd72b9 9314 assert (fr_opcode != NULL);
e0001a05 9315
b5e4a23d 9316 xg_clear_vinsn (&cur_vinsn);
e0001a05 9317
b5e4a23d 9318 vinsn_from_chars (&cur_vinsn, fr_opcode);
b2d179be 9319 if (cur_vinsn.num_slots > 1)
43cd72b9 9320 wide_insn = TRUE;
e0001a05 9321
b5e4a23d 9322 orig_tinsn = cur_vinsn.slots[slot];
43cd72b9
BW		 9323 tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
9324
9325 is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1;
e0001a05 9326
b08b5071 9327 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
43cd72b9 9328 branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP);
e0001a05
NC		 9329
9330 if (branch_jmp_to_next && !next_frag_is_loop_target (fragP))
9331 {
9332 /* Conversion just inserts a NOP and marks the fix as completed. */
43cd72b9
BW		 9333 bytes = xtensa_format_length (isa, fmt);
9334 if (bytes >= 4)
9335 {
b5e4a23d
BW		 9336 cur_vinsn.slots[slot].opcode =
9337 xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot);
9338 cur_vinsn.slots[slot].ntok = 0;
43cd72b9
BW		 9339 }
9340 else
9341 {
9342 bytes += fragP->tc_frag_data.text_expansion[0];
9343 assert (bytes == 2 || bytes == 3);
b5e4a23d 9344 build_nop (&cur_vinsn.slots[0], bytes);
43cd72b9
BW		 9345 fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
9346 }
e7da6241 9347 vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE);
d77b99c9 9348 xtensa_insnbuf_to_chars
b5e4a23d 9349 (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0);
e0001a05
NC		 9350 fragP->fr_var = 0;
9351 }
7c834684 9352 else
e0001a05 9353 {
43cd72b9
BW		 9354 /* Here is the fun stuff: Get the immediate field from this
9355 instruction. If it fits, we're done. If not, find the next
9356 instruction sequence that fits. */
9357
e0001a05
NC		 9358 IStack istack;
9359 int i;
9360 symbolS *lit_sym = NULL;
9361 int total_size = 0;
43cd72b9 9362 int target_offset = 0;
e0001a05
NC		 9363 int old_size;
9364 int diff;
9365 symbolS *gen_label = NULL;
9366 offsetT frag_offset;
43cd72b9
BW		 9367 bfd_boolean first = TRUE;
9368 bfd_boolean last_is_jump;
e0001a05 9369
43cd72b9 9370 /* It does not fit. Find something that does and
e0001a05 9371 convert immediately. */
43cd72b9 9372 frag_offset = fr_opcode - fragP->fr_literal;
e0001a05 9373 istack_init (&istack);
43cd72b9 9374 xg_assembly_relax (&istack, &orig_tinsn,
e0001a05
NC		 9375 segP, fragP, frag_offset, min_steps, 0);
9376
43cd72b9 9377 old_size = xtensa_format_length (isa, fmt);
e0001a05
NC		 9378
9379 /* Assemble this right inline. */
9380
9381 /* First, create the mapping from a label name to the REAL label. */
43cd72b9 9382 target_offset = 0;
e0001a05
NC		 9383 for (i = 0; i < istack.ninsn; i++)
9384 {
43cd72b9 9385 TInsn *tinsn = &istack.insn[i];
e0001a05
NC		 9386 fragS *lit_frag;
9387
43cd72b9 9388 switch (tinsn->insn_type)
e0001a05
NC		 9389 {
9390 case ITYPE_LITERAL:
9391 if (lit_sym != NULL)
9392 as_bad (_("multiple literals in expansion"));
9393 /* First find the appropriate space in the literal pool. */
43cd72b9 9394 lit_frag = fragP->tc_frag_data.literal_frags[slot];
e0001a05
NC		 9395 if (lit_frag == NULL)
9396 as_bad (_("no registered fragment for literal"));
43cd72b9 9397 if (tinsn->ntok != 1)
e0001a05
NC		 9398 as_bad (_("number of literal tokens != 1"));
9399
9400 /* Set the literal symbol and add a fixup. */
9401 lit_sym = lit_frag->fr_symbol;
9402 break;
9403
9404 case ITYPE_LABEL:
43cd72b9
BW		 9405 if (align_targets && !is_loop)
9406 {
9407 fragS *unreach = fragP->fr_next;
9408 while (!(unreach->fr_type == rs_machine_dependent
9409 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9410 || unreach->fr_subtype == RELAX_UNREACHABLE)))
9411 {
9412 unreach = unreach->fr_next;
9413 }
9414
9415 assert (unreach->fr_type == rs_machine_dependent
9416 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9417 || unreach->fr_subtype == RELAX_UNREACHABLE));
9418
9419 target_offset += unreach->tc_frag_data.text_expansion[0];
9420 }
e0001a05
NC		 9421 assert (gen_label == NULL);
9422 gen_label = symbol_new (FAKE_LABEL_NAME, now_seg,
43cd72b9
BW		 9423 fr_opcode - fragP->fr_literal
9424 + target_offset, fragP);
e0001a05
NC		 9425 break;
9426
9427 case ITYPE_INSN:
43cd72b9
BW		 9428 if (first && wide_insn)
9429 {
9430 target_offset += xtensa_format_length (isa, fmt);
9431 first = FALSE;
9432 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9433 target_offset += xg_get_single_size (tinsn->opcode);
9434 }
9435 else
9436 target_offset += xg_get_single_size (tinsn->opcode);
e0001a05
NC		 9437 break;
9438 }
9439 }
9440
9441 total_size = 0;
43cd72b9
BW		 9442 first = TRUE;
9443 last_is_jump = FALSE;
e0001a05
NC		 9444 for (i = 0; i < istack.ninsn; i++)
9445 {
43cd72b9 9446 TInsn *tinsn = &istack.insn[i];
e0001a05
NC		 9447 fragS *lit_frag;
9448 int size;
9449 segT target_seg;
43cd72b9 9450 bfd_reloc_code_real_type reloc_type;
e0001a05 9451
43cd72b9 9452 switch (tinsn->insn_type)
e0001a05
NC		 9453 {
9454 case ITYPE_LITERAL:
43cd72b9
BW		 9455 lit_frag = fragP->tc_frag_data.literal_frags[slot];
9456 /* Already checked. */
e0001a05
NC		 9457 assert (lit_frag != NULL);
9458 assert (lit_sym != NULL);
43cd72b9
BW		 9459 assert (tinsn->ntok == 1);
9460 /* Add a fixup. */
e0001a05
NC		 9461 target_seg = S_GET_SEGMENT (lit_sym);
9462 assert (target_seg);
bbdd25a8 9463 reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op);
e0001a05 9464 fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
43cd72b9 9465 &tinsn->tok[0], FALSE, reloc_type);
e0001a05
NC		 9466 break;
9467
9468 case ITYPE_LABEL:
9469 break;
9470
9471 case ITYPE_INSN:
43cd72b9
BW		 9472 xg_resolve_labels (tinsn, gen_label);
9473 xg_resolve_literals (tinsn, lit_sym);
9474 if (wide_insn && first)
9475 {
9476 first = FALSE;
9477 if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9478 {
b5e4a23d 9479 cur_vinsn.slots[slot] = *tinsn;
43cd72b9
BW		 9480 }
9481 else
9482 {
b5e4a23d 9483 cur_vinsn.slots[slot].opcode =
43cd72b9 9484 xtensa_format_slot_nop_opcode (isa, fmt, slot);
b5e4a23d 9485 cur_vinsn.slots[slot].ntok = 0;
43cd72b9 9486 }
b5e4a23d
BW		 9487 vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE);
9488 xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf,
d77b99c9 9489 (unsigned char *) immed_instr, 0);
43cd72b9
BW		 9490 fragP->tc_frag_data.is_insn = TRUE;
9491 size = xtensa_format_length (isa, fmt);
9492 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9493 {
43cd72b9 9494 xg_emit_insn_to_buf
b2d179be 9495 (tinsn, immed_instr + size, fragP,
43cd72b9
BW		 9496 immed_instr - fragP->fr_literal + size, TRUE);
9497 size += xg_get_single_size (tinsn->opcode);
9498 }
9499 }
9500 else
9501 {
43cd72b9 9502 size = xg_get_single_size (tinsn->opcode);
b2d179be 9503 xg_emit_insn_to_buf (tinsn, immed_instr, fragP,
43cd72b9 9504 immed_instr - fragP->fr_literal, TRUE);
43cd72b9 9505 }
e0001a05 9506 immed_instr += size;
43cd72b9 9507 total_size += size;
e0001a05
NC		 9508 break;
9509 }
9510 }
9511
9512 diff = total_size - old_size;
9513 assert (diff >= 0);
9514 if (diff != 0)
9515 expanded = TRUE;
9516 assert (diff <= fragP->fr_var);
9517 fragP->fr_var -= diff;
9518 fragP->fr_fix += diff;
9519 }
9520
e0001a05 9521 /* Check for undefined immediates in LOOP instructions. */
43cd72b9 9522 if (is_loop)
e0001a05
NC		 9523 {
9524 symbolS *sym;
43cd72b9 9525 sym = orig_tinsn.tok[1].X_add_symbol;
e0001a05
NC		 9526 if (sym != NULL && !S_IS_DEFINED (sym))
9527 {
9528 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9529 return;
9530 }
43cd72b9 9531 sym = orig_tinsn.tok[1].X_op_symbol;
e0001a05
NC		 9532 if (sym != NULL && !S_IS_DEFINED (sym))
9533 {
9534 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9535 return;
9536 }
9537 }
9538
43cd72b9
BW		 9539 if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1)
9540 convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn);
e0001a05 9541
43cd72b9 9542 if (expanded && is_direct_call_opcode (orig_tinsn.opcode))
e0001a05
NC		 9543 {
9544 /* Add an expansion note on the expanded instruction. */
9545 fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
43cd72b9 9546 &orig_tinsn.tok[0], TRUE,
e0001a05 9547 BFD_RELOC_XTENSA_ASM_EXPAND);
e0001a05
NC		 9548 }
9549}
9550
9551
9552/* Add a new fix expression into the desired segment. We have to
9553 switch to that segment to do this. */
9554
9555static fixS *
7fa3d080
BW		 9556fix_new_exp_in_seg (segT new_seg,
9557 subsegT new_subseg,
9558 fragS *frag,
9559 int where,
9560 int size,
9561 expressionS *exp,
9562 int pcrel,
9563 bfd_reloc_code_real_type r_type)
e0001a05
NC		 9564{
9565 fixS *new_fix;
9566 segT seg = now_seg;
9567 subsegT subseg = now_subseg;
43cd72b9 9568
e0001a05
NC		 9569 assert (new_seg != 0);
9570 subseg_set (new_seg, new_subseg);
9571
e0001a05
NC		 9572 new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
9573 subseg_set (seg, subseg);
9574 return new_fix;
9575}
9576
9577
43cd72b9
BW		 9578/* Relax a loop instruction so that it can span loop >256 bytes.
9579
9580 loop as, .L1
9581 .L0:
9582 rsr as, LEND
9583 wsr as, LBEG
9584 addi as, as, lo8 (label-.L1)
9585 addmi as, as, mid8 (label-.L1)
9586 wsr as, LEND
9587 isync
9588 rsr as, LCOUNT
9589 addi as, as, 1
9590 .L1:
9591 <<body>>
9592 label:
9593*/
e0001a05
NC		 9594
9595static void
7fa3d080 9596convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn)
e0001a05
NC		 9597{
9598 TInsn loop_insn;
9599 TInsn addi_insn;
9600 TInsn addmi_insn;
9601 unsigned long target;
9602 static xtensa_insnbuf insnbuf = NULL;
9603 unsigned int loop_length, loop_length_hi, loop_length_lo;
9604 xtensa_isa isa = xtensa_default_isa;
9605 addressT loop_offset;
9606 addressT addi_offset = 9;
9607 addressT addmi_offset = 12;
43cd72b9 9608 fragS *next_fragP;
d77b99c9 9609 int target_count;
e0001a05
NC		 9610
9611 if (!insnbuf)
9612 insnbuf = xtensa_insnbuf_alloc (isa);
9613
9614 /* Get the loop offset. */
43cd72b9 9615 loop_offset = get_expanded_loop_offset (tinsn->opcode);
e0001a05 9616
43cd72b9
BW		 9617 /* Validate that there really is a LOOP at the loop_offset. Because
9618 loops are not bundleable, we can assume that the instruction will be
9619 in slot 0. */
9620 tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0);
9621 tinsn_immed_from_frag (&loop_insn, fragP, 0);
9622
9623 assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1);
e0001a05
NC		 9624 addi_offset += loop_offset;
9625 addmi_offset += loop_offset;
9626
43cd72b9 9627 assert (tinsn->ntok == 2);
b08b5071
BW		 9628 if (tinsn->tok[1].X_op == O_constant)
9629 target = tinsn->tok[1].X_add_number;
9630 else if (tinsn->tok[1].X_op == O_symbol)
9631 {
9632 /* Find the fragment. */
9633 symbolS *sym = tinsn->tok[1].X_add_symbol;
9634 assert (S_GET_SEGMENT (sym) == segP
9635 || S_GET_SEGMENT (sym) == absolute_section);
9636 target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number);
9637 }
9638 else
9639 {
9640 as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op);
9641 target = 0;
9642 }
e0001a05 9643
e0001a05
NC		 9644 loop_length = target - (fragP->fr_address + fragP->fr_fix);
9645 loop_length_hi = loop_length & ~0x0ff;
9646 loop_length_lo = loop_length & 0x0ff;
9647 if (loop_length_lo >= 128)
9648 {
9649 loop_length_lo -= 256;
9650 loop_length_hi += 256;
9651 }
9652
43cd72b9 9653 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
e0001a05
NC		 9654 32512. If the loop is larger than that, then we just fail. */
9655 if (loop_length_hi > 32512)
9656 as_bad_where (fragP->fr_file, fragP->fr_line,
9657 _("loop too long for LOOP instruction"));
9658
43cd72b9 9659 tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0);
e0001a05
NC		 9660 assert (addi_insn.opcode == xtensa_addi_opcode);
9661
43cd72b9 9662 tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0);
e0001a05
NC		 9663 assert (addmi_insn.opcode == xtensa_addmi_opcode);
9664
9665 set_expr_const (&addi_insn.tok[2], loop_length_lo);
9666 tinsn_to_insnbuf (&addi_insn, insnbuf);
43cd72b9 9667
e0001a05 9668 fragP->tc_frag_data.is_insn = TRUE;
d77b99c9
BW		 9669 xtensa_insnbuf_to_chars
9670 (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0);
e0001a05
NC		 9671
9672 set_expr_const (&addmi_insn.tok[2], loop_length_hi);
9673 tinsn_to_insnbuf (&addmi_insn, insnbuf);
d77b99c9
BW		 9674 xtensa_insnbuf_to_chars
9675 (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0);
43cd72b9
BW		 9676
9677 /* Walk through all of the frags from here to the loop end
9678 and mark them as no_transform to keep them from being modified
9679 by the linker. If we ever have a relocation for the
9680 addi/addmi of the difference of two symbols we can remove this. */
9681
9682 target_count = 0;
9683 for (next_fragP = fragP; next_fragP != NULL;
9684 next_fragP = next_fragP->fr_next)
9685 {
b08b5071 9686 next_fragP->tc_frag_data.is_no_transform = TRUE;
43cd72b9
BW		 9687 if (next_fragP->tc_frag_data.is_loop_target)
9688 target_count++;
9689 if (target_count == 2)
9690 break;
9691 }
e0001a05
NC		 9692}
9693
b08b5071
BW		 9694\f
9695/* A map that keeps information on a per-subsegment basis. This is
9696 maintained during initial assembly, but is invalid once the
9697 subsegments are smashed together. I.E., it cannot be used during
9698 the relaxation. */
e0001a05 9699
b08b5071 9700typedef struct subseg_map_struct
e0001a05 9701{
b08b5071
BW		 9702 /* the key */
9703 segT seg;
9704 subsegT subseg;
e0001a05 9705
b08b5071
BW		 9706 /* the data */
9707 unsigned flags;
9708 float total_freq; /* fall-through + branch target frequency */
9709 float target_freq; /* branch target frequency alone */
9710
9711 struct subseg_map_struct *next;
9712} subseg_map;
e0001a05 9713
e0001a05 9714
e0001a05
NC		 9715static subseg_map *sseg_map = NULL;
9716
43cd72b9 9717static subseg_map *
7fa3d080 9718get_subseg_info (segT seg, subsegT subseg)
e0001a05
NC		 9719{
9720 subseg_map *subseg_e;
9721
9722 for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
e0001a05 9723 {
43cd72b9 9724 if (seg == subseg_e->seg && subseg == subseg_e->subseg)
b08b5071 9725 break;
e0001a05 9726 }
b08b5071
BW		 9727 return subseg_e;
9728}
9729
9730
9731static subseg_map *
9732add_subseg_info (segT seg, subsegT subseg)
9733{
9734 subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map));
43cd72b9
BW		 9735 memset (subseg_e, 0, sizeof (subseg_map));
9736 subseg_e->seg = seg;
9737 subseg_e->subseg = subseg;
9738 subseg_e->flags = 0;
9739 /* Start off considering every branch target very important. */
b08b5071
BW		 9740 subseg_e->target_freq = 1.0;
9741 subseg_e->total_freq = 1.0;
43cd72b9
BW		 9742 subseg_e->next = sseg_map;
9743 sseg_map = subseg_e;
43cd72b9
BW		 9744 return subseg_e;
9745}
e0001a05 9746
7fa3d080
BW		 9747
9748static unsigned
9749get_last_insn_flags (segT seg, subsegT subseg)
9750{
9751 subseg_map *subseg_e = get_subseg_info (seg, subseg);
b08b5071
BW		 9752 if (subseg_e)
9753 return subseg_e->flags;
9754 return 0;
7fa3d080
BW		 9755}
9756
9757
43cd72b9 9758static void
7fa3d080
BW		 9759set_last_insn_flags (segT seg,
9760 subsegT subseg,
9761 unsigned fl,
9762 bfd_boolean val)
43cd72b9
BW		 9763{
9764 subseg_map *subseg_e = get_subseg_info (seg, subseg);
b08b5071
BW		 9765 if (! subseg_e)
9766 subseg_e = add_subseg_info (seg, subseg);
e0001a05
NC		 9767 if (val)
9768 subseg_e->flags |= fl;
9769 else
9770 subseg_e->flags &= ~fl;
9771}
9772
b08b5071
BW		 9773
9774static float
9775get_subseg_total_freq (segT seg, subsegT subseg)
9776{
9777 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9778 if (subseg_e)
9779 return subseg_e->total_freq;
9780 return 1.0;
9781}
9782
9783
9784static float
9785get_subseg_target_freq (segT seg, subsegT subseg)
9786{
9787 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9788 if (subseg_e)
9789 return subseg_e->target_freq;
9790 return 1.0;
9791}
9792
9793
9794static void
9795set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f)
9796{
9797 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9798 if (! subseg_e)
9799 subseg_e = add_subseg_info (seg, subseg);
9800 subseg_e->total_freq = total_f;
9801 subseg_e->target_freq = target_f;
9802}
9803
e0001a05
NC		 9804\f
9805/* Segment Lists and emit_state Stuff. */
9806
e0001a05 9807static void
7fa3d080 9808xtensa_move_seg_list_to_beginning (seg_list *head)
e0001a05
NC		 9809{
9810 head = head->next;
9811 while (head)
9812 {
9813 segT literal_section = head->seg;
9814
9815 /* Move the literal section to the front of the section list. */
9816 assert (literal_section);
69852798
AM		 9817 if (literal_section != stdoutput->sections)
9818 {
9819 bfd_section_list_remove (stdoutput, literal_section);
9820 bfd_section_list_prepend (stdoutput, literal_section);
9821 }
e0001a05
NC		 9822 head = head->next;
9823 }
9824}
9825
9826
7fa3d080
BW		 9827static void mark_literal_frags (seg_list *);
9828
9829static void
9830xtensa_move_literals (void)
e0001a05
NC		 9831{
9832 seg_list *segment;
9833 frchainS *frchain_from, *frchain_to;
9834 fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after;
9835 fragS **frag_splice;
9836 emit_state state;
9837 segT dest_seg;
9838 fixS *fix, *next_fix, **fix_splice;
82e7541d 9839 sym_list *lit;
e0001a05 9840
a7877748 9841 mark_literal_frags (literal_head->next);
e0001a05
NC		 9842
9843 if (use_literal_section)
9844 return;
9845
74869ac7 9846 for (segment = literal_head->next; segment; segment = segment->next)
e0001a05 9847 {
74869ac7
BW		 9848 /* Keep the literals for .init and .fini in separate sections. */
9849 if (!strcmp (segment_name (segment->seg), INIT_SECTION_NAME)
9850 || !strcmp (segment_name (segment->seg), FINI_SECTION_NAME))
9851 continue;
9852
e0001a05
NC		 9853 frchain_from = seg_info (segment->seg)->frchainP;
9854 search_frag = frchain_from->frch_root;
9855 literal_pool = NULL;
9856 frchain_to = NULL;
9857 frag_splice = &(frchain_from->frch_root);
9858
9859 while (!search_frag->tc_frag_data.literal_frag)
9860 {
9861 assert (search_frag->fr_fix == 0
9862 || search_frag->fr_type == rs_align);
9863 search_frag = search_frag->fr_next;
9864 }
9865
9866 assert (search_frag->tc_frag_data.literal_frag->fr_subtype
9867 == RELAX_LITERAL_POOL_BEGIN);
9868 xtensa_switch_section_emit_state (&state, segment->seg, 0);
9869
9870 /* Make sure that all the frags in this series are closed, and
9871 that there is at least one left over of zero-size. This
9872 prevents us from making a segment with an frchain without any
9873 frags in it. */
9874 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 9875 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 9876 last_frag = frag_now;
9877 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 9878 xtensa_set_frag_assembly_state (frag_now);
e0001a05 9879
43cd72b9 9880 while (search_frag != frag_now)
e0001a05
NC		 9881 {
9882 next_frag = search_frag->fr_next;
9883
43cd72b9 9884 /* First, move the frag out of the literal section and
e0001a05
NC		 9885 to the appropriate place. */
9886 if (search_frag->tc_frag_data.literal_frag)
9887 {
9888 literal_pool = search_frag->tc_frag_data.literal_frag;
9889 assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN);
dd49a749
BW		 9890 frchain_to = literal_pool->tc_frag_data.lit_frchain;
9891 assert (frchain_to);
e0001a05 9892 }
c48aaca0 9893 insert_after = literal_pool->tc_frag_data.literal_frag;
dd49a749 9894 dest_seg = insert_after->fr_next->tc_frag_data.lit_seg;
43cd72b9 9895
e0001a05
NC		 9896 *frag_splice = next_frag;
9897 search_frag->fr_next = insert_after->fr_next;
9898 insert_after->fr_next = search_frag;
9899 search_frag->tc_frag_data.lit_seg = dest_seg;
c48aaca0 9900 literal_pool->tc_frag_data.literal_frag = search_frag;
e0001a05
NC		 9901
9902 /* Now move any fixups associated with this frag to the
9903 right section. */
9904 fix = frchain_from->fix_root;
9905 fix_splice = &(frchain_from->fix_root);
9906 while (fix)
9907 {
9908 next_fix = fix->fx_next;
9909 if (fix->fx_frag == search_frag)
9910 {
9911 *fix_splice = next_fix;
9912 fix->fx_next = frchain_to->fix_root;
9913 frchain_to->fix_root = fix;
9914 if (frchain_to->fix_tail == NULL)
9915 frchain_to->fix_tail = fix;
9916 }
9917 else
9918 fix_splice = &(fix->fx_next);
9919 fix = next_fix;
9920 }
9921 search_frag = next_frag;
9922 }
9923
9924 if (frchain_from->fix_root != NULL)
9925 {
9926 frchain_from = seg_info (segment->seg)->frchainP;
9927 as_warn (_("fixes not all moved from %s"), segment->seg->name);
9928
9929 assert (frchain_from->fix_root == NULL);
9930 }
9931 frchain_from->fix_tail = NULL;
9932 xtensa_restore_emit_state (&state);
e0001a05
NC		 9933 }
9934
82e7541d
BW		 9935 /* Now fix up the SEGMENT value for all the literal symbols. */
9936 for (lit = literal_syms; lit; lit = lit->next)
9937 {
9938 symbolS *lit_sym = lit->sym;
9939 segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg;
43cd72b9
BW		 9940 if (dest_seg)
9941 S_SET_SEGMENT (lit_sym, dest_seg);
82e7541d 9942 }
e0001a05
NC		 9943}
9944
9945
a7877748
BW		 9946/* Walk over all the frags for segments in a list and mark them as
9947 containing literals. As clunky as this is, we can't rely on frag_var
9948 and frag_variant to get called in all situations. */
9949
9950static void
7fa3d080 9951mark_literal_frags (seg_list *segment)
a7877748
BW		 9952{
9953 frchainS *frchain_from;
9954 fragS *search_frag;
9955
9956 while (segment)
9957 {
9958 frchain_from = seg_info (segment->seg)->frchainP;
9959 search_frag = frchain_from->frch_root;
c138bc38 9960 while (search_frag)
a7877748
BW		 9961 {
9962 search_frag->tc_frag_data.is_literal = TRUE;
9963 search_frag = search_frag->fr_next;
9964 }
9965 segment = segment->next;
9966 }
9967}
9968
9969
e0001a05 9970static void
7fa3d080 9971xtensa_reorder_seg_list (seg_list *head, segT after)
e0001a05
NC		 9972{
9973 /* Move all of the sections in the section list to come
9974 after "after" in the gnu segment list. */
9975
9976 head = head->next;
9977 while (head)
9978 {
9979 segT literal_section = head->seg;
9980
9981 /* Move the literal section after "after". */
9982 assert (literal_section);
9983 if (literal_section != after)
9984 {
69852798
AM		 9985 bfd_section_list_remove (stdoutput, literal_section);
9986 bfd_section_list_insert_after (stdoutput, after, literal_section);
e0001a05
NC		 9987 }
9988
9989 head = head->next;
9990 }
9991}
9992
9993
9994/* Push all the literal segments to the end of the gnu list. */
9995
7fa3d080
BW		 9996static void
9997xtensa_reorder_segments (void)
e0001a05
NC		 9998{
9999 segT sec;
b08b5071 10000 segT last_sec = 0;
e0001a05
NC		 10001 int old_count = 0;
10002 int new_count = 0;
10003
10004 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
b08b5071
BW		 10005 {
10006 last_sec = sec;
10007 old_count++;
10008 }
e0001a05
NC		 10009
10010 /* Now that we have the last section, push all the literal
10011 sections to the end. */
e0001a05 10012 xtensa_reorder_seg_list (literal_head, last_sec);
e0001a05
NC		 10013
10014 /* Now perform the final error check. */
10015 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
10016 new_count++;
10017 assert (new_count == old_count);
10018}
10019
10020
e0001a05
NC		 10021/* Change the emit state (seg, subseg, and frag related stuff) to the
10022 correct location. Return a emit_state which can be passed to
10023 xtensa_restore_emit_state to return to current fragment. */
10024
7fa3d080
BW		 10025static void
10026xtensa_switch_to_literal_fragment (emit_state *result)
43cd72b9
BW		 10027{
10028 if (directive_state[directive_absolute_literals])
10029 {
74869ac7
BW		 10030 segT lit4_seg = cache_literal_section (TRUE);
10031 xtensa_switch_section_emit_state (result, lit4_seg, 0);
43cd72b9
BW		 10032 }
10033 else
10034 xtensa_switch_to_non_abs_literal_fragment (result);
10035
10036 /* Do a 4-byte align here. */
10037 frag_align (2, 0, 0);
10038 record_alignment (now_seg, 2);
10039}
10040
10041
7fa3d080
BW		 10042static void
10043xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
e0001a05 10044{
e0001a05
NC		 10045 static bfd_boolean recursive = FALSE;
10046 fragS *pool_location = get_literal_pool_location (now_seg);
74869ac7 10047 segT lit_seg;
c138bc38 10048 bfd_boolean is_init =
e0001a05 10049 (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME));
c138bc38 10050 bfd_boolean is_fini =
e0001a05 10051 (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME));
e0001a05 10052
43cd72b9
BW		 10053 if (pool_location == NULL
10054 && !use_literal_section
e0001a05
NC		 10055 && !recursive
10056 && !is_init && ! is_fini)
10057 {
43cd72b9 10058 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
74869ac7
BW		 10059
10060 /* When we mark a literal pool location, we want to put a frag in
10061 the literal pool that points to it. But to do that, we want to
10062 switch_to_literal_fragment. But literal sections don't have
10063 literal pools, so their location is always null, so we would
10064 recurse forever. This is kind of hacky, but it works. */
10065
e0001a05 10066 recursive = TRUE;
61846f28 10067 xtensa_mark_literal_pool_location ();
e0001a05
NC		 10068 recursive = FALSE;
10069 }
10070
74869ac7
BW		 10071 lit_seg = cache_literal_section (FALSE);
10072 xtensa_switch_section_emit_state (result, lit_seg, 0);
e0001a05 10073
43cd72b9
BW		 10074 if (!use_literal_section
10075 && !is_init && !is_fini
10076 && get_literal_pool_location (now_seg) != pool_location)
e0001a05
NC		 10077 {
10078 /* Close whatever frag is there. */
10079 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 10080 xtensa_set_frag_assembly_state (frag_now);
e0001a05
NC		 10081 frag_now->tc_frag_data.literal_frag = pool_location;
10082 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
43cd72b9 10083 xtensa_set_frag_assembly_state (frag_now);
e0001a05 10084 }
e0001a05
NC		 10085}
10086
10087
10088/* Call this function before emitting data into the literal section.
10089 This is a helper function for xtensa_switch_to_literal_fragment.
10090 This is similar to a .section new_now_seg subseg. */
10091
7fa3d080
BW		 10092static void
10093xtensa_switch_section_emit_state (emit_state *state,
10094 segT new_now_seg,
10095 subsegT new_now_subseg)
e0001a05
NC		 10096{
10097 state->name = now_seg->name;
10098 state->now_seg = now_seg;
10099 state->now_subseg = now_subseg;
10100 state->generating_literals = generating_literals;
10101 generating_literals++;
2b0210eb 10102 subseg_set (new_now_seg, new_now_subseg);
e0001a05
NC		 10103}
10104
10105
10106/* Use to restore the emitting into the normal place. */
10107
7fa3d080
BW		 10108static void
10109xtensa_restore_emit_state (emit_state *state)
e0001a05
NC		 10110{
10111 generating_literals = state->generating_literals;
2b0210eb 10112 subseg_set (state->now_seg, state->now_subseg);
e0001a05
NC		 10113}
10114
10115
74869ac7 10116/* Predicate function used to look up a section in a particular group. */
e0001a05 10117
74869ac7
BW		 10118static bfd_boolean
10119match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf)
e0001a05 10120{
74869ac7
BW		 10121 const char *gname = inf;
10122 const char *group_name = elf_group_name (sec);
10123
10124 return (group_name == gname
10125 || (group_name != NULL
10126 && gname != NULL
10127 && strcmp (group_name, gname) == 0));
10128}
e0001a05 10129
e0001a05 10130
74869ac7
BW		 10131/* Get the literal section to be used for the current text section.
10132 The result may be cached in the default_lit_sections structure. */
10133
10134static segT
10135cache_literal_section (bfd_boolean use_abs_literals)
10136{
10137 const char *text_name, *group_name = 0;
10138 char *base_name, *name, *suffix;
10139 segT *pcached;
10140 segT seg, current_section;
10141 int current_subsec;
10142 bfd_boolean linkonce = FALSE;
10143
10144 /* Save the current section/subsection. */
10145 current_section = now_seg;
10146 current_subsec = now_subseg;
10147
10148 /* Clear the cached values if they are no longer valid. */
10149 if (now_seg != default_lit_sections.current_text_seg)
b08b5071 10150 {
74869ac7
BW		 10151 default_lit_sections.current_text_seg = now_seg;
10152 default_lit_sections.lit_seg = NULL;
10153 default_lit_sections.lit4_seg = NULL;
10154 }
10155
10156 /* Check if the literal section is already cached. */
10157 if (use_abs_literals)
10158 pcached = &default_lit_sections.lit4_seg;
10159 else
10160 pcached = &default_lit_sections.lit_seg;
10161
10162 if (*pcached)
10163 return *pcached;
10164
10165 text_name = default_lit_sections.lit_prefix;
10166 if (! text_name || ! *text_name)
10167 {
10168 text_name = segment_name (current_section);
10169 group_name = elf_group_name (current_section);
10170 linkonce = (current_section->flags & SEC_LINK_ONCE) != 0;
10171 }
10172
10173 base_name = use_abs_literals ? ".lit4" : ".literal";
10174 if (group_name)
10175 {
10176 name = xmalloc (strlen (base_name) + strlen (group_name) + 2);
10177 sprintf (name, "%s.%s", base_name, group_name);
10178 }
10179 else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0)
10180 {
10181 suffix = strchr (text_name + linkonce_len, '.');
10182
10183 name = xmalloc (linkonce_len + strlen (base_name) + 1
10184 + (suffix ? strlen (suffix) : 0));
10185 strcpy (name, ".gnu.linkonce");
10186 strcat (name, base_name);
10187 if (suffix)
10188 strcat (name, suffix);
10189 linkonce = TRUE;
10190 }
10191 else
10192 {
10193 /* If the section name ends with ".text", then replace that suffix
10194 instead of appending an additional suffix. */
10195 size_t len = strlen (text_name);
10196 if (len >= 5 && strcmp (text_name + len - 5, ".text") == 0)
10197 len -= 5;
10198
10199 name = xmalloc (len + strlen (base_name) + 1);
10200 strcpy (name, text_name);
10201 strcpy (name + len, base_name);
b08b5071 10202 }
e0001a05 10203
74869ac7
BW		 10204 /* Canonicalize section names to allow renaming literal sections.
10205 The group name, if any, came from the current text section and
10206 has already been canonicalized. */
10207 name = tc_canonicalize_symbol_name (name);
10208
10209 seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group,
10210 (void *) group_name);
10211 if (! seg)
e0001a05 10212 {
74869ac7
BW		 10213 flagword flags;
10214
10215 seg = subseg_force_new (name, 0);
10216
10217 if (! use_abs_literals)
b08b5071 10218 {
74869ac7 10219 /* Add the newly created literal segment to the list. */
b08b5071
BW		 10220 seg_list *n = (seg_list *) xmalloc (sizeof (seg_list));
10221 n->seg = seg;
74869ac7
BW		 10222 n->next = literal_head->next;
10223 literal_head->next = n;
b08b5071 10224 }
74869ac7
BW		 10225
10226 flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD
10227 | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0)
10228 | (use_abs_literals ? SEC_DATA : SEC_CODE));
10229
10230 elf_group_name (seg) = group_name;
10231
10232 bfd_set_section_flags (stdoutput, seg, flags);
b08b5071 10233 bfd_set_section_alignment (stdoutput, seg, 2);
e0001a05
NC		 10234 }
10235
74869ac7 10236 *pcached = seg;
b08b5071 10237 subseg_set (current_section, current_subsec);
74869ac7 10238 return seg;
e0001a05
NC		 10239}
10240
43cd72b9
BW		 10241\f
10242/* Property Tables Stuff. */
10243
7fa3d080
BW		 10244#define XTENSA_INSN_SEC_NAME ".xt.insn"
10245#define XTENSA_LIT_SEC_NAME ".xt.lit"
10246#define XTENSA_PROP_SEC_NAME ".xt.prop"
10247
10248typedef bfd_boolean (*frag_predicate) (const fragS *);
10249typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
10250
b08b5071 10251static bfd_boolean get_frag_is_literal (const fragS *);
7fa3d080
BW		 10252static void xtensa_create_property_segments
10253 (frag_predicate, frag_predicate, const char *, xt_section_type);
10254static void xtensa_create_xproperty_segments
10255 (frag_flags_fn, const char *, xt_section_type);
10256static segment_info_type *retrieve_segment_info (segT);
7fa3d080
BW		 10257static bfd_boolean section_has_property (segT, frag_predicate);
10258static bfd_boolean section_has_xproperty (segT, frag_flags_fn);
10259static void add_xt_block_frags
10260 (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate);
10261static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *);
10262static void xtensa_frag_flags_init (frag_flags *);
10263static void get_frag_property_flags (const fragS *, frag_flags *);
10264static bfd_vma frag_flags_to_number (const frag_flags *);
10265static void add_xt_prop_frags
10266 (segT, segT, xtensa_block_info **, frag_flags_fn);
10267
10268/* Set up property tables after relaxation. */
10269
10270void
10271xtensa_post_relax_hook (void)
10272{
10273 xtensa_move_seg_list_to_beginning (literal_head);
7fa3d080
BW		 10274
10275 xtensa_find_unmarked_state_frags ();
99ded152 10276 xtensa_mark_frags_for_org ();
6a7eedfe 10277 xtensa_mark_difference_of_two_symbols ();
7fa3d080 10278
b29757dc
BW		 10279 xtensa_create_property_segments (get_frag_is_literal,
10280 NULL,
10281 XTENSA_LIT_SEC_NAME,
10282 xt_literal_sec);
7fa3d080
BW		 10283 xtensa_create_xproperty_segments (get_frag_property_flags,
10284 XTENSA_PROP_SEC_NAME,
10285 xt_prop_sec);
10286
10287 if (warn_unaligned_branch_targets)
10288 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0);
10289 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0);
10290}
10291
10292
43cd72b9
BW		 10293/* This function is only meaningful after xtensa_move_literals. */
10294
10295static bfd_boolean
7fa3d080 10296get_frag_is_literal (const fragS *fragP)
43cd72b9
BW		 10297{
10298 assert (fragP != NULL);
10299 return fragP->tc_frag_data.is_literal;
10300}
10301
10302
43cd72b9 10303static void
7fa3d080
BW		 10304xtensa_create_property_segments (frag_predicate property_function,
10305 frag_predicate end_property_function,
10306 const char *section_name_base,
10307 xt_section_type sec_type)
43cd72b9
BW		 10308{
10309 segT *seclist;
10310
10311 /* Walk over all of the current segments.
10312 Walk over each fragment
10313 For each non-empty fragment,
10314 Build a property record (append where possible). */
10315
10316 for (seclist = &stdoutput->sections;
10317 seclist && *seclist;
10318 seclist = &(*seclist)->next)
10319 {
10320 segT sec = *seclist;
10321 flagword flags;
10322
10323 flags = bfd_get_section_flags (stdoutput, sec);
10324 if (flags & SEC_DEBUGGING)
10325 continue;
10326 if (!(flags & SEC_ALLOC))
10327 continue;
10328
10329 if (section_has_property (sec, property_function))
10330 {
74869ac7
BW		 10331 segT insn_sec =
10332 xtensa_get_property_section (sec, section_name_base);
43cd72b9
BW		 10333 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
10334 xtensa_block_info **xt_blocks =
10335 &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10336 /* Walk over all of the frchains here and add new sections. */
10337 add_xt_block_frags (sec, insn_sec, xt_blocks, property_function,
10338 end_property_function);
10339 }
10340 }
10341
10342 /* Now we fill them out.... */
10343
10344 for (seclist = &stdoutput->sections;
10345 seclist && *seclist;
10346 seclist = &(*seclist)->next)
10347 {
10348 segment_info_type *seginfo;
10349 xtensa_block_info *block;
10350 segT sec = *seclist;
10351
10352 seginfo = seg_info (sec);
10353 block = seginfo->tc_segment_info_data.blocks[sec_type];
10354
10355 if (block)
10356 {
10357 xtensa_block_info *cur_block;
10358 /* This is a section with some data. */
10359 int num_recs = 0;
d77b99c9 10360 bfd_size_type rec_size;
43cd72b9
BW		 10361
10362 for (cur_block = block; cur_block; cur_block = cur_block->next)
10363 num_recs++;
10364
10365 rec_size = num_recs * 8;
10366 bfd_set_section_size (stdoutput, sec, rec_size);
10367
10368 /* In order to make this work with the assembler, we have to
10369 build some frags and then build the "fixups" for it. It
10370 would be easier to just set the contents then set the
10371 arlents. */
10372
10373 if (num_recs)
10374 {
10375 /* Allocate a fragment and leak it. */
10376 fragS *fragP;
d77b99c9 10377 bfd_size_type frag_size;
43cd72b9
BW		 10378 fixS *fixes;
10379 frchainS *frchainP;
10380 int i;
10381 char *frag_data;
10382
10383 frag_size = sizeof (fragS) + rec_size;
10384 fragP = (fragS *) xmalloc (frag_size);
e0001a05 10385
43cd72b9
BW		 10386 memset (fragP, 0, frag_size);
10387 fragP->fr_address = 0;
10388 fragP->fr_next = NULL;
10389 fragP->fr_fix = rec_size;
10390 fragP->fr_var = 0;
10391 fragP->fr_type = rs_fill;
10392 /* The rest are zeros. */
e0001a05 10393
43cd72b9
BW		 10394 frchainP = seginfo->frchainP;
10395 frchainP->frch_root = fragP;
10396 frchainP->frch_last = fragP;
e0001a05 10397
43cd72b9
BW		 10398 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
10399 memset (fixes, 0, sizeof (fixS) * num_recs);
e0001a05 10400
43cd72b9
BW		 10401 seginfo->fix_root = fixes;
10402 seginfo->fix_tail = &fixes[num_recs - 1];
10403 cur_block = block;
10404 frag_data = &fragP->fr_literal[0];
10405 for (i = 0; i < num_recs; i++)
10406 {
10407 fixS *fix = &fixes[i];
10408 assert (cur_block);
e0001a05 10409
43cd72b9
BW		 10410 /* Write the fixup. */
10411 if (i != num_recs - 1)
10412 fix->fx_next = &fixes[i + 1];
10413 else
10414 fix->fx_next = NULL;
10415 fix->fx_size = 4;
10416 fix->fx_done = 0;
10417 fix->fx_frag = fragP;
10418 fix->fx_where = i * 8;
10419 fix->fx_addsy = section_symbol (cur_block->sec);
10420 fix->fx_offset = cur_block->offset;
10421 fix->fx_r_type = BFD_RELOC_32;
10422 fix->fx_file = "Internal Assembly";
10423 fix->fx_line = 0;
e0001a05 10424
43cd72b9
BW		 10425 /* Write the length. */
10426 md_number_to_chars (&frag_data[4 + 8 * i],
10427 cur_block->size, 4);
10428 cur_block = cur_block->next;
10429 }
10430 }
10431 }
10432 }
e0001a05
NC		 10433}
10434
10435
7fa3d080
BW		 10436static void
10437xtensa_create_xproperty_segments (frag_flags_fn flag_fn,
10438 const char *section_name_base,
10439 xt_section_type sec_type)
e0001a05
NC		 10440{
10441 segT *seclist;
10442
10443 /* Walk over all of the current segments.
43cd72b9
BW		 10444 Walk over each fragment.
10445 For each fragment that has instructions,
10446 build an instruction record (append where possible). */
e0001a05
NC		 10447
10448 for (seclist = &stdoutput->sections;
10449 seclist && *seclist;
10450 seclist = &(*seclist)->next)
10451 {
10452 segT sec = *seclist;
43cd72b9
BW		 10453 flagword flags;
10454
10455 flags = bfd_get_section_flags (stdoutput, sec);
6624cbde
BW		 10456 if ((flags & SEC_DEBUGGING)
10457 || !(flags & SEC_ALLOC)
10458 || (flags & SEC_MERGE))
43cd72b9
BW		 10459 continue;
10460
10461 if (section_has_xproperty (sec, flag_fn))
e0001a05 10462 {
74869ac7
BW		 10463 segT insn_sec =
10464 xtensa_get_property_section (sec, section_name_base);
e0001a05 10465 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
43cd72b9 10466 xtensa_block_info **xt_blocks =
e0001a05
NC		 10467 &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10468 /* Walk over all of the frchains here and add new sections. */
43cd72b9 10469 add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn);
e0001a05
NC		 10470 }
10471 }
10472
10473 /* Now we fill them out.... */
10474
10475 for (seclist = &stdoutput->sections;
10476 seclist && *seclist;
10477 seclist = &(*seclist)->next)
10478 {
10479 segment_info_type *seginfo;
10480 xtensa_block_info *block;
10481 segT sec = *seclist;
43cd72b9 10482
e0001a05
NC		 10483 seginfo = seg_info (sec);
10484 block = seginfo->tc_segment_info_data.blocks[sec_type];
10485
10486 if (block)
10487 {
10488 xtensa_block_info *cur_block;
10489 /* This is a section with some data. */
43cd72b9 10490 int num_recs = 0;
d77b99c9 10491 bfd_size_type rec_size;
e0001a05
NC		 10492
10493 for (cur_block = block; cur_block; cur_block = cur_block->next)
10494 num_recs++;
10495
43cd72b9 10496 rec_size = num_recs * (8 + 4);
e0001a05
NC		 10497 bfd_set_section_size (stdoutput, sec, rec_size);
10498
43cd72b9
BW		 10499 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10500
10501 /* In order to make this work with the assembler, we have to build
10502 some frags then build the "fixups" for it. It would be easier to
10503 just set the contents then set the arlents. */
e0001a05
NC		 10504
10505 if (num_recs)
10506 {
43cd72b9 10507 /* Allocate a fragment and (unfortunately) leak it. */
e0001a05 10508 fragS *fragP;
d77b99c9 10509 bfd_size_type frag_size;
e0001a05
NC		 10510 fixS *fixes;
10511 frchainS *frchainP;
43cd72b9 10512 int i;
e0001a05
NC		 10513 char *frag_data;
10514
10515 frag_size = sizeof (fragS) + rec_size;
10516 fragP = (fragS *) xmalloc (frag_size);
10517
10518 memset (fragP, 0, frag_size);
10519 fragP->fr_address = 0;
10520 fragP->fr_next = NULL;
10521 fragP->fr_fix = rec_size;
10522 fragP->fr_var = 0;
10523 fragP->fr_type = rs_fill;
43cd72b9 10524 /* The rest are zeros. */
e0001a05
NC		 10525
10526 frchainP = seginfo->frchainP;
10527 frchainP->frch_root = fragP;
10528 frchainP->frch_last = fragP;
10529
10530 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
10531 memset (fixes, 0, sizeof (fixS) * num_recs);
10532
10533 seginfo->fix_root = fixes;
10534 seginfo->fix_tail = &fixes[num_recs - 1];
10535 cur_block = block;
10536 frag_data = &fragP->fr_literal[0];
10537 for (i = 0; i < num_recs; i++)
10538 {
10539 fixS *fix = &fixes[i];
10540 assert (cur_block);
10541
10542 /* Write the fixup. */
10543 if (i != num_recs - 1)
10544 fix->fx_next = &fixes[i + 1];
10545 else
10546 fix->fx_next = NULL;
10547 fix->fx_size = 4;
10548 fix->fx_done = 0;
10549 fix->fx_frag = fragP;
43cd72b9 10550 fix->fx_where = i * (8 + 4);
e0001a05
NC		 10551 fix->fx_addsy = section_symbol (cur_block->sec);
10552 fix->fx_offset = cur_block->offset;
10553 fix->fx_r_type = BFD_RELOC_32;
10554 fix->fx_file = "Internal Assembly";
10555 fix->fx_line = 0;
10556
10557 /* Write the length. */
43cd72b9 10558 md_number_to_chars (&frag_data[4 + (8+4) * i],
e0001a05 10559 cur_block->size, 4);
43cd72b9
BW		 10560 md_number_to_chars (&frag_data[8 + (8+4) * i],
10561 frag_flags_to_number (&cur_block->flags),
10562 4);
e0001a05
NC		 10563 cur_block = cur_block->next;
10564 }
10565 }
10566 }
10567 }
10568}
10569
10570
7fa3d080
BW		 10571static segment_info_type *
10572retrieve_segment_info (segT seg)
e0001a05
NC		 10573{
10574 segment_info_type *seginfo;
10575 seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg);
10576 if (!seginfo)
10577 {
10578 frchainS *frchainP;
10579
10580 seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
7fa3d080 10581 memset ((void *) seginfo, 0, sizeof (*seginfo));
e0001a05
NC		 10582 seginfo->fix_root = NULL;
10583 seginfo->fix_tail = NULL;
10584 seginfo->bfd_section = seg;
10585 seginfo->sym = 0;
10586 /* We will not be dealing with these, only our special ones. */
65ec77d2 10587 bfd_set_section_userdata (stdoutput, seg, (void *) seginfo);
e0001a05
NC		 10588
10589 frchainP = (frchainS *) xmalloc (sizeof (frchainS));
10590 frchainP->frch_root = NULL;
10591 frchainP->frch_last = NULL;
10592 frchainP->frch_next = NULL;
e0001a05
NC		 10593 frchainP->frch_subseg = 0;
10594 frchainP->fix_root = NULL;
10595 frchainP->fix_tail = NULL;
10596 /* Do not init the objstack. */
10597 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10598 /* frchainP->frch_frag_now = fragP; */
10599 frchainP->frch_frag_now = NULL;
10600
10601 seginfo->frchainP = frchainP;
10602 }
10603
10604 return seginfo;
10605}
10606
10607
7fa3d080
BW		 10608static bfd_boolean
10609section_has_property (segT sec, frag_predicate property_function)
e0001a05
NC		 10610{
10611 segment_info_type *seginfo = seg_info (sec);
10612 fragS *fragP;
10613
10614 if (seginfo && seginfo->frchainP)
10615 {
10616 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10617 {
10618 if (property_function (fragP)
10619 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10620 return TRUE;
10621 }
10622 }
10623 return FALSE;
10624}
10625
10626
7fa3d080
BW		 10627static bfd_boolean
10628section_has_xproperty (segT sec, frag_flags_fn property_function)
43cd72b9
BW		 10629{
10630 segment_info_type *seginfo = seg_info (sec);
10631 fragS *fragP;
10632
10633 if (seginfo && seginfo->frchainP)
10634 {
10635 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10636 {
10637 frag_flags prop_flags;
10638 property_function (fragP, &prop_flags);
10639 if (!xtensa_frag_flags_is_empty (&prop_flags))
10640 return TRUE;
10641 }
10642 }
10643 return FALSE;
10644}
10645
10646
e0001a05
NC		 10647/* Two types of block sections exist right now: literal and insns. */
10648
7fa3d080
BW		 10649static void
10650add_xt_block_frags (segT sec,
10651 segT xt_block_sec,
10652 xtensa_block_info **xt_block,
10653 frag_predicate property_function,
10654 frag_predicate end_property_function)
e0001a05
NC		 10655{
10656 segment_info_type *seg_info;
10657 segment_info_type *xt_seg_info;
10658 bfd_vma seg_offset;
10659 fragS *fragP;
10660
10661 xt_seg_info = retrieve_segment_info (xt_block_sec);
10662 seg_info = retrieve_segment_info (sec);
10663
10664 /* Build it if needed. */
10665 while (*xt_block != NULL)
10666 xt_block = &(*xt_block)->next;
10667 /* We are either at NULL at the beginning or at the end. */
10668
10669 /* Walk through the frags. */
10670 seg_offset = 0;
10671
10672 if (seg_info->frchainP)
10673 {
10674 for (fragP = seg_info->frchainP->frch_root;
10675 fragP;
10676 fragP = fragP->fr_next)
10677 {
10678 if (property_function (fragP)
10679 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10680 {
10681 if (*xt_block != NULL)
10682 {
10683 if ((*xt_block)->offset + (*xt_block)->size
10684 == fragP->fr_address)
10685 (*xt_block)->size += fragP->fr_fix;
10686 else
10687 xt_block = &((*xt_block)->next);
10688 }
10689 if (*xt_block == NULL)
10690 {
43cd72b9
BW		 10691 xtensa_block_info *new_block = (xtensa_block_info *)
10692 xmalloc (sizeof (xtensa_block_info));
10693 new_block->sec = sec;
10694 new_block->offset = fragP->fr_address;
10695 new_block->size = fragP->fr_fix;
10696 new_block->next = NULL;
10697 xtensa_frag_flags_init (&new_block->flags);
10698 *xt_block = new_block;
10699 }
10700 if (end_property_function
10701 && end_property_function (fragP))
10702 {
10703 xt_block = &((*xt_block)->next);
10704 }
10705 }
10706 }
10707 }
10708}
10709
10710
10711/* Break the encapsulation of add_xt_prop_frags here. */
10712
7fa3d080
BW		 10713static bfd_boolean
10714xtensa_frag_flags_is_empty (const frag_flags *prop_flags)
43cd72b9
BW		 10715{
10716 if (prop_flags->is_literal
10717 || prop_flags->is_insn
10718 || prop_flags->is_data
10719 || prop_flags->is_unreachable)
10720 return FALSE;
10721 return TRUE;
10722}
10723
10724
7fa3d080
BW		 10725static void
10726xtensa_frag_flags_init (frag_flags *prop_flags)
43cd72b9
BW		 10727{
10728 memset (prop_flags, 0, sizeof (frag_flags));
10729}
10730
10731
7fa3d080
BW		 10732static void
10733get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
43cd72b9
BW		 10734{
10735 xtensa_frag_flags_init (prop_flags);
10736 if (fragP->tc_frag_data.is_literal)
10737 prop_flags->is_literal = TRUE;
99ded152
BW		 10738 if (fragP->tc_frag_data.is_specific_opcode
10739 || fragP->tc_frag_data.is_no_transform)
10740 prop_flags->is_no_transform = TRUE;
43cd72b9 10741 if (fragP->tc_frag_data.is_unreachable)
7fa3d080 10742 prop_flags->is_unreachable = TRUE;
43cd72b9
BW		 10743 else if (fragP->tc_frag_data.is_insn)
10744 {
10745 prop_flags->is_insn = TRUE;
10746 if (fragP->tc_frag_data.is_loop_target)
10747 prop_flags->insn.is_loop_target = TRUE;
10748 if (fragP->tc_frag_data.is_branch_target)
10749 prop_flags->insn.is_branch_target = TRUE;
43cd72b9
BW		 10750 if (fragP->tc_frag_data.is_no_density)
10751 prop_flags->insn.is_no_density = TRUE;
10752 if (fragP->tc_frag_data.use_absolute_literals)
10753 prop_flags->insn.is_abslit = TRUE;
10754 }
10755 if (fragP->tc_frag_data.is_align)
10756 {
10757 prop_flags->is_align = TRUE;
10758 prop_flags->alignment = fragP->tc_frag_data.alignment;
10759 if (xtensa_frag_flags_is_empty (prop_flags))
10760 prop_flags->is_data = TRUE;
10761 }
10762}
10763
10764
7fa3d080
BW		 10765static bfd_vma
10766frag_flags_to_number (const frag_flags *prop_flags)
43cd72b9
BW		 10767{
10768 bfd_vma num = 0;
10769 if (prop_flags->is_literal)
10770 num |= XTENSA_PROP_LITERAL;
10771 if (prop_flags->is_insn)
10772 num |= XTENSA_PROP_INSN;
10773 if (prop_flags->is_data)
10774 num |= XTENSA_PROP_DATA;
10775 if (prop_flags->is_unreachable)
10776 num |= XTENSA_PROP_UNREACHABLE;
10777 if (prop_flags->insn.is_loop_target)
10778 num |= XTENSA_PROP_INSN_LOOP_TARGET;
10779 if (prop_flags->insn.is_branch_target)
10780 {
10781 num |= XTENSA_PROP_INSN_BRANCH_TARGET;
10782 num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority);
10783 }
10784
10785 if (prop_flags->insn.is_no_density)
10786 num |= XTENSA_PROP_INSN_NO_DENSITY;
99ded152
BW		 10787 if (prop_flags->is_no_transform)
10788 num |= XTENSA_PROP_NO_TRANSFORM;
43cd72b9
BW		 10789 if (prop_flags->insn.is_no_reorder)
10790 num |= XTENSA_PROP_INSN_NO_REORDER;
10791 if (prop_flags->insn.is_abslit)
10792 num |= XTENSA_PROP_INSN_ABSLIT;
10793
10794 if (prop_flags->is_align)
10795 {
10796 num |= XTENSA_PROP_ALIGN;
10797 num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment);
10798 }
10799
10800 return num;
10801}
10802
10803
10804static bfd_boolean
7fa3d080
BW		 10805xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
10806 const frag_flags *prop_flags_2)
43cd72b9
BW		 10807{
10808 /* Cannot combine with an end marker. */
10809
10810 if (prop_flags_1->is_literal != prop_flags_2->is_literal)
10811 return FALSE;
10812 if (prop_flags_1->is_insn != prop_flags_2->is_insn)
10813 return FALSE;
10814 if (prop_flags_1->is_data != prop_flags_2->is_data)
10815 return FALSE;
10816
10817 if (prop_flags_1->is_insn)
10818 {
10819 /* Properties of the beginning of the frag. */
10820 if (prop_flags_2->insn.is_loop_target)
10821 return FALSE;
10822 if (prop_flags_2->insn.is_branch_target)
10823 return FALSE;
10824 if (prop_flags_1->insn.is_no_density !=
10825 prop_flags_2->insn.is_no_density)
10826 return FALSE;
99ded152
BW		 10827 if (prop_flags_1->is_no_transform !=
10828 prop_flags_2->is_no_transform)
43cd72b9
BW		 10829 return FALSE;
10830 if (prop_flags_1->insn.is_no_reorder !=
10831 prop_flags_2->insn.is_no_reorder)
10832 return FALSE;
10833 if (prop_flags_1->insn.is_abslit !=
10834 prop_flags_2->insn.is_abslit)
10835 return FALSE;
10836 }
10837
10838 if (prop_flags_1->is_align)
10839 return FALSE;
10840
10841 return TRUE;
10842}
10843
10844
7fa3d080
BW		 10845static bfd_vma
10846xt_block_aligned_size (const xtensa_block_info *xt_block)
43cd72b9
BW		 10847{
10848 bfd_vma end_addr;
d77b99c9 10849 unsigned align_bits;
43cd72b9
BW		 10850
10851 if (!xt_block->flags.is_align)
10852 return xt_block->size;
10853
10854 end_addr = xt_block->offset + xt_block->size;
10855 align_bits = xt_block->flags.alignment;
10856 end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits;
10857 return end_addr - xt_block->offset;
10858}
10859
10860
10861static bfd_boolean
7fa3d080
BW		 10862xtensa_xt_block_combine (xtensa_block_info *xt_block,
10863 const xtensa_block_info *xt_block_2)
43cd72b9
BW		 10864{
10865 if (xt_block->sec != xt_block_2->sec)
10866 return FALSE;
10867 if (xt_block->offset + xt_block_aligned_size (xt_block)
10868 != xt_block_2->offset)
10869 return FALSE;
10870
10871 if (xt_block_2->size == 0
10872 && (!xt_block_2->flags.is_unreachable
10873 || xt_block->flags.is_unreachable))
10874 {
10875 if (xt_block_2->flags.is_align
10876 && xt_block->flags.is_align)
10877 {
10878 /* Nothing needed. */
10879 if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
10880 return TRUE;
10881 }
10882 else
10883 {
10884 if (xt_block_2->flags.is_align)
10885 {
10886 /* Push alignment to previous entry. */
10887 xt_block->flags.is_align = xt_block_2->flags.is_align;
10888 xt_block->flags.alignment = xt_block_2->flags.alignment;
10889 }
10890 return TRUE;
10891 }
10892 }
10893 if (!xtensa_frag_flags_combinable (&xt_block->flags,
10894 &xt_block_2->flags))
10895 return FALSE;
10896
10897 xt_block->size += xt_block_2->size;
10898
10899 if (xt_block_2->flags.is_align)
10900 {
10901 xt_block->flags.is_align = TRUE;
10902 xt_block->flags.alignment = xt_block_2->flags.alignment;
10903 }
10904
10905 return TRUE;
10906}
10907
10908
7fa3d080
BW		 10909static void
10910add_xt_prop_frags (segT sec,
10911 segT xt_block_sec,
10912 xtensa_block_info **xt_block,
10913 frag_flags_fn property_function)
43cd72b9
BW		 10914{
10915 segment_info_type *seg_info;
10916 segment_info_type *xt_seg_info;
10917 bfd_vma seg_offset;
10918 fragS *fragP;
10919
10920 xt_seg_info = retrieve_segment_info (xt_block_sec);
10921 seg_info = retrieve_segment_info (sec);
10922 /* Build it if needed. */
10923 while (*xt_block != NULL)
10924 {
10925 xt_block = &(*xt_block)->next;
10926 }
10927 /* We are either at NULL at the beginning or at the end. */
10928
10929 /* Walk through the frags. */
10930 seg_offset = 0;
10931
10932 if (seg_info->frchainP)
10933 {
10934 for (fragP = seg_info->frchainP->frch_root; fragP;
10935 fragP = fragP->fr_next)
10936 {
10937 xtensa_block_info tmp_block;
10938 tmp_block.sec = sec;
10939 tmp_block.offset = fragP->fr_address;
10940 tmp_block.size = fragP->fr_fix;
10941 tmp_block.next = NULL;
10942 property_function (fragP, &tmp_block.flags);
10943
10944 if (!xtensa_frag_flags_is_empty (&tmp_block.flags))
10945 /* && fragP->fr_fix != 0) */
10946 {
10947 if ((*xt_block) == NULL
10948 || !xtensa_xt_block_combine (*xt_block, &tmp_block))
10949 {
10950 xtensa_block_info *new_block;
10951 if ((*xt_block) != NULL)
10952 xt_block = &(*xt_block)->next;
10953 new_block = (xtensa_block_info *)
10954 xmalloc (sizeof (xtensa_block_info));
10955 *new_block = tmp_block;
10956 *xt_block = new_block;
10957 }
10958 }
10959 }
10960 }
10961}
10962
10963\f
10964/* op_placement_info_table */
10965
10966/* op_placement_info makes it easier to determine which
10967 ops can go in which slots. */
10968
10969static void
7fa3d080 10970init_op_placement_info_table (void)
43cd72b9
BW		 10971{
10972 xtensa_isa isa = xtensa_default_isa;
10973 xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa);
10974 xtensa_opcode opcode;
10975 xtensa_format fmt;
10976 int slot;
10977 int num_opcodes = xtensa_isa_num_opcodes (isa);
10978
10979 op_placement_table = (op_placement_info_table)
10980 xmalloc (sizeof (op_placement_info) * num_opcodes);
10981 assert (xtensa_isa_num_formats (isa) < MAX_FORMATS);
10982
10983 for (opcode = 0; opcode < num_opcodes; opcode++)
10984 {
10985 op_placement_info *opi = &op_placement_table[opcode];
10986 /* FIXME: Make tinsn allocation dynamic. */
10987 if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS)
10988 as_fatal (_("too many operands in instruction"));
43cd72b9
BW		 10989 opi->narrowest = XTENSA_UNDEFINED;
10990 opi->narrowest_size = 0x7F;
b2d179be 10991 opi->narrowest_slot = 0;
43cd72b9
BW		 10992 opi->formats = 0;
10993 opi->num_formats = 0;
10994 opi->issuef = 0;
10995 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
10996 {
10997 opi->slots[fmt] = 0;
10998 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
10999 {
11000 if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0)
11001 {
11002 int fmt_length = xtensa_format_length (isa, fmt);
11003 opi->issuef++;
11004 set_bit (fmt, opi->formats);
11005 set_bit (slot, opi->slots[fmt]);
a02728c8
BW		 11006 if (fmt_length < opi->narrowest_size
11007 || (fmt_length == opi->narrowest_size
11008 && (xtensa_format_num_slots (isa, fmt)
11009 < xtensa_format_num_slots (isa,
11010 opi->narrowest))))
43cd72b9
BW		 11011 {
11012 opi->narrowest = fmt;
11013 opi->narrowest_size = fmt_length;
b2d179be 11014 opi->narrowest_slot = slot;
43cd72b9 11015 }
e0001a05
NC		 11016 }
11017 }
43cd72b9
BW		 11018 if (opi->formats)
11019 opi->num_formats++;
e0001a05
NC		 11020 }
11021 }
43cd72b9
BW		 11022 xtensa_insnbuf_free (isa, ibuf);
11023}
11024
11025
11026bfd_boolean
7fa3d080 11027opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot)
43cd72b9
BW		 11028{
11029 return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
11030}
11031
11032
11033/* If the opcode is available in a single slot format, return its size. */
11034
7fa3d080
BW		 11035static int
11036xg_get_single_size (xtensa_opcode opcode)
43cd72b9 11037{
b2d179be 11038 return op_placement_table[opcode].narrowest_size;
43cd72b9
BW		 11039}
11040
11041
7fa3d080
BW		 11042static xtensa_format
11043xg_get_single_format (xtensa_opcode opcode)
43cd72b9 11044{
b2d179be
BW		 11045 return op_placement_table[opcode].narrowest;
11046}
11047
11048
11049static int
11050xg_get_single_slot (xtensa_opcode opcode)
11051{
11052 return op_placement_table[opcode].narrowest_slot;
e0001a05
NC		 11053}
11054
11055\f
11056/* Instruction Stack Functions (from "xtensa-istack.h"). */
11057
11058void
7fa3d080 11059istack_init (IStack *stack)
e0001a05
NC		 11060{
11061 memset (stack, 0, sizeof (IStack));
11062 stack->ninsn = 0;
11063}
11064
11065
11066bfd_boolean
7fa3d080 11067istack_empty (IStack *stack)
e0001a05
NC		 11068{
11069 return (stack->ninsn == 0);
11070}
11071
11072
11073bfd_boolean
7fa3d080 11074istack_full (IStack *stack)
e0001a05
NC		 11075{
11076 return (stack->ninsn == MAX_ISTACK);
11077}
11078
11079
11080/* Return a pointer to the top IStack entry.
43cd72b9 11081 It is an error to call this if istack_empty () is TRUE. */
e0001a05
NC		 11082
11083TInsn *
7fa3d080 11084istack_top (IStack *stack)
e0001a05
NC		 11085{
11086 int rec = stack->ninsn - 1;
11087 assert (!istack_empty (stack));
11088 return &stack->insn[rec];
11089}
11090
11091
11092/* Add a new TInsn to an IStack.
43cd72b9 11093 It is an error to call this if istack_full () is TRUE. */
e0001a05
NC		 11094
11095void
7fa3d080 11096istack_push (IStack *stack, TInsn *insn)
e0001a05
NC		 11097{
11098 int rec = stack->ninsn;
11099 assert (!istack_full (stack));
43cd72b9 11100 stack->insn[rec] = *insn;
e0001a05
NC		 11101 stack->ninsn++;
11102}
11103
11104
11105/* Clear space for the next TInsn on the IStack and return a pointer
43cd72b9 11106 to it. It is an error to call this if istack_full () is TRUE. */
e0001a05
NC		 11107
11108TInsn *
7fa3d080 11109istack_push_space (IStack *stack)
e0001a05
NC		 11110{
11111 int rec = stack->ninsn;
11112 TInsn *insn;
11113 assert (!istack_full (stack));
11114 insn = &stack->insn[rec];
60242db2 11115 tinsn_init (insn);
e0001a05
NC		 11116 stack->ninsn++;
11117 return insn;
11118}
11119
11120
11121/* Remove the last pushed instruction. It is an error to call this if
43cd72b9 11122 istack_empty () returns TRUE. */
e0001a05
NC		 11123
11124void
7fa3d080 11125istack_pop (IStack *stack)
e0001a05
NC		 11126{
11127 int rec = stack->ninsn - 1;
11128 assert (!istack_empty (stack));
11129 stack->ninsn--;
60242db2 11130 tinsn_init (&stack->insn[rec]);
e0001a05
NC		 11131}
11132
11133\f
11134/* TInsn functions. */
11135
11136void
7fa3d080 11137tinsn_init (TInsn *dst)
e0001a05
NC		 11138{
11139 memset (dst, 0, sizeof (TInsn));
11140}
11141
11142
43cd72b9 11143/* Return TRUE if ANY of the operands in the insn are symbolic. */
e0001a05
NC		 11144
11145static bfd_boolean
7fa3d080 11146tinsn_has_symbolic_operands (const TInsn *insn)
e0001a05
NC		 11147{
11148 int i;
11149 int n = insn->ntok;
11150
11151 assert (insn->insn_type == ITYPE_INSN);
11152
11153 for (i = 0; i < n; ++i)
11154 {
11155 switch (insn->tok[i].X_op)
11156 {
11157 case O_register:
11158 case O_constant:
11159 break;
11160 default:
11161 return TRUE;
11162 }
11163 }
11164 return FALSE;
11165}
11166
11167
11168bfd_boolean
7fa3d080 11169tinsn_has_invalid_symbolic_operands (const TInsn *insn)
e0001a05 11170{
43cd72b9 11171 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 11172 int i;
11173 int n = insn->ntok;
11174
11175 assert (insn->insn_type == ITYPE_INSN);
11176
11177 for (i = 0; i < n; ++i)
11178 {
11179 switch (insn->tok[i].X_op)
11180 {
11181 case O_register:
11182 case O_constant:
11183 break;
43cd72b9
BW		 11184 case O_big:
11185 case O_illegal:
11186 case O_absent:
11187 /* Errors for these types are caught later. */
11188 break;
11189 case O_hi16:
11190 case O_lo16:
e0001a05 11191 default:
43cd72b9
BW		 11192 /* Symbolic immediates are only allowed on the last immediate
11193 operand. At this time, CONST16 is the only opcode where we
e7da6241 11194 support non-PC-relative relocations. */
43cd72b9
BW		 11195 if (i != get_relaxable_immed (insn->opcode)
11196 || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1
11197 && insn->opcode != xtensa_const16_opcode))
11198 {
431ad2d0 11199 as_bad (_("invalid symbolic operand"));
43cd72b9
BW		 11200 return TRUE;
11201 }
e0001a05
NC		 11202 }
11203 }
11204 return FALSE;
11205}
11206
11207
11208/* For assembly code with complex expressions (e.g. subtraction),
11209 we have to build them in the literal pool so that
11210 their results are calculated correctly after relaxation.
11211 The relaxation only handles expressions that
11212 boil down to SYMBOL + OFFSET. */
11213
11214static bfd_boolean
7fa3d080 11215tinsn_has_complex_operands (const TInsn *insn)
e0001a05
NC		 11216{
11217 int i;
11218 int n = insn->ntok;
11219 assert (insn->insn_type == ITYPE_INSN);
11220 for (i = 0; i < n; ++i)
11221 {
11222 switch (insn->tok[i].X_op)
11223 {
11224 case O_register:
11225 case O_constant:
11226 case O_symbol:
43cd72b9
BW		 11227 case O_lo16:
11228 case O_hi16:
e0001a05
NC		 11229 break;
11230 default:
11231 return TRUE;
11232 }
11233 }
11234 return FALSE;
11235}
11236
11237
b2d179be
BW		 11238/* Encode a TInsn opcode and its constant operands into slotbuf.
11239 Return TRUE if there is a symbol in the immediate field. This
11240 function assumes that:
11241 1) The number of operands are correct.
11242 2) The insn_type is ITYPE_INSN.
11243 3) The opcode can be encoded in the specified format and slot.
11244 4) Operands are either O_constant or O_symbol, and all constants fit. */
43cd72b9
BW		 11245
11246static bfd_boolean
7fa3d080
BW		 11247tinsn_to_slotbuf (xtensa_format fmt,
11248 int slot,
11249 TInsn *tinsn,
11250 xtensa_insnbuf slotbuf)
43cd72b9
BW		 11251{
11252 xtensa_isa isa = xtensa_default_isa;
11253 xtensa_opcode opcode = tinsn->opcode;
11254 bfd_boolean has_fixup = FALSE;
11255 int noperands = xtensa_opcode_num_operands (isa, opcode);
11256 int i;
11257
43cd72b9
BW		 11258 assert (tinsn->insn_type == ITYPE_INSN);
11259 if (noperands != tinsn->ntok)
11260 as_fatal (_("operand number mismatch"));
11261
11262 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode))
11263 {
11264 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11265 xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
11266 return FALSE;
11267 }
11268
11269 for (i = 0; i < noperands; i++)
11270 {
11271 expressionS *expr = &tinsn->tok[i];
d77b99c9
BW		 11272 int rc;
11273 unsigned line;
43cd72b9
BW		 11274 char *file_name;
11275 uint32 opnd_value;
11276
11277 switch (expr->X_op)
11278 {
11279 case O_register:
11280 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11281 break;
11282 /* The register number has already been checked in
11283 expression_maybe_register, so we don't need to check here. */
11284 opnd_value = expr->X_add_number;
11285 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
11286 rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf,
11287 opnd_value);
11288 if (rc != 0)
11289 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa));
11290 break;
11291
11292 case O_constant:
11293 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11294 break;
11295 as_where (&file_name, &line);
11296 /* It is a constant and we called this function
11297 then we have to try to fit it. */
11298 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i,
e0001a05
NC		 11299 expr->X_add_number, file_name, line);
11300 break;
11301
e0001a05
NC		 11302 default:
11303 has_fixup = TRUE;
11304 break;
11305 }
11306 }
43cd72b9 11307
e0001a05
NC		 11308 return has_fixup;
11309}
11310
11311
b2d179be
BW		 11312/* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11313 into a multi-slot instruction, fill the other slots with NOPs.
11314 Return TRUE if there is a symbol in the immediate field. See also the
11315 assumptions listed for tinsn_to_slotbuf. */
11316
11317static bfd_boolean
11318tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf)
11319{
11320 static xtensa_insnbuf slotbuf = 0;
11321 static vliw_insn vinsn;
11322 xtensa_isa isa = xtensa_default_isa;
11323 bfd_boolean has_fixup = FALSE;
11324 int i;
11325
11326 if (!slotbuf)
11327 {
11328 slotbuf = xtensa_insnbuf_alloc (isa);
11329 xg_init_vinsn (&vinsn);
11330 }
11331
11332 xg_clear_vinsn (&vinsn);
11333
11334 bundle_tinsn (tinsn, &vinsn);
11335
11336 xtensa_format_encode (isa, vinsn.format, insnbuf);
11337
11338 for (i = 0; i < vinsn.num_slots; i++)
11339 {
11340 /* Only one slot may have a fix-up because the rest contains NOPs. */
11341 has_fixup |=
11342 tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]);
11343 xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]);
11344 }
11345
11346 return has_fixup;
11347}
11348
11349
43cd72b9 11350/* Check the instruction arguments. Return TRUE on failure. */
e0001a05 11351
7fa3d080
BW		 11352static bfd_boolean
11353tinsn_check_arguments (const TInsn *insn)
e0001a05
NC		 11354{
11355 xtensa_isa isa = xtensa_default_isa;
11356 xtensa_opcode opcode = insn->opcode;
11357
11358 if (opcode == XTENSA_UNDEFINED)
11359 {
11360 as_bad (_("invalid opcode"));
11361 return TRUE;
11362 }
11363
43cd72b9 11364 if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
e0001a05
NC		 11365 {
11366 as_bad (_("too few operands"));
11367 return TRUE;
11368 }
11369
43cd72b9 11370 if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
e0001a05
NC		 11371 {
11372 as_bad (_("too many operands"));
11373 return TRUE;
11374 }
11375 return FALSE;
11376}
11377
11378
11379/* Load an instruction from its encoded form. */
11380
11381static void
7fa3d080 11382tinsn_from_chars (TInsn *tinsn, char *f, int slot)
e0001a05 11383{
43cd72b9 11384 vliw_insn vinsn;
e0001a05 11385
43cd72b9
BW		 11386 xg_init_vinsn (&vinsn);
11387 vinsn_from_chars (&vinsn, f);
11388
11389 *tinsn = vinsn.slots[slot];
11390 xg_free_vinsn (&vinsn);
11391}
e0001a05 11392
43cd72b9
BW		 11393
11394static void
7fa3d080
BW		 11395tinsn_from_insnbuf (TInsn *tinsn,
11396 xtensa_insnbuf slotbuf,
11397 xtensa_format fmt,
11398 int slot)
43cd72b9
BW		 11399{
11400 int i;
11401 xtensa_isa isa = xtensa_default_isa;
e0001a05
NC		 11402
11403 /* Find the immed. */
43cd72b9
BW		 11404 tinsn_init (tinsn);
11405 tinsn->insn_type = ITYPE_INSN;
11406 tinsn->is_specific_opcode = FALSE; /* must not be specific */
11407 tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
11408 tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
11409 for (i = 0; i < tinsn->ntok; i++)
e0001a05 11410 {
43cd72b9
BW		 11411 set_expr_const (&tinsn->tok[i],
11412 xtensa_insnbuf_get_operand (slotbuf, fmt, slot,
11413 tinsn->opcode, i));
e0001a05
NC		 11414 }
11415}
11416
11417
11418/* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11419
11420static void
7fa3d080 11421tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot)
e0001a05 11422{
43cd72b9 11423 xtensa_opcode opcode = tinsn->opcode;
e0001a05
NC		 11424 int opnum;
11425
43cd72b9 11426 if (fragP->tc_frag_data.slot_symbols[slot])
e0001a05
NC		 11427 {
11428 opnum = get_relaxable_immed (opcode);
43cd72b9 11429 assert (opnum >= 0);
e7da6241
BW		 11430 set_expr_symbol_offset (&tinsn->tok[opnum],
11431 fragP->tc_frag_data.slot_symbols[slot],
11432 fragP->tc_frag_data.slot_offsets[slot]);
e0001a05
NC		 11433 }
11434}
11435
11436
11437static int
7fa3d080 11438get_num_stack_text_bytes (IStack *istack)
e0001a05
NC		 11439{
11440 int i;
11441 int text_bytes = 0;
11442
11443 for (i = 0; i < istack->ninsn; i++)
11444 {
43cd72b9
BW		 11445 TInsn *tinsn = &istack->insn[i];
11446 if (tinsn->insn_type == ITYPE_INSN)
11447 text_bytes += xg_get_single_size (tinsn->opcode);
e0001a05
NC		 11448 }
11449 return text_bytes;
11450}
11451
11452
11453static int
7fa3d080 11454get_num_stack_literal_bytes (IStack *istack)
e0001a05
NC		 11455{
11456 int i;
11457 int lit_bytes = 0;
11458
11459 for (i = 0; i < istack->ninsn; i++)
11460 {
43cd72b9
BW		 11461 TInsn *tinsn = &istack->insn[i];
11462 if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1)
e0001a05
NC		 11463 lit_bytes += 4;
11464 }
11465 return lit_bytes;
11466}
11467
43cd72b9
BW		 11468\f
11469/* vliw_insn functions. */
11470
7fa3d080
BW		 11471static void
11472xg_init_vinsn (vliw_insn *v)
43cd72b9
BW		 11473{
11474 int i;
11475 xtensa_isa isa = xtensa_default_isa;
11476
11477 xg_clear_vinsn (v);
11478
11479 v->insnbuf = xtensa_insnbuf_alloc (isa);
11480 if (v->insnbuf == NULL)
11481 as_fatal (_("out of memory"));
11482
11483 for (i = 0; i < MAX_SLOTS; i++)
11484 {
43cd72b9
BW		 11485 v->slotbuf[i] = xtensa_insnbuf_alloc (isa);
11486 if (v->slotbuf[i] == NULL)
11487 as_fatal (_("out of memory"));
11488 }
11489}
11490
11491
7fa3d080
BW		 11492static void
11493xg_clear_vinsn (vliw_insn *v)
43cd72b9
BW		 11494{
11495 int i;
65738a7d
BW		 11496
11497 memset (v, 0, offsetof (vliw_insn, insnbuf));
11498
43cd72b9
BW		 11499 v->format = XTENSA_UNDEFINED;
11500 v->num_slots = 0;
11501 v->inside_bundle = FALSE;
11502
11503 if (xt_saved_debug_type != DEBUG_NONE)
11504 debug_type = xt_saved_debug_type;
11505
11506 for (i = 0; i < MAX_SLOTS; i++)
65738a7d 11507 v->slots[i].opcode = XTENSA_UNDEFINED;
43cd72b9
BW		 11508}
11509
11510
7fa3d080
BW		 11511static bfd_boolean
11512vinsn_has_specific_opcodes (vliw_insn *v)
43cd72b9
BW		 11513{
11514 int i;
c138bc38 11515
43cd72b9
BW		 11516 for (i = 0; i < v->num_slots; i++)
11517 {
11518 if (v->slots[i].is_specific_opcode)
11519 return TRUE;
11520 }
11521 return FALSE;
11522}
11523
11524
7fa3d080
BW		 11525static void
11526xg_free_vinsn (vliw_insn *v)
43cd72b9
BW		 11527{
11528 int i;
11529 xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf);
11530 for (i = 0; i < MAX_SLOTS; i++)
11531 xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]);
11532}
11533
11534
e7da6241
BW		 11535/* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11536 operands. See also the assumptions listed for tinsn_to_slotbuf. */
43cd72b9
BW		 11537
11538static bfd_boolean
7fa3d080
BW		 11539vinsn_to_insnbuf (vliw_insn *vinsn,
11540 char *frag_offset,
11541 fragS *fragP,
11542 bfd_boolean record_fixup)
43cd72b9
BW		 11543{
11544 xtensa_isa isa = xtensa_default_isa;
11545 xtensa_format fmt = vinsn->format;
11546 xtensa_insnbuf insnbuf = vinsn->insnbuf;
11547 int slot;
11548 bfd_boolean has_fixup = FALSE;
11549
11550 xtensa_format_encode (isa, fmt, insnbuf);
11551
11552 for (slot = 0; slot < vinsn->num_slots; slot++)
11553 {
11554 TInsn *tinsn = &vinsn->slots[slot];
11555 bfd_boolean tinsn_has_fixup =
11556 tinsn_to_slotbuf (vinsn->format, slot, tinsn,
11557 vinsn->slotbuf[slot]);
11558
11559 xtensa_format_set_slot (isa, fmt, slot,
11560 insnbuf, vinsn->slotbuf[slot]);
e7da6241 11561 if (tinsn_has_fixup)
43cd72b9
BW		 11562 {
11563 int i;
11564 xtensa_opcode opcode = tinsn->opcode;
11565 int noperands = xtensa_opcode_num_operands (isa, opcode);
11566 has_fixup = TRUE;
11567
11568 for (i = 0; i < noperands; i++)
11569 {
11570 expressionS* expr = &tinsn->tok[i];
11571 switch (expr->X_op)
11572 {
11573 case O_symbol:
11574 case O_lo16:
11575 case O_hi16:
11576 if (get_relaxable_immed (opcode) == i)
11577 {
e7da6241
BW		 11578 /* Add a fix record for the instruction, except if this
11579 function is being called prior to relaxation, i.e.,
11580 if record_fixup is false, and the instruction might
11581 be relaxed later. */
11582 if (record_fixup
11583 || tinsn->is_specific_opcode
11584 || !xg_is_relaxable_insn (tinsn, 0))
43cd72b9 11585 {
e7da6241
BW		 11586 xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP,
11587 frag_offset - fragP->fr_literal);
43cd72b9
BW		 11588 }
11589 else
11590 {
e7da6241
BW		 11591 if (expr->X_op != O_symbol)
11592 as_bad (_("invalid operand"));
43cd72b9
BW		 11593 tinsn->symbol = expr->X_add_symbol;
11594 tinsn->offset = expr->X_add_number;
11595 }
11596 }
11597 else
e7da6241 11598 as_bad (_("symbolic operand not allowed"));
43cd72b9
BW		 11599 break;
11600
11601 case O_constant:
11602 case O_register:
11603 break;
11604
43cd72b9 11605 default:
e7da6241 11606 as_bad (_("expression too complex"));
43cd72b9
BW		 11607 break;
11608 }
11609 }
11610 }
11611 }
11612
11613 return has_fixup;
11614}
11615
11616
11617static void
7fa3d080 11618vinsn_from_chars (vliw_insn *vinsn, char *f)
43cd72b9
BW		 11619{
11620 static xtensa_insnbuf insnbuf = NULL;
11621 static xtensa_insnbuf slotbuf = NULL;
11622 int i;
11623 xtensa_format fmt;
11624 xtensa_isa isa = xtensa_default_isa;
11625
11626 if (!insnbuf)
11627 {
11628 insnbuf = xtensa_insnbuf_alloc (isa);
11629 slotbuf = xtensa_insnbuf_alloc (isa);
11630 }
11631
d77b99c9 11632 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0);
43cd72b9
BW		 11633 fmt = xtensa_format_decode (isa, insnbuf);
11634 if (fmt == XTENSA_UNDEFINED)
11635 as_fatal (_("cannot decode instruction format"));
11636 vinsn->format = fmt;
11637 vinsn->num_slots = xtensa_format_num_slots (isa, fmt);
11638
11639 for (i = 0; i < vinsn->num_slots; i++)
11640 {
11641 TInsn *tinsn = &vinsn->slots[i];
11642 xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf);
11643 tinsn_from_insnbuf (tinsn, slotbuf, fmt, i);
11644 }
11645}
11646
e0001a05
NC		 11647\f
11648/* Expression utilities. */
11649
43cd72b9 11650/* Return TRUE if the expression is an integer constant. */
e0001a05
NC		 11651
11652bfd_boolean
7fa3d080 11653expr_is_const (const expressionS *s)
e0001a05
NC		 11654{
11655 return (s->X_op == O_constant);
11656}
11657
11658
11659/* Get the expression constant.
43cd72b9 11660 Calling this is illegal if expr_is_const () returns TRUE. */
e0001a05
NC		 11661
11662offsetT
7fa3d080 11663get_expr_const (const expressionS *s)
e0001a05
NC		 11664{
11665 assert (expr_is_const (s));
11666 return s->X_add_number;
11667}
11668
11669
11670/* Set the expression to a constant value. */
11671
11672void
7fa3d080 11673set_expr_const (expressionS *s, offsetT val)
e0001a05
NC		 11674{
11675 s->X_op = O_constant;
11676 s->X_add_number = val;
11677 s->X_add_symbol = NULL;
11678 s->X_op_symbol = NULL;
11679}
11680
11681
43cd72b9 11682bfd_boolean
7fa3d080 11683expr_is_register (const expressionS *s)
43cd72b9
BW		 11684{
11685 return (s->X_op == O_register);
11686}
11687
11688
11689/* Get the expression constant.
11690 Calling this is illegal if expr_is_const () returns TRUE. */
11691
11692offsetT
7fa3d080 11693get_expr_register (const expressionS *s)
43cd72b9
BW		 11694{
11695 assert (expr_is_register (s));
11696 return s->X_add_number;
11697}
11698
11699
e0001a05
NC		 11700/* Set the expression to a symbol + constant offset. */
11701
11702void
7fa3d080 11703set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset)
e0001a05
NC		 11704{
11705 s->X_op = O_symbol;
11706 s->X_add_symbol = sym;
11707 s->X_op_symbol = NULL; /* unused */
11708 s->X_add_number = offset;
11709}
11710
11711
43cd72b9
BW		 11712/* Return TRUE if the two expressions are equal. */
11713
e0001a05 11714bfd_boolean
7fa3d080 11715expr_is_equal (expressionS *s1, expressionS *s2)
e0001a05
NC		 11716{
11717 if (s1->X_op != s2->X_op)
11718 return FALSE;
11719 if (s1->X_add_symbol != s2->X_add_symbol)
11720 return FALSE;
11721 if (s1->X_op_symbol != s2->X_op_symbol)
11722 return FALSE;
11723 if (s1->X_add_number != s2->X_add_number)
11724 return FALSE;
11725 return TRUE;
11726}
11727
11728
11729static void
7fa3d080 11730copy_expr (expressionS *dst, const expressionS *src)
e0001a05
NC		 11731{
11732 memcpy (dst, src, sizeof (expressionS));
11733}
11734
11735\f
9456465c 11736/* Support for the "--rename-section" option. */
e0001a05
NC		 11737
11738struct rename_section_struct
11739{
11740 char *old_name;
11741 char *new_name;
11742 struct rename_section_struct *next;
11743};
11744
11745static struct rename_section_struct *section_rename;
11746
11747
9456465c
BW		 11748/* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11749 entries to the section_rename list. Note: Specifying multiple
11750 renamings separated by colons is not documented and is retained only
11751 for backward compatibility. */
e0001a05 11752
7fa3d080
BW		 11753static void
11754build_section_rename (const char *arg)
e0001a05 11755{
9456465c 11756 struct rename_section_struct *r;
e0001a05
NC		 11757 char *this_arg = NULL;
11758 char *next_arg = NULL;
11759
9456465c 11760 for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg)
e0001a05 11761 {
9456465c
BW		 11762 char *old_name, *new_name;
11763
e0001a05
NC		 11764 if (this_arg)
11765 {
11766 next_arg = strchr (this_arg, ':');
11767 if (next_arg)
11768 {
11769 *next_arg = '\0';
11770 next_arg++;
11771 }
11772 }
e0001a05 11773
9456465c
BW		 11774 old_name = this_arg;
11775 new_name = strchr (this_arg, '=');
e0001a05 11776
9456465c
BW		 11777 if (*old_name == '\0')
11778 {
11779 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11780 continue;
11781 }
11782 if (!new_name || new_name[1] == '\0')
11783 {
11784 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11785 old_name);
11786 continue;
11787 }
11788 *new_name = '\0';
11789 new_name++;
e0001a05 11790
9456465c
BW		 11791 /* Check for invalid section renaming. */
11792 for (r = section_rename; r != NULL; r = r->next)
11793 {
11794 if (strcmp (r->old_name, old_name) == 0)
11795 as_bad (_("section %s renamed multiple times"), old_name);
11796 if (strcmp (r->new_name, new_name) == 0)
11797 as_bad (_("multiple sections remapped to output section %s"),
11798 new_name);
11799 }
e0001a05 11800
9456465c
BW		 11801 /* Now add it. */
11802 r = (struct rename_section_struct *)
11803 xmalloc (sizeof (struct rename_section_struct));
11804 r->old_name = xstrdup (old_name);
11805 r->new_name = xstrdup (new_name);
11806 r->next = section_rename;
11807 section_rename = r;
e0001a05 11808 }
e0001a05
NC		 11809}
11810
11811
9456465c
BW		 11812char *
11813xtensa_section_rename (char *name)
e0001a05
NC		 11814{
11815 struct rename_section_struct *r = section_rename;
11816
11817 for (r = section_rename; r != NULL; r = r->next)
43cd72b9
BW		 11818 {
11819 if (strcmp (r->old_name, name) == 0)
11820 return r->new_name;
11821 }
e0001a05
NC		 11822
11823 return name;
11824}
GDB Binutils - Deliverables
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