Commit | Line | Data |
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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
aef6203b | 2 | Copyright 2003, 2004, 2005 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
43cd72b9 | 18 | the Free Software Foundation, 59 Temple Place - Suite 330, Boston, |
e0001a05 NC |
19 | MA 02111-1307, USA. */ |
20 | ||
21 | #include <string.h> | |
43cd72b9 | 22 | #include <limits.h> |
e0001a05 NC |
23 | #include "as.h" |
24 | #include "sb.h" | |
25 | #include "safe-ctype.h" | |
26 | #include "tc-xtensa.h" | |
27 | #include "frags.h" | |
28 | #include "subsegs.h" | |
29 | #include "xtensa-relax.h" | |
30 | #include "xtensa-istack.h" | |
cda2eb9e | 31 | #include "dwarf2dbg.h" |
e0001a05 NC |
32 | #include "struc-symbol.h" |
33 | #include "xtensa-config.h" | |
34 | ||
35 | #ifndef uint32 | |
36 | #define uint32 unsigned int | |
37 | #endif | |
38 | #ifndef int32 | |
39 | #define int32 signed int | |
40 | #endif | |
41 | ||
42 | /* Notes: | |
43 | ||
e0001a05 NC |
44 | Naming conventions (used somewhat inconsistently): |
45 | The xtensa_ functions are exported | |
46 | The xg_ functions are internal | |
47 | ||
48 | We also have a couple of different extensibility mechanisms. | |
49 | 1) The idiom replacement: | |
50 | This is used when a line is first parsed to | |
51 | replace an instruction pattern with another instruction | |
52 | It is currently limited to replacements of instructions | |
53 | with constant operands. | |
54 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
55 | replacement patterns. When an instruction's immediate field | |
56 | does not fit the next instruction sequence is attempted. | |
57 | In addition, "narrow" opcodes are supported this way. */ | |
58 | ||
59 | ||
60 | /* Define characters with special meanings to GAS. */ | |
61 | const char comment_chars[] = "#"; | |
62 | const char line_comment_chars[] = "#"; | |
63 | const char line_separator_chars[] = ";"; | |
64 | const char EXP_CHARS[] = "eE"; | |
65 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
66 | ||
67 | ||
43cd72b9 BW |
68 | /* Flags to indicate whether the hardware supports the density and |
69 | absolute literals options. */ | |
e0001a05 | 70 | |
e0001a05 | 71 | bfd_boolean density_supported = XCHAL_HAVE_DENSITY; |
43cd72b9 BW |
72 | bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; |
73 | ||
74 | /* Maximum width we would pad an unreachable frag to get alignment. */ | |
75 | #define UNREACHABLE_MAX_WIDTH 8 | |
e0001a05 | 76 | |
43cd72b9 BW |
77 | static vliw_insn cur_vinsn; |
78 | ||
d77b99c9 | 79 | unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; |
43cd72b9 BW |
80 | |
81 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
82 | ||
83 | /* Some functions are only valid in the front end. This variable | |
84 | allows us to assert that we haven't crossed over into the | |
85 | back end. */ | |
86 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
87 | |
88 | /* Flags for properties of the last instruction in a segment. */ | |
89 | #define FLAG_IS_A0_WRITER 0x1 | |
90 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
91 | ||
92 | ||
93 | /* We define a special segment names ".literal" to place literals | |
94 | into. The .fini and .init sections are special because they | |
95 | contain code that is moved together by the linker. We give them | |
96 | their own special .fini.literal and .init.literal sections. */ | |
97 | ||
98 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 99 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 NC |
100 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
101 | #define INIT_SECTION_NAME xtensa_section_rename (".init") | |
102 | #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal") | |
103 | #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal") | |
104 | ||
105 | ||
43cd72b9 | 106 | /* This type is used for the directive_stack to keep track of the |
e0001a05 NC |
107 | state of the literal collection pools. */ |
108 | ||
109 | typedef struct lit_state_struct | |
110 | { | |
111 | const char *lit_seg_name; | |
43cd72b9 | 112 | const char *lit4_seg_name; |
e0001a05 NC |
113 | const char *init_lit_seg_name; |
114 | const char *fini_lit_seg_name; | |
115 | segT lit_seg; | |
43cd72b9 | 116 | segT lit4_seg; |
e0001a05 NC |
117 | segT init_lit_seg; |
118 | segT fini_lit_seg; | |
119 | } lit_state; | |
120 | ||
121 | static lit_state default_lit_sections; | |
122 | ||
123 | ||
124 | /* We keep lists of literal segments. The seg_list type is the node | |
125 | for such a list. The *_literal_head locals are the heads of the | |
126 | various lists. All of these lists have a dummy node at the start. */ | |
127 | ||
128 | typedef struct seg_list_struct | |
129 | { | |
130 | struct seg_list_struct *next; | |
131 | segT seg; | |
132 | } seg_list; | |
133 | ||
134 | static seg_list literal_head_h; | |
135 | static seg_list *literal_head = &literal_head_h; | |
136 | static seg_list init_literal_head_h; | |
137 | static seg_list *init_literal_head = &init_literal_head_h; | |
138 | static seg_list fini_literal_head_h; | |
139 | static seg_list *fini_literal_head = &fini_literal_head_h; | |
140 | ||
141 | ||
82e7541d BW |
142 | /* Lists of symbols. We keep a list of symbols that label the current |
143 | instruction, so that we can adjust the symbols when inserting alignment | |
144 | for various instructions. We also keep a list of all the symbols on | |
145 | literals, so that we can fix up those symbols when the literals are | |
146 | later moved into the text sections. */ | |
147 | ||
148 | typedef struct sym_list_struct | |
149 | { | |
150 | struct sym_list_struct *next; | |
151 | symbolS *sym; | |
152 | } sym_list; | |
153 | ||
154 | static sym_list *insn_labels = NULL; | |
155 | static sym_list *free_insn_labels = NULL; | |
156 | static sym_list *saved_insn_labels = NULL; | |
157 | ||
158 | static sym_list *literal_syms; | |
159 | ||
160 | ||
43cd72b9 BW |
161 | /* Flags to determine whether to prefer const16 or l32r |
162 | if both options are available. */ | |
163 | int prefer_const16 = 0; | |
164 | int prefer_l32r = 0; | |
165 | ||
e0001a05 NC |
166 | /* Global flag to indicate when we are emitting literals. */ |
167 | int generating_literals = 0; | |
168 | ||
43cd72b9 BW |
169 | /* The following PROPERTY table definitions are copied from |
170 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
171 | ||
172 | /* Flags in the property tables to specify whether blocks of memory | |
173 | are literals, instructions, data, or unreachable. For | |
174 | instructions, blocks that begin loop targets and branch targets are | |
175 | designated. Blocks that do not allow density, instruction | |
176 | reordering or transformation are also specified. Finally, for | |
177 | branch targets, branch target alignment priority is included. | |
178 | Alignment of the next block is specified in the current block | |
179 | and the size of the current block does not include any fill required | |
180 | to align to the next block. */ | |
181 | ||
182 | #define XTENSA_PROP_LITERAL 0x00000001 | |
183 | #define XTENSA_PROP_INSN 0x00000002 | |
184 | #define XTENSA_PROP_DATA 0x00000004 | |
185 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
186 | /* Instruction only properties at beginning of code. */ | |
187 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
188 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
189 | /* Instruction only properties about code. */ | |
190 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
191 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
192 | #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100 | |
193 | ||
194 | /* Branch target alignment information. This transmits information | |
195 | to the linker optimization about the priority of aligning a | |
196 | particular block for branch target alignment: None, low priority, | |
197 | high priority, or required. These only need to be checked in | |
198 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
199 | Common usage is | |
200 | ||
201 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
202 | case XTENSA_PROP_BT_ALIGN_NONE: | |
203 | case XTENSA_PROP_BT_ALIGN_LOW: | |
204 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
205 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
206 | */ | |
207 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
208 | ||
209 | /* No branch target alignment. */ | |
210 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
211 | /* Low priority branch target alignment. */ | |
212 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
213 | /* High priority branch target alignment. */ | |
214 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
215 | /* Required branch target alignment. */ | |
216 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
217 | ||
218 | #define GET_XTENSA_PROP_BT_ALIGN(flag) \ | |
219 | (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) | |
220 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ | |
221 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
222 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
223 | ||
224 | ||
225 | /* Alignment is specified in the block BEFORE the one that needs | |
226 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
227 | get the required alignment specified as a power of 2. Use | |
228 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
229 | alignment. Be careful of side effects since the SET will evaluate | |
230 | flags twice. Also, note that the SIZE of a block in the property | |
231 | table does not include the alignment size, so the alignment fill | |
232 | must be calculated to determine if two blocks are contiguous. | |
233 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
234 | possible future implementation. */ | |
235 | ||
236 | #define XTENSA_PROP_ALIGN 0x00000800 | |
237 | ||
238 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
239 | ||
240 | #define GET_XTENSA_PROP_ALIGNMENT(flag) \ | |
241 | (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) | |
242 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ | |
243 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
244 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
245 | ||
246 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
247 | ||
248 | ||
249 | /* Structure for saving instruction and alignment per-fragment data | |
250 | that will be written to the object file. This structure is | |
251 | equivalent to the actual data that will be written out to the file | |
252 | but is easier to use. We provide a conversion to file flags | |
253 | in frag_flags_to_number. */ | |
254 | ||
255 | typedef struct frag_flags_struct frag_flags; | |
256 | ||
257 | struct frag_flags_struct | |
258 | { | |
259 | /* is_literal should only be used after xtensa_move_literals. | |
260 | If you need to check if you are generating a literal fragment, | |
261 | then use the generating_literals global. */ | |
262 | ||
263 | unsigned is_literal : 1; | |
264 | unsigned is_insn : 1; | |
265 | unsigned is_data : 1; | |
266 | unsigned is_unreachable : 1; | |
267 | ||
268 | struct | |
269 | { | |
270 | unsigned is_loop_target : 1; | |
271 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
272 | unsigned bt_align_priority : 2; | |
273 | ||
274 | unsigned is_no_density : 1; | |
275 | /* no_longcalls flag does not need to be placed in the object file. */ | |
276 | /* is_specific_opcode implies no_transform. */ | |
277 | unsigned is_no_transform : 1; | |
278 | ||
279 | unsigned is_no_reorder : 1; | |
280 | ||
281 | /* Uses absolute literal addressing for l32r. */ | |
282 | unsigned is_abslit : 1; | |
283 | } insn; | |
284 | unsigned is_align : 1; | |
285 | unsigned alignment : 5; | |
286 | }; | |
287 | ||
288 | ||
289 | /* Structure for saving information about a block of property data | |
290 | for frags that have the same flags. */ | |
291 | struct xtensa_block_info_struct | |
292 | { | |
293 | segT sec; | |
294 | bfd_vma offset; | |
295 | size_t size; | |
296 | frag_flags flags; | |
297 | struct xtensa_block_info_struct *next; | |
298 | }; | |
299 | ||
e0001a05 NC |
300 | |
301 | /* Structure for saving the current state before emitting literals. */ | |
302 | typedef struct emit_state_struct | |
303 | { | |
304 | const char *name; | |
305 | segT now_seg; | |
306 | subsegT now_subseg; | |
307 | int generating_literals; | |
308 | } emit_state; | |
309 | ||
310 | ||
43cd72b9 BW |
311 | /* Opcode placement information */ |
312 | ||
313 | typedef unsigned long long bitfield; | |
314 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
315 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
316 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
317 | ||
318 | #define MAX_FORMATS 32 | |
319 | ||
320 | typedef struct op_placement_info_struct | |
321 | { | |
322 | int num_formats; | |
323 | /* A number describing how restrictive the issue is for this | |
324 | opcode. For example, an opcode that fits lots of different | |
325 | formats has a high freedom, as does an opcode that fits | |
326 | only one format but many slots in that format. The most | |
327 | restrictive is the opcode that fits only one slot in one | |
328 | format. */ | |
329 | int issuef; | |
330 | /* The single format (i.e., if the op can live in a bundle by itself), | |
331 | narrowest format, and widest format the op can be bundled in | |
332 | and their sizes: */ | |
333 | xtensa_format single; | |
334 | xtensa_format narrowest; | |
335 | xtensa_format widest; | |
336 | char narrowest_size; | |
337 | char widest_size; | |
338 | char single_size; | |
339 | ||
340 | /* formats is a bitfield with the Nth bit set | |
341 | if the opcode fits in the Nth xtensa_format. */ | |
342 | bitfield formats; | |
343 | ||
344 | /* slots[N]'s Mth bit is set if the op fits in the | |
345 | Mth slot of the Nth xtensa_format. */ | |
346 | bitfield slots[MAX_FORMATS]; | |
347 | ||
348 | /* A count of the number of slots in a given format | |
349 | an op can fit (i.e., the bitcount of the slot field above). */ | |
350 | char slots_in_format[MAX_FORMATS]; | |
351 | ||
352 | } op_placement_info, *op_placement_info_table; | |
353 | ||
354 | op_placement_info_table op_placement_table; | |
355 | ||
356 | ||
357 | /* Extra expression types. */ | |
358 | ||
359 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
360 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
361 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
362 | ||
363 | ||
e0001a05 NC |
364 | /* Directives. */ |
365 | ||
366 | typedef enum | |
367 | { | |
368 | directive_none = 0, | |
369 | directive_literal, | |
370 | directive_density, | |
43cd72b9 | 371 | directive_transform, |
e0001a05 NC |
372 | directive_freeregs, |
373 | directive_longcalls, | |
43cd72b9 BW |
374 | directive_literal_prefix, |
375 | directive_schedule, | |
376 | directive_absolute_literals, | |
377 | directive_last_directive | |
e0001a05 NC |
378 | } directiveE; |
379 | ||
380 | typedef struct | |
381 | { | |
382 | const char *name; | |
383 | bfd_boolean can_be_negated; | |
384 | } directive_infoS; | |
385 | ||
386 | const directive_infoS directive_info[] = | |
387 | { | |
43cd72b9 BW |
388 | { "none", FALSE }, |
389 | { "literal", FALSE }, | |
390 | { "density", TRUE }, | |
391 | { "transform", TRUE }, | |
392 | { "freeregs", FALSE }, | |
393 | { "longcalls", TRUE }, | |
394 | { "literal_prefix", FALSE }, | |
395 | { "schedule", TRUE }, | |
396 | { "absolute-literals", TRUE } | |
e0001a05 NC |
397 | }; |
398 | ||
399 | bfd_boolean directive_state[] = | |
400 | { | |
401 | FALSE, /* none */ | |
402 | FALSE, /* literal */ | |
43cd72b9 | 403 | #if !XCHAL_HAVE_DENSITY |
e0001a05 NC |
404 | FALSE, /* density */ |
405 | #else | |
406 | TRUE, /* density */ | |
407 | #endif | |
43cd72b9 | 408 | TRUE, /* transform */ |
e0001a05 NC |
409 | FALSE, /* freeregs */ |
410 | FALSE, /* longcalls */ | |
43cd72b9 BW |
411 | FALSE, /* literal_prefix */ |
412 | TRUE, /* schedule */ | |
413 | #if XSHAL_USE_ABSOLUTE_LITERALS | |
414 | TRUE /* absolute_literals */ | |
415 | #else | |
416 | FALSE /* absolute_literals */ | |
417 | #endif | |
e0001a05 NC |
418 | }; |
419 | ||
e0001a05 NC |
420 | |
421 | /* Directive functions. */ | |
422 | ||
7fa3d080 BW |
423 | static void xtensa_begin_directive (int); |
424 | static void xtensa_end_directive (int); | |
425 | static void xtensa_dwarf2_directive_loc (int); | |
426 | static void xtensa_literal_prefix (char const *, int); | |
427 | static void xtensa_literal_position (int); | |
428 | static void xtensa_literal_pseudo (int); | |
429 | static void xtensa_frequency_pseudo (int); | |
430 | static void xtensa_elf_cons (int); | |
e0001a05 | 431 | |
7fa3d080 | 432 | /* Parsing and Idiom Translation. */ |
e0001a05 | 433 | |
7fa3d080 | 434 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 435 | |
e0001a05 NC |
436 | /* Various Other Internal Functions. */ |
437 | ||
7fa3d080 BW |
438 | static void xtensa_mark_literal_pool_location (void); |
439 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
440 | static fragS *get_literal_pool_location (segT); | |
441 | static void set_literal_pool_location (segT, fragS *); | |
442 | static void xtensa_set_frag_assembly_state (fragS *); | |
443 | static void finish_vinsn (vliw_insn *); | |
444 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 445 | static int total_frag_text_expansion (fragS *); |
e0001a05 NC |
446 | |
447 | /* Alignment Functions. */ | |
448 | ||
d77b99c9 BW |
449 | static int get_text_align_power (unsigned); |
450 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 451 | static int branch_align_power (segT); |
e0001a05 NC |
452 | |
453 | /* Helpers for xtensa_relax_frag(). */ | |
454 | ||
7fa3d080 | 455 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 456 | |
b08b5071 | 457 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 458 | |
7fa3d080 BW |
459 | static unsigned get_last_insn_flags (segT, subsegT); |
460 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
461 | static float get_subseg_total_freq (segT, subsegT); |
462 | static float get_subseg_target_freq (segT, subsegT); | |
463 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
464 | |
465 | /* Segment list functions. */ | |
466 | ||
7fa3d080 BW |
467 | static void xtensa_move_literals (void); |
468 | static void xtensa_reorder_segments (void); | |
469 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
470 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
471 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
472 | static void xtensa_restore_emit_state (emit_state *); | |
e0001a05 | 473 | static void cache_literal_section |
7fa3d080 | 474 | (seg_list *, const char *, segT *, bfd_boolean); |
e0001a05 | 475 | |
e0001a05 | 476 | /* Import from elf32-xtensa.c in BFD library. */ |
43cd72b9 | 477 | |
7fa3d080 | 478 | extern char *xtensa_get_property_section_name (asection *, const char *); |
e0001a05 | 479 | |
43cd72b9 BW |
480 | /* op_placement_info functions. */ |
481 | ||
7fa3d080 BW |
482 | static void init_op_placement_info_table (void); |
483 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
484 | static int xg_get_single_size (xtensa_opcode); | |
485 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
43cd72b9 | 486 | |
e0001a05 | 487 | /* TInsn and IStack functions. */ |
43cd72b9 | 488 | |
7fa3d080 BW |
489 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
490 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
491 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
492 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
493 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
494 | static void tinsn_from_chars (TInsn *, char *, int); | |
495 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
496 | static int get_num_stack_text_bytes (IStack *); | |
497 | static int get_num_stack_literal_bytes (IStack *); | |
e0001a05 | 498 | |
43cd72b9 BW |
499 | /* vliw_insn functions. */ |
500 | ||
7fa3d080 BW |
501 | static void xg_init_vinsn (vliw_insn *); |
502 | static void xg_clear_vinsn (vliw_insn *); | |
503 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
504 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 505 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
506 | (vliw_insn *, char *, fragS *, bfd_boolean); |
507 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 508 | |
e0001a05 | 509 | /* Expression Utilities. */ |
43cd72b9 | 510 | |
7fa3d080 BW |
511 | bfd_boolean expr_is_const (const expressionS *); |
512 | offsetT get_expr_const (const expressionS *); | |
513 | void set_expr_const (expressionS *, offsetT); | |
514 | bfd_boolean expr_is_register (const expressionS *); | |
515 | offsetT get_expr_register (const expressionS *); | |
516 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
43cd72b9 | 517 | static void set_expr_symbol_offset_diff |
7fa3d080 BW |
518 | (expressionS *, symbolS *, symbolS *, offsetT); |
519 | bfd_boolean expr_is_equal (expressionS *, expressionS *); | |
520 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 521 | |
9456465c BW |
522 | /* Section renaming. */ |
523 | ||
7fa3d080 | 524 | static void build_section_rename (const char *); |
e0001a05 | 525 | |
e0001a05 NC |
526 | |
527 | /* ISA imported from bfd. */ | |
528 | extern xtensa_isa xtensa_default_isa; | |
529 | ||
530 | extern int target_big_endian; | |
531 | ||
532 | static xtensa_opcode xtensa_addi_opcode; | |
533 | static xtensa_opcode xtensa_addmi_opcode; | |
534 | static xtensa_opcode xtensa_call0_opcode; | |
535 | static xtensa_opcode xtensa_call4_opcode; | |
536 | static xtensa_opcode xtensa_call8_opcode; | |
537 | static xtensa_opcode xtensa_call12_opcode; | |
538 | static xtensa_opcode xtensa_callx0_opcode; | |
539 | static xtensa_opcode xtensa_callx4_opcode; | |
540 | static xtensa_opcode xtensa_callx8_opcode; | |
541 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 542 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 543 | static xtensa_opcode xtensa_entry_opcode; |
43cd72b9 BW |
544 | static xtensa_opcode xtensa_movi_opcode; |
545 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 546 | static xtensa_opcode xtensa_isync_opcode; |
e0001a05 | 547 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 548 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
549 | static xtensa_opcode xtensa_loop_opcode; |
550 | static xtensa_opcode xtensa_loopnez_opcode; | |
551 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 552 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
553 | static xtensa_opcode xtensa_nop_n_opcode; |
554 | static xtensa_opcode xtensa_or_opcode; | |
555 | static xtensa_opcode xtensa_ret_opcode; | |
556 | static xtensa_opcode xtensa_ret_n_opcode; | |
557 | static xtensa_opcode xtensa_retw_opcode; | |
558 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 559 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 NC |
560 | static xtensa_opcode xtensa_waiti_opcode; |
561 | ||
562 | \f | |
563 | /* Command-line Options. */ | |
564 | ||
565 | bfd_boolean use_literal_section = TRUE; | |
566 | static bfd_boolean align_targets = TRUE; | |
43cd72b9 | 567 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 568 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
569 | static bfd_boolean workaround_a0_b_retw = FALSE; |
570 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
571 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 572 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 573 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 NC |
574 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
575 | ||
43cd72b9 BW |
576 | /* When workaround_short_loops is TRUE, all loops with early exits must |
577 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
578 | to the workaround_short_loop flag. In addition to the | |
579 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
580 | must have at least 3 instructions. */ | |
e0001a05 | 581 | |
43cd72b9 | 582 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 583 | |
7fa3d080 BW |
584 | |
585 | static void | |
586 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
587 | { | |
588 | if (earliest > latest) | |
589 | as_fatal (_("illegal range of target hardware versions")); | |
590 | ||
591 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
592 | if (earliest < 105000 || latest < 105000) | |
593 | { | |
594 | workaround_a0_b_retw |= TRUE; | |
595 | workaround_b_j_loop_end |= TRUE; | |
596 | workaround_short_loop |= TRUE; | |
597 | workaround_close_loop_end |= TRUE; | |
598 | workaround_all_short_loops |= TRUE; | |
599 | } | |
600 | } | |
601 | ||
602 | ||
e0001a05 NC |
603 | enum |
604 | { | |
605 | option_density = OPTION_MD_BASE, | |
606 | option_no_density, | |
607 | ||
608 | option_relax, | |
609 | option_no_relax, | |
610 | ||
43cd72b9 BW |
611 | option_link_relax, |
612 | option_no_link_relax, | |
613 | ||
e0001a05 NC |
614 | option_generics, |
615 | option_no_generics, | |
616 | ||
43cd72b9 BW |
617 | option_transform, |
618 | option_no_transform, | |
619 | ||
e0001a05 NC |
620 | option_text_section_literals, |
621 | option_no_text_section_literals, | |
622 | ||
43cd72b9 BW |
623 | option_absolute_literals, |
624 | option_no_absolute_literals, | |
625 | ||
e0001a05 NC |
626 | option_align_targets, |
627 | option_no_align_targets, | |
628 | ||
43cd72b9 | 629 | option_warn_unaligned_targets, |
e0001a05 NC |
630 | |
631 | option_longcalls, | |
632 | option_no_longcalls, | |
633 | ||
634 | option_workaround_a0_b_retw, | |
635 | option_no_workaround_a0_b_retw, | |
636 | ||
637 | option_workaround_b_j_loop_end, | |
638 | option_no_workaround_b_j_loop_end, | |
639 | ||
640 | option_workaround_short_loop, | |
641 | option_no_workaround_short_loop, | |
642 | ||
643 | option_workaround_all_short_loops, | |
644 | option_no_workaround_all_short_loops, | |
645 | ||
646 | option_workaround_close_loop_end, | |
647 | option_no_workaround_close_loop_end, | |
648 | ||
649 | option_no_workarounds, | |
650 | ||
e0001a05 | 651 | option_rename_section_name, |
e0001a05 | 652 | |
43cd72b9 BW |
653 | option_prefer_l32r, |
654 | option_prefer_const16, | |
655 | ||
656 | option_target_hardware | |
e0001a05 NC |
657 | }; |
658 | ||
659 | const char *md_shortopts = ""; | |
660 | ||
661 | struct option md_longopts[] = | |
662 | { | |
43cd72b9 BW |
663 | { "density", no_argument, NULL, option_density }, |
664 | { "no-density", no_argument, NULL, option_no_density }, | |
665 | ||
666 | /* Both "relax" and "generics" are deprecated and treated as equivalent | |
667 | to the "transform" option. */ | |
668 | { "relax", no_argument, NULL, option_relax }, | |
669 | { "no-relax", no_argument, NULL, option_no_relax }, | |
670 | { "generics", no_argument, NULL, option_generics }, | |
671 | { "no-generics", no_argument, NULL, option_no_generics }, | |
672 | ||
673 | { "transform", no_argument, NULL, option_transform }, | |
674 | { "no-transform", no_argument, NULL, option_no_transform }, | |
675 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
676 | { "no-text-section-literals", no_argument, NULL, | |
677 | option_no_text_section_literals }, | |
678 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
679 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
680 | /* This option was changed from -align-target to -target-align |
681 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 682 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
683 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
684 | { "warn-unaligned-targets", no_argument, NULL, | |
685 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
686 | { "longcalls", no_argument, NULL, option_longcalls }, |
687 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
688 | ||
689 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
690 | option_no_workaround_a0_b_retw }, | |
691 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 692 | |
43cd72b9 BW |
693 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
694 | option_no_workaround_b_j_loop_end }, | |
695 | { "workaround-b-j-loop-end", no_argument, NULL, | |
696 | option_workaround_b_j_loop_end }, | |
e0001a05 | 697 | |
43cd72b9 BW |
698 | { "no-workaround-short-loops", no_argument, NULL, |
699 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
700 | { "workaround-short-loops", no_argument, NULL, |
701 | option_workaround_short_loop }, | |
e0001a05 | 702 | |
43cd72b9 BW |
703 | { "no-workaround-all-short-loops", no_argument, NULL, |
704 | option_no_workaround_all_short_loops }, | |
705 | { "workaround-all-short-loop", no_argument, NULL, | |
706 | option_workaround_all_short_loops }, | |
707 | ||
708 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
709 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
710 | ||
711 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
712 | ||
713 | { "no-workaround-close-loop-end", no_argument, NULL, | |
714 | option_no_workaround_close_loop_end }, | |
715 | { "workaround-close-loop-end", no_argument, NULL, | |
716 | option_workaround_close_loop_end }, | |
e0001a05 | 717 | |
7fa3d080 | 718 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 719 | |
43cd72b9 BW |
720 | { "link-relax", no_argument, NULL, option_link_relax }, |
721 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
722 | ||
723 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
724 | ||
725 | { NULL, no_argument, NULL, 0 } | |
e0001a05 NC |
726 | }; |
727 | ||
728 | size_t md_longopts_size = sizeof md_longopts; | |
729 | ||
730 | ||
731 | int | |
7fa3d080 | 732 | md_parse_option (int c, char *arg) |
e0001a05 NC |
733 | { |
734 | switch (c) | |
735 | { | |
736 | case option_density: | |
43cd72b9 | 737 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
738 | return 1; |
739 | case option_no_density: | |
43cd72b9 | 740 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 741 | return 1; |
43cd72b9 BW |
742 | case option_link_relax: |
743 | linkrelax = 1; | |
e0001a05 | 744 | return 1; |
43cd72b9 BW |
745 | case option_no_link_relax: |
746 | linkrelax = 0; | |
e0001a05 | 747 | return 1; |
43cd72b9 BW |
748 | case option_generics: |
749 | as_warn (_("--generics is deprecated; use --transform instead")); | |
750 | return md_parse_option (option_transform, arg); | |
751 | case option_no_generics: | |
752 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
753 | return md_parse_option (option_no_transform, arg); | |
754 | case option_relax: | |
755 | as_warn (_("--relax is deprecated; use --transform instead")); | |
756 | return md_parse_option (option_transform, arg); | |
757 | case option_no_relax: | |
758 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
759 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
760 | case option_longcalls: |
761 | directive_state[directive_longcalls] = TRUE; | |
762 | return 1; | |
763 | case option_no_longcalls: | |
764 | directive_state[directive_longcalls] = FALSE; | |
765 | return 1; | |
766 | case option_text_section_literals: | |
767 | use_literal_section = FALSE; | |
768 | return 1; | |
769 | case option_no_text_section_literals: | |
770 | use_literal_section = TRUE; | |
771 | return 1; | |
43cd72b9 BW |
772 | case option_absolute_literals: |
773 | if (!absolute_literals_supported) | |
774 | { | |
775 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
776 | return 0; | |
777 | } | |
778 | directive_state[directive_absolute_literals] = TRUE; | |
779 | return 1; | |
780 | case option_no_absolute_literals: | |
781 | directive_state[directive_absolute_literals] = FALSE; | |
782 | return 1; | |
783 | ||
e0001a05 NC |
784 | case option_workaround_a0_b_retw: |
785 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
786 | return 1; |
787 | case option_no_workaround_a0_b_retw: | |
788 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
789 | return 1; |
790 | case option_workaround_b_j_loop_end: | |
791 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
792 | return 1; |
793 | case option_no_workaround_b_j_loop_end: | |
794 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
795 | return 1; |
796 | ||
797 | case option_workaround_short_loop: | |
798 | workaround_short_loop = TRUE; | |
e0001a05 NC |
799 | return 1; |
800 | case option_no_workaround_short_loop: | |
801 | workaround_short_loop = FALSE; | |
e0001a05 NC |
802 | return 1; |
803 | ||
804 | case option_workaround_all_short_loops: | |
805 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
806 | return 1; |
807 | case option_no_workaround_all_short_loops: | |
808 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
809 | return 1; |
810 | ||
811 | case option_workaround_close_loop_end: | |
812 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
813 | return 1; |
814 | case option_no_workaround_close_loop_end: | |
815 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
816 | return 1; |
817 | ||
818 | case option_no_workarounds: | |
819 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 820 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 821 | workaround_short_loop = FALSE; |
e0001a05 | 822 | workaround_all_short_loops = FALSE; |
e0001a05 | 823 | workaround_close_loop_end = FALSE; |
e0001a05 | 824 | return 1; |
43cd72b9 | 825 | |
e0001a05 NC |
826 | case option_align_targets: |
827 | align_targets = TRUE; | |
828 | return 1; | |
829 | case option_no_align_targets: | |
830 | align_targets = FALSE; | |
831 | return 1; | |
832 | ||
43cd72b9 BW |
833 | case option_warn_unaligned_targets: |
834 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
835 | return 1; |
836 | ||
e0001a05 NC |
837 | case option_rename_section_name: |
838 | build_section_rename (arg); | |
839 | return 1; | |
e0001a05 NC |
840 | |
841 | case 'Q': | |
842 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
843 | should be emitted or not. FIXME: Not implemented. */ | |
844 | return 1; | |
845 | ||
43cd72b9 BW |
846 | case option_prefer_l32r: |
847 | if (prefer_const16) | |
848 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
849 | prefer_l32r = 1; | |
850 | return 1; | |
851 | ||
852 | case option_prefer_const16: | |
853 | if (prefer_l32r) | |
854 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
855 | prefer_const16 = 1; | |
856 | return 1; | |
857 | ||
858 | case option_target_hardware: | |
859 | { | |
860 | int earliest, latest = 0; | |
861 | if (*arg == 0 || *arg == '-') | |
862 | as_fatal (_("invalid target hardware version")); | |
863 | ||
864 | earliest = strtol (arg, &arg, 0); | |
865 | ||
866 | if (*arg == 0) | |
867 | latest = earliest; | |
868 | else if (*arg == '-') | |
869 | { | |
870 | if (*++arg == 0) | |
871 | as_fatal (_("invalid target hardware version")); | |
872 | latest = strtol (arg, &arg, 0); | |
873 | } | |
874 | if (*arg != 0) | |
875 | as_fatal (_("invalid target hardware version")); | |
876 | ||
877 | xtensa_setup_hw_workarounds (earliest, latest); | |
878 | return 1; | |
879 | } | |
880 | ||
881 | case option_transform: | |
882 | /* This option has no affect other than to use the defaults, | |
883 | which are already set. */ | |
884 | return 1; | |
885 | ||
886 | case option_no_transform: | |
887 | /* This option turns off all transformations of any kind. | |
888 | However, because we want to preserve the state of other | |
889 | directives, we only change its own field. Thus, before | |
890 | you perform any transformation, always check if transform | |
891 | is available. If you use the functions we provide for this | |
892 | purpose, you will be ok. */ | |
893 | directive_state[directive_transform] = FALSE; | |
894 | return 1; | |
895 | ||
e0001a05 NC |
896 | default: |
897 | return 0; | |
898 | } | |
899 | } | |
900 | ||
901 | ||
902 | void | |
7fa3d080 | 903 | md_show_usage (FILE *stream) |
e0001a05 | 904 | { |
43cd72b9 BW |
905 | fputs ("\n\ |
906 | Xtensa options:\n\ | |
9456465c BW |
907 | --[no-]text-section-literals\n\ |
908 | [Do not] put literals in the text section\n\ | |
909 | --[no-]absolute-literals\n\ | |
910 | [Do not] default to use non-PC-relative literals\n\ | |
911 | --[no-]target-align [Do not] try to align branch targets\n\ | |
912 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
913 | --[no-]transform [Do not] transform instructions\n\ | |
914 | --rename-section old=new Rename section 'old' to 'new'\n", stream); | |
e0001a05 NC |
915 | } |
916 | ||
7fa3d080 BW |
917 | \f |
918 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
919 | |
920 | static void | |
7fa3d080 | 921 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 922 | { |
7fa3d080 | 923 | sym_list *l; |
43cd72b9 | 924 | |
7fa3d080 BW |
925 | if (!free_insn_labels) |
926 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
927 | else | |
43cd72b9 | 928 | { |
7fa3d080 BW |
929 | l = free_insn_labels; |
930 | free_insn_labels = l->next; | |
931 | } | |
932 | ||
933 | l->sym = sym; | |
934 | l->next = insn_labels; | |
935 | insn_labels = l; | |
936 | } | |
937 | ||
938 | ||
939 | static void | |
940 | xtensa_clear_insn_labels (void) | |
941 | { | |
942 | sym_list **pl; | |
943 | ||
944 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
945 | ; | |
946 | *pl = insn_labels; | |
947 | insn_labels = NULL; | |
948 | } | |
949 | ||
950 | ||
951 | /* The "loops_ok" argument is provided to allow ignoring labels that | |
952 | define loop ends. This fixes a bug where the NOPs to align a | |
953 | loop opcode were included in a previous zero-cost loop: | |
954 | ||
955 | loop a0, loopend | |
956 | <loop1 body> | |
957 | loopend: | |
958 | ||
959 | loop a2, loopend2 | |
960 | <loop2 body> | |
961 | ||
962 | would become: | |
963 | ||
964 | loop a0, loopend | |
965 | <loop1 body> | |
966 | nop.n <===== bad! | |
967 | loopend: | |
968 | ||
969 | loop a2, loopend2 | |
970 | <loop2 body> | |
971 | ||
972 | This argument is used to prevent moving the NOP to before the | |
973 | loop-end label, which is what you want in this special case. */ | |
974 | ||
975 | static void | |
976 | xtensa_move_labels (fragS *new_frag, valueT new_offset, bfd_boolean loops_ok) | |
977 | { | |
978 | sym_list *lit; | |
979 | ||
980 | for (lit = insn_labels; lit; lit = lit->next) | |
981 | { | |
982 | symbolS *lit_sym = lit->sym; | |
983 | if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target) | |
984 | { | |
985 | S_SET_VALUE (lit_sym, new_offset); | |
986 | symbol_set_frag (lit_sym, new_frag); | |
987 | } | |
43cd72b9 BW |
988 | } |
989 | } | |
990 | ||
e0001a05 NC |
991 | \f |
992 | /* Directive data and functions. */ | |
993 | ||
994 | typedef struct state_stackS_struct | |
995 | { | |
996 | directiveE directive; | |
997 | bfd_boolean negated; | |
998 | bfd_boolean old_state; | |
999 | const char *file; | |
1000 | unsigned int line; | |
1001 | const void *datum; | |
1002 | struct state_stackS_struct *prev; | |
1003 | } state_stackS; | |
1004 | ||
1005 | state_stackS *directive_state_stack; | |
1006 | ||
1007 | const pseudo_typeS md_pseudo_table[] = | |
1008 | { | |
43cd72b9 BW |
1009 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1010 | { "literal_position", xtensa_literal_position, 0 }, | |
1011 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1012 | { "long", xtensa_elf_cons, 4 }, | |
1013 | { "word", xtensa_elf_cons, 4 }, | |
1014 | { "short", xtensa_elf_cons, 2 }, | |
1015 | { "begin", xtensa_begin_directive, 0 }, | |
1016 | { "end", xtensa_end_directive, 0 }, | |
1017 | { "loc", xtensa_dwarf2_directive_loc, 0 }, | |
1018 | { "literal", xtensa_literal_pseudo, 0 }, | |
1019 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1020 | { NULL, 0, 0 }, | |
e0001a05 NC |
1021 | }; |
1022 | ||
1023 | ||
7fa3d080 BW |
1024 | static bfd_boolean |
1025 | use_transform (void) | |
e0001a05 | 1026 | { |
43cd72b9 BW |
1027 | /* After md_end, you should be checking frag by frag, rather |
1028 | than state directives. */ | |
1029 | assert (!past_xtensa_end); | |
1030 | return directive_state[directive_transform]; | |
e0001a05 NC |
1031 | } |
1032 | ||
1033 | ||
7fa3d080 BW |
1034 | static bfd_boolean |
1035 | do_align_targets (void) | |
e0001a05 | 1036 | { |
7b1cc377 BW |
1037 | /* Do not use this function after md_end; just look at align_targets |
1038 | instead. There is no target-align directive, so alignment is either | |
1039 | enabled for all frags or not done at all. */ | |
43cd72b9 BW |
1040 | assert (!past_xtensa_end); |
1041 | return align_targets && use_transform (); | |
e0001a05 NC |
1042 | } |
1043 | ||
1044 | ||
1045 | static void | |
7fa3d080 | 1046 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 NC |
1047 | { |
1048 | char *file; | |
1049 | unsigned int line; | |
1050 | state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); | |
1051 | ||
1052 | as_where (&file, &line); | |
1053 | ||
1054 | stack->directive = directive; | |
1055 | stack->negated = negated; | |
1056 | stack->old_state = directive_state[directive]; | |
1057 | stack->file = file; | |
1058 | stack->line = line; | |
1059 | stack->datum = datum; | |
1060 | stack->prev = directive_state_stack; | |
1061 | directive_state_stack = stack; | |
1062 | ||
1063 | directive_state[directive] = !negated; | |
1064 | } | |
1065 | ||
7fa3d080 | 1066 | |
e0001a05 | 1067 | static void |
7fa3d080 BW |
1068 | directive_pop (directiveE *directive, |
1069 | bfd_boolean *negated, | |
1070 | const char **file, | |
1071 | unsigned int *line, | |
1072 | const void **datum) | |
e0001a05 NC |
1073 | { |
1074 | state_stackS *top = directive_state_stack; | |
1075 | ||
1076 | if (!directive_state_stack) | |
1077 | { | |
1078 | as_bad (_("unmatched end directive")); | |
1079 | *directive = directive_none; | |
1080 | return; | |
1081 | } | |
1082 | ||
1083 | directive_state[directive_state_stack->directive] = top->old_state; | |
1084 | *directive = top->directive; | |
1085 | *negated = top->negated; | |
1086 | *file = top->file; | |
1087 | *line = top->line; | |
1088 | *datum = top->datum; | |
1089 | directive_state_stack = top->prev; | |
1090 | free (top); | |
1091 | } | |
1092 | ||
1093 | ||
1094 | static void | |
7fa3d080 | 1095 | directive_balance (void) |
e0001a05 NC |
1096 | { |
1097 | while (directive_state_stack) | |
1098 | { | |
1099 | directiveE directive; | |
1100 | bfd_boolean negated; | |
1101 | const char *file; | |
1102 | unsigned int line; | |
1103 | const void *datum; | |
1104 | ||
1105 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1106 | as_warn_where ((char *) file, line, | |
1107 | _(".begin directive with no matching .end directive")); | |
1108 | } | |
1109 | } | |
1110 | ||
1111 | ||
1112 | static bfd_boolean | |
7fa3d080 | 1113 | inside_directive (directiveE dir) |
e0001a05 NC |
1114 | { |
1115 | state_stackS *top = directive_state_stack; | |
1116 | ||
1117 | while (top && top->directive != dir) | |
1118 | top = top->prev; | |
1119 | ||
1120 | return (top != NULL); | |
1121 | } | |
1122 | ||
1123 | ||
1124 | static void | |
7fa3d080 | 1125 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1126 | { |
1127 | int len; | |
1128 | unsigned i; | |
43cd72b9 | 1129 | char *directive_string; |
e0001a05 NC |
1130 | |
1131 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1132 | *negated = FALSE; | |
1133 | else | |
1134 | { | |
1135 | *negated = TRUE; | |
1136 | input_line_pointer += 3; | |
1137 | } | |
1138 | ||
1139 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1140 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1141 | ||
1142 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1143 | equivalent to .begin [no-]transform. We should remove it when | |
1144 | we stop accepting those options. */ | |
1145 | ||
1146 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) | |
1147 | { | |
1148 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1149 | directive_string = "transform"; | |
1150 | } | |
1151 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1152 | { | |
1153 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1154 | directive_string = "transform"; | |
1155 | } | |
1156 | else | |
1157 | directive_string = input_line_pointer; | |
e0001a05 NC |
1158 | |
1159 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1160 | { | |
43cd72b9 | 1161 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1162 | { |
1163 | input_line_pointer += len; | |
1164 | *directive = (directiveE) i; | |
1165 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1166 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1167 | directive_info[i].name); |
1168 | return; | |
1169 | } | |
1170 | } | |
1171 | ||
1172 | as_bad (_("unknown directive")); | |
1173 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1174 | } | |
1175 | ||
1176 | ||
1177 | static void | |
7fa3d080 | 1178 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1179 | { |
1180 | directiveE directive; | |
1181 | bfd_boolean negated; | |
1182 | emit_state *state; | |
1183 | int len; | |
1184 | lit_state *ls; | |
1185 | ||
1186 | get_directive (&directive, &negated); | |
1187 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1188 | { | |
1189 | discard_rest_of_line (); | |
1190 | return; | |
1191 | } | |
1192 | ||
43cd72b9 BW |
1193 | if (cur_vinsn.inside_bundle) |
1194 | as_bad (_("directives are not valid inside bundles")); | |
1195 | ||
e0001a05 NC |
1196 | switch (directive) |
1197 | { | |
1198 | case directive_literal: | |
82e7541d BW |
1199 | if (!inside_directive (directive_literal)) |
1200 | { | |
1201 | /* Previous labels go with whatever follows this directive, not with | |
1202 | the literal, so save them now. */ | |
1203 | saved_insn_labels = insn_labels; | |
1204 | insn_labels = NULL; | |
1205 | } | |
43cd72b9 | 1206 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
e0001a05 NC |
1207 | state = (emit_state *) xmalloc (sizeof (emit_state)); |
1208 | xtensa_switch_to_literal_fragment (state); | |
1209 | directive_push (directive_literal, negated, state); | |
1210 | break; | |
1211 | ||
1212 | case directive_literal_prefix: | |
43cd72b9 BW |
1213 | /* Have to flush pending output because a movi relaxed to an l32r |
1214 | might produce a literal. */ | |
1215 | md_flush_pending_output (); | |
e0001a05 NC |
1216 | /* Check to see if the current fragment is a literal |
1217 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1218 | if (generating_literals) |
e0001a05 NC |
1219 | { |
1220 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1221 | return; | |
1222 | } | |
1223 | ||
1224 | /* Allocate the literal state for this section and push | |
1225 | onto the directive stack. */ | |
1226 | ls = xmalloc (sizeof (lit_state)); | |
1227 | assert (ls); | |
1228 | ||
1229 | *ls = default_lit_sections; | |
1230 | ||
1231 | directive_push (directive_literal_prefix, negated, ls); | |
1232 | ||
1233 | /* Parse the new prefix from the input_line_pointer. */ | |
1234 | SKIP_WHITESPACE (); | |
1235 | len = strspn (input_line_pointer, | |
1236 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1237 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
1238 | ||
1239 | /* Process the new prefix. */ | |
1240 | xtensa_literal_prefix (input_line_pointer, len); | |
1241 | ||
1242 | /* Skip the name in the input line. */ | |
1243 | input_line_pointer += len; | |
1244 | break; | |
1245 | ||
1246 | case directive_freeregs: | |
1247 | /* This information is currently unused, but we'll accept the statement | |
1248 | and just discard the rest of the line. This won't check the syntax, | |
1249 | but it will accept every correct freeregs directive. */ | |
1250 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1251 | directive_push (directive_freeregs, negated, 0); | |
1252 | break; | |
1253 | ||
43cd72b9 BW |
1254 | case directive_schedule: |
1255 | md_flush_pending_output (); | |
1256 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1257 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1258 | directive_push (directive_schedule, negated, 0); | |
1259 | xtensa_set_frag_assembly_state (frag_now); | |
1260 | break; | |
1261 | ||
e0001a05 | 1262 | case directive_density: |
43cd72b9 BW |
1263 | as_warn (_(".begin [no-]density is ignored")); |
1264 | break; | |
1265 | ||
1266 | case directive_absolute_literals: | |
1267 | md_flush_pending_output (); | |
1268 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1269 | { |
43cd72b9 | 1270 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1271 | break; |
1272 | } | |
43cd72b9 BW |
1273 | xtensa_set_frag_assembly_state (frag_now); |
1274 | directive_push (directive, negated, 0); | |
1275 | break; | |
e0001a05 NC |
1276 | |
1277 | default: | |
43cd72b9 BW |
1278 | md_flush_pending_output (); |
1279 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1280 | directive_push (directive, negated, 0); |
1281 | break; | |
1282 | } | |
1283 | ||
1284 | demand_empty_rest_of_line (); | |
1285 | } | |
1286 | ||
1287 | ||
1288 | static void | |
7fa3d080 | 1289 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1290 | { |
1291 | directiveE begin_directive, end_directive; | |
1292 | bfd_boolean begin_negated, end_negated; | |
1293 | const char *file; | |
1294 | unsigned int line; | |
1295 | emit_state *state; | |
43cd72b9 | 1296 | emit_state **state_ptr; |
e0001a05 NC |
1297 | lit_state *s; |
1298 | ||
43cd72b9 BW |
1299 | if (cur_vinsn.inside_bundle) |
1300 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1301 | |
e0001a05 | 1302 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1303 | |
1304 | md_flush_pending_output (); | |
1305 | ||
1306 | switch (end_directive) | |
e0001a05 | 1307 | { |
43cd72b9 | 1308 | case (directiveE) XTENSA_UNDEFINED: |
e0001a05 NC |
1309 | discard_rest_of_line (); |
1310 | return; | |
e0001a05 | 1311 | |
43cd72b9 BW |
1312 | case directive_density: |
1313 | as_warn (_(".end [no-]density is ignored")); | |
e0001a05 | 1314 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1315 | break; |
1316 | ||
1317 | case directive_absolute_literals: | |
1318 | if (!absolute_literals_supported && !end_negated) | |
1319 | { | |
1320 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1321 | demand_empty_rest_of_line (); | |
1322 | return; | |
1323 | } | |
1324 | break; | |
1325 | ||
1326 | default: | |
1327 | break; | |
e0001a05 NC |
1328 | } |
1329 | ||
43cd72b9 | 1330 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1331 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1332 | (const void **) state_ptr); |
e0001a05 NC |
1333 | |
1334 | if (begin_directive != directive_none) | |
1335 | { | |
1336 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1337 | { | |
1338 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1339 | begin_negated ? "no-" : "", | |
1340 | directive_info[begin_directive].name, file, line); | |
1341 | } | |
1342 | else | |
1343 | { | |
1344 | switch (end_directive) | |
1345 | { | |
1346 | case directive_literal: | |
1347 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1348 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1349 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1350 | free (state); |
82e7541d BW |
1351 | if (!inside_directive (directive_literal)) |
1352 | { | |
1353 | /* Restore the list of current labels. */ | |
1354 | xtensa_clear_insn_labels (); | |
1355 | insn_labels = saved_insn_labels; | |
1356 | } | |
e0001a05 NC |
1357 | break; |
1358 | ||
e0001a05 NC |
1359 | case directive_literal_prefix: |
1360 | /* Restore the default collection sections from saved state. */ | |
1361 | s = (lit_state *) state; | |
1362 | assert (s); | |
1363 | ||
1364 | if (use_literal_section) | |
1365 | default_lit_sections = *s; | |
1366 | ||
1367 | /* free the state storage */ | |
1368 | free (s); | |
1369 | break; | |
1370 | ||
43cd72b9 BW |
1371 | case directive_schedule: |
1372 | case directive_freeregs: | |
1373 | break; | |
1374 | ||
e0001a05 | 1375 | default: |
43cd72b9 | 1376 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1377 | break; |
1378 | } | |
1379 | } | |
1380 | } | |
1381 | ||
1382 | demand_empty_rest_of_line (); | |
1383 | } | |
1384 | ||
1385 | ||
43cd72b9 BW |
1386 | /* Wrap dwarf2 functions so that we correctly support the .loc directive. */ |
1387 | ||
1388 | static bfd_boolean xtensa_loc_directive_seen = FALSE; | |
1389 | ||
1390 | static void | |
7fa3d080 | 1391 | xtensa_dwarf2_directive_loc (int x) |
43cd72b9 BW |
1392 | { |
1393 | xtensa_loc_directive_seen = TRUE; | |
1394 | dwarf2_directive_loc (x); | |
1395 | } | |
1396 | ||
1397 | ||
1398 | static void | |
7fa3d080 | 1399 | xtensa_dwarf2_emit_insn (int size, struct dwarf2_line_info *loc) |
43cd72b9 BW |
1400 | { |
1401 | if (debug_type != DEBUG_DWARF2 && ! xtensa_loc_directive_seen) | |
1402 | return; | |
1403 | xtensa_loc_directive_seen = FALSE; | |
1404 | dwarf2_gen_line_info (frag_now_fix () - size, loc); | |
1405 | } | |
1406 | ||
1407 | ||
e0001a05 NC |
1408 | /* Place an aligned literal fragment at the current location. */ |
1409 | ||
1410 | static void | |
7fa3d080 | 1411 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1412 | { |
43cd72b9 BW |
1413 | md_flush_pending_output (); |
1414 | ||
e0001a05 NC |
1415 | if (inside_directive (directive_literal)) |
1416 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1417 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1418 | |
1419 | demand_empty_rest_of_line (); | |
82e7541d | 1420 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1421 | } |
1422 | ||
1423 | ||
43cd72b9 | 1424 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1425 | |
1426 | static void | |
7fa3d080 | 1427 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1428 | { |
1429 | emit_state state; | |
1745fcba | 1430 | char *p, *base_name; |
e0001a05 | 1431 | char c; |
e0001a05 NC |
1432 | segT dest_seg; |
1433 | ||
82e7541d BW |
1434 | if (inside_directive (directive_literal)) |
1435 | { | |
1436 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1437 | ignore_rest_of_line (); | |
1438 | return; | |
1439 | } | |
1440 | ||
43cd72b9 BW |
1441 | md_flush_pending_output (); |
1442 | ||
82e7541d BW |
1443 | /* Previous labels go with whatever follows this directive, not with |
1444 | the literal, so save them now. */ | |
1445 | saved_insn_labels = insn_labels; | |
1446 | insn_labels = NULL; | |
1447 | ||
e0001a05 NC |
1448 | /* If we are using text-section literals, then this is the right value... */ |
1449 | dest_seg = now_seg; | |
1450 | ||
1451 | base_name = input_line_pointer; | |
1452 | ||
1453 | xtensa_switch_to_literal_fragment (&state); | |
1454 | ||
43cd72b9 | 1455 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1456 | need to put them in the section we just switched to. */ |
43cd72b9 | 1457 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1458 | dest_seg = now_seg; |
1459 | ||
43cd72b9 BW |
1460 | /* All literals are aligned to four-byte boundaries. */ |
1461 | frag_align (2, 0, 0); | |
1462 | record_alignment (now_seg, 2); | |
e0001a05 NC |
1463 | |
1464 | c = get_symbol_end (); | |
1465 | /* Just after name is now '\0'. */ | |
1466 | p = input_line_pointer; | |
1467 | *p = c; | |
1468 | SKIP_WHITESPACE (); | |
1469 | ||
1470 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1471 | { | |
1472 | as_bad (_("expected comma or colon after symbol name; " | |
1473 | "rest of line ignored")); | |
1474 | ignore_rest_of_line (); | |
1475 | xtensa_restore_emit_state (&state); | |
1476 | return; | |
1477 | } | |
1478 | *p = 0; | |
1479 | ||
e0001a05 | 1480 | colon (base_name); |
e0001a05 | 1481 | |
e0001a05 | 1482 | *p = c; |
43cd72b9 | 1483 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1484 | |
43cd72b9 | 1485 | xtensa_elf_cons (4); |
e0001a05 NC |
1486 | |
1487 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1488 | |
1489 | /* Restore the list of current labels. */ | |
1490 | xtensa_clear_insn_labels (); | |
1491 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1492 | } |
1493 | ||
1494 | ||
1495 | static void | |
7fa3d080 | 1496 | xtensa_literal_prefix (char const *start, int len) |
e0001a05 | 1497 | { |
43cd72b9 BW |
1498 | char *name, *linkonce_suffix; |
1499 | char *newname, *newname4; | |
1500 | size_t linkonce_len; | |
e0001a05 NC |
1501 | |
1502 | /* Get a null-terminated copy of the name. */ | |
1503 | name = xmalloc (len + 1); | |
1504 | assert (name); | |
1505 | ||
1506 | strncpy (name, start, len); | |
1507 | name[len] = 0; | |
1508 | ||
1509 | /* Allocate the sections (interesting note: the memory pointing to | |
1510 | the name is actually used for the name by the new section). */ | |
43cd72b9 | 1511 | |
e0001a05 | 1512 | newname = xmalloc (len + strlen (".literal") + 1); |
43cd72b9 | 1513 | newname4 = xmalloc (len + strlen (".lit4") + 1); |
e0001a05 | 1514 | |
43cd72b9 BW |
1515 | linkonce_len = sizeof (".gnu.linkonce.") - 1; |
1516 | if (strncmp (name, ".gnu.linkonce.", linkonce_len) == 0 | |
1517 | && (linkonce_suffix = strchr (name + linkonce_len, '.')) != 0) | |
1518 | { | |
1519 | strcpy (newname, ".gnu.linkonce.literal"); | |
1520 | strcpy (newname4, ".gnu.linkonce.lit4"); | |
e0001a05 | 1521 | |
43cd72b9 BW |
1522 | strcat (newname, linkonce_suffix); |
1523 | strcat (newname4, linkonce_suffix); | |
1524 | } | |
1525 | else | |
1526 | { | |
1527 | int suffix_pos = len; | |
1528 | ||
1529 | /* If the section name ends with ".text", then replace that suffix | |
1530 | instead of appending an additional suffix. */ | |
1531 | if (len >= 5 && strcmp (name + len - 5, ".text") == 0) | |
1532 | suffix_pos -= 5; | |
1533 | ||
1534 | strcpy (newname, name); | |
1535 | strcpy (newname4, name); | |
1536 | ||
1537 | strcpy (newname + suffix_pos, ".literal"); | |
1538 | strcpy (newname4 + suffix_pos, ".lit4"); | |
1539 | } | |
1540 | ||
b08b5071 | 1541 | /* Note that cache_literal_section does not create a segment if |
43cd72b9 BW |
1542 | it already exists. */ |
1543 | default_lit_sections.lit_seg = NULL; | |
1544 | default_lit_sections.lit4_seg = NULL; | |
1545 | ||
1546 | /* Canonicalizing section names allows renaming literal | |
e0001a05 | 1547 | sections to occur correctly. */ |
43cd72b9 BW |
1548 | default_lit_sections.lit_seg_name = tc_canonicalize_symbol_name (newname); |
1549 | default_lit_sections.lit4_seg_name = tc_canonicalize_symbol_name (newname4); | |
e0001a05 NC |
1550 | |
1551 | free (name); | |
43cd72b9 BW |
1552 | } |
1553 | ||
1554 | ||
1555 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1556 | ||
1557 | static void | |
7fa3d080 | 1558 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1559 | { |
1560 | float fall_through_f, target_f; | |
43cd72b9 BW |
1561 | |
1562 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1563 | if (fall_through_f < 0) | |
1564 | { | |
1565 | as_bad (_("fall through frequency must be greater than 0")); | |
1566 | ignore_rest_of_line (); | |
1567 | return; | |
1568 | } | |
1569 | ||
1570 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1571 | if (target_f < 0) | |
1572 | { | |
1573 | as_bad (_("branch target frequency must be greater than 0")); | |
1574 | ignore_rest_of_line (); | |
1575 | return; | |
1576 | } | |
1577 | ||
b08b5071 | 1578 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1579 | |
1580 | demand_empty_rest_of_line (); | |
1581 | } | |
1582 | ||
1583 | ||
1584 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1585 | Clobbers input_line_pointer, checks end-of-line. */ | |
1586 | ||
1587 | static void | |
7fa3d080 | 1588 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1589 | { |
1590 | expressionS exp; | |
1591 | bfd_reloc_code_real_type reloc; | |
1592 | ||
1593 | md_flush_pending_output (); | |
1594 | ||
1595 | if (cur_vinsn.inside_bundle) | |
1596 | as_bad (_("directives are not valid inside bundles")); | |
1597 | ||
1598 | if (is_it_end_of_statement ()) | |
1599 | { | |
1600 | demand_empty_rest_of_line (); | |
1601 | return; | |
1602 | } | |
1603 | ||
1604 | do | |
1605 | { | |
1606 | expression (&exp); | |
1607 | if (exp.X_op == O_symbol | |
1608 | && *input_line_pointer == '@' | |
1609 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1610 | != BFD_RELOC_NONE)) | |
1611 | { | |
1612 | reloc_howto_type *reloc_howto = | |
1613 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1614 | ||
1615 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1616 | as_bad (_("unsupported relocation")); | |
1617 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1618 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1619 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1620 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1621 | as_bad (_("opcode-specific %s relocation used outside " | |
1622 | "an instruction"), reloc_howto->name); | |
1623 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
1624 | as_bad (_("%s relocations do not fit in %d bytes"), | |
1625 | reloc_howto->name, nbytes); | |
1626 | else | |
1627 | { | |
1628 | char *p = frag_more ((int) nbytes); | |
1629 | xtensa_set_frag_assembly_state (frag_now); | |
1630 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1631 | nbytes, &exp, 0, reloc); | |
1632 | } | |
1633 | } | |
1634 | else | |
1635 | emit_expr (&exp, (unsigned int) nbytes); | |
1636 | } | |
1637 | while (*input_line_pointer++ == ','); | |
1638 | ||
1639 | input_line_pointer--; /* Put terminator back into stream. */ | |
1640 | demand_empty_rest_of_line (); | |
1641 | } | |
1642 | ||
7fa3d080 BW |
1643 | \f |
1644 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1645 | |
1646 | /* Parse @plt, etc. and return the desired relocation. */ | |
1647 | static bfd_reloc_code_real_type | |
7fa3d080 | 1648 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 BW |
1649 | { |
1650 | struct map_bfd | |
1651 | { | |
1652 | char *string; | |
1653 | int length; | |
1654 | bfd_reloc_code_real_type reloc; | |
1655 | }; | |
1656 | ||
1657 | char ident[20]; | |
1658 | char *str = *str_p; | |
1659 | char *str2; | |
1660 | int ch; | |
1661 | int len; | |
1662 | struct map_bfd *ptr; | |
1663 | ||
1664 | #define MAP(str,reloc) { str, sizeof (str) - 1, reloc } | |
e0001a05 | 1665 | |
43cd72b9 BW |
1666 | static struct map_bfd mapping[] = |
1667 | { | |
1668 | MAP ("l", BFD_RELOC_LO16), | |
1669 | MAP ("h", BFD_RELOC_HI16), | |
1670 | MAP ("plt", BFD_RELOC_XTENSA_PLT), | |
1671 | { (char *) 0, 0, BFD_RELOC_UNUSED } | |
1672 | }; | |
1673 | ||
1674 | if (*str++ != '@') | |
1675 | return BFD_RELOC_NONE; | |
1676 | ||
1677 | for (ch = *str, str2 = ident; | |
1678 | (str2 < ident + sizeof (ident) - 1 | |
1679 | && (ISALNUM (ch) || ch == '@')); | |
1680 | ch = *++str) | |
1681 | { | |
1682 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1683 | } | |
1684 | ||
1685 | *str2 = '\0'; | |
1686 | len = str2 - ident; | |
1687 | ||
1688 | ch = ident[0]; | |
1689 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
1690 | if (ch == ptr->string[0] | |
1691 | && len == ptr->length | |
1692 | && memcmp (ident, ptr->string, ptr->length) == 0) | |
1693 | { | |
1694 | /* Now check for "identifier@suffix+constant". */ | |
1695 | if (*str == '-' || *str == '+') | |
1696 | { | |
1697 | char *orig_line = input_line_pointer; | |
1698 | expressionS new_exp; | |
1699 | ||
1700 | input_line_pointer = str; | |
1701 | expression (&new_exp); | |
1702 | if (new_exp.X_op == O_constant) | |
1703 | { | |
1704 | exp_p->X_add_number += new_exp.X_add_number; | |
1705 | str = input_line_pointer; | |
1706 | } | |
1707 | ||
1708 | if (&input_line_pointer != str_p) | |
1709 | input_line_pointer = orig_line; | |
1710 | } | |
1711 | ||
1712 | *str_p = str; | |
1713 | return ptr->reloc; | |
1714 | } | |
1715 | ||
1716 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1717 | } |
1718 | ||
e0001a05 NC |
1719 | |
1720 | static const char * | |
7fa3d080 | 1721 | expression_end (const char *name) |
e0001a05 NC |
1722 | { |
1723 | while (1) | |
1724 | { | |
1725 | switch (*name) | |
1726 | { | |
43cd72b9 | 1727 | case '}': |
e0001a05 NC |
1728 | case ';': |
1729 | case '\0': | |
1730 | case ',': | |
43cd72b9 | 1731 | case ':': |
e0001a05 NC |
1732 | return name; |
1733 | case ' ': | |
1734 | case '\t': | |
1735 | ++name; | |
1736 | continue; | |
1737 | default: | |
1738 | return 0; | |
1739 | } | |
1740 | } | |
1741 | } | |
1742 | ||
1743 | ||
1744 | #define ERROR_REG_NUM ((unsigned) -1) | |
1745 | ||
1746 | static unsigned | |
7fa3d080 | 1747 | tc_get_register (const char *prefix) |
e0001a05 NC |
1748 | { |
1749 | unsigned reg; | |
1750 | const char *next_expr; | |
1751 | const char *old_line_pointer; | |
1752 | ||
1753 | SKIP_WHITESPACE (); | |
1754 | old_line_pointer = input_line_pointer; | |
1755 | ||
1756 | if (*input_line_pointer == '$') | |
1757 | ++input_line_pointer; | |
1758 | ||
1759 | /* Accept "sp" as a synonym for "a1". */ | |
1760 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1761 | && expression_end (input_line_pointer + 2)) | |
1762 | { | |
1763 | input_line_pointer += 2; | |
1764 | return 1; /* AR[1] */ | |
1765 | } | |
1766 | ||
1767 | while (*input_line_pointer++ == *prefix++) | |
1768 | ; | |
1769 | --input_line_pointer; | |
1770 | --prefix; | |
1771 | ||
1772 | if (*prefix) | |
1773 | { | |
1774 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1775 | return ERROR_REG_NUM; | |
1776 | } | |
1777 | ||
1778 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1779 | { | |
1780 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1781 | return ERROR_REG_NUM; | |
1782 | } | |
1783 | ||
1784 | reg = 0; | |
1785 | ||
1786 | while (ISDIGIT ((int) *input_line_pointer)) | |
1787 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1788 | ||
1789 | if (!(next_expr = expression_end (input_line_pointer))) | |
1790 | { | |
1791 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1792 | return ERROR_REG_NUM; | |
1793 | } | |
1794 | ||
1795 | input_line_pointer = (char *) next_expr; | |
1796 | ||
1797 | return reg; | |
1798 | } | |
1799 | ||
1800 | ||
e0001a05 | 1801 | static void |
7fa3d080 | 1802 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1803 | { |
43cd72b9 | 1804 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1805 | |
43cd72b9 BW |
1806 | /* Check if this is an immediate operand. */ |
1807 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1808 | { |
43cd72b9 | 1809 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1810 | segT t = expression (tok); |
43cd72b9 BW |
1811 | if (t == absolute_section |
1812 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 NC |
1813 | { |
1814 | assert (tok->X_op == O_constant); | |
1815 | tok->X_op = O_symbol; | |
1816 | tok->X_add_symbol = &abs_symbol; | |
1817 | } | |
43cd72b9 BW |
1818 | |
1819 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
1820 | && (reloc = xtensa_elf_suffix (&input_line_pointer, tok)) | |
1821 | && (reloc != BFD_RELOC_NONE)) | |
e0001a05 | 1822 | { |
43cd72b9 BW |
1823 | switch (reloc) |
1824 | { | |
1825 | default: | |
1826 | case BFD_RELOC_UNUSED: | |
1827 | as_bad (_("unsupported relocation")); | |
1828 | break; | |
1829 | ||
1830 | case BFD_RELOC_XTENSA_PLT: | |
1831 | tok->X_op = O_pltrel; | |
1832 | break; | |
1833 | ||
1834 | case BFD_RELOC_LO16: | |
1835 | if (tok->X_op == O_constant) | |
1836 | tok->X_add_number &= 0xffff; | |
1837 | else | |
1838 | tok->X_op = O_lo16; | |
1839 | break; | |
1840 | ||
1841 | case BFD_RELOC_HI16: | |
1842 | if (tok->X_op == O_constant) | |
1843 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; | |
1844 | else | |
1845 | tok->X_op = O_hi16; | |
1846 | break; | |
1847 | } | |
e0001a05 | 1848 | } |
e0001a05 NC |
1849 | } |
1850 | else | |
1851 | { | |
43cd72b9 BW |
1852 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1853 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1854 | |
1855 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1856 | { | |
1857 | uint32 buf = reg; | |
43cd72b9 | 1858 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1859 | as_bad (_("register number out of range")); |
1860 | } | |
1861 | ||
1862 | tok->X_op = O_register; | |
1863 | tok->X_add_symbol = 0; | |
1864 | tok->X_add_number = reg; | |
1865 | } | |
1866 | } | |
1867 | ||
1868 | ||
1869 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1870 | ||
1871 | static int | |
7fa3d080 | 1872 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1873 | { |
1874 | char *old_input_line_pointer; | |
1875 | bfd_boolean saw_comma = FALSE; | |
1876 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1877 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1878 | int num_args = 0; |
1879 | char *arg_end, *arg; | |
1880 | int arg_len; | |
43cd72b9 BW |
1881 | |
1882 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1883 | old_input_line_pointer = input_line_pointer; |
1884 | input_line_pointer = str; | |
1885 | ||
1886 | while (*input_line_pointer) | |
1887 | { | |
1888 | SKIP_WHITESPACE (); | |
1889 | switch (*input_line_pointer) | |
1890 | { | |
1891 | case '\0': | |
43cd72b9 | 1892 | case '}': |
e0001a05 NC |
1893 | goto fini; |
1894 | ||
43cd72b9 BW |
1895 | case ':': |
1896 | input_line_pointer++; | |
1897 | if (saw_comma || saw_colon || !saw_arg) | |
1898 | goto err; | |
1899 | saw_colon = TRUE; | |
1900 | break; | |
1901 | ||
e0001a05 NC |
1902 | case ',': |
1903 | input_line_pointer++; | |
43cd72b9 | 1904 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
1905 | goto err; |
1906 | saw_comma = TRUE; | |
1907 | break; | |
1908 | ||
1909 | default: | |
43cd72b9 | 1910 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
1911 | goto err; |
1912 | ||
1913 | arg_end = input_line_pointer + 1; | |
1914 | while (!expression_end (arg_end)) | |
1915 | arg_end += 1; | |
43cd72b9 | 1916 | |
e0001a05 | 1917 | arg_len = arg_end - input_line_pointer; |
43cd72b9 | 1918 | arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
1919 | args[num_args] = arg; |
1920 | ||
43cd72b9 BW |
1921 | if (saw_colon) |
1922 | *arg++ = ':'; | |
e0001a05 NC |
1923 | strncpy (arg, input_line_pointer, arg_len); |
1924 | arg[arg_len] = '\0'; | |
43cd72b9 | 1925 | |
e0001a05 NC |
1926 | input_line_pointer = arg_end; |
1927 | num_args += 1; | |
1928 | saw_comma = FALSE; | |
43cd72b9 | 1929 | saw_colon = FALSE; |
e0001a05 NC |
1930 | saw_arg = TRUE; |
1931 | break; | |
1932 | } | |
1933 | } | |
1934 | ||
1935 | fini: | |
43cd72b9 | 1936 | if (saw_comma || saw_colon) |
e0001a05 NC |
1937 | goto err; |
1938 | input_line_pointer = old_input_line_pointer; | |
1939 | return num_args; | |
1940 | ||
1941 | err: | |
43cd72b9 BW |
1942 | if (saw_comma) |
1943 | as_bad (_("extra comma")); | |
1944 | else if (saw_colon) | |
1945 | as_bad (_("extra colon")); | |
1946 | else if (!saw_arg) | |
1947 | as_bad (_("missing argument")); | |
1948 | else | |
1949 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
1950 | input_line_pointer = old_input_line_pointer; |
1951 | return -1; | |
1952 | } | |
1953 | ||
1954 | ||
43cd72b9 | 1955 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
1956 | |
1957 | static bfd_boolean | |
7fa3d080 | 1958 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 1959 | { |
43cd72b9 | 1960 | expressionS *tok, *last_tok; |
e0001a05 NC |
1961 | xtensa_opcode opcode = insn->opcode; |
1962 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
1963 | xtensa_isa isa = xtensa_default_isa; |
1964 | int n, num_regs = 0; | |
e0001a05 | 1965 | int opcode_operand_count; |
43cd72b9 BW |
1966 | int opnd_cnt, last_opnd_cnt; |
1967 | unsigned int next_reg = 0; | |
e0001a05 NC |
1968 | char *old_input_line_pointer; |
1969 | ||
1970 | if (insn->insn_type == ITYPE_LITERAL) | |
1971 | opcode_operand_count = 1; | |
1972 | else | |
43cd72b9 | 1973 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 1974 | |
43cd72b9 | 1975 | tok = insn->tok; |
e0001a05 NC |
1976 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
1977 | ||
1978 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
1979 | old_input_line_pointer = input_line_pointer; |
1980 | ||
1981 | last_tok = 0; | |
1982 | last_opnd_cnt = -1; | |
1983 | opnd_cnt = 0; | |
1984 | ||
1985 | /* Skip invisible operands. */ | |
1986 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
1987 | { | |
1988 | opnd_cnt += 1; | |
1989 | tok++; | |
1990 | } | |
e0001a05 NC |
1991 | |
1992 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 1993 | { |
e0001a05 | 1994 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
1995 | if (*input_line_pointer == ':') |
1996 | { | |
1997 | xtensa_regfile opnd_rf; | |
1998 | input_line_pointer++; | |
1999 | if (num_regs == 0) | |
2000 | goto err; | |
2001 | assert (opnd_cnt > 0); | |
2002 | num_regs--; | |
2003 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
2004 | if (next_reg | |
2005 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
2006 | as_warn (_("incorrect register number, ignoring")); | |
2007 | next_reg++; | |
2008 | } | |
2009 | else | |
2010 | { | |
2011 | if (opnd_cnt >= opcode_operand_count) | |
2012 | { | |
2013 | as_warn (_("too many arguments")); | |
2014 | goto err; | |
2015 | } | |
2016 | assert (opnd_cnt < MAX_INSN_ARGS); | |
2017 | ||
2018 | expression_maybe_register (opcode, opnd_cnt, tok); | |
2019 | next_reg = tok->X_add_number + 1; | |
2020 | ||
2021 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
2022 | goto err; | |
2023 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
2024 | { | |
2025 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
2026 | /* minus 1 because we are seeing one right now */ | |
2027 | } | |
2028 | else | |
2029 | num_regs = 0; | |
e0001a05 | 2030 | |
43cd72b9 BW |
2031 | last_tok = tok; |
2032 | last_opnd_cnt = opnd_cnt; | |
e0001a05 | 2033 | |
43cd72b9 BW |
2034 | do |
2035 | { | |
2036 | opnd_cnt += 1; | |
2037 | tok++; | |
2038 | } | |
2039 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
2040 | } | |
2041 | } | |
e0001a05 | 2042 | |
43cd72b9 BW |
2043 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
2044 | goto err; | |
e0001a05 NC |
2045 | |
2046 | insn->ntok = tok - insn->tok; | |
2047 | had_error = FALSE; | |
2048 | ||
2049 | err: | |
43cd72b9 | 2050 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2051 | return had_error; |
2052 | } | |
2053 | ||
2054 | ||
43cd72b9 | 2055 | static int |
7fa3d080 | 2056 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2057 | { |
2058 | xtensa_isa isa = xtensa_default_isa; | |
2059 | static xtensa_insnbuf slotbuf = NULL; | |
2060 | xtensa_format fmt; | |
2061 | xtensa_opcode opc = insn->opcode; | |
2062 | int slot, opnd, fmt_found; | |
2063 | unsigned val; | |
2064 | ||
2065 | if (!slotbuf) | |
2066 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2067 | ||
2068 | /* Find format/slot where this can be encoded. */ | |
2069 | fmt_found = 0; | |
2070 | slot = 0; | |
2071 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2072 | { | |
2073 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2074 | { | |
2075 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2076 | { | |
2077 | fmt_found = 1; | |
2078 | break; | |
2079 | } | |
2080 | } | |
2081 | if (fmt_found) break; | |
2082 | } | |
2083 | ||
2084 | if (!fmt_found) | |
2085 | { | |
2086 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2087 | return -1; | |
2088 | } | |
2089 | ||
2090 | /* First encode all the visible operands | |
2091 | (to deal with shared field operands). */ | |
2092 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2093 | { | |
2094 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2095 | && (insn->tok[opnd].X_op == O_register | |
2096 | || insn->tok[opnd].X_op == O_constant)) | |
2097 | { | |
2098 | val = insn->tok[opnd].X_add_number; | |
2099 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2100 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2101 | } | |
2102 | } | |
2103 | ||
2104 | /* Then pull out the values for the invisible ones. */ | |
2105 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2106 | { | |
2107 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2108 | { | |
2109 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2110 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2111 | insn->tok[opnd].X_add_number = val; | |
2112 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2113 | insn->tok[opnd].X_op = O_register; | |
2114 | else | |
2115 | insn->tok[opnd].X_op = O_constant; | |
2116 | } | |
2117 | } | |
2118 | ||
2119 | return 0; | |
2120 | } | |
2121 | ||
2122 | ||
e0001a05 | 2123 | static void |
7fa3d080 | 2124 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2125 | { |
2126 | char *cnt_arg, *new_arg; | |
2127 | cnt_arg = *cnt_argp; | |
2128 | ||
2129 | /* replace the argument with "31-(argument)" */ | |
2130 | new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); | |
2131 | sprintf (new_arg, "31-(%s)", cnt_arg); | |
2132 | ||
2133 | free (cnt_arg); | |
2134 | *cnt_argp = new_arg; | |
2135 | } | |
2136 | ||
2137 | ||
2138 | /* If "arg" is a constant expression, return non-zero with the value | |
2139 | in *valp. */ | |
2140 | ||
2141 | static int | |
7fa3d080 | 2142 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2143 | { |
2144 | expressionS exp; | |
2145 | char *save_ptr = input_line_pointer; | |
2146 | ||
2147 | input_line_pointer = arg; | |
2148 | expression (&exp); | |
2149 | input_line_pointer = save_ptr; | |
2150 | ||
2151 | if (exp.X_op == O_constant) | |
2152 | { | |
2153 | *valp = exp.X_add_number; | |
2154 | return 1; | |
2155 | } | |
2156 | ||
2157 | return 0; | |
2158 | } | |
2159 | ||
2160 | ||
2161 | static void | |
7fa3d080 | 2162 | xg_replace_opname (char **popname, char *newop) |
e0001a05 NC |
2163 | { |
2164 | free (*popname); | |
2165 | *popname = (char *) xmalloc (strlen (newop) + 1); | |
2166 | strcpy (*popname, newop); | |
2167 | } | |
2168 | ||
2169 | ||
2170 | static int | |
7fa3d080 BW |
2171 | xg_check_num_args (int *pnum_args, |
2172 | int expected_num, | |
2173 | char *opname, | |
2174 | char **arg_strings) | |
e0001a05 NC |
2175 | { |
2176 | int num_args = *pnum_args; | |
2177 | ||
43cd72b9 | 2178 | if (num_args < expected_num) |
e0001a05 NC |
2179 | { |
2180 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2181 | num_args, opname, expected_num); | |
2182 | return -1; | |
2183 | } | |
2184 | ||
2185 | if (num_args > expected_num) | |
2186 | { | |
2187 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2188 | num_args, opname, expected_num); | |
2189 | while (num_args-- > expected_num) | |
2190 | { | |
2191 | free (arg_strings[num_args]); | |
2192 | arg_strings[num_args] = 0; | |
2193 | } | |
2194 | *pnum_args = expected_num; | |
2195 | return -1; | |
2196 | } | |
2197 | ||
2198 | return 0; | |
2199 | } | |
2200 | ||
2201 | ||
43cd72b9 BW |
2202 | /* If the register is not specified as part of the opcode, |
2203 | then get it from the operand and move it to the opcode. */ | |
2204 | ||
e0001a05 | 2205 | static int |
7fa3d080 | 2206 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2207 | { |
43cd72b9 BW |
2208 | xtensa_isa isa = xtensa_default_isa; |
2209 | xtensa_sysreg sr; | |
e0001a05 | 2210 | char *opname, *new_opname; |
43cd72b9 BW |
2211 | const char *sr_name; |
2212 | int is_user, is_write; | |
e0001a05 NC |
2213 | bfd_boolean has_underbar = FALSE; |
2214 | ||
2215 | opname = *popname; | |
2216 | if (*opname == '_') | |
2217 | { | |
2218 | has_underbar = TRUE; | |
2219 | opname += 1; | |
2220 | } | |
43cd72b9 BW |
2221 | is_user = (opname[1] == 'u'); |
2222 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2223 | |
43cd72b9 | 2224 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2225 | |
43cd72b9 BW |
2226 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2227 | return -1; | |
e0001a05 | 2228 | |
43cd72b9 BW |
2229 | /* Check if the argument is a symbolic register name. */ |
2230 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2231 | /* Handle WSR to "INTSET" as a special case. */ | |
2232 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2233 | && !strcasecmp (arg_strings[1], "intset")) | |
2234 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2235 | if (sr == XTENSA_UNDEFINED | |
2236 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2237 | { | |
2238 | /* Maybe it's a register number.... */ | |
2239 | offsetT val; | |
e0001a05 NC |
2240 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2241 | { | |
43cd72b9 BW |
2242 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2243 | arg_strings[1], opname); | |
e0001a05 NC |
2244 | return -1; |
2245 | } | |
43cd72b9 BW |
2246 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2247 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2248 | { |
43cd72b9 | 2249 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2250 | (long) val, opname); |
e0001a05 NC |
2251 | return -1; |
2252 | } | |
43cd72b9 | 2253 | } |
e0001a05 | 2254 | |
43cd72b9 BW |
2255 | /* Remove the last argument, which is now part of the opcode. */ |
2256 | free (arg_strings[1]); | |
2257 | arg_strings[1] = 0; | |
2258 | *pnum_args = 1; | |
2259 | ||
2260 | /* Translate the opcode. */ | |
2261 | sr_name = xtensa_sysreg_name (isa, sr); | |
2262 | /* Another special case for "WSR.INTSET".... */ | |
2263 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2264 | sr_name = "intset"; | |
2265 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
2266 | sprintf (new_opname, "%s%s.%s", (has_underbar ? "_" : ""), | |
2267 | *popname, sr_name); | |
2268 | free (*popname); | |
2269 | *popname = new_opname; | |
2270 | ||
2271 | return 0; | |
2272 | } | |
2273 | ||
2274 | ||
2275 | static int | |
7fa3d080 | 2276 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2277 | { |
2278 | xtensa_isa isa = xtensa_default_isa; | |
2279 | xtensa_sysreg sr; | |
2280 | char *opname, *new_opname; | |
2281 | const char *sr_name; | |
2282 | bfd_boolean has_underbar = FALSE; | |
2283 | ||
2284 | opname = *popname; | |
2285 | if (opname[0] == '_') | |
2286 | { | |
2287 | has_underbar = TRUE; | |
2288 | opname += 1; | |
2289 | } | |
2290 | ||
2291 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2292 | if (sr != XTENSA_UNDEFINED) | |
2293 | { | |
2294 | /* The new default name ("nnn") is different from the old default | |
2295 | name ("URnnn"). The old default is handled below, and we don't | |
2296 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2297 | default. */ | |
2298 | static char namebuf[10]; | |
2299 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2300 | if (strcmp (namebuf, opname + 1) == 0) | |
2301 | return 0; | |
2302 | } | |
2303 | else | |
2304 | { | |
2305 | offsetT val; | |
2306 | char *end; | |
2307 | ||
2308 | /* Only continue if the reg name is "URnnn". */ | |
2309 | if (opname[1] != 'u' || opname[2] != 'r') | |
2310 | return 0; | |
2311 | val = strtoul (opname + 3, &end, 10); | |
2312 | if (*end != '\0') | |
2313 | return 0; | |
2314 | ||
2315 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2316 | if (sr == XTENSA_UNDEFINED) | |
2317 | { | |
2318 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2319 | (long) val, opname); |
43cd72b9 BW |
2320 | return -1; |
2321 | } | |
2322 | } | |
2323 | ||
2324 | /* Translate the opcode. */ | |
2325 | sr_name = xtensa_sysreg_name (isa, sr); | |
2326 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
2327 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), | |
2328 | opname[0], sr_name); | |
2329 | free (*popname); | |
2330 | *popname = new_opname; | |
2331 | ||
2332 | return 0; | |
2333 | } | |
2334 | ||
2335 | ||
2336 | static int | |
7fa3d080 BW |
2337 | xtensa_translate_zero_immed (char *old_op, |
2338 | char *new_op, | |
2339 | char **popname, | |
2340 | int *pnum_args, | |
2341 | char **arg_strings) | |
43cd72b9 BW |
2342 | { |
2343 | char *opname; | |
2344 | offsetT val; | |
2345 | ||
2346 | opname = *popname; | |
2347 | assert (opname[0] != '_'); | |
2348 | ||
2349 | if (strcmp (opname, old_op) != 0) | |
2350 | return 0; | |
e0001a05 | 2351 | |
43cd72b9 BW |
2352 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2353 | return -1; | |
2354 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2355 | { | |
2356 | xg_replace_opname (popname, new_op); | |
2357 | free (arg_strings[1]); | |
2358 | arg_strings[1] = arg_strings[2]; | |
2359 | arg_strings[2] = 0; | |
2360 | *pnum_args = 2; | |
e0001a05 NC |
2361 | } |
2362 | ||
2363 | return 0; | |
2364 | } | |
2365 | ||
2366 | ||
2367 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2368 | Returns non-zero if an error was found. */ | |
2369 | ||
2370 | static int | |
7fa3d080 | 2371 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2372 | { |
2373 | char *opname = *popname; | |
2374 | bfd_boolean has_underbar = FALSE; | |
2375 | ||
43cd72b9 BW |
2376 | if (cur_vinsn.inside_bundle) |
2377 | return 0; | |
2378 | ||
e0001a05 NC |
2379 | if (*opname == '_') |
2380 | { | |
2381 | has_underbar = TRUE; | |
2382 | opname += 1; | |
2383 | } | |
2384 | ||
2385 | if (strcmp (opname, "mov") == 0) | |
2386 | { | |
43cd72b9 | 2387 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2388 | xg_replace_opname (popname, "mov.n"); |
2389 | else | |
2390 | { | |
2391 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2392 | return -1; | |
2393 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2394 | arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); | |
2395 | strcpy (arg_strings[2], arg_strings[1]); | |
2396 | *pnum_args = 3; | |
2397 | } | |
2398 | return 0; | |
2399 | } | |
2400 | ||
2401 | if (strcmp (opname, "bbsi.l") == 0) | |
2402 | { | |
2403 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2404 | return -1; | |
2405 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2406 | if (target_big_endian) | |
2407 | xg_reverse_shift_count (&arg_strings[1]); | |
2408 | return 0; | |
2409 | } | |
2410 | ||
2411 | if (strcmp (opname, "bbci.l") == 0) | |
2412 | { | |
2413 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2414 | return -1; | |
2415 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2416 | if (target_big_endian) | |
2417 | xg_reverse_shift_count (&arg_strings[1]); | |
2418 | return 0; | |
2419 | } | |
2420 | ||
43cd72b9 BW |
2421 | if (xtensa_nop_opcode == XTENSA_UNDEFINED |
2422 | && strcmp (opname, "nop") == 0) | |
e0001a05 | 2423 | { |
43cd72b9 | 2424 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2425 | xg_replace_opname (popname, "nop.n"); |
2426 | else | |
2427 | { | |
2428 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2429 | return -1; | |
2430 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2431 | arg_strings[0] = (char *) xmalloc (3); | |
2432 | arg_strings[1] = (char *) xmalloc (3); | |
2433 | arg_strings[2] = (char *) xmalloc (3); | |
2434 | strcpy (arg_strings[0], "a1"); | |
2435 | strcpy (arg_strings[1], "a1"); | |
2436 | strcpy (arg_strings[2], "a1"); | |
2437 | *pnum_args = 3; | |
2438 | } | |
2439 | return 0; | |
2440 | } | |
2441 | ||
43cd72b9 BW |
2442 | /* Recognize [RW]UR and [RWX]SR. */ |
2443 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2444 | && (opname[1] == 'u' || opname[1] == 's')) | |
2445 | || (opname[0] == 'x' && opname[1] == 's')) | |
2446 | && opname[2] == 'r' | |
2447 | && opname[3] == '\0') | |
e0001a05 NC |
2448 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2449 | ||
43cd72b9 BW |
2450 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2451 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2452 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2453 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2454 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2455 | |
43cd72b9 BW |
2456 | /* Relax branches that don't allow comparisons against an immediate value |
2457 | of zero to the corresponding branches with implicit zero immediates. */ | |
2458 | if (!has_underbar && use_transform ()) | |
2459 | { | |
2460 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2461 | pnum_args, arg_strings)) | |
2462 | return -1; | |
e0001a05 | 2463 | |
43cd72b9 BW |
2464 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2465 | pnum_args, arg_strings)) | |
2466 | return -1; | |
e0001a05 | 2467 | |
43cd72b9 BW |
2468 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2469 | pnum_args, arg_strings)) | |
2470 | return -1; | |
e0001a05 | 2471 | |
43cd72b9 BW |
2472 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2473 | pnum_args, arg_strings)) | |
2474 | return -1; | |
2475 | } | |
e0001a05 | 2476 | |
43cd72b9 BW |
2477 | return 0; |
2478 | } | |
e0001a05 | 2479 | |
43cd72b9 BW |
2480 | \f |
2481 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2482 | |
43cd72b9 BW |
2483 | /* Currently the assembler only allows us to use a single target per |
2484 | fragment. Because of this, only one operand for a given | |
2485 | instruction may be symbolic. If there is a PC-relative operand, | |
2486 | the last one is chosen. Otherwise, the result is the number of the | |
2487 | last immediate operand, and if there are none of those, we fail and | |
2488 | return -1. */ | |
e0001a05 | 2489 | |
7fa3d080 BW |
2490 | static int |
2491 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2492 | { |
2493 | int last_immed = -1; | |
2494 | int noperands, opi; | |
e0001a05 | 2495 | |
43cd72b9 BW |
2496 | if (opcode == XTENSA_UNDEFINED) |
2497 | return -1; | |
e0001a05 | 2498 | |
43cd72b9 BW |
2499 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2500 | for (opi = noperands - 1; opi >= 0; opi--) | |
2501 | { | |
2502 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2503 | continue; | |
2504 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2505 | return opi; | |
2506 | if (last_immed == -1 | |
2507 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2508 | last_immed = opi; | |
e0001a05 | 2509 | } |
43cd72b9 | 2510 | return last_immed; |
e0001a05 NC |
2511 | } |
2512 | ||
e0001a05 | 2513 | |
43cd72b9 | 2514 | static xtensa_opcode |
7fa3d080 | 2515 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2516 | { |
43cd72b9 BW |
2517 | static xtensa_insnbuf insnbuf = NULL; |
2518 | static xtensa_insnbuf slotbuf = NULL; | |
2519 | xtensa_isa isa = xtensa_default_isa; | |
2520 | xtensa_format fmt; | |
2521 | ||
2522 | if (!insnbuf) | |
e0001a05 | 2523 | { |
43cd72b9 BW |
2524 | insnbuf = xtensa_insnbuf_alloc (isa); |
2525 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2526 | } |
e0001a05 | 2527 | |
d77b99c9 | 2528 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2529 | fmt = xtensa_format_decode (isa, insnbuf); |
2530 | if (fmt == XTENSA_UNDEFINED) | |
2531 | return XTENSA_UNDEFINED; | |
e0001a05 | 2532 | |
43cd72b9 BW |
2533 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2534 | return XTENSA_UNDEFINED; | |
e0001a05 | 2535 | |
43cd72b9 BW |
2536 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2537 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2538 | } |
2539 | ||
2540 | ||
43cd72b9 | 2541 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2542 | |
43cd72b9 | 2543 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2544 | |
7fa3d080 BW |
2545 | static void |
2546 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2547 | { |
2548 | int num_opcodes, num_operands; | |
2549 | xtensa_opcode opcode; | |
2550 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2551 | |
43cd72b9 BW |
2552 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2553 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2554 | { |
43cd72b9 BW |
2555 | int opn; |
2556 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2557 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2558 | for (opn = 0; opn < num_operands; opn++) | |
2559 | { | |
2560 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2561 | continue; | |
2562 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2563 | { | |
2564 | xtensa_regfile opnd_rf = | |
2565 | xtensa_operand_regfile (isa, opcode, opn); | |
2566 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2567 | } | |
2568 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2569 | fputs ("[lLr] ", stderr); | |
2570 | else | |
2571 | fputs ("i ", stderr); | |
2572 | } | |
2573 | fprintf (stderr, "\n"); | |
e0001a05 | 2574 | } |
e0001a05 NC |
2575 | } |
2576 | ||
2577 | ||
43cd72b9 | 2578 | static void |
7fa3d080 | 2579 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2580 | { |
e0001a05 | 2581 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2582 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2583 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2584 | int op; | |
e0001a05 | 2585 | |
43cd72b9 | 2586 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2587 | |
43cd72b9 BW |
2588 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2589 | { | |
2590 | xtensa_opcode opcode; | |
2591 | const char *opname; | |
2592 | int operands; | |
2593 | ||
2594 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2595 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2596 | opname = xtensa_opcode_name (isa, opcode); | |
2597 | ||
2598 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2599 | fprintf (stderr, " operands = "); | |
2600 | for (operands = 0; | |
2601 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2602 | operands++) | |
2603 | { | |
2604 | unsigned int val; | |
2605 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2606 | continue; | |
2607 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2608 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2609 | fprintf (stderr, "%d ", val); | |
2610 | } | |
2611 | fprintf (stderr, "\n"); | |
2612 | } | |
2613 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2614 | } |
2615 | ||
43cd72b9 BW |
2616 | #endif /* TENSILICA_DEBUG */ |
2617 | ||
e0001a05 NC |
2618 | |
2619 | static bfd_boolean | |
7fa3d080 | 2620 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2621 | { |
43cd72b9 BW |
2622 | xtensa_isa isa = xtensa_default_isa; |
2623 | int n, num_operands; | |
e0001a05 | 2624 | |
43cd72b9 | 2625 | if (xtensa_opcode_is_call (isa, opcode) == 0) |
e0001a05 NC |
2626 | return FALSE; |
2627 | ||
43cd72b9 BW |
2628 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2629 | for (n = 0; n < num_operands; n++) | |
2630 | { | |
2631 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2632 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2633 | return TRUE; | |
2634 | } | |
2635 | return FALSE; | |
e0001a05 NC |
2636 | } |
2637 | ||
2638 | ||
43cd72b9 BW |
2639 | /* Convert from BFD relocation type code to slot and operand number. |
2640 | Returns non-zero on failure. */ | |
e0001a05 | 2641 | |
43cd72b9 | 2642 | static int |
7fa3d080 | 2643 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2644 | { |
43cd72b9 BW |
2645 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2646 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2647 | { |
43cd72b9 BW |
2648 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2649 | *is_alt = FALSE; | |
e0001a05 | 2650 | } |
43cd72b9 BW |
2651 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2652 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2653 | { |
43cd72b9 BW |
2654 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2655 | *is_alt = TRUE; | |
e0001a05 | 2656 | } |
43cd72b9 BW |
2657 | else |
2658 | return -1; | |
2659 | ||
2660 | return 0; | |
e0001a05 NC |
2661 | } |
2662 | ||
2663 | ||
43cd72b9 BW |
2664 | /* Convert from slot number to BFD relocation type code for the |
2665 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2666 | failure. */ | |
e0001a05 | 2667 | |
43cd72b9 | 2668 | static bfd_reloc_code_real_type |
7fa3d080 | 2669 | encode_reloc (int slot) |
e0001a05 | 2670 | { |
43cd72b9 BW |
2671 | if (slot < 0 || slot > 14) |
2672 | return BFD_RELOC_NONE; | |
2673 | ||
2674 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2675 | } |
2676 | ||
2677 | ||
43cd72b9 BW |
2678 | /* Convert from slot numbers to BFD relocation type code for the |
2679 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2680 | |
43cd72b9 | 2681 | static bfd_reloc_code_real_type |
7fa3d080 | 2682 | encode_alt_reloc (int slot) |
e0001a05 | 2683 | { |
43cd72b9 BW |
2684 | if (slot < 0 || slot > 14) |
2685 | return BFD_RELOC_NONE; | |
2686 | ||
2687 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2688 | } |
2689 | ||
2690 | ||
2691 | static void | |
7fa3d080 BW |
2692 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2693 | xtensa_format fmt, | |
2694 | int slot, | |
2695 | xtensa_opcode opcode, | |
2696 | int operand, | |
2697 | uint32 value, | |
2698 | const char *file, | |
2699 | unsigned int line) | |
e0001a05 | 2700 | { |
e0001a05 NC |
2701 | uint32 valbuf = value; |
2702 | ||
43cd72b9 | 2703 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2704 | { |
43cd72b9 BW |
2705 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2706 | == 1) | |
2707 | as_bad_where ((char *) file, line, | |
2708 | _("operand %u is out of range for '%s'"), value, | |
2709 | xtensa_opcode_name (xtensa_default_isa, opcode)); | |
2710 | else | |
2711 | as_bad_where ((char *) file, line, | |
2712 | _("operand %u is invalid for '%s'"), value, | |
2713 | xtensa_opcode_name (xtensa_default_isa, opcode)); | |
2714 | return; | |
e0001a05 NC |
2715 | } |
2716 | ||
43cd72b9 BW |
2717 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2718 | slotbuf, valbuf); | |
e0001a05 NC |
2719 | } |
2720 | ||
2721 | ||
2722 | static uint32 | |
7fa3d080 BW |
2723 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2724 | xtensa_format fmt, | |
2725 | int slot, | |
2726 | xtensa_opcode opcode, | |
2727 | int opnum) | |
e0001a05 | 2728 | { |
43cd72b9 BW |
2729 | uint32 val = 0; |
2730 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2731 | fmt, slot, slotbuf, &val); | |
2732 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2733 | return val; | |
e0001a05 NC |
2734 | } |
2735 | ||
e0001a05 | 2736 | \f |
7fa3d080 | 2737 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2738 | |
7fa3d080 BW |
2739 | /* The routine xg_instruction_matches_option_term must return TRUE |
2740 | when a given option term is true. The meaning of all of the option | |
2741 | terms is given interpretation by this function. This is needed when | |
2742 | an option depends on the state of a directive, but there are no such | |
2743 | options in use right now. */ | |
e0001a05 | 2744 | |
7fa3d080 BW |
2745 | static bfd_boolean |
2746 | xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED, | |
2747 | const ReqOrOption *option) | |
e0001a05 | 2748 | { |
7fa3d080 BW |
2749 | if (strcmp (option->option_name, "realnop") == 0 |
2750 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2751 | { | |
2752 | /* These conditions were evaluated statically when building the | |
2753 | relaxation table. There's no need to reevaluate them now. */ | |
2754 | return TRUE; | |
2755 | } | |
2756 | else | |
2757 | { | |
2758 | as_fatal (_("internal error: unknown option name '%s'"), | |
2759 | option->option_name); | |
2760 | } | |
e0001a05 NC |
2761 | } |
2762 | ||
2763 | ||
7fa3d080 BW |
2764 | static bfd_boolean |
2765 | xg_instruction_matches_or_options (TInsn *insn, | |
2766 | const ReqOrOptionList *or_option) | |
e0001a05 | 2767 | { |
7fa3d080 BW |
2768 | const ReqOrOption *option; |
2769 | /* Must match each of the AND terms. */ | |
2770 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2771 | { |
7fa3d080 BW |
2772 | if (xg_instruction_matches_option_term (insn, option)) |
2773 | return TRUE; | |
e0001a05 | 2774 | } |
7fa3d080 | 2775 | return FALSE; |
e0001a05 NC |
2776 | } |
2777 | ||
2778 | ||
7fa3d080 BW |
2779 | static bfd_boolean |
2780 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2781 | { |
7fa3d080 BW |
2782 | const ReqOption *req_options; |
2783 | /* Must match each of the AND terms. */ | |
2784 | for (req_options = options; | |
2785 | req_options != NULL; | |
2786 | req_options = req_options->next) | |
e0001a05 | 2787 | { |
7fa3d080 BW |
2788 | /* Must match one of the OR clauses. */ |
2789 | if (!xg_instruction_matches_or_options (insn, | |
2790 | req_options->or_option_terms)) | |
2791 | return FALSE; | |
e0001a05 | 2792 | } |
7fa3d080 | 2793 | return TRUE; |
e0001a05 NC |
2794 | } |
2795 | ||
2796 | ||
7fa3d080 | 2797 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2798 | |
7fa3d080 BW |
2799 | static bfd_boolean |
2800 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2801 | { |
7fa3d080 | 2802 | PreconditionList *condition_l; |
e0001a05 | 2803 | |
7fa3d080 BW |
2804 | if (rule->opcode != insn->opcode) |
2805 | return FALSE; | |
e0001a05 | 2806 | |
7fa3d080 BW |
2807 | for (condition_l = rule->conditions; |
2808 | condition_l != NULL; | |
2809 | condition_l = condition_l->next) | |
e0001a05 | 2810 | { |
7fa3d080 BW |
2811 | expressionS *exp1; |
2812 | expressionS *exp2; | |
2813 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2814 | |
7fa3d080 | 2815 | switch (cond->typ) |
e0001a05 | 2816 | { |
7fa3d080 BW |
2817 | case OP_CONSTANT: |
2818 | /* The expression must be the constant. */ | |
2819 | assert (cond->op_num < insn->ntok); | |
2820 | exp1 = &insn->tok[cond->op_num]; | |
2821 | if (expr_is_const (exp1)) | |
2822 | { | |
2823 | switch (cond->cmp) | |
2824 | { | |
2825 | case OP_EQUAL: | |
2826 | if (get_expr_const (exp1) != cond->op_data) | |
2827 | return FALSE; | |
2828 | break; | |
2829 | case OP_NOTEQUAL: | |
2830 | if (get_expr_const (exp1) == cond->op_data) | |
2831 | return FALSE; | |
2832 | break; | |
2833 | default: | |
2834 | return FALSE; | |
2835 | } | |
2836 | } | |
2837 | else if (expr_is_register (exp1)) | |
2838 | { | |
2839 | switch (cond->cmp) | |
2840 | { | |
2841 | case OP_EQUAL: | |
2842 | if (get_expr_register (exp1) != cond->op_data) | |
2843 | return FALSE; | |
2844 | break; | |
2845 | case OP_NOTEQUAL: | |
2846 | if (get_expr_register (exp1) == cond->op_data) | |
2847 | return FALSE; | |
2848 | break; | |
2849 | default: | |
2850 | return FALSE; | |
2851 | } | |
2852 | } | |
2853 | else | |
2854 | return FALSE; | |
2855 | break; | |
2856 | ||
2857 | case OP_OPERAND: | |
2858 | assert (cond->op_num < insn->ntok); | |
2859 | assert (cond->op_data < insn->ntok); | |
2860 | exp1 = &insn->tok[cond->op_num]; | |
2861 | exp2 = &insn->tok[cond->op_data]; | |
2862 | ||
2863 | switch (cond->cmp) | |
2864 | { | |
2865 | case OP_EQUAL: | |
2866 | if (!expr_is_equal (exp1, exp2)) | |
2867 | return FALSE; | |
2868 | break; | |
2869 | case OP_NOTEQUAL: | |
2870 | if (expr_is_equal (exp1, exp2)) | |
2871 | return FALSE; | |
2872 | break; | |
2873 | } | |
2874 | break; | |
2875 | ||
2876 | case OP_LITERAL: | |
2877 | case OP_LABEL: | |
2878 | default: | |
2879 | return FALSE; | |
2880 | } | |
2881 | } | |
2882 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2883 | return FALSE; | |
2884 | ||
2885 | return TRUE; | |
2886 | } | |
2887 | ||
2888 | ||
2889 | static int | |
2890 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2891 | { | |
2892 | bfd_boolean a_greater = FALSE; | |
2893 | bfd_boolean b_greater = FALSE; | |
2894 | ||
2895 | ReqOptionList *l_a = a->options; | |
2896 | ReqOptionList *l_b = b->options; | |
2897 | ||
2898 | /* We only care if they both are the same except for | |
2899 | a const16 vs. an l32r. */ | |
2900 | ||
2901 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2902 | { | |
2903 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2904 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2905 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2906 | { | |
2907 | if (l_or_a->is_true != l_or_b->is_true) | |
2908 | return 0; | |
2909 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2910 | { | |
2911 | /* This is the case we care about. */ | |
2912 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
2913 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
2914 | { | |
2915 | if (prefer_const16) | |
2916 | a_greater = TRUE; | |
2917 | else | |
2918 | b_greater = TRUE; | |
2919 | } | |
2920 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
2921 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
2922 | { | |
2923 | if (prefer_const16) | |
2924 | b_greater = TRUE; | |
2925 | else | |
2926 | a_greater = TRUE; | |
2927 | } | |
2928 | else | |
2929 | return 0; | |
2930 | } | |
2931 | l_or_a = l_or_a->next; | |
2932 | l_or_b = l_or_b->next; | |
2933 | } | |
2934 | if (l_or_a || l_or_b) | |
2935 | return 0; | |
2936 | ||
2937 | l_a = l_a->next; | |
2938 | l_b = l_b->next; | |
2939 | } | |
2940 | if (l_a || l_b) | |
2941 | return 0; | |
2942 | ||
2943 | /* Incomparable if the substitution was used differently in two cases. */ | |
2944 | if (a_greater && b_greater) | |
2945 | return 0; | |
2946 | ||
2947 | if (b_greater) | |
2948 | return 1; | |
2949 | if (a_greater) | |
2950 | return -1; | |
2951 | ||
2952 | return 0; | |
2953 | } | |
2954 | ||
2955 | ||
2956 | static TransitionRule * | |
2957 | xg_instruction_match (TInsn *insn) | |
2958 | { | |
2959 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
2960 | TransitionList *l; | |
2961 | assert (insn->opcode < table->num_opcodes); | |
2962 | ||
2963 | /* Walk through all of the possible transitions. */ | |
2964 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2965 | { | |
2966 | TransitionRule *rule = l->rule; | |
2967 | if (xg_instruction_matches_rule (insn, rule)) | |
2968 | return rule; | |
2969 | } | |
2970 | return NULL; | |
2971 | } | |
2972 | ||
2973 | \f | |
2974 | /* Various Other Internal Functions. */ | |
2975 | ||
2976 | static bfd_boolean | |
2977 | is_unique_insn_expansion (TransitionRule *r) | |
2978 | { | |
2979 | if (!r->to_instr || r->to_instr->next != NULL) | |
2980 | return FALSE; | |
2981 | if (r->to_instr->typ != INSTR_INSTR) | |
2982 | return FALSE; | |
2983 | return TRUE; | |
2984 | } | |
2985 | ||
2986 | ||
2987 | static int | |
2988 | xg_get_build_instr_size (BuildInstr *insn) | |
2989 | { | |
2990 | assert (insn->typ == INSTR_INSTR); | |
2991 | return xg_get_single_size (insn->opcode); | |
2992 | } | |
2993 | ||
2994 | ||
2995 | static bfd_boolean | |
2996 | xg_is_narrow_insn (TInsn *insn) | |
2997 | { | |
2998 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
2999 | TransitionList *l; | |
3000 | int num_match = 0; | |
3001 | assert (insn->insn_type == ITYPE_INSN); | |
3002 | assert (insn->opcode < table->num_opcodes); | |
3003 | ||
3004 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3005 | { | |
3006 | TransitionRule *rule = l->rule; | |
3007 | ||
3008 | if (xg_instruction_matches_rule (insn, rule) | |
3009 | && is_unique_insn_expansion (rule)) | |
3010 | { | |
3011 | /* It only generates one instruction... */ | |
3012 | assert (insn->insn_type == ITYPE_INSN); | |
3013 | /* ...and it is a larger instruction. */ | |
3014 | if (xg_get_single_size (insn->opcode) | |
3015 | < xg_get_build_instr_size (rule->to_instr)) | |
3016 | { | |
3017 | num_match++; | |
3018 | if (num_match > 1) | |
3019 | return FALSE; | |
3020 | } | |
3021 | } | |
3022 | } | |
3023 | return (num_match == 1); | |
3024 | } | |
3025 | ||
3026 | ||
3027 | static bfd_boolean | |
3028 | xg_is_single_relaxable_insn (TInsn *insn) | |
3029 | { | |
3030 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3031 | TransitionList *l; | |
3032 | int num_match = 0; | |
3033 | assert (insn->insn_type == ITYPE_INSN); | |
3034 | assert (insn->opcode < table->num_opcodes); | |
3035 | ||
3036 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3037 | { | |
3038 | TransitionRule *rule = l->rule; | |
3039 | ||
3040 | if (xg_instruction_matches_rule (insn, rule) | |
3041 | && is_unique_insn_expansion (rule)) | |
3042 | { | |
3043 | /* It only generates one instruction... */ | |
3044 | assert (insn->insn_type == ITYPE_INSN); | |
3045 | /* ... and it is a larger instruction. */ | |
3046 | if (xg_get_single_size (insn->opcode) | |
3047 | <= xg_get_build_instr_size (rule->to_instr)) | |
3048 | { | |
3049 | num_match++; | |
3050 | if (num_match > 1) | |
3051 | return FALSE; | |
3052 | } | |
3053 | } | |
3054 | } | |
3055 | return (num_match == 1); | |
3056 | } | |
3057 | ||
3058 | ||
3059 | /* Return the maximum number of bytes this opcode can expand to. */ | |
3060 | ||
3061 | static int | |
3062 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
3063 | { | |
3064 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3065 | TransitionList *l; | |
3066 | int max_size = xg_get_single_size (opcode); | |
3067 | ||
3068 | assert (opcode < table->num_opcodes); | |
3069 | ||
3070 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3071 | { | |
3072 | TransitionRule *rule = l->rule; | |
3073 | BuildInstr *build_list; | |
3074 | int this_size = 0; | |
3075 | ||
3076 | if (!rule) | |
3077 | continue; | |
3078 | build_list = rule->to_instr; | |
3079 | if (is_unique_insn_expansion (rule)) | |
3080 | { | |
3081 | assert (build_list->typ == INSTR_INSTR); | |
3082 | this_size = xg_get_max_insn_widen_size (build_list->opcode); | |
3083 | } | |
3084 | else | |
3085 | for (; build_list != NULL; build_list = build_list->next) | |
3086 | { | |
3087 | switch (build_list->typ) | |
3088 | { | |
3089 | case INSTR_INSTR: | |
3090 | this_size += xg_get_single_size (build_list->opcode); | |
3091 | break; | |
3092 | case INSTR_LITERAL_DEF: | |
3093 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3094 | default: |
3095 | break; | |
3096 | } | |
3097 | } | |
3098 | if (this_size > max_size) | |
3099 | max_size = this_size; | |
3100 | } | |
3101 | return max_size; | |
3102 | } | |
3103 | ||
3104 | ||
3105 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3106 | ||
7fa3d080 BW |
3107 | static int |
3108 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3109 | { |
43cd72b9 | 3110 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3111 | TransitionList *l; |
3112 | int max_size = 0; | |
3113 | ||
3114 | assert (opcode < table->num_opcodes); | |
3115 | ||
3116 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3117 | { | |
3118 | TransitionRule *rule = l->rule; | |
3119 | BuildInstr *build_list; | |
3120 | int this_size = 0; | |
3121 | ||
3122 | if (!rule) | |
3123 | continue; | |
3124 | build_list = rule->to_instr; | |
3125 | if (is_unique_insn_expansion (rule)) | |
3126 | { | |
3127 | assert (build_list->typ == INSTR_INSTR); | |
3128 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); | |
3129 | } | |
3130 | else | |
3131 | for (; build_list != NULL; build_list = build_list->next) | |
3132 | { | |
3133 | switch (build_list->typ) | |
3134 | { | |
3135 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3136 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3137 | this_size += 4; |
3138 | break; | |
3139 | case INSTR_INSTR: | |
3140 | case INSTR_LABEL_DEF: | |
3141 | default: | |
3142 | break; | |
3143 | } | |
3144 | } | |
3145 | if (this_size > max_size) | |
3146 | max_size = this_size; | |
3147 | } | |
3148 | return max_size; | |
3149 | } | |
3150 | ||
3151 | ||
7fa3d080 BW |
3152 | static bfd_boolean |
3153 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3154 | { | |
3155 | int steps_taken = 0; | |
3156 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3157 | TransitionList *l; | |
3158 | ||
3159 | assert (insn->insn_type == ITYPE_INSN); | |
3160 | assert (insn->opcode < table->num_opcodes); | |
3161 | ||
3162 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3163 | { | |
3164 | TransitionRule *rule = l->rule; | |
3165 | ||
3166 | if (xg_instruction_matches_rule (insn, rule)) | |
3167 | { | |
3168 | if (steps_taken == lateral_steps) | |
3169 | return TRUE; | |
3170 | steps_taken++; | |
3171 | } | |
3172 | } | |
3173 | return FALSE; | |
3174 | } | |
3175 | ||
3176 | ||
3177 | static symbolS * | |
3178 | get_special_literal_symbol (void) | |
3179 | { | |
3180 | static symbolS *sym = NULL; | |
3181 | ||
3182 | if (sym == NULL) | |
3183 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3184 | return sym; | |
3185 | } | |
3186 | ||
3187 | ||
3188 | static symbolS * | |
3189 | get_special_label_symbol (void) | |
3190 | { | |
3191 | static symbolS *sym = NULL; | |
3192 | ||
3193 | if (sym == NULL) | |
3194 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3195 | return sym; | |
3196 | } | |
3197 | ||
3198 | ||
3199 | static bfd_boolean | |
3200 | xg_valid_literal_expression (const expressionS *exp) | |
3201 | { | |
3202 | switch (exp->X_op) | |
3203 | { | |
3204 | case O_constant: | |
3205 | case O_symbol: | |
3206 | case O_big: | |
3207 | case O_uminus: | |
3208 | case O_subtract: | |
3209 | case O_pltrel: | |
3210 | return TRUE; | |
3211 | default: | |
3212 | return FALSE; | |
3213 | } | |
3214 | } | |
3215 | ||
3216 | ||
3217 | /* This will check to see if the value can be converted into the | |
3218 | operand type. It will return TRUE if it does not fit. */ | |
3219 | ||
3220 | static bfd_boolean | |
3221 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3222 | { | |
3223 | uint32 valbuf = value; | |
3224 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3225 | return TRUE; | |
3226 | return FALSE; | |
3227 | } | |
3228 | ||
3229 | ||
3230 | /* Assumes: All immeds are constants. Check that all constants fit | |
3231 | into their immeds; return FALSE if not. */ | |
3232 | ||
3233 | static bfd_boolean | |
3234 | xg_immeds_fit (const TInsn *insn) | |
3235 | { | |
3236 | xtensa_isa isa = xtensa_default_isa; | |
3237 | int i; | |
3238 | ||
3239 | int n = insn->ntok; | |
3240 | assert (insn->insn_type == ITYPE_INSN); | |
3241 | for (i = 0; i < n; ++i) | |
3242 | { | |
3243 | const expressionS *expr = &insn->tok[i]; | |
3244 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3245 | continue; | |
3246 | ||
3247 | switch (expr->X_op) | |
3248 | { | |
3249 | case O_register: | |
3250 | case O_constant: | |
3251 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3252 | return FALSE; | |
3253 | break; | |
3254 | ||
3255 | default: | |
3256 | /* The symbol should have a fixup associated with it. */ | |
3257 | assert (FALSE); | |
3258 | break; | |
3259 | } | |
3260 | } | |
3261 | return TRUE; | |
3262 | } | |
3263 | ||
3264 | ||
3265 | /* This should only be called after we have an initial | |
3266 | estimate of the addresses. */ | |
3267 | ||
3268 | static bfd_boolean | |
3269 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3270 | segT pc_seg, | |
3271 | fragS *pc_frag, | |
3272 | offsetT pc_offset, | |
3273 | long stretch) | |
e0001a05 | 3274 | { |
7fa3d080 BW |
3275 | xtensa_isa isa = xtensa_default_isa; |
3276 | symbolS *symbolP; | |
3277 | fragS *sym_frag; | |
3278 | offsetT target, pc; | |
3279 | uint32 new_offset; | |
3280 | int i; | |
3281 | int n = insn->ntok; | |
e0001a05 NC |
3282 | |
3283 | assert (insn->insn_type == ITYPE_INSN); | |
e0001a05 | 3284 | |
7fa3d080 | 3285 | for (i = 0; i < n; ++i) |
e0001a05 | 3286 | { |
7fa3d080 BW |
3287 | const expressionS *expr = &insn->tok[i]; |
3288 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3289 | continue; | |
e0001a05 | 3290 | |
7fa3d080 | 3291 | switch (expr->X_op) |
e0001a05 | 3292 | { |
7fa3d080 BW |
3293 | case O_register: |
3294 | case O_constant: | |
3295 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3296 | return FALSE; | |
3297 | break; | |
e0001a05 | 3298 | |
7fa3d080 BW |
3299 | case O_lo16: |
3300 | case O_hi16: | |
3301 | /* Check for the worst case. */ | |
3302 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3303 | return FALSE; | |
3304 | break; | |
e0001a05 | 3305 | |
7fa3d080 | 3306 | case O_symbol: |
7c834684 | 3307 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3308 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3309 | if (pc_frag == 0 |
3310 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3311 | return FALSE; |
e0001a05 | 3312 | |
7c834684 BW |
3313 | /* If it is a weak symbol, then assume it won't reach. */ |
3314 | if (S_IS_WEAK (expr->X_add_symbol)) | |
7fa3d080 | 3315 | return FALSE; |
e0001a05 | 3316 | |
7c834684 BW |
3317 | if (is_direct_call_opcode (insn->opcode) |
3318 | && ! pc_frag->tc_frag_data.use_longcalls) | |
3319 | { | |
3320 | /* If callee is undefined or in a different segment, be | |
3321 | optimistic and assume it will be in range. */ | |
3322 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
3323 | return TRUE; | |
3324 | } | |
3325 | ||
3326 | /* Only references within a segment can be known to fit in the | |
3327 | operands at assembly time. */ | |
3328 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
7fa3d080 | 3329 | return FALSE; |
e0001a05 | 3330 | |
7fa3d080 BW |
3331 | symbolP = expr->X_add_symbol; |
3332 | sym_frag = symbol_get_frag (symbolP); | |
3333 | target = S_GET_VALUE (symbolP) + expr->X_add_number; | |
3334 | pc = pc_frag->fr_address + pc_offset; | |
e0001a05 | 3335 | |
7fa3d080 BW |
3336 | /* If frag has yet to be reached on this pass, assume it |
3337 | will move by STRETCH just as we did. If this is not so, | |
3338 | it will be because some frag between grows, and that will | |
3339 | force another pass. Beware zero-length frags. There | |
3340 | should be a faster way to do this. */ | |
3341 | ||
3342 | if (stretch != 0 | |
3343 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3344 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3345 | { | |
3346 | target += stretch; | |
3347 | } | |
3348 | ||
3349 | new_offset = target; | |
3350 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3351 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3352 | return FALSE; | |
3353 | break; | |
3354 | ||
3355 | default: | |
3356 | /* The symbol should have a fixup associated with it. */ | |
3357 | return FALSE; | |
3358 | } | |
3359 | } | |
3360 | ||
3361 | return TRUE; | |
e0001a05 NC |
3362 | } |
3363 | ||
3364 | ||
43cd72b9 | 3365 | /* Return TRUE on success. */ |
e0001a05 | 3366 | |
7fa3d080 BW |
3367 | static bfd_boolean |
3368 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3369 | { |
3370 | BuildOp *op; | |
3371 | symbolS *sym; | |
3372 | ||
3373 | memset (targ, 0, sizeof (TInsn)); | |
43cd72b9 | 3374 | targ->loc = insn->loc; |
e0001a05 NC |
3375 | switch (bi->typ) |
3376 | { | |
3377 | case INSTR_INSTR: | |
3378 | op = bi->ops; | |
3379 | targ->opcode = bi->opcode; | |
3380 | targ->insn_type = ITYPE_INSN; | |
3381 | targ->is_specific_opcode = FALSE; | |
3382 | ||
3383 | for (; op != NULL; op = op->next) | |
3384 | { | |
3385 | int op_num = op->op_num; | |
3386 | int op_data = op->op_data; | |
3387 | ||
3388 | assert (op->op_num < MAX_INSN_ARGS); | |
3389 | ||
3390 | if (targ->ntok <= op_num) | |
3391 | targ->ntok = op_num + 1; | |
3392 | ||
3393 | switch (op->typ) | |
3394 | { | |
3395 | case OP_CONSTANT: | |
3396 | set_expr_const (&targ->tok[op_num], op_data); | |
3397 | break; | |
3398 | case OP_OPERAND: | |
3399 | assert (op_data < insn->ntok); | |
3400 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3401 | break; | |
3402 | case OP_LITERAL: | |
3403 | sym = get_special_literal_symbol (); | |
3404 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3405 | break; | |
3406 | case OP_LABEL: | |
3407 | sym = get_special_label_symbol (); | |
3408 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3409 | break; | |
43cd72b9 BW |
3410 | case OP_OPERAND_HI16U: |
3411 | case OP_OPERAND_LOW16U: | |
3412 | assert (op_data < insn->ntok); | |
3413 | if (expr_is_const (&insn->tok[op_data])) | |
3414 | { | |
3415 | long val; | |
3416 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3417 | val = xg_apply_userdef_op_fn (op->typ, | |
3418 | targ->tok[op_num]. | |
3419 | X_add_number); | |
3420 | targ->tok[op_num].X_add_number = val; | |
3421 | } | |
3422 | else | |
3423 | { | |
3424 | /* For const16 we can create relocations for these. */ | |
3425 | if (targ->opcode == XTENSA_UNDEFINED | |
3426 | || (targ->opcode != xtensa_const16_opcode)) | |
3427 | return FALSE; | |
3428 | assert (op_data < insn->ntok); | |
3429 | /* Need to build a O_lo16 or O_hi16. */ | |
3430 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3431 | if (targ->tok[op_num].X_op == O_symbol) | |
3432 | { | |
3433 | if (op->typ == OP_OPERAND_HI16U) | |
3434 | targ->tok[op_num].X_op = O_hi16; | |
3435 | else if (op->typ == OP_OPERAND_LOW16U) | |
3436 | targ->tok[op_num].X_op = O_lo16; | |
3437 | else | |
3438 | return FALSE; | |
3439 | } | |
3440 | } | |
3441 | break; | |
e0001a05 NC |
3442 | default: |
3443 | /* currently handles: | |
3444 | OP_OPERAND_LOW8 | |
3445 | OP_OPERAND_HI24S | |
3446 | OP_OPERAND_F32MINUS */ | |
3447 | if (xg_has_userdef_op_fn (op->typ)) | |
3448 | { | |
3449 | assert (op_data < insn->ntok); | |
3450 | if (expr_is_const (&insn->tok[op_data])) | |
3451 | { | |
3452 | long val; | |
3453 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3454 | val = xg_apply_userdef_op_fn (op->typ, | |
3455 | targ->tok[op_num]. | |
3456 | X_add_number); | |
3457 | targ->tok[op_num].X_add_number = val; | |
3458 | } | |
3459 | else | |
3460 | return FALSE; /* We cannot use a relocation for this. */ | |
3461 | break; | |
3462 | } | |
3463 | assert (0); | |
3464 | break; | |
3465 | } | |
3466 | } | |
3467 | break; | |
3468 | ||
3469 | case INSTR_LITERAL_DEF: | |
3470 | op = bi->ops; | |
3471 | targ->opcode = XTENSA_UNDEFINED; | |
3472 | targ->insn_type = ITYPE_LITERAL; | |
3473 | targ->is_specific_opcode = FALSE; | |
3474 | for (; op != NULL; op = op->next) | |
3475 | { | |
3476 | int op_num = op->op_num; | |
3477 | int op_data = op->op_data; | |
3478 | assert (op->op_num < MAX_INSN_ARGS); | |
3479 | ||
3480 | if (targ->ntok <= op_num) | |
3481 | targ->ntok = op_num + 1; | |
3482 | ||
3483 | switch (op->typ) | |
3484 | { | |
3485 | case OP_OPERAND: | |
3486 | assert (op_data < insn->ntok); | |
43cd72b9 BW |
3487 | /* We can only pass resolvable literals through. */ |
3488 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3489 | return FALSE; | |
e0001a05 NC |
3490 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3491 | break; | |
3492 | case OP_LITERAL: | |
3493 | case OP_CONSTANT: | |
3494 | case OP_LABEL: | |
3495 | default: | |
3496 | assert (0); | |
3497 | break; | |
3498 | } | |
3499 | } | |
3500 | break; | |
3501 | ||
3502 | case INSTR_LABEL_DEF: | |
3503 | op = bi->ops; | |
3504 | targ->opcode = XTENSA_UNDEFINED; | |
3505 | targ->insn_type = ITYPE_LABEL; | |
3506 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3507 | /* Literal with no ops is a label? */ |
e0001a05 NC |
3508 | assert (op == NULL); |
3509 | break; | |
3510 | ||
3511 | default: | |
3512 | assert (0); | |
3513 | } | |
3514 | ||
3515 | return TRUE; | |
3516 | } | |
3517 | ||
3518 | ||
43cd72b9 | 3519 | /* Return TRUE on success. */ |
e0001a05 | 3520 | |
7fa3d080 BW |
3521 | static bfd_boolean |
3522 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3523 | { |
3524 | for (; bi != NULL; bi = bi->next) | |
3525 | { | |
3526 | TInsn *next_insn = istack_push_space (istack); | |
3527 | ||
3528 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3529 | return FALSE; | |
3530 | } | |
3531 | return TRUE; | |
3532 | } | |
3533 | ||
3534 | ||
43cd72b9 | 3535 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3536 | |
7fa3d080 BW |
3537 | static bfd_boolean |
3538 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3539 | { |
3540 | int stack_size = istack->ninsn; | |
3541 | int steps_taken = 0; | |
43cd72b9 | 3542 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3543 | TransitionList *l; |
3544 | ||
3545 | assert (insn->insn_type == ITYPE_INSN); | |
3546 | assert (insn->opcode < table->num_opcodes); | |
3547 | ||
3548 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3549 | { | |
3550 | TransitionRule *rule = l->rule; | |
3551 | ||
3552 | if (xg_instruction_matches_rule (insn, rule)) | |
3553 | { | |
3554 | if (lateral_steps == steps_taken) | |
3555 | { | |
3556 | int i; | |
3557 | ||
3558 | /* This is it. Expand the rule to the stack. */ | |
3559 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3560 | return FALSE; | |
3561 | ||
3562 | /* Check to see if it fits. */ | |
3563 | for (i = stack_size; i < istack->ninsn; i++) | |
3564 | { | |
3565 | TInsn *insn = &istack->insn[i]; | |
3566 | ||
3567 | if (insn->insn_type == ITYPE_INSN | |
3568 | && !tinsn_has_symbolic_operands (insn) | |
3569 | && !xg_immeds_fit (insn)) | |
3570 | { | |
3571 | istack->ninsn = stack_size; | |
3572 | return FALSE; | |
3573 | } | |
3574 | } | |
3575 | return TRUE; | |
3576 | } | |
3577 | steps_taken++; | |
3578 | } | |
3579 | } | |
3580 | return FALSE; | |
3581 | } | |
3582 | ||
3583 | ||
7fa3d080 BW |
3584 | static bfd_boolean |
3585 | xg_expand_narrow (TInsn *targ, TInsn *insn) | |
e0001a05 | 3586 | { |
43cd72b9 | 3587 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3588 | TransitionList *l; |
3589 | ||
3590 | assert (insn->insn_type == ITYPE_INSN); | |
3591 | assert (insn->opcode < table->num_opcodes); | |
3592 | ||
3593 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3594 | { | |
3595 | TransitionRule *rule = l->rule; | |
3596 | if (xg_instruction_matches_rule (insn, rule) | |
3597 | && is_unique_insn_expansion (rule)) | |
3598 | { | |
3599 | /* Is it a larger instruction? */ | |
43cd72b9 | 3600 | if (xg_get_single_size (insn->opcode) |
e0001a05 NC |
3601 | <= xg_get_build_instr_size (rule->to_instr)) |
3602 | { | |
3603 | xg_build_to_insn (targ, insn, rule->to_instr); | |
3604 | return FALSE; | |
3605 | } | |
3606 | } | |
3607 | } | |
3608 | return TRUE; | |
3609 | } | |
3610 | ||
43cd72b9 | 3611 | \f |
43cd72b9 BW |
3612 | /* Relax the assembly instruction at least "min_steps". |
3613 | Return the number of steps taken. */ | |
e0001a05 | 3614 | |
7fa3d080 BW |
3615 | static int |
3616 | xg_assembly_relax (IStack *istack, | |
3617 | TInsn *insn, | |
3618 | segT pc_seg, | |
3619 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3620 | offsetT pc_offset, /* offset in fragment */ | |
3621 | int min_steps, /* minimum conversion steps */ | |
3622 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3623 | { |
3624 | int steps_taken = 0; | |
3625 | ||
3626 | /* assert (has no symbolic operands) | |
3627 | Some of its immeds don't fit. | |
3628 | Try to build a relaxed version. | |
3629 | This may go through a couple of stages | |
3630 | of single instruction transformations before | |
3631 | we get there. */ | |
3632 | ||
3633 | TInsn single_target; | |
3634 | TInsn current_insn; | |
3635 | int lateral_steps = 0; | |
3636 | int istack_size = istack->ninsn; | |
3637 | ||
3638 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3639 | && steps_taken >= min_steps) | |
3640 | { | |
3641 | istack_push (istack, insn); | |
3642 | return steps_taken; | |
3643 | } | |
43cd72b9 | 3644 | current_insn = *insn; |
e0001a05 | 3645 | |
7c834684 | 3646 | /* Walk through all of the single instruction expansions. */ |
e0001a05 NC |
3647 | while (xg_is_single_relaxable_insn (¤t_insn)) |
3648 | { | |
3649 | int error_val = xg_expand_narrow (&single_target, ¤t_insn); | |
3650 | ||
3651 | assert (!error_val); | |
3652 | ||
3653 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, | |
3654 | stretch)) | |
3655 | { | |
3656 | steps_taken++; | |
3657 | if (steps_taken >= min_steps) | |
3658 | { | |
3659 | istack_push (istack, &single_target); | |
3660 | return steps_taken; | |
3661 | } | |
3662 | } | |
43cd72b9 | 3663 | current_insn = single_target; |
e0001a05 NC |
3664 | } |
3665 | ||
3666 | /* Now check for a multi-instruction expansion. */ | |
3667 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3668 | { | |
3669 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3670 | stretch)) | |
3671 | { | |
3672 | if (steps_taken >= min_steps) | |
3673 | { | |
3674 | istack_push (istack, ¤t_insn); | |
3675 | return steps_taken; | |
3676 | } | |
3677 | } | |
3678 | steps_taken++; | |
3679 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3680 | { | |
3681 | if (steps_taken >= min_steps) | |
3682 | return steps_taken; | |
3683 | } | |
3684 | lateral_steps++; | |
3685 | istack->ninsn = istack_size; | |
3686 | } | |
3687 | ||
3688 | /* It's not going to work -- use the original. */ | |
3689 | istack_push (istack, insn); | |
3690 | return steps_taken; | |
3691 | } | |
3692 | ||
3693 | ||
3694 | static void | |
7fa3d080 | 3695 | xg_force_frag_space (int size) |
e0001a05 NC |
3696 | { |
3697 | /* This may have the side effect of creating a new fragment for the | |
3698 | space to go into. I just do not like the name of the "frag" | |
3699 | functions. */ | |
3700 | frag_grow (size); | |
3701 | } | |
3702 | ||
3703 | ||
7fa3d080 BW |
3704 | static void |
3705 | xg_finish_frag (char *last_insn, | |
3706 | enum xtensa_relax_statesE frag_state, | |
3707 | enum xtensa_relax_statesE slot0_state, | |
3708 | int max_growth, | |
3709 | bfd_boolean is_insn) | |
e0001a05 NC |
3710 | { |
3711 | /* Finish off this fragment so that it has at LEAST the desired | |
3712 | max_growth. If it doesn't fit in this fragment, close this one | |
3713 | and start a new one. In either case, return a pointer to the | |
3714 | beginning of the growth area. */ | |
3715 | ||
3716 | fragS *old_frag; | |
43cd72b9 | 3717 | |
e0001a05 NC |
3718 | xg_force_frag_space (max_growth); |
3719 | ||
3720 | old_frag = frag_now; | |
3721 | ||
3722 | frag_now->fr_opcode = last_insn; | |
3723 | if (is_insn) | |
3724 | frag_now->tc_frag_data.is_insn = TRUE; | |
3725 | ||
3726 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3727 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3728 | ||
3729 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3730 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3731 | |
3732 | /* Just to make sure that we did not split it up. */ | |
3733 | assert (old_frag->fr_next == frag_now); | |
3734 | } | |
3735 | ||
3736 | ||
7fa3d080 BW |
3737 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3738 | ||
3739 | static bfd_boolean | |
3740 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3741 | { | |
3742 | if (fragP == NULL) | |
3743 | return FALSE; | |
3744 | ||
3745 | for (; fragP; fragP = fragP->fr_next) | |
3746 | { | |
3747 | if (fragP == target) | |
3748 | return TRUE; | |
3749 | if (fragP->fr_fix != 0) | |
3750 | return FALSE; | |
3751 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3752 | return FALSE; | |
3753 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3754 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3755 | return FALSE; | |
3756 | if (fragP->fr_type == rs_space) | |
3757 | return FALSE; | |
3758 | } | |
3759 | return FALSE; | |
3760 | } | |
3761 | ||
3762 | ||
e0001a05 | 3763 | static bfd_boolean |
7fa3d080 | 3764 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3765 | { |
3766 | xtensa_isa isa = xtensa_default_isa; | |
3767 | int i; | |
43cd72b9 | 3768 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3769 | int target_op = -1; |
3770 | symbolS *sym; | |
3771 | fragS *target_frag; | |
3772 | ||
43cd72b9 BW |
3773 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 0 |
3774 | && xtensa_opcode_is_jump (isa, insn->opcode) == 0) | |
e0001a05 NC |
3775 | return FALSE; |
3776 | ||
3777 | for (i = 0; i < num_ops; i++) | |
3778 | { | |
43cd72b9 | 3779 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3780 | { |
3781 | target_op = i; | |
3782 | break; | |
3783 | } | |
3784 | } | |
3785 | if (target_op == -1) | |
3786 | return FALSE; | |
3787 | ||
3788 | if (insn->ntok <= target_op) | |
3789 | return FALSE; | |
3790 | ||
3791 | if (insn->tok[target_op].X_op != O_symbol) | |
3792 | return FALSE; | |
3793 | ||
3794 | sym = insn->tok[target_op].X_add_symbol; | |
3795 | if (sym == NULL) | |
3796 | return FALSE; | |
3797 | ||
3798 | if (insn->tok[target_op].X_add_number != 0) | |
3799 | return FALSE; | |
3800 | ||
3801 | target_frag = symbol_get_frag (sym); | |
3802 | if (target_frag == NULL) | |
3803 | return FALSE; | |
3804 | ||
3805 | if (is_next_frag_target (fragP->fr_next, target_frag) | |
3806 | && S_GET_VALUE (sym) == target_frag->fr_address) | |
3807 | return TRUE; | |
3808 | ||
3809 | return FALSE; | |
3810 | } | |
3811 | ||
3812 | ||
3813 | static void | |
7fa3d080 | 3814 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3815 | { |
3816 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3817 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3818 | |
7fa3d080 BW |
3819 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3820 | { | |
3821 | int i = 1; | |
3822 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3823 | && insn->tok[i].X_op == O_symbol) | |
3824 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3825 | return; | |
3826 | } | |
e0001a05 | 3827 | |
7fa3d080 BW |
3828 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3829 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3830 | { |
7fa3d080 BW |
3831 | int i; |
3832 | ||
3833 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3834 | { | |
3835 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3836 | && insn->tok[i].X_op == O_symbol) | |
3837 | { | |
3838 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3839 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3840 | if (S_IS_DEFINED (sym)) | |
3841 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3842 | } | |
3843 | } | |
e0001a05 | 3844 | } |
e0001a05 NC |
3845 | } |
3846 | ||
3847 | ||
43cd72b9 | 3848 | /* Return FALSE if no error. */ |
e0001a05 | 3849 | |
7fa3d080 BW |
3850 | static bfd_boolean |
3851 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3852 | { |
3853 | int num_ops = 0; | |
3854 | BuildOp *b_op; | |
3855 | ||
3856 | switch (instr_spec->typ) | |
3857 | { | |
3858 | case INSTR_INSTR: | |
3859 | new_insn->insn_type = ITYPE_INSN; | |
3860 | new_insn->opcode = instr_spec->opcode; | |
3861 | new_insn->is_specific_opcode = FALSE; | |
43cd72b9 | 3862 | new_insn->loc = old_insn->loc; |
e0001a05 NC |
3863 | break; |
3864 | case INSTR_LITERAL_DEF: | |
3865 | new_insn->insn_type = ITYPE_LITERAL; | |
3866 | new_insn->opcode = XTENSA_UNDEFINED; | |
3867 | new_insn->is_specific_opcode = FALSE; | |
43cd72b9 | 3868 | new_insn->loc = old_insn->loc; |
e0001a05 NC |
3869 | break; |
3870 | case INSTR_LABEL_DEF: | |
3871 | as_bad (_("INSTR_LABEL_DEF not supported yet")); | |
3872 | break; | |
3873 | } | |
3874 | ||
3875 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3876 | { | |
3877 | expressionS *exp; | |
3878 | const expressionS *src_exp; | |
3879 | ||
3880 | num_ops++; | |
3881 | switch (b_op->typ) | |
3882 | { | |
3883 | case OP_CONSTANT: | |
3884 | /* The expression must be the constant. */ | |
3885 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3886 | exp = &new_insn->tok[b_op->op_num]; | |
3887 | set_expr_const (exp, b_op->op_data); | |
3888 | break; | |
3889 | ||
3890 | case OP_OPERAND: | |
3891 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3892 | assert (b_op->op_data < (unsigned) old_insn->ntok); | |
3893 | src_exp = &old_insn->tok[b_op->op_data]; | |
3894 | exp = &new_insn->tok[b_op->op_num]; | |
3895 | copy_expr (exp, src_exp); | |
3896 | break; | |
3897 | ||
3898 | case OP_LITERAL: | |
3899 | case OP_LABEL: | |
3900 | as_bad (_("can't handle generation of literal/labels yet")); | |
3901 | assert (0); | |
3902 | ||
3903 | default: | |
3904 | as_bad (_("can't handle undefined OP TYPE")); | |
3905 | assert (0); | |
3906 | } | |
3907 | } | |
3908 | ||
3909 | new_insn->ntok = num_ops; | |
3910 | return FALSE; | |
3911 | } | |
3912 | ||
3913 | ||
43cd72b9 | 3914 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3915 | |
7fa3d080 BW |
3916 | static bfd_boolean |
3917 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3918 | { |
43cd72b9 | 3919 | TransitionRule *rule; |
e0001a05 | 3920 | BuildInstr *insn_spec; |
43cd72b9 BW |
3921 | |
3922 | if (old_insn->is_specific_opcode || !density_supported) | |
3923 | return FALSE; | |
3924 | ||
3925 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3926 | if (rule == NULL) |
3927 | return FALSE; | |
3928 | ||
3929 | insn_spec = rule->to_instr; | |
3930 | /* There should only be one. */ | |
3931 | assert (insn_spec != NULL); | |
3932 | assert (insn_spec->next == NULL); | |
3933 | if (insn_spec->next != NULL) | |
3934 | return FALSE; | |
3935 | ||
3936 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3937 | ||
3938 | return TRUE; | |
3939 | } | |
3940 | ||
3941 | ||
3942 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3943 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
3944 | tokens into the stack or relax it and place multiple |
3945 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
3946 | |
3947 | static bfd_boolean | |
7fa3d080 | 3948 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
3949 | { |
3950 | int noperands; | |
3951 | TInsn new_insn; | |
7c834684 BW |
3952 | bfd_boolean do_expand; |
3953 | ||
e0001a05 NC |
3954 | memset (&new_insn, 0, sizeof (TInsn)); |
3955 | ||
43cd72b9 BW |
3956 | /* Narrow it if we can. xg_simplify_insn now does all the |
3957 | appropriate checking (e.g., for the density option). */ | |
3958 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
3959 | orig_insn = &new_insn; | |
e0001a05 | 3960 | |
43cd72b9 BW |
3961 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
3962 | orig_insn->opcode); | |
e0001a05 NC |
3963 | if (orig_insn->ntok < noperands) |
3964 | { | |
3965 | as_bad (_("found %d operands for '%s': Expected %d"), | |
3966 | orig_insn->ntok, | |
3967 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3968 | noperands); | |
3969 | return TRUE; | |
3970 | } | |
3971 | if (orig_insn->ntok > noperands) | |
3972 | as_warn (_("found too many (%d) operands for '%s': Expected %d"), | |
3973 | orig_insn->ntok, | |
3974 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3975 | noperands); | |
3976 | ||
43cd72b9 | 3977 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 3978 | are too many, just cut out the extras here. */ |
e0001a05 NC |
3979 | orig_insn->ntok = noperands; |
3980 | ||
e0001a05 NC |
3981 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
3982 | return TRUE; | |
3983 | ||
7c834684 BW |
3984 | /* If the instruction will definitely need to be relaxed, it is better |
3985 | to expand it now for better scheduling. Decide whether to expand | |
3986 | now.... */ | |
3987 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
3988 | ||
3989 | /* Calls should be expanded to longcalls only in the backend relaxation | |
3990 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
3991 | adjacent. */ | |
3992 | if (is_direct_call_opcode (orig_insn->opcode)) | |
3993 | do_expand = FALSE; | |
e0001a05 NC |
3994 | |
3995 | if (tinsn_has_symbolic_operands (orig_insn)) | |
3996 | { | |
7c834684 BW |
3997 | /* The values of symbolic operands are not known yet, so only expand |
3998 | now if an operand is "complex" (e.g., difference of symbols) and | |
3999 | will have to be stored as a literal regardless of the value. */ | |
4000 | if (!tinsn_has_complex_operands (orig_insn)) | |
4001 | do_expand = FALSE; | |
e0001a05 | 4002 | } |
7c834684 BW |
4003 | else if (xg_immeds_fit (orig_insn)) |
4004 | do_expand = FALSE; | |
4005 | ||
4006 | if (do_expand) | |
4007 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 4008 | else |
7c834684 | 4009 | istack_push (istack, orig_insn); |
e0001a05 | 4010 | |
e0001a05 NC |
4011 | return FALSE; |
4012 | } | |
4013 | ||
4014 | ||
7fa3d080 BW |
4015 | /* Return TRUE if the section flags are marked linkonce |
4016 | or the name is .gnu.linkonce*. */ | |
4017 | ||
4018 | static bfd_boolean | |
4019 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
4020 | { | |
4021 | flagword flags, link_once_flags; | |
4022 | ||
4023 | flags = bfd_get_section_flags (abfd, sec); | |
4024 | link_once_flags = (flags & SEC_LINK_ONCE); | |
4025 | ||
4026 | /* Flags might not be set yet. */ | |
4027 | if (!link_once_flags) | |
4028 | { | |
4029 | static size_t len = sizeof ".gnu.linkonce.t."; | |
4030 | ||
4031 | if (strncmp (segment_name (sec), ".gnu.linkonce.t.", len - 1) == 0) | |
4032 | link_once_flags = SEC_LINK_ONCE; | |
4033 | } | |
4034 | return (link_once_flags != 0); | |
4035 | } | |
4036 | ||
4037 | ||
4038 | static void | |
4039 | xtensa_add_literal_sym (symbolS *sym) | |
4040 | { | |
4041 | sym_list *l; | |
4042 | ||
4043 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
4044 | l->sym = sym; | |
4045 | l->next = literal_syms; | |
4046 | literal_syms = l; | |
4047 | } | |
4048 | ||
4049 | ||
4050 | static symbolS * | |
4051 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
4052 | { | |
4053 | static int lit_num = 0; | |
4054 | static char name[256]; | |
4055 | symbolS *symbolP; | |
4056 | ||
4057 | sprintf (name, ".L_lit_sym%d", lit_num); | |
4058 | ||
4059 | /* Create a local symbol. If it is in a linkonce section, we have to | |
4060 | be careful to make sure that if it is used in a relocation that the | |
4061 | symbol will be in the output file. */ | |
4062 | if (get_is_linkonce_section (stdoutput, sec)) | |
4063 | { | |
4064 | symbolP = symbol_new (name, sec, 0, frag); | |
4065 | S_CLEAR_EXTERNAL (symbolP); | |
4066 | /* symbolP->local = 1; */ | |
4067 | } | |
4068 | else | |
4069 | symbolP = symbol_new (name, sec, 0, frag); | |
4070 | ||
4071 | xtensa_add_literal_sym (symbolP); | |
4072 | ||
4073 | frag->tc_frag_data.is_literal = TRUE; | |
4074 | lit_num++; | |
4075 | return symbolP; | |
4076 | } | |
4077 | ||
4078 | ||
e0001a05 NC |
4079 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
4080 | ||
7fa3d080 BW |
4081 | static symbolS * |
4082 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
4083 | { |
4084 | emit_state state; | |
4085 | symbolS *lit_sym = NULL; | |
4086 | ||
4087 | /* size = 4 for L32R. It could easily be larger when we move to | |
4088 | larger constants. Add a parameter later. */ | |
4089 | offsetT litsize = 4; | |
4090 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4091 | expressionS saved_loc; | |
43cd72b9 BW |
4092 | expressionS * emit_val; |
4093 | ||
e0001a05 NC |
4094 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4095 | ||
4096 | assert (insn->insn_type == ITYPE_LITERAL); | |
77cd6497 | 4097 | assert (insn->ntok == 1); /* must be only one token here */ |
e0001a05 NC |
4098 | |
4099 | xtensa_switch_to_literal_fragment (&state); | |
4100 | ||
43cd72b9 BW |
4101 | emit_val = &insn->tok[0]; |
4102 | if (emit_val->X_op == O_big) | |
4103 | { | |
4104 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4105 | if (size > litsize) | |
4106 | { | |
4107 | /* This happens when someone writes a "movi a2, big_number". */ | |
4108 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
4109 | _("invalid immediate")); | |
4110 | xtensa_restore_emit_state (&state); | |
4111 | return NULL; | |
4112 | } | |
4113 | } | |
4114 | ||
e0001a05 NC |
4115 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4116 | literals done with this function have a frag to themselves. That's | |
4117 | important for the way text section literals work. */ | |
4118 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4119 | record_alignment (now_seg, litalign); |
e0001a05 | 4120 | |
43cd72b9 BW |
4121 | if (emit_val->X_op == O_pltrel) |
4122 | { | |
4123 | char *p = frag_more (litsize); | |
4124 | xtensa_set_frag_assembly_state (frag_now); | |
4125 | if (emit_val->X_add_symbol) | |
4126 | emit_val->X_op = O_symbol; | |
4127 | else | |
4128 | emit_val->X_op = O_constant; | |
4129 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
4130 | litsize, emit_val, 0, BFD_RELOC_XTENSA_PLT); | |
4131 | } | |
4132 | else | |
4133 | emit_expr (emit_val, litsize); | |
e0001a05 NC |
4134 | |
4135 | assert (frag_now->tc_frag_data.literal_frag == NULL); | |
4136 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
4137 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4138 | lit_sym = frag_now->fr_symbol; | |
4139 | frag_now->tc_frag_data.is_literal = TRUE; | |
4140 | ||
4141 | /* Go back. */ | |
4142 | xtensa_restore_emit_state (&state); | |
4143 | return lit_sym; | |
4144 | } | |
4145 | ||
4146 | ||
4147 | static void | |
7fa3d080 | 4148 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4149 | { |
4150 | emit_state state; | |
43cd72b9 | 4151 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4152 | takes effect if something is placed here. */ |
4153 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4154 | fragS *lit_saved_frag; | |
4155 | ||
e0001a05 | 4156 | assert (size % 4 == 0); |
e0001a05 NC |
4157 | |
4158 | xtensa_switch_to_literal_fragment (&state); | |
4159 | ||
4160 | /* Force a 4-byte align here. */ | |
4161 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4162 | record_alignment (now_seg, litalign); |
e0001a05 NC |
4163 | |
4164 | xg_force_frag_space (size); | |
4165 | ||
4166 | lit_saved_frag = frag_now; | |
4167 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
4168 | frag_now->tc_frag_data.is_literal = TRUE; | |
4169 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
43cd72b9 | 4170 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4171 | |
4172 | /* Go back. */ | |
4173 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4174 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4175 | } |
4176 | ||
4177 | ||
e0001a05 | 4178 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4179 | Return TRUE on success. */ |
e0001a05 | 4180 | |
7fa3d080 BW |
4181 | static bfd_boolean |
4182 | xg_add_opcode_fix (TInsn *tinsn, | |
4183 | int opnum, | |
4184 | xtensa_format fmt, | |
4185 | int slot, | |
4186 | expressionS *expr, | |
4187 | fragS *fragP, | |
4188 | offsetT offset) | |
43cd72b9 BW |
4189 | { |
4190 | xtensa_opcode opcode = tinsn->opcode; | |
4191 | bfd_reloc_code_real_type reloc; | |
4192 | reloc_howto_type *howto; | |
4193 | int fmt_length; | |
e0001a05 NC |
4194 | fixS *the_fix; |
4195 | ||
43cd72b9 BW |
4196 | reloc = BFD_RELOC_NONE; |
4197 | ||
4198 | /* First try the special cases for "alternate" relocs. */ | |
4199 | if (opcode == xtensa_l32r_opcode) | |
4200 | { | |
4201 | if (fragP->tc_frag_data.use_absolute_literals) | |
4202 | reloc = encode_alt_reloc (slot); | |
4203 | } | |
4204 | else if (opcode == xtensa_const16_opcode) | |
4205 | { | |
4206 | if (expr->X_op == O_lo16) | |
4207 | { | |
4208 | reloc = encode_reloc (slot); | |
4209 | expr->X_op = O_symbol; | |
4210 | } | |
4211 | else if (expr->X_op == O_hi16) | |
4212 | { | |
4213 | reloc = encode_alt_reloc (slot); | |
4214 | expr->X_op = O_symbol; | |
4215 | } | |
4216 | } | |
4217 | ||
4218 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4219 | { |
43cd72b9 | 4220 | as_bad (_("invalid relocation for operand %i of '%s'"), |
e0001a05 NC |
4221 | opnum, xtensa_opcode_name (xtensa_default_isa, opcode)); |
4222 | return FALSE; | |
4223 | } | |
4224 | ||
43cd72b9 BW |
4225 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4226 | into the symbol table where the generic portions of the assembler | |
4227 | won't know what to do with them. */ | |
4228 | if (expr->X_op == O_lo16 || expr->X_op == O_hi16) | |
4229 | { | |
4230 | as_bad (_("invalid expression for operand %i of '%s'"), | |
4231 | opnum, xtensa_opcode_name (xtensa_default_isa, opcode)); | |
4232 | return FALSE; | |
4233 | } | |
4234 | ||
4235 | /* Next try the generic relocs. */ | |
4236 | if (reloc == BFD_RELOC_NONE) | |
4237 | reloc = encode_reloc (slot); | |
4238 | if (reloc == BFD_RELOC_NONE) | |
4239 | { | |
4240 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4241 | return FALSE; | |
4242 | } | |
e0001a05 | 4243 | |
43cd72b9 | 4244 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4245 | if (!howto) |
4246 | { | |
43cd72b9 | 4247 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4248 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4249 | return FALSE; | |
4250 | } | |
4251 | ||
43cd72b9 BW |
4252 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
4253 | the_fix = fix_new_exp (fragP, offset, fmt_length, expr, | |
e0001a05 | 4254 | howto->pc_relative, reloc); |
d9740523 | 4255 | the_fix->fx_no_overflow = 1; |
e0001a05 | 4256 | |
7fa3d080 BW |
4257 | if (expr->X_add_symbol |
4258 | && (S_IS_EXTERNAL (expr->X_add_symbol) | |
4259 | || S_IS_WEAK (expr->X_add_symbol))) | |
4260 | the_fix->fx_plt = TRUE; | |
4261 | ||
4262 | the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol; | |
4263 | the_fix->tc_fix_data.X_add_number = expr->X_add_number; | |
4264 | the_fix->tc_fix_data.slot = slot; | |
4265 | ||
4266 | return TRUE; | |
4267 | } | |
4268 | ||
4269 | ||
4270 | static bfd_boolean | |
4271 | xg_emit_insn_to_buf (TInsn *tinsn, | |
4272 | xtensa_format fmt, | |
4273 | char *buf, | |
4274 | fragS *fragP, | |
4275 | offsetT offset, | |
4276 | bfd_boolean build_fix) | |
4277 | { | |
4278 | static xtensa_insnbuf insnbuf = NULL; | |
4279 | bfd_boolean has_symbolic_immed = FALSE; | |
4280 | bfd_boolean ok = TRUE; | |
4281 | if (!insnbuf) | |
4282 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4283 | ||
4284 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4285 | if (has_symbolic_immed && build_fix) | |
4286 | { | |
4287 | /* Add a fixup. */ | |
4288 | int opnum = get_relaxable_immed (tinsn->opcode); | |
4289 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4290 | |
7fa3d080 BW |
4291 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, 0, exp, fragP, offset)) |
4292 | ok = FALSE; | |
4293 | } | |
4294 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4295 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4296 | (unsigned char *) buf, 0); | |
7fa3d080 | 4297 | return ok; |
e0001a05 NC |
4298 | } |
4299 | ||
4300 | ||
7fa3d080 BW |
4301 | static void |
4302 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4303 | { |
4304 | symbolS *sym = get_special_literal_symbol (); | |
4305 | int i; | |
4306 | if (lit_sym == 0) | |
4307 | return; | |
4308 | assert (insn->insn_type == ITYPE_INSN); | |
4309 | for (i = 0; i < insn->ntok; i++) | |
4310 | if (insn->tok[i].X_add_symbol == sym) | |
4311 | insn->tok[i].X_add_symbol = lit_sym; | |
4312 | ||
4313 | } | |
4314 | ||
4315 | ||
7fa3d080 BW |
4316 | static void |
4317 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4318 | { |
4319 | symbolS *sym = get_special_label_symbol (); | |
4320 | int i; | |
43cd72b9 | 4321 | /* assert (!insn->is_literal); */ |
e0001a05 NC |
4322 | for (i = 0; i < insn->ntok; i++) |
4323 | if (insn->tok[i].X_add_symbol == sym) | |
4324 | insn->tok[i].X_add_symbol = label_sym; | |
4325 | ||
4326 | } | |
4327 | ||
4328 | ||
43cd72b9 | 4329 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4330 | integer register. */ |
4331 | ||
4332 | static bfd_boolean | |
7fa3d080 | 4333 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4334 | { |
4335 | int i; | |
4336 | int num_ops; | |
4337 | xtensa_isa isa = xtensa_default_isa; | |
4338 | ||
43cd72b9 | 4339 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4340 | |
4341 | for (i = 0; i < num_ops; i++) | |
4342 | { | |
43cd72b9 BW |
4343 | char inout; |
4344 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4345 | if ((inout == 'o' || inout == 'm') | |
4346 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4347 | { |
43cd72b9 BW |
4348 | xtensa_regfile opnd_rf = |
4349 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4350 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4351 | { |
4352 | if ((insn->tok[i].X_op == O_register) | |
4353 | && (insn->tok[i].X_add_number == regnum)) | |
4354 | return TRUE; | |
4355 | } | |
4356 | } | |
4357 | } | |
4358 | return FALSE; | |
4359 | } | |
4360 | ||
4361 | ||
4362 | static bfd_boolean | |
7fa3d080 | 4363 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4364 | { |
4365 | xtensa_opcode opcode = tinsn->opcode; | |
4366 | ||
4367 | if (opcode == XTENSA_UNDEFINED) | |
4368 | return FALSE; | |
4369 | ||
4370 | if (opcode == xtensa_call0_opcode | |
4371 | || opcode == xtensa_callx0_opcode | |
4372 | || opcode == xtensa_call4_opcode | |
4373 | || opcode == xtensa_callx4_opcode | |
4374 | || opcode == xtensa_call8_opcode | |
4375 | || opcode == xtensa_callx8_opcode | |
4376 | || opcode == xtensa_call12_opcode | |
4377 | || opcode == xtensa_callx12_opcode | |
4378 | || opcode == xtensa_isync_opcode | |
4379 | || opcode == xtensa_ret_opcode | |
4380 | || opcode == xtensa_ret_n_opcode | |
4381 | || opcode == xtensa_retw_opcode | |
4382 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4383 | || opcode == xtensa_waiti_opcode |
4384 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 NC |
4385 | return TRUE; |
4386 | ||
e0001a05 NC |
4387 | return FALSE; |
4388 | } | |
4389 | ||
4390 | ||
4391 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4392 | This allows the debugger to add unaligned labels. | |
4393 | Also, the assembler generates stabs labels that need | |
4394 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4395 | ||
7fa3d080 BW |
4396 | static bfd_boolean |
4397 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4398 | { |
4399 | const char *name = S_GET_NAME (sym); | |
4400 | static size_t fake_size = 0; | |
4401 | ||
4402 | if (name | |
4403 | && name[0] == '.' | |
4404 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4405 | return TRUE; | |
4406 | ||
4407 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4408 | if (fake_size == 0) | |
4409 | fake_size = strlen (FAKE_LABEL_NAME); | |
4410 | ||
43cd72b9 | 4411 | if (name |
e0001a05 NC |
4412 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4413 | && (name[fake_size] == 'F' | |
4414 | || name[fake_size] == 'L' | |
4415 | || (name[fake_size] == 'e' | |
4416 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4417 | return TRUE; | |
4418 | ||
4419 | return FALSE; | |
4420 | } | |
4421 | ||
4422 | ||
7fa3d080 BW |
4423 | static fragS * |
4424 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4425 | { |
4426 | fragS *next_fragP = fragP->fr_next; | |
4427 | ||
4428 | /* Sometimes an empty will end up here due storage allocation issues. | |
4429 | So we have to skip until we find something legit. */ | |
4430 | while (next_fragP && next_fragP->fr_fix == 0) | |
4431 | next_fragP = next_fragP->fr_next; | |
4432 | ||
4433 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4434 | return NULL; | |
4435 | ||
4436 | return next_fragP; | |
4437 | } | |
4438 | ||
4439 | ||
43cd72b9 | 4440 | static bfd_boolean |
7fa3d080 | 4441 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4442 | { |
4443 | xtensa_opcode out_opcode; | |
4444 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4445 | ||
4446 | if (next_fragP == NULL) | |
4447 | return FALSE; | |
4448 | ||
4449 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4450 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4451 | { | |
4452 | *opcode = out_opcode; | |
4453 | return TRUE; | |
4454 | } | |
4455 | return FALSE; | |
4456 | } | |
4457 | ||
4458 | ||
4459 | static int | |
7fa3d080 | 4460 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4461 | { |
e0001a05 NC |
4462 | static xtensa_insnbuf insnbuf = NULL; |
4463 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 BW |
4464 | xtensa_format fmt; |
4465 | int fmt_size; | |
e0001a05 NC |
4466 | |
4467 | if (!insnbuf) | |
4468 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4469 | ||
43cd72b9 BW |
4470 | if (fragP == NULL) |
4471 | return XTENSA_UNDEFINED; | |
4472 | ||
d77b99c9 BW |
4473 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4474 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4475 | |
4476 | fmt = xtensa_format_decode (isa, insnbuf); | |
4477 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4478 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4479 | fmt_size = xtensa_format_length (isa, fmt); |
4480 | ||
4481 | /* If the next format won't be changing due to relaxation, just | |
4482 | return the length of the first format. */ | |
4483 | if (fragP->fr_opcode != fragP->fr_literal) | |
4484 | return fmt_size; | |
4485 | ||
4486 | /* If during relaxation we have to pull an instruction out of a | |
4487 | multi-slot instruction, we will return the more conservative | |
4488 | number. This works because alignment on bigger instructions | |
4489 | is more restrictive than alignment on smaller instructions. | |
4490 | This is more conservative than we would like, but it happens | |
4491 | infrequently. */ | |
4492 | ||
4493 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4494 | return fmt_size; | |
4495 | ||
4496 | /* If we aren't doing one of our own relaxations or it isn't | |
4497 | slot-based, then the insn size won't change. */ | |
4498 | if (fragP->fr_type != rs_machine_dependent) | |
4499 | return fmt_size; | |
4500 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4501 | return fmt_size; | |
4502 | ||
4503 | /* If an instruction is about to grow, return the longer size. */ | |
4504 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
4505 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2) | |
4506 | return 3; | |
4507 | ||
4508 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
4509 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4510 | |
43cd72b9 | 4511 | return fmt_size; |
e0001a05 NC |
4512 | } |
4513 | ||
4514 | ||
7fa3d080 BW |
4515 | static int |
4516 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4517 | { |
7fa3d080 BW |
4518 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4519 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4520 | } |
4521 | ||
4522 | ||
4523 | /* If the next legit fragment is an end-of-loop marker, | |
4524 | switch its state so it will instantiate a NOP. */ | |
4525 | ||
4526 | static void | |
1d19a770 | 4527 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4528 | { |
4529 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4530 | fragS *new_target = NULL; |
e0001a05 | 4531 | |
7b1cc377 | 4532 | if (align_targets) |
43cd72b9 BW |
4533 | { |
4534 | /* We are guaranteed there will be one of these... */ | |
4535 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4536 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4537 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4538 | next_fragP = next_fragP->fr_next; | |
4539 | ||
4540 | assert (next_fragP->fr_type == rs_machine_dependent | |
4541 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4542 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4543 | ||
4544 | /* ...and one of these. */ | |
4545 | new_target = next_fragP->fr_next; | |
4546 | while (!(new_target->fr_type == rs_machine_dependent | |
4547 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4548 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4549 | new_target = new_target->fr_next; | |
4550 | ||
4551 | assert (new_target->fr_type == rs_machine_dependent | |
4552 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4553 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4554 | } | |
43cd72b9 | 4555 | |
1d19a770 | 4556 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4557 | { |
1d19a770 BW |
4558 | if (next_fragP->fr_type == rs_machine_dependent |
4559 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4560 | { |
1d19a770 BW |
4561 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4562 | return; | |
e0001a05 | 4563 | } |
1d19a770 BW |
4564 | |
4565 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4566 | } |
4567 | } | |
4568 | ||
4569 | ||
4570 | static bfd_boolean | |
7fa3d080 | 4571 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4572 | { |
43cd72b9 | 4573 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4574 | so we have to skip until we find something legit. */ |
4575 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4576 | { | |
4577 | if (fragP->tc_frag_data.is_branch_target) | |
4578 | return TRUE; | |
4579 | if (fragP->fr_fix != 0) | |
4580 | break; | |
4581 | } | |
4582 | return FALSE; | |
4583 | } | |
4584 | ||
4585 | ||
4586 | static bfd_boolean | |
7fa3d080 | 4587 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 NC |
4588 | { |
4589 | /* Sometimes an empty will end up here due storage allocation issues. | |
4590 | So we have to skip until we find something legit. */ | |
4591 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4592 | { | |
4593 | if (fragP->tc_frag_data.is_loop_target) | |
4594 | return TRUE; | |
4595 | if (fragP->fr_fix != 0) | |
4596 | break; | |
4597 | } | |
4598 | return FALSE; | |
4599 | } | |
4600 | ||
4601 | ||
4602 | static addressT | |
7fa3d080 | 4603 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4604 | { |
4605 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4606 | xtensa_opcode next_opcode; |
e0001a05 | 4607 | |
43cd72b9 | 4608 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4609 | return 0; |
4610 | ||
43cd72b9 BW |
4611 | /* Sometimes an empty will end up here due to storage allocation issues, |
4612 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4613 | while (next_fragp->fr_fix == 0) |
4614 | next_fragp = next_fragp->fr_next; | |
4615 | ||
4616 | if (next_fragp->fr_type != rs_machine_dependent) | |
4617 | return 0; | |
4618 | ||
4619 | /* There is some implicit knowledge encoded in here. | |
4620 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4621 | been relaxed. Note that we can assume that the LOOP |
4622 | instruction is in slot 0 because loops aren't bundleable. */ | |
4623 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
e0001a05 NC |
4624 | return get_expanded_loop_offset (next_opcode); |
4625 | ||
4626 | return 0; | |
4627 | } | |
4628 | ||
4629 | ||
4630 | /* Mark a location where we can later insert literal frags. Update | |
4631 | the section's literal_pool_loc, so subsequent literals can be | |
4632 | placed nearest to their use. */ | |
4633 | ||
4634 | static void | |
7fa3d080 | 4635 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4636 | { |
4637 | /* Any labels pointing to the current location need | |
4638 | to be adjusted to after the literal pool. */ | |
4639 | emit_state s; | |
e0001a05 | 4640 | fragS *pool_location; |
e0001a05 | 4641 | |
43cd72b9 BW |
4642 | if (use_literal_section && !directive_state[directive_absolute_literals]) |
4643 | return; | |
4644 | ||
e0001a05 | 4645 | frag_align (2, 0, 0); |
43cd72b9 | 4646 | record_alignment (now_seg, 2); |
e0001a05 | 4647 | |
dd49a749 BW |
4648 | /* We stash info in these frags so we can later move the literal's |
4649 | fixes into this frchain's fix list. */ | |
e0001a05 | 4650 | pool_location = frag_now; |
dd49a749 BW |
4651 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
4652 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4653 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4654 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4655 | frag_now->tc_frag_data.lit_seg = now_seg; |
4656 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4657 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4658 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4659 | |
4660 | /* Now put a frag into the literal pool that points to this location. */ | |
4661 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4662 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4663 | frag_align (2, 0, 0); | |
4664 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4665 | |
4666 | /* Close whatever frag is there. */ | |
4667 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4668 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4669 | frag_now->tc_frag_data.literal_frag = pool_location; |
4670 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4671 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4672 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4673 | } |
4674 | ||
4675 | ||
43cd72b9 BW |
4676 | /* Build a nop of the correct size into tinsn. */ |
4677 | ||
4678 | static void | |
7fa3d080 | 4679 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4680 | { |
4681 | tinsn_init (tinsn); | |
4682 | switch (size) | |
4683 | { | |
4684 | case 2: | |
4685 | tinsn->opcode = xtensa_nop_n_opcode; | |
4686 | tinsn->ntok = 0; | |
4687 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4688 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4689 | break; | |
4690 | ||
4691 | case 3: | |
4692 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4693 | { | |
4694 | tinsn->opcode = xtensa_or_opcode; | |
4695 | set_expr_const (&tinsn->tok[0], 1); | |
4696 | set_expr_const (&tinsn->tok[1], 1); | |
4697 | set_expr_const (&tinsn->tok[2], 1); | |
4698 | tinsn->ntok = 3; | |
4699 | } | |
4700 | else | |
4701 | tinsn->opcode = xtensa_nop_opcode; | |
4702 | ||
4703 | assert (tinsn->opcode != XTENSA_UNDEFINED); | |
4704 | } | |
4705 | } | |
4706 | ||
4707 | ||
e0001a05 NC |
4708 | /* Assemble a NOP of the requested size in the buffer. User must have |
4709 | allocated "buf" with at least "size" bytes. */ | |
4710 | ||
7fa3d080 | 4711 | static void |
d77b99c9 | 4712 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4713 | { |
4714 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4715 | TInsn tinsn; |
e0001a05 | 4716 | |
43cd72b9 | 4717 | build_nop (&tinsn, size); |
e0001a05 | 4718 | |
43cd72b9 BW |
4719 | if (!insnbuf) |
4720 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4721 | |
43cd72b9 | 4722 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4723 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4724 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4725 | } |
4726 | ||
4727 | ||
4728 | /* Return the number of bytes for the offset of the expanded loop | |
4729 | instruction. This should be incorporated into the relaxation | |
4730 | specification but is hard-coded here. This is used to auto-align | |
4731 | the loop instruction. It is invalid to call this function if the | |
4732 | configuration does not have loops or if the opcode is not a loop | |
4733 | opcode. */ | |
4734 | ||
4735 | static addressT | |
7fa3d080 | 4736 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4737 | { |
4738 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4739 | This MUST correspond directly to the specification of the loop | |
4740 | expansion. It will be validated on fragment conversion. */ | |
43cd72b9 | 4741 | assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4742 | if (opcode == xtensa_loop_opcode) |
4743 | return 0; | |
4744 | if (opcode == xtensa_loopnez_opcode) | |
4745 | return 3; | |
4746 | if (opcode == xtensa_loopgtz_opcode) | |
4747 | return 6; | |
4748 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4749 | return 0; | |
4750 | } | |
4751 | ||
4752 | ||
7fa3d080 BW |
4753 | static fragS * |
4754 | get_literal_pool_location (segT seg) | |
e0001a05 NC |
4755 | { |
4756 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; | |
4757 | } | |
4758 | ||
4759 | ||
4760 | static void | |
7fa3d080 | 4761 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4762 | { |
4763 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4764 | } | |
4765 | ||
43cd72b9 BW |
4766 | |
4767 | /* Set frag assembly state should be called when a new frag is | |
4768 | opened and after a frag has been closed. */ | |
4769 | ||
7fa3d080 BW |
4770 | static void |
4771 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4772 | { |
4773 | if (!density_supported) | |
4774 | fragP->tc_frag_data.is_no_density = TRUE; | |
4775 | ||
4776 | /* This function is called from subsegs_finish, which is called | |
4777 | after xtensa_end, so we can't use "use_transform" or | |
4778 | "use_schedule" here. */ | |
4779 | if (!directive_state[directive_transform]) | |
4780 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4781 | if (directive_state[directive_longcalls]) |
4782 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4783 | fragP->tc_frag_data.use_absolute_literals = |
4784 | directive_state[directive_absolute_literals]; | |
4785 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4786 | } | |
4787 | ||
4788 | ||
7fa3d080 BW |
4789 | static bfd_boolean |
4790 | relaxable_section (asection *sec) | |
43cd72b9 BW |
4791 | { |
4792 | return (sec->flags & SEC_DEBUGGING) == 0; | |
4793 | } | |
4794 | ||
4795 | ||
4796 | static void | |
7fa3d080 | 4797 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
4798 | { |
4799 | segT *seclist; | |
4800 | ||
4801 | /* Walk over each fragment of all of the current segments. For each | |
4802 | unmarked fragment, mark it with the same info as the previous | |
4803 | fragment. */ | |
4804 | for (seclist = &stdoutput->sections; | |
4805 | seclist && *seclist; | |
4806 | seclist = &(*seclist)->next) | |
4807 | { | |
4808 | segT sec = *seclist; | |
4809 | segment_info_type *seginfo; | |
4810 | fragS *fragP; | |
4811 | flagword flags; | |
4812 | flags = bfd_get_section_flags (stdoutput, sec); | |
4813 | if (flags & SEC_DEBUGGING) | |
4814 | continue; | |
4815 | if (!(flags & SEC_ALLOC)) | |
4816 | continue; | |
4817 | ||
4818 | seginfo = seg_info (sec); | |
4819 | if (seginfo && seginfo->frchainP) | |
4820 | { | |
4821 | fragS *last_fragP = 0; | |
4822 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4823 | fragP = fragP->fr_next) | |
4824 | { | |
4825 | if (fragP->fr_fix != 0 | |
4826 | && !fragP->tc_frag_data.is_assembly_state_set) | |
4827 | { | |
4828 | if (last_fragP == 0) | |
4829 | { | |
4830 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
4831 | _("assembly state not set for first frag in section %s"), | |
4832 | sec->name); | |
4833 | } | |
4834 | else | |
4835 | { | |
4836 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4837 | fragP->tc_frag_data.is_no_density = | |
4838 | last_fragP->tc_frag_data.is_no_density; | |
4839 | fragP->tc_frag_data.is_no_transform = | |
4840 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
4841 | fragP->tc_frag_data.use_longcalls = |
4842 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
4843 | fragP->tc_frag_data.use_absolute_literals = |
4844 | last_fragP->tc_frag_data.use_absolute_literals; | |
4845 | } | |
4846 | } | |
4847 | if (fragP->tc_frag_data.is_assembly_state_set) | |
4848 | last_fragP = fragP; | |
4849 | } | |
4850 | } | |
4851 | } | |
4852 | } | |
4853 | ||
4854 | ||
4855 | static void | |
7fa3d080 BW |
4856 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
4857 | asection *sec, | |
4858 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4859 | { |
4860 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4861 | segment_info_type *seginfo = seg_info (sec); | |
4862 | fragS *frag = seginfo->frchainP->frch_root; | |
4863 | ||
4864 | if (flags & SEC_CODE) | |
4865 | { | |
4866 | xtensa_isa isa = xtensa_default_isa; | |
4867 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
4868 | while (frag != NULL) | |
4869 | { | |
4870 | if (frag->tc_frag_data.is_branch_target) | |
4871 | { | |
4872 | int op_size; | |
664df4e4 | 4873 | addressT branch_align, frag_addr; |
43cd72b9 BW |
4874 | xtensa_format fmt; |
4875 | ||
d77b99c9 BW |
4876 | xtensa_insnbuf_from_chars |
4877 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4878 | fmt = xtensa_format_decode (isa, insnbuf); |
4879 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
4880 | branch_align = 1 << branch_align_power (sec); |
4881 | frag_addr = frag->fr_address % branch_align; | |
4882 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
4883 | as_warn_where (frag->fr_file, frag->fr_line, |
4884 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 4885 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4886 | } |
4887 | frag = frag->fr_next; | |
4888 | } | |
4889 | xtensa_insnbuf_free (isa, insnbuf); | |
4890 | } | |
4891 | } | |
4892 | ||
4893 | ||
4894 | static void | |
7fa3d080 BW |
4895 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
4896 | asection *sec, | |
4897 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4898 | { |
4899 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4900 | segment_info_type *seginfo = seg_info (sec); | |
4901 | fragS *frag = seginfo->frchainP->frch_root; | |
4902 | xtensa_isa isa = xtensa_default_isa; | |
4903 | ||
4904 | if (flags & SEC_CODE) | |
4905 | { | |
4906 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
4907 | while (frag != NULL) | |
4908 | { | |
4909 | if (frag->tc_frag_data.is_first_loop_insn) | |
4910 | { | |
4911 | int op_size; | |
d77b99c9 | 4912 | addressT frag_addr; |
43cd72b9 BW |
4913 | xtensa_format fmt; |
4914 | ||
d77b99c9 BW |
4915 | xtensa_insnbuf_from_chars |
4916 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4917 | fmt = xtensa_format_decode (isa, insnbuf); |
4918 | op_size = xtensa_format_length (isa, fmt); | |
4919 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
4920 | ||
d77b99c9 | 4921 | if (frag_addr + op_size > xtensa_fetch_width) |
43cd72b9 BW |
4922 | as_warn_where (frag->fr_file, frag->fr_line, |
4923 | _("unaligned loop: %d bytes at 0x%lx"), | |
dd49a749 | 4924 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4925 | } |
4926 | frag = frag->fr_next; | |
4927 | } | |
4928 | xtensa_insnbuf_free (isa, insnbuf); | |
4929 | } | |
4930 | } | |
4931 | ||
4932 | ||
30f725a1 BW |
4933 | static int |
4934 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
4935 | { |
4936 | xtensa_isa isa = xtensa_default_isa; | |
4937 | static xtensa_insnbuf insnbuf = NULL; | |
4938 | static xtensa_insnbuf slotbuf = NULL; | |
4939 | xtensa_format fmt; | |
4940 | int slot; | |
4941 | bfd_boolean alt_reloc; | |
4942 | xtensa_opcode opcode; | |
4943 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
4944 | ||
4945 | (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc); | |
4946 | if (alt_reloc) | |
4947 | as_fatal (_("unexpected fix")); | |
4948 | ||
4949 | if (!insnbuf) | |
4950 | { | |
4951 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4952 | slotbuf = xtensa_insnbuf_alloc (isa); | |
4953 | } | |
4954 | ||
d77b99c9 | 4955 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
4956 | fmt = xtensa_format_decode (isa, insnbuf); |
4957 | if (fmt == XTENSA_UNDEFINED) | |
4958 | as_fatal (_("undecodable fix")); | |
4959 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
4960 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
4961 | if (opcode == XTENSA_UNDEFINED) | |
4962 | as_fatal (_("undecodable fix")); | |
4963 | ||
4964 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
4965 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 4966 | of a CONST16 operand. */ |
43cd72b9 | 4967 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 4968 | return 0; |
43cd72b9 BW |
4969 | |
4970 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
4971 | get_relaxable_immed (opcode), val, | |
4972 | fixP->fx_file, fixP->fx_line); | |
4973 | ||
4974 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 4975 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
4976 | |
4977 | return 1; | |
43cd72b9 BW |
4978 | } |
4979 | ||
e0001a05 NC |
4980 | \f |
4981 | /* External Functions and Other GAS Hooks. */ | |
4982 | ||
4983 | const char * | |
7fa3d080 | 4984 | xtensa_target_format (void) |
e0001a05 NC |
4985 | { |
4986 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
4987 | } | |
4988 | ||
4989 | ||
4990 | void | |
7fa3d080 | 4991 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
4992 | { |
4993 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
4994 | } | |
4995 | ||
4996 | ||
4997 | void | |
7fa3d080 | 4998 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
4999 | { |
5000 | if (target_big_endian) | |
5001 | number_to_chars_bigendian (buf, val, n); | |
5002 | else | |
5003 | number_to_chars_littleendian (buf, val, n); | |
5004 | } | |
5005 | ||
5006 | ||
5007 | /* This function is called once, at assembler startup time. It should | |
5008 | set up all the tables, etc. that the MD part of the assembler will | |
5009 | need. */ | |
5010 | ||
5011 | void | |
7fa3d080 | 5012 | md_begin (void) |
e0001a05 NC |
5013 | { |
5014 | segT current_section = now_seg; | |
5015 | int current_subsec = now_subseg; | |
5016 | xtensa_isa isa; | |
5017 | ||
43cd72b9 | 5018 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 5019 | isa = xtensa_default_isa; |
e0001a05 | 5020 | |
43cd72b9 BW |
5021 | linkrelax = 1; |
5022 | ||
5023 | /* Set up the .literal, .fini.literal and .init.literal sections. */ | |
e0001a05 NC |
5024 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
5025 | default_lit_sections.init_lit_seg_name = INIT_LITERAL_SECTION_NAME; | |
5026 | default_lit_sections.fini_lit_seg_name = FINI_LITERAL_SECTION_NAME; | |
5027 | default_lit_sections.lit_seg_name = LITERAL_SECTION_NAME; | |
43cd72b9 | 5028 | default_lit_sections.lit4_seg_name = LIT4_SECTION_NAME; |
e0001a05 NC |
5029 | |
5030 | subseg_set (current_section, current_subsec); | |
5031 | ||
43cd72b9 BW |
5032 | xg_init_vinsn (&cur_vinsn); |
5033 | ||
e0001a05 NC |
5034 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); |
5035 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
5036 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
5037 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
5038 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
5039 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
5040 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
5041 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
5042 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
5043 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 5044 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 5045 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
43cd72b9 BW |
5046 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
5047 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 5048 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
e0001a05 | 5049 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 5050 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
5051 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
5052 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
5053 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 5054 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
5055 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
5056 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
5057 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
5058 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
5059 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
5060 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 5061 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 5062 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 BW |
5063 | |
5064 | init_op_placement_info_table (); | |
5065 | ||
5066 | /* Set up the assembly state. */ | |
5067 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5068 | xtensa_set_frag_assembly_state (frag_now); | |
5069 | } | |
5070 | ||
5071 | ||
5072 | /* TC_INIT_FIX_DATA hook */ | |
5073 | ||
5074 | void | |
7fa3d080 | 5075 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5076 | { |
5077 | x->tc_fix_data.slot = 0; | |
5078 | x->tc_fix_data.X_add_symbol = NULL; | |
5079 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5080 | } |
5081 | ||
5082 | ||
5083 | /* tc_frob_label hook */ | |
5084 | ||
5085 | void | |
7fa3d080 | 5086 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5087 | { |
7b1cc377 BW |
5088 | float freq = get_subseg_target_freq (now_seg, now_subseg); |
5089 | ||
43cd72b9 BW |
5090 | /* Since the label was already attached to a frag associated with the |
5091 | previous basic block, it now needs to be reset to the current frag. */ | |
5092 | symbol_set_frag (sym, frag_now); | |
5093 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5094 | ||
82e7541d BW |
5095 | if (generating_literals) |
5096 | xtensa_add_literal_sym (sym); | |
5097 | else | |
5098 | xtensa_add_insn_label (sym); | |
5099 | ||
7b1cc377 BW |
5100 | if (symbol_get_tc (sym)->is_loop_target) |
5101 | { | |
5102 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5103 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5104 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5105 | ||
5106 | xtensa_set_frag_assembly_state (frag_now); | |
5107 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5108 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5109 | ||
5110 | xtensa_set_frag_assembly_state (frag_now); | |
5111 | xtensa_move_labels (frag_now, 0, TRUE); | |
5112 | } | |
e0001a05 NC |
5113 | |
5114 | /* No target aligning in the absolute section. */ | |
61846f28 | 5115 | if (now_seg != absolute_section |
43cd72b9 | 5116 | && do_align_targets () |
61846f28 | 5117 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5118 | && !generating_literals) |
5119 | { | |
43cd72b9 BW |
5120 | xtensa_set_frag_assembly_state (frag_now); |
5121 | ||
43cd72b9 | 5122 | frag_var (rs_machine_dependent, |
7b1cc377 | 5123 | 0, (int) freq, |
e0001a05 NC |
5124 | RELAX_DESIRE_ALIGN_IF_TARGET, |
5125 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5126 | xtensa_set_frag_assembly_state (frag_now); |
82e7541d | 5127 | xtensa_move_labels (frag_now, 0, TRUE); |
43cd72b9 BW |
5128 | } |
5129 | ||
5130 | /* We need to mark the following properties even if we aren't aligning. */ | |
5131 | ||
5132 | /* If the label is already known to be a branch target, i.e., a | |
5133 | forward branch, mark the frag accordingly. Backward branches | |
5134 | are handled by xg_add_branch_and_loop_targets. */ | |
5135 | if (symbol_get_tc (sym)->is_branch_target) | |
5136 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5137 | ||
5138 | /* Loops only go forward, so they can be identified here. */ | |
5139 | if (symbol_get_tc (sym)->is_loop_target) | |
5140 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
5141 | } | |
5142 | ||
5143 | ||
5144 | /* tc_unrecognized_line hook */ | |
5145 | ||
5146 | int | |
7fa3d080 | 5147 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5148 | { |
5149 | switch (ch) | |
5150 | { | |
5151 | case '{' : | |
5152 | if (cur_vinsn.inside_bundle == 0) | |
5153 | { | |
5154 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5155 | when using --gstabs. Temporarily disable debug info. */ | |
5156 | generate_lineno_debug (); | |
5157 | if (debug_type == DEBUG_STABS) | |
5158 | { | |
5159 | xt_saved_debug_type = debug_type; | |
5160 | debug_type = DEBUG_NONE; | |
5161 | } | |
82e7541d | 5162 | |
43cd72b9 BW |
5163 | cur_vinsn.inside_bundle = 1; |
5164 | } | |
5165 | else | |
5166 | { | |
5167 | as_bad (_("extra opening brace")); | |
5168 | return 0; | |
5169 | } | |
5170 | break; | |
82e7541d | 5171 | |
43cd72b9 BW |
5172 | case '}' : |
5173 | if (cur_vinsn.inside_bundle) | |
5174 | finish_vinsn (&cur_vinsn); | |
5175 | else | |
5176 | { | |
5177 | as_bad (_("extra closing brace")); | |
5178 | return 0; | |
5179 | } | |
5180 | break; | |
5181 | default: | |
5182 | as_bad (_("syntax error")); | |
5183 | return 0; | |
e0001a05 | 5184 | } |
43cd72b9 | 5185 | return 1; |
e0001a05 NC |
5186 | } |
5187 | ||
5188 | ||
5189 | /* md_flush_pending_output hook */ | |
5190 | ||
5191 | void | |
7fa3d080 | 5192 | xtensa_flush_pending_output (void) |
e0001a05 | 5193 | { |
43cd72b9 BW |
5194 | if (cur_vinsn.inside_bundle) |
5195 | as_bad (_("missing closing brace")); | |
5196 | ||
e0001a05 NC |
5197 | /* If there is a non-zero instruction fragment, close it. */ |
5198 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5199 | { | |
5200 | frag_wane (frag_now); | |
5201 | frag_new (0); | |
43cd72b9 | 5202 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5203 | } |
5204 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5205 | |
5206 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5207 | } |
5208 | ||
5209 | ||
43cd72b9 BW |
5210 | /* We had an error while parsing an instruction. The string might look |
5211 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5212 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5213 | and the num_slots field will grow past the end of the array of slots, | |
5214 | and bad things happen. */ | |
5215 | ||
5216 | static void | |
7fa3d080 | 5217 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5218 | { |
5219 | if (cur_vinsn.inside_bundle) | |
5220 | { | |
5221 | if (*input_line_pointer == '}' | |
5222 | || *(input_line_pointer - 1) == '}' | |
5223 | || *(input_line_pointer - 2) == '}') | |
5224 | xg_clear_vinsn (&cur_vinsn); | |
5225 | } | |
5226 | } | |
5227 | ||
5228 | ||
e0001a05 | 5229 | void |
7fa3d080 | 5230 | md_assemble (char *str) |
e0001a05 NC |
5231 | { |
5232 | xtensa_isa isa = xtensa_default_isa; | |
5233 | char *opname; | |
5234 | unsigned opnamelen; | |
5235 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5236 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5237 | int num_args; |
e0001a05 | 5238 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5239 | |
e0001a05 NC |
5240 | tinsn_init (&orig_insn); |
5241 | ||
5242 | /* Split off the opcode. */ | |
5243 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
5244 | opname = xmalloc (opnamelen + 1); | |
5245 | memcpy (opname, str, opnamelen); | |
5246 | opname[opnamelen] = '\0'; | |
5247 | ||
5248 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5249 | if (num_args == -1) | |
5250 | { | |
5251 | as_bad (_("syntax error")); | |
5252 | return; | |
5253 | } | |
5254 | ||
5255 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5256 | return; | |
5257 | ||
5258 | /* Check for an underbar prefix. */ | |
5259 | if (*opname == '_') | |
5260 | { | |
5261 | has_underbar = TRUE; | |
5262 | opname += 1; | |
5263 | } | |
5264 | ||
5265 | orig_insn.insn_type = ITYPE_INSN; | |
5266 | orig_insn.ntok = 0; | |
43cd72b9 | 5267 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 NC |
5268 | |
5269 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); | |
5270 | if (orig_insn.opcode == XTENSA_UNDEFINED) | |
5271 | { | |
43cd72b9 BW |
5272 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5273 | if (fmt == XTENSA_UNDEFINED) | |
5274 | { | |
5275 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5276 | error_reset_cur_vinsn (); | |
5277 | return; | |
5278 | } | |
5279 | if (!cur_vinsn.inside_bundle) | |
5280 | { | |
5281 | as_bad (_("format names only valid inside bundles")); | |
5282 | error_reset_cur_vinsn (); | |
5283 | return; | |
5284 | } | |
5285 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5286 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5287 | opname); | |
5288 | cur_vinsn.format = fmt; | |
5289 | free (has_underbar ? opname - 1 : opname); | |
5290 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5291 | return; |
5292 | } | |
5293 | ||
e0001a05 NC |
5294 | /* Parse the arguments. */ |
5295 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5296 | { | |
5297 | as_bad (_("syntax error")); | |
43cd72b9 | 5298 | error_reset_cur_vinsn (); |
e0001a05 NC |
5299 | return; |
5300 | } | |
5301 | ||
5302 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5303 | free (has_underbar ? opname - 1 : opname); | |
5304 | opname = 0; | |
5305 | while (num_args-- > 0) | |
5306 | free (arg_strings[num_args]); | |
5307 | ||
43cd72b9 BW |
5308 | /* Get expressions for invisible operands. */ |
5309 | if (get_invisible_operands (&orig_insn)) | |
5310 | { | |
5311 | error_reset_cur_vinsn (); | |
5312 | return; | |
5313 | } | |
5314 | ||
e0001a05 NC |
5315 | /* Check for the right number and type of arguments. */ |
5316 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5317 | { |
43cd72b9 BW |
5318 | error_reset_cur_vinsn (); |
5319 | return; | |
e0001a05 NC |
5320 | } |
5321 | ||
43cd72b9 BW |
5322 | dwarf2_where (&orig_insn.loc); |
5323 | ||
5324 | xg_add_branch_and_loop_targets (&orig_insn); | |
5325 | ||
61846f28 | 5326 | /* Special-case for "entry" instruction. */ |
b08b5071 | 5327 | if (orig_insn.opcode == xtensa_entry_opcode) |
e0001a05 | 5328 | { |
43cd72b9 BW |
5329 | /* Check that the third opcode (#2) is >= 16. */ |
5330 | if (orig_insn.ntok >= 3) | |
e0001a05 | 5331 | { |
43cd72b9 | 5332 | expressionS *exp = &orig_insn.tok[2]; |
e0001a05 NC |
5333 | switch (exp->X_op) |
5334 | { | |
5335 | case O_constant: | |
5336 | if (exp->X_add_number < 16) | |
5337 | as_warn (_("entry instruction with stack decrement < 16")); | |
5338 | break; | |
5339 | ||
5340 | default: | |
5341 | as_warn (_("entry instruction with non-constant decrement")); | |
5342 | } | |
5343 | } | |
e0001a05 NC |
5344 | } |
5345 | ||
e0001a05 | 5346 | /* Finish it off: |
43cd72b9 BW |
5347 | assemble_tokens (opcode, tok, ntok); |
5348 | expand the tokens from the orig_insn into the | |
5349 | stack of instructions that will not expand | |
e0001a05 | 5350 | unless required at relaxation time. */ |
e0001a05 | 5351 | |
43cd72b9 BW |
5352 | if (!cur_vinsn.inside_bundle) |
5353 | emit_single_op (&orig_insn); | |
5354 | else /* We are inside a bundle. */ | |
e0001a05 | 5355 | { |
43cd72b9 BW |
5356 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5357 | cur_vinsn.num_slots++; | |
5358 | if (*input_line_pointer == '}' | |
5359 | || *(input_line_pointer - 1) == '}' | |
5360 | || *(input_line_pointer - 2) == '}') | |
5361 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5362 | } |
5363 | ||
43cd72b9 BW |
5364 | /* We've just emitted a new instruction so clear the list of labels. */ |
5365 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5366 | } |
5367 | ||
5368 | ||
43cd72b9 | 5369 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5370 | |
43cd72b9 BW |
5371 | /* For a .align directive, we mark the previous block with the alignment |
5372 | information. This will be placed in the object file in the | |
5373 | property section corresponding to this section. */ | |
e0001a05 | 5374 | |
43cd72b9 | 5375 | void |
7fa3d080 | 5376 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5377 | { |
5378 | if (linkrelax | |
b08b5071 | 5379 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5380 | && (fragP->fr_type == rs_align |
5381 | || fragP->fr_type == rs_align_code) | |
5382 | && fragP->fr_address + fragP->fr_fix > 0 | |
5383 | && fragP->fr_offset > 0 | |
5384 | && now_seg != bss_section) | |
e0001a05 | 5385 | { |
43cd72b9 BW |
5386 | fragP->tc_frag_data.is_align = TRUE; |
5387 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5388 | } |
5389 | ||
43cd72b9 | 5390 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5391 | { |
43cd72b9 BW |
5392 | int count; |
5393 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5394 | if (count != 0) | |
5395 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
5396 | _("unaligned entry instruction")); | |
e0001a05 | 5397 | } |
e0001a05 | 5398 | } |
43cd72b9 | 5399 | |
e0001a05 NC |
5400 | |
5401 | /* TC_FRAG_INIT hook */ | |
5402 | ||
5403 | void | |
7fa3d080 | 5404 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5405 | { |
43cd72b9 | 5406 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5407 | } |
5408 | ||
5409 | ||
5410 | symbolS * | |
7fa3d080 | 5411 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5412 | { |
5413 | return NULL; | |
5414 | } | |
5415 | ||
5416 | ||
5417 | /* Round up a section size to the appropriate boundary. */ | |
5418 | ||
5419 | valueT | |
7fa3d080 | 5420 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5421 | { |
5422 | return size; /* Byte alignment is fine. */ | |
5423 | } | |
5424 | ||
5425 | ||
5426 | long | |
7fa3d080 | 5427 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5428 | { |
5429 | char *insn_p; | |
5430 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5431 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5432 | int opnum; |
43cd72b9 | 5433 | uint32 opnd_value; |
e0001a05 | 5434 | xtensa_opcode opcode; |
43cd72b9 BW |
5435 | xtensa_format fmt; |
5436 | int slot; | |
e0001a05 NC |
5437 | xtensa_isa isa = xtensa_default_isa; |
5438 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5439 | bfd_boolean alt_reloc; |
e0001a05 | 5440 | |
e0001a05 | 5441 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5442 | return 0; |
e0001a05 NC |
5443 | |
5444 | if (!insnbuf) | |
43cd72b9 BW |
5445 | { |
5446 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5447 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5448 | } | |
e0001a05 NC |
5449 | |
5450 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5451 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5452 | fmt = xtensa_format_decode (isa, insnbuf); |
5453 | ||
5454 | if (fmt == XTENSA_UNDEFINED) | |
5455 | as_fatal (_("bad instruction format")); | |
5456 | ||
5457 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5458 | as_fatal (_("invalid relocation")); | |
5459 | ||
5460 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5461 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5462 | ||
30f725a1 BW |
5463 | /* Check for "alternate" relocations (operand not specified). None |
5464 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5465 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5466 | { | |
5467 | if (opcode != xtensa_l32r_opcode | |
5468 | && opcode != xtensa_const16_opcode) | |
5469 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5470 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5471 | return 0; |
e0001a05 NC |
5472 | } |
5473 | ||
43cd72b9 BW |
5474 | opnum = get_relaxable_immed (opcode); |
5475 | opnd_value = 0; | |
5476 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5477 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5478 | { |
5479 | as_bad_where (fixP->fx_file, | |
5480 | fixP->fx_line, | |
5481 | _("invalid relocation for operand %d of '%s'"), | |
5482 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5483 | return 0; |
e0001a05 | 5484 | } |
43cd72b9 BW |
5485 | return 0 - opnd_value; |
5486 | } | |
5487 | ||
5488 | ||
5489 | /* TC_FORCE_RELOCATION hook */ | |
5490 | ||
5491 | int | |
7fa3d080 | 5492 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5493 | { |
5494 | switch (fix->fx_r_type) | |
30f725a1 BW |
5495 | { |
5496 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5497 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5498 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5499 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5500 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5501 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5502 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5503 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5504 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5505 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5506 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5507 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5508 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5509 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5510 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5511 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5512 | return 1; |
5513 | default: | |
5514 | break; | |
e0001a05 NC |
5515 | } |
5516 | ||
43cd72b9 BW |
5517 | if (linkrelax && fix->fx_addsy |
5518 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5519 | return 1; | |
5520 | ||
5521 | return generic_force_reloc (fix); | |
5522 | } | |
5523 | ||
5524 | ||
30f725a1 BW |
5525 | /* TC_VALIDATE_FIX_SUB hook */ |
5526 | ||
5527 | int | |
5528 | xtensa_validate_fix_sub (fixS *fix) | |
5529 | { | |
5530 | segT add_symbol_segment, sub_symbol_segment; | |
5531 | ||
5532 | /* The difference of two symbols should be resolved by the assembler when | |
5533 | linkrelax is not set. If the linker may relax the section containing | |
5534 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5535 | the linker knows to adjust the difference value. */ | |
5536 | if (!linkrelax || fix->fx_addsy == NULL) | |
5537 | return 0; | |
5538 | ||
5539 | /* Make sure both symbols are in the same segment, and that segment is | |
5540 | "normal" and relaxable. If the segment is not "normal", then the | |
5541 | fix is not valid. If the segment is not "relaxable", then the fix | |
5542 | should have been handled earlier. */ | |
5543 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5544 | if (! SEG_NORMAL (add_symbol_segment) || | |
5545 | ! relaxable_section (add_symbol_segment)) | |
5546 | return 0; | |
5547 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5548 | return (sub_symbol_segment == add_symbol_segment); | |
5549 | } | |
5550 | ||
5551 | ||
43cd72b9 BW |
5552 | /* NO_PSEUDO_DOT hook */ |
5553 | ||
5554 | /* This function has nothing to do with pseudo dots, but this is the | |
5555 | nearest macro to where the check needs to take place. FIXME: This | |
5556 | seems wrong. */ | |
5557 | ||
5558 | bfd_boolean | |
7fa3d080 | 5559 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5560 | { |
5561 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5562 | as_bad (_("directives are not valid inside bundles")); | |
5563 | ||
5564 | /* This function must always return FALSE because it is called via a | |
5565 | macro that has nothing to do with bundling. */ | |
5566 | return FALSE; | |
e0001a05 NC |
5567 | } |
5568 | ||
5569 | ||
43cd72b9 | 5570 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5571 | |
5572 | void | |
7fa3d080 | 5573 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5574 | { |
43cd72b9 BW |
5575 | /* Set up the assembly state. */ |
5576 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5577 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5578 | } |
5579 | ||
5580 | ||
5581 | /* tc_fix_adjustable hook */ | |
5582 | ||
5583 | bfd_boolean | |
7fa3d080 | 5584 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 | 5585 | { |
43cd72b9 BW |
5586 | /* An offset is not allowed in combination with the difference of two |
5587 | symbols, but that cannot be easily detected after a local symbol | |
5588 | has been adjusted to a (section+offset) form. Return 0 so that such | |
5589 | an fix will not be adjusted. */ | |
5590 | if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset | |
5591 | && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy))) | |
5592 | return 0; | |
5593 | ||
e0001a05 NC |
5594 | /* We need the symbol name for the VTABLE entries. */ |
5595 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5596 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5597 | return 0; | |
5598 | ||
5599 | return 1; | |
5600 | } | |
5601 | ||
5602 | ||
5603 | void | |
30f725a1 | 5604 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5605 | { |
30f725a1 BW |
5606 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
5607 | valueT val; | |
5608 | ||
5609 | switch (fixP->fx_r_type) | |
e0001a05 | 5610 | { |
30f725a1 BW |
5611 | case BFD_RELOC_32: |
5612 | case BFD_RELOC_16: | |
5613 | case BFD_RELOC_8: | |
5614 | if (linkrelax && fixP->fx_subsy) | |
5615 | { | |
5616 | switch (fixP->fx_r_type) | |
5617 | { | |
5618 | case BFD_RELOC_8: | |
5619 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
5620 | break; | |
5621 | case BFD_RELOC_16: | |
5622 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
5623 | break; | |
5624 | case BFD_RELOC_32: | |
5625 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
5626 | break; | |
5627 | default: | |
5628 | break; | |
5629 | } | |
e0001a05 | 5630 | |
30f725a1 BW |
5631 | /* An offset is only allowed when it results from adjusting a |
5632 | local symbol into a section-relative offset. If the offset | |
5633 | came from the original expression, tc_fix_adjustable will have | |
5634 | prevented the fix from being converted to a section-relative | |
5635 | form so that we can flag the error here. */ | |
5636 | if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy)) | |
5637 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5638 | _("cannot represent subtraction with an offset")); | |
5639 | ||
5640 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5641 | - S_GET_VALUE (fixP->fx_subsy)); | |
5642 | ||
5643 | /* The difference value gets written out, and the DIFF reloc | |
5644 | identifies the address of the subtracted symbol (i.e., the one | |
5645 | with the lowest address). */ | |
5646 | *valP = val; | |
5647 | fixP->fx_offset -= val; | |
5648 | fixP->fx_subsy = NULL; | |
5649 | } | |
5650 | else if (! fixP->fx_addsy) | |
e0001a05 | 5651 | { |
30f725a1 | 5652 | val = *valP; |
e0001a05 | 5653 | fixP->fx_done = 1; |
30f725a1 BW |
5654 | } |
5655 | else | |
5656 | break; | |
5657 | md_number_to_chars (fixpos, val, fixP->fx_size); | |
5658 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5659 | break; | |
e0001a05 | 5660 | |
30f725a1 BW |
5661 | case BFD_RELOC_XTENSA_SLOT0_OP: |
5662 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
5663 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
5664 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
5665 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
5666 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
5667 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
5668 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
5669 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
5670 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
5671 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
5672 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
5673 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
5674 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
5675 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
5676 | if (linkrelax) | |
5677 | { | |
5678 | /* Write the tentative value of a PC-relative relocation to a | |
5679 | local symbol into the instruction. The value will be ignored | |
5680 | by the linker, and it makes the object file disassembly | |
5681 | readable when all branch targets are encoded in relocations. */ | |
5682 | ||
5683 | assert (fixP->fx_addsy); | |
5684 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg && !fixP->fx_plt | |
5685 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) | |
5686 | { | |
5687 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5688 | - md_pcrel_from (fixP)); | |
5689 | (void) xg_apply_fix_value (fixP, val); | |
5690 | } | |
5691 | } | |
5692 | else if (! fixP->fx_addsy) | |
5693 | { | |
5694 | val = *valP; | |
5695 | if (xg_apply_fix_value (fixP, val)) | |
5696 | fixP->fx_done = 1; | |
5697 | } | |
5698 | break; | |
e0001a05 | 5699 | |
6e2a91a3 | 5700 | case BFD_RELOC_XTENSA_PLT: |
30f725a1 BW |
5701 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
5702 | case BFD_RELOC_XTENSA_SLOT0_ALT: | |
5703 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5704 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5705 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5706 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5707 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5708 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5709 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5710 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5711 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5712 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5713 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5714 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5715 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5716 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
5717 | /* These all need to be resolved at link-time. Do nothing now. */ | |
5718 | break; | |
e0001a05 | 5719 | |
30f725a1 BW |
5720 | case BFD_RELOC_VTABLE_INHERIT: |
5721 | case BFD_RELOC_VTABLE_ENTRY: | |
5722 | fixP->fx_done = 0; | |
5723 | break; | |
e0001a05 | 5724 | |
30f725a1 BW |
5725 | default: |
5726 | as_bad (_("unhandled local relocation fix %s"), | |
5727 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
5728 | } |
5729 | } | |
5730 | ||
5731 | ||
5732 | char * | |
7fa3d080 | 5733 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 NC |
5734 | { |
5735 | int prec; | |
5736 | LITTLENUM_TYPE words[4]; | |
5737 | char *t; | |
5738 | int i; | |
5739 | ||
5740 | switch (type) | |
5741 | { | |
5742 | case 'f': | |
5743 | prec = 2; | |
5744 | break; | |
5745 | ||
5746 | case 'd': | |
5747 | prec = 4; | |
5748 | break; | |
5749 | ||
5750 | default: | |
5751 | *sizeP = 0; | |
5752 | return "bad call to md_atof"; | |
5753 | } | |
5754 | ||
5755 | t = atof_ieee (input_line_pointer, type, words); | |
5756 | if (t) | |
5757 | input_line_pointer = t; | |
5758 | ||
5759 | *sizeP = prec * 2; | |
5760 | ||
5761 | for (i = prec - 1; i >= 0; i--) | |
5762 | { | |
5763 | int idx = i; | |
5764 | if (target_big_endian) | |
5765 | idx = (prec - 1 - i); | |
5766 | ||
5767 | md_number_to_chars (litP, (valueT) words[idx], 2); | |
5768 | litP += 2; | |
5769 | } | |
5770 | ||
5771 | return NULL; | |
5772 | } | |
5773 | ||
5774 | ||
5775 | int | |
7fa3d080 | 5776 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 5777 | { |
34e41783 | 5778 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
5779 | } |
5780 | ||
5781 | ||
5782 | /* Translate internal representation of relocation info to BFD target | |
5783 | format. */ | |
5784 | ||
5785 | arelent * | |
30f725a1 | 5786 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
5787 | { |
5788 | arelent *reloc; | |
5789 | ||
5790 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
5791 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
5792 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
5793 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
5794 | ||
5795 | /* Make sure none of our internal relocations make it this far. | |
5796 | They'd better have been fully resolved by this point. */ | |
5797 | assert ((int) fixp->fx_r_type > 0); | |
5798 | ||
30f725a1 | 5799 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 5800 | |
e0001a05 NC |
5801 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
5802 | if (reloc->howto == NULL) | |
5803 | { | |
5804 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
5805 | _("cannot represent `%s' relocation in object file"), | |
5806 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
5807 | free (reloc->sym_ptr_ptr); |
5808 | free (reloc); | |
e0001a05 NC |
5809 | return NULL; |
5810 | } | |
5811 | ||
5812 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
43cd72b9 BW |
5813 | as_fatal (_("internal error? cannot generate `%s' relocation"), |
5814 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
e0001a05 | 5815 | |
e0001a05 NC |
5816 | return reloc; |
5817 | } | |
5818 | ||
7fa3d080 BW |
5819 | \f |
5820 | /* Checks for resource conflicts between instructions. */ | |
5821 | ||
5822 | /* The func unit stuff could be implemented as bit-vectors rather | |
5823 | than the iterative approach here. If it ends up being too | |
5824 | slow, we will switch it. */ | |
5825 | ||
5826 | resource_table * | |
5827 | new_resource_table (void *data, | |
5828 | int cycles, | |
5829 | int nu, | |
5830 | unit_num_copies_func uncf, | |
5831 | opcode_num_units_func onuf, | |
5832 | opcode_funcUnit_use_unit_func ouuf, | |
5833 | opcode_funcUnit_use_stage_func ousf) | |
5834 | { | |
5835 | int i; | |
5836 | resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); | |
5837 | rt->data = data; | |
5838 | rt->cycles = cycles; | |
5839 | rt->allocated_cycles = cycles; | |
5840 | rt->num_units = nu; | |
5841 | rt->unit_num_copies = uncf; | |
5842 | rt->opcode_num_units = onuf; | |
5843 | rt->opcode_unit_use = ouuf; | |
5844 | rt->opcode_unit_stage = ousf; | |
5845 | ||
5846 | rt->units = (char **) xcalloc (cycles, sizeof (char *)); | |
5847 | for (i = 0; i < cycles; i++) | |
5848 | rt->units[i] = (char *) xcalloc (nu, sizeof (char)); | |
5849 | ||
5850 | return rt; | |
5851 | } | |
5852 | ||
5853 | ||
5854 | void | |
5855 | clear_resource_table (resource_table *rt) | |
5856 | { | |
5857 | int i, j; | |
5858 | for (i = 0; i < rt->allocated_cycles; i++) | |
5859 | for (j = 0; j < rt->num_units; j++) | |
5860 | rt->units[i][j] = 0; | |
5861 | } | |
5862 | ||
5863 | ||
5864 | /* We never shrink it, just fake it into thinking so. */ | |
5865 | ||
5866 | void | |
5867 | resize_resource_table (resource_table *rt, int cycles) | |
5868 | { | |
5869 | int i, old_cycles; | |
5870 | ||
5871 | rt->cycles = cycles; | |
5872 | if (cycles <= rt->allocated_cycles) | |
5873 | return; | |
5874 | ||
5875 | old_cycles = rt->allocated_cycles; | |
5876 | rt->allocated_cycles = cycles; | |
5877 | ||
5878 | rt->units = xrealloc (rt->units, sizeof (char *) * rt->allocated_cycles); | |
5879 | for (i = 0; i < old_cycles; i++) | |
5880 | rt->units[i] = xrealloc (rt->units[i], sizeof (char) * rt->num_units); | |
5881 | for (i = old_cycles; i < cycles; i++) | |
5882 | rt->units[i] = xcalloc (rt->num_units, sizeof (char)); | |
5883 | } | |
5884 | ||
5885 | ||
5886 | bfd_boolean | |
5887 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) | |
5888 | { | |
5889 | int i; | |
5890 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5891 | ||
5892 | for (i = 0; i < uses; i++) | |
5893 | { | |
5894 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5895 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
5896 | int copies_in_use = rt->units[stage + cycle][unit]; | |
5897 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
5898 | if (copies_in_use >= copies) | |
5899 | return FALSE; | |
5900 | } | |
5901 | return TRUE; | |
5902 | } | |
5903 | ||
5904 | ||
5905 | void | |
5906 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) | |
5907 | { | |
5908 | int i; | |
5909 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5910 | ||
5911 | for (i = 0; i < uses; i++) | |
5912 | { | |
5913 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5914 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
5915 | /* Note that this allows resources to be oversubscribed. That's | |
5916 | essential to the way the optional scheduler works. | |
5917 | resources_available reports when a resource is over-subscribed, | |
5918 | so it's easy to tell. */ | |
5919 | rt->units[stage + cycle][unit]++; | |
5920 | } | |
5921 | } | |
5922 | ||
5923 | ||
5924 | void | |
5925 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) | |
5926 | { | |
5927 | int i; | |
5928 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5929 | ||
5930 | for (i = 0; i < uses; i++) | |
5931 | { | |
5932 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5933 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
5934 | rt->units[stage + cycle][unit]--; | |
5935 | assert (rt->units[stage + cycle][unit] >= 0); | |
5936 | } | |
5937 | } | |
5938 | ||
5939 | ||
5940 | /* Wrapper functions make parameterized resource reservation | |
5941 | more convenient. */ | |
5942 | ||
5943 | int | |
5944 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) | |
5945 | { | |
5946 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
5947 | return use->unit; | |
5948 | } | |
5949 | ||
5950 | ||
5951 | int | |
5952 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) | |
5953 | { | |
5954 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
5955 | return use->stage; | |
5956 | } | |
5957 | ||
5958 | ||
5959 | /* Note that this function does not check issue constraints, but | |
5960 | solely whether the hardware is available to execute the given | |
5961 | instructions together. It also doesn't check if the tinsns | |
5962 | write the same state, or access the same tieports. That is | |
a1ace8d8 | 5963 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
5964 | |
5965 | static bfd_boolean | |
5966 | resources_conflict (vliw_insn *vinsn) | |
5967 | { | |
5968 | int i; | |
5969 | static resource_table *rt = NULL; | |
5970 | ||
5971 | /* This is the most common case by far. Optimize it. */ | |
5972 | if (vinsn->num_slots == 1) | |
5973 | return FALSE; | |
43cd72b9 | 5974 | |
7fa3d080 BW |
5975 | if (rt == NULL) |
5976 | { | |
5977 | xtensa_isa isa = xtensa_default_isa; | |
5978 | rt = new_resource_table | |
5979 | (isa, xtensa_isa_num_pipe_stages (isa), | |
5980 | xtensa_isa_num_funcUnits (isa), | |
5981 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
5982 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
5983 | opcode_funcUnit_use_unit, | |
5984 | opcode_funcUnit_use_stage); | |
5985 | } | |
43cd72b9 | 5986 | |
7fa3d080 | 5987 | clear_resource_table (rt); |
43cd72b9 | 5988 | |
7fa3d080 BW |
5989 | for (i = 0; i < vinsn->num_slots; i++) |
5990 | { | |
5991 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
5992 | return TRUE; | |
5993 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
5994 | } | |
e0001a05 | 5995 | |
7fa3d080 BW |
5996 | return FALSE; |
5997 | } | |
e0001a05 | 5998 | |
7fa3d080 BW |
5999 | \f |
6000 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 6001 | |
7fa3d080 BW |
6002 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
6003 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
6004 | static void bundle_single_op (TInsn *); | |
6005 | static void xg_assemble_vliw_tokens (vliw_insn *); | |
e0001a05 NC |
6006 | |
6007 | ||
43cd72b9 BW |
6008 | /* We have reached the end of a bundle; emit into the frag. */ |
6009 | ||
e0001a05 | 6010 | static void |
7fa3d080 | 6011 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 6012 | { |
43cd72b9 BW |
6013 | IStack slotstack; |
6014 | int i; | |
6015 | char *file_name; | |
d77b99c9 | 6016 | unsigned line; |
e0001a05 | 6017 | |
43cd72b9 | 6018 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
6019 | { |
6020 | xg_clear_vinsn (vinsn); | |
6021 | return; | |
6022 | } | |
43cd72b9 BW |
6023 | |
6024 | /* First, find a format that works. */ | |
6025 | if (vinsn->format == XTENSA_UNDEFINED) | |
6026 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6027 | ||
6028 | if (vinsn->format == XTENSA_UNDEFINED) | |
6029 | { | |
6030 | as_where (&file_name, &line); | |
6031 | as_bad_where (file_name, line, | |
6032 | _("couldn't find a valid instruction format")); | |
6033 | fprintf (stderr, _(" ops were: ")); | |
6034 | for (i = 0; i < vinsn->num_slots; i++) | |
6035 | fprintf (stderr, _(" %s;"), | |
6036 | xtensa_opcode_name (xtensa_default_isa, | |
6037 | vinsn->slots[i].opcode)); | |
6038 | fprintf (stderr, _("\n")); | |
6039 | xg_clear_vinsn (vinsn); | |
6040 | return; | |
6041 | } | |
6042 | ||
6043 | if (vinsn->num_slots | |
6044 | != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) | |
e0001a05 | 6045 | { |
43cd72b9 BW |
6046 | as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), |
6047 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
6048 | xtensa_format_num_slots (xtensa_default_isa, vinsn->format), | |
6049 | vinsn->num_slots); | |
6050 | xg_clear_vinsn (vinsn); | |
6051 | return; | |
6052 | } | |
e0001a05 | 6053 | |
43cd72b9 BW |
6054 | if (resources_conflict (vinsn)) |
6055 | { | |
6056 | as_where (&file_name, &line); | |
6057 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6058 | fprintf (stderr, " ops were: "); | |
6059 | for (i = 0; i < vinsn->num_slots; i++) | |
6060 | fprintf (stderr, " %s;", | |
6061 | xtensa_opcode_name (xtensa_default_isa, | |
6062 | vinsn->slots[i].opcode)); | |
6063 | fprintf (stderr, "\n"); | |
6064 | xg_clear_vinsn (vinsn); | |
6065 | return; | |
6066 | } | |
6067 | ||
6068 | for (i = 0; i < vinsn->num_slots; i++) | |
6069 | { | |
6070 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6071 | { |
43cd72b9 BW |
6072 | symbolS *lit_sym = NULL; |
6073 | int j; | |
6074 | bfd_boolean e = FALSE; | |
6075 | bfd_boolean saved_density = density_supported; | |
6076 | ||
6077 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6078 | if (vinsn->num_slots > 1) | |
6079 | density_supported = FALSE; | |
6080 | ||
6081 | istack_init (&slotstack); | |
6082 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6083 | { |
43cd72b9 BW |
6084 | vinsn->slots[i].opcode = |
6085 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6086 | vinsn->format, i); | |
6087 | vinsn->slots[i].ntok = 0; | |
6088 | } | |
e0001a05 | 6089 | |
43cd72b9 BW |
6090 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6091 | { | |
6092 | e = TRUE; | |
6093 | continue; | |
e0001a05 | 6094 | } |
e0001a05 | 6095 | |
43cd72b9 | 6096 | density_supported = saved_density; |
e0001a05 | 6097 | |
43cd72b9 BW |
6098 | if (e) |
6099 | { | |
6100 | xg_clear_vinsn (vinsn); | |
6101 | return; | |
6102 | } | |
e0001a05 | 6103 | |
0fa77c95 | 6104 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6105 | { |
6106 | TInsn *insn = &slotstack.insn[j]; | |
6107 | if (insn->insn_type == ITYPE_LITERAL) | |
6108 | { | |
6109 | assert (lit_sym == NULL); | |
6110 | lit_sym = xg_assemble_literal (insn); | |
6111 | } | |
6112 | else | |
6113 | { | |
0fa77c95 | 6114 | assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6115 | if (lit_sym) |
6116 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6117 | if (j != slotstack.ninsn - 1) |
6118 | emit_single_op (insn); | |
43cd72b9 BW |
6119 | } |
6120 | } | |
6121 | ||
6122 | if (vinsn->num_slots > 1) | |
6123 | { | |
6124 | if (opcode_fits_format_slot | |
6125 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6126 | vinsn->format, i)) | |
6127 | { | |
6128 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6129 | } | |
6130 | else | |
6131 | { | |
6132 | bundle_single_op (&slotstack.insn[slotstack.ninsn - 1]); | |
6133 | if (vinsn->format == XTENSA_UNDEFINED) | |
6134 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6135 | else | |
6136 | vinsn->slots[i].opcode | |
6137 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6138 | vinsn->format, i); | |
6139 | ||
6140 | vinsn->slots[i].ntok = 0; | |
6141 | } | |
6142 | } | |
6143 | else | |
6144 | { | |
6145 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6146 | vinsn->format = XTENSA_UNDEFINED; | |
6147 | } | |
6148 | } | |
6149 | } | |
6150 | ||
6151 | /* Now check resource conflicts on the modified bundle. */ | |
6152 | if (resources_conflict (vinsn)) | |
6153 | { | |
6154 | as_where (&file_name, &line); | |
6155 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6156 | fprintf (stderr, " ops were: "); | |
6157 | for (i = 0; i < vinsn->num_slots; i++) | |
6158 | fprintf (stderr, " %s;", | |
6159 | xtensa_opcode_name (xtensa_default_isa, | |
6160 | vinsn->slots[i].opcode)); | |
6161 | fprintf (stderr, "\n"); | |
6162 | xg_clear_vinsn (vinsn); | |
6163 | return; | |
6164 | } | |
6165 | ||
6166 | /* First, find a format that works. */ | |
6167 | if (vinsn->format == XTENSA_UNDEFINED) | |
6168 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6169 | ||
6170 | xg_assemble_vliw_tokens (vinsn); | |
6171 | ||
6172 | xg_clear_vinsn (vinsn); | |
6173 | } | |
6174 | ||
6175 | ||
6176 | /* Given an vliw instruction, what conflicts are there in register | |
6177 | usage and in writes to states and queues? | |
6178 | ||
6179 | This function does two things: | |
6180 | 1. Reports an error when a vinsn contains illegal combinations | |
6181 | of writes to registers states or queues. | |
6182 | 2. Marks individual tinsns as not relaxable if the combination | |
6183 | contains antidependencies. | |
6184 | ||
6185 | Job 2 handles things like swap semantics in instructions that need | |
6186 | to be relaxed. For example, | |
6187 | ||
6188 | addi a0, a1, 100000 | |
6189 | ||
6190 | normally would be relaxed to | |
6191 | ||
6192 | l32r a0, some_label | |
6193 | add a0, a1, a0 | |
6194 | ||
6195 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6196 | ||
6197 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6198 | ||
6199 | then we can't relax it into | |
6200 | ||
6201 | l32r a0, some_label | |
6202 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6203 | ||
6204 | because the value of a0 is trashed before the second add can read it. */ | |
6205 | ||
7fa3d080 BW |
6206 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6207 | ||
43cd72b9 | 6208 | static bfd_boolean |
7fa3d080 | 6209 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6210 | { |
6211 | int i, j; | |
6212 | int branches = 0; | |
6213 | xtensa_isa isa = xtensa_default_isa; | |
6214 | ||
6215 | assert (!past_xtensa_end); | |
6216 | ||
6217 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6218 | { | |
6219 | TInsn *op1 = &vinsn->slots[i]; | |
6220 | if (op1->is_specific_opcode) | |
6221 | op1->keep_wide = TRUE; | |
6222 | else | |
6223 | op1->keep_wide = FALSE; | |
6224 | } | |
6225 | ||
6226 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6227 | { | |
6228 | TInsn *op1 = &vinsn->slots[i]; | |
6229 | ||
6230 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6231 | branches++; | |
6232 | ||
6233 | for (j = 0; j < vinsn->num_slots; j++) | |
6234 | { | |
6235 | if (i != j) | |
6236 | { | |
6237 | TInsn *op2 = &vinsn->slots[j]; | |
6238 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6239 | switch (conflict_type) | |
6240 | { | |
6241 | case 'c': | |
6242 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6243 | xtensa_opcode_name (isa, op1->opcode), i, | |
6244 | xtensa_opcode_name (isa, op2->opcode), j); | |
6245 | return TRUE; | |
6246 | case 'd': | |
6247 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6248 | xtensa_opcode_name (isa, op1->opcode), i, | |
6249 | xtensa_opcode_name (isa, op2->opcode), j); | |
6250 | return TRUE; | |
6251 | case 'e': | |
6252 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"), | |
6253 | xtensa_opcode_name (isa, op1->opcode), i, | |
6254 | xtensa_opcode_name (isa, op2->opcode), j); | |
6255 | return TRUE; | |
6256 | case 'f': | |
6257 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"), | |
6258 | xtensa_opcode_name (isa, op1->opcode), i, | |
6259 | xtensa_opcode_name (isa, op2->opcode), j); | |
6260 | return TRUE; | |
6261 | default: | |
6262 | /* Everything is OK. */ | |
6263 | break; | |
6264 | } | |
6265 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6266 | || conflict_type == 'a'); | |
6267 | } | |
6268 | } | |
6269 | } | |
6270 | ||
6271 | if (branches > 1) | |
6272 | { | |
6273 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6274 | return TRUE; | |
6275 | } | |
6276 | ||
6277 | return FALSE; | |
6278 | } | |
6279 | ||
6280 | ||
a1ace8d8 | 6281 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6282 | Cases found are: |
6283 | ||
6284 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6285 | case B: no relationship between what is read and written (both could | |
6286 | read the same reg though) | |
6287 | case C: t1 writes a register t2 writes (a register conflict within a | |
6288 | bundle) | |
6289 | case D: t1 writes a state that t2 also writes | |
6290 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6291 | case F: two volatile queue accesses |
43cd72b9 BW |
6292 | */ |
6293 | ||
6294 | static char | |
7fa3d080 | 6295 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6296 | { |
6297 | xtensa_isa isa = xtensa_default_isa; | |
6298 | xtensa_regfile t1_regfile, t2_regfile; | |
6299 | int t1_reg, t2_reg; | |
6300 | int t1_base_reg, t1_last_reg; | |
6301 | int t2_base_reg, t2_last_reg; | |
6302 | char t1_inout, t2_inout; | |
6303 | int i, j; | |
6304 | char conflict = 'b'; | |
6305 | int t1_states; | |
6306 | int t2_states; | |
6307 | int t1_interfaces; | |
6308 | int t2_interfaces; | |
6309 | bfd_boolean t1_volatile = FALSE; | |
6310 | bfd_boolean t2_volatile = FALSE; | |
6311 | ||
6312 | /* Check registers. */ | |
6313 | for (j = 0; j < t2->ntok; j++) | |
6314 | { | |
6315 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6316 | continue; | |
6317 | ||
6318 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6319 | t2_base_reg = t2->tok[j].X_add_number; | |
6320 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6321 | ||
6322 | for (i = 0; i < t1->ntok; i++) | |
6323 | { | |
6324 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6325 | continue; | |
6326 | ||
6327 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6328 | ||
6329 | if (t1_regfile != t2_regfile) | |
6330 | continue; | |
6331 | ||
6332 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6333 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6334 | ||
6335 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6336 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6337 | { | |
6338 | if (t1_inout == 'm' || t1_inout == 'o' | |
6339 | || t2_inout == 'm' || t2_inout == 'o') | |
6340 | { | |
6341 | conflict = 'a'; | |
6342 | continue; | |
6343 | } | |
6344 | } | |
6345 | ||
6346 | t1_base_reg = t1->tok[i].X_add_number; | |
6347 | t1_last_reg = (t1_base_reg | |
6348 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6349 | ||
6350 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6351 | { | |
6352 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6353 | { | |
6354 | if (t1_reg != t2_reg) | |
6355 | continue; | |
6356 | ||
6357 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6358 | { |
6359 | conflict = 'a'; | |
6360 | continue; | |
6361 | } | |
43cd72b9 | 6362 | |
7fa3d080 BW |
6363 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6364 | { | |
6365 | conflict = 'a'; | |
6366 | continue; | |
6367 | } | |
43cd72b9 | 6368 | |
7fa3d080 BW |
6369 | if (t1_inout != 'i' && t2_inout != 'i') |
6370 | return 'c'; | |
6371 | } | |
6372 | } | |
6373 | } | |
6374 | } | |
43cd72b9 | 6375 | |
7fa3d080 BW |
6376 | /* Check states. */ |
6377 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6378 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6379 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6380 | { |
7fa3d080 BW |
6381 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6382 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6383 | for (i = 0; i < t1_states; i++) | |
6384 | { | |
6385 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6386 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
6387 | if (t1_so != t2_so) | |
6388 | continue; | |
43cd72b9 | 6389 | |
7fa3d080 BW |
6390 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6391 | { | |
6392 | conflict = 'a'; | |
6393 | continue; | |
6394 | } | |
6395 | ||
6396 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) | |
6397 | { | |
6398 | conflict = 'a'; | |
6399 | continue; | |
6400 | } | |
6401 | ||
6402 | if (t1_inout != 'i' && t2_inout != 'i') | |
6403 | return 'd'; | |
6404 | } | |
6405 | } | |
43cd72b9 | 6406 | |
7fa3d080 BW |
6407 | /* Check tieports. */ |
6408 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6409 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
6410 | for (j = 0; j < t2_interfaces; j++) | |
43cd72b9 | 6411 | { |
7fa3d080 BW |
6412 | xtensa_interface t2_int |
6413 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6414 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6415 | ||
7fa3d080 | 6416 | t2_inout = xtensa_interface_inout (isa, j); |
a1ace8d8 | 6417 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6418 | t2_volatile = TRUE; |
a1ace8d8 | 6419 | |
7fa3d080 BW |
6420 | for (i = 0; i < t1_interfaces; i++) |
6421 | { | |
6422 | xtensa_interface t1_int | |
6423 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6424 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6425 | |
7fa3d080 | 6426 | t1_inout = xtensa_interface_inout (isa, i); |
a1ace8d8 | 6427 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6428 | t1_volatile = TRUE; |
a1ace8d8 BW |
6429 | |
6430 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6431 | return 'f'; | |
7fa3d080 BW |
6432 | |
6433 | if (t1_int != t2_int) | |
6434 | continue; | |
6435 | ||
6436 | if (t2_inout == 'i' && t1_inout == 'o') | |
6437 | { | |
6438 | conflict = 'a'; | |
6439 | continue; | |
6440 | } | |
6441 | ||
6442 | if (t1_inout == 'i' && t2_inout == 'o') | |
6443 | { | |
6444 | conflict = 'a'; | |
6445 | continue; | |
6446 | } | |
6447 | ||
6448 | if (t1_inout != 'i' && t2_inout != 'i') | |
6449 | return 'e'; | |
6450 | } | |
43cd72b9 | 6451 | } |
7fa3d080 BW |
6452 | |
6453 | return conflict; | |
43cd72b9 BW |
6454 | } |
6455 | ||
6456 | ||
6457 | static xtensa_format | |
7fa3d080 | 6458 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6459 | { |
6460 | /* Right now we assume that the ops within the vinsn are properly | |
6461 | ordered for the slots that the programmer wanted them in. In | |
6462 | other words, we don't rearrange the ops in hopes of finding a | |
6463 | better format. The scheduler handles that. */ | |
6464 | ||
6465 | xtensa_isa isa = xtensa_default_isa; | |
6466 | xtensa_format format; | |
6467 | vliw_insn v_copy = *vinsn; | |
6468 | xtensa_opcode nop_opcode = xtensa_nop_opcode; | |
6469 | ||
6470 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) | |
6471 | { | |
6472 | v_copy = *vinsn; | |
6473 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) | |
6474 | { | |
6475 | int slot; | |
6476 | int fit = 0; | |
6477 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6478 | { | |
6479 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6480 | { | |
6481 | v_copy.slots[slot].opcode = | |
6482 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6483 | v_copy.slots[slot].ntok = 0; | |
6484 | } | |
6485 | ||
6486 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6487 | format, slot)) | |
6488 | fit++; | |
7fa3d080 | 6489 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6490 | { |
7fa3d080 BW |
6491 | TInsn widened; |
6492 | /* Try the widened version. */ | |
6493 | if (!v_copy.slots[slot].keep_wide | |
6494 | && !v_copy.slots[slot].is_specific_opcode | |
6495 | && xg_is_narrow_insn (&v_copy.slots[slot]) | |
6496 | && !xg_expand_narrow (&widened, &v_copy.slots[slot]) | |
6497 | && opcode_fits_format_slot (widened.opcode, | |
6498 | format, slot)) | |
43cd72b9 | 6499 | { |
7fa3d080 | 6500 | /* The xg_is_narrow clause requires some explanation: |
43cd72b9 | 6501 | |
7fa3d080 BW |
6502 | addi can be "widened" to an addmi, which is then |
6503 | expanded to an addmi/addi pair if the immediate | |
6504 | requires it, but here we must have a single widen | |
6505 | only. | |
43cd72b9 | 6506 | |
7fa3d080 BW |
6507 | xg_is_narrow tells us that addi isn't really |
6508 | narrow. The widen_spec_list says that there are | |
6509 | other cases. */ | |
43cd72b9 | 6510 | |
7fa3d080 BW |
6511 | v_copy.slots[slot] = widened; |
6512 | fit++; | |
43cd72b9 BW |
6513 | } |
6514 | } | |
6515 | } | |
6516 | if (fit == v_copy.num_slots) | |
6517 | { | |
6518 | *vinsn = v_copy; | |
6519 | xtensa_format_encode (isa, format, vinsn->insnbuf); | |
6520 | vinsn->format = format; | |
6521 | break; | |
6522 | } | |
6523 | } | |
6524 | } | |
6525 | ||
6526 | if (format == xtensa_isa_num_formats (isa)) | |
6527 | return XTENSA_UNDEFINED; | |
6528 | ||
6529 | return format; | |
6530 | } | |
6531 | ||
6532 | ||
6533 | /* Return the additional space needed in a frag | |
6534 | for possible relaxations of any ops in a VLIW insn. | |
6535 | Also fill out the relaxations that might be required of | |
6536 | each tinsn in the vinsn. */ | |
6537 | ||
6538 | static int | |
7fa3d080 | 6539 | relaxation_requirements (vliw_insn *vinsn) |
43cd72b9 BW |
6540 | { |
6541 | int extra_space = 0; | |
6542 | int slot; | |
6543 | ||
6544 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6545 | { | |
6546 | TInsn *tinsn = &vinsn->slots[slot]; | |
6547 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6548 | { | |
6549 | /* A narrow instruction could be widened later to help | |
6550 | alignment issues. */ | |
6551 | if (xg_is_narrow_insn (tinsn) | |
6552 | && !tinsn->is_specific_opcode | |
6553 | && vinsn->num_slots == 1) | |
6554 | { | |
6555 | /* Difference in bytes between narrow and wide insns... */ | |
6556 | extra_space += 1; | |
6557 | tinsn->subtype = RELAX_NARROW; | |
6558 | tinsn->record_fix = TRUE; | |
6559 | break; | |
6560 | } | |
6561 | else | |
6562 | { | |
6563 | tinsn->record_fix = FALSE; | |
6564 | /* No extra_space needed. */ | |
6565 | } | |
6566 | } | |
6567 | else | |
6568 | { | |
b08b5071 BW |
6569 | if (workaround_b_j_loop_end |
6570 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6571 | && use_transform ()) |
6572 | { | |
6573 | /* Add 2 of these. */ | |
6574 | extra_space += 3; /* for the nop size */ | |
6575 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6576 | } | |
6577 | ||
6578 | /* Need to assemble it with space for the relocation. */ | |
6579 | if (xg_is_relaxable_insn (tinsn, 0) | |
6580 | && !tinsn->is_specific_opcode) | |
6581 | { | |
6582 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6583 | int max_literal_size = | |
6584 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
6585 | ||
6586 | tinsn->literal_space = max_literal_size; | |
6587 | ||
6588 | tinsn->subtype = RELAX_IMMED; | |
6589 | tinsn->record_fix = FALSE; | |
6590 | extra_space += max_size; | |
6591 | } | |
6592 | else | |
6593 | { | |
6594 | tinsn->record_fix = TRUE; | |
6595 | /* No extra space needed. */ | |
6596 | } | |
6597 | } | |
6598 | } | |
6599 | return extra_space; | |
6600 | } | |
6601 | ||
6602 | ||
6603 | static void | |
7fa3d080 | 6604 | bundle_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6605 | { |
6606 | xtensa_isa isa = xtensa_default_isa; | |
6607 | vliw_insn v; | |
6608 | int slot; | |
6609 | ||
6610 | xg_init_vinsn (&v); | |
6611 | v.format = op_placement_table[orig_insn->opcode].narrowest; | |
6612 | assert (v.format != XTENSA_UNDEFINED); | |
6613 | v.num_slots = xtensa_format_num_slots (isa, v.format); | |
6614 | ||
6615 | for (slot = 0; | |
6616 | !opcode_fits_format_slot (orig_insn->opcode, v.format, slot); | |
6617 | slot++) | |
6618 | { | |
6619 | v.slots[slot].opcode = | |
6620 | xtensa_format_slot_nop_opcode (isa, v.format, slot); | |
6621 | v.slots[slot].ntok = 0; | |
6622 | v.slots[slot].insn_type = ITYPE_INSN; | |
6623 | } | |
6624 | ||
6625 | v.slots[slot] = *orig_insn; | |
6626 | slot++; | |
6627 | ||
6628 | for ( ; slot < v.num_slots; slot++) | |
6629 | { | |
6630 | v.slots[slot].opcode = | |
6631 | xtensa_format_slot_nop_opcode (isa, v.format, slot); | |
6632 | v.slots[slot].ntok = 0; | |
6633 | v.slots[slot].insn_type = ITYPE_INSN; | |
6634 | } | |
6635 | ||
6636 | finish_vinsn (&v); | |
6637 | xg_free_vinsn (&v); | |
6638 | } | |
6639 | ||
6640 | ||
6641 | static bfd_boolean | |
7fa3d080 | 6642 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6643 | { |
6644 | int i; | |
6645 | IStack istack; /* put instructions into here */ | |
6646 | symbolS *lit_sym = NULL; | |
6647 | symbolS *label_sym = NULL; | |
6648 | ||
6649 | istack_init (&istack); | |
6650 | ||
6651 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
6652 | Because the scheduling and bundling characteristics of movi and | |
6653 | l32r or const16 are so different, we can do much better if we relax | |
6654 | it prior to scheduling and bundling, rather than after. */ | |
b08b5071 BW |
6655 | if ((orig_insn->opcode == xtensa_movi_opcode |
6656 | || orig_insn->opcode == xtensa_movi_n_opcode) | |
6657 | && !cur_vinsn.inside_bundle | |
43cd72b9 BW |
6658 | && (orig_insn->tok[1].X_op == O_symbol |
6659 | || orig_insn->tok[1].X_op == O_pltrel)) | |
6660 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); | |
6661 | else | |
6662 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6663 | return TRUE; | |
6664 | ||
6665 | for (i = 0; i < istack.ninsn; i++) | |
6666 | { | |
6667 | TInsn *insn = &istack.insn[i]; | |
6668 | switch (insn->insn_type) | |
6669 | { | |
6670 | case ITYPE_LITERAL: | |
6671 | assert (lit_sym == NULL); | |
6672 | lit_sym = xg_assemble_literal (insn); | |
6673 | break; | |
6674 | case ITYPE_LABEL: | |
6675 | { | |
6676 | static int relaxed_sym_idx = 0; | |
6677 | char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); | |
6678 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); | |
6679 | colon (label); | |
6680 | assert (label_sym == NULL); | |
6681 | label_sym = symbol_find_or_make (label); | |
6682 | assert (label_sym); | |
6683 | free (label); | |
6684 | } | |
6685 | break; | |
6686 | case ITYPE_INSN: | |
6687 | if (lit_sym) | |
6688 | xg_resolve_literals (insn, lit_sym); | |
6689 | if (label_sym) | |
6690 | xg_resolve_labels (insn, label_sym); | |
6691 | bundle_single_op (insn); | |
6692 | break; | |
6693 | default: | |
6694 | assert (0); | |
6695 | break; | |
6696 | } | |
6697 | } | |
6698 | return FALSE; | |
6699 | } | |
6700 | ||
6701 | ||
34e41783 BW |
6702 | static int |
6703 | total_frag_text_expansion (fragS *fragP) | |
6704 | { | |
6705 | int slot; | |
6706 | int total_expansion = 0; | |
6707 | ||
6708 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
6709 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; | |
6710 | ||
6711 | return total_expansion; | |
6712 | } | |
6713 | ||
6714 | ||
43cd72b9 BW |
6715 | /* Emit a vliw instruction to the current fragment. */ |
6716 | ||
7fa3d080 BW |
6717 | static void |
6718 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 BW |
6719 | { |
6720 | bfd_boolean finish_frag = FALSE; | |
6721 | bfd_boolean is_jump = FALSE; | |
6722 | bfd_boolean is_branch = FALSE; | |
6723 | xtensa_isa isa = xtensa_default_isa; | |
6724 | int i; | |
6725 | int insn_size; | |
6726 | int extra_space; | |
6727 | char *f = NULL; | |
6728 | int slot; | |
6729 | struct dwarf2_line_info best_loc; | |
6730 | ||
6731 | best_loc.line = INT_MAX; | |
6732 | ||
6733 | if (generating_literals) | |
6734 | { | |
6735 | static int reported = 0; | |
6736 | if (reported < 4) | |
6737 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
6738 | _("cannot assemble into a literal fragment")); | |
6739 | if (reported == 3) | |
6740 | as_bad (_("...")); | |
6741 | reported++; | |
6742 | return; | |
6743 | } | |
6744 | ||
6745 | if (frag_now_fix () != 0 | |
b08b5071 | 6746 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 6747 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
b08b5071 | 6748 | || !use_transform () != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
6749 | || (directive_state[directive_longcalls] |
6750 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
6751 | || (directive_state[directive_absolute_literals] |
6752 | != frag_now->tc_frag_data.use_absolute_literals))) | |
6753 | { | |
6754 | frag_wane (frag_now); | |
6755 | frag_new (0); | |
6756 | xtensa_set_frag_assembly_state (frag_now); | |
6757 | } | |
6758 | ||
6759 | if (workaround_a0_b_retw | |
6760 | && vinsn->num_slots == 1 | |
6761 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
6762 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
6763 | && use_transform ()) | |
6764 | { | |
6765 | has_a0_b_retw = TRUE; | |
6766 | ||
6767 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
6768 | After the first assembly pass we will check all of them and | |
6769 | add a nop if needed. */ | |
6770 | frag_now->tc_frag_data.is_insn = TRUE; | |
6771 | frag_var (rs_machine_dependent, 4, 4, | |
6772 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6773 | frag_now->fr_symbol, | |
6774 | frag_now->fr_offset, | |
6775 | NULL); | |
6776 | xtensa_set_frag_assembly_state (frag_now); | |
6777 | frag_now->tc_frag_data.is_insn = TRUE; | |
6778 | frag_var (rs_machine_dependent, 4, 4, | |
6779 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6780 | frag_now->fr_symbol, | |
6781 | frag_now->fr_offset, | |
6782 | NULL); | |
6783 | xtensa_set_frag_assembly_state (frag_now); | |
6784 | } | |
6785 | ||
6786 | for (i = 0; i < vinsn->num_slots; i++) | |
6787 | { | |
6788 | /* See if the instruction implies an aligned section. */ | |
6789 | if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1) | |
6790 | record_alignment (now_seg, 2); | |
6791 | ||
6792 | /* Also determine the best line number for debug info. */ | |
6793 | best_loc = vinsn->slots[i].loc.line < best_loc.line | |
6794 | ? vinsn->slots[i].loc : best_loc; | |
6795 | } | |
6796 | ||
6797 | /* Special cases for instructions that force an alignment... */ | |
6798 | /* None of these opcodes are bundle-able. */ | |
6799 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
6800 | { | |
d77b99c9 | 6801 | int max_fill; |
43cd72b9 BW |
6802 | |
6803 | xtensa_set_frag_assembly_state (frag_now); | |
6804 | frag_now->tc_frag_data.is_insn = TRUE; | |
6805 | ||
6806 | max_fill = get_text_align_max_fill_size | |
6807 | (get_text_align_power (xtensa_fetch_width), | |
6808 | TRUE, frag_now->tc_frag_data.is_no_density); | |
6809 | ||
6810 | if (use_transform ()) | |
6811 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
6812 | RELAX_ALIGN_NEXT_OPCODE, | |
6813 | frag_now->fr_symbol, | |
6814 | frag_now->fr_offset, | |
6815 | NULL); | |
6816 | else | |
6817 | frag_var (rs_machine_dependent, 0, 0, | |
6818 | RELAX_CHECK_ALIGN_NEXT_OPCODE, 0, 0, NULL); | |
6819 | xtensa_set_frag_assembly_state (frag_now); | |
6820 | ||
6821 | xtensa_move_labels (frag_now, 0, FALSE); | |
6822 | } | |
6823 | ||
b08b5071 | 6824 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
6825 | && !vinsn->slots[0].is_specific_opcode) |
6826 | { | |
6827 | xtensa_mark_literal_pool_location (); | |
6828 | xtensa_move_labels (frag_now, 0, TRUE); | |
6829 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); | |
6830 | } | |
6831 | ||
6832 | if (vinsn->num_slots == 1) | |
6833 | { | |
6834 | if (workaround_a0_b_retw && use_transform ()) | |
6835 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
6836 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
6837 | ||
6838 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
6839 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
6840 | } | |
6841 | else | |
6842 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
6843 | ||
6844 | insn_size = xtensa_format_length (isa, vinsn->format); | |
6845 | ||
6846 | extra_space = relaxation_requirements (vinsn); | |
6847 | ||
6848 | /* vinsn_to_insnbuf will produce the error. */ | |
6849 | if (vinsn->format != XTENSA_UNDEFINED) | |
6850 | { | |
d77b99c9 | 6851 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
6852 | xtensa_set_frag_assembly_state (frag_now); |
6853 | frag_now->tc_frag_data.is_insn = TRUE; | |
6854 | } | |
6855 | ||
6856 | vinsn_to_insnbuf (vinsn, f, frag_now, TRUE); | |
6857 | if (vinsn->format == XTENSA_UNDEFINED) | |
6858 | return; | |
6859 | ||
d77b99c9 | 6860 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
6861 | |
6862 | xtensa_dwarf2_emit_insn (insn_size - extra_space, &best_loc); | |
6863 | ||
6864 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6865 | { | |
6866 | TInsn *tinsn = &vinsn->slots[slot]; | |
6867 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; | |
7c834684 BW |
6868 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
6869 | frag_now->tc_frag_data.slot_sub_symbols[slot] = tinsn->sub_symbol; | |
6870 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; | |
43cd72b9 BW |
6871 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
6872 | if (tinsn->literal_space != 0) | |
6873 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
6874 | ||
6875 | if (tinsn->subtype == RELAX_NARROW) | |
6876 | assert (vinsn->num_slots == 1); | |
6877 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) | |
6878 | is_jump = TRUE; | |
6879 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
6880 | is_branch = TRUE; | |
6881 | ||
6882 | if (tinsn->subtype || tinsn->symbol || tinsn->record_fix | |
6883 | || tinsn->offset || tinsn->literal_frag || is_jump || is_branch) | |
6884 | finish_frag = TRUE; | |
6885 | } | |
6886 | ||
6887 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 6888 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
6889 | |
6890 | if (finish_frag) | |
6891 | { | |
6892 | frag_variant (rs_machine_dependent, | |
6893 | extra_space, extra_space, RELAX_SLOTS, | |
6894 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
6895 | xtensa_set_frag_assembly_state (frag_now); | |
6896 | } | |
6897 | ||
6898 | /* Special cases for loops: | |
6899 | close_loop_end should be inserted AFTER short_loop. | |
6900 | Make sure that CLOSE loops are processed BEFORE short_loops | |
6901 | when converting them. */ | |
6902 | ||
6903 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
6904 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) | |
6905 | && !vinsn->slots[0].is_specific_opcode) | |
6906 | { | |
6907 | if (workaround_short_loop && use_transform ()) | |
6908 | { | |
6909 | maybe_has_short_loop = TRUE; | |
6910 | frag_now->tc_frag_data.is_insn = TRUE; | |
6911 | frag_var (rs_machine_dependent, 4, 4, | |
6912 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6913 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6914 | frag_now->tc_frag_data.is_insn = TRUE; | |
6915 | frag_var (rs_machine_dependent, 4, 4, | |
6916 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6917 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6918 | } | |
6919 | ||
6920 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
6921 | loop at least 12 bytes away from another loop's end. */ | |
6922 | if (workaround_close_loop_end && use_transform ()) | |
6923 | { | |
6924 | maybe_has_close_loop_end = TRUE; | |
6925 | frag_now->tc_frag_data.is_insn = TRUE; | |
6926 | frag_var (rs_machine_dependent, 12, 12, | |
6927 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
6928 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6929 | } | |
6930 | } | |
6931 | ||
6932 | if (use_transform ()) | |
6933 | { | |
6934 | if (is_jump) | |
6935 | { | |
6936 | assert (finish_frag); | |
6937 | frag_var (rs_machine_dependent, | |
6938 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6939 | RELAX_UNREACHABLE, | |
6940 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6941 | xtensa_set_frag_assembly_state (frag_now); | |
6942 | } | |
7b1cc377 | 6943 | else if (is_branch && do_align_targets ()) |
43cd72b9 BW |
6944 | { |
6945 | assert (finish_frag); | |
6946 | frag_var (rs_machine_dependent, | |
6947 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6948 | RELAX_MAYBE_UNREACHABLE, | |
6949 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6950 | xtensa_set_frag_assembly_state (frag_now); | |
6951 | frag_var (rs_machine_dependent, | |
6952 | 0, 0, | |
6953 | RELAX_MAYBE_DESIRE_ALIGN, | |
6954 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6955 | xtensa_set_frag_assembly_state (frag_now); | |
6956 | } | |
6957 | } | |
6958 | ||
6959 | /* Now, if the original opcode was a call... */ | |
6960 | if (do_align_targets () | |
6961 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
6962 | { | |
b08b5071 | 6963 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
6964 | frag_now->tc_frag_data.is_insn = TRUE; |
6965 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
6966 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6967 | xtensa_set_frag_assembly_state (frag_now); | |
6968 | } | |
6969 | ||
6970 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
6971 | { | |
6972 | frag_wane (frag_now); | |
6973 | frag_new (0); | |
6974 | xtensa_set_frag_assembly_state (frag_now); | |
6975 | } | |
6976 | } | |
6977 | ||
6978 | \f | |
7fa3d080 BW |
6979 | /* xtensa_end and helper functions. */ |
6980 | ||
6981 | static void xtensa_cleanup_align_frags (void); | |
6982 | static void xtensa_fix_target_frags (void); | |
6983 | static void xtensa_mark_narrow_branches (void); | |
6984 | static void xtensa_mark_zcl_first_insns (void); | |
6985 | static void xtensa_fix_a0_b_retw_frags (void); | |
6986 | static void xtensa_fix_b_j_loop_end_frags (void); | |
6987 | static void xtensa_fix_close_loop_end_frags (void); | |
6988 | static void xtensa_fix_short_loop_frags (void); | |
6989 | static void xtensa_sanity_check (void); | |
6990 | ||
43cd72b9 | 6991 | void |
7fa3d080 | 6992 | xtensa_end (void) |
43cd72b9 BW |
6993 | { |
6994 | directive_balance (); | |
6995 | xtensa_flush_pending_output (); | |
6996 | ||
6997 | past_xtensa_end = TRUE; | |
6998 | ||
6999 | xtensa_move_literals (); | |
7000 | ||
7001 | xtensa_reorder_segments (); | |
7002 | xtensa_cleanup_align_frags (); | |
7003 | xtensa_fix_target_frags (); | |
7004 | if (workaround_a0_b_retw && has_a0_b_retw) | |
7005 | xtensa_fix_a0_b_retw_frags (); | |
7006 | if (workaround_b_j_loop_end) | |
7007 | xtensa_fix_b_j_loop_end_frags (); | |
7008 | ||
7009 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
7010 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
7011 | xtensa_fix_close_loop_end_frags (); | |
7012 | ||
7013 | if (workaround_short_loop && maybe_has_short_loop) | |
7014 | xtensa_fix_short_loop_frags (); | |
7015 | xtensa_mark_narrow_branches (); | |
7016 | xtensa_mark_zcl_first_insns (); | |
7017 | ||
7018 | xtensa_sanity_check (); | |
7019 | } | |
7020 | ||
7021 | ||
7022 | static void | |
7fa3d080 | 7023 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
7024 | { |
7025 | frchainS *frchP; | |
7026 | ||
7027 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7028 | { | |
7029 | fragS *fragP; | |
7030 | /* Walk over all of the fragments in a subsection. */ | |
7031 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7032 | { | |
7033 | if ((fragP->fr_type == rs_align | |
7034 | || fragP->fr_type == rs_align_code | |
7035 | || (fragP->fr_type == rs_machine_dependent | |
7036 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
7037 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
7038 | && fragP->fr_fix == 0) | |
7039 | { | |
7040 | fragS *next = fragP->fr_next; | |
7041 | ||
7042 | while (next | |
7043 | && next->fr_fix == 0 | |
7044 | && next->fr_type == rs_machine_dependent | |
7045 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7046 | { | |
7047 | frag_wane (next); | |
7048 | next = next->fr_next; | |
7049 | } | |
7050 | } | |
7051 | /* If we don't widen branch targets, then they | |
7052 | will be easier to align. */ | |
7053 | if (fragP->tc_frag_data.is_branch_target | |
7054 | && fragP->fr_opcode == fragP->fr_literal | |
7055 | && fragP->fr_type == rs_machine_dependent | |
7056 | && fragP->fr_subtype == RELAX_SLOTS | |
7057 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
7058 | frag_wane (fragP); | |
7059 | if (fragP->fr_type == rs_machine_dependent | |
7060 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
7061 | fragP->tc_frag_data.is_unreachable = TRUE; | |
7062 | } | |
7063 | } | |
7064 | } | |
7065 | ||
7066 | ||
7067 | /* Re-process all of the fragments looking to convert all of the | |
7068 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
7069 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 7070 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 7071 | |
43cd72b9 | 7072 | static void |
7fa3d080 | 7073 | xtensa_fix_target_frags (void) |
e0001a05 NC |
7074 | { |
7075 | frchainS *frchP; | |
7076 | ||
7077 | /* When this routine is called, all of the subsections are still intact | |
7078 | so we walk over subsections instead of sections. */ | |
7079 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7080 | { | |
e0001a05 NC |
7081 | fragS *fragP; |
7082 | ||
7083 | /* Walk over all of the fragments in a subsection. */ | |
7084 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7085 | { | |
7086 | if (fragP->fr_type == rs_machine_dependent | |
7087 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7088 | { | |
7b1cc377 | 7089 | if (next_frag_is_branch_target (fragP)) |
e0001a05 NC |
7090 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; |
7091 | else | |
7092 | frag_wane (fragP); | |
7093 | } | |
e0001a05 NC |
7094 | } |
7095 | } | |
7096 | } | |
7097 | ||
7098 | ||
7fa3d080 BW |
7099 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7100 | ||
43cd72b9 | 7101 | static void |
7fa3d080 | 7102 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
7103 | { |
7104 | frchainS *frchP; | |
7105 | ||
7106 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7107 | { | |
7108 | fragS *fragP; | |
7109 | /* Walk over all of the fragments in a subsection. */ | |
7110 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7111 | { | |
7112 | if (fragP->fr_type == rs_machine_dependent | |
7113 | && fragP->fr_subtype == RELAX_SLOTS | |
7114 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
7115 | { | |
7116 | vliw_insn vinsn; | |
7117 | const expressionS *expr; | |
7118 | symbolS *symbolP; | |
7119 | ||
7120 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
7121 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
7122 | ||
7123 | expr = &vinsn.slots[0].tok[1]; | |
7124 | symbolP = expr->X_add_symbol; | |
7125 | ||
7126 | if (vinsn.num_slots == 1 | |
7127 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
7128 | vinsn.slots[0].opcode) | |
7129 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 | |
7130 | && is_narrow_branch_guaranteed_in_range (fragP, | |
7131 | &vinsn.slots[0])) | |
7132 | { | |
7133 | fragP->fr_subtype = RELAX_SLOTS; | |
7134 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
7135 | } | |
7136 | } | |
7137 | } | |
7138 | } | |
7139 | } | |
7140 | ||
7141 | ||
7142 | /* A branch is typically widened only when its target is out of | |
7143 | range. However, we would like to widen them to align a subsequent | |
7144 | branch target when possible. | |
7145 | ||
7146 | Because the branch relaxation code is so convoluted, the optimal solution | |
7147 | (combining the two cases) is difficult to get right in all circumstances. | |
7148 | We therefore go with an "almost as good" solution, where we only | |
7149 | use for alignment narrow branches that definitely will not expand to a | |
7150 | jump and a branch. These functions find and mark these cases. */ | |
7151 | ||
a67517f4 BW |
7152 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
7153 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
7154 | We start counting beginning with the frag after the 2-byte branch, so the | |
7155 | maximum offset is (4 - 2) + 63 = 65. */ | |
7156 | #define MAX_IMMED6 65 | |
43cd72b9 | 7157 | |
d77b99c9 | 7158 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 7159 | |
43cd72b9 | 7160 | static bfd_boolean |
7fa3d080 | 7161 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 BW |
7162 | { |
7163 | const expressionS *expr = &tinsn->tok[1]; | |
7164 | symbolS *symbolP = expr->X_add_symbol; | |
7165 | fragS *target_frag = symbol_get_frag (symbolP); | |
d77b99c9 | 7166 | offsetT max_distance = expr->X_add_number; |
43cd72b9 BW |
7167 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
7168 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
7169 | return FALSE; | |
7170 | ||
7171 | /* The branch doesn't branch over it's own frag, | |
7172 | but over the subsequent ones. */ | |
7173 | fragP = fragP->fr_next; | |
7174 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
7175 | { | |
7176 | max_distance += unrelaxed_frag_max_size (fragP); | |
7177 | fragP = fragP->fr_next; | |
7178 | } | |
7179 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
7180 | return TRUE; | |
e0001a05 NC |
7181 | return FALSE; |
7182 | } | |
7183 | ||
7184 | ||
43cd72b9 | 7185 | static void |
7fa3d080 | 7186 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
7187 | { |
7188 | frchainS *frchP; | |
7189 | ||
7190 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7191 | { | |
7192 | fragS *fragP; | |
7193 | /* Walk over all of the fragments in a subsection. */ | |
7194 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7195 | { | |
7196 | if (fragP->fr_type == rs_machine_dependent | |
7197 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
7198 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
7199 | { | |
7200 | /* Find the loop frag. */ | |
7201 | fragS *targ_frag = next_non_empty_frag (fragP); | |
7202 | /* Find the first insn frag. */ | |
7203 | targ_frag = next_non_empty_frag (targ_frag); | |
7204 | ||
7205 | /* Of course, sometimes (mostly for toy test cases) a | |
7206 | zero-cost loop instruction is the last in a section. */ | |
7207 | if (targ_frag) | |
7208 | { | |
7209 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
7210 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
7211 | frag_wane (fragP); | |
7212 | } | |
7213 | } | |
7214 | } | |
7215 | } | |
7216 | } | |
7217 | ||
7218 | ||
e0001a05 NC |
7219 | /* Re-process all of the fragments looking to convert all of the |
7220 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
7221 | conditional branch or a retw/retw.n, convert this frag to one that | |
7222 | will generate a NOP. In any case close it off with a .fill 0. */ | |
7223 | ||
7fa3d080 BW |
7224 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
7225 | ||
e0001a05 | 7226 | static void |
7fa3d080 | 7227 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
7228 | { |
7229 | frchainS *frchP; | |
7230 | ||
7231 | /* When this routine is called, all of the subsections are still intact | |
7232 | so we walk over subsections instead of sections. */ | |
7233 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7234 | { | |
7235 | fragS *fragP; | |
7236 | ||
7237 | /* Walk over all of the fragments in a subsection. */ | |
7238 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7239 | { | |
7240 | if (fragP->fr_type == rs_machine_dependent | |
7241 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
7242 | { | |
7243 | if (next_instrs_are_b_retw (fragP)) | |
43cd72b9 | 7244 | { |
b08b5071 | 7245 | if (fragP->tc_frag_data.is_no_transform) |
43cd72b9 BW |
7246 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); |
7247 | else | |
7248 | relax_frag_add_nop (fragP); | |
7249 | } | |
7250 | frag_wane (fragP); | |
e0001a05 NC |
7251 | } |
7252 | } | |
7253 | } | |
7254 | } | |
7255 | ||
7256 | ||
7fa3d080 BW |
7257 | static bfd_boolean |
7258 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
7259 | { |
7260 | xtensa_opcode opcode; | |
43cd72b9 | 7261 | xtensa_format fmt; |
e0001a05 NC |
7262 | const fragS *next_fragP = next_non_empty_frag (fragP); |
7263 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 7264 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
7265 | xtensa_isa isa = xtensa_default_isa; |
7266 | int offset = 0; | |
43cd72b9 BW |
7267 | int slot; |
7268 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
7269 | |
7270 | if (!insnbuf) | |
43cd72b9 BW |
7271 | { |
7272 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7273 | slotbuf = xtensa_insnbuf_alloc (isa); | |
7274 | } | |
e0001a05 NC |
7275 | |
7276 | if (next_fragP == NULL) | |
7277 | return FALSE; | |
7278 | ||
7279 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
7280 | xtensa_insnbuf_from_chars |
7281 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7282 | fmt = xtensa_format_decode (isa, insnbuf); |
7283 | if (fmt == XTENSA_UNDEFINED) | |
7284 | return FALSE; | |
7285 | ||
7286 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
7287 | { | |
7288 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
7289 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
7290 | ||
7291 | branch_seen = (branch_seen | |
7292 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
7293 | } | |
e0001a05 | 7294 | |
43cd72b9 | 7295 | if (!branch_seen) |
e0001a05 NC |
7296 | return FALSE; |
7297 | ||
43cd72b9 | 7298 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7299 | if (offset == next_fragP->fr_fix) |
7300 | { | |
7301 | next_fragP = next_non_empty_frag (next_fragP); | |
7302 | offset = 0; | |
7303 | } | |
43cd72b9 | 7304 | |
e0001a05 NC |
7305 | if (next_fragP == NULL) |
7306 | return FALSE; | |
7307 | ||
7308 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
7309 | xtensa_insnbuf_from_chars |
7310 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7311 | fmt = xtensa_format_decode (isa, insnbuf); |
7312 | ||
7313 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
7314 | have no problems. */ | |
7315 | if (fmt == XTENSA_UNDEFINED | |
7316 | || xtensa_format_num_slots (isa, fmt) != 1) | |
7317 | return FALSE; | |
7318 | ||
7319 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
7320 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 7321 | |
b08b5071 | 7322 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 7323 | return TRUE; |
43cd72b9 | 7324 | |
e0001a05 NC |
7325 | return FALSE; |
7326 | } | |
7327 | ||
7328 | ||
7329 | /* Re-process all of the fragments looking to convert all of the | |
7330 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
7331 | loop end label, convert this frag to one that will generate a NOP. | |
7332 | In any case close it off with a .fill 0. */ | |
7333 | ||
7fa3d080 BW |
7334 | static bfd_boolean next_instr_is_loop_end (fragS *); |
7335 | ||
e0001a05 | 7336 | static void |
7fa3d080 | 7337 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
7338 | { |
7339 | frchainS *frchP; | |
7340 | ||
7341 | /* When this routine is called, all of the subsections are still intact | |
7342 | so we walk over subsections instead of sections. */ | |
7343 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7344 | { | |
7345 | fragS *fragP; | |
7346 | ||
7347 | /* Walk over all of the fragments in a subsection. */ | |
7348 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7349 | { | |
7350 | if (fragP->fr_type == rs_machine_dependent | |
7351 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
7352 | { | |
7353 | if (next_instr_is_loop_end (fragP)) | |
43cd72b9 | 7354 | { |
b08b5071 | 7355 | if (fragP->tc_frag_data.is_no_transform) |
43cd72b9 BW |
7356 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); |
7357 | else | |
7358 | relax_frag_add_nop (fragP); | |
7359 | } | |
7360 | frag_wane (fragP); | |
e0001a05 NC |
7361 | } |
7362 | } | |
7363 | } | |
7364 | } | |
7365 | ||
7366 | ||
7fa3d080 BW |
7367 | static bfd_boolean |
7368 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
7369 | { |
7370 | const fragS *next_fragP; | |
7371 | ||
7372 | if (next_frag_is_loop_target (fragP)) | |
7373 | return FALSE; | |
7374 | ||
7375 | next_fragP = next_non_empty_frag (fragP); | |
7376 | if (next_fragP == NULL) | |
7377 | return FALSE; | |
7378 | ||
7379 | if (!next_frag_is_loop_target (next_fragP)) | |
7380 | return FALSE; | |
7381 | ||
7382 | /* If the size is >= 3 then there is more than one instruction here. | |
7383 | The hardware bug will not fire. */ | |
7384 | if (next_fragP->fr_fix > 3) | |
7385 | return FALSE; | |
7386 | ||
7387 | return TRUE; | |
7388 | } | |
7389 | ||
7390 | ||
7391 | /* Re-process all of the fragments looking to convert all of the | |
7392 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
7393 | not MY loop's loop end within 12 bytes, add enough nops here to | |
7394 | make it at least 12 bytes away. In any case close it off with a | |
7395 | .fill 0. */ | |
7396 | ||
d77b99c9 BW |
7397 | static offsetT min_bytes_to_other_loop_end |
7398 | (fragS *, fragS *, offsetT, offsetT); | |
7fa3d080 | 7399 | |
e0001a05 | 7400 | static void |
7fa3d080 | 7401 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
7402 | { |
7403 | frchainS *frchP; | |
7404 | ||
7405 | /* When this routine is called, all of the subsections are still intact | |
7406 | so we walk over subsections instead of sections. */ | |
7407 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7408 | { | |
7409 | fragS *fragP; | |
7410 | ||
7411 | fragS *current_target = NULL; | |
7412 | offsetT current_offset = 0; | |
7413 | ||
7414 | /* Walk over all of the fragments in a subsection. */ | |
7415 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7416 | { | |
7417 | if (fragP->fr_type == rs_machine_dependent | |
43cd72b9 BW |
7418 | && ((fragP->fr_subtype == RELAX_IMMED) |
7419 | || ((fragP->fr_subtype == RELAX_SLOTS) | |
7420 | && (fragP->tc_frag_data.slot_subtypes[0] | |
7421 | == RELAX_IMMED)))) | |
e0001a05 NC |
7422 | { |
7423 | /* Read it. If the instruction is a loop, get the target. */ | |
43cd72b9 BW |
7424 | TInsn t_insn; |
7425 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
7426 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
7427 | t_insn.opcode) == 1) | |
e0001a05 | 7428 | { |
e0001a05 | 7429 | /* Get the current fragment target. */ |
43cd72b9 | 7430 | if (fragP->tc_frag_data.slot_symbols[0]) |
e0001a05 | 7431 | { |
43cd72b9 BW |
7432 | symbolS *sym = fragP->tc_frag_data.slot_symbols[0]; |
7433 | current_target = symbol_get_frag (sym); | |
e0001a05 NC |
7434 | current_offset = fragP->fr_offset; |
7435 | } | |
7436 | } | |
7437 | } | |
7438 | ||
7439 | if (current_target | |
7440 | && fragP->fr_type == rs_machine_dependent | |
7441 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
7442 | { | |
d77b99c9 BW |
7443 | offsetT min_bytes; |
7444 | int bytes_added = 0; | |
e0001a05 NC |
7445 | |
7446 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
7447 | /* Max out at 12. */ | |
7448 | min_bytes = min_bytes_to_other_loop_end | |
7449 | (fragP->fr_next, current_target, current_offset, | |
7450 | REQUIRED_LOOP_DIVIDING_BYTES); | |
7451 | ||
7452 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
7453 | { | |
b08b5071 | 7454 | if (fragP->tc_frag_data.is_no_transform) |
43cd72b9 BW |
7455 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); |
7456 | else | |
e0001a05 | 7457 | { |
43cd72b9 BW |
7458 | while (min_bytes + bytes_added |
7459 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
e0001a05 | 7460 | { |
43cd72b9 BW |
7461 | int length = 3; |
7462 | ||
7463 | if (fragP->fr_var < length) | |
7464 | as_fatal (_("fr_var %lu < length %d"), | |
dd49a749 | 7465 | (long) fragP->fr_var, length); |
43cd72b9 BW |
7466 | else |
7467 | { | |
7468 | assemble_nop (length, | |
7469 | fragP->fr_literal + fragP->fr_fix); | |
7470 | fragP->fr_fix += length; | |
7471 | fragP->fr_var -= length; | |
7472 | } | |
7473 | bytes_added += length; | |
e0001a05 | 7474 | } |
e0001a05 NC |
7475 | } |
7476 | } | |
7477 | frag_wane (fragP); | |
7478 | } | |
43cd72b9 BW |
7479 | assert (fragP->fr_type != rs_machine_dependent |
7480 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); | |
e0001a05 NC |
7481 | } |
7482 | } | |
7483 | } | |
7484 | ||
7485 | ||
d77b99c9 | 7486 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 7487 | |
d77b99c9 | 7488 | static offsetT |
7fa3d080 BW |
7489 | min_bytes_to_other_loop_end (fragS *fragP, |
7490 | fragS *current_target, | |
7491 | offsetT current_offset, | |
d77b99c9 | 7492 | offsetT max_size) |
e0001a05 | 7493 | { |
d77b99c9 | 7494 | offsetT offset = 0; |
e0001a05 NC |
7495 | fragS *current_fragP; |
7496 | ||
7497 | for (current_fragP = fragP; | |
7498 | current_fragP; | |
7499 | current_fragP = current_fragP->fr_next) | |
7500 | { | |
7501 | if (current_fragP->tc_frag_data.is_loop_target | |
7502 | && current_fragP != current_target) | |
7503 | return offset + current_offset; | |
7504 | ||
7505 | offset += unrelaxed_frag_min_size (current_fragP); | |
7506 | ||
7507 | if (offset + current_offset >= max_size) | |
7508 | return max_size; | |
7509 | } | |
7510 | return max_size; | |
7511 | } | |
7512 | ||
7513 | ||
d77b99c9 | 7514 | static offsetT |
7fa3d080 | 7515 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 7516 | { |
d77b99c9 | 7517 | offsetT size = fragP->fr_fix; |
e0001a05 | 7518 | |
d77b99c9 | 7519 | /* Add fill size. */ |
e0001a05 NC |
7520 | if (fragP->fr_type == rs_fill) |
7521 | size += fragP->fr_offset; | |
7522 | ||
7523 | return size; | |
7524 | } | |
7525 | ||
7526 | ||
d77b99c9 | 7527 | static offsetT |
7fa3d080 | 7528 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 7529 | { |
d77b99c9 | 7530 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
7531 | switch (fragP->fr_type) |
7532 | { | |
7533 | case 0: | |
7534 | /* Empty frags created by the obstack allocation scheme | |
7535 | end up with type 0. */ | |
7536 | break; | |
7537 | case rs_fill: | |
7538 | case rs_org: | |
7539 | case rs_space: | |
7540 | size += fragP->fr_offset; | |
7541 | break; | |
7542 | case rs_align: | |
7543 | case rs_align_code: | |
7544 | case rs_align_test: | |
7545 | case rs_leb128: | |
7546 | case rs_cfa: | |
7547 | case rs_dwarf2dbg: | |
7548 | /* No further adjustments needed. */ | |
7549 | break; | |
7550 | case rs_machine_dependent: | |
7551 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
7552 | size += fragP->fr_var; | |
7553 | break; | |
7554 | default: | |
7555 | /* We had darn well better know how big it is. */ | |
7556 | assert (0); | |
7557 | break; | |
7558 | } | |
7559 | ||
7560 | return size; | |
7561 | } | |
7562 | ||
7563 | ||
e0001a05 NC |
7564 | /* Re-process all of the fragments looking to convert all |
7565 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
7566 | ||
7567 | A) | |
7568 | 1) the instruction size count to the loop end label | |
7569 | is too short (<= 2 instructions), | |
7570 | 2) loop has a jump or branch in it | |
7571 | ||
7572 | or B) | |
43cd72b9 | 7573 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
7574 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
7575 | 3) the instruction size count to the loop end label is too short | |
7576 | (<= 2 instructions) | |
7577 | then convert this frag (and maybe the next one) to generate a NOP. | |
7578 | In any case close it off with a .fill 0. */ | |
7579 | ||
d77b99c9 | 7580 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
7581 | static bfd_boolean branch_before_loop_end (fragS *); |
7582 | ||
e0001a05 | 7583 | static void |
7fa3d080 | 7584 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
7585 | { |
7586 | frchainS *frchP; | |
7587 | ||
7588 | /* When this routine is called, all of the subsections are still intact | |
7589 | so we walk over subsections instead of sections. */ | |
7590 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7591 | { | |
7592 | fragS *fragP; | |
7593 | fragS *current_target = NULL; | |
7594 | offsetT current_offset = 0; | |
7595 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; | |
7596 | ||
7597 | /* Walk over all of the fragments in a subsection. */ | |
7598 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7599 | { | |
43cd72b9 | 7600 | /* Check on the current loop. */ |
e0001a05 | 7601 | if (fragP->fr_type == rs_machine_dependent |
43cd72b9 BW |
7602 | && ((fragP->fr_subtype == RELAX_IMMED) |
7603 | || ((fragP->fr_subtype == RELAX_SLOTS) | |
7604 | && (fragP->tc_frag_data.slot_subtypes[0] | |
7605 | == RELAX_IMMED)))) | |
e0001a05 | 7606 | { |
43cd72b9 BW |
7607 | TInsn t_insn; |
7608 | ||
e0001a05 | 7609 | /* Read it. If the instruction is a loop, get the target. */ |
43cd72b9 BW |
7610 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); |
7611 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
7612 | t_insn.opcode) == 1) | |
e0001a05 | 7613 | { |
e0001a05 | 7614 | /* Get the current fragment target. */ |
43cd72b9 | 7615 | if (fragP->tc_frag_data.slot_symbols[0]) |
e0001a05 | 7616 | { |
43cd72b9 BW |
7617 | symbolS *sym = fragP->tc_frag_data.slot_symbols[0]; |
7618 | current_target = symbol_get_frag (sym); | |
e0001a05 | 7619 | current_offset = fragP->fr_offset; |
43cd72b9 | 7620 | current_opcode = t_insn.opcode; |
e0001a05 NC |
7621 | } |
7622 | } | |
7623 | } | |
7624 | ||
7625 | if (fragP->fr_type == rs_machine_dependent | |
7626 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7627 | { | |
d77b99c9 | 7628 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 |
e0001a05 | 7629 | && (branch_before_loop_end (fragP->fr_next) |
43cd72b9 | 7630 | || (workaround_all_short_loops |
e0001a05 | 7631 | && current_opcode != XTENSA_UNDEFINED |
b08b5071 | 7632 | && current_opcode != xtensa_loop_opcode))) |
43cd72b9 | 7633 | { |
b08b5071 | 7634 | if (fragP->tc_frag_data.is_no_transform) |
43cd72b9 BW |
7635 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); |
7636 | else | |
7637 | relax_frag_add_nop (fragP); | |
7638 | } | |
7639 | frag_wane (fragP); | |
e0001a05 NC |
7640 | } |
7641 | } | |
7642 | } | |
7643 | } | |
7644 | ||
7645 | ||
d77b99c9 | 7646 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 7647 | |
d77b99c9 | 7648 | static int |
7fa3d080 BW |
7649 | count_insns_to_loop_end (fragS *base_fragP, |
7650 | bfd_boolean count_relax_add, | |
d77b99c9 | 7651 | int max_count) |
e0001a05 NC |
7652 | { |
7653 | fragS *fragP = NULL; | |
d77b99c9 | 7654 | int insn_count = 0; |
e0001a05 NC |
7655 | |
7656 | fragP = base_fragP; | |
7657 | ||
7658 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
7659 | { | |
7660 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
7661 | if (insn_count >= max_count) | |
7662 | return max_count; | |
7663 | ||
7664 | if (count_relax_add) | |
7665 | { | |
7666 | if (fragP->fr_type == rs_machine_dependent | |
7667 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7668 | { | |
7669 | /* In order to add the appropriate number of | |
7670 | NOPs, we count an instruction for downstream | |
7671 | occurrences. */ | |
7672 | insn_count++; | |
7673 | if (insn_count >= max_count) | |
7674 | return max_count; | |
7675 | } | |
7676 | } | |
7677 | } | |
7678 | return insn_count; | |
7679 | } | |
7680 | ||
7681 | ||
d77b99c9 | 7682 | static int |
7fa3d080 | 7683 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 7684 | { |
43cd72b9 BW |
7685 | xtensa_isa isa = xtensa_default_isa; |
7686 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 7687 | int insn_count = 0; |
e0001a05 NC |
7688 | int offset = 0; |
7689 | ||
7690 | if (!fragP->tc_frag_data.is_insn) | |
7691 | return insn_count; | |
7692 | ||
43cd72b9 BW |
7693 | if (!insnbuf) |
7694 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7695 | ||
e0001a05 NC |
7696 | /* Decode the fixed instructions. */ |
7697 | while (offset < fragP->fr_fix) | |
7698 | { | |
43cd72b9 BW |
7699 | xtensa_format fmt; |
7700 | ||
d77b99c9 BW |
7701 | xtensa_insnbuf_from_chars |
7702 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7703 | fmt = xtensa_format_decode (isa, insnbuf); |
7704 | ||
7705 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
7706 | { |
7707 | as_fatal (_("undecodable instruction in instruction frag")); | |
7708 | return insn_count; | |
7709 | } | |
43cd72b9 | 7710 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7711 | insn_count++; |
7712 | } | |
7713 | ||
7714 | return insn_count; | |
7715 | } | |
7716 | ||
7717 | ||
7fa3d080 BW |
7718 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
7719 | ||
43cd72b9 | 7720 | static bfd_boolean |
7fa3d080 | 7721 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
7722 | { |
7723 | fragS *fragP; | |
7724 | ||
7725 | for (fragP = base_fragP; | |
7726 | fragP && !fragP->tc_frag_data.is_loop_target; | |
7727 | fragP = fragP->fr_next) | |
7728 | { | |
7729 | if (unrelaxed_frag_has_b_j (fragP)) | |
7730 | return TRUE; | |
7731 | } | |
7732 | return FALSE; | |
7733 | } | |
7734 | ||
7735 | ||
43cd72b9 | 7736 | static bfd_boolean |
7fa3d080 | 7737 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 7738 | { |
43cd72b9 BW |
7739 | static xtensa_insnbuf insnbuf = NULL; |
7740 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
7741 | int offset = 0; |
7742 | ||
7743 | if (!fragP->tc_frag_data.is_insn) | |
7744 | return FALSE; | |
7745 | ||
43cd72b9 BW |
7746 | if (!insnbuf) |
7747 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7748 | ||
e0001a05 NC |
7749 | /* Decode the fixed instructions. */ |
7750 | while (offset < fragP->fr_fix) | |
7751 | { | |
43cd72b9 BW |
7752 | xtensa_format fmt; |
7753 | int slot; | |
7754 | ||
d77b99c9 BW |
7755 | xtensa_insnbuf_from_chars |
7756 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7757 | fmt = xtensa_format_decode (isa, insnbuf); |
7758 | if (fmt == XTENSA_UNDEFINED) | |
7759 | return FALSE; | |
7760 | ||
7761 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 7762 | { |
43cd72b9 BW |
7763 | xtensa_opcode opcode = |
7764 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
7765 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
7766 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
7767 | return TRUE; | |
e0001a05 | 7768 | } |
43cd72b9 | 7769 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7770 | } |
7771 | return FALSE; | |
7772 | } | |
7773 | ||
7774 | ||
7775 | /* Checks to be made after initial assembly but before relaxation. */ | |
7776 | ||
7fa3d080 BW |
7777 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
7778 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
7779 | ||
e0001a05 | 7780 | static void |
7fa3d080 | 7781 | xtensa_sanity_check (void) |
e0001a05 NC |
7782 | { |
7783 | char *file_name; | |
d77b99c9 | 7784 | unsigned line; |
e0001a05 NC |
7785 | |
7786 | frchainS *frchP; | |
7787 | ||
7788 | as_where (&file_name, &line); | |
7789 | for (frchP = frchain_root; frchP; frchP = frchP->frch_next) | |
7790 | { | |
7791 | fragS *fragP; | |
7792 | ||
7793 | /* Walk over all of the fragments in a subsection. */ | |
7794 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7795 | { | |
7796 | /* Currently we only check for empty loops here. */ | |
7797 | if (fragP->fr_type == rs_machine_dependent | |
7798 | && fragP->fr_subtype == RELAX_IMMED) | |
7799 | { | |
7800 | static xtensa_insnbuf insnbuf = NULL; | |
7801 | TInsn t_insn; | |
7802 | ||
7803 | if (fragP->fr_opcode != NULL) | |
7804 | { | |
7805 | if (!insnbuf) | |
7806 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
43cd72b9 BW |
7807 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); |
7808 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
e0001a05 | 7809 | |
43cd72b9 BW |
7810 | if (xtensa_opcode_is_loop (xtensa_default_isa, |
7811 | t_insn.opcode) == 1) | |
e0001a05 NC |
7812 | { |
7813 | if (is_empty_loop (&t_insn, fragP)) | |
7814 | { | |
7815 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7816 | as_bad (_("invalid empty loop")); | |
7817 | } | |
7818 | if (!is_local_forward_loop (&t_insn, fragP)) | |
7819 | { | |
7820 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7821 | as_bad (_("loop target does not follow " | |
7822 | "loop instruction in section")); | |
7823 | } | |
7824 | } | |
7825 | } | |
7826 | } | |
7827 | } | |
7828 | } | |
7829 | new_logical_line (file_name, line); | |
7830 | } | |
7831 | ||
7832 | ||
7833 | #define LOOP_IMMED_OPN 1 | |
7834 | ||
43cd72b9 | 7835 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 7836 | |
7fa3d080 BW |
7837 | static bfd_boolean |
7838 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7839 | { |
7840 | const expressionS *expr; | |
7841 | symbolS *symbolP; | |
7842 | fragS *next_fragP; | |
7843 | ||
7844 | if (insn->insn_type != ITYPE_INSN) | |
7845 | return FALSE; | |
7846 | ||
43cd72b9 | 7847 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7848 | return FALSE; |
7849 | ||
7850 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7851 | return FALSE; | |
7852 | ||
7853 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7854 | ||
7855 | if (expr->X_op != O_symbol) | |
7856 | return FALSE; | |
7857 | ||
7858 | symbolP = expr->X_add_symbol; | |
7859 | if (!symbolP) | |
7860 | return FALSE; | |
7861 | ||
7862 | if (symbol_get_frag (symbolP) == NULL) | |
7863 | return FALSE; | |
7864 | ||
7865 | if (S_GET_VALUE (symbolP) != 0) | |
7866 | return FALSE; | |
7867 | ||
7868 | /* Walk through the zero-size fragments from this one. If we find | |
7869 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 7870 | |
e0001a05 NC |
7871 | for (next_fragP = fragP->fr_next; |
7872 | next_fragP != NULL; | |
7873 | next_fragP = next_fragP->fr_next) | |
7874 | { | |
7875 | if (next_fragP == symbol_get_frag (symbolP)) | |
7876 | return TRUE; | |
7877 | if (next_fragP->fr_fix != 0) | |
7878 | return FALSE; | |
7879 | } | |
7880 | return FALSE; | |
7881 | } | |
7882 | ||
7883 | ||
7fa3d080 BW |
7884 | static bfd_boolean |
7885 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7886 | { |
7887 | const expressionS *expr; | |
7888 | symbolS *symbolP; | |
7889 | fragS *next_fragP; | |
7890 | ||
7891 | if (insn->insn_type != ITYPE_INSN) | |
7892 | return FALSE; | |
7893 | ||
43cd72b9 | 7894 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) == 0) |
e0001a05 NC |
7895 | return FALSE; |
7896 | ||
7897 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7898 | return FALSE; | |
7899 | ||
7900 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7901 | ||
7902 | if (expr->X_op != O_symbol) | |
7903 | return FALSE; | |
7904 | ||
7905 | symbolP = expr->X_add_symbol; | |
7906 | if (!symbolP) | |
7907 | return FALSE; | |
7908 | ||
7909 | if (symbol_get_frag (symbolP) == NULL) | |
7910 | return FALSE; | |
7911 | ||
7912 | /* Walk through fragments until we find the target. | |
7913 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 7914 | |
e0001a05 NC |
7915 | for (next_fragP = fragP->fr_next; |
7916 | next_fragP != NULL; | |
7917 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
7918 | { |
7919 | if (next_fragP == symbol_get_frag (symbolP)) | |
7920 | return TRUE; | |
7921 | } | |
e0001a05 NC |
7922 | |
7923 | return FALSE; | |
7924 | } | |
7925 | ||
7926 | \f | |
7927 | /* Alignment Functions. */ | |
7928 | ||
d77b99c9 BW |
7929 | static int |
7930 | get_text_align_power (unsigned target_size) | |
e0001a05 | 7931 | { |
d77b99c9 BW |
7932 | int i = 0; |
7933 | unsigned power = 1; | |
7934 | ||
7935 | assert (target_size <= INT_MAX); | |
7936 | while (target_size > power) | |
e0001a05 | 7937 | { |
d77b99c9 BW |
7938 | power <<= 1; |
7939 | i += 1; | |
e0001a05 | 7940 | } |
d77b99c9 | 7941 | return i; |
e0001a05 NC |
7942 | } |
7943 | ||
7944 | ||
d77b99c9 | 7945 | static int |
7fa3d080 BW |
7946 | get_text_align_max_fill_size (int align_pow, |
7947 | bfd_boolean use_nops, | |
7948 | bfd_boolean use_no_density) | |
e0001a05 NC |
7949 | { |
7950 | if (!use_nops) | |
7951 | return (1 << align_pow); | |
7952 | if (use_no_density) | |
7953 | return 3 * (1 << align_pow); | |
7954 | ||
7955 | return 1 + (1 << align_pow); | |
7956 | } | |
7957 | ||
7958 | ||
d77b99c9 BW |
7959 | /* Calculate the minimum bytes of fill needed at "address" to align a |
7960 | target instruction of size "target_size" so that it does not cross a | |
7961 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
7962 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
7963 | be filled by NOP instructions. */ | |
e0001a05 | 7964 | |
d77b99c9 | 7965 | static int |
7fa3d080 BW |
7966 | get_text_align_fill_size (addressT address, |
7967 | int align_pow, | |
7968 | int target_size, | |
7969 | bfd_boolean use_nops, | |
7970 | bfd_boolean use_no_density) | |
e0001a05 | 7971 | { |
d77b99c9 BW |
7972 | addressT alignment, fill, fill_limit, fill_step; |
7973 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 7974 | |
d77b99c9 BW |
7975 | alignment = (1 << align_pow); |
7976 | assert (target_size > 0 && alignment >= (addressT) target_size); | |
43cd72b9 | 7977 | |
e0001a05 NC |
7978 | if (!use_nops) |
7979 | { | |
d77b99c9 BW |
7980 | fill_limit = alignment; |
7981 | fill_step = 1; | |
e0001a05 | 7982 | } |
d77b99c9 | 7983 | else if (!use_no_density) |
e0001a05 | 7984 | { |
d77b99c9 BW |
7985 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
7986 | fill_limit = alignment * 2; | |
7987 | fill_step = 1; | |
7988 | skip_one = TRUE; | |
e0001a05 NC |
7989 | } |
7990 | else | |
7991 | { | |
d77b99c9 BW |
7992 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
7993 | fill_limit = alignment * 3; | |
7994 | fill_step = 3; | |
7995 | } | |
e0001a05 | 7996 | |
d77b99c9 BW |
7997 | /* Try all fill sizes until finding one that works. */ |
7998 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
7999 | { | |
8000 | if (skip_one && fill == 1) | |
8001 | continue; | |
8002 | if ((address + fill) >> align_pow | |
8003 | == (address + fill + target_size - 1) >> align_pow) | |
8004 | return fill; | |
e0001a05 NC |
8005 | } |
8006 | assert (0); | |
8007 | return 0; | |
8008 | } | |
8009 | ||
8010 | ||
664df4e4 BW |
8011 | static int |
8012 | branch_align_power (segT sec) | |
8013 | { | |
8014 | /* If the Xtensa processor has a fetch width of 8 bytes, and the section | |
8015 | is aligned to at least an 8-byte boundary, then a branch target need | |
8016 | only fit within an 8-byte aligned block of memory to avoid a stall. | |
8017 | Otherwise, try to fit branch targets within 4-byte aligned blocks | |
8018 | (which may be insufficient, e.g., if the section has no alignment, but | |
8019 | it's good enough). */ | |
8020 | if (xtensa_fetch_width == 8) | |
8021 | { | |
8022 | if (get_recorded_alignment (sec) >= 3) | |
8023 | return 3; | |
8024 | } | |
8025 | else | |
8026 | assert (xtensa_fetch_width == 4); | |
8027 | ||
8028 | return 2; | |
8029 | } | |
8030 | ||
8031 | ||
e0001a05 NC |
8032 | /* This will assert if it is not possible. */ |
8033 | ||
d77b99c9 BW |
8034 | static int |
8035 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 8036 | { |
d77b99c9 BW |
8037 | int count = 0; |
8038 | ||
e0001a05 NC |
8039 | if (use_no_density) |
8040 | { | |
8041 | assert (fill_size % 3 == 0); | |
8042 | return (fill_size / 3); | |
8043 | } | |
8044 | ||
8045 | assert (fill_size != 1); /* Bad argument. */ | |
8046 | ||
8047 | while (fill_size > 1) | |
8048 | { | |
d77b99c9 | 8049 | int insn_size = 3; |
e0001a05 NC |
8050 | if (fill_size == 2 || fill_size == 4) |
8051 | insn_size = 2; | |
8052 | fill_size -= insn_size; | |
8053 | count++; | |
8054 | } | |
8055 | assert (fill_size != 1); /* Bad algorithm. */ | |
8056 | return count; | |
8057 | } | |
8058 | ||
8059 | ||
d77b99c9 BW |
8060 | static int |
8061 | get_text_align_nth_nop_size (offsetT fill_size, | |
8062 | int n, | |
7fa3d080 | 8063 | bfd_boolean use_no_density) |
e0001a05 | 8064 | { |
d77b99c9 | 8065 | int count = 0; |
e0001a05 NC |
8066 | |
8067 | if (use_no_density) | |
8068 | return 3; | |
8069 | ||
d77b99c9 BW |
8070 | assert (fill_size != 1); /* Bad argument. */ |
8071 | ||
e0001a05 NC |
8072 | while (fill_size > 1) |
8073 | { | |
d77b99c9 | 8074 | int insn_size = 3; |
e0001a05 NC |
8075 | if (fill_size == 2 || fill_size == 4) |
8076 | insn_size = 2; | |
8077 | fill_size -= insn_size; | |
8078 | count++; | |
8079 | if (n + 1 == count) | |
8080 | return insn_size; | |
8081 | } | |
8082 | assert (0); | |
8083 | return 0; | |
8084 | } | |
8085 | ||
8086 | ||
8087 | /* For the given fragment, find the appropriate address | |
8088 | for it to begin at if we are using NOPs to align it. */ | |
8089 | ||
8090 | static addressT | |
7fa3d080 | 8091 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 8092 | { |
43cd72b9 BW |
8093 | /* The rule is: get next fragment's FIRST instruction. Find |
8094 | the smallest number of bytes that need to be added to | |
8095 | ensure that the next fragment's FIRST instruction will fit | |
8096 | in a single word. | |
8097 | ||
8098 | E.G., 2 bytes : 0, 1, 2 mod 4 | |
8099 | 3 bytes: 0, 1 mod 4 | |
8100 | ||
8101 | If the FIRST instruction MIGHT be relaxed, | |
8102 | assume that it will become a 3-byte instruction. | |
8103 | ||
8104 | Note again here that LOOP instructions are not bundleable, | |
8105 | and this relaxation only applies to LOOP opcodes. */ | |
8106 | ||
d77b99c9 | 8107 | int fill_size = 0; |
43cd72b9 BW |
8108 | int first_insn_size; |
8109 | int loop_insn_size; | |
8110 | addressT pre_opcode_bytes; | |
d77b99c9 | 8111 | int align_power; |
43cd72b9 BW |
8112 | fragS *first_insn; |
8113 | xtensa_opcode opcode; | |
8114 | bfd_boolean is_loop; | |
e0001a05 | 8115 | |
43cd72b9 BW |
8116 | assert (fragP->fr_type == rs_machine_dependent); |
8117 | assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 8118 | |
43cd72b9 BW |
8119 | /* Find the loop frag. */ |
8120 | first_insn = next_non_empty_frag (fragP); | |
8121 | /* Now find the first insn frag. */ | |
8122 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 8123 | |
43cd72b9 BW |
8124 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
8125 | assert (is_loop); | |
8126 | loop_insn_size = xg_get_single_size (opcode); | |
e0001a05 | 8127 | |
43cd72b9 BW |
8128 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
8129 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 8130 | |
43cd72b9 BW |
8131 | /* For loops, the alignment depends on the size of the |
8132 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 8133 | |
43cd72b9 BW |
8134 | if (first_insn == NULL) |
8135 | return address; | |
e0001a05 | 8136 | |
43cd72b9 | 8137 | assert (first_insn->tc_frag_data.is_first_loop_insn); |
e0001a05 | 8138 | |
43cd72b9 | 8139 | first_insn_size = frag_format_size (first_insn); |
e0001a05 | 8140 | |
43cd72b9 BW |
8141 | if (first_insn_size == 2 || first_insn_size == XTENSA_UNDEFINED) |
8142 | first_insn_size = 3; /* ISA specifies this */ | |
e0001a05 | 8143 | |
43cd72b9 | 8144 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
8145 | align_power = get_text_align_power (first_insn_size); |
8146 | record_alignment (now_seg, align_power); | |
43cd72b9 BW |
8147 | |
8148 | fill_size = get_text_align_fill_size | |
d77b99c9 BW |
8149 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
8150 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
8151 | |
8152 | return address + fill_size; | |
8153 | } | |
8154 | ||
8155 | ||
43cd72b9 BW |
8156 | /* 3 mechanisms for relaxing an alignment: |
8157 | ||
8158 | Align to a power of 2. | |
8159 | Align so the next fragment's instruction does not cross a word boundary. | |
8160 | Align the current instruction so that if the next instruction | |
8161 | were 3 bytes, it would not cross a word boundary. | |
8162 | ||
e0001a05 NC |
8163 | We can align with: |
8164 | ||
43cd72b9 BW |
8165 | zeros - This is easy; always insert zeros. |
8166 | nops - 3-byte and 2-byte instructions | |
8167 | 2 - 2-byte nop | |
8168 | 3 - 3-byte nop | |
8169 | 4 - 2 2-byte nops | |
8170 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
8171 | widening - widen previous instructions. */ |
8172 | ||
d77b99c9 BW |
8173 | static offsetT |
8174 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 8175 | { |
43cd72b9 BW |
8176 | addressT target_address, loop_insn_offset; |
8177 | int target_size; | |
8178 | xtensa_opcode loop_opcode; | |
8179 | bfd_boolean is_loop; | |
d77b99c9 BW |
8180 | int align_power; |
8181 | offsetT opt_diff; | |
664df4e4 | 8182 | addressT branch_align; |
e0001a05 | 8183 | |
43cd72b9 BW |
8184 | assert (fragP->fr_type == rs_machine_dependent); |
8185 | switch (fragP->fr_subtype) | |
e0001a05 | 8186 | { |
43cd72b9 BW |
8187 | case RELAX_DESIRE_ALIGN: |
8188 | target_size = next_frag_format_size (fragP); | |
8189 | if (target_size == XTENSA_UNDEFINED) | |
8190 | target_size = 3; | |
664df4e4 BW |
8191 | align_power = branch_align_power (now_seg); |
8192 | branch_align = 1 << align_power; | |
0e5cd789 BW |
8193 | /* Don't count on the section alignment being as large as the target. */ |
8194 | if (target_size > branch_align) | |
8195 | target_size = branch_align; | |
d77b99c9 | 8196 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
8197 | target_size, FALSE, FALSE); |
8198 | ||
664df4e4 BW |
8199 | *max_diff = (opt_diff + branch_align |
8200 | - (target_size + ((address + opt_diff) % branch_align))); | |
43cd72b9 BW |
8201 | assert (*max_diff >= opt_diff); |
8202 | return opt_diff; | |
e0001a05 | 8203 | |
43cd72b9 BW |
8204 | case RELAX_ALIGN_NEXT_OPCODE: |
8205 | target_size = next_frag_format_size (fragP); | |
8206 | loop_insn_offset = 0; | |
8207 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
8208 | assert (is_loop); | |
8209 | ||
8210 | /* If the loop has been expanded then the LOOP instruction | |
8211 | could be at an offset from this fragment. */ | |
8212 | if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0] | |
8213 | != RELAX_IMMED) | |
8214 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); | |
8215 | ||
8216 | if (target_size == 2) | |
8217 | target_size = 3; /* ISA specifies this */ | |
8218 | ||
8219 | /* In an ideal world, which is what we are shooting for here, | |
8220 | we wouldn't need to use any NOPs immediately prior to the | |
8221 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
8222 | will call get_noop_aligned_address. */ | |
8223 | target_address = | |
8224 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
d77b99c9 BW |
8225 | align_power = get_text_align_power (target_size), |
8226 | opt_diff = get_text_align_fill_size (target_address, align_power, | |
43cd72b9 BW |
8227 | target_size, FALSE, FALSE); |
8228 | ||
8229 | *max_diff = xtensa_fetch_width | |
8230 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
8231 | - target_size + opt_diff; | |
8232 | assert (*max_diff >= opt_diff); | |
8233 | return opt_diff; | |
e0001a05 | 8234 | |
43cd72b9 BW |
8235 | default: |
8236 | break; | |
e0001a05 | 8237 | } |
43cd72b9 BW |
8238 | assert (0); |
8239 | return 0; | |
e0001a05 NC |
8240 | } |
8241 | ||
8242 | \f | |
8243 | /* md_relax_frag Hook and Helper Functions. */ | |
8244 | ||
7fa3d080 BW |
8245 | static long relax_frag_loop_align (fragS *, long); |
8246 | static long relax_frag_for_align (fragS *, long); | |
8247 | static long relax_frag_immed | |
8248 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
8249 | ||
8250 | ||
e0001a05 NC |
8251 | /* Return the number of bytes added to this fragment, given that the |
8252 | input has been stretched already by "stretch". */ | |
8253 | ||
8254 | long | |
7fa3d080 | 8255 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 8256 | { |
43cd72b9 | 8257 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
8258 | int unreported = fragP->tc_frag_data.unreported_expansion; |
8259 | long new_stretch = 0; | |
8260 | char *file_name; | |
d77b99c9 BW |
8261 | unsigned line; |
8262 | int lit_size; | |
43cd72b9 BW |
8263 | static xtensa_insnbuf vbuf = NULL; |
8264 | int slot, num_slots; | |
8265 | xtensa_format fmt; | |
e0001a05 NC |
8266 | |
8267 | as_where (&file_name, &line); | |
8268 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8269 | ||
8270 | fragP->tc_frag_data.unreported_expansion = 0; | |
8271 | ||
8272 | switch (fragP->fr_subtype) | |
8273 | { | |
8274 | case RELAX_ALIGN_NEXT_OPCODE: | |
8275 | /* Always convert. */ | |
43cd72b9 BW |
8276 | if (fragP->tc_frag_data.relax_seen) |
8277 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
8278 | break; |
8279 | ||
8280 | case RELAX_LOOP_END: | |
8281 | /* Do nothing. */ | |
8282 | break; | |
8283 | ||
8284 | case RELAX_LOOP_END_ADD_NOP: | |
8285 | /* Add a NOP and switch to .fill 0. */ | |
8286 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 8287 | frag_wane (fragP); |
e0001a05 NC |
8288 | break; |
8289 | ||
8290 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 8291 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
8292 | it or not. */ |
8293 | break; | |
8294 | ||
8295 | case RELAX_LITERAL: | |
8296 | case RELAX_LITERAL_FINAL: | |
8297 | return 0; | |
8298 | ||
8299 | case RELAX_LITERAL_NR: | |
8300 | lit_size = 4; | |
8301 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
8302 | assert (unreported == lit_size); | |
8303 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); | |
8304 | fragP->fr_var -= lit_size; | |
8305 | fragP->fr_fix += lit_size; | |
8306 | new_stretch = 4; | |
8307 | break; | |
8308 | ||
43cd72b9 BW |
8309 | case RELAX_SLOTS: |
8310 | if (vbuf == NULL) | |
8311 | vbuf = xtensa_insnbuf_alloc (isa); | |
8312 | ||
d77b99c9 BW |
8313 | xtensa_insnbuf_from_chars |
8314 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
8315 | fmt = xtensa_format_decode (isa, vbuf); |
8316 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 8317 | |
43cd72b9 BW |
8318 | for (slot = 0; slot < num_slots; slot++) |
8319 | { | |
8320 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
8321 | { | |
8322 | case RELAX_NARROW: | |
8323 | if (fragP->tc_frag_data.relax_seen) | |
8324 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8325 | break; | |
8326 | ||
8327 | case RELAX_IMMED: | |
8328 | case RELAX_IMMED_STEP1: | |
8329 | case RELAX_IMMED_STEP2: | |
8330 | /* Place the immediate. */ | |
8331 | new_stretch += relax_frag_immed | |
8332 | (now_seg, fragP, stretch, | |
8333 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8334 | fmt, slot, stretched_p, FALSE); | |
8335 | break; | |
8336 | ||
8337 | default: | |
8338 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
8339 | break; | |
8340 | } | |
8341 | } | |
e0001a05 NC |
8342 | break; |
8343 | ||
8344 | case RELAX_LITERAL_POOL_BEGIN: | |
8345 | case RELAX_LITERAL_POOL_END: | |
43cd72b9 BW |
8346 | case RELAX_MAYBE_UNREACHABLE: |
8347 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
8348 | /* No relaxation required. */ |
8349 | break; | |
8350 | ||
43cd72b9 BW |
8351 | case RELAX_FILL_NOP: |
8352 | case RELAX_UNREACHABLE: | |
8353 | if (fragP->tc_frag_data.relax_seen) | |
8354 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8355 | break; | |
8356 | ||
e0001a05 NC |
8357 | default: |
8358 | as_bad (_("bad relaxation state")); | |
8359 | } | |
8360 | ||
43cd72b9 BW |
8361 | /* Tell gas we need another relaxation pass. */ |
8362 | if (! fragP->tc_frag_data.relax_seen) | |
8363 | { | |
8364 | fragP->tc_frag_data.relax_seen = TRUE; | |
8365 | *stretched_p = 1; | |
8366 | } | |
8367 | ||
e0001a05 NC |
8368 | new_logical_line (file_name, line); |
8369 | return new_stretch; | |
8370 | } | |
8371 | ||
8372 | ||
8373 | static long | |
7fa3d080 | 8374 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
8375 | { |
8376 | addressT old_address, old_next_address, old_size; | |
8377 | addressT new_address, new_next_address, new_size; | |
8378 | addressT growth; | |
8379 | ||
43cd72b9 BW |
8380 | /* All the frags with relax_frag_for_alignment prior to this one in the |
8381 | section have been done, hopefully eliminating the need for a NOP here. | |
8382 | But, this will put it in if necessary. */ | |
e0001a05 NC |
8383 | |
8384 | /* Calculate the old address of this fragment and the next fragment. */ | |
8385 | old_address = fragP->fr_address - stretch; | |
8386 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 8387 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
8388 | old_size = old_next_address - old_address; |
8389 | ||
8390 | /* Calculate the new address of this fragment and the next fragment. */ | |
8391 | new_address = fragP->fr_address; | |
8392 | new_next_address = | |
8393 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
8394 | new_size = new_next_address - new_address; | |
8395 | ||
8396 | growth = new_size - old_size; | |
8397 | ||
8398 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 8399 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
8400 | return growth; |
8401 | } | |
8402 | ||
8403 | ||
43cd72b9 | 8404 | /* Add a NOP instruction. */ |
e0001a05 NC |
8405 | |
8406 | static long | |
7fa3d080 | 8407 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 8408 | { |
e0001a05 | 8409 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
8410 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
8411 | assemble_nop (length, nop_buf); | |
e0001a05 | 8412 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 8413 | |
e0001a05 NC |
8414 | if (fragP->fr_var < length) |
8415 | { | |
dd49a749 | 8416 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
8417 | return 0; |
8418 | } | |
8419 | ||
8420 | fragP->fr_fix += length; | |
8421 | fragP->fr_var -= length; | |
e0001a05 NC |
8422 | return length; |
8423 | } | |
8424 | ||
8425 | ||
7fa3d080 BW |
8426 | static long future_alignment_required (fragS *, long); |
8427 | ||
e0001a05 | 8428 | static long |
7fa3d080 | 8429 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 8430 | { |
43cd72b9 BW |
8431 | /* Overview of the relaxation procedure for alignment: |
8432 | We can widen with NOPs or by widening instructions or by filling | |
8433 | bytes after jump instructions. Find the opportune places and widen | |
8434 | them if necessary. */ | |
8435 | ||
8436 | long stretch_me; | |
8437 | long diff; | |
e0001a05 | 8438 | |
43cd72b9 BW |
8439 | assert (fragP->fr_subtype == RELAX_FILL_NOP |
8440 | || fragP->fr_subtype == RELAX_UNREACHABLE | |
8441 | || (fragP->fr_subtype == RELAX_SLOTS | |
8442 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
8443 | ||
8444 | stretch_me = future_alignment_required (fragP, stretch); | |
8445 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
8446 | if (diff == 0) | |
8447 | return 0; | |
e0001a05 | 8448 | |
43cd72b9 | 8449 | if (diff < 0) |
e0001a05 | 8450 | { |
43cd72b9 BW |
8451 | /* We expanded on a previous pass. Can we shrink now? */ |
8452 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
8453 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 8454 | { |
43cd72b9 BW |
8455 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
8456 | return -shrink; | |
e0001a05 NC |
8457 | } |
8458 | return 0; | |
8459 | } | |
8460 | ||
43cd72b9 BW |
8461 | /* Below here, diff > 0. */ |
8462 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 8463 | |
43cd72b9 | 8464 | return diff; |
e0001a05 NC |
8465 | } |
8466 | ||
8467 | ||
43cd72b9 BW |
8468 | /* Return the address of the next frag that should be aligned. |
8469 | ||
8470 | By "address" we mean the address it _would_ be at if there | |
8471 | is no action taken to align it between here and the target frag. | |
8472 | In other words, if no narrows and no fill nops are used between | |
8473 | here and the frag to align, _even_if_ some of the frags we use | |
8474 | to align targets have already expanded on a previous relaxation | |
8475 | pass. | |
8476 | ||
8477 | Also, count each frag that may be used to help align the target. | |
8478 | ||
8479 | Return 0 if there are no frags left in the chain that need to be | |
8480 | aligned. */ | |
8481 | ||
8482 | static addressT | |
7fa3d080 BW |
8483 | find_address_of_next_align_frag (fragS **fragPP, |
8484 | int *wide_nops, | |
8485 | int *narrow_nops, | |
8486 | int *widens, | |
8487 | bfd_boolean *paddable) | |
e0001a05 | 8488 | { |
43cd72b9 BW |
8489 | fragS *fragP = *fragPP; |
8490 | addressT address = fragP->fr_address; | |
8491 | ||
8492 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
8493 | |
8494 | while (fragP) | |
8495 | { | |
8496 | /* Limit this to a small search. */ | |
43cd72b9 BW |
8497 | if (*widens > 8) |
8498 | { | |
8499 | *fragPP = fragP; | |
8500 | return 0; | |
8501 | } | |
e0001a05 NC |
8502 | address += fragP->fr_fix; |
8503 | ||
43cd72b9 BW |
8504 | if (fragP->fr_type == rs_fill) |
8505 | address += fragP->fr_offset * fragP->fr_var; | |
8506 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 8507 | { |
e0001a05 NC |
8508 | switch (fragP->fr_subtype) |
8509 | { | |
43cd72b9 BW |
8510 | case RELAX_UNREACHABLE: |
8511 | *paddable = TRUE; | |
8512 | break; | |
8513 | ||
8514 | case RELAX_FILL_NOP: | |
8515 | (*wide_nops)++; | |
8516 | if (!fragP->tc_frag_data.is_no_density) | |
8517 | (*narrow_nops)++; | |
8518 | break; | |
8519 | ||
8520 | case RELAX_SLOTS: | |
8521 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8522 | { | |
8523 | (*widens)++; | |
8524 | break; | |
8525 | } | |
34e41783 | 8526 | address += total_frag_text_expansion (fragP);; |
e0001a05 NC |
8527 | break; |
8528 | ||
8529 | case RELAX_IMMED: | |
43cd72b9 | 8530 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
8531 | break; |
8532 | ||
8533 | case RELAX_ALIGN_NEXT_OPCODE: | |
8534 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
8535 | *fragPP = fragP; |
8536 | return address; | |
8537 | ||
8538 | case RELAX_MAYBE_UNREACHABLE: | |
8539 | case RELAX_MAYBE_DESIRE_ALIGN: | |
8540 | /* Do nothing. */ | |
e0001a05 NC |
8541 | break; |
8542 | ||
8543 | default: | |
43cd72b9 BW |
8544 | /* Just punt if we don't know the type. */ |
8545 | *fragPP = fragP; | |
8546 | return 0; | |
e0001a05 | 8547 | } |
43cd72b9 BW |
8548 | } |
8549 | else | |
8550 | { | |
8551 | /* Just punt if we don't know the type. */ | |
8552 | *fragPP = fragP; | |
8553 | return 0; | |
8554 | } | |
8555 | fragP = fragP->fr_next; | |
8556 | } | |
8557 | ||
8558 | *fragPP = fragP; | |
8559 | return 0; | |
8560 | } | |
8561 | ||
8562 | ||
7fa3d080 BW |
8563 | static long bytes_to_stretch (fragS *, int, int, int, int); |
8564 | ||
43cd72b9 BW |
8565 | /* Undefine LOOKAHEAD_ALIGNER to get the older behavior. |
8566 | I'll leave this in until I am more confident this works. */ | |
8567 | ||
8568 | #define LOOKAHEAD_ALIGNER 1 | |
8569 | ||
8570 | static long | |
7fa3d080 | 8571 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
8572 | { |
8573 | fragS *this_frag = fragP; | |
8574 | long address; | |
8575 | int num_widens = 0; | |
8576 | int wide_nops = 0; | |
8577 | int narrow_nops = 0; | |
8578 | bfd_boolean paddable = FALSE; | |
8579 | offsetT local_opt_diff; | |
8580 | offsetT opt_diff; | |
8581 | offsetT max_diff; | |
8582 | int stretch_amount = 0; | |
8583 | int local_stretch_amount; | |
8584 | int global_stretch_amount; | |
8585 | ||
7fa3d080 BW |
8586 | address = find_address_of_next_align_frag |
8587 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 BW |
8588 | |
8589 | if (address) | |
8590 | { | |
8591 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
8592 | opt_diff = local_opt_diff; | |
8593 | assert (opt_diff >= 0); | |
8594 | assert (max_diff >= opt_diff); | |
8595 | if (max_diff == 0) | |
8596 | return 0; | |
8597 | #ifdef LOOKAHEAD_ALIGNER | |
8598 | if (fragP) | |
8599 | fragP = fragP->fr_next; | |
8600 | ||
8601 | while (fragP && opt_diff < max_diff && address) | |
8602 | { | |
8603 | /* We only use these to determine if we can exit early | |
8604 | because there will be plenty of ways to align future | |
8605 | align frags. */ | |
d77b99c9 | 8606 | int glob_widens = 0; |
43cd72b9 BW |
8607 | int dnn = 0; |
8608 | int dw = 0; | |
8609 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
8610 | address = find_address_of_next_align_frag |
8611 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 8612 | /* If there is a padable portion, then skip. */ |
664df4e4 | 8613 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
43cd72b9 BW |
8614 | break; |
8615 | ||
8616 | if (address) | |
8617 | { | |
8618 | offsetT next_m_diff; | |
8619 | offsetT next_o_diff; | |
8620 | ||
8621 | /* Downrange frags haven't had stretch added to them yet. */ | |
8622 | address += stretch; | |
8623 | ||
8624 | /* The address also includes any text expansion from this | |
8625 | frag in a previous pass, but we don't want that. */ | |
8626 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
8627 | ||
8628 | /* Assume we are going to move at least opt_diff. In | |
8629 | reality, we might not be able to, but assuming that | |
8630 | we will helps catch cases where moving opt_diff pushes | |
8631 | the next target from aligned to unaligned. */ | |
8632 | address += opt_diff; | |
8633 | ||
8634 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
8635 | ||
8636 | /* Now cleanup for the adjustments to address. */ | |
8637 | next_o_diff += opt_diff; | |
8638 | next_m_diff += opt_diff; | |
8639 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
8640 | opt_diff = next_o_diff; | |
8641 | if (next_m_diff < max_diff) | |
8642 | max_diff = next_m_diff; | |
8643 | fragP = fragP->fr_next; | |
8644 | } | |
8645 | } | |
8646 | #endif /* LOOKAHEAD_ALIGNER */ | |
8647 | /* If there are enough wideners in between, do it. */ | |
8648 | if (paddable) | |
8649 | { | |
8650 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
8651 | { | |
8652 | assert (opt_diff <= UNREACHABLE_MAX_WIDTH); | |
8653 | return opt_diff; | |
8654 | } | |
8655 | return 0; | |
8656 | } | |
8657 | local_stretch_amount | |
8658 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
8659 | num_widens, local_opt_diff); | |
8660 | #ifdef LOOKAHEAD_ALIGNER | |
8661 | global_stretch_amount | |
8662 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
8663 | num_widens, opt_diff); | |
8664 | /* If the condition below is true, then the frag couldn't | |
8665 | stretch the correct amount for the global case, so we just | |
8666 | optimize locally. We'll rely on the subsequent frags to get | |
8667 | the correct alignment in the global case. */ | |
8668 | if (global_stretch_amount < local_stretch_amount) | |
8669 | stretch_amount = local_stretch_amount; | |
8670 | else | |
8671 | stretch_amount = global_stretch_amount; | |
8672 | #else /* ! LOOKAHEAD_ALIGNER */ | |
8673 | stretch_amount = local_stretch_amount; | |
8674 | #endif /* ! LOOKAHEAD_ALIGNER */ | |
8675 | if (this_frag->fr_subtype == RELAX_SLOTS | |
8676 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8677 | assert (stretch_amount <= 1); | |
8678 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8679 | { | |
8680 | if (this_frag->tc_frag_data.is_no_density) | |
8681 | assert (stretch_amount == 3 || stretch_amount == 0); | |
8682 | else | |
8683 | assert (stretch_amount <= 3); | |
8684 | } | |
8685 | } | |
8686 | return stretch_amount; | |
8687 | } | |
8688 | ||
8689 | ||
8690 | /* The idea: widen everything you can to get a target or loop aligned, | |
8691 | then start using NOPs. | |
8692 | ||
8693 | When we must have a NOP, here is a table of how we decide | |
8694 | (so you don't have to fight through the control flow below): | |
8695 | ||
8696 | wide_nops = the number of wide NOPs available for aligning | |
8697 | narrow_nops = the number of narrow NOPs available for aligning | |
8698 | (a subset of wide_nops) | |
8699 | widens = the number of narrow instructions that should be widened | |
8700 | ||
8701 | Desired wide narrow | |
8702 | Diff nop nop widens | |
8703 | 1 0 0 1 | |
8704 | 2 0 1 0 | |
8705 | 3a 1 0 0 | |
8706 | b 0 1 1 (case 3a makes this case unnecessary) | |
8707 | 4a 1 0 1 | |
8708 | b 0 2 0 | |
8709 | c 0 1 2 (case 4a makes this case unnecessary) | |
8710 | 5a 1 0 2 | |
8711 | b 1 1 0 | |
8712 | c 0 2 1 (case 5b makes this case unnecessary) | |
8713 | 6a 2 0 0 | |
8714 | b 1 0 3 | |
8715 | c 0 1 4 (case 6b makes this case unneccesary) | |
8716 | d 1 1 1 (case 6a makes this case unnecessary) | |
8717 | e 0 2 2 (case 6a makes this case unnecessary) | |
8718 | f 0 3 0 (case 6a makes this case unnecessary) | |
8719 | 7a 1 0 4 | |
8720 | b 2 0 1 | |
8721 | c 1 1 2 (case 7b makes this case unnecessary) | |
8722 | d 0 1 5 (case 7a makes this case unnecessary) | |
8723 | e 0 2 3 (case 7b makes this case unnecessary) | |
8724 | f 0 3 1 (case 7b makes this case unnecessary) | |
8725 | g 1 2 1 (case 7b makes this case unnecessary) | |
8726 | */ | |
8727 | ||
8728 | static long | |
7fa3d080 BW |
8729 | bytes_to_stretch (fragS *this_frag, |
8730 | int wide_nops, | |
8731 | int narrow_nops, | |
8732 | int num_widens, | |
8733 | int desired_diff) | |
43cd72b9 BW |
8734 | { |
8735 | int bytes_short = desired_diff - num_widens; | |
8736 | ||
8737 | assert (desired_diff >= 0 && desired_diff < 8); | |
8738 | if (desired_diff == 0) | |
8739 | return 0; | |
8740 | ||
8741 | assert (wide_nops > 0 || num_widens > 0); | |
e0001a05 | 8742 | |
43cd72b9 BW |
8743 | /* Always prefer widening to NOP-filling. */ |
8744 | if (bytes_short < 0) | |
8745 | { | |
8746 | /* There are enough RELAX_NARROW frags after this one | |
8747 | to align the target without widening this frag in any way. */ | |
8748 | return 0; | |
8749 | } | |
8750 | ||
8751 | if (bytes_short == 0) | |
8752 | { | |
8753 | /* Widen every narrow between here and the align target | |
8754 | and the align target will be properly aligned. */ | |
8755 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8756 | return 0; | |
8757 | else | |
8758 | return 1; | |
8759 | } | |
8760 | ||
8761 | /* From here we will need at least one NOP to get an alignment. | |
8762 | However, we may not be able to align at all, in which case, | |
8763 | don't widen. */ | |
8764 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8765 | { | |
8766 | switch (desired_diff) | |
8767 | { | |
8768 | case 1: | |
8769 | return 0; | |
8770 | case 2: | |
8771 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1) | |
8772 | return 2; /* case 2 */ | |
8773 | return 0; | |
8774 | case 3: | |
8775 | if (wide_nops > 1) | |
8776 | return 0; | |
8777 | else | |
8778 | return 3; /* case 3a */ | |
8779 | case 4: | |
8780 | if (num_widens >= 1 && wide_nops == 1) | |
8781 | return 3; /* case 4a */ | |
8782 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2) | |
8783 | return 2; /* case 4b */ | |
8784 | return 0; | |
8785 | case 5: | |
8786 | if (num_widens >= 2 && wide_nops == 1) | |
8787 | return 3; /* case 5a */ | |
8788 | /* We will need two nops. Are there enough nops | |
8789 | between here and the align target? */ | |
8790 | if (wide_nops < 2 || narrow_nops == 0) | |
8791 | return 0; | |
8792 | /* Are there other nops closer that can serve instead? */ | |
8793 | if (wide_nops > 2 && narrow_nops > 1) | |
8794 | return 0; | |
8795 | /* Take the density one first, because there might not be | |
8796 | another density one available. */ | |
8797 | if (!this_frag->tc_frag_data.is_no_density) | |
8798 | return 2; /* case 5b narrow */ | |
8799 | else | |
8800 | return 3; /* case 5b wide */ | |
8801 | return 0; | |
8802 | case 6: | |
8803 | if (wide_nops == 2) | |
8804 | return 3; /* case 6a */ | |
8805 | else if (num_widens >= 3 && wide_nops == 1) | |
8806 | return 3; /* case 6b */ | |
8807 | return 0; | |
8808 | case 7: | |
8809 | if (wide_nops == 1 && num_widens >= 4) | |
8810 | return 3; /* case 7a */ | |
8811 | else if (wide_nops == 2 && num_widens >= 1) | |
8812 | return 3; /* case 7b */ | |
8813 | return 0; | |
e0001a05 | 8814 | default: |
43cd72b9 | 8815 | assert (0); |
e0001a05 | 8816 | } |
e0001a05 | 8817 | } |
43cd72b9 BW |
8818 | else |
8819 | { | |
8820 | /* We will need a NOP no matter what, but should we widen | |
8821 | this instruction to help? | |
e0001a05 | 8822 | |
43cd72b9 BW |
8823 | This is a RELAX_FRAG_NARROW frag. */ |
8824 | switch (desired_diff) | |
8825 | { | |
8826 | case 1: | |
8827 | assert (0); | |
8828 | return 0; | |
8829 | case 2: | |
8830 | case 3: | |
8831 | return 0; | |
8832 | case 4: | |
8833 | if (wide_nops >= 1 && num_widens == 1) | |
8834 | return 1; /* case 4a */ | |
8835 | return 0; | |
8836 | case 5: | |
8837 | if (wide_nops >= 1 && num_widens == 2) | |
8838 | return 1; /* case 5a */ | |
8839 | return 0; | |
8840 | case 6: | |
8841 | if (wide_nops >= 2) | |
8842 | return 0; /* case 6a */ | |
8843 | else if (wide_nops >= 1 && num_widens == 3) | |
8844 | return 1; /* case 6b */ | |
8845 | return 0; | |
8846 | case 7: | |
8847 | if (wide_nops >= 1 && num_widens == 4) | |
8848 | return 1; /* case 7a */ | |
8849 | else if (wide_nops >= 2 && num_widens == 1) | |
8850 | return 1; /* case 7b */ | |
8851 | return 0; | |
8852 | default: | |
8853 | assert (0); | |
8854 | return 0; | |
8855 | } | |
8856 | } | |
8857 | assert (0); | |
8858 | return 0; | |
e0001a05 NC |
8859 | } |
8860 | ||
8861 | ||
8862 | static long | |
7fa3d080 BW |
8863 | relax_frag_immed (segT segP, |
8864 | fragS *fragP, | |
8865 | long stretch, | |
8866 | int min_steps, | |
8867 | xtensa_format fmt, | |
8868 | int slot, | |
8869 | int *stretched_p, | |
8870 | bfd_boolean estimate_only) | |
e0001a05 | 8871 | { |
43cd72b9 BW |
8872 | TInsn tinsn; |
8873 | vliw_insn orig_vinsn; | |
e0001a05 NC |
8874 | int old_size; |
8875 | bfd_boolean negatable_branch = FALSE; | |
8876 | bfd_boolean branch_jmp_to_next = FALSE; | |
43cd72b9 BW |
8877 | bfd_boolean wide_insn = FALSE; |
8878 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
8879 | IStack istack; |
8880 | offsetT frag_offset; | |
8881 | int num_steps; | |
8882 | fragS *lit_fragP; | |
8883 | int num_text_bytes, num_literal_bytes; | |
43cd72b9 | 8884 | int literal_diff, total_text_diff, this_text_diff, first; |
e0001a05 NC |
8885 | |
8886 | assert (fragP->fr_opcode != NULL); | |
8887 | ||
43cd72b9 BW |
8888 | xg_init_vinsn (&orig_vinsn); |
8889 | vinsn_from_chars (&orig_vinsn, fragP->fr_opcode); | |
8890 | if (xtensa_format_num_slots (isa, fmt) > 1) | |
8891 | wide_insn = TRUE; | |
8892 | ||
8893 | tinsn = orig_vinsn.slots[slot]; | |
8894 | tinsn_immed_from_frag (&tinsn, fragP, slot); | |
e0001a05 | 8895 | |
43cd72b9 BW |
8896 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode)) |
8897 | return 0; | |
e0001a05 | 8898 | |
b08b5071 | 8899 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 8900 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 8901 | |
43cd72b9 | 8902 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 8903 | |
43cd72b9 | 8904 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
8905 | |
8906 | /* Special case: replace a branch to the next instruction with a NOP. | |
8907 | This is required to work around a hardware bug in T1040.0 and also | |
8908 | serves as an optimization. */ | |
8909 | ||
8910 | if (branch_jmp_to_next | |
8911 | && ((old_size == 2) || (old_size == 3)) | |
8912 | && !next_frag_is_loop_target (fragP)) | |
8913 | return 0; | |
8914 | ||
8915 | /* Here is the fun stuff: Get the immediate field from this | |
8916 | instruction. If it fits, we are done. If not, find the next | |
8917 | instruction sequence that fits. */ | |
8918 | ||
8919 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
8920 | istack_init (&istack); | |
43cd72b9 | 8921 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 NC |
8922 | min_steps, stretch); |
8923 | if (num_steps < min_steps) | |
8924 | { | |
8925 | as_fatal (_("internal error: relaxation failed")); | |
8926 | return 0; | |
8927 | } | |
8928 | ||
8929 | if (num_steps > RELAX_IMMED_MAXSTEPS) | |
8930 | { | |
8931 | as_fatal (_("internal error: relaxation requires too many steps")); | |
8932 | return 0; | |
8933 | } | |
8934 | ||
43cd72b9 | 8935 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
8936 | |
8937 | /* Figure out the number of bytes needed. */ | |
8938 | lit_fragP = 0; | |
e0001a05 | 8939 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
43cd72b9 BW |
8940 | literal_diff = |
8941 | num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
8942 | first = 0; | |
8943 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
8944 | first++; | |
8945 | num_text_bytes = get_num_stack_text_bytes (&istack); | |
8946 | if (wide_insn) | |
8947 | { | |
8948 | num_text_bytes += old_size; | |
8949 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
8950 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
8951 | } | |
8952 | total_text_diff = num_text_bytes - old_size; | |
8953 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
8954 | |
8955 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
43cd72b9 BW |
8956 | assert (num_text_bytes >= 0); |
8957 | assert (literal_diff >= 0); | |
8958 | assert (total_text_diff >= 0); | |
e0001a05 | 8959 | |
43cd72b9 BW |
8960 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
8961 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
8962 | assert (fragP->tc_frag_data.text_expansion[slot] >= 0); | |
8963 | assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
8964 | |
8965 | /* Find the associated expandable literal for this. */ | |
8966 | if (literal_diff != 0) | |
8967 | { | |
43cd72b9 | 8968 | lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
8969 | if (lit_fragP) |
8970 | { | |
8971 | assert (literal_diff == 4); | |
8972 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; | |
8973 | ||
8974 | /* We expect that the literal section state has NOT been | |
8975 | modified yet. */ | |
8976 | assert (lit_fragP->fr_type == rs_machine_dependent | |
8977 | && lit_fragP->fr_subtype == RELAX_LITERAL); | |
8978 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
8979 | ||
8980 | /* We need to mark this section for another iteration | |
8981 | of relaxation. */ | |
8982 | (*stretched_p)++; | |
8983 | } | |
8984 | } | |
8985 | ||
43cd72b9 | 8986 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 8987 | update_next_frag_state (fragP); |
e0001a05 | 8988 | |
43cd72b9 | 8989 | return this_text_diff; |
e0001a05 NC |
8990 | } |
8991 | ||
8992 | \f | |
8993 | /* md_convert_frag Hook and Helper Functions. */ | |
8994 | ||
7fa3d080 BW |
8995 | static void convert_frag_align_next_opcode (fragS *); |
8996 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
8997 | static void convert_frag_fill_nop (fragS *); | |
8998 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
8999 | ||
e0001a05 | 9000 | void |
7fa3d080 | 9001 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 9002 | { |
43cd72b9 BW |
9003 | static xtensa_insnbuf vbuf = NULL; |
9004 | xtensa_isa isa = xtensa_default_isa; | |
9005 | int slot; | |
9006 | int num_slots; | |
9007 | xtensa_format fmt; | |
e0001a05 | 9008 | char *file_name; |
d77b99c9 | 9009 | unsigned line; |
e0001a05 NC |
9010 | |
9011 | as_where (&file_name, &line); | |
9012 | new_logical_line (fragp->fr_file, fragp->fr_line); | |
9013 | ||
9014 | switch (fragp->fr_subtype) | |
9015 | { | |
9016 | case RELAX_ALIGN_NEXT_OPCODE: | |
9017 | /* Always convert. */ | |
9018 | convert_frag_align_next_opcode (fragp); | |
9019 | break; | |
9020 | ||
9021 | case RELAX_DESIRE_ALIGN: | |
9022 | /* Do nothing. If not aligned already, too bad. */ | |
9023 | break; | |
9024 | ||
43cd72b9 BW |
9025 | case RELAX_LITERAL: |
9026 | case RELAX_LITERAL_FINAL: | |
9027 | break; | |
9028 | ||
9029 | case RELAX_SLOTS: | |
9030 | if (vbuf == NULL) | |
9031 | vbuf = xtensa_insnbuf_alloc (isa); | |
9032 | ||
d77b99c9 BW |
9033 | xtensa_insnbuf_from_chars |
9034 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
9035 | fmt = xtensa_format_decode (isa, vbuf); |
9036 | num_slots = xtensa_format_num_slots (isa, fmt); | |
9037 | ||
9038 | for (slot = 0; slot < num_slots; slot++) | |
9039 | { | |
9040 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
9041 | { | |
9042 | case RELAX_NARROW: | |
9043 | convert_frag_narrow (sec, fragp, fmt, slot); | |
9044 | break; | |
9045 | ||
9046 | case RELAX_IMMED: | |
9047 | case RELAX_IMMED_STEP1: | |
9048 | case RELAX_IMMED_STEP2: | |
9049 | /* Place the immediate. */ | |
9050 | convert_frag_immed | |
9051 | (sec, fragp, | |
9052 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
9053 | fmt, slot); | |
9054 | break; | |
9055 | ||
9056 | default: | |
9057 | /* This is OK because some slots could have | |
9058 | relaxations and others have none. */ | |
9059 | break; | |
9060 | } | |
9061 | } | |
9062 | break; | |
9063 | ||
9064 | case RELAX_UNREACHABLE: | |
9065 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
9066 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
9067 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
9068 | frag_wane (fragp); | |
e0001a05 NC |
9069 | break; |
9070 | ||
43cd72b9 BW |
9071 | case RELAX_MAYBE_UNREACHABLE: |
9072 | case RELAX_MAYBE_DESIRE_ALIGN: | |
9073 | frag_wane (fragp); | |
e0001a05 NC |
9074 | break; |
9075 | ||
43cd72b9 BW |
9076 | case RELAX_FILL_NOP: |
9077 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
9078 | break; |
9079 | ||
9080 | case RELAX_LITERAL_NR: | |
9081 | if (use_literal_section) | |
9082 | { | |
9083 | /* This should have been handled during relaxation. When | |
9084 | relaxing a code segment, literals sometimes need to be | |
9085 | added to the corresponding literal segment. If that | |
9086 | literal segment has already been relaxed, then we end up | |
9087 | in this situation. Marking the literal segments as data | |
9088 | would make this happen less often (since GAS always relaxes | |
9089 | code before data), but we could still get into trouble if | |
9090 | there are instructions in a segment that is not marked as | |
9091 | containing code. Until we can implement a better solution, | |
9092 | cheat and adjust the addresses of all the following frags. | |
9093 | This could break subsequent alignments, but the linker's | |
9094 | literal coalescing will do that anyway. */ | |
9095 | ||
9096 | fragS *f; | |
9097 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9098 | assert (fragp->tc_frag_data.unreported_expansion == 4); | |
9099 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); | |
9100 | fragp->fr_var -= 4; | |
9101 | fragp->fr_fix += 4; | |
9102 | for (f = fragp->fr_next; f; f = f->fr_next) | |
9103 | f->fr_address += 4; | |
9104 | } | |
9105 | else | |
9106 | as_bad (_("invalid relaxation fragment result")); | |
9107 | break; | |
9108 | } | |
9109 | ||
9110 | fragp->fr_var = 0; | |
9111 | new_logical_line (file_name, line); | |
9112 | } | |
9113 | ||
9114 | ||
7fa3d080 BW |
9115 | static void |
9116 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
9117 | { |
9118 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
9119 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
9120 | addressT aligned_address; | |
d77b99c9 BW |
9121 | offsetT fill_size; |
9122 | int nop, nop_count; | |
e0001a05 NC |
9123 | |
9124 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
9125 | fragp->fr_fix); | |
9126 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
9127 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
9128 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
9129 | ||
d77b99c9 | 9130 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 9131 | { |
d77b99c9 BW |
9132 | int nop_size; |
9133 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
9134 | |
9135 | assemble_nop (nop_size, nop_buf); | |
9136 | nop_buf += nop_size; | |
9137 | } | |
9138 | ||
9139 | fragp->fr_fix += fill_size; | |
9140 | fragp->fr_var -= fill_size; | |
9141 | } | |
9142 | ||
9143 | ||
9144 | static void | |
7fa3d080 | 9145 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 9146 | { |
43cd72b9 BW |
9147 | TInsn tinsn, single_target; |
9148 | xtensa_format single_fmt; | |
e0001a05 NC |
9149 | int size, old_size, diff, error_val; |
9150 | offsetT frag_offset; | |
9151 | ||
43cd72b9 BW |
9152 | assert (slot == 0); |
9153 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); | |
9154 | ||
9155 | if (xtensa_opcode_is_branch (xtensa_default_isa, tinsn.opcode) == 1) | |
9156 | { | |
9157 | assert (fragP->tc_frag_data.text_expansion[0] == 1 | |
9158 | || fragP->tc_frag_data.text_expansion[0] == 0); | |
9159 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
9160 | fmt, slot); | |
9161 | return; | |
9162 | } | |
9163 | ||
9164 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
9165 | { |
9166 | /* No conversion. */ | |
9167 | fragP->fr_var = 0; | |
9168 | return; | |
9169 | } | |
9170 | ||
9171 | assert (fragP->fr_opcode != NULL); | |
9172 | ||
43cd72b9 BW |
9173 | /* Frags in this relaxation state should only contain |
9174 | single instruction bundles. */ | |
9175 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
9176 | |
9177 | /* Just convert it to a wide form.... */ | |
9178 | size = 0; | |
43cd72b9 | 9179 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
9180 | |
9181 | tinsn_init (&single_target); | |
9182 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9183 | ||
43cd72b9 | 9184 | error_val = xg_expand_narrow (&single_target, &tinsn); |
e0001a05 | 9185 | if (error_val) |
43cd72b9 BW |
9186 | { |
9187 | as_bad (_("unable to widen instruction")); | |
9188 | return; | |
9189 | } | |
9190 | ||
9191 | size = xg_get_single_size (single_target.opcode); | |
9192 | single_fmt = xg_get_single_format (single_target.opcode); | |
e0001a05 | 9193 | |
43cd72b9 | 9194 | xg_emit_insn_to_buf (&single_target, single_fmt, fragP->fr_opcode, |
e0001a05 NC |
9195 | fragP, frag_offset, TRUE); |
9196 | ||
9197 | diff = size - old_size; | |
9198 | assert (diff >= 0); | |
9199 | assert (diff <= fragP->fr_var); | |
9200 | fragP->fr_var -= diff; | |
9201 | fragP->fr_fix += diff; | |
9202 | ||
9203 | /* clean it up */ | |
9204 | fragP->fr_var = 0; | |
9205 | } | |
9206 | ||
9207 | ||
9208 | static void | |
7fa3d080 | 9209 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
9210 | { |
9211 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
9212 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9213 | assert ((unsigned) size == (fragP->fr_next->fr_address | |
9214 | - fragP->fr_address - fragP->fr_fix)); | |
9215 | if (size == 0) | |
9216 | { | |
9217 | /* No conversion. */ | |
9218 | fragP->fr_var = 0; | |
9219 | return; | |
9220 | } | |
9221 | assemble_nop (size, loc); | |
9222 | fragP->tc_frag_data.is_insn = TRUE; | |
9223 | fragP->fr_var -= size; | |
9224 | fragP->fr_fix += size; | |
9225 | frag_wane (fragP); | |
9226 | } | |
9227 | ||
9228 | ||
7fa3d080 BW |
9229 | static fixS *fix_new_exp_in_seg |
9230 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
9231 | bfd_reloc_code_real_type); | |
9232 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
9233 | ||
43cd72b9 | 9234 | static void |
7fa3d080 BW |
9235 | convert_frag_immed (segT segP, |
9236 | fragS *fragP, | |
9237 | int min_steps, | |
9238 | xtensa_format fmt, | |
9239 | int slot) | |
e0001a05 NC |
9240 | { |
9241 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 9242 | TInsn orig_tinsn; |
e0001a05 | 9243 | bfd_boolean expanded = FALSE; |
e0001a05 | 9244 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 BW |
9245 | char *fr_opcode = fragP->fr_opcode; |
9246 | vliw_insn orig_vinsn; | |
9247 | xtensa_isa isa = xtensa_default_isa; | |
9248 | bfd_boolean wide_insn = FALSE; | |
9249 | int bytes; | |
9250 | bfd_boolean is_loop; | |
e0001a05 | 9251 | |
43cd72b9 | 9252 | assert (fr_opcode != NULL); |
e0001a05 | 9253 | |
43cd72b9 | 9254 | xg_init_vinsn (&orig_vinsn); |
e0001a05 | 9255 | |
43cd72b9 BW |
9256 | vinsn_from_chars (&orig_vinsn, fr_opcode); |
9257 | if (xtensa_format_num_slots (isa, fmt) > 1) | |
9258 | wide_insn = TRUE; | |
e0001a05 | 9259 | |
43cd72b9 BW |
9260 | orig_tinsn = orig_vinsn.slots[slot]; |
9261 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); | |
9262 | ||
9263 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 9264 | |
b08b5071 | 9265 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9266 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
9267 | |
9268 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
9269 | { | |
9270 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
9271 | bytes = xtensa_format_length (isa, fmt); |
9272 | if (bytes >= 4) | |
9273 | { | |
9274 | orig_vinsn.slots[slot].opcode = | |
9275 | xtensa_format_slot_nop_opcode (isa, orig_vinsn.format, slot); | |
9276 | orig_vinsn.slots[slot].ntok = 0; | |
9277 | } | |
9278 | else | |
9279 | { | |
9280 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9281 | assert (bytes == 2 || bytes == 3); | |
9282 | build_nop (&orig_vinsn.slots[0], bytes); | |
9283 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; | |
9284 | } | |
9285 | vinsn_to_insnbuf (&orig_vinsn, fr_opcode, frag_now, FALSE); | |
d77b99c9 BW |
9286 | xtensa_insnbuf_to_chars |
9287 | (isa, orig_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); | |
e0001a05 NC |
9288 | fragP->fr_var = 0; |
9289 | } | |
7c834684 | 9290 | else |
e0001a05 | 9291 | { |
43cd72b9 BW |
9292 | /* Here is the fun stuff: Get the immediate field from this |
9293 | instruction. If it fits, we're done. If not, find the next | |
9294 | instruction sequence that fits. */ | |
9295 | ||
e0001a05 NC |
9296 | IStack istack; |
9297 | int i; | |
9298 | symbolS *lit_sym = NULL; | |
9299 | int total_size = 0; | |
43cd72b9 | 9300 | int target_offset = 0; |
e0001a05 NC |
9301 | int old_size; |
9302 | int diff; | |
9303 | symbolS *gen_label = NULL; | |
9304 | offsetT frag_offset; | |
43cd72b9 BW |
9305 | bfd_boolean first = TRUE; |
9306 | bfd_boolean last_is_jump; | |
e0001a05 | 9307 | |
43cd72b9 | 9308 | /* It does not fit. Find something that does and |
e0001a05 | 9309 | convert immediately. */ |
43cd72b9 | 9310 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 9311 | istack_init (&istack); |
43cd72b9 | 9312 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
9313 | segP, fragP, frag_offset, min_steps, 0); |
9314 | ||
43cd72b9 | 9315 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9316 | |
9317 | /* Assemble this right inline. */ | |
9318 | ||
9319 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 9320 | target_offset = 0; |
e0001a05 NC |
9321 | for (i = 0; i < istack.ninsn; i++) |
9322 | { | |
43cd72b9 | 9323 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9324 | fragS *lit_frag; |
9325 | ||
43cd72b9 | 9326 | switch (tinsn->insn_type) |
e0001a05 NC |
9327 | { |
9328 | case ITYPE_LITERAL: | |
9329 | if (lit_sym != NULL) | |
9330 | as_bad (_("multiple literals in expansion")); | |
9331 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 9332 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9333 | if (lit_frag == NULL) |
9334 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 9335 | if (tinsn->ntok != 1) |
e0001a05 NC |
9336 | as_bad (_("number of literal tokens != 1")); |
9337 | ||
9338 | /* Set the literal symbol and add a fixup. */ | |
9339 | lit_sym = lit_frag->fr_symbol; | |
9340 | break; | |
9341 | ||
9342 | case ITYPE_LABEL: | |
43cd72b9 BW |
9343 | if (align_targets && !is_loop) |
9344 | { | |
9345 | fragS *unreach = fragP->fr_next; | |
9346 | while (!(unreach->fr_type == rs_machine_dependent | |
9347 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9348 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
9349 | { | |
9350 | unreach = unreach->fr_next; | |
9351 | } | |
9352 | ||
9353 | assert (unreach->fr_type == rs_machine_dependent | |
9354 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9355 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
9356 | ||
9357 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
9358 | } | |
e0001a05 NC |
9359 | assert (gen_label == NULL); |
9360 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, | |
43cd72b9 BW |
9361 | fr_opcode - fragP->fr_literal |
9362 | + target_offset, fragP); | |
e0001a05 NC |
9363 | break; |
9364 | ||
9365 | case ITYPE_INSN: | |
43cd72b9 BW |
9366 | if (first && wide_insn) |
9367 | { | |
9368 | target_offset += xtensa_format_length (isa, fmt); | |
9369 | first = FALSE; | |
9370 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9371 | target_offset += xg_get_single_size (tinsn->opcode); | |
9372 | } | |
9373 | else | |
9374 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
9375 | break; |
9376 | } | |
9377 | } | |
9378 | ||
9379 | total_size = 0; | |
43cd72b9 BW |
9380 | first = TRUE; |
9381 | last_is_jump = FALSE; | |
e0001a05 NC |
9382 | for (i = 0; i < istack.ninsn; i++) |
9383 | { | |
43cd72b9 | 9384 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9385 | fragS *lit_frag; |
9386 | int size; | |
9387 | segT target_seg; | |
43cd72b9 | 9388 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 9389 | |
43cd72b9 | 9390 | switch (tinsn->insn_type) |
e0001a05 NC |
9391 | { |
9392 | case ITYPE_LITERAL: | |
43cd72b9 BW |
9393 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
9394 | /* Already checked. */ | |
e0001a05 NC |
9395 | assert (lit_frag != NULL); |
9396 | assert (lit_sym != NULL); | |
43cd72b9 BW |
9397 | assert (tinsn->ntok == 1); |
9398 | /* Add a fixup. */ | |
e0001a05 NC |
9399 | target_seg = S_GET_SEGMENT (lit_sym); |
9400 | assert (target_seg); | |
43cd72b9 BW |
9401 | if (tinsn->tok[0].X_op == O_pltrel) |
9402 | reloc_type = BFD_RELOC_XTENSA_PLT; | |
9403 | else | |
9404 | reloc_type = BFD_RELOC_32; | |
e0001a05 | 9405 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 9406 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
9407 | break; |
9408 | ||
9409 | case ITYPE_LABEL: | |
9410 | break; | |
9411 | ||
9412 | case ITYPE_INSN: | |
43cd72b9 BW |
9413 | xg_resolve_labels (tinsn, gen_label); |
9414 | xg_resolve_literals (tinsn, lit_sym); | |
9415 | if (wide_insn && first) | |
9416 | { | |
9417 | first = FALSE; | |
9418 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9419 | { | |
9420 | tinsn->record_fix = TRUE; | |
9421 | orig_vinsn.slots[slot] = *tinsn; | |
9422 | } | |
9423 | else | |
9424 | { | |
9425 | orig_vinsn.slots[slot].opcode = | |
9426 | xtensa_format_slot_nop_opcode (isa, fmt, slot); | |
9427 | orig_vinsn.slots[slot].ntok = 0; | |
9428 | orig_vinsn.slots[slot].record_fix = FALSE; | |
9429 | } | |
9430 | vinsn_to_insnbuf (&orig_vinsn, immed_instr, fragP, TRUE); | |
9431 | xtensa_insnbuf_to_chars (isa, orig_vinsn.insnbuf, | |
d77b99c9 | 9432 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
9433 | fragP->tc_frag_data.is_insn = TRUE; |
9434 | size = xtensa_format_length (isa, fmt); | |
9435 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9436 | { | |
9437 | xtensa_format single_fmt = | |
9438 | xg_get_single_format (tinsn->opcode); | |
9439 | ||
9440 | xg_emit_insn_to_buf | |
9441 | (tinsn, single_fmt, immed_instr + size, fragP, | |
9442 | immed_instr - fragP->fr_literal + size, TRUE); | |
9443 | size += xg_get_single_size (tinsn->opcode); | |
9444 | } | |
9445 | } | |
9446 | else | |
9447 | { | |
9448 | xtensa_format single_format; | |
9449 | size = xg_get_single_size (tinsn->opcode); | |
9450 | single_format = xg_get_single_format (tinsn->opcode); | |
9451 | xg_emit_insn_to_buf (tinsn, single_format, immed_instr, | |
9452 | fragP, | |
9453 | immed_instr - fragP->fr_literal, TRUE); | |
43cd72b9 | 9454 | } |
e0001a05 | 9455 | immed_instr += size; |
43cd72b9 | 9456 | total_size += size; |
e0001a05 NC |
9457 | break; |
9458 | } | |
9459 | } | |
9460 | ||
9461 | diff = total_size - old_size; | |
9462 | assert (diff >= 0); | |
9463 | if (diff != 0) | |
9464 | expanded = TRUE; | |
9465 | assert (diff <= fragP->fr_var); | |
9466 | fragP->fr_var -= diff; | |
9467 | fragP->fr_fix += diff; | |
9468 | } | |
9469 | ||
9470 | /* Clean it up. */ | |
43cd72b9 | 9471 | xg_free_vinsn (&orig_vinsn); |
e0001a05 NC |
9472 | |
9473 | /* Check for undefined immediates in LOOP instructions. */ | |
43cd72b9 | 9474 | if (is_loop) |
e0001a05 NC |
9475 | { |
9476 | symbolS *sym; | |
43cd72b9 | 9477 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
9478 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9479 | { | |
9480 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9481 | return; | |
9482 | } | |
43cd72b9 | 9483 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
9484 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9485 | { | |
9486 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9487 | return; | |
9488 | } | |
9489 | } | |
9490 | ||
43cd72b9 BW |
9491 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
9492 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 9493 | |
43cd72b9 | 9494 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
9495 | { |
9496 | /* Add an expansion note on the expanded instruction. */ | |
9497 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 9498 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 9499 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
9500 | } |
9501 | } | |
9502 | ||
9503 | ||
9504 | /* Add a new fix expression into the desired segment. We have to | |
9505 | switch to that segment to do this. */ | |
9506 | ||
9507 | static fixS * | |
7fa3d080 BW |
9508 | fix_new_exp_in_seg (segT new_seg, |
9509 | subsegT new_subseg, | |
9510 | fragS *frag, | |
9511 | int where, | |
9512 | int size, | |
9513 | expressionS *exp, | |
9514 | int pcrel, | |
9515 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
9516 | { |
9517 | fixS *new_fix; | |
9518 | segT seg = now_seg; | |
9519 | subsegT subseg = now_subseg; | |
43cd72b9 | 9520 | |
e0001a05 NC |
9521 | assert (new_seg != 0); |
9522 | subseg_set (new_seg, new_subseg); | |
9523 | ||
e0001a05 NC |
9524 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
9525 | subseg_set (seg, subseg); | |
9526 | return new_fix; | |
9527 | } | |
9528 | ||
9529 | ||
43cd72b9 BW |
9530 | /* Relax a loop instruction so that it can span loop >256 bytes. |
9531 | ||
9532 | loop as, .L1 | |
9533 | .L0: | |
9534 | rsr as, LEND | |
9535 | wsr as, LBEG | |
9536 | addi as, as, lo8 (label-.L1) | |
9537 | addmi as, as, mid8 (label-.L1) | |
9538 | wsr as, LEND | |
9539 | isync | |
9540 | rsr as, LCOUNT | |
9541 | addi as, as, 1 | |
9542 | .L1: | |
9543 | <<body>> | |
9544 | label: | |
9545 | */ | |
e0001a05 NC |
9546 | |
9547 | static void | |
7fa3d080 | 9548 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
9549 | { |
9550 | TInsn loop_insn; | |
9551 | TInsn addi_insn; | |
9552 | TInsn addmi_insn; | |
9553 | unsigned long target; | |
9554 | static xtensa_insnbuf insnbuf = NULL; | |
9555 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
9556 | xtensa_isa isa = xtensa_default_isa; | |
9557 | addressT loop_offset; | |
9558 | addressT addi_offset = 9; | |
9559 | addressT addmi_offset = 12; | |
43cd72b9 | 9560 | fragS *next_fragP; |
d77b99c9 | 9561 | int target_count; |
e0001a05 NC |
9562 | |
9563 | if (!insnbuf) | |
9564 | insnbuf = xtensa_insnbuf_alloc (isa); | |
9565 | ||
9566 | /* Get the loop offset. */ | |
43cd72b9 | 9567 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 9568 | |
43cd72b9 BW |
9569 | /* Validate that there really is a LOOP at the loop_offset. Because |
9570 | loops are not bundleable, we can assume that the instruction will be | |
9571 | in slot 0. */ | |
9572 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
9573 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
9574 | ||
9575 | assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); | |
e0001a05 NC |
9576 | addi_offset += loop_offset; |
9577 | addmi_offset += loop_offset; | |
9578 | ||
43cd72b9 | 9579 | assert (tinsn->ntok == 2); |
b08b5071 BW |
9580 | if (tinsn->tok[1].X_op == O_constant) |
9581 | target = tinsn->tok[1].X_add_number; | |
9582 | else if (tinsn->tok[1].X_op == O_symbol) | |
9583 | { | |
9584 | /* Find the fragment. */ | |
9585 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9586 | assert (S_GET_SEGMENT (sym) == segP | |
9587 | || S_GET_SEGMENT (sym) == absolute_section); | |
9588 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
9589 | } | |
9590 | else | |
9591 | { | |
9592 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
9593 | target = 0; | |
9594 | } | |
e0001a05 NC |
9595 | |
9596 | know (symbolP); | |
9597 | know (symbolP->sy_frag); | |
9598 | know (!(S_GET_SEGMENT (symbolP) == absolute_section) | |
9599 | || symbol_get_frag (symbolP) == &zero_address_frag); | |
9600 | ||
9601 | loop_length = target - (fragP->fr_address + fragP->fr_fix); | |
9602 | loop_length_hi = loop_length & ~0x0ff; | |
9603 | loop_length_lo = loop_length & 0x0ff; | |
9604 | if (loop_length_lo >= 128) | |
9605 | { | |
9606 | loop_length_lo -= 256; | |
9607 | loop_length_hi += 256; | |
9608 | } | |
9609 | ||
43cd72b9 | 9610 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
9611 | 32512. If the loop is larger than that, then we just fail. */ |
9612 | if (loop_length_hi > 32512) | |
9613 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9614 | _("loop too long for LOOP instruction")); | |
9615 | ||
43cd72b9 | 9616 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
e0001a05 NC |
9617 | assert (addi_insn.opcode == xtensa_addi_opcode); |
9618 | ||
43cd72b9 | 9619 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
e0001a05 NC |
9620 | assert (addmi_insn.opcode == xtensa_addmi_opcode); |
9621 | ||
9622 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
9623 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 9624 | |
e0001a05 | 9625 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
9626 | xtensa_insnbuf_to_chars |
9627 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
9628 | |
9629 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
9630 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
9631 | xtensa_insnbuf_to_chars |
9632 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
9633 | |
9634 | /* Walk through all of the frags from here to the loop end | |
9635 | and mark them as no_transform to keep them from being modified | |
9636 | by the linker. If we ever have a relocation for the | |
9637 | addi/addmi of the difference of two symbols we can remove this. */ | |
9638 | ||
9639 | target_count = 0; | |
9640 | for (next_fragP = fragP; next_fragP != NULL; | |
9641 | next_fragP = next_fragP->fr_next) | |
9642 | { | |
b08b5071 | 9643 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
9644 | if (next_fragP->tc_frag_data.is_loop_target) |
9645 | target_count++; | |
9646 | if (target_count == 2) | |
9647 | break; | |
9648 | } | |
e0001a05 NC |
9649 | } |
9650 | ||
b08b5071 BW |
9651 | \f |
9652 | /* A map that keeps information on a per-subsegment basis. This is | |
9653 | maintained during initial assembly, but is invalid once the | |
9654 | subsegments are smashed together. I.E., it cannot be used during | |
9655 | the relaxation. */ | |
e0001a05 | 9656 | |
b08b5071 | 9657 | typedef struct subseg_map_struct |
e0001a05 | 9658 | { |
b08b5071 BW |
9659 | /* the key */ |
9660 | segT seg; | |
9661 | subsegT subseg; | |
e0001a05 | 9662 | |
b08b5071 BW |
9663 | /* the data */ |
9664 | unsigned flags; | |
9665 | float total_freq; /* fall-through + branch target frequency */ | |
9666 | float target_freq; /* branch target frequency alone */ | |
9667 | ||
9668 | struct subseg_map_struct *next; | |
9669 | } subseg_map; | |
e0001a05 | 9670 | |
e0001a05 | 9671 | |
e0001a05 NC |
9672 | static subseg_map *sseg_map = NULL; |
9673 | ||
43cd72b9 | 9674 | static subseg_map * |
7fa3d080 | 9675 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
9676 | { |
9677 | subseg_map *subseg_e; | |
9678 | ||
9679 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 9680 | { |
43cd72b9 | 9681 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 9682 | break; |
e0001a05 | 9683 | } |
b08b5071 BW |
9684 | return subseg_e; |
9685 | } | |
9686 | ||
9687 | ||
9688 | static subseg_map * | |
9689 | add_subseg_info (segT seg, subsegT subseg) | |
9690 | { | |
9691 | subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); | |
43cd72b9 BW |
9692 | memset (subseg_e, 0, sizeof (subseg_map)); |
9693 | subseg_e->seg = seg; | |
9694 | subseg_e->subseg = subseg; | |
9695 | subseg_e->flags = 0; | |
9696 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
9697 | subseg_e->target_freq = 1.0; |
9698 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
9699 | subseg_e->next = sseg_map; |
9700 | sseg_map = subseg_e; | |
43cd72b9 BW |
9701 | return subseg_e; |
9702 | } | |
e0001a05 | 9703 | |
7fa3d080 BW |
9704 | |
9705 | static unsigned | |
9706 | get_last_insn_flags (segT seg, subsegT subseg) | |
9707 | { | |
9708 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9709 | if (subseg_e) |
9710 | return subseg_e->flags; | |
9711 | return 0; | |
7fa3d080 BW |
9712 | } |
9713 | ||
9714 | ||
43cd72b9 | 9715 | static void |
7fa3d080 BW |
9716 | set_last_insn_flags (segT seg, |
9717 | subsegT subseg, | |
9718 | unsigned fl, | |
9719 | bfd_boolean val) | |
43cd72b9 BW |
9720 | { |
9721 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9722 | if (! subseg_e) |
9723 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
9724 | if (val) |
9725 | subseg_e->flags |= fl; | |
9726 | else | |
9727 | subseg_e->flags &= ~fl; | |
9728 | } | |
9729 | ||
b08b5071 BW |
9730 | |
9731 | static float | |
9732 | get_subseg_total_freq (segT seg, subsegT subseg) | |
9733 | { | |
9734 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9735 | if (subseg_e) | |
9736 | return subseg_e->total_freq; | |
9737 | return 1.0; | |
9738 | } | |
9739 | ||
9740 | ||
9741 | static float | |
9742 | get_subseg_target_freq (segT seg, subsegT subseg) | |
9743 | { | |
9744 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9745 | if (subseg_e) | |
9746 | return subseg_e->target_freq; | |
9747 | return 1.0; | |
9748 | } | |
9749 | ||
9750 | ||
9751 | static void | |
9752 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
9753 | { | |
9754 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9755 | if (! subseg_e) | |
9756 | subseg_e = add_subseg_info (seg, subseg); | |
9757 | subseg_e->total_freq = total_f; | |
9758 | subseg_e->target_freq = target_f; | |
9759 | } | |
9760 | ||
e0001a05 NC |
9761 | \f |
9762 | /* Segment Lists and emit_state Stuff. */ | |
9763 | ||
9764 | /* Remove the segment from the global sections list. */ | |
9765 | ||
9766 | static void | |
7fa3d080 | 9767 | xtensa_remove_section (segT sec) |
e0001a05 NC |
9768 | { |
9769 | /* Handle brain-dead bfd_section_list_remove macro, which | |
9770 | expect the address of the prior section's "next" field, not | |
9771 | just the address of the section to remove. */ | |
9772 | ||
9773 | segT *ps_next_ptr = &stdoutput->sections; | |
9774 | while (*ps_next_ptr != sec && *ps_next_ptr != NULL) | |
9775 | ps_next_ptr = &(*ps_next_ptr)->next; | |
9776 | ||
9777 | assert (*ps_next_ptr != NULL); | |
9778 | ||
9779 | bfd_section_list_remove (stdoutput, ps_next_ptr); | |
9780 | } | |
9781 | ||
9782 | ||
9783 | static void | |
7fa3d080 | 9784 | xtensa_insert_section (segT after_sec, segT sec) |
e0001a05 NC |
9785 | { |
9786 | segT *after_sec_next; | |
9787 | if (after_sec == NULL) | |
9788 | after_sec_next = &stdoutput->sections; | |
9789 | else | |
9790 | after_sec_next = &after_sec->next; | |
9791 | ||
9792 | bfd_section_list_insert (stdoutput, after_sec_next, sec); | |
9793 | } | |
9794 | ||
9795 | ||
9796 | static void | |
7fa3d080 | 9797 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
9798 | { |
9799 | head = head->next; | |
9800 | while (head) | |
9801 | { | |
9802 | segT literal_section = head->seg; | |
9803 | ||
9804 | /* Move the literal section to the front of the section list. */ | |
9805 | assert (literal_section); | |
9806 | xtensa_remove_section (literal_section); | |
9807 | xtensa_insert_section (NULL, literal_section); | |
9808 | ||
9809 | head = head->next; | |
9810 | } | |
9811 | } | |
9812 | ||
9813 | ||
7fa3d080 BW |
9814 | static void mark_literal_frags (seg_list *); |
9815 | ||
9816 | static void | |
9817 | xtensa_move_literals (void) | |
e0001a05 NC |
9818 | { |
9819 | seg_list *segment; | |
9820 | frchainS *frchain_from, *frchain_to; | |
9821 | fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after; | |
9822 | fragS **frag_splice; | |
9823 | emit_state state; | |
9824 | segT dest_seg; | |
9825 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 9826 | sym_list *lit; |
e0001a05 | 9827 | |
a7877748 BW |
9828 | mark_literal_frags (literal_head->next); |
9829 | mark_literal_frags (init_literal_head->next); | |
9830 | mark_literal_frags (fini_literal_head->next); | |
e0001a05 NC |
9831 | |
9832 | if (use_literal_section) | |
9833 | return; | |
9834 | ||
9835 | segment = literal_head->next; | |
9836 | while (segment) | |
9837 | { | |
9838 | frchain_from = seg_info (segment->seg)->frchainP; | |
9839 | search_frag = frchain_from->frch_root; | |
9840 | literal_pool = NULL; | |
9841 | frchain_to = NULL; | |
9842 | frag_splice = &(frchain_from->frch_root); | |
9843 | ||
9844 | while (!search_frag->tc_frag_data.literal_frag) | |
9845 | { | |
9846 | assert (search_frag->fr_fix == 0 | |
9847 | || search_frag->fr_type == rs_align); | |
9848 | search_frag = search_frag->fr_next; | |
9849 | } | |
9850 | ||
9851 | assert (search_frag->tc_frag_data.literal_frag->fr_subtype | |
9852 | == RELAX_LITERAL_POOL_BEGIN); | |
9853 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
9854 | ||
9855 | /* Make sure that all the frags in this series are closed, and | |
9856 | that there is at least one left over of zero-size. This | |
9857 | prevents us from making a segment with an frchain without any | |
9858 | frags in it. */ | |
9859 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9860 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
9861 | last_frag = frag_now; |
9862 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9863 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 9864 | |
43cd72b9 | 9865 | while (search_frag != frag_now) |
e0001a05 NC |
9866 | { |
9867 | next_frag = search_frag->fr_next; | |
9868 | ||
43cd72b9 | 9869 | /* First, move the frag out of the literal section and |
e0001a05 NC |
9870 | to the appropriate place. */ |
9871 | if (search_frag->tc_frag_data.literal_frag) | |
9872 | { | |
9873 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9874 | assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); | |
dd49a749 BW |
9875 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9876 | assert (frchain_to); | |
e0001a05 NC |
9877 | } |
9878 | insert_after = literal_pool; | |
43cd72b9 | 9879 | |
e0001a05 NC |
9880 | while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END) |
9881 | insert_after = insert_after->fr_next; | |
9882 | ||
dd49a749 | 9883 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
43cd72b9 | 9884 | |
e0001a05 NC |
9885 | *frag_splice = next_frag; |
9886 | search_frag->fr_next = insert_after->fr_next; | |
9887 | insert_after->fr_next = search_frag; | |
9888 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
9889 | ||
9890 | /* Now move any fixups associated with this frag to the | |
9891 | right section. */ | |
9892 | fix = frchain_from->fix_root; | |
9893 | fix_splice = &(frchain_from->fix_root); | |
9894 | while (fix) | |
9895 | { | |
9896 | next_fix = fix->fx_next; | |
9897 | if (fix->fx_frag == search_frag) | |
9898 | { | |
9899 | *fix_splice = next_fix; | |
9900 | fix->fx_next = frchain_to->fix_root; | |
9901 | frchain_to->fix_root = fix; | |
9902 | if (frchain_to->fix_tail == NULL) | |
9903 | frchain_to->fix_tail = fix; | |
9904 | } | |
9905 | else | |
9906 | fix_splice = &(fix->fx_next); | |
9907 | fix = next_fix; | |
9908 | } | |
9909 | search_frag = next_frag; | |
9910 | } | |
9911 | ||
9912 | if (frchain_from->fix_root != NULL) | |
9913 | { | |
9914 | frchain_from = seg_info (segment->seg)->frchainP; | |
9915 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
9916 | ||
9917 | assert (frchain_from->fix_root == NULL); | |
9918 | } | |
9919 | frchain_from->fix_tail = NULL; | |
9920 | xtensa_restore_emit_state (&state); | |
9921 | segment = segment->next; | |
9922 | } | |
9923 | ||
82e7541d BW |
9924 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
9925 | for (lit = literal_syms; lit; lit = lit->next) | |
9926 | { | |
9927 | symbolS *lit_sym = lit->sym; | |
9928 | segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; | |
43cd72b9 BW |
9929 | if (dest_seg) |
9930 | S_SET_SEGMENT (lit_sym, dest_seg); | |
82e7541d | 9931 | } |
e0001a05 NC |
9932 | } |
9933 | ||
9934 | ||
a7877748 BW |
9935 | /* Walk over all the frags for segments in a list and mark them as |
9936 | containing literals. As clunky as this is, we can't rely on frag_var | |
9937 | and frag_variant to get called in all situations. */ | |
9938 | ||
9939 | static void | |
7fa3d080 | 9940 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
9941 | { |
9942 | frchainS *frchain_from; | |
9943 | fragS *search_frag; | |
9944 | ||
9945 | while (segment) | |
9946 | { | |
9947 | frchain_from = seg_info (segment->seg)->frchainP; | |
9948 | search_frag = frchain_from->frch_root; | |
9949 | while (search_frag) | |
9950 | { | |
9951 | search_frag->tc_frag_data.is_literal = TRUE; | |
9952 | search_frag = search_frag->fr_next; | |
9953 | } | |
9954 | segment = segment->next; | |
9955 | } | |
9956 | } | |
9957 | ||
9958 | ||
e0001a05 | 9959 | static void |
7fa3d080 | 9960 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
9961 | { |
9962 | /* Move all of the sections in the section list to come | |
9963 | after "after" in the gnu segment list. */ | |
9964 | ||
9965 | head = head->next; | |
9966 | while (head) | |
9967 | { | |
9968 | segT literal_section = head->seg; | |
9969 | ||
9970 | /* Move the literal section after "after". */ | |
9971 | assert (literal_section); | |
9972 | if (literal_section != after) | |
9973 | { | |
9974 | xtensa_remove_section (literal_section); | |
9975 | xtensa_insert_section (after, literal_section); | |
9976 | } | |
9977 | ||
9978 | head = head->next; | |
9979 | } | |
9980 | } | |
9981 | ||
9982 | ||
9983 | /* Push all the literal segments to the end of the gnu list. */ | |
9984 | ||
7fa3d080 BW |
9985 | static void |
9986 | xtensa_reorder_segments (void) | |
e0001a05 NC |
9987 | { |
9988 | segT sec; | |
b08b5071 | 9989 | segT last_sec = 0; |
e0001a05 NC |
9990 | int old_count = 0; |
9991 | int new_count = 0; | |
9992 | ||
9993 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
9994 | { |
9995 | last_sec = sec; | |
9996 | old_count++; | |
9997 | } | |
e0001a05 NC |
9998 | |
9999 | /* Now that we have the last section, push all the literal | |
10000 | sections to the end. */ | |
e0001a05 NC |
10001 | xtensa_reorder_seg_list (literal_head, last_sec); |
10002 | xtensa_reorder_seg_list (init_literal_head, last_sec); | |
10003 | xtensa_reorder_seg_list (fini_literal_head, last_sec); | |
10004 | ||
10005 | /* Now perform the final error check. */ | |
10006 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
10007 | new_count++; | |
10008 | assert (new_count == old_count); | |
10009 | } | |
10010 | ||
10011 | ||
e0001a05 NC |
10012 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
10013 | correct location. Return a emit_state which can be passed to | |
10014 | xtensa_restore_emit_state to return to current fragment. */ | |
10015 | ||
7fa3d080 BW |
10016 | static void |
10017 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
10018 | { |
10019 | if (directive_state[directive_absolute_literals]) | |
10020 | { | |
10021 | cache_literal_section (0, default_lit_sections.lit4_seg_name, | |
10022 | &default_lit_sections.lit4_seg, FALSE); | |
10023 | xtensa_switch_section_emit_state (result, | |
10024 | default_lit_sections.lit4_seg, 0); | |
10025 | } | |
10026 | else | |
10027 | xtensa_switch_to_non_abs_literal_fragment (result); | |
10028 | ||
10029 | /* Do a 4-byte align here. */ | |
10030 | frag_align (2, 0, 0); | |
10031 | record_alignment (now_seg, 2); | |
10032 | } | |
10033 | ||
10034 | ||
7fa3d080 BW |
10035 | static void |
10036 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 NC |
10037 | { |
10038 | /* When we mark a literal pool location, we want to put a frag in | |
10039 | the literal pool that points to it. But to do that, we want to | |
10040 | switch_to_literal_fragment. But literal sections don't have | |
10041 | literal pools, so their location is always null, so we would | |
10042 | recurse forever. This is kind of hacky, but it works. */ | |
10043 | ||
10044 | static bfd_boolean recursive = FALSE; | |
10045 | fragS *pool_location = get_literal_pool_location (now_seg); | |
10046 | bfd_boolean is_init = | |
10047 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); | |
10048 | ||
10049 | bfd_boolean is_fini = | |
10050 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); | |
e0001a05 | 10051 | |
43cd72b9 BW |
10052 | if (pool_location == NULL |
10053 | && !use_literal_section | |
e0001a05 NC |
10054 | && !recursive |
10055 | && !is_init && ! is_fini) | |
10056 | { | |
43cd72b9 | 10057 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); |
e0001a05 | 10058 | recursive = TRUE; |
61846f28 | 10059 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
10060 | recursive = FALSE; |
10061 | } | |
10062 | ||
10063 | /* Special case: If we are in the ".fini" or ".init" section, then | |
10064 | we will ALWAYS be generating to the ".fini.literal" and | |
10065 | ".init.literal" sections. */ | |
10066 | ||
10067 | if (is_init) | |
10068 | { | |
10069 | cache_literal_section (init_literal_head, | |
10070 | default_lit_sections.init_lit_seg_name, | |
43cd72b9 | 10071 | &default_lit_sections.init_lit_seg, TRUE); |
e0001a05 NC |
10072 | xtensa_switch_section_emit_state (result, |
10073 | default_lit_sections.init_lit_seg, 0); | |
10074 | } | |
10075 | else if (is_fini) | |
10076 | { | |
10077 | cache_literal_section (fini_literal_head, | |
10078 | default_lit_sections.fini_lit_seg_name, | |
43cd72b9 | 10079 | &default_lit_sections.fini_lit_seg, TRUE); |
e0001a05 NC |
10080 | xtensa_switch_section_emit_state (result, |
10081 | default_lit_sections.fini_lit_seg, 0); | |
10082 | } | |
43cd72b9 | 10083 | else |
e0001a05 NC |
10084 | { |
10085 | cache_literal_section (literal_head, | |
10086 | default_lit_sections.lit_seg_name, | |
43cd72b9 | 10087 | &default_lit_sections.lit_seg, TRUE); |
e0001a05 NC |
10088 | xtensa_switch_section_emit_state (result, |
10089 | default_lit_sections.lit_seg, 0); | |
10090 | } | |
10091 | ||
43cd72b9 BW |
10092 | if (!use_literal_section |
10093 | && !is_init && !is_fini | |
10094 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
10095 | { |
10096 | /* Close whatever frag is there. */ | |
10097 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10098 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
10099 | frag_now->tc_frag_data.literal_frag = pool_location; |
10100 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 10101 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 10102 | } |
e0001a05 NC |
10103 | } |
10104 | ||
10105 | ||
10106 | /* Call this function before emitting data into the literal section. | |
10107 | This is a helper function for xtensa_switch_to_literal_fragment. | |
10108 | This is similar to a .section new_now_seg subseg. */ | |
10109 | ||
7fa3d080 BW |
10110 | static void |
10111 | xtensa_switch_section_emit_state (emit_state *state, | |
10112 | segT new_now_seg, | |
10113 | subsegT new_now_subseg) | |
e0001a05 NC |
10114 | { |
10115 | state->name = now_seg->name; | |
10116 | state->now_seg = now_seg; | |
10117 | state->now_subseg = now_subseg; | |
10118 | state->generating_literals = generating_literals; | |
10119 | generating_literals++; | |
2b0210eb | 10120 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
10121 | } |
10122 | ||
10123 | ||
10124 | /* Use to restore the emitting into the normal place. */ | |
10125 | ||
7fa3d080 BW |
10126 | static void |
10127 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
10128 | { |
10129 | generating_literals = state->generating_literals; | |
2b0210eb | 10130 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
10131 | } |
10132 | ||
10133 | ||
10134 | /* Get a segment of a given name. If the segment is already | |
10135 | present, return it; otherwise, create a new one. */ | |
10136 | ||
10137 | static void | |
7fa3d080 BW |
10138 | cache_literal_section (seg_list *head, |
10139 | const char *name, | |
b08b5071 | 10140 | segT *pseg, |
7fa3d080 | 10141 | bfd_boolean is_code) |
e0001a05 NC |
10142 | { |
10143 | segT current_section = now_seg; | |
10144 | int current_subsec = now_subseg; | |
b08b5071 | 10145 | segT seg; |
e0001a05 | 10146 | |
b08b5071 | 10147 | if (*pseg != 0) |
e0001a05 | 10148 | return; |
e0001a05 | 10149 | |
b08b5071 BW |
10150 | /* Check if the named section exists. */ |
10151 | for (seg = stdoutput->sections; seg; seg = seg->next) | |
10152 | { | |
10153 | if (!strcmp (segment_name (seg), name)) | |
10154 | break; | |
10155 | } | |
e0001a05 | 10156 | |
b08b5071 | 10157 | if (!seg) |
e0001a05 | 10158 | { |
b08b5071 BW |
10159 | /* Create a new literal section. */ |
10160 | seg = subseg_new (name, (subsegT) 0); | |
43cd72b9 | 10161 | if (head) |
b08b5071 BW |
10162 | { |
10163 | /* Add the newly created literal segment to the specified list. */ | |
10164 | seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); | |
10165 | n->seg = seg; | |
10166 | n->next = head->next; | |
10167 | head->next = n; | |
10168 | } | |
10169 | bfd_set_section_flags (stdoutput, seg, SEC_HAS_CONTENTS | | |
43cd72b9 BW |
10170 | SEC_READONLY | SEC_ALLOC | SEC_LOAD |
10171 | | (is_code ? SEC_CODE : SEC_DATA)); | |
b08b5071 | 10172 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
10173 | } |
10174 | ||
b08b5071 BW |
10175 | *pseg = seg; |
10176 | subseg_set (current_section, current_subsec); | |
e0001a05 NC |
10177 | } |
10178 | ||
43cd72b9 BW |
10179 | \f |
10180 | /* Property Tables Stuff. */ | |
10181 | ||
7fa3d080 BW |
10182 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
10183 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
10184 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
10185 | ||
10186 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
10187 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
10188 | ||
b08b5071 | 10189 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
10190 | static void xtensa_create_property_segments |
10191 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
10192 | static void xtensa_create_xproperty_segments | |
10193 | (frag_flags_fn, const char *, xt_section_type); | |
10194 | static segment_info_type *retrieve_segment_info (segT); | |
10195 | static segT retrieve_xtensa_section (char *); | |
10196 | static bfd_boolean section_has_property (segT, frag_predicate); | |
10197 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
10198 | static void add_xt_block_frags | |
10199 | (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate); | |
10200 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); | |
10201 | static void xtensa_frag_flags_init (frag_flags *); | |
10202 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
10203 | static bfd_vma frag_flags_to_number (const frag_flags *); | |
10204 | static void add_xt_prop_frags | |
10205 | (segT, segT, xtensa_block_info **, frag_flags_fn); | |
10206 | ||
10207 | /* Set up property tables after relaxation. */ | |
10208 | ||
10209 | void | |
10210 | xtensa_post_relax_hook (void) | |
10211 | { | |
10212 | xtensa_move_seg_list_to_beginning (literal_head); | |
10213 | xtensa_move_seg_list_to_beginning (init_literal_head); | |
10214 | xtensa_move_seg_list_to_beginning (fini_literal_head); | |
10215 | ||
10216 | xtensa_find_unmarked_state_frags (); | |
10217 | ||
10218 | if (use_literal_section) | |
10219 | xtensa_create_property_segments (get_frag_is_literal, | |
10220 | NULL, | |
10221 | XTENSA_LIT_SEC_NAME, | |
10222 | xt_literal_sec); | |
10223 | xtensa_create_xproperty_segments (get_frag_property_flags, | |
10224 | XTENSA_PROP_SEC_NAME, | |
10225 | xt_prop_sec); | |
10226 | ||
10227 | if (warn_unaligned_branch_targets) | |
10228 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
10229 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
10230 | } | |
10231 | ||
10232 | ||
43cd72b9 BW |
10233 | /* This function is only meaningful after xtensa_move_literals. */ |
10234 | ||
10235 | static bfd_boolean | |
7fa3d080 | 10236 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 BW |
10237 | { |
10238 | assert (fragP != NULL); | |
10239 | return fragP->tc_frag_data.is_literal; | |
10240 | } | |
10241 | ||
10242 | ||
43cd72b9 | 10243 | static void |
7fa3d080 BW |
10244 | xtensa_create_property_segments (frag_predicate property_function, |
10245 | frag_predicate end_property_function, | |
10246 | const char *section_name_base, | |
10247 | xt_section_type sec_type) | |
43cd72b9 BW |
10248 | { |
10249 | segT *seclist; | |
10250 | ||
10251 | /* Walk over all of the current segments. | |
10252 | Walk over each fragment | |
10253 | For each non-empty fragment, | |
10254 | Build a property record (append where possible). */ | |
10255 | ||
10256 | for (seclist = &stdoutput->sections; | |
10257 | seclist && *seclist; | |
10258 | seclist = &(*seclist)->next) | |
10259 | { | |
10260 | segT sec = *seclist; | |
10261 | flagword flags; | |
10262 | ||
10263 | flags = bfd_get_section_flags (stdoutput, sec); | |
10264 | if (flags & SEC_DEBUGGING) | |
10265 | continue; | |
10266 | if (!(flags & SEC_ALLOC)) | |
10267 | continue; | |
10268 | ||
10269 | if (section_has_property (sec, property_function)) | |
10270 | { | |
10271 | char *property_section_name = | |
10272 | xtensa_get_property_section_name (sec, section_name_base); | |
10273 | segT insn_sec = retrieve_xtensa_section (property_section_name); | |
10274 | segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); | |
10275 | xtensa_block_info **xt_blocks = | |
10276 | &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10277 | /* Walk over all of the frchains here and add new sections. */ | |
10278 | add_xt_block_frags (sec, insn_sec, xt_blocks, property_function, | |
10279 | end_property_function); | |
10280 | } | |
10281 | } | |
10282 | ||
10283 | /* Now we fill them out.... */ | |
10284 | ||
10285 | for (seclist = &stdoutput->sections; | |
10286 | seclist && *seclist; | |
10287 | seclist = &(*seclist)->next) | |
10288 | { | |
10289 | segment_info_type *seginfo; | |
10290 | xtensa_block_info *block; | |
10291 | segT sec = *seclist; | |
10292 | ||
10293 | seginfo = seg_info (sec); | |
10294 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10295 | ||
10296 | if (block) | |
10297 | { | |
10298 | xtensa_block_info *cur_block; | |
10299 | /* This is a section with some data. */ | |
10300 | int num_recs = 0; | |
d77b99c9 | 10301 | bfd_size_type rec_size; |
43cd72b9 BW |
10302 | |
10303 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10304 | num_recs++; | |
10305 | ||
10306 | rec_size = num_recs * 8; | |
10307 | bfd_set_section_size (stdoutput, sec, rec_size); | |
10308 | ||
10309 | /* In order to make this work with the assembler, we have to | |
10310 | build some frags and then build the "fixups" for it. It | |
10311 | would be easier to just set the contents then set the | |
10312 | arlents. */ | |
10313 | ||
10314 | if (num_recs) | |
10315 | { | |
10316 | /* Allocate a fragment and leak it. */ | |
10317 | fragS *fragP; | |
d77b99c9 | 10318 | bfd_size_type frag_size; |
43cd72b9 BW |
10319 | fixS *fixes; |
10320 | frchainS *frchainP; | |
10321 | int i; | |
10322 | char *frag_data; | |
10323 | ||
10324 | frag_size = sizeof (fragS) + rec_size; | |
10325 | fragP = (fragS *) xmalloc (frag_size); | |
e0001a05 | 10326 | |
43cd72b9 BW |
10327 | memset (fragP, 0, frag_size); |
10328 | fragP->fr_address = 0; | |
10329 | fragP->fr_next = NULL; | |
10330 | fragP->fr_fix = rec_size; | |
10331 | fragP->fr_var = 0; | |
10332 | fragP->fr_type = rs_fill; | |
10333 | /* The rest are zeros. */ | |
e0001a05 | 10334 | |
43cd72b9 BW |
10335 | frchainP = seginfo->frchainP; |
10336 | frchainP->frch_root = fragP; | |
10337 | frchainP->frch_last = fragP; | |
e0001a05 | 10338 | |
43cd72b9 BW |
10339 | fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); |
10340 | memset (fixes, 0, sizeof (fixS) * num_recs); | |
e0001a05 | 10341 | |
43cd72b9 BW |
10342 | seginfo->fix_root = fixes; |
10343 | seginfo->fix_tail = &fixes[num_recs - 1]; | |
10344 | cur_block = block; | |
10345 | frag_data = &fragP->fr_literal[0]; | |
10346 | for (i = 0; i < num_recs; i++) | |
10347 | { | |
10348 | fixS *fix = &fixes[i]; | |
10349 | assert (cur_block); | |
e0001a05 | 10350 | |
43cd72b9 BW |
10351 | /* Write the fixup. */ |
10352 | if (i != num_recs - 1) | |
10353 | fix->fx_next = &fixes[i + 1]; | |
10354 | else | |
10355 | fix->fx_next = NULL; | |
10356 | fix->fx_size = 4; | |
10357 | fix->fx_done = 0; | |
10358 | fix->fx_frag = fragP; | |
10359 | fix->fx_where = i * 8; | |
10360 | fix->fx_addsy = section_symbol (cur_block->sec); | |
10361 | fix->fx_offset = cur_block->offset; | |
10362 | fix->fx_r_type = BFD_RELOC_32; | |
10363 | fix->fx_file = "Internal Assembly"; | |
10364 | fix->fx_line = 0; | |
e0001a05 | 10365 | |
43cd72b9 BW |
10366 | /* Write the length. */ |
10367 | md_number_to_chars (&frag_data[4 + 8 * i], | |
10368 | cur_block->size, 4); | |
10369 | cur_block = cur_block->next; | |
10370 | } | |
10371 | } | |
10372 | } | |
10373 | } | |
e0001a05 NC |
10374 | } |
10375 | ||
10376 | ||
7fa3d080 BW |
10377 | static void |
10378 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
10379 | const char *section_name_base, | |
10380 | xt_section_type sec_type) | |
e0001a05 NC |
10381 | { |
10382 | segT *seclist; | |
10383 | ||
10384 | /* Walk over all of the current segments. | |
43cd72b9 BW |
10385 | Walk over each fragment. |
10386 | For each fragment that has instructions, | |
10387 | build an instruction record (append where possible). */ | |
e0001a05 NC |
10388 | |
10389 | for (seclist = &stdoutput->sections; | |
10390 | seclist && *seclist; | |
10391 | seclist = &(*seclist)->next) | |
10392 | { | |
10393 | segT sec = *seclist; | |
43cd72b9 BW |
10394 | flagword flags; |
10395 | ||
10396 | flags = bfd_get_section_flags (stdoutput, sec); | |
6624cbde BW |
10397 | if ((flags & SEC_DEBUGGING) |
10398 | || !(flags & SEC_ALLOC) | |
10399 | || (flags & SEC_MERGE)) | |
43cd72b9 BW |
10400 | continue; |
10401 | ||
10402 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 10403 | { |
b614a702 BW |
10404 | char *property_section_name = |
10405 | xtensa_get_property_section_name (sec, section_name_base); | |
e0001a05 NC |
10406 | segT insn_sec = retrieve_xtensa_section (property_section_name); |
10407 | segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); | |
43cd72b9 | 10408 | xtensa_block_info **xt_blocks = |
e0001a05 NC |
10409 | &xt_seg_info->tc_segment_info_data.blocks[sec_type]; |
10410 | /* Walk over all of the frchains here and add new sections. */ | |
43cd72b9 | 10411 | add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn); |
e0001a05 NC |
10412 | } |
10413 | } | |
10414 | ||
10415 | /* Now we fill them out.... */ | |
10416 | ||
10417 | for (seclist = &stdoutput->sections; | |
10418 | seclist && *seclist; | |
10419 | seclist = &(*seclist)->next) | |
10420 | { | |
10421 | segment_info_type *seginfo; | |
10422 | xtensa_block_info *block; | |
10423 | segT sec = *seclist; | |
43cd72b9 | 10424 | |
e0001a05 NC |
10425 | seginfo = seg_info (sec); |
10426 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10427 | ||
10428 | if (block) | |
10429 | { | |
10430 | xtensa_block_info *cur_block; | |
10431 | /* This is a section with some data. */ | |
43cd72b9 | 10432 | int num_recs = 0; |
d77b99c9 | 10433 | bfd_size_type rec_size; |
e0001a05 NC |
10434 | |
10435 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10436 | num_recs++; | |
10437 | ||
43cd72b9 | 10438 | rec_size = num_recs * (8 + 4); |
e0001a05 NC |
10439 | bfd_set_section_size (stdoutput, sec, rec_size); |
10440 | ||
43cd72b9 BW |
10441 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
10442 | ||
10443 | /* In order to make this work with the assembler, we have to build | |
10444 | some frags then build the "fixups" for it. It would be easier to | |
10445 | just set the contents then set the arlents. */ | |
e0001a05 NC |
10446 | |
10447 | if (num_recs) | |
10448 | { | |
43cd72b9 | 10449 | /* Allocate a fragment and (unfortunately) leak it. */ |
e0001a05 | 10450 | fragS *fragP; |
d77b99c9 | 10451 | bfd_size_type frag_size; |
e0001a05 NC |
10452 | fixS *fixes; |
10453 | frchainS *frchainP; | |
43cd72b9 | 10454 | int i; |
e0001a05 NC |
10455 | char *frag_data; |
10456 | ||
10457 | frag_size = sizeof (fragS) + rec_size; | |
10458 | fragP = (fragS *) xmalloc (frag_size); | |
10459 | ||
10460 | memset (fragP, 0, frag_size); | |
10461 | fragP->fr_address = 0; | |
10462 | fragP->fr_next = NULL; | |
10463 | fragP->fr_fix = rec_size; | |
10464 | fragP->fr_var = 0; | |
10465 | fragP->fr_type = rs_fill; | |
43cd72b9 | 10466 | /* The rest are zeros. */ |
e0001a05 NC |
10467 | |
10468 | frchainP = seginfo->frchainP; | |
10469 | frchainP->frch_root = fragP; | |
10470 | frchainP->frch_last = fragP; | |
10471 | ||
10472 | fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); | |
10473 | memset (fixes, 0, sizeof (fixS) * num_recs); | |
10474 | ||
10475 | seginfo->fix_root = fixes; | |
10476 | seginfo->fix_tail = &fixes[num_recs - 1]; | |
10477 | cur_block = block; | |
10478 | frag_data = &fragP->fr_literal[0]; | |
10479 | for (i = 0; i < num_recs; i++) | |
10480 | { | |
10481 | fixS *fix = &fixes[i]; | |
10482 | assert (cur_block); | |
10483 | ||
10484 | /* Write the fixup. */ | |
10485 | if (i != num_recs - 1) | |
10486 | fix->fx_next = &fixes[i + 1]; | |
10487 | else | |
10488 | fix->fx_next = NULL; | |
10489 | fix->fx_size = 4; | |
10490 | fix->fx_done = 0; | |
10491 | fix->fx_frag = fragP; | |
43cd72b9 | 10492 | fix->fx_where = i * (8 + 4); |
e0001a05 NC |
10493 | fix->fx_addsy = section_symbol (cur_block->sec); |
10494 | fix->fx_offset = cur_block->offset; | |
10495 | fix->fx_r_type = BFD_RELOC_32; | |
10496 | fix->fx_file = "Internal Assembly"; | |
10497 | fix->fx_line = 0; | |
10498 | ||
10499 | /* Write the length. */ | |
43cd72b9 | 10500 | md_number_to_chars (&frag_data[4 + (8+4) * i], |
e0001a05 | 10501 | cur_block->size, 4); |
43cd72b9 BW |
10502 | md_number_to_chars (&frag_data[8 + (8+4) * i], |
10503 | frag_flags_to_number (&cur_block->flags), | |
10504 | 4); | |
e0001a05 NC |
10505 | cur_block = cur_block->next; |
10506 | } | |
10507 | } | |
10508 | } | |
10509 | } | |
10510 | } | |
10511 | ||
10512 | ||
7fa3d080 BW |
10513 | static segment_info_type * |
10514 | retrieve_segment_info (segT seg) | |
e0001a05 NC |
10515 | { |
10516 | segment_info_type *seginfo; | |
10517 | seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg); | |
10518 | if (!seginfo) | |
10519 | { | |
10520 | frchainS *frchainP; | |
10521 | ||
10522 | seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo)); | |
7fa3d080 | 10523 | memset ((void *) seginfo, 0, sizeof (*seginfo)); |
e0001a05 NC |
10524 | seginfo->fix_root = NULL; |
10525 | seginfo->fix_tail = NULL; | |
10526 | seginfo->bfd_section = seg; | |
10527 | seginfo->sym = 0; | |
10528 | /* We will not be dealing with these, only our special ones. */ | |
65ec77d2 | 10529 | bfd_set_section_userdata (stdoutput, seg, (void *) seginfo); |
e0001a05 NC |
10530 | |
10531 | frchainP = (frchainS *) xmalloc (sizeof (frchainS)); | |
10532 | frchainP->frch_root = NULL; | |
10533 | frchainP->frch_last = NULL; | |
10534 | frchainP->frch_next = NULL; | |
10535 | frchainP->frch_seg = seg; | |
10536 | frchainP->frch_subseg = 0; | |
10537 | frchainP->fix_root = NULL; | |
10538 | frchainP->fix_tail = NULL; | |
10539 | /* Do not init the objstack. */ | |
10540 | /* obstack_begin (&frchainP->frch_obstack, chunksize); */ | |
10541 | /* frchainP->frch_frag_now = fragP; */ | |
10542 | frchainP->frch_frag_now = NULL; | |
10543 | ||
10544 | seginfo->frchainP = frchainP; | |
10545 | } | |
10546 | ||
10547 | return seginfo; | |
10548 | } | |
10549 | ||
10550 | ||
7fa3d080 BW |
10551 | static segT |
10552 | retrieve_xtensa_section (char *sec_name) | |
e0001a05 NC |
10553 | { |
10554 | bfd *abfd = stdoutput; | |
10555 | flagword flags, out_flags, link_once_flags; | |
10556 | segT s; | |
10557 | ||
10558 | flags = bfd_get_section_flags (abfd, now_seg); | |
10559 | link_once_flags = (flags & SEC_LINK_ONCE); | |
10560 | if (link_once_flags) | |
10561 | link_once_flags |= (flags & SEC_LINK_DUPLICATES); | |
10562 | out_flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY | link_once_flags); | |
10563 | ||
10564 | s = bfd_make_section_old_way (abfd, sec_name); | |
10565 | if (s == NULL) | |
10566 | as_bad (_("could not create section %s"), sec_name); | |
10567 | if (!bfd_set_section_flags (abfd, s, out_flags)) | |
10568 | as_bad (_("invalid flag combination on section %s"), sec_name); | |
10569 | ||
10570 | return s; | |
10571 | } | |
10572 | ||
10573 | ||
7fa3d080 BW |
10574 | static bfd_boolean |
10575 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
10576 | { |
10577 | segment_info_type *seginfo = seg_info (sec); | |
10578 | fragS *fragP; | |
10579 | ||
10580 | if (seginfo && seginfo->frchainP) | |
10581 | { | |
10582 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10583 | { | |
10584 | if (property_function (fragP) | |
10585 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10586 | return TRUE; | |
10587 | } | |
10588 | } | |
10589 | return FALSE; | |
10590 | } | |
10591 | ||
10592 | ||
7fa3d080 BW |
10593 | static bfd_boolean |
10594 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
10595 | { |
10596 | segment_info_type *seginfo = seg_info (sec); | |
10597 | fragS *fragP; | |
10598 | ||
10599 | if (seginfo && seginfo->frchainP) | |
10600 | { | |
10601 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10602 | { | |
10603 | frag_flags prop_flags; | |
10604 | property_function (fragP, &prop_flags); | |
10605 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
10606 | return TRUE; | |
10607 | } | |
10608 | } | |
10609 | return FALSE; | |
10610 | } | |
10611 | ||
10612 | ||
e0001a05 NC |
10613 | /* Two types of block sections exist right now: literal and insns. */ |
10614 | ||
7fa3d080 BW |
10615 | static void |
10616 | add_xt_block_frags (segT sec, | |
10617 | segT xt_block_sec, | |
10618 | xtensa_block_info **xt_block, | |
10619 | frag_predicate property_function, | |
10620 | frag_predicate end_property_function) | |
e0001a05 NC |
10621 | { |
10622 | segment_info_type *seg_info; | |
10623 | segment_info_type *xt_seg_info; | |
10624 | bfd_vma seg_offset; | |
10625 | fragS *fragP; | |
10626 | ||
10627 | xt_seg_info = retrieve_segment_info (xt_block_sec); | |
10628 | seg_info = retrieve_segment_info (sec); | |
10629 | ||
10630 | /* Build it if needed. */ | |
10631 | while (*xt_block != NULL) | |
10632 | xt_block = &(*xt_block)->next; | |
10633 | /* We are either at NULL at the beginning or at the end. */ | |
10634 | ||
10635 | /* Walk through the frags. */ | |
10636 | seg_offset = 0; | |
10637 | ||
10638 | if (seg_info->frchainP) | |
10639 | { | |
10640 | for (fragP = seg_info->frchainP->frch_root; | |
10641 | fragP; | |
10642 | fragP = fragP->fr_next) | |
10643 | { | |
10644 | if (property_function (fragP) | |
10645 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10646 | { | |
10647 | if (*xt_block != NULL) | |
10648 | { | |
10649 | if ((*xt_block)->offset + (*xt_block)->size | |
10650 | == fragP->fr_address) | |
10651 | (*xt_block)->size += fragP->fr_fix; | |
10652 | else | |
10653 | xt_block = &((*xt_block)->next); | |
10654 | } | |
10655 | if (*xt_block == NULL) | |
10656 | { | |
43cd72b9 BW |
10657 | xtensa_block_info *new_block = (xtensa_block_info *) |
10658 | xmalloc (sizeof (xtensa_block_info)); | |
10659 | new_block->sec = sec; | |
10660 | new_block->offset = fragP->fr_address; | |
10661 | new_block->size = fragP->fr_fix; | |
10662 | new_block->next = NULL; | |
10663 | xtensa_frag_flags_init (&new_block->flags); | |
10664 | *xt_block = new_block; | |
10665 | } | |
10666 | if (end_property_function | |
10667 | && end_property_function (fragP)) | |
10668 | { | |
10669 | xt_block = &((*xt_block)->next); | |
10670 | } | |
10671 | } | |
10672 | } | |
10673 | } | |
10674 | } | |
10675 | ||
10676 | ||
10677 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
10678 | ||
7fa3d080 BW |
10679 | static bfd_boolean |
10680 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
10681 | { |
10682 | if (prop_flags->is_literal | |
10683 | || prop_flags->is_insn | |
10684 | || prop_flags->is_data | |
10685 | || prop_flags->is_unreachable) | |
10686 | return FALSE; | |
10687 | return TRUE; | |
10688 | } | |
10689 | ||
10690 | ||
7fa3d080 BW |
10691 | static void |
10692 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
10693 | { |
10694 | memset (prop_flags, 0, sizeof (frag_flags)); | |
10695 | } | |
10696 | ||
10697 | ||
7fa3d080 BW |
10698 | static void |
10699 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
10700 | { |
10701 | xtensa_frag_flags_init (prop_flags); | |
10702 | if (fragP->tc_frag_data.is_literal) | |
10703 | prop_flags->is_literal = TRUE; | |
10704 | if (fragP->tc_frag_data.is_unreachable) | |
7fa3d080 | 10705 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
10706 | else if (fragP->tc_frag_data.is_insn) |
10707 | { | |
10708 | prop_flags->is_insn = TRUE; | |
10709 | if (fragP->tc_frag_data.is_loop_target) | |
10710 | prop_flags->insn.is_loop_target = TRUE; | |
10711 | if (fragP->tc_frag_data.is_branch_target) | |
10712 | prop_flags->insn.is_branch_target = TRUE; | |
10713 | if (fragP->tc_frag_data.is_specific_opcode | |
10714 | || fragP->tc_frag_data.is_no_transform) | |
10715 | prop_flags->insn.is_no_transform = TRUE; | |
10716 | if (fragP->tc_frag_data.is_no_density) | |
10717 | prop_flags->insn.is_no_density = TRUE; | |
10718 | if (fragP->tc_frag_data.use_absolute_literals) | |
10719 | prop_flags->insn.is_abslit = TRUE; | |
10720 | } | |
10721 | if (fragP->tc_frag_data.is_align) | |
10722 | { | |
10723 | prop_flags->is_align = TRUE; | |
10724 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
10725 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10726 | prop_flags->is_data = TRUE; | |
10727 | } | |
10728 | } | |
10729 | ||
10730 | ||
7fa3d080 BW |
10731 | static bfd_vma |
10732 | frag_flags_to_number (const frag_flags *prop_flags) | |
43cd72b9 BW |
10733 | { |
10734 | bfd_vma num = 0; | |
10735 | if (prop_flags->is_literal) | |
10736 | num |= XTENSA_PROP_LITERAL; | |
10737 | if (prop_flags->is_insn) | |
10738 | num |= XTENSA_PROP_INSN; | |
10739 | if (prop_flags->is_data) | |
10740 | num |= XTENSA_PROP_DATA; | |
10741 | if (prop_flags->is_unreachable) | |
10742 | num |= XTENSA_PROP_UNREACHABLE; | |
10743 | if (prop_flags->insn.is_loop_target) | |
10744 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
10745 | if (prop_flags->insn.is_branch_target) | |
10746 | { | |
10747 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
10748 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
10749 | } | |
10750 | ||
10751 | if (prop_flags->insn.is_no_density) | |
10752 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
10753 | if (prop_flags->insn.is_no_transform) | |
10754 | num |= XTENSA_PROP_INSN_NO_TRANSFORM; | |
10755 | if (prop_flags->insn.is_no_reorder) | |
10756 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
10757 | if (prop_flags->insn.is_abslit) | |
10758 | num |= XTENSA_PROP_INSN_ABSLIT; | |
10759 | ||
10760 | if (prop_flags->is_align) | |
10761 | { | |
10762 | num |= XTENSA_PROP_ALIGN; | |
10763 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
10764 | } | |
10765 | ||
10766 | return num; | |
10767 | } | |
10768 | ||
10769 | ||
10770 | static bfd_boolean | |
7fa3d080 BW |
10771 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
10772 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
10773 | { |
10774 | /* Cannot combine with an end marker. */ | |
10775 | ||
10776 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
10777 | return FALSE; | |
10778 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
10779 | return FALSE; | |
10780 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
10781 | return FALSE; | |
10782 | ||
10783 | if (prop_flags_1->is_insn) | |
10784 | { | |
10785 | /* Properties of the beginning of the frag. */ | |
10786 | if (prop_flags_2->insn.is_loop_target) | |
10787 | return FALSE; | |
10788 | if (prop_flags_2->insn.is_branch_target) | |
10789 | return FALSE; | |
10790 | if (prop_flags_1->insn.is_no_density != | |
10791 | prop_flags_2->insn.is_no_density) | |
10792 | return FALSE; | |
10793 | if (prop_flags_1->insn.is_no_transform != | |
10794 | prop_flags_2->insn.is_no_transform) | |
10795 | return FALSE; | |
10796 | if (prop_flags_1->insn.is_no_reorder != | |
10797 | prop_flags_2->insn.is_no_reorder) | |
10798 | return FALSE; | |
10799 | if (prop_flags_1->insn.is_abslit != | |
10800 | prop_flags_2->insn.is_abslit) | |
10801 | return FALSE; | |
10802 | } | |
10803 | ||
10804 | if (prop_flags_1->is_align) | |
10805 | return FALSE; | |
10806 | ||
10807 | return TRUE; | |
10808 | } | |
10809 | ||
10810 | ||
7fa3d080 BW |
10811 | static bfd_vma |
10812 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
10813 | { |
10814 | bfd_vma end_addr; | |
d77b99c9 | 10815 | unsigned align_bits; |
43cd72b9 BW |
10816 | |
10817 | if (!xt_block->flags.is_align) | |
10818 | return xt_block->size; | |
10819 | ||
10820 | end_addr = xt_block->offset + xt_block->size; | |
10821 | align_bits = xt_block->flags.alignment; | |
10822 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
10823 | return end_addr - xt_block->offset; | |
10824 | } | |
10825 | ||
10826 | ||
10827 | static bfd_boolean | |
7fa3d080 BW |
10828 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
10829 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
10830 | { |
10831 | if (xt_block->sec != xt_block_2->sec) | |
10832 | return FALSE; | |
10833 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
10834 | != xt_block_2->offset) | |
10835 | return FALSE; | |
10836 | ||
10837 | if (xt_block_2->size == 0 | |
10838 | && (!xt_block_2->flags.is_unreachable | |
10839 | || xt_block->flags.is_unreachable)) | |
10840 | { | |
10841 | if (xt_block_2->flags.is_align | |
10842 | && xt_block->flags.is_align) | |
10843 | { | |
10844 | /* Nothing needed. */ | |
10845 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
10846 | return TRUE; | |
10847 | } | |
10848 | else | |
10849 | { | |
10850 | if (xt_block_2->flags.is_align) | |
10851 | { | |
10852 | /* Push alignment to previous entry. */ | |
10853 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
10854 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10855 | } | |
10856 | return TRUE; | |
10857 | } | |
10858 | } | |
10859 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
10860 | &xt_block_2->flags)) | |
10861 | return FALSE; | |
10862 | ||
10863 | xt_block->size += xt_block_2->size; | |
10864 | ||
10865 | if (xt_block_2->flags.is_align) | |
10866 | { | |
10867 | xt_block->flags.is_align = TRUE; | |
10868 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10869 | } | |
10870 | ||
10871 | return TRUE; | |
10872 | } | |
10873 | ||
10874 | ||
7fa3d080 BW |
10875 | static void |
10876 | add_xt_prop_frags (segT sec, | |
10877 | segT xt_block_sec, | |
10878 | xtensa_block_info **xt_block, | |
10879 | frag_flags_fn property_function) | |
43cd72b9 BW |
10880 | { |
10881 | segment_info_type *seg_info; | |
10882 | segment_info_type *xt_seg_info; | |
10883 | bfd_vma seg_offset; | |
10884 | fragS *fragP; | |
10885 | ||
10886 | xt_seg_info = retrieve_segment_info (xt_block_sec); | |
10887 | seg_info = retrieve_segment_info (sec); | |
10888 | /* Build it if needed. */ | |
10889 | while (*xt_block != NULL) | |
10890 | { | |
10891 | xt_block = &(*xt_block)->next; | |
10892 | } | |
10893 | /* We are either at NULL at the beginning or at the end. */ | |
10894 | ||
10895 | /* Walk through the frags. */ | |
10896 | seg_offset = 0; | |
10897 | ||
10898 | if (seg_info->frchainP) | |
10899 | { | |
10900 | for (fragP = seg_info->frchainP->frch_root; fragP; | |
10901 | fragP = fragP->fr_next) | |
10902 | { | |
10903 | xtensa_block_info tmp_block; | |
10904 | tmp_block.sec = sec; | |
10905 | tmp_block.offset = fragP->fr_address; | |
10906 | tmp_block.size = fragP->fr_fix; | |
10907 | tmp_block.next = NULL; | |
10908 | property_function (fragP, &tmp_block.flags); | |
10909 | ||
10910 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
10911 | /* && fragP->fr_fix != 0) */ | |
10912 | { | |
10913 | if ((*xt_block) == NULL | |
10914 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
10915 | { | |
10916 | xtensa_block_info *new_block; | |
10917 | if ((*xt_block) != NULL) | |
10918 | xt_block = &(*xt_block)->next; | |
10919 | new_block = (xtensa_block_info *) | |
10920 | xmalloc (sizeof (xtensa_block_info)); | |
10921 | *new_block = tmp_block; | |
10922 | *xt_block = new_block; | |
10923 | } | |
10924 | } | |
10925 | } | |
10926 | } | |
10927 | } | |
10928 | ||
10929 | \f | |
10930 | /* op_placement_info_table */ | |
10931 | ||
10932 | /* op_placement_info makes it easier to determine which | |
10933 | ops can go in which slots. */ | |
10934 | ||
10935 | static void | |
7fa3d080 | 10936 | init_op_placement_info_table (void) |
43cd72b9 BW |
10937 | { |
10938 | xtensa_isa isa = xtensa_default_isa; | |
10939 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
10940 | xtensa_opcode opcode; | |
10941 | xtensa_format fmt; | |
10942 | int slot; | |
10943 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
10944 | ||
10945 | op_placement_table = (op_placement_info_table) | |
10946 | xmalloc (sizeof (op_placement_info) * num_opcodes); | |
10947 | assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); | |
10948 | ||
10949 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
10950 | { | |
10951 | op_placement_info *opi = &op_placement_table[opcode]; | |
10952 | /* FIXME: Make tinsn allocation dynamic. */ | |
10953 | if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS) | |
10954 | as_fatal (_("too many operands in instruction")); | |
10955 | opi->single = XTENSA_UNDEFINED; | |
10956 | opi->single_size = 0; | |
10957 | opi->widest = XTENSA_UNDEFINED; | |
10958 | opi->widest_size = 0; | |
10959 | opi->narrowest = XTENSA_UNDEFINED; | |
10960 | opi->narrowest_size = 0x7F; | |
10961 | opi->formats = 0; | |
10962 | opi->num_formats = 0; | |
10963 | opi->issuef = 0; | |
10964 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
10965 | { | |
10966 | opi->slots[fmt] = 0; | |
10967 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
10968 | { | |
10969 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
10970 | { | |
10971 | int fmt_length = xtensa_format_length (isa, fmt); | |
10972 | opi->issuef++; | |
10973 | set_bit (fmt, opi->formats); | |
10974 | set_bit (slot, opi->slots[fmt]); | |
10975 | /* opi->slot_count[fmt]++; */ | |
10976 | if (fmt_length < opi->narrowest_size) | |
10977 | { | |
10978 | opi->narrowest = fmt; | |
10979 | opi->narrowest_size = fmt_length; | |
10980 | } | |
10981 | if (fmt_length > opi->widest_size) | |
10982 | { | |
10983 | opi->widest = fmt; | |
10984 | opi->widest_size = fmt_length; | |
10985 | } | |
10986 | if (xtensa_format_num_slots (isa, fmt) == 1) | |
10987 | { | |
10988 | if (opi->single_size == 0 | |
10989 | || fmt_length < opi->single_size) | |
10990 | { | |
10991 | opi->single = fmt; | |
10992 | opi->single_size = fmt_length; | |
10993 | } | |
10994 | } | |
e0001a05 NC |
10995 | } |
10996 | } | |
43cd72b9 BW |
10997 | if (opi->formats) |
10998 | opi->num_formats++; | |
e0001a05 NC |
10999 | } |
11000 | } | |
43cd72b9 BW |
11001 | xtensa_insnbuf_free (isa, ibuf); |
11002 | } | |
11003 | ||
11004 | ||
11005 | bfd_boolean | |
7fa3d080 | 11006 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
11007 | { |
11008 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
11009 | } | |
11010 | ||
11011 | ||
11012 | /* If the opcode is available in a single slot format, return its size. */ | |
11013 | ||
7fa3d080 BW |
11014 | static int |
11015 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 BW |
11016 | { |
11017 | assert (op_placement_table[opcode].single != XTENSA_UNDEFINED); | |
11018 | return op_placement_table[opcode].single_size; | |
11019 | } | |
11020 | ||
11021 | ||
7fa3d080 BW |
11022 | static xtensa_format |
11023 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 BW |
11024 | { |
11025 | return op_placement_table[opcode].single; | |
e0001a05 NC |
11026 | } |
11027 | ||
11028 | \f | |
11029 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
11030 | ||
11031 | void | |
7fa3d080 | 11032 | istack_init (IStack *stack) |
e0001a05 NC |
11033 | { |
11034 | memset (stack, 0, sizeof (IStack)); | |
11035 | stack->ninsn = 0; | |
11036 | } | |
11037 | ||
11038 | ||
11039 | bfd_boolean | |
7fa3d080 | 11040 | istack_empty (IStack *stack) |
e0001a05 NC |
11041 | { |
11042 | return (stack->ninsn == 0); | |
11043 | } | |
11044 | ||
11045 | ||
11046 | bfd_boolean | |
7fa3d080 | 11047 | istack_full (IStack *stack) |
e0001a05 NC |
11048 | { |
11049 | return (stack->ninsn == MAX_ISTACK); | |
11050 | } | |
11051 | ||
11052 | ||
11053 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 11054 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
11055 | |
11056 | TInsn * | |
7fa3d080 | 11057 | istack_top (IStack *stack) |
e0001a05 NC |
11058 | { |
11059 | int rec = stack->ninsn - 1; | |
11060 | assert (!istack_empty (stack)); | |
11061 | return &stack->insn[rec]; | |
11062 | } | |
11063 | ||
11064 | ||
11065 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 11066 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11067 | |
11068 | void | |
7fa3d080 | 11069 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
11070 | { |
11071 | int rec = stack->ninsn; | |
11072 | assert (!istack_full (stack)); | |
43cd72b9 | 11073 | stack->insn[rec] = *insn; |
e0001a05 NC |
11074 | stack->ninsn++; |
11075 | } | |
11076 | ||
11077 | ||
11078 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 11079 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
11080 | |
11081 | TInsn * | |
7fa3d080 | 11082 | istack_push_space (IStack *stack) |
e0001a05 NC |
11083 | { |
11084 | int rec = stack->ninsn; | |
11085 | TInsn *insn; | |
11086 | assert (!istack_full (stack)); | |
11087 | insn = &stack->insn[rec]; | |
11088 | memset (insn, 0, sizeof (TInsn)); | |
11089 | stack->ninsn++; | |
11090 | return insn; | |
11091 | } | |
11092 | ||
11093 | ||
11094 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 11095 | istack_empty () returns TRUE. */ |
e0001a05 NC |
11096 | |
11097 | void | |
7fa3d080 | 11098 | istack_pop (IStack *stack) |
e0001a05 NC |
11099 | { |
11100 | int rec = stack->ninsn - 1; | |
11101 | assert (!istack_empty (stack)); | |
11102 | stack->ninsn--; | |
11103 | memset (&stack->insn[rec], 0, sizeof (TInsn)); | |
11104 | } | |
11105 | ||
11106 | \f | |
11107 | /* TInsn functions. */ | |
11108 | ||
11109 | void | |
7fa3d080 | 11110 | tinsn_init (TInsn *dst) |
e0001a05 NC |
11111 | { |
11112 | memset (dst, 0, sizeof (TInsn)); | |
11113 | } | |
11114 | ||
11115 | ||
e0001a05 NC |
11116 | /* Get the ``num''th token of the TInsn. |
11117 | It is illegal to call this if num > insn->ntoks. */ | |
11118 | ||
11119 | expressionS * | |
7fa3d080 | 11120 | tinsn_get_tok (TInsn *insn, int num) |
e0001a05 NC |
11121 | { |
11122 | assert (num < insn->ntok); | |
11123 | return &insn->tok[num]; | |
11124 | } | |
11125 | ||
11126 | ||
43cd72b9 | 11127 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
11128 | |
11129 | static bfd_boolean | |
7fa3d080 | 11130 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
11131 | { |
11132 | int i; | |
11133 | int n = insn->ntok; | |
11134 | ||
11135 | assert (insn->insn_type == ITYPE_INSN); | |
11136 | ||
11137 | for (i = 0; i < n; ++i) | |
11138 | { | |
11139 | switch (insn->tok[i].X_op) | |
11140 | { | |
11141 | case O_register: | |
11142 | case O_constant: | |
11143 | break; | |
11144 | default: | |
11145 | return TRUE; | |
11146 | } | |
11147 | } | |
11148 | return FALSE; | |
11149 | } | |
11150 | ||
11151 | ||
11152 | bfd_boolean | |
7fa3d080 | 11153 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 11154 | { |
43cd72b9 | 11155 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
11156 | int i; |
11157 | int n = insn->ntok; | |
11158 | ||
11159 | assert (insn->insn_type == ITYPE_INSN); | |
11160 | ||
11161 | for (i = 0; i < n; ++i) | |
11162 | { | |
11163 | switch (insn->tok[i].X_op) | |
11164 | { | |
11165 | case O_register: | |
11166 | case O_constant: | |
11167 | break; | |
43cd72b9 BW |
11168 | case O_big: |
11169 | case O_illegal: | |
11170 | case O_absent: | |
11171 | /* Errors for these types are caught later. */ | |
11172 | break; | |
11173 | case O_hi16: | |
11174 | case O_lo16: | |
e0001a05 | 11175 | default: |
43cd72b9 BW |
11176 | /* Symbolic immediates are only allowed on the last immediate |
11177 | operand. At this time, CONST16 is the only opcode where we | |
11178 | support non-PC-relative relocations. (It isn't necessary | |
11179 | to complain about non-PC-relative relocations here, but | |
11180 | otherwise, no error is reported until the relocations are | |
11181 | generated, and the assembler won't get that far if there | |
11182 | are any other errors. It's nice to see all the problems | |
11183 | at once.) */ | |
11184 | if (i != get_relaxable_immed (insn->opcode) | |
11185 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
11186 | && insn->opcode != xtensa_const16_opcode)) | |
11187 | { | |
11188 | as_bad (_("invalid symbolic operand %d on '%s'"), | |
11189 | i, xtensa_opcode_name (isa, insn->opcode)); | |
11190 | return TRUE; | |
11191 | } | |
e0001a05 NC |
11192 | } |
11193 | } | |
11194 | return FALSE; | |
11195 | } | |
11196 | ||
11197 | ||
11198 | /* For assembly code with complex expressions (e.g. subtraction), | |
11199 | we have to build them in the literal pool so that | |
11200 | their results are calculated correctly after relaxation. | |
11201 | The relaxation only handles expressions that | |
11202 | boil down to SYMBOL + OFFSET. */ | |
11203 | ||
11204 | static bfd_boolean | |
7fa3d080 | 11205 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
11206 | { |
11207 | int i; | |
11208 | int n = insn->ntok; | |
11209 | assert (insn->insn_type == ITYPE_INSN); | |
11210 | for (i = 0; i < n; ++i) | |
11211 | { | |
11212 | switch (insn->tok[i].X_op) | |
11213 | { | |
11214 | case O_register: | |
11215 | case O_constant: | |
11216 | case O_symbol: | |
43cd72b9 BW |
11217 | case O_lo16: |
11218 | case O_hi16: | |
e0001a05 NC |
11219 | break; |
11220 | default: | |
11221 | return TRUE; | |
11222 | } | |
11223 | } | |
11224 | return FALSE; | |
11225 | } | |
11226 | ||
11227 | ||
43cd72b9 BW |
11228 | /* Convert the constant operands in the tinsn to insnbuf. |
11229 | Return TRUE if there is a symbol in the immediate field. | |
e0001a05 | 11230 | |
43cd72b9 | 11231 | Before this is called, |
e0001a05 | 11232 | 1) the number of operands are correct |
43cd72b9 | 11233 | 2) the tinsn is a ITYPE_INSN |
e0001a05 NC |
11234 | 3) ONLY the relaxable_ is built |
11235 | 4) All operands are O_constant, O_symbol. All constants fit | |
11236 | The return value tells whether there are any remaining O_symbols. */ | |
11237 | ||
11238 | static bfd_boolean | |
7fa3d080 | 11239 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) |
e0001a05 | 11240 | { |
43cd72b9 | 11241 | static xtensa_insnbuf slotbuf = 0; |
e0001a05 | 11242 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
11243 | xtensa_opcode opcode = tinsn->opcode; |
11244 | xtensa_format fmt = xg_get_single_format (opcode); | |
e0001a05 | 11245 | bfd_boolean has_fixup = FALSE; |
43cd72b9 | 11246 | int noperands = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 NC |
11247 | int i; |
11248 | uint32 opnd_value; | |
11249 | char *file_name; | |
d77b99c9 | 11250 | unsigned line; |
e0001a05 | 11251 | |
43cd72b9 BW |
11252 | if (!slotbuf) |
11253 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11254 | ||
11255 | assert (tinsn->insn_type == ITYPE_INSN); | |
11256 | if (noperands != tinsn->ntok) | |
e0001a05 NC |
11257 | as_fatal (_("operand number mismatch")); |
11258 | ||
43cd72b9 BW |
11259 | if (xtensa_opcode_encode (isa, fmt, 0, slotbuf, opcode)) |
11260 | as_fatal (_("cannot encode opcode")); | |
e0001a05 NC |
11261 | |
11262 | for (i = 0; i < noperands; ++i) | |
11263 | { | |
43cd72b9 | 11264 | expressionS *expr = &tinsn->tok[i]; |
e0001a05 NC |
11265 | switch (expr->X_op) |
11266 | { | |
11267 | case O_register: | |
43cd72b9 BW |
11268 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) |
11269 | break; | |
11270 | /* The register number has already been checked in | |
e0001a05 NC |
11271 | expression_maybe_register, so we don't need to check here. */ |
11272 | opnd_value = expr->X_add_number; | |
43cd72b9 BW |
11273 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); |
11274 | xtensa_operand_set_field (isa, opcode, i, fmt, 0, | |
11275 | slotbuf, opnd_value); | |
e0001a05 NC |
11276 | break; |
11277 | ||
11278 | case O_constant: | |
43cd72b9 BW |
11279 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) |
11280 | break; | |
e0001a05 NC |
11281 | as_where (&file_name, &line); |
11282 | /* It is a constant and we called this function, | |
11283 | then we have to try to fit it. */ | |
43cd72b9 BW |
11284 | xtensa_insnbuf_set_operand (slotbuf, fmt, 0, opcode, i, |
11285 | expr->X_add_number, file_name, line); | |
11286 | break; | |
11287 | ||
11288 | default: | |
11289 | has_fixup = TRUE; | |
11290 | break; | |
11291 | } | |
11292 | } | |
11293 | ||
11294 | xtensa_format_encode (isa, fmt, insnbuf); | |
11295 | xtensa_format_set_slot (isa, fmt, 0, insnbuf, slotbuf); | |
11296 | ||
11297 | return has_fixup; | |
11298 | } | |
11299 | ||
11300 | ||
11301 | /* Convert the constant operands in the tinsn to slotbuf. | |
11302 | Return TRUE if there is a symbol in the immediate field. | |
11303 | (Eventually this should replace tinsn_to_insnbuf.) */ | |
11304 | ||
11305 | /* Before this is called, | |
11306 | 1) the number of operands are correct | |
11307 | 2) the tinsn is a ITYPE_INSN | |
11308 | 3) ONLY the relaxable_ is built | |
11309 | 4) All operands are | |
11310 | O_constant, O_symbol | |
11311 | All constants fit | |
11312 | ||
11313 | The return value tells whether there are any remaining O_symbols. */ | |
11314 | ||
11315 | static bfd_boolean | |
7fa3d080 BW |
11316 | tinsn_to_slotbuf (xtensa_format fmt, |
11317 | int slot, | |
11318 | TInsn *tinsn, | |
11319 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
11320 | { |
11321 | xtensa_isa isa = xtensa_default_isa; | |
11322 | xtensa_opcode opcode = tinsn->opcode; | |
11323 | bfd_boolean has_fixup = FALSE; | |
11324 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11325 | int i; | |
11326 | ||
11327 | *((int *) &slotbuf[0]) = 0; | |
11328 | *((int *) &slotbuf[1]) = 0; | |
11329 | assert (tinsn->insn_type == ITYPE_INSN); | |
11330 | if (noperands != tinsn->ntok) | |
11331 | as_fatal (_("operand number mismatch")); | |
11332 | ||
11333 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
11334 | { | |
11335 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
11336 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
11337 | return FALSE; | |
11338 | } | |
11339 | ||
11340 | for (i = 0; i < noperands; i++) | |
11341 | { | |
11342 | expressionS *expr = &tinsn->tok[i]; | |
d77b99c9 BW |
11343 | int rc; |
11344 | unsigned line; | |
43cd72b9 BW |
11345 | char *file_name; |
11346 | uint32 opnd_value; | |
11347 | ||
11348 | switch (expr->X_op) | |
11349 | { | |
11350 | case O_register: | |
11351 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11352 | break; | |
11353 | /* The register number has already been checked in | |
11354 | expression_maybe_register, so we don't need to check here. */ | |
11355 | opnd_value = expr->X_add_number; | |
11356 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); | |
11357 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
11358 | opnd_value); | |
11359 | if (rc != 0) | |
11360 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
11361 | break; | |
11362 | ||
11363 | case O_constant: | |
11364 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11365 | break; | |
11366 | as_where (&file_name, &line); | |
11367 | /* It is a constant and we called this function | |
11368 | then we have to try to fit it. */ | |
11369 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
e0001a05 NC |
11370 | expr->X_add_number, file_name, line); |
11371 | break; | |
11372 | ||
e0001a05 NC |
11373 | default: |
11374 | has_fixup = TRUE; | |
11375 | break; | |
11376 | } | |
11377 | } | |
43cd72b9 | 11378 | |
e0001a05 NC |
11379 | return has_fixup; |
11380 | } | |
11381 | ||
11382 | ||
43cd72b9 | 11383 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 11384 | |
7fa3d080 BW |
11385 | static bfd_boolean |
11386 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
11387 | { |
11388 | xtensa_isa isa = xtensa_default_isa; | |
11389 | xtensa_opcode opcode = insn->opcode; | |
11390 | ||
11391 | if (opcode == XTENSA_UNDEFINED) | |
11392 | { | |
11393 | as_bad (_("invalid opcode")); | |
11394 | return TRUE; | |
11395 | } | |
11396 | ||
43cd72b9 | 11397 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
11398 | { |
11399 | as_bad (_("too few operands")); | |
11400 | return TRUE; | |
11401 | } | |
11402 | ||
43cd72b9 | 11403 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
11404 | { |
11405 | as_bad (_("too many operands")); | |
11406 | return TRUE; | |
11407 | } | |
11408 | return FALSE; | |
11409 | } | |
11410 | ||
11411 | ||
11412 | /* Load an instruction from its encoded form. */ | |
11413 | ||
11414 | static void | |
7fa3d080 | 11415 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 11416 | { |
43cd72b9 | 11417 | vliw_insn vinsn; |
e0001a05 | 11418 | |
43cd72b9 BW |
11419 | xg_init_vinsn (&vinsn); |
11420 | vinsn_from_chars (&vinsn, f); | |
11421 | ||
11422 | *tinsn = vinsn.slots[slot]; | |
11423 | xg_free_vinsn (&vinsn); | |
11424 | } | |
e0001a05 | 11425 | |
43cd72b9 BW |
11426 | |
11427 | static void | |
7fa3d080 BW |
11428 | tinsn_from_insnbuf (TInsn *tinsn, |
11429 | xtensa_insnbuf slotbuf, | |
11430 | xtensa_format fmt, | |
11431 | int slot) | |
43cd72b9 BW |
11432 | { |
11433 | int i; | |
11434 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
11435 | |
11436 | /* Find the immed. */ | |
43cd72b9 BW |
11437 | tinsn_init (tinsn); |
11438 | tinsn->insn_type = ITYPE_INSN; | |
11439 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
11440 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
11441 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
11442 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 11443 | { |
43cd72b9 BW |
11444 | set_expr_const (&tinsn->tok[i], |
11445 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
11446 | tinsn->opcode, i)); | |
e0001a05 NC |
11447 | } |
11448 | } | |
11449 | ||
11450 | ||
11451 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
11452 | ||
11453 | static void | |
7fa3d080 | 11454 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 11455 | { |
43cd72b9 | 11456 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
11457 | int opnum; |
11458 | ||
43cd72b9 | 11459 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
11460 | { |
11461 | opnum = get_relaxable_immed (opcode); | |
43cd72b9 BW |
11462 | assert (opnum >= 0); |
11463 | if (fragP->tc_frag_data.slot_sub_symbols[slot]) | |
11464 | { | |
11465 | set_expr_symbol_offset_diff | |
11466 | (&tinsn->tok[opnum], | |
11467 | fragP->tc_frag_data.slot_symbols[slot], | |
11468 | fragP->tc_frag_data.slot_sub_symbols[slot], | |
11469 | fragP->tc_frag_data.slot_offsets[slot]); | |
11470 | } | |
11471 | else | |
11472 | { | |
11473 | set_expr_symbol_offset | |
11474 | (&tinsn->tok[opnum], | |
11475 | fragP->tc_frag_data.slot_symbols[slot], | |
11476 | fragP->tc_frag_data.slot_offsets[slot]); | |
11477 | } | |
e0001a05 NC |
11478 | } |
11479 | } | |
11480 | ||
11481 | ||
11482 | static int | |
7fa3d080 | 11483 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
11484 | { |
11485 | int i; | |
11486 | int text_bytes = 0; | |
11487 | ||
11488 | for (i = 0; i < istack->ninsn; i++) | |
11489 | { | |
43cd72b9 BW |
11490 | TInsn *tinsn = &istack->insn[i]; |
11491 | if (tinsn->insn_type == ITYPE_INSN) | |
11492 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
11493 | } |
11494 | return text_bytes; | |
11495 | } | |
11496 | ||
11497 | ||
11498 | static int | |
7fa3d080 | 11499 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
11500 | { |
11501 | int i; | |
11502 | int lit_bytes = 0; | |
11503 | ||
11504 | for (i = 0; i < istack->ninsn; i++) | |
11505 | { | |
43cd72b9 BW |
11506 | TInsn *tinsn = &istack->insn[i]; |
11507 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
11508 | lit_bytes += 4; |
11509 | } | |
11510 | return lit_bytes; | |
11511 | } | |
11512 | ||
43cd72b9 BW |
11513 | \f |
11514 | /* vliw_insn functions. */ | |
11515 | ||
7fa3d080 BW |
11516 | static void |
11517 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11518 | { |
11519 | int i; | |
11520 | xtensa_isa isa = xtensa_default_isa; | |
11521 | ||
11522 | xg_clear_vinsn (v); | |
11523 | ||
11524 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
11525 | if (v->insnbuf == NULL) | |
11526 | as_fatal (_("out of memory")); | |
11527 | ||
11528 | for (i = 0; i < MAX_SLOTS; i++) | |
11529 | { | |
11530 | tinsn_init (&v->slots[i]); | |
11531 | v->slots[i].opcode = XTENSA_UNDEFINED; | |
11532 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); | |
11533 | if (v->slotbuf[i] == NULL) | |
11534 | as_fatal (_("out of memory")); | |
11535 | } | |
11536 | } | |
11537 | ||
11538 | ||
7fa3d080 BW |
11539 | static void |
11540 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11541 | { |
11542 | int i; | |
11543 | v->format = XTENSA_UNDEFINED; | |
11544 | v->num_slots = 0; | |
11545 | v->inside_bundle = FALSE; | |
11546 | ||
11547 | if (xt_saved_debug_type != DEBUG_NONE) | |
11548 | debug_type = xt_saved_debug_type; | |
11549 | ||
11550 | for (i = 0; i < MAX_SLOTS; i++) | |
11551 | { | |
11552 | memset (&v->slots[i], 0, sizeof (TInsn)); | |
11553 | v->slots[i].opcode = XTENSA_UNDEFINED; | |
11554 | } | |
11555 | } | |
11556 | ||
11557 | ||
7fa3d080 BW |
11558 | static bfd_boolean |
11559 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
11560 | { |
11561 | int i; | |
11562 | ||
11563 | for (i = 0; i < v->num_slots; i++) | |
11564 | { | |
11565 | if (v->slots[i].is_specific_opcode) | |
11566 | return TRUE; | |
11567 | } | |
11568 | return FALSE; | |
11569 | } | |
11570 | ||
11571 | ||
7fa3d080 BW |
11572 | static void |
11573 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11574 | { |
11575 | int i; | |
11576 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
11577 | for (i = 0; i < MAX_SLOTS; i++) | |
11578 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); | |
11579 | } | |
11580 | ||
11581 | ||
11582 | /* Before this is called, we should have | |
11583 | filled out the following fields: | |
11584 | ||
11585 | 1) the number of operands for each opcode are correct | |
11586 | 2) the tinsn in the slots are ITYPE_INSN | |
11587 | 3) ONLY the relaxable_ is built | |
11588 | 4) All operands are | |
11589 | O_constant, O_symbol | |
11590 | All constants fit | |
11591 | ||
11592 | The return value tells whether there are any remaining O_symbols. */ | |
11593 | ||
11594 | static bfd_boolean | |
7fa3d080 BW |
11595 | vinsn_to_insnbuf (vliw_insn *vinsn, |
11596 | char *frag_offset, | |
11597 | fragS *fragP, | |
11598 | bfd_boolean record_fixup) | |
43cd72b9 BW |
11599 | { |
11600 | xtensa_isa isa = xtensa_default_isa; | |
11601 | xtensa_format fmt = vinsn->format; | |
11602 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
11603 | int slot; | |
11604 | bfd_boolean has_fixup = FALSE; | |
11605 | ||
11606 | xtensa_format_encode (isa, fmt, insnbuf); | |
11607 | ||
11608 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
11609 | { | |
11610 | TInsn *tinsn = &vinsn->slots[slot]; | |
11611 | bfd_boolean tinsn_has_fixup = | |
11612 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
11613 | vinsn->slotbuf[slot]); | |
11614 | ||
11615 | xtensa_format_set_slot (isa, fmt, slot, | |
11616 | insnbuf, vinsn->slotbuf[slot]); | |
11617 | /* tinsn_has_fixup tracks if there is a fixup at all. | |
11618 | record_fixup controls globally. I.E., we use this | |
11619 | function from several places, some of which are after | |
11620 | fixups have already been recorded. Finally, | |
11621 | tinsn->record_fixup controls based on the individual ops, | |
11622 | which may or may not need it based on the relaxation | |
11623 | requirements. */ | |
11624 | if (tinsn_has_fixup && record_fixup) | |
11625 | { | |
11626 | int i; | |
11627 | xtensa_opcode opcode = tinsn->opcode; | |
11628 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11629 | has_fixup = TRUE; | |
11630 | ||
11631 | for (i = 0; i < noperands; i++) | |
11632 | { | |
11633 | expressionS* expr = &tinsn->tok[i]; | |
11634 | switch (expr->X_op) | |
11635 | { | |
11636 | case O_symbol: | |
11637 | case O_lo16: | |
11638 | case O_hi16: | |
11639 | if (get_relaxable_immed (opcode) == i) | |
11640 | { | |
11641 | if (tinsn->record_fix || expr->X_op != O_symbol) | |
11642 | { | |
11643 | if (!xg_add_opcode_fix | |
11644 | (tinsn, i, fmt, slot, expr, fragP, | |
11645 | frag_offset - fragP->fr_literal)) | |
11646 | as_bad (_("instruction with constant operands does not fit")); | |
11647 | } | |
11648 | else | |
11649 | { | |
11650 | tinsn->symbol = expr->X_add_symbol; | |
11651 | tinsn->offset = expr->X_add_number; | |
11652 | } | |
11653 | } | |
11654 | else | |
11655 | as_bad (_("invalid operand %d on '%s'"), | |
11656 | i, xtensa_opcode_name (isa, opcode)); | |
11657 | break; | |
11658 | ||
11659 | case O_constant: | |
11660 | case O_register: | |
11661 | break; | |
11662 | ||
11663 | case O_subtract: | |
11664 | if (get_relaxable_immed (opcode) == i) | |
11665 | { | |
11666 | if (tinsn->record_fix) | |
11667 | as_bad (_("invalid subtract operand")); | |
11668 | else | |
11669 | { | |
11670 | tinsn->symbol = expr->X_add_symbol; | |
11671 | tinsn->sub_symbol = expr->X_op_symbol; | |
11672 | tinsn->offset = expr->X_add_number; | |
11673 | } | |
11674 | } | |
11675 | else | |
11676 | as_bad (_("invalid operand %d on '%s'"), | |
11677 | i, xtensa_opcode_name (isa, opcode)); | |
11678 | break; | |
11679 | ||
11680 | default: | |
11681 | as_bad (_("invalid expression for operand %d on '%s'"), | |
11682 | i, xtensa_opcode_name (isa, opcode)); | |
11683 | break; | |
11684 | } | |
11685 | } | |
11686 | } | |
11687 | } | |
11688 | ||
11689 | return has_fixup; | |
11690 | } | |
11691 | ||
11692 | ||
11693 | static void | |
7fa3d080 | 11694 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
11695 | { |
11696 | static xtensa_insnbuf insnbuf = NULL; | |
11697 | static xtensa_insnbuf slotbuf = NULL; | |
11698 | int i; | |
11699 | xtensa_format fmt; | |
11700 | xtensa_isa isa = xtensa_default_isa; | |
11701 | ||
11702 | if (!insnbuf) | |
11703 | { | |
11704 | insnbuf = xtensa_insnbuf_alloc (isa); | |
11705 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11706 | } | |
11707 | ||
d77b99c9 | 11708 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
11709 | fmt = xtensa_format_decode (isa, insnbuf); |
11710 | if (fmt == XTENSA_UNDEFINED) | |
11711 | as_fatal (_("cannot decode instruction format")); | |
11712 | vinsn->format = fmt; | |
11713 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
11714 | ||
11715 | for (i = 0; i < vinsn->num_slots; i++) | |
11716 | { | |
11717 | TInsn *tinsn = &vinsn->slots[i]; | |
11718 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
11719 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
11720 | } | |
11721 | } | |
11722 | ||
e0001a05 NC |
11723 | \f |
11724 | /* Expression utilities. */ | |
11725 | ||
43cd72b9 | 11726 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
11727 | |
11728 | bfd_boolean | |
7fa3d080 | 11729 | expr_is_const (const expressionS *s) |
e0001a05 NC |
11730 | { |
11731 | return (s->X_op == O_constant); | |
11732 | } | |
11733 | ||
11734 | ||
11735 | /* Get the expression constant. | |
43cd72b9 | 11736 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
11737 | |
11738 | offsetT | |
7fa3d080 | 11739 | get_expr_const (const expressionS *s) |
e0001a05 NC |
11740 | { |
11741 | assert (expr_is_const (s)); | |
11742 | return s->X_add_number; | |
11743 | } | |
11744 | ||
11745 | ||
11746 | /* Set the expression to a constant value. */ | |
11747 | ||
11748 | void | |
7fa3d080 | 11749 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
11750 | { |
11751 | s->X_op = O_constant; | |
11752 | s->X_add_number = val; | |
11753 | s->X_add_symbol = NULL; | |
11754 | s->X_op_symbol = NULL; | |
11755 | } | |
11756 | ||
11757 | ||
43cd72b9 | 11758 | bfd_boolean |
7fa3d080 | 11759 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
11760 | { |
11761 | return (s->X_op == O_register); | |
11762 | } | |
11763 | ||
11764 | ||
11765 | /* Get the expression constant. | |
11766 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
11767 | ||
11768 | offsetT | |
7fa3d080 | 11769 | get_expr_register (const expressionS *s) |
43cd72b9 BW |
11770 | { |
11771 | assert (expr_is_register (s)); | |
11772 | return s->X_add_number; | |
11773 | } | |
11774 | ||
11775 | ||
e0001a05 NC |
11776 | /* Set the expression to a symbol + constant offset. */ |
11777 | ||
11778 | void | |
7fa3d080 | 11779 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
11780 | { |
11781 | s->X_op = O_symbol; | |
11782 | s->X_add_symbol = sym; | |
11783 | s->X_op_symbol = NULL; /* unused */ | |
11784 | s->X_add_number = offset; | |
11785 | } | |
11786 | ||
11787 | ||
43cd72b9 BW |
11788 | /* Set the expression to symbol - minus_sym + offset. */ |
11789 | ||
7fa3d080 BW |
11790 | static void |
11791 | set_expr_symbol_offset_diff (expressionS *s, | |
11792 | symbolS *sym, | |
11793 | symbolS *minus_sym, | |
11794 | offsetT offset) | |
43cd72b9 BW |
11795 | { |
11796 | s->X_op = O_subtract; | |
11797 | s->X_add_symbol = sym; | |
11798 | s->X_op_symbol = minus_sym; /* unused */ | |
11799 | s->X_add_number = offset; | |
11800 | } | |
11801 | ||
11802 | ||
11803 | /* Return TRUE if the two expressions are equal. */ | |
11804 | ||
e0001a05 | 11805 | bfd_boolean |
7fa3d080 | 11806 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
11807 | { |
11808 | if (s1->X_op != s2->X_op) | |
11809 | return FALSE; | |
11810 | if (s1->X_add_symbol != s2->X_add_symbol) | |
11811 | return FALSE; | |
11812 | if (s1->X_op_symbol != s2->X_op_symbol) | |
11813 | return FALSE; | |
11814 | if (s1->X_add_number != s2->X_add_number) | |
11815 | return FALSE; | |
11816 | return TRUE; | |
11817 | } | |
11818 | ||
11819 | ||
11820 | static void | |
7fa3d080 | 11821 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
11822 | { |
11823 | memcpy (dst, src, sizeof (expressionS)); | |
11824 | } | |
11825 | ||
11826 | \f | |
9456465c | 11827 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
11828 | |
11829 | struct rename_section_struct | |
11830 | { | |
11831 | char *old_name; | |
11832 | char *new_name; | |
11833 | struct rename_section_struct *next; | |
11834 | }; | |
11835 | ||
11836 | static struct rename_section_struct *section_rename; | |
11837 | ||
11838 | ||
9456465c BW |
11839 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
11840 | entries to the section_rename list. Note: Specifying multiple | |
11841 | renamings separated by colons is not documented and is retained only | |
11842 | for backward compatibility. */ | |
e0001a05 | 11843 | |
7fa3d080 BW |
11844 | static void |
11845 | build_section_rename (const char *arg) | |
e0001a05 | 11846 | { |
9456465c | 11847 | struct rename_section_struct *r; |
e0001a05 NC |
11848 | char *this_arg = NULL; |
11849 | char *next_arg = NULL; | |
11850 | ||
9456465c | 11851 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 11852 | { |
9456465c BW |
11853 | char *old_name, *new_name; |
11854 | ||
e0001a05 NC |
11855 | if (this_arg) |
11856 | { | |
11857 | next_arg = strchr (this_arg, ':'); | |
11858 | if (next_arg) | |
11859 | { | |
11860 | *next_arg = '\0'; | |
11861 | next_arg++; | |
11862 | } | |
11863 | } | |
e0001a05 | 11864 | |
9456465c BW |
11865 | old_name = this_arg; |
11866 | new_name = strchr (this_arg, '='); | |
e0001a05 | 11867 | |
9456465c BW |
11868 | if (*old_name == '\0') |
11869 | { | |
11870 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
11871 | continue; | |
11872 | } | |
11873 | if (!new_name || new_name[1] == '\0') | |
11874 | { | |
11875 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
11876 | old_name); | |
11877 | continue; | |
11878 | } | |
11879 | *new_name = '\0'; | |
11880 | new_name++; | |
e0001a05 | 11881 | |
9456465c BW |
11882 | /* Check for invalid section renaming. */ |
11883 | for (r = section_rename; r != NULL; r = r->next) | |
11884 | { | |
11885 | if (strcmp (r->old_name, old_name) == 0) | |
11886 | as_bad (_("section %s renamed multiple times"), old_name); | |
11887 | if (strcmp (r->new_name, new_name) == 0) | |
11888 | as_bad (_("multiple sections remapped to output section %s"), | |
11889 | new_name); | |
11890 | } | |
e0001a05 | 11891 | |
9456465c BW |
11892 | /* Now add it. */ |
11893 | r = (struct rename_section_struct *) | |
11894 | xmalloc (sizeof (struct rename_section_struct)); | |
11895 | r->old_name = xstrdup (old_name); | |
11896 | r->new_name = xstrdup (new_name); | |
11897 | r->next = section_rename; | |
11898 | section_rename = r; | |
e0001a05 | 11899 | } |
e0001a05 NC |
11900 | } |
11901 | ||
11902 | ||
9456465c BW |
11903 | char * |
11904 | xtensa_section_rename (char *name) | |
e0001a05 NC |
11905 | { |
11906 | struct rename_section_struct *r = section_rename; | |
11907 | ||
11908 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
11909 | { |
11910 | if (strcmp (r->old_name, name) == 0) | |
11911 | return r->new_name; | |
11912 | } | |
e0001a05 NC |
11913 | |
11914 | return name; | |
11915 | } |