i386: Append ".p2align 4,0" to gas tests
[deliverable/binutils-gdb.git] / gas / doc / c-aarch64.texi
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219d1afa 1@c Copyright (C) 2009-2018 Free Software Foundation, Inc.
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2@c Contributed by ARM Ltd.
3@c This is part of the GAS manual.
4@c For copying conditions, see the file as.texinfo.
5@c man end
6
7@ifset GENERIC
8@page
9@node AArch64-Dependent
10@chapter AArch64 Dependent Features
11@end ifset
12
13@ifclear GENERIC
14@node Machine Dependencies
15@chapter AArch64 Dependent Features
16@end ifclear
17
18@cindex AArch64 support
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19@menu
20* AArch64 Options:: Options
df359aa7 21* AArch64 Extensions:: Extensions
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22* AArch64 Syntax:: Syntax
23* AArch64 Floating Point:: Floating Point
24* AArch64 Directives:: AArch64 Machine Directives
25* AArch64 Opcodes:: Opcodes
26* AArch64 Mapping Symbols:: Mapping Symbols
27@end menu
28
29@node AArch64 Options
30@section Options
31@cindex AArch64 options (none)
32@cindex options for AArch64 (none)
33
34@c man begin OPTIONS
35@table @gcctabopt
36
df359aa7 37@cindex @option{-EB} command line option, AArch64
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38@item -EB
39This option specifies that the output generated by the assembler should
40be marked as being encoded for a big-endian processor.
41
df359aa7 42@cindex @option{-EL} command line option, AArch64
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43@item -EL
44This option specifies that the output generated by the assembler should
45be marked as being encoded for a little-endian processor.
46
df359aa7 47@cindex @option{-mabi=} command line option, AArch64
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48@item -mabi=@var{abi}
49Specify which ABI the source code uses. The recognized arguments
50are: @code{ilp32} and @code{lp64}, which decides the generated object
51file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
52
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53@cindex @option{-mcpu=} command line option, AArch64
54@item -mcpu=@var{processor}[+@var{extension}@dots{}]
55This option specifies the target processor. The assembler will issue an error
56message if an attempt is made to assemble an instruction which will not execute
57on the target processor. The following processor names are recognized:
9c352f1c 58@code{cortex-a35},
df359aa7 59@code{cortex-a53},
1e292627 60@code{cortex-a55},
df359aa7 61@code{cortex-a57},
2abdd192 62@code{cortex-a72},
1aa70332 63@code{cortex-a73},
1e292627 64@code{cortex-a75},
2412d878 65@code{exynos-m1},
2fe9c2a0 66@code{falkor},
6b21c2bf 67@code{qdf24xx},
7605d944 68@code{saphira},
55fbd992 69@code{thunderx},
0a8be2fe 70@code{vulcan},
0a9ce86d 71@code{xgene1}
df359aa7 72and
0a9ce86d 73@code{xgene2}.
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74The special name @code{all} may be used to allow the assembler to accept
75instructions valid for any supported processor, including all optional
76extensions.
77
78In addition to the basic instruction set, the assembler can be told to
79accept, or restrict, various extension mnemonics that extend the
80processor. @xref{AArch64 Extensions}.
81
82If some implementations of a particular processor can have an
83extension, then then those extensions are automatically enabled.
84Consequently, you will not normally have to specify any additional
85extensions.
86
87@cindex @option{-march=} command line option, AArch64
88@item -march=@var{architecture}[+@var{extension}@dots{}]
89This option specifies the target architecture. The assembler will
90issue an error message if an attempt is made to assemble an
91instruction which will not execute on the target architecture. The
acb787b0 92following architecture names are recognized: @code{armv8-a},
68ffd936 93@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a} and @code{armv8.4-a}.
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94
95If both @option{-mcpu} and @option{-march} are specified, the
96assembler will use the setting for @option{-mcpu}. If neither are
97specified, the assembler will default to @option{-mcpu=all}.
98
99The architecture option can be extended with the same instruction set
100extension options as the @option{-mcpu} option. Unlike
101@option{-mcpu}, extensions are not always enabled by default,
102@xref{AArch64 Extensions}.
103
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104@cindex @code{-mverbose-error} command line option, AArch64
105@item -mverbose-error
106This option enables verbose error messages for AArch64 gas. This option
107is enabled by default.
108
109@cindex @code{-mno-verbose-error} command line option, AArch64
110@item -mno-verbose-error
111This option disables verbose error messages in AArch64 gas.
112
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113@end table
114@c man end
115
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116@node AArch64 Extensions
117@section Architecture Extensions
118
119The table below lists the permitted architecture extensions that are
120supported by the assembler and the conditions under which they are
121automatically enabled.
122
123Multiple extensions may be specified, separated by a @code{+}.
124Extension mnemonics may also be removed from those the assembler
125accepts. This is done by prepending @code{no} to the option that adds
126the extension. Extensions that are removed must be listed after all
127extensions that have been added.
128
129Enabling an extension that requires other extensions will
130automatically cause those extensions to be enabled. Similarly,
131disabling an extension that is required by other extensions will
132automatically cause those extensions to be disabled.
133
134@multitable @columnfractions .12 .17 .17 .54
135@headitem Extension @tab Minimum Architecture @tab Enabled by default
136 @tab Description
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137@item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
138 @tab Enable the complex number SIMD extensions. This implies
139 @code{fp16} and @code{simd}.
af117b3c 140@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
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141 @tab Enable CRC instructions.
142@item @code{crypto} @tab ARMv8-A @tab No
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143 @tab Enable cryptographic extensions. This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
144@item @code{aes} @tab ARMv8-A @tab No
145 @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
146@item @code{sha2} @tab ARMv8-A @tab No
147 @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
148@item @code{sha3} @tab ARMv8.2-A @tab No
149 @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
150@item @code{sm4} @tab ARMv8.2-A @tab No
151 @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
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152@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
153 @tab Enable floating-point extensions.
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154@item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
155 @tab Enable ARMv8.2 16-bit floating-point support. This implies
156 @code{fp}.
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157@item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
158 @tab Enable Limited Ordering Regions extensions.
159@item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
160 @tab Enable Large System extensions.
161@item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
162 @tab Enable Privileged Access Never support.
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163@item @code{profile} @tab ARMv8.2-A @tab No
164 @tab Enable statistical profiling extensions.
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165@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
166 @tab Enable the Reliability, Availability and Serviceability
167 extension.
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168@item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
169 @tab Enable the weak release consistency extension.
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170@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
171 @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
172@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
173 @tab Enable Advanced SIMD extensions. This implies @code{fp}.
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174@item @code{sve} @tab ARMv8.2-A @tab No
175 @tab Enable the Scalable Vector Extensions. This implies @code{fp16},
176 @code{simd} and @code{compnum}.
68ffd936 177@item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
65a55fbb 178 @tab Enable the Dot Product extension. This implies @code{simd}.
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179@item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
180 @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
181 This implies @code{fp16}.
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182@end multitable
183
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184@node AArch64 Syntax
185@section Syntax
186@menu
187* AArch64-Chars:: Special Characters
188* AArch64-Regs:: Register Names
189* AArch64-Relocations:: Relocations
190@end menu
191
192@node AArch64-Chars
193@subsection Special Characters
194
195@cindex line comment character, AArch64
196@cindex AArch64 line comment character
197The presence of a @samp{//} on a line indicates the start of a comment
198that extends to the end of the current line. If a @samp{#} appears as
199the first character of a line, the whole line is treated as a comment.
200
201@cindex line separator, AArch64
202@cindex statement separator, AArch64
203@cindex AArch64 line separator
204The @samp{;} character can be used instead of a newline to separate
205statements.
206
207@cindex immediate character, AArch64
208@cindex AArch64 immediate character
209The @samp{#} can be optionally used to indicate immediate operands.
210
211@node AArch64-Regs
212@subsection Register Names
213
214@cindex AArch64 register names
215@cindex register names, AArch64
216Please refer to the section @samp{4.4 Register Names} of
217@samp{ARMv8 Instruction Set Overview}, which is available at
218@uref{http://infocenter.arm.com}.
219
220@node AArch64-Relocations
221@subsection Relocations
222
223@cindex relocations, AArch64
224@cindex AArch64 relocations
225@cindex MOVN, MOVZ and MOVK group relocations, AArch64
226Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
227by prefixing the label with @samp{#:abs_g2:} etc.
228For example to load the 48-bit absolute address of @var{foo} into x0:
229
230@smallexample
231 movz x0, #:abs_g2:foo // bits 32-47, overflow check
232 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
233 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
234@end smallexample
235
236@cindex ADRP, ADD, LDR/STR group relocations, AArch64
237Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
238instructions can be generated by prefixing the label with
34fd659b 239@samp{:pg_hi21:} and @samp{#:lo12:} respectively.
a06ea964 240
34bca508 241For example to use 33-bit (+/-4GB) pc-relative addressing to
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242load the address of @var{foo} into x0:
243
244@smallexample
34fd659b 245 adrp x0, :pg_hi21:foo
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246 add x0, x0, #:lo12:foo
247@end smallexample
248
249Or to load the value of @var{foo} into x0:
250
251@smallexample
34fd659b 252 adrp x0, :pg_hi21:foo
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253 ldr x0, [x0, #:lo12:foo]
254@end smallexample
255
34fd659b 256Note that @samp{:pg_hi21:} is optional.
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257
258@smallexample
259 adrp x0, foo
260@end smallexample
261
262is equivalent to
263
264@smallexample
34fd659b 265 adrp x0, :pg_hi21:foo
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266@end smallexample
267
268@node AArch64 Floating Point
269@section Floating Point
270
271@cindex floating point, AArch64 (@sc{ieee})
272@cindex AArch64 floating point (@sc{ieee})
273The AArch64 architecture uses @sc{ieee} floating-point numbers.
274
275@node AArch64 Directives
276@section AArch64 Machine Directives
277
278@cindex machine directives, AArch64
279@cindex AArch64 machine directives
280@table @code
281
282@c AAAAAAAAAAAAAAAAAAAAAAAAA
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283
284@cindex @code{.arch} directive, AArch64
285@item .arch @var{name}
286Select the target architecture. Valid values for @var{name} are the same as
287for the @option{-march} commandline option.
288
289Specifying @code{.arch} clears any previously selected architecture
290extensions.
291
292@cindex @code{.arch_extension} directive, AArch64
293@item .arch_extension @var{name}
294Add or remove an architecture extension to the target architecture. Valid
295values for @var{name} are the same as those accepted as architectural
296extensions by the @option{-mcpu} commandline option.
297
298@code{.arch_extension} may be used multiple times to add or remove extensions
299incrementally to the architecture being compiled for.
300
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301@c BBBBBBBBBBBBBBBBBBBBBBBBBB
302
303@cindex @code{.bss} directive, AArch64
304@item .bss
305This directive switches to the @code{.bss} section.
306
307@c CCCCCCCCCCCCCCCCCCCCCCCCCC
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308
309@cindex @code{.cpu} directive, AArch64
310@item .cpu @var{name}
311Set the target processor. Valid values for @var{name} are the same as
312those accepted by the @option{-mcpu=} command line option.
313
a06ea964 314@c DDDDDDDDDDDDDDDDDDDDDDDDDD
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315
316@cindex @code{.dword} directive, AArch64
317@item .dword @var{expressions}
318The @code{.dword} directive produces 64 bit values.
319
a06ea964 320@c EEEEEEEEEEEEEEEEEEEEEEEEEE
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321
322@cindex @code{.even} directive, AArch64
323@item .even
324The @code{.even} directive aligns the output on the next even byte
325boundary.
326
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327@c FFFFFFFFFFFFFFFFFFFFFFFFFF
328@c GGGGGGGGGGGGGGGGGGGGGGGGGG
329@c HHHHHHHHHHHHHHHHHHHHHHHHHH
330@c IIIIIIIIIIIIIIIIIIIIIIIIII
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331
332@cindex @code{.inst} directive, AArch64
333@item .inst @var{expressions}
334Inserts the expressions into the output as if they were instructions,
335rather than data.
336
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337@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
338@c KKKKKKKKKKKKKKKKKKKKKKKKKK
339@c LLLLLLLLLLLLLLLLLLLLLLLLLL
340
341@cindex @code{.ltorg} directive, AArch64
342@item .ltorg
343This directive causes the current contents of the literal pool to be
344dumped into the current section (which is assumed to be the .text
345section) at the current location (aligned to a word boundary).
df359aa7 346GAS maintains a separate literal pool for each section and each
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347sub-section. The @code{.ltorg} directive will only affect the literal
348pool of the current section and sub-section. At the end of assembly
349all remaining, un-empty literal pools will automatically be dumped.
350
df359aa7 351Note - older versions of GAS would dump the current literal
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352pool any time a section change occurred. This is no longer done, since
353it prevents accurate control of the placement of literal pools.
354
355@c MMMMMMMMMMMMMMMMMMMMMMMMMM
356
357@c NNNNNNNNNNNNNNNNNNNNNNNNNN
358@c OOOOOOOOOOOOOOOOOOOOOOOOOO
359
360@c PPPPPPPPPPPPPPPPPPPPPPPPPP
361
362@cindex @code{.pool} directive, AArch64
363@item .pool
364This is a synonym for .ltorg.
365
366@c QQQQQQQQQQQQQQQQQQQQQQQQQQ
367@c RRRRRRRRRRRRRRRRRRRRRRRRRR
368
369@cindex @code{.req} directive, AArch64
370@item @var{name} .req @var{register name}
371This creates an alias for @var{register name} called @var{name}. For
372example:
373
374@smallexample
375 foo .req w0
376@end smallexample
377
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378ip0, ip1, lr and fp are automatically defined to
379alias to X16, X17, X30 and X29 respectively.
380
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381@c SSSSSSSSSSSSSSSSSSSSSSSSSS
382
383@c TTTTTTTTTTTTTTTTTTTTTTTTTT
384
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385@cindex @code{.tlsdescadd} directive, AArch64
386@item @code{.tlsdescadd}
387Emits a TLSDESC_ADD reloc on the next instruction.
388
389@cindex @code{.tlsdesccall} directive, AArch64
390@item @code{.tlsdesccall}
391Emits a TLSDESC_CALL reloc on the next instruction.
392
393@cindex @code{.tlsdescldr} directive, AArch64
394@item @code{.tlsdescldr}
395Emits a TLSDESC_LDR reloc on the next instruction.
396
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397@c UUUUUUUUUUUUUUUUUUUUUUUUUU
398
399@cindex @code{.unreq} directive, AArch64
400@item .unreq @var{alias-name}
401This undefines a register alias which was previously defined using the
402@code{req} directive. For example:
403
404@smallexample
405 foo .req w0
406 .unreq foo
407@end smallexample
408
409An error occurs if the name is undefined. Note - this pseudo op can
410be used to delete builtin in register name aliases (eg 'w0'). This
411should only be done if it is really necessary.
412
413@c VVVVVVVVVVVVVVVVVVVVVVVVVV
414
415@c WWWWWWWWWWWWWWWWWWWWWWWWWW
416@c XXXXXXXXXXXXXXXXXXXXXXXXXX
a06ea964 417
edc66de9 418@cindex @code{.xword} directive, AArch64
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419@item .xword @var{expressions}
420The @code{.xword} directive produces 64 bit values. This is the same
421as the @code{.dword} directive.
422
423@c YYYYYYYYYYYYYYYYYYYYYYYYYY
424@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
edc66de9 425
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426@end table
427
428@node AArch64 Opcodes
429@section Opcodes
430
431@cindex AArch64 opcodes
432@cindex opcodes for AArch64
df359aa7 433GAS implements all the standard AArch64 opcodes. It also
a06ea964 434implements several pseudo opcodes, including several synthetic load
34bca508 435instructions.
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436
437@table @code
438
439@cindex @code{LDR reg,=<expr>} pseudo op, AArch64
440@item LDR =
441@smallexample
442 ldr <register> , =<expression>
443@end smallexample
444
445The constant expression will be placed into the nearest literal pool (if it not
446already there) and a PC-relative LDR instruction will be generated.
447
448@end table
449
450For more information on the AArch64 instruction set and assembly language
451notation, see @samp{ARMv8 Instruction Set Overview} available at
452@uref{http://infocenter.arm.com}.
453
454
455@node AArch64 Mapping Symbols
456@section Mapping Symbols
457
458The AArch64 ELF specification requires that special symbols be inserted
459into object files to mark certain features:
460
461@table @code
462
463@cindex @code{$x}
464@item $x
465At the start of a region of code containing AArch64 instructions.
466
467@cindex @code{$d}
468@item $d
469At the start of a region of data.
470
471@end table
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