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1 | @c Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc. |
2 | @c Contributed by ARM Ltd. | |
3 | @c This is part of the GAS manual. | |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | @c man end | |
6 | ||
7 | @ifset GENERIC | |
8 | @page | |
9 | @node AArch64-Dependent | |
10 | @chapter AArch64 Dependent Features | |
11 | @end ifset | |
12 | ||
13 | @ifclear GENERIC | |
14 | @node Machine Dependencies | |
15 | @chapter AArch64 Dependent Features | |
16 | @end ifclear | |
17 | ||
18 | @cindex AArch64 support | |
19 | @cindex Thumb support | |
20 | @menu | |
21 | * AArch64 Options:: Options | |
22 | * AArch64 Syntax:: Syntax | |
23 | * AArch64 Floating Point:: Floating Point | |
24 | * AArch64 Directives:: AArch64 Machine Directives | |
25 | * AArch64 Opcodes:: Opcodes | |
26 | * AArch64 Mapping Symbols:: Mapping Symbols | |
27 | @end menu | |
28 | ||
29 | @node AArch64 Options | |
30 | @section Options | |
31 | @cindex AArch64 options (none) | |
32 | @cindex options for AArch64 (none) | |
33 | ||
34 | @c man begin OPTIONS | |
35 | @table @gcctabopt | |
36 | ||
37 | @cindex @code{-EB} command line option, AArch64 | |
38 | @item -EB | |
39 | This option specifies that the output generated by the assembler should | |
40 | be marked as being encoded for a big-endian processor. | |
41 | ||
42 | @cindex @code{-EL} command line option, AArch64 | |
43 | @item -EL | |
44 | This option specifies that the output generated by the assembler should | |
45 | be marked as being encoded for a little-endian processor. | |
46 | ||
69091a2c YZ |
47 | @cindex @code{-mabi=} command line option, AArch64 |
48 | @item -mabi=@var{abi} | |
49 | Specify which ABI the source code uses. The recognized arguments | |
50 | are: @code{ilp32} and @code{lp64}, which decides the generated object | |
51 | file in ELF32 and ELF64 format respectively. The default is @code{lp64}. | |
52 | ||
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53 | @end table |
54 | @c man end | |
55 | ||
56 | @node AArch64 Syntax | |
57 | @section Syntax | |
58 | @menu | |
59 | * AArch64-Chars:: Special Characters | |
60 | * AArch64-Regs:: Register Names | |
61 | * AArch64-Relocations:: Relocations | |
62 | @end menu | |
63 | ||
64 | @node AArch64-Chars | |
65 | @subsection Special Characters | |
66 | ||
67 | @cindex line comment character, AArch64 | |
68 | @cindex AArch64 line comment character | |
69 | The presence of a @samp{//} on a line indicates the start of a comment | |
70 | that extends to the end of the current line. If a @samp{#} appears as | |
71 | the first character of a line, the whole line is treated as a comment. | |
72 | ||
73 | @cindex line separator, AArch64 | |
74 | @cindex statement separator, AArch64 | |
75 | @cindex AArch64 line separator | |
76 | The @samp{;} character can be used instead of a newline to separate | |
77 | statements. | |
78 | ||
79 | @cindex immediate character, AArch64 | |
80 | @cindex AArch64 immediate character | |
81 | The @samp{#} can be optionally used to indicate immediate operands. | |
82 | ||
83 | @node AArch64-Regs | |
84 | @subsection Register Names | |
85 | ||
86 | @cindex AArch64 register names | |
87 | @cindex register names, AArch64 | |
88 | Please refer to the section @samp{4.4 Register Names} of | |
89 | @samp{ARMv8 Instruction Set Overview}, which is available at | |
90 | @uref{http://infocenter.arm.com}. | |
91 | ||
92 | @node AArch64-Relocations | |
93 | @subsection Relocations | |
94 | ||
95 | @cindex relocations, AArch64 | |
96 | @cindex AArch64 relocations | |
97 | @cindex MOVN, MOVZ and MOVK group relocations, AArch64 | |
98 | Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated | |
99 | by prefixing the label with @samp{#:abs_g2:} etc. | |
100 | For example to load the 48-bit absolute address of @var{foo} into x0: | |
101 | ||
102 | @smallexample | |
103 | movz x0, #:abs_g2:foo // bits 32-47, overflow check | |
104 | movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check | |
105 | movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check | |
106 | @end smallexample | |
107 | ||
108 | @cindex ADRP, ADD, LDR/STR group relocations, AArch64 | |
109 | Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR} | |
110 | instructions can be generated by prefixing the label with | |
111 | @samp{#:pg_hi21:} and @samp{#:lo12:} respectively. | |
112 | ||
34bca508 | 113 | For example to use 33-bit (+/-4GB) pc-relative addressing to |
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114 | load the address of @var{foo} into x0: |
115 | ||
116 | @smallexample | |
117 | adrp x0, #:pg_hi21:foo | |
118 | add x0, x0, #:lo12:foo | |
119 | @end smallexample | |
120 | ||
121 | Or to load the value of @var{foo} into x0: | |
122 | ||
123 | @smallexample | |
124 | adrp x0, #:pg_hi21:foo | |
125 | ldr x0, [x0, #:lo12:foo] | |
126 | @end smallexample | |
127 | ||
128 | Note that @samp{#:pg_hi21:} is optional. | |
129 | ||
130 | @smallexample | |
131 | adrp x0, foo | |
132 | @end smallexample | |
133 | ||
134 | is equivalent to | |
135 | ||
136 | @smallexample | |
137 | adrp x0, #:pg_hi21:foo | |
138 | @end smallexample | |
139 | ||
140 | @node AArch64 Floating Point | |
141 | @section Floating Point | |
142 | ||
143 | @cindex floating point, AArch64 (@sc{ieee}) | |
144 | @cindex AArch64 floating point (@sc{ieee}) | |
145 | The AArch64 architecture uses @sc{ieee} floating-point numbers. | |
146 | ||
147 | @node AArch64 Directives | |
148 | @section AArch64 Machine Directives | |
149 | ||
150 | @cindex machine directives, AArch64 | |
151 | @cindex AArch64 machine directives | |
152 | @table @code | |
153 | ||
154 | @c AAAAAAAAAAAAAAAAAAAAAAAAA | |
155 | @c BBBBBBBBBBBBBBBBBBBBBBBBBB | |
156 | ||
157 | @cindex @code{.bss} directive, AArch64 | |
158 | @item .bss | |
159 | This directive switches to the @code{.bss} section. | |
160 | ||
161 | @c CCCCCCCCCCCCCCCCCCCCCCCCCC | |
162 | @c DDDDDDDDDDDDDDDDDDDDDDDDDD | |
163 | @c EEEEEEEEEEEEEEEEEEEEEEEEEE | |
164 | @c FFFFFFFFFFFFFFFFFFFFFFFFFF | |
165 | @c GGGGGGGGGGGGGGGGGGGGGGGGGG | |
166 | @c HHHHHHHHHHHHHHHHHHHHHHHHHH | |
167 | @c IIIIIIIIIIIIIIIIIIIIIIIIII | |
168 | @c JJJJJJJJJJJJJJJJJJJJJJJJJJ | |
169 | @c KKKKKKKKKKKKKKKKKKKKKKKKKK | |
170 | @c LLLLLLLLLLLLLLLLLLLLLLLLLL | |
171 | ||
172 | @cindex @code{.ltorg} directive, AArch64 | |
173 | @item .ltorg | |
174 | This directive causes the current contents of the literal pool to be | |
175 | dumped into the current section (which is assumed to be the .text | |
176 | section) at the current location (aligned to a word boundary). | |
177 | @code{GAS} maintains a separate literal pool for each section and each | |
178 | sub-section. The @code{.ltorg} directive will only affect the literal | |
179 | pool of the current section and sub-section. At the end of assembly | |
180 | all remaining, un-empty literal pools will automatically be dumped. | |
181 | ||
182 | Note - older versions of @code{GAS} would dump the current literal | |
183 | pool any time a section change occurred. This is no longer done, since | |
184 | it prevents accurate control of the placement of literal pools. | |
185 | ||
186 | @c MMMMMMMMMMMMMMMMMMMMMMMMMM | |
187 | ||
188 | @c NNNNNNNNNNNNNNNNNNNNNNNNNN | |
189 | @c OOOOOOOOOOOOOOOOOOOOOOOOOO | |
190 | ||
191 | @c PPPPPPPPPPPPPPPPPPPPPPPPPP | |
192 | ||
193 | @cindex @code{.pool} directive, AArch64 | |
194 | @item .pool | |
195 | This is a synonym for .ltorg. | |
196 | ||
197 | @c QQQQQQQQQQQQQQQQQQQQQQQQQQ | |
198 | @c RRRRRRRRRRRRRRRRRRRRRRRRRR | |
199 | ||
200 | @cindex @code{.req} directive, AArch64 | |
201 | @item @var{name} .req @var{register name} | |
202 | This creates an alias for @var{register name} called @var{name}. For | |
203 | example: | |
204 | ||
205 | @smallexample | |
206 | foo .req w0 | |
207 | @end smallexample | |
208 | ||
209 | @c SSSSSSSSSSSSSSSSSSSSSSSSSS | |
210 | ||
211 | @c TTTTTTTTTTTTTTTTTTTTTTTTTT | |
212 | ||
213 | @c UUUUUUUUUUUUUUUUUUUUUUUUUU | |
214 | ||
215 | @cindex @code{.unreq} directive, AArch64 | |
216 | @item .unreq @var{alias-name} | |
217 | This undefines a register alias which was previously defined using the | |
218 | @code{req} directive. For example: | |
219 | ||
220 | @smallexample | |
221 | foo .req w0 | |
222 | .unreq foo | |
223 | @end smallexample | |
224 | ||
225 | An error occurs if the name is undefined. Note - this pseudo op can | |
226 | be used to delete builtin in register name aliases (eg 'w0'). This | |
227 | should only be done if it is really necessary. | |
228 | ||
229 | @c VVVVVVVVVVVVVVVVVVVVVVVVVV | |
230 | ||
231 | @c WWWWWWWWWWWWWWWWWWWWWWWWWW | |
232 | @c XXXXXXXXXXXXXXXXXXXXXXXXXX | |
233 | @c YYYYYYYYYYYYYYYYYYYYYYYYYY | |
234 | @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ | |
235 | ||
236 | @end table | |
237 | ||
238 | @node AArch64 Opcodes | |
239 | @section Opcodes | |
240 | ||
241 | @cindex AArch64 opcodes | |
242 | @cindex opcodes for AArch64 | |
243 | @code{@value{AS}} implements all the standard AArch64 opcodes. It also | |
244 | implements several pseudo opcodes, including several synthetic load | |
34bca508 | 245 | instructions. |
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246 | |
247 | @table @code | |
248 | ||
249 | @cindex @code{LDR reg,=<expr>} pseudo op, AArch64 | |
250 | @item LDR = | |
251 | @smallexample | |
252 | ldr <register> , =<expression> | |
253 | @end smallexample | |
254 | ||
255 | The constant expression will be placed into the nearest literal pool (if it not | |
256 | already there) and a PC-relative LDR instruction will be generated. | |
257 | ||
258 | @end table | |
259 | ||
260 | For more information on the AArch64 instruction set and assembly language | |
261 | notation, see @samp{ARMv8 Instruction Set Overview} available at | |
262 | @uref{http://infocenter.arm.com}. | |
263 | ||
264 | ||
265 | @node AArch64 Mapping Symbols | |
266 | @section Mapping Symbols | |
267 | ||
268 | The AArch64 ELF specification requires that special symbols be inserted | |
269 | into object files to mark certain features: | |
270 | ||
271 | @table @code | |
272 | ||
273 | @cindex @code{$x} | |
274 | @item $x | |
275 | At the start of a region of code containing AArch64 instructions. | |
276 | ||
277 | @cindex @code{$d} | |
278 | @item $d | |
279 | At the start of a region of data. | |
280 | ||
281 | @end table |