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b90efa5b | 1 | @c Copyright (C) 2009-2015 Free Software Foundation, Inc. |
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2 | @c Contributed by ARM Ltd. |
3 | @c This is part of the GAS manual. | |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | @c man end | |
6 | ||
7 | @ifset GENERIC | |
8 | @page | |
9 | @node AArch64-Dependent | |
10 | @chapter AArch64 Dependent Features | |
11 | @end ifset | |
12 | ||
13 | @ifclear GENERIC | |
14 | @node Machine Dependencies | |
15 | @chapter AArch64 Dependent Features | |
16 | @end ifclear | |
17 | ||
18 | @cindex AArch64 support | |
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19 | @menu |
20 | * AArch64 Options:: Options | |
df359aa7 | 21 | * AArch64 Extensions:: Extensions |
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22 | * AArch64 Syntax:: Syntax |
23 | * AArch64 Floating Point:: Floating Point | |
24 | * AArch64 Directives:: AArch64 Machine Directives | |
25 | * AArch64 Opcodes:: Opcodes | |
26 | * AArch64 Mapping Symbols:: Mapping Symbols | |
27 | @end menu | |
28 | ||
29 | @node AArch64 Options | |
30 | @section Options | |
31 | @cindex AArch64 options (none) | |
32 | @cindex options for AArch64 (none) | |
33 | ||
34 | @c man begin OPTIONS | |
35 | @table @gcctabopt | |
36 | ||
df359aa7 | 37 | @cindex @option{-EB} command line option, AArch64 |
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38 | @item -EB |
39 | This option specifies that the output generated by the assembler should | |
40 | be marked as being encoded for a big-endian processor. | |
41 | ||
df359aa7 | 42 | @cindex @option{-EL} command line option, AArch64 |
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43 | @item -EL |
44 | This option specifies that the output generated by the assembler should | |
45 | be marked as being encoded for a little-endian processor. | |
46 | ||
df359aa7 | 47 | @cindex @option{-mabi=} command line option, AArch64 |
69091a2c YZ |
48 | @item -mabi=@var{abi} |
49 | Specify which ABI the source code uses. The recognized arguments | |
50 | are: @code{ilp32} and @code{lp64}, which decides the generated object | |
51 | file in ELF32 and ELF64 format respectively. The default is @code{lp64}. | |
52 | ||
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53 | @cindex @option{-mcpu=} command line option, AArch64 |
54 | @item -mcpu=@var{processor}[+@var{extension}@dots{}] | |
55 | This option specifies the target processor. The assembler will issue an error | |
56 | message if an attempt is made to assemble an instruction which will not execute | |
57 | on the target processor. The following processor names are recognized: | |
58 | @code{cortex-a53}, | |
59 | @code{cortex-a57}, | |
2abdd192 | 60 | @code{cortex-a72}, |
2412d878 | 61 | @code{exynos-m1}, |
55fbd992 | 62 | @code{thunderx}, |
0a9ce86d | 63 | @code{xgene1} |
df359aa7 | 64 | and |
0a9ce86d | 65 | @code{xgene2}. |
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66 | The special name @code{all} may be used to allow the assembler to accept |
67 | instructions valid for any supported processor, including all optional | |
68 | extensions. | |
69 | ||
70 | In addition to the basic instruction set, the assembler can be told to | |
71 | accept, or restrict, various extension mnemonics that extend the | |
72 | processor. @xref{AArch64 Extensions}. | |
73 | ||
74 | If some implementations of a particular processor can have an | |
75 | extension, then then those extensions are automatically enabled. | |
76 | Consequently, you will not normally have to specify any additional | |
77 | extensions. | |
78 | ||
79 | @cindex @option{-march=} command line option, AArch64 | |
80 | @item -march=@var{architecture}[+@var{extension}@dots{}] | |
81 | This option specifies the target architecture. The assembler will | |
82 | issue an error message if an attempt is made to assemble an | |
83 | instruction which will not execute on the target architecture. The | |
88f0ea34 MW |
84 | following architecture names are recognized: @code{armv8-a} and |
85 | @code{armv8.1-a}. | |
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86 | |
87 | If both @option{-mcpu} and @option{-march} are specified, the | |
88 | assembler will use the setting for @option{-mcpu}. If neither are | |
89 | specified, the assembler will default to @option{-mcpu=all}. | |
90 | ||
91 | The architecture option can be extended with the same instruction set | |
92 | extension options as the @option{-mcpu} option. Unlike | |
93 | @option{-mcpu}, extensions are not always enabled by default, | |
94 | @xref{AArch64 Extensions}. | |
95 | ||
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96 | @cindex @code{-mverbose-error} command line option, AArch64 |
97 | @item -mverbose-error | |
98 | This option enables verbose error messages for AArch64 gas. This option | |
99 | is enabled by default. | |
100 | ||
101 | @cindex @code{-mno-verbose-error} command line option, AArch64 | |
102 | @item -mno-verbose-error | |
103 | This option disables verbose error messages in AArch64 gas. | |
104 | ||
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105 | @end table |
106 | @c man end | |
107 | ||
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108 | @node AArch64 Extensions |
109 | @section Architecture Extensions | |
110 | ||
111 | The table below lists the permitted architecture extensions that are | |
112 | supported by the assembler and the conditions under which they are | |
113 | automatically enabled. | |
114 | ||
115 | Multiple extensions may be specified, separated by a @code{+}. | |
116 | Extension mnemonics may also be removed from those the assembler | |
117 | accepts. This is done by prepending @code{no} to the option that adds | |
118 | the extension. Extensions that are removed must be listed after all | |
119 | extensions that have been added. | |
120 | ||
121 | Enabling an extension that requires other extensions will | |
122 | automatically cause those extensions to be enabled. Similarly, | |
123 | disabling an extension that is required by other extensions will | |
124 | automatically cause those extensions to be disabled. | |
125 | ||
126 | @multitable @columnfractions .12 .17 .17 .54 | |
127 | @headitem Extension @tab Minimum Architecture @tab Enabled by default | |
128 | @tab Description | |
129 | @item @code{crc} @tab ARMv8-A @tab No | |
130 | @tab Enable CRC instructions. | |
131 | @item @code{crypto} @tab ARMv8-A @tab No | |
132 | @tab Enable cryptographic extensions. This implies @code{fp} and @code{simd}. | |
133 | @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later | |
134 | @tab Enable floating-point extensions. | |
135 | @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later | |
136 | @tab Enable Advanced SIMD extensions. This implies @code{fp}. | |
72ca8fad MW |
137 | @item @code{pan} @tab ARMv8-A @tab ARMv8-A or later |
138 | @tab Enable Privileged Access Never support. | |
290806fd MW |
139 | @item @code{lor} @tab ARMv8-A @tab ARMv8-A or later |
140 | @tab Enable Limited Ordering Regions extensions. | |
9e1f0fa7 MW |
141 | @item @code{rdma} @tab ARMv8-A @tab ARMv8-A or later |
142 | @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}. | |
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143 | @end multitable |
144 | ||
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145 | @node AArch64 Syntax |
146 | @section Syntax | |
147 | @menu | |
148 | * AArch64-Chars:: Special Characters | |
149 | * AArch64-Regs:: Register Names | |
150 | * AArch64-Relocations:: Relocations | |
151 | @end menu | |
152 | ||
153 | @node AArch64-Chars | |
154 | @subsection Special Characters | |
155 | ||
156 | @cindex line comment character, AArch64 | |
157 | @cindex AArch64 line comment character | |
158 | The presence of a @samp{//} on a line indicates the start of a comment | |
159 | that extends to the end of the current line. If a @samp{#} appears as | |
160 | the first character of a line, the whole line is treated as a comment. | |
161 | ||
162 | @cindex line separator, AArch64 | |
163 | @cindex statement separator, AArch64 | |
164 | @cindex AArch64 line separator | |
165 | The @samp{;} character can be used instead of a newline to separate | |
166 | statements. | |
167 | ||
168 | @cindex immediate character, AArch64 | |
169 | @cindex AArch64 immediate character | |
170 | The @samp{#} can be optionally used to indicate immediate operands. | |
171 | ||
172 | @node AArch64-Regs | |
173 | @subsection Register Names | |
174 | ||
175 | @cindex AArch64 register names | |
176 | @cindex register names, AArch64 | |
177 | Please refer to the section @samp{4.4 Register Names} of | |
178 | @samp{ARMv8 Instruction Set Overview}, which is available at | |
179 | @uref{http://infocenter.arm.com}. | |
180 | ||
181 | @node AArch64-Relocations | |
182 | @subsection Relocations | |
183 | ||
184 | @cindex relocations, AArch64 | |
185 | @cindex AArch64 relocations | |
186 | @cindex MOVN, MOVZ and MOVK group relocations, AArch64 | |
187 | Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated | |
188 | by prefixing the label with @samp{#:abs_g2:} etc. | |
189 | For example to load the 48-bit absolute address of @var{foo} into x0: | |
190 | ||
191 | @smallexample | |
192 | movz x0, #:abs_g2:foo // bits 32-47, overflow check | |
193 | movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check | |
194 | movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check | |
195 | @end smallexample | |
196 | ||
197 | @cindex ADRP, ADD, LDR/STR group relocations, AArch64 | |
198 | Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR} | |
199 | instructions can be generated by prefixing the label with | |
34fd659b | 200 | @samp{:pg_hi21:} and @samp{#:lo12:} respectively. |
a06ea964 | 201 | |
34bca508 | 202 | For example to use 33-bit (+/-4GB) pc-relative addressing to |
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203 | load the address of @var{foo} into x0: |
204 | ||
205 | @smallexample | |
34fd659b | 206 | adrp x0, :pg_hi21:foo |
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207 | add x0, x0, #:lo12:foo |
208 | @end smallexample | |
209 | ||
210 | Or to load the value of @var{foo} into x0: | |
211 | ||
212 | @smallexample | |
34fd659b | 213 | adrp x0, :pg_hi21:foo |
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214 | ldr x0, [x0, #:lo12:foo] |
215 | @end smallexample | |
216 | ||
34fd659b | 217 | Note that @samp{:pg_hi21:} is optional. |
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218 | |
219 | @smallexample | |
220 | adrp x0, foo | |
221 | @end smallexample | |
222 | ||
223 | is equivalent to | |
224 | ||
225 | @smallexample | |
34fd659b | 226 | adrp x0, :pg_hi21:foo |
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227 | @end smallexample |
228 | ||
229 | @node AArch64 Floating Point | |
230 | @section Floating Point | |
231 | ||
232 | @cindex floating point, AArch64 (@sc{ieee}) | |
233 | @cindex AArch64 floating point (@sc{ieee}) | |
234 | The AArch64 architecture uses @sc{ieee} floating-point numbers. | |
235 | ||
236 | @node AArch64 Directives | |
237 | @section AArch64 Machine Directives | |
238 | ||
239 | @cindex machine directives, AArch64 | |
240 | @cindex AArch64 machine directives | |
241 | @table @code | |
242 | ||
243 | @c AAAAAAAAAAAAAAAAAAAAAAAAA | |
8e02d7f5 JW |
244 | |
245 | @cindex @code{.arch} directive, AArch64 | |
246 | @item .arch @var{name} | |
247 | Select the target architecture. Valid values for @var{name} are the same as | |
248 | for the @option{-march} commandline option. | |
249 | ||
250 | Specifying @code{.arch} clears any previously selected architecture | |
251 | extensions. | |
252 | ||
253 | @cindex @code{.arch_extension} directive, AArch64 | |
254 | @item .arch_extension @var{name} | |
255 | Add or remove an architecture extension to the target architecture. Valid | |
256 | values for @var{name} are the same as those accepted as architectural | |
257 | extensions by the @option{-mcpu} commandline option. | |
258 | ||
259 | @code{.arch_extension} may be used multiple times to add or remove extensions | |
260 | incrementally to the architecture being compiled for. | |
261 | ||
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262 | @c BBBBBBBBBBBBBBBBBBBBBBBBBB |
263 | ||
264 | @cindex @code{.bss} directive, AArch64 | |
265 | @item .bss | |
266 | This directive switches to the @code{.bss} section. | |
267 | ||
268 | @c CCCCCCCCCCCCCCCCCCCCCCCCCC | |
269 | @c DDDDDDDDDDDDDDDDDDDDDDDDDD | |
270 | @c EEEEEEEEEEEEEEEEEEEEEEEEEE | |
271 | @c FFFFFFFFFFFFFFFFFFFFFFFFFF | |
272 | @c GGGGGGGGGGGGGGGGGGGGGGGGGG | |
273 | @c HHHHHHHHHHHHHHHHHHHHHHHHHH | |
274 | @c IIIIIIIIIIIIIIIIIIIIIIIIII | |
275 | @c JJJJJJJJJJJJJJJJJJJJJJJJJJ | |
276 | @c KKKKKKKKKKKKKKKKKKKKKKKKKK | |
277 | @c LLLLLLLLLLLLLLLLLLLLLLLLLL | |
278 | ||
279 | @cindex @code{.ltorg} directive, AArch64 | |
280 | @item .ltorg | |
281 | This directive causes the current contents of the literal pool to be | |
282 | dumped into the current section (which is assumed to be the .text | |
283 | section) at the current location (aligned to a word boundary). | |
df359aa7 | 284 | GAS maintains a separate literal pool for each section and each |
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285 | sub-section. The @code{.ltorg} directive will only affect the literal |
286 | pool of the current section and sub-section. At the end of assembly | |
287 | all remaining, un-empty literal pools will automatically be dumped. | |
288 | ||
df359aa7 | 289 | Note - older versions of GAS would dump the current literal |
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290 | pool any time a section change occurred. This is no longer done, since |
291 | it prevents accurate control of the placement of literal pools. | |
292 | ||
293 | @c MMMMMMMMMMMMMMMMMMMMMMMMMM | |
294 | ||
295 | @c NNNNNNNNNNNNNNNNNNNNNNNNNN | |
296 | @c OOOOOOOOOOOOOOOOOOOOOOOOOO | |
297 | ||
298 | @c PPPPPPPPPPPPPPPPPPPPPPPPPP | |
299 | ||
300 | @cindex @code{.pool} directive, AArch64 | |
301 | @item .pool | |
302 | This is a synonym for .ltorg. | |
303 | ||
304 | @c QQQQQQQQQQQQQQQQQQQQQQQQQQ | |
305 | @c RRRRRRRRRRRRRRRRRRRRRRRRRR | |
306 | ||
307 | @cindex @code{.req} directive, AArch64 | |
308 | @item @var{name} .req @var{register name} | |
309 | This creates an alias for @var{register name} called @var{name}. For | |
310 | example: | |
311 | ||
312 | @smallexample | |
313 | foo .req w0 | |
314 | @end smallexample | |
315 | ||
316 | @c SSSSSSSSSSSSSSSSSSSSSSSSSS | |
317 | ||
318 | @c TTTTTTTTTTTTTTTTTTTTTTTTTT | |
319 | ||
320 | @c UUUUUUUUUUUUUUUUUUUUUUUUUU | |
321 | ||
322 | @cindex @code{.unreq} directive, AArch64 | |
323 | @item .unreq @var{alias-name} | |
324 | This undefines a register alias which was previously defined using the | |
325 | @code{req} directive. For example: | |
326 | ||
327 | @smallexample | |
328 | foo .req w0 | |
329 | .unreq foo | |
330 | @end smallexample | |
331 | ||
332 | An error occurs if the name is undefined. Note - this pseudo op can | |
333 | be used to delete builtin in register name aliases (eg 'w0'). This | |
334 | should only be done if it is really necessary. | |
335 | ||
336 | @c VVVVVVVVVVVVVVVVVVVVVVVVVV | |
337 | ||
338 | @c WWWWWWWWWWWWWWWWWWWWWWWWWW | |
339 | @c XXXXXXXXXXXXXXXXXXXXXXXXXX | |
340 | @c YYYYYYYYYYYYYYYYYYYYYYYYYY | |
341 | @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ | |
342 | ||
edc66de9 TP |
343 | @cindex @code{.xword} directive, AArch64 |
344 | @item .xword | |
345 | The @code{.xword} directive produces 64 bit values. | |
346 | ||
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347 | @end table |
348 | ||
349 | @node AArch64 Opcodes | |
350 | @section Opcodes | |
351 | ||
352 | @cindex AArch64 opcodes | |
353 | @cindex opcodes for AArch64 | |
df359aa7 | 354 | GAS implements all the standard AArch64 opcodes. It also |
a06ea964 | 355 | implements several pseudo opcodes, including several synthetic load |
34bca508 | 356 | instructions. |
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357 | |
358 | @table @code | |
359 | ||
360 | @cindex @code{LDR reg,=<expr>} pseudo op, AArch64 | |
361 | @item LDR = | |
362 | @smallexample | |
363 | ldr <register> , =<expression> | |
364 | @end smallexample | |
365 | ||
366 | The constant expression will be placed into the nearest literal pool (if it not | |
367 | already there) and a PC-relative LDR instruction will be generated. | |
368 | ||
369 | @end table | |
370 | ||
371 | For more information on the AArch64 instruction set and assembly language | |
372 | notation, see @samp{ARMv8 Instruction Set Overview} available at | |
373 | @uref{http://infocenter.arm.com}. | |
374 | ||
375 | ||
376 | @node AArch64 Mapping Symbols | |
377 | @section Mapping Symbols | |
378 | ||
379 | The AArch64 ELF specification requires that special symbols be inserted | |
380 | into object files to mark certain features: | |
381 | ||
382 | @table @code | |
383 | ||
384 | @cindex @code{$x} | |
385 | @item $x | |
386 | At the start of a region of code containing AArch64 instructions. | |
387 | ||
388 | @cindex @code{$d} | |
389 | @item $d | |
390 | At the start of a region of data. | |
391 | ||
392 | @end table |