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6f2750fe | 1 | @c Copyright (C) 2000-2016 Free Software Foundation, Inc. |
2d73a4ca NC |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | ||
5 | @ifset GENERIC | |
6 | @page | |
7 | @node ARC-Dependent | |
8 | @chapter ARC Dependent Features | |
9 | @end ifset | |
10 | ||
11 | @ifclear GENERIC | |
12 | @node Machine Dependencies | |
13 | @chapter ARC Dependent Features | |
14 | @end ifclear | |
15 | ||
bcee8eb8 | 16 | @set ARC_CORE_DEFAULT 6 |
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17 | |
18 | @cindex ARC support | |
19 | @menu | |
20 | * ARC Options:: Options | |
21 | * ARC Syntax:: Syntax | |
2d73a4ca | 22 | * ARC Directives:: ARC Machine Directives |
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23 | * ARC Modifiers:: ARC Assembler Modifiers |
24 | * ARC Symbols:: ARC Pre-defined Symbols | |
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25 | * ARC Opcodes:: Opcodes |
26 | @end menu | |
27 | ||
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28 | @node ARC Options |
29 | @section Options | |
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30 | @cindex ARC options |
31 | @cindex options for ARC | |
32 | ||
33 | The following options control the type of CPU for which code is | |
34 | assembled, and generic constraints on the code generated: | |
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35 | |
36 | @table @code | |
37 | ||
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38 | @item -mcpu=@var{cpu} |
39 | @cindex @code{-mcpu=@var{cpu}} command line option, ARC | |
40 | Set architecture type and register usage for @var{cpu}. There are | |
41 | also shortcut alias options available for backward compatibility and | |
42 | convenience. Supported values for @var{cpu} are | |
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43 | |
44 | @table @code | |
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45 | @cindex @code{mA6} command line option, ARC |
46 | @cindex @code{marc600} command line option, ARC | |
47 | @item arc600 | |
48 | Assemble for ARC 600. Aliases: @code{-mA6}, @code{-mARC600}. | |
2d73a4ca | 49 | |
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50 | @item arc601 |
51 | @cindex @code{mARC601} command line option, ARC | |
52 | Assemble for ARC 601. Alias: @code{-mARC601}. | |
2d73a4ca | 53 | |
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54 | @item arc700 |
55 | @cindex @code{mA7} command line option, ARC | |
56 | @cindex @code{mARC700} command line option, ARC | |
57 | Assemble for ARC 700. Aliases: @code{-mA7}, @code{-mARC700}. | |
2d73a4ca | 58 | |
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59 | @item nps400 |
60 | Assemble for NPS400. | |
61 | ||
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62 | @item arcem |
63 | @cindex @code{mEM} command line option, ARC | |
64 | Assemble for ARC EM. Aliases: @code{-mEM} | |
2d73a4ca | 65 | |
886a2506 NC |
66 | @item archs |
67 | @cindex @code{mHS} command line option, ARC | |
68 | Assemble for ARC HS. Aliases: @code{-mHS}, @code{-mav2hs}. | |
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69 | |
70 | @end table | |
71 | ||
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72 | Note: the @code{.cpu} directive (@pxref{ARC Directives}) can |
73 | to be used to select a core variant from within assembly code. | |
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74 | |
75 | @cindex @code{-EB} command line option, ARC | |
76 | @item -EB | |
77 | This option specifies that the output generated by the assembler should | |
78 | be marked as being encoded for a big-endian processor. | |
79 | ||
80 | @cindex @code{-EL} command line option, ARC | |
81 | @item -EL | |
82 | This option specifies that the output generated by the assembler should | |
83 | be marked as being encoded for a little-endian processor - this is the | |
84 | default. | |
85 | ||
886a2506 NC |
86 | @cindex @code{-mcode-density} command line option, ARC |
87 | @item -mcode-density | |
88 | This option turns on Code Density instructions. Only valid for ARC EM | |
89 | processors. | |
90 | ||
4670103e CZ |
91 | @cindex @code{-mrelax} command line option, ARC |
92 | @item -mrelax | |
93 | Enable support for assembly-time relaxation. The assembler will | |
94 | replace a longer version of an instruction with a shorter one, | |
95 | whenever it is possible. | |
96 | ||
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97 | @end table |
98 | ||
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99 | @node ARC Syntax |
100 | @section Syntax | |
101 | @menu | |
102 | * ARC-Chars:: Special Characters | |
103 | * ARC-Regs:: Register Names | |
104 | @end menu | |
105 | ||
106 | @node ARC-Chars | |
107 | @subsection Special Characters | |
108 | ||
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109 | @table @code |
110 | @item % | |
111 | @cindex register name prefix character, ARC | |
112 | @cindex ARC register name prefix character | |
113 | A register name can optionally be prefixed by a @samp{%} character. So | |
114 | register @code{%r0} is equivalent to @code{r0} in the assembly code. | |
115 | ||
116 | @item # | |
7c31ae13 NC |
117 | @cindex line comment character, ARC |
118 | @cindex ARC line comment character | |
886a2506 NC |
119 | The presence of a @samp{#} character within a line (but not at the |
120 | start of a line) indicates the start of a comment that extends to the | |
121 | end of the current line. | |
122 | ||
123 | @emph{Note:} if a line starts with a @samp{#} character then it can | |
124 | also be a logical line number directive (@pxref{Comments}) or a | |
125 | preprocessor control command (@pxref{Preprocessing}). | |
126 | ||
127 | @item @@ | |
128 | @cindex symbol prefix character, ARC | |
129 | @cindex ARC symbol prefix character | |
130 | Prefixing an operand with an @samp{@@} specifies that the operand is a | |
131 | symbol and not a register. This is how the assembler disambiguates | |
132 | the use of an ARC register name as a symbol. So the instruction | |
133 | @example | |
134 | mov r0, @@r0 | |
135 | @end example | |
136 | moves the address of symbol @code{r0} into register @code{r0}. | |
137 | ||
138 | @item ` | |
7c31ae13 NC |
139 | @cindex line separator, ARC |
140 | @cindex statement separator, ARC | |
141 | @cindex ARC line separator | |
886a2506 NC |
142 | The @samp{`} (backtick) character is used to separate statements on a |
143 | single line. | |
144 | ||
145 | @cindex line | |
146 | @item - | |
147 | @cindex C preprocessor macro separator, ARC | |
148 | @cindex ARC C preprocessor macro separator | |
149 | Used as a separator to obtain a sequence of commands from a C | |
150 | preprocessor macro. | |
151 | ||
152 | @end table | |
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153 | |
154 | @node ARC-Regs | |
155 | @subsection Register Names | |
156 | ||
157 | @cindex ARC register names | |
158 | @cindex register names, ARC | |
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159 | The ARC assembler uses the following register names for its core |
160 | registers: | |
161 | ||
162 | @table @code | |
163 | @item r0-r31 | |
164 | @cindex core general registers, ARC | |
165 | @cindex ARC core general registers | |
166 | The core general registers. Registers @code{r26} through @code{r31} | |
167 | have special functions, and are usually referred to by those synonyms. | |
168 | ||
169 | @item gp | |
170 | @cindex global pointer, ARC | |
171 | @cindex ARC global pointer | |
172 | The global pointer and a synonym for @code{r26}. | |
173 | ||
174 | @item fp | |
175 | @cindex frame pointer, ARC | |
176 | @cindex ARC frame pointer | |
177 | The frame pointer and a synonym for @code{r27}. | |
178 | ||
179 | @item sp | |
180 | @cindex stack pointer, ARC | |
181 | @cindex ARC stack pointer | |
182 | The stack pointer and a synonym for @code{r28}. | |
183 | ||
184 | @item ilink1 | |
185 | @cindex level 1 interrupt link register, ARC | |
186 | @cindex ARC level 1 interrupt link register | |
187 | For ARC 600 and ARC 700, the level 1 interrupt link register and a | |
188 | synonym for @code{r29}. Not supported for ARCv2. | |
189 | ||
190 | @item ilink | |
191 | @cindex interrupt link register, ARC | |
192 | @cindex ARC interrupt link register | |
193 | For ARCv2, the interrupt link register and a synonym for @code{r29}. | |
194 | Not supported for ARC 600 and ARC 700. | |
195 | ||
196 | @item ilink2 | |
197 | @cindex level 2 interrupt link register, ARC | |
198 | @cindex ARC level 2 interrupt link register | |
199 | For ARC 600 and ARC 700, the level 2 interrupt link register and a | |
200 | synonym for @code{r30}. Not supported for ARC v2. | |
201 | ||
202 | @item blink | |
203 | @cindex link register, ARC | |
204 | @cindex ARC link register | |
205 | The link register and a synonym for @code{r31}. | |
206 | ||
207 | @item r32-r59 | |
208 | @cindex extension core registers, ARC | |
209 | @cindex ARC extension core registers | |
210 | The extension core registers. | |
211 | ||
212 | @item lp_count | |
213 | @cindex loop counter, ARC | |
214 | @cindex ARC loop counter | |
215 | The loop count register. | |
216 | ||
217 | @item pcl | |
218 | @cindex word aligned program counter, ARC | |
219 | @cindex ARC word aligned program counter | |
220 | The word aligned program counter. | |
221 | ||
222 | @end table | |
2d73a4ca | 223 | |
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224 | In addition the ARC processor has a large number of @emph{auxiliary |
225 | registers}. The precise set depends on the extensions being | |
226 | supported, but the following baseline set are always defined: | |
2d73a4ca | 227 | |
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228 | @table @code |
229 | @item identity | |
230 | @cindex Processor Identification register, ARC | |
231 | @cindex ARC Processor Identification register | |
232 | Processor Identification register. Auxiliary register address 0x4. | |
233 | ||
234 | @item pc | |
235 | @cindex Program Counter, ARC | |
236 | @cindex ARC Program Counter | |
237 | Program Counter. Auxiliary register address 0x6. | |
238 | ||
239 | @item status32 | |
240 | @cindex Status register, ARC | |
241 | @cindex ARC Status register | |
242 | Status register. Auxiliary register address 0x0a. | |
243 | ||
244 | @item bta | |
245 | @cindex Branch Target Address, ARC | |
246 | @cindex ARC Branch Target Address | |
247 | Branch Target Address. Auxiliary register address 0x412. | |
248 | ||
249 | @item ecr | |
250 | @cindex Exception Cause Register, ARC | |
251 | @cindex ARC Exception Cause Register | |
252 | Exception Cause Register. Auxiliary register address 0x403. | |
253 | ||
254 | @item int_vector_base | |
255 | @cindex Interrupt Vector Base address, ARC | |
256 | @cindex ARC Interrupt Vector Base address | |
257 | Interrupt Vector Base address. Auxiliary register address 0x25. | |
258 | ||
259 | @item status32_p0 | |
260 | @cindex Stored STATUS32 register on entry to level P0 interrupts, ARC | |
261 | @cindex ARC Stored STATUS32 register on entry to level P0 interrupts | |
262 | Stored STATUS32 register on entry to level P0 interrupts. Auxiliary | |
263 | register address 0xb. | |
264 | ||
265 | @item aux_user_sp | |
266 | @cindex Saved User Stack Pointer, ARC | |
267 | @cindex ARC Saved User Stack Pointer | |
268 | Saved User Stack Pointer. Auxiliary register address 0xd. | |
269 | ||
270 | @item eret | |
271 | @cindex Exception Return Address, ARC | |
272 | @cindex ARC Exception Return Address | |
273 | Exception Return Address. Auxiliary register address 0x400. | |
274 | ||
275 | @item erbta | |
276 | @cindex BTA saved on exception entry, ARC | |
277 | @cindex ARC BTA saved on exception entry | |
278 | BTA saved on exception entry. Auxiliary register address 0x401. | |
279 | ||
280 | @item erstatus | |
281 | @cindex STATUS32 saved on exception, ARC | |
282 | @cindex ARC STATUS32 saved on exception | |
283 | STATUS32 saved on exception. Auxiliary register address 0x402. | |
284 | ||
285 | @item bcr_ver | |
286 | @cindex Build Configuration Registers Version, ARC | |
287 | @cindex ARC Build Configuration Registers Version | |
288 | Build Configuration Registers Version. Auxiliary register address 0x60. | |
289 | ||
290 | @item bta_link_build | |
291 | @cindex Build configuration for: BTA Registers, ARC | |
292 | @cindex ARC Build configuration for: BTA Registers | |
293 | Build configuration for: BTA Registers. Auxiliary register address 0x63. | |
294 | ||
295 | @item vecbase_ac_build | |
296 | @cindex Build configuration for: Interrupts, ARC | |
297 | @cindex ARC Build configuration for: Interrupts | |
298 | Build configuration for: Interrupts. Auxiliary register address 0x68. | |
299 | ||
300 | @item rf_build | |
301 | @cindex Build configuration for: Core Registers, ARC | |
302 | @cindex ARC Build configuration for: Core Registers | |
303 | Build configuration for: Core Registers. Auxiliary register address 0x6e. | |
304 | ||
305 | @item dccm_build | |
306 | @cindex DCCM RAM Configuration Register, ARC | |
307 | @cindex ARC DCCM RAM Configuration Register | |
308 | DCCM RAM Configuration Register. Auxiliary register address 0xc1. | |
2d73a4ca | 309 | |
886a2506 | 310 | @end table |
2d73a4ca | 311 | |
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312 | Additional auxiliary register names are defined according to the |
313 | processor architecture version and extensions selected by the options. | |
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314 | |
315 | @node ARC Directives | |
316 | @section ARC Machine Directives | |
317 | ||
318 | @cindex machine directives, ARC | |
319 | @cindex ARC machine directives | |
320 | The ARC version of @code{@value{AS}} supports the following additional | |
321 | machine directives: | |
322 | ||
323 | @table @code | |
324 | ||
886a2506 | 325 | @cindex @code{lcomm} directive |
b99747ae | 326 | @item .lcomm @var{symbol}, @var{length}[, @var{alignment}] |
886a2506 NC |
327 | Reserve @var{length} (an absolute expression) bytes for a local common |
328 | denoted by @var{symbol}. The section and value of @var{symbol} are | |
329 | those of the new local common. The addresses are allocated in the bss | |
330 | section, so that at run-time the bytes start off zeroed. Since | |
331 | @var{symbol} is not declared global, it is normally not visible to | |
332 | @code{@value{LD}}. The optional third parameter, @var{alignment}, | |
333 | specifies the desired alignment of the symbol in the bss section, | |
334 | specified as a byte boundary (for example, an alignment of 16 means | |
335 | that the least significant 4 bits of the address should be zero). The | |
336 | alignment must be an absolute expression, and it must be a power of | |
337 | two. If no alignment is specified, as will set the alignment to the | |
338 | largest power of two less than or equal to the size of the symbol, up | |
339 | to a maximum of 16. | |
340 | ||
f36e33da | 341 | @cindex @code{lcommon} directive, ARC |
b99747ae | 342 | @item .lcommon @var{symbol}, @var{length}[, @var{alignment}] |
886a2506 NC |
343 | The same as @code{lcomm} directive. |
344 | ||
f36e33da | 345 | @cindex @code{cpu} directive, ARC |
b99747ae | 346 | @item .cpu @var{cpu} |
886a2506 NC |
347 | The @code{.cpu} directive must be followed by the desired core |
348 | version. Permitted values for CPU are: | |
802a113d | 349 | @table @code |
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350 | @item ARC600 |
351 | Assemble for the ARC600 instruction set. | |
2d73a4ca | 352 | |
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353 | @item ARC700 |
354 | Assemble for the ARC700 instruction set. | |
802a113d | 355 | |
2533af11 AB |
356 | @item NPS400 |
357 | Assemble for the NPS400 instruction set. | |
358 | ||
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359 | @item EM |
360 | Assemble for the ARC EM instruction set. | |
2d73a4ca | 361 | |
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362 | @item HS |
363 | Assemble for the ARC HS instruction set. | |
34bca508 | 364 | |
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365 | @end table |
366 | ||
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367 | Note: the @code{.cpu} directive overrides the command line option |
368 | @code{-mcpu=@var{cpu}}; a warning is emitted when the version is not | |
369 | consistent between the two. | |
b99747ae | 370 | |
f36e33da CZ |
371 | @item .extAuxRegister @var{name}, @var{addr}, @var{mode} |
372 | @cindex @code{extAuxRegister} directive, ARC | |
373 | Auxiliary registers can be defined in the assembler source code by | |
374 | using this directive. The first parameter, @var{name}, is the name of the | |
375 | new auxiliary register. The second parameter, @var{addr}, is | |
376 | address the of the auxiliary register. The third parameter, | |
377 | @var{mode}, specifies whether the register is readable and/or writable | |
378 | and is one of: | |
379 | @table @code | |
380 | @item r | |
381 | Read only; | |
382 | ||
383 | @item w | |
384 | Write only; | |
385 | ||
386 | @item r|w | |
387 | Read and write. | |
388 | ||
389 | @end table | |
390 | ||
391 | For example: | |
392 | @example | |
393 | .extAuxRegister mulhi, 0x12, w | |
394 | @end example | |
395 | specifies a write only extension auxiliary register, @var{mulhi} at | |
396 | address 0x12. | |
397 | ||
398 | @item .extCondCode @var{suffix}, @var{val} | |
399 | @cindex @code{extCondCode} directive, ARC | |
400 | ARC supports extensible condition codes. This directive defines a new | |
401 | condition code, to be known by the suffix, @var{suffix} and will | |
402 | depend on the value, @var{val} in the condition code. | |
403 | ||
404 | For example: | |
405 | @example | |
406 | .extCondCode is_busy,0x14 | |
407 | add.is_busy r1,r2,r3 | |
408 | @end example | |
409 | will only execute the @code{add} instruction if the condition code | |
410 | value is 0x14. | |
411 | ||
412 | @item .extCoreRegister @var{name}, @var{regnum}, @var{mode}, @var{shortcut} | |
413 | @cindex @code{extCoreRegister} directive, ARC | |
414 | Specifies an extension core register named @var{name} as a synonym for | |
415 | the register numbered @var{regnum}. The register number must be | |
416 | between 32 and 59. The third argument, @var{mode}, indicates whether | |
417 | the register is readable and/or writable and is one of: | |
418 | @table @code | |
419 | @item r | |
420 | Read only; | |
421 | ||
422 | @item w | |
423 | Write only; | |
424 | ||
425 | @item r|w | |
426 | Read and write. | |
427 | ||
428 | @end table | |
429 | ||
430 | The final parameter, @var{shortcut} indicates whether the register has | |
431 | a short cut in the pipeline. The valid values are: | |
432 | @table @code | |
433 | @item can_shortcut | |
434 | The register has a short cut in the pipeline; | |
435 | ||
436 | @item cannot_shortcut | |
437 | The register does not have a short cut in the pipeline. | |
438 | @end table | |
439 | ||
440 | For example: | |
441 | @example | |
442 | .extCoreRegister mlo, 57, r , can_shortcut | |
443 | @end example | |
444 | defines a read only extension core register, @code{mlo}, which is | |
445 | register 57, and can short cut the pipeline. | |
446 | ||
b99747ae | 447 | @item .extInstruction @var{name}, @var{opcode}, @var{subopcode}, @var{suffixclass}, @var{syntaxclass} |
f36e33da | 448 | @cindex @code{extInstruction} directive, ARC |
b99747ae CZ |
449 | ARC allows the user to specify extension instructions. These |
450 | extension instructions are not macros; the assembler creates encodings | |
451 | for use of these instructions according to the specification by the | |
452 | user. | |
453 | ||
454 | The first argument, @var{name}, gives the name of the instruction. | |
455 | ||
456 | The second argument, @var{opcode}, is the opcode to be used (bits 31:27 | |
457 | in the encoding). | |
458 | ||
459 | The third argument, @var{subopcode}, is the sub-opcode to be used, but | |
460 | the correct value also depends on the fifth argument, | |
461 | @var{syntaxclass} | |
462 | ||
463 | The fourth argument, @var{suffixclass}, determines the kinds of | |
464 | suffixes to be allowed. Valid values are: | |
465 | @table @code | |
466 | @item SUFFIX_NONE | |
467 | No suffixes are permitted; | |
468 | ||
469 | @item SUFFIX_COND | |
470 | Conditional suffixes are permitted; | |
471 | ||
472 | @item SUFFIX_FLAG | |
473 | Flag setting suffixes are permitted. | |
474 | ||
475 | @item SUFFIX_COND|SUFFIX_FLAG | |
476 | Both conditional and flag setting suffices are permitted. | |
477 | ||
478 | @end table | |
479 | ||
480 | The fifth and final argument, @var{syntaxclass}, determines the syntax | |
481 | class for the instruction. It can have the following values: | |
482 | @table @code | |
483 | @item SYNTAX_2OP | |
484 | Two Operand Instruction; | |
485 | ||
486 | @item SYNTAX_3OP | |
487 | Three Operand Instruction. | |
945e0f82 CZ |
488 | |
489 | @item SYNTAX_1OP | |
490 | One Operand Instruction. | |
491 | ||
492 | @item SYNTAX_NOP | |
493 | No Operand Instruction. | |
b99747ae CZ |
494 | @end table |
495 | ||
496 | The syntax class may be followed by @samp{|} and one of the following | |
497 | modifiers. | |
498 | @table @code | |
499 | ||
500 | @item OP1_MUST_BE_IMM | |
501 | Modifies syntax class @code{SYNTAX_3OP}, specifying that the first | |
502 | operand of a three-operand instruction must be an immediate (i.e., the | |
503 | result is discarded). This is usually used to set the flags using | |
504 | specific instructions and not retain results. | |
505 | ||
506 | @item OP1_IMM_IMPLIED | |
507 | Modifies syntax class @code{SYNTAX_20P}, specifying that there is an | |
508 | implied immediate destination operand which does not appear in the | |
509 | syntax. | |
510 | ||
511 | For example, if the source code contains an instruction like: | |
512 | @example | |
513 | inst r1,r2 | |
514 | @end example | |
515 | the first argument is an implied immediate (that is, the result is | |
516 | discarded). This is the same as though the source code were: inst | |
517 | 0,r1,r2. | |
518 | ||
519 | @end table | |
520 | ||
521 | For example, defining a 64-bit multiplier with immediate operands: | |
522 | @example | |
523 | .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG, | |
524 | SYNTAX_3OP|OP1_MUST_BE_IMM | |
525 | @end example | |
526 | which specifies an extension instruction named @code{mp64} with 3 | |
527 | operands. It sets the flags and can be used with a condition code, | |
528 | for which the first operand is an immediate, i.e. equivalent to | |
529 | discarding the result of the operation. | |
530 | ||
531 | A two operands instruction variant would be: | |
532 | @example | |
533 | .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND, | |
534 | SYNTAX_2OP|OP1_IMM_IMPLIED | |
535 | @end example | |
536 | which describes a two operand instruction with an implicit first | |
537 | immediate operand. The result of this operation would be discarded. | |
538 | ||
802a113d NC |
539 | @end table |
540 | ||
886a2506 NC |
541 | @node ARC Modifiers |
542 | @section ARC Assembler Modifiers | |
802a113d | 543 | |
886a2506 NC |
544 | The following additional assembler modifiers have been added for |
545 | position-independent code. These modifiers are available only with | |
546 | the ARC 700 and above processors and generate relocation entries, | |
547 | which are interpreted by the linker as follows: | |
802a113d NC |
548 | |
549 | @table @code | |
886a2506 NC |
550 | @item @@pcl(@var{symbol}) |
551 | @cindex @@pcl(@var{symbol}), ARC modifier | |
552 | Relative distance of @var{symbol}'s from the current program counter | |
553 | location. | |
554 | ||
555 | @item @@gotpc(@var{symbol}) | |
556 | @cindex @@gotpc(@var{symbol}), ARC modifier | |
557 | Relative distance of @var{symbol}'s Global Offset Table entry from the | |
558 | current program counter location. | |
559 | ||
560 | @item @@gotoff(@var{symbol}) | |
561 | @cindex @@gotoff(@var{symbol}), ARC modifier | |
562 | Distance of @var{symbol} from the base of the Global Offset Table. | |
563 | ||
564 | @item @@plt(@var{symbol}) | |
565 | @cindex @@plt(@var{symbol}), ARC modifier | |
566 | Distance of @var{symbol}'s Procedure Linkage Table entry from the | |
567 | current program counter. This is valid only with branch and link | |
568 | instructions and PC-relative calls. | |
569 | ||
570 | @item @@sda(@var{symbol}) | |
571 | @cindex @@sda(@var{symbol}), ARC modifier | |
572 | Relative distance of @var{symbol} from the base of the Small Data | |
573 | Pointer. | |
802a113d | 574 | |
886a2506 | 575 | @end table |
2d73a4ca | 576 | |
886a2506 NC |
577 | @node ARC Symbols |
578 | @section ARC Pre-defined Symbols | |
2d73a4ca | 579 | |
886a2506 NC |
580 | The following assembler symbols will prove useful when developing |
581 | position-independent code. These symbols are available only with the | |
582 | ARC 700 and above processors. | |
2d73a4ca | 583 | |
886a2506 NC |
584 | @table @code |
585 | @item __GLOBAL_OFFSET_TABLE__ | |
586 | @cindex __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol | |
587 | Symbol referring to the base of the Global Offset Table. | |
2d73a4ca | 588 | |
886a2506 NC |
589 | @item __DYNAMIC__ |
590 | @cindex __DYNAMIC__, ARC pre-defined symbol | |
591 | An alias for the Global Offset Table | |
592 | @code{Base__GLOBAL_OFFSET_TABLE__}. It can be used only with | |
593 | @code{@@gotpc} modifiers. | |
2d73a4ca NC |
594 | |
595 | @end table | |
596 | ||
2d73a4ca NC |
597 | @node ARC Opcodes |
598 | @section Opcodes | |
599 | ||
600 | @cindex ARC opcodes | |
601 | @cindex opcodes for ARC | |
602 | ||
603 | For information on the ARC instruction set, see @cite{ARC Programmers | |
886a2506 | 604 | Reference Manual}, available where you download the processor IP library. |