Commit | Line | Data |
---|---|---|
aa820537 AM |
1 | @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, |
2 | @c 2006, 2007, 2008, 2009 Free Software Foundation, Inc. | |
252b5132 RH |
3 | @c This is part of the GAS manual. |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | ||
6 | @ifset GENERIC | |
7 | @page | |
8 | @node ARM-Dependent | |
9 | @chapter ARM Dependent Features | |
10 | @end ifset | |
11 | ||
12 | @ifclear GENERIC | |
13 | @node Machine Dependencies | |
14 | @chapter ARM Dependent Features | |
15 | @end ifclear | |
16 | ||
17 | @cindex ARM support | |
18 | @cindex Thumb support | |
19 | @menu | |
20 | * ARM Options:: Options | |
21 | * ARM Syntax:: Syntax | |
22 | * ARM Floating Point:: Floating Point | |
23 | * ARM Directives:: ARM Machine Directives | |
24 | * ARM Opcodes:: Opcodes | |
6057a28f | 25 | * ARM Mapping Symbols:: Mapping Symbols |
7da4f750 | 26 | * ARM Unwinding Tutorial:: Unwinding |
252b5132 RH |
27 | @end menu |
28 | ||
29 | @node ARM Options | |
30 | @section Options | |
31 | @cindex ARM options (none) | |
32 | @cindex options for ARM (none) | |
adcf07e6 | 33 | |
252b5132 | 34 | @table @code |
adcf07e6 | 35 | |
03b1477f | 36 | @cindex @code{-mcpu=} command line option, ARM |
92081f48 | 37 | @item -mcpu=@var{processor}[+@var{extension}@dots{}] |
252b5132 RH |
38 | This option specifies the target processor. The assembler will issue an |
39 | error message if an attempt is made to assemble an instruction which | |
03b1477f RE |
40 | will not execute on the target processor. The following processor names are |
41 | recognized: | |
42 | @code{arm1}, | |
43 | @code{arm2}, | |
44 | @code{arm250}, | |
45 | @code{arm3}, | |
46 | @code{arm6}, | |
47 | @code{arm60}, | |
48 | @code{arm600}, | |
49 | @code{arm610}, | |
50 | @code{arm620}, | |
51 | @code{arm7}, | |
52 | @code{arm7m}, | |
53 | @code{arm7d}, | |
54 | @code{arm7dm}, | |
55 | @code{arm7di}, | |
56 | @code{arm7dmi}, | |
57 | @code{arm70}, | |
58 | @code{arm700}, | |
59 | @code{arm700i}, | |
60 | @code{arm710}, | |
61 | @code{arm710t}, | |
62 | @code{arm720}, | |
63 | @code{arm720t}, | |
64 | @code{arm740t}, | |
65 | @code{arm710c}, | |
66 | @code{arm7100}, | |
67 | @code{arm7500}, | |
68 | @code{arm7500fe}, | |
69 | @code{arm7t}, | |
70 | @code{arm7tdmi}, | |
1ff4677c | 71 | @code{arm7tdmi-s}, |
03b1477f RE |
72 | @code{arm8}, |
73 | @code{arm810}, | |
74 | @code{strongarm}, | |
75 | @code{strongarm1}, | |
76 | @code{strongarm110}, | |
77 | @code{strongarm1100}, | |
78 | @code{strongarm1110}, | |
79 | @code{arm9}, | |
80 | @code{arm920}, | |
81 | @code{arm920t}, | |
82 | @code{arm922t}, | |
83 | @code{arm940t}, | |
84 | @code{arm9tdmi}, | |
7fac0536 NC |
85 | @code{fa526} (Faraday FA526 processor), |
86 | @code{fa626} (Faraday FA626 processor), | |
03b1477f | 87 | @code{arm9e}, |
7de9afa2 | 88 | @code{arm926e}, |
1ff4677c | 89 | @code{arm926ej-s}, |
03b1477f RE |
90 | @code{arm946e-r0}, |
91 | @code{arm946e}, | |
db8ac8f9 | 92 | @code{arm946e-s}, |
03b1477f RE |
93 | @code{arm966e-r0}, |
94 | @code{arm966e}, | |
db8ac8f9 PB |
95 | @code{arm966e-s}, |
96 | @code{arm968e-s}, | |
03b1477f | 97 | @code{arm10t}, |
db8ac8f9 | 98 | @code{arm10tdmi}, |
03b1477f RE |
99 | @code{arm10e}, |
100 | @code{arm1020}, | |
101 | @code{arm1020t}, | |
7de9afa2 | 102 | @code{arm1020e}, |
db8ac8f9 | 103 | @code{arm1022e}, |
1ff4677c | 104 | @code{arm1026ej-s}, |
7fac0536 NC |
105 | @code{fa626te} (Faraday FA626TE processor), |
106 | @code{fa726te} (Faraday FA726TE processor), | |
1ff4677c RE |
107 | @code{arm1136j-s}, |
108 | @code{arm1136jf-s}, | |
db8ac8f9 PB |
109 | @code{arm1156t2-s}, |
110 | @code{arm1156t2f-s}, | |
0dd132b6 NC |
111 | @code{arm1176jz-s}, |
112 | @code{arm1176jzf-s}, | |
113 | @code{mpcore}, | |
114 | @code{mpcorenovfp}, | |
b38f9f31 | 115 | @code{cortex-a5}, |
62b3e311 | 116 | @code{cortex-a8}, |
15290f0a | 117 | @code{cortex-a9}, |
62b3e311 | 118 | @code{cortex-r4}, |
307c948d | 119 | @code{cortex-r4f}, |
62b3e311 | 120 | @code{cortex-m3}, |
5b19eaba NC |
121 | @code{cortex-m1}, |
122 | @code{cortex-m0}, | |
03b1477f RE |
123 | @code{ep9312} (ARM920 with Cirrus Maverick coprocessor), |
124 | @code{i80200} (Intel XScale processor) | |
e16bb312 | 125 | @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) |
03b1477f RE |
126 | and |
127 | @code{xscale}. | |
128 | The special name @code{all} may be used to allow the | |
129 | assembler to accept instructions valid for any ARM processor. | |
130 | ||
131 | In addition to the basic instruction set, the assembler can be told to | |
132 | accept various extension mnemonics that extend the processor using the | |
133 | co-processor instruction space. For example, @code{-mcpu=arm920+maverick} | |
134 | is equivalent to specifying @code{-mcpu=ep9312}. The following extensions | |
135 | are currently supported: | |
136 | @code{+maverick} | |
e16bb312 | 137 | @code{+iwmmxt} |
03b1477f RE |
138 | and |
139 | @code{+xscale}. | |
140 | ||
141 | @cindex @code{-march=} command line option, ARM | |
92081f48 | 142 | @item -march=@var{architecture}[+@var{extension}@dots{}] |
252b5132 RH |
143 | This option specifies the target architecture. The assembler will issue |
144 | an error message if an attempt is made to assemble an instruction which | |
03b1477f RE |
145 | will not execute on the target architecture. The following architecture |
146 | names are recognized: | |
147 | @code{armv1}, | |
148 | @code{armv2}, | |
149 | @code{armv2a}, | |
150 | @code{armv2s}, | |
151 | @code{armv3}, | |
152 | @code{armv3m}, | |
153 | @code{armv4}, | |
154 | @code{armv4xm}, | |
155 | @code{armv4t}, | |
156 | @code{armv4txm}, | |
157 | @code{armv5}, | |
158 | @code{armv5t}, | |
159 | @code{armv5txm}, | |
160 | @code{armv5te}, | |
09d92015 | 161 | @code{armv5texp}, |
c5f98204 | 162 | @code{armv6}, |
1ddd7f43 | 163 | @code{armv6j}, |
0dd132b6 NC |
164 | @code{armv6k}, |
165 | @code{armv6z}, | |
166 | @code{armv6zk}, | |
62b3e311 | 167 | @code{armv7}, |
c450d570 PB |
168 | @code{armv7-a}, |
169 | @code{armv7-r}, | |
170 | @code{armv7-m}, | |
9e3c6df6 | 171 | @code{armv7e-m}, |
e16bb312 | 172 | @code{iwmmxt} |
03b1477f RE |
173 | and |
174 | @code{xscale}. | |
175 | If both @code{-mcpu} and | |
176 | @code{-march} are specified, the assembler will use | |
177 | the setting for @code{-mcpu}. | |
178 | ||
179 | The architecture option can be extended with the same instruction set | |
180 | extension options as the @code{-mcpu} option. | |
181 | ||
182 | @cindex @code{-mfpu=} command line option, ARM | |
183 | @item -mfpu=@var{floating-point-format} | |
184 | ||
185 | This option specifies the floating point format to assemble for. The | |
186 | assembler will issue an error message if an attempt is made to assemble | |
187 | an instruction which will not execute on the target floating point unit. | |
188 | The following format options are recognized: | |
189 | @code{softfpa}, | |
190 | @code{fpe}, | |
bc89618b RE |
191 | @code{fpe2}, |
192 | @code{fpe3}, | |
03b1477f RE |
193 | @code{fpa}, |
194 | @code{fpa10}, | |
195 | @code{fpa11}, | |
196 | @code{arm7500fe}, | |
197 | @code{softvfp}, | |
198 | @code{softvfp+vfp}, | |
199 | @code{vfp}, | |
200 | @code{vfp10}, | |
201 | @code{vfp10-r0}, | |
202 | @code{vfp9}, | |
203 | @code{vfpxd}, | |
62f3b8c8 PB |
204 | @code{vfpv2}, |
205 | @code{vfpv3}, | |
206 | @code{vfpv3-fp16}, | |
207 | @code{vfpv3-d16}, | |
208 | @code{vfpv3-d16-fp16}, | |
209 | @code{vfpv3xd}, | |
210 | @code{vfpv3xd-d16}, | |
211 | @code{vfpv4}, | |
212 | @code{vfpv4-d16}, | |
09d92015 MM |
213 | @code{arm1020t}, |
214 | @code{arm1020e}, | |
b1cc4aeb | 215 | @code{arm1136jf-s}, |
62f3b8c8 PB |
216 | @code{maverick}, |
217 | @code{neon}, | |
03b1477f | 218 | and |
62f3b8c8 | 219 | @code{neon-vfpv4}. |
03b1477f RE |
220 | |
221 | In addition to determining which instructions are assembled, this option | |
222 | also affects the way in which the @code{.double} assembler directive behaves | |
223 | when assembling little-endian code. | |
224 | ||
225 | The default is dependent on the processor selected. For Architecture 5 or | |
226 | later, the default is to assembler for VFP instructions; for earlier | |
227 | architectures the default is to assemble for FPA instructions. | |
adcf07e6 | 228 | |
252b5132 RH |
229 | @cindex @code{-mthumb} command line option, ARM |
230 | @item -mthumb | |
03b1477f RE |
231 | This option specifies that the assembler should start assembling Thumb |
232 | instructions; that is, it should behave as though the file starts with a | |
233 | @code{.code 16} directive. | |
adcf07e6 | 234 | |
252b5132 RH |
235 | @cindex @code{-mthumb-interwork} command line option, ARM |
236 | @item -mthumb-interwork | |
237 | This option specifies that the output generated by the assembler should | |
238 | be marked as supporting interworking. | |
adcf07e6 | 239 | |
52970753 NC |
240 | @cindex @code{-mimplicit-it} command line option, ARM |
241 | @item -mimplicit-it=never | |
242 | @itemx -mimplicit-it=always | |
243 | @itemx -mimplicit-it=arm | |
244 | @itemx -mimplicit-it=thumb | |
245 | The @code{-mimplicit-it} option controls the behavior of the assembler when | |
246 | conditional instructions are not enclosed in IT blocks. | |
247 | There are four possible behaviors. | |
248 | If @code{never} is specified, such constructs cause a warning in ARM | |
249 | code and an error in Thumb-2 code. | |
250 | If @code{always} is specified, such constructs are accepted in both | |
251 | ARM and Thumb-2 code, where the IT instruction is added implicitly. | |
252 | If @code{arm} is specified, such constructs are accepted in ARM code | |
253 | and cause an error in Thumb-2 code. | |
254 | If @code{thumb} is specified, such constructs cause a warning in ARM | |
255 | code and are accepted in Thumb-2 code. If you omit this option, the | |
256 | behavior is equivalent to @code{-mimplicit-it=arm}. | |
e07e6e58 | 257 | |
5a5829dd NS |
258 | @cindex @code{-mapcs-26} command line option, ARM |
259 | @cindex @code{-mapcs-32} command line option, ARM | |
260 | @item -mapcs-26 | |
261 | @itemx -mapcs-32 | |
262 | These options specify that the output generated by the assembler should | |
252b5132 RH |
263 | be marked as supporting the indicated version of the Arm Procedure. |
264 | Calling Standard. | |
adcf07e6 | 265 | |
077b8428 NC |
266 | @cindex @code{-matpcs} command line option, ARM |
267 | @item -matpcs | |
268 | This option specifies that the output generated by the assembler should | |
269 | be marked as supporting the Arm/Thumb Procedure Calling Standard. If | |
270 | enabled this option will cause the assembler to create an empty | |
271 | debugging section in the object file called .arm.atpcs. Debuggers can | |
272 | use this to determine the ABI being used by. | |
273 | ||
adcf07e6 | 274 | @cindex @code{-mapcs-float} command line option, ARM |
252b5132 | 275 | @item -mapcs-float |
1be59579 | 276 | This indicates the floating point variant of the APCS should be |
252b5132 | 277 | used. In this variant floating point arguments are passed in FP |
550262c4 | 278 | registers rather than integer registers. |
adcf07e6 NC |
279 | |
280 | @cindex @code{-mapcs-reentrant} command line option, ARM | |
252b5132 RH |
281 | @item -mapcs-reentrant |
282 | This indicates that the reentrant variant of the APCS should be used. | |
283 | This variant supports position independent code. | |
adcf07e6 | 284 | |
33a392fb PB |
285 | @cindex @code{-mfloat-abi=} command line option, ARM |
286 | @item -mfloat-abi=@var{abi} | |
287 | This option specifies that the output generated by the assembler should be | |
288 | marked as using specified floating point ABI. | |
289 | The following values are recognized: | |
290 | @code{soft}, | |
291 | @code{softfp} | |
292 | and | |
293 | @code{hard}. | |
294 | ||
d507cf36 PB |
295 | @cindex @code{-eabi=} command line option, ARM |
296 | @item -meabi=@var{ver} | |
297 | This option specifies which EABI version the produced object files should | |
298 | conform to. | |
b45619c0 | 299 | The following values are recognized: |
3a4a14e9 PB |
300 | @code{gnu}, |
301 | @code{4} | |
d507cf36 | 302 | and |
3a4a14e9 | 303 | @code{5}. |
d507cf36 | 304 | |
252b5132 RH |
305 | @cindex @code{-EB} command line option, ARM |
306 | @item -EB | |
307 | This option specifies that the output generated by the assembler should | |
308 | be marked as being encoded for a big-endian processor. | |
adcf07e6 | 309 | |
252b5132 RH |
310 | @cindex @code{-EL} command line option, ARM |
311 | @item -EL | |
312 | This option specifies that the output generated by the assembler should | |
313 | be marked as being encoded for a little-endian processor. | |
adcf07e6 | 314 | |
252b5132 RH |
315 | @cindex @code{-k} command line option, ARM |
316 | @cindex PIC code generation for ARM | |
317 | @item -k | |
a349d9dd PB |
318 | This option specifies that the output of the assembler should be marked |
319 | as position-independent code (PIC). | |
adcf07e6 | 320 | |
845b51d6 PB |
321 | @cindex @code{--fix-v4bx} command line option, ARM |
322 | @item --fix-v4bx | |
323 | Allow @code{BX} instructions in ARMv4 code. This is intended for use with | |
324 | the linker option of the same name. | |
325 | ||
278df34e NS |
326 | @cindex @code{-mwarn-deprecated} command line option, ARM |
327 | @item -mwarn-deprecated | |
328 | @itemx -mno-warn-deprecated | |
329 | Enable or disable warnings about using deprecated options or | |
330 | features. The default is to warn. | |
331 | ||
252b5132 RH |
332 | @end table |
333 | ||
334 | ||
335 | @node ARM Syntax | |
336 | @section Syntax | |
337 | @menu | |
cab7e4d9 | 338 | * ARM-Instruction-Set:: Instruction Set |
252b5132 RH |
339 | * ARM-Chars:: Special Characters |
340 | * ARM-Regs:: Register Names | |
b6895b4f | 341 | * ARM-Relocations:: Relocations |
99f1a7a7 | 342 | * ARM-Neon-Alignment:: NEON Alignment Specifiers |
252b5132 RH |
343 | @end menu |
344 | ||
cab7e4d9 NC |
345 | @node ARM-Instruction-Set |
346 | @subsection Instruction Set Syntax | |
347 | Two slightly different syntaxes are support for ARM and THUMB | |
348 | instructions. The default, @code{divided}, uses the old style where | |
349 | ARM and THUMB instructions had their own, separate syntaxes. The new, | |
350 | @code{unified} syntax, which can be selected via the @code{.syntax} | |
351 | directive, and has the following main features: | |
352 | ||
353 | @table @bullet | |
354 | @item | |
355 | Immediate operands do not require a @code{#} prefix. | |
356 | ||
357 | @item | |
358 | The @code{IT} instruction may appear, and if it does it is validated | |
359 | against subsequent conditional affixes. In ARM mode it does not | |
360 | generate machine code, in THUMB mode it does. | |
361 | ||
362 | @item | |
363 | For ARM instructions the conditional affixes always appear at the end | |
364 | of the instruction. For THUMB instructions conditional affixes can be | |
365 | used, but only inside the scope of an @code{IT} instruction. | |
366 | ||
367 | @item | |
368 | All of the instructions new to the V6T2 architecture (and later) are | |
369 | available. (Only a few such instructions can be written in the | |
370 | @code{divided} syntax). | |
371 | ||
372 | @item | |
373 | The @code{.N} and @code{.W} suffixes are recognized and honored. | |
374 | ||
375 | @item | |
376 | All instructions set the flags if and only if they have an @code{s} | |
377 | affix. | |
378 | @end table | |
379 | ||
252b5132 RH |
380 | @node ARM-Chars |
381 | @subsection Special Characters | |
382 | ||
383 | @cindex line comment character, ARM | |
384 | @cindex ARM line comment character | |
550262c4 NC |
385 | The presence of a @samp{@@} on a line indicates the start of a comment |
386 | that extends to the end of the current line. If a @samp{#} appears as | |
387 | the first character of a line, the whole line is treated as a comment. | |
388 | ||
389 | @cindex line separator, ARM | |
390 | @cindex statement separator, ARM | |
391 | @cindex ARM line separator | |
a349d9dd PB |
392 | The @samp{;} character can be used instead of a newline to separate |
393 | statements. | |
550262c4 NC |
394 | |
395 | @cindex immediate character, ARM | |
396 | @cindex ARM immediate character | |
397 | Either @samp{#} or @samp{$} can be used to indicate immediate operands. | |
252b5132 RH |
398 | |
399 | @cindex identifiers, ARM | |
400 | @cindex ARM identifiers | |
401 | *TODO* Explain about /data modifier on symbols. | |
402 | ||
403 | @node ARM-Regs | |
404 | @subsection Register Names | |
405 | ||
406 | @cindex ARM register names | |
407 | @cindex register names, ARM | |
408 | *TODO* Explain about ARM register naming, and the predefined names. | |
409 | ||
99f1a7a7 DG |
410 | @node ARM-Neon-Alignment |
411 | @subsection NEON Alignment Specifiers | |
412 | ||
413 | @cindex alignment for NEON instructions | |
414 | Some NEON load/store instructions allow an optional address | |
415 | alignment qualifier. | |
416 | The ARM documentation specifies that this is indicated by | |
417 | @samp{@@ @var{align}}. However GAS already interprets | |
418 | the @samp{@@} character as a "line comment" start, | |
419 | so @samp{: @var{align}} is used instead. For example: | |
420 | ||
421 | @smallexample | |
422 | vld1.8 @{q0@}, [r0, :128] | |
423 | @end smallexample | |
424 | ||
252b5132 RH |
425 | @node ARM Floating Point |
426 | @section Floating Point | |
427 | ||
428 | @cindex floating point, ARM (@sc{ieee}) | |
429 | @cindex ARM floating point (@sc{ieee}) | |
430 | The ARM family uses @sc{ieee} floating-point numbers. | |
431 | ||
b6895b4f PB |
432 | @node ARM-Relocations |
433 | @subsection ARM relocation generation | |
434 | ||
435 | @cindex data relocations, ARM | |
436 | @cindex ARM data relocations | |
437 | Specific data relocations can be generated by putting the relocation name | |
438 | in parentheses after the symbol name. For example: | |
439 | ||
440 | @smallexample | |
441 | .word foo(TARGET1) | |
442 | @end smallexample | |
443 | ||
444 | This will generate an @samp{R_ARM_TARGET1} relocation against the symbol | |
445 | @var{foo}. | |
446 | The following relocations are supported: | |
447 | @code{GOT}, | |
448 | @code{GOTOFF}, | |
449 | @code{TARGET1}, | |
450 | @code{TARGET2}, | |
451 | @code{SBREL}, | |
452 | @code{TLSGD}, | |
453 | @code{TLSLDM}, | |
454 | @code{TLSLDO}, | |
b43420e6 NC |
455 | @code{GOTTPOFF}, |
456 | @code{GOT_PREL} | |
b6895b4f PB |
457 | and |
458 | @code{TPOFF}. | |
459 | ||
460 | For compatibility with older toolchains the assembler also accepts | |
461 | @code{(PLT)} after branch targets. This will generate the deprecated | |
462 | @samp{R_ARM_PLT32} relocation. | |
463 | ||
464 | @cindex MOVW and MOVT relocations, ARM | |
465 | Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated | |
466 | by prefixing the value with @samp{#:lower16:} and @samp{#:upper16} | |
b45619c0 | 467 | respectively. For example to load the 32-bit address of foo into r0: |
252b5132 | 468 | |
b6895b4f PB |
469 | @smallexample |
470 | MOVW r0, #:lower16:foo | |
471 | MOVT r0, #:upper16:foo | |
472 | @end smallexample | |
252b5132 RH |
473 | |
474 | @node ARM Directives | |
475 | @section ARM Machine Directives | |
476 | ||
477 | @cindex machine directives, ARM | |
478 | @cindex ARM machine directives | |
479 | @table @code | |
480 | ||
4a6bc624 NS |
481 | @c AAAAAAAAAAAAAAAAAAAAAAAAA |
482 | ||
483 | @cindex @code{.2byte} directive, ARM | |
484 | @cindex @code{.4byte} directive, ARM | |
485 | @cindex @code{.8byte} directive, ARM | |
486 | @item .2byte @var{expression} [, @var{expression}]* | |
487 | @itemx .4byte @var{expression} [, @var{expression}]* | |
488 | @itemx .8byte @var{expression} [, @var{expression}]* | |
489 | These directives write 2, 4 or 8 byte values to the output section. | |
490 | ||
491 | @cindex @code{.align} directive, ARM | |
adcf07e6 NC |
492 | @item .align @var{expression} [, @var{expression}] |
493 | This is the generic @var{.align} directive. For the ARM however if the | |
494 | first argument is zero (ie no alignment is needed) the assembler will | |
495 | behave as if the argument had been 2 (ie pad to the next four byte | |
062b7c0c | 496 | boundary). This is for compatibility with ARM's own assembler. |
adcf07e6 | 497 | |
4a6bc624 NS |
498 | @cindex @code{.arch} directive, ARM |
499 | @item .arch @var{name} | |
500 | Select the target architecture. Valid values for @var{name} are the same as | |
501 | for the @option{-march} commandline option. | |
252b5132 | 502 | |
4a6bc624 NS |
503 | @cindex @code{.arm} directive, ARM |
504 | @item .arm | |
505 | This performs the same action as @var{.code 32}. | |
252b5132 | 506 | |
4a6bc624 NS |
507 | @anchor{arm_pad} |
508 | @cindex @code{.pad} directive, ARM | |
509 | @item .pad #@var{count} | |
510 | Generate unwinder annotations for a stack adjustment of @var{count} bytes. | |
511 | A positive value indicates the function prologue allocated stack space by | |
512 | decrementing the stack pointer. | |
0bbf2aa4 | 513 | |
4a6bc624 | 514 | @c BBBBBBBBBBBBBBBBBBBBBBBBBB |
0bbf2aa4 | 515 | |
4a6bc624 NS |
516 | @cindex @code{.bss} directive, ARM |
517 | @item .bss | |
518 | This directive switches to the @code{.bss} section. | |
0bbf2aa4 | 519 | |
4a6bc624 NS |
520 | @c CCCCCCCCCCCCCCCCCCCCCCCCCC |
521 | ||
522 | @cindex @code{.cantunwind} directive, ARM | |
523 | @item .cantunwind | |
524 | Prevents unwinding through the current function. No personality routine | |
525 | or exception table data is required or permitted. | |
526 | ||
527 | @cindex @code{.code} directive, ARM | |
528 | @item .code @code{[16|32]} | |
529 | This directive selects the instruction set being generated. The value 16 | |
530 | selects Thumb, with the value 32 selecting ARM. | |
531 | ||
532 | @cindex @code{.cpu} directive, ARM | |
533 | @item .cpu @var{name} | |
534 | Select the target processor. Valid values for @var{name} are the same as | |
535 | for the @option{-mcpu} commandline option. | |
536 | ||
537 | @c DDDDDDDDDDDDDDDDDDDDDDDDDD | |
538 | ||
539 | @cindex @code{.dn} and @code{.qn} directives, ARM | |
f467aa98 | 540 | @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]] |
1f9bb1ca | 541 | @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]] |
23753660 JB |
542 | |
543 | The @code{dn} and @code{qn} directives are used to create typed | |
544 | and/or indexed register aliases for use in Advanced SIMD Extension | |
545 | (Neon) instructions. The former should be used to create aliases | |
546 | of double-precision registers, and the latter to create aliases of | |
547 | quad-precision registers. | |
548 | ||
549 | If these directives are used to create typed aliases, those aliases can | |
550 | be used in Neon instructions instead of writing types after the mnemonic | |
551 | or after each operand. For example: | |
552 | ||
553 | @smallexample | |
554 | x .dn d2.f32 | |
555 | y .dn d3.f32 | |
556 | z .dn d4.f32[1] | |
557 | vmul x,y,z | |
558 | @end smallexample | |
559 | ||
560 | This is equivalent to writing the following: | |
561 | ||
562 | @smallexample | |
563 | vmul.f32 d2,d3,d4[1] | |
564 | @end smallexample | |
565 | ||
566 | Aliases created using @code{dn} or @code{qn} can be destroyed using | |
567 | @code{unreq}. | |
568 | ||
4a6bc624 | 569 | @c EEEEEEEEEEEEEEEEEEEEEEEEEE |
252b5132 | 570 | |
4a6bc624 NS |
571 | @cindex @code{.eabi_attribute} directive, ARM |
572 | @item .eabi_attribute @var{tag}, @var{value} | |
573 | Set the EABI object attribute @var{tag} to @var{value}. | |
252b5132 | 574 | |
4a6bc624 NS |
575 | The @var{tag} is either an attribute number, or one of the following: |
576 | @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch}, | |
577 | @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use}, | |
75375b3e | 578 | @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch}, |
4a6bc624 NS |
579 | @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config}, |
580 | @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data}, | |
581 | @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use}, | |
582 | @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding}, | |
583 | @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions}, | |
584 | @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model}, | |
75375b3e | 585 | @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved}, |
4a6bc624 NS |
586 | @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use}, |
587 | @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args}, | |
588 | @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals}, | |
589 | @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access}, | |
75375b3e | 590 | @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format}, |
cd21e546 | 591 | @code{Tag_MPextension_use}, @code{Tag_DIV_use}, |
4a6bc624 NS |
592 | @code{Tag_nodefaults}, @code{Tag_also_compatible_with}, |
593 | @code{Tag_conformance}, @code{Tag_T2EE_use}, | |
cd21e546 | 594 | @code{Tag_Virtualization_use} |
4a6bc624 NS |
595 | |
596 | The @var{value} is either a @code{number}, @code{"string"}, or | |
597 | @code{number, "string"} depending on the tag. | |
598 | ||
75375b3e MGD |
599 | Note - the following legacy values are also accepted by @var{tag}: |
600 | @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed}, | |
601 | @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension}, | |
602 | ||
4a6bc624 NS |
603 | @cindex @code{.even} directive, ARM |
604 | @item .even | |
605 | This directive aligns to an even-numbered address. | |
606 | ||
607 | @cindex @code{.extend} directive, ARM | |
608 | @cindex @code{.ldouble} directive, ARM | |
609 | @item .extend @var{expression} [, @var{expression}]* | |
610 | @itemx .ldouble @var{expression} [, @var{expression}]* | |
611 | These directives write 12byte long double floating-point values to the | |
612 | output section. These are not compatible with current ARM processors | |
613 | or ABIs. | |
614 | ||
615 | @c FFFFFFFFFFFFFFFFFFFFFFFFFF | |
616 | ||
617 | @anchor{arm_fnend} | |
618 | @cindex @code{.fnend} directive, ARM | |
619 | @item .fnend | |
620 | Marks the end of a function with an unwind table entry. The unwind index | |
621 | table entry is created when this directive is processed. | |
252b5132 | 622 | |
4a6bc624 NS |
623 | If no personality routine has been specified then standard personality |
624 | routine 0 or 1 will be used, depending on the number of unwind opcodes | |
625 | required. | |
626 | ||
627 | @anchor{arm_fnstart} | |
628 | @cindex @code{.fnstart} directive, ARM | |
629 | @item .fnstart | |
630 | Marks the start of a function with an unwind table entry. | |
631 | ||
632 | @cindex @code{.force_thumb} directive, ARM | |
252b5132 RH |
633 | @item .force_thumb |
634 | This directive forces the selection of Thumb instructions, even if the | |
635 | target processor does not support those instructions | |
636 | ||
4a6bc624 NS |
637 | @cindex @code{.fpu} directive, ARM |
638 | @item .fpu @var{name} | |
639 | Select the floating-point unit to assemble for. Valid values for @var{name} | |
640 | are the same as for the @option{-mfpu} commandline option. | |
252b5132 | 641 | |
4a6bc624 NS |
642 | @c GGGGGGGGGGGGGGGGGGGGGGGGGG |
643 | @c HHHHHHHHHHHHHHHHHHHHHHHHHH | |
e1da3f5b | 644 | |
4a6bc624 NS |
645 | @cindex @code{.handlerdata} directive, ARM |
646 | @item .handlerdata | |
647 | Marks the end of the current function, and the start of the exception table | |
648 | entry for that function. Anything between this directive and the | |
649 | @code{.fnend} directive will be added to the exception table entry. | |
650 | ||
651 | Must be preceded by a @code{.personality} or @code{.personalityindex} | |
652 | directive. | |
653 | ||
654 | @c IIIIIIIIIIIIIIIIIIIIIIIIII | |
c921be7d NC |
655 | |
656 | @cindex @code{.inst} directive, ARM | |
657 | @item .inst @var{opcode} [ , @dots{} ] | |
1f9bb1ca AS |
658 | @itemx .inst.n @var{opcode} [ , @dots{} ] |
659 | @itemx .inst.w @var{opcode} [ , @dots{} ] | |
c921be7d NC |
660 | Generates the instruction corresponding to the numerical value @var{opcode}. |
661 | @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be | |
662 | specified explicitly, overriding the normal encoding rules. | |
663 | ||
4a6bc624 NS |
664 | @c JJJJJJJJJJJJJJJJJJJJJJJJJJ |
665 | @c KKKKKKKKKKKKKKKKKKKKKKKKKK | |
666 | @c LLLLLLLLLLLLLLLLLLLLLLLLLL | |
667 | ||
668 | @item .ldouble @var{expression} [, @var{expression}]* | |
669 | See @code{.extend}. | |
5395a469 | 670 | |
252b5132 RH |
671 | @cindex @code{.ltorg} directive, ARM |
672 | @item .ltorg | |
673 | This directive causes the current contents of the literal pool to be | |
674 | dumped into the current section (which is assumed to be the .text | |
675 | section) at the current location (aligned to a word boundary). | |
3d0c9500 NC |
676 | @code{GAS} maintains a separate literal pool for each section and each |
677 | sub-section. The @code{.ltorg} directive will only affect the literal | |
678 | pool of the current section and sub-section. At the end of assembly | |
679 | all remaining, un-empty literal pools will automatically be dumped. | |
680 | ||
681 | Note - older versions of @code{GAS} would dump the current literal | |
682 | pool any time a section change occurred. This is no longer done, since | |
683 | it prevents accurate control of the placement of literal pools. | |
252b5132 | 684 | |
4a6bc624 | 685 | @c MMMMMMMMMMMMMMMMMMMMMMMMMM |
252b5132 | 686 | |
4a6bc624 NS |
687 | @cindex @code{.movsp} directive, ARM |
688 | @item .movsp @var{reg} [, #@var{offset}] | |
689 | Tell the unwinder that @var{reg} contains an offset from the current | |
690 | stack pointer. If @var{offset} is not specified then it is assumed to be | |
691 | zero. | |
7ed4c4c5 | 692 | |
4a6bc624 NS |
693 | @c NNNNNNNNNNNNNNNNNNNNNNNNNN |
694 | @c OOOOOOOOOOOOOOOOOOOOOOOOOO | |
7ed4c4c5 | 695 | |
4a6bc624 NS |
696 | @cindex @code{.object_arch} directive, ARM |
697 | @item .object_arch @var{name} | |
698 | Override the architecture recorded in the EABI object attribute section. | |
699 | Valid values for @var{name} are the same as for the @code{.arch} directive. | |
700 | Typically this is useful when code uses runtime detection of CPU features. | |
7ed4c4c5 | 701 | |
4a6bc624 NS |
702 | @c PPPPPPPPPPPPPPPPPPPPPPPPPP |
703 | ||
704 | @cindex @code{.packed} directive, ARM | |
705 | @item .packed @var{expression} [, @var{expression}]* | |
706 | This directive writes 12-byte packed floating-point values to the | |
707 | output section. These are not compatible with current ARM processors | |
708 | or ABIs. | |
709 | ||
710 | @cindex @code{.pad} directive, ARM | |
711 | @item .pad #@var{count} | |
712 | Generate unwinder annotations for a stack adjustment of @var{count} bytes. | |
713 | A positive value indicates the function prologue allocated stack space by | |
714 | decrementing the stack pointer. | |
7ed4c4c5 NC |
715 | |
716 | @cindex @code{.personality} directive, ARM | |
717 | @item .personality @var{name} | |
718 | Sets the personality routine for the current function to @var{name}. | |
719 | ||
720 | @cindex @code{.personalityindex} directive, ARM | |
721 | @item .personalityindex @var{index} | |
722 | Sets the personality routine for the current function to the EABI standard | |
723 | routine number @var{index} | |
724 | ||
4a6bc624 NS |
725 | @cindex @code{.pool} directive, ARM |
726 | @item .pool | |
727 | This is a synonym for .ltorg. | |
7ed4c4c5 | 728 | |
4a6bc624 NS |
729 | @c QQQQQQQQQQQQQQQQQQQQQQQQQQ |
730 | @c RRRRRRRRRRRRRRRRRRRRRRRRRR | |
731 | ||
732 | @cindex @code{.req} directive, ARM | |
733 | @item @var{name} .req @var{register name} | |
734 | This creates an alias for @var{register name} called @var{name}. For | |
735 | example: | |
736 | ||
737 | @smallexample | |
738 | foo .req r0 | |
739 | @end smallexample | |
740 | ||
741 | @c SSSSSSSSSSSSSSSSSSSSSSSSSS | |
7ed4c4c5 | 742 | |
7da4f750 | 743 | @anchor{arm_save} |
7ed4c4c5 NC |
744 | @cindex @code{.save} directive, ARM |
745 | @item .save @var{reglist} | |
746 | Generate unwinder annotations to restore the registers in @var{reglist}. | |
747 | The format of @var{reglist} is the same as the corresponding store-multiple | |
748 | instruction. | |
749 | ||
750 | @smallexample | |
751 | @exdent @emph{core registers} | |
752 | .save @{r4, r5, r6, lr@} | |
753 | stmfd sp!, @{r4, r5, r6, lr@} | |
754 | @exdent @emph{FPA registers} | |
755 | .save f4, 2 | |
756 | sfmfd f4, 2, [sp]! | |
757 | @exdent @emph{VFP registers} | |
758 | .save @{d8, d9, d10@} | |
fa073d69 | 759 | fstmdx sp!, @{d8, d9, d10@} |
7ed4c4c5 NC |
760 | @exdent @emph{iWMMXt registers} |
761 | .save @{wr10, wr11@} | |
762 | wstrd wr11, [sp, #-8]! | |
763 | wstrd wr10, [sp, #-8]! | |
764 | or | |
765 | .save wr11 | |
766 | wstrd wr11, [sp, #-8]! | |
767 | .save wr10 | |
768 | wstrd wr10, [sp, #-8]! | |
769 | @end smallexample | |
770 | ||
7da4f750 | 771 | @anchor{arm_setfp} |
7ed4c4c5 NC |
772 | @cindex @code{.setfp} directive, ARM |
773 | @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}] | |
4a6bc624 | 774 | Make all unwinder annotations relative to a frame pointer. Without this |
7ed4c4c5 NC |
775 | the unwinder will use offsets from the stack pointer. |
776 | ||
a5b82cbe | 777 | The syntax of this directive is the same as the @code{add} or @code{mov} |
7ed4c4c5 NC |
778 | instruction used to set the frame pointer. @var{spreg} must be either |
779 | @code{sp} or mentioned in a previous @code{.movsp} directive. | |
780 | ||
781 | @smallexample | |
782 | .movsp ip | |
783 | mov ip, sp | |
784 | @dots{} | |
785 | .setfp fp, ip, #4 | |
a5b82cbe | 786 | add fp, ip, #4 |
7ed4c4c5 NC |
787 | @end smallexample |
788 | ||
4a6bc624 NS |
789 | @cindex @code{.secrel32} directive, ARM |
790 | @item .secrel32 @var{expression} [, @var{expression}]* | |
791 | This directive emits relocations that evaluate to the section-relative | |
792 | offset of each expression's symbol. This directive is only supported | |
793 | for PE targets. | |
794 | ||
cab7e4d9 NC |
795 | @cindex @code{.syntax} directive, ARM |
796 | @item .syntax [@code{unified} | @code{divided}] | |
797 | This directive sets the Instruction Set Syntax as described in the | |
798 | @ref{ARM-Instruction-Set} section. | |
799 | ||
4a6bc624 NS |
800 | @c TTTTTTTTTTTTTTTTTTTTTTTTTT |
801 | ||
802 | @cindex @code{.thumb} directive, ARM | |
803 | @item .thumb | |
804 | This performs the same action as @var{.code 16}. | |
805 | ||
806 | @cindex @code{.thumb_func} directive, ARM | |
807 | @item .thumb_func | |
808 | This directive specifies that the following symbol is the name of a | |
809 | Thumb encoded function. This information is necessary in order to allow | |
810 | the assembler and linker to generate correct code for interworking | |
811 | between Arm and Thumb instructions and should be used even if | |
812 | interworking is not going to be performed. The presence of this | |
813 | directive also implies @code{.thumb} | |
814 | ||
815 | This directive is not neccessary when generating EABI objects. On these | |
816 | targets the encoding is implicit when generating Thumb code. | |
817 | ||
818 | @cindex @code{.thumb_set} directive, ARM | |
819 | @item .thumb_set | |
820 | This performs the equivalent of a @code{.set} directive in that it | |
821 | creates a symbol which is an alias for another symbol (possibly not yet | |
822 | defined). This directive also has the added property in that it marks | |
823 | the aliased symbol as being a thumb function entry point, in the same | |
824 | way that the @code{.thumb_func} directive does. | |
825 | ||
826 | @c UUUUUUUUUUUUUUUUUUUUUUUUUU | |
827 | ||
828 | @cindex @code{.unreq} directive, ARM | |
829 | @item .unreq @var{alias-name} | |
830 | This undefines a register alias which was previously defined using the | |
831 | @code{req}, @code{dn} or @code{qn} directives. For example: | |
832 | ||
833 | @smallexample | |
834 | foo .req r0 | |
835 | .unreq foo | |
836 | @end smallexample | |
837 | ||
838 | An error occurs if the name is undefined. Note - this pseudo op can | |
839 | be used to delete builtin in register name aliases (eg 'r0'). This | |
840 | should only be done if it is really necessary. | |
841 | ||
7ed4c4c5 | 842 | @cindex @code{.unwind_raw} directive, ARM |
4a6bc624 | 843 | @item .unwind_raw @var{offset}, @var{byte1}, @dots{} |
7ed4c4c5 NC |
844 | Insert one of more arbitary unwind opcode bytes, which are known to adjust |
845 | the stack pointer by @var{offset} bytes. | |
846 | ||
847 | For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to | |
848 | @code{.save @{r0@}} | |
849 | ||
4a6bc624 | 850 | @c VVVVVVVVVVVVVVVVVVVVVVVVVV |
ee065d83 | 851 | |
4a6bc624 NS |
852 | @cindex @code{.vsave} directive, ARM |
853 | @item .vsave @var{vfp-reglist} | |
854 | Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist} | |
855 | using FLDMD. Also works for VFPv3 registers | |
856 | that are to be restored using VLDM. | |
857 | The format of @var{vfp-reglist} is the same as the corresponding store-multiple | |
858 | instruction. | |
ee065d83 | 859 | |
4a6bc624 NS |
860 | @smallexample |
861 | @exdent @emph{VFP registers} | |
862 | .vsave @{d8, d9, d10@} | |
863 | fstmdd sp!, @{d8, d9, d10@} | |
864 | @exdent @emph{VFPv3 registers} | |
865 | .vsave @{d15, d16, d17@} | |
866 | vstm sp!, @{d15, d16, d17@} | |
867 | @end smallexample | |
e04befd0 | 868 | |
4a6bc624 NS |
869 | Since FLDMX and FSTMX are now deprecated, this directive should be |
870 | used in favour of @code{.save} for saving VFP registers for ARMv6 and above. | |
e04befd0 | 871 | |
4a6bc624 NS |
872 | @c WWWWWWWWWWWWWWWWWWWWWWWWWW |
873 | @c XXXXXXXXXXXXXXXXXXXXXXXXXX | |
874 | @c YYYYYYYYYYYYYYYYYYYYYYYYYY | |
875 | @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ | |
ee065d83 | 876 | |
252b5132 RH |
877 | @end table |
878 | ||
879 | @node ARM Opcodes | |
880 | @section Opcodes | |
881 | ||
882 | @cindex ARM opcodes | |
883 | @cindex opcodes for ARM | |
49a5575c NC |
884 | @code{@value{AS}} implements all the standard ARM opcodes. It also |
885 | implements several pseudo opcodes, including several synthetic load | |
886 | instructions. | |
252b5132 | 887 | |
49a5575c NC |
888 | @table @code |
889 | ||
890 | @cindex @code{NOP} pseudo op, ARM | |
891 | @item NOP | |
892 | @smallexample | |
893 | nop | |
894 | @end smallexample | |
252b5132 | 895 | |
49a5575c NC |
896 | This pseudo op will always evaluate to a legal ARM instruction that does |
897 | nothing. Currently it will evaluate to MOV r0, r0. | |
252b5132 | 898 | |
49a5575c NC |
899 | @cindex @code{LDR reg,=<label>} pseudo op, ARM |
900 | @item LDR | |
252b5132 RH |
901 | @smallexample |
902 | ldr <register> , = <expression> | |
903 | @end smallexample | |
904 | ||
905 | If expression evaluates to a numeric constant then a MOV or MVN | |
906 | instruction will be used in place of the LDR instruction, if the | |
907 | constant can be generated by either of these instructions. Otherwise | |
908 | the constant will be placed into the nearest literal pool (if it not | |
909 | already there) and a PC relative LDR instruction will be generated. | |
910 | ||
49a5575c NC |
911 | @cindex @code{ADR reg,<label>} pseudo op, ARM |
912 | @item ADR | |
913 | @smallexample | |
914 | adr <register> <label> | |
915 | @end smallexample | |
916 | ||
917 | This instruction will load the address of @var{label} into the indicated | |
918 | register. The instruction will evaluate to a PC relative ADD or SUB | |
919 | instruction depending upon where the label is located. If the label is | |
920 | out of range, or if it is not defined in the same file (and section) as | |
921 | the ADR instruction, then an error will be generated. This instruction | |
922 | will not make use of the literal pool. | |
923 | ||
924 | @cindex @code{ADRL reg,<label>} pseudo op, ARM | |
925 | @item ADRL | |
926 | @smallexample | |
927 | adrl <register> <label> | |
928 | @end smallexample | |
929 | ||
930 | This instruction will load the address of @var{label} into the indicated | |
a349d9dd | 931 | register. The instruction will evaluate to one or two PC relative ADD |
49a5575c NC |
932 | or SUB instructions depending upon where the label is located. If a |
933 | second instruction is not needed a NOP instruction will be generated in | |
934 | its place, so that this instruction is always 8 bytes long. | |
935 | ||
936 | If the label is out of range, or if it is not defined in the same file | |
937 | (and section) as the ADRL instruction, then an error will be generated. | |
938 | This instruction will not make use of the literal pool. | |
939 | ||
940 | @end table | |
941 | ||
252b5132 RH |
942 | For information on the ARM or Thumb instruction sets, see @cite{ARM |
943 | Software Development Toolkit Reference Manual}, Advanced RISC Machines | |
944 | Ltd. | |
945 | ||
6057a28f NC |
946 | @node ARM Mapping Symbols |
947 | @section Mapping Symbols | |
948 | ||
949 | The ARM ELF specification requires that special symbols be inserted | |
950 | into object files to mark certain features: | |
951 | ||
952 | @table @code | |
953 | ||
954 | @cindex @code{$a} | |
955 | @item $a | |
956 | At the start of a region of code containing ARM instructions. | |
957 | ||
958 | @cindex @code{$t} | |
959 | @item $t | |
960 | At the start of a region of code containing THUMB instructions. | |
961 | ||
962 | @cindex @code{$d} | |
963 | @item $d | |
964 | At the start of a region of data. | |
965 | ||
966 | @end table | |
967 | ||
968 | The assembler will automatically insert these symbols for you - there | |
969 | is no need to code them yourself. Support for tagging symbols ($b, | |
970 | $f, $p and $m) which is also mentioned in the current ARM ELF | |
971 | specification is not implemented. This is because they have been | |
972 | dropped from the new EABI and so tools cannot rely upon their | |
973 | presence. | |
974 | ||
7da4f750 MM |
975 | @node ARM Unwinding Tutorial |
976 | @section Unwinding | |
977 | ||
978 | The ABI for the ARM Architecture specifies a standard format for | |
979 | exception unwind information. This information is used when an | |
980 | exception is thrown to determine where control should be transferred. | |
981 | In particular, the unwind information is used to determine which | |
982 | function called the function that threw the exception, and which | |
983 | function called that one, and so forth. This information is also used | |
984 | to restore the values of callee-saved registers in the function | |
985 | catching the exception. | |
986 | ||
987 | If you are writing functions in assembly code, and those functions | |
988 | call other functions that throw exceptions, you must use assembly | |
989 | pseudo ops to ensure that appropriate exception unwind information is | |
990 | generated. Otherwise, if one of the functions called by your assembly | |
991 | code throws an exception, the run-time library will be unable to | |
992 | unwind the stack through your assembly code and your program will not | |
993 | behave correctly. | |
994 | ||
995 | To illustrate the use of these pseudo ops, we will examine the code | |
996 | that G++ generates for the following C++ input: | |
997 | ||
998 | @verbatim | |
999 | void callee (int *); | |
1000 | ||
1001 | int | |
1002 | caller () | |
1003 | { | |
1004 | int i; | |
1005 | callee (&i); | |
1006 | return i; | |
1007 | } | |
1008 | @end verbatim | |
1009 | ||
1010 | This example does not show how to throw or catch an exception from | |
1011 | assembly code. That is a much more complex operation and should | |
1012 | always be done in a high-level language, such as C++, that directly | |
1013 | supports exceptions. | |
1014 | ||
1015 | The code generated by one particular version of G++ when compiling the | |
1016 | example above is: | |
1017 | ||
1018 | @verbatim | |
1019 | _Z6callerv: | |
1020 | .fnstart | |
1021 | .LFB2: | |
1022 | @ Function supports interworking. | |
1023 | @ args = 0, pretend = 0, frame = 8 | |
1024 | @ frame_needed = 1, uses_anonymous_args = 0 | |
1025 | stmfd sp!, {fp, lr} | |
1026 | .save {fp, lr} | |
1027 | .LCFI0: | |
1028 | .setfp fp, sp, #4 | |
1029 | add fp, sp, #4 | |
1030 | .LCFI1: | |
1031 | .pad #8 | |
1032 | sub sp, sp, #8 | |
1033 | .LCFI2: | |
1034 | sub r3, fp, #8 | |
1035 | mov r0, r3 | |
1036 | bl _Z6calleePi | |
1037 | ldr r3, [fp, #-8] | |
1038 | mov r0, r3 | |
1039 | sub sp, fp, #4 | |
1040 | ldmfd sp!, {fp, lr} | |
1041 | bx lr | |
1042 | .LFE2: | |
1043 | .fnend | |
1044 | @end verbatim | |
1045 | ||
1046 | Of course, the sequence of instructions varies based on the options | |
1047 | you pass to GCC and on the version of GCC in use. The exact | |
1048 | instructions are not important since we are focusing on the pseudo ops | |
1049 | that are used to generate unwind information. | |
1050 | ||
1051 | An important assumption made by the unwinder is that the stack frame | |
1052 | does not change during the body of the function. In particular, since | |
1053 | we assume that the assembly code does not itself throw an exception, | |
1054 | the only point where an exception can be thrown is from a call, such | |
1055 | as the @code{bl} instruction above. At each call site, the same saved | |
1056 | registers (including @code{lr}, which indicates the return address) | |
1057 | must be located in the same locations relative to the frame pointer. | |
1058 | ||
1059 | The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo | |
1060 | op appears immediately before the first instruction of the function | |
1061 | while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo | |
1062 | op appears immediately after the last instruction of the function. | |
1063 | These pseudo ops specify the range of the function. | |
1064 | ||
1065 | Only the order of the other pseudos ops (e.g., @code{.setfp} or | |
1066 | @code{.pad}) matters; their exact locations are irrelevant. In the | |
1067 | example above, the compiler emits the pseudo ops with particular | |
1068 | instructions. That makes it easier to understand the code, but it is | |
1069 | not required for correctness. It would work just as well to emit all | |
1070 | of the pseudo ops other than @code{.fnend} in the same order, but | |
1071 | immediately after @code{.fnstart}. | |
1072 | ||
1073 | The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op | |
1074 | indicates registers that have been saved to the stack so that they can | |
1075 | be restored before the function returns. The argument to the | |
1076 | @code{.save} pseudo op is a list of registers to save. If a register | |
1077 | is ``callee-saved'' (as specified by the ABI) and is modified by the | |
1078 | function you are writing, then your code must save the value before it | |
1079 | is modified and restore the original value before the function | |
1080 | returns. If an exception is thrown, the run-time library restores the | |
1081 | values of these registers from their locations on the stack before | |
1082 | returning control to the exception handler. (Of course, if an | |
1083 | exception is not thrown, the function that contains the @code{.save} | |
1084 | pseudo op restores these registers in the function epilogue, as is | |
1085 | done with the @code{ldmfd} instruction above.) | |
1086 | ||
1087 | You do not have to save callee-saved registers at the very beginning | |
1088 | of the function and you do not need to use the @code{.save} pseudo op | |
1089 | immediately following the point at which the registers are saved. | |
1090 | However, if you modify a callee-saved register, you must save it on | |
1091 | the stack before modifying it and before calling any functions which | |
1092 | might throw an exception. And, you must use the @code{.save} pseudo | |
1093 | op to indicate that you have done so. | |
1094 | ||
1095 | The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a | |
1096 | modification of the stack pointer that does not save any registers. | |
1097 | The argument is the number of bytes (in decimal) that are subtracted | |
1098 | from the stack pointer. (On ARM CPUs, the stack grows downwards, so | |
1099 | subtracting from the stack pointer increases the size of the stack.) | |
1100 | ||
1101 | The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op | |
1102 | indicates the register that contains the frame pointer. The first | |
1103 | argument is the register that is set, which is typically @code{fp}. | |
1104 | The second argument indicates the register from which the frame | |
1105 | pointer takes its value. The third argument, if present, is the value | |
1106 | (in decimal) added to the register specified by the second argument to | |
1107 | compute the value of the frame pointer. You should not modify the | |
1108 | frame pointer in the body of the function. | |
1109 | ||
1110 | If you do not use a frame pointer, then you should not use the | |
1111 | @code{.setfp} pseudo op. If you do not use a frame pointer, then you | |
1112 | should avoid modifying the stack pointer outside of the function | |
1113 | prologue. Otherwise, the run-time library will be unable to find | |
1114 | saved registers when it is unwinding the stack. | |
1115 | ||
1116 | The pseudo ops described above are sufficient for writing assembly | |
1117 | code that calls functions which may throw exceptions. If you need to | |
1118 | know more about the object-file format used to represent unwind | |
1119 | information, you may consult the @cite{Exception Handling ABI for the | |
1120 | ARM Architecture} available from @uref{http://infocenter.arm.com}. |