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b3adc24a | 1 | @c Copyright (C) 1996-2020 Free Software Foundation, Inc. |
252b5132 RH |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | ||
5 | @ifset GENERIC | |
6 | @page | |
7 | @node ARM-Dependent | |
8 | @chapter ARM Dependent Features | |
9 | @end ifset | |
10 | ||
11 | @ifclear GENERIC | |
12 | @node Machine Dependencies | |
13 | @chapter ARM Dependent Features | |
14 | @end ifclear | |
15 | ||
16 | @cindex ARM support | |
17 | @cindex Thumb support | |
18 | @menu | |
19 | * ARM Options:: Options | |
20 | * ARM Syntax:: Syntax | |
21 | * ARM Floating Point:: Floating Point | |
22 | * ARM Directives:: ARM Machine Directives | |
23 | * ARM Opcodes:: Opcodes | |
6057a28f | 24 | * ARM Mapping Symbols:: Mapping Symbols |
7da4f750 | 25 | * ARM Unwinding Tutorial:: Unwinding |
252b5132 RH |
26 | @end menu |
27 | ||
28 | @node ARM Options | |
29 | @section Options | |
30 | @cindex ARM options (none) | |
31 | @cindex options for ARM (none) | |
adcf07e6 | 32 | |
252b5132 | 33 | @table @code |
adcf07e6 | 34 | |
a05a5b64 | 35 | @cindex @code{-mcpu=} command-line option, ARM |
92081f48 | 36 | @item -mcpu=@var{processor}[+@var{extension}@dots{}] |
252b5132 RH |
37 | This option specifies the target processor. The assembler will issue an |
38 | error message if an attempt is made to assemble an instruction which | |
03b1477f | 39 | will not execute on the target processor. The following processor names are |
34bca508 | 40 | recognized: |
03b1477f RE |
41 | @code{arm1}, |
42 | @code{arm2}, | |
43 | @code{arm250}, | |
44 | @code{arm3}, | |
45 | @code{arm6}, | |
46 | @code{arm60}, | |
47 | @code{arm600}, | |
48 | @code{arm610}, | |
49 | @code{arm620}, | |
50 | @code{arm7}, | |
51 | @code{arm7m}, | |
52 | @code{arm7d}, | |
53 | @code{arm7dm}, | |
54 | @code{arm7di}, | |
55 | @code{arm7dmi}, | |
56 | @code{arm70}, | |
57 | @code{arm700}, | |
58 | @code{arm700i}, | |
59 | @code{arm710}, | |
60 | @code{arm710t}, | |
61 | @code{arm720}, | |
62 | @code{arm720t}, | |
63 | @code{arm740t}, | |
64 | @code{arm710c}, | |
65 | @code{arm7100}, | |
66 | @code{arm7500}, | |
67 | @code{arm7500fe}, | |
68 | @code{arm7t}, | |
69 | @code{arm7tdmi}, | |
1ff4677c | 70 | @code{arm7tdmi-s}, |
03b1477f RE |
71 | @code{arm8}, |
72 | @code{arm810}, | |
73 | @code{strongarm}, | |
74 | @code{strongarm1}, | |
75 | @code{strongarm110}, | |
76 | @code{strongarm1100}, | |
77 | @code{strongarm1110}, | |
78 | @code{arm9}, | |
79 | @code{arm920}, | |
80 | @code{arm920t}, | |
81 | @code{arm922t}, | |
82 | @code{arm940t}, | |
83 | @code{arm9tdmi}, | |
7fac0536 NC |
84 | @code{fa526} (Faraday FA526 processor), |
85 | @code{fa626} (Faraday FA626 processor), | |
03b1477f | 86 | @code{arm9e}, |
7de9afa2 | 87 | @code{arm926e}, |
1ff4677c | 88 | @code{arm926ej-s}, |
03b1477f RE |
89 | @code{arm946e-r0}, |
90 | @code{arm946e}, | |
db8ac8f9 | 91 | @code{arm946e-s}, |
03b1477f RE |
92 | @code{arm966e-r0}, |
93 | @code{arm966e}, | |
db8ac8f9 PB |
94 | @code{arm966e-s}, |
95 | @code{arm968e-s}, | |
03b1477f | 96 | @code{arm10t}, |
db8ac8f9 | 97 | @code{arm10tdmi}, |
03b1477f RE |
98 | @code{arm10e}, |
99 | @code{arm1020}, | |
100 | @code{arm1020t}, | |
7de9afa2 | 101 | @code{arm1020e}, |
db8ac8f9 | 102 | @code{arm1022e}, |
1ff4677c | 103 | @code{arm1026ej-s}, |
4a58c4bd NC |
104 | @code{fa606te} (Faraday FA606TE processor), |
105 | @code{fa616te} (Faraday FA616TE processor), | |
7fac0536 | 106 | @code{fa626te} (Faraday FA626TE processor), |
4a58c4bd | 107 | @code{fmp626} (Faraday FMP626 processor), |
7fac0536 | 108 | @code{fa726te} (Faraday FA726TE processor), |
1ff4677c RE |
109 | @code{arm1136j-s}, |
110 | @code{arm1136jf-s}, | |
db8ac8f9 PB |
111 | @code{arm1156t2-s}, |
112 | @code{arm1156t2f-s}, | |
0dd132b6 NC |
113 | @code{arm1176jz-s}, |
114 | @code{arm1176jzf-s}, | |
115 | @code{mpcore}, | |
116 | @code{mpcorenovfp}, | |
b38f9f31 | 117 | @code{cortex-a5}, |
c90460e4 | 118 | @code{cortex-a7}, |
62b3e311 | 119 | @code{cortex-a8}, |
15290f0a | 120 | @code{cortex-a9}, |
dbb1f804 | 121 | @code{cortex-a15}, |
ed5491b9 | 122 | @code{cortex-a17}, |
6735952f | 123 | @code{cortex-a32}, |
43cdc0a8 | 124 | @code{cortex-a35}, |
4469186b | 125 | @code{cortex-a53}, |
15a7695f | 126 | @code{cortex-a55}, |
4469186b KT |
127 | @code{cortex-a57}, |
128 | @code{cortex-a72}, | |
362a3eba | 129 | @code{cortex-a73}, |
15a7695f | 130 | @code{cortex-a75}, |
7ebd1359 | 131 | @code{cortex-a76}, |
0535e5d7 DZ |
132 | @code{cortex-a76ae}, |
133 | @code{cortex-a77}, | |
ef8df4ca | 134 | @code{ares}, |
62b3e311 | 135 | @code{cortex-r4}, |
307c948d | 136 | @code{cortex-r4f}, |
70a8bc5b | 137 | @code{cortex-r5}, |
138 | @code{cortex-r7}, | |
5f474010 | 139 | @code{cortex-r8}, |
0cda1e19 | 140 | @code{cortex-r52}, |
0535e5d7 | 141 | @code{cortex-m35p}, |
b19ea8d2 | 142 | @code{cortex-m33}, |
ce1b0a45 | 143 | @code{cortex-m23}, |
a715796b | 144 | @code{cortex-m7}, |
7ef07ba0 | 145 | @code{cortex-m4}, |
62b3e311 | 146 | @code{cortex-m3}, |
5b19eaba NC |
147 | @code{cortex-m1}, |
148 | @code{cortex-m0}, | |
ce32bd10 | 149 | @code{cortex-m0plus}, |
394e9bf6 | 150 | @code{cortex-x1}, |
246496bb | 151 | @code{exynos-m1}, |
ea0d6bb9 PT |
152 | @code{marvell-pj4}, |
153 | @code{marvell-whitney}, | |
83f43c83 | 154 | @code{neoverse-n1}, |
f3034e25 | 155 | @code{neoverse-n2}, |
6eee0315 | 156 | @code{neoverse-v1}, |
ea0d6bb9 PT |
157 | @code{xgene1}, |
158 | @code{xgene2}, | |
03b1477f RE |
159 | @code{ep9312} (ARM920 with Cirrus Maverick coprocessor), |
160 | @code{i80200} (Intel XScale processor) | |
334fe02b | 161 | @code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor) |
03b1477f | 162 | and |
34bca508 | 163 | @code{xscale}. |
03b1477f RE |
164 | The special name @code{all} may be used to allow the |
165 | assembler to accept instructions valid for any ARM processor. | |
166 | ||
34bca508 L |
167 | In addition to the basic instruction set, the assembler can be told to |
168 | accept various extension mnemonics that extend the processor using the | |
03b1477f | 169 | co-processor instruction space. For example, @code{-mcpu=arm920+maverick} |
34bca508 | 170 | is equivalent to specifying @code{-mcpu=ep9312}. |
69133863 | 171 | |
34bca508 | 172 | Multiple extensions may be specified, separated by a @code{+}. The |
69133863 MGD |
173 | extensions should be specified in ascending alphabetical order. |
174 | ||
34bca508 | 175 | Some extensions may be restricted to particular architectures; this is |
60e5ef9f MGD |
176 | documented in the list of extensions below. |
177 | ||
34bca508 L |
178 | Extension mnemonics may also be removed from those the assembler accepts. |
179 | This is done be prepending @code{no} to the option that adds the extension. | |
180 | Extensions that are removed should be listed after all extensions which have | |
181 | been added, again in ascending alphabetical order. For example, | |
69133863 MGD |
182 | @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}. |
183 | ||
184 | ||
eea54501 | 185 | The following extensions are currently supported: |
aab2c27d | 186 | @code{bf16} (BFloat16 extensions for v8.6-A architecture), |
616ce08e | 187 | @code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture), |
ea0d6bb9 | 188 | @code{crc} |
bca38921 | 189 | @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}), |
c604a79a | 190 | @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}), |
bca38921 | 191 | @code{fp} (Floating Point Extensions for v8-A architecture), |
01f48020 TC |
192 | @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}), |
193 | @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}), | |
bca38921 | 194 | @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures), |
69133863 MGD |
195 | @code{iwmmxt}, |
196 | @code{iwmmxt2}, | |
ea0d6bb9 | 197 | @code{xscale}, |
69133863 | 198 | @code{maverick}, |
ea0d6bb9 PT |
199 | @code{mp} (Multiprocessing Extensions for v7-A and v7-R |
200 | architectures), | |
b2a5fbdc | 201 | @code{os} (Operating System for v6M architecture), |
dad0c3bf SD |
202 | @code{predres} (Execution and Data Prediction Restriction Instruction for |
203 | v8-A architectures, added by default from v8.5-A), | |
7fadb25d SD |
204 | @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by |
205 | default from v8.5-A), | |
f4c65163 | 206 | @code{sec} (Security Extensions for v6K and v7-A architectures), |
bca38921 | 207 | @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}), |
34bca508 | 208 | @code{virt} (Virtualization Extensions for v7-A architecture, implies |
90ec0d68 | 209 | @code{idiv}), |
33eaf5de | 210 | @code{pan} (Privileged Access Never Extensions for v8-A architecture), |
4d1464f2 MW |
211 | @code{ras} (Reliability, Availability and Serviceability extensions |
212 | for v8-A architecture), | |
d6b4b13e MW |
213 | @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies |
214 | @code{simd}) | |
03b1477f | 215 | and |
69133863 | 216 | @code{xscale}. |
03b1477f | 217 | |
a05a5b64 | 218 | @cindex @code{-march=} command-line option, ARM |
92081f48 | 219 | @item -march=@var{architecture}[+@var{extension}@dots{}] |
252b5132 RH |
220 | This option specifies the target architecture. The assembler will issue |
221 | an error message if an attempt is made to assemble an instruction which | |
34bca508 L |
222 | will not execute on the target architecture. The following architecture |
223 | names are recognized: | |
03b1477f RE |
224 | @code{armv1}, |
225 | @code{armv2}, | |
226 | @code{armv2a}, | |
227 | @code{armv2s}, | |
228 | @code{armv3}, | |
229 | @code{armv3m}, | |
230 | @code{armv4}, | |
231 | @code{armv4xm}, | |
232 | @code{armv4t}, | |
233 | @code{armv4txm}, | |
234 | @code{armv5}, | |
235 | @code{armv5t}, | |
236 | @code{armv5txm}, | |
237 | @code{armv5te}, | |
09d92015 | 238 | @code{armv5texp}, |
c5f98204 | 239 | @code{armv6}, |
1ddd7f43 | 240 | @code{armv6j}, |
0dd132b6 NC |
241 | @code{armv6k}, |
242 | @code{armv6z}, | |
f33026a9 | 243 | @code{armv6kz}, |
b2a5fbdc MGD |
244 | @code{armv6-m}, |
245 | @code{armv6s-m}, | |
62b3e311 | 246 | @code{armv7}, |
c450d570 | 247 | @code{armv7-a}, |
c9fb6e58 | 248 | @code{armv7ve}, |
c450d570 PB |
249 | @code{armv7-r}, |
250 | @code{armv7-m}, | |
9e3c6df6 | 251 | @code{armv7e-m}, |
bca38921 | 252 | @code{armv8-a}, |
a5932920 | 253 | @code{armv8.1-a}, |
56a1b672 | 254 | @code{armv8.2-a}, |
a12fd8e1 | 255 | @code{armv8.3-a}, |
ced40572 | 256 | @code{armv8-r}, |
dec41383 | 257 | @code{armv8.4-a}, |
23f233a5 | 258 | @code{armv8.5-a}, |
34ef62f4 AV |
259 | @code{armv8-m.base}, |
260 | @code{armv8-m.main}, | |
e0991585 | 261 | @code{armv8.1-m.main}, |
aab2c27d | 262 | @code{armv8.6-a}, |
34ef62f4 | 263 | @code{iwmmxt}, |
ea0d6bb9 | 264 | @code{iwmmxt2} |
03b1477f RE |
265 | and |
266 | @code{xscale}. | |
267 | If both @code{-mcpu} and | |
268 | @code{-march} are specified, the assembler will use | |
269 | the setting for @code{-mcpu}. | |
270 | ||
34ef62f4 AV |
271 | The architecture option can be extended with a set extension options. These |
272 | extensions are context sensitive, i.e. the same extension may mean different | |
273 | things when used with different architectures. When used together with a | |
274 | @code{-mfpu} option, the union of both feature enablement is taken. | |
275 | See their availability and meaning below: | |
276 | ||
277 | For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}: | |
278 | ||
279 | @code{+fp}: Enables VFPv2 instructions. | |
280 | @code{+nofp}: Disables all FPU instrunctions. | |
281 | ||
282 | For @code{armv7}: | |
283 | ||
284 | @code{+fp}: Enables VFPv3 instructions with 16 double-word registers. | |
285 | @code{+nofp}: Disables all FPU instructions. | |
286 | ||
287 | For @code{armv7-a}: | |
288 | ||
289 | @code{+fp}: Enables VFPv3 instructions with 16 double-word registers. | |
290 | @code{+vfpv3-d16}: Alias for @code{+fp}. | |
291 | @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers. | |
292 | @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point | |
293 | conversion instructions and 16 double-word registers. | |
294 | @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion | |
295 | instructions and 32 double-word registers. | |
296 | @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers. | |
297 | @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers. | |
298 | @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word | |
299 | registers. | |
300 | @code{+neon}: Alias for @code{+simd}. | |
301 | @code{+neon-vfpv3}: Alias for @code{+simd}. | |
302 | @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and | |
303 | NEONv1 instructions with 32 double-word registers. | |
304 | @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 | |
305 | double-word registers. | |
306 | @code{+mp}: Enables Multiprocessing Extensions. | |
307 | @code{+sec}: Enables Security Extensions. | |
308 | @code{+nofp}: Disables all FPU and NEON instructions. | |
309 | @code{+nosimd}: Disables all NEON instructions. | |
310 | ||
311 | For @code{armv7ve}: | |
312 | ||
313 | @code{+fp}: Enables VFPv4 instructions with 16 double-word registers. | |
314 | @code{+vfpv4-d16}: Alias for @code{+fp}. | |
315 | @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers. | |
316 | @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers. | |
317 | @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point | |
318 | conversion instructions and 16 double-word registers. | |
319 | @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion | |
320 | instructions and 32 double-word registers. | |
321 | @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers. | |
322 | @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 | |
323 | double-word registers. | |
324 | @code{+neon-vfpv4}: Alias for @code{+simd}. | |
325 | @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word | |
326 | registers. | |
327 | @code{+neon-vfpv3}: Alias for @code{+neon}. | |
328 | @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and | |
329 | NEONv1 instructions with 32 double-word registers. | |
330 | double-word registers. | |
331 | @code{+nofp}: Disables all FPU and NEON instructions. | |
332 | @code{+nosimd}: Disables all NEON instructions. | |
333 | ||
334 | For @code{armv7-r}: | |
335 | ||
336 | @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16 | |
337 | double-word registers. | |
338 | @code{+vfpv3xd}: Alias for @code{+fp.sp}. | |
339 | @code{+fp}: Enables VFPv3 instructions with 16 double-word registers. | |
340 | @code{+vfpv3-d16}: Alias for @code{+fp}. | |
341 | @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half | |
342 | floating-point conversion instructions with 16 double-word registers. | |
343 | @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point | |
344 | conversion instructions with 16 double-word registers. | |
345 | @code{+idiv}: Enables integer division instructions in ARM mode. | |
346 | @code{+nofp}: Disables all FPU instructions. | |
347 | ||
348 | For @code{armv7e-m}: | |
349 | ||
350 | @code{+fp}: Enables single-precision only VFPv4 instructions with 16 | |
351 | double-word registers. | |
352 | @code{+vfpvf4-sp-d16}: Alias for @code{+fp}. | |
353 | @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16 | |
354 | double-word registers. | |
355 | @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers. | |
356 | @code{+fpv5-d16"}: Alias for @code{+fp.dp}. | |
357 | @code{+nofp}: Disables all FPU instructions. | |
358 | ||
359 | For @code{armv8-m.main}: | |
360 | ||
361 | @code{+dsp}: Enables DSP Extension. | |
362 | @code{+fp}: Enables single-precision only VFPv5 instructions with 16 | |
363 | double-word registers. | |
364 | @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers. | |
4934a27c MM |
365 | @code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0), |
366 | @code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1), | |
367 | @code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2), | |
368 | @code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3), | |
369 | @code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4), | |
370 | @code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5), | |
371 | @code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6), | |
372 | @code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7), | |
34ef62f4 AV |
373 | @code{+nofp}: Disables all FPU instructions. |
374 | @code{+nodsp}: Disables DSP Extension. | |
375 | ||
e0991585 AV |
376 | For @code{armv8.1-m.main}: |
377 | ||
378 | @code{+dsp}: Enables DSP Extension. | |
379 | @code{+fp}: Enables single and half precision scalar Floating Point Extensions | |
380 | for Armv8.1-M Mainline with 16 double-word registers. | |
381 | @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for | |
382 | Armv8.1-M Mainline, implies @code{+fp}. | |
a7ad558c AV |
383 | @code{+mve}: Enables integer only M-profile Vector Extension for |
384 | Armv8.1-M Mainline, implies @code{+dsp}. | |
385 | @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for | |
386 | Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}. | |
e0991585 AV |
387 | @code{+nofp}: Disables all FPU instructions. |
388 | @code{+nodsp}: Disables DSP Extension. | |
a7ad558c | 389 | @code{+nomve}: Disables all M-profile Vector Extensions. |
e0991585 | 390 | |
34ef62f4 AV |
391 | For @code{armv8-a}: |
392 | ||
393 | @code{+crc}: Enables CRC32 Extension. | |
394 | @code{+simd}: Enables VFP and NEON for Armv8-A. | |
395 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies | |
396 | @code{+simd}. | |
397 | @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. | |
398 | @code{+predres}: Enables Execution and Data Prediction Restriction Instruction | |
399 | for Armv8-A. | |
400 | @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. | |
401 | @code{+nocrypto}: Disables Cryptography Extensions. | |
402 | ||
403 | For @code{armv8.1-a}: | |
404 | ||
405 | @code{+simd}: Enables VFP and NEON for Armv8.1-A. | |
406 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies | |
407 | @code{+simd}. | |
408 | @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. | |
409 | @code{+predres}: Enables Execution and Data Prediction Restriction Instruction | |
410 | for Armv8-A. | |
411 | @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. | |
412 | @code{+nocrypto}: Disables Cryptography Extensions. | |
413 | ||
414 | For @code{armv8.2-a} and @code{armv8.3-a}: | |
415 | ||
416 | @code{+simd}: Enables VFP and NEON for Armv8.1-A. | |
417 | @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}. | |
418 | @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions | |
419 | for Armv8.2-A, implies @code{+fp16}. | |
420 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies | |
421 | @code{+simd}. | |
422 | @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies | |
423 | @code{+simd}. | |
424 | @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. | |
425 | @code{+predres}: Enables Execution and Data Prediction Restriction Instruction | |
426 | for Armv8-A. | |
427 | @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. | |
428 | @code{+nocrypto}: Disables Cryptography Extensions. | |
429 | ||
430 | For @code{armv8.4-a}: | |
431 | ||
432 | @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for | |
433 | Armv8.2-A. | |
434 | @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication | |
435 | Variant Extensions for Armv8.2-A, implies @code{+simd}. | |
436 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies | |
437 | @code{+simd}. | |
438 | @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. | |
439 | @code{+predres}: Enables Execution and Data Prediction Restriction Instruction | |
440 | for Armv8-A. | |
441 | @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. | |
442 | @code{+nocryptp}: Disables Cryptography Extensions. | |
443 | ||
444 | For @code{armv8.5-a}: | |
445 | ||
446 | @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for | |
447 | Armv8.2-A. | |
448 | @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication | |
449 | Variant Extensions for Armv8.2-A, implies @code{+simd}. | |
450 | @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies | |
451 | @code{+simd}. | |
452 | @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. | |
453 | @code{+nocryptp}: Disables Cryptography Extensions. | |
454 | ||
03b1477f | 455 | |
a05a5b64 | 456 | @cindex @code{-mfpu=} command-line option, ARM |
03b1477f RE |
457 | @item -mfpu=@var{floating-point-format} |
458 | ||
459 | This option specifies the floating point format to assemble for. The | |
460 | assembler will issue an error message if an attempt is made to assemble | |
34bca508 | 461 | an instruction which will not execute on the target floating point unit. |
03b1477f RE |
462 | The following format options are recognized: |
463 | @code{softfpa}, | |
464 | @code{fpe}, | |
bc89618b RE |
465 | @code{fpe2}, |
466 | @code{fpe3}, | |
03b1477f RE |
467 | @code{fpa}, |
468 | @code{fpa10}, | |
469 | @code{fpa11}, | |
470 | @code{arm7500fe}, | |
471 | @code{softvfp}, | |
472 | @code{softvfp+vfp}, | |
473 | @code{vfp}, | |
474 | @code{vfp10}, | |
475 | @code{vfp10-r0}, | |
476 | @code{vfp9}, | |
477 | @code{vfpxd}, | |
62f3b8c8 PB |
478 | @code{vfpv2}, |
479 | @code{vfpv3}, | |
480 | @code{vfpv3-fp16}, | |
481 | @code{vfpv3-d16}, | |
482 | @code{vfpv3-d16-fp16}, | |
483 | @code{vfpv3xd}, | |
484 | @code{vfpv3xd-d16}, | |
485 | @code{vfpv4}, | |
486 | @code{vfpv4-d16}, | |
f0cd0667 | 487 | @code{fpv4-sp-d16}, |
a715796b TG |
488 | @code{fpv5-sp-d16}, |
489 | @code{fpv5-d16}, | |
bca38921 | 490 | @code{fp-armv8}, |
09d92015 MM |
491 | @code{arm1020t}, |
492 | @code{arm1020e}, | |
b1cc4aeb | 493 | @code{arm1136jf-s}, |
62f3b8c8 PB |
494 | @code{maverick}, |
495 | @code{neon}, | |
d5e0ba9c RE |
496 | @code{neon-vfpv3}, |
497 | @code{neon-fp16}, | |
bca38921 MGD |
498 | @code{neon-vfpv4}, |
499 | @code{neon-fp-armv8}, | |
081e4c7d MW |
500 | @code{crypto-neon-fp-armv8}, |
501 | @code{neon-fp-armv8.1} | |
d6b4b13e | 502 | and |
081e4c7d | 503 | @code{crypto-neon-fp-armv8.1}. |
03b1477f RE |
504 | |
505 | In addition to determining which instructions are assembled, this option | |
506 | also affects the way in which the @code{.double} assembler directive behaves | |
507 | when assembling little-endian code. | |
508 | ||
34bca508 | 509 | The default is dependent on the processor selected. For Architecture 5 or |
d5e0ba9c | 510 | later, the default is to assemble for VFP instructions; for earlier |
03b1477f | 511 | architectures the default is to assemble for FPA instructions. |
adcf07e6 | 512 | |
5312fe52 BW |
513 | @cindex @code{-mfp16-format=} command-line option |
514 | @item -mfp16-format=@var{format} | |
515 | This option specifies the half-precision floating point format to use | |
516 | when assembling floating point numbers emitted by the @code{.float16} | |
517 | directive. | |
518 | The following format options are recognized: | |
519 | @code{ieee}, | |
520 | @code{alternative}. | |
521 | If @code{ieee} is specified then the IEEE 754-2008 half-precision floating | |
522 | point format is used, if @code{alternative} is specified then the Arm | |
523 | alternative half-precision format is used. If this option is set on the | |
524 | command line then the format is fixed and cannot be changed with | |
525 | the @code{float16_format} directive. If this value is not set then | |
526 | the IEEE 754-2008 format is used until the format is explicitly set with | |
527 | the @code{float16_format} directive. | |
528 | ||
a05a5b64 | 529 | @cindex @code{-mthumb} command-line option, ARM |
252b5132 | 530 | @item -mthumb |
03b1477f | 531 | This option specifies that the assembler should start assembling Thumb |
34bca508 | 532 | instructions; that is, it should behave as though the file starts with a |
03b1477f | 533 | @code{.code 16} directive. |
adcf07e6 | 534 | |
a05a5b64 | 535 | @cindex @code{-mthumb-interwork} command-line option, ARM |
252b5132 RH |
536 | @item -mthumb-interwork |
537 | This option specifies that the output generated by the assembler should | |
fc6141f0 NC |
538 | be marked as supporting interworking. It also affects the behaviour |
539 | of the @code{ADR} and @code{ADRL} pseudo opcodes. | |
adcf07e6 | 540 | |
a05a5b64 | 541 | @cindex @code{-mimplicit-it} command-line option, ARM |
52970753 NC |
542 | @item -mimplicit-it=never |
543 | @itemx -mimplicit-it=always | |
544 | @itemx -mimplicit-it=arm | |
545 | @itemx -mimplicit-it=thumb | |
546 | The @code{-mimplicit-it} option controls the behavior of the assembler when | |
547 | conditional instructions are not enclosed in IT blocks. | |
548 | There are four possible behaviors. | |
549 | If @code{never} is specified, such constructs cause a warning in ARM | |
550 | code and an error in Thumb-2 code. | |
551 | If @code{always} is specified, such constructs are accepted in both | |
552 | ARM and Thumb-2 code, where the IT instruction is added implicitly. | |
553 | If @code{arm} is specified, such constructs are accepted in ARM code | |
554 | and cause an error in Thumb-2 code. | |
555 | If @code{thumb} is specified, such constructs cause a warning in ARM | |
556 | code and are accepted in Thumb-2 code. If you omit this option, the | |
557 | behavior is equivalent to @code{-mimplicit-it=arm}. | |
e07e6e58 | 558 | |
a05a5b64 TP |
559 | @cindex @code{-mapcs-26} command-line option, ARM |
560 | @cindex @code{-mapcs-32} command-line option, ARM | |
5a5829dd NS |
561 | @item -mapcs-26 |
562 | @itemx -mapcs-32 | |
563 | These options specify that the output generated by the assembler should | |
252b5132 RH |
564 | be marked as supporting the indicated version of the Arm Procedure. |
565 | Calling Standard. | |
adcf07e6 | 566 | |
a05a5b64 | 567 | @cindex @code{-matpcs} command-line option, ARM |
077b8428 | 568 | @item -matpcs |
34bca508 | 569 | This option specifies that the output generated by the assembler should |
077b8428 NC |
570 | be marked as supporting the Arm/Thumb Procedure Calling Standard. If |
571 | enabled this option will cause the assembler to create an empty | |
572 | debugging section in the object file called .arm.atpcs. Debuggers can | |
573 | use this to determine the ABI being used by. | |
574 | ||
a05a5b64 | 575 | @cindex @code{-mapcs-float} command-line option, ARM |
252b5132 | 576 | @item -mapcs-float |
1be59579 | 577 | This indicates the floating point variant of the APCS should be |
252b5132 | 578 | used. In this variant floating point arguments are passed in FP |
550262c4 | 579 | registers rather than integer registers. |
adcf07e6 | 580 | |
a05a5b64 | 581 | @cindex @code{-mapcs-reentrant} command-line option, ARM |
252b5132 RH |
582 | @item -mapcs-reentrant |
583 | This indicates that the reentrant variant of the APCS should be used. | |
584 | This variant supports position independent code. | |
adcf07e6 | 585 | |
a05a5b64 | 586 | @cindex @code{-mfloat-abi=} command-line option, ARM |
33a392fb PB |
587 | @item -mfloat-abi=@var{abi} |
588 | This option specifies that the output generated by the assembler should be | |
589 | marked as using specified floating point ABI. | |
590 | The following values are recognized: | |
591 | @code{soft}, | |
592 | @code{softfp} | |
593 | and | |
594 | @code{hard}. | |
595 | ||
a05a5b64 | 596 | @cindex @code{-eabi=} command-line option, ARM |
d507cf36 PB |
597 | @item -meabi=@var{ver} |
598 | This option specifies which EABI version the produced object files should | |
599 | conform to. | |
b45619c0 | 600 | The following values are recognized: |
3a4a14e9 PB |
601 | @code{gnu}, |
602 | @code{4} | |
d507cf36 | 603 | and |
3a4a14e9 | 604 | @code{5}. |
d507cf36 | 605 | |
a05a5b64 | 606 | @cindex @code{-EB} command-line option, ARM |
252b5132 RH |
607 | @item -EB |
608 | This option specifies that the output generated by the assembler should | |
609 | be marked as being encoded for a big-endian processor. | |
adcf07e6 | 610 | |
080bb7bb NC |
611 | Note: If a program is being built for a system with big-endian data |
612 | and little-endian instructions then it should be assembled with the | |
613 | @option{-EB} option, (all of it, code and data) and then linked with | |
614 | the @option{--be8} option. This will reverse the endianness of the | |
615 | instructions back to little-endian, but leave the data as big-endian. | |
616 | ||
a05a5b64 | 617 | @cindex @code{-EL} command-line option, ARM |
252b5132 RH |
618 | @item -EL |
619 | This option specifies that the output generated by the assembler should | |
620 | be marked as being encoded for a little-endian processor. | |
adcf07e6 | 621 | |
a05a5b64 | 622 | @cindex @code{-k} command-line option, ARM |
252b5132 RH |
623 | @cindex PIC code generation for ARM |
624 | @item -k | |
a349d9dd PB |
625 | This option specifies that the output of the assembler should be marked |
626 | as position-independent code (PIC). | |
adcf07e6 | 627 | |
a05a5b64 | 628 | @cindex @code{--fix-v4bx} command-line option, ARM |
845b51d6 PB |
629 | @item --fix-v4bx |
630 | Allow @code{BX} instructions in ARMv4 code. This is intended for use with | |
631 | the linker option of the same name. | |
632 | ||
a05a5b64 | 633 | @cindex @code{-mwarn-deprecated} command-line option, ARM |
278df34e NS |
634 | @item -mwarn-deprecated |
635 | @itemx -mno-warn-deprecated | |
636 | Enable or disable warnings about using deprecated options or | |
637 | features. The default is to warn. | |
638 | ||
a05a5b64 | 639 | @cindex @code{-mccs} command-line option, ARM |
2e6976a8 DG |
640 | @item -mccs |
641 | Turns on CodeComposer Studio assembly syntax compatibility mode. | |
642 | ||
a05a5b64 | 643 | @cindex @code{-mwarn-syms} command-line option, ARM |
8b2d793c NC |
644 | @item -mwarn-syms |
645 | @itemx -mno-warn-syms | |
646 | Enable or disable warnings about symbols that match the names of ARM | |
647 | instructions. The default is to warn. | |
648 | ||
252b5132 RH |
649 | @end table |
650 | ||
651 | ||
652 | @node ARM Syntax | |
653 | @section Syntax | |
654 | @menu | |
cab7e4d9 | 655 | * ARM-Instruction-Set:: Instruction Set |
252b5132 RH |
656 | * ARM-Chars:: Special Characters |
657 | * ARM-Regs:: Register Names | |
b6895b4f | 658 | * ARM-Relocations:: Relocations |
99f1a7a7 | 659 | * ARM-Neon-Alignment:: NEON Alignment Specifiers |
252b5132 RH |
660 | @end menu |
661 | ||
cab7e4d9 NC |
662 | @node ARM-Instruction-Set |
663 | @subsection Instruction Set Syntax | |
664 | Two slightly different syntaxes are support for ARM and THUMB | |
665 | instructions. The default, @code{divided}, uses the old style where | |
666 | ARM and THUMB instructions had their own, separate syntaxes. The new, | |
667 | @code{unified} syntax, which can be selected via the @code{.syntax} | |
668 | directive, and has the following main features: | |
669 | ||
9e6f3811 AS |
670 | @itemize @bullet |
671 | @item | |
cab7e4d9 NC |
672 | Immediate operands do not require a @code{#} prefix. |
673 | ||
9e6f3811 | 674 | @item |
cab7e4d9 NC |
675 | The @code{IT} instruction may appear, and if it does it is validated |
676 | against subsequent conditional affixes. In ARM mode it does not | |
677 | generate machine code, in THUMB mode it does. | |
678 | ||
9e6f3811 | 679 | @item |
cab7e4d9 NC |
680 | For ARM instructions the conditional affixes always appear at the end |
681 | of the instruction. For THUMB instructions conditional affixes can be | |
682 | used, but only inside the scope of an @code{IT} instruction. | |
683 | ||
9e6f3811 | 684 | @item |
cab7e4d9 NC |
685 | All of the instructions new to the V6T2 architecture (and later) are |
686 | available. (Only a few such instructions can be written in the | |
687 | @code{divided} syntax). | |
688 | ||
9e6f3811 | 689 | @item |
cab7e4d9 NC |
690 | The @code{.N} and @code{.W} suffixes are recognized and honored. |
691 | ||
9e6f3811 | 692 | @item |
cab7e4d9 NC |
693 | All instructions set the flags if and only if they have an @code{s} |
694 | affix. | |
9e6f3811 | 695 | @end itemize |
cab7e4d9 | 696 | |
252b5132 RH |
697 | @node ARM-Chars |
698 | @subsection Special Characters | |
699 | ||
700 | @cindex line comment character, ARM | |
701 | @cindex ARM line comment character | |
7c31ae13 NC |
702 | The presence of a @samp{@@} anywhere on a line indicates the start of |
703 | a comment that extends to the end of that line. | |
704 | ||
705 | If a @samp{#} appears as the first character of a line then the whole | |
706 | line is treated as a comment, but in this case the line could also be | |
707 | a logical line number directive (@pxref{Comments}) or a preprocessor | |
708 | control command (@pxref{Preprocessing}). | |
550262c4 NC |
709 | |
710 | @cindex line separator, ARM | |
711 | @cindex statement separator, ARM | |
712 | @cindex ARM line separator | |
a349d9dd PB |
713 | The @samp{;} character can be used instead of a newline to separate |
714 | statements. | |
550262c4 NC |
715 | |
716 | @cindex immediate character, ARM | |
717 | @cindex ARM immediate character | |
718 | Either @samp{#} or @samp{$} can be used to indicate immediate operands. | |
252b5132 RH |
719 | |
720 | @cindex identifiers, ARM | |
721 | @cindex ARM identifiers | |
722 | *TODO* Explain about /data modifier on symbols. | |
723 | ||
724 | @node ARM-Regs | |
725 | @subsection Register Names | |
726 | ||
727 | @cindex ARM register names | |
728 | @cindex register names, ARM | |
729 | *TODO* Explain about ARM register naming, and the predefined names. | |
730 | ||
b6895b4f PB |
731 | @node ARM-Relocations |
732 | @subsection ARM relocation generation | |
733 | ||
734 | @cindex data relocations, ARM | |
735 | @cindex ARM data relocations | |
736 | Specific data relocations can be generated by putting the relocation name | |
737 | in parentheses after the symbol name. For example: | |
738 | ||
739 | @smallexample | |
740 | .word foo(TARGET1) | |
741 | @end smallexample | |
742 | ||
743 | This will generate an @samp{R_ARM_TARGET1} relocation against the symbol | |
744 | @var{foo}. | |
745 | The following relocations are supported: | |
746 | @code{GOT}, | |
747 | @code{GOTOFF}, | |
748 | @code{TARGET1}, | |
749 | @code{TARGET2}, | |
750 | @code{SBREL}, | |
751 | @code{TLSGD}, | |
752 | @code{TLSLDM}, | |
753 | @code{TLSLDO}, | |
0855e32b NS |
754 | @code{TLSDESC}, |
755 | @code{TLSCALL}, | |
b43420e6 NC |
756 | @code{GOTTPOFF}, |
757 | @code{GOT_PREL} | |
b6895b4f PB |
758 | and |
759 | @code{TPOFF}. | |
760 | ||
761 | For compatibility with older toolchains the assembler also accepts | |
3da1d841 NC |
762 | @code{(PLT)} after branch targets. On legacy targets this will |
763 | generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI | |
764 | targets it will encode either the @samp{R_ARM_CALL} or | |
765 | @samp{R_ARM_JUMP24} relocation, as appropriate. | |
b6895b4f PB |
766 | |
767 | @cindex MOVW and MOVT relocations, ARM | |
768 | Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated | |
769 | by prefixing the value with @samp{#:lower16:} and @samp{#:upper16} | |
b45619c0 | 770 | respectively. For example to load the 32-bit address of foo into r0: |
252b5132 | 771 | |
b6895b4f PB |
772 | @smallexample |
773 | MOVW r0, #:lower16:foo | |
774 | MOVT r0, #:upper16:foo | |
775 | @end smallexample | |
252b5132 | 776 | |
72d98d16 MG |
777 | Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC}, |
778 | @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be | |
779 | generated by prefixing the value with @samp{#:lower0_7:#}, | |
780 | @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#} | |
781 | respectively. For example to load the 32-bit address of foo into r0: | |
782 | ||
783 | @smallexample | |
784 | MOVS r0, #:upper8_15:#foo | |
785 | LSLS r0, r0, #8 | |
786 | ADDS r0, #:upper0_7:#foo | |
787 | LSLS r0, r0, #8 | |
788 | ADDS r0, #:lower8_15:#foo | |
789 | LSLS r0, r0, #8 | |
790 | ADDS r0, #:lower0_7:#foo | |
791 | @end smallexample | |
792 | ||
ba724cfc NC |
793 | @node ARM-Neon-Alignment |
794 | @subsection NEON Alignment Specifiers | |
795 | ||
796 | @cindex alignment for NEON instructions | |
797 | Some NEON load/store instructions allow an optional address | |
798 | alignment qualifier. | |
799 | The ARM documentation specifies that this is indicated by | |
800 | @samp{@@ @var{align}}. However GAS already interprets | |
801 | the @samp{@@} character as a "line comment" start, | |
802 | so @samp{: @var{align}} is used instead. For example: | |
803 | ||
804 | @smallexample | |
805 | vld1.8 @{q0@}, [r0, :128] | |
806 | @end smallexample | |
807 | ||
808 | @node ARM Floating Point | |
809 | @section Floating Point | |
810 | ||
811 | @cindex floating point, ARM (@sc{ieee}) | |
812 | @cindex ARM floating point (@sc{ieee}) | |
813 | The ARM family uses @sc{ieee} floating-point numbers. | |
814 | ||
252b5132 RH |
815 | @node ARM Directives |
816 | @section ARM Machine Directives | |
817 | ||
818 | @cindex machine directives, ARM | |
819 | @cindex ARM machine directives | |
820 | @table @code | |
821 | ||
4a6bc624 NS |
822 | @c AAAAAAAAAAAAAAAAAAAAAAAAA |
823 | ||
2b841ec2 | 824 | @ifclear ELF |
4a6bc624 NS |
825 | @cindex @code{.2byte} directive, ARM |
826 | @cindex @code{.4byte} directive, ARM | |
827 | @cindex @code{.8byte} directive, ARM | |
828 | @item .2byte @var{expression} [, @var{expression}]* | |
829 | @itemx .4byte @var{expression} [, @var{expression}]* | |
830 | @itemx .8byte @var{expression} [, @var{expression}]* | |
831 | These directives write 2, 4 or 8 byte values to the output section. | |
2b841ec2 | 832 | @end ifclear |
4a6bc624 NS |
833 | |
834 | @cindex @code{.align} directive, ARM | |
adcf07e6 NC |
835 | @item .align @var{expression} [, @var{expression}] |
836 | This is the generic @var{.align} directive. For the ARM however if the | |
837 | first argument is zero (ie no alignment is needed) the assembler will | |
838 | behave as if the argument had been 2 (ie pad to the next four byte | |
062b7c0c | 839 | boundary). This is for compatibility with ARM's own assembler. |
adcf07e6 | 840 | |
4a6bc624 NS |
841 | @cindex @code{.arch} directive, ARM |
842 | @item .arch @var{name} | |
843 | Select the target architecture. Valid values for @var{name} are the same as | |
54691107 TP |
844 | for the @option{-march} command-line option without the instruction set |
845 | extension. | |
252b5132 | 846 | |
34bca508 | 847 | Specifying @code{.arch} clears any previously selected architecture |
69133863 MGD |
848 | extensions. |
849 | ||
850 | @cindex @code{.arch_extension} directive, ARM | |
851 | @item .arch_extension @var{name} | |
34bca508 L |
852 | Add or remove an architecture extension to the target architecture. Valid |
853 | values for @var{name} are the same as those accepted as architectural | |
a05a5b64 | 854 | extensions by the @option{-mcpu} and @option{-march} command-line options. |
69133863 MGD |
855 | |
856 | @code{.arch_extension} may be used multiple times to add or remove extensions | |
857 | incrementally to the architecture being compiled for. | |
858 | ||
4a6bc624 NS |
859 | @cindex @code{.arm} directive, ARM |
860 | @item .arm | |
861 | This performs the same action as @var{.code 32}. | |
252b5132 | 862 | |
4a6bc624 | 863 | @c BBBBBBBBBBBBBBBBBBBBBBBBBB |
0bbf2aa4 | 864 | |
4a6bc624 NS |
865 | @cindex @code{.bss} directive, ARM |
866 | @item .bss | |
867 | This directive switches to the @code{.bss} section. | |
0bbf2aa4 | 868 | |
4a6bc624 NS |
869 | @c CCCCCCCCCCCCCCCCCCCCCCCCCC |
870 | ||
871 | @cindex @code{.cantunwind} directive, ARM | |
872 | @item .cantunwind | |
873 | Prevents unwinding through the current function. No personality routine | |
874 | or exception table data is required or permitted. | |
875 | ||
876 | @cindex @code{.code} directive, ARM | |
877 | @item .code @code{[16|32]} | |
878 | This directive selects the instruction set being generated. The value 16 | |
879 | selects Thumb, with the value 32 selecting ARM. | |
880 | ||
881 | @cindex @code{.cpu} directive, ARM | |
882 | @item .cpu @var{name} | |
883 | Select the target processor. Valid values for @var{name} are the same as | |
54691107 TP |
884 | for the @option{-mcpu} command-line option without the instruction set |
885 | extension. | |
4a6bc624 | 886 | |
34bca508 | 887 | Specifying @code{.cpu} clears any previously selected architecture |
69133863 MGD |
888 | extensions. |
889 | ||
4a6bc624 NS |
890 | @c DDDDDDDDDDDDDDDDDDDDDDDDDD |
891 | ||
892 | @cindex @code{.dn} and @code{.qn} directives, ARM | |
f467aa98 | 893 | @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]] |
1f9bb1ca | 894 | @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]] |
23753660 JB |
895 | |
896 | The @code{dn} and @code{qn} directives are used to create typed | |
897 | and/or indexed register aliases for use in Advanced SIMD Extension | |
898 | (Neon) instructions. The former should be used to create aliases | |
899 | of double-precision registers, and the latter to create aliases of | |
900 | quad-precision registers. | |
901 | ||
902 | If these directives are used to create typed aliases, those aliases can | |
903 | be used in Neon instructions instead of writing types after the mnemonic | |
904 | or after each operand. For example: | |
905 | ||
906 | @smallexample | |
907 | x .dn d2.f32 | |
908 | y .dn d3.f32 | |
909 | z .dn d4.f32[1] | |
910 | vmul x,y,z | |
911 | @end smallexample | |
912 | ||
913 | This is equivalent to writing the following: | |
914 | ||
915 | @smallexample | |
916 | vmul.f32 d2,d3,d4[1] | |
917 | @end smallexample | |
918 | ||
919 | Aliases created using @code{dn} or @code{qn} can be destroyed using | |
920 | @code{unreq}. | |
921 | ||
4a6bc624 | 922 | @c EEEEEEEEEEEEEEEEEEEEEEEEEE |
252b5132 | 923 | |
4a6bc624 NS |
924 | @cindex @code{.eabi_attribute} directive, ARM |
925 | @item .eabi_attribute @var{tag}, @var{value} | |
926 | Set the EABI object attribute @var{tag} to @var{value}. | |
252b5132 | 927 | |
4a6bc624 NS |
928 | The @var{tag} is either an attribute number, or one of the following: |
929 | @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch}, | |
930 | @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use}, | |
75375b3e | 931 | @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch}, |
a7ad558c | 932 | @code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config}, |
4a6bc624 NS |
933 | @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data}, |
934 | @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use}, | |
935 | @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding}, | |
936 | @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions}, | |
937 | @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model}, | |
75375b3e | 938 | @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved}, |
4a6bc624 NS |
939 | @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use}, |
940 | @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args}, | |
941 | @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals}, | |
942 | @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access}, | |
75375b3e | 943 | @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format}, |
cd21e546 | 944 | @code{Tag_MPextension_use}, @code{Tag_DIV_use}, |
4a6bc624 NS |
945 | @code{Tag_nodefaults}, @code{Tag_also_compatible_with}, |
946 | @code{Tag_conformance}, @code{Tag_T2EE_use}, | |
cd21e546 | 947 | @code{Tag_Virtualization_use} |
4a6bc624 NS |
948 | |
949 | The @var{value} is either a @code{number}, @code{"string"}, or | |
950 | @code{number, "string"} depending on the tag. | |
951 | ||
75375b3e | 952 | Note - the following legacy values are also accepted by @var{tag}: |
34bca508 | 953 | @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed}, |
75375b3e MGD |
954 | @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension}, |
955 | ||
4a6bc624 NS |
956 | @cindex @code{.even} directive, ARM |
957 | @item .even | |
958 | This directive aligns to an even-numbered address. | |
959 | ||
960 | @cindex @code{.extend} directive, ARM | |
961 | @cindex @code{.ldouble} directive, ARM | |
962 | @item .extend @var{expression} [, @var{expression}]* | |
963 | @itemx .ldouble @var{expression} [, @var{expression}]* | |
964 | These directives write 12byte long double floating-point values to the | |
965 | output section. These are not compatible with current ARM processors | |
966 | or ABIs. | |
967 | ||
968 | @c FFFFFFFFFFFFFFFFFFFFFFFFFF | |
969 | ||
5312fe52 BW |
970 | @cindex @code{.float16} directive, ARM |
971 | @item .float16 @var{value [,...,value_n]} | |
972 | Place the half precision floating point representation of one or more | |
973 | floating-point values into the current section. The exact format of the | |
974 | encoding is specified by @code{.float16_format}. If the format has not | |
975 | been explicitly set yet (either via the @code{.float16_format} directive or | |
976 | the command line option) then the IEEE 754-2008 format is used. | |
977 | ||
978 | @cindex @code{.float16_format} directive, ARM | |
979 | @item .float16_format @var{format} | |
980 | Set the format to use when encoding float16 values emitted by | |
981 | the @code{.float16} directive. | |
982 | Once the format has been set it cannot be changed. | |
983 | @code{format} should be one of the following: @code{ieee} (encode in | |
984 | the IEEE 754-2008 half precision format) or @code{alternative} (encode in | |
985 | the Arm alternative half precision format). | |
986 | ||
4a6bc624 NS |
987 | @anchor{arm_fnend} |
988 | @cindex @code{.fnend} directive, ARM | |
989 | @item .fnend | |
990 | Marks the end of a function with an unwind table entry. The unwind index | |
991 | table entry is created when this directive is processed. | |
252b5132 | 992 | |
4a6bc624 NS |
993 | If no personality routine has been specified then standard personality |
994 | routine 0 or 1 will be used, depending on the number of unwind opcodes | |
995 | required. | |
996 | ||
997 | @anchor{arm_fnstart} | |
998 | @cindex @code{.fnstart} directive, ARM | |
999 | @item .fnstart | |
1000 | Marks the start of a function with an unwind table entry. | |
1001 | ||
1002 | @cindex @code{.force_thumb} directive, ARM | |
252b5132 RH |
1003 | @item .force_thumb |
1004 | This directive forces the selection of Thumb instructions, even if the | |
1005 | target processor does not support those instructions | |
1006 | ||
4a6bc624 NS |
1007 | @cindex @code{.fpu} directive, ARM |
1008 | @item .fpu @var{name} | |
1009 | Select the floating-point unit to assemble for. Valid values for @var{name} | |
a05a5b64 | 1010 | are the same as for the @option{-mfpu} command-line option. |
252b5132 | 1011 | |
4a6bc624 NS |
1012 | @c GGGGGGGGGGGGGGGGGGGGGGGGGG |
1013 | @c HHHHHHHHHHHHHHHHHHHHHHHHHH | |
e1da3f5b | 1014 | |
4a6bc624 NS |
1015 | @cindex @code{.handlerdata} directive, ARM |
1016 | @item .handlerdata | |
1017 | Marks the end of the current function, and the start of the exception table | |
1018 | entry for that function. Anything between this directive and the | |
1019 | @code{.fnend} directive will be added to the exception table entry. | |
1020 | ||
1021 | Must be preceded by a @code{.personality} or @code{.personalityindex} | |
1022 | directive. | |
1023 | ||
1024 | @c IIIIIIIIIIIIIIIIIIIIIIIIII | |
c921be7d NC |
1025 | |
1026 | @cindex @code{.inst} directive, ARM | |
1027 | @item .inst @var{opcode} [ , @dots{} ] | |
1f9bb1ca AS |
1028 | @itemx .inst.n @var{opcode} [ , @dots{} ] |
1029 | @itemx .inst.w @var{opcode} [ , @dots{} ] | |
c921be7d NC |
1030 | Generates the instruction corresponding to the numerical value @var{opcode}. |
1031 | @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be | |
1032 | specified explicitly, overriding the normal encoding rules. | |
1033 | ||
4a6bc624 NS |
1034 | @c JJJJJJJJJJJJJJJJJJJJJJJJJJ |
1035 | @c KKKKKKKKKKKKKKKKKKKKKKKKKK | |
1036 | @c LLLLLLLLLLLLLLLLLLLLLLLLLL | |
1037 | ||
1038 | @item .ldouble @var{expression} [, @var{expression}]* | |
1039 | See @code{.extend}. | |
5395a469 | 1040 | |
252b5132 RH |
1041 | @cindex @code{.ltorg} directive, ARM |
1042 | @item .ltorg | |
1043 | This directive causes the current contents of the literal pool to be | |
1044 | dumped into the current section (which is assumed to be the .text | |
1045 | section) at the current location (aligned to a word boundary). | |
3d0c9500 NC |
1046 | @code{GAS} maintains a separate literal pool for each section and each |
1047 | sub-section. The @code{.ltorg} directive will only affect the literal | |
1048 | pool of the current section and sub-section. At the end of assembly | |
1049 | all remaining, un-empty literal pools will automatically be dumped. | |
1050 | ||
1051 | Note - older versions of @code{GAS} would dump the current literal | |
1052 | pool any time a section change occurred. This is no longer done, since | |
1053 | it prevents accurate control of the placement of literal pools. | |
252b5132 | 1054 | |
4a6bc624 | 1055 | @c MMMMMMMMMMMMMMMMMMMMMMMMMM |
252b5132 | 1056 | |
4a6bc624 NS |
1057 | @cindex @code{.movsp} directive, ARM |
1058 | @item .movsp @var{reg} [, #@var{offset}] | |
1059 | Tell the unwinder that @var{reg} contains an offset from the current | |
1060 | stack pointer. If @var{offset} is not specified then it is assumed to be | |
1061 | zero. | |
7ed4c4c5 | 1062 | |
4a6bc624 NS |
1063 | @c NNNNNNNNNNNNNNNNNNNNNNNNNN |
1064 | @c OOOOOOOOOOOOOOOOOOOOOOOOOO | |
7ed4c4c5 | 1065 | |
4a6bc624 NS |
1066 | @cindex @code{.object_arch} directive, ARM |
1067 | @item .object_arch @var{name} | |
1068 | Override the architecture recorded in the EABI object attribute section. | |
1069 | Valid values for @var{name} are the same as for the @code{.arch} directive. | |
1070 | Typically this is useful when code uses runtime detection of CPU features. | |
7ed4c4c5 | 1071 | |
4a6bc624 NS |
1072 | @c PPPPPPPPPPPPPPPPPPPPPPPPPP |
1073 | ||
1074 | @cindex @code{.packed} directive, ARM | |
1075 | @item .packed @var{expression} [, @var{expression}]* | |
1076 | This directive writes 12-byte packed floating-point values to the | |
1077 | output section. These are not compatible with current ARM processors | |
1078 | or ABIs. | |
1079 | ||
ea4cff4f | 1080 | @anchor{arm_pad} |
4a6bc624 NS |
1081 | @cindex @code{.pad} directive, ARM |
1082 | @item .pad #@var{count} | |
1083 | Generate unwinder annotations for a stack adjustment of @var{count} bytes. | |
1084 | A positive value indicates the function prologue allocated stack space by | |
1085 | decrementing the stack pointer. | |
7ed4c4c5 NC |
1086 | |
1087 | @cindex @code{.personality} directive, ARM | |
1088 | @item .personality @var{name} | |
1089 | Sets the personality routine for the current function to @var{name}. | |
1090 | ||
1091 | @cindex @code{.personalityindex} directive, ARM | |
1092 | @item .personalityindex @var{index} | |
1093 | Sets the personality routine for the current function to the EABI standard | |
1094 | routine number @var{index} | |
1095 | ||
4a6bc624 NS |
1096 | @cindex @code{.pool} directive, ARM |
1097 | @item .pool | |
1098 | This is a synonym for .ltorg. | |
7ed4c4c5 | 1099 | |
4a6bc624 NS |
1100 | @c QQQQQQQQQQQQQQQQQQQQQQQQQQ |
1101 | @c RRRRRRRRRRRRRRRRRRRRRRRRRR | |
1102 | ||
1103 | @cindex @code{.req} directive, ARM | |
1104 | @item @var{name} .req @var{register name} | |
1105 | This creates an alias for @var{register name} called @var{name}. For | |
1106 | example: | |
1107 | ||
1108 | @smallexample | |
1109 | foo .req r0 | |
1110 | @end smallexample | |
1111 | ||
1112 | @c SSSSSSSSSSSSSSSSSSSSSSSSSS | |
7ed4c4c5 | 1113 | |
7da4f750 | 1114 | @anchor{arm_save} |
7ed4c4c5 NC |
1115 | @cindex @code{.save} directive, ARM |
1116 | @item .save @var{reglist} | |
1117 | Generate unwinder annotations to restore the registers in @var{reglist}. | |
1118 | The format of @var{reglist} is the same as the corresponding store-multiple | |
1119 | instruction. | |
1120 | ||
1121 | @smallexample | |
1122 | @exdent @emph{core registers} | |
1123 | .save @{r4, r5, r6, lr@} | |
1124 | stmfd sp!, @{r4, r5, r6, lr@} | |
1125 | @exdent @emph{FPA registers} | |
1126 | .save f4, 2 | |
1127 | sfmfd f4, 2, [sp]! | |
1128 | @exdent @emph{VFP registers} | |
1129 | .save @{d8, d9, d10@} | |
fa073d69 | 1130 | fstmdx sp!, @{d8, d9, d10@} |
7ed4c4c5 NC |
1131 | @exdent @emph{iWMMXt registers} |
1132 | .save @{wr10, wr11@} | |
1133 | wstrd wr11, [sp, #-8]! | |
1134 | wstrd wr10, [sp, #-8]! | |
1135 | or | |
1136 | .save wr11 | |
1137 | wstrd wr11, [sp, #-8]! | |
1138 | .save wr10 | |
1139 | wstrd wr10, [sp, #-8]! | |
1140 | @end smallexample | |
1141 | ||
7da4f750 | 1142 | @anchor{arm_setfp} |
7ed4c4c5 NC |
1143 | @cindex @code{.setfp} directive, ARM |
1144 | @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}] | |
4a6bc624 | 1145 | Make all unwinder annotations relative to a frame pointer. Without this |
7ed4c4c5 NC |
1146 | the unwinder will use offsets from the stack pointer. |
1147 | ||
a5b82cbe | 1148 | The syntax of this directive is the same as the @code{add} or @code{mov} |
7ed4c4c5 NC |
1149 | instruction used to set the frame pointer. @var{spreg} must be either |
1150 | @code{sp} or mentioned in a previous @code{.movsp} directive. | |
1151 | ||
1152 | @smallexample | |
1153 | .movsp ip | |
1154 | mov ip, sp | |
1155 | @dots{} | |
1156 | .setfp fp, ip, #4 | |
a5b82cbe | 1157 | add fp, ip, #4 |
7ed4c4c5 NC |
1158 | @end smallexample |
1159 | ||
4a6bc624 NS |
1160 | @cindex @code{.secrel32} directive, ARM |
1161 | @item .secrel32 @var{expression} [, @var{expression}]* | |
1162 | This directive emits relocations that evaluate to the section-relative | |
1163 | offset of each expression's symbol. This directive is only supported | |
1164 | for PE targets. | |
1165 | ||
cab7e4d9 NC |
1166 | @cindex @code{.syntax} directive, ARM |
1167 | @item .syntax [@code{unified} | @code{divided}] | |
1168 | This directive sets the Instruction Set Syntax as described in the | |
1169 | @ref{ARM-Instruction-Set} section. | |
1170 | ||
4a6bc624 NS |
1171 | @c TTTTTTTTTTTTTTTTTTTTTTTTTT |
1172 | ||
1173 | @cindex @code{.thumb} directive, ARM | |
1174 | @item .thumb | |
1175 | This performs the same action as @var{.code 16}. | |
1176 | ||
1177 | @cindex @code{.thumb_func} directive, ARM | |
1178 | @item .thumb_func | |
1179 | This directive specifies that the following symbol is the name of a | |
1180 | Thumb encoded function. This information is necessary in order to allow | |
1181 | the assembler and linker to generate correct code for interworking | |
1182 | between Arm and Thumb instructions and should be used even if | |
1183 | interworking is not going to be performed. The presence of this | |
1184 | directive also implies @code{.thumb} | |
1185 | ||
33eaf5de | 1186 | This directive is not necessary when generating EABI objects. On these |
4a6bc624 NS |
1187 | targets the encoding is implicit when generating Thumb code. |
1188 | ||
1189 | @cindex @code{.thumb_set} directive, ARM | |
1190 | @item .thumb_set | |
1191 | This performs the equivalent of a @code{.set} directive in that it | |
1192 | creates a symbol which is an alias for another symbol (possibly not yet | |
1193 | defined). This directive also has the added property in that it marks | |
1194 | the aliased symbol as being a thumb function entry point, in the same | |
1195 | way that the @code{.thumb_func} directive does. | |
1196 | ||
0855e32b NS |
1197 | @cindex @code{.tlsdescseq} directive, ARM |
1198 | @item .tlsdescseq @var{tls-variable} | |
1199 | This directive is used to annotate parts of an inlined TLS descriptor | |
1200 | trampoline. Normally the trampoline is provided by the linker, and | |
1201 | this directive is not needed. | |
1202 | ||
4a6bc624 NS |
1203 | @c UUUUUUUUUUUUUUUUUUUUUUUUUU |
1204 | ||
1205 | @cindex @code{.unreq} directive, ARM | |
1206 | @item .unreq @var{alias-name} | |
1207 | This undefines a register alias which was previously defined using the | |
1208 | @code{req}, @code{dn} or @code{qn} directives. For example: | |
1209 | ||
1210 | @smallexample | |
1211 | foo .req r0 | |
1212 | .unreq foo | |
1213 | @end smallexample | |
1214 | ||
1215 | An error occurs if the name is undefined. Note - this pseudo op can | |
1216 | be used to delete builtin in register name aliases (eg 'r0'). This | |
1217 | should only be done if it is really necessary. | |
1218 | ||
7ed4c4c5 | 1219 | @cindex @code{.unwind_raw} directive, ARM |
4a6bc624 | 1220 | @item .unwind_raw @var{offset}, @var{byte1}, @dots{} |
33eaf5de | 1221 | Insert one of more arbitrary unwind opcode bytes, which are known to adjust |
7ed4c4c5 NC |
1222 | the stack pointer by @var{offset} bytes. |
1223 | ||
1224 | For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to | |
1225 | @code{.save @{r0@}} | |
1226 | ||
4a6bc624 | 1227 | @c VVVVVVVVVVVVVVVVVVVVVVVVVV |
ee065d83 | 1228 | |
4a6bc624 NS |
1229 | @cindex @code{.vsave} directive, ARM |
1230 | @item .vsave @var{vfp-reglist} | |
1231 | Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist} | |
1232 | using FLDMD. Also works for VFPv3 registers | |
1233 | that are to be restored using VLDM. | |
1234 | The format of @var{vfp-reglist} is the same as the corresponding store-multiple | |
1235 | instruction. | |
ee065d83 | 1236 | |
4a6bc624 NS |
1237 | @smallexample |
1238 | @exdent @emph{VFP registers} | |
1239 | .vsave @{d8, d9, d10@} | |
1240 | fstmdd sp!, @{d8, d9, d10@} | |
1241 | @exdent @emph{VFPv3 registers} | |
1242 | .vsave @{d15, d16, d17@} | |
1243 | vstm sp!, @{d15, d16, d17@} | |
1244 | @end smallexample | |
e04befd0 | 1245 | |
4a6bc624 NS |
1246 | Since FLDMX and FSTMX are now deprecated, this directive should be |
1247 | used in favour of @code{.save} for saving VFP registers for ARMv6 and above. | |
e04befd0 | 1248 | |
4a6bc624 NS |
1249 | @c WWWWWWWWWWWWWWWWWWWWWWWWWW |
1250 | @c XXXXXXXXXXXXXXXXXXXXXXXXXX | |
1251 | @c YYYYYYYYYYYYYYYYYYYYYYYYYY | |
1252 | @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ | |
ee065d83 | 1253 | |
252b5132 RH |
1254 | @end table |
1255 | ||
1256 | @node ARM Opcodes | |
1257 | @section Opcodes | |
1258 | ||
1259 | @cindex ARM opcodes | |
1260 | @cindex opcodes for ARM | |
49a5575c NC |
1261 | @code{@value{AS}} implements all the standard ARM opcodes. It also |
1262 | implements several pseudo opcodes, including several synthetic load | |
34bca508 | 1263 | instructions. |
252b5132 | 1264 | |
49a5575c NC |
1265 | @table @code |
1266 | ||
1267 | @cindex @code{NOP} pseudo op, ARM | |
1268 | @item NOP | |
1269 | @smallexample | |
1270 | nop | |
1271 | @end smallexample | |
252b5132 | 1272 | |
49a5575c NC |
1273 | This pseudo op will always evaluate to a legal ARM instruction that does |
1274 | nothing. Currently it will evaluate to MOV r0, r0. | |
252b5132 | 1275 | |
49a5575c | 1276 | @cindex @code{LDR reg,=<label>} pseudo op, ARM |
34bca508 | 1277 | @item LDR |
252b5132 RH |
1278 | @smallexample |
1279 | ldr <register> , = <expression> | |
1280 | @end smallexample | |
1281 | ||
1282 | If expression evaluates to a numeric constant then a MOV or MVN | |
1283 | instruction will be used in place of the LDR instruction, if the | |
1284 | constant can be generated by either of these instructions. Otherwise | |
1285 | the constant will be placed into the nearest literal pool (if it not | |
1286 | already there) and a PC relative LDR instruction will be generated. | |
1287 | ||
49a5575c NC |
1288 | @cindex @code{ADR reg,<label>} pseudo op, ARM |
1289 | @item ADR | |
1290 | @smallexample | |
1291 | adr <register> <label> | |
1292 | @end smallexample | |
1293 | ||
1294 | This instruction will load the address of @var{label} into the indicated | |
1295 | register. The instruction will evaluate to a PC relative ADD or SUB | |
1296 | instruction depending upon where the label is located. If the label is | |
1297 | out of range, or if it is not defined in the same file (and section) as | |
1298 | the ADR instruction, then an error will be generated. This instruction | |
1299 | will not make use of the literal pool. | |
1300 | ||
fc6141f0 NC |
1301 | If @var{label} is a thumb function symbol, and thumb interworking has |
1302 | been enabled via the @option{-mthumb-interwork} option then the bottom | |
1303 | bit of the value stored into @var{register} will be set. This allows | |
1304 | the following sequence to work as expected: | |
1305 | ||
1306 | @smallexample | |
1307 | adr r0, thumb_function | |
1308 | blx r0 | |
1309 | @end smallexample | |
1310 | ||
49a5575c | 1311 | @cindex @code{ADRL reg,<label>} pseudo op, ARM |
34bca508 | 1312 | @item ADRL |
49a5575c NC |
1313 | @smallexample |
1314 | adrl <register> <label> | |
1315 | @end smallexample | |
1316 | ||
1317 | This instruction will load the address of @var{label} into the indicated | |
a349d9dd | 1318 | register. The instruction will evaluate to one or two PC relative ADD |
49a5575c NC |
1319 | or SUB instructions depending upon where the label is located. If a |
1320 | second instruction is not needed a NOP instruction will be generated in | |
1321 | its place, so that this instruction is always 8 bytes long. | |
1322 | ||
1323 | If the label is out of range, or if it is not defined in the same file | |
1324 | (and section) as the ADRL instruction, then an error will be generated. | |
1325 | This instruction will not make use of the literal pool. | |
1326 | ||
fc6141f0 NC |
1327 | If @var{label} is a thumb function symbol, and thumb interworking has |
1328 | been enabled via the @option{-mthumb-interwork} option then the bottom | |
1329 | bit of the value stored into @var{register} will be set. | |
1330 | ||
49a5575c NC |
1331 | @end table |
1332 | ||
252b5132 RH |
1333 | For information on the ARM or Thumb instruction sets, see @cite{ARM |
1334 | Software Development Toolkit Reference Manual}, Advanced RISC Machines | |
1335 | Ltd. | |
1336 | ||
6057a28f NC |
1337 | @node ARM Mapping Symbols |
1338 | @section Mapping Symbols | |
1339 | ||
1340 | The ARM ELF specification requires that special symbols be inserted | |
1341 | into object files to mark certain features: | |
1342 | ||
1343 | @table @code | |
1344 | ||
1345 | @cindex @code{$a} | |
1346 | @item $a | |
1347 | At the start of a region of code containing ARM instructions. | |
1348 | ||
1349 | @cindex @code{$t} | |
1350 | @item $t | |
1351 | At the start of a region of code containing THUMB instructions. | |
1352 | ||
1353 | @cindex @code{$d} | |
1354 | @item $d | |
1355 | At the start of a region of data. | |
1356 | ||
1357 | @end table | |
1358 | ||
1359 | The assembler will automatically insert these symbols for you - there | |
1360 | is no need to code them yourself. Support for tagging symbols ($b, | |
1361 | $f, $p and $m) which is also mentioned in the current ARM ELF | |
1362 | specification is not implemented. This is because they have been | |
1363 | dropped from the new EABI and so tools cannot rely upon their | |
1364 | presence. | |
1365 | ||
7da4f750 MM |
1366 | @node ARM Unwinding Tutorial |
1367 | @section Unwinding | |
1368 | ||
1369 | The ABI for the ARM Architecture specifies a standard format for | |
1370 | exception unwind information. This information is used when an | |
1371 | exception is thrown to determine where control should be transferred. | |
1372 | In particular, the unwind information is used to determine which | |
1373 | function called the function that threw the exception, and which | |
1374 | function called that one, and so forth. This information is also used | |
1375 | to restore the values of callee-saved registers in the function | |
1376 | catching the exception. | |
1377 | ||
1378 | If you are writing functions in assembly code, and those functions | |
1379 | call other functions that throw exceptions, you must use assembly | |
1380 | pseudo ops to ensure that appropriate exception unwind information is | |
1381 | generated. Otherwise, if one of the functions called by your assembly | |
1382 | code throws an exception, the run-time library will be unable to | |
1383 | unwind the stack through your assembly code and your program will not | |
1384 | behave correctly. | |
1385 | ||
1386 | To illustrate the use of these pseudo ops, we will examine the code | |
1387 | that G++ generates for the following C++ input: | |
1388 | ||
1389 | @verbatim | |
1390 | void callee (int *); | |
1391 | ||
34bca508 L |
1392 | int |
1393 | caller () | |
7da4f750 MM |
1394 | { |
1395 | int i; | |
1396 | callee (&i); | |
34bca508 | 1397 | return i; |
7da4f750 MM |
1398 | } |
1399 | @end verbatim | |
1400 | ||
1401 | This example does not show how to throw or catch an exception from | |
1402 | assembly code. That is a much more complex operation and should | |
1403 | always be done in a high-level language, such as C++, that directly | |
1404 | supports exceptions. | |
1405 | ||
1406 | The code generated by one particular version of G++ when compiling the | |
1407 | example above is: | |
1408 | ||
1409 | @verbatim | |
1410 | _Z6callerv: | |
1411 | .fnstart | |
1412 | .LFB2: | |
1413 | @ Function supports interworking. | |
1414 | @ args = 0, pretend = 0, frame = 8 | |
1415 | @ frame_needed = 1, uses_anonymous_args = 0 | |
1416 | stmfd sp!, {fp, lr} | |
1417 | .save {fp, lr} | |
1418 | .LCFI0: | |
1419 | .setfp fp, sp, #4 | |
1420 | add fp, sp, #4 | |
1421 | .LCFI1: | |
1422 | .pad #8 | |
1423 | sub sp, sp, #8 | |
1424 | .LCFI2: | |
1425 | sub r3, fp, #8 | |
1426 | mov r0, r3 | |
1427 | bl _Z6calleePi | |
1428 | ldr r3, [fp, #-8] | |
1429 | mov r0, r3 | |
1430 | sub sp, fp, #4 | |
1431 | ldmfd sp!, {fp, lr} | |
1432 | bx lr | |
1433 | .LFE2: | |
1434 | .fnend | |
1435 | @end verbatim | |
1436 | ||
1437 | Of course, the sequence of instructions varies based on the options | |
1438 | you pass to GCC and on the version of GCC in use. The exact | |
1439 | instructions are not important since we are focusing on the pseudo ops | |
1440 | that are used to generate unwind information. | |
1441 | ||
1442 | An important assumption made by the unwinder is that the stack frame | |
1443 | does not change during the body of the function. In particular, since | |
1444 | we assume that the assembly code does not itself throw an exception, | |
1445 | the only point where an exception can be thrown is from a call, such | |
1446 | as the @code{bl} instruction above. At each call site, the same saved | |
1447 | registers (including @code{lr}, which indicates the return address) | |
1448 | must be located in the same locations relative to the frame pointer. | |
1449 | ||
1450 | The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo | |
1451 | op appears immediately before the first instruction of the function | |
1452 | while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo | |
1453 | op appears immediately after the last instruction of the function. | |
34bca508 | 1454 | These pseudo ops specify the range of the function. |
7da4f750 MM |
1455 | |
1456 | Only the order of the other pseudos ops (e.g., @code{.setfp} or | |
1457 | @code{.pad}) matters; their exact locations are irrelevant. In the | |
1458 | example above, the compiler emits the pseudo ops with particular | |
1459 | instructions. That makes it easier to understand the code, but it is | |
1460 | not required for correctness. It would work just as well to emit all | |
1461 | of the pseudo ops other than @code{.fnend} in the same order, but | |
1462 | immediately after @code{.fnstart}. | |
1463 | ||
1464 | The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op | |
1465 | indicates registers that have been saved to the stack so that they can | |
1466 | be restored before the function returns. The argument to the | |
1467 | @code{.save} pseudo op is a list of registers to save. If a register | |
1468 | is ``callee-saved'' (as specified by the ABI) and is modified by the | |
1469 | function you are writing, then your code must save the value before it | |
1470 | is modified and restore the original value before the function | |
1471 | returns. If an exception is thrown, the run-time library restores the | |
1472 | values of these registers from their locations on the stack before | |
1473 | returning control to the exception handler. (Of course, if an | |
1474 | exception is not thrown, the function that contains the @code{.save} | |
1475 | pseudo op restores these registers in the function epilogue, as is | |
1476 | done with the @code{ldmfd} instruction above.) | |
1477 | ||
1478 | You do not have to save callee-saved registers at the very beginning | |
1479 | of the function and you do not need to use the @code{.save} pseudo op | |
1480 | immediately following the point at which the registers are saved. | |
1481 | However, if you modify a callee-saved register, you must save it on | |
1482 | the stack before modifying it and before calling any functions which | |
1483 | might throw an exception. And, you must use the @code{.save} pseudo | |
1484 | op to indicate that you have done so. | |
1485 | ||
1486 | The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a | |
1487 | modification of the stack pointer that does not save any registers. | |
1488 | The argument is the number of bytes (in decimal) that are subtracted | |
1489 | from the stack pointer. (On ARM CPUs, the stack grows downwards, so | |
1490 | subtracting from the stack pointer increases the size of the stack.) | |
1491 | ||
1492 | The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op | |
1493 | indicates the register that contains the frame pointer. The first | |
1494 | argument is the register that is set, which is typically @code{fp}. | |
1495 | The second argument indicates the register from which the frame | |
1496 | pointer takes its value. The third argument, if present, is the value | |
1497 | (in decimal) added to the register specified by the second argument to | |
1498 | compute the value of the frame pointer. You should not modify the | |
1499 | frame pointer in the body of the function. | |
1500 | ||
1501 | If you do not use a frame pointer, then you should not use the | |
1502 | @code{.setfp} pseudo op. If you do not use a frame pointer, then you | |
1503 | should avoid modifying the stack pointer outside of the function | |
1504 | prologue. Otherwise, the run-time library will be unable to find | |
1505 | saved registers when it is unwinding the stack. | |
1506 | ||
1507 | The pseudo ops described above are sufficient for writing assembly | |
1508 | code that calls functions which may throw exceptions. If you need to | |
1509 | know more about the object-file format used to represent unwind | |
1510 | information, you may consult the @cite{Exception Handling ABI for the | |
1511 | ARM Architecture} available from @uref{http://infocenter.arm.com}. | |
91f68a68 | 1512 |