Commit | Line | Data |
---|---|---|
7c31ae13 | 1 | @c Copyright 2005, 2006, 2009, 2010, 2011 |
07c1b327 CM |
2 | @c Free Software Foundation, Inc. |
3 | @c This is part of the GAS manual. | |
4 | @c For copying conditions, see the file as.texinfo. | |
8611b8fd MF |
5 | @c man end |
6 | ||
07c1b327 CM |
7 | @ifset GENERIC |
8 | @page | |
3b4e1885 | 9 | @node Blackfin-Dependent |
07c1b327 CM |
10 | @chapter Blackfin Dependent Features |
11 | @end ifset | |
8611b8fd | 12 | |
07c1b327 CM |
13 | @ifclear GENERIC |
14 | @node Machine Dependencies | |
15 | @chapter Blackfin Dependent Features | |
16 | @end ifclear | |
17 | ||
18 | @cindex Blackfin support | |
19 | @menu | |
6306cd85 BS |
20 | * Blackfin Options:: Blackfin Options |
21 | * Blackfin Syntax:: Blackfin Syntax | |
22 | * Blackfin Directives:: Blackfin Directives | |
07c1b327 CM |
23 | @end menu |
24 | ||
6306cd85 BS |
25 | @node Blackfin Options |
26 | @section Options | |
27 | @cindex Blackfin options (none) | |
28 | @cindex options for Blackfin (none) | |
29 | ||
8611b8fd MF |
30 | @c man begin OPTIONS |
31 | @table @gcctabopt | |
6306cd85 BS |
32 | |
33 | @cindex @code{-mcpu=} command line option, Blackfin | |
34 | @item -mcpu=@var{processor}@r{[}-@var{sirevision}@r{]} | |
35 | This option specifies the target processor. The optional @var{sirevision} | |
36 | is not used in assembler. It's here such that GCC can easily pass down its | |
37 | @code{-mcpu=} option. The assembler will issue an | |
38 | error message if an attempt is made to assemble an instruction which | |
39 | will not execute on the target processor. The following processor names are | |
40 | recognized: | |
a23c851a MF |
41 | @code{bf504}, |
42 | @code{bf506}, | |
3b4e1885 JZ |
43 | @code{bf512}, |
44 | @code{bf514}, | |
45 | @code{bf516}, | |
46 | @code{bf518}, | |
6306cd85 BS |
47 | @code{bf522}, |
48 | @code{bf523}, | |
49 | @code{bf524}, | |
50 | @code{bf525}, | |
51 | @code{bf526}, | |
52 | @code{bf527}, | |
53 | @code{bf531}, | |
54 | @code{bf532}, | |
55 | @code{bf533}, | |
56 | @code{bf534}, | |
57 | @code{bf535} (not implemented yet), | |
58 | @code{bf536}, | |
59 | @code{bf537}, | |
60 | @code{bf538}, | |
61 | @code{bf539}, | |
62 | @code{bf542}, | |
63 | @code{bf542m}, | |
64 | @code{bf544}, | |
65 | @code{bf544m}, | |
66 | @code{bf547}, | |
67 | @code{bf547m}, | |
68 | @code{bf548}, | |
69 | @code{bf548m}, | |
70 | @code{bf549}, | |
71 | @code{bf549m}, | |
6e38d384 | 72 | @code{bf561}, |
6306cd85 | 73 | and |
6e38d384 | 74 | @code{bf592}. |
6306cd85 | 75 | |
9982501a JZ |
76 | @cindex @code{-mfdpic} command line option, Blackfin |
77 | @item -mfdpic | |
78 | Assemble for the FDPIC ABI. | |
79 | ||
80 | @cindex @code{-mno-fdpic} command line option, Blackfin | |
81 | @cindex @code{-mnopic} command line option, Blackfin | |
1f9bb1ca AS |
82 | @item -mno-fdpic |
83 | @itemx -mnopic | |
9982501a | 84 | Disable -mfdpic. |
6306cd85 | 85 | @end table |
8611b8fd | 86 | @c man end |
6306cd85 BS |
87 | |
88 | @node Blackfin Syntax | |
07c1b327 | 89 | @section Syntax |
6306cd85 BS |
90 | @cindex Blackfin syntax |
91 | @cindex syntax, Blackfin | |
07c1b327 CM |
92 | |
93 | @table @code | |
94 | @item Special Characters | |
95 | Assembler input is free format and may appear anywhere on the line. | |
96 | One instruction may extend across multiple lines or more than one | |
97 | instruction may appear on the same line. White space (space, tab, | |
98 | comments or newline) may appear anywhere between tokens. A token must | |
99 | not have embedded spaces. Tokens include numbers, register names, | |
100 | keywords, user identifiers, and also some multicharacter special | |
101 | symbols like "+=", "/*" or "||". | |
102 | ||
7c31ae13 NC |
103 | Comments are introduced by the @samp{#} character and extend to the |
104 | end of the current line. If the @samp{#} appears as the first | |
105 | character of a line, the whole line is treated as a comment, but in | |
106 | this case the line can also be a logical line number directive | |
107 | (@pxref{Comments}) or a preprocessor control command | |
108 | (@pxref{Preprocessing}). | |
109 | ||
07c1b327 CM |
110 | @item Instruction Delimiting |
111 | A semicolon must terminate every instruction. Sometimes a complete | |
112 | instruction will consist of more than one operation. There are two | |
113 | cases where this occurs. The first is when two general operations | |
114 | are combined. Normally a comma separates the different parts, as in | |
115 | ||
116 | @smallexample | |
117 | a0= r3.h * r2.l, a1 = r3.l * r2.h ; | |
118 | @end smallexample | |
119 | ||
120 | The second case occurs when a general instruction is combined with one | |
121 | or two memory references for joint issue. The latter portions are | |
122 | set off by a "||" token. | |
123 | ||
124 | @smallexample | |
125 | a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; | |
126 | @end smallexample | |
127 | ||
347d120a | 128 | Multiple instructions can occur on the same line. Each must be |
7c31ae13 NC |
129 | terminated by a semicolon character. |
130 | ||
07c1b327 CM |
131 | @item Register Names |
132 | ||
133 | The assembler treats register names and instruction keywords in a case | |
134 | insensitive manner. User identifiers are case sensitive. Thus, R3.l, | |
135 | R3.L, r3.l and r3.L are all equivalent input to the assembler. | |
136 | ||
137 | Register names are reserved and may not be used as program identifiers. | |
138 | ||
139 | Some operations (such as "Move Register") require a register pair. | |
140 | Register pairs are always data registers and are denoted using a colon, | |
141 | eg., R3:2. The larger number must be written firsts. Note that the | |
142 | hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0. | |
143 | ||
144 | Some instructions (such as --SP (Push Multiple)) require a group of | |
145 | adjacent registers. Adjacent registers are denoted in the syntax by | |
146 | the range enclosed in parentheses and separated by a colon, eg., (R7:3). | |
147 | Again, the larger number appears first. | |
148 | ||
149 | Portions of a particular register may be individually specified. This | |
150 | is written with a dot (".") following the register name and then a | |
151 | letter denoting the desired portion. For 32-bit registers, ".H" | |
152 | denotes the most significant ("High") portion. ".L" denotes the | |
153 | least-significant portion. The subdivisions of the 40-bit registers | |
154 | are described later. | |
155 | ||
156 | @item Accumulators | |
157 | The set of 40-bit registers A1 and A0 that normally contain data that | |
158 | is being manipulated. Each accumulator can be accessed in four ways. | |
159 | ||
160 | @table @code | |
161 | @item one 40-bit register | |
162 | The register will be referred to as A1 or A0. | |
163 | @item one 32-bit register | |
164 | The registers are designated as A1.W or A0.W. | |
165 | @item two 16-bit registers | |
166 | The registers are designated as A1.H, A1.L, A0.H or A0.L. | |
167 | @item one 8-bit register | |
168 | The registers are designated as A1.X or A0.X for the bits that | |
169 | extend beyond bit 31. | |
170 | @end table | |
171 | ||
172 | @item Data Registers | |
173 | The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that | |
174 | normally contain data for manipulation. These are abbreviated as | |
175 | D-register or Dreg. Data registers can be accessed as 32-bit registers | |
176 | or as two independent 16-bit registers. The least significant 16 bits | |
b45619c0 | 177 | of each register is called the "low" half and is designated with ".L" |
07c1b327 | 178 | following the register name. The most significant 16 bits are called |
b45619c0 | 179 | the "high" half and is designated with ".H" following the name. |
07c1b327 CM |
180 | |
181 | @smallexample | |
182 | R7.L, r2.h, r4.L, R0.H | |
183 | @end smallexample | |
184 | ||
185 | @item Pointer Registers | |
186 | The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that | |
187 | normally contain byte addresses of data structures. These are | |
188 | abbreviated as P-register or Preg. | |
189 | ||
190 | @smallexample | |
191 | p2, p5, fp, sp | |
192 | @end smallexample | |
193 | ||
194 | @item Stack Pointer SP | |
195 | The stack pointer contains the 32-bit address of the last occupied | |
196 | byte location in the stack. The stack grows by decrementing the | |
197 | stack pointer. | |
198 | ||
199 | @item Frame Pointer FP | |
200 | The frame pointer contains the 32-bit address of the previous frame | |
201 | pointer in the stack. It is located at the top of a frame. | |
202 | ||
203 | @item Loop Top | |
204 | LT0 and LT1. These registers contain the 32-bit address of the top of | |
205 | a zero overhead loop. | |
206 | ||
207 | @item Loop Count | |
208 | LC0 and LC1. These registers contain the 32-bit counter of the zero | |
209 | overhead loop executions. | |
210 | ||
211 | @item Loop Bottom | |
212 | LB0 and LB1. These registers contain the 32-bit address of the bottom | |
213 | of a zero overhead loop. | |
214 | ||
215 | @item Index Registers | |
216 | The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte | |
217 | addresses of data structures. Abbreviated I-register or Ireg. | |
218 | ||
219 | @item Modify Registers | |
220 | The set of 32-bit registers (M0, M1, M2, M3) that normally contain | |
347d120a | 221 | offset values that are added and subtracted to one of the index |
07c1b327 CM |
222 | registers. Abbreviated as Mreg. |
223 | ||
224 | @item Length Registers | |
225 | The set of 32-bit registers (L0, L1, L2, L3) that normally contain the | |
226 | length in bytes of the circular buffer. Abbreviated as Lreg. Clear | |
227 | the Lreg to disable circular addressing for the corresponding Ireg. | |
228 | ||
229 | @item Base Registers | |
230 | The set of 32-bit registers (B0, B1, B2, B3) that normally contain the | |
231 | base address in bytes of the circular buffer. Abbreviated as Breg. | |
232 | ||
233 | @item Floating Point | |
234 | The Blackfin family has no hardware floating point but the .float | |
235 | directive generates ieee floating point numbers for use with software | |
236 | floating point libraries. | |
237 | ||
238 | @item Blackfin Opcodes | |
239 | For detailed information on the Blackfin machine instruction set, see | |
240 | the Blackfin(r) Processor Instruction Set Reference. | |
241 | ||
242 | @end table | |
243 | ||
6306cd85 | 244 | @node Blackfin Directives |
07c1b327 | 245 | @section Directives |
6306cd85 BS |
246 | @cindex Blackfin directives |
247 | @cindex directives, Blackfin | |
07c1b327 CM |
248 | |
249 | The following directives are provided for compatibility with the VDSP assembler. | |
250 | ||
251 | @table @code | |
252 | @item .byte2 | |
07c1b327 | 253 | Initializes a two byte data object. |
347d120a MF |
254 | |
255 | This maps to the @code{.short} directive. | |
256 | @item .byte4 | |
257 | Initializes a four byte data object. | |
258 | ||
259 | This maps to the @code{.int} directive. | |
07c1b327 | 260 | @item .db |
347d120a MF |
261 | Initializes a single byte data object. |
262 | ||
263 | This directive is a synonym for @code{.byte}. | |
07c1b327 | 264 | @item .dw |
347d120a MF |
265 | Initializes a two byte data object. |
266 | ||
267 | This directive is a synonym for @code{.byte2}. | |
268 | @item .dd | |
269 | Initializes a four byte data object. | |
270 | ||
271 | This directive is a synonym for @code{.byte4}. | |
07c1b327 CM |
272 | @item .var |
273 | Define and initialize a 32 bit data object. | |
274 | @end table |