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1 | @c Copyright (C) 1996 Free Software Foundation, Inc. |
2 | @c This is part of the GAS manual. | |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | @ifset GENERIC | |
5 | @page | |
6 | @node D10V-Dependent | |
7 | @chapter D10V Dependent Features | |
8 | @end ifset | |
9 | @ifclear GENERIC | |
10 | @node Machine Dependencies | |
11 | @chapter D10V Dependent Features | |
12 | @end ifclear | |
13 | ||
14 | @cindex D10V support | |
15 | @menu | |
16 | * D10V-Opts:: D10V Options | |
17 | * D10V-Syntax:: Syntax | |
18 | * D10V-Float:: Floating Point | |
19 | * D10V-opcodes:: Opcodes | |
20 | @end menu | |
21 | ||
22 | @node D10V-Opts | |
23 | @section D10V Options | |
24 | @cindex options, D10V | |
25 | @cindex D10V options | |
26 | The Mitsubishi D10V version of @code{@value{AS}} has a few machine | |
27 | dependent options. | |
28 | ||
29 | @table @samp | |
30 | @item -O | |
31 | The D10V can often execute two sub-instructions in parallel. When this option | |
32 | is used, @code{@value{AS}} will attempt to optimize its output by detecting when | |
33 | instructions can be executed in parallel. | |
34 | @end table | |
35 | ||
36 | @node D10V-Syntax | |
37 | @section Syntax | |
38 | @cindex D10V syntax | |
39 | @cindex syntax, D10V | |
40 | ||
41 | The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual. | |
42 | The differences are detailed below. | |
43 | ||
44 | @menu | |
45 | * D10V-Regs:: Register Names | |
46 | * D10V-Size:: Size Modifiers | |
d0810b2b | 47 | * D10V-Subs:: Sub-Instructions |
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48 | * D10V-Chars:: Special Characters |
49 | * D10V-Addressing:: Addressing Modes | |
50 | @end menu | |
51 | ||
52 | @node D10V-Regs | |
53 | @subsection Register Names | |
54 | @cindex D10V registers | |
55 | @cindex registers, D10V | |
56 | You can use the predefined symbols @samp{r0} through @samp{r15} to refer to the D10V | |
57 | registers. You can also use @samp{sp} as an alias for @samp{r15}. The accumulators | |
58 | are @samp{a0} and @samp{a1}. Register names are not case sensitive. | |
59 | ||
60 | The D10V also has predefined symbols for these control registers and status bits: | |
61 | @table @code | |
62 | @item psw | |
63 | Processor Status Word | |
64 | @item bpsw | |
65 | Backup Processor Status Word | |
66 | @item pc | |
67 | Program Counter | |
68 | @item bpc | |
69 | Backup Program Counter | |
70 | @item rpt_c | |
71 | Repeat Count | |
72 | @item rpt_s | |
73 | Repeat Start address | |
74 | @item rpt_e | |
75 | Repeat End address | |
76 | @item mod_s | |
77 | Modulo Start address | |
78 | @item mod_e | |
79 | Modulo End address | |
80 | @item iba | |
81 | Instruction Break Address | |
82 | @item f0 | |
83 | Flag 0 | |
84 | @item f1 | |
85 | Flag 1 | |
86 | @item c | |
87 | Carry flag | |
88 | @end table | |
d0810b2b | 89 | |
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90 | @node D10V-Size |
91 | @subsection Size Modifiers | |
92 | @cindex D10V size modifiers | |
93 | @cindex size modifiers, D10V | |
94 | The D10V version of @code{@value{AS}} uses the instruction names in the D10V | |
95 | Architecture Manual. However, the names in the manual are sometimes ambiguous. | |
96 | There are instruction names that can assemble to a short or long form opcode. | |
97 | How does the assembler pick the correct form? @code{@value{AS}} will always pick the | |
98 | smallest form if it can. When dealing with a symbol that is not defined yet when a | |
99 | line is being assembled, it will always use the long form. If you need to force the | |
100 | assembler to use either the short or long form of the instruction, you can append | |
101 | either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing | |
102 | an assembly program and you want to do a branch to a symbol that is defined later | |
103 | in your program, you can write @samp{bra.s foo}. | |
104 | Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which | |
105 | have both short and long forms. | |
106 | ||
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107 | @node D10V-Subs |
108 | @subsection Sub-Instructions | |
109 | @cindex D10V sub-instructions | |
110 | @cindex sub-instructions, D10V | |
111 | The D10V assembler takes as input a series of instructions, either one-per-line, | |
112 | or in the special two-per-line format described in the next section. Some of these | |
113 | instructions will be short-form or sub-instructions. These sub-instructions can be packed | |
114 | into a single instruction. The assembler will do this automatically. It will also detect | |
115 | when it should not pack instructions. For example, when a label is defined, the next | |
116 | instruction will never be packaged with the previous one. Whenever a branch and link | |
117 | instruction is called, it will not be packaged with the next instruction so the return | |
118 | address will be valid. Nops are automatically inserted when necessary. | |
119 | ||
120 | If you do not want the assembler automatically making these decisions, you can control | |
121 | the packaging and execution type (parallel or sequential) with the special execution | |
122 | symbols described in the next section. | |
123 | ||
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124 | @node D10V-Chars |
125 | @subsection Special Characters | |
126 | @cindex line comment character, D10V | |
127 | @cindex D10V line comment character | |
128 | @samp{;} and @samp{#} are the line comment characters. | |
129 | @cindex sub-instruction ordering, D10V | |
130 | @cindex D10V sub-instruction ordering | |
131 | Sub-instructions may be executed in order, in reverse-order, or in parallel. | |
132 | Instructions listed in the standard one-per-line format will be executed sequentially. | |
133 | To specify the executing order, use the following symbols: | |
134 | @table @samp | |
135 | @item -> | |
136 | Sequential with instruction on the left first. | |
137 | @item <- | |
138 | Sequential with instruction on the right first. | |
139 | @item || | |
140 | Parallel | |
141 | @end table | |
142 | The D10V syntax allows either one instruction per line, one instruction per line with | |
143 | the execution symbol, or two instructions per line. For example | |
144 | @table @code | |
145 | @item abs a1 -> abs r0 | |
146 | Execute these sequentially. The instruction on the right is in the right | |
147 | container and is executed second. | |
148 | @item abs r0 <- abs a1 | |
149 | Execute these reverse-sequentially. The instruction on the right is in the right | |
150 | container, and is executed first. | |
d0810b2b | 151 | @item ld2w r2,@@r8+ || mac a0,r0,r7 |
337350a3 | 152 | Execute these in parallel. |
d0810b2b | 153 | @item ld2w r2,@@r8+ || |
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154 | @itemx mac a0,r0,r7 |
155 | Two-line format. Execute these in parallel. | |
d0810b2b | 156 | @item ld2w r2,@@r8+ |
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157 | @itemx mac a0,r0,r7 |
158 | Two-line format. Execute these sequentially. Assembler will | |
159 | put them in the proper containers. | |
d0810b2b | 160 | @item ld2w r2,@@r8+ -> |
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161 | @itemx mac a0,r0,r7 |
162 | Two-line format. Execute these sequentially. Same as above but | |
163 | second instruction will always go into right container. | |
164 | @end table | |
165 | @cindex symbol names, @samp{$} in | |
166 | @cindex @code{$} in symbol names | |
167 | Since @samp{$} has no special meaning, you may use it in symbol names. | |
168 | ||
169 | @node D10V-Addressing | |
170 | @subsection Addressing Modes | |
171 | @cindex addressing modes, D10V | |
172 | @cindex D10V addressing modes | |
173 | @code{@value{AS}} understands the following addressing modes for the D10V. | |
174 | @code{R@var{n}} in the following refers to any of the numbered | |
175 | registers, but @emph{not} the control registers. | |
176 | @table @code | |
177 | @item R@var{n} | |
178 | Register direct | |
179 | @item @@R@var{n} | |
180 | Register indirect | |
181 | @item @@R@var{n}+ | |
182 | Register indirect with post-increment | |
183 | @item @@R@var{n}- | |
184 | Register indirect with post-decrement | |
185 | @item @@-SP | |
186 | Register indirect with pre-decrement | |
187 | @item @@(@var{disp}, R@var{n}) | |
188 | Register indirect with displacement | |
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189 | @item @var{addr} |
190 | PC relative address (for branch or rep). | |
191 | @item #@var{imm} | |
192 | Immediate data | |
193 | @end table | |
194 | ||
195 | @node D10V-Float | |
196 | @section Floating Point | |
197 | @cindex floating point, D10V | |
198 | @cindex D10V floating point | |
199 | The D10V has no hardware floating point, but the @code{.float} and @code{.double} | |
200 | directives generates @sc{ieee} floating-point numbers for compatibility | |
201 | with other development tools. | |
202 | ||
203 | @node D10V Opcodes | |
204 | @section Opcodes | |
205 | @cindex D10V opcode summary | |
206 | @cindex opcode summary, D10V | |
207 | @cindex mnemonics, D10V | |
208 | @cindex instruction summary, D10V | |
209 | For detailed information on the D10V machine instruction set, see | |
210 | @cite{D10V Architecture: A VLIW Microprocessor for Multimedia Applications} | |
211 | (Mitsubishi Electric Corp.). | |
212 | @code{@value{AS}} implements all the standard D10V opcodes. The only changes are those | |
213 | described in the section on size modifiers | |
214 |