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1 | @c Copyright (C) 1991, 92, 93, 94, 95, 97, 1998 Free Software Foundation, Inc. |
2 | @c This is part of the GAS manual. | |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | @ifset GENERIC | |
5 | @page | |
6 | @node i386-Dependent | |
7 | @chapter 80386 Dependent Features | |
8 | @end ifset | |
9 | @ifclear GENERIC | |
10 | @node Machine Dependencies | |
11 | @chapter 80386 Dependent Features | |
12 | @end ifclear | |
13 | ||
14 | @cindex i386 support | |
15 | @cindex i80306 support | |
16 | @menu | |
17 | * i386-Options:: Options | |
18 | * i386-Syntax:: AT&T Syntax versus Intel Syntax | |
19 | * i386-Mnemonics:: Instruction Naming | |
20 | * i386-Regs:: Register Naming | |
21 | * i386-Prefixes:: Instruction Prefixes | |
22 | * i386-Memory:: Memory References | |
23 | * i386-jumps:: Handling of Jump Instructions | |
24 | * i386-Float:: Floating Point | |
25 | * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations | |
26 | * i386-16bit:: Writing 16-bit Code | |
e413e4e9 | 27 | * i386-Arch:: Specifying an x86 CPU architecture |
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28 | * i386-Bugs:: AT&T Syntax bugs |
29 | * i386-Notes:: Notes | |
30 | @end menu | |
31 | ||
32 | @node i386-Options | |
33 | @section Options | |
34 | ||
35 | @cindex options for i386 (none) | |
36 | @cindex i386 options (none) | |
37 | The 80386 has no machine dependent options. | |
38 | ||
e413e4e9 | 39 | |
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40 | @node i386-Syntax |
41 | @section AT&T Syntax versus Intel Syntax | |
42 | ||
e413e4e9 AM |
43 | @cindex i386 intel_syntax pseudo op |
44 | @cindex intel_syntax pseudo op, i386 | |
45 | @cindex i386 att_syntax pseudo op | |
46 | @cindex att_syntax pseudo op, i386 | |
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47 | @cindex i386 syntax compatibility |
48 | @cindex syntax compatibility, i386 | |
e413e4e9 AM |
49 | |
50 | @code{@value{AS}} now supports assembly using Intel assembler syntax. | |
51 | @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches | |
52 | back to the usual AT&T mode for compatibility with the output of | |
53 | @code{@value{GCC}}. Either of these directives may have an optional | |
54 | argument, @code{prefix}, or @code{noprefix} specifying whether registers | |
55 | require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite | |
252b5132 RH |
56 | different from Intel syntax. We mention these differences because |
57 | almost all 80386 documents use Intel syntax. Notable differences | |
58 | between the two syntaxes are: | |
59 | ||
60 | @cindex immediate operands, i386 | |
61 | @cindex i386 immediate operands | |
62 | @cindex register operands, i386 | |
63 | @cindex i386 register operands | |
64 | @cindex jump/call operands, i386 | |
65 | @cindex i386 jump/call operands | |
66 | @cindex operand delimiters, i386 | |
67 | @itemize @bullet | |
68 | @item | |
69 | AT&T immediate operands are preceded by @samp{$}; Intel immediate | |
70 | operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). | |
71 | AT&T register operands are preceded by @samp{%}; Intel register operands | |
72 | are undelimited. AT&T absolute (as opposed to PC relative) jump/call | |
73 | operands are prefixed by @samp{*}; they are undelimited in Intel syntax. | |
74 | ||
75 | @cindex i386 source, destination operands | |
76 | @cindex source, destination operands; i386 | |
77 | @item | |
78 | AT&T and Intel syntax use the opposite order for source and destination | |
79 | operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The | |
80 | @samp{source, dest} convention is maintained for compatibility with | |
81 | previous Unix assemblers. Note that instructions with more than one | |
82 | source operand, such as the @samp{enter} instruction, do @emph{not} have | |
83 | reversed order. @ref{i386-Bugs}. | |
84 | ||
85 | @cindex mnemonic suffixes, i386 | |
86 | @cindex sizes operands, i386 | |
87 | @cindex i386 size suffixes | |
88 | @item | |
89 | In AT&T syntax the size of memory operands is determined from the last | |
90 | character of the instruction mnemonic. Mnemonic suffixes of @samp{b}, | |
91 | @samp{w}, and @samp{l} specify byte (8-bit), word (16-bit), and long | |
92 | (32-bit) memory references. Intel syntax accomplishes this by prefixing | |
93 | memory operands (@emph{not} the instruction mnemonics) with @samp{byte | |
94 | ptr}, @samp{word ptr}, and @samp{dword ptr}. Thus, Intel @samp{mov al, | |
95 | byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T syntax. | |
96 | ||
97 | @cindex return instructions, i386 | |
98 | @cindex i386 jump, call, return | |
99 | @item | |
100 | Immediate form long jumps and calls are | |
101 | @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the | |
102 | Intel syntax is | |
103 | @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return | |
104 | instruction | |
105 | is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is | |
106 | @samp{ret far @var{stack-adjust}}. | |
107 | ||
108 | @cindex sections, i386 | |
109 | @cindex i386 sections | |
110 | @item | |
111 | The AT&T assembler does not provide support for multiple section | |
112 | programs. Unix style systems expect all programs to be single sections. | |
113 | @end itemize | |
114 | ||
115 | @node i386-Mnemonics | |
116 | @section Instruction Naming | |
117 | ||
118 | @cindex i386 instruction naming | |
119 | @cindex instruction naming, i386 | |
120 | Instruction mnemonics are suffixed with one character modifiers which | |
121 | specify the size of operands. The letters @samp{b}, @samp{w}, and | |
122 | @samp{l} specify byte, word, and long operands. If no suffix is | |
123 | specified by an instruction then @code{@value{AS}} tries to fill in the | |
124 | missing suffix based on the destination register operand (the last one | |
125 | by convention). Thus, @samp{mov %ax, %bx} is equivalent to @samp{movw | |
126 | %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to @samp{movw $1, | |
127 | %bx}. Note that this is incompatible with the AT&T Unix assembler which | |
128 | assumes that a missing mnemonic suffix implies long operand size. (This | |
129 | incompatibility does not affect compiler output since compilers always | |
130 | explicitly specify the mnemonic suffix.) | |
131 | ||
132 | Almost all instructions have the same names in AT&T and Intel format. | |
133 | There are a few exceptions. The sign extend and zero extend | |
134 | instructions need two sizes to specify them. They need a size to | |
135 | sign/zero extend @emph{from} and a size to zero extend @emph{to}. This | |
136 | is accomplished by using two instruction mnemonic suffixes in AT&T | |
137 | syntax. Base names for sign extend and zero extend are | |
138 | @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx} | |
139 | and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes | |
140 | are tacked on to this base name, the @emph{from} suffix before the | |
141 | @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for | |
142 | ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes, | |
143 | thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), | |
144 | and @samp{wl} (from word to long). | |
145 | ||
146 | @cindex conversion instructions, i386 | |
147 | @cindex i386 conversion instructions | |
148 | The Intel-syntax conversion instructions | |
149 | ||
150 | @itemize @bullet | |
151 | @item | |
152 | @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, | |
153 | ||
154 | @item | |
155 | @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, | |
156 | ||
157 | @item | |
158 | @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, | |
159 | ||
160 | @item | |
161 | @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, | |
162 | @end itemize | |
163 | ||
164 | @noindent | |
165 | are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, and @samp{cltd} in | |
166 | AT&T naming. @code{@value{AS}} accepts either naming for these instructions. | |
167 | ||
168 | @cindex jump instructions, i386 | |
169 | @cindex call instructions, i386 | |
170 | Far call/jump instructions are @samp{lcall} and @samp{ljmp} in | |
171 | AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel | |
172 | convention. | |
173 | ||
174 | @node i386-Regs | |
175 | @section Register Naming | |
176 | ||
177 | @cindex i386 registers | |
178 | @cindex registers, i386 | |
179 | Register operands are always prefixed with @samp{%}. The 80386 registers | |
180 | consist of | |
181 | ||
182 | @itemize @bullet | |
183 | @item | |
184 | the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, | |
185 | @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the | |
186 | frame pointer), and @samp{%esp} (the stack pointer). | |
187 | ||
188 | @item | |
189 | the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, | |
190 | @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. | |
191 | ||
192 | @item | |
193 | the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, | |
194 | @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These | |
195 | are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, | |
196 | @samp{%cx}, and @samp{%dx}) | |
197 | ||
198 | @item | |
199 | the 6 section registers @samp{%cs} (code section), @samp{%ds} | |
200 | (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, | |
201 | and @samp{%gs}. | |
202 | ||
203 | @item | |
204 | the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and | |
205 | @samp{%cr3}. | |
206 | ||
207 | @item | |
208 | the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, | |
209 | @samp{%db3}, @samp{%db6}, and @samp{%db7}. | |
210 | ||
211 | @item | |
212 | the 2 test registers @samp{%tr6} and @samp{%tr7}. | |
213 | ||
214 | @item | |
215 | the 8 floating point register stack @samp{%st} or equivalently | |
216 | @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, | |
217 | @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. | |
218 | @end itemize | |
219 | ||
220 | @node i386-Prefixes | |
221 | @section Instruction Prefixes | |
222 | ||
223 | @cindex i386 instruction prefixes | |
224 | @cindex instruction prefixes, i386 | |
225 | @cindex prefixes, i386 | |
226 | Instruction prefixes are used to modify the following instruction. They | |
227 | are used to repeat string instructions, to provide section overrides, to | |
228 | perform bus lock operations, and to change operand and address sizes. | |
229 | (Most instructions that normally operate on 32-bit operands will use | |
230 | 16-bit operands if the instruction has an ``operand size'' prefix.) | |
231 | Instruction prefixes are best written on the same line as the instruction | |
232 | they act upon. For example, the @samp{scas} (scan string) instruction is | |
233 | repeated with: | |
234 | ||
235 | @smallexample | |
236 | repne scas %es:(%edi),%al | |
237 | @end smallexample | |
238 | ||
239 | You may also place prefixes on the lines immediately preceding the | |
240 | instruction, but this circumvents checks that @code{@value{AS}} does | |
241 | with prefixes, and will not work with all prefixes. | |
242 | ||
243 | Here is a list of instruction prefixes: | |
244 | ||
245 | @cindex section override prefixes, i386 | |
246 | @itemize @bullet | |
247 | @item | |
248 | Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, | |
249 | @samp{fs}, @samp{gs}. These are automatically added by specifying | |
250 | using the @var{section}:@var{memory-operand} form for memory references. | |
251 | ||
252 | @cindex size prefixes, i386 | |
253 | @item | |
254 | Operand/Address size prefixes @samp{data16} and @samp{addr16} | |
255 | change 32-bit operands/addresses into 16-bit operands/addresses, | |
256 | while @samp{data32} and @samp{addr32} change 16-bit ones (in a | |
257 | @code{.code16} section) into 32-bit operands/addresses. These prefixes | |
258 | @emph{must} appear on the same line of code as the instruction they | |
259 | modify. For example, in a 16-bit @code{.code16} section, you might | |
260 | write: | |
261 | ||
262 | @smallexample | |
263 | addr32 jmpl *(%ebx) | |
264 | @end smallexample | |
265 | ||
266 | @cindex bus lock prefixes, i386 | |
267 | @cindex inhibiting interrupts, i386 | |
268 | @item | |
269 | The bus lock prefix @samp{lock} inhibits interrupts during execution of | |
270 | the instruction it precedes. (This is only valid with certain | |
271 | instructions; see a 80386 manual for details). | |
272 | ||
273 | @cindex coprocessor wait, i386 | |
274 | @item | |
275 | The wait for coprocessor prefix @samp{wait} waits for the coprocessor to | |
276 | complete the current instruction. This should never be needed for the | |
277 | 80386/80387 combination. | |
278 | ||
279 | @cindex repeat prefixes, i386 | |
280 | @item | |
281 | The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added | |
282 | to string instructions to make them repeat @samp{%ecx} times (@samp{%cx} | |
283 | times if the current address size is 16-bits). | |
284 | @end itemize | |
285 | ||
286 | @node i386-Memory | |
287 | @section Memory References | |
288 | ||
289 | @cindex i386 memory references | |
290 | @cindex memory references, i386 | |
291 | An Intel syntax indirect memory reference of the form | |
292 | ||
293 | @smallexample | |
294 | @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] | |
295 | @end smallexample | |
296 | ||
297 | @noindent | |
298 | is translated into the AT&T syntax | |
299 | ||
300 | @smallexample | |
301 | @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) | |
302 | @end smallexample | |
303 | ||
304 | @noindent | |
305 | where @var{base} and @var{index} are the optional 32-bit base and | |
306 | index registers, @var{disp} is the optional displacement, and | |
307 | @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} | |
308 | to calculate the address of the operand. If no @var{scale} is | |
309 | specified, @var{scale} is taken to be 1. @var{section} specifies the | |
310 | optional section register for the memory operand, and may override the | |
311 | default section register (see a 80386 manual for section register | |
312 | defaults). Note that section overrides in AT&T syntax @emph{must} | |
313 | be preceded by a @samp{%}. If you specify a section override which | |
314 | coincides with the default section register, @code{@value{AS}} does @emph{not} | |
315 | output any section register override prefixes to assemble the given | |
316 | instruction. Thus, section overrides can be specified to emphasize which | |
317 | section register is used for a given memory operand. | |
318 | ||
319 | Here are some examples of Intel and AT&T style memory references: | |
320 | ||
321 | @table @asis | |
322 | @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} | |
323 | @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is | |
324 | missing, and the default section is used (@samp{%ss} for addressing with | |
325 | @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. | |
326 | ||
327 | @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} | |
328 | @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is | |
329 | @samp{foo}. All other fields are missing. The section register here | |
330 | defaults to @samp{%ds}. | |
331 | ||
332 | @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} | |
333 | This uses the value pointed to by @samp{foo} as a memory operand. | |
334 | Note that @var{base} and @var{index} are both missing, but there is only | |
335 | @emph{one} @samp{,}. This is a syntactic exception. | |
336 | ||
337 | @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} | |
338 | This selects the contents of the variable @samp{foo} with section | |
339 | register @var{section} being @samp{%gs}. | |
340 | @end table | |
341 | ||
342 | Absolute (as opposed to PC relative) call and jump operands must be | |
343 | prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} | |
344 | always chooses PC relative addressing for jump/call labels. | |
345 | ||
346 | Any instruction that has a memory operand, but no register operand, | |
347 | @emph{must} specify its size (byte, word, or long) with an instruction | |
348 | mnemonic suffix (@samp{b}, @samp{w}, or @samp{l}, respectively). | |
349 | ||
350 | @node i386-jumps | |
351 | @section Handling of Jump Instructions | |
352 | ||
353 | @cindex jump optimization, i386 | |
354 | @cindex i386 jump optimization | |
355 | Jump instructions are always optimized to use the smallest possible | |
356 | displacements. This is accomplished by using byte (8-bit) displacement | |
357 | jumps whenever the target is sufficiently close. If a byte displacement | |
358 | is insufficient a long (32-bit) displacement is used. We do not support | |
359 | word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump | |
360 | instruction with the @samp{data16} instruction prefix), since the 80386 | |
361 | insists upon masking @samp{%eip} to 16 bits after the word displacement | |
362 | is added. | |
363 | ||
364 | Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, | |
365 | @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte | |
366 | displacements, so that if you use these instructions (@code{@value{GCC}} does | |
367 | not use them) you may get an error message (and incorrect code). The AT&T | |
368 | 80386 assembler tries to get around this problem by expanding @samp{jcxz foo} | |
369 | to | |
370 | ||
371 | @smallexample | |
372 | jcxz cx_zero | |
373 | jmp cx_nonzero | |
374 | cx_zero: jmp foo | |
375 | cx_nonzero: | |
376 | @end smallexample | |
377 | ||
378 | @node i386-Float | |
379 | @section Floating Point | |
380 | ||
381 | @cindex i386 floating point | |
382 | @cindex floating point, i386 | |
383 | All 80387 floating point types except packed BCD are supported. | |
384 | (BCD support may be added without much difficulty). These data | |
385 | types are 16-, 32-, and 64- bit integers, and single (32-bit), | |
386 | double (64-bit), and extended (80-bit) precision floating point. | |
387 | Each supported type has an instruction mnemonic suffix and a constructor | |
388 | associated with it. Instruction mnemonic suffixes specify the operand's | |
389 | data type. Constructors build these data types into memory. | |
390 | ||
391 | @cindex @code{float} directive, i386 | |
392 | @cindex @code{single} directive, i386 | |
393 | @cindex @code{double} directive, i386 | |
394 | @cindex @code{tfloat} directive, i386 | |
395 | @itemize @bullet | |
396 | @item | |
397 | Floating point constructors are @samp{.float} or @samp{.single}, | |
398 | @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. | |
399 | These correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, | |
400 | and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 | |
401 | only supports this format via the @samp{fldt} (load 80-bit real to stack | |
402 | top) and @samp{fstpt} (store 80-bit real and pop stack) instructions. | |
403 | ||
404 | @cindex @code{word} directive, i386 | |
405 | @cindex @code{long} directive, i386 | |
406 | @cindex @code{int} directive, i386 | |
407 | @cindex @code{quad} directive, i386 | |
408 | @item | |
409 | Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and | |
410 | @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The | |
411 | corresponding instruction mnemonic suffixes are @samp{s} (single), | |
412 | @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, | |
413 | the 64-bit @samp{q} format is only present in the @samp{fildq} (load | |
414 | quad integer to stack top) and @samp{fistpq} (store quad integer and pop | |
415 | stack) instructions. | |
416 | @end itemize | |
417 | ||
418 | Register to register operations should not use instruction mnemonic suffixes. | |
419 | @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you | |
420 | wrote @samp{fst %st, %st(1)}, since all register to register operations | |
421 | use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, | |
422 | which converts @samp{%st} from 80-bit to 64-bit floating point format, | |
423 | then stores the result in the 4 byte location @samp{mem}) | |
424 | ||
425 | @node i386-SIMD | |
426 | @section Intel's MMX and AMD's 3DNow! SIMD Operations | |
427 | ||
428 | @cindex MMX, i386 | |
429 | @cindex 3DNow!, i386 | |
430 | @cindex SIMD, i386 | |
431 | ||
432 | @code{@value{AS}} supports Intel's MMX instruction set (SIMD | |
433 | instructions for integer data), available on Intel's Pentium MMX | |
434 | processors and Pentium II processors, AMD's K6 and K6-2 processors, | |
435 | Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow! | |
436 | instruction set (SIMD instructions for 32-bit floating point data) | |
437 | available on AMD's K6-2 processor and possibly others in the future. | |
438 | ||
439 | Currently, @code{@value{AS}} does not support Intel's floating point | |
440 | SIMD, Katmai (KNI). | |
441 | ||
442 | The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, | |
443 | @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four | |
444 | 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit | |
445 | floating point values. The MMX registers cannot be used at the same time | |
446 | as the floating point stack. | |
447 | ||
448 | See Intel and AMD documentation, keeping in mind that the operand order in | |
449 | instructions is reversed from the Intel syntax. | |
450 | ||
451 | @node i386-16bit | |
452 | @section Writing 16-bit Code | |
453 | ||
454 | @cindex i386 16-bit code | |
455 | @cindex 16-bit code, i386 | |
456 | @cindex real-mode code, i386 | |
eecb386c | 457 | @cindex @code{code16gcc} directive, i386 |
252b5132 RH |
458 | @cindex @code{code16} directive, i386 |
459 | @cindex @code{code32} directive, i386 | |
460 | While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code, | |
461 | it also supports writing code to run in real mode or in 16-bit protected | |
eecb386c AM |
462 | mode code segments. To do this, put a @samp{.code16} or |
463 | @samp{.code16gcc} directive before the assembly language instructions to | |
464 | be run in 16-bit mode. You can switch @code{@value{AS}} back to writing | |
465 | normal 32-bit code with the @samp{.code32} directive. | |
466 | ||
467 | @samp{.code16gcc} provides experimental support for generating 16-bit | |
468 | code from gcc, and differs from @samp{.code16} in that @samp{call}, | |
469 | @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, | |
470 | @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions | |
471 | default to 32-bit size. This is so that the stack pointer is | |
472 | manipulated in the same way over function calls, allowing access to | |
473 | function parameters at the same stack offsets as in 32-bit mode. | |
474 | @samp{.code16gcc} also automatically adds address size prefixes where | |
475 | necessary to use the 32-bit addressing modes that gcc generates. | |
252b5132 RH |
476 | |
477 | The code which @code{@value{AS}} generates in 16-bit mode will not | |
478 | necessarily run on a 16-bit pre-80386 processor. To write code that | |
479 | runs on such a processor, you must refrain from using @emph{any} 32-bit | |
480 | constructs which require @code{@value{AS}} to output address or operand | |
481 | size prefixes. | |
482 | ||
483 | Note that writing 16-bit code instructions by explicitly specifying a | |
484 | prefix or an instruction mnemonic suffix within a 32-bit code section | |
485 | generates different machine instructions than those generated for a | |
486 | 16-bit code segment. In a 32-bit code section, the following code | |
487 | generates the machine opcode bytes @samp{66 6a 04}, which pushes the | |
488 | value @samp{4} onto the stack, decrementing @samp{%esp} by 2. | |
489 | ||
490 | @smallexample | |
491 | pushw $4 | |
492 | @end smallexample | |
493 | ||
494 | The same code in a 16-bit code section would generate the machine | |
495 | opcode bytes @samp{6a 04} (ie. without the operand size prefix), which | |
496 | is correct since the processor default operand size is assumed to be 16 | |
497 | bits in a 16-bit code section. | |
498 | ||
499 | @node i386-Bugs | |
500 | @section AT&T Syntax bugs | |
501 | ||
502 | The UnixWare assembler, and probably other AT&T derived ix86 Unix | |
503 | assemblers, generate floating point instructions with reversed source | |
504 | and destination registers in certain cases. Unfortunately, gcc and | |
505 | possibly many other programs use this reversed syntax, so we're stuck | |
506 | with it. | |
507 | ||
508 | For example | |
509 | ||
510 | @smallexample | |
511 | fsub %st,%st(3) | |
512 | @end smallexample | |
513 | @noindent | |
514 | results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather | |
515 | than the expected @samp{%st(3) - %st}. This happens with all the | |
516 | non-commutative arithmetic floating point operations with two register | |
517 | operands where the source register is @samp{%st} and the destination | |
518 | register is @samp{%st(i)}. | |
519 | ||
e413e4e9 AM |
520 | @node i386-Arch |
521 | @section Specifying CPU Architecture | |
522 | ||
523 | @cindex arch directive, i386 | |
524 | @cindex i386 arch directive | |
525 | ||
526 | @code{@value{AS}} may be told to assemble for a particular CPU | |
527 | architecture with the @code{.arch @var{cpu_type}} directive. This | |
528 | directive enables a warning when gas detects an instruction that is not | |
529 | supported on the CPU specified. The choices for @var{cpu_type} are: | |
530 | ||
531 | @multitable @columnfractions .20 .20 .20 .20 | |
532 | @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} | |
533 | @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} | |
534 | @item @samp{pentiumpro} @tab @samp{k6} @tab @samp{athlon} | |
535 | @end multitable | |
536 | ||
537 | Apart from the warning, there is only one other effect on | |
538 | @code{@value{AS}} operation; If you specify a CPU other than | |
539 | @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax} | |
540 | will automatically use a two byte opcode sequence. The larger three | |
541 | byte opcode sequence is used on the 486 (and when no architecture is | |
542 | specified) because it executes faster on the 486. Note that you can | |
543 | explicitly request the two byte opcode by writing @samp{sarl %eax}. | |
544 | ||
252b5132 RH |
545 | @node i386-Notes |
546 | @section Notes | |
547 | ||
548 | @cindex i386 @code{mul}, @code{imul} instructions | |
549 | @cindex @code{mul} instruction, i386 | |
550 | @cindex @code{imul} instruction, i386 | |
551 | There is some trickery concerning the @samp{mul} and @samp{imul} | |
552 | instructions that deserves mention. The 16-, 32-, and 64-bit expanding | |
553 | multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 | |
554 | for @samp{imul}) can be output only in the one operand form. Thus, | |
555 | @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; | |
556 | the expanding multiply would clobber the @samp{%edx} register, and this | |
557 | would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the | |
558 | 64-bit product in @samp{%edx:%eax}. | |
559 | ||
560 | We have added a two operand form of @samp{imul} when the first operand | |
561 | is an immediate mode expression and the second operand is a register. | |
562 | This is just a shorthand, so that, multiplying @samp{%eax} by 69, for | |
563 | example, can be done with @samp{imul $69, %eax} rather than @samp{imul | |
564 | $69, %eax, %eax}. | |
565 |