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1 | @c Copyright (C) 1991, 92, 93, 94, 95, 97, 1998 Free Software Foundation, Inc. |
2 | @c This is part of the GAS manual. | |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | @ifset GENERIC | |
5 | @page | |
6 | @node i386-Dependent | |
7 | @chapter 80386 Dependent Features | |
8 | @end ifset | |
9 | @ifclear GENERIC | |
10 | @node Machine Dependencies | |
11 | @chapter 80386 Dependent Features | |
12 | @end ifclear | |
13 | ||
14 | @cindex i386 support | |
15 | @cindex i80306 support | |
16 | @menu | |
17 | * i386-Options:: Options | |
18 | * i386-Syntax:: AT&T Syntax versus Intel Syntax | |
19 | * i386-Opcodes:: Opcode Naming | |
20 | * i386-Regs:: Register Naming | |
21 | * i386-prefixes:: Opcode Prefixes | |
22 | * i386-Memory:: Memory References | |
23 | * i386-jumps:: Handling of Jump Instructions | |
24 | * i386-Float:: Floating Point | |
25 | * i386-16bit:: Writing 16-bit Code | |
26 | * i386-Bugs:: AT&T Syntax bugs | |
27 | * i386-Notes:: Notes | |
28 | @end menu | |
29 | ||
30 | @node i386-Options | |
31 | @section Options | |
32 | ||
33 | @cindex options for i386 (none) | |
34 | @cindex i386 options (none) | |
35 | The 80386 has no machine dependent options. | |
36 | ||
37 | @node i386-Syntax | |
38 | @section AT&T Syntax versus Intel Syntax | |
39 | ||
40 | @cindex i386 syntax compatibility | |
41 | @cindex syntax compatibility, i386 | |
42 | In order to maintain compatibility with the output of @code{@value{GCC}}, | |
43 | @code{@value{AS}} supports AT&T System V/386 assembler syntax. This is quite | |
44 | different from Intel syntax. We mention these differences because | |
45 | almost all 80386 documents use Intel syntax. Notable differences | |
46 | between the two syntaxes are: | |
47 | ||
48 | @cindex immediate operands, i386 | |
49 | @cindex i386 immediate operands | |
50 | @cindex register operands, i386 | |
51 | @cindex i386 register operands | |
52 | @cindex jump/call operands, i386 | |
53 | @cindex i386 jump/call operands | |
54 | @cindex operand delimiters, i386 | |
55 | @itemize @bullet | |
56 | @item | |
57 | AT&T immediate operands are preceded by @samp{$}; Intel immediate | |
58 | operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). | |
59 | AT&T register operands are preceded by @samp{%}; Intel register operands | |
60 | are undelimited. AT&T absolute (as opposed to PC relative) jump/call | |
61 | operands are prefixed by @samp{*}; they are undelimited in Intel syntax. | |
62 | ||
63 | @cindex i386 source, destination operands | |
64 | @cindex source, destination operands; i386 | |
65 | @item | |
66 | AT&T and Intel syntax use the opposite order for source and destination | |
67 | operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The | |
68 | @samp{source, dest} convention is maintained for compatibility with | |
69 | previous Unix assemblers. Note that instructions with more than one | |
70 | source operand, such as the @samp{enter} instruction, do @emph{not} have | |
71 | reversed order. @ref{i386-Bugs}. | |
72 | ||
73 | @cindex opcode suffixes, i386 | |
74 | @cindex sizes operands, i386 | |
75 | @cindex i386 size suffixes | |
76 | @item | |
77 | In AT&T syntax the size of memory operands is determined from the last | |
78 | character of the opcode name. Opcode suffixes of @samp{b}, @samp{w}, | |
79 | and @samp{l} specify byte (8-bit), word (16-bit), and long (32-bit) | |
83d0817a | 80 | memory references. Intel syntax accomplishes this by prefixing memory |
e03a9757 ILT |
81 | operands (@emph{not} the opcodes themselves) with @samp{byte ptr}, |
82 | @samp{word ptr}, and @samp{dword ptr}. Thus, Intel @samp{mov al, byte | |
83 | ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T syntax. | |
84 | ||
85 | @cindex return instructions, i386 | |
86 | @cindex i386 jump, call, return | |
87 | @item | |
88 | Immediate form long jumps and calls are | |
89 | @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the | |
90 | Intel syntax is | |
91 | @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return | |
92 | instruction | |
93 | is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is | |
94 | @samp{ret far @var{stack-adjust}}. | |
95 | ||
96 | @cindex sections, i386 | |
97 | @cindex i386 sections | |
98 | @item | |
99 | The AT&T assembler does not provide support for multiple section | |
100 | programs. Unix style systems expect all programs to be single sections. | |
101 | @end itemize | |
102 | ||
103 | @node i386-Opcodes | |
104 | @section Opcode Naming | |
105 | ||
106 | @cindex i386 opcode naming | |
107 | @cindex opcode naming, i386 | |
108 | Opcode names are suffixed with one character modifiers which specify the | |
109 | size of operands. The letters @samp{b}, @samp{w}, and @samp{l} specify | |
110 | byte, word, and long operands. If no suffix is specified by an | |
111 | instruction then @code{@value{AS}} tries to | |
112 | fill in the missing suffix based on the destination register operand | |
113 | (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent | |
114 | to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to | |
115 | @samp{movw $1, %bx}. Note that this is incompatible with the AT&T Unix | |
116 | assembler which assumes that a missing opcode suffix implies long | |
117 | operand size. (This incompatibility does not affect compiler output | |
118 | since compilers always explicitly specify the opcode suffix.) | |
119 | ||
120 | Almost all opcodes have the same names in AT&T and Intel format. There | |
121 | are a few exceptions. The sign extend and zero extend instructions need | |
122 | two sizes to specify them. They need a size to sign/zero extend | |
123 | @emph{from} and a size to zero extend @emph{to}. This is accomplished | |
124 | by using two opcode suffixes in AT&T syntax. Base names for sign extend | |
125 | and zero extend are @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T | |
126 | syntax (@samp{movsx} and @samp{movzx} in Intel syntax). The opcode | |
127 | suffixes are tacked on to this base name, the @emph{from} suffix before | |
128 | the @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for | |
129 | ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes, | |
130 | thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), | |
131 | and @samp{wl} (from word to long). | |
132 | ||
133 | @cindex conversion instructions, i386 | |
134 | @cindex i386 conversion instructions | |
135 | The Intel-syntax conversion instructions | |
136 | ||
137 | @itemize @bullet | |
138 | @item | |
139 | @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, | |
140 | ||
141 | @item | |
142 | @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, | |
143 | ||
144 | @item | |
145 | @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, | |
146 | ||
147 | @item | |
148 | @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, | |
149 | @end itemize | |
150 | ||
151 | @noindent | |
152 | are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, and @samp{cltd} in | |
153 | AT&T naming. @code{@value{AS}} accepts either naming for these instructions. | |
154 | ||
155 | @cindex jump instructions, i386 | |
156 | @cindex call instructions, i386 | |
157 | Far call/jump instructions are @samp{lcall} and @samp{ljmp} in | |
158 | AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel | |
159 | convention. | |
160 | ||
161 | @node i386-Regs | |
162 | @section Register Naming | |
163 | ||
164 | @cindex i386 registers | |
165 | @cindex registers, i386 | |
166 | Register operands are always prefixed with @samp{%}. The 80386 registers | |
167 | consist of | |
168 | ||
169 | @itemize @bullet | |
170 | @item | |
171 | the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, | |
172 | @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the | |
173 | frame pointer), and @samp{%esp} (the stack pointer). | |
174 | ||
175 | @item | |
176 | the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, | |
177 | @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. | |
178 | ||
179 | @item | |
180 | the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, | |
181 | @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These | |
182 | are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, | |
183 | @samp{%cx}, and @samp{%dx}) | |
184 | ||
185 | @item | |
186 | the 6 section registers @samp{%cs} (code section), @samp{%ds} | |
187 | (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, | |
188 | and @samp{%gs}. | |
189 | ||
190 | @item | |
191 | the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and | |
192 | @samp{%cr3}. | |
193 | ||
194 | @item | |
195 | the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, | |
196 | @samp{%db3}, @samp{%db6}, and @samp{%db7}. | |
197 | ||
198 | @item | |
199 | the 2 test registers @samp{%tr6} and @samp{%tr7}. | |
200 | ||
201 | @item | |
202 | the 8 floating point register stack @samp{%st} or equivalently | |
203 | @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, | |
204 | @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. | |
205 | @end itemize | |
206 | ||
207 | @node i386-prefixes | |
208 | @section Opcode Prefixes | |
209 | ||
210 | @cindex i386 opcode prefixes | |
211 | @cindex opcode prefixes, i386 | |
212 | @cindex prefixes, i386 | |
213 | Opcode prefixes are used to modify the following opcode. They are used | |
214 | to repeat string instructions, to provide section overrides, to perform | |
215 | bus lock operations, and to give operand and address size (16-bit | |
216 | operands are specified in an instruction by prefixing what would | |
217 | normally be 32-bit operands with a ``operand size'' opcode prefix). | |
83d0817a ILT |
218 | Opcode prefixes are best written on the same line as the instruction |
219 | they act upon. For example, the @samp{scas} (scan string) instruction is | |
220 | repeated with: | |
221 | ||
e03a9757 | 222 | @smallexample |
83d0817a | 223 | repne scas %es:(%edi),%al |
e03a9757 ILT |
224 | @end smallexample |
225 | ||
83d0817a ILT |
226 | You may also place prefixes on the lines immediately preceding the |
227 | opcode, but this circumvents checks that @code{@value{AS}} does with | |
228 | prefixes, and will not work with all prefixes. | |
229 | ||
e03a9757 ILT |
230 | Here is a list of opcode prefixes: |
231 | ||
232 | @cindex section override prefixes, i386 | |
233 | @itemize @bullet | |
234 | @item | |
235 | Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, | |
236 | @samp{fs}, @samp{gs}. These are automatically added by specifying | |
237 | using the @var{section}:@var{memory-operand} form for memory references. | |
238 | ||
239 | @cindex size prefixes, i386 | |
240 | @item | |
241 | Operand/Address size prefixes @samp{data16} and @samp{addr16} | |
242 | change 32-bit operands/addresses into 16-bit operands/addresses, | |
243 | while @samp{data32} and @samp{addr32} change 16-bit ones (in a | |
83d0817a ILT |
244 | @code{.code16} section) into 32-bit operands/addresses. These prefixes |
245 | @emph{must} appear on the same line of code as the opcode they modify. | |
246 | For example, in a 16-bit @code{.code16} section, you might write: | |
247 | ||
248 | @smallexample | |
249 | addr32 jmpl *(%ebx) | |
250 | @end smallexample | |
e03a9757 ILT |
251 | |
252 | @cindex bus lock prefixes, i386 | |
253 | @cindex inhibiting interrupts, i386 | |
254 | @item | |
255 | The bus lock prefix @samp{lock} inhibits interrupts during | |
256 | execution of the instruction it precedes. (This is only valid with | |
257 | certain instructions; see a 80386 manual for details). | |
258 | ||
259 | @cindex coprocessor wait, i386 | |
260 | @item | |
261 | The wait for coprocessor prefix @samp{wait} waits for the | |
262 | coprocessor to complete the current instruction. This should never be | |
263 | needed for the 80386/80387 combination. | |
264 | ||
265 | @cindex repeat prefixes, i386 | |
266 | @item | |
267 | The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added | |
268 | to string instructions to make them repeat @samp{%ecx} times. | |
269 | @end itemize | |
270 | ||
271 | @node i386-Memory | |
272 | @section Memory References | |
273 | ||
274 | @cindex i386 memory references | |
275 | @cindex memory references, i386 | |
276 | An Intel syntax indirect memory reference of the form | |
277 | ||
278 | @smallexample | |
279 | @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] | |
280 | @end smallexample | |
281 | ||
282 | @noindent | |
283 | is translated into the AT&T syntax | |
284 | ||
285 | @smallexample | |
286 | @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) | |
287 | @end smallexample | |
288 | ||
289 | @noindent | |
290 | where @var{base} and @var{index} are the optional 32-bit base and | |
291 | index registers, @var{disp} is the optional displacement, and | |
292 | @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} | |
293 | to calculate the address of the operand. If no @var{scale} is | |
294 | specified, @var{scale} is taken to be 1. @var{section} specifies the | |
295 | optional section register for the memory operand, and may override the | |
296 | default section register (see a 80386 manual for section register | |
83d0817a | 297 | defaults). Note that section overrides in AT&T syntax @emph{must} |
e03a9757 ILT |
298 | be preceded by a @samp{%}. If you specify a section override which |
299 | coincides with the default section register, @code{@value{AS}} does @emph{not} | |
300 | output any section register override prefixes to assemble the given | |
301 | instruction. Thus, section overrides can be specified to emphasize which | |
302 | section register is used for a given memory operand. | |
303 | ||
304 | Here are some examples of Intel and AT&T style memory references: | |
305 | ||
306 | @table @asis | |
307 | @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} | |
308 | @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is | |
309 | missing, and the default section is used (@samp{%ss} for addressing with | |
310 | @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. | |
311 | ||
312 | @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} | |
313 | @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is | |
314 | @samp{foo}. All other fields are missing. The section register here | |
315 | defaults to @samp{%ds}. | |
316 | ||
317 | @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} | |
318 | This uses the value pointed to by @samp{foo} as a memory operand. | |
319 | Note that @var{base} and @var{index} are both missing, but there is only | |
320 | @emph{one} @samp{,}. This is a syntactic exception. | |
321 | ||
322 | @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} | |
323 | This selects the contents of the variable @samp{foo} with section | |
324 | register @var{section} being @samp{%gs}. | |
325 | @end table | |
326 | ||
327 | Absolute (as opposed to PC relative) call and jump operands must be | |
328 | prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} | |
329 | always chooses PC relative addressing for jump/call labels. | |
330 | ||
331 | Any instruction that has a memory operand, but no register operand, | |
332 | @emph{must} specify its size (byte, word, or long) with an opcode suffix | |
333 | (@samp{b}, @samp{w}, or @samp{l}, respectively). | |
334 | ||
335 | @node i386-jumps | |
336 | @section Handling of Jump Instructions | |
337 | ||
338 | @cindex jump optimization, i386 | |
339 | @cindex i386 jump optimization | |
340 | Jump instructions are always optimized to use the smallest possible | |
341 | displacements. This is accomplished by using byte (8-bit) displacement | |
342 | jumps whenever the target is sufficiently close. If a byte displacement | |
343 | is insufficient a long (32-bit) displacement is used. We do not support | |
344 | word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump instruction | |
345 | with the @samp{data16} opcode prefix), since the 80386 insists upon masking | |
346 | @samp{%eip} to 16 bits after the word displacement is added. | |
347 | ||
348 | Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, | |
349 | @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte | |
350 | displacements, so that if you use these instructions (@code{@value{GCC}} does | |
351 | not use them) you may get an error message (and incorrect code). The AT&T | |
352 | 80386 assembler tries to get around this problem by expanding @samp{jcxz foo} | |
353 | to | |
354 | ||
355 | @smallexample | |
356 | jcxz cx_zero | |
357 | jmp cx_nonzero | |
358 | cx_zero: jmp foo | |
359 | cx_nonzero: | |
360 | @end smallexample | |
361 | ||
362 | @node i386-Float | |
363 | @section Floating Point | |
364 | ||
365 | @cindex i386 floating point | |
366 | @cindex floating point, i386 | |
367 | All 80387 floating point types except packed BCD are supported. | |
368 | (BCD support may be added without much difficulty). These data | |
369 | types are 16-, 32-, and 64- bit integers, and single (32-bit), | |
370 | double (64-bit), and extended (80-bit) precision floating point. | |
371 | Each supported type has an opcode suffix and a constructor | |
372 | associated with it. Opcode suffixes specify operand's data | |
373 | types. Constructors build these data types into memory. | |
374 | ||
375 | @cindex @code{float} directive, i386 | |
376 | @cindex @code{single} directive, i386 | |
377 | @cindex @code{double} directive, i386 | |
378 | @cindex @code{tfloat} directive, i386 | |
379 | @itemize @bullet | |
380 | @item | |
381 | Floating point constructors are @samp{.float} or @samp{.single}, | |
382 | @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. | |
383 | These correspond to opcode suffixes @samp{s}, @samp{l}, and @samp{t}. | |
83d0817a ILT |
384 | @samp{t} stands for 80-bit real. The 80387 only supports this format |
385 | via the @samp{fldt} (load 80-bit real to stack top) and @samp{fstpt} | |
386 | (store 80-bit real and pop stack) instructions. | |
e03a9757 ILT |
387 | |
388 | @cindex @code{word} directive, i386 | |
389 | @cindex @code{long} directive, i386 | |
390 | @cindex @code{int} directive, i386 | |
391 | @cindex @code{quad} directive, i386 | |
392 | @item | |
393 | Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and | |
83d0817a ILT |
394 | @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The |
395 | corresponding opcode suffixes are @samp{s} (single), @samp{l} (long), | |
396 | and @samp{q} (quad). As with the 80-bit real format, the 64-bit | |
397 | @samp{q} format is only present in the @samp{fildq} (load quad integer | |
398 | to stack top) and @samp{fistpq} (store quad integer and pop stack) | |
399 | instructions. | |
e03a9757 ILT |
400 | @end itemize |
401 | ||
402 | Register to register operations should not use opcode suffixes. | |
403 | @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you | |
404 | wrote @samp{fst %st, %st(1)}, since all register to register operations | |
405 | use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, | |
406 | which converts @samp{%st} from 80-bit to 64-bit floating point format, | |
407 | then stores the result in the 4 byte location @samp{mem}) | |
408 | ||
409 | @node i386-16bit | |
410 | @section Writing 16-bit Code | |
411 | ||
412 | @cindex i386 16-bit code | |
413 | @cindex 16-bit code, i386 | |
414 | @cindex real-mode code, i386 | |
415 | @cindex @code{code16} directive, i386 | |
416 | @cindex @code{code32} directive, i386 | |
417 | While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code, | |
418 | it also supports writing code to run in real mode or in 16-bit protected | |
419 | mode code segments. To do this, put a @samp{.code16} directive before | |
420 | the assembly language instructions to be run in 16-bit mode. You can | |
421 | switch @code{@value{AS}} back to writing normal 32-bit code with the | |
422 | @samp{.code32} directive. | |
423 | ||
424 | The code which @code{@value{AS}} generates in 16-bit mode will not | |
425 | necessarily run on a 16-bit pre-80386 processor. To write code that | |
426 | runs on such a processor, you must refrain from using @emph{any} 32-bit | |
427 | constructs which require @code{@value{AS}} to output address or operand | |
428 | size prefixes. | |
429 | ||
430 | Note that writing 16-bit code instructions by explicitly specifying a | |
431 | prefix or a suffix within a 32-bit code section generates different | |
432 | machine instructions than those generated for a 16-bit code segment. In a | |
433 | 32-bit code section, the following code generates the machine | |
434 | instruction sequence @samp{66 6a 04}, which pushes the value @samp{4} onto | |
435 | the stack, decrementing @samp{%esp} by 2. | |
436 | ||
437 | @smallexample | |
438 | pushw $4 | |
439 | @end smallexample | |
440 | ||
441 | The same code in a 16-bit code section would generate the machine | |
442 | instruction sequence @samp{6a 04} (ie. without the operand size prefix), | |
443 | which is correct since the processor default operand size is assumed to | |
444 | be 16 bits in a 16-bit code section. | |
445 | ||
446 | @node i386-Bugs | |
447 | @section AT&T Syntax bugs | |
448 | ||
449 | The UnixWare assembler, and probably other AT&T derived ix86 Unix | |
450 | assemblers, generate floating point instructions with reversed source | |
451 | and destination registers in certain cases. Unfortunately, gcc and | |
452 | possibly many other programs use this reversed syntax, so we're stuck | |
453 | with it. | |
454 | ||
455 | For example | |
456 | ||
457 | @smallexample | |
458 | fsub %st,%st(3) | |
459 | @end smallexample | |
460 | @noindent | |
461 | results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather | |
462 | than the expected @samp{%st(3) - %st}. This happens with all the | |
463 | non-commutative arithmetic floating point operations with two register | |
464 | operands where the source register is @samp{%st} and the destination | |
465 | register is @samp{%st(i)}. | |
466 | ||
467 | @node i386-Notes | |
468 | @section Notes | |
469 | ||
470 | @cindex i386 @code{mul}, @code{imul} instructions | |
471 | @cindex @code{mul} instruction, i386 | |
472 | @cindex @code{imul} instruction, i386 | |
473 | There is some trickery concerning the @samp{mul} and @samp{imul} | |
474 | instructions that deserves mention. The 16-, 32-, and 64-bit expanding | |
475 | multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 | |
476 | for @samp{imul}) can be output only in the one operand form. Thus, | |
477 | @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; | |
478 | the expanding multiply would clobber the @samp{%edx} register, and this | |
479 | would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the | |
480 | 64-bit product in @samp{%edx:%eax}. | |
481 | ||
482 | We have added a two operand form of @samp{imul} when the first operand | |
483 | is an immediate mode expression and the second operand is a register. | |
484 | This is just a shorthand, so that, multiplying @samp{%eax} by 69, for | |
485 | example, can be done with @samp{imul $69, %eax} rather than @samp{imul | |
486 | $69, %eax, %eax}. | |
487 |