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f7e42eb4 | 1 | @c Copyright 2000 Free Software Foundation, Inc. |
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2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | @ifset GENERIC | |
5 | @page | |
6 | @node i860-Dependent | |
7 | @chapter Intel i860 Dependent Features | |
8 | @end ifset | |
9 | @ifclear GENERIC | |
10 | @node Machine Dependencies | |
11 | @chapter Intel i860 Dependent Features | |
12 | @end ifclear | |
13 | ||
14 | @ignore | |
15 | @c FIXME: This is basically a stub for i860. There is tons more information | |
16 | that I will add later (jle@cygnus.com). The assembler is still being | |
17 | written. The i860 assembler that existed previously was never finished | |
18 | and doesn't even build. Further, its not BFD_ASSEMBLER and it doesn't | |
19 | do ELF (it doesn't do anything, but you get the point). | |
20 | @end ignore | |
21 | ||
22 | @cindex i860 support | |
23 | @menu | |
a9c99419 | 24 | * Notes-i860:: i860 Notes |
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25 | * Options-i860:: i860 Command-line Options |
26 | * Directives-i860:: i860 Machine Directives | |
27 | * Opcodes for i860:: i860 Opcodes | |
28 | @end menu | |
29 | ||
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30 | @node Notes-i860 |
31 | @section i860 Notes | |
32 | This is a fairly complete i860 assembler which is compatible with the | |
33 | UNIX System V/860 Release 4 assembler. However, it does not currently | |
34 | support SVR4 PIC (i.e., @code{@@GOT, @@GOTOFF, @@PLT}). | |
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36 | Like the SVR4/860 assembler, the output object format is ELF32. Currently, |
37 | this is the only supported object format. If there is sufficient interest, | |
38 | other formats such as COFF may be implemented. | |
39 | @node Options-i860 | |
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40 | @section i860 Command-line Options |
41 | @subsection SVR4 compatibility options | |
42 | @table @code | |
43 | @item -V | |
44 | Print assembler version. | |
45 | @item -Qy | |
46 | Ignored. | |
47 | @item -Qn | |
48 | Ignored. | |
49 | @end table | |
50 | @subsection Other options | |
51 | @table @code | |
52 | @item -EL | |
53 | Select little endian output (this is the default). | |
54 | @item -EB | |
55 | Select big endian output. Note that the i860 always reads instructions | |
56 | as little endian data, so this option only effects data and not | |
57 | instructions. | |
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58 | @item -mwarn-expand |
59 | Emit a warning message if any pseudo-instruction expansions occurred. | |
60 | For example, a @code{or} instruction with an immediate larger than 16-bits | |
61 | will be expanded into two instructions. This is a very undesirable feature to | |
62 | rely on, so this flag can help detect any code where it happens. One | |
63 | use of it, for instance, has been to find and eliminate any place | |
64 | where @code{gcc} may emit these pseudo-instructions. | |
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65 | @end table |
66 | ||
67 | @node Directives-i860 | |
68 | @section i860 Machine Directives | |
69 | ||
70 | @cindex machine directives, i860 | |
71 | @cindex i860 machine directives | |
72 | ||
73 | @table @code | |
74 | @cindex @code{dual} directive, i860 | |
75 | @item .dual | |
76 | Enter dual instruction mode. While this directive is supported, the | |
77 | preferred way to use dual instruction mode is to explicitly code | |
78 | the dual bit with the @code{d.} prefix. | |
79 | @end table | |
80 | ||
81 | @table @code | |
82 | @cindex @code{enddual} directive, i860 | |
83 | @item .enddual | |
84 | Exit dual instruction mode. While this directive is supported, the | |
85 | preferred way to use dual instruction mode is to explicitly code | |
86 | the dual bit with the @code{d.} prefix. | |
87 | @end table | |
88 | ||
89 | @table @code | |
90 | @cindex @code{atmp} directive, i860 | |
91 | @item .atmp | |
92 | Change the temporary register used when expanding pseudo operations. The | |
93 | default register is @code{r31}. | |
94 | @end table | |
95 | ||
96 | @node Opcodes for i860 | |
97 | @section i860 Opcodes | |
98 | ||
99 | @cindex opcodes, i860 | |
100 | @cindex i860 opcodes | |
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101 | All of the Intel i860 machine instructions are supported. Please see |
102 | either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information. | |
103 | @subsection Other instruction support (pseudo-instructions) | |
104 | For compatibility with some other i860 assemblers, a number of | |
105 | pseudo-instructions are supported. While these are supported, they are | |
106 | a very undesirable feature that should be avoided -- in particular, when | |
107 | they result in an expansion to multiple actual i860 instructions. Below | |
108 | are the pseudo-instructions that result in expansions. | |
109 | @itemize @bullet | |
9fc2dda2 | 110 | @item Load large immediate into general register: |
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111 | |
112 | The pseudo-instruction @code{mov imm,%rn} (where the immediate does | |
113 | not fit within a signed 16-bit field) will be expanded into: | |
114 | @smallexample | |
115 | orh large_imm@@h,%r0,%rn | |
116 | or large_imm@@l,%rn,%rn | |
117 | @end smallexample | |
9fc2dda2 | 118 | @item Load/store with relocatable address expression: |
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119 | |
120 | For example, the pseudo-instruction @code{ld.b addr,%rn} | |
121 | will be expanded into: | |
122 | @smallexample | |
123 | orh addr_exp@@ha,%r0,%r31 | |
124 | ld.l addr_exp@@l(%r31),%rn | |
125 | @end smallexample | |
126 | ||
127 | The analogous expansions apply to @code{ld.x, st.x, fld.x, pfld.x, fst.x}, and @code{pst.x} as well. | |
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128 | @item Signed large immediate with add/subtract: |
129 | ||
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130 | If any of the arithmetic operations @code{adds, addu, subs, subu} are used |
131 | with an immediate larger than 16-bits (signed), then they will be expanded. | |
132 | For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to: | |
133 | @smallexample | |
134 | orh large_imm@@h,%r0,%r31 | |
135 | or large_imm@@l,%r31,%r31 | |
136 | adds %r31,%rx,%rn | |
137 | @end smallexample | |
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138 | @item Unsigned large immediate with logical operations: |
139 | ||
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140 | Logical operations (@code{or, andnot, or, xor}) also result in expansions. |
141 | The pseudo-instruction @code{or large_imm,%rx,%rn} results in: | |
142 | @smallexample | |
143 | orh large_imm@@h,%rx,%r31 | |
144 | or large_imm@@l,%r31,%rn | |
145 | @end smallexample | |
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147 | Similarly for the others, except for @code{and} which expands to: |
148 | @smallexample | |
149 | andnot (-1 - large_imm)@@h,%rx,%r31 | |
150 | andnot (-1 - large_imm)@@l,%r31,%rn | |
151 | @end smallexample | |
152 | @end itemize | |
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